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module Vga_dev(clk, reset, hsync, vsync, color, VGA_R, VGA_G, VGA_B, x_ptr, y_ptr);
// VGA 640*480 60Hz
input clk;
input reset;
input [7: 0] color;
output vsync, hsync;
output [2: 0] VGA_R, VGA_G;
output [1: 0] VGA_B;
output [9: 0] x_ptr, y_ptr;
reg [9: 0] x_cnt, y_cnt;
reg [1: 0] cnt = 0;
wire [7: 0] color;
always @(posedge clk or posedge reset) begin
if (reset) cnt <= 0;
else cnt <= cnt + 1;
end
parameter
HPIXELS = 10'd800,
VLINES = 10'd521,
HBP = 10'd144,
HFP = 10'd784,
VBP = 10'd31,
VFP = 10'd511;
initial begin
x_cnt = 0;
y_cnt = 0;
end
always @(posedge cnt[1]) begin
if (x_cnt == HPIXELS - 1)
x_cnt <= 0;
else
x_cnt <= x_cnt + 1;
end
always @(posedge cnt[1]) begin
if (x_cnt == HPIXELS - 1) begin
if (y_cnt == VLINES - 1)
y_cnt <= 0;
else y_cnt <= y_cnt + 1;
end else
y_cnt <= y_cnt;
end
assign valid = (x_cnt > HBP) && (x_cnt < HFP) && (y_cnt > VBP) && (y_cnt < VFP);
assign hsync = (x_cnt >= 10'd96) ? 1'b1 : 1'b0;
assign vsync = (y_cnt >= 10'd2) ? 1'b1 : 1'b0;
assign x_ptr = x_cnt - HBP;
assign y_ptr = y_cnt - VBP;
assign VGA_R = valid ? color[7: 5] : 0;
assign VGA_G = valid ? color[4: 2] : 0;
assign VGA_B = valid ? color[1: 0] : 0;
endmodule
|
// +----------------------------------------------------------------------------
// GNU General Public License
// -----------------------------------------------------------------------------
// This file is part of uDLX (micro-DeLuX) soft IP-core.
//
// uDLX is free soft IP-core: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// uDLX soft core is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with uDLX. If not, see <http://www.gnu.org/licenses/>.
// +----------------------------------------------------------------------------
// PROJECT: uDLX core Processor
// ------------------------------------------------------------------------------
// FILE NAME : dlx_processor.v
// KEYWORDS : dlx, pipeline, core, toplevel
// -----------------------------------------------------------------------------
// PURPOSE: Top level entity of uDLX core processor
// -----------------------------------------------------------------------------
module dlx_processor
#(
parameter DATA_WIDTH = 32,
parameter INST_ADDR_WIDTH = 20,
parameter DATA_ADDR_WIDTH = 32
)
(
input clk,
input rst_n,
input enable,
output instr_rd_en,
output [INST_ADDR_WIDTH-1:0] instr_addr,
input [DATA_WIDTH-1:0] instruction,
output data_rd_en,
output data_wr_en,
output [DATA_ADDR_WIDTH-1:0] data_addr,
input [DATA_WIDTH-1:0] data_read,
output [DATA_WIDTH-1:0] data_write,
input boot_mode
);
localparam INSTRUCTION_WIDTH = DATA_WIDTH;
localparam PC_WIDTH = INST_ADDR_WIDTH;
localparam REG_ADDR_WIDTH = 5;
localparam OPCODE_WIDTH = 6;
localparam FUNCTION_WIDTH = 6;
localparam IMEDIATE_WIDTH = 16;
localparam PC_OFFSET_WIDTH = 26;
localparam PC_INITIAL_ADDRESS = 20'h00000;
// -----------------------------------------------------------------------------
// Internal signals
// -----------------------------------------------------------------------------
// Wires
// -----------------------------------------------------------------------------
// IF/ID Wires
// -----------------------------------------------------------------------------
wire [PC_WIDTH-1:0] if_id_new_pc;
wire [PC_WIDTH-1:0] new_pc;
wire [INSTRUCTION_WIDTH-1:0] if_id_instruction;
// wire [PC_WIDTH-1:0] instr_addr;
wire stall;
wire flush;
// -----------------------------------------------------------------------------
// ID/EX Wires
// -----------------------------------------------------------------------------
wire [DATA_WIDTH-1:0] data_alu_a;
wire [DATA_WIDTH-1:0] data_alu_b;
wire [OPCODE_WIDTH-1:0] opcode;
wire [FUNCTION_WIDTH-1:0] inst_function;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr1;
wire [REG_ADDR_WIDTH-1:0] reg_rd_addr2;
// wire [REG_ADDR_WIDTH-1:0] reg_wr_addr;
// wire reg_wr_en;
wire [REG_ADDR_WIDTH-1:0] reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] reg_b_wr_addr;
wire reg_a_wr_en;
wire reg_b_wr_en;
wire imm_inst;
wire [DATA_WIDTH-1:0] constant;
wire [PC_OFFSET_WIDTH-1:0] pc_offset;
wire mem_data_wr_en;
wire mem_data_rd_en;
wire write_back_mux_sel;
wire branch_inst;
wire branch_use_r;
wire jump_inst;
wire jump_use_r;
wire decode_flush;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_a_addr;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_b_addr;
wire [INSTRUCTION_WIDTH-1:0] id_ex_instruction;
wire [OPCODE_WIDTH-1:0] id_ex_opcode;
wire [FUNCTION_WIDTH-1:0] id_ex_function;
wire id_ex_mem_data_rd_en;
wire id_ex_mem_data_wr_en;
wire id_ex_write_back_mux_sel;
// wire id_ex_reg_rd_en; TODO see
// wire id_ex_reg_wr_en;
// wire [REG_ADDR_WIDTH-1:0] id_ex_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] id_ex_reg_b_wr_addr;
wire id_ex_reg_a_wr_en;
wire id_ex_reg_b_wr_en;
wire [DATA_WIDTH-1:0] id_ex_constant;
//wire id_ex_imm_inst;
wire [DATA_WIDTH-1:0] id_ex_data_alu_a;
wire [DATA_WIDTH-1:0] id_ex_data_alu_b;
wire [PC_WIDTH-1:0] id_ex_new_pc;
wire [PC_OFFSET_WIDTH-1:0] id_ex_pc_offset;
wire id_ex_branch_inst;
wire id_ex_branch_use_r;
wire id_ex_jump_inst;
wire id_ex_jump_use_r;
// -----------------------------------------------------------------------------
// EX/MEM Wires
// -----------------------------------------------------------------------------
wire ex_mem_data_rd_en;
wire ex_mem_data_wr_en;
wire [DATA_WIDTH-1:0] ex_mem_data_write;
wire [DATA_WIDTH-1:0] ex_mem_alu_data;
wire [DATA_WIDTH-1:0] ex_mem_hi_data;
wire [DATA_WIDTH-1:0] ex_mem_reg_data;
// wire ex_mem_reg_wr_en;
// wire [REG_ADDR_WIDTH-1:0] ex_mem_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] ex_mem_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] ex_mem_reg_b_wr_addr;
// wire [DATA_WIDTH-1:0] ex_mem_reg_a_wr_data;
// wire [DATA_WIDTH-1:0] ex_mem_reg_b_wr_data;
wire ex_mem_reg_a_wr_en;
wire ex_mem_reg_b_wr_en;
wire ex_mem_write_back_mux_sel;
wire ex_mem_select_new_pc;
wire [PC_WIDTH-1:0] ex_mem_new_pc;
wire [INSTRUCTION_WIDTH-1:0] ex_mem_instruction;
wire [DATA_WIDTH-1:0] mem_data;
wire [DATA_WIDTH-1:0] alu_data;
wire [DATA_WIDTH-1:0] hi_data;
wire fetch_select_new_pc;
wire [PC_WIDTH-1:0] fetch_new_pc;
// -----------------------------------------------------------------------------
// MEM/WB wires
// -----------------------------------------------------------------------------
wire mem_wb_write_back_mux_sel;
// wire [DATA_WIDTH-1:0] mem_wb_mem_data;
wire [DATA_WIDTH-1:0] mem_wb_alu_data;
wire [DATA_WIDTH-1:0] mem_wb_hi_data;
// wire mem_wb_reg_wr_en;
// wire [REG_ADDR_WIDTH-1:0] mem_wb_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] mem_wb_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] mem_wb_reg_b_wr_addr;
// wire [DATA_WIDTH-1:0] mem_wb_reg_a_wr_data;
// wire [DATA_WIDTH-1:0] mem_wb_reg_b_wr_data;
wire mem_wb_reg_a_wr_en;
wire mem_wb_reg_b_wr_en;
wire [INSTRUCTION_WIDTH-1:0] mem_wb_instruction;
// -----------------------------------------------------------------------------
// WB wires
// -----------------------------------------------------------------------------
// wire wb_write_enable;
// wire [DATA_WIDTH-1:0] wb_write_data;
// wire [REG_ADDR_WIDTH-1:0] wb_reg_wr_addr;
wire [REG_ADDR_WIDTH-1:0] wb_reg_a_wr_addr;
wire [REG_ADDR_WIDTH-1:0] wb_reg_b_wr_addr;
wire [DATA_WIDTH-1:0] wb_reg_a_wr_data;
wire [DATA_WIDTH-1:0] wb_reg_b_wr_data;
wire wb_reg_a_wr_en;
wire wb_reg_b_wr_en;
// -----------------------------------------------------------------------------
// Instruction Fetch modules
// -----------------------------------------------------------------------------
// Program Counter top level (including PC mux)
top_fetch
#(
.PC_DATA_WIDTH(PC_WIDTH),
.INSTRUCTION_WIDTH(DATA_WIDTH),
.PC_INITIAL_ADDRESS(PC_INITIAL_ADDRESS)
)
instruction_fetch_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.stall(stall),
.select_new_pc_in(fetch_select_new_pc),
.new_pc_in(fetch_new_pc),
.pc_out(new_pc),
.inst_mem_addr_out(instr_addr),
.boot_mode(boot_mode)
);
// -----------------------------------------------------------------------------
// Pipeline registers IF/ID
// -----------------------------------------------------------------------------
if_id_reg
#(
.INSTRUCTION_WIDTH(DATA_WIDTH),
.PC_DATA_WIDTH(PC_WIDTH)
)
if_id_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.stall(stall),
.flush(flush),
.inst_mem_data_in(instruction),
.pc_in(new_pc),
.new_pc_out(if_id_new_pc),
.instruction_reg_out(if_id_instruction)
);
// -----------------------------------------------------------------------------
// Instruction Decode modules
// -----------------------------------------------------------------------------
instruction_decode
#(
.PC_WIDTH(PC_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.IMEDIATE_WIDTH(IMEDIATE_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
instruction_decode_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.instruction_in(if_id_instruction),
// write back
.reg_a_wr_addr_in(wb_reg_a_wr_addr),
.reg_b_wr_addr_in(wb_reg_b_wr_addr),
.reg_a_wr_data_in(wb_reg_a_wr_data),
.reg_b_wr_data_in(wb_reg_b_wr_data),
.reg_a_wr_en_in(wb_reg_a_wr_en),
.reg_b_wr_en_in(wb_reg_b_wr_en),
// .wb_write_enable_in(wb_write_enable),
// .wb_write_data_in(wb_write_data),
// .wb_reg_wr_addr_in(wb_reg_wr_addr),
.select_new_pc_in(ex_mem_select_new_pc),
// ----- Hazzard control -----
.id_ex_mem_data_rd_en_in(id_ex_mem_data_rd_en),
.id_ex_reg_wr_addr_in(id_ex_reg_a_wr_addr),
// -----
.reg_rd_addr1_out(reg_rd_addr1), //(id_ex_reg_a_addr),
.reg_rd_addr2_out(reg_rd_addr2), //(id_ex_reg_b_addr),
.opcode_out(opcode),
.inst_function_out(inst_function),
.mem_data_rd_en_out(mem_data_rd_en),//(id_ex_mem_data_rd_en),
.mem_data_wr_en_out(mem_data_wr_en),//(id_ex_mem_data_wr_en),
.write_back_mux_sel_out(write_back_mux_sel),//(id_ex_write_back_mux_sel),
// .reg_wr_en_out(reg_wr_en),(id_ex_reg_wr_en),
// .reg_wr_addr_out(reg_wr_addr),(id_ex_reg_wr_addr),
.reg_a_wr_addr_out(reg_a_wr_addr),
.reg_b_wr_addr_out(reg_b_wr_addr),
.reg_a_wr_en_out(reg_a_wr_en),
.reg_b_wr_en_out(reg_b_wr_en),
.constant_out(constant), //(id_ex_constant),
.imm_inst_out(imm_inst), //(id_ex_imm_inst),
.data_alu_a_out(data_alu_a),//(id_ex_data_alu_a),
.data_alu_b_out(data_alu_b),//(id_ex_data_alu_b),
.pc_offset_out(pc_offset),//(id_ex_pc_offset),
.branch_inst_out(branch_inst),//(id_ex_branch_inst),
.branch_use_r_out(branch_use_r),
.jump_inst_out(jump_inst),//(id_ex_jump_inst),
.jump_use_r_out(jump_use_r),//(id_ex_jump_use_r),
.rd_inst_ena_out(instr_rd_en),
.stall_out(stall),
.general_flush_out(flush),
.decode_flush_out(decode_flush)
);
// -----------------------------------------------------------------------------
// Pipeline registers ID/EX
// -----------------------------------------------------------------------------
id_ex_reg
#(
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.PC_WIDTH(PC_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.IMEDIATE_WIDTH(IMEDIATE_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
id_ex_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.flush_in(decode_flush),
.data_alu_a_in(data_alu_a),
.data_alu_b_in(data_alu_b),
.new_pc_in(if_id_new_pc),
.instruction_in(if_id_instruction),
.opcode_in(opcode),
.inst_function_in(inst_function),
.reg_rd_addr1_in(reg_rd_addr1),
.reg_rd_addr2_in(reg_rd_addr2),
// .reg_wr_addr_in(reg_wr_addr),
// .reg_wr_en_in(reg_wr_en),
.reg_a_wr_addr_in(reg_a_wr_addr),
.reg_b_wr_addr_in(reg_b_wr_addr),
.reg_a_wr_en_in(reg_a_wr_en),
.reg_b_wr_en_in(reg_b_wr_en),
.constant_in(constant),
.imm_inst_in(imm_inst),
.pc_offset_in(pc_offset),
.mem_data_wr_en_in(mem_data_wr_en),
.mem_data_rd_en_in(mem_data_rd_en),
.write_back_mux_sel_in(write_back_mux_sel),
.branch_inst_in(branch_inst),
.branch_use_r_in(branch_use_r),
.jump_inst_in(jump_inst),
.jump_use_r_in(jump_use_r),
// Outputs
.data_alu_a_out(id_ex_data_alu_a),
.data_alu_b_out(id_ex_data_alu_b),
.new_pc_out(id_ex_new_pc),
.instruction_out(id_ex_instruction),
.opcode_out(id_ex_opcode),
.inst_function_out(id_ex_function),
.reg_rd_addr1_out(id_ex_reg_a_addr),
.reg_rd_addr2_out(id_ex_reg_b_addr),
// .reg_wr_addr_out(id_ex_reg_wr_addr),
// .reg_wr_en_out(id_ex_reg_wr_en),
.reg_a_wr_addr_out(id_ex_reg_a_wr_addr),
.reg_b_wr_addr_out(id_ex_reg_b_wr_addr),
.reg_a_wr_en_out(id_ex_reg_a_wr_en),
.reg_b_wr_en_out(id_ex_reg_b_wr_en),
.constant_out(id_ex_constant),
.imm_inst_out(id_ex_imm_inst),
.pc_offset_out(id_ex_pc_offset),
.mem_data_wr_en_out(id_ex_mem_data_wr_en),
.mem_data_rd_en_out(id_ex_mem_data_rd_en),
.write_back_mux_sel_out(id_ex_write_back_mux_sel),
.branch_inst_out(id_ex_branch_inst),
.branch_use_r_out(id_ex_branch_use_r),
.jump_inst_out(id_ex_jump_inst),
.jump_use_r_out(id_ex_jump_use_r)
);
// -----------------------------------------------------------------------------
// Execute modules
// -----------------------------------------------------------------------------
execute_address_calculate
#(
.DATA_WIDTH(DATA_WIDTH),
.PC_WIDTH(PC_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.OPCODE_WIDTH(OPCODE_WIDTH),
.FUNCTION_WIDTH(FUNCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH),
.PC_OFFSET_WIDTH(PC_OFFSET_WIDTH)
)
execute_address_calculate_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.alu_opcode_in(id_ex_opcode),
.alu_function_in(id_ex_function),
.data_alu_a_in(id_ex_data_alu_a),
.data_alu_b_in(id_ex_data_alu_b),
.reg_a_addr_in(id_ex_reg_a_addr),
.reg_b_addr_in(id_ex_reg_b_addr),
.constant_in(id_ex_constant),
.imm_inst_in(id_ex_imm_inst),
.new_pc_in(id_ex_new_pc),
.pc_offset_in(id_ex_pc_offset),
.branch_inst_in(id_ex_branch_inst),
.branch_use_r_in(id_ex_branch_use_r),
.jmp_inst_in(id_ex_jump_inst),
.jmp_use_r_in(id_ex_jump_use_r),
.instruction_in(id_ex_instruction),
//fowarding input
.ex_mem_reg_a_data_in(ex_mem_alu_data),//ex_mem_reg_a_wr_data),//input
.ex_mem_reg_b_data_in(ex_mem_hi_data),//ex_mem_reg_b_wr_data),//input
.ex_mem_reg_a_addr_in(ex_mem_reg_a_wr_addr),//input
.ex_mem_reg_b_addr_in(ex_mem_reg_b_wr_addr),//input
.ex_mem_reg_a_wr_ena_in(ex_mem_reg_a_wr_en),//input
.ex_mem_reg_b_wr_ena_in(ex_mem_reg_b_wr_en),//input
.wb_reg_a_data_in(wb_reg_a_wr_data),
.wb_reg_b_data_in(wb_reg_b_wr_data),
.wb_reg_a_addr_in(wb_reg_a_wr_addr),
.wb_reg_b_addr_in(wb_reg_b_wr_addr),
.wb_reg_a_wr_ena_in(wb_reg_a_wr_en),
.wb_reg_b_wr_ena_in(wb_reg_b_wr_en),
.mem_data_out(mem_data),
.alu_data_out(alu_data),
.hi_data_out(hi_data),
.fetch_new_pc_out(fetch_new_pc),
.fetch_select_new_pc_out(fetch_select_new_pc)
);
assign data_addr = ex_mem_alu_data;
assign data_rd_en = ex_mem_data_rd_en;
assign data_wr_en = ex_mem_data_wr_en;
assign data_write = ex_mem_data_write;
assign ex_mem_reg_data = ex_mem_alu_data;
// -----------------------------------------------------------------------------
// Pipeline registers EX/MEM
// -----------------------------------------------------------------------------
ex_mem_reg
#(
.PC_WIDTH(PC_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
ex_mem_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.flush_in(flush),
.mem_data_rd_en_in(id_ex_mem_data_rd_en),
.mem_data_wr_en_in(id_ex_mem_data_wr_en),
.mem_data_in(mem_data),
.alu_data_in(alu_data),
.hi_data_in(hi_data),
// .reg_wr_en_in(id_ex_reg_wr_en),
// .reg_wr_addr_in(id_ex_reg_wr_addr),
.reg_a_wr_addr_in(id_ex_reg_a_wr_addr),
.reg_b_wr_addr_in(id_ex_reg_b_wr_addr),
.reg_a_wr_en_in(id_ex_reg_a_wr_en),
.reg_b_wr_en_in(id_ex_reg_b_wr_en),
.write_back_mux_sel_in(id_ex_write_back_mux_sel),
.select_new_pc_in(fetch_select_new_pc),
.new_pc_in(fetch_new_pc),
.instruction_in(id_ex_instruction),
.mem_data_rd_en_out(ex_mem_data_rd_en),
.mem_data_wr_en_out(ex_mem_data_wr_en),
.mem_data_out(ex_mem_data_write),
.alu_data_out(ex_mem_alu_data),
.hi_data_out(ex_mem_hi_data),
// .reg_wr_en_out(ex_mem_reg_wr_en),
// .reg_wr_addr_out(ex_mem_reg_wr_addr),
.reg_a_wr_addr_out(ex_mem_reg_a_wr_addr),
.reg_b_wr_addr_out(ex_mem_reg_b_wr_addr),
.reg_a_wr_en_out(ex_mem_reg_a_wr_en),
.reg_b_wr_en_out(ex_mem_reg_b_wr_en),
.write_back_mux_sel_out(ex_mem_write_back_mux_sel),
.select_new_pc_out(ex_mem_select_new_pc),
.new_pc_out(ex_mem_new_pc),
.instruction_out(ex_mem_instruction)
);
// -----------------------------------------------------------------------------
// Memory Access modules
// Due to data memory to be outside Core processor, this RTL contains only
// the pipeline registers. The memory access is due by the Memory Interface.
// -----------------------------------------------------------------------------
// -----------------------------------------------------------------------------
// Pipeline registers MEM/WB
// -----------------------------------------------------------------------------
mem_wb_reg
#(
.DATA_WIDTH(DATA_WIDTH),
.INSTRUCTION_WIDTH(INSTRUCTION_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
mem_wb_reg_u0
(
.clk(clk),
.rst_n(rst_n),
.en(enable),
.write_back_mux_sel_in(ex_mem_write_back_mux_sel),
.alu_data_in(ex_mem_alu_data),
.hi_data_in(ex_mem_hi_data),
// .reg_wr_en_in(ex_mem_reg_wr_en),
// .reg_wr_addr_in(ex_mem_reg_wr_addr),
.reg_a_wr_addr_in(ex_mem_reg_a_wr_addr),
.reg_b_wr_addr_in(ex_mem_reg_b_wr_addr),
.reg_a_wr_en_in(ex_mem_reg_a_wr_en),
.reg_b_wr_en_in(ex_mem_reg_b_wr_en),
.instruction_in(ex_mem_instruction),
.write_back_mux_sel_out(mem_wb_write_back_mux_sel),
.alu_data_out(mem_wb_alu_data),
.hi_data_out(mem_wb_hi_data),
// .reg_wr_en_out(mem_wb_reg_wr_en),
// .reg_wr_addr_out(mem_wb_reg_wr_addr),
.reg_a_wr_addr_out(mem_wb_reg_a_wr_addr),
.reg_b_wr_addr_out(mem_wb_reg_b_wr_addr),
.reg_a_wr_en_out(mem_wb_reg_a_wr_en),
.reg_b_wr_en_out(mem_wb_reg_b_wr_en),
.instruction_out(mem_wb_instruction)
);
// -----------------------------------------------------------------------------
// Write-back multiplexer
// -----------------------------------------------------------------------------
write_back
#(
.DATA_WIDTH(DATA_WIDTH),
.REG_ADDR_WIDTH(REG_ADDR_WIDTH)
)
write_back_u0
(
.mem_data_in(data_read),
.alu_data_in(mem_wb_alu_data),
.hi_data_in(mem_wb_hi_data),
// .reg_wr_en_in(mem_wb_reg_wr_en),
// .reg_wr_addr_in(mem_wb_reg_wr_addr),
.reg_a_wr_addr_in(mem_wb_reg_a_wr_addr),
.reg_b_wr_addr_in(mem_wb_reg_b_wr_addr),
.reg_a_wr_en_in(mem_wb_reg_a_wr_en),
.reg_b_wr_en_in(mem_wb_reg_b_wr_en),
.write_back_mux_sel(mem_wb_write_back_mux_sel),
.reg_a_wr_addr_out(wb_reg_a_wr_addr),
.reg_b_wr_addr_out(wb_reg_b_wr_addr),
.reg_a_wr_data_out(wb_reg_a_wr_data),
.reg_b_wr_data_out(wb_reg_b_wr_data),
.reg_a_wr_en_out(wb_reg_a_wr_en),
.reg_b_wr_en_out(wb_reg_b_wr_en)
);
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2013 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a FIFO with same clock for both reads and writes. *
* *
******************************************************************************/
module altera_up_sync_fifo (
// Inputs
clk,
reset,
write_en,
write_data,
read_en,
// Bidirectionals
// Outputs
fifo_is_empty,
fifo_is_full,
words_used,
read_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 31;
parameter DATA_DEPTH = 128;
parameter AW = 6;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input write_en;
input [DW: 0] write_data;
input read_en;
// Bidirectionals
// Outputs
output fifo_is_empty;
output fifo_is_full;
output [AW: 0] words_used;
output [DW: 0] read_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
scfifo Sync_FIFO (
// Inputs
.clock (clk),
.sclr (reset),
.data (write_data),
.wrreq (write_en),
.rdreq (read_en),
// Bidirectionals
// Outputs
.empty (fifo_is_empty),
.full (fifo_is_full),
.usedw (words_used),
.q (read_data),
// Unused
// synopsys translate_off
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
Sync_FIFO.add_ram_output_register = "OFF",
Sync_FIFO.intended_device_family = "Cyclone II",
Sync_FIFO.lpm_numwords = DATA_DEPTH,
Sync_FIFO.lpm_showahead = "ON",
Sync_FIFO.lpm_type = "scfifo",
Sync_FIFO.lpm_width = DW + 1,
Sync_FIFO.lpm_widthu = AW + 1,
Sync_FIFO.overflow_checking = "OFF",
Sync_FIFO.underflow_checking = "OFF",
Sync_FIFO.use_eab = "ON";
endmodule
|
//`include "definitions.v"
module decodificador(
input wire Clock,
input wire[15:0] wInstruction,
input wire wZa, wZb, wCa, wCb, wNa, wNb,
output reg rBranch_taken,
output reg rJumpTaken;
output reg[9:0] rBranch_dir,
//output reg[7:0] rA,
//output reg[7:0] rB,
output reg[7:0] rC,
output reg rMux_a_sel,
output reg rMux_b_sel
);
always @(posedge Clock)
begin
case(wInstruction[15:0])
`LDA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`LDB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`STA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`STB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ADDA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ADDB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`SUBA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`SUBB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ANDA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ANDB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ORA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ORB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ASLA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`ASRA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC<=8'b0;
end
`LDCA:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`LDCB:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ADDCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ADDCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`SUBCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`SUBCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ANDCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ANDCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ORCA:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=1;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`ORCB:
begin
rJumpTaken<=0;
rMux_a_sel<=1;
rMux_b_sel<=0;
rBranch_taken<=0;
rBranch_dir<=10'b0;
rC=wInstruction[7:0];
end
`JMP:
begin
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rJumpTaken<=1;
rBranch_dir<=wInstruction[9:0];
rC<=8'b0;
end
`BAEQ:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZa==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BANE:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZa==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BACS:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCa==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BACC:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCa==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BAMI:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNa==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BAPL:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNa==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBEQ:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZb==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBNE:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wZb==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBCS:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCb==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBCC:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wCb==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBMI:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNb==1)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
`BBPL:
begin
rJumpTaken<=0;
rMux_a_sel<=0;
rMux_b_sel<=0;
rC<=8'b0;
if(wNb==0)
begin
rBranch_taken<=1;
rBranch_dir<=wInstruction[6:0];
end
else
rBranch_taken<=0;
end
default:
begin
rMux_a_sel<=0;
rMux_b_sel<=0;
rBranch_taken<=0;
rJumpTaken<=0;
rBranch_dir<=10'b0;
rC=8'b0;
end
endcase
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:06:15 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_sim_netlist.v
// Design : vio_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k160tffg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "vio_0,vio,{}" *) (* X_CORE_INFO = "vio,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
wire clk;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
wire [0:0]NLW_inst_probe_out0_UNCONNECTED;
wire [0:0]NLW_inst_probe_out1_UNCONNECTED;
wire [0:0]NLW_inst_probe_out10_UNCONNECTED;
wire [0:0]NLW_inst_probe_out100_UNCONNECTED;
wire [0:0]NLW_inst_probe_out101_UNCONNECTED;
wire [0:0]NLW_inst_probe_out102_UNCONNECTED;
wire [0:0]NLW_inst_probe_out103_UNCONNECTED;
wire [0:0]NLW_inst_probe_out104_UNCONNECTED;
wire [0:0]NLW_inst_probe_out105_UNCONNECTED;
wire [0:0]NLW_inst_probe_out106_UNCONNECTED;
wire [0:0]NLW_inst_probe_out107_UNCONNECTED;
wire [0:0]NLW_inst_probe_out108_UNCONNECTED;
wire [0:0]NLW_inst_probe_out109_UNCONNECTED;
wire [0:0]NLW_inst_probe_out11_UNCONNECTED;
wire [0:0]NLW_inst_probe_out110_UNCONNECTED;
wire [0:0]NLW_inst_probe_out111_UNCONNECTED;
wire [0:0]NLW_inst_probe_out112_UNCONNECTED;
wire [0:0]NLW_inst_probe_out113_UNCONNECTED;
wire [0:0]NLW_inst_probe_out114_UNCONNECTED;
wire [0:0]NLW_inst_probe_out115_UNCONNECTED;
wire [0:0]NLW_inst_probe_out116_UNCONNECTED;
wire [0:0]NLW_inst_probe_out117_UNCONNECTED;
wire [0:0]NLW_inst_probe_out118_UNCONNECTED;
wire [0:0]NLW_inst_probe_out119_UNCONNECTED;
wire [0:0]NLW_inst_probe_out12_UNCONNECTED;
wire [0:0]NLW_inst_probe_out120_UNCONNECTED;
wire [0:0]NLW_inst_probe_out121_UNCONNECTED;
wire [0:0]NLW_inst_probe_out122_UNCONNECTED;
wire [0:0]NLW_inst_probe_out123_UNCONNECTED;
wire [0:0]NLW_inst_probe_out124_UNCONNECTED;
wire [0:0]NLW_inst_probe_out125_UNCONNECTED;
wire [0:0]NLW_inst_probe_out126_UNCONNECTED;
wire [0:0]NLW_inst_probe_out127_UNCONNECTED;
wire [0:0]NLW_inst_probe_out128_UNCONNECTED;
wire [0:0]NLW_inst_probe_out129_UNCONNECTED;
wire [0:0]NLW_inst_probe_out13_UNCONNECTED;
wire [0:0]NLW_inst_probe_out130_UNCONNECTED;
wire [0:0]NLW_inst_probe_out131_UNCONNECTED;
wire [0:0]NLW_inst_probe_out132_UNCONNECTED;
wire [0:0]NLW_inst_probe_out133_UNCONNECTED;
wire [0:0]NLW_inst_probe_out134_UNCONNECTED;
wire [0:0]NLW_inst_probe_out135_UNCONNECTED;
wire [0:0]NLW_inst_probe_out136_UNCONNECTED;
wire [0:0]NLW_inst_probe_out137_UNCONNECTED;
wire [0:0]NLW_inst_probe_out138_UNCONNECTED;
wire [0:0]NLW_inst_probe_out139_UNCONNECTED;
wire [0:0]NLW_inst_probe_out14_UNCONNECTED;
wire [0:0]NLW_inst_probe_out140_UNCONNECTED;
wire [0:0]NLW_inst_probe_out141_UNCONNECTED;
wire [0:0]NLW_inst_probe_out142_UNCONNECTED;
wire [0:0]NLW_inst_probe_out143_UNCONNECTED;
wire [0:0]NLW_inst_probe_out144_UNCONNECTED;
wire [0:0]NLW_inst_probe_out145_UNCONNECTED;
wire [0:0]NLW_inst_probe_out146_UNCONNECTED;
wire [0:0]NLW_inst_probe_out147_UNCONNECTED;
wire [0:0]NLW_inst_probe_out148_UNCONNECTED;
wire [0:0]NLW_inst_probe_out149_UNCONNECTED;
wire [0:0]NLW_inst_probe_out15_UNCONNECTED;
wire [0:0]NLW_inst_probe_out150_UNCONNECTED;
wire [0:0]NLW_inst_probe_out151_UNCONNECTED;
wire [0:0]NLW_inst_probe_out152_UNCONNECTED;
wire [0:0]NLW_inst_probe_out153_UNCONNECTED;
wire [0:0]NLW_inst_probe_out154_UNCONNECTED;
wire [0:0]NLW_inst_probe_out155_UNCONNECTED;
wire [0:0]NLW_inst_probe_out156_UNCONNECTED;
wire [0:0]NLW_inst_probe_out157_UNCONNECTED;
wire [0:0]NLW_inst_probe_out158_UNCONNECTED;
wire [0:0]NLW_inst_probe_out159_UNCONNECTED;
wire [0:0]NLW_inst_probe_out16_UNCONNECTED;
wire [0:0]NLW_inst_probe_out160_UNCONNECTED;
wire [0:0]NLW_inst_probe_out161_UNCONNECTED;
wire [0:0]NLW_inst_probe_out162_UNCONNECTED;
wire [0:0]NLW_inst_probe_out163_UNCONNECTED;
wire [0:0]NLW_inst_probe_out164_UNCONNECTED;
wire [0:0]NLW_inst_probe_out165_UNCONNECTED;
wire [0:0]NLW_inst_probe_out166_UNCONNECTED;
wire [0:0]NLW_inst_probe_out167_UNCONNECTED;
wire [0:0]NLW_inst_probe_out168_UNCONNECTED;
wire [0:0]NLW_inst_probe_out169_UNCONNECTED;
wire [0:0]NLW_inst_probe_out17_UNCONNECTED;
wire [0:0]NLW_inst_probe_out170_UNCONNECTED;
wire [0:0]NLW_inst_probe_out171_UNCONNECTED;
wire [0:0]NLW_inst_probe_out172_UNCONNECTED;
wire [0:0]NLW_inst_probe_out173_UNCONNECTED;
wire [0:0]NLW_inst_probe_out174_UNCONNECTED;
wire [0:0]NLW_inst_probe_out175_UNCONNECTED;
wire [0:0]NLW_inst_probe_out176_UNCONNECTED;
wire [0:0]NLW_inst_probe_out177_UNCONNECTED;
wire [0:0]NLW_inst_probe_out178_UNCONNECTED;
wire [0:0]NLW_inst_probe_out179_UNCONNECTED;
wire [0:0]NLW_inst_probe_out18_UNCONNECTED;
wire [0:0]NLW_inst_probe_out180_UNCONNECTED;
wire [0:0]NLW_inst_probe_out181_UNCONNECTED;
wire [0:0]NLW_inst_probe_out182_UNCONNECTED;
wire [0:0]NLW_inst_probe_out183_UNCONNECTED;
wire [0:0]NLW_inst_probe_out184_UNCONNECTED;
wire [0:0]NLW_inst_probe_out185_UNCONNECTED;
wire [0:0]NLW_inst_probe_out186_UNCONNECTED;
wire [0:0]NLW_inst_probe_out187_UNCONNECTED;
wire [0:0]NLW_inst_probe_out188_UNCONNECTED;
wire [0:0]NLW_inst_probe_out189_UNCONNECTED;
wire [0:0]NLW_inst_probe_out19_UNCONNECTED;
wire [0:0]NLW_inst_probe_out190_UNCONNECTED;
wire [0:0]NLW_inst_probe_out191_UNCONNECTED;
wire [0:0]NLW_inst_probe_out192_UNCONNECTED;
wire [0:0]NLW_inst_probe_out193_UNCONNECTED;
wire [0:0]NLW_inst_probe_out194_UNCONNECTED;
wire [0:0]NLW_inst_probe_out195_UNCONNECTED;
wire [0:0]NLW_inst_probe_out196_UNCONNECTED;
wire [0:0]NLW_inst_probe_out197_UNCONNECTED;
wire [0:0]NLW_inst_probe_out198_UNCONNECTED;
wire [0:0]NLW_inst_probe_out199_UNCONNECTED;
wire [0:0]NLW_inst_probe_out2_UNCONNECTED;
wire [0:0]NLW_inst_probe_out20_UNCONNECTED;
wire [0:0]NLW_inst_probe_out200_UNCONNECTED;
wire [0:0]NLW_inst_probe_out201_UNCONNECTED;
wire [0:0]NLW_inst_probe_out202_UNCONNECTED;
wire [0:0]NLW_inst_probe_out203_UNCONNECTED;
wire [0:0]NLW_inst_probe_out204_UNCONNECTED;
wire [0:0]NLW_inst_probe_out205_UNCONNECTED;
wire [0:0]NLW_inst_probe_out206_UNCONNECTED;
wire [0:0]NLW_inst_probe_out207_UNCONNECTED;
wire [0:0]NLW_inst_probe_out208_UNCONNECTED;
wire [0:0]NLW_inst_probe_out209_UNCONNECTED;
wire [0:0]NLW_inst_probe_out21_UNCONNECTED;
wire [0:0]NLW_inst_probe_out210_UNCONNECTED;
wire [0:0]NLW_inst_probe_out211_UNCONNECTED;
wire [0:0]NLW_inst_probe_out212_UNCONNECTED;
wire [0:0]NLW_inst_probe_out213_UNCONNECTED;
wire [0:0]NLW_inst_probe_out214_UNCONNECTED;
wire [0:0]NLW_inst_probe_out215_UNCONNECTED;
wire [0:0]NLW_inst_probe_out216_UNCONNECTED;
wire [0:0]NLW_inst_probe_out217_UNCONNECTED;
wire [0:0]NLW_inst_probe_out218_UNCONNECTED;
wire [0:0]NLW_inst_probe_out219_UNCONNECTED;
wire [0:0]NLW_inst_probe_out22_UNCONNECTED;
wire [0:0]NLW_inst_probe_out220_UNCONNECTED;
wire [0:0]NLW_inst_probe_out221_UNCONNECTED;
wire [0:0]NLW_inst_probe_out222_UNCONNECTED;
wire [0:0]NLW_inst_probe_out223_UNCONNECTED;
wire [0:0]NLW_inst_probe_out224_UNCONNECTED;
wire [0:0]NLW_inst_probe_out225_UNCONNECTED;
wire [0:0]NLW_inst_probe_out226_UNCONNECTED;
wire [0:0]NLW_inst_probe_out227_UNCONNECTED;
wire [0:0]NLW_inst_probe_out228_UNCONNECTED;
wire [0:0]NLW_inst_probe_out229_UNCONNECTED;
wire [0:0]NLW_inst_probe_out23_UNCONNECTED;
wire [0:0]NLW_inst_probe_out230_UNCONNECTED;
wire [0:0]NLW_inst_probe_out231_UNCONNECTED;
wire [0:0]NLW_inst_probe_out232_UNCONNECTED;
wire [0:0]NLW_inst_probe_out233_UNCONNECTED;
wire [0:0]NLW_inst_probe_out234_UNCONNECTED;
wire [0:0]NLW_inst_probe_out235_UNCONNECTED;
wire [0:0]NLW_inst_probe_out236_UNCONNECTED;
wire [0:0]NLW_inst_probe_out237_UNCONNECTED;
wire [0:0]NLW_inst_probe_out238_UNCONNECTED;
wire [0:0]NLW_inst_probe_out239_UNCONNECTED;
wire [0:0]NLW_inst_probe_out24_UNCONNECTED;
wire [0:0]NLW_inst_probe_out240_UNCONNECTED;
wire [0:0]NLW_inst_probe_out241_UNCONNECTED;
wire [0:0]NLW_inst_probe_out242_UNCONNECTED;
wire [0:0]NLW_inst_probe_out243_UNCONNECTED;
wire [0:0]NLW_inst_probe_out244_UNCONNECTED;
wire [0:0]NLW_inst_probe_out245_UNCONNECTED;
wire [0:0]NLW_inst_probe_out246_UNCONNECTED;
wire [0:0]NLW_inst_probe_out247_UNCONNECTED;
wire [0:0]NLW_inst_probe_out248_UNCONNECTED;
wire [0:0]NLW_inst_probe_out249_UNCONNECTED;
wire [0:0]NLW_inst_probe_out25_UNCONNECTED;
wire [0:0]NLW_inst_probe_out250_UNCONNECTED;
wire [0:0]NLW_inst_probe_out251_UNCONNECTED;
wire [0:0]NLW_inst_probe_out252_UNCONNECTED;
wire [0:0]NLW_inst_probe_out253_UNCONNECTED;
wire [0:0]NLW_inst_probe_out254_UNCONNECTED;
wire [0:0]NLW_inst_probe_out255_UNCONNECTED;
wire [0:0]NLW_inst_probe_out26_UNCONNECTED;
wire [0:0]NLW_inst_probe_out27_UNCONNECTED;
wire [0:0]NLW_inst_probe_out28_UNCONNECTED;
wire [0:0]NLW_inst_probe_out29_UNCONNECTED;
wire [0:0]NLW_inst_probe_out3_UNCONNECTED;
wire [0:0]NLW_inst_probe_out30_UNCONNECTED;
wire [0:0]NLW_inst_probe_out31_UNCONNECTED;
wire [0:0]NLW_inst_probe_out32_UNCONNECTED;
wire [0:0]NLW_inst_probe_out33_UNCONNECTED;
wire [0:0]NLW_inst_probe_out34_UNCONNECTED;
wire [0:0]NLW_inst_probe_out35_UNCONNECTED;
wire [0:0]NLW_inst_probe_out36_UNCONNECTED;
wire [0:0]NLW_inst_probe_out37_UNCONNECTED;
wire [0:0]NLW_inst_probe_out38_UNCONNECTED;
wire [0:0]NLW_inst_probe_out39_UNCONNECTED;
wire [0:0]NLW_inst_probe_out4_UNCONNECTED;
wire [0:0]NLW_inst_probe_out40_UNCONNECTED;
wire [0:0]NLW_inst_probe_out41_UNCONNECTED;
wire [0:0]NLW_inst_probe_out42_UNCONNECTED;
wire [0:0]NLW_inst_probe_out43_UNCONNECTED;
wire [0:0]NLW_inst_probe_out44_UNCONNECTED;
wire [0:0]NLW_inst_probe_out45_UNCONNECTED;
wire [0:0]NLW_inst_probe_out46_UNCONNECTED;
wire [0:0]NLW_inst_probe_out47_UNCONNECTED;
wire [0:0]NLW_inst_probe_out48_UNCONNECTED;
wire [0:0]NLW_inst_probe_out49_UNCONNECTED;
wire [0:0]NLW_inst_probe_out5_UNCONNECTED;
wire [0:0]NLW_inst_probe_out50_UNCONNECTED;
wire [0:0]NLW_inst_probe_out51_UNCONNECTED;
wire [0:0]NLW_inst_probe_out52_UNCONNECTED;
wire [0:0]NLW_inst_probe_out53_UNCONNECTED;
wire [0:0]NLW_inst_probe_out54_UNCONNECTED;
wire [0:0]NLW_inst_probe_out55_UNCONNECTED;
wire [0:0]NLW_inst_probe_out56_UNCONNECTED;
wire [0:0]NLW_inst_probe_out57_UNCONNECTED;
wire [0:0]NLW_inst_probe_out58_UNCONNECTED;
wire [0:0]NLW_inst_probe_out59_UNCONNECTED;
wire [0:0]NLW_inst_probe_out6_UNCONNECTED;
wire [0:0]NLW_inst_probe_out60_UNCONNECTED;
wire [0:0]NLW_inst_probe_out61_UNCONNECTED;
wire [0:0]NLW_inst_probe_out62_UNCONNECTED;
wire [0:0]NLW_inst_probe_out63_UNCONNECTED;
wire [0:0]NLW_inst_probe_out64_UNCONNECTED;
wire [0:0]NLW_inst_probe_out65_UNCONNECTED;
wire [0:0]NLW_inst_probe_out66_UNCONNECTED;
wire [0:0]NLW_inst_probe_out67_UNCONNECTED;
wire [0:0]NLW_inst_probe_out68_UNCONNECTED;
wire [0:0]NLW_inst_probe_out69_UNCONNECTED;
wire [0:0]NLW_inst_probe_out7_UNCONNECTED;
wire [0:0]NLW_inst_probe_out70_UNCONNECTED;
wire [0:0]NLW_inst_probe_out71_UNCONNECTED;
wire [0:0]NLW_inst_probe_out72_UNCONNECTED;
wire [0:0]NLW_inst_probe_out73_UNCONNECTED;
wire [0:0]NLW_inst_probe_out74_UNCONNECTED;
wire [0:0]NLW_inst_probe_out75_UNCONNECTED;
wire [0:0]NLW_inst_probe_out76_UNCONNECTED;
wire [0:0]NLW_inst_probe_out77_UNCONNECTED;
wire [0:0]NLW_inst_probe_out78_UNCONNECTED;
wire [0:0]NLW_inst_probe_out79_UNCONNECTED;
wire [0:0]NLW_inst_probe_out8_UNCONNECTED;
wire [0:0]NLW_inst_probe_out80_UNCONNECTED;
wire [0:0]NLW_inst_probe_out81_UNCONNECTED;
wire [0:0]NLW_inst_probe_out82_UNCONNECTED;
wire [0:0]NLW_inst_probe_out83_UNCONNECTED;
wire [0:0]NLW_inst_probe_out84_UNCONNECTED;
wire [0:0]NLW_inst_probe_out85_UNCONNECTED;
wire [0:0]NLW_inst_probe_out86_UNCONNECTED;
wire [0:0]NLW_inst_probe_out87_UNCONNECTED;
wire [0:0]NLW_inst_probe_out88_UNCONNECTED;
wire [0:0]NLW_inst_probe_out89_UNCONNECTED;
wire [0:0]NLW_inst_probe_out9_UNCONNECTED;
wire [0:0]NLW_inst_probe_out90_UNCONNECTED;
wire [0:0]NLW_inst_probe_out91_UNCONNECTED;
wire [0:0]NLW_inst_probe_out92_UNCONNECTED;
wire [0:0]NLW_inst_probe_out93_UNCONNECTED;
wire [0:0]NLW_inst_probe_out94_UNCONNECTED;
wire [0:0]NLW_inst_probe_out95_UNCONNECTED;
wire [0:0]NLW_inst_probe_out96_UNCONNECTED;
wire [0:0]NLW_inst_probe_out97_UNCONNECTED;
wire [0:0]NLW_inst_probe_out98_UNCONNECTED;
wire [0:0]NLW_inst_probe_out99_UNCONNECTED;
wire [16:0]NLW_inst_sl_oport0_UNCONNECTED;
(* C_BUILD_REVISION = "0" *)
(* C_BUS_ADDR_WIDTH = "17" *)
(* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_EN_PROBE_IN_ACTIVITY = "1" *)
(* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MAX_NUM_PROBE = "256" *)
(* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *)
(* C_PROBE_IN101_WIDTH = "1" *)
(* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *)
(* C_PROBE_IN104_WIDTH = "1" *)
(* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *)
(* C_PROBE_IN107_WIDTH = "1" *)
(* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *)
(* C_PROBE_IN10_WIDTH = "1" *)
(* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *)
(* C_PROBE_IN112_WIDTH = "1" *)
(* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *)
(* C_PROBE_IN115_WIDTH = "1" *)
(* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *)
(* C_PROBE_IN118_WIDTH = "1" *)
(* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *)
(* C_PROBE_IN120_WIDTH = "1" *)
(* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *)
(* C_PROBE_IN123_WIDTH = "1" *)
(* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *)
(* C_PROBE_IN126_WIDTH = "1" *)
(* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *)
(* C_PROBE_IN129_WIDTH = "1" *)
(* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *)
(* C_PROBE_IN131_WIDTH = "1" *)
(* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *)
(* C_PROBE_IN134_WIDTH = "1" *)
(* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *)
(* C_PROBE_IN137_WIDTH = "1" *)
(* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *)
(* C_PROBE_IN13_WIDTH = "1" *)
(* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *)
(* C_PROBE_IN142_WIDTH = "1" *)
(* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *)
(* C_PROBE_IN145_WIDTH = "1" *)
(* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *)
(* C_PROBE_IN148_WIDTH = "1" *)
(* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *)
(* C_PROBE_IN150_WIDTH = "1" *)
(* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *)
(* C_PROBE_IN153_WIDTH = "1" *)
(* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *)
(* C_PROBE_IN156_WIDTH = "1" *)
(* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *)
(* C_PROBE_IN159_WIDTH = "1" *)
(* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *)
(* C_PROBE_IN161_WIDTH = "1" *)
(* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *)
(* C_PROBE_IN164_WIDTH = "1" *)
(* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *)
(* C_PROBE_IN167_WIDTH = "1" *)
(* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *)
(* C_PROBE_IN16_WIDTH = "1" *)
(* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *)
(* C_PROBE_IN172_WIDTH = "1" *)
(* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *)
(* C_PROBE_IN175_WIDTH = "1" *)
(* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *)
(* C_PROBE_IN178_WIDTH = "1" *)
(* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *)
(* C_PROBE_IN180_WIDTH = "1" *)
(* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *)
(* C_PROBE_IN183_WIDTH = "1" *)
(* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *)
(* C_PROBE_IN186_WIDTH = "1" *)
(* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *)
(* C_PROBE_IN189_WIDTH = "1" *)
(* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *)
(* C_PROBE_IN191_WIDTH = "1" *)
(* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *)
(* C_PROBE_IN194_WIDTH = "1" *)
(* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *)
(* C_PROBE_IN197_WIDTH = "1" *)
(* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *)
(* C_PROBE_IN19_WIDTH = "1" *)
(* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *)
(* C_PROBE_IN201_WIDTH = "1" *)
(* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *)
(* C_PROBE_IN204_WIDTH = "1" *)
(* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *)
(* C_PROBE_IN207_WIDTH = "1" *)
(* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *)
(* C_PROBE_IN20_WIDTH = "1" *)
(* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *)
(* C_PROBE_IN212_WIDTH = "1" *)
(* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *)
(* C_PROBE_IN215_WIDTH = "1" *)
(* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *)
(* C_PROBE_IN218_WIDTH = "1" *)
(* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *)
(* C_PROBE_IN220_WIDTH = "1" *)
(* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *)
(* C_PROBE_IN223_WIDTH = "1" *)
(* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *)
(* C_PROBE_IN226_WIDTH = "1" *)
(* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *)
(* C_PROBE_IN229_WIDTH = "1" *)
(* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *)
(* C_PROBE_IN231_WIDTH = "1" *)
(* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *)
(* C_PROBE_IN234_WIDTH = "1" *)
(* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *)
(* C_PROBE_IN237_WIDTH = "1" *)
(* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *)
(* C_PROBE_IN23_WIDTH = "1" *)
(* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *)
(* C_PROBE_IN242_WIDTH = "1" *)
(* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *)
(* C_PROBE_IN245_WIDTH = "1" *)
(* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *)
(* C_PROBE_IN248_WIDTH = "1" *)
(* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *)
(* C_PROBE_IN250_WIDTH = "1" *)
(* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *)
(* C_PROBE_IN253_WIDTH = "1" *)
(* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *)
(* C_PROBE_IN25_WIDTH = "1" *)
(* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *)
(* C_PROBE_IN28_WIDTH = "1" *)
(* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *)
(* C_PROBE_IN30_WIDTH = "1" *)
(* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *)
(* C_PROBE_IN33_WIDTH = "1" *)
(* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *)
(* C_PROBE_IN36_WIDTH = "1" *)
(* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *)
(* C_PROBE_IN39_WIDTH = "1" *)
(* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *)
(* C_PROBE_IN41_WIDTH = "1" *)
(* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *)
(* C_PROBE_IN44_WIDTH = "1" *)
(* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *)
(* C_PROBE_IN47_WIDTH = "1" *)
(* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *)
(* C_PROBE_IN4_WIDTH = "1" *)
(* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *)
(* C_PROBE_IN52_WIDTH = "1" *)
(* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *)
(* C_PROBE_IN55_WIDTH = "1" *)
(* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *)
(* C_PROBE_IN58_WIDTH = "1" *)
(* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *)
(* C_PROBE_IN60_WIDTH = "1" *)
(* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *)
(* C_PROBE_IN63_WIDTH = "1" *)
(* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *)
(* C_PROBE_IN66_WIDTH = "1" *)
(* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *)
(* C_PROBE_IN69_WIDTH = "1" *)
(* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *)
(* C_PROBE_IN71_WIDTH = "1" *)
(* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *)
(* C_PROBE_IN74_WIDTH = "1" *)
(* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *)
(* C_PROBE_IN77_WIDTH = "1" *)
(* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *)
(* C_PROBE_IN7_WIDTH = "1" *)
(* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *)
(* C_PROBE_IN82_WIDTH = "1" *)
(* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *)
(* C_PROBE_IN85_WIDTH = "1" *)
(* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *)
(* C_PROBE_IN88_WIDTH = "1" *)
(* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *)
(* C_PROBE_IN90_WIDTH = "1" *)
(* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *)
(* C_PROBE_IN93_WIDTH = "1" *)
(* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *)
(* C_PROBE_IN96_WIDTH = "1" *)
(* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *)
(* C_PROBE_IN99_WIDTH = "1" *)
(* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT0_WIDTH = "1" *)
(* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *)
(* C_PROBE_OUT101_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT102_WIDTH = "1" *)
(* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *)
(* C_PROBE_OUT104_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT105_WIDTH = "1" *)
(* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *)
(* C_PROBE_OUT107_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT108_WIDTH = "1" *)
(* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *)
(* C_PROBE_OUT10_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT110_WIDTH = "1" *)
(* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *)
(* C_PROBE_OUT112_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT113_WIDTH = "1" *)
(* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *)
(* C_PROBE_OUT115_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT116_WIDTH = "1" *)
(* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *)
(* C_PROBE_OUT118_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT119_WIDTH = "1" *)
(* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *)
(* C_PROBE_OUT120_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT121_WIDTH = "1" *)
(* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *)
(* C_PROBE_OUT123_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT124_WIDTH = "1" *)
(* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *)
(* C_PROBE_OUT126_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT127_WIDTH = "1" *)
(* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *)
(* C_PROBE_OUT129_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT12_WIDTH = "1" *)
(* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *)
(* C_PROBE_OUT131_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT132_WIDTH = "1" *)
(* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *)
(* C_PROBE_OUT134_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT135_WIDTH = "1" *)
(* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *)
(* C_PROBE_OUT137_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT138_WIDTH = "1" *)
(* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *)
(* C_PROBE_OUT13_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT140_WIDTH = "1" *)
(* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *)
(* C_PROBE_OUT142_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT143_WIDTH = "1" *)
(* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *)
(* C_PROBE_OUT145_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT146_WIDTH = "1" *)
(* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *)
(* C_PROBE_OUT148_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT149_WIDTH = "1" *)
(* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *)
(* C_PROBE_OUT150_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT151_WIDTH = "1" *)
(* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *)
(* C_PROBE_OUT153_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT154_WIDTH = "1" *)
(* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *)
(* C_PROBE_OUT156_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT157_WIDTH = "1" *)
(* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *)
(* C_PROBE_OUT159_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT15_WIDTH = "1" *)
(* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *)
(* C_PROBE_OUT161_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT162_WIDTH = "1" *)
(* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *)
(* C_PROBE_OUT164_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT165_WIDTH = "1" *)
(* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *)
(* C_PROBE_OUT167_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT168_WIDTH = "1" *)
(* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *)
(* C_PROBE_OUT16_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT170_WIDTH = "1" *)
(* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *)
(* C_PROBE_OUT172_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT173_WIDTH = "1" *)
(* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *)
(* C_PROBE_OUT175_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT176_WIDTH = "1" *)
(* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *)
(* C_PROBE_OUT178_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT179_WIDTH = "1" *)
(* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *)
(* C_PROBE_OUT180_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT181_WIDTH = "1" *)
(* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *)
(* C_PROBE_OUT183_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT184_WIDTH = "1" *)
(* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *)
(* C_PROBE_OUT186_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT187_WIDTH = "1" *)
(* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *)
(* C_PROBE_OUT189_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT18_WIDTH = "1" *)
(* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *)
(* C_PROBE_OUT191_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT192_WIDTH = "1" *)
(* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *)
(* C_PROBE_OUT194_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT195_WIDTH = "1" *)
(* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *)
(* C_PROBE_OUT197_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT198_WIDTH = "1" *)
(* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *)
(* C_PROBE_OUT19_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT1_WIDTH = "1" *)
(* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *)
(* C_PROBE_OUT201_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT202_WIDTH = "1" *)
(* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *)
(* C_PROBE_OUT204_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT205_WIDTH = "1" *)
(* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *)
(* C_PROBE_OUT207_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT208_WIDTH = "1" *)
(* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *)
(* C_PROBE_OUT20_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT210_WIDTH = "1" *)
(* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *)
(* C_PROBE_OUT212_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT213_WIDTH = "1" *)
(* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *)
(* C_PROBE_OUT215_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT216_WIDTH = "1" *)
(* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *)
(* C_PROBE_OUT218_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT219_WIDTH = "1" *)
(* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *)
(* C_PROBE_OUT220_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT221_WIDTH = "1" *)
(* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *)
(* C_PROBE_OUT223_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT224_WIDTH = "1" *)
(* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *)
(* C_PROBE_OUT226_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT227_WIDTH = "1" *)
(* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *)
(* C_PROBE_OUT229_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT22_WIDTH = "1" *)
(* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *)
(* C_PROBE_OUT231_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT232_WIDTH = "1" *)
(* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *)
(* C_PROBE_OUT234_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT235_WIDTH = "1" *)
(* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *)
(* C_PROBE_OUT237_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT238_WIDTH = "1" *)
(* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *)
(* C_PROBE_OUT23_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT240_WIDTH = "1" *)
(* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *)
(* C_PROBE_OUT242_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT243_WIDTH = "1" *)
(* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *)
(* C_PROBE_OUT245_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT246_WIDTH = "1" *)
(* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *)
(* C_PROBE_OUT248_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT249_WIDTH = "1" *)
(* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *)
(* C_PROBE_OUT250_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT251_WIDTH = "1" *)
(* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *)
(* C_PROBE_OUT253_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT254_WIDTH = "1" *)
(* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *)
(* C_PROBE_OUT25_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT26_WIDTH = "1" *)
(* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *)
(* C_PROBE_OUT28_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT29_WIDTH = "1" *)
(* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *)
(* C_PROBE_OUT30_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT31_WIDTH = "1" *)
(* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *)
(* C_PROBE_OUT33_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT34_WIDTH = "1" *)
(* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *)
(* C_PROBE_OUT36_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT37_WIDTH = "1" *)
(* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *)
(* C_PROBE_OUT39_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT3_WIDTH = "1" *)
(* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *)
(* C_PROBE_OUT41_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT42_WIDTH = "1" *)
(* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *)
(* C_PROBE_OUT44_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT45_WIDTH = "1" *)
(* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *)
(* C_PROBE_OUT47_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT48_WIDTH = "1" *)
(* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *)
(* C_PROBE_OUT4_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT50_WIDTH = "1" *)
(* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *)
(* C_PROBE_OUT52_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT53_WIDTH = "1" *)
(* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *)
(* C_PROBE_OUT55_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT56_WIDTH = "1" *)
(* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *)
(* C_PROBE_OUT58_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT59_WIDTH = "1" *)
(* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *)
(* C_PROBE_OUT60_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT61_WIDTH = "1" *)
(* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *)
(* C_PROBE_OUT63_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT64_WIDTH = "1" *)
(* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *)
(* C_PROBE_OUT66_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT67_WIDTH = "1" *)
(* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *)
(* C_PROBE_OUT69_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT6_WIDTH = "1" *)
(* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *)
(* C_PROBE_OUT71_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT72_WIDTH = "1" *)
(* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *)
(* C_PROBE_OUT74_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT75_WIDTH = "1" *)
(* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *)
(* C_PROBE_OUT77_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT78_WIDTH = "1" *)
(* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *)
(* C_PROBE_OUT7_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT80_WIDTH = "1" *)
(* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *)
(* C_PROBE_OUT82_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT83_WIDTH = "1" *)
(* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *)
(* C_PROBE_OUT85_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT86_WIDTH = "1" *)
(* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *)
(* C_PROBE_OUT88_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT89_WIDTH = "1" *)
(* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *)
(* C_PROBE_OUT90_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT91_WIDTH = "1" *)
(* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *)
(* C_PROBE_OUT93_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT94_WIDTH = "1" *)
(* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *)
(* C_PROBE_OUT96_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT97_WIDTH = "1" *)
(* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *)
(* C_PROBE_OUT99_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT9_WIDTH = "1" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XLNX_HW_PROBE_INFO = "DEFAULT" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *)
(* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *)
(* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *)
(* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *)
(* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *)
(* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *)
(* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *)
(* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *)
(* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *)
(* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *)
(* syn_noprune = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio inst
(.clk(clk),
.probe_in0(probe_in0),
.probe_in1(probe_in1),
.probe_in10(1'b0),
.probe_in100(1'b0),
.probe_in101(1'b0),
.probe_in102(1'b0),
.probe_in103(1'b0),
.probe_in104(1'b0),
.probe_in105(1'b0),
.probe_in106(1'b0),
.probe_in107(1'b0),
.probe_in108(1'b0),
.probe_in109(1'b0),
.probe_in11(1'b0),
.probe_in110(1'b0),
.probe_in111(1'b0),
.probe_in112(1'b0),
.probe_in113(1'b0),
.probe_in114(1'b0),
.probe_in115(1'b0),
.probe_in116(1'b0),
.probe_in117(1'b0),
.probe_in118(1'b0),
.probe_in119(1'b0),
.probe_in12(1'b0),
.probe_in120(1'b0),
.probe_in121(1'b0),
.probe_in122(1'b0),
.probe_in123(1'b0),
.probe_in124(1'b0),
.probe_in125(1'b0),
.probe_in126(1'b0),
.probe_in127(1'b0),
.probe_in128(1'b0),
.probe_in129(1'b0),
.probe_in13(1'b0),
.probe_in130(1'b0),
.probe_in131(1'b0),
.probe_in132(1'b0),
.probe_in133(1'b0),
.probe_in134(1'b0),
.probe_in135(1'b0),
.probe_in136(1'b0),
.probe_in137(1'b0),
.probe_in138(1'b0),
.probe_in139(1'b0),
.probe_in14(1'b0),
.probe_in140(1'b0),
.probe_in141(1'b0),
.probe_in142(1'b0),
.probe_in143(1'b0),
.probe_in144(1'b0),
.probe_in145(1'b0),
.probe_in146(1'b0),
.probe_in147(1'b0),
.probe_in148(1'b0),
.probe_in149(1'b0),
.probe_in15(1'b0),
.probe_in150(1'b0),
.probe_in151(1'b0),
.probe_in152(1'b0),
.probe_in153(1'b0),
.probe_in154(1'b0),
.probe_in155(1'b0),
.probe_in156(1'b0),
.probe_in157(1'b0),
.probe_in158(1'b0),
.probe_in159(1'b0),
.probe_in16(1'b0),
.probe_in160(1'b0),
.probe_in161(1'b0),
.probe_in162(1'b0),
.probe_in163(1'b0),
.probe_in164(1'b0),
.probe_in165(1'b0),
.probe_in166(1'b0),
.probe_in167(1'b0),
.probe_in168(1'b0),
.probe_in169(1'b0),
.probe_in17(1'b0),
.probe_in170(1'b0),
.probe_in171(1'b0),
.probe_in172(1'b0),
.probe_in173(1'b0),
.probe_in174(1'b0),
.probe_in175(1'b0),
.probe_in176(1'b0),
.probe_in177(1'b0),
.probe_in178(1'b0),
.probe_in179(1'b0),
.probe_in18(1'b0),
.probe_in180(1'b0),
.probe_in181(1'b0),
.probe_in182(1'b0),
.probe_in183(1'b0),
.probe_in184(1'b0),
.probe_in185(1'b0),
.probe_in186(1'b0),
.probe_in187(1'b0),
.probe_in188(1'b0),
.probe_in189(1'b0),
.probe_in19(1'b0),
.probe_in190(1'b0),
.probe_in191(1'b0),
.probe_in192(1'b0),
.probe_in193(1'b0),
.probe_in194(1'b0),
.probe_in195(1'b0),
.probe_in196(1'b0),
.probe_in197(1'b0),
.probe_in198(1'b0),
.probe_in199(1'b0),
.probe_in2(probe_in2),
.probe_in20(1'b0),
.probe_in200(1'b0),
.probe_in201(1'b0),
.probe_in202(1'b0),
.probe_in203(1'b0),
.probe_in204(1'b0),
.probe_in205(1'b0),
.probe_in206(1'b0),
.probe_in207(1'b0),
.probe_in208(1'b0),
.probe_in209(1'b0),
.probe_in21(1'b0),
.probe_in210(1'b0),
.probe_in211(1'b0),
.probe_in212(1'b0),
.probe_in213(1'b0),
.probe_in214(1'b0),
.probe_in215(1'b0),
.probe_in216(1'b0),
.probe_in217(1'b0),
.probe_in218(1'b0),
.probe_in219(1'b0),
.probe_in22(1'b0),
.probe_in220(1'b0),
.probe_in221(1'b0),
.probe_in222(1'b0),
.probe_in223(1'b0),
.probe_in224(1'b0),
.probe_in225(1'b0),
.probe_in226(1'b0),
.probe_in227(1'b0),
.probe_in228(1'b0),
.probe_in229(1'b0),
.probe_in23(1'b0),
.probe_in230(1'b0),
.probe_in231(1'b0),
.probe_in232(1'b0),
.probe_in233(1'b0),
.probe_in234(1'b0),
.probe_in235(1'b0),
.probe_in236(1'b0),
.probe_in237(1'b0),
.probe_in238(1'b0),
.probe_in239(1'b0),
.probe_in24(1'b0),
.probe_in240(1'b0),
.probe_in241(1'b0),
.probe_in242(1'b0),
.probe_in243(1'b0),
.probe_in244(1'b0),
.probe_in245(1'b0),
.probe_in246(1'b0),
.probe_in247(1'b0),
.probe_in248(1'b0),
.probe_in249(1'b0),
.probe_in25(1'b0),
.probe_in250(1'b0),
.probe_in251(1'b0),
.probe_in252(1'b0),
.probe_in253(1'b0),
.probe_in254(1'b0),
.probe_in255(1'b0),
.probe_in26(1'b0),
.probe_in27(1'b0),
.probe_in28(1'b0),
.probe_in29(1'b0),
.probe_in3(probe_in3),
.probe_in30(1'b0),
.probe_in31(1'b0),
.probe_in32(1'b0),
.probe_in33(1'b0),
.probe_in34(1'b0),
.probe_in35(1'b0),
.probe_in36(1'b0),
.probe_in37(1'b0),
.probe_in38(1'b0),
.probe_in39(1'b0),
.probe_in4(1'b0),
.probe_in40(1'b0),
.probe_in41(1'b0),
.probe_in42(1'b0),
.probe_in43(1'b0),
.probe_in44(1'b0),
.probe_in45(1'b0),
.probe_in46(1'b0),
.probe_in47(1'b0),
.probe_in48(1'b0),
.probe_in49(1'b0),
.probe_in5(1'b0),
.probe_in50(1'b0),
.probe_in51(1'b0),
.probe_in52(1'b0),
.probe_in53(1'b0),
.probe_in54(1'b0),
.probe_in55(1'b0),
.probe_in56(1'b0),
.probe_in57(1'b0),
.probe_in58(1'b0),
.probe_in59(1'b0),
.probe_in6(1'b0),
.probe_in60(1'b0),
.probe_in61(1'b0),
.probe_in62(1'b0),
.probe_in63(1'b0),
.probe_in64(1'b0),
.probe_in65(1'b0),
.probe_in66(1'b0),
.probe_in67(1'b0),
.probe_in68(1'b0),
.probe_in69(1'b0),
.probe_in7(1'b0),
.probe_in70(1'b0),
.probe_in71(1'b0),
.probe_in72(1'b0),
.probe_in73(1'b0),
.probe_in74(1'b0),
.probe_in75(1'b0),
.probe_in76(1'b0),
.probe_in77(1'b0),
.probe_in78(1'b0),
.probe_in79(1'b0),
.probe_in8(1'b0),
.probe_in80(1'b0),
.probe_in81(1'b0),
.probe_in82(1'b0),
.probe_in83(1'b0),
.probe_in84(1'b0),
.probe_in85(1'b0),
.probe_in86(1'b0),
.probe_in87(1'b0),
.probe_in88(1'b0),
.probe_in89(1'b0),
.probe_in9(1'b0),
.probe_in90(1'b0),
.probe_in91(1'b0),
.probe_in92(1'b0),
.probe_in93(1'b0),
.probe_in94(1'b0),
.probe_in95(1'b0),
.probe_in96(1'b0),
.probe_in97(1'b0),
.probe_in98(1'b0),
.probe_in99(1'b0),
.probe_out0(NLW_inst_probe_out0_UNCONNECTED[0]),
.probe_out1(NLW_inst_probe_out1_UNCONNECTED[0]),
.probe_out10(NLW_inst_probe_out10_UNCONNECTED[0]),
.probe_out100(NLW_inst_probe_out100_UNCONNECTED[0]),
.probe_out101(NLW_inst_probe_out101_UNCONNECTED[0]),
.probe_out102(NLW_inst_probe_out102_UNCONNECTED[0]),
.probe_out103(NLW_inst_probe_out103_UNCONNECTED[0]),
.probe_out104(NLW_inst_probe_out104_UNCONNECTED[0]),
.probe_out105(NLW_inst_probe_out105_UNCONNECTED[0]),
.probe_out106(NLW_inst_probe_out106_UNCONNECTED[0]),
.probe_out107(NLW_inst_probe_out107_UNCONNECTED[0]),
.probe_out108(NLW_inst_probe_out108_UNCONNECTED[0]),
.probe_out109(NLW_inst_probe_out109_UNCONNECTED[0]),
.probe_out11(NLW_inst_probe_out11_UNCONNECTED[0]),
.probe_out110(NLW_inst_probe_out110_UNCONNECTED[0]),
.probe_out111(NLW_inst_probe_out111_UNCONNECTED[0]),
.probe_out112(NLW_inst_probe_out112_UNCONNECTED[0]),
.probe_out113(NLW_inst_probe_out113_UNCONNECTED[0]),
.probe_out114(NLW_inst_probe_out114_UNCONNECTED[0]),
.probe_out115(NLW_inst_probe_out115_UNCONNECTED[0]),
.probe_out116(NLW_inst_probe_out116_UNCONNECTED[0]),
.probe_out117(NLW_inst_probe_out117_UNCONNECTED[0]),
.probe_out118(NLW_inst_probe_out118_UNCONNECTED[0]),
.probe_out119(NLW_inst_probe_out119_UNCONNECTED[0]),
.probe_out12(NLW_inst_probe_out12_UNCONNECTED[0]),
.probe_out120(NLW_inst_probe_out120_UNCONNECTED[0]),
.probe_out121(NLW_inst_probe_out121_UNCONNECTED[0]),
.probe_out122(NLW_inst_probe_out122_UNCONNECTED[0]),
.probe_out123(NLW_inst_probe_out123_UNCONNECTED[0]),
.probe_out124(NLW_inst_probe_out124_UNCONNECTED[0]),
.probe_out125(NLW_inst_probe_out125_UNCONNECTED[0]),
.probe_out126(NLW_inst_probe_out126_UNCONNECTED[0]),
.probe_out127(NLW_inst_probe_out127_UNCONNECTED[0]),
.probe_out128(NLW_inst_probe_out128_UNCONNECTED[0]),
.probe_out129(NLW_inst_probe_out129_UNCONNECTED[0]),
.probe_out13(NLW_inst_probe_out13_UNCONNECTED[0]),
.probe_out130(NLW_inst_probe_out130_UNCONNECTED[0]),
.probe_out131(NLW_inst_probe_out131_UNCONNECTED[0]),
.probe_out132(NLW_inst_probe_out132_UNCONNECTED[0]),
.probe_out133(NLW_inst_probe_out133_UNCONNECTED[0]),
.probe_out134(NLW_inst_probe_out134_UNCONNECTED[0]),
.probe_out135(NLW_inst_probe_out135_UNCONNECTED[0]),
.probe_out136(NLW_inst_probe_out136_UNCONNECTED[0]),
.probe_out137(NLW_inst_probe_out137_UNCONNECTED[0]),
.probe_out138(NLW_inst_probe_out138_UNCONNECTED[0]),
.probe_out139(NLW_inst_probe_out139_UNCONNECTED[0]),
.probe_out14(NLW_inst_probe_out14_UNCONNECTED[0]),
.probe_out140(NLW_inst_probe_out140_UNCONNECTED[0]),
.probe_out141(NLW_inst_probe_out141_UNCONNECTED[0]),
.probe_out142(NLW_inst_probe_out142_UNCONNECTED[0]),
.probe_out143(NLW_inst_probe_out143_UNCONNECTED[0]),
.probe_out144(NLW_inst_probe_out144_UNCONNECTED[0]),
.probe_out145(NLW_inst_probe_out145_UNCONNECTED[0]),
.probe_out146(NLW_inst_probe_out146_UNCONNECTED[0]),
.probe_out147(NLW_inst_probe_out147_UNCONNECTED[0]),
.probe_out148(NLW_inst_probe_out148_UNCONNECTED[0]),
.probe_out149(NLW_inst_probe_out149_UNCONNECTED[0]),
.probe_out15(NLW_inst_probe_out15_UNCONNECTED[0]),
.probe_out150(NLW_inst_probe_out150_UNCONNECTED[0]),
.probe_out151(NLW_inst_probe_out151_UNCONNECTED[0]),
.probe_out152(NLW_inst_probe_out152_UNCONNECTED[0]),
.probe_out153(NLW_inst_probe_out153_UNCONNECTED[0]),
.probe_out154(NLW_inst_probe_out154_UNCONNECTED[0]),
.probe_out155(NLW_inst_probe_out155_UNCONNECTED[0]),
.probe_out156(NLW_inst_probe_out156_UNCONNECTED[0]),
.probe_out157(NLW_inst_probe_out157_UNCONNECTED[0]),
.probe_out158(NLW_inst_probe_out158_UNCONNECTED[0]),
.probe_out159(NLW_inst_probe_out159_UNCONNECTED[0]),
.probe_out16(NLW_inst_probe_out16_UNCONNECTED[0]),
.probe_out160(NLW_inst_probe_out160_UNCONNECTED[0]),
.probe_out161(NLW_inst_probe_out161_UNCONNECTED[0]),
.probe_out162(NLW_inst_probe_out162_UNCONNECTED[0]),
.probe_out163(NLW_inst_probe_out163_UNCONNECTED[0]),
.probe_out164(NLW_inst_probe_out164_UNCONNECTED[0]),
.probe_out165(NLW_inst_probe_out165_UNCONNECTED[0]),
.probe_out166(NLW_inst_probe_out166_UNCONNECTED[0]),
.probe_out167(NLW_inst_probe_out167_UNCONNECTED[0]),
.probe_out168(NLW_inst_probe_out168_UNCONNECTED[0]),
.probe_out169(NLW_inst_probe_out169_UNCONNECTED[0]),
.probe_out17(NLW_inst_probe_out17_UNCONNECTED[0]),
.probe_out170(NLW_inst_probe_out170_UNCONNECTED[0]),
.probe_out171(NLW_inst_probe_out171_UNCONNECTED[0]),
.probe_out172(NLW_inst_probe_out172_UNCONNECTED[0]),
.probe_out173(NLW_inst_probe_out173_UNCONNECTED[0]),
.probe_out174(NLW_inst_probe_out174_UNCONNECTED[0]),
.probe_out175(NLW_inst_probe_out175_UNCONNECTED[0]),
.probe_out176(NLW_inst_probe_out176_UNCONNECTED[0]),
.probe_out177(NLW_inst_probe_out177_UNCONNECTED[0]),
.probe_out178(NLW_inst_probe_out178_UNCONNECTED[0]),
.probe_out179(NLW_inst_probe_out179_UNCONNECTED[0]),
.probe_out18(NLW_inst_probe_out18_UNCONNECTED[0]),
.probe_out180(NLW_inst_probe_out180_UNCONNECTED[0]),
.probe_out181(NLW_inst_probe_out181_UNCONNECTED[0]),
.probe_out182(NLW_inst_probe_out182_UNCONNECTED[0]),
.probe_out183(NLW_inst_probe_out183_UNCONNECTED[0]),
.probe_out184(NLW_inst_probe_out184_UNCONNECTED[0]),
.probe_out185(NLW_inst_probe_out185_UNCONNECTED[0]),
.probe_out186(NLW_inst_probe_out186_UNCONNECTED[0]),
.probe_out187(NLW_inst_probe_out187_UNCONNECTED[0]),
.probe_out188(NLW_inst_probe_out188_UNCONNECTED[0]),
.probe_out189(NLW_inst_probe_out189_UNCONNECTED[0]),
.probe_out19(NLW_inst_probe_out19_UNCONNECTED[0]),
.probe_out190(NLW_inst_probe_out190_UNCONNECTED[0]),
.probe_out191(NLW_inst_probe_out191_UNCONNECTED[0]),
.probe_out192(NLW_inst_probe_out192_UNCONNECTED[0]),
.probe_out193(NLW_inst_probe_out193_UNCONNECTED[0]),
.probe_out194(NLW_inst_probe_out194_UNCONNECTED[0]),
.probe_out195(NLW_inst_probe_out195_UNCONNECTED[0]),
.probe_out196(NLW_inst_probe_out196_UNCONNECTED[0]),
.probe_out197(NLW_inst_probe_out197_UNCONNECTED[0]),
.probe_out198(NLW_inst_probe_out198_UNCONNECTED[0]),
.probe_out199(NLW_inst_probe_out199_UNCONNECTED[0]),
.probe_out2(NLW_inst_probe_out2_UNCONNECTED[0]),
.probe_out20(NLW_inst_probe_out20_UNCONNECTED[0]),
.probe_out200(NLW_inst_probe_out200_UNCONNECTED[0]),
.probe_out201(NLW_inst_probe_out201_UNCONNECTED[0]),
.probe_out202(NLW_inst_probe_out202_UNCONNECTED[0]),
.probe_out203(NLW_inst_probe_out203_UNCONNECTED[0]),
.probe_out204(NLW_inst_probe_out204_UNCONNECTED[0]),
.probe_out205(NLW_inst_probe_out205_UNCONNECTED[0]),
.probe_out206(NLW_inst_probe_out206_UNCONNECTED[0]),
.probe_out207(NLW_inst_probe_out207_UNCONNECTED[0]),
.probe_out208(NLW_inst_probe_out208_UNCONNECTED[0]),
.probe_out209(NLW_inst_probe_out209_UNCONNECTED[0]),
.probe_out21(NLW_inst_probe_out21_UNCONNECTED[0]),
.probe_out210(NLW_inst_probe_out210_UNCONNECTED[0]),
.probe_out211(NLW_inst_probe_out211_UNCONNECTED[0]),
.probe_out212(NLW_inst_probe_out212_UNCONNECTED[0]),
.probe_out213(NLW_inst_probe_out213_UNCONNECTED[0]),
.probe_out214(NLW_inst_probe_out214_UNCONNECTED[0]),
.probe_out215(NLW_inst_probe_out215_UNCONNECTED[0]),
.probe_out216(NLW_inst_probe_out216_UNCONNECTED[0]),
.probe_out217(NLW_inst_probe_out217_UNCONNECTED[0]),
.probe_out218(NLW_inst_probe_out218_UNCONNECTED[0]),
.probe_out219(NLW_inst_probe_out219_UNCONNECTED[0]),
.probe_out22(NLW_inst_probe_out22_UNCONNECTED[0]),
.probe_out220(NLW_inst_probe_out220_UNCONNECTED[0]),
.probe_out221(NLW_inst_probe_out221_UNCONNECTED[0]),
.probe_out222(NLW_inst_probe_out222_UNCONNECTED[0]),
.probe_out223(NLW_inst_probe_out223_UNCONNECTED[0]),
.probe_out224(NLW_inst_probe_out224_UNCONNECTED[0]),
.probe_out225(NLW_inst_probe_out225_UNCONNECTED[0]),
.probe_out226(NLW_inst_probe_out226_UNCONNECTED[0]),
.probe_out227(NLW_inst_probe_out227_UNCONNECTED[0]),
.probe_out228(NLW_inst_probe_out228_UNCONNECTED[0]),
.probe_out229(NLW_inst_probe_out229_UNCONNECTED[0]),
.probe_out23(NLW_inst_probe_out23_UNCONNECTED[0]),
.probe_out230(NLW_inst_probe_out230_UNCONNECTED[0]),
.probe_out231(NLW_inst_probe_out231_UNCONNECTED[0]),
.probe_out232(NLW_inst_probe_out232_UNCONNECTED[0]),
.probe_out233(NLW_inst_probe_out233_UNCONNECTED[0]),
.probe_out234(NLW_inst_probe_out234_UNCONNECTED[0]),
.probe_out235(NLW_inst_probe_out235_UNCONNECTED[0]),
.probe_out236(NLW_inst_probe_out236_UNCONNECTED[0]),
.probe_out237(NLW_inst_probe_out237_UNCONNECTED[0]),
.probe_out238(NLW_inst_probe_out238_UNCONNECTED[0]),
.probe_out239(NLW_inst_probe_out239_UNCONNECTED[0]),
.probe_out24(NLW_inst_probe_out24_UNCONNECTED[0]),
.probe_out240(NLW_inst_probe_out240_UNCONNECTED[0]),
.probe_out241(NLW_inst_probe_out241_UNCONNECTED[0]),
.probe_out242(NLW_inst_probe_out242_UNCONNECTED[0]),
.probe_out243(NLW_inst_probe_out243_UNCONNECTED[0]),
.probe_out244(NLW_inst_probe_out244_UNCONNECTED[0]),
.probe_out245(NLW_inst_probe_out245_UNCONNECTED[0]),
.probe_out246(NLW_inst_probe_out246_UNCONNECTED[0]),
.probe_out247(NLW_inst_probe_out247_UNCONNECTED[0]),
.probe_out248(NLW_inst_probe_out248_UNCONNECTED[0]),
.probe_out249(NLW_inst_probe_out249_UNCONNECTED[0]),
.probe_out25(NLW_inst_probe_out25_UNCONNECTED[0]),
.probe_out250(NLW_inst_probe_out250_UNCONNECTED[0]),
.probe_out251(NLW_inst_probe_out251_UNCONNECTED[0]),
.probe_out252(NLW_inst_probe_out252_UNCONNECTED[0]),
.probe_out253(NLW_inst_probe_out253_UNCONNECTED[0]),
.probe_out254(NLW_inst_probe_out254_UNCONNECTED[0]),
.probe_out255(NLW_inst_probe_out255_UNCONNECTED[0]),
.probe_out26(NLW_inst_probe_out26_UNCONNECTED[0]),
.probe_out27(NLW_inst_probe_out27_UNCONNECTED[0]),
.probe_out28(NLW_inst_probe_out28_UNCONNECTED[0]),
.probe_out29(NLW_inst_probe_out29_UNCONNECTED[0]),
.probe_out3(NLW_inst_probe_out3_UNCONNECTED[0]),
.probe_out30(NLW_inst_probe_out30_UNCONNECTED[0]),
.probe_out31(NLW_inst_probe_out31_UNCONNECTED[0]),
.probe_out32(NLW_inst_probe_out32_UNCONNECTED[0]),
.probe_out33(NLW_inst_probe_out33_UNCONNECTED[0]),
.probe_out34(NLW_inst_probe_out34_UNCONNECTED[0]),
.probe_out35(NLW_inst_probe_out35_UNCONNECTED[0]),
.probe_out36(NLW_inst_probe_out36_UNCONNECTED[0]),
.probe_out37(NLW_inst_probe_out37_UNCONNECTED[0]),
.probe_out38(NLW_inst_probe_out38_UNCONNECTED[0]),
.probe_out39(NLW_inst_probe_out39_UNCONNECTED[0]),
.probe_out4(NLW_inst_probe_out4_UNCONNECTED[0]),
.probe_out40(NLW_inst_probe_out40_UNCONNECTED[0]),
.probe_out41(NLW_inst_probe_out41_UNCONNECTED[0]),
.probe_out42(NLW_inst_probe_out42_UNCONNECTED[0]),
.probe_out43(NLW_inst_probe_out43_UNCONNECTED[0]),
.probe_out44(NLW_inst_probe_out44_UNCONNECTED[0]),
.probe_out45(NLW_inst_probe_out45_UNCONNECTED[0]),
.probe_out46(NLW_inst_probe_out46_UNCONNECTED[0]),
.probe_out47(NLW_inst_probe_out47_UNCONNECTED[0]),
.probe_out48(NLW_inst_probe_out48_UNCONNECTED[0]),
.probe_out49(NLW_inst_probe_out49_UNCONNECTED[0]),
.probe_out5(NLW_inst_probe_out5_UNCONNECTED[0]),
.probe_out50(NLW_inst_probe_out50_UNCONNECTED[0]),
.probe_out51(NLW_inst_probe_out51_UNCONNECTED[0]),
.probe_out52(NLW_inst_probe_out52_UNCONNECTED[0]),
.probe_out53(NLW_inst_probe_out53_UNCONNECTED[0]),
.probe_out54(NLW_inst_probe_out54_UNCONNECTED[0]),
.probe_out55(NLW_inst_probe_out55_UNCONNECTED[0]),
.probe_out56(NLW_inst_probe_out56_UNCONNECTED[0]),
.probe_out57(NLW_inst_probe_out57_UNCONNECTED[0]),
.probe_out58(NLW_inst_probe_out58_UNCONNECTED[0]),
.probe_out59(NLW_inst_probe_out59_UNCONNECTED[0]),
.probe_out6(NLW_inst_probe_out6_UNCONNECTED[0]),
.probe_out60(NLW_inst_probe_out60_UNCONNECTED[0]),
.probe_out61(NLW_inst_probe_out61_UNCONNECTED[0]),
.probe_out62(NLW_inst_probe_out62_UNCONNECTED[0]),
.probe_out63(NLW_inst_probe_out63_UNCONNECTED[0]),
.probe_out64(NLW_inst_probe_out64_UNCONNECTED[0]),
.probe_out65(NLW_inst_probe_out65_UNCONNECTED[0]),
.probe_out66(NLW_inst_probe_out66_UNCONNECTED[0]),
.probe_out67(NLW_inst_probe_out67_UNCONNECTED[0]),
.probe_out68(NLW_inst_probe_out68_UNCONNECTED[0]),
.probe_out69(NLW_inst_probe_out69_UNCONNECTED[0]),
.probe_out7(NLW_inst_probe_out7_UNCONNECTED[0]),
.probe_out70(NLW_inst_probe_out70_UNCONNECTED[0]),
.probe_out71(NLW_inst_probe_out71_UNCONNECTED[0]),
.probe_out72(NLW_inst_probe_out72_UNCONNECTED[0]),
.probe_out73(NLW_inst_probe_out73_UNCONNECTED[0]),
.probe_out74(NLW_inst_probe_out74_UNCONNECTED[0]),
.probe_out75(NLW_inst_probe_out75_UNCONNECTED[0]),
.probe_out76(NLW_inst_probe_out76_UNCONNECTED[0]),
.probe_out77(NLW_inst_probe_out77_UNCONNECTED[0]),
.probe_out78(NLW_inst_probe_out78_UNCONNECTED[0]),
.probe_out79(NLW_inst_probe_out79_UNCONNECTED[0]),
.probe_out8(NLW_inst_probe_out8_UNCONNECTED[0]),
.probe_out80(NLW_inst_probe_out80_UNCONNECTED[0]),
.probe_out81(NLW_inst_probe_out81_UNCONNECTED[0]),
.probe_out82(NLW_inst_probe_out82_UNCONNECTED[0]),
.probe_out83(NLW_inst_probe_out83_UNCONNECTED[0]),
.probe_out84(NLW_inst_probe_out84_UNCONNECTED[0]),
.probe_out85(NLW_inst_probe_out85_UNCONNECTED[0]),
.probe_out86(NLW_inst_probe_out86_UNCONNECTED[0]),
.probe_out87(NLW_inst_probe_out87_UNCONNECTED[0]),
.probe_out88(NLW_inst_probe_out88_UNCONNECTED[0]),
.probe_out89(NLW_inst_probe_out89_UNCONNECTED[0]),
.probe_out9(NLW_inst_probe_out9_UNCONNECTED[0]),
.probe_out90(NLW_inst_probe_out90_UNCONNECTED[0]),
.probe_out91(NLW_inst_probe_out91_UNCONNECTED[0]),
.probe_out92(NLW_inst_probe_out92_UNCONNECTED[0]),
.probe_out93(NLW_inst_probe_out93_UNCONNECTED[0]),
.probe_out94(NLW_inst_probe_out94_UNCONNECTED[0]),
.probe_out95(NLW_inst_probe_out95_UNCONNECTED[0]),
.probe_out96(NLW_inst_probe_out96_UNCONNECTED[0]),
.probe_out97(NLW_inst_probe_out97_UNCONNECTED[0]),
.probe_out98(NLW_inst_probe_out98_UNCONNECTED[0]),
.probe_out99(NLW_inst_probe_out99_UNCONNECTED[0]),
.sl_iport0({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.sl_oport0(NLW_inst_sl_oport0_UNCONNECTED[16:0]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder
(s_drdy_i,
\wr_en_reg[4]_0 ,
\wr_en_reg[4]_1 ,
\wr_en_reg[4]_2 ,
E,
s_do_i,
s_rst_o,
Q,
out,
s_daddr_o,
s_dwe_o,
s_den_o,
\Bus_Data_out_reg[11] );
output s_drdy_i;
output \wr_en_reg[4]_0 ;
output \wr_en_reg[4]_1 ;
output \wr_en_reg[4]_2 ;
output [0:0]E;
output [15:0]s_do_i;
input s_rst_o;
input [15:0]Q;
input out;
input [16:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [11:0]\Bus_Data_out_reg[11] ;
wire [11:0]\Bus_Data_out_reg[11] ;
wire [0:0]E;
wire Hold_probe_in;
wire [15:0]Q;
wire clear_int;
wire committ_int;
wire [15:0]data_info_probe_in__67;
wire int_cnt_rst;
wire out;
wire [15:0]probe_out_modified;
wire rd_en_p1;
wire rd_en_p2;
wire [16:0]s_daddr_o;
wire s_den_o;
wire [15:0]s_do_i;
wire s_drdy_i;
wire s_dwe_o;
wire s_rst_o;
wire wr_control_reg;
wire \wr_en[2]_i_1_n_0 ;
wire \wr_en[2]_i_2_n_0 ;
wire \wr_en[4]_i_1_n_0 ;
wire \wr_en[4]_i_6_n_0 ;
wire \wr_en_reg[4]_0 ;
wire \wr_en_reg[4]_1 ;
wire \wr_en_reg[4]_2 ;
wire wr_probe_out_modified;
wire [2:0]xsdb_addr_2_0_p1;
wire [2:0]xsdb_addr_2_0_p2;
wire xsdb_addr_8_p1;
wire xsdb_addr_8_p2;
wire xsdb_drdy_i_1_n_0;
wire xsdb_rd;
wire xsdb_wr;
LUT6 #(
.INIT(64'hAF00AF000FC000C0))
\Bus_data_out[0]_i_1
(.I0(\Bus_Data_out_reg[11] [0]),
.I1(probe_out_modified[0]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(committ_int),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[0]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[10]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[10]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [10]),
.O(data_info_probe_in__67[10]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[11]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[11]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [11]),
.O(data_info_probe_in__67[11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[12]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[12]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[13]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[13]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[13]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[14]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[14]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[14]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h0020))
\Bus_data_out[15]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[1]),
.I2(probe_out_modified[15]),
.I3(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[15]));
LUT6 #(
.INIT(64'hA0000FC0A00000C0))
\Bus_data_out[1]_i_1
(.I0(\Bus_Data_out_reg[11] [1]),
.I1(probe_out_modified[1]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(xsdb_addr_2_0_p2[0]),
.I5(clear_int),
.O(data_info_probe_in__67[1]));
LUT6 #(
.INIT(64'hA0A000000F00CFCF))
\Bus_data_out[2]_i_1
(.I0(\Bus_Data_out_reg[11] [2]),
.I1(probe_out_modified[2]),
.I2(xsdb_addr_2_0_p2[2]),
.I3(int_cnt_rst),
.I4(xsdb_addr_2_0_p2[1]),
.I5(xsdb_addr_2_0_p2[0]),
.O(data_info_probe_in__67[2]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[3]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[3]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [3]),
.O(data_info_probe_in__67[3]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[4]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[4]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [4]),
.O(data_info_probe_in__67[4]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[5]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[5]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [5]),
.O(data_info_probe_in__67[5]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[6]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[6]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [6]),
.O(data_info_probe_in__67[6]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[7]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[7]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [7]),
.O(data_info_probe_in__67[7]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[8]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[8]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [8]),
.O(data_info_probe_in__67[8]));
LUT5 #(
.INIT(32'h88200020))
\Bus_data_out[9]_i_1
(.I0(xsdb_addr_2_0_p2[2]),
.I1(xsdb_addr_2_0_p2[0]),
.I2(probe_out_modified[9]),
.I3(xsdb_addr_2_0_p2[1]),
.I4(\Bus_Data_out_reg[11] [9]),
.O(data_info_probe_in__67[9]));
FDRE \Bus_data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[0]),
.Q(s_do_i[0]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[10]),
.Q(s_do_i[10]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[11]),
.Q(s_do_i[11]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[12]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[12]),
.Q(s_do_i[12]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[13]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[13]),
.Q(s_do_i[13]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[14]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[14]),
.Q(s_do_i[14]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[15]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[15]),
.Q(s_do_i[15]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[1]),
.Q(s_do_i[1]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[2]),
.Q(s_do_i[2]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[3]),
.Q(s_do_i[3]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[4]),
.Q(s_do_i[4]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[5]),
.Q(s_do_i[5]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[6]),
.Q(s_do_i[6]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[7]),
.Q(s_do_i[7]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[8]),
.Q(s_do_i[8]),
.R(xsdb_addr_8_p2));
FDRE \Bus_data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(data_info_probe_in__67[9]),
.Q(s_do_i[9]),
.R(xsdb_addr_8_p2));
FDRE Hold_probe_in_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[3]),
.Q(Hold_probe_in),
.R(s_rst_o));
FDRE clear_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[1]),
.Q(clear_int),
.R(s_rst_o));
FDRE committ_int_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[0]),
.Q(committ_int),
.R(s_rst_o));
FDRE int_cnt_rst_reg
(.C(out),
.CE(wr_control_reg),
.D(Q[2]),
.Q(int_cnt_rst),
.R(s_rst_o));
LUT1 #(
.INIT(2'h1))
\probe_in_reg[3]_i_1
(.I0(Hold_probe_in),
.O(E));
FDRE \probe_out_modified_reg[0]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[0]),
.Q(probe_out_modified[0]),
.R(clear_int));
FDRE \probe_out_modified_reg[10]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[10]),
.Q(probe_out_modified[10]),
.R(clear_int));
FDRE \probe_out_modified_reg[11]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[11]),
.Q(probe_out_modified[11]),
.R(clear_int));
FDRE \probe_out_modified_reg[12]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[12]),
.Q(probe_out_modified[12]),
.R(clear_int));
FDRE \probe_out_modified_reg[13]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[13]),
.Q(probe_out_modified[13]),
.R(clear_int));
FDRE \probe_out_modified_reg[14]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[14]),
.Q(probe_out_modified[14]),
.R(clear_int));
FDRE \probe_out_modified_reg[15]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[15]),
.Q(probe_out_modified[15]),
.R(clear_int));
FDRE \probe_out_modified_reg[1]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[1]),
.Q(probe_out_modified[1]),
.R(clear_int));
FDRE \probe_out_modified_reg[2]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[2]),
.Q(probe_out_modified[2]),
.R(clear_int));
FDRE \probe_out_modified_reg[3]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[3]),
.Q(probe_out_modified[3]),
.R(clear_int));
FDRE \probe_out_modified_reg[4]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[4]),
.Q(probe_out_modified[4]),
.R(clear_int));
FDRE \probe_out_modified_reg[5]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[5]),
.Q(probe_out_modified[5]),
.R(clear_int));
FDRE \probe_out_modified_reg[6]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[6]),
.Q(probe_out_modified[6]),
.R(clear_int));
FDRE \probe_out_modified_reg[7]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[7]),
.Q(probe_out_modified[7]),
.R(clear_int));
FDRE \probe_out_modified_reg[8]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[8]),
.Q(probe_out_modified[8]),
.R(clear_int));
FDRE \probe_out_modified_reg[9]
(.C(out),
.CE(wr_probe_out_modified),
.D(Q[9]),
.Q(probe_out_modified[9]),
.R(clear_int));
LUT2 #(
.INIT(4'h2))
rd_en_p1_i_1
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_rd));
FDRE rd_en_p1_reg
(.C(out),
.CE(1'b1),
.D(xsdb_rd),
.Q(rd_en_p1),
.R(s_rst_o));
FDRE rd_en_p2_reg
(.C(out),
.CE(1'b1),
.D(rd_en_p1),
.Q(rd_en_p2),
.R(s_rst_o));
LUT6 #(
.INIT(64'h0000000000000002))
\wr_en[2]_i_1
(.I0(xsdb_wr),
.I1(s_daddr_o[2]),
.I2(\wr_en_reg[4]_0 ),
.I3(\wr_en_reg[4]_2 ),
.I4(\wr_en_reg[4]_1 ),
.I5(\wr_en[2]_i_2_n_0 ),
.O(\wr_en[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hB))
\wr_en[2]_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000020000))
\wr_en[4]_i_1
(.I0(xsdb_wr),
.I1(\wr_en_reg[4]_0 ),
.I2(\wr_en_reg[4]_2 ),
.I3(\wr_en_reg[4]_1 ),
.I4(s_daddr_o[2]),
.I5(\wr_en[4]_i_6_n_0 ),
.O(\wr_en[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h8))
\wr_en[4]_i_2
(.I0(s_den_o),
.I1(s_dwe_o),
.O(xsdb_wr));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\wr_en[4]_i_3
(.I0(s_daddr_o[15]),
.I1(s_daddr_o[16]),
.I2(s_daddr_o[13]),
.I3(s_daddr_o[14]),
.I4(s_daddr_o[4]),
.I5(s_daddr_o[3]),
.O(\wr_en_reg[4]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_4
(.I0(s_daddr_o[6]),
.I1(s_daddr_o[5]),
.I2(s_daddr_o[8]),
.I3(s_daddr_o[7]),
.O(\wr_en_reg[4]_2 ));
LUT4 #(
.INIT(16'hFFFE))
\wr_en[4]_i_5
(.I0(s_daddr_o[10]),
.I1(s_daddr_o[9]),
.I2(s_daddr_o[12]),
.I3(s_daddr_o[11]),
.O(\wr_en_reg[4]_1 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'hE))
\wr_en[4]_i_6
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.O(\wr_en[4]_i_6_n_0 ));
FDRE \wr_en_reg[2]
(.C(out),
.CE(1'b1),
.D(\wr_en[2]_i_1_n_0 ),
.Q(wr_control_reg),
.R(1'b0));
FDRE \wr_en_reg[4]
(.C(out),
.CE(1'b1),
.D(\wr_en[4]_i_1_n_0 ),
.Q(wr_probe_out_modified),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[0]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[0]),
.Q(xsdb_addr_2_0_p1[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[1]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[1]),
.Q(xsdb_addr_2_0_p1[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p1_reg[2]
(.C(out),
.CE(1'b1),
.D(s_daddr_o[2]),
.Q(xsdb_addr_2_0_p1[2]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[0]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[0]),
.Q(xsdb_addr_2_0_p2[0]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[1]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[1]),
.Q(xsdb_addr_2_0_p2[1]),
.R(1'b0));
FDRE \xsdb_addr_2_0_p2_reg[2]
(.C(out),
.CE(1'b1),
.D(xsdb_addr_2_0_p1[2]),
.Q(xsdb_addr_2_0_p2[2]),
.R(1'b0));
FDRE xsdb_addr_8_p1_reg
(.C(out),
.CE(1'b1),
.D(s_daddr_o[8]),
.Q(xsdb_addr_8_p1),
.R(1'b0));
FDRE xsdb_addr_8_p2_reg
(.C(out),
.CE(1'b1),
.D(xsdb_addr_8_p1),
.Q(xsdb_addr_8_p2),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF8))
xsdb_drdy_i_1
(.I0(s_dwe_o),
.I1(s_den_o),
.I2(rd_en_p2),
.O(xsdb_drdy_i_1_n_0));
FDRE xsdb_drdy_reg
(.C(out),
.CE(1'b1),
.D(xsdb_drdy_i_1_n_0),
.Q(s_drdy_i),
.R(s_rst_o));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one
(Q,
out,
\wr_en[4]_i_3 ,
\wr_en[4]_i_4 ,
\wr_en[4]_i_5 ,
s_daddr_o,
s_dwe_o,
s_den_o,
E,
D,
clk,
s_rst_o);
output [11:0]Q;
input out;
input \wr_en[4]_i_3 ;
input \wr_en[4]_i_4 ;
input \wr_en[4]_i_5 ;
input [2:0]s_daddr_o;
input s_dwe_o;
input s_den_o;
input [0:0]E;
input [3:0]D;
input clk;
input s_rst_o;
wire [3:0]D;
wire \DECODER_INST/rd_en_int_7 ;
wire [0:0]E;
wire [11:0]Q;
wire Read_int;
wire Read_int_i_2_n_0;
wire clk;
(* async_reg = "true" *) wire [3:0]data_int_sync1;
(* async_reg = "true" *) wire [3:0]data_int_sync2;
wire \dn_activity[0]_i_1_n_0 ;
wire \dn_activity[1]_i_1_n_0 ;
wire \dn_activity[2]_i_1_n_0 ;
wire \dn_activity[3]_i_1_n_0 ;
wire \dn_activity_reg_n_0_[0] ;
wire \dn_activity_reg_n_0_[3] ;
wire out;
wire p_6_in;
wire p_9_in;
(* DONT_TOUCH *) wire [3:0]probe_in_reg;
(* MAX_FANOUT = "200" *) (* RTL_MAX_FANOUT = "found" *) wire read_done;
wire read_done_i_1_n_0;
wire [2:0]s_daddr_o;
wire s_den_o;
wire s_dwe_o;
wire s_rst_o;
wire \up_activity[0]_i_1_n_0 ;
wire \up_activity[1]_i_1_n_0 ;
wire \up_activity[2]_i_1_n_0 ;
wire \up_activity[3]_i_1_n_0 ;
wire \up_activity_reg_n_0_[0] ;
wire \up_activity_reg_n_0_[1] ;
wire \up_activity_reg_n_0_[2] ;
wire \up_activity_reg_n_0_[3] ;
wire \wr_en[4]_i_3 ;
wire \wr_en[4]_i_4 ;
wire \wr_en[4]_i_5 ;
FDRE \Bus_Data_out_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \Bus_Data_out_reg[10]
(.C(out),
.CE(1'b1),
.D(p_9_in),
.Q(Q[10]),
.R(1'b0));
FDRE \Bus_Data_out_reg[11]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[3] ),
.Q(Q[11]),
.R(1'b0));
FDRE \Bus_Data_out_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \Bus_Data_out_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \Bus_Data_out_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync2[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \Bus_Data_out_reg[4]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[0] ),
.Q(Q[4]),
.R(1'b0));
FDRE \Bus_Data_out_reg[5]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[1] ),
.Q(Q[5]),
.R(1'b0));
FDRE \Bus_Data_out_reg[6]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[2] ),
.Q(Q[6]),
.R(1'b0));
FDRE \Bus_Data_out_reg[7]
(.C(out),
.CE(1'b1),
.D(\up_activity_reg_n_0_[3] ),
.Q(Q[7]),
.R(1'b0));
FDRE \Bus_Data_out_reg[8]
(.C(out),
.CE(1'b1),
.D(\dn_activity_reg_n_0_[0] ),
.Q(Q[8]),
.R(1'b0));
FDRE \Bus_Data_out_reg[9]
(.C(out),
.CE(1'b1),
.D(p_6_in),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'h0002))
Read_int_i_1
(.I0(Read_int_i_2_n_0),
.I1(\wr_en[4]_i_3 ),
.I2(\wr_en[4]_i_4 ),
.I3(\wr_en[4]_i_5 ),
.O(\DECODER_INST/rd_en_int_7 ));
LUT5 #(
.INIT(32'h00800000))
Read_int_i_2
(.I0(s_daddr_o[0]),
.I1(s_daddr_o[1]),
.I2(s_daddr_o[2]),
.I3(s_dwe_o),
.I4(s_den_o),
.O(Read_int_i_2_n_0));
FDRE Read_int_reg
(.C(out),
.CE(1'b1),
.D(\DECODER_INST/rd_en_int_7 ),
.Q(Read_int),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[0]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[0]),
.Q(data_int_sync1[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[1]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[1]),
.Q(data_int_sync1[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[2]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[2]),
.Q(data_int_sync1[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync1_reg[3]
(.C(out),
.CE(1'b1),
.D(probe_in_reg[3]),
.Q(data_int_sync1[3]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[0]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[0]),
.Q(data_int_sync2[0]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[1]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[1]),
.Q(data_int_sync2[1]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[2]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[2]),
.Q(data_int_sync2[2]),
.R(1'b0));
(* ASYNC_REG *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\data_int_sync2_reg[3]
(.C(out),
.CE(1'b1),
.D(data_int_sync1[3]),
.Q(data_int_sync2[3]),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\dn_activity[0]_i_1
(.I0(\dn_activity_reg_n_0_[0] ),
.I1(data_int_sync1[0]),
.I2(data_int_sync2[0]),
.O(\dn_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[1]_i_1
(.I0(p_6_in),
.I1(data_int_sync1[1]),
.I2(data_int_sync2[1]),
.O(\dn_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[2]_i_1
(.I0(p_9_in),
.I1(data_int_sync1[2]),
.I2(data_int_sync2[2]),
.O(\dn_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\dn_activity[3]_i_1
(.I0(\dn_activity_reg_n_0_[3] ),
.I1(data_int_sync1[3]),
.I2(data_int_sync2[3]),
.O(\dn_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\dn_activity[0]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\dn_activity[1]_i_1_n_0 ),
.Q(p_6_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\dn_activity[2]_i_1_n_0 ),
.Q(p_9_in),
.R(read_done));
FDRE #(
.INIT(1'b0))
\dn_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\dn_activity[3]_i_1_n_0 ),
.Q(\dn_activity_reg_n_0_[3] ),
.R(read_done));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[0]
(.C(clk),
.CE(E),
.D(D[0]),
.Q(probe_in_reg[0]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[1]
(.C(clk),
.CE(E),
.D(D[1]),
.Q(probe_in_reg[1]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[2]
(.C(clk),
.CE(E),
.D(D[2]),
.Q(probe_in_reg[2]),
.R(1'b0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\probe_in_reg_reg[3]
(.C(clk),
.CE(E),
.D(D[3]),
.Q(probe_in_reg[3]),
.R(1'b0));
LUT3 #(
.INIT(8'h02))
read_done_i_1
(.I0(Read_int),
.I1(read_done),
.I2(s_rst_o),
.O(read_done_i_1_n_0));
(* RTL_MAX_FANOUT = "found" *)
FDRE read_done_reg
(.C(out),
.CE(1'b1),
.D(read_done_i_1_n_0),
.Q(read_done),
.R(1'b0));
LUT3 #(
.INIT(8'hBA))
\up_activity[0]_i_1
(.I0(\up_activity_reg_n_0_[0] ),
.I1(data_int_sync2[0]),
.I2(data_int_sync1[0]),
.O(\up_activity[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[1]_i_1
(.I0(\up_activity_reg_n_0_[1] ),
.I1(data_int_sync2[1]),
.I2(data_int_sync1[1]),
.O(\up_activity[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[2]_i_1
(.I0(\up_activity_reg_n_0_[2] ),
.I1(data_int_sync2[2]),
.I2(data_int_sync1[2]),
.O(\up_activity[2]_i_1_n_0 ));
LUT3 #(
.INIT(8'hBA))
\up_activity[3]_i_1
(.I0(\up_activity_reg_n_0_[3] ),
.I1(data_int_sync2[3]),
.I2(data_int_sync1[3]),
.O(\up_activity[3]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\up_activity_reg[0]
(.C(out),
.CE(1'b1),
.D(\up_activity[0]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[0] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[1]
(.C(out),
.CE(1'b1),
.D(\up_activity[1]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[1] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[2]
(.C(out),
.CE(1'b1),
.D(\up_activity[2]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[2] ),
.R(read_done));
FDRE #(
.INIT(1'b0))
\up_activity_reg[3]
(.C(out),
.CE(1'b1),
.D(\up_activity[3]_i_1_n_0 ),
.Q(\up_activity_reg_n_0_[3] ),
.R(read_done));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_BUS_ADDR_WIDTH = "17" *) (* C_BUS_DATA_WIDTH = "16" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_ALPHA_VER = "97" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_EN_PROBE_IN_ACTIVITY = "1" *) (* C_EN_SYNCHRONIZATION = "1" *)
(* C_MAJOR_VERSION = "2013" *) (* C_MAX_NUM_PROBE = "256" *) (* C_MAX_WIDTH_PER_PROBE = "256" *)
(* C_MINOR_VERSION = "1" *) (* C_NEXT_SLAVE = "0" *) (* C_NUM_PROBE_IN = "4" *)
(* C_NUM_PROBE_OUT = "0" *) (* C_PIPE_IFACE = "0" *) (* C_PROBE_IN0_WIDTH = "1" *)
(* C_PROBE_IN100_WIDTH = "1" *) (* C_PROBE_IN101_WIDTH = "1" *) (* C_PROBE_IN102_WIDTH = "1" *)
(* C_PROBE_IN103_WIDTH = "1" *) (* C_PROBE_IN104_WIDTH = "1" *) (* C_PROBE_IN105_WIDTH = "1" *)
(* C_PROBE_IN106_WIDTH = "1" *) (* C_PROBE_IN107_WIDTH = "1" *) (* C_PROBE_IN108_WIDTH = "1" *)
(* C_PROBE_IN109_WIDTH = "1" *) (* C_PROBE_IN10_WIDTH = "1" *) (* C_PROBE_IN110_WIDTH = "1" *)
(* C_PROBE_IN111_WIDTH = "1" *) (* C_PROBE_IN112_WIDTH = "1" *) (* C_PROBE_IN113_WIDTH = "1" *)
(* C_PROBE_IN114_WIDTH = "1" *) (* C_PROBE_IN115_WIDTH = "1" *) (* C_PROBE_IN116_WIDTH = "1" *)
(* C_PROBE_IN117_WIDTH = "1" *) (* C_PROBE_IN118_WIDTH = "1" *) (* C_PROBE_IN119_WIDTH = "1" *)
(* C_PROBE_IN11_WIDTH = "1" *) (* C_PROBE_IN120_WIDTH = "1" *) (* C_PROBE_IN121_WIDTH = "1" *)
(* C_PROBE_IN122_WIDTH = "1" *) (* C_PROBE_IN123_WIDTH = "1" *) (* C_PROBE_IN124_WIDTH = "1" *)
(* C_PROBE_IN125_WIDTH = "1" *) (* C_PROBE_IN126_WIDTH = "1" *) (* C_PROBE_IN127_WIDTH = "1" *)
(* C_PROBE_IN128_WIDTH = "1" *) (* C_PROBE_IN129_WIDTH = "1" *) (* C_PROBE_IN12_WIDTH = "1" *)
(* C_PROBE_IN130_WIDTH = "1" *) (* C_PROBE_IN131_WIDTH = "1" *) (* C_PROBE_IN132_WIDTH = "1" *)
(* C_PROBE_IN133_WIDTH = "1" *) (* C_PROBE_IN134_WIDTH = "1" *) (* C_PROBE_IN135_WIDTH = "1" *)
(* C_PROBE_IN136_WIDTH = "1" *) (* C_PROBE_IN137_WIDTH = "1" *) (* C_PROBE_IN138_WIDTH = "1" *)
(* C_PROBE_IN139_WIDTH = "1" *) (* C_PROBE_IN13_WIDTH = "1" *) (* C_PROBE_IN140_WIDTH = "1" *)
(* C_PROBE_IN141_WIDTH = "1" *) (* C_PROBE_IN142_WIDTH = "1" *) (* C_PROBE_IN143_WIDTH = "1" *)
(* C_PROBE_IN144_WIDTH = "1" *) (* C_PROBE_IN145_WIDTH = "1" *) (* C_PROBE_IN146_WIDTH = "1" *)
(* C_PROBE_IN147_WIDTH = "1" *) (* C_PROBE_IN148_WIDTH = "1" *) (* C_PROBE_IN149_WIDTH = "1" *)
(* C_PROBE_IN14_WIDTH = "1" *) (* C_PROBE_IN150_WIDTH = "1" *) (* C_PROBE_IN151_WIDTH = "1" *)
(* C_PROBE_IN152_WIDTH = "1" *) (* C_PROBE_IN153_WIDTH = "1" *) (* C_PROBE_IN154_WIDTH = "1" *)
(* C_PROBE_IN155_WIDTH = "1" *) (* C_PROBE_IN156_WIDTH = "1" *) (* C_PROBE_IN157_WIDTH = "1" *)
(* C_PROBE_IN158_WIDTH = "1" *) (* C_PROBE_IN159_WIDTH = "1" *) (* C_PROBE_IN15_WIDTH = "1" *)
(* C_PROBE_IN160_WIDTH = "1" *) (* C_PROBE_IN161_WIDTH = "1" *) (* C_PROBE_IN162_WIDTH = "1" *)
(* C_PROBE_IN163_WIDTH = "1" *) (* C_PROBE_IN164_WIDTH = "1" *) (* C_PROBE_IN165_WIDTH = "1" *)
(* C_PROBE_IN166_WIDTH = "1" *) (* C_PROBE_IN167_WIDTH = "1" *) (* C_PROBE_IN168_WIDTH = "1" *)
(* C_PROBE_IN169_WIDTH = "1" *) (* C_PROBE_IN16_WIDTH = "1" *) (* C_PROBE_IN170_WIDTH = "1" *)
(* C_PROBE_IN171_WIDTH = "1" *) (* C_PROBE_IN172_WIDTH = "1" *) (* C_PROBE_IN173_WIDTH = "1" *)
(* C_PROBE_IN174_WIDTH = "1" *) (* C_PROBE_IN175_WIDTH = "1" *) (* C_PROBE_IN176_WIDTH = "1" *)
(* C_PROBE_IN177_WIDTH = "1" *) (* C_PROBE_IN178_WIDTH = "1" *) (* C_PROBE_IN179_WIDTH = "1" *)
(* C_PROBE_IN17_WIDTH = "1" *) (* C_PROBE_IN180_WIDTH = "1" *) (* C_PROBE_IN181_WIDTH = "1" *)
(* C_PROBE_IN182_WIDTH = "1" *) (* C_PROBE_IN183_WIDTH = "1" *) (* C_PROBE_IN184_WIDTH = "1" *)
(* C_PROBE_IN185_WIDTH = "1" *) (* C_PROBE_IN186_WIDTH = "1" *) (* C_PROBE_IN187_WIDTH = "1" *)
(* C_PROBE_IN188_WIDTH = "1" *) (* C_PROBE_IN189_WIDTH = "1" *) (* C_PROBE_IN18_WIDTH = "1" *)
(* C_PROBE_IN190_WIDTH = "1" *) (* C_PROBE_IN191_WIDTH = "1" *) (* C_PROBE_IN192_WIDTH = "1" *)
(* C_PROBE_IN193_WIDTH = "1" *) (* C_PROBE_IN194_WIDTH = "1" *) (* C_PROBE_IN195_WIDTH = "1" *)
(* C_PROBE_IN196_WIDTH = "1" *) (* C_PROBE_IN197_WIDTH = "1" *) (* C_PROBE_IN198_WIDTH = "1" *)
(* C_PROBE_IN199_WIDTH = "1" *) (* C_PROBE_IN19_WIDTH = "1" *) (* C_PROBE_IN1_WIDTH = "1" *)
(* C_PROBE_IN200_WIDTH = "1" *) (* C_PROBE_IN201_WIDTH = "1" *) (* C_PROBE_IN202_WIDTH = "1" *)
(* C_PROBE_IN203_WIDTH = "1" *) (* C_PROBE_IN204_WIDTH = "1" *) (* C_PROBE_IN205_WIDTH = "1" *)
(* C_PROBE_IN206_WIDTH = "1" *) (* C_PROBE_IN207_WIDTH = "1" *) (* C_PROBE_IN208_WIDTH = "1" *)
(* C_PROBE_IN209_WIDTH = "1" *) (* C_PROBE_IN20_WIDTH = "1" *) (* C_PROBE_IN210_WIDTH = "1" *)
(* C_PROBE_IN211_WIDTH = "1" *) (* C_PROBE_IN212_WIDTH = "1" *) (* C_PROBE_IN213_WIDTH = "1" *)
(* C_PROBE_IN214_WIDTH = "1" *) (* C_PROBE_IN215_WIDTH = "1" *) (* C_PROBE_IN216_WIDTH = "1" *)
(* C_PROBE_IN217_WIDTH = "1" *) (* C_PROBE_IN218_WIDTH = "1" *) (* C_PROBE_IN219_WIDTH = "1" *)
(* C_PROBE_IN21_WIDTH = "1" *) (* C_PROBE_IN220_WIDTH = "1" *) (* C_PROBE_IN221_WIDTH = "1" *)
(* C_PROBE_IN222_WIDTH = "1" *) (* C_PROBE_IN223_WIDTH = "1" *) (* C_PROBE_IN224_WIDTH = "1" *)
(* C_PROBE_IN225_WIDTH = "1" *) (* C_PROBE_IN226_WIDTH = "1" *) (* C_PROBE_IN227_WIDTH = "1" *)
(* C_PROBE_IN228_WIDTH = "1" *) (* C_PROBE_IN229_WIDTH = "1" *) (* C_PROBE_IN22_WIDTH = "1" *)
(* C_PROBE_IN230_WIDTH = "1" *) (* C_PROBE_IN231_WIDTH = "1" *) (* C_PROBE_IN232_WIDTH = "1" *)
(* C_PROBE_IN233_WIDTH = "1" *) (* C_PROBE_IN234_WIDTH = "1" *) (* C_PROBE_IN235_WIDTH = "1" *)
(* C_PROBE_IN236_WIDTH = "1" *) (* C_PROBE_IN237_WIDTH = "1" *) (* C_PROBE_IN238_WIDTH = "1" *)
(* C_PROBE_IN239_WIDTH = "1" *) (* C_PROBE_IN23_WIDTH = "1" *) (* C_PROBE_IN240_WIDTH = "1" *)
(* C_PROBE_IN241_WIDTH = "1" *) (* C_PROBE_IN242_WIDTH = "1" *) (* C_PROBE_IN243_WIDTH = "1" *)
(* C_PROBE_IN244_WIDTH = "1" *) (* C_PROBE_IN245_WIDTH = "1" *) (* C_PROBE_IN246_WIDTH = "1" *)
(* C_PROBE_IN247_WIDTH = "1" *) (* C_PROBE_IN248_WIDTH = "1" *) (* C_PROBE_IN249_WIDTH = "1" *)
(* C_PROBE_IN24_WIDTH = "1" *) (* C_PROBE_IN250_WIDTH = "1" *) (* C_PROBE_IN251_WIDTH = "1" *)
(* C_PROBE_IN252_WIDTH = "1" *) (* C_PROBE_IN253_WIDTH = "1" *) (* C_PROBE_IN254_WIDTH = "1" *)
(* C_PROBE_IN255_WIDTH = "1" *) (* C_PROBE_IN25_WIDTH = "1" *) (* C_PROBE_IN26_WIDTH = "1" *)
(* C_PROBE_IN27_WIDTH = "1" *) (* C_PROBE_IN28_WIDTH = "1" *) (* C_PROBE_IN29_WIDTH = "1" *)
(* C_PROBE_IN2_WIDTH = "1" *) (* C_PROBE_IN30_WIDTH = "1" *) (* C_PROBE_IN31_WIDTH = "1" *)
(* C_PROBE_IN32_WIDTH = "1" *) (* C_PROBE_IN33_WIDTH = "1" *) (* C_PROBE_IN34_WIDTH = "1" *)
(* C_PROBE_IN35_WIDTH = "1" *) (* C_PROBE_IN36_WIDTH = "1" *) (* C_PROBE_IN37_WIDTH = "1" *)
(* C_PROBE_IN38_WIDTH = "1" *) (* C_PROBE_IN39_WIDTH = "1" *) (* C_PROBE_IN3_WIDTH = "1" *)
(* C_PROBE_IN40_WIDTH = "1" *) (* C_PROBE_IN41_WIDTH = "1" *) (* C_PROBE_IN42_WIDTH = "1" *)
(* C_PROBE_IN43_WIDTH = "1" *) (* C_PROBE_IN44_WIDTH = "1" *) (* C_PROBE_IN45_WIDTH = "1" *)
(* C_PROBE_IN46_WIDTH = "1" *) (* C_PROBE_IN47_WIDTH = "1" *) (* C_PROBE_IN48_WIDTH = "1" *)
(* C_PROBE_IN49_WIDTH = "1" *) (* C_PROBE_IN4_WIDTH = "1" *) (* C_PROBE_IN50_WIDTH = "1" *)
(* C_PROBE_IN51_WIDTH = "1" *) (* C_PROBE_IN52_WIDTH = "1" *) (* C_PROBE_IN53_WIDTH = "1" *)
(* C_PROBE_IN54_WIDTH = "1" *) (* C_PROBE_IN55_WIDTH = "1" *) (* C_PROBE_IN56_WIDTH = "1" *)
(* C_PROBE_IN57_WIDTH = "1" *) (* C_PROBE_IN58_WIDTH = "1" *) (* C_PROBE_IN59_WIDTH = "1" *)
(* C_PROBE_IN5_WIDTH = "1" *) (* C_PROBE_IN60_WIDTH = "1" *) (* C_PROBE_IN61_WIDTH = "1" *)
(* C_PROBE_IN62_WIDTH = "1" *) (* C_PROBE_IN63_WIDTH = "1" *) (* C_PROBE_IN64_WIDTH = "1" *)
(* C_PROBE_IN65_WIDTH = "1" *) (* C_PROBE_IN66_WIDTH = "1" *) (* C_PROBE_IN67_WIDTH = "1" *)
(* C_PROBE_IN68_WIDTH = "1" *) (* C_PROBE_IN69_WIDTH = "1" *) (* C_PROBE_IN6_WIDTH = "1" *)
(* C_PROBE_IN70_WIDTH = "1" *) (* C_PROBE_IN71_WIDTH = "1" *) (* C_PROBE_IN72_WIDTH = "1" *)
(* C_PROBE_IN73_WIDTH = "1" *) (* C_PROBE_IN74_WIDTH = "1" *) (* C_PROBE_IN75_WIDTH = "1" *)
(* C_PROBE_IN76_WIDTH = "1" *) (* C_PROBE_IN77_WIDTH = "1" *) (* C_PROBE_IN78_WIDTH = "1" *)
(* C_PROBE_IN79_WIDTH = "1" *) (* C_PROBE_IN7_WIDTH = "1" *) (* C_PROBE_IN80_WIDTH = "1" *)
(* C_PROBE_IN81_WIDTH = "1" *) (* C_PROBE_IN82_WIDTH = "1" *) (* C_PROBE_IN83_WIDTH = "1" *)
(* C_PROBE_IN84_WIDTH = "1" *) (* C_PROBE_IN85_WIDTH = "1" *) (* C_PROBE_IN86_WIDTH = "1" *)
(* C_PROBE_IN87_WIDTH = "1" *) (* C_PROBE_IN88_WIDTH = "1" *) (* C_PROBE_IN89_WIDTH = "1" *)
(* C_PROBE_IN8_WIDTH = "1" *) (* C_PROBE_IN90_WIDTH = "1" *) (* C_PROBE_IN91_WIDTH = "1" *)
(* C_PROBE_IN92_WIDTH = "1" *) (* C_PROBE_IN93_WIDTH = "1" *) (* C_PROBE_IN94_WIDTH = "1" *)
(* C_PROBE_IN95_WIDTH = "1" *) (* C_PROBE_IN96_WIDTH = "1" *) (* C_PROBE_IN97_WIDTH = "1" *)
(* C_PROBE_IN98_WIDTH = "1" *) (* C_PROBE_IN99_WIDTH = "1" *) (* C_PROBE_IN9_WIDTH = "1" *)
(* C_PROBE_OUT0_INIT_VAL = "1'b0" *) (* C_PROBE_OUT0_WIDTH = "1" *) (* C_PROBE_OUT100_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT100_WIDTH = "1" *) (* C_PROBE_OUT101_INIT_VAL = "1'b0" *) (* C_PROBE_OUT101_WIDTH = "1" *)
(* C_PROBE_OUT102_INIT_VAL = "1'b0" *) (* C_PROBE_OUT102_WIDTH = "1" *) (* C_PROBE_OUT103_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT103_WIDTH = "1" *) (* C_PROBE_OUT104_INIT_VAL = "1'b0" *) (* C_PROBE_OUT104_WIDTH = "1" *)
(* C_PROBE_OUT105_INIT_VAL = "1'b0" *) (* C_PROBE_OUT105_WIDTH = "1" *) (* C_PROBE_OUT106_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT106_WIDTH = "1" *) (* C_PROBE_OUT107_INIT_VAL = "1'b0" *) (* C_PROBE_OUT107_WIDTH = "1" *)
(* C_PROBE_OUT108_INIT_VAL = "1'b0" *) (* C_PROBE_OUT108_WIDTH = "1" *) (* C_PROBE_OUT109_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT109_WIDTH = "1" *) (* C_PROBE_OUT10_INIT_VAL = "1'b0" *) (* C_PROBE_OUT10_WIDTH = "1" *)
(* C_PROBE_OUT110_INIT_VAL = "1'b0" *) (* C_PROBE_OUT110_WIDTH = "1" *) (* C_PROBE_OUT111_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT111_WIDTH = "1" *) (* C_PROBE_OUT112_INIT_VAL = "1'b0" *) (* C_PROBE_OUT112_WIDTH = "1" *)
(* C_PROBE_OUT113_INIT_VAL = "1'b0" *) (* C_PROBE_OUT113_WIDTH = "1" *) (* C_PROBE_OUT114_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT114_WIDTH = "1" *) (* C_PROBE_OUT115_INIT_VAL = "1'b0" *) (* C_PROBE_OUT115_WIDTH = "1" *)
(* C_PROBE_OUT116_INIT_VAL = "1'b0" *) (* C_PROBE_OUT116_WIDTH = "1" *) (* C_PROBE_OUT117_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT117_WIDTH = "1" *) (* C_PROBE_OUT118_INIT_VAL = "1'b0" *) (* C_PROBE_OUT118_WIDTH = "1" *)
(* C_PROBE_OUT119_INIT_VAL = "1'b0" *) (* C_PROBE_OUT119_WIDTH = "1" *) (* C_PROBE_OUT11_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT11_WIDTH = "1" *) (* C_PROBE_OUT120_INIT_VAL = "1'b0" *) (* C_PROBE_OUT120_WIDTH = "1" *)
(* C_PROBE_OUT121_INIT_VAL = "1'b0" *) (* C_PROBE_OUT121_WIDTH = "1" *) (* C_PROBE_OUT122_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT122_WIDTH = "1" *) (* C_PROBE_OUT123_INIT_VAL = "1'b0" *) (* C_PROBE_OUT123_WIDTH = "1" *)
(* C_PROBE_OUT124_INIT_VAL = "1'b0" *) (* C_PROBE_OUT124_WIDTH = "1" *) (* C_PROBE_OUT125_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT125_WIDTH = "1" *) (* C_PROBE_OUT126_INIT_VAL = "1'b0" *) (* C_PROBE_OUT126_WIDTH = "1" *)
(* C_PROBE_OUT127_INIT_VAL = "1'b0" *) (* C_PROBE_OUT127_WIDTH = "1" *) (* C_PROBE_OUT128_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT128_WIDTH = "1" *) (* C_PROBE_OUT129_INIT_VAL = "1'b0" *) (* C_PROBE_OUT129_WIDTH = "1" *)
(* C_PROBE_OUT12_INIT_VAL = "1'b0" *) (* C_PROBE_OUT12_WIDTH = "1" *) (* C_PROBE_OUT130_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT130_WIDTH = "1" *) (* C_PROBE_OUT131_INIT_VAL = "1'b0" *) (* C_PROBE_OUT131_WIDTH = "1" *)
(* C_PROBE_OUT132_INIT_VAL = "1'b0" *) (* C_PROBE_OUT132_WIDTH = "1" *) (* C_PROBE_OUT133_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT133_WIDTH = "1" *) (* C_PROBE_OUT134_INIT_VAL = "1'b0" *) (* C_PROBE_OUT134_WIDTH = "1" *)
(* C_PROBE_OUT135_INIT_VAL = "1'b0" *) (* C_PROBE_OUT135_WIDTH = "1" *) (* C_PROBE_OUT136_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT136_WIDTH = "1" *) (* C_PROBE_OUT137_INIT_VAL = "1'b0" *) (* C_PROBE_OUT137_WIDTH = "1" *)
(* C_PROBE_OUT138_INIT_VAL = "1'b0" *) (* C_PROBE_OUT138_WIDTH = "1" *) (* C_PROBE_OUT139_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT139_WIDTH = "1" *) (* C_PROBE_OUT13_INIT_VAL = "1'b0" *) (* C_PROBE_OUT13_WIDTH = "1" *)
(* C_PROBE_OUT140_INIT_VAL = "1'b0" *) (* C_PROBE_OUT140_WIDTH = "1" *) (* C_PROBE_OUT141_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT141_WIDTH = "1" *) (* C_PROBE_OUT142_INIT_VAL = "1'b0" *) (* C_PROBE_OUT142_WIDTH = "1" *)
(* C_PROBE_OUT143_INIT_VAL = "1'b0" *) (* C_PROBE_OUT143_WIDTH = "1" *) (* C_PROBE_OUT144_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT144_WIDTH = "1" *) (* C_PROBE_OUT145_INIT_VAL = "1'b0" *) (* C_PROBE_OUT145_WIDTH = "1" *)
(* C_PROBE_OUT146_INIT_VAL = "1'b0" *) (* C_PROBE_OUT146_WIDTH = "1" *) (* C_PROBE_OUT147_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT147_WIDTH = "1" *) (* C_PROBE_OUT148_INIT_VAL = "1'b0" *) (* C_PROBE_OUT148_WIDTH = "1" *)
(* C_PROBE_OUT149_INIT_VAL = "1'b0" *) (* C_PROBE_OUT149_WIDTH = "1" *) (* C_PROBE_OUT14_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT14_WIDTH = "1" *) (* C_PROBE_OUT150_INIT_VAL = "1'b0" *) (* C_PROBE_OUT150_WIDTH = "1" *)
(* C_PROBE_OUT151_INIT_VAL = "1'b0" *) (* C_PROBE_OUT151_WIDTH = "1" *) (* C_PROBE_OUT152_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT152_WIDTH = "1" *) (* C_PROBE_OUT153_INIT_VAL = "1'b0" *) (* C_PROBE_OUT153_WIDTH = "1" *)
(* C_PROBE_OUT154_INIT_VAL = "1'b0" *) (* C_PROBE_OUT154_WIDTH = "1" *) (* C_PROBE_OUT155_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT155_WIDTH = "1" *) (* C_PROBE_OUT156_INIT_VAL = "1'b0" *) (* C_PROBE_OUT156_WIDTH = "1" *)
(* C_PROBE_OUT157_INIT_VAL = "1'b0" *) (* C_PROBE_OUT157_WIDTH = "1" *) (* C_PROBE_OUT158_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT158_WIDTH = "1" *) (* C_PROBE_OUT159_INIT_VAL = "1'b0" *) (* C_PROBE_OUT159_WIDTH = "1" *)
(* C_PROBE_OUT15_INIT_VAL = "1'b0" *) (* C_PROBE_OUT15_WIDTH = "1" *) (* C_PROBE_OUT160_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT160_WIDTH = "1" *) (* C_PROBE_OUT161_INIT_VAL = "1'b0" *) (* C_PROBE_OUT161_WIDTH = "1" *)
(* C_PROBE_OUT162_INIT_VAL = "1'b0" *) (* C_PROBE_OUT162_WIDTH = "1" *) (* C_PROBE_OUT163_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT163_WIDTH = "1" *) (* C_PROBE_OUT164_INIT_VAL = "1'b0" *) (* C_PROBE_OUT164_WIDTH = "1" *)
(* C_PROBE_OUT165_INIT_VAL = "1'b0" *) (* C_PROBE_OUT165_WIDTH = "1" *) (* C_PROBE_OUT166_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT166_WIDTH = "1" *) (* C_PROBE_OUT167_INIT_VAL = "1'b0" *) (* C_PROBE_OUT167_WIDTH = "1" *)
(* C_PROBE_OUT168_INIT_VAL = "1'b0" *) (* C_PROBE_OUT168_WIDTH = "1" *) (* C_PROBE_OUT169_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT169_WIDTH = "1" *) (* C_PROBE_OUT16_INIT_VAL = "1'b0" *) (* C_PROBE_OUT16_WIDTH = "1" *)
(* C_PROBE_OUT170_INIT_VAL = "1'b0" *) (* C_PROBE_OUT170_WIDTH = "1" *) (* C_PROBE_OUT171_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT171_WIDTH = "1" *) (* C_PROBE_OUT172_INIT_VAL = "1'b0" *) (* C_PROBE_OUT172_WIDTH = "1" *)
(* C_PROBE_OUT173_INIT_VAL = "1'b0" *) (* C_PROBE_OUT173_WIDTH = "1" *) (* C_PROBE_OUT174_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT174_WIDTH = "1" *) (* C_PROBE_OUT175_INIT_VAL = "1'b0" *) (* C_PROBE_OUT175_WIDTH = "1" *)
(* C_PROBE_OUT176_INIT_VAL = "1'b0" *) (* C_PROBE_OUT176_WIDTH = "1" *) (* C_PROBE_OUT177_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT177_WIDTH = "1" *) (* C_PROBE_OUT178_INIT_VAL = "1'b0" *) (* C_PROBE_OUT178_WIDTH = "1" *)
(* C_PROBE_OUT179_INIT_VAL = "1'b0" *) (* C_PROBE_OUT179_WIDTH = "1" *) (* C_PROBE_OUT17_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT17_WIDTH = "1" *) (* C_PROBE_OUT180_INIT_VAL = "1'b0" *) (* C_PROBE_OUT180_WIDTH = "1" *)
(* C_PROBE_OUT181_INIT_VAL = "1'b0" *) (* C_PROBE_OUT181_WIDTH = "1" *) (* C_PROBE_OUT182_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT182_WIDTH = "1" *) (* C_PROBE_OUT183_INIT_VAL = "1'b0" *) (* C_PROBE_OUT183_WIDTH = "1" *)
(* C_PROBE_OUT184_INIT_VAL = "1'b0" *) (* C_PROBE_OUT184_WIDTH = "1" *) (* C_PROBE_OUT185_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT185_WIDTH = "1" *) (* C_PROBE_OUT186_INIT_VAL = "1'b0" *) (* C_PROBE_OUT186_WIDTH = "1" *)
(* C_PROBE_OUT187_INIT_VAL = "1'b0" *) (* C_PROBE_OUT187_WIDTH = "1" *) (* C_PROBE_OUT188_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT188_WIDTH = "1" *) (* C_PROBE_OUT189_INIT_VAL = "1'b0" *) (* C_PROBE_OUT189_WIDTH = "1" *)
(* C_PROBE_OUT18_INIT_VAL = "1'b0" *) (* C_PROBE_OUT18_WIDTH = "1" *) (* C_PROBE_OUT190_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT190_WIDTH = "1" *) (* C_PROBE_OUT191_INIT_VAL = "1'b0" *) (* C_PROBE_OUT191_WIDTH = "1" *)
(* C_PROBE_OUT192_INIT_VAL = "1'b0" *) (* C_PROBE_OUT192_WIDTH = "1" *) (* C_PROBE_OUT193_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT193_WIDTH = "1" *) (* C_PROBE_OUT194_INIT_VAL = "1'b0" *) (* C_PROBE_OUT194_WIDTH = "1" *)
(* C_PROBE_OUT195_INIT_VAL = "1'b0" *) (* C_PROBE_OUT195_WIDTH = "1" *) (* C_PROBE_OUT196_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT196_WIDTH = "1" *) (* C_PROBE_OUT197_INIT_VAL = "1'b0" *) (* C_PROBE_OUT197_WIDTH = "1" *)
(* C_PROBE_OUT198_INIT_VAL = "1'b0" *) (* C_PROBE_OUT198_WIDTH = "1" *) (* C_PROBE_OUT199_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT199_WIDTH = "1" *) (* C_PROBE_OUT19_INIT_VAL = "1'b0" *) (* C_PROBE_OUT19_WIDTH = "1" *)
(* C_PROBE_OUT1_INIT_VAL = "1'b0" *) (* C_PROBE_OUT1_WIDTH = "1" *) (* C_PROBE_OUT200_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT200_WIDTH = "1" *) (* C_PROBE_OUT201_INIT_VAL = "1'b0" *) (* C_PROBE_OUT201_WIDTH = "1" *)
(* C_PROBE_OUT202_INIT_VAL = "1'b0" *) (* C_PROBE_OUT202_WIDTH = "1" *) (* C_PROBE_OUT203_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT203_WIDTH = "1" *) (* C_PROBE_OUT204_INIT_VAL = "1'b0" *) (* C_PROBE_OUT204_WIDTH = "1" *)
(* C_PROBE_OUT205_INIT_VAL = "1'b0" *) (* C_PROBE_OUT205_WIDTH = "1" *) (* C_PROBE_OUT206_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT206_WIDTH = "1" *) (* C_PROBE_OUT207_INIT_VAL = "1'b0" *) (* C_PROBE_OUT207_WIDTH = "1" *)
(* C_PROBE_OUT208_INIT_VAL = "1'b0" *) (* C_PROBE_OUT208_WIDTH = "1" *) (* C_PROBE_OUT209_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT209_WIDTH = "1" *) (* C_PROBE_OUT20_INIT_VAL = "1'b0" *) (* C_PROBE_OUT20_WIDTH = "1" *)
(* C_PROBE_OUT210_INIT_VAL = "1'b0" *) (* C_PROBE_OUT210_WIDTH = "1" *) (* C_PROBE_OUT211_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT211_WIDTH = "1" *) (* C_PROBE_OUT212_INIT_VAL = "1'b0" *) (* C_PROBE_OUT212_WIDTH = "1" *)
(* C_PROBE_OUT213_INIT_VAL = "1'b0" *) (* C_PROBE_OUT213_WIDTH = "1" *) (* C_PROBE_OUT214_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT214_WIDTH = "1" *) (* C_PROBE_OUT215_INIT_VAL = "1'b0" *) (* C_PROBE_OUT215_WIDTH = "1" *)
(* C_PROBE_OUT216_INIT_VAL = "1'b0" *) (* C_PROBE_OUT216_WIDTH = "1" *) (* C_PROBE_OUT217_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT217_WIDTH = "1" *) (* C_PROBE_OUT218_INIT_VAL = "1'b0" *) (* C_PROBE_OUT218_WIDTH = "1" *)
(* C_PROBE_OUT219_INIT_VAL = "1'b0" *) (* C_PROBE_OUT219_WIDTH = "1" *) (* C_PROBE_OUT21_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT21_WIDTH = "1" *) (* C_PROBE_OUT220_INIT_VAL = "1'b0" *) (* C_PROBE_OUT220_WIDTH = "1" *)
(* C_PROBE_OUT221_INIT_VAL = "1'b0" *) (* C_PROBE_OUT221_WIDTH = "1" *) (* C_PROBE_OUT222_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT222_WIDTH = "1" *) (* C_PROBE_OUT223_INIT_VAL = "1'b0" *) (* C_PROBE_OUT223_WIDTH = "1" *)
(* C_PROBE_OUT224_INIT_VAL = "1'b0" *) (* C_PROBE_OUT224_WIDTH = "1" *) (* C_PROBE_OUT225_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT225_WIDTH = "1" *) (* C_PROBE_OUT226_INIT_VAL = "1'b0" *) (* C_PROBE_OUT226_WIDTH = "1" *)
(* C_PROBE_OUT227_INIT_VAL = "1'b0" *) (* C_PROBE_OUT227_WIDTH = "1" *) (* C_PROBE_OUT228_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT228_WIDTH = "1" *) (* C_PROBE_OUT229_INIT_VAL = "1'b0" *) (* C_PROBE_OUT229_WIDTH = "1" *)
(* C_PROBE_OUT22_INIT_VAL = "1'b0" *) (* C_PROBE_OUT22_WIDTH = "1" *) (* C_PROBE_OUT230_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT230_WIDTH = "1" *) (* C_PROBE_OUT231_INIT_VAL = "1'b0" *) (* C_PROBE_OUT231_WIDTH = "1" *)
(* C_PROBE_OUT232_INIT_VAL = "1'b0" *) (* C_PROBE_OUT232_WIDTH = "1" *) (* C_PROBE_OUT233_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT233_WIDTH = "1" *) (* C_PROBE_OUT234_INIT_VAL = "1'b0" *) (* C_PROBE_OUT234_WIDTH = "1" *)
(* C_PROBE_OUT235_INIT_VAL = "1'b0" *) (* C_PROBE_OUT235_WIDTH = "1" *) (* C_PROBE_OUT236_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT236_WIDTH = "1" *) (* C_PROBE_OUT237_INIT_VAL = "1'b0" *) (* C_PROBE_OUT237_WIDTH = "1" *)
(* C_PROBE_OUT238_INIT_VAL = "1'b0" *) (* C_PROBE_OUT238_WIDTH = "1" *) (* C_PROBE_OUT239_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT239_WIDTH = "1" *) (* C_PROBE_OUT23_INIT_VAL = "1'b0" *) (* C_PROBE_OUT23_WIDTH = "1" *)
(* C_PROBE_OUT240_INIT_VAL = "1'b0" *) (* C_PROBE_OUT240_WIDTH = "1" *) (* C_PROBE_OUT241_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT241_WIDTH = "1" *) (* C_PROBE_OUT242_INIT_VAL = "1'b0" *) (* C_PROBE_OUT242_WIDTH = "1" *)
(* C_PROBE_OUT243_INIT_VAL = "1'b0" *) (* C_PROBE_OUT243_WIDTH = "1" *) (* C_PROBE_OUT244_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT244_WIDTH = "1" *) (* C_PROBE_OUT245_INIT_VAL = "1'b0" *) (* C_PROBE_OUT245_WIDTH = "1" *)
(* C_PROBE_OUT246_INIT_VAL = "1'b0" *) (* C_PROBE_OUT246_WIDTH = "1" *) (* C_PROBE_OUT247_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT247_WIDTH = "1" *) (* C_PROBE_OUT248_INIT_VAL = "1'b0" *) (* C_PROBE_OUT248_WIDTH = "1" *)
(* C_PROBE_OUT249_INIT_VAL = "1'b0" *) (* C_PROBE_OUT249_WIDTH = "1" *) (* C_PROBE_OUT24_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT24_WIDTH = "1" *) (* C_PROBE_OUT250_INIT_VAL = "1'b0" *) (* C_PROBE_OUT250_WIDTH = "1" *)
(* C_PROBE_OUT251_INIT_VAL = "1'b0" *) (* C_PROBE_OUT251_WIDTH = "1" *) (* C_PROBE_OUT252_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT252_WIDTH = "1" *) (* C_PROBE_OUT253_INIT_VAL = "1'b0" *) (* C_PROBE_OUT253_WIDTH = "1" *)
(* C_PROBE_OUT254_INIT_VAL = "1'b0" *) (* C_PROBE_OUT254_WIDTH = "1" *) (* C_PROBE_OUT255_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT255_WIDTH = "1" *) (* C_PROBE_OUT25_INIT_VAL = "1'b0" *) (* C_PROBE_OUT25_WIDTH = "1" *)
(* C_PROBE_OUT26_INIT_VAL = "1'b0" *) (* C_PROBE_OUT26_WIDTH = "1" *) (* C_PROBE_OUT27_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT27_WIDTH = "1" *) (* C_PROBE_OUT28_INIT_VAL = "1'b0" *) (* C_PROBE_OUT28_WIDTH = "1" *)
(* C_PROBE_OUT29_INIT_VAL = "1'b0" *) (* C_PROBE_OUT29_WIDTH = "1" *) (* C_PROBE_OUT2_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT2_WIDTH = "1" *) (* C_PROBE_OUT30_INIT_VAL = "1'b0" *) (* C_PROBE_OUT30_WIDTH = "1" *)
(* C_PROBE_OUT31_INIT_VAL = "1'b0" *) (* C_PROBE_OUT31_WIDTH = "1" *) (* C_PROBE_OUT32_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT32_WIDTH = "1" *) (* C_PROBE_OUT33_INIT_VAL = "1'b0" *) (* C_PROBE_OUT33_WIDTH = "1" *)
(* C_PROBE_OUT34_INIT_VAL = "1'b0" *) (* C_PROBE_OUT34_WIDTH = "1" *) (* C_PROBE_OUT35_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT35_WIDTH = "1" *) (* C_PROBE_OUT36_INIT_VAL = "1'b0" *) (* C_PROBE_OUT36_WIDTH = "1" *)
(* C_PROBE_OUT37_INIT_VAL = "1'b0" *) (* C_PROBE_OUT37_WIDTH = "1" *) (* C_PROBE_OUT38_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT38_WIDTH = "1" *) (* C_PROBE_OUT39_INIT_VAL = "1'b0" *) (* C_PROBE_OUT39_WIDTH = "1" *)
(* C_PROBE_OUT3_INIT_VAL = "1'b0" *) (* C_PROBE_OUT3_WIDTH = "1" *) (* C_PROBE_OUT40_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT40_WIDTH = "1" *) (* C_PROBE_OUT41_INIT_VAL = "1'b0" *) (* C_PROBE_OUT41_WIDTH = "1" *)
(* C_PROBE_OUT42_INIT_VAL = "1'b0" *) (* C_PROBE_OUT42_WIDTH = "1" *) (* C_PROBE_OUT43_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT43_WIDTH = "1" *) (* C_PROBE_OUT44_INIT_VAL = "1'b0" *) (* C_PROBE_OUT44_WIDTH = "1" *)
(* C_PROBE_OUT45_INIT_VAL = "1'b0" *) (* C_PROBE_OUT45_WIDTH = "1" *) (* C_PROBE_OUT46_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT46_WIDTH = "1" *) (* C_PROBE_OUT47_INIT_VAL = "1'b0" *) (* C_PROBE_OUT47_WIDTH = "1" *)
(* C_PROBE_OUT48_INIT_VAL = "1'b0" *) (* C_PROBE_OUT48_WIDTH = "1" *) (* C_PROBE_OUT49_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT49_WIDTH = "1" *) (* C_PROBE_OUT4_INIT_VAL = "1'b0" *) (* C_PROBE_OUT4_WIDTH = "1" *)
(* C_PROBE_OUT50_INIT_VAL = "1'b0" *) (* C_PROBE_OUT50_WIDTH = "1" *) (* C_PROBE_OUT51_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT51_WIDTH = "1" *) (* C_PROBE_OUT52_INIT_VAL = "1'b0" *) (* C_PROBE_OUT52_WIDTH = "1" *)
(* C_PROBE_OUT53_INIT_VAL = "1'b0" *) (* C_PROBE_OUT53_WIDTH = "1" *) (* C_PROBE_OUT54_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT54_WIDTH = "1" *) (* C_PROBE_OUT55_INIT_VAL = "1'b0" *) (* C_PROBE_OUT55_WIDTH = "1" *)
(* C_PROBE_OUT56_INIT_VAL = "1'b0" *) (* C_PROBE_OUT56_WIDTH = "1" *) (* C_PROBE_OUT57_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT57_WIDTH = "1" *) (* C_PROBE_OUT58_INIT_VAL = "1'b0" *) (* C_PROBE_OUT58_WIDTH = "1" *)
(* C_PROBE_OUT59_INIT_VAL = "1'b0" *) (* C_PROBE_OUT59_WIDTH = "1" *) (* C_PROBE_OUT5_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT5_WIDTH = "1" *) (* C_PROBE_OUT60_INIT_VAL = "1'b0" *) (* C_PROBE_OUT60_WIDTH = "1" *)
(* C_PROBE_OUT61_INIT_VAL = "1'b0" *) (* C_PROBE_OUT61_WIDTH = "1" *) (* C_PROBE_OUT62_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT62_WIDTH = "1" *) (* C_PROBE_OUT63_INIT_VAL = "1'b0" *) (* C_PROBE_OUT63_WIDTH = "1" *)
(* C_PROBE_OUT64_INIT_VAL = "1'b0" *) (* C_PROBE_OUT64_WIDTH = "1" *) (* C_PROBE_OUT65_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT65_WIDTH = "1" *) (* C_PROBE_OUT66_INIT_VAL = "1'b0" *) (* C_PROBE_OUT66_WIDTH = "1" *)
(* C_PROBE_OUT67_INIT_VAL = "1'b0" *) (* C_PROBE_OUT67_WIDTH = "1" *) (* C_PROBE_OUT68_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT68_WIDTH = "1" *) (* C_PROBE_OUT69_INIT_VAL = "1'b0" *) (* C_PROBE_OUT69_WIDTH = "1" *)
(* C_PROBE_OUT6_INIT_VAL = "1'b0" *) (* C_PROBE_OUT6_WIDTH = "1" *) (* C_PROBE_OUT70_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT70_WIDTH = "1" *) (* C_PROBE_OUT71_INIT_VAL = "1'b0" *) (* C_PROBE_OUT71_WIDTH = "1" *)
(* C_PROBE_OUT72_INIT_VAL = "1'b0" *) (* C_PROBE_OUT72_WIDTH = "1" *) (* C_PROBE_OUT73_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT73_WIDTH = "1" *) (* C_PROBE_OUT74_INIT_VAL = "1'b0" *) (* C_PROBE_OUT74_WIDTH = "1" *)
(* C_PROBE_OUT75_INIT_VAL = "1'b0" *) (* C_PROBE_OUT75_WIDTH = "1" *) (* C_PROBE_OUT76_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT76_WIDTH = "1" *) (* C_PROBE_OUT77_INIT_VAL = "1'b0" *) (* C_PROBE_OUT77_WIDTH = "1" *)
(* C_PROBE_OUT78_INIT_VAL = "1'b0" *) (* C_PROBE_OUT78_WIDTH = "1" *) (* C_PROBE_OUT79_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT79_WIDTH = "1" *) (* C_PROBE_OUT7_INIT_VAL = "1'b0" *) (* C_PROBE_OUT7_WIDTH = "1" *)
(* C_PROBE_OUT80_INIT_VAL = "1'b0" *) (* C_PROBE_OUT80_WIDTH = "1" *) (* C_PROBE_OUT81_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT81_WIDTH = "1" *) (* C_PROBE_OUT82_INIT_VAL = "1'b0" *) (* C_PROBE_OUT82_WIDTH = "1" *)
(* C_PROBE_OUT83_INIT_VAL = "1'b0" *) (* C_PROBE_OUT83_WIDTH = "1" *) (* C_PROBE_OUT84_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT84_WIDTH = "1" *) (* C_PROBE_OUT85_INIT_VAL = "1'b0" *) (* C_PROBE_OUT85_WIDTH = "1" *)
(* C_PROBE_OUT86_INIT_VAL = "1'b0" *) (* C_PROBE_OUT86_WIDTH = "1" *) (* C_PROBE_OUT87_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT87_WIDTH = "1" *) (* C_PROBE_OUT88_INIT_VAL = "1'b0" *) (* C_PROBE_OUT88_WIDTH = "1" *)
(* C_PROBE_OUT89_INIT_VAL = "1'b0" *) (* C_PROBE_OUT89_WIDTH = "1" *) (* C_PROBE_OUT8_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT8_WIDTH = "1" *) (* C_PROBE_OUT90_INIT_VAL = "1'b0" *) (* C_PROBE_OUT90_WIDTH = "1" *)
(* C_PROBE_OUT91_INIT_VAL = "1'b0" *) (* C_PROBE_OUT91_WIDTH = "1" *) (* C_PROBE_OUT92_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT92_WIDTH = "1" *) (* C_PROBE_OUT93_INIT_VAL = "1'b0" *) (* C_PROBE_OUT93_WIDTH = "1" *)
(* C_PROBE_OUT94_INIT_VAL = "1'b0" *) (* C_PROBE_OUT94_WIDTH = "1" *) (* C_PROBE_OUT95_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT95_WIDTH = "1" *) (* C_PROBE_OUT96_INIT_VAL = "1'b0" *) (* C_PROBE_OUT96_WIDTH = "1" *)
(* C_PROBE_OUT97_INIT_VAL = "1'b0" *) (* C_PROBE_OUT97_WIDTH = "1" *) (* C_PROBE_OUT98_INIT_VAL = "1'b0" *)
(* C_PROBE_OUT98_WIDTH = "1" *) (* C_PROBE_OUT99_INIT_VAL = "1'b0" *) (* C_PROBE_OUT99_WIDTH = "1" *)
(* C_PROBE_OUT9_INIT_VAL = "1'b0" *) (* C_PROBE_OUT9_WIDTH = "1" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XLNX_HW_PROBE_INFO = "DEFAULT" *) (* C_XSDB_SLAVE_TYPE = "33" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* LC_HIGH_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *) (* LC_HIGH_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *) (* LC_HIGH_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_HIGH_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_HIGH_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_HIGH_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_HIGH_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_HIGH_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_HIGH_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *) (* LC_HIGH_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *) (* LC_HIGH_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_HIGH_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *) (* LC_HIGH_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *) (* LC_HIGH_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_HIGH_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *) (* LC_HIGH_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_HIGH_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_HIGH_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_HIGH_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *) (* LC_HIGH_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *) (* LC_HIGH_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_HIGH_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *) (* LC_HIGH_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_HIGH_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *) (* LC_HIGH_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *)
(* LC_HIGH_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_HIGH_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *) (* LC_HIGH_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_HIGH_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *) (* LC_HIGH_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_HIGH_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *) (* LC_HIGH_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_HIGH_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *)
(* LC_HIGH_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_HIGH_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *) (* LC_HIGH_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_HIGH_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *) (* LC_HIGH_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_HIGH_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *) (* LC_HIGH_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *) (* LC_HIGH_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *)
(* LC_HIGH_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_HIGH_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *) (* LC_HIGH_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_HIGH_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *) (* LC_HIGH_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_HIGH_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *) (* LC_HIGH_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *)
(* LC_HIGH_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_HIGH_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *) (* LC_HIGH_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *) (* LC_HIGH_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_HIGH_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *) (* LC_HIGH_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_HIGH_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *) (* LC_HIGH_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *)
(* LC_HIGH_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_HIGH_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *) (* LC_HIGH_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_HIGH_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *) (* LC_HIGH_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_HIGH_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *) (* LC_HIGH_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_HIGH_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *) (* LC_HIGH_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *)
(* LC_HIGH_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_HIGH_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *) (* LC_HIGH_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *)
(* LC_HIGH_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_HIGH_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *) (* LC_HIGH_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *)
(* LC_HIGH_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_HIGH_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *) (* LC_LOW_BIT_POS_PROBE_OUT0 = "16'b0000000000000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT1 = "16'b0000000000000001" *) (* LC_LOW_BIT_POS_PROBE_OUT10 = "16'b0000000000001010" *) (* LC_LOW_BIT_POS_PROBE_OUT100 = "16'b0000000001100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT101 = "16'b0000000001100101" *) (* LC_LOW_BIT_POS_PROBE_OUT102 = "16'b0000000001100110" *) (* LC_LOW_BIT_POS_PROBE_OUT103 = "16'b0000000001100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT104 = "16'b0000000001101000" *) (* LC_LOW_BIT_POS_PROBE_OUT105 = "16'b0000000001101001" *) (* LC_LOW_BIT_POS_PROBE_OUT106 = "16'b0000000001101010" *)
(* LC_LOW_BIT_POS_PROBE_OUT107 = "16'b0000000001101011" *) (* LC_LOW_BIT_POS_PROBE_OUT108 = "16'b0000000001101100" *) (* LC_LOW_BIT_POS_PROBE_OUT109 = "16'b0000000001101101" *)
(* LC_LOW_BIT_POS_PROBE_OUT11 = "16'b0000000000001011" *) (* LC_LOW_BIT_POS_PROBE_OUT110 = "16'b0000000001101110" *) (* LC_LOW_BIT_POS_PROBE_OUT111 = "16'b0000000001101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT112 = "16'b0000000001110000" *) (* LC_LOW_BIT_POS_PROBE_OUT113 = "16'b0000000001110001" *) (* LC_LOW_BIT_POS_PROBE_OUT114 = "16'b0000000001110010" *)
(* LC_LOW_BIT_POS_PROBE_OUT115 = "16'b0000000001110011" *) (* LC_LOW_BIT_POS_PROBE_OUT116 = "16'b0000000001110100" *) (* LC_LOW_BIT_POS_PROBE_OUT117 = "16'b0000000001110101" *)
(* LC_LOW_BIT_POS_PROBE_OUT118 = "16'b0000000001110110" *) (* LC_LOW_BIT_POS_PROBE_OUT119 = "16'b0000000001110111" *) (* LC_LOW_BIT_POS_PROBE_OUT12 = "16'b0000000000001100" *)
(* LC_LOW_BIT_POS_PROBE_OUT120 = "16'b0000000001111000" *) (* LC_LOW_BIT_POS_PROBE_OUT121 = "16'b0000000001111001" *) (* LC_LOW_BIT_POS_PROBE_OUT122 = "16'b0000000001111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT123 = "16'b0000000001111011" *) (* LC_LOW_BIT_POS_PROBE_OUT124 = "16'b0000000001111100" *) (* LC_LOW_BIT_POS_PROBE_OUT125 = "16'b0000000001111101" *)
(* LC_LOW_BIT_POS_PROBE_OUT126 = "16'b0000000001111110" *) (* LC_LOW_BIT_POS_PROBE_OUT127 = "16'b0000000001111111" *) (* LC_LOW_BIT_POS_PROBE_OUT128 = "16'b0000000010000000" *)
(* LC_LOW_BIT_POS_PROBE_OUT129 = "16'b0000000010000001" *) (* LC_LOW_BIT_POS_PROBE_OUT13 = "16'b0000000000001101" *) (* LC_LOW_BIT_POS_PROBE_OUT130 = "16'b0000000010000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT131 = "16'b0000000010000011" *) (* LC_LOW_BIT_POS_PROBE_OUT132 = "16'b0000000010000100" *) (* LC_LOW_BIT_POS_PROBE_OUT133 = "16'b0000000010000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT134 = "16'b0000000010000110" *) (* LC_LOW_BIT_POS_PROBE_OUT135 = "16'b0000000010000111" *) (* LC_LOW_BIT_POS_PROBE_OUT136 = "16'b0000000010001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT137 = "16'b0000000010001001" *) (* LC_LOW_BIT_POS_PROBE_OUT138 = "16'b0000000010001010" *) (* LC_LOW_BIT_POS_PROBE_OUT139 = "16'b0000000010001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT14 = "16'b0000000000001110" *) (* LC_LOW_BIT_POS_PROBE_OUT140 = "16'b0000000010001100" *) (* LC_LOW_BIT_POS_PROBE_OUT141 = "16'b0000000010001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT142 = "16'b0000000010001110" *) (* LC_LOW_BIT_POS_PROBE_OUT143 = "16'b0000000010001111" *) (* LC_LOW_BIT_POS_PROBE_OUT144 = "16'b0000000010010000" *)
(* LC_LOW_BIT_POS_PROBE_OUT145 = "16'b0000000010010001" *) (* LC_LOW_BIT_POS_PROBE_OUT146 = "16'b0000000010010010" *) (* LC_LOW_BIT_POS_PROBE_OUT147 = "16'b0000000010010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT148 = "16'b0000000010010100" *) (* LC_LOW_BIT_POS_PROBE_OUT149 = "16'b0000000010010101" *) (* LC_LOW_BIT_POS_PROBE_OUT15 = "16'b0000000000001111" *)
(* LC_LOW_BIT_POS_PROBE_OUT150 = "16'b0000000010010110" *) (* LC_LOW_BIT_POS_PROBE_OUT151 = "16'b0000000010010111" *) (* LC_LOW_BIT_POS_PROBE_OUT152 = "16'b0000000010011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT153 = "16'b0000000010011001" *) (* LC_LOW_BIT_POS_PROBE_OUT154 = "16'b0000000010011010" *) (* LC_LOW_BIT_POS_PROBE_OUT155 = "16'b0000000010011011" *)
(* LC_LOW_BIT_POS_PROBE_OUT156 = "16'b0000000010011100" *) (* LC_LOW_BIT_POS_PROBE_OUT157 = "16'b0000000010011101" *) (* LC_LOW_BIT_POS_PROBE_OUT158 = "16'b0000000010011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT159 = "16'b0000000010011111" *) (* LC_LOW_BIT_POS_PROBE_OUT16 = "16'b0000000000010000" *) (* LC_LOW_BIT_POS_PROBE_OUT160 = "16'b0000000010100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT161 = "16'b0000000010100001" *) (* LC_LOW_BIT_POS_PROBE_OUT162 = "16'b0000000010100010" *) (* LC_LOW_BIT_POS_PROBE_OUT163 = "16'b0000000010100011" *)
(* LC_LOW_BIT_POS_PROBE_OUT164 = "16'b0000000010100100" *) (* LC_LOW_BIT_POS_PROBE_OUT165 = "16'b0000000010100101" *) (* LC_LOW_BIT_POS_PROBE_OUT166 = "16'b0000000010100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT167 = "16'b0000000010100111" *) (* LC_LOW_BIT_POS_PROBE_OUT168 = "16'b0000000010101000" *) (* LC_LOW_BIT_POS_PROBE_OUT169 = "16'b0000000010101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT17 = "16'b0000000000010001" *) (* LC_LOW_BIT_POS_PROBE_OUT170 = "16'b0000000010101010" *) (* LC_LOW_BIT_POS_PROBE_OUT171 = "16'b0000000010101011" *)
(* LC_LOW_BIT_POS_PROBE_OUT172 = "16'b0000000010101100" *) (* LC_LOW_BIT_POS_PROBE_OUT173 = "16'b0000000010101101" *) (* LC_LOW_BIT_POS_PROBE_OUT174 = "16'b0000000010101110" *)
(* LC_LOW_BIT_POS_PROBE_OUT175 = "16'b0000000010101111" *) (* LC_LOW_BIT_POS_PROBE_OUT176 = "16'b0000000010110000" *) (* LC_LOW_BIT_POS_PROBE_OUT177 = "16'b0000000010110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT178 = "16'b0000000010110010" *) (* LC_LOW_BIT_POS_PROBE_OUT179 = "16'b0000000010110011" *) (* LC_LOW_BIT_POS_PROBE_OUT18 = "16'b0000000000010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT180 = "16'b0000000010110100" *) (* LC_LOW_BIT_POS_PROBE_OUT181 = "16'b0000000010110101" *) (* LC_LOW_BIT_POS_PROBE_OUT182 = "16'b0000000010110110" *)
(* LC_LOW_BIT_POS_PROBE_OUT183 = "16'b0000000010110111" *) (* LC_LOW_BIT_POS_PROBE_OUT184 = "16'b0000000010111000" *) (* LC_LOW_BIT_POS_PROBE_OUT185 = "16'b0000000010111001" *)
(* LC_LOW_BIT_POS_PROBE_OUT186 = "16'b0000000010111010" *) (* LC_LOW_BIT_POS_PROBE_OUT187 = "16'b0000000010111011" *) (* LC_LOW_BIT_POS_PROBE_OUT188 = "16'b0000000010111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT189 = "16'b0000000010111101" *) (* LC_LOW_BIT_POS_PROBE_OUT19 = "16'b0000000000010011" *) (* LC_LOW_BIT_POS_PROBE_OUT190 = "16'b0000000010111110" *)
(* LC_LOW_BIT_POS_PROBE_OUT191 = "16'b0000000010111111" *) (* LC_LOW_BIT_POS_PROBE_OUT192 = "16'b0000000011000000" *) (* LC_LOW_BIT_POS_PROBE_OUT193 = "16'b0000000011000001" *)
(* LC_LOW_BIT_POS_PROBE_OUT194 = "16'b0000000011000010" *) (* LC_LOW_BIT_POS_PROBE_OUT195 = "16'b0000000011000011" *) (* LC_LOW_BIT_POS_PROBE_OUT196 = "16'b0000000011000100" *)
(* LC_LOW_BIT_POS_PROBE_OUT197 = "16'b0000000011000101" *) (* LC_LOW_BIT_POS_PROBE_OUT198 = "16'b0000000011000110" *) (* LC_LOW_BIT_POS_PROBE_OUT199 = "16'b0000000011000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT2 = "16'b0000000000000010" *) (* LC_LOW_BIT_POS_PROBE_OUT20 = "16'b0000000000010100" *) (* LC_LOW_BIT_POS_PROBE_OUT200 = "16'b0000000011001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT201 = "16'b0000000011001001" *) (* LC_LOW_BIT_POS_PROBE_OUT202 = "16'b0000000011001010" *) (* LC_LOW_BIT_POS_PROBE_OUT203 = "16'b0000000011001011" *)
(* LC_LOW_BIT_POS_PROBE_OUT204 = "16'b0000000011001100" *) (* LC_LOW_BIT_POS_PROBE_OUT205 = "16'b0000000011001101" *) (* LC_LOW_BIT_POS_PROBE_OUT206 = "16'b0000000011001110" *)
(* LC_LOW_BIT_POS_PROBE_OUT207 = "16'b0000000011001111" *) (* LC_LOW_BIT_POS_PROBE_OUT208 = "16'b0000000011010000" *) (* LC_LOW_BIT_POS_PROBE_OUT209 = "16'b0000000011010001" *)
(* LC_LOW_BIT_POS_PROBE_OUT21 = "16'b0000000000010101" *) (* LC_LOW_BIT_POS_PROBE_OUT210 = "16'b0000000011010010" *) (* LC_LOW_BIT_POS_PROBE_OUT211 = "16'b0000000011010011" *)
(* LC_LOW_BIT_POS_PROBE_OUT212 = "16'b0000000011010100" *) (* LC_LOW_BIT_POS_PROBE_OUT213 = "16'b0000000011010101" *) (* LC_LOW_BIT_POS_PROBE_OUT214 = "16'b0000000011010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT215 = "16'b0000000011010111" *) (* LC_LOW_BIT_POS_PROBE_OUT216 = "16'b0000000011011000" *) (* LC_LOW_BIT_POS_PROBE_OUT217 = "16'b0000000011011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT218 = "16'b0000000011011010" *) (* LC_LOW_BIT_POS_PROBE_OUT219 = "16'b0000000011011011" *) (* LC_LOW_BIT_POS_PROBE_OUT22 = "16'b0000000000010110" *)
(* LC_LOW_BIT_POS_PROBE_OUT220 = "16'b0000000011011100" *) (* LC_LOW_BIT_POS_PROBE_OUT221 = "16'b0000000011011101" *) (* LC_LOW_BIT_POS_PROBE_OUT222 = "16'b0000000011011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT223 = "16'b0000000011011111" *) (* LC_LOW_BIT_POS_PROBE_OUT224 = "16'b0000000011100000" *) (* LC_LOW_BIT_POS_PROBE_OUT225 = "16'b0000000011100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT226 = "16'b0000000011100010" *) (* LC_LOW_BIT_POS_PROBE_OUT227 = "16'b0000000011100011" *) (* LC_LOW_BIT_POS_PROBE_OUT228 = "16'b0000000011100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT229 = "16'b0000000011100101" *) (* LC_LOW_BIT_POS_PROBE_OUT23 = "16'b0000000000010111" *) (* LC_LOW_BIT_POS_PROBE_OUT230 = "16'b0000000011100110" *)
(* LC_LOW_BIT_POS_PROBE_OUT231 = "16'b0000000011100111" *) (* LC_LOW_BIT_POS_PROBE_OUT232 = "16'b0000000011101000" *) (* LC_LOW_BIT_POS_PROBE_OUT233 = "16'b0000000011101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT234 = "16'b0000000011101010" *) (* LC_LOW_BIT_POS_PROBE_OUT235 = "16'b0000000011101011" *) (* LC_LOW_BIT_POS_PROBE_OUT236 = "16'b0000000011101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT237 = "16'b0000000011101101" *) (* LC_LOW_BIT_POS_PROBE_OUT238 = "16'b0000000011101110" *) (* LC_LOW_BIT_POS_PROBE_OUT239 = "16'b0000000011101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT24 = "16'b0000000000011000" *) (* LC_LOW_BIT_POS_PROBE_OUT240 = "16'b0000000011110000" *) (* LC_LOW_BIT_POS_PROBE_OUT241 = "16'b0000000011110001" *)
(* LC_LOW_BIT_POS_PROBE_OUT242 = "16'b0000000011110010" *) (* LC_LOW_BIT_POS_PROBE_OUT243 = "16'b0000000011110011" *) (* LC_LOW_BIT_POS_PROBE_OUT244 = "16'b0000000011110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT245 = "16'b0000000011110101" *) (* LC_LOW_BIT_POS_PROBE_OUT246 = "16'b0000000011110110" *) (* LC_LOW_BIT_POS_PROBE_OUT247 = "16'b0000000011110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT248 = "16'b0000000011111000" *) (* LC_LOW_BIT_POS_PROBE_OUT249 = "16'b0000000011111001" *) (* LC_LOW_BIT_POS_PROBE_OUT25 = "16'b0000000000011001" *)
(* LC_LOW_BIT_POS_PROBE_OUT250 = "16'b0000000011111010" *) (* LC_LOW_BIT_POS_PROBE_OUT251 = "16'b0000000011111011" *) (* LC_LOW_BIT_POS_PROBE_OUT252 = "16'b0000000011111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT253 = "16'b0000000011111101" *) (* LC_LOW_BIT_POS_PROBE_OUT254 = "16'b0000000011111110" *) (* LC_LOW_BIT_POS_PROBE_OUT255 = "16'b0000000011111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT26 = "16'b0000000000011010" *) (* LC_LOW_BIT_POS_PROBE_OUT27 = "16'b0000000000011011" *) (* LC_LOW_BIT_POS_PROBE_OUT28 = "16'b0000000000011100" *)
(* LC_LOW_BIT_POS_PROBE_OUT29 = "16'b0000000000011101" *) (* LC_LOW_BIT_POS_PROBE_OUT3 = "16'b0000000000000011" *) (* LC_LOW_BIT_POS_PROBE_OUT30 = "16'b0000000000011110" *)
(* LC_LOW_BIT_POS_PROBE_OUT31 = "16'b0000000000011111" *) (* LC_LOW_BIT_POS_PROBE_OUT32 = "16'b0000000000100000" *) (* LC_LOW_BIT_POS_PROBE_OUT33 = "16'b0000000000100001" *)
(* LC_LOW_BIT_POS_PROBE_OUT34 = "16'b0000000000100010" *) (* LC_LOW_BIT_POS_PROBE_OUT35 = "16'b0000000000100011" *) (* LC_LOW_BIT_POS_PROBE_OUT36 = "16'b0000000000100100" *)
(* LC_LOW_BIT_POS_PROBE_OUT37 = "16'b0000000000100101" *) (* LC_LOW_BIT_POS_PROBE_OUT38 = "16'b0000000000100110" *) (* LC_LOW_BIT_POS_PROBE_OUT39 = "16'b0000000000100111" *)
(* LC_LOW_BIT_POS_PROBE_OUT4 = "16'b0000000000000100" *) (* LC_LOW_BIT_POS_PROBE_OUT40 = "16'b0000000000101000" *) (* LC_LOW_BIT_POS_PROBE_OUT41 = "16'b0000000000101001" *)
(* LC_LOW_BIT_POS_PROBE_OUT42 = "16'b0000000000101010" *) (* LC_LOW_BIT_POS_PROBE_OUT43 = "16'b0000000000101011" *) (* LC_LOW_BIT_POS_PROBE_OUT44 = "16'b0000000000101100" *)
(* LC_LOW_BIT_POS_PROBE_OUT45 = "16'b0000000000101101" *) (* LC_LOW_BIT_POS_PROBE_OUT46 = "16'b0000000000101110" *) (* LC_LOW_BIT_POS_PROBE_OUT47 = "16'b0000000000101111" *)
(* LC_LOW_BIT_POS_PROBE_OUT48 = "16'b0000000000110000" *) (* LC_LOW_BIT_POS_PROBE_OUT49 = "16'b0000000000110001" *) (* LC_LOW_BIT_POS_PROBE_OUT5 = "16'b0000000000000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT50 = "16'b0000000000110010" *) (* LC_LOW_BIT_POS_PROBE_OUT51 = "16'b0000000000110011" *) (* LC_LOW_BIT_POS_PROBE_OUT52 = "16'b0000000000110100" *)
(* LC_LOW_BIT_POS_PROBE_OUT53 = "16'b0000000000110101" *) (* LC_LOW_BIT_POS_PROBE_OUT54 = "16'b0000000000110110" *) (* LC_LOW_BIT_POS_PROBE_OUT55 = "16'b0000000000110111" *)
(* LC_LOW_BIT_POS_PROBE_OUT56 = "16'b0000000000111000" *) (* LC_LOW_BIT_POS_PROBE_OUT57 = "16'b0000000000111001" *) (* LC_LOW_BIT_POS_PROBE_OUT58 = "16'b0000000000111010" *)
(* LC_LOW_BIT_POS_PROBE_OUT59 = "16'b0000000000111011" *) (* LC_LOW_BIT_POS_PROBE_OUT6 = "16'b0000000000000110" *) (* LC_LOW_BIT_POS_PROBE_OUT60 = "16'b0000000000111100" *)
(* LC_LOW_BIT_POS_PROBE_OUT61 = "16'b0000000000111101" *) (* LC_LOW_BIT_POS_PROBE_OUT62 = "16'b0000000000111110" *) (* LC_LOW_BIT_POS_PROBE_OUT63 = "16'b0000000000111111" *)
(* LC_LOW_BIT_POS_PROBE_OUT64 = "16'b0000000001000000" *) (* LC_LOW_BIT_POS_PROBE_OUT65 = "16'b0000000001000001" *) (* LC_LOW_BIT_POS_PROBE_OUT66 = "16'b0000000001000010" *)
(* LC_LOW_BIT_POS_PROBE_OUT67 = "16'b0000000001000011" *) (* LC_LOW_BIT_POS_PROBE_OUT68 = "16'b0000000001000100" *) (* LC_LOW_BIT_POS_PROBE_OUT69 = "16'b0000000001000101" *)
(* LC_LOW_BIT_POS_PROBE_OUT7 = "16'b0000000000000111" *) (* LC_LOW_BIT_POS_PROBE_OUT70 = "16'b0000000001000110" *) (* LC_LOW_BIT_POS_PROBE_OUT71 = "16'b0000000001000111" *)
(* LC_LOW_BIT_POS_PROBE_OUT72 = "16'b0000000001001000" *) (* LC_LOW_BIT_POS_PROBE_OUT73 = "16'b0000000001001001" *) (* LC_LOW_BIT_POS_PROBE_OUT74 = "16'b0000000001001010" *)
(* LC_LOW_BIT_POS_PROBE_OUT75 = "16'b0000000001001011" *) (* LC_LOW_BIT_POS_PROBE_OUT76 = "16'b0000000001001100" *) (* LC_LOW_BIT_POS_PROBE_OUT77 = "16'b0000000001001101" *)
(* LC_LOW_BIT_POS_PROBE_OUT78 = "16'b0000000001001110" *) (* LC_LOW_BIT_POS_PROBE_OUT79 = "16'b0000000001001111" *) (* LC_LOW_BIT_POS_PROBE_OUT8 = "16'b0000000000001000" *)
(* LC_LOW_BIT_POS_PROBE_OUT80 = "16'b0000000001010000" *) (* LC_LOW_BIT_POS_PROBE_OUT81 = "16'b0000000001010001" *) (* LC_LOW_BIT_POS_PROBE_OUT82 = "16'b0000000001010010" *)
(* LC_LOW_BIT_POS_PROBE_OUT83 = "16'b0000000001010011" *) (* LC_LOW_BIT_POS_PROBE_OUT84 = "16'b0000000001010100" *) (* LC_LOW_BIT_POS_PROBE_OUT85 = "16'b0000000001010101" *)
(* LC_LOW_BIT_POS_PROBE_OUT86 = "16'b0000000001010110" *) (* LC_LOW_BIT_POS_PROBE_OUT87 = "16'b0000000001010111" *) (* LC_LOW_BIT_POS_PROBE_OUT88 = "16'b0000000001011000" *)
(* LC_LOW_BIT_POS_PROBE_OUT89 = "16'b0000000001011001" *) (* LC_LOW_BIT_POS_PROBE_OUT9 = "16'b0000000000001001" *) (* LC_LOW_BIT_POS_PROBE_OUT90 = "16'b0000000001011010" *)
(* LC_LOW_BIT_POS_PROBE_OUT91 = "16'b0000000001011011" *) (* LC_LOW_BIT_POS_PROBE_OUT92 = "16'b0000000001011100" *) (* LC_LOW_BIT_POS_PROBE_OUT93 = "16'b0000000001011101" *)
(* LC_LOW_BIT_POS_PROBE_OUT94 = "16'b0000000001011110" *) (* LC_LOW_BIT_POS_PROBE_OUT95 = "16'b0000000001011111" *) (* LC_LOW_BIT_POS_PROBE_OUT96 = "16'b0000000001100000" *)
(* LC_LOW_BIT_POS_PROBE_OUT97 = "16'b0000000001100001" *) (* LC_LOW_BIT_POS_PROBE_OUT98 = "16'b0000000001100010" *) (* LC_LOW_BIT_POS_PROBE_OUT99 = "16'b0000000001100011" *)
(* LC_PROBE_IN_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_PROBE_OUT_HIGH_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_INIT_VAL_STRING = "256'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* LC_PROBE_OUT_LOW_BIT_POS_STRING = "4096'b0000000011111111000000001111111000000000111111010000000011111100000000001111101100000000111110100000000011111001000000001111100000000000111101110000000011110110000000001111010100000000111101000000000011110011000000001111001000000000111100010000000011110000000000001110111100000000111011100000000011101101000000001110110000000000111010110000000011101010000000001110100100000000111010000000000011100111000000001110011000000000111001010000000011100100000000001110001100000000111000100000000011100001000000001110000000000000110111110000000011011110000000001101110100000000110111000000000011011011000000001101101000000000110110010000000011011000000000001101011100000000110101100000000011010101000000001101010000000000110100110000000011010010000000001101000100000000110100000000000011001111000000001100111000000000110011010000000011001100000000001100101100000000110010100000000011001001000000001100100000000000110001110000000011000110000000001100010100000000110001000000000011000011000000001100001000000000110000010000000011000000000000001011111100000000101111100000000010111101000000001011110000000000101110110000000010111010000000001011100100000000101110000000000010110111000000001011011000000000101101010000000010110100000000001011001100000000101100100000000010110001000000001011000000000000101011110000000010101110000000001010110100000000101011000000000010101011000000001010101000000000101010010000000010101000000000001010011100000000101001100000000010100101000000001010010000000000101000110000000010100010000000001010000100000000101000000000000010011111000000001001111000000000100111010000000010011100000000001001101100000000100110100000000010011001000000001001100000000000100101110000000010010110000000001001010100000000100101000000000010010011000000001001001000000000100100010000000010010000000000001000111100000000100011100000000010001101000000001000110000000000100010110000000010001010000000001000100100000000100010000000000010000111000000001000011000000000100001010000000010000100000000001000001100000000100000100000000010000001000000001000000000000000011111110000000001111110000000000111110100000000011111000000000001111011000000000111101000000000011110010000000001111000000000000111011100000000011101100000000001110101000000000111010000000000011100110000000001110010000000000111000100000000011100000000000001101111000000000110111000000000011011010000000001101100000000000110101100000000011010100000000001101001000000000110100000000000011001110000000001100110000000000110010100000000011001000000000001100011000000000110001000000000011000010000000001100000000000000101111100000000010111100000000001011101000000000101110000000000010110110000000001011010000000000101100100000000010110000000000001010111000000000101011000000000010101010000000001010100000000000101001100000000010100100000000001010001000000000101000000000000010011110000000001001110000000000100110100000000010011000000000001001011000000000100101000000000010010010000000001001000000000000100011100000000010001100000000001000101000000000100010000000000010000110000000001000010000000000100000100000000010000000000000000111111000000000011111000000000001111010000000000111100000000000011101100000000001110100000000000111001000000000011100000000000001101110000000000110110000000000011010100000000001101000000000000110011000000000011001000000000001100010000000000110000000000000010111100000000001011100000000000101101000000000010110000000000001010110000000000101010000000000010100100000000001010000000000000100111000000000010011000000000001001010000000000100100000000000010001100000000001000100000000000100001000000000010000000000000000111110000000000011110000000000001110100000000000111000000000000011011000000000001101000000000000110010000000000011000000000000001011100000000000101100000000000010101000000000001010000000000000100110000000000010010000000000001000100000000000100000000000000001111000000000000111000000000000011010000000000001100000000000000101100000000000010100000000000001001000000000000100000000000000001110000000000000110000000000000010100000000000001000000000000000011000000000000001000000000000000010000000000000000" *) (* LC_PROBE_OUT_WIDTH_STRING = "2048'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* LC_TOTAL_PROBE_IN_WIDTH = "4" *)
(* LC_TOTAL_PROBE_OUT_WIDTH = "0" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_vio
(clk,
probe_in0,
probe_in1,
probe_in2,
probe_in3,
probe_in4,
probe_in5,
probe_in6,
probe_in7,
probe_in8,
probe_in9,
probe_in10,
probe_in11,
probe_in12,
probe_in13,
probe_in14,
probe_in15,
probe_in16,
probe_in17,
probe_in18,
probe_in19,
probe_in20,
probe_in21,
probe_in22,
probe_in23,
probe_in24,
probe_in25,
probe_in26,
probe_in27,
probe_in28,
probe_in29,
probe_in30,
probe_in31,
probe_in32,
probe_in33,
probe_in34,
probe_in35,
probe_in36,
probe_in37,
probe_in38,
probe_in39,
probe_in40,
probe_in41,
probe_in42,
probe_in43,
probe_in44,
probe_in45,
probe_in46,
probe_in47,
probe_in48,
probe_in49,
probe_in50,
probe_in51,
probe_in52,
probe_in53,
probe_in54,
probe_in55,
probe_in56,
probe_in57,
probe_in58,
probe_in59,
probe_in60,
probe_in61,
probe_in62,
probe_in63,
probe_in64,
probe_in65,
probe_in66,
probe_in67,
probe_in68,
probe_in69,
probe_in70,
probe_in71,
probe_in72,
probe_in73,
probe_in74,
probe_in75,
probe_in76,
probe_in77,
probe_in78,
probe_in79,
probe_in80,
probe_in81,
probe_in82,
probe_in83,
probe_in84,
probe_in85,
probe_in86,
probe_in87,
probe_in88,
probe_in89,
probe_in90,
probe_in91,
probe_in92,
probe_in93,
probe_in94,
probe_in95,
probe_in96,
probe_in97,
probe_in98,
probe_in99,
probe_in100,
probe_in101,
probe_in102,
probe_in103,
probe_in104,
probe_in105,
probe_in106,
probe_in107,
probe_in108,
probe_in109,
probe_in110,
probe_in111,
probe_in112,
probe_in113,
probe_in114,
probe_in115,
probe_in116,
probe_in117,
probe_in118,
probe_in119,
probe_in120,
probe_in121,
probe_in122,
probe_in123,
probe_in124,
probe_in125,
probe_in126,
probe_in127,
probe_in128,
probe_in129,
probe_in130,
probe_in131,
probe_in132,
probe_in133,
probe_in134,
probe_in135,
probe_in136,
probe_in137,
probe_in138,
probe_in139,
probe_in140,
probe_in141,
probe_in142,
probe_in143,
probe_in144,
probe_in145,
probe_in146,
probe_in147,
probe_in148,
probe_in149,
probe_in150,
probe_in151,
probe_in152,
probe_in153,
probe_in154,
probe_in155,
probe_in156,
probe_in157,
probe_in158,
probe_in159,
probe_in160,
probe_in161,
probe_in162,
probe_in163,
probe_in164,
probe_in165,
probe_in166,
probe_in167,
probe_in168,
probe_in169,
probe_in170,
probe_in171,
probe_in172,
probe_in173,
probe_in174,
probe_in175,
probe_in176,
probe_in177,
probe_in178,
probe_in179,
probe_in180,
probe_in181,
probe_in182,
probe_in183,
probe_in184,
probe_in185,
probe_in186,
probe_in187,
probe_in188,
probe_in189,
probe_in190,
probe_in191,
probe_in192,
probe_in193,
probe_in194,
probe_in195,
probe_in196,
probe_in197,
probe_in198,
probe_in199,
probe_in200,
probe_in201,
probe_in202,
probe_in203,
probe_in204,
probe_in205,
probe_in206,
probe_in207,
probe_in208,
probe_in209,
probe_in210,
probe_in211,
probe_in212,
probe_in213,
probe_in214,
probe_in215,
probe_in216,
probe_in217,
probe_in218,
probe_in219,
probe_in220,
probe_in221,
probe_in222,
probe_in223,
probe_in224,
probe_in225,
probe_in226,
probe_in227,
probe_in228,
probe_in229,
probe_in230,
probe_in231,
probe_in232,
probe_in233,
probe_in234,
probe_in235,
probe_in236,
probe_in237,
probe_in238,
probe_in239,
probe_in240,
probe_in241,
probe_in242,
probe_in243,
probe_in244,
probe_in245,
probe_in246,
probe_in247,
probe_in248,
probe_in249,
probe_in250,
probe_in251,
probe_in252,
probe_in253,
probe_in254,
probe_in255,
sl_iport0,
sl_oport0,
probe_out0,
probe_out1,
probe_out2,
probe_out3,
probe_out4,
probe_out5,
probe_out6,
probe_out7,
probe_out8,
probe_out9,
probe_out10,
probe_out11,
probe_out12,
probe_out13,
probe_out14,
probe_out15,
probe_out16,
probe_out17,
probe_out18,
probe_out19,
probe_out20,
probe_out21,
probe_out22,
probe_out23,
probe_out24,
probe_out25,
probe_out26,
probe_out27,
probe_out28,
probe_out29,
probe_out30,
probe_out31,
probe_out32,
probe_out33,
probe_out34,
probe_out35,
probe_out36,
probe_out37,
probe_out38,
probe_out39,
probe_out40,
probe_out41,
probe_out42,
probe_out43,
probe_out44,
probe_out45,
probe_out46,
probe_out47,
probe_out48,
probe_out49,
probe_out50,
probe_out51,
probe_out52,
probe_out53,
probe_out54,
probe_out55,
probe_out56,
probe_out57,
probe_out58,
probe_out59,
probe_out60,
probe_out61,
probe_out62,
probe_out63,
probe_out64,
probe_out65,
probe_out66,
probe_out67,
probe_out68,
probe_out69,
probe_out70,
probe_out71,
probe_out72,
probe_out73,
probe_out74,
probe_out75,
probe_out76,
probe_out77,
probe_out78,
probe_out79,
probe_out80,
probe_out81,
probe_out82,
probe_out83,
probe_out84,
probe_out85,
probe_out86,
probe_out87,
probe_out88,
probe_out89,
probe_out90,
probe_out91,
probe_out92,
probe_out93,
probe_out94,
probe_out95,
probe_out96,
probe_out97,
probe_out98,
probe_out99,
probe_out100,
probe_out101,
probe_out102,
probe_out103,
probe_out104,
probe_out105,
probe_out106,
probe_out107,
probe_out108,
probe_out109,
probe_out110,
probe_out111,
probe_out112,
probe_out113,
probe_out114,
probe_out115,
probe_out116,
probe_out117,
probe_out118,
probe_out119,
probe_out120,
probe_out121,
probe_out122,
probe_out123,
probe_out124,
probe_out125,
probe_out126,
probe_out127,
probe_out128,
probe_out129,
probe_out130,
probe_out131,
probe_out132,
probe_out133,
probe_out134,
probe_out135,
probe_out136,
probe_out137,
probe_out138,
probe_out139,
probe_out140,
probe_out141,
probe_out142,
probe_out143,
probe_out144,
probe_out145,
probe_out146,
probe_out147,
probe_out148,
probe_out149,
probe_out150,
probe_out151,
probe_out152,
probe_out153,
probe_out154,
probe_out155,
probe_out156,
probe_out157,
probe_out158,
probe_out159,
probe_out160,
probe_out161,
probe_out162,
probe_out163,
probe_out164,
probe_out165,
probe_out166,
probe_out167,
probe_out168,
probe_out169,
probe_out170,
probe_out171,
probe_out172,
probe_out173,
probe_out174,
probe_out175,
probe_out176,
probe_out177,
probe_out178,
probe_out179,
probe_out180,
probe_out181,
probe_out182,
probe_out183,
probe_out184,
probe_out185,
probe_out186,
probe_out187,
probe_out188,
probe_out189,
probe_out190,
probe_out191,
probe_out192,
probe_out193,
probe_out194,
probe_out195,
probe_out196,
probe_out197,
probe_out198,
probe_out199,
probe_out200,
probe_out201,
probe_out202,
probe_out203,
probe_out204,
probe_out205,
probe_out206,
probe_out207,
probe_out208,
probe_out209,
probe_out210,
probe_out211,
probe_out212,
probe_out213,
probe_out214,
probe_out215,
probe_out216,
probe_out217,
probe_out218,
probe_out219,
probe_out220,
probe_out221,
probe_out222,
probe_out223,
probe_out224,
probe_out225,
probe_out226,
probe_out227,
probe_out228,
probe_out229,
probe_out230,
probe_out231,
probe_out232,
probe_out233,
probe_out234,
probe_out235,
probe_out236,
probe_out237,
probe_out238,
probe_out239,
probe_out240,
probe_out241,
probe_out242,
probe_out243,
probe_out244,
probe_out245,
probe_out246,
probe_out247,
probe_out248,
probe_out249,
probe_out250,
probe_out251,
probe_out252,
probe_out253,
probe_out254,
probe_out255);
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
input [0:0]probe_in4;
input [0:0]probe_in5;
input [0:0]probe_in6;
input [0:0]probe_in7;
input [0:0]probe_in8;
input [0:0]probe_in9;
input [0:0]probe_in10;
input [0:0]probe_in11;
input [0:0]probe_in12;
input [0:0]probe_in13;
input [0:0]probe_in14;
input [0:0]probe_in15;
input [0:0]probe_in16;
input [0:0]probe_in17;
input [0:0]probe_in18;
input [0:0]probe_in19;
input [0:0]probe_in20;
input [0:0]probe_in21;
input [0:0]probe_in22;
input [0:0]probe_in23;
input [0:0]probe_in24;
input [0:0]probe_in25;
input [0:0]probe_in26;
input [0:0]probe_in27;
input [0:0]probe_in28;
input [0:0]probe_in29;
input [0:0]probe_in30;
input [0:0]probe_in31;
input [0:0]probe_in32;
input [0:0]probe_in33;
input [0:0]probe_in34;
input [0:0]probe_in35;
input [0:0]probe_in36;
input [0:0]probe_in37;
input [0:0]probe_in38;
input [0:0]probe_in39;
input [0:0]probe_in40;
input [0:0]probe_in41;
input [0:0]probe_in42;
input [0:0]probe_in43;
input [0:0]probe_in44;
input [0:0]probe_in45;
input [0:0]probe_in46;
input [0:0]probe_in47;
input [0:0]probe_in48;
input [0:0]probe_in49;
input [0:0]probe_in50;
input [0:0]probe_in51;
input [0:0]probe_in52;
input [0:0]probe_in53;
input [0:0]probe_in54;
input [0:0]probe_in55;
input [0:0]probe_in56;
input [0:0]probe_in57;
input [0:0]probe_in58;
input [0:0]probe_in59;
input [0:0]probe_in60;
input [0:0]probe_in61;
input [0:0]probe_in62;
input [0:0]probe_in63;
input [0:0]probe_in64;
input [0:0]probe_in65;
input [0:0]probe_in66;
input [0:0]probe_in67;
input [0:0]probe_in68;
input [0:0]probe_in69;
input [0:0]probe_in70;
input [0:0]probe_in71;
input [0:0]probe_in72;
input [0:0]probe_in73;
input [0:0]probe_in74;
input [0:0]probe_in75;
input [0:0]probe_in76;
input [0:0]probe_in77;
input [0:0]probe_in78;
input [0:0]probe_in79;
input [0:0]probe_in80;
input [0:0]probe_in81;
input [0:0]probe_in82;
input [0:0]probe_in83;
input [0:0]probe_in84;
input [0:0]probe_in85;
input [0:0]probe_in86;
input [0:0]probe_in87;
input [0:0]probe_in88;
input [0:0]probe_in89;
input [0:0]probe_in90;
input [0:0]probe_in91;
input [0:0]probe_in92;
input [0:0]probe_in93;
input [0:0]probe_in94;
input [0:0]probe_in95;
input [0:0]probe_in96;
input [0:0]probe_in97;
input [0:0]probe_in98;
input [0:0]probe_in99;
input [0:0]probe_in100;
input [0:0]probe_in101;
input [0:0]probe_in102;
input [0:0]probe_in103;
input [0:0]probe_in104;
input [0:0]probe_in105;
input [0:0]probe_in106;
input [0:0]probe_in107;
input [0:0]probe_in108;
input [0:0]probe_in109;
input [0:0]probe_in110;
input [0:0]probe_in111;
input [0:0]probe_in112;
input [0:0]probe_in113;
input [0:0]probe_in114;
input [0:0]probe_in115;
input [0:0]probe_in116;
input [0:0]probe_in117;
input [0:0]probe_in118;
input [0:0]probe_in119;
input [0:0]probe_in120;
input [0:0]probe_in121;
input [0:0]probe_in122;
input [0:0]probe_in123;
input [0:0]probe_in124;
input [0:0]probe_in125;
input [0:0]probe_in126;
input [0:0]probe_in127;
input [0:0]probe_in128;
input [0:0]probe_in129;
input [0:0]probe_in130;
input [0:0]probe_in131;
input [0:0]probe_in132;
input [0:0]probe_in133;
input [0:0]probe_in134;
input [0:0]probe_in135;
input [0:0]probe_in136;
input [0:0]probe_in137;
input [0:0]probe_in138;
input [0:0]probe_in139;
input [0:0]probe_in140;
input [0:0]probe_in141;
input [0:0]probe_in142;
input [0:0]probe_in143;
input [0:0]probe_in144;
input [0:0]probe_in145;
input [0:0]probe_in146;
input [0:0]probe_in147;
input [0:0]probe_in148;
input [0:0]probe_in149;
input [0:0]probe_in150;
input [0:0]probe_in151;
input [0:0]probe_in152;
input [0:0]probe_in153;
input [0:0]probe_in154;
input [0:0]probe_in155;
input [0:0]probe_in156;
input [0:0]probe_in157;
input [0:0]probe_in158;
input [0:0]probe_in159;
input [0:0]probe_in160;
input [0:0]probe_in161;
input [0:0]probe_in162;
input [0:0]probe_in163;
input [0:0]probe_in164;
input [0:0]probe_in165;
input [0:0]probe_in166;
input [0:0]probe_in167;
input [0:0]probe_in168;
input [0:0]probe_in169;
input [0:0]probe_in170;
input [0:0]probe_in171;
input [0:0]probe_in172;
input [0:0]probe_in173;
input [0:0]probe_in174;
input [0:0]probe_in175;
input [0:0]probe_in176;
input [0:0]probe_in177;
input [0:0]probe_in178;
input [0:0]probe_in179;
input [0:0]probe_in180;
input [0:0]probe_in181;
input [0:0]probe_in182;
input [0:0]probe_in183;
input [0:0]probe_in184;
input [0:0]probe_in185;
input [0:0]probe_in186;
input [0:0]probe_in187;
input [0:0]probe_in188;
input [0:0]probe_in189;
input [0:0]probe_in190;
input [0:0]probe_in191;
input [0:0]probe_in192;
input [0:0]probe_in193;
input [0:0]probe_in194;
input [0:0]probe_in195;
input [0:0]probe_in196;
input [0:0]probe_in197;
input [0:0]probe_in198;
input [0:0]probe_in199;
input [0:0]probe_in200;
input [0:0]probe_in201;
input [0:0]probe_in202;
input [0:0]probe_in203;
input [0:0]probe_in204;
input [0:0]probe_in205;
input [0:0]probe_in206;
input [0:0]probe_in207;
input [0:0]probe_in208;
input [0:0]probe_in209;
input [0:0]probe_in210;
input [0:0]probe_in211;
input [0:0]probe_in212;
input [0:0]probe_in213;
input [0:0]probe_in214;
input [0:0]probe_in215;
input [0:0]probe_in216;
input [0:0]probe_in217;
input [0:0]probe_in218;
input [0:0]probe_in219;
input [0:0]probe_in220;
input [0:0]probe_in221;
input [0:0]probe_in222;
input [0:0]probe_in223;
input [0:0]probe_in224;
input [0:0]probe_in225;
input [0:0]probe_in226;
input [0:0]probe_in227;
input [0:0]probe_in228;
input [0:0]probe_in229;
input [0:0]probe_in230;
input [0:0]probe_in231;
input [0:0]probe_in232;
input [0:0]probe_in233;
input [0:0]probe_in234;
input [0:0]probe_in235;
input [0:0]probe_in236;
input [0:0]probe_in237;
input [0:0]probe_in238;
input [0:0]probe_in239;
input [0:0]probe_in240;
input [0:0]probe_in241;
input [0:0]probe_in242;
input [0:0]probe_in243;
input [0:0]probe_in244;
input [0:0]probe_in245;
input [0:0]probe_in246;
input [0:0]probe_in247;
input [0:0]probe_in248;
input [0:0]probe_in249;
input [0:0]probe_in250;
input [0:0]probe_in251;
input [0:0]probe_in252;
input [0:0]probe_in253;
input [0:0]probe_in254;
input [0:0]probe_in255;
(* dont_touch = "true" *) input [36:0]sl_iport0;
(* dont_touch = "true" *) output [16:0]sl_oport0;
output [0:0]probe_out0;
output [0:0]probe_out1;
output [0:0]probe_out2;
output [0:0]probe_out3;
output [0:0]probe_out4;
output [0:0]probe_out5;
output [0:0]probe_out6;
output [0:0]probe_out7;
output [0:0]probe_out8;
output [0:0]probe_out9;
output [0:0]probe_out10;
output [0:0]probe_out11;
output [0:0]probe_out12;
output [0:0]probe_out13;
output [0:0]probe_out14;
output [0:0]probe_out15;
output [0:0]probe_out16;
output [0:0]probe_out17;
output [0:0]probe_out18;
output [0:0]probe_out19;
output [0:0]probe_out20;
output [0:0]probe_out21;
output [0:0]probe_out22;
output [0:0]probe_out23;
output [0:0]probe_out24;
output [0:0]probe_out25;
output [0:0]probe_out26;
output [0:0]probe_out27;
output [0:0]probe_out28;
output [0:0]probe_out29;
output [0:0]probe_out30;
output [0:0]probe_out31;
output [0:0]probe_out32;
output [0:0]probe_out33;
output [0:0]probe_out34;
output [0:0]probe_out35;
output [0:0]probe_out36;
output [0:0]probe_out37;
output [0:0]probe_out38;
output [0:0]probe_out39;
output [0:0]probe_out40;
output [0:0]probe_out41;
output [0:0]probe_out42;
output [0:0]probe_out43;
output [0:0]probe_out44;
output [0:0]probe_out45;
output [0:0]probe_out46;
output [0:0]probe_out47;
output [0:0]probe_out48;
output [0:0]probe_out49;
output [0:0]probe_out50;
output [0:0]probe_out51;
output [0:0]probe_out52;
output [0:0]probe_out53;
output [0:0]probe_out54;
output [0:0]probe_out55;
output [0:0]probe_out56;
output [0:0]probe_out57;
output [0:0]probe_out58;
output [0:0]probe_out59;
output [0:0]probe_out60;
output [0:0]probe_out61;
output [0:0]probe_out62;
output [0:0]probe_out63;
output [0:0]probe_out64;
output [0:0]probe_out65;
output [0:0]probe_out66;
output [0:0]probe_out67;
output [0:0]probe_out68;
output [0:0]probe_out69;
output [0:0]probe_out70;
output [0:0]probe_out71;
output [0:0]probe_out72;
output [0:0]probe_out73;
output [0:0]probe_out74;
output [0:0]probe_out75;
output [0:0]probe_out76;
output [0:0]probe_out77;
output [0:0]probe_out78;
output [0:0]probe_out79;
output [0:0]probe_out80;
output [0:0]probe_out81;
output [0:0]probe_out82;
output [0:0]probe_out83;
output [0:0]probe_out84;
output [0:0]probe_out85;
output [0:0]probe_out86;
output [0:0]probe_out87;
output [0:0]probe_out88;
output [0:0]probe_out89;
output [0:0]probe_out90;
output [0:0]probe_out91;
output [0:0]probe_out92;
output [0:0]probe_out93;
output [0:0]probe_out94;
output [0:0]probe_out95;
output [0:0]probe_out96;
output [0:0]probe_out97;
output [0:0]probe_out98;
output [0:0]probe_out99;
output [0:0]probe_out100;
output [0:0]probe_out101;
output [0:0]probe_out102;
output [0:0]probe_out103;
output [0:0]probe_out104;
output [0:0]probe_out105;
output [0:0]probe_out106;
output [0:0]probe_out107;
output [0:0]probe_out108;
output [0:0]probe_out109;
output [0:0]probe_out110;
output [0:0]probe_out111;
output [0:0]probe_out112;
output [0:0]probe_out113;
output [0:0]probe_out114;
output [0:0]probe_out115;
output [0:0]probe_out116;
output [0:0]probe_out117;
output [0:0]probe_out118;
output [0:0]probe_out119;
output [0:0]probe_out120;
output [0:0]probe_out121;
output [0:0]probe_out122;
output [0:0]probe_out123;
output [0:0]probe_out124;
output [0:0]probe_out125;
output [0:0]probe_out126;
output [0:0]probe_out127;
output [0:0]probe_out128;
output [0:0]probe_out129;
output [0:0]probe_out130;
output [0:0]probe_out131;
output [0:0]probe_out132;
output [0:0]probe_out133;
output [0:0]probe_out134;
output [0:0]probe_out135;
output [0:0]probe_out136;
output [0:0]probe_out137;
output [0:0]probe_out138;
output [0:0]probe_out139;
output [0:0]probe_out140;
output [0:0]probe_out141;
output [0:0]probe_out142;
output [0:0]probe_out143;
output [0:0]probe_out144;
output [0:0]probe_out145;
output [0:0]probe_out146;
output [0:0]probe_out147;
output [0:0]probe_out148;
output [0:0]probe_out149;
output [0:0]probe_out150;
output [0:0]probe_out151;
output [0:0]probe_out152;
output [0:0]probe_out153;
output [0:0]probe_out154;
output [0:0]probe_out155;
output [0:0]probe_out156;
output [0:0]probe_out157;
output [0:0]probe_out158;
output [0:0]probe_out159;
output [0:0]probe_out160;
output [0:0]probe_out161;
output [0:0]probe_out162;
output [0:0]probe_out163;
output [0:0]probe_out164;
output [0:0]probe_out165;
output [0:0]probe_out166;
output [0:0]probe_out167;
output [0:0]probe_out168;
output [0:0]probe_out169;
output [0:0]probe_out170;
output [0:0]probe_out171;
output [0:0]probe_out172;
output [0:0]probe_out173;
output [0:0]probe_out174;
output [0:0]probe_out175;
output [0:0]probe_out176;
output [0:0]probe_out177;
output [0:0]probe_out178;
output [0:0]probe_out179;
output [0:0]probe_out180;
output [0:0]probe_out181;
output [0:0]probe_out182;
output [0:0]probe_out183;
output [0:0]probe_out184;
output [0:0]probe_out185;
output [0:0]probe_out186;
output [0:0]probe_out187;
output [0:0]probe_out188;
output [0:0]probe_out189;
output [0:0]probe_out190;
output [0:0]probe_out191;
output [0:0]probe_out192;
output [0:0]probe_out193;
output [0:0]probe_out194;
output [0:0]probe_out195;
output [0:0]probe_out196;
output [0:0]probe_out197;
output [0:0]probe_out198;
output [0:0]probe_out199;
output [0:0]probe_out200;
output [0:0]probe_out201;
output [0:0]probe_out202;
output [0:0]probe_out203;
output [0:0]probe_out204;
output [0:0]probe_out205;
output [0:0]probe_out206;
output [0:0]probe_out207;
output [0:0]probe_out208;
output [0:0]probe_out209;
output [0:0]probe_out210;
output [0:0]probe_out211;
output [0:0]probe_out212;
output [0:0]probe_out213;
output [0:0]probe_out214;
output [0:0]probe_out215;
output [0:0]probe_out216;
output [0:0]probe_out217;
output [0:0]probe_out218;
output [0:0]probe_out219;
output [0:0]probe_out220;
output [0:0]probe_out221;
output [0:0]probe_out222;
output [0:0]probe_out223;
output [0:0]probe_out224;
output [0:0]probe_out225;
output [0:0]probe_out226;
output [0:0]probe_out227;
output [0:0]probe_out228;
output [0:0]probe_out229;
output [0:0]probe_out230;
output [0:0]probe_out231;
output [0:0]probe_out232;
output [0:0]probe_out233;
output [0:0]probe_out234;
output [0:0]probe_out235;
output [0:0]probe_out236;
output [0:0]probe_out237;
output [0:0]probe_out238;
output [0:0]probe_out239;
output [0:0]probe_out240;
output [0:0]probe_out241;
output [0:0]probe_out242;
output [0:0]probe_out243;
output [0:0]probe_out244;
output [0:0]probe_out245;
output [0:0]probe_out246;
output [0:0]probe_out247;
output [0:0]probe_out248;
output [0:0]probe_out249;
output [0:0]probe_out250;
output [0:0]probe_out251;
output [0:0]probe_out252;
output [0:0]probe_out253;
output [0:0]probe_out254;
output [0:0]probe_out255;
wire \<const0> ;
wire [11:0]Bus_Data_out;
wire DECODER_INST_n_1;
wire DECODER_INST_n_2;
wire DECODER_INST_n_3;
wire DECODER_INST_n_4;
wire [16:0]bus_addr;
(* DONT_TOUCH *) wire bus_clk;
wire \bus_data_int_reg_n_0_[0] ;
wire \bus_data_int_reg_n_0_[10] ;
wire \bus_data_int_reg_n_0_[11] ;
wire \bus_data_int_reg_n_0_[12] ;
wire \bus_data_int_reg_n_0_[13] ;
wire \bus_data_int_reg_n_0_[14] ;
wire \bus_data_int_reg_n_0_[15] ;
wire \bus_data_int_reg_n_0_[2] ;
wire \bus_data_int_reg_n_0_[3] ;
wire \bus_data_int_reg_n_0_[4] ;
wire \bus_data_int_reg_n_0_[5] ;
wire \bus_data_int_reg_n_0_[6] ;
wire \bus_data_int_reg_n_0_[7] ;
wire \bus_data_int_reg_n_0_[8] ;
wire \bus_data_int_reg_n_0_[9] ;
wire bus_den;
wire [15:0]bus_di;
wire [15:0]bus_do;
wire bus_drdy;
wire bus_dwe;
wire bus_rst;
wire clk;
wire p_0_in;
wire [0:0]probe_in0;
wire [0:0]probe_in1;
wire [0:0]probe_in2;
wire [0:0]probe_in3;
(* DONT_TOUCH *) wire [36:0]sl_iport0;
(* DONT_TOUCH *) wire [16:0]sl_oport0;
assign probe_out0[0] = \<const0> ;
assign probe_out1[0] = \<const0> ;
assign probe_out10[0] = \<const0> ;
assign probe_out100[0] = \<const0> ;
assign probe_out101[0] = \<const0> ;
assign probe_out102[0] = \<const0> ;
assign probe_out103[0] = \<const0> ;
assign probe_out104[0] = \<const0> ;
assign probe_out105[0] = \<const0> ;
assign probe_out106[0] = \<const0> ;
assign probe_out107[0] = \<const0> ;
assign probe_out108[0] = \<const0> ;
assign probe_out109[0] = \<const0> ;
assign probe_out11[0] = \<const0> ;
assign probe_out110[0] = \<const0> ;
assign probe_out111[0] = \<const0> ;
assign probe_out112[0] = \<const0> ;
assign probe_out113[0] = \<const0> ;
assign probe_out114[0] = \<const0> ;
assign probe_out115[0] = \<const0> ;
assign probe_out116[0] = \<const0> ;
assign probe_out117[0] = \<const0> ;
assign probe_out118[0] = \<const0> ;
assign probe_out119[0] = \<const0> ;
assign probe_out12[0] = \<const0> ;
assign probe_out120[0] = \<const0> ;
assign probe_out121[0] = \<const0> ;
assign probe_out122[0] = \<const0> ;
assign probe_out123[0] = \<const0> ;
assign probe_out124[0] = \<const0> ;
assign probe_out125[0] = \<const0> ;
assign probe_out126[0] = \<const0> ;
assign probe_out127[0] = \<const0> ;
assign probe_out128[0] = \<const0> ;
assign probe_out129[0] = \<const0> ;
assign probe_out13[0] = \<const0> ;
assign probe_out130[0] = \<const0> ;
assign probe_out131[0] = \<const0> ;
assign probe_out132[0] = \<const0> ;
assign probe_out133[0] = \<const0> ;
assign probe_out134[0] = \<const0> ;
assign probe_out135[0] = \<const0> ;
assign probe_out136[0] = \<const0> ;
assign probe_out137[0] = \<const0> ;
assign probe_out138[0] = \<const0> ;
assign probe_out139[0] = \<const0> ;
assign probe_out14[0] = \<const0> ;
assign probe_out140[0] = \<const0> ;
assign probe_out141[0] = \<const0> ;
assign probe_out142[0] = \<const0> ;
assign probe_out143[0] = \<const0> ;
assign probe_out144[0] = \<const0> ;
assign probe_out145[0] = \<const0> ;
assign probe_out146[0] = \<const0> ;
assign probe_out147[0] = \<const0> ;
assign probe_out148[0] = \<const0> ;
assign probe_out149[0] = \<const0> ;
assign probe_out15[0] = \<const0> ;
assign probe_out150[0] = \<const0> ;
assign probe_out151[0] = \<const0> ;
assign probe_out152[0] = \<const0> ;
assign probe_out153[0] = \<const0> ;
assign probe_out154[0] = \<const0> ;
assign probe_out155[0] = \<const0> ;
assign probe_out156[0] = \<const0> ;
assign probe_out157[0] = \<const0> ;
assign probe_out158[0] = \<const0> ;
assign probe_out159[0] = \<const0> ;
assign probe_out16[0] = \<const0> ;
assign probe_out160[0] = \<const0> ;
assign probe_out161[0] = \<const0> ;
assign probe_out162[0] = \<const0> ;
assign probe_out163[0] = \<const0> ;
assign probe_out164[0] = \<const0> ;
assign probe_out165[0] = \<const0> ;
assign probe_out166[0] = \<const0> ;
assign probe_out167[0] = \<const0> ;
assign probe_out168[0] = \<const0> ;
assign probe_out169[0] = \<const0> ;
assign probe_out17[0] = \<const0> ;
assign probe_out170[0] = \<const0> ;
assign probe_out171[0] = \<const0> ;
assign probe_out172[0] = \<const0> ;
assign probe_out173[0] = \<const0> ;
assign probe_out174[0] = \<const0> ;
assign probe_out175[0] = \<const0> ;
assign probe_out176[0] = \<const0> ;
assign probe_out177[0] = \<const0> ;
assign probe_out178[0] = \<const0> ;
assign probe_out179[0] = \<const0> ;
assign probe_out18[0] = \<const0> ;
assign probe_out180[0] = \<const0> ;
assign probe_out181[0] = \<const0> ;
assign probe_out182[0] = \<const0> ;
assign probe_out183[0] = \<const0> ;
assign probe_out184[0] = \<const0> ;
assign probe_out185[0] = \<const0> ;
assign probe_out186[0] = \<const0> ;
assign probe_out187[0] = \<const0> ;
assign probe_out188[0] = \<const0> ;
assign probe_out189[0] = \<const0> ;
assign probe_out19[0] = \<const0> ;
assign probe_out190[0] = \<const0> ;
assign probe_out191[0] = \<const0> ;
assign probe_out192[0] = \<const0> ;
assign probe_out193[0] = \<const0> ;
assign probe_out194[0] = \<const0> ;
assign probe_out195[0] = \<const0> ;
assign probe_out196[0] = \<const0> ;
assign probe_out197[0] = \<const0> ;
assign probe_out198[0] = \<const0> ;
assign probe_out199[0] = \<const0> ;
assign probe_out2[0] = \<const0> ;
assign probe_out20[0] = \<const0> ;
assign probe_out200[0] = \<const0> ;
assign probe_out201[0] = \<const0> ;
assign probe_out202[0] = \<const0> ;
assign probe_out203[0] = \<const0> ;
assign probe_out204[0] = \<const0> ;
assign probe_out205[0] = \<const0> ;
assign probe_out206[0] = \<const0> ;
assign probe_out207[0] = \<const0> ;
assign probe_out208[0] = \<const0> ;
assign probe_out209[0] = \<const0> ;
assign probe_out21[0] = \<const0> ;
assign probe_out210[0] = \<const0> ;
assign probe_out211[0] = \<const0> ;
assign probe_out212[0] = \<const0> ;
assign probe_out213[0] = \<const0> ;
assign probe_out214[0] = \<const0> ;
assign probe_out215[0] = \<const0> ;
assign probe_out216[0] = \<const0> ;
assign probe_out217[0] = \<const0> ;
assign probe_out218[0] = \<const0> ;
assign probe_out219[0] = \<const0> ;
assign probe_out22[0] = \<const0> ;
assign probe_out220[0] = \<const0> ;
assign probe_out221[0] = \<const0> ;
assign probe_out222[0] = \<const0> ;
assign probe_out223[0] = \<const0> ;
assign probe_out224[0] = \<const0> ;
assign probe_out225[0] = \<const0> ;
assign probe_out226[0] = \<const0> ;
assign probe_out227[0] = \<const0> ;
assign probe_out228[0] = \<const0> ;
assign probe_out229[0] = \<const0> ;
assign probe_out23[0] = \<const0> ;
assign probe_out230[0] = \<const0> ;
assign probe_out231[0] = \<const0> ;
assign probe_out232[0] = \<const0> ;
assign probe_out233[0] = \<const0> ;
assign probe_out234[0] = \<const0> ;
assign probe_out235[0] = \<const0> ;
assign probe_out236[0] = \<const0> ;
assign probe_out237[0] = \<const0> ;
assign probe_out238[0] = \<const0> ;
assign probe_out239[0] = \<const0> ;
assign probe_out24[0] = \<const0> ;
assign probe_out240[0] = \<const0> ;
assign probe_out241[0] = \<const0> ;
assign probe_out242[0] = \<const0> ;
assign probe_out243[0] = \<const0> ;
assign probe_out244[0] = \<const0> ;
assign probe_out245[0] = \<const0> ;
assign probe_out246[0] = \<const0> ;
assign probe_out247[0] = \<const0> ;
assign probe_out248[0] = \<const0> ;
assign probe_out249[0] = \<const0> ;
assign probe_out25[0] = \<const0> ;
assign probe_out250[0] = \<const0> ;
assign probe_out251[0] = \<const0> ;
assign probe_out252[0] = \<const0> ;
assign probe_out253[0] = \<const0> ;
assign probe_out254[0] = \<const0> ;
assign probe_out255[0] = \<const0> ;
assign probe_out26[0] = \<const0> ;
assign probe_out27[0] = \<const0> ;
assign probe_out28[0] = \<const0> ;
assign probe_out29[0] = \<const0> ;
assign probe_out3[0] = \<const0> ;
assign probe_out30[0] = \<const0> ;
assign probe_out31[0] = \<const0> ;
assign probe_out32[0] = \<const0> ;
assign probe_out33[0] = \<const0> ;
assign probe_out34[0] = \<const0> ;
assign probe_out35[0] = \<const0> ;
assign probe_out36[0] = \<const0> ;
assign probe_out37[0] = \<const0> ;
assign probe_out38[0] = \<const0> ;
assign probe_out39[0] = \<const0> ;
assign probe_out4[0] = \<const0> ;
assign probe_out40[0] = \<const0> ;
assign probe_out41[0] = \<const0> ;
assign probe_out42[0] = \<const0> ;
assign probe_out43[0] = \<const0> ;
assign probe_out44[0] = \<const0> ;
assign probe_out45[0] = \<const0> ;
assign probe_out46[0] = \<const0> ;
assign probe_out47[0] = \<const0> ;
assign probe_out48[0] = \<const0> ;
assign probe_out49[0] = \<const0> ;
assign probe_out5[0] = \<const0> ;
assign probe_out50[0] = \<const0> ;
assign probe_out51[0] = \<const0> ;
assign probe_out52[0] = \<const0> ;
assign probe_out53[0] = \<const0> ;
assign probe_out54[0] = \<const0> ;
assign probe_out55[0] = \<const0> ;
assign probe_out56[0] = \<const0> ;
assign probe_out57[0] = \<const0> ;
assign probe_out58[0] = \<const0> ;
assign probe_out59[0] = \<const0> ;
assign probe_out6[0] = \<const0> ;
assign probe_out60[0] = \<const0> ;
assign probe_out61[0] = \<const0> ;
assign probe_out62[0] = \<const0> ;
assign probe_out63[0] = \<const0> ;
assign probe_out64[0] = \<const0> ;
assign probe_out65[0] = \<const0> ;
assign probe_out66[0] = \<const0> ;
assign probe_out67[0] = \<const0> ;
assign probe_out68[0] = \<const0> ;
assign probe_out69[0] = \<const0> ;
assign probe_out7[0] = \<const0> ;
assign probe_out70[0] = \<const0> ;
assign probe_out71[0] = \<const0> ;
assign probe_out72[0] = \<const0> ;
assign probe_out73[0] = \<const0> ;
assign probe_out74[0] = \<const0> ;
assign probe_out75[0] = \<const0> ;
assign probe_out76[0] = \<const0> ;
assign probe_out77[0] = \<const0> ;
assign probe_out78[0] = \<const0> ;
assign probe_out79[0] = \<const0> ;
assign probe_out8[0] = \<const0> ;
assign probe_out80[0] = \<const0> ;
assign probe_out81[0] = \<const0> ;
assign probe_out82[0] = \<const0> ;
assign probe_out83[0] = \<const0> ;
assign probe_out84[0] = \<const0> ;
assign probe_out85[0] = \<const0> ;
assign probe_out86[0] = \<const0> ;
assign probe_out87[0] = \<const0> ;
assign probe_out88[0] = \<const0> ;
assign probe_out89[0] = \<const0> ;
assign probe_out9[0] = \<const0> ;
assign probe_out90[0] = \<const0> ;
assign probe_out91[0] = \<const0> ;
assign probe_out92[0] = \<const0> ;
assign probe_out93[0] = \<const0> ;
assign probe_out94[0] = \<const0> ;
assign probe_out95[0] = \<const0> ;
assign probe_out96[0] = \<const0> ;
assign probe_out97[0] = \<const0> ;
assign probe_out98[0] = \<const0> ;
assign probe_out99[0] = \<const0> ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_decoder DECODER_INST
(.\Bus_Data_out_reg[11] (Bus_Data_out),
.E(DECODER_INST_n_4),
.Q({\bus_data_int_reg_n_0_[15] ,\bus_data_int_reg_n_0_[14] ,\bus_data_int_reg_n_0_[13] ,\bus_data_int_reg_n_0_[12] ,\bus_data_int_reg_n_0_[11] ,\bus_data_int_reg_n_0_[10] ,\bus_data_int_reg_n_0_[9] ,\bus_data_int_reg_n_0_[8] ,\bus_data_int_reg_n_0_[7] ,\bus_data_int_reg_n_0_[6] ,\bus_data_int_reg_n_0_[5] ,\bus_data_int_reg_n_0_[4] ,\bus_data_int_reg_n_0_[3] ,\bus_data_int_reg_n_0_[2] ,p_0_in,\bus_data_int_reg_n_0_[0] }),
.out(bus_clk),
.s_daddr_o(bus_addr),
.s_den_o(bus_den),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en_reg[4]_0 (DECODER_INST_n_1),
.\wr_en_reg[4]_1 (DECODER_INST_n_2),
.\wr_en_reg[4]_2 (DECODER_INST_n_3));
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_vio_v3_0_13_probe_in_one PROBE_IN_INST
(.D({probe_in3,probe_in2,probe_in1,probe_in0}),
.E(DECODER_INST_n_4),
.Q(Bus_Data_out),
.clk(clk),
.out(bus_clk),
.s_daddr_o(bus_addr[2:0]),
.s_den_o(bus_den),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.\wr_en[4]_i_3 (DECODER_INST_n_1),
.\wr_en[4]_i_4 (DECODER_INST_n_3),
.\wr_en[4]_i_5 (DECODER_INST_n_2));
(* C_BUILD_REVISION = "0" *)
(* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *)
(* C_CORE_MINOR_VER = "0" *)
(* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *)
(* C_MAJOR_VERSION = "2013" *)
(* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *)
(* C_PIPE_IFACE = "0" *)
(* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *)
(* C_XSDB_SLAVE_TYPE = "33" *)
(* DONT_TOUCH *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs U_XSDB_SLAVE
(.s_daddr_o(bus_addr),
.s_dclk_o(bus_clk),
.s_den_o(bus_den),
.s_di_o(bus_di),
.s_do_i(bus_do),
.s_drdy_i(bus_drdy),
.s_dwe_o(bus_dwe),
.s_rst_o(bus_rst),
.sl_iport_i(sl_iport0),
.sl_oport_o(sl_oport0));
FDRE \bus_data_int_reg[0]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[0]),
.Q(\bus_data_int_reg_n_0_[0] ),
.R(1'b0));
FDRE \bus_data_int_reg[10]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[10]),
.Q(\bus_data_int_reg_n_0_[10] ),
.R(1'b0));
FDRE \bus_data_int_reg[11]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[11]),
.Q(\bus_data_int_reg_n_0_[11] ),
.R(1'b0));
FDRE \bus_data_int_reg[12]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[12]),
.Q(\bus_data_int_reg_n_0_[12] ),
.R(1'b0));
FDRE \bus_data_int_reg[13]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[13]),
.Q(\bus_data_int_reg_n_0_[13] ),
.R(1'b0));
FDRE \bus_data_int_reg[14]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[14]),
.Q(\bus_data_int_reg_n_0_[14] ),
.R(1'b0));
FDRE \bus_data_int_reg[15]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[15]),
.Q(\bus_data_int_reg_n_0_[15] ),
.R(1'b0));
FDRE \bus_data_int_reg[1]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[1]),
.Q(p_0_in),
.R(1'b0));
FDRE \bus_data_int_reg[2]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[2]),
.Q(\bus_data_int_reg_n_0_[2] ),
.R(1'b0));
FDRE \bus_data_int_reg[3]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[3]),
.Q(\bus_data_int_reg_n_0_[3] ),
.R(1'b0));
FDRE \bus_data_int_reg[4]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[4]),
.Q(\bus_data_int_reg_n_0_[4] ),
.R(1'b0));
FDRE \bus_data_int_reg[5]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[5]),
.Q(\bus_data_int_reg_n_0_[5] ),
.R(1'b0));
FDRE \bus_data_int_reg[6]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[6]),
.Q(\bus_data_int_reg_n_0_[6] ),
.R(1'b0));
FDRE \bus_data_int_reg[7]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[7]),
.Q(\bus_data_int_reg_n_0_[7] ),
.R(1'b0));
FDRE \bus_data_int_reg[8]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[8]),
.Q(\bus_data_int_reg_n_0_[8] ),
.R(1'b0));
FDRE \bus_data_int_reg[9]
(.C(bus_clk),
.CE(1'b1),
.D(bus_di[9]),
.Q(\bus_data_int_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* C_BUILD_REVISION = "0" *) (* C_CORE_INFO1 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *) (* C_CORE_INFO2 = "128'b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" *)
(* C_CORE_MAJOR_VER = "2" *) (* C_CORE_MINOR_VER = "0" *) (* C_CORE_TYPE = "2" *)
(* C_CSE_DRV_VER = "1" *) (* C_MAJOR_VERSION = "2013" *) (* C_MINOR_VERSION = "1" *)
(* C_NEXT_SLAVE = "0" *) (* C_PIPE_IFACE = "0" *) (* C_USE_TEST_REG = "1" *)
(* C_XDEVICEFAMILY = "kintex7" *) (* C_XSDB_SLAVE_TYPE = "33" *) (* dont_touch = "true" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_xsdbs_v1_0_2_xsdbs
(s_rst_o,
s_dclk_o,
s_den_o,
s_dwe_o,
s_daddr_o,
s_di_o,
sl_oport_o,
s_do_i,
sl_iport_i,
s_drdy_i);
output s_rst_o;
output s_dclk_o;
output s_den_o;
output s_dwe_o;
output [16:0]s_daddr_o;
output [15:0]s_di_o;
output [16:0]sl_oport_o;
input [15:0]s_do_i;
input [36:0]sl_iport_i;
input s_drdy_i;
wire [8:0]reg_do;
wire \reg_do[10]_i_1_n_0 ;
wire \reg_do[10]_i_2_n_0 ;
wire \reg_do[15]_i_1_n_0 ;
wire \reg_do[1]_i_2_n_0 ;
wire \reg_do[2]_i_1_n_0 ;
wire \reg_do[3]_i_1_n_0 ;
wire \reg_do[4]_i_1_n_0 ;
wire \reg_do[5]_i_2_n_0 ;
wire \reg_do[6]_i_1_n_0 ;
wire \reg_do[7]_i_1_n_0 ;
wire \reg_do[8]_i_2_n_0 ;
wire \reg_do[9]_i_1_n_0 ;
wire \reg_do_reg_n_0_[0] ;
wire \reg_do_reg_n_0_[10] ;
wire \reg_do_reg_n_0_[11] ;
wire \reg_do_reg_n_0_[12] ;
wire \reg_do_reg_n_0_[13] ;
wire \reg_do_reg_n_0_[14] ;
wire \reg_do_reg_n_0_[15] ;
wire \reg_do_reg_n_0_[1] ;
wire \reg_do_reg_n_0_[2] ;
wire \reg_do_reg_n_0_[3] ;
wire \reg_do_reg_n_0_[4] ;
wire \reg_do_reg_n_0_[5] ;
wire \reg_do_reg_n_0_[6] ;
wire \reg_do_reg_n_0_[7] ;
wire \reg_do_reg_n_0_[8] ;
wire \reg_do_reg_n_0_[9] ;
wire reg_drdy;
wire reg_drdy_i_1_n_0;
wire [15:0]reg_test;
wire reg_test0;
wire s_den_o;
wire s_den_o_INST_0_i_1_n_0;
wire [15:0]s_do_i;
wire s_drdy_i;
wire [36:0]sl_iport_i;
wire [16:0]sl_oport_o;
assign s_daddr_o[16:0] = sl_iport_i[20:4];
assign s_dclk_o = sl_iport_i[1];
assign s_di_o[15:0] = sl_iport_i[36:21];
assign s_dwe_o = sl_iport_i[3];
assign s_rst_o = sl_iport_i[0];
LUT6 #(
.INIT(64'hBAAAFFFFAAAAAAAA))
\reg_do[0]_i_1
(.I0(\reg_do[5]_i_2_n_0 ),
.I1(sl_iport_i[4]),
.I2(reg_test[0]),
.I3(sl_iport_i[6]),
.I4(sl_iport_i[5]),
.I5(sl_iport_i[8]),
.O(reg_do[0]));
LUT3 #(
.INIT(8'h40))
\reg_do[10]_i_1
(.I0(sl_iport_i[5]),
.I1(\reg_do[8]_i_2_n_0 ),
.I2(sl_iport_i[4]),
.O(\reg_do[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[10]_i_2
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[10]),
.O(\reg_do[10]_i_2_n_0 ));
LUT3 #(
.INIT(8'hF7))
\reg_do[15]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.O(\reg_do[15]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20220000))
\reg_do[1]_i_1
(.I0(sl_iport_i[5]),
.I1(sl_iport_i[4]),
.I2(reg_test[1]),
.I3(sl_iport_i[6]),
.I4(\reg_do[1]_i_2_n_0 ),
.O(reg_do[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00800000))
\reg_do[1]_i_2
(.I0(sl_iport_i[8]),
.I1(sl_iport_i[10]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[7]),
.I4(sl_iport_i[9]),
.O(\reg_do[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[2]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[2]),
.O(\reg_do[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[3]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[3]),
.O(\reg_do[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[4]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[4]),
.O(\reg_do[4]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00800044))
\reg_do[5]_i_1
(.I0(sl_iport_i[6]),
.I1(sl_iport_i[8]),
.I2(reg_test[5]),
.I3(sl_iport_i[4]),
.I4(sl_iport_i[5]),
.I5(\reg_do[5]_i_2_n_0 ),
.O(reg_do[5]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hBFFFFFFC))
\reg_do[5]_i_2
(.I0(sl_iport_i[7]),
.I1(sl_iport_i[8]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[9]),
.O(\reg_do[5]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[6]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[6]),
.O(\reg_do[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h0800))
\reg_do[7]_i_1
(.I0(\reg_do[8]_i_2_n_0 ),
.I1(sl_iport_i[5]),
.I2(sl_iport_i[4]),
.I3(reg_test[7]),
.O(\reg_do[7]_i_1_n_0 ));
LUT4 #(
.INIT(16'h2F00))
\reg_do[8]_i_1
(.I0(reg_test[8]),
.I1(sl_iport_i[4]),
.I2(sl_iport_i[5]),
.I3(\reg_do[8]_i_2_n_0 ),
.O(reg_do[8]));
LUT6 #(
.INIT(64'h2000000000000000))
\reg_do[8]_i_2
(.I0(sl_iport_i[9]),
.I1(sl_iport_i[7]),
.I2(sl_iport_i[11]),
.I3(sl_iport_i[10]),
.I4(sl_iport_i[8]),
.I5(sl_iport_i[6]),
.O(\reg_do[8]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0C008000))
\reg_do[9]_i_1
(.I0(reg_test[9]),
.I1(\reg_do[1]_i_2_n_0 ),
.I2(sl_iport_i[6]),
.I3(sl_iport_i[5]),
.I4(sl_iport_i[4]),
.O(\reg_do[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[0]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[0]),
.Q(\reg_do_reg_n_0_[0] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[10]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[10]_i_2_n_0 ),
.Q(\reg_do_reg_n_0_[10] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[11]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[11]),
.Q(\reg_do_reg_n_0_[11] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[12]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[12]),
.Q(\reg_do_reg_n_0_[12] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[13]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[13]),
.Q(\reg_do_reg_n_0_[13] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[14]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[14]),
.Q(\reg_do_reg_n_0_[14] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[15]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_test[15]),
.Q(\reg_do_reg_n_0_[15] ),
.R(\reg_do[15]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[1]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[1]),
.Q(\reg_do_reg_n_0_[1] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[2]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[2]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[2] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[3]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[3]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[3] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[4]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[4]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[4] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[5]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[5]),
.Q(\reg_do_reg_n_0_[5] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[6]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[6]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[6] ),
.S(\reg_do[10]_i_1_n_0 ));
FDSE #(
.INIT(1'b0))
\reg_do_reg[7]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[7]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[7] ),
.S(\reg_do[10]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\reg_do_reg[8]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_do[8]),
.Q(\reg_do_reg_n_0_[8] ),
.R(1'b0));
FDSE #(
.INIT(1'b0))
\reg_do_reg[9]
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(\reg_do[9]_i_1_n_0 ),
.Q(\reg_do_reg_n_0_[9] ),
.S(\reg_do[10]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000000080000000))
reg_drdy_i_1
(.I0(sl_iport_i[2]),
.I1(s_den_o_INST_0_i_1_n_0),
.I2(sl_iport_i[12]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[14]),
.I5(sl_iport_i[0]),
.O(reg_drdy_i_1_n_0));
FDRE #(
.INIT(1'b0))
reg_drdy_reg
(.C(sl_iport_i[1]),
.CE(1'b1),
.D(reg_drdy_i_1_n_0),
.Q(reg_drdy),
.R(1'b0));
LUT6 #(
.INIT(64'h8000000000000000))
\reg_test[15]_i_1
(.I0(sl_iport_i[3]),
.I1(sl_iport_i[2]),
.I2(sl_iport_i[14]),
.I3(sl_iport_i[13]),
.I4(sl_iport_i[12]),
.I5(s_den_o_INST_0_i_1_n_0),
.O(reg_test0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[0]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[21]),
.Q(reg_test[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[10]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[31]),
.Q(reg_test[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[11]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[32]),
.Q(reg_test[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[12]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[33]),
.Q(reg_test[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[13]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[34]),
.Q(reg_test[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[14]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[35]),
.Q(reg_test[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[15]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[36]),
.Q(reg_test[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[1]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[22]),
.Q(reg_test[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[2]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[23]),
.Q(reg_test[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[3]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[24]),
.Q(reg_test[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[4]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[25]),
.Q(reg_test[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[5]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[26]),
.Q(reg_test[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[6]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[27]),
.Q(reg_test[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[7]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[28]),
.Q(reg_test[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[8]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[29]),
.Q(reg_test[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\reg_test_reg[9]
(.C(sl_iport_i[1]),
.CE(reg_test0),
.D(sl_iport_i[30]),
.Q(reg_test[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h2AAAAAAA))
s_den_o_INST_0
(.I0(sl_iport_i[2]),
.I1(sl_iport_i[14]),
.I2(sl_iport_i[13]),
.I3(sl_iport_i[12]),
.I4(s_den_o_INST_0_i_1_n_0),
.O(s_den_o));
LUT6 #(
.INIT(64'h8000000000000000))
s_den_o_INST_0_i_1
(.I0(sl_iport_i[15]),
.I1(sl_iport_i[16]),
.I2(sl_iport_i[17]),
.I3(sl_iport_i[18]),
.I4(sl_iport_i[20]),
.I5(sl_iport_i[19]),
.O(s_den_o_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'hE))
\sl_oport_o[0]_INST_0
(.I0(s_drdy_i),
.I1(reg_drdy),
.O(sl_oport_o[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[10]_INST_0
(.I0(\reg_do_reg_n_0_[9] ),
.I1(s_do_i[9]),
.I2(reg_drdy),
.O(sl_oport_o[10]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[11]_INST_0
(.I0(\reg_do_reg_n_0_[10] ),
.I1(s_do_i[10]),
.I2(reg_drdy),
.O(sl_oport_o[11]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[12]_INST_0
(.I0(\reg_do_reg_n_0_[11] ),
.I1(s_do_i[11]),
.I2(reg_drdy),
.O(sl_oport_o[12]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[13]_INST_0
(.I0(\reg_do_reg_n_0_[12] ),
.I1(s_do_i[12]),
.I2(reg_drdy),
.O(sl_oport_o[13]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[14]_INST_0
(.I0(\reg_do_reg_n_0_[13] ),
.I1(s_do_i[13]),
.I2(reg_drdy),
.O(sl_oport_o[14]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[15]_INST_0
(.I0(\reg_do_reg_n_0_[14] ),
.I1(s_do_i[14]),
.I2(reg_drdy),
.O(sl_oport_o[15]));
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[16]_INST_0
(.I0(\reg_do_reg_n_0_[15] ),
.I1(s_do_i[15]),
.I2(reg_drdy),
.O(sl_oport_o[16]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[1]_INST_0
(.I0(\reg_do_reg_n_0_[0] ),
.I1(s_do_i[0]),
.I2(reg_drdy),
.O(sl_oport_o[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[2]_INST_0
(.I0(\reg_do_reg_n_0_[1] ),
.I1(s_do_i[1]),
.I2(reg_drdy),
.O(sl_oport_o[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[3]_INST_0
(.I0(\reg_do_reg_n_0_[2] ),
.I1(s_do_i[2]),
.I2(reg_drdy),
.O(sl_oport_o[3]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[4]_INST_0
(.I0(\reg_do_reg_n_0_[3] ),
.I1(s_do_i[3]),
.I2(reg_drdy),
.O(sl_oport_o[4]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[5]_INST_0
(.I0(\reg_do_reg_n_0_[4] ),
.I1(s_do_i[4]),
.I2(reg_drdy),
.O(sl_oport_o[5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[6]_INST_0
(.I0(\reg_do_reg_n_0_[5] ),
.I1(s_do_i[5]),
.I2(reg_drdy),
.O(sl_oport_o[6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[7]_INST_0
(.I0(\reg_do_reg_n_0_[6] ),
.I1(s_do_i[6]),
.I2(reg_drdy),
.O(sl_oport_o[7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[8]_INST_0
(.I0(\reg_do_reg_n_0_[7] ),
.I1(s_do_i[7]),
.I2(reg_drdy),
.O(sl_oport_o[8]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\sl_oport_o[9]_INST_0
(.I0(\reg_do_reg_n_0_[8] ),
.I1(s_do_i[8]),
.I2(reg_drdy),
.O(sl_oport_o[9]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module j1soc#(
//parameter bootram_file = "../../firmware/hello_world/j1.mem" // For synthesis
parameter bootram_file = "../firmware/Hello_World/j1.mem" // For simulation
)(
uart_tx, ledout,
sys_clk_i, sys_rst_i, mosi ,miso, sck, ss, SDA, SCL, pwm, adelante, atras, rs, e , data, tx_channel, rx_channel, rx_busy, tx_busy
);
// entradas y salidas fisicas
input sys_clk_i, sys_rst_i;
output uart_tx;
output ledout;
//spi
input mosi;
output miso;
output sck;
output ss;
// I2C
inout SDA;
output SCL;
//pwm
output [2:0] pwm ;
// Direccion
output [1:0] adelante ;
output [1:0] atras ;
//LCD
output rs;
output e;
output [7:0] data;
//posicion
output SCL;
inout SDA;
wire SDA_oen, SDA_out ;
// Uart 2
input rx_channel; // Canal de lectura
output tx_channel; // Canal de escritura (tranmision)
output tx_busy; // Canal de transmision esta ocupado
output rx_busy ; // Canal de lectura esta ocupado
assign SDA = (SDA_oen) ? SDA_out : 1'bz;
assign SDA_in = SDA;
//------------------------------------ regs and wires-------------------------------
wire j1_io_rd;//********************** J1
wire j1_io_wr;//********************** J1
wire [15:0] j1_io_addr;//************* J1
reg [15:0] j1_io_din;//************** J1
wire [15:0] j1_io_dout;//************* J1
reg [1:14]cs; // CHIP-SELECT //cantidad de modulos
wire [15:0] mult_dout;
wire [15:0] div_dout;
wire uart_dout; // misma señal que uart_busy from uart.v
wire [15:0] dp_ram_dout;
wire [15:0] spi_master_dout;
wire [15:0] crc_7_dout;
wire [15:0] crc_16_dout;
wire [15:0] pwm_dout;
wire [15:0] lcd_dout;
wire [15:0] posicion_dout;
wire [15:0] timmer_dout;
wire [15:0] distancia_dout;
wire [15:0] direccion;
wire [15:0] uart_2;
//------------------------------------ regs and wires-------------------------------
j1 #(bootram_file) cpu0(sys_clk_i, sys_rst_i, j1_io_din, j1_io_rd, j1_io_wr, j1_io_addr, j1_io_dout);
peripheral_mult per_m ( .clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[1]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(mult_dout) );
peripheral_div per_d (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[2]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(div_dout));
peripheral_uart per_u (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[3]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(uart_dout), .uart_tx(uart_tx), .ledout(ledout));
dpRAM_interface dpRm(.clk(sys_clk_i), .d_in(j1_io_dout), .cs(cs[4]), .addr(j1_io_addr[7:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(dp_ram_dout));
peripheral_spi_master per_spi (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[5]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(spi_master_dout) , .mosi(mosi) ,.miso(miso), .sck(sck), .ss(ss) ); //se instancia el peripheral de spi
peripheral_crc_7 per_crc_7 (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[6]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(crc_7_dout) ); //se instancia el peripheral de crc_7
peripheral_crc_16 per_crc_16 (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[7]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(crc_16_dout) ); //se instancia el peripheral de crc_16
peripheral_pwm per_pwm (.clk(sys_clk_i),.rst(sys_rst_i),.d_in(j1_io_dout),.d_out(pwm_out),.cs(cs[8]),.addr(j1_io_addr[3:0]),.rd(j1_io_rd),.wr(j1_io_wr),.pwm(pwm));
LCD_Peripheral per_lcd (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[9]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(lcd_out), .rs(lcd_rs), .e(lcd_e), .data(lcd_data), .int_cnt(int_cnt), .en_cnt(en_cnt), .limit_cnt(limit_cnt) );
position_peripheral (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[10]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(posicion_out), .clk_freq(clk_freq), .counter_rst(counter_rst), .counter_en (counter_en), . int_en(int_en), .int_limit(int_limit), .SCL(SCL), .SDA_out(SDA_out), .SDA_oen(SDA_oen), .counter_count(counter_count), .clk_frame(clk_frame), .int_o(int_o), .SDA_in(SDA_in));
peripheral_timmer (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[11]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr),.d_out( timmer_out ));
peripheral_distancia (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_dout), .cs(cs[12]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr),.d_out( distancia_out ));
peripheral_direccion per_dir (.clk(sys_clk_i),.rst(sys_rst_i),.d_in(j1_io_dout),.d_out(pwm_out),.cs(cs[13]),.addr(j1_io_addr[3:0]),.rd(j1_io_rd),.wr(j1_io_wr),.adelante(adelante),.atras(atras));
peripheral_uart_2 per_uart (.clk(sys_clk_i), .rst(sys_rst_i), .d_in(j1_io_din), .cs(cs[14]), .addr(j1_io_addr[3:0]), .rd(j1_io_rd), .wr(j1_io_wr), .d_out(d_out), .rx_channel(rx_channel), .tx_channel(tx_channel), .tx_busy(tx_busy), .rx_busy(rx_busy) ) ;
// ============== Chip_Select (Addres decoder) ======================== // se hace con los 8 bits mas significativos de j1_io_addr
always @*
begin
case (j1_io_addr[15:8]) // direcciones - chip_select
8'h67: cs= 14'b10000000000000; //mult
8'h68: cs= 14'b01000000000000; //div
8'h69: cs= 14'b00100000000000; //uart
8'h70: cs= 14'b00010000000000; //dp_ram
8'h72: cs= 14'b00001000000000; //spi
8'h74: cs= 14'b00000100000000; //crc_7
8'h76: cs= 14'b00000010000000; //crc_16
8'h60: cs= 14'b00000001000000; //pwm
8'h61: cs= 14'b00000000100000; //lcd
8'h62: cs= 14'b00000000010000; //posicion
8'h63: cs= 14'b00000000001000; //timmer
8'h64: cs= 14'b00000000000100; //distancia
8'h65: cs= 14'b00000000000010; //direccion
8'h65: cs= 14'b00000000000001; //Segunda Uart
default: cs= 14'b0000000000000;
endcase
end
// ============== Chip_Select (Addres decoder) ======================== //
// ============== MUX ======================== // se encarga de lecturas del J1
always @*
begin
case (cs)
14'b10000000000000: j1_io_din = mult_dout;
14'b01000000000000: j1_io_din = div_dout;
14'b00100000000000: j1_io_din = uart_dout;
14'b00010000000000: j1_io_din = dp_ram_dout;
14'b00001000000000: j1_io_din = spi_master_dout;
14'b00000100000000: j1_io_din = crc_7_dout;
14'b00000010000000: j1_io_din = crc_16_dout;
14'b00000001000000: j1_io_din = pwm_dout;
14'b00000000100000: j1_io_din = lcd_dout;
14'b00000000010000: j1_io_din = posicion_dout;
14'b00000000001000: j1_io_din = timmer_dout;
14'b00000000000100: j1_io_din = distancia_dout;
14'b00000000000010: j1_io_din = direccion;
14'b00000000000001: j1_io_din = uart_2;
default: j1_io_din = 16'h0666;
endcase
end
// ============== MUX ======================== //
endmodule // top
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Ramdon_gen.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:19 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:45 Administrator
// no message
//
module Ramdon_gen(
Reset ,
Clk ,
Init ,
RetryCnt ,
Random_time_meet
);
input Reset ;
input Clk ;
input Init ;
input [3:0] RetryCnt ;
output Random_time_meet;
//******************************************************************************
//internal signals
//******************************************************************************
reg [9:0] Random_sequence ;
reg [9:0] Ramdom ;
reg [9:0] Ramdom_counter ;
reg [7:0] Slot_time_counter; //256*2=512bit=1 slot time
reg Random_time_meet;
//******************************************************************************
always @ (posedge Clk or posedge Reset)
if (Reset)
Random_sequence <=0;
else
Random_sequence <={Random_sequence[8:0],~(Random_sequence[2]^Random_sequence[9])};
always @ (RetryCnt or Random_sequence)
case (RetryCnt)
4'h0 : Ramdom={9'b0,Random_sequence[0]};
4'h1 : Ramdom={8'b0,Random_sequence[1:0]};
4'h2 : Ramdom={7'b0,Random_sequence[2:0]};
4'h3 : Ramdom={6'b0,Random_sequence[3:0]};
4'h4 : Ramdom={5'b0,Random_sequence[4:0]};
4'h5 : Ramdom={4'b0,Random_sequence[5:0]};
4'h6 : Ramdom={3'b0,Random_sequence[6:0]};
4'h7 : Ramdom={2'b0,Random_sequence[7:0]};
4'h8 : Ramdom={1'b0,Random_sequence[8:0]};
4'h9 : Ramdom={ Random_sequence[9:0]};
default : Ramdom={ Random_sequence[9:0]};
endcase
always @ (posedge Clk or posedge Reset)
if (Reset)
Slot_time_counter <=0;
else if(Init)
Slot_time_counter <=0;
else if(!Random_time_meet)
Slot_time_counter <=Slot_time_counter+1;
always @ (posedge Clk or posedge Reset)
if (Reset)
Ramdom_counter <=0;
else if (Init)
Ramdom_counter <=Ramdom;
else if (Ramdom_counter!=0&&Slot_time_counter==255)
Ramdom_counter <=Ramdom_counter -1 ;
always @ (posedge Clk or posedge Reset)
if (Reset)
Random_time_meet <=1;
else if (Init)
Random_time_meet <=0;
else if (Ramdom_counter==0)
Random_time_meet <=1;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Wed Oct 18 15:15:21 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_processing_system7_0_0_stub.v
// Design : ip_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID,
M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID,
M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_CLK1, FCLK_RESET0_N, MIO,
DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB,
DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK,
PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_CLK1,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/******************************************************************************/
/* Test Bench for FPGA Sort on VC707 Ryohei Kobayashi */
/* 2016-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
`include "user_logic.v"
`include "sorter.v"
/******************************************************************************/
module tb_USER_LOGIC();
reg CLK, RST;
wire chnl_rx_clk;
wire chnl_rx;
wire chnl_rx_ack;
wire chnl_rx_last;
wire [31:0] chnl_rx_len;
wire [30:0] chnl_rx_off;
wire [128-1:0] chnl_rx_data;
wire chnl_rx_data_valid;
wire chnl_rx_data_ren;
wire chnl_tx_clk;
wire chnl_tx;
wire chnl_tx_ack;
wire chnl_tx_last;
wire [31:0] chnl_tx_len;
wire [30:0] chnl_tx_off;
wire [128-1:0] chnl_tx_data;
wire chnl_tx_data_vaild;
wire chnl_tx_data_ren = 1;
wire d_busy;
wire d_w;
wire [`DRAMW-1:0] d_din;
wire [`DRAMW-1:0] d_dout;
wire d_douten;
wire [1:0] d_req; // DRAM access request (read/write)
wire [31:0] d_initadr; // dram initial address for the access
wire [31:0] d_blocks; // the number of blocks per one access(read/write)
reg sortdone;
initial begin CLK=0; forever #50 CLK=~CLK; end
initial begin RST=1; #400 RST=0; end
reg [31:0] cnt;
always @(posedge CLK) cnt <= (RST) ? 0 : cnt + 1;
reg [31:0] cnt0, cnt1, cnt2, cnt3, cnt4, cnt5, cnt6, cnt7, cnt8, cnt9;
always @(posedge CLK) cnt0 <= (RST) ? 0 : (u.core.phase==0) ? cnt0 + 1 : cnt0;
always @(posedge CLK) cnt1 <= (RST) ? 0 : (u.core.phase==1) ? cnt1 + 1 : cnt1;
always @(posedge CLK) cnt2 <= (RST) ? 0 : (u.core.phase==2) ? cnt2 + 1 : cnt2;
always @(posedge CLK) cnt3 <= (RST) ? 0 : (u.core.phase==3) ? cnt3 + 1 : cnt3;
always @(posedge CLK) cnt4 <= (RST) ? 0 : (u.core.phase==4) ? cnt4 + 1 : cnt4;
always @(posedge CLK) cnt5 <= (RST) ? 0 : (u.core.phase==5) ? cnt5 + 1 : cnt5;
always @(posedge CLK) cnt6 <= (RST) ? 0 : (u.core.phase==6) ? cnt6 + 1 : cnt6;
always @(posedge CLK) cnt7 <= (RST) ? 0 : (u.core.phase==7) ? cnt7 + 1 : cnt7;
always @(posedge CLK) cnt8 <= (RST) ? 0 : (u.core.phase==8) ? cnt8 + 1 : cnt8;
always @(posedge CLK) cnt9 <= (RST) ? 0 : (u.core.phase==9) ? cnt9 + 1 : cnt9;
reg [31:0] rslt_cnt;
always @(posedge CLK) begin
if (RST) begin
rslt_cnt <= 0;
end else begin
if (chnl_tx_data_vaild) rslt_cnt <= rslt_cnt + 4;
end
end
always @(posedge CLK) begin
if (RST) sortdone <= 0;
else if (rslt_cnt == `SORT_ELM) sortdone <= 1;
end
// Debug Info
always @(posedge CLK) begin
if (!RST) begin
$write("%d|%d|P%d|%d%d%d|%d", cnt[19:0], u.core.elem, u.core.phase[2:0], u.core.iter_done, u.core.pchange, u.core.irst, u.core.ecnt);
$write("|");
if (d_douten) $write("%08x %08x ", d_dout[63:32], d_dout[31:0]); else $write(" ");
// $write("%d %d %x ", u.rState, u.rx_wait, u.core.req_pzero);
// if (u.idata_valid) $write("%08x %08x ", u.idata[63:32], u.idata[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_t) $write("%08x %08x ", u.core.dout_t[63:32], u.core.dout_t[31:0]); else $write(" ");
// $write("|");
// if (u.core.doen_tc) $write("%08x %08x ", u.core.dout_tc[63:32], u.core.dout_tc[31:0]); else $write(" ");
$write("|");
$write("[%d](%d)", u.core.req, u.core.state);
$write("| %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d %d|",
u.core.im00.imf.cnt, u.core.im01.imf.cnt, u.core.im02.imf.cnt, u.core.im03.imf.cnt,
u.core.im04.imf.cnt, u.core.im05.imf.cnt, u.core.im06.imf.cnt, u.core.im07.imf.cnt,
u.core.im08.imf.cnt, u.core.im09.imf.cnt, u.core.im10.imf.cnt, u.core.im11.imf.cnt,
u.core.im12.imf.cnt, u.core.im13.imf.cnt, u.core.im14.imf.cnt, u.core.im15.imf.cnt);
// $write("| %d %d %d %d %d %d %d %d|",
// u.core.im00.im_deq, u.core.im01.im_deq, u.core.im02.im_deq, u.core.im03.im_deq,
// u.core.im04.im_deq, u.core.im05.im_deq, u.core.im06.im_deq, u.core.im07.im_deq,
// u.core.im08.im_deq, u.core.im09.im_deq, u.core.im10.im_deq, u.core.im11.im_deq,
// u.core.im12.im_deq, u.core.im13.im_deq, u.core.im14.im_deq, u.core.im15.im_deq);
$write(" ");
if (u.core.F01_deq) $write("%08x %08x %08x %08x ", u.core.F01_dot[127:96], u.core.F01_dot[95:64], u.core.F01_dot[63:32], u.core.F01_dot[31:0]); else $write(" ");
$write("| ");
$write("%d", u.core.dcnt);
if (d.app_wdf_wren) $write(" |M%d %d ", d_din[63:32], d_din[31:0]);
$write("\n");
$fflush();
end
end
// checking the result
generate
if (`INITTYPE=="sorted" || `INITTYPE=="reverse") begin
reg [`MERGW-1:0] check_cnt;
always @(posedge CLK) begin
if (RST) begin
check_cnt[31 : 0] <= 1;
check_cnt[63 :32] <= 2;
check_cnt[95 :64] <= 3;
check_cnt[127:96] <= 4;
end else begin
if (chnl_tx_data_vaild) begin
if (check_cnt != chnl_tx_data) begin
$write("Error in sorter.v: %d %d\n", chnl_tx_data, check_cnt); // for simulation
$finish(); // for simulation
end
check_cnt[31 : 0] <= check_cnt[31 : 0] + 4;
check_cnt[63 :32] <= check_cnt[63 :32] + 4;
check_cnt[95 :64] <= check_cnt[95 :64] + 4;
check_cnt[127:96] <= check_cnt[127:96] + 4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
integer fp;
initial begin fp = $fopen("log.txt", "w"); end
always @(posedge CLK) begin
if (chnl_tx_data_vaild) begin
$fwrite(fp, "%08x\n", chnl_tx_data[31:0]);
$fwrite(fp, "%08x\n", chnl_tx_data[63:32]);
$fwrite(fp, "%08x\n", chnl_tx_data[95:64]);
$fwrite(fp, "%08x\n", chnl_tx_data[127:96]);
$fflush();
end
if (sortdone) $fclose(fp);
end
end else begin
always @(posedge CLK) begin
$write("Error! INITTYPE is wrong.\n");
$write("Please make sure src/define.vh\n");
$finish();
end
end
endgenerate
// Show the elapsed cycles
always @(posedge CLK) begin
if(sortdone) begin : simulation_finish
$write("\nIt takes %d cycles\n", cnt);
$write("phase0: %d cycles\n", cnt0);
$write("phase1: %d cycles\n", cnt1);
$write("phase2: %d cycles\n", cnt2);
$write("phase3: %d cycles\n", cnt3);
$write("phase4: %d cycles\n", cnt4);
$write("phase5: %d cycles\n", cnt5);
$write("phase6: %d cycles\n", cnt6);
$write("phase7: %d cycles\n", cnt7);
$write("phase8: %d cycles\n", cnt8);
$write("phase9: %d cycles\n", cnt9);
$write("Sorting finished!\n");
$finish();
end
end
// Stub modules
/**********************************************************************************************/
Host_to_FPGA h2f(CLK, RST, chnl_rx_data_ren, chnl_rx, chnl_rx_data, chnl_rx_data_valid, chnl_rx_len);
DRAM d(CLK, RST, d_req, d_initadr, d_blocks, d_din, d_w, d_dout, d_douten, d_busy);
/***** Core Module Instantiation *****/
/**********************************************************************************************/
USER_LOGIC u(CLK,
RST,
chnl_rx_clk,
chnl_rx,
chnl_rx_ack,
chnl_rx_last,
chnl_rx_len,
chnl_rx_off,
chnl_rx_data,
chnl_rx_data_valid,
chnl_rx_data_ren,
chnl_tx_clk,
chnl_tx,
chnl_tx_ack,
chnl_tx_last,
chnl_tx_len,
chnl_tx_off,
chnl_tx_data,
chnl_tx_data_vaild,
chnl_tx_data_ren,
d_busy, // DRAM busy
d_din, // DRAM data in
d_w, // DRAM write flag
d_dout, // DRAM data out
d_douten, // DRAM data out enable
d_req, // DRAM REQ access request (read/write)
d_initadr, // DRAM REQ initial address for the access
d_blocks // DRAM REQ the number of blocks per one access
);
endmodule
/**************************************************************************************************/
/***** Xorshift *****/
/**************************************************************************************************/
module XORSHIFT #(parameter WIDTH = 32,
parameter SEED = 1)
(input wire CLK,
input wire RST,
input wire EN,
output wire [WIDTH-1:0] RAND_VAL);
reg [WIDTH-1:0] x;
reg [WIDTH-1:0] y;
reg [WIDTH-1:0] z;
reg [WIDTH-1:0] w;
wire [WIDTH-1:0] t = x^(x<<11);
// Mask MSB for not generating the maximum value
assign RAND_VAL = {1'b0, w[WIDTH-2:0]};
reg ocen;
always @(posedge CLK) ocen <= RST;
always @(posedge CLK) begin
if (RST) begin
x <= 123456789;
y <= 362436069;
z <= 521288629;
w <= 88675123 ^ SEED;
end else begin
if (EN || ocen) begin
x <= y;
y <= z;
z <= w;
w <= (w^(w>>19))^(t^(t>>8));
end
end
end
endmodule
/**************************************************************************************************/
module Host_to_FPGA(input wire CLK,
input wire RST,
input wire ren,
output reg chnl_rx,
output wire [`MERGW-1:0] dot,
output wire doten,
output wire [31:0] length);
reg rst_buf; always @(posedge CLK) rst_buf <= RST;
wire enq;
wire deq;
wire [`MERGW-1:0] din;
wire emp;
wire ful;
wire [4:0] cnt;
reg [`SORTW-1:0] i_d,i_c,i_b,i_a;
reg onetime;
reg [31:0] enqcnt;
reg enqstop;
wire [`SORTW-1:0] r15,r14,r13,r12,r11,r10,r09,r08,r07,r06,r05,r04,r03,r02,r01,r00;
reg [1:0] selector;
wire [`MERGW-1:0] din_xorshift = (selector == 0) ? {r03,r02,r01,r00} :
(selector == 1) ? {r07,r06,r05,r04} :
(selector == 2) ? {r11,r10,r09,r08} :
(selector == 3) ? {r15,r14,r13,r12} : 0;
SRL_FIFO #(4, `MERGW) fifo(CLK, rst_buf, enq, deq, din, dot, emp, ful, cnt);
assign enq = (!enqstop && !ful);
assign deq = (ren && !emp);
assign din = (`INITTYPE=="xorshift") ? din_xorshift : {i_d,i_c,i_b,i_a};
assign doten = deq;
assign length = `SORT_ELM;
always @(posedge CLK) begin
if (rst_buf) begin
chnl_rx <= 0;
onetime <= 1;
end else begin
chnl_rx <= onetime;
onetime <= 0;
end
end
always @(posedge CLK) begin
if (rst_buf) enqcnt <= 0;
else if (enq) enqcnt <= enqcnt + 4;
end
always @(posedge CLK) begin
if (rst_buf) enqstop <= 0;
else if (enq && (enqcnt == `SORT_ELM-4)) enqstop <= 1;
end
always @(posedge CLK) begin
if (rst_buf) selector <= 0;
else if (enq) selector <= selector + 1;
end
generate
if (`INITTYPE=="sorted") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= 1;
i_b <= 2;
i_c <= 3;
i_d <= 4;
end else begin
if (enq) begin
i_a <= i_a+4;
i_b <= i_b+4;
i_c <= i_c+4;
i_d <= i_d+4;
end
end
end
end else if (`INITTYPE=="reverse") begin
always @(posedge CLK) begin
if (rst_buf) begin
i_a <= `SORT_ELM;
i_b <= `SORT_ELM-1;
i_c <= `SORT_ELM-2;
i_d <= `SORT_ELM-3;
end else begin
if (enq) begin
i_a <= i_a-4;
i_b <= i_b-4;
i_c <= i_c-4;
i_d <= i_d-4;
end
end
end
end else if (`INITTYPE=="xorshift") begin
XORSHIFT #(`SORTW, 32'h00000001) xorshift00(CLK, RST, (enq && selector == 0), r00);
XORSHIFT #(`SORTW, 32'h00000002) xorshift01(CLK, RST, (enq && selector == 0), r01);
XORSHIFT #(`SORTW, 32'h00000004) xorshift02(CLK, RST, (enq && selector == 0), r02);
XORSHIFT #(`SORTW, 32'h00000008) xorshift03(CLK, RST, (enq && selector == 0), r03);
XORSHIFT #(`SORTW, 32'h00000010) xorshift04(CLK, RST, (enq && selector == 1), r04);
XORSHIFT #(`SORTW, 32'h00000020) xorshift05(CLK, RST, (enq && selector == 1), r05);
XORSHIFT #(`SORTW, 32'h00000040) xorshift06(CLK, RST, (enq && selector == 1), r06);
XORSHIFT #(`SORTW, 32'h00000080) xorshift07(CLK, RST, (enq && selector == 1), r07);
XORSHIFT #(`SORTW, 32'h00000100) xorshift08(CLK, RST, (enq && selector == 2), r08);
XORSHIFT #(`SORTW, 32'h00000200) xorshift09(CLK, RST, (enq && selector == 2), r09);
XORSHIFT #(`SORTW, 32'h00000400) xorshift10(CLK, RST, (enq && selector == 2), r10);
XORSHIFT #(`SORTW, 32'h00000800) xorshift11(CLK, RST, (enq && selector == 2), r11);
XORSHIFT #(`SORTW, 32'h00001000) xorshift12(CLK, RST, (enq && selector == 3), r12);
XORSHIFT #(`SORTW, 32'h00002000) xorshift13(CLK, RST, (enq && selector == 3), r13);
XORSHIFT #(`SORTW, 32'h00004000) xorshift14(CLK, RST, (enq && selector == 3), r14);
XORSHIFT #(`SORTW, 32'h00008000) xorshift15(CLK, RST, (enq && selector == 3), r15);
end
endgenerate
endmodule
/**************************************************************************************************/
module DRAM(input wire CLK, //
input wire RST, //
input wire [1:0] D_REQ, // dram request, load or store
input wire [31:0] D_INITADR, // dram request, initial address
input wire [31:0] D_ELEM, // dram request, the number of elements
input wire [`DRAMW-1:0] D_DIN, //
output wire D_W, //
output reg [`DRAMW-1:0] D_DOUT, //
output reg D_DOUTEN, //
output wire D_BUSY); //
/******* DRAM ******************************************************/
localparam M_REQ = 0;
localparam M_WRITE = 1;
localparam M_READ = 2;
///////////////////////////////////////////////////////////////////////////////////
reg [`DDR3_CMD] app_cmd;
reg app_en;
wire [`DRAMW-1:0] app_wdf_data;
reg app_wdf_wren;
wire app_wdf_end = app_wdf_wren;
// outputs of u_dram
wire [`DRAMW-1:0] app_rd_data;
wire app_rd_data_end;
wire app_rd_data_valid=1; // in simulation, always ready !!
wire app_rdy = 1; // in simulation, always ready !!
wire app_wdf_rdy = 1; // in simulation, always ready !!
wire ui_clk = CLK;
reg [1:0] mode;
reg [`DRAMW-1:0] app_wdf_data_buf;
reg [31:0] caddr; // check address
reg [31:0] remain, remain2; //
reg [7:0] req_state; //
///////////////////////////////////////////////////////////////////////////////////
reg [`DRAMW-1:0] mem [`DRAM_SIZE-1:0];
reg [31:0] app_addr;
reg [31:0] dram_addr;
always @(posedge CLK) dram_addr <= app_addr;
always @(posedge CLK) begin /***** DRAM WRITE *****/
if (RST) begin end
else if(app_wdf_wren) mem[dram_addr[27:3]] <= app_wdf_data;
end
assign app_rd_data = mem[app_addr[27:3]];
assign app_wdf_data = D_DIN;
assign D_BUSY = (mode!=M_REQ); // DRAM busy
assign D_W = (mode==M_WRITE && app_rdy && app_wdf_rdy); // store one element
///// READ & WRITE PORT CONTROL (begin) ////////////////////////////////////////////
always @(posedge ui_clk) begin
if (RST) begin
mode <= M_REQ;
{app_addr, app_cmd, app_en, app_wdf_wren} <= 0;
{D_DOUT, D_DOUTEN} <= 0;
{caddr, remain, remain2, req_state} <= 0;
end else begin
case (mode)
///////////////////////////////////////////////////////////////// request
M_REQ: begin
D_DOUTEN <= 0;
if(D_REQ==`DRAM_REQ_WRITE) begin ///// WRITE or STORE request
app_cmd <= `DRAM_CMD_WRITE;
mode <= M_WRITE;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // the number of blocks to be written
end
else if(D_REQ==`DRAM_REQ_READ) begin ///// READ or LOAD request
app_cmd <= `DRAM_CMD_READ;
mode <= M_READ;
app_wdf_wren <= 0;
app_en <= 1;
app_addr <= D_INITADR; // param, initial address
remain <= D_ELEM; // param, the number of blocks to be read
remain2 <= D_ELEM; // param, the number of blocks to be read
end
else begin
app_wdf_wren <= 0;
app_en <= 0;
end
end
//////////////////////////////////////////////////////////////////// read
M_READ: begin
if (app_rdy) begin // read request is accepted.
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain2 <= remain2 - 1;
if(remain2==1) app_en <= 0;
end
D_DOUTEN <= app_rd_data_valid; // dram data_out enable
if (app_rd_data_valid) begin
D_DOUT <= app_rd_data;
caddr <= (caddr==`MEM_LAST_ADDR) ? 0 : caddr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
end
end
end
/////////////////////////////////////////////////////////////////// write
M_WRITE: begin
if (app_rdy && app_wdf_rdy) begin
app_wdf_wren <= 1;
app_addr <= (app_addr==`MEM_LAST_ADDR) ? 0 : app_addr + 8;
remain <= remain - 1;
if(remain==1) begin
mode <= M_REQ;
app_en <= 0;
end
end
else app_wdf_wren <= 0;
end
endcase
end
end
///// READ & WRITE PORT CONTROL (end) //////////////////////////////////////
endmodule
/**************************************************************************************************/
`default_nettype wire
|
`timescale 1ns / 1ps
module SimpleAI (
input [8:0] X_state,
input [8:0] O_state,
output wire [8:0] AIMove
);
wire [8:0] win, block, empty;
// Win as X
TwoInGrid winX(X_state, O_state, win);
// Block O from Winning
TwoInGrid blockO(O_state, X_state, block);
// Pick a "Random" Empty square
Empty emptyx (~(X_state | O_state), empty);
Select3 pick(win, block, empty, AIMove);
endmodule
module TwoInRow(
input [2:0] Xin,
input [2:0] Yin,
output wire [2:0] cout
);
assign cout[0] = ~Yin[0] & ~Xin[0] & Xin[1] & Xin[2];
assign cout[1] = ~Yin[1] & Xin[0] & ~Xin[1] & Xin[2];
assign cout[2] = ~Yin[2] & Xin[0] & Xin[1] & ~Xin[2];
endmodule
//Note that this module is actually reversible -- If you assign Y to X and X to Y it'll behave as expected.
//This solves for X with the current terminology (finds all spaces that have two in a row for X).
module TwoInGrid(
input [8:0] X_state,
input [8:0] Y_state,
output wire [8:0] cout
);
wire [8:0] rows, cols;
wire [2:0] diag1, diag2;
//check rows
TwoInRow row1 (X_state[2:0], Y_state[2:0], rows[2:0]);
TwoInRow row2 (X_state[5:3], Y_state[5:3], rows[5:3]);
TwoInRow row3 (X_state[8:6], Y_state[8:6], rows[8:6]);
//check columns
TwoInRow col1 ({X_state[2], X_state[5], X_state[8]}, {Y_state[2], Y_state[5], Y_state[8]}, {cols[2], cols[5], cols[8]});
TwoInRow col2 ({X_state[1], X_state[4], X_state[7]}, {Y_state[1], Y_state[4], Y_state[7]}, {cols[1], cols[4], cols[7]});
TwoInRow col3 ({X_state[0], X_state[3], X_state[6]}, {Y_state[0], Y_state[3], Y_state[6]}, {cols[0], cols[3], cols[6]});
//check diagonals
TwoInRow diagCheck1 ({X_state[8], X_state[4], X_state[0]}, {Y_state[8], Y_state[4], Y_state[0]}, diag1);
TwoInRow diagCheck2 ({X_state[6], X_state[4], X_state[2]}, {Y_state[6], Y_state[4], Y_state[2]}, diag2);
assign cout = rows | cols |
{diag1[2], 1'b0, 1'b0, 1'b0, diag1[1], 1'b0, 1'b0, 1'b0, diag1[0]} | //diag1
{1'b0, 1'b0, diag2[2], 1'b0, diag2[1], 1'b0, diag2[0], 1'b0, 1'b0}; //diag2
endmodule
// Arbitriter, selecting the most significant bit.
module RARb #(parameter n = 8)
(r, g);
input [n - 1 : 0] r;
output [n - 1 : 0] g;
wire [ n - 1 : 0 ] c = {1'b1, (~r[n-1:1] & c[n-1:1])};
assign g = r & c;
endmodule
module Empty(
input [8:0] in,
output [8:0] out);
RARb #(9) ra({in[4],in[0],in[2],in[6],in[8],in[1],in[3],in[5],in[7]},
{out[4],out[0],out[2],out[6],out[8],out[1],out[3],out[5],out[7]}) ;
endmodule
module Select3(
input [8:0] a,
input [8:0] b,
input [8:0] c,
output wire [8:0] out);
wire [26:0] x;
RARb #(27) ra({a, b, c}, x);
assign out = x[26:18] | x[17:9] | x[8:0];
endmodule
module Select2(
input [8:0] a,
input [8:0] b,
output wire [8:0] out);
wire [17:0] x;
RARb #(18) ra({a, b}, x);
assign out = x[17:9] | x[8:0];
endmodule
|
`timescale 1ns/1ns
`include "aluop_def.v"
module ShiftRight(
input signed [31:0] inp,
input [4:0] shamt,
input isSrl,
output [31:0] out
);
assign out = (isSrl)? $signed(inp>>shamt):
(inp>>>shamt);
endmodule
module alu (a,b,op,c,over);
input [31:0] a,b;
input [3:0] op;
output [31:0] c;
output over;
wire [31:0] tmp,slt_result;
wire [31:0] sr_result;
wire [32:0] sltu_result;
ShiftRight sr(b,a[4:0],op==`ALU_SRL,sr_result);
assign tmp=((op==`ALU_SUB)?~b+1:b);
assign slt_result=a-b;
assign sltu_result={1'b0,a}-{1'b0,b};
assign c=(op==`ALU_ADD)?a+b:
(op==`ALU_SUB)?a-b:
(op==`ALU_OR)?a|b:
(op==`ALU_AND)?a & b:
(op==`ALU_XOR)?a ^ b:
(op==`ALU_NOR)?~(a|b):
(op==`ALU_SLL)?b<<a[4:0]:
(op==`ALU_SRL||op==`ALU_SRA)?sr_result:
(op==`ALU_SLT)?{31'd0,slt_result[31]}:
(op==`ALU_SLTU)?{31'd0,sltu_result[32]}:
32'hBBAACCDD;//for debug
assign over=((op==`ALU_ADD || op==`ALU_SUB) &&
a[31]==tmp[31] && tmp[31]==~c[31]);
endmodule
|
/*
* Simple 8-bit FPGA softcore CPU.
* Copyright (C) 2015 P. Heinonen.
* Licensed under the MIT License. For more details, read the LICENSE file.
*
* compiler: Icarus Verilog 0.9.7
* Timing analysis with GTKWave
*
*/
module waterbear(
input clk,
input rst,
output[7:0] PC);
// Control Unit stages
// Classic RISC type pipeline without MEM stage
parameter IF=2'b00;
parameter ID=2'b01;
parameter EX=2'b10;
parameter WB=2'b11;
// index for memcopy in store step
integer i;
// Control Unit registers
reg[1:0] control_unit_current;
reg[1:0] control_unit_next;
// mnemonics of opcodes
parameter LDR = 4'b001; // load
parameter STR = 4'b010; // store
parameter ADD = 4'b011; // add
parameter SUB = 4'b100; // substract
parameter EQU = 4'b101; // compare equal
parameter JMP = 4'b110; // jump
parameter HLT = 4'b111; // halt
// memory structure
reg[15:0] MEM[0:255]; // Main Memory - 16 bit wide 256 memory cells
reg[5:0] WORKMEM[0:127]; // ALU intermediate register
reg[5:0] DESTMEM[0:127]; // destination register
reg[5:0] R1; // accumulator
reg[7:0] PC; // program counter
reg[7:0] MAR; // Memory Address register
reg[15:0] MDR; // Memory Data/Buffer Register
reg[15:0] CIR; // Current Instruction Register
// instruction set structure
reg[4:0] reserved = 5'b00000;
reg[3:0] op_code = 0;
reg numbit = 0;
reg[5:0] operand = 0;
/*
RAM memory layout contains 256 memorycells which are 16-bit wide
to store instruction set.
+-----5----+---4----+---1----+---6-----+
INSTRUCTION SET | | | | |
STRUCTURE | RESERVED | OPCODE | NUMBIT | OPERAND |
| | | | |
+----------+--------+--------+---------+
*/
// initial cpu bootup
initial begin
// initialize memory and registers
init_regs();
// memory initialization for testbench
// Sample program calculates equation: x=5+7;
/*
MEM[0] = {reserved, LDR, 1'b1, 6'b000101}; //Load value 5 into R1, mcode: 00000 001 1 000010
MEM[1] = {reserved, STR, 1'b0, 6'b001101}; //Store value from R1 in memory addr 13
MEM[2] = {reserved, LDR, 1'b1, 6'b000111}; //Load value 7 into R1
MEM[3] = {reserved, STR, 1'b0, 6'b001110}; //Store value from R1 in memory addr 14
MEM[4] = {reserved, LDR, 1'b0, 6'b001101}; //Load value from memory addr 13 into R1
MEM[5] = {reserved, ADD, 1'b0, 6'b001110}; //Add value from memory addr 14 to R1
MEM[6] = {reserved, STR, 1'b0, 6'b000010}; //Store value from R1 into memory addr 15
MEM[7] = {reserved, HLT, 1'b0, 6'b000000}; //Stop execution
*/
// Sample program: Counter to count from 0 to some user coded limit, here 5.
MEM[0] = {reserved, LDR, 1'b1, 6'b000101}; //set count value to 5
MEM[1] = {reserved, STR, 1'b0, 6'b001111}; //store count value to address 15
MEM[2] = {reserved, LDR, 1'b1, 6'b000000}; //initialize count to zero
MEM[3] = {reserved, EQU, 1'b0, 6'b001111}; //check if count is complete, if yes skip next
MEM[4] = {reserved, JMP, 1'b1, 6'b000110}; //set PC to 6
MEM[5] = {reserved, HLT, 1'b0, 6'b000000}; //stop program
MEM[6] = {reserved, ADD, 1'b1, 6'b000001}; //increment counter in accumulator
MEM[7] = {reserved, JMP, 1'b1, 6'b000011}; //set PC to 3
end
// clock cycles
always @ (clk, rst) begin
if(rst) begin
init_regs();
end
else begin
// Control Unit Finite state machine
case(control_unit_current)
IF: begin
MAR = PC;
PC = PC +1;
MDR = MEM[MAR];
CIR = MDR;
control_unit_next=ID;
end
ID: begin
control_unit_next=EX;
InstructionDecoder(CIR, op_code, numbit, operand);
end
EX: begin
// execute ALU instructions
case(op_code)
LDR: begin
if(numbit==1) begin
R1 = operand; // direct assign
end else begin
R1 = WORKMEM[operand]; // assign from address
end
control_unit_next=WB;
end
STR: begin
WORKMEM[operand] = R1;
control_unit_next=WB;
end
ADD: begin
if(numbit==1) begin
R1=R1+operand;
end else begin
R1=R1+WORKMEM[operand];
end
control_unit_next=WB;
end
JMP : begin
PC=operand;
control_unit_next=WB;
end
EQU: begin
if(R1 == WORKMEM[operand]) begin
PC=PC+1;
end
control_unit_next=WB;
end
HLT: begin
control_unit_next=EX; // continue loop
end
default: begin end
endcase
end // end of execute ALU instructions
WB: begin
// Loop is synthesizable:
// http://www.lcdm-eng.com/papers/snug13_SNUG-SV-2013_Synthesizable-SystemVerilog_paper.pdf
for (i=0; i<127; i=i+1 ) begin
DESTMEM[i] <= WORKMEM[i];
end
control_unit_next=IF;
end
default: begin end
endcase
control_unit_current=control_unit_next;
end
end
// task to initialize registers and memory
task init_regs;
begin
PC = 0;
R1 = 0;
MDR = 0;
MAR = 0;
CIR = 0;
//WORKMEM = 0; //{0,128'h80};
//DESTMEM = 0; //{0,128'h80};
control_unit_current = IF;
numbit = 0;
operand = 0;
op_code = 0;
reserved = 0;
end
endtask
// in execute, Control Unit
task InstructionDecoder;
input[15:0] CIR;
output[3:0] op_code;
output numbit;
output[5:0] operand;
begin
op_code= CIR[10:7];
numbit=CIR[6:6];
operand=CIR[5:0];
end
endtask
endmodule
// For the test 4 core test
module multicore(
input clk,
input rst,
output[7:0] PC);
waterbear core1(clk, reset, PC);
waterbear core2(clk, reset, PC);
waterbear core3(clk, reset, PC);
waterbear core4(clk, reset, PC);
endmodule
|
// Clock-rate agnostic
// RX_CLOCK_MUL must be >= 1
// TODO:
// other control lines?
module uart
#(parameter WAIT_DELAY = 200,
RX_CLOCK_MUL = 5,
STOPBITS = 1,
PARITY = 0,
BITSIZE = 8)
(input reset,
input uart_clock,
input [7:0] tx_data,
input tx_wren,
output reg tx,
output wire tx_led,
output reg tx_accept,
input rx_clock,
input rx,
output wire rx_led,
output reg [7:0] rx_data,
output reg rx_data_ready);
localparam WAIT_DELAY_BITS = $clog2(WAIT_DELAY);
reg [WAIT_DELAY_BITS-1:0] wait_count;
localparam TX_INIT=0, TX_IDLE=1, TX_START_BIT=2, TX_SEND_8BIT=3, TX_PARITY_BIT=4, TX_STOP_BIT=5;
reg [2:0] tx_state;
// tx output
assign tx_led = (tx_state == TX_START_BIT || tx_state == TX_SEND_8BIT || tx_state == TX_STOP_BIT);
reg [2:0] tx_bit_count;
// data input
reg [7:0] tx_bits;
// flow
reg tx_stopbits;
reg tx_parity;
always @(posedge uart_clock or posedge reset)
begin
if(reset) begin
// state
wait_count <= 'b0;
tx_state <= TX_INIT;
// TX
tx <= 'b1;
tx_accept <= 'b0;
tx_bits <= 'b0;
tx_bit_count <= 0;
tx_stopbits <= 1'b0;
tx_parity <= 1'b0;
end else begin
case(tx_state)
TX_INIT: begin
tx <= 'b1; // Put the tx pin into idle immediately
// Wait some time sending any data
if(wait_count == (WAIT_DELAY - 1)) begin
tx_state <= TX_IDLE;
end else begin
wait_count <= wait_count + 1;
end
end
TX_IDLE: begin
tx <= 'b1;
if(tx_wren)
begin
tx_bits <= tx_data;
tx_accept <= 'b1;
tx_state <= TX_START_BIT;
end
end
TX_START_BIT: begin
// For one clock cycle pull tx low to 0 to trigger a start bit
tx <= 'b0;
// The data input clock goes low in the start_bit so that new data can be prepared asap
tx_accept <= 'b0;
// Send 8 bits of data...
tx_bit_count <= 0;
tx_parity <= 1'b0;
tx_state <= TX_SEND_8BIT;
end
TX_SEND_8BIT: begin
// Set current output bit and rotate
tx_parity <= tx_parity ^ tx_bits[0];
tx <= tx_bits[0];
tx_bits <= {1'b0, tx_bits[7:1]};
// After BITSIZE bits, send a parity bit or skip to stop bit
if(tx_bit_count == (BITSIZE - 1)) begin
tx_stopbits <= 1'b0;
tx_state <= (PARITY == 1 || PARITY == 2) ? TX_PARITY_BIT : TX_STOP_BIT;
end else begin
tx_bit_count <= tx_bit_count + 1;
end
end
TX_PARITY_BIT: begin
// If there were an odd number of 1s, tx_parity is 1 right now
// If there were an even number of 1s, tx_parity is 0 right now
// ODD mode (PARITY==1), wants a 1 if there were an even number of ones
// EVEN mode (PARITY==2), wants a 1 if there were an odd number of ones
tx <= (PARITY == 1) ? ~tx_parity : tx_parity;
tx_state <= TX_STOP_BIT; // Only one bit of parity
end
TX_STOP_BIT: begin
// Send a '1' for the stop bit
tx <= 'b1;
// If there's 1 stop bit, then proceed to the next byte in one cycle
// otherwise, for 2 stop bits, wait one extra stop bit cycle before
// the next byte
if((STOPBITS == 1) || ((STOPBITS == 2 && tx_stopbits == 1'b1))) begin
// If tx_wren is high then there's more data
if(tx_wren)
begin
tx_bits <= tx_data;
tx_accept <= 'b1;
tx_state <= TX_START_BIT;
end else begin
// If there's no data to transmit, go into IDLE leaving tx high
tx_state <= TX_IDLE;
end
end else begin
tx_stopbits <= 1'b1;
end
end
default: begin
tx <= 'b0;
tx_accept <= 'b1;
tx_bit_count <= 0;
tx_state <= TX_IDLE;
end
endcase
end
end
localparam RX_START_BIT_SAMPLES = (RX_CLOCK_MUL + 1) / 2;
localparam RX_IDLE=0, RX_START_BIT=1, RX_SAMPLE_BITS=2, RX_PARITY_BIT=3, RX_STOP_BIT=4;
reg [2:0] rx_state;
reg [($clog2(RX_CLOCK_MUL)-1):0] rx_counter;
reg [2:0] rx_bit_count;
reg [7:0] rx_bits;
assign rx_led = (rx_state == RX_START_BIT || rx_state == RX_SAMPLE_BITS || rx_state == RX_STOP_BIT);
reg rx_stopbits;
reg rx_parity;
always @(posedge rx_clock or posedge reset)
begin
if(reset) begin
rx_counter <= 0;
rx_bit_count <= 0;
rx_bits <= 8'b0;
rx_data <= 8'b0;
rx_data_ready <= 0;
rx_state <= RX_IDLE;
rx_stopbits <= 1'b0;
rx_parity <= 1'b0;
end else begin
case(rx_state)
RX_IDLE: begin
// In idle, wait for rx to go low for a long enough period of time
if(~rx) begin
if(rx_counter == (RX_START_BIT_SAMPLES - 1)) begin
rx_counter <= 0;
rx_state <= RX_START_BIT;
end else begin
rx_counter <= rx_counter + 1;
end
end else begin
rx_counter <= 0;
end
end
RX_START_BIT: begin
// now wait for a full uart clock cycle before sampling data..
if(rx_counter == (RX_CLOCK_MUL - 1)) begin
rx_bit_count <= 0;
rx_counter <= 0;
rx_parity <= 1'b0;
rx_state <= RX_SAMPLE_BITS;
end else begin
rx_counter <= rx_counter + 1;
end
end
RX_SAMPLE_BITS: begin
if(rx_counter == 0) begin
rx_parity <= rx_parity ^ rx;
if(rx_bit_count == (BITSIZE - 1)) begin
// On SIZEs < 8, we have to shift bits into position, but this works for 8 too
rx_bits <= {rx, rx_bits[7:1]} >> (8 - BITSIZE);
rx_state <= (PARITY == 1 || PARITY == 2) ? RX_PARITY_BIT : RX_STOP_BIT;
rx_stopbits <= 1'b0;
rx_data_ready <= 1'b0;
end else begin
rx_bits <= {rx, rx_bits[7:1]};
rx_bit_count <= rx_bit_count + 1;
end
end
if(rx_counter == (RX_CLOCK_MUL - 1)) begin
rx_counter <= 0;
end else begin
rx_counter <= rx_counter + 1;
end
end
RX_PARITY_BIT: begin
// counter is at 1 when entering this state
if(rx_counter == 0) begin
// If there were an odd number of 1s, tx_parity is 1 right now
// If there were an even number of 1s, tx_parity is 0 right now
// ODD mode (PARITY==1), wants a 1 if there were an even number of ones
// EVEN mode (PARITY==2), wants a 1 if there were an odd number of ones
if(((PARITY == 1) && (rx == ~rx_parity)) || ((PARITY == 2) && (rx == rx_parity))) begin
rx_state <= RX_STOP_BIT;
end else begin
// The parity bit was incorrect so back to IDLE...TODO: transmission error output signal
rx_state <= RX_IDLE;
end
end
if(rx_counter == (RX_CLOCK_MUL - 1)) begin
rx_counter <= 0;
end else begin
rx_counter <= rx_counter + 1;
end
end
RX_STOP_BIT: begin
// counter is at 1 when entering this state
if(rx_counter == 0) begin
if(rx) begin // transmission done
// Stop bit received
if((STOPBITS == 1) || ((STOPBITS == 2) && rx_stopbits == 1'b1)) begin
rx_data <= rx_bits;
rx_state <= RX_IDLE;
// the system has until the next stop bit to pull the data
// and must wait for rx_data_ready to go low before the next data
// is available
rx_data_ready <= 1'b1;
end else begin
rx_stopbits <= 1'b1;
end
end else begin
// There's no stop bit, so we assume there's a transmission error
// For now, ignore the data. TODO: transmission error output signal
rx_state <= RX_IDLE;
end
end
if(rx_counter == (RX_CLOCK_MUL - 1)) begin
rx_counter <= 0;
end else begin
rx_counter <= rx_counter + 1;
end
end
default: begin
rx_counter <= 0;
rx_bit_count <= 0;
rx_bits <= 8'b0;
rx_data <= 8'b0;
rx_data_ready <= 0;
rx_state <= RX_IDLE;
end
endcase
end
end
endmodule
|
// Copyright (c) 2013 Andrew Downing
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
`timescale 1ns / 1ps
module OperateTb();
// constants
localparam INSTRUC_SIZE = 32, ARG_SIZE = 8, DATA_SIZE = 8;
// inputs
reg clk, reset, start, ack;
reg [(INSTRUC_SIZE - 1) : 0] instruc;
reg [(DATA_SIZE - 1) : 0] rdData;
// outputs
wire rdEn; // data read enable
wire wrEn; // data write enable
wire [(ARG_SIZE - 1) : 0] addr; // data read/write address
wire [(DATA_SIZE - 1) : 0] wrData; // data write value
wire [(ARG_SIZE - 1) : 0] pc; // program counter
wire done;
Operate uut(.clk(clk), .reset(reset), .start(start), .ack(ack), .instruc(instruc), .rdData(rdData),
.rdEn(rdEn), .wrEn(wrEn), .addr(addr), .wrData(wrData), .pc(pc), .done(done));
initial begin : CLOCK_GEN
clk = 1;
forever begin
#5;
clk = ~clk;
end
end
initial begin
// do reset
reset = 1;
#15;
// start program
reset = 0;
start = 1;
ack = 0;
#10;
start = 0;
#10;
// add
instruc = 32'h00_01_02_03;
#20;
rdData = 4;
#10;
rdData = 5;
#10;
rdData = 8'bx;
#10;
// halt
instruc = 32'h0f_xx_xx_xx;
wait (done);
#5;
// ack
ack = 1;
wait (!done);
#5;
ack = 0;
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_1_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_1_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog wrapper for dlygate4sd1 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__dlygate4sd1.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd1_1 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__dlygate4sd1 base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__dlygate4sd1_1 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__dlygate4sd1 base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_2_V
`define SKY130_FD_SC_LP__DLRBP_2_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_2 (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_2_V
|
(** * IndPrinciples: Induction Principles *)
(** With the Curry-Howard correspondence and its realization in Coq in
mind, we can now take a deeper look at induction principles. *)
Set Warnings "-notation-overridden,-parsing,-deprecated-hint-without-locality".
From LF Require Export ProofObjects.
(* ################################################################# *)
(** * Basics *)
(** Every time we declare a new [Inductive] datatype, Coq
automatically generates an _induction principle_ for this type.
This induction principle is a theorem like any other: If [t] is
defined inductively, the corresponding induction principle is
called [t_ind]. Here is the one for natural numbers: *)
Check nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n.
(** In English: Suppose [P] is a property of natural numbers (that is,
[P n] is a [Prop] for every [n]). To show that [P n] holds of all
[n], it suffices to show:
- [P] holds of [0]
- for any [n], if [P] holds of [n], then [P] holds of [S n]. *)
(** The [induction] tactic is a straightforward wrapper that, at its
core, simply performs [apply t_ind]. To see this more clearly,
let's experiment with directly using [apply nat_ind], instead of
the [induction] tactic, to carry out some proofs. Here, for
example, is an alternate proof of a theorem that we saw in the
[Induction] chapter. *)
Theorem mul_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *) simpl. intros n' IHn'. rewrite -> IHn'.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting.
First, in the induction step of the proof (the [S] case), we
have to do a little bookkeeping manually (the [intros]) that
[induction] does automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. By contrast, the
[induction] tactic works either with a variable in the context or
a quantified variable in the goal.
Third, we had to manually supply the name of the induction principle
with [apply], but [induction] figures that out itself.
These conveniences make [induction] nicer to use in practice than
applying induction principles like [nat_ind] directly. But it is
important to realize that, modulo these bits of bookkeeping,
applying [nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, standard (plus_one_r')
Complete this proof without using the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Coq generates induction principles for every datatype
defined with [Inductive], including those that aren't recursive.
Although of course we don't need the proof technique of induction
to prove properties of non-recursive datatypes, the idea of an
induction principle still makes sense for them: it gives a way to
prove that a property holds for all values of the type. *)
(** These generated principles follow a similar pattern. If we
define a type [t] with constructors [c1] ... [cn], Coq generates a
theorem with this shape:
t_ind : forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... -> ...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. *)
(** Before trying to write down a general rule, let's look at
some more examples. First, an example where the constructors take
no arguments: *)
Inductive time : Type :=
| day
| night.
Check time_ind :
forall P : time -> Prop,
P day ->
P night ->
forall t : time, P t.
(** **** Exercise: 1 star, standard, optional (rgb)
Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red
| green
| blue.
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil
| ncons (n : nat) (l : natlist).
Check natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist),
P l -> P (ncons n l)) ->
forall l : natlist, P l.
(** In general, the automatically generated induction principle for
inductive type [t] is formed as follows:
- Each constructor [c] generates one case of the principle.
- If [c] takes no arguments, that case is:
"P holds of c"
- If [c] takes arguments [x1:a1] ... [xn:an], that case is:
"For all x1:a1 ... xn:an,
if [P] holds of each of the arguments of type [t],
then [P] holds of [c x1 ... xn]"
But that oversimplifies a little. An assumption about [P]
holding of an argument [x] of type [t] actually occurs
immediately after the quantification of [x].
*)
(** For example, suppose we had written the definition of [natlist] a little
differently: *)
Inductive natlist' : Type :=
| nnil'
| nsnoc (l : natlist') (n : nat).
(** Now the induction principle case for [nsnoc1] is a bit different
than the earlier case for [ncons]: *)
Check natlist'_ind :
forall P : natlist' -> Prop,
P nnil' ->
(forall l : natlist', P l -> forall n : nat, P (nsnoc l n)) ->
forall n : natlist', P n.
(** **** Exercise: 1 star, standard (booltree_ind)
In the comment below, write out the induction principle that Coq
will generate for the following datatype. *)
Inductive booltree : Type :=
| bt_empty
| bt_leaf (b : bool)
| bt_branch (b : bool) (t1 t2 : booltree).
(* FILL IN HERE:
... *)
(* Do not modify the following line: *)
Definition manual_grade_for_booltree_ind : option (nat*string) := None.
(** [] *)
(** **** Exercise: 1 star, standard (toy_ind)
Here is an induction principle for a toy type:
forall P : Toy -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (t : Toy), P t -> P (con2 n t)) ->
forall t : Toy, P t
Give an [Inductive] definition of [Toy], such that the induction
principle Coq generates is that given above: *)
Inductive Toy : Type :=
(* FILL IN HERE *)
.
(* Do not modify the following line: *)
Definition manual_grade_for_toy_ind : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Polymorphism *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
*)
(** The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note that the _whole_ induction principle is parameterized on
[X]. That is, [list_ind] can be thought of as a polymorphic
function that, when applied to a type [X], gives us back an
induction principle specialized to the type [list X]. *)
(** **** Exercise: 1 star, standard, optional (tree)
Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf (x : X)
| node (t1 t2 : tree X).
Check tree_ind.
(** [] *)
(** **** Exercise: 1 star, standard, optional (mytype)
Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
(** [] *)
(** **** Exercise: 1 star, standard, optional (foo)
Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
(** [] *)
(** **** Exercise: 1 star, standard, optional (foo')
Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 (l : list X) (f : foo' X)
| C2.
(** What induction principle will Coq generate for [foo']? (Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
_______________________ ->
_______________________ ) ->
___________________________________________ ->
forall f : foo' X, ________________________
*)
(** [] *)
(* ################################################################# *)
(** * Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (or rather, strictly speaking, for all families of
propositions [P] indexed by a number [n]). Each time we
use this principle, we are choosing [P] to be a particular
expression of type [nat -> Prop].
We can make proofs by induction more explicit by giving
this expression a name. For example, instead of stating
the theorem [mul_0_r] as "[forall n, n * 0 = 0]," we can
write it as "[forall n, P_m0r n]", where [P_m0r] is defined
as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently: *)
Definition P_m0r' : nat -> Prop :=
fun n => n * 0 = 0.
(** Now it is easier to see where [P_m0r] appears in the proof. *)
Theorem mul_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
- (* n = O *) reflexivity.
- (* n = S n' *)
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ################################################################# *)
(** * More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
*)
(** What Coq actually does in this situation, internally, is it
"re-generalizes" the variable we perform induction on. For
example, in our original proof that [plus] is associative... *)
Theorem add_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
- (* n = O *) reflexivity.
- (* n = S n' *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem add_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
- (* n = O *) intros m. rewrite -> add_0_r. reflexivity.
- (* n = S n' *) intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem add_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m']. (* [n] is already introduced into the context *)
- (* m = O *) simpl. rewrite -> add_0_r. reflexivity.
- (* m = S m' *) simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, standard, optional (plus_explicit_prop)
Rewrite both [add_assoc'] and [add_comm'] and their proofs in
the same style as [mul_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
(* FILL IN HERE
[] *)
(* ################################################################# *)
(** * Induction Principles for Propositions *)
(** Inductive definitions of propositions also cause Coq to generate
induction priniciples. For example, recall our proposition [ev]
from [IndProp]: *)
Print ev.
(* ===>
Inductive ev : nat -> Prop :=
| ev_0 : ev 0
| ev_SS : forall n : nat, ev n -> ev (S (S n)))
*)
Check ev_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, ev n -> P n -> P (S (S n))) ->
forall n : nat, ev n -> P n.
(** In English, [ev_ind] says: Suppose [P] is a property of natural
numbers. To show that [P n] holds whenever [n] is even, it suffices
to show:
- [P] holds for [0],
- for any [n], if [n] is even and [P] holds for [n], then [P]
holds for [S (S n)]. *)
(** As expected, we can apply [ev_ind] directly instead of using
[induction]. For example, we can use it to show that [ev'] (the
slightly awkward alternate definition of evenness that we saw in
an exercise in the [IndProp] chapter) is equivalent to the
cleaner inductive definition [ev]: *)
Inductive ev' : nat -> Prop :=
| ev'_0 : ev' 0
| ev'_2 : ev' 2
| ev'_sum n m (Hn : ev' n) (Hm : ev' m) : ev' (n + m).
Theorem ev_ev' : forall n, ev n -> ev' n.
Proof.
apply ev_ind.
- (* ev_0 *)
apply ev'_0.
- (* ev_SS *)
intros m Hm IH.
apply (ev'_sum 2 m).
+ apply ev'_2.
+ apply IH.
Qed.
(** The precise form of an [Inductive] definition can affect the
induction principle Coq generates. *)
Inductive le1 : nat -> nat -> Prop :=
| le1_n : forall n, le1 n n
| le1_S : forall n m, (le1 n m) -> (le1 n (S m)).
Notation "m <=1 n" := (le1 m n) (at level 70).
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le2 (n:nat) : nat -> Prop :=
| le2_n : le2 n n
| le2_S m (H : le2 n m) : le2 n (S m).
Notation "m <=2 n" := (le2 m n) (at level 70).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le1_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, n <=1 m -> P n m -> P n (S m)) ->
forall n n0 : nat, n <=1 n0 -> P n n0.
Check le2_ind :
forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <=2 m -> P m -> P (S m)) ->
forall n0 : nat, n <=2 n0 -> P n0.
(* ################################################################# *)
(** * Another Form of Induction Principles on Propositions (Optional) *)
(** The induction principle that Coq generated for [ev] was parameterized
on a natural number [n]. It could have additionally been parameterized
on the evidence that [n] was even, which would have led to this
induction principle:
forall P : (forall n : nat, ev'' n -> Prop),
P O ev_0 ->
(forall (m : nat) (E : ev'' m),
P m E -> P (S (S m)) (ev_SS m E)) ->
forall (n : nat) (E : ev'' n), P n E
*)
(** ... because:
- Since [ev] is indexed by a number [n] (every [ev] object [E] is
a piece of evidence that some particular number [n] is even),
the proposition [P] is parameterized by both [n] and [E] --
that is, the induction principle can be used to prove
assertions involving both an even number and the evidence that
it is even.
- Since there are two ways of giving evidence of evenness ([even]
has two constructors), applying the induction principle
generates two subgoals:
- We must prove that [P] holds for [O] and [ev_0].
- We must prove that, whenever [m] is an even number and [E]
is an evidence of its evenness, if [P] holds of [m] and
[E], then it also holds of [S (S m)] and [ev_SS m E].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ even numbers [n] and
evidence [E] of their evenness.
This is more flexibility than we normally need or want: it is
giving us a way to prove logical assertions where the assertion
involves properties of some piece of _evidence_ of evenness, while
all we really care about is proving properties of _numbers_ that
are even -- we are interested in assertions about numbers, not
about evidence. It would therefore be more convenient to have an
induction principle for proving propositions [P] that are
parameterized just by [n] and whose conclusion establishes [P] for
all even numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat,
even n -> P n
That is why Coq actually generates the induction principle
[ev_ind] that we saw before. *)
(* ################################################################# *)
(** * Formal vs. Informal Proofs by Induction *)
(** Question: What is the relation between a formal proof of a
proposition [P] and an informal proof of the same proposition [P]?
Answer: The latter should _teach_ the reader everything they would
need to understand to be able to produce the former.
Question: How much detail does that require?
Unfortunately, there is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the "informal" proof will amount to just
transcribing the formal one into words). This may give the reader
the ability to reproduce the formal one for themselves, but it
probably doesn't _teach_ them anything much.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because often
writing the proof requires one or more significant insights into
the thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard work that we
went through to find the proof in the first place) plus high-level
suggestions for the more routine parts to save the reader from
spending too much time reconstructing these (e.g., what the IH says
and what must be shown in each case of an inductive proof), but not
so much detail that the main ideas are obscured.
Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief and
telegraphic. Although the ideal is somewhere in between, while one
is getting used to the style it is better to start out at the
pedantic end. Also, during the learning phase, it is probably
helpful to have a clear standard to compare against. With this in
mind, we offer two templates -- one for proofs by induction over
_data_ (i.e., where the thing we're doing induction on lives in
[Type]) and one for proofs by induction over _evidence_ (i.e.,
where the inductively defined thing lives in [Prop]). *)
(* ================================================================= *)
(** ** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if [length [] = n], then [index (S n) [] =
None].
This follows immediately from the definition of [index].
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
But this follows directly from the induction hypothesis,
picking [n'] to be [length l']. [] *)
(* ================================================================= *)
(** ** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* ################################################################# *)
(** * Explicit Proof Objects for Induction (Optional) *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall again the induction principle on naturals that Coq generates for
us automatically from the Inductive declaration for [nat]. *)
Check nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n.
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind.
(** We can rewrite that more tidily as follows: *)
Fixpoint build_proof
(P : nat -> Prop)
(evPO : P 0)
(evPS : forall n : nat, P n -> P (S n))
(n : nat) : P n :=
match n with
| 0 => evPO
| S k => evPS k (build_proof P evPO evPS k)
end.
Definition nat_ind_tidy := build_proof.
(** We can read [build_proof] as follows: Suppose we have
evidence [evPO] that [P] holds on 0, and evidence [evPS] that [forall
n:nat, P n -> P (S n)]. Then we can prove that [P] holds of an
arbitrary nat [n] using recursive function [build_proof], which
pattern matches on [n]:
- If [n] is 0, [build_proof] returns [evPO] to show that [P n]
holds.
- If [n] is [S k], [build_proof] applies itself recursively on
[k] to obtain evidence that [P k] holds; then it applies
[evPS] on that evidence to show that [P (S n)] holds. *)
(** Recursive function [build_proof] thus pattern matches against
[n], recursing all the way down to 0, and building up a proof
as it returns. *)
(** The actual [nat_ind] that Coq generates uses a recursive
function [F] defined with [fix] instead of [Fixpoint]. *)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. As a motivating example,
suppose that we want to prove the following lemma, directly
relating the [ev] predicate we defined in [IndProp]
to the [even] function defined in [Basics]. *)
Lemma even_ev : forall n: nat, even n = true -> ev n.
Proof.
induction n; intros.
- apply ev_0.
- destruct n.
+ simpl in H. inversion H.
+ simpl in H.
apply ev_SS.
Abort.
(** Attempts to prove this by standard induction on [n] fail in the case for
[S (S n)], because the induction hypothesis only tells us something about
[S n], which is useless. There are various ways to hack around this problem;
for example, we _can_ use ordinary induction on [n] to prove this (try it!):
[Lemma even_ev' : forall n : nat,
(even n = true -> ev n) /\ (even (S n) = true -> ev (S n))].
But we can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive.
The [induction ... using] tactic variant gives a convenient way to
utilize a non-standard induction principle like this. *)
Lemma even_ev : forall n, even n = true -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
- apply ev_0.
- simpl in H.
inversion H.
- simpl in H.
apply ev_SS.
apply IHn'.
apply H.
Qed.
(* 2021-08-11 15:08 *)
|
Require Import List.
Import ListNotations.
Require Import Omega.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import InfSeqExt.infseq.
Require Import Chord.InfSeqTactics.
Require Import Chord.Chord.
Require Import Chord.ChannelLemmas.
Require Import Chord.HandlerLemmas.
Require Import Chord.SystemLemmas.
Require Import Chord.SystemReachable.
Require Import Chord.SystemPointers.
Require Import Chord.LabeledLemmas.
Require Import Chord.LabeledMeasures.
Require Import Chord.FirstSuccNeverSelf.
Require Import Chord.QueryInvariant.
Require Import Chord.LiveNodesStayLive.
Require Import Chord.LiveNodesNotClients.
Require Import Chord.DeadNodesGoQuiet.
Require Import Chord.ValidPointersInvariant.
Require Import Chord.NodesAlwaysHaveLiveSuccs.
Require Import Chord.NodesHaveState.
Require Import Chord.WfPtrSuccListInvariant.
Require Import Chord.SuccessorNodesAlwaysValid.
Require Import Chord.StabilizeOnlyWithFirstSucc.
Require Import Chord.NodesNotJoinedHaveNoSuccessors.
Require Import Chord.QueriesEventuallyStop.
Require Import Chord.LiveNodeHasTickInTimeouts.
Set Bullet Behavior "Strict Subproofs".
Open Scope nat_scope.
Definition has_dead_first_succ (gst : global_state) (h : addr) (s : pointer) :=
exists st,
sigma gst h = Some st /\
exists rest,
succ_list st = s :: rest /\
In (addr_of s) (failed_nodes gst).
Lemma has_dead_first_succ_intro :
forall gst h s st rest,
sigma gst h = Some st ->
succ_list st = s :: rest ->
In (addr_of s) (failed_nodes gst) ->
has_dead_first_succ gst h s.
Proof.
firstorder eauto.
Qed.
(* cf. zave page 11 *)
Definition first_succ_is_best_succ (gst : global_state) (h : addr) :=
exists st s rest,
sigma gst h = Some st /\
succ_list st = s :: rest /\
best_succ gst h (addr_of s).
Definition all_first_succs_best (gst : global_state) :=
forall h,
live_node gst h ->
first_succ_is_best_succ gst h.
Definition phase_one (o : occurrence) : Prop :=
all_first_succs_best (occ_gst o).
(* Defining the error for phase one: the norm approach *)
Fixpoint succ_list_leading_failed_nodes (failed : list addr) (succs : list pointer) : nat :=
match succs with
| h :: rest =>
if In_dec addr_eq_dec (addr_of h) failed
then S (succ_list_leading_failed_nodes failed rest)
else 0
| [] => 0
end.
(* The local error measure for phase one. *)
Definition leading_failed_succs (h : addr) (gst : global_state) : nat :=
match sigma gst h with
| Some st =>
succ_list_leading_failed_nodes (failed_nodes gst) (succ_list st)
| None =>
0
end.
Lemma leading_failed_succs_st :
forall h gst st,
sigma gst h = Some st ->
leading_failed_succs h gst = succ_list_leading_failed_nodes (failed_nodes gst) (succ_list st).
Proof.
unfold leading_failed_succs.
intros.
break_match; congruence.
Qed.
Definition phase_one_error : global_state -> nat :=
global_measure leading_failed_succs.
Lemma successor_nodes_valid_inv :
forall gst h p st,
In p (succ_list st) ->
successor_nodes_valid gst ->
sigma gst h = Some st ->
In (addr_of p) (nodes gst) /\
exists pst, sigma gst (addr_of p) = Some pst /\
joined pst = true.
Proof.
eauto.
Qed.
Lemma zero_leading_failed_nodes_leading_node_live :
forall gst h st s rest,
succ_list_leading_failed_nodes (failed_nodes gst) (succ_list st) = 0 ->
reachable_st gst ->
sigma gst h = Some st ->
succ_list st = s :: rest ->
wf_ptr s ->
wf_ptr s /\ live_node gst (addr_of s).
Proof.
intros.
repeat find_rewrite.
simpl in *.
break_if; try congruence.
unfold succ_list_leading_failed_nodes.
find_apply_lem_hyp successor_nodes_always_valid.
assert (In s (succ_list st)).
{
find_rewrite.
apply in_eq.
}
find_eapply_lem_hyp successor_nodes_valid_inv; eauto; repeat (break_exists_name pst || break_and).
eauto using live_node_characterization.
Qed.
Lemma maybe_count_failed_nodes_Some :
forall gst h st n,
leading_failed_succs h gst = n ->
sigma gst h = Some st ->
succ_list_leading_failed_nodes (failed_nodes gst) (succ_list st) = n.
Proof.
unfold leading_failed_succs.
intros.
break_match; congruence.
Qed.
Lemma zero_failed_nodes_total_implies_zero_locally :
forall gst h st,
phase_one_error gst = 0 ->
live_node gst h ->
sigma gst h = Some st ->
succ_list_leading_failed_nodes (failed_nodes gst) (succ_list st) = 0.
Proof.
unfold phase_one_error in *.
intros.
cut (leading_failed_succs h gst = 0);
eauto using maybe_count_failed_nodes_Some.
find_eapply_lem_hyp local_all_zero_global_zero.
find_eapply_lem_hyp Forall_forall; eauto.
inv_prop live_node; break_and.
eauto using in_nodes_not_failed_in_active.
Qed.
Lemma zero_leading_failed_nodes_best_succ :
forall gst h st s rest,
succ_list_leading_failed_nodes (failed_nodes gst) (succ_list st) = 0 ->
reachable_st gst ->
sigma gst h = Some st ->
succ_list st = s :: rest ->
wf_ptr s ->
live_node gst h ->
best_succ gst h (addr_of s).
Proof.
unfold best_succ.
intros.
exists st.
exists [].
exists (map addr_of rest).
simpl.
intuition.
- repeat find_rewrite.
apply map_cons.
- find_copy_eapply_lem_hyp zero_leading_failed_nodes_leading_node_live; eauto; tauto.
Qed.
Theorem zero_leading_failed_nodes_implies_all_first_succs_best :
forall gst,
reachable_st gst ->
(* total leading failed nodes says nothing about the length of successor lists *)
nonempty_succ_lists gst ->
phase_one_error gst = 0 ->
all_first_succs_best gst.
Proof.
unfold all_first_succs_best, first_succ_is_best_succ, phase_one_error.
intros.
find_copy_apply_lem_hyp local_all_zero_global_zero;
rewrite Forall_forall in *.
inv_prop live_node;
repeat (break_and; break_exists_exists).
unfold nonempty_succ_lists in *.
find_copy_apply_hyp_hyp.
destruct (succ_list _) as [| p rest] eqn:?H; [firstorder congruence|].
exists p. exists rest.
repeat split; auto.
(* need an (easy) invariant *)
assert (wf_ptr p) by eauto using wf_ptr_succ_list_invariant.
assert (live_node gst h) by eauto.
find_copy_apply_lem_hyp zero_failed_nodes_total_implies_zero_locally; auto.
eapply zero_leading_failed_nodes_best_succ; eauto.
Qed.
Lemma zero_error_implies_phase_one :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
now (measure_zero phase_one_error) ex ->
now phase_one ex.
Proof.
intros.
destruct ex.
simpl in *.
eapply zero_leading_failed_nodes_implies_all_first_succs_best; eauto.
eapply nodes_have_nonempty_succ_lists; eauto.
Qed.
Theorem continuously_zero_total_leading_failed_nodes_implies_phase_one :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
infseq.continuously (now (measure_zero phase_one_error)) ex ->
continuously (now phase_one) ex.
Proof.
intros.
pose proof zero_error_implies_phase_one.
unfold continuously in *.
prep_always_monotonic.
eapply eventually_monotonic_simple.
eapply always_monotonic; eauto.
eapply continuously_and_tl; eauto.
apply E0.
eapply reachable_st_always; eauto.
Qed.
Lemma succ_list_leading_failed_nodes_nonzero_means_dead_succ :
forall failed succs,
succ_list_leading_failed_nodes failed succs > 0 ->
exists p rest,
succs = p :: rest /\
In (addr_of p) failed.
Proof.
unfold succ_list_leading_failed_nodes.
destruct succs; intros.
- omega.
- break_if.
+ eexists; eauto.
+ omega.
Qed.
Lemma leading_failed_succs_nonzero_means_dead_succ :
forall h gst,
leading_failed_succs h gst > 0 ->
exists s,
has_dead_first_succ gst h s.
Proof.
unfold leading_failed_succs, has_dead_first_succ.
intros.
break_match; [|omega].
find_apply_lem_hyp succ_list_leading_failed_nodes_nonzero_means_dead_succ.
expand_def.
eexists; eauto.
Qed.
Lemma phase_one_error_nonzero_means_dead_succ :
forall gst,
phase_one_error gst > 0 ->
exists h,
In h (nodes gst) /\
~ In h (failed_nodes gst) /\
exists s,
has_dead_first_succ gst h s.
Proof.
intros.
find_apply_lem_hyp sum_nonzero_implies_addend_nonzero.
break_exists; break_and.
find_eapply_lem_hyp in_map_iff.
break_exists_exists.
firstorder using in_active_in_nodes, in_active_not_failed.
apply leading_failed_succs_nonzero_means_dead_succ; omega.
Qed.
Definition open_stabilize_request_to (gst : global_state) (h : addr) (dst : addr) : Prop :=
In GetPredAndSuccs (channel gst h dst) /\
open_request_to gst h dst GetPredAndSuccs.
Hint Unfold open_stabilize_request_to.
Definition open_stabilize_request (gst : global_state) (h : addr) : Prop :=
exists p,
open_stabilize_request_to gst h (addr_of p) /\
wf_ptr p.
Hint Unfold open_stabilize_request.
(** If h is a valid node with a first successor s in gst, then h has an open
stabilize request to s in gst. *)
Definition open_stabilize_request_to_first_succ (gst : global_state) (h : addr) : Prop :=
forall st dst rest,
sigma gst h = Some st ->
succ_list st = dst :: rest ->
open_stabilize_request_to gst h (addr_of dst).
Lemma open_stabilize_request_to_first_succ_intro :
forall gst h s,
has_first_succ gst h s ->
In GetPredAndSuccs (channel gst h (addr_of s)) ->
open_request_to gst h (addr_of s) GetPredAndSuccs ->
open_stabilize_request_to_first_succ gst h.
Proof.
intros.
inv_prop has_first_succ. break_and.
find_apply_lem_hyp hd_error_tl_exists.
break_exists.
unfold open_stabilize_request_to_first_succ, open_stabilize_request_to.
intuition congruence.
Qed.
Hint Resolve open_stabilize_request_to_first_succ_intro.
Lemma timeout_handler_eff_StartStabilize :
forall h st r eff,
timeout_handler_eff h st Tick = (r, eff) ->
joined st = true /\ cur_request st = None <->
eff = StartStabilize.
Proof.
intros.
destruct (timeout_handler_eff _ _ _) as [[[[?st' ?ms] ?nts] ?cts] ?eff] eqn:?H.
find_apply_lem_hyp timeout_handler_eff_definition; expand_def;
repeat find_rewrite; try congruence.
find_eapply_lem_hyp tick_handler_definition; expand_def;
repeat find_rewrite; firstorder congruence.
Qed.
Lemma timeout_handler_eff_is_timeout_handler_l :
forall h st t res eff,
timeout_handler_eff h st t = (res, eff) <->
timeout_handler_l h st t = (res, Timeout h t eff).
Proof.
intros.
unfold timeout_handler_l.
break_let.
split; intros; solve_by_inversion.
Qed.
Lemma loaded_Tick_enabled_when_cur_request_None :
forall gst h st,
reachable_st gst ->
live_node gst h ->
sigma gst h = Some st ->
cur_request st = None ->
In Tick (timeouts gst h) ->
enabled (Timeout h Tick StartStabilize) gst.
Proof.
intros.
break_live_node.
(* replace x from live_node with st *)
repeat find_rewrite; find_injection.
destruct (timeout_handler_eff h st Tick) as [[[[st' ms] nts] cts] eff] eqn:?H.
assert (eff = StartStabilize)
by (eapply timeout_handler_eff_StartStabilize; eauto).
subst.
exists (apply_handler_result h (st', ms, nts, Tick :: cts) [e_timeout h Tick] gst).
eapply LTimeout; eauto.
- now apply timeout_handler_eff_is_timeout_handler_l.
- now constructor.
Qed.
Lemma always_busy_or_not_busy :
forall h occ,
not_busy_if_live h occ \/ busy_if_live h occ.
Proof.
intros.
unfold not_busy_if_live, busy_if_live.
destruct (sigma (occ_gst occ) h) as [d|];
[destruct (cur_request d) eqn:?H|];
firstorder congruence.
Qed.
Lemma not_busy_inf_often :
forall h ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
always (~_ (now circular_wait)) ex ->
inf_often (now (not_busy_if_live h)) ex.
Proof.
intro.
pose proof (always_busy_or_not_busy h) as H_bnb.
cofix c.
intros.
constructor.
- pose proof (H_bnb (hd ex)).
destruct ex.
break_or_hyp.
+ constructor.
assumption.
+ apply queries_eventually_stop; auto.
- destruct ex.
simpl.
eapply c.
+ eapply lb_execution_invar; eauto.
+ destruct ex.
eapply reachable_st_lb_execution_cons; eauto.
+ eapply strong_local_fairness_invar; eauto.
+ inv_lb_execution.
eapply live_node_invariant; eauto.
+ eapply always_invar; eauto.
Qed.
Lemma loaded_Tick_enabled_if_now_not_busy_if_live :
forall h ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
now (not_busy_if_live h) ex ->
now (l_enabled (Timeout h Tick StartStabilize)) ex.
Proof.
intros.
destruct ex.
find_copy_apply_lem_hyp live_node_has_Tick_in_timeouts; eauto.
simpl in *.
find_copy_apply_lem_hyp live_node_joined; break_exists; break_and.
unfold not_busy_if_live in *; find_copy_apply_hyp_hyp.
eapply loaded_Tick_enabled_when_cur_request_None; eauto.
Qed.
Lemma loaded_Tick_inf_enabled :
forall h ex,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
always (~_ (now circular_wait)) ex ->
inf_enabled (Timeout h Tick StartStabilize) ex.
Proof.
intros h.
pose proof (always_busy_or_not_busy h) as H_bnb.
intros.
unfold inf_enabled.
find_copy_apply_lem_hyp not_busy_inf_often; eauto.
lift_inf_often (loaded_Tick_enabled_if_now_not_busy_if_live h);
invar_eauto.
Qed.
Lemma loaded_Tick_inf_often :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
strong_local_fairness ex ->
live_node (occ_gst (hd ex)) h ->
always (~_ (now circular_wait)) ex ->
inf_occurred (Timeout h Tick StartStabilize) ex.
Proof.
auto using loaded_Tick_inf_enabled.
Qed.
Lemma get_open_stabilize_request_to_first_succ_from_req_to :
forall gst h st dst rest,
open_stabilize_request_to gst h (addr_of dst) ->
sigma gst h = Some st ->
succ_list st = dst :: rest ->
open_stabilize_request_to_first_succ gst h.
Proof.
unfold open_stabilize_request_to_first_succ.
intros.
now repeat (find_injection || find_rewrite).
Qed.
Lemma open_stabilize_request_to_first_succ_elim :
forall gst h s,
open_stabilize_request_to_first_succ gst h ->
has_first_succ gst h s ->
In GetPredAndSuccs (channel gst h (addr_of s)) /\
open_request_to gst h (addr_of s) GetPredAndSuccs.
Proof.
unfold has_first_succ.
intros.
break_exists; break_and.
find_apply_lem_hyp hd_error_tl_exists.
firstorder.
Qed.
Lemma open_stabilize_request_to_first_succ_res_on_wire :
forall gst h s,
open_stabilize_request_to_first_succ gst h ->
has_first_succ gst h s ->
In GetPredAndSuccs (channel gst h (addr_of s)).
Proof.
apply open_stabilize_request_to_first_succ_elim.
Qed.
Hint Resolve open_stabilize_request_to_first_succ_res_on_wire.
Lemma get_open_request_to_from_open_stabilize_request :
forall gst h s,
open_stabilize_request_to_first_succ gst h ->
has_first_succ gst h s ->
open_request_to gst h (addr_of s) GetPredAndSuccs.
Proof.
apply open_stabilize_request_to_first_succ_elim.
Qed.
Hint Resolve get_open_request_to_from_open_stabilize_request.
Lemma make_request_Stabilize_needs_succ_list :
forall h st dst m,
make_request h st Stabilize = Some (dst, m) ->
exists rest,
succ_list st = dst :: rest.
Proof.
intros.
unfold make_request in *; simpl in *.
find_apply_lem_hyp option_map_Some; break_exists; break_and.
find_copy_apply_lem_hyp hd_error_some_nil.
destruct (succ_list st) eqn:?H; [discriminate|].
simpl in *.
tuple_inversion.
find_injection.
eexists; eauto.
Qed.
Lemma make_request_Stabilize_None :
forall h st,
make_request h st Stabilize = None ->
succ_list st = [].
Proof.
intros.
unfold make_request in *; simpl in *.
simpl in *.
find_eapply_lem_hyp option_map_None.
destruct (succ_list st) eqn:?H; simpl in *; congruence.
Qed.
Lemma succ_list_preserved_by_Tick :
forall gst gst' h st st',
labeled_step_dynamic gst (Timeout h Tick StartStabilize) gst' ->
sigma gst h = Some st ->
sigma gst' h = Some st' ->
succ_list st' = succ_list st.
Proof.
intros.
inv_labeled_step; clean_up_labeled_step_cases.
find_apply_lem_hyp timeout_handler_l_definition; expand_def.
find_apply_lem_hyp timeout_handler_eff_definition; expand_def;
try congruence.
find_injection.
find_apply_lem_hyp tick_handler_definition; expand_def;
try congruence.
rewrite sigma_ahr_updates in *; find_injection.
destruct (start_query _ _ _) as [[[?st' ?ms] ?nts] ?cts] eqn:?H.
find_eapply_lem_hyp add_tick_definition; expand_def.
find_apply_lem_hyp start_query_definition; expand_def;
repeat find_rewrite; solve_by_inversion.
Qed.
Lemma effective_Tick_sends_request :
forall gst gst' h st s1 rest,
sigma gst h = Some st ->
succ_list st = s1 :: rest ->
labeled_step_dynamic gst (Timeout h Tick StartStabilize) gst' ->
open_stabilize_request_to gst' h (addr_of s1).
Proof.
intros.
inv_labeled_step; clean_up_labeled_step_cases.
find_apply_lem_hyp timeout_handler_l_definition; expand_def.
find_apply_lem_hyp timeout_handler_eff_definition; expand_def;
try congruence.
find_injection.
find_apply_lem_hyp tick_handler_definition; expand_def;
try congruence.
unfold add_tick in *; repeat break_let;
find_apply_lem_hyp start_query_definition; expand_def.
- find_apply_lem_hyp option_map_Some; expand_def.
find_apply_lem_hyp hd_error_tl_exists; expand_def.
repeat (find_rewrite; repeat find_injection).
simpl in *.
repeat split;
try apply channel_contents; simpl in *;
rewrite_update; repeat eexists;
eauto with datatypes.
- simpl in *.
find_rewrite.
find_injection.
repeat find_rewrite.
discriminate.
Qed.
Lemma effective_Tick_sends_request' :
forall gst gst' h st s1 rest,
sigma gst' h = Some st ->
succ_list st = s1 :: rest ->
labeled_step_dynamic gst (Timeout h Tick StartStabilize) gst' ->
open_stabilize_request_to gst' h (addr_of s1).
Proof.
intros.
inv_labeled_step; clean_up_labeled_step_cases.
find_apply_lem_hyp timeout_handler_l_definition; expand_def.
find_apply_lem_hyp timeout_handler_eff_definition; expand_def;
try congruence.
find_injection.
find_apply_lem_hyp tick_handler_definition; expand_def;
try congruence.
destruct (start_query _ _ _) as [[[?st' ?ms] ?nts] ?cts] eqn:?H.
match goal with
| H : context[labeled_step_dynamic] |- _ =>
copy_eapply succ_list_preserved_by_Tick H; eauto
end.
repeat find_rewrite.
find_eapply_lem_hyp start_query_definition; expand_def.
- find_copy_apply_lem_hyp make_request_Stabilize_needs_succ_list; break_exists.
repeat find_rewrite.
find_injection.
eauto using effective_Tick_sends_request.
- find_eapply_lem_hyp make_request_Stabilize_None.
repeat find_rewrite.
congruence.
Qed.
Lemma effective_Tick_occurred_sent_request :
forall h ex,
lb_execution ex ->
now (occurred (Timeout h Tick StartStabilize)) ex ->
next (now (fun o => open_stabilize_request_to_first_succ (occ_gst o) h)) ex.
Proof.
intros.
do 2 destruct ex.
simpl in *.
inv_lb_execution.
unfold occurred in *.
repeat find_reverse_rewrite.
find_copy_apply_lem_hyp timeout_implies_state_exists_after; break_exists_name st'.
find_copy_apply_lem_hyp timeout_implies_state_exists; break_exists_name st.
destruct (succ_list st') eqn:?H.
- congruence.
- eapply get_open_stabilize_request_to_first_succ_from_req_to; eauto.
eapply effective_Tick_sends_request'; eauto.
Qed.
Lemma start_stabilize_with_first_successor_eventually :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
live_node (occ_gst (hd ex)) h ->
eventually (now (fun o => open_stabilize_request_to_first_succ o.(occ_gst) h)) ex.
Proof.
intros.
find_copy_apply_lem_hyp loaded_Tick_inf_often; auto.
inv_prop inf_occurred.
eapply eventually_next.
lift_eventually (effective_Tick_occurred_sent_request h).
invar_eauto.
Qed.
Lemma stabilize_timeout_means_successor_dead :
forall ex h dst,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
now (occurred (Timeout h (Request dst GetPredAndSuccs) DetectFailure)) ex ->
exists s,
addr_of s = dst /\
has_dead_first_succ ex.(hd).(occ_gst) h s.
Proof.
intros.
destruct ex as [o [o' ex]].
simpl in *.
unfold occurred in *.
inv_prop lb_execution.
repeat find_reverse_rewrite.
inv_labeled_step; clean_up_labeled_step_cases.
find_apply_lem_hyp timeout_handler_l_definition; expand_def;
try congruence.
find_apply_lem_hyp timeout_handler_eff_definition; expand_def;
try congruence.
repeat find_rewrite; find_injection.
inv_prop timeout_constraint.
find_eapply_lem_hyp stabilize_only_with_first_succ; eauto; break_exists_exists.
firstorder.
eexists; firstorder eauto.
find_apply_lem_hyp hd_error_tl_exists; break_exists_exists; firstorder.
now find_rewrite.
Qed.
Lemma stabilize_Request_timeout_removes_succ :
forall ex h st s rest dst p,
lb_execution ex ->
sigma ex.(hd).(occ_gst) h = Some st ->
succ_list st = s :: rest ->
open_stabilize_request_to ex.(hd).(occ_gst) h dst ->
now (occurred (Timeout h (Request dst p) DetectFailure)) ex ->
next
(now
(fun occ =>
exists st, sigma occ.(occ_gst) h = Some st /\
succ_list st = rest))
ex.
Proof.
intros.
unfold open_stabilize_request, open_stabilize_request_to in *; break_exists; break_and.
do 2 destruct ex.
match goal with
| [ H : lb_execution _ |- _ ] =>
inv H; simpl in *
end.
unfold occurred in *.
repeat find_reverse_rewrite.
invc_labeled_step; simpl in *.
(* This should be a lemma about timeout_handler_l. *)
assert (h0 = h).
{
find_apply_lem_hyp timeout_handler_l_definition; expand_def.
now find_injection.
}
subst_max.
repeat find_rewrite; simpl.
rewrite update_same.
eexists; split; eauto.
find_injection.
find_apply_lem_hyp timeout_handler_l_definition; expand_def.
repeat find_reverse_rewrite.
find_injection.
inv_prop open_request_to; expand_def.
inv_prop query_request.
simpl in *.
find_apply_lem_hyp request_timeout_handler_definition; expand_def; try congruence.
find_eapply_lem_hyp handle_query_timeout_definition; expand_def; try congruence.
repeat find_rewrite; repeat find_injection.
(* Should use a definition lemma about start_query here. *)
unfold start_query, update_query in *.
simpl in *.
repeat break_match;
try find_apply_lem_hyp succ_list_preserved_by_do_delayed_queries;
simpl in *;
tuple_inversion;
simpl in *;
congruence.
Qed.
Lemma removing_head_decreases_failed_node_count :
forall gst l gst' s rest,
labeled_step_dynamic gst l gst' ->
In (addr_of s) (failed_nodes gst) ->
succ_list_leading_failed_nodes (failed_nodes gst') rest <
succ_list_leading_failed_nodes (failed_nodes gst) (s :: rest).
Proof.
intros.
erewrite <- failed_nodes_eq; eauto.
simpl.
break_if;
[|exfalso];
auto with arith.
Qed.
Lemma stabilize_Request_timeout_decreases_error :
forall ex h dst,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
open_stabilize_request_to ex.(hd).(occ_gst) h dst ->
now (occurred (Timeout h (Request dst GetPredAndSuccs) DetectFailure)) ex ->
consecutive (measure_decreasing (leading_failed_succs h)) ex.
Proof.
intros.
find_copy_eapply_lem_hyp stabilize_timeout_means_successor_dead; eauto.
break_exists_name s; break_and.
inv_prop has_dead_first_succ; expand_def.
destruct ex as [o [o' ex]].
find_copy_eapply_lem_hyp stabilize_Request_timeout_removes_succ; eauto.
simpl in *; break_exists; break_and.
unfold measure_decreasing.
erewrite !leading_failed_succs_st; eauto.
repeat find_rewrite.
inv_prop lb_execution.
eapply removing_head_decreases_failed_node_count; eauto.
Qed.
Lemma ahr_unrelated_channel_unchanged :
forall src h,
h <> src ->
forall dst res tr gst,
channel (apply_handler_result h res tr gst) src dst = channel gst src dst.
Proof.
intros.
unfold apply_handler_result; repeat break_match; subst.
unfold channel.
simpl.
rewrite filterMap_app.
rewrite filterMap_all_None.
auto with datatypes.
intros.
find_apply_lem_hyp in_map_iff; expand_def; simpl.
destruct (addr_eq_dec h src); simpl; congruence.
Qed.
Hint Rewrite ahr_unrelated_channel_unchanged using congruence.
Lemma ahr_related_preserved :
forall h dst res tr gst m,
In m (channel gst h dst) ->
In m (channel (apply_handler_result h res tr gst) h dst).
Proof.
intros.
unfold apply_handler_result; repeat break_match; subst.
unfold channel; simpl.
rewrite filterMap_app.
apply in_or_app; tauto.
Qed.
Hint Resolve ahr_related_preserved.
Lemma update_msgs_channel_preserved :
forall src dst m gst xs ys,
msgs gst = xs ++ m :: ys ->
fst (snd m) <> dst ->
channel (update_msgs gst (xs ++ ys)) src dst = channel gst src dst.
Proof.
intros.
unfold update_msgs, channel; simpl.
repeat find_rewrite.
rewrite !filterMap_app.
f_equal.
simpl.
destruct (addr_eq_dec (fst (snd m)) dst); try congruence.
destruct (addr_eq_dec (fst m) src); simpl; auto.
Qed.
Hint Rewrite update_msgs_channel_preserved using congruence.
Lemma msgs_eq_channel_eq :
forall gst gst',
msgs gst = msgs gst' ->
forall src dst,
channel gst src dst = channel gst' src dst.
Proof.
unfold channel.
congruence.
Qed.
Lemma update_msgs_and_trace_update_msgs :
forall gst ms t,
msgs (update_msgs_and_trace gst ms t) = msgs (update_msgs gst ms).
Proof.
reflexivity.
Qed.
Definition node_local (P : global_state -> addr -> Prop) : Prop :=
forall gst gst' h,
P gst h ->
In h (nodes gst) <-> In h (nodes gst') ->
sigma gst' h = sigma gst h ->
timeouts gst' h = timeouts gst h ->
P gst' h.
Hint Unfold node_local.
Lemma open_request_to_node_local :
forall dst req,
node_local (fun gst h => open_request_to gst h dst req).
Proof.
autounfold; simpl; intros.
inv_prop open_request_to; expand_def.
repeat find_rewrite.
eapply open_request_to_intro; eauto.
congruence.
Qed.
Hint Resolve open_request_to_node_local.
Inductive lbl_loc : label -> addr -> Prop :=
| RecvAt :
forall src dst p,
lbl_loc (RecvMsg src dst p) dst
| TimeoutAt :
forall h t eff,
lbl_loc (Timeout h t eff) h.
Hint Constructors lbl_loc.
Lemma input_not_lbl_loc :
forall h src dst m,
~ lbl_loc (Input src dst m) h.
Proof.
unfold not.
intros.
inv_prop lbl_loc.
Qed.
Hint Resolve input_not_lbl_loc.
Lemma output_not_lbl_loc :
forall h src dst m,
~ lbl_loc (Output src dst m) h.
Proof.
unfold not.
intros.
inv_prop lbl_loc.
Qed.
Hint Resolve output_not_lbl_loc.
Lemma recv_elsewhere_not_lbl_loc :
forall h src dst m,
h <> dst ->
~ lbl_loc (RecvMsg src dst m) h.
Proof.
intros; intro.
inv_prop lbl_loc.
congruence.
Qed.
Hint Resolve recv_elsewhere_not_lbl_loc.
Lemma timeout_elsewhere_not_lbl_loc :
forall h h' t eff,
h <> h' ->
~ lbl_loc (Timeout h' t eff) h.
Proof.
intros; intro.
inv_prop lbl_loc.
congruence.
Qed.
Hint Resolve timeout_elsewhere_not_lbl_loc.
Lemma ahr_nodes :
forall h r tr gst,
nodes (apply_handler_result h r tr gst) = nodes gst.
Proof.
unfold apply_handler_result.
intros.
repeat break_match; reflexivity.
Qed.
Hint Rewrite ahr_nodes.
Lemma node_local_preserved :
forall P gst l gst' h,
node_local P ->
P gst h ->
labeled_step_dynamic gst l gst' ->
~ lbl_loc l h ->
P gst' h.
Proof.
intros.
inv_labeled_step.
- destruct (addr_eq_dec h0 h); subst.
+ exfalso.
repeat (handler_def; auto).
+ find_eapply_prop node_local; eauto; simpl; try tauto; repeat handler_simpl.
- destruct (addr_eq_dec (fst (snd m)) h); subst.
+ unfold recv_handler_l in *.
find_injection.
exfalso; auto.
+ find_eapply_prop node_local; eauto; simpl; try tauto; repeat handler_simpl.
- find_eapply_prop node_local; eauto; simpl; tauto.
- find_eapply_prop node_local; eauto; simpl; tauto.
Qed.
Lemma open_request_to_dead_node_stays_or_timeout :
forall gst l gst',
reachable_st gst ->
labeled_step_dynamic gst l gst' ->
forall h dst req,
open_request_to gst h dst req ->
In req (channel gst h dst) ->
In dst (nodes gst) ->
In dst (failed_nodes gst) ->
open_request_to gst' h dst req /\
In req (channel gst' h dst) /\
l <> Timeout h (Request dst req) DetectFailure \/
l = Timeout h (Request dst req) DetectFailure.
Proof.
intros.
inv_prop open_request_to.
break_exists_name q.
break_exists_name st.
break_exists_name dstp.
break_and; subst.
pose proof (open_request_to_node_local (addr_of dstp) req) as Hnl.
pose proof (node_local_preserved _ gst l gst' h Hnl ltac:(auto) ltac:(auto)).
simpl in *.
assert (cur_request_timeouts_ok' (cur_request st) (timeouts gst h))
by eauto using only_nodes_have_state.
repeat find_rewrite.
inv_labeled_step.
- destruct (addr_eq_dec h0 h); subst.
+ destruct t;
match goal with
| |- context[Request _ _ :: _] => idtac
| |- _ =>
left; repeat split;
solve
[ repeat (handler_def || congruence);
eapply open_request_to_intro; eauto; simpl; rewrite_update;
eauto using in_cons, remove_preserve; congruence
| apply in_msgs_in_channel; simpl; eauto with datatypes
| eauto ]
end.
handler_def; try congruence.
handler_def; try congruence.
handler_def; try congruence.
* find_injection.
right.
f_equal.
eapply at_most_one_request_timeout'_uniqueness; try eassumption.
now inv_prop cur_request_timeouts_ok'.
* repeat (find_rewrite; repeat find_injection).
inv_prop cur_request_timeouts_ok'.
match goal with
| H: In (Request ?a ?b) (timeouts gst h),
H': In (Request ?a' ?b') (timeouts gst h) |- _ =>
assert (Request a b = Request a' b')
by eauto using at_most_one_request_timeout'_uniqueness
end.
congruence.
+ left.
repeat (split; try solve [handler_def; eauto | autorewrite with core; eauto]).
- destruct (addr_eq_dec (fst (snd m)) h); subst.
+ left; split.
* unfold recv_handler_l in *; find_injection.
assert (wf_ptr dstp).
{
cut (valid_ptr gst dstp); [unfold valid_ptr; tauto|].
repeat find_rewrite.
find_injection.
eapply cur_request_valid; invar_eauto.
}
find_eapply_lem_hyp constrained_Request_not_cleared_by_recv_handler; eauto.
-- match goal with
| |- open_request_to ?gst' ?src ?dst ?req =>
assert (In (Request dst req) (timeouts gst' src))
by (simpl; rewrite_update; break_or_hyp; in_crush;
eauto using in_remove_all_preserve);
assert (cur_request_timeouts_ok' (cur_request st0) (timeouts gst' src))
end.
{
apply cur_request_timeouts_ok'_complete.
eapply cur_request_timeouts_related_invariant_elim; invar_eauto.
simpl; now rewrite_update.
}
repeat find_rewrite.
inv_prop cur_request_timeouts_ok';
try solve [exfalso; find_eapply_prop Request; eauto].
match goal with
| H: In (Request ?a ?b) (timeouts ?gst ?h),
H': In (Request ?a' ?b') (timeouts ?gst ?h) |- _ =>
assert (Request a b = Request a' b')
by eauto using at_most_one_request_timeout'_uniqueness
end.
repeat find_injection.
eapply open_request_to_intro; eauto.
++ simpl; rewrite_update; eauto.
++ assert (wf_ptr dstp0).
{
cut (exists gst, valid_ptr gst dstp0);
[unfold valid_ptr in *; firstorder|].
eexists; eapply cur_request_valid;
[|eapply apply_handler_result_updates_sigma; eauto|eauto].
invar_eauto.
}
rewrite (wf_ptr_eq dstp); eauto.
repeat find_rewrite.
rewrite <- (wf_ptr_eq dstp0); auto.
-- constructor; eauto.
intros.
assert (exists st, sigma gst (addr_of dstp) = Some st) by auto.
break_exists_name st__dst.
intro Hin. apply in_msgs_in_channel in Hin.
find_eapply_lem_hyp (query_message_ok'_invariant gst ltac:(auto) (fst (snd m)) (addr_of dstp)); eauto.
invcs_prop query_message_ok'.
++ tauto.
++ repeat find_rewrite; eapply_prop no_requests; eauto.
++ eapply_prop no_responses; eauto.
++ inv_option_map; congruence.
++ inv_option_map; congruence.
-- destruct m as [? [? ?]]; simpl in *.
repeat find_rewrite; in_crush.
* split.
-- apply ahr_related_preserved.
erewrite update_msgs_channel_preserved; eauto.
-- unfold recv_handler_l in *; find_injection; auto.
+ unfold recv_handler_l in *; find_injection.
left; repeat (split; eauto).
autorewrite with core.
erewrite update_msgs_channel_preserved; eauto.
- left; repeat (split; eauto).
apply in_msgs_in_channel.
simpl; auto.
- left; repeat (split; eauto).
autorewrite with core.
erewrite msgs_eq_channel_eq; try apply update_msgs_and_trace_update_msgs.
erewrite update_msgs_channel_preserved; eauto.
intro; repeat find_rewrite.
eapply nodes_not_clients; eauto.
Qed.
Lemma open_stabilize_request_stays_or_timeout :
forall gst l gst',
reachable_st gst ->
labeled_step_dynamic gst l gst' ->
forall h dst,
open_stabilize_request_to gst h dst ->
In dst (nodes gst) ->
In dst (failed_nodes gst) ->
open_stabilize_request_to gst' h dst /\
l <> Timeout h (Request dst GetPredAndSuccs) DetectFailure \/
l = Timeout h (Request dst GetPredAndSuccs) DetectFailure.
Proof.
intros.
inv_prop open_stabilize_request_to.
find_eapply_lem_hyp open_request_to_dead_node_stays_or_timeout; eauto.
firstorder.
Qed.
Lemma open_stabilize_request_until_timeout :
forall ex h dst,
lb_execution ex ->
reachable_st (occ_gst (hd ex)) ->
open_stabilize_request_to ex.(hd).(occ_gst) h dst ->
In dst (failed_nodes (occ_gst (hd ex))) ->
In dst (nodes (occ_gst (hd ex))) ->
weak_until (now (fun occ => open_stabilize_request_to (occ_gst occ) h dst) /\_
~_ now (occurred (Timeout h (Request dst GetPredAndSuccs) DetectFailure)))
(now (fun occ => open_stabilize_request_to (occ_gst occ) h dst) /\_
now (occurred (Timeout h (Request dst GetPredAndSuccs) DetectFailure)))
ex.
Proof.
cofix c.
intros.
destruct ex as [o [o' [o'' ex]]].
inv_prop lb_execution.
find_copy_eapply_lem_hyp open_stabilize_request_stays_or_timeout;
try solve [clear c; eauto].
expand_def.
- apply W_tl.
+ split; simpl;
try intro; auto.
+ eapply c; invar_eauto;
eauto using failed_nodes_never_removed, nodes_never_removed.
- apply W0.
split; eauto.
unfold occurred; simpl; auto.
Qed.
Lemma open_stabilize_request_eventually_decreases_error :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
live_node (occ_gst (hd ex)) h ->
leading_failed_succs h (occ_gst (hd ex)) > 0 ->
open_stabilize_request_to_first_succ (occ_gst (hd ex)) h ->
forall dst,
has_dead_first_succ (occ_gst (hd ex)) h dst ->
channel (occ_gst (hd ex)) (addr_of dst) h = [] ->
eventually (consecutive (measure_decreasing (leading_failed_succs h))) ex.
Proof.
intros.
find_copy_apply_lem_hyp leading_failed_succs_nonzero_means_dead_succ; expand_def.
unfold open_stabilize_request_to_first_succ in *.
invc_prop has_dead_first_succ; expand_def.
inv_prop has_dead_first_succ; expand_def.
find_copy_apply_hyp_hyp.
inv_prop open_stabilize_request_to.
find_copy_eapply_lem_hyp open_stabilize_request_until_timeout;
eauto using in_failed_in_nodes.
find_copy_apply_lem_hyp request_eventually_fires;
eauto using strong_local_fairness_weak.
find_copy_apply_lem_hyp eventually_weak_until_cumul; eauto.
find_copy_apply_lem_hyp reachable_st_always; auto.
- eapply eventually_monotonic; [| | eauto | eauto]; intros.
+ invar_eauto.
+ invc_prop always.
unfold and_tl in *; break_and.
invcs_prop weak_until;
destruct s;
eapply stabilize_Request_timeout_decreases_error; eauto.
- eapply weak_until_latch_eventually; eauto.
Qed.
Lemma nonzero_phase_one_error_eventually_drops_dead_quiet :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
always (now no_msgs_to_live_from_dead_nodes) ex ->
live_node (occ_gst (hd ex)) h ->
leading_failed_succs h (occ_gst (hd ex)) > 0 ->
eventually (consecutive (measure_decreasing (leading_failed_succs h))) ex.
Proof.
intros.
find_copy_eapply_lem_hyp start_stabilize_with_first_successor_eventually; eauto.
induction 0 as [ex|o ex].
- find_copy_apply_lem_hyp leading_failed_succs_nonzero_means_dead_succ; expand_def.
destruct ex.
eapply open_stabilize_request_eventually_decreases_error; simpl in *; eauto.
inv_prop has_dead_first_succ; expand_def.
inv_prop no_msgs_to_live_from_dead_nodes; simpl in *.
eapply no_msgs_from_dead_nodes_elim; eauto.
- destruct ex as [o' ex].
destruct (leading_failed_succs h (occ_gst o')) eqn:?H.
+ apply E0.
simpl in *.
unfold measure_decreasing.
omega.
+ apply E_next.
apply IHeventually; invar_eauto.
simpl in *; omega.
Qed.
Lemma nonzero_phase_one_error_eventually_drops :
forall ex h,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
live_node (occ_gst (hd ex)) h ->
leading_failed_succs h (occ_gst (hd ex)) > 0 ->
eventually (consecutive (measure_decreasing (leading_failed_succs h))) ex.
Proof.
intros.
find_copy_eapply_lem_hyp dead_nodes_go_quiet;
eauto using strong_local_fairness_weak.
induction 0 as [ex | o [o' ex]].
- eauto using nonzero_phase_one_error_eventually_drops_dead_quiet.
- destruct (leading_failed_succs h (occ_gst o')) eqn:?H.
+ apply E0; simpl in *.
unfold measure_decreasing; omega.
+ apply E_next.
apply IHeventually; invar_eauto.
simpl in *; omega.
Qed.
Lemma nonempty_succ_list_implies_joined :
forall gst h st s rest,
reachable_st gst ->
sigma gst h = Some st ->
succ_list st = s :: rest ->
joined st = true.
Proof.
intros.
destruct (joined st) eqn:?H;
[|find_apply_lem_hyp nodes_not_joined_have_no_successors; auto];
congruence.
Qed.
Lemma has_dead_first_succ_implies_error_nonzero :
forall gst h s,
has_dead_first_succ gst h s ->
leading_failed_succs h gst > 0.
Proof.
unfold has_dead_first_succ.
intros.
expand_def.
unfold leading_failed_succs, succ_list_leading_failed_nodes.
repeat find_rewrite.
break_if; [|exfalso];
auto with arith.
Qed.
Theorem phase_one_nonzero_error_causes_measure_drop :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
always (nonzero_error_causes_measure_drop leading_failed_succs) ex.
Proof.
cofix c.
intros.
destruct ex.
constructor.
- intro.
find_copy_apply_lem_hyp phase_one_error_nonzero_means_dead_succ.
break_exists_exists; expand_def.
split; auto using in_nodes_not_failed_in_active.
inv_prop has_dead_first_succ; expand_def.
eapply nonzero_phase_one_error_eventually_drops; eauto.
+ find_eapply_lem_hyp nonempty_succ_list_implies_joined;
eauto using live_node_characterization.
+ eauto using has_dead_first_succ_intro, has_dead_first_succ_implies_error_nonzero.
- apply c; invar_eauto.
Qed.
Theorem phase_one_error_continuously_nonincreasing :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
continuously (local_measures_nonincreasing leading_failed_succs) ex.
Proof.
(*
This needs to be reduced to an invariant proof showing that:
if the predecessor of h is p,
and it changes to p' in one step,
then either p is dead
or between p p' h.
DIFFICULTY: Ryan
USED: In phase one.
*)
Admitted.
Theorem phase_one_continuously :
forall ex,
lb_execution ex ->
reachable_st (occ_gst (infseq.hd ex)) ->
strong_local_fairness ex ->
always (~_ (now circular_wait)) ex ->
continuously (now phase_one) ex.
Proof.
intros.
eapply continuously_zero_total_leading_failed_nodes_implies_phase_one; eauto.
eapply local_measure_causes_measure_zero_continuosly; eauto.
- eapply phase_one_error_continuously_nonincreasing; eauto.
- eauto using always_continuously, phase_one_nonzero_error_causes_measure_drop.
Qed.
Print Assumptions phase_one_continuously.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg toggle;
integer cyc; initial cyc=1;
Test suba (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subb (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
Test subc (/*AUTOINST*/
// Inputs
.clk (clk),
.toggle (toggle),
.cyc (cyc[31:0]));
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
toggle <= !cyc[0];
if (cyc==9) begin
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module Test
(
input clk,
input toggle,
input [31:0] cyc
);
// Don't flatten out these modules please:
// verilator no_inline_module
// Labeled cover
cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_2_V
`define SKY130_FD_SC_MS__A2111OI_2_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__a2111oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2111oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__a2111oi_2 (
Y ,
A1,
A2,
B1,
C1,
D1
);
output Y ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__a2111oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_2_V
|
/**
* bsg_mem_1rw_sync_mask_write_bit_banked.v
*
* This module has the same interface/functionality as
* bsg_mem_1rw_sync_mask_write_bit.
*
* This module can be used for breaking a big SRAM block into
* smaller blocks. This might be useful, if the SRAM generator does not
* support sizes of SRAM that are too wide or too deep.
* It is also useful for power and delay perspective, since only one depth
* bank is activated while reading or writing.
*
*
* - width_p : width of the total memory
* - els_p : depth of the total memory
*
* - num_width_bank_p : Number of banks for the memory's width. width_p has
* to be a multiple of this number.
* - num_depth_bank_p : Number of banks for the memory's depth. els_p has to
* be a multiple of this number.
*
*
*/
`include "bsg_defines.v"
module bsg_mem_1rw_sync_mask_write_bit_banked
#(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter latch_last_read_p=0
// bank parameters
, parameter num_width_bank_p=1
, parameter num_depth_bank_p=1
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter bank_depth_lp=(els_p/num_depth_bank_p)
, parameter bank_addr_width_lp=`BSG_SAFE_CLOG2(bank_depth_lp)
, parameter depth_bank_idx_width_lp=`BSG_SAFE_CLOG2(num_depth_bank_p)
, parameter bank_width_lp=(width_p/num_width_bank_p)
)
(
input clk_i
, input reset_i
, input v_i
, input w_i
, input [addr_width_lp-1:0] addr_i
, input [width_p-1:0] data_i
, input [width_p-1:0] w_mask_i
, output [width_p-1:0] data_o
);
if (num_depth_bank_p==1) begin: db1
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(v_i)
,.w_i(w_i)
,.addr_i(addr_i)
,.data_i(data_i[bank_width_lp*i+:bank_width_lp])
,.w_mask_i(w_mask_i[bank_width_lp*i+:bank_width_lp])
,.data_o(data_o[bank_width_lp*i+:bank_width_lp])
);
end
end
else begin: dbn
wire [depth_bank_idx_width_lp-1:0] depth_bank_idx_li = addr_i[0+:depth_bank_idx_width_lp];
wire [bank_addr_width_lp-1:0] bank_addr_li = addr_i[depth_bank_idx_width_lp+:bank_addr_width_lp];
logic [num_depth_bank_p-1:0] bank_v_li;
logic [num_depth_bank_p-1:0][width_p-1:0] bank_data_lo;
bsg_decode_with_v #(
.num_out_p(num_depth_bank_p)
) demux_v (
.i(depth_bank_idx_li)
,.v_i(v_i)
,.o(bank_v_li)
);
for (genvar i = 0; i < num_width_bank_p; i++) begin: wb
for (genvar j = 0; j < num_depth_bank_p; j++) begin: db
bsg_mem_1rw_sync_mask_write_bit #(
.width_p(bank_width_lp)
,.els_p(bank_depth_lp)
,.latch_last_read_p(latch_last_read_p)
) bank (
.clk_i(clk_i)
,.reset_i(reset_i)
,.v_i(bank_v_li[j])
,.w_i(w_i)
,.addr_i(bank_addr_li)
,.data_i(data_i[i*bank_width_lp+:bank_width_lp])
,.w_mask_i(w_mask_i[i*bank_width_lp+:bank_width_lp])
,.data_o(bank_data_lo[j][i*bank_width_lp+:bank_width_lp])
);
end
end
logic [depth_bank_idx_width_lp-1:0] depth_bank_idx_r;
bsg_dff_en #(
.width_p(depth_bank_idx_width_lp)
) depth_bank_idx_dff (
.clk_i(clk_i)
,.en_i(v_i & ~w_i)
,.data_i(depth_bank_idx_li)
,.data_o(depth_bank_idx_r)
);
bsg_mux #(
.els_p(num_depth_bank_p)
,.width_p(width_p)
) data_out_mux (
.data_i(bank_data_lo)
,.sel_i(depth_bank_idx_r)
,.data_o(data_o)
);
end
// synopsys translate_off
initial begin
assert(els_p % num_depth_bank_p == 0)
else $error("[BSG_ERROR] num_depth_bank_p does not divide even with els_p. %m");
assert(width_p % num_width_bank_p == 0)
else $error("[BSG_ERROR] num_width_bank_p does not divide even with width_p. %m");
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit_banked)
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:03:44 05/12/2015
// Design Name: organisation
// Module Name: /media/BELGELER/Workspaces/Xilinx/processor/test_organisation.v
// Project Name: processor
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: organisation
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_organisation;
// Inputs
reg clock;
reg [2:0] reg_read_adr1;
reg [2:0] reg_read_adr2;
reg [2:0] reg_write_adr;
reg reg_write;
reg flush_e;
reg [1:0] forward1;
reg [1:0] forward2;
reg [7:0] ALU_con;
reg ALU_source2;
reg [15:0] offset;
reg mem_write;
reg mem_to_reg;
reg [15:0] processor_input;
// Outputs
wire N;
wire Z;
wire C;
wire V;
wire [15:0] processor_output;
// Instantiate the Unit Under Test (UUT)
organisation uut (
.clock(clock),
.reg_read_adr1(reg_read_adr1),
.reg_read_adr2(reg_read_adr2),
.reg_write_adr(reg_write_adr),
.reg_write(reg_write),
.flush_e(flush_e),
.forward1(forward1),
.forward2(forward2),
.ALU_con(ALU_con),
.ALU_source2(ALU_source2),
.offset(offset),
.mem_write(mem_write),
.mem_to_reg(mem_to_reg),
.processor_input(processor_input),
.N(N),
.Z(Z),
.C(C),
.V(V),
.processor_output(processor_output)
);
initial begin
// Initialize Inputs
clock = 0;
reg_read_adr1 = 0;
reg_read_adr2 = 0;
reg_write_adr = 0;
reg_write = 0;
flush_e = 0;
reg_write = 0;
forward1 = 0;
forward2 = 0;
ALU_con = 0;
ALU_source2 = 0;
offset = 0;
mem_write = 0;
mem_to_reg = 0;
processor_input = 0;
// Wait 100 ns for global reset to finish
// #100;
#2;
offset = 16'h0003;
ALU_source2 = 1;
ALU_con = 8'haf;
#2;
offset = 0;
ALU_source2 = 0;
ALU_con = 0;
forward1 = 1;
forward2 = 1;
#2;
forward1 = 0;
forward2 = 0;
reg_write = 1;
#2;
reg_write = 0;
end
always #1 clock = !clock;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2111OI_FUNCTIONAL_PP_V |
// -*- Mode: Verilog -*-
// Filename : equation_sum.v
// Description : Equation Sum
// Author : Philip Tracton
// Created On : Wed Jan 13 16:03:27 2016
// Last Modified By: Philip Tracton
// Last Modified On: Wed Jan 13 16:03:27 2016
// Update Count : 0
// Status : Unknown, Use with caution!
module equation_sum (/*AUTOARG*/
// Outputs
wb_adr_o, wb_dat_o, wb_sel_o, wb_we_o, wb_cyc_o, wb_stb_o,
wb_cti_o, wb_bte_o, equation_done,
// Inputs
wb_clk, wb_rst, wb_dat_i, wb_ack_i, wb_err_i, wb_rty_i,
base_address, equation_enable
) ;
parameter dw = 32;
parameter aw = 32;
parameter DEBUG = 0;
input wb_clk;
input wb_rst;
output wire [aw-1:0] wb_adr_o;
output wire [dw-1:0] wb_dat_o;
output wire [3:0] wb_sel_o;
output wire wb_we_o;
output wire wb_cyc_o;
output wire wb_stb_o;
output wire [2:0] wb_cti_o;
output wire [1:0] wb_bte_o;
input [dw-1:0] wb_dat_i;
input wb_ack_i;
input wb_err_i;
input wb_rty_i;
input [aw-1:0] base_address;
input equation_enable;
output equation_done;
assign wb_adr_o = 0 & {aw{equation_enable}};
assign wb_dat_o = 0 & {dw{equation_enable}};
assign wb_sel_o = 0 & equation_enable;
assign wb_we_o = 0 & equation_enable;
assign wb_cyc_o = 0 & equation_enable;
assign wb_stb_o = 0 & equation_enable;
assign wb_cti_o = 0 & equation_enable;
assign wb_bte_o = 0 & equation_enable;
assign equation_done = 0;
endmodule // equation_sum
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_l_pp_pg/sky130_fd_sc_hd__udp_pwrgood_l_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X ,
A ,
LOWLVPWR,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input LOWLVPWR;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire pwrgood0_out_A;
wire buf0_out_X ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood0 (pwrgood0_out_A, A, LOWLVPWR, VGND );
buf buf0 (buf0_out_X , pwrgood0_out_A );
sky130_fd_sc_hd__udp_pwrgood$l_pp$PG pwrgood1 (X , buf0_out_X, VPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_PP_V |
// Arbitrer aggregates the traffict from one core data to have a single
// interface.
//
// WHen a request comes to the L2, the arbitrer broadcast the message to all
// the TLBs, or when it goes to the cache it sends it only to the approviate
// cache looking at the address.
//
// For each core, there are two aggregators. One for TLBs and another for
// dcaches
`include "scmem.vh"
`define ARBL2TLB_PASSTHROUGH
module arbl2tlb(
/* verilator lint_off UNUSED */
/* verilator lint_off UNDRIVEN */
input clk
,input reset
// L2D_0 DATA
,input logic l2d_0todr_req_valid
,output logic l2d_0todr_req_retry
,input I_l2todr_req_type l2d_0todr_req
,output logic drtol2d_0_snack_valid
,input logic drtol2d_0_snack_retry
,output I_drtol2_snack_type drtol2d_0_snack
,input l2d_0todr_snoop_ack_valid
,output l2d_0todr_snoop_ack_retry
,input I_l2snoop_ack_type l2d_0todr_snoop_ack
,input logic l2d_0todr_disp_valid
,output logic l2d_0todr_disp_retry
,input I_l2todr_disp_type l2d_0todr_disp
,output logic drtol2d_0_dack_valid
,input logic drtol2d_0_dack_retry
,output I_drtol2_dack_type drtol2d_0_dack
// L2D_1
,input logic l2d_1todr_req_valid
,output logic l2d_1todr_req_retry
,input I_l2todr_req_type l2d_1todr_req
,output logic drtol2d_1_snack_valid
,input logic drtol2d_1_snack_retry
,output I_drtol2_snack_type drtol2d_1_snack
,input l2d_1todr_snoop_ack_valid
,output l2d_1todr_snoop_ack_retry
,input I_l2snoop_ack_type l2d_1todr_snoop_ack
,input logic l2d_1todr_disp_valid
,output logic l2d_1todr_disp_retry
,input I_l2todr_disp_type l2d_1todr_disp
,output logic drtol2d_1_dack_valid
,input logic drtol2d_1_dack_retry
,output I_drtol2_dack_type drtol2d_1_dack
`ifdef SC_4PIPE
// l2d_2 DATA
,input logic l2d_2todr_req_valid
,output logic l2d_2todr_req_retry
,input I_l2todr_req_type l2d_2todr_req
,output logic drtol2d_2_snack_valid
,input logic drtol2d_2_snack_retry
,output I_drtol2_snack_type drtol2d_2_snack
,input l2d_2todr_snoop_ack_valid
,output l2d_2todr_snoop_ack_retry
,input I_l2snoop_ack_type l2d_2todr_snoop_ack
,input logic l2d_2todr_disp_valid
,output logic l2d_2todr_disp_retry
,input I_l2todr_disp_type l2d_2todr_disp
,output logic drtol2d_2_dack_valid
,input logic drtol2d_2_dack_retry
,output I_drtol2_dack_type drtol2d_2_dack
// l2d_3 DATA
,input logic l2d_3todr_req_valid
,output logic l2d_3todr_req_retry
,input I_l2todr_req_type l2d_3todr_req
,output logic drtol2d_3_snack_valid
,input logic drtol2d_3_snack_retry
,output I_drtol2_snack_type drtol2d_3_snack
,input l2d_3todr_snoop_ack_valid
,output l2d_3todr_snoop_ack_retry
,input I_l2snoop_ack_type l2d_3todr_snoop_ack
,input logic l2d_3todr_disp_valid
,output logic l2d_3todr_disp_retry
,input I_l2todr_disp_type l2d_3todr_disp
,output logic drtol2d_3_dack_valid
,input logic drtol2d_3_dack_retry
,output I_drtol2_dack_type drtol2d_3_dack
`endif
// directory aggregator
,output l2todr_req_valid
,input l2todr_req_retry
,output I_l2todr_req_type l2todr_req
,input drtol2_snack_valid
,output drtol2_snack_retry
,input I_drtol2_snack_type drtol2_snack
,output l2todr_disp_valid
,input l2todr_disp_retry
,output I_l2todr_disp_type l2todr_disp
,input drtol2_dack_valid
,output drtol2_dack_retry
,input I_drtol2_dack_type drtol2_dack
,output l2todr_snoop_ack_valid
,input l2todr_snoop_ack_retry
,output I_drsnoop_ack_type l2todr_snoop_ack
/* verilator lint_on UNUSED */
/* verilator lint_on UNDRIVEN */
);
`ifdef ARBL2TLB_PASSTHROUGH
I_l2todr_req_type l2todr_req_next;
logic l2todr_req_valid_next, l2todr_req_retry_next;
always_comb begin
if(l2d_0todr_req_valid) begin
l2todr_req_next = l2d_0todr_req;
l2todr_req_next.nid[4:3] = 2'b00;
l2todr_req_valid_next = l2d_0todr_req_valid;
l2d_0todr_req_retry = l2todr_req_retry_next;
l2d_1todr_req_retry = l2d_1todr_req_valid;
`ifdef SC_4PIPE
l2d_2todr_req_retry = l2d_2todr_req_valid;
l2d_3todr_req_retry = l2d_3todr_req_valid;
`endif
end else if (l2d_1todr_req_valid) begin
l2todr_req_next = l2d_1todr_req;
l2todr_req_next.nid[4:3] = 2'b01;
l2todr_req_valid_next = l2d_1todr_req_valid;
l2d_0todr_req_retry = 1'b0;
l2d_1todr_req_retry = l2todr_req_retry_next;
`ifdef SC_4PIPE
l2d_2todr_req_retry = l2d_2todr_req_valid;
l2d_3todr_req_retry = l2d_3todr_req_valid;
end else if (l2d_2todr_req_valid) begin
l2todr_req_next = l2d_2todr_req;
l2todr_req_next.nid[4:3] = 2'b10;
l2todr_req_valid_next = l2d_2todr_req_valid;
l2d_0todr_req_retry = 1'b0;
l2d_1todr_req_retry = 1'b0;
l2d_2todr_req_retry = l2todr_req_retry_next;
l2d_3todr_req_retry = l2d_3todr_req_valid;
end else if (l2d_3todr_req_valid) begin
l2todr_req_next = l2d_3todr_req;
l2todr_req_next.nid[4:3] = 2'b11;
l2todr_req_valid_next = l2d_3todr_req_valid;
l2d_0todr_req_retry = 1'b0;
l2d_1todr_req_retry = 1'b0;
l2d_2todr_req_retry = 1'b0;
l2d_3todr_req_retry = l2todr_req_retry_next;
`endif
end else begin
l2todr_req_valid_next = 1'b0;
l2d_0todr_req_retry = 1'b0;
l2d_1todr_req_retry = 1'b0;
l2d_2todr_req_retry = 1'b0;
l2d_3todr_req_retry = 1'b0;
end
end
fflop #(.Size($bits(I_l2todr_req_type))) l2todr_req_ff(
.clk(clk)
,.reset(reset)
,.dinValid(l2todr_req_valid_next)
,.dinRetry(l2todr_req_retry_next)
,.din(l2todr_req_next)
,.qValid(l2todr_req_valid)
,.qRetry(l2todr_req_retry)
,.q(l2todr_req)
);
I_drtol2_snack_type drtol2d_0_snack_next, drtol2d_1_snack_next;
logic drtol2d_0_snack_retry_next, drtol2d_0_snack_valid_next;
logic drtol2d_1_snack_retry_next, drtol2d_1_snack_valid_next;
`ifdef SC_4PIPE
I_drtol2_snack_type drtol2d_2_snack_next, drtol2d_3_snack_next;
logic drtol2d_2_snack_retry_next, drtol2d_2_snack_valid_next;
logic drtol2d_3_snack_retry_next, drtol2d_3_snack_valid_next;
`endif
always_comb begin
if (drtol2_snack_valid) begin
if(drtol2_snack.nid[4:3] == 2'b00) begin
drtol2d_0_snack_valid_next = drtol2_snack_valid;
drtol2_snack_retry = drtol2d_0_snack_retry_next;
drtol2d_0_snack_next = drtol2_snack;
drtol2d_1_snack_valid_next = 1'b0;
`ifdef SC_4PIPE
drtol2d_2_snack_valid_next = 1'b0;
drtol2d_3_snack_valid_next = 1'b0;
`endif
end else if (drtol2_snack.nid[4:3] == 2'b01) begin
drtol2d_1_snack_valid_next = drtol2_snack_valid;
drtol2_snack_retry = drtol2d_1_snack_retry_next;
drtol2d_1_snack_next = drtol2_snack;
drtol2d_1_snack_valid_next = 1'b0;
`ifdef SC_4PIPE
drtol2d_2_snack_valid_next = 1'b0;
drtol2d_3_snack_valid_next = 1'b0;
end else if (drtol2_snack.nid[4:3] == 2'b10) begin
drtol2d_2_snack_valid_next = drtol2_snack_valid;
drtol2_snack_retry = drtol2d_2_snack_retry_next;
drtol2d_2_snack_next = drtol2_snack;
drtol2d_0_snack_valid_next = 1'b0;
drtol2d_1_snack_valid_next = 1'b0;
drtol2d_3_snack_valid_next = 1'b0;
end else if (drtol2_snack.nid[4:3] == 2'b11) begin
drtol2d_3_snack_valid_next = drtol2_snack_valid;
drtol2_snack_retry = drtol2d_3_snack_retry_next;
drtol2d_3_snack_next = drtol2_snack;
drtol2d_0_snack_valid_next = 1'b0;
drtol2d_1_snack_valid_next = 1'b0;
drtol2d_2_snack_valid_next = 1'b0;
`endif
end else begin
drtol2d_0_snack_valid_next = 1'b0;
drtol2d_1_snack_valid_next = 1'b0;
`ifdef SC_4PIPE
drtol2d_2_snack_valid_next = 1'b0;
drtol2d_3_snack_valid_next = 1'b0;
`endif
drtol2_snack_retry = 1'b0;
end
end else begin
drtol2d_0_snack_valid_next = 1'b0;
drtol2d_1_snack_valid_next = 1'b0;
`ifdef SC_4PIPE
drtol2d_2_snack_valid_next = 1'b0;
drtol2d_3_snack_valid_next = 1'b0;
`endif
drtol2_snack_retry = 1'b0;
end
end
fflop #(.Size($bits(I_drtol2_snack_type))) drtol2_0_snack_ff(
.clk(clk)
,.reset(reset)
,.dinValid(drtol2d_0_snack_valid_next)
,.dinRetry(drtol2d_0_snack_retry_next)
,.din(drtol2d_0_snack_next)
,.qValid(drtol2d_0_snack_valid)
,.qRetry(drtol2d_0_snack_retry)
,.q(drtol2d_0_snack)
);
fflop #(.Size($bits(I_drtol2_snack_type))) drtol2_1_snack_ff(
.clk(clk)
,.reset(reset)
,.dinValid(drtol2d_1_snack_valid_next)
,.dinRetry(drtol2d_1_snack_retry_next)
,.din(drtol2d_1_snack_next)
,.qValid(drtol2d_1_snack_valid)
,.qRetry(drtol2d_1_snack_retry)
,.q(drtol2d_1_snack)
);
`ifdef SC_4PIPE
fflop #(.Size($bits(I_drtol2_snack_type))) drtol2_2_snack_ff(
.clk(clk)
,.reset(reset)
,.dinValid(drtol2d_2_snack_valid_next)
,.dinRetry(drtol2d_2_snack_retry_next)
,.din(drtol2d_2_snack_next)
,.qValid(drtol2d_2_snack_valid)
,.qRetry(drtol2d_2_snack_retry)
,.q(drtol2d_2_snack)
);
fflop #(.Size($bits(I_drtol2_snack_type))) drtol2_3_snack_ff(
.clk(clk)
,.reset(reset)
,.dinValid(drtol2d_3_snack_valid_next)
,.dinRetry(drtol2d_3_snack_retry_next)
,.din(drtol2d_3_snack_next)
,.qValid(drtol2d_3_snack_valid)
,.qRetry(drtol2d_3_snack_retry)
,.q(drtol2d_3_snack)
);
`endif
`endif
endmodule
|
// megafunction wizard: %Arria V Hard IP for PCI Express v14.0%
// GENERATION: XML
// pcie_c5_4x.v
// Generated using ACDS version 14.0 209 at 2014.10.14.19:00:11
`timescale 1 ps / 1 ps
module pcie_c5_4x (
input wire npor, // npor.npor
input wire pin_perst, // .pin_perst
input wire [31:0] test_in, // hip_ctrl.test_in
input wire simu_mode_pipe, // .simu_mode_pipe
input wire pld_clk, // pld_clk.clk
output wire coreclkout, // coreclkout_hip.clk
input wire refclk, // refclk.clk
input wire rx_in0, // hip_serial.rx_in0
input wire rx_in1, // .rx_in1
input wire rx_in2, // .rx_in2
input wire rx_in3, // .rx_in3
output wire tx_out0, // .tx_out0
output wire tx_out1, // .tx_out1
output wire tx_out2, // .tx_out2
output wire tx_out3, // .tx_out3
output wire rx_st_valid, // rx_st.valid
output wire rx_st_sop, // .startofpacket
output wire rx_st_eop, // .endofpacket
input wire rx_st_ready, // .ready
output wire rx_st_err, // .error
output wire [63:0] rx_st_data, // .data
output wire [7:0] rx_st_bar, // rx_bar_be.rx_st_bar
input wire rx_st_mask, // .rx_st_mask
input wire tx_st_valid, // tx_st.valid
input wire tx_st_sop, // .startofpacket
input wire tx_st_eop, // .endofpacket
output wire tx_st_ready, // .ready
input wire tx_st_err, // .error
input wire [63:0] tx_st_data, // .data
output wire tx_fifo_empty, // tx_fifo.fifo_empty
output wire [11:0] tx_cred_datafccp, // tx_cred.tx_cred_datafccp
output wire [11:0] tx_cred_datafcnp, // .tx_cred_datafcnp
output wire [11:0] tx_cred_datafcp, // .tx_cred_datafcp
output wire [5:0] tx_cred_fchipcons, // .tx_cred_fchipcons
output wire [5:0] tx_cred_fcinfinite, // .tx_cred_fcinfinite
output wire [7:0] tx_cred_hdrfccp, // .tx_cred_hdrfccp
output wire [7:0] tx_cred_hdrfcnp, // .tx_cred_hdrfcnp
output wire [7:0] tx_cred_hdrfcp, // .tx_cred_hdrfcp
input wire sim_pipe_pclk_in, // hip_pipe.sim_pipe_pclk_in
output wire [1:0] sim_pipe_rate, // .sim_pipe_rate
output wire [4:0] sim_ltssmstate, // .sim_ltssmstate
output wire [2:0] eidleinfersel0, // .eidleinfersel0
output wire [2:0] eidleinfersel1, // .eidleinfersel1
output wire [2:0] eidleinfersel2, // .eidleinfersel2
output wire [2:0] eidleinfersel3, // .eidleinfersel3
output wire [1:0] powerdown0, // .powerdown0
output wire [1:0] powerdown1, // .powerdown1
output wire [1:0] powerdown2, // .powerdown2
output wire [1:0] powerdown3, // .powerdown3
output wire rxpolarity0, // .rxpolarity0
output wire rxpolarity1, // .rxpolarity1
output wire rxpolarity2, // .rxpolarity2
output wire rxpolarity3, // .rxpolarity3
output wire txcompl0, // .txcompl0
output wire txcompl1, // .txcompl1
output wire txcompl2, // .txcompl2
output wire txcompl3, // .txcompl3
output wire [7:0] txdata0, // .txdata0
output wire [7:0] txdata1, // .txdata1
output wire [7:0] txdata2, // .txdata2
output wire [7:0] txdata3, // .txdata3
output wire txdatak0, // .txdatak0
output wire txdatak1, // .txdatak1
output wire txdatak2, // .txdatak2
output wire txdatak3, // .txdatak3
output wire txdetectrx0, // .txdetectrx0
output wire txdetectrx1, // .txdetectrx1
output wire txdetectrx2, // .txdetectrx2
output wire txdetectrx3, // .txdetectrx3
output wire txelecidle0, // .txelecidle0
output wire txelecidle1, // .txelecidle1
output wire txelecidle2, // .txelecidle2
output wire txelecidle3, // .txelecidle3
output wire txswing0, // .txswing0
output wire txswing1, // .txswing1
output wire txswing2, // .txswing2
output wire txswing3, // .txswing3
output wire [2:0] txmargin0, // .txmargin0
output wire [2:0] txmargin1, // .txmargin1
output wire [2:0] txmargin2, // .txmargin2
output wire [2:0] txmargin3, // .txmargin3
output wire txdeemph0, // .txdeemph0
output wire txdeemph1, // .txdeemph1
output wire txdeemph2, // .txdeemph2
output wire txdeemph3, // .txdeemph3
input wire phystatus0, // .phystatus0
input wire phystatus1, // .phystatus1
input wire phystatus2, // .phystatus2
input wire phystatus3, // .phystatus3
input wire [7:0] rxdata0, // .rxdata0
input wire [7:0] rxdata1, // .rxdata1
input wire [7:0] rxdata2, // .rxdata2
input wire [7:0] rxdata3, // .rxdata3
input wire rxdatak0, // .rxdatak0
input wire rxdatak1, // .rxdatak1
input wire rxdatak2, // .rxdatak2
input wire rxdatak3, // .rxdatak3
input wire rxelecidle0, // .rxelecidle0
input wire rxelecidle1, // .rxelecidle1
input wire rxelecidle2, // .rxelecidle2
input wire rxelecidle3, // .rxelecidle3
input wire [2:0] rxstatus0, // .rxstatus0
input wire [2:0] rxstatus1, // .rxstatus1
input wire [2:0] rxstatus2, // .rxstatus2
input wire [2:0] rxstatus3, // .rxstatus3
input wire rxvalid0, // .rxvalid0
input wire rxvalid1, // .rxvalid1
input wire rxvalid2, // .rxvalid2
input wire rxvalid3, // .rxvalid3
output wire reset_status, // hip_rst.reset_status
output wire serdes_pll_locked, // .serdes_pll_locked
output wire pld_clk_inuse, // .pld_clk_inuse
input wire pld_core_ready, // .pld_core_ready
output wire testin_zero, // .testin_zero
input wire [11:0] lmi_addr, // lmi.lmi_addr
input wire [31:0] lmi_din, // .lmi_din
input wire lmi_rden, // .lmi_rden
input wire lmi_wren, // .lmi_wren
output wire lmi_ack, // .lmi_ack
output wire [31:0] lmi_dout, // .lmi_dout
input wire pm_auxpwr, // power_mngt.pm_auxpwr
input wire [9:0] pm_data, // .pm_data
input wire pme_to_cr, // .pme_to_cr
input wire pm_event, // .pm_event
output wire pme_to_sr, // .pme_to_sr
input wire [349:0] reconfig_to_xcvr, // reconfig_to_xcvr.reconfig_to_xcvr
output wire [229:0] reconfig_from_xcvr, // reconfig_from_xcvr.reconfig_from_xcvr
input wire [4:0] app_msi_num, // int_msi.app_msi_num
input wire app_msi_req, // .app_msi_req
input wire [2:0] app_msi_tc, // .app_msi_tc
output wire app_msi_ack, // .app_msi_ack
input wire app_int_sts_vec, // .app_int_sts
input wire [4:0] tl_hpg_ctrl_er, // config_tl.hpg_ctrler
output wire [31:0] tl_cfg_ctl, // .tl_cfg_ctl
input wire [6:0] cpl_err, // .cpl_err
output wire [3:0] tl_cfg_add, // .tl_cfg_add
output wire tl_cfg_ctl_wr, // .tl_cfg_ctl_wr
output wire tl_cfg_sts_wr, // .tl_cfg_sts_wr
output wire [52:0] tl_cfg_sts, // .tl_cfg_sts
input wire [0:0] cpl_pending, // .cpl_pending
output wire derr_cor_ext_rcv0, // hip_status.derr_cor_ext_rcv
output wire derr_cor_ext_rpl, // .derr_cor_ext_rpl
output wire derr_rpl, // .derr_rpl
output wire dlup_exit, // .dlup_exit
output wire [4:0] dl_ltssm, // .ltssmstate
output wire ev128ns, // .ev128ns
output wire ev1us, // .ev1us
output wire hotrst_exit, // .hotrst_exit
output wire [3:0] int_status, // .int_status
output wire l2_exit, // .l2_exit
output wire [3:0] lane_act, // .lane_act
output wire [7:0] ko_cpl_spc_header, // .ko_cpl_spc_header
output wire [11:0] ko_cpl_spc_data, // .ko_cpl_spc_data
output wire [1:0] dl_current_speed // hip_currentspeed.currentspeed
);
altpcie_av_hip_ast_hwtcl #(
.ACDS_VERSION_HWTCL ("14.0"),
.lane_mask_hwtcl ("x4"),
.gen12_lane_rate_mode_hwtcl ("Gen1 (2.5 Gbps)"),
.pcie_spec_version_hwtcl ("2.1"),
.ast_width_hwtcl ("Avalon-ST 64-bit"),
.pll_refclk_freq_hwtcl ("100 MHz"),
.set_pld_clk_x1_625MHz_hwtcl (0),
.in_cvp_mode_hwtcl (0),
.hip_reconfig_hwtcl (0),
.num_of_func_hwtcl (1),
.use_crc_forwarding_hwtcl (0),
.port_link_number_hwtcl (1),
.slotclkcfg_hwtcl (1),
.enable_slot_register_hwtcl (0),
.porttype_func0_hwtcl ("Native endpoint"),
.bar0_size_mask_0_hwtcl (7),
.bar0_io_space_0_hwtcl ("Disabled"),
.bar0_64bit_mem_space_0_hwtcl ("Enabled"),
.bar0_prefetchable_0_hwtcl ("Enabled"),
.bar1_size_mask_0_hwtcl (0),
.bar1_io_space_0_hwtcl ("Disabled"),
.bar1_prefetchable_0_hwtcl ("Disabled"),
.bar2_size_mask_0_hwtcl (0),
.bar2_io_space_0_hwtcl ("Disabled"),
.bar2_64bit_mem_space_0_hwtcl ("Disabled"),
.bar2_prefetchable_0_hwtcl ("Disabled"),
.bar3_size_mask_0_hwtcl (0),
.bar3_io_space_0_hwtcl ("Disabled"),
.bar3_prefetchable_0_hwtcl ("Disabled"),
.bar4_size_mask_0_hwtcl (0),
.bar4_io_space_0_hwtcl ("Disabled"),
.bar4_64bit_mem_space_0_hwtcl ("Disabled"),
.bar4_prefetchable_0_hwtcl ("Disabled"),
.bar5_size_mask_0_hwtcl (0),
.bar5_io_space_0_hwtcl ("Disabled"),
.bar5_prefetchable_0_hwtcl ("Disabled"),
.expansion_base_address_register_0_hwtcl (0),
.io_window_addr_width_hwtcl (0),
.prefetchable_mem_window_addr_width_hwtcl (0),
.vendor_id_0_hwtcl (4466),
.device_id_0_hwtcl (60395),
.revision_id_0_hwtcl (1),
.class_code_0_hwtcl (16711680),
.subsystem_vendor_id_0_hwtcl (4466),
.subsystem_device_id_0_hwtcl (60395),
.max_payload_size_0_hwtcl (128),
.extend_tag_field_0_hwtcl ("32"),
.completion_timeout_0_hwtcl ("ABCD"),
.enable_completion_timeout_disable_0_hwtcl (1),
.flr_capability_0_hwtcl (0),
.use_aer_0_hwtcl (0),
.ecrc_check_capable_0_hwtcl (0),
.ecrc_gen_capable_0_hwtcl (0),
.dll_active_report_support_0_hwtcl (0),
.surprise_down_error_support_0_hwtcl (0),
.msi_multi_message_capable_0_hwtcl ("1"),
.msi_64bit_addressing_capable_0_hwtcl ("true"),
.msi_masking_capable_0_hwtcl ("false"),
.msi_support_0_hwtcl ("true"),
.enable_function_msix_support_0_hwtcl (0),
.msix_table_size_0_hwtcl (0),
.msix_table_offset_0_hwtcl ("0"),
.msix_table_bir_0_hwtcl (0),
.msix_pba_offset_0_hwtcl ("0"),
.msix_pba_bir_0_hwtcl (0),
.interrupt_pin_0_hwtcl ("inta"),
.slot_power_scale_0_hwtcl (0),
.slot_power_limit_0_hwtcl (0),
.slot_number_0_hwtcl (0),
.rx_ei_l0s_0_hwtcl (0),
.endpoint_l0_latency_0_hwtcl (0),
.endpoint_l1_latency_0_hwtcl (0),
.reconfig_to_xcvr_width (350),
.hip_hard_reset_hwtcl (1),
.reconfig_from_xcvr_width (230),
.single_rx_detect_hwtcl (4),
.enable_l0s_aspm_hwtcl ("false"),
.aspm_optionality_hwtcl ("true"),
.enable_adapter_half_rate_mode_hwtcl ("false"),
.millisecond_cycle_count_hwtcl (124250),
.credit_buffer_allocation_aux_hwtcl ("absolute"),
.vc0_rx_flow_ctrl_posted_header_hwtcl (18),
.vc0_rx_flow_ctrl_posted_data_hwtcl (94),
.vc0_rx_flow_ctrl_nonposted_header_hwtcl (32),
.vc0_rx_flow_ctrl_nonposted_data_hwtcl (0),
.vc0_rx_flow_ctrl_compl_header_hwtcl (0),
.vc0_rx_flow_ctrl_compl_data_hwtcl (0),
.cpl_spc_header_hwtcl (44),
.cpl_spc_data_hwtcl (196),
.port_width_data_hwtcl (64),
.bypass_clk_switch_hwtcl ("disable"),
.cvp_rate_sel_hwtcl ("full_rate"),
.cvp_data_compressed_hwtcl ("false"),
.cvp_data_encrypted_hwtcl ("false"),
.cvp_mode_reset_hwtcl ("false"),
.cvp_clk_reset_hwtcl ("false"),
.core_clk_sel_hwtcl ("pld_clk"),
.enable_rx_buffer_checking_hwtcl ("false"),
.disable_link_x2_support_hwtcl ("false"),
.device_number_hwtcl (0),
.pipex1_debug_sel_hwtcl ("disable"),
.pclk_out_sel_hwtcl ("pclk"),
.no_soft_reset_hwtcl ("false"),
.d1_support_hwtcl ("false"),
.d2_support_hwtcl ("false"),
.d0_pme_hwtcl ("false"),
.d1_pme_hwtcl ("false"),
.d2_pme_hwtcl ("false"),
.d3_hot_pme_hwtcl ("false"),
.d3_cold_pme_hwtcl ("false"),
.low_priority_vc_hwtcl ("single_vc"),
.enable_l1_aspm_hwtcl ("false"),
.l1_exit_latency_sameclock_hwtcl (0),
.l1_exit_latency_diffclock_hwtcl (0),
.hot_plug_support_hwtcl (0),
.no_command_completed_hwtcl ("false"),
.eie_before_nfts_count_hwtcl (4),
.gen2_diffclock_nfts_count_hwtcl (255),
.gen2_sameclock_nfts_count_hwtcl (255),
.deemphasis_enable_hwtcl ("false"),
.l0_exit_latency_sameclock_hwtcl (6),
.l0_exit_latency_diffclock_hwtcl (6),
.vc0_clk_enable_hwtcl ("true"),
.register_pipe_signals_hwtcl ("true"),
.tx_cdc_almost_empty_hwtcl (5),
.rx_l0s_count_idl_hwtcl (0),
.cdc_dummy_insert_limit_hwtcl (11),
.ei_delay_powerdown_count_hwtcl (10),
.skp_os_schedule_count_hwtcl (0),
.fc_init_timer_hwtcl (1024),
.l01_entry_latency_hwtcl (31),
.flow_control_update_count_hwtcl (30),
.flow_control_timeout_count_hwtcl (200),
.retry_buffer_last_active_address_hwtcl (255),
.reserved_debug_hwtcl (0),
.use_tl_cfg_sync_hwtcl (1),
.diffclock_nfts_count_hwtcl (255),
.sameclock_nfts_count_hwtcl (255),
.l2_async_logic_hwtcl ("disable"),
.rx_cdc_almost_full_hwtcl (12),
.tx_cdc_almost_full_hwtcl (11),
.indicator_hwtcl (0),
.maximum_current_0_hwtcl (0),
.disable_snoop_packet_0_hwtcl ("false"),
.bridge_port_vga_enable_0_hwtcl ("false"),
.bridge_port_ssid_support_0_hwtcl ("false"),
.ssvid_0_hwtcl (0),
.ssid_0_hwtcl (0),
.porttype_func1_hwtcl ("Native endpoint"),
.bar0_size_mask_1_hwtcl (28),
.bar0_io_space_1_hwtcl ("Disabled"),
.bar0_64bit_mem_space_1_hwtcl ("Enabled"),
.bar0_prefetchable_1_hwtcl ("Enabled"),
.bar1_size_mask_1_hwtcl (0),
.bar1_io_space_1_hwtcl ("Disabled"),
.bar1_prefetchable_1_hwtcl ("Disabled"),
.bar2_size_mask_1_hwtcl (0),
.bar2_io_space_1_hwtcl ("Disabled"),
.bar2_64bit_mem_space_1_hwtcl ("Disabled"),
.bar2_prefetchable_1_hwtcl ("Disabled"),
.bar3_size_mask_1_hwtcl (0),
.bar3_io_space_1_hwtcl ("Disabled"),
.bar3_prefetchable_1_hwtcl ("Disabled"),
.bar4_size_mask_1_hwtcl (0),
.bar4_io_space_1_hwtcl ("Disabled"),
.bar4_64bit_mem_space_1_hwtcl ("Disabled"),
.bar4_prefetchable_1_hwtcl ("Disabled"),
.bar5_size_mask_1_hwtcl (0),
.bar5_io_space_1_hwtcl ("Disabled"),
.bar5_prefetchable_1_hwtcl ("Disabled"),
.expansion_base_address_register_1_hwtcl (0),
.vendor_id_1_hwtcl (0),
.device_id_1_hwtcl (1),
.revision_id_1_hwtcl (1),
.class_code_1_hwtcl (0),
.subsystem_vendor_id_1_hwtcl (0),
.subsystem_device_id_1_hwtcl (0),
.max_payload_size_1_hwtcl (128),
.extend_tag_field_1_hwtcl ("32"),
.completion_timeout_1_hwtcl ("ABCD"),
.enable_completion_timeout_disable_1_hwtcl (1),
.flr_capability_1_hwtcl (0),
.use_aer_1_hwtcl (0),
.ecrc_check_capable_1_hwtcl (0),
.ecrc_gen_capable_1_hwtcl (0),
.dll_active_report_support_1_hwtcl (0),
.surprise_down_error_support_1_hwtcl (0),
.msi_multi_message_capable_1_hwtcl ("4"),
.msi_64bit_addressing_capable_1_hwtcl ("true"),
.msi_masking_capable_1_hwtcl ("false"),
.msi_support_1_hwtcl ("true"),
.enable_function_msix_support_1_hwtcl (0),
.msix_table_size_1_hwtcl (0),
.msix_table_offset_1_hwtcl ("0"),
.msix_table_bir_1_hwtcl (0),
.msix_pba_offset_1_hwtcl ("0"),
.msix_pba_bir_1_hwtcl (0),
.interrupt_pin_1_hwtcl ("inta"),
.slot_power_scale_1_hwtcl (0),
.slot_power_limit_1_hwtcl (0),
.slot_number_1_hwtcl (0),
.rx_ei_l0s_1_hwtcl (0),
.endpoint_l0_latency_1_hwtcl (0),
.endpoint_l1_latency_1_hwtcl (0),
.maximum_current_1_hwtcl (0),
.disable_snoop_packet_1_hwtcl ("false"),
.bridge_port_vga_enable_1_hwtcl ("false"),
.bridge_port_ssid_support_1_hwtcl ("false"),
.ssvid_1_hwtcl (0),
.ssid_1_hwtcl (0),
.porttype_func2_hwtcl ("Native endpoint"),
.bar0_size_mask_2_hwtcl (28),
.bar0_io_space_2_hwtcl ("Disabled"),
.bar0_64bit_mem_space_2_hwtcl ("Enabled"),
.bar0_prefetchable_2_hwtcl ("Enabled"),
.bar1_size_mask_2_hwtcl (0),
.bar1_io_space_2_hwtcl ("Disabled"),
.bar1_prefetchable_2_hwtcl ("Disabled"),
.bar2_size_mask_2_hwtcl (0),
.bar2_io_space_2_hwtcl ("Disabled"),
.bar2_64bit_mem_space_2_hwtcl ("Disabled"),
.bar2_prefetchable_2_hwtcl ("Disabled"),
.bar3_size_mask_2_hwtcl (0),
.bar3_io_space_2_hwtcl ("Disabled"),
.bar3_prefetchable_2_hwtcl ("Disabled"),
.bar4_size_mask_2_hwtcl (0),
.bar4_io_space_2_hwtcl ("Disabled"),
.bar4_64bit_mem_space_2_hwtcl ("Disabled"),
.bar4_prefetchable_2_hwtcl ("Disabled"),
.bar5_size_mask_2_hwtcl (0),
.bar5_io_space_2_hwtcl ("Disabled"),
.bar5_prefetchable_2_hwtcl ("Disabled"),
.expansion_base_address_register_2_hwtcl (0),
.vendor_id_2_hwtcl (0),
.device_id_2_hwtcl (1),
.revision_id_2_hwtcl (1),
.class_code_2_hwtcl (0),
.subsystem_vendor_id_2_hwtcl (0),
.subsystem_device_id_2_hwtcl (0),
.max_payload_size_2_hwtcl (128),
.extend_tag_field_2_hwtcl ("32"),
.completion_timeout_2_hwtcl ("ABCD"),
.enable_completion_timeout_disable_2_hwtcl (1),
.flr_capability_2_hwtcl (0),
.use_aer_2_hwtcl (0),
.ecrc_check_capable_2_hwtcl (0),
.ecrc_gen_capable_2_hwtcl (0),
.dll_active_report_support_2_hwtcl (0),
.surprise_down_error_support_2_hwtcl (0),
.msi_multi_message_capable_2_hwtcl ("4"),
.msi_64bit_addressing_capable_2_hwtcl ("true"),
.msi_masking_capable_2_hwtcl ("false"),
.msi_support_2_hwtcl ("true"),
.enable_function_msix_support_2_hwtcl (0),
.msix_table_size_2_hwtcl (0),
.msix_table_offset_2_hwtcl ("0"),
.msix_table_bir_2_hwtcl (0),
.msix_pba_offset_2_hwtcl ("0"),
.msix_pba_bir_2_hwtcl (0),
.interrupt_pin_2_hwtcl ("inta"),
.slot_power_scale_2_hwtcl (0),
.slot_power_limit_2_hwtcl (0),
.slot_number_2_hwtcl (0),
.rx_ei_l0s_2_hwtcl (0),
.endpoint_l0_latency_2_hwtcl (0),
.endpoint_l1_latency_2_hwtcl (0),
.maximum_current_2_hwtcl (0),
.disable_snoop_packet_2_hwtcl ("false"),
.bridge_port_vga_enable_2_hwtcl ("false"),
.bridge_port_ssid_support_2_hwtcl ("false"),
.ssvid_2_hwtcl (0),
.ssid_2_hwtcl (0),
.porttype_func3_hwtcl ("Native endpoint"),
.bar0_size_mask_3_hwtcl (28),
.bar0_io_space_3_hwtcl ("Disabled"),
.bar0_64bit_mem_space_3_hwtcl ("Enabled"),
.bar0_prefetchable_3_hwtcl ("Enabled"),
.bar1_size_mask_3_hwtcl (0),
.bar1_io_space_3_hwtcl ("Disabled"),
.bar1_prefetchable_3_hwtcl ("Disabled"),
.bar2_size_mask_3_hwtcl (0),
.bar2_io_space_3_hwtcl ("Disabled"),
.bar2_64bit_mem_space_3_hwtcl ("Disabled"),
.bar2_prefetchable_3_hwtcl ("Disabled"),
.bar3_size_mask_3_hwtcl (0),
.bar3_io_space_3_hwtcl ("Disabled"),
.bar3_prefetchable_3_hwtcl ("Disabled"),
.bar4_size_mask_3_hwtcl (0),
.bar4_io_space_3_hwtcl ("Disabled"),
.bar4_64bit_mem_space_3_hwtcl ("Disabled"),
.bar4_prefetchable_3_hwtcl ("Disabled"),
.bar5_size_mask_3_hwtcl (0),
.bar5_io_space_3_hwtcl ("Disabled"),
.bar5_prefetchable_3_hwtcl ("Disabled"),
.expansion_base_address_register_3_hwtcl (0),
.vendor_id_3_hwtcl (0),
.device_id_3_hwtcl (1),
.revision_id_3_hwtcl (1),
.class_code_3_hwtcl (0),
.subsystem_vendor_id_3_hwtcl (0),
.subsystem_device_id_3_hwtcl (0),
.max_payload_size_3_hwtcl (128),
.extend_tag_field_3_hwtcl ("32"),
.completion_timeout_3_hwtcl ("ABCD"),
.enable_completion_timeout_disable_3_hwtcl (1),
.flr_capability_3_hwtcl (0),
.use_aer_3_hwtcl (0),
.ecrc_check_capable_3_hwtcl (0),
.ecrc_gen_capable_3_hwtcl (0),
.dll_active_report_support_3_hwtcl (0),
.surprise_down_error_support_3_hwtcl (0),
.msi_multi_message_capable_3_hwtcl ("4"),
.msi_64bit_addressing_capable_3_hwtcl ("true"),
.msi_masking_capable_3_hwtcl ("false"),
.msi_support_3_hwtcl ("true"),
.enable_function_msix_support_3_hwtcl (0),
.msix_table_size_3_hwtcl (0),
.msix_table_offset_3_hwtcl ("0"),
.msix_table_bir_3_hwtcl (0),
.msix_pba_offset_3_hwtcl ("0"),
.msix_pba_bir_3_hwtcl (0),
.interrupt_pin_3_hwtcl ("inta"),
.slot_power_scale_3_hwtcl (0),
.slot_power_limit_3_hwtcl (0),
.slot_number_3_hwtcl (0),
.rx_ei_l0s_3_hwtcl (0),
.endpoint_l0_latency_3_hwtcl (0),
.endpoint_l1_latency_3_hwtcl (0),
.maximum_current_3_hwtcl (0),
.disable_snoop_packet_3_hwtcl ("false"),
.bridge_port_vga_enable_3_hwtcl ("false"),
.bridge_port_ssid_support_3_hwtcl ("false"),
.ssvid_3_hwtcl (0),
.ssid_3_hwtcl (0),
.porttype_func4_hwtcl ("Native endpoint"),
.bar0_size_mask_4_hwtcl (28),
.bar0_io_space_4_hwtcl ("Disabled"),
.bar0_64bit_mem_space_4_hwtcl ("Enabled"),
.bar0_prefetchable_4_hwtcl ("Enabled"),
.bar1_size_mask_4_hwtcl (0),
.bar1_io_space_4_hwtcl ("Disabled"),
.bar1_prefetchable_4_hwtcl ("Disabled"),
.bar2_size_mask_4_hwtcl (0),
.bar2_io_space_4_hwtcl ("Disabled"),
.bar2_64bit_mem_space_4_hwtcl ("Disabled"),
.bar2_prefetchable_4_hwtcl ("Disabled"),
.bar3_size_mask_4_hwtcl (0),
.bar3_io_space_4_hwtcl ("Disabled"),
.bar3_prefetchable_4_hwtcl ("Disabled"),
.bar4_size_mask_4_hwtcl (0),
.bar4_io_space_4_hwtcl ("Disabled"),
.bar4_64bit_mem_space_4_hwtcl ("Disabled"),
.bar4_prefetchable_4_hwtcl ("Disabled"),
.bar5_size_mask_4_hwtcl (0),
.bar5_io_space_4_hwtcl ("Disabled"),
.bar5_prefetchable_4_hwtcl ("Disabled"),
.expansion_base_address_register_4_hwtcl (0),
.vendor_id_4_hwtcl (0),
.device_id_4_hwtcl (1),
.revision_id_4_hwtcl (1),
.class_code_4_hwtcl (0),
.subsystem_vendor_id_4_hwtcl (0),
.subsystem_device_id_4_hwtcl (0),
.max_payload_size_4_hwtcl (128),
.extend_tag_field_4_hwtcl ("32"),
.completion_timeout_4_hwtcl ("ABCD"),
.enable_completion_timeout_disable_4_hwtcl (1),
.flr_capability_4_hwtcl (0),
.use_aer_4_hwtcl (0),
.ecrc_check_capable_4_hwtcl (0),
.ecrc_gen_capable_4_hwtcl (0),
.dll_active_report_support_4_hwtcl (0),
.surprise_down_error_support_4_hwtcl (0),
.msi_multi_message_capable_4_hwtcl ("4"),
.msi_64bit_addressing_capable_4_hwtcl ("true"),
.msi_masking_capable_4_hwtcl ("false"),
.msi_support_4_hwtcl ("true"),
.enable_function_msix_support_4_hwtcl (0),
.msix_table_size_4_hwtcl (0),
.msix_table_offset_4_hwtcl ("0"),
.msix_table_bir_4_hwtcl (0),
.msix_pba_offset_4_hwtcl ("0"),
.msix_pba_bir_4_hwtcl (0),
.interrupt_pin_4_hwtcl ("inta"),
.slot_power_scale_4_hwtcl (0),
.slot_power_limit_4_hwtcl (0),
.slot_number_4_hwtcl (0),
.rx_ei_l0s_4_hwtcl (0),
.endpoint_l0_latency_4_hwtcl (0),
.endpoint_l1_latency_4_hwtcl (0),
.maximum_current_4_hwtcl (0),
.disable_snoop_packet_4_hwtcl ("false"),
.bridge_port_vga_enable_4_hwtcl ("false"),
.bridge_port_ssid_support_4_hwtcl ("false"),
.ssvid_4_hwtcl (0),
.ssid_4_hwtcl (0),
.porttype_func5_hwtcl ("Native endpoint"),
.bar0_size_mask_5_hwtcl (28),
.bar0_io_space_5_hwtcl ("Disabled"),
.bar0_64bit_mem_space_5_hwtcl ("Enabled"),
.bar0_prefetchable_5_hwtcl ("Enabled"),
.bar1_size_mask_5_hwtcl (0),
.bar1_io_space_5_hwtcl ("Disabled"),
.bar1_prefetchable_5_hwtcl ("Disabled"),
.bar2_size_mask_5_hwtcl (0),
.bar2_io_space_5_hwtcl ("Disabled"),
.bar2_64bit_mem_space_5_hwtcl ("Disabled"),
.bar2_prefetchable_5_hwtcl ("Disabled"),
.bar3_size_mask_5_hwtcl (0),
.bar3_io_space_5_hwtcl ("Disabled"),
.bar3_prefetchable_5_hwtcl ("Disabled"),
.bar4_size_mask_5_hwtcl (0),
.bar4_io_space_5_hwtcl ("Disabled"),
.bar4_64bit_mem_space_5_hwtcl ("Disabled"),
.bar4_prefetchable_5_hwtcl ("Disabled"),
.bar5_size_mask_5_hwtcl (0),
.bar5_io_space_5_hwtcl ("Disabled"),
.bar5_prefetchable_5_hwtcl ("Disabled"),
.expansion_base_address_register_5_hwtcl (0),
.vendor_id_5_hwtcl (0),
.device_id_5_hwtcl (1),
.revision_id_5_hwtcl (1),
.class_code_5_hwtcl (0),
.subsystem_vendor_id_5_hwtcl (0),
.subsystem_device_id_5_hwtcl (0),
.max_payload_size_5_hwtcl (128),
.extend_tag_field_5_hwtcl ("32"),
.completion_timeout_5_hwtcl ("ABCD"),
.enable_completion_timeout_disable_5_hwtcl (1),
.flr_capability_5_hwtcl (0),
.use_aer_5_hwtcl (0),
.ecrc_check_capable_5_hwtcl (0),
.ecrc_gen_capable_5_hwtcl (0),
.dll_active_report_support_5_hwtcl (0),
.surprise_down_error_support_5_hwtcl (0),
.msi_multi_message_capable_5_hwtcl ("4"),
.msi_64bit_addressing_capable_5_hwtcl ("true"),
.msi_masking_capable_5_hwtcl ("false"),
.msi_support_5_hwtcl ("true"),
.enable_function_msix_support_5_hwtcl (0),
.msix_table_size_5_hwtcl (0),
.msix_table_offset_5_hwtcl ("0"),
.msix_table_bir_5_hwtcl (0),
.msix_pba_offset_5_hwtcl ("0"),
.msix_pba_bir_5_hwtcl (0),
.interrupt_pin_5_hwtcl ("inta"),
.slot_power_scale_5_hwtcl (0),
.slot_power_limit_5_hwtcl (0),
.slot_number_5_hwtcl (0),
.rx_ei_l0s_5_hwtcl (0),
.endpoint_l0_latency_5_hwtcl (0),
.endpoint_l1_latency_5_hwtcl (0),
.maximum_current_5_hwtcl (0),
.disable_snoop_packet_5_hwtcl ("false"),
.bridge_port_vga_enable_5_hwtcl ("false"),
.bridge_port_ssid_support_5_hwtcl ("false"),
.ssvid_5_hwtcl (0),
.ssid_5_hwtcl (0),
.porttype_func6_hwtcl ("Native endpoint"),
.bar0_size_mask_6_hwtcl (28),
.bar0_io_space_6_hwtcl ("Disabled"),
.bar0_64bit_mem_space_6_hwtcl ("Enabled"),
.bar0_prefetchable_6_hwtcl ("Enabled"),
.bar1_size_mask_6_hwtcl (0),
.bar1_io_space_6_hwtcl ("Disabled"),
.bar1_prefetchable_6_hwtcl ("Disabled"),
.bar2_size_mask_6_hwtcl (0),
.bar2_io_space_6_hwtcl ("Disabled"),
.bar2_64bit_mem_space_6_hwtcl ("Disabled"),
.bar2_prefetchable_6_hwtcl ("Disabled"),
.bar3_size_mask_6_hwtcl (0),
.bar3_io_space_6_hwtcl ("Disabled"),
.bar3_prefetchable_6_hwtcl ("Disabled"),
.bar4_size_mask_6_hwtcl (0),
.bar4_io_space_6_hwtcl ("Disabled"),
.bar4_64bit_mem_space_6_hwtcl ("Disabled"),
.bar4_prefetchable_6_hwtcl ("Disabled"),
.bar5_size_mask_6_hwtcl (0),
.bar5_io_space_6_hwtcl ("Disabled"),
.bar5_prefetchable_6_hwtcl ("Disabled"),
.expansion_base_address_register_6_hwtcl (0),
.vendor_id_6_hwtcl (0),
.device_id_6_hwtcl (1),
.revision_id_6_hwtcl (1),
.class_code_6_hwtcl (0),
.subsystem_vendor_id_6_hwtcl (0),
.subsystem_device_id_6_hwtcl (0),
.max_payload_size_6_hwtcl (128),
.extend_tag_field_6_hwtcl ("32"),
.completion_timeout_6_hwtcl ("ABCD"),
.enable_completion_timeout_disable_6_hwtcl (1),
.flr_capability_6_hwtcl (0),
.use_aer_6_hwtcl (0),
.ecrc_check_capable_6_hwtcl (0),
.ecrc_gen_capable_6_hwtcl (0),
.dll_active_report_support_6_hwtcl (0),
.surprise_down_error_support_6_hwtcl (0),
.msi_multi_message_capable_6_hwtcl ("4"),
.msi_64bit_addressing_capable_6_hwtcl ("true"),
.msi_masking_capable_6_hwtcl ("false"),
.msi_support_6_hwtcl ("true"),
.enable_function_msix_support_6_hwtcl (0),
.msix_table_size_6_hwtcl (0),
.msix_table_offset_6_hwtcl ("0"),
.msix_table_bir_6_hwtcl (0),
.msix_pba_offset_6_hwtcl ("0"),
.msix_pba_bir_6_hwtcl (0),
.interrupt_pin_6_hwtcl ("inta"),
.slot_power_scale_6_hwtcl (0),
.slot_power_limit_6_hwtcl (0),
.slot_number_6_hwtcl (0),
.rx_ei_l0s_6_hwtcl (0),
.endpoint_l0_latency_6_hwtcl (0),
.endpoint_l1_latency_6_hwtcl (0),
.maximum_current_6_hwtcl (0),
.disable_snoop_packet_6_hwtcl ("false"),
.bridge_port_vga_enable_6_hwtcl ("false"),
.bridge_port_ssid_support_6_hwtcl ("false"),
.ssvid_6_hwtcl (0),
.ssid_6_hwtcl (0),
.porttype_func7_hwtcl ("Native endpoint"),
.bar0_size_mask_7_hwtcl (28),
.bar0_io_space_7_hwtcl ("Disabled"),
.bar0_64bit_mem_space_7_hwtcl ("Enabled"),
.bar0_prefetchable_7_hwtcl ("Enabled"),
.bar1_size_mask_7_hwtcl (0),
.bar1_io_space_7_hwtcl ("Disabled"),
.bar1_prefetchable_7_hwtcl ("Disabled"),
.bar2_size_mask_7_hwtcl (0),
.bar2_io_space_7_hwtcl ("Disabled"),
.bar2_64bit_mem_space_7_hwtcl ("Disabled"),
.bar2_prefetchable_7_hwtcl ("Disabled"),
.bar3_size_mask_7_hwtcl (0),
.bar3_io_space_7_hwtcl ("Disabled"),
.bar3_prefetchable_7_hwtcl ("Disabled"),
.bar4_size_mask_7_hwtcl (0),
.bar4_io_space_7_hwtcl ("Disabled"),
.bar4_64bit_mem_space_7_hwtcl ("Disabled"),
.bar4_prefetchable_7_hwtcl ("Disabled"),
.bar5_size_mask_7_hwtcl (0),
.bar5_io_space_7_hwtcl ("Disabled"),
.bar5_prefetchable_7_hwtcl ("Disabled"),
.expansion_base_address_register_7_hwtcl (0),
.vendor_id_7_hwtcl (0),
.device_id_7_hwtcl (1),
.revision_id_7_hwtcl (1),
.class_code_7_hwtcl (0),
.subsystem_vendor_id_7_hwtcl (0),
.subsystem_device_id_7_hwtcl (0),
.max_payload_size_7_hwtcl (128),
.extend_tag_field_7_hwtcl ("32"),
.completion_timeout_7_hwtcl ("ABCD"),
.enable_completion_timeout_disable_7_hwtcl (1),
.flr_capability_7_hwtcl (0),
.use_aer_7_hwtcl (0),
.ecrc_check_capable_7_hwtcl (0),
.ecrc_gen_capable_7_hwtcl (0),
.dll_active_report_support_7_hwtcl (0),
.surprise_down_error_support_7_hwtcl (0),
.msi_multi_message_capable_7_hwtcl ("4"),
.msi_64bit_addressing_capable_7_hwtcl ("true"),
.msi_masking_capable_7_hwtcl ("false"),
.msi_support_7_hwtcl ("true"),
.enable_function_msix_support_7_hwtcl (0),
.msix_table_size_7_hwtcl (0),
.msix_table_offset_7_hwtcl ("0"),
.msix_table_bir_7_hwtcl (0),
.msix_pba_offset_7_hwtcl ("0"),
.msix_pba_bir_7_hwtcl (0),
.interrupt_pin_7_hwtcl ("inta"),
.slot_power_scale_7_hwtcl (0),
.slot_power_limit_7_hwtcl (0),
.slot_number_7_hwtcl (0),
.rx_ei_l0s_7_hwtcl (0),
.endpoint_l0_latency_7_hwtcl (0),
.endpoint_l1_latency_7_hwtcl (0),
.maximum_current_7_hwtcl (0),
.disable_snoop_packet_7_hwtcl ("false"),
.bridge_port_vga_enable_7_hwtcl ("false"),
.bridge_port_ssid_support_7_hwtcl ("false"),
.ssvid_7_hwtcl (0),
.ssid_7_hwtcl (0),
.rpre_emph_a_val_hwtcl (12),
.rpre_emph_b_val_hwtcl (0),
.rpre_emph_c_val_hwtcl (19),
.rpre_emph_d_val_hwtcl (13),
.rpre_emph_e_val_hwtcl (21),
.rvod_sel_a_val_hwtcl (42),
.rvod_sel_b_val_hwtcl (30),
.rvod_sel_c_val_hwtcl (43),
.rvod_sel_d_val_hwtcl (43),
.rvod_sel_e_val_hwtcl (9)
) pcie_c5_4x_inst (
.npor (npor), // npor.npor
.pin_perst (pin_perst), // .pin_perst
.test_in (test_in), // hip_ctrl.test_in
.simu_mode_pipe (simu_mode_pipe), // .simu_mode_pipe
.pld_clk (pld_clk), // pld_clk.clk
.coreclkout (coreclkout), // coreclkout_hip.clk
.refclk (refclk), // refclk.clk
.rx_in0 (rx_in0), // hip_serial.rx_in0
.rx_in1 (rx_in1), // .rx_in1
.rx_in2 (rx_in2), // .rx_in2
.rx_in3 (rx_in3), // .rx_in3
.tx_out0 (tx_out0), // .tx_out0
.tx_out1 (tx_out1), // .tx_out1
.tx_out2 (tx_out2), // .tx_out2
.tx_out3 (tx_out3), // .tx_out3
.rx_st_valid (rx_st_valid), // rx_st.valid
.rx_st_sop (rx_st_sop), // .startofpacket
.rx_st_eop (rx_st_eop), // .endofpacket
.rx_st_ready (rx_st_ready), // .ready
.rx_st_err (rx_st_err), // .error
.rx_st_data (rx_st_data), // .data
.rx_st_bar (rx_st_bar), // rx_bar_be.rx_st_bar
.rx_st_mask (rx_st_mask), // .rx_st_mask
.tx_st_valid (tx_st_valid), // tx_st.valid
.tx_st_sop (tx_st_sop), // .startofpacket
.tx_st_eop (tx_st_eop), // .endofpacket
.tx_st_ready (tx_st_ready), // .ready
.tx_st_err (tx_st_err), // .error
.tx_st_data (tx_st_data), // .data
.tx_fifo_empty (tx_fifo_empty), // tx_fifo.fifo_empty
.tx_cred_datafccp (tx_cred_datafccp), // tx_cred.tx_cred_datafccp
.tx_cred_datafcnp (tx_cred_datafcnp), // .tx_cred_datafcnp
.tx_cred_datafcp (tx_cred_datafcp), // .tx_cred_datafcp
.tx_cred_fchipcons (tx_cred_fchipcons), // .tx_cred_fchipcons
.tx_cred_fcinfinite (tx_cred_fcinfinite), // .tx_cred_fcinfinite
.tx_cred_hdrfccp (tx_cred_hdrfccp), // .tx_cred_hdrfccp
.tx_cred_hdrfcnp (tx_cred_hdrfcnp), // .tx_cred_hdrfcnp
.tx_cred_hdrfcp (tx_cred_hdrfcp), // .tx_cred_hdrfcp
.sim_pipe_pclk_in (sim_pipe_pclk_in), // hip_pipe.sim_pipe_pclk_in
.sim_pipe_rate (sim_pipe_rate), // .sim_pipe_rate
.sim_ltssmstate (sim_ltssmstate), // .sim_ltssmstate
.eidleinfersel0 (eidleinfersel0), // .eidleinfersel0
.eidleinfersel1 (eidleinfersel1), // .eidleinfersel1
.eidleinfersel2 (eidleinfersel2), // .eidleinfersel2
.eidleinfersel3 (eidleinfersel3), // .eidleinfersel3
.powerdown0 (powerdown0), // .powerdown0
.powerdown1 (powerdown1), // .powerdown1
.powerdown2 (powerdown2), // .powerdown2
.powerdown3 (powerdown3), // .powerdown3
.rxpolarity0 (rxpolarity0), // .rxpolarity0
.rxpolarity1 (rxpolarity1), // .rxpolarity1
.rxpolarity2 (rxpolarity2), // .rxpolarity2
.rxpolarity3 (rxpolarity3), // .rxpolarity3
.txcompl0 (txcompl0), // .txcompl0
.txcompl1 (txcompl1), // .txcompl1
.txcompl2 (txcompl2), // .txcompl2
.txcompl3 (txcompl3), // .txcompl3
.txdata0 (txdata0), // .txdata0
.txdata1 (txdata1), // .txdata1
.txdata2 (txdata2), // .txdata2
.txdata3 (txdata3), // .txdata3
.txdatak0 (txdatak0), // .txdatak0
.txdatak1 (txdatak1), // .txdatak1
.txdatak2 (txdatak2), // .txdatak2
.txdatak3 (txdatak3), // .txdatak3
.txdetectrx0 (txdetectrx0), // .txdetectrx0
.txdetectrx1 (txdetectrx1), // .txdetectrx1
.txdetectrx2 (txdetectrx2), // .txdetectrx2
.txdetectrx3 (txdetectrx3), // .txdetectrx3
.txelecidle0 (txelecidle0), // .txelecidle0
.txelecidle1 (txelecidle1), // .txelecidle1
.txelecidle2 (txelecidle2), // .txelecidle2
.txelecidle3 (txelecidle3), // .txelecidle3
.txswing0 (txswing0), // .txswing0
.txswing1 (txswing1), // .txswing1
.txswing2 (txswing2), // .txswing2
.txswing3 (txswing3), // .txswing3
.txmargin0 (txmargin0), // .txmargin0
.txmargin1 (txmargin1), // .txmargin1
.txmargin2 (txmargin2), // .txmargin2
.txmargin3 (txmargin3), // .txmargin3
.txdeemph0 (txdeemph0), // .txdeemph0
.txdeemph1 (txdeemph1), // .txdeemph1
.txdeemph2 (txdeemph2), // .txdeemph2
.txdeemph3 (txdeemph3), // .txdeemph3
.phystatus0 (phystatus0), // .phystatus0
.phystatus1 (phystatus1), // .phystatus1
.phystatus2 (phystatus2), // .phystatus2
.phystatus3 (phystatus3), // .phystatus3
.rxdata0 (rxdata0), // .rxdata0
.rxdata1 (rxdata1), // .rxdata1
.rxdata2 (rxdata2), // .rxdata2
.rxdata3 (rxdata3), // .rxdata3
.rxdatak0 (rxdatak0), // .rxdatak0
.rxdatak1 (rxdatak1), // .rxdatak1
.rxdatak2 (rxdatak2), // .rxdatak2
.rxdatak3 (rxdatak3), // .rxdatak3
.rxelecidle0 (rxelecidle0), // .rxelecidle0
.rxelecidle1 (rxelecidle1), // .rxelecidle1
.rxelecidle2 (rxelecidle2), // .rxelecidle2
.rxelecidle3 (rxelecidle3), // .rxelecidle3
.rxstatus0 (rxstatus0), // .rxstatus0
.rxstatus1 (rxstatus1), // .rxstatus1
.rxstatus2 (rxstatus2), // .rxstatus2
.rxstatus3 (rxstatus3), // .rxstatus3
.rxvalid0 (rxvalid0), // .rxvalid0
.rxvalid1 (rxvalid1), // .rxvalid1
.rxvalid2 (rxvalid2), // .rxvalid2
.rxvalid3 (rxvalid3), // .rxvalid3
.reset_status (reset_status), // hip_rst.reset_status
.serdes_pll_locked (serdes_pll_locked), // .serdes_pll_locked
.pld_clk_inuse (pld_clk_inuse), // .pld_clk_inuse
.pld_core_ready (pld_core_ready), // .pld_core_ready
.testin_zero (testin_zero), // .testin_zero
.lmi_addr (lmi_addr), // lmi.lmi_addr
.lmi_din (lmi_din), // .lmi_din
.lmi_rden (lmi_rden), // .lmi_rden
.lmi_wren (lmi_wren), // .lmi_wren
.lmi_ack (lmi_ack), // .lmi_ack
.lmi_dout (lmi_dout), // .lmi_dout
.pm_auxpwr (pm_auxpwr), // power_mngt.pm_auxpwr
.pm_data (pm_data), // .pm_data
.pme_to_cr (pme_to_cr), // .pme_to_cr
.pm_event (pm_event), // .pm_event
.pme_to_sr (pme_to_sr), // .pme_to_sr
.reconfig_to_xcvr (reconfig_to_xcvr), // reconfig_to_xcvr.reconfig_to_xcvr
.reconfig_from_xcvr (reconfig_from_xcvr), // reconfig_from_xcvr.reconfig_from_xcvr
.app_msi_num (app_msi_num), // int_msi.app_msi_num
.app_msi_req (app_msi_req), // .app_msi_req
.app_msi_tc (app_msi_tc), // .app_msi_tc
.app_msi_ack (app_msi_ack), // .app_msi_ack
.app_int_sts_vec (app_int_sts_vec), // .app_int_sts
.tl_hpg_ctrl_er (tl_hpg_ctrl_er), // config_tl.hpg_ctrler
.tl_cfg_ctl (tl_cfg_ctl), // .tl_cfg_ctl
.cpl_err (cpl_err), // .cpl_err
.tl_cfg_add (tl_cfg_add), // .tl_cfg_add
.tl_cfg_ctl_wr (tl_cfg_ctl_wr), // .tl_cfg_ctl_wr
.tl_cfg_sts_wr (tl_cfg_sts_wr), // .tl_cfg_sts_wr
.tl_cfg_sts (tl_cfg_sts), // .tl_cfg_sts
.cpl_pending (cpl_pending), // .cpl_pending
.derr_cor_ext_rcv0 (derr_cor_ext_rcv0), // hip_status.derr_cor_ext_rcv
.derr_cor_ext_rpl (derr_cor_ext_rpl), // .derr_cor_ext_rpl
.derr_rpl (derr_rpl), // .derr_rpl
.dlup_exit (dlup_exit), // .dlup_exit
.dl_ltssm (dl_ltssm), // .ltssmstate
.ev128ns (ev128ns), // .ev128ns
.ev1us (ev1us), // .ev1us
.hotrst_exit (hotrst_exit), // .hotrst_exit
.int_status (int_status), // .int_status
.l2_exit (l2_exit), // .l2_exit
.lane_act (lane_act), // .lane_act
.ko_cpl_spc_header (ko_cpl_spc_header), // .ko_cpl_spc_header
.ko_cpl_spc_data (ko_cpl_spc_data), // .ko_cpl_spc_data
.dl_current_speed (dl_current_speed), // hip_currentspeed.currentspeed
.rx_in4 (1'b0), // (terminated)
.rx_in5 (1'b0), // (terminated)
.rx_in6 (1'b0), // (terminated)
.rx_in7 (1'b0), // (terminated)
.tx_out4 (), // (terminated)
.tx_out5 (), // (terminated)
.tx_out6 (), // (terminated)
.tx_out7 (), // (terminated)
.rx_st_empty (), // (terminated)
.rx_fifo_empty (), // (terminated)
.rx_fifo_full (), // (terminated)
.rx_bar_dec_func_num (), // (terminated)
.rx_st_be (), // (terminated)
.tx_st_empty (1'b0), // (terminated)
.tx_fifo_full (), // (terminated)
.tx_fifo_rdp (), // (terminated)
.tx_fifo_wrp (), // (terminated)
.eidleinfersel4 (), // (terminated)
.eidleinfersel5 (), // (terminated)
.eidleinfersel6 (), // (terminated)
.eidleinfersel7 (), // (terminated)
.powerdown4 (), // (terminated)
.powerdown5 (), // (terminated)
.powerdown6 (), // (terminated)
.powerdown7 (), // (terminated)
.rxpolarity4 (), // (terminated)
.rxpolarity5 (), // (terminated)
.rxpolarity6 (), // (terminated)
.rxpolarity7 (), // (terminated)
.txcompl4 (), // (terminated)
.txcompl5 (), // (terminated)
.txcompl6 (), // (terminated)
.txcompl7 (), // (terminated)
.txdata4 (), // (terminated)
.txdata5 (), // (terminated)
.txdata6 (), // (terminated)
.txdata7 (), // (terminated)
.txdatak4 (), // (terminated)
.txdatak5 (), // (terminated)
.txdatak6 (), // (terminated)
.txdatak7 (), // (terminated)
.txdetectrx4 (), // (terminated)
.txdetectrx5 (), // (terminated)
.txdetectrx6 (), // (terminated)
.txdetectrx7 (), // (terminated)
.txelecidle4 (), // (terminated)
.txelecidle5 (), // (terminated)
.txelecidle6 (), // (terminated)
.txelecidle7 (), // (terminated)
.txswing4 (), // (terminated)
.txswing5 (), // (terminated)
.txswing6 (), // (terminated)
.txswing7 (), // (terminated)
.txmargin4 (), // (terminated)
.txmargin5 (), // (terminated)
.txmargin6 (), // (terminated)
.txmargin7 (), // (terminated)
.txdeemph4 (), // (terminated)
.txdeemph5 (), // (terminated)
.txdeemph6 (), // (terminated)
.txdeemph7 (), // (terminated)
.phystatus4 (1'b0), // (terminated)
.phystatus5 (1'b0), // (terminated)
.phystatus6 (1'b0), // (terminated)
.phystatus7 (1'b0), // (terminated)
.rxdata4 (8'b00000000), // (terminated)
.rxdata5 (8'b00000000), // (terminated)
.rxdata6 (8'b00000000), // (terminated)
.rxdata7 (8'b00000000), // (terminated)
.rxdatak4 (1'b0), // (terminated)
.rxdatak5 (1'b0), // (terminated)
.rxdatak6 (1'b0), // (terminated)
.rxdatak7 (1'b0), // (terminated)
.rxelecidle4 (1'b0), // (terminated)
.rxelecidle5 (1'b0), // (terminated)
.rxelecidle6 (1'b0), // (terminated)
.rxelecidle7 (1'b0), // (terminated)
.rxstatus4 (3'b000), // (terminated)
.rxstatus5 (3'b000), // (terminated)
.rxstatus6 (3'b000), // (terminated)
.rxstatus7 (3'b000), // (terminated)
.rxvalid4 (1'b0), // (terminated)
.rxvalid5 (1'b0), // (terminated)
.rxvalid6 (1'b0), // (terminated)
.rxvalid7 (1'b0), // (terminated)
.sim_pipe_pclk_out (), // (terminated)
.pm_event_func (3'b000), // (terminated)
.hip_reconfig_clk (1'b0), // (terminated)
.hip_reconfig_rst_n (1'b0), // (terminated)
.hip_reconfig_address (10'b0000000000), // (terminated)
.hip_reconfig_byte_en (2'b00), // (terminated)
.hip_reconfig_read (1'b0), // (terminated)
.hip_reconfig_readdata (), // (terminated)
.hip_reconfig_write (1'b0), // (terminated)
.hip_reconfig_writedata (16'b0000000000000000), // (terminated)
.ser_shift_load (1'b0), // (terminated)
.interface_sel (1'b0), // (terminated)
.app_msi_func (3'b000), // (terminated)
.serr_out (), // (terminated)
.aer_msi_num (5'b00000), // (terminated)
.pex_msi_num (5'b00000), // (terminated)
.cpl_err_func (3'b000) // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2014 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pcie_av_hip_ast" version="14.0.2" >
// Retrieval info: <generic name="ACDS_VERSION_HWTCL" value="14.0" />
// Retrieval info: <generic name="INTENDED_DEVICE_FAMILY" value="Arria V" />
// Retrieval info: <generic name="pcie_qsys" value="1" />
// Retrieval info: <generic name="lane_mask_hwtcl" value="x4" />
// Retrieval info: <generic name="gen12_lane_rate_mode_hwtcl" value="Gen1 (2.5 Gbps)" />
// Retrieval info: <generic name="porttype_func_hwtcl" value="Native endpoint" />
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// Retrieval info: <generic name="altpcie_avmm_hwtcl" value="0" />
// Retrieval info: <generic name="ast_width_hwtcl" value="Avalon-ST 64-bit" />
// Retrieval info: <generic name="rxbuffer_rxreq_hwtcl" value="Balanced" />
// Retrieval info: <generic name="pll_refclk_freq_hwtcl" value="100 MHz" />
// Retrieval info: <generic name="set_pld_clk_x1_625MHz_hwtcl" value="0" />
// Retrieval info: <generic name="use_rx_st_be_hwtcl" value="0" />
// Retrieval info: <generic name="in_cvp_mode_hwtcl" value="0" />
// Retrieval info: <generic name="hip_reconfig_hwtcl" value="0" />
// Retrieval info: <generic name="num_of_func_hwtcl" value="1" />
// Retrieval info: <generic name="max_payload_size_hwtcl" value="128" />
// Retrieval info: <generic name="extend_tag_field_hwtcl" value="32" />
// Retrieval info: <generic name="completion_timeout_hwtcl" value="ABCD" />
// Retrieval info: <generic name="enable_completion_timeout_disable_hwtcl" value="1" />
// Retrieval info: <generic name="use_aer_hwtcl" value="0" />
// Retrieval info: <generic name="ecrc_check_capable_hwtcl" value="0" />
// Retrieval info: <generic name="ecrc_gen_capable_hwtcl" value="0" />
// Retrieval info: <generic name="use_crc_forwarding_hwtcl" value="0" />
// Retrieval info: <generic name="port_link_number_hwtcl" value="1" />
// Retrieval info: <generic name="slotclkcfg_hwtcl" value="1" />
// Retrieval info: <generic name="enable_slot_register_hwtcl" value="0" />
// Retrieval info: <generic name="slot_power_scale_hwtcl" value="0" />
// Retrieval info: <generic name="slot_power_limit_hwtcl" value="0" />
// Retrieval info: <generic name="slot_number_hwtcl" value="0" />
// Retrieval info: <generic name="endpoint_l0_latency_hwtcl" value="0" />
// Retrieval info: <generic name="endpoint_l1_latency_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_0_hwtcl" value="1" />
// Retrieval info: <generic name="bar0_size_mask_0_hwtcl" value="7" />
// Retrieval info: <generic name="bar1_type_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_size_mask_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_type_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_size_mask_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_type_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_0_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_0_hwtcl" value="0" />
// Retrieval info: <generic name="io_window_addr_width_hwtcl" value="0" />
// Retrieval info: <generic name="prefetchable_mem_window_addr_width_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_0_hwtcl" value="4466" />
// Retrieval info: <generic name="device_id_0_hwtcl" value="60395" />
// Retrieval info: <generic name="revision_id_0_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_0_hwtcl" value="16711680" />
// Retrieval info: <generic name="subsystem_vendor_id_0_hwtcl" value="4466" />
// Retrieval info: <generic name="subsystem_device_id_0_hwtcl" value="60395" />
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// Retrieval info: <generic name="msix_pba_bir_0_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_0_hwtcl" value="inta" />
// Retrieval info: <generic name="force_hrc" value="0" />
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// Retrieval info: <generic name="override_rxbuffer_cred_preset" value="0" />
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// Retrieval info: <generic name="d1_pme_advanced_default_hwtcl" value="false" />
// Retrieval info: <generic name="d2_pme_advanced_default_hwtcl" value="false" />
// Retrieval info: <generic name="d3_hot_pme_advanced_default_hwtcl" value="false" />
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// Retrieval info: <generic name="low_priority_vc_advanced_default_hwtcl" value="single_vc" />
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// Retrieval info: <generic name="l1_exit_latency_diffclock_advanced_default_hwtcl" value="0" />
// Retrieval info: <generic name="hot_plug_support_advanced_default_hwtcl" value="0" />
// Retrieval info: <generic name="no_command_completed_advanced_default_hwtcl" value="false" />
// Retrieval info: <generic name="eie_before_nfts_count_advanced_default_hwtcl" value="4" />
// Retrieval info: <generic name="gen2_diffclock_nfts_count_advanced_default_hwtcl" value="255" />
// Retrieval info: <generic name="gen2_sameclock_nfts_count_advanced_default_hwtcl" value="255" />
// Retrieval info: <generic name="deemphasis_enable_advanced_default_hwtcl" value="false" />
// Retrieval info: <generic name="l0_exit_latency_sameclock_advanced_default_hwtcl" value="6" />
// Retrieval info: <generic name="l0_exit_latency_diffclock_advanced_default_hwtcl" value="6" />
// Retrieval info: <generic name="vc0_clk_enable_advanced_default_hwtcl" value="true" />
// Retrieval info: <generic name="register_pipe_signals_advanced_default_hwtcl" value="true" />
// Retrieval info: <generic name="tx_cdc_almost_empty_advanced_default_hwtcl" value="5" />
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// Retrieval info: <generic name="ei_delay_powerdown_count_advanced_default_hwtcl" value="10" />
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// Retrieval info: <generic name="diffclock_nfts_count_advanced_default_hwtcl" value="255" />
// Retrieval info: <generic name="sameclock_nfts_count_advanced_default_hwtcl" value="255" />
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// Retrieval info: <generic name="rx_cdc_almost_full_advanced_default_hwtcl" value="12" />
// Retrieval info: <generic name="tx_cdc_almost_full_advanced_default_hwtcl" value="11" />
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// Retrieval info: <generic name="maximum_current_0_hwtcl" value="0" />
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// Retrieval info: <generic name="bridge_port_vga_enable_0_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_0_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_0_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_0_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_1_hwtcl" value="1" />
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// Retrieval info: <generic name="bar1_type_1_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_1_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_1_hwtcl" value="0" />
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// Retrieval info: <generic name="bar3_type_1_hwtcl" value="0" />
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// Retrieval info: <generic name="bar5_type_1_hwtcl" value="0" />
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// Retrieval info: <generic name="vendor_id_1_hwtcl" value="0" />
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// Retrieval info: <generic name="surprise_down_error_support_1_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_1_hwtcl" value="4" />
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// Retrieval info: <generic name="bar2_type_2_hwtcl" value="0" />
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// Retrieval info: <generic name="bar4_type_2_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_2_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_2_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_2_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_2_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_2_hwtcl" value="0" />
// Retrieval info: <generic name="device_id_2_hwtcl" value="1" />
// Retrieval info: <generic name="revision_id_2_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_2_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_vendor_id_2_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_device_id_2_hwtcl" value="0" />
// Retrieval info: <generic name="flr_capability_2_hwtcl" value="0" />
// Retrieval info: <generic name="dll_active_report_support_2_hwtcl" value="0" />
// Retrieval info: <generic name="surprise_down_error_support_2_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_2_hwtcl" value="4" />
// Retrieval info: <generic name="msi_64bit_addressing_capable_2_hwtcl" value="true" />
// Retrieval info: <generic name="msi_masking_capable_2_hwtcl" value="false" />
// Retrieval info: <generic name="msi_support_2_hwtcl" value="true" />
// Retrieval info: <generic name="enable_function_msix_support_2_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_size_2_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_offset_2_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_bir_2_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_offset_2_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_bir_2_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_2_hwtcl" value="inta" />
// Retrieval info: <generic name="maximum_current_2_hwtcl" value="0" />
// Retrieval info: <generic name="disable_snoop_packet_2_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_vga_enable_2_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_2_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_2_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_2_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_3_hwtcl" value="1" />
// Retrieval info: <generic name="bar0_size_mask_3_hwtcl" value="28" />
// Retrieval info: <generic name="bar1_type_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_size_mask_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_type_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_size_mask_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_type_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_3_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_3_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_3_hwtcl" value="0" />
// Retrieval info: <generic name="device_id_3_hwtcl" value="1" />
// Retrieval info: <generic name="revision_id_3_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_3_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_vendor_id_3_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_device_id_3_hwtcl" value="0" />
// Retrieval info: <generic name="flr_capability_3_hwtcl" value="0" />
// Retrieval info: <generic name="dll_active_report_support_3_hwtcl" value="0" />
// Retrieval info: <generic name="surprise_down_error_support_3_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_3_hwtcl" value="4" />
// Retrieval info: <generic name="msi_64bit_addressing_capable_3_hwtcl" value="true" />
// Retrieval info: <generic name="msi_masking_capable_3_hwtcl" value="false" />
// Retrieval info: <generic name="msi_support_3_hwtcl" value="true" />
// Retrieval info: <generic name="enable_function_msix_support_3_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_size_3_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_offset_3_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_bir_3_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_offset_3_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_bir_3_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_3_hwtcl" value="inta" />
// Retrieval info: <generic name="maximum_current_3_hwtcl" value="0" />
// Retrieval info: <generic name="disable_snoop_packet_3_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_vga_enable_3_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_3_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_3_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_3_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_4_hwtcl" value="1" />
// Retrieval info: <generic name="bar0_size_mask_4_hwtcl" value="28" />
// Retrieval info: <generic name="bar1_type_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_size_mask_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_type_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_size_mask_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_type_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_4_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_4_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_4_hwtcl" value="0" />
// Retrieval info: <generic name="device_id_4_hwtcl" value="1" />
// Retrieval info: <generic name="revision_id_4_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_4_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_vendor_id_4_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_device_id_4_hwtcl" value="0" />
// Retrieval info: <generic name="flr_capability_4_hwtcl" value="0" />
// Retrieval info: <generic name="dll_active_report_support_4_hwtcl" value="0" />
// Retrieval info: <generic name="surprise_down_error_support_4_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_4_hwtcl" value="4" />
// Retrieval info: <generic name="msi_64bit_addressing_capable_4_hwtcl" value="true" />
// Retrieval info: <generic name="msi_masking_capable_4_hwtcl" value="false" />
// Retrieval info: <generic name="msi_support_4_hwtcl" value="true" />
// Retrieval info: <generic name="enable_function_msix_support_4_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_size_4_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_offset_4_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_bir_4_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_offset_4_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_bir_4_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_4_hwtcl" value="inta" />
// Retrieval info: <generic name="maximum_current_4_hwtcl" value="0" />
// Retrieval info: <generic name="disable_snoop_packet_4_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_vga_enable_4_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_4_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_4_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_4_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_5_hwtcl" value="1" />
// Retrieval info: <generic name="bar0_size_mask_5_hwtcl" value="28" />
// Retrieval info: <generic name="bar1_type_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_size_mask_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_type_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_size_mask_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_type_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_5_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_5_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_5_hwtcl" value="0" />
// Retrieval info: <generic name="device_id_5_hwtcl" value="1" />
// Retrieval info: <generic name="revision_id_5_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_5_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_vendor_id_5_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_device_id_5_hwtcl" value="0" />
// Retrieval info: <generic name="flr_capability_5_hwtcl" value="0" />
// Retrieval info: <generic name="dll_active_report_support_5_hwtcl" value="0" />
// Retrieval info: <generic name="surprise_down_error_support_5_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_5_hwtcl" value="4" />
// Retrieval info: <generic name="msi_64bit_addressing_capable_5_hwtcl" value="true" />
// Retrieval info: <generic name="msi_masking_capable_5_hwtcl" value="false" />
// Retrieval info: <generic name="msi_support_5_hwtcl" value="true" />
// Retrieval info: <generic name="enable_function_msix_support_5_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_size_5_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_offset_5_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_bir_5_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_offset_5_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_bir_5_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_5_hwtcl" value="inta" />
// Retrieval info: <generic name="maximum_current_5_hwtcl" value="0" />
// Retrieval info: <generic name="disable_snoop_packet_5_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_vga_enable_5_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_5_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_5_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_5_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_6_hwtcl" value="1" />
// Retrieval info: <generic name="bar0_size_mask_6_hwtcl" value="28" />
// Retrieval info: <generic name="bar1_type_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_size_mask_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_type_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_size_mask_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_type_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_6_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_6_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_6_hwtcl" value="0" />
// Retrieval info: <generic name="device_id_6_hwtcl" value="1" />
// Retrieval info: <generic name="revision_id_6_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_6_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_vendor_id_6_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_device_id_6_hwtcl" value="0" />
// Retrieval info: <generic name="flr_capability_6_hwtcl" value="0" />
// Retrieval info: <generic name="dll_active_report_support_6_hwtcl" value="0" />
// Retrieval info: <generic name="surprise_down_error_support_6_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_6_hwtcl" value="4" />
// Retrieval info: <generic name="msi_64bit_addressing_capable_6_hwtcl" value="true" />
// Retrieval info: <generic name="msi_masking_capable_6_hwtcl" value="false" />
// Retrieval info: <generic name="msi_support_6_hwtcl" value="true" />
// Retrieval info: <generic name="enable_function_msix_support_6_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_size_6_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_offset_6_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_bir_6_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_offset_6_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_bir_6_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_6_hwtcl" value="inta" />
// Retrieval info: <generic name="maximum_current_6_hwtcl" value="0" />
// Retrieval info: <generic name="disable_snoop_packet_6_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_vga_enable_6_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_6_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_6_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_6_hwtcl" value="0" />
// Retrieval info: <generic name="bar0_type_7_hwtcl" value="1" />
// Retrieval info: <generic name="bar0_size_mask_7_hwtcl" value="28" />
// Retrieval info: <generic name="bar1_type_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar1_size_mask_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_type_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar2_size_mask_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_type_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar3_size_mask_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_type_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar4_size_mask_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_type_7_hwtcl" value="0" />
// Retrieval info: <generic name="bar5_size_mask_7_hwtcl" value="0" />
// Retrieval info: <generic name="expansion_base_address_register_7_hwtcl" value="0" />
// Retrieval info: <generic name="vendor_id_7_hwtcl" value="0" />
// Retrieval info: <generic name="device_id_7_hwtcl" value="1" />
// Retrieval info: <generic name="revision_id_7_hwtcl" value="1" />
// Retrieval info: <generic name="class_code_7_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_vendor_id_7_hwtcl" value="0" />
// Retrieval info: <generic name="subsystem_device_id_7_hwtcl" value="0" />
// Retrieval info: <generic name="flr_capability_7_hwtcl" value="0" />
// Retrieval info: <generic name="dll_active_report_support_7_hwtcl" value="0" />
// Retrieval info: <generic name="surprise_down_error_support_7_hwtcl" value="0" />
// Retrieval info: <generic name="msi_multi_message_capable_7_hwtcl" value="4" />
// Retrieval info: <generic name="msi_64bit_addressing_capable_7_hwtcl" value="true" />
// Retrieval info: <generic name="msi_masking_capable_7_hwtcl" value="false" />
// Retrieval info: <generic name="msi_support_7_hwtcl" value="true" />
// Retrieval info: <generic name="enable_function_msix_support_7_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_size_7_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_offset_7_hwtcl" value="0" />
// Retrieval info: <generic name="msix_table_bir_7_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_offset_7_hwtcl" value="0" />
// Retrieval info: <generic name="msix_pba_bir_7_hwtcl" value="0" />
// Retrieval info: <generic name="interrupt_pin_7_hwtcl" value="inta" />
// Retrieval info: <generic name="maximum_current_7_hwtcl" value="0" />
// Retrieval info: <generic name="disable_snoop_packet_7_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_vga_enable_7_hwtcl" value="false" />
// Retrieval info: <generic name="bridge_port_ssid_support_7_hwtcl" value="false" />
// Retrieval info: <generic name="ssvid_7_hwtcl" value="0" />
// Retrieval info: <generic name="ssid_7_hwtcl" value="0" />
// Retrieval info: <generic name="rpre_emph_a_val_hwtcl" value="12" />
// Retrieval info: <generic name="rpre_emph_b_val_hwtcl" value="0" />
// Retrieval info: <generic name="rpre_emph_c_val_hwtcl" value="19" />
// Retrieval info: <generic name="rpre_emph_d_val_hwtcl" value="13" />
// Retrieval info: <generic name="rpre_emph_e_val_hwtcl" value="21" />
// Retrieval info: <generic name="rvod_sel_a_val_hwtcl" value="42" />
// Retrieval info: <generic name="rvod_sel_b_val_hwtcl" value="30" />
// Retrieval info: <generic name="rvod_sel_c_val_hwtcl" value="43" />
// Retrieval info: <generic name="rvod_sel_d_val_hwtcl" value="43" />
// Retrieval info: <generic name="rvod_sel_e_val_hwtcl" value="9" />
// Retrieval info: </instance>
// IPFS_FILES : pcie_c5_4x.vo
// RELATED_FILES: pcie_c5_4x.v, altpcie_av_hip_ast_hwtcl.v, altpcie_rs_serdes.v, altpcie_rs_hip.v, altpcie_av_hip_128bit_atom.v, altera_xcvr_functions.sv, sv_reconfig_bundle_to_xcvr.sv, sv_reconfig_bundle_to_ip.sv, sv_reconfig_bundle_merger.sv, av_xcvr_h.sv, av_xcvr_avmm_csr.sv, av_tx_pma_ch.sv, av_tx_pma.sv, av_rx_pma.sv, av_pma.sv, av_pcs_ch.sv, av_pcs.sv, av_xcvr_avmm.sv, av_xcvr_native.sv, av_xcvr_plls.sv, av_xcvr_data_adapter.sv, av_reconfig_bundle_to_basic.sv, av_reconfig_bundle_to_xcvr.sv, av_hssi_8g_rx_pcs_rbc.sv, av_hssi_8g_tx_pcs_rbc.sv, av_hssi_common_pcs_pma_interface_rbc.sv, av_hssi_common_pld_pcs_interface_rbc.sv, av_hssi_pipe_gen1_2_rbc.sv, av_hssi_rx_pcs_pma_interface_rbc.sv, av_hssi_rx_pld_pcs_interface_rbc.sv, av_hssi_tx_pcs_pma_interface_rbc.sv, av_hssi_tx_pld_pcs_interface_rbc.sv, alt_reset_ctrl_lego.sv, alt_reset_ctrl_tgx_cdrauto.sv, alt_xcvr_resync.sv, alt_xcvr_csr_common_h.sv, alt_xcvr_csr_common.sv, alt_xcvr_csr_pcs8g_h.sv, alt_xcvr_csr_pcs8g.sv, alt_xcvr_csr_selector.sv, alt_xcvr_mgmt2dec.sv, altera_wait_generate.v, av_xcvr_emsip_adapter.sv, av_xcvr_pipe_native_hip.sv
|
`timescale 1 ns / 1 ps
// This component will read in a column of interest, and hash the value.
module hash_phase (
input clk,
input rst,
output done,
input [63:0] hash_mask_in,
output afull_out,
input write_en_in,
input [63:0] value_in,
output empty_out,
input read_en_in,
output [63:0] value_out,
output [63:0] hash_out
);
wire function_valid_out_s;
wire [63:0] function_data_out_s;
hash_function FUNCTION (
.clk (clk),
.rst (rst),
.valid_in (write_en_in),
.data_in ({32'd0, value_in[63:32]}),
.valid_out (function_valid_out_s),
.data_out (function_data_out_s)
);
wire [1:0] fifo_afull_s;
wire fifo_empty_s;
wire [63:0] hash_fifo_data_out_s;
sync_2_fifo FIFO (
.clk (clk),
.rst (rst),
.afull_out (fifo_afull_s),
.write_en_in ({write_en_in, function_valid_out_s}),
.data_1_in (value_in),
.data_0_in (function_data_out_s),
.empty_out (fifo_empty_s),
.read_en_in (read_en_in),
.data_1_out (value_out),
.data_0_out (hash_fifo_data_out_s)
);
assign hash_out = hash_fifo_data_out_s & hash_mask_in;
assign afull_out = (fifo_afull_s != 2'd0);
assign empty_out = fifo_empty_s;
assign done = fifo_empty_s;
endmodule
|
// ethernet_port_interface_0.v
// Generated using ACDS version 12.0 178 at 2012.08.08.17:01:19
`timescale 1 ps / 1 ps
module ethernet_port_interface_0 (
input wire clk, // clock.clk
input wire reset, // reset.reset
input wire [26:0] control_port_address, // control_port.address
input wire control_port_read, // .read
output wire [31:0] control_port_readdata, // .readdata
input wire control_port_write, // .write
input wire [31:0] control_port_writedata, // .writedata
output wire control_port_waitrequest, // .waitrequest
input wire [7:0] sink_data0, // avalon_streaming_sink.data
output wire sink_ready0, // .ready
input wire sink_valid0, // .valid
input wire [5:0] sink_error0, // .error
input wire sink_startofpacket0, // .startofpacket
input wire sink_endofpacket0, // .endofpacket
output wire [7:0] source_data0, // avalon_streaming_source.data
input wire source_ready0, // .ready
output wire source_valid0, // .valid
output wire source_error0, // .error
output wire source_startofpacket0, // .startofpacket
output wire source_endofpacket0 // .endofpacket
);
ethernet_port_interface ethernet_port_interface_0_inst (
.clk (clk), // clock.clk
.reset (reset), // reset.reset
.control_port_address (control_port_address), // control_port.address
.control_port_read (control_port_read), // .read
.control_port_readdata (control_port_readdata), // .readdata
.control_port_write (control_port_write), // .write
.control_port_writedata (control_port_writedata), // .writedata
.control_port_waitrequest (control_port_waitrequest), // .waitrequest
.sink_data0 (sink_data0), // avalon_streaming_sink.data
.sink_ready0 (sink_ready0), // .ready
.sink_valid0 (sink_valid0), // .valid
.sink_error0 (sink_error0), // .error
.sink_startofpacket0 (sink_startofpacket0), // .startofpacket
.sink_endofpacket0 (sink_endofpacket0), // .endofpacket
.source_data0 (source_data0), // avalon_streaming_source.data
.source_ready0 (source_ready0), // .ready
.source_valid0 (source_valid0), // .valid
.source_error0 (source_error0), // .error
.source_startofpacket0 (source_startofpacket0), // .startofpacket
.source_endofpacket0 (source_endofpacket0) // .endofpacket
);
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4" *)
(* CHECK_LICENSE_TYPE = "base_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "base_zynq_design_auto_pc_0,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=1,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module base_zynq_design_auto_pc_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo_82x256.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo_82x256 (
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input clock;
input [81:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [81:0] q;
output [7:0] usedw;
wire [7:0] sub_wire0;
wire sub_wire1;
wire [81:0] sub_wire2;
wire sub_wire3;
wire [7:0] usedw = sub_wire0[7:0];
wire empty = sub_wire1;
wire [81:0] q = sub_wire2[81:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full (),
.sclr ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 256,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 82,
scfifo_component.lpm_widthu = 8,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "82"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "82"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "82"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 82 0 INPUT NODEFVAL data[81..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 82 0 OUTPUT NODEFVAL q[81..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL usedw[7..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 82 0 data 0 0 82 0
// Retrieval info: CONNECT: q 0 0 82 0 @q 0 0 82 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_82x256_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__INV_PP_BLACKBOX_V
/**
* inv: Inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__inv (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKINV_2_V
`define SKY130_FD_SC_HDLL__CLKINV_2_V
/**
* clkinv: Clock tree inverter.
*
* Verilog wrapper for clkinv with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_2 (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkinv_2 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKINV_2_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__XNOR2_SYMBOL_V
`define SKY130_FD_SC_HVL__XNOR2_SYMBOL_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__xnor2 (
//# {{data|Data Signals}}
input A,
input B,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__XNOR2_SYMBOL_V
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
spdif,
sys_rst,
sys_clk_p,
sys_clk_n,
ddr3_addr,
ddr3_ba,
ddr3_cas_n,
ddr3_ck_n,
ddr3_ck_p,
ddr3_cke,
ddr3_cs_n,
ddr3_dm,
ddr3_dq,
ddr3_dqs_n,
ddr3_dqs_p,
ddr3_odt,
ddr3_ras_n,
ddr3_reset_n,
ddr3_we_n,
iic_scl,
iic_sda,
rx_ref_clk_p,
rx_ref_clk_n,
rx_sysref_p,
rx_sysref_n,
rx_sync_p,
rx_sync_n,
rx_data_p,
rx_data_n,
adc_irq,
adc_fd,
spi_adc_csn,
spi_adc_clk,
spi_adc_sdio,
spi_ext_csn_0,
spi_ext_csn_1,
spi_ext_clk,
spi_ext_sdio);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [14:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [23:0] hdmi_data;
output spdif;
input sys_rst;
input sys_clk_p;
input sys_clk_n;
output [13:0] ddr3_addr;
output [ 2:0] ddr3_ba;
output ddr3_cas_n;
output [ 0:0] ddr3_ck_n;
output [ 0:0] ddr3_ck_p;
output [ 0:0] ddr3_cke;
output [ 0:0] ddr3_cs_n;
output [ 7:0] ddr3_dm;
inout [63:0] ddr3_dq;
inout [ 7:0] ddr3_dqs_n;
inout [ 7:0] ddr3_dqs_p;
output [ 0:0] ddr3_odt;
output ddr3_ras_n;
output ddr3_reset_n;
output ddr3_we_n;
inout iic_scl;
inout iic_sda;
input rx_ref_clk_p;
input rx_ref_clk_n;
output rx_sysref_p;
output rx_sysref_n;
output rx_sync_p;
output rx_sync_n;
input [ 7:0] rx_data_p;
input [ 7:0] rx_data_n;
inout adc_irq;
inout adc_fd;
output spi_adc_csn;
output spi_adc_clk;
inout spi_adc_sdio;
output spi_ext_csn_0;
output spi_ext_csn_1;
output spi_ext_clk;
inout spi_ext_sdio;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
// spi
assign spi_adc_csn = spi0_csn[0];
assign spi_adc_clk = spi0_clk;
assign spi_ext_csn_0 = spi0_csn[1];
assign spi_ext_csn_1 = spi0_csn[2];
assign spi_ext_clk = spi0_clk;
// instantiations
IBUFDS_GTE2 i_ibufds_rx_ref_clk (
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
OBUFDS i_obufds_rx_sysref (
.I (rx_sysref),
.O (rx_sysref_p),
.OB (rx_sysref_n));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
fmcadc2_spi i_fmcadc2_spi (
.spi_adc_csn (spi_adc_csn),
.spi_ext_csn_0 (spi_ext_csn_0),
.spi_ext_csn_1 (spi_ext_csn_1),
.spi_clk (spi0_clk),
.spi_mosi (spi0_mosi),
.spi_miso (spi0_miso),
.spi_adc_sdio (spi_adc_sdio),
.spi_ext_sdio (spi_ext_sdio));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
.dio_t (gpio_t[33:32]),
.dio_i (gpio_o[33:32]),
.dio_o (gpio_i[33:32]),
.dio_p ({ adc_irq, // 33
adc_fd})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_12 (1'b0),
.rx_data_n (rx_data_n),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),
.spi0_csn_0_o (spi0_csn[0]),
.spi0_csn_1_o (spi0_csn[1]),
.spi0_csn_2_o (spi0_csn[2]),
.spi0_csn_i (1'b1),
.spi0_sdi_i (spi0_miso),
.spi0_sdo_i (spi0_mosi),
.spi0_sdo_o (spi0_mosi),
.spi1_clk_i (spi1_clk),
.spi1_clk_o (spi1_clk),
.spi1_csn_0_o (spi1_csn[0]),
.spi1_csn_1_o (spi1_csn[1]),
.spi1_csn_2_o (spi1_csn[2]),
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b1),
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.sys_clk_clk_n (sys_clk_n),
.sys_clk_clk_p (sys_clk_p),
.sys_rst (sys_rst));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2018 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
import "DPI-C" dpii_sys_task = function void \$dpii_sys ();
import "DPI-C" dpii_failure = function int \$dpii_failure ();
module t (clk);
input clk;
integer cyc;
integer failure;
initial cyc = 0;
`ifndef verilator
`error "Only Verilator supports PLI-ish DPI calls."
`endif
always @ (posedge clk) begin
if (cyc == 2) begin
failure = $dpii_failure();
$write("* failure = %0d\n", failure);
if (failure > 0) begin
$stop;
end
$write("*-* All Finished *-*\n");
$finish;
end
cyc <= cyc + 1;
end
// The purpose of this test is to confirm that the DPI-call serialization
// code in V3Partition does ensure that these DPI calls do not run
// concurrently.
//
// Alternatively, the test may be run with "--threads-dpi all" in which case
// it should confirm that the calls do run concurrently and do detect a
// collision (they should, if the test is set up right.) This is
// t_dpi_threads_collide.pl.
//
// Q) Is it a risk that the partitioner will merge or serialize these always
// blocks, just by luck, even if the DPI-call serialization code fails?
//
// A) Yes, that's why t_dpi_threads_collide.pl also passes
// --no-threads-do-coaren to disable MTask coarsening. This ensures that
// the MTask graph at the end of FixDataHazards (where we resolve DPI
// hazards) is basically the final MTasks graph, and that data hazards
// which persist beyond FixDataHazards should persist in the final
// generated C code.
always @ (posedge clk) begin
$dpii_sys();
end
always @ (posedge clk) begin
$dpii_sys();
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__AND4B_FUNCTIONAL_PP_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__and4b (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B, C, D );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND4B_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
module normal_clock_domain(
input clk,
input rst,
output miso,
input mosi,
input ss,
input sclk,
output led_out,
output acq_enable,
output acq_reset,
output clock_select,
output [7:0] clock_divisor,
output [15:0] channel_enable,
input fifo_overflow,
input clklock
);
wire [6:0] reg_num;
wire reg_write;
reg [7:0] reg_data_read;
wire [7:0] reg_data_write;
regaccess reg_file
(
.clk(clk),
.rst(rst),
.ss(ss),
.mosi(mosi),
.miso(miso),
.sck(sclk),
.regnum(reg_num),
.regdata_read(reg_data_read),
.regdata_write(reg_data_write),
.read(),
.write(reg_write)
);
localparam VERSION = 8'h10;
// Registers
localparam REG_VERSION = 'h00;
localparam REG_STATUS_CONTROL = 'h01;
localparam REG_CHANNEL_SELECT_LOW = 'h02;
localparam REG_CHANNEL_SELECT_HIGH = 'h03;
localparam REG_SAMPLE_RATE_DIVISOR = 'h04;
localparam REG_LED_BRIGHTNESS = 'h05;
localparam REG_PRIMER_DATA1 = 'h06;
localparam REG_PRIMER_CONTROL = 'h07;
localparam REG_MODE = 'h0a;
localparam REG_PRIMER_DATA2 = 'h0c;
reg [7:0] led_brightness_d, led_brightness_q;
reg sc_unknown_2_d, sc_unknown_2_q;
reg acq_enable_d, acq_enable_q;
reg acq_reset_d, acq_reset_q;
reg clock_select_d, clock_select_q;
reg [7:0] clock_divisor_d, clock_divisor_q;
reg [7:0] channel_select_low_d, channel_select_low_q;
reg [7:0] channel_select_high_d, channel_select_high_q;
always @(*) begin
led_brightness_d = led_brightness_q;
sc_unknown_2_d = sc_unknown_2_q;
acq_enable_d = acq_enable_q;
acq_reset_d = acq_reset_q;
clock_select_d = clock_select_q;
clock_divisor_d = clock_divisor_q;
channel_select_low_d = channel_select_low_q;
channel_select_high_d = channel_select_high_q;
case (reg_num)
REG_VERSION: reg_data_read = VERSION;
REG_STATUS_CONTROL: begin
reg_data_read = {1'b0, sc_unknown_2_q, fifo_overflow,
1'b0, clklock, 1'b0, acq_reset_q, acq_enable_q };
if (reg_write) begin
sc_unknown_2_d = reg_data_write[6];
acq_enable_d = reg_data_write[0];
acq_reset_d = reg_data_write[1];
end
end
REG_CHANNEL_SELECT_LOW: begin
reg_data_read = channel_select_low_q;
if (reg_write) channel_select_low_d = reg_data_write;
end
REG_CHANNEL_SELECT_HIGH: begin
reg_data_read = channel_select_high_q;
if (reg_write) channel_select_high_d = reg_data_write;
end
REG_SAMPLE_RATE_DIVISOR: begin
reg_data_read = clock_divisor_q;
if (reg_write) clock_divisor_d = reg_data_write;
end
REG_LED_BRIGHTNESS: begin
reg_data_read = led_brightness_q;
if (reg_write) led_brightness_d = reg_data_write;
end
REG_MODE: begin
reg_data_read = { 7'b0000000, clock_select_q };
if (reg_write) begin
clock_select_d = reg_data_write[0];
end
end
default: reg_data_read = 8'b00000000;
endcase
end
always @(posedge clk) begin
if (rst) begin
led_brightness_q <= 8'h00;
sc_unknown_2_q <= 1'b0;
acq_enable_q <= 1'b0;
acq_reset_q <= 1'b0;
clock_select_q <= 1'b0;
clock_divisor_q <= 8'h00;
channel_select_low_q <= 8'h00;
channel_select_high_q <= 8'h00;
end else begin
led_brightness_q <= led_brightness_d;
sc_unknown_2_q <= sc_unknown_2_d;
acq_enable_q <= acq_enable_d;
acq_reset_q <= acq_reset_d;
clock_select_q <= clock_select_d;
clock_divisor_q <= clock_divisor_d;
channel_select_low_q <= channel_select_low_d;
channel_select_high_q <= channel_select_high_d;
end
end
// LED
wire led_pwm_out;
pwm #(18, 8) led_pwm(.clk(clk), .rst(rst), .pulse_width(led_brightness_q),
.out(led_pwm_out));
assign led_out = ~led_pwm_out;
assign acq_enable = acq_enable_q;
assign acq_reset = acq_reset_q | rst;
assign clock_select = clock_select_q;
assign clock_divisor = clock_divisor_q;
assign channel_enable = { channel_select_high_q, channel_select_low_q };
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O2111A_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__O2111A_BEHAVIORAL_PP_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o2111a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , B1, C1, or0_out, D1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O2111A_BEHAVIORAL_PP_V |
// ECE 429
//FIXME: include output port busy
module memory(clock, address, data_in, access_size, rw, enable, busy, data_out);
parameter data_width = 32;
parameter address_width = 32;
parameter depth = 1048576;
// -1 for 0 based indexed
parameter bytes_in_word = 4-1;
parameter bits_in_bytes = 8-1;
parameter BYTE = 8;
parameter start_addr = 32'h80020000;
// Input Ports
input clock;
input [address_width-1:0] address;
input [data_width-1:0] data_in;
input [1:0] access_size;
input rw;
input enable;
// Output Ports
//FIXME: change to output port.
output reg busy;
output reg [data_width-1:0] data_out;
// Create a 1MB deep memory of 8-bits (1 byte) width
reg [7:0] mem[0:depth]; // should be [7:0] since its byte addressible memory
reg [7:0] data;
reg [7:0] byte[3:0];
reg [31:0] global_cur_addr;
reg [31:0] global_cur_addr_write;
reg [31:0] global_cur_addr_read;
integer cyc_ctr = 0;
integer cyc_ctr_write = 0;
integer i = 0;
integer words_written = 0;
integer words_read = 0;
integer write_total_words = 0;
integer read_total_words = 0;
integer fd;
integer status_read, status_write;
integer blah;
reg [31:0] fd_in;
reg [31:0] str;
always @(posedge clock, data_in, rw)
begin : WRITE
// rw = 1
if ((!rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(write_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
mem[address-start_addr+3] <= data_in[7:0];
mem[address-start_addr+2] <= data_in[15:8];
mem[address-start_addr+1] <= data_in[23:16];
mem[address-start_addr] <= data_in[31:24];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
write_total_words = 4;
// skip over the already written bytes
global_cur_addr_write = address-start_addr;
if (words_written < 4) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_written = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
write_total_words = 8;
global_cur_addr_write = address-start_addr;
if (words_written < 8) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
// 11: 16 words
else if (access_size == 2'b1_1) begin
write_total_words = 16;
if (words_written < 16) begin
if (words_written < write_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
mem[global_cur_addr_write+3] <= data_in[7:0];
mem[global_cur_addr_write+2] <= data_in[15:8];
mem[global_cur_addr_write+1] <= data_in[23:16];
mem[global_cur_addr_write] <= data_in[31:24];
words_written <= words_written + 1;
end
else begin
words_written = 0;
end
end
end
end
/*
00: 1 word (4-bytes)
01: 4 words (16-bytes)
10: 8 words (32-bytes)
11: 16 words (64-bytes)
*/
always @(posedge clock, address, rw)
begin : READ
if ((rw && enable)) begin
// busy is to be asserted in case of burst transactions.
if(read_total_words > 1) begin
busy = 1;
end
// this will give busy an initial value.
// Note: This would also be set for burst transactions (which is fine).
else begin
busy = 0;
end
// 00: 1 word
if (access_size == 2'b0_0 ) begin
// read 4 bytes at max in 1 clock cycle.
//assign data_out = {mem[address-start_addr], mem[address-start_addr+1], mem[address-start_addr+2], mem[address-start_addr+3]};
data_out[7:0] <= mem[address-start_addr+3];
data_out[15:8] <= mem[address-start_addr+2];
data_out[23:16] <= mem[address-start_addr+1];
data_out[31:24] <= mem[address-start_addr];
end
// 01: 4 words
else if (access_size == 2'b0_1) begin
read_total_words = 4;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 4) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
// 10: 8 words
else if (access_size == 2'b1_0) begin
read_total_words = 8;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 8) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
// 11: 16 words
end else if (access_size == 2'b1_1) begin
read_total_words = 16;
// skip over the already written bytes
global_cur_addr_read = address-start_addr;
if (words_read < 16) begin
if (words_read < read_total_words - 1) begin
busy = 1;
end
else begin
busy = 0;
end
data_out[7:0] <= mem[global_cur_addr_read+3];
data_out[15:8] <= mem[global_cur_addr_read+2];
data_out[23:16] <= mem[global_cur_addr_read+1];
data_out[31:24] <= mem[global_cur_addr_read];
words_read <= words_read + 1;
end
// reset stuff when all words in the access_size window are written.
else begin
words_read = 0;
end
end
end
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_dqs_pad.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_dqs_pad(/*AUTOARG*/
// Outputs
dqs_pad_clk_so, clk_sel, bso,
// Inouts
pad,
// Inputs
vrefcode, vdd_h, update_dr, testmode_l, shift_dr, odt_enable_mask,
mode_ctrl, hiz_n, dram_io_drive_enable, dram_io_drive_data,
dram_io_channel_disabled, dqs_pad_clk_si, dqs_pad_clk_se,
clock_dr, clk, cbu, cbd, bsi
);
//////////////////////////////////////////////////////////////////////////
// INPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input bsi; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbd; // To sstl_pad of dram_sstl_pad.v
input [8:1] cbu; // To sstl_pad of dram_sstl_pad.v
input clk; // To dqs_edgelogic of dram_dqs_edgelogic.v
input clock_dr; // To sstl_pad of dram_sstl_pad.v
input dqs_pad_clk_se; // To dqs_edgelogic of dram_dqs_edgelogic.v
input dqs_pad_clk_si; // To dqs_edgelogic of dram_dqs_edgelogic.v
input dram_io_channel_disabled;// To dqs_edgelogic of dram_dqs_edgelogic.v
input dram_io_drive_data; // To dqs_edgelogic of dram_dqs_edgelogic.v
input dram_io_drive_enable; // To dqs_edgelogic of dram_dqs_edgelogic.v
input hiz_n; // To sstl_pad of dram_sstl_pad.v
input mode_ctrl; // To sstl_pad of dram_sstl_pad.v
input odt_enable_mask; // To sstl_pad of dram_sstl_pad.v
input shift_dr; // To sstl_pad of dram_sstl_pad.v
input testmode_l; // To dqs_edgelogic of dram_dqs_edgelogic.v
input update_dr; // To sstl_pad of dram_sstl_pad.v
input vdd_h; // To sstl_pad of dram_sstl_pad.v
input [7:0] vrefcode; // To sstl_pad of dram_sstl_pad.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// INOUTPUTS
//////////////////////////////////////////////////////////////////////////
inout pad;
//////////////////////////////////////////////////////////////////////////
// OUTPUTS
//////////////////////////////////////////////////////////////////////////
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output bso; // From sstl_pad of dram_sstl_pad.v
output clk_sel; // From dqs_edgelogic of dram_dqs_edgelogic.v
output dqs_pad_clk_so; // From dqs_edgelogic of dram_dqs_edgelogic.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oe; // From dqs_edgelogic of dram_dqs_edgelogic.v
wire to_core; // From sstl_pad of dram_sstl_pad.v
wire to_pad; // From dqs_edgelogic of dram_dqs_edgelogic.v
// End of automatics
//////////////////////////////////////////////////////////////////////////
// CODE
//////////////////////////////////////////////////////////////////////////
// INSTANTIATING PAD LOGIC
dram_dqs_edgelogic dqs_edgelogic(/*AUTOINST*/
// Outputs
.clk_sel(clk_sel),
.dqs_pad_clk_so(dqs_pad_clk_so),
.to_pad(to_pad),
.oe (oe),
// Inputs
.clk (clk),
.testmode_l(testmode_l),
.dqs_pad_clk_se(dqs_pad_clk_se),
.dqs_pad_clk_si(dqs_pad_clk_si),
.dram_io_drive_enable(dram_io_drive_enable),
.dram_io_drive_data(dram_io_drive_data),
.dram_io_channel_disabled(dram_io_channel_disabled),
.to_core(to_core));
// SSTL LOGIC
/*dram_sstl_pad AUTO_TEMPLATE(
.pad (pad),
.oe (oe),
.data_in (to_pad));
*/
dram_sstl_pad sstl_pad(/*AUTOINST*/
// Outputs
.bso (bso),
.to_core (to_core),
// Inouts
.pad (pad), // Templated
// Inputs
.bsi (bsi),
.cbd (cbd[8:1]),
.cbu (cbu[8:1]),
.clock_dr (clock_dr),
.data_in (to_pad), // Templated
.hiz_n (hiz_n),
.mode_ctrl (mode_ctrl),
.odt_enable_mask (odt_enable_mask),
.oe (oe), // Templated
.shift_dr (shift_dr),
.update_dr (update_dr),
.vdd_h (vdd_h),
.vrefcode (vrefcode[7:0]));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10:30:32 03/24/2014
// Design Name:
// Module Name: rom
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// A module used to mimic inst memory, for the EC413 project.
// Returns hardcoded instructions based on the current PC.
//
// DATA_WIDTH: instruction and data width (i.e 32 bits).
//
// IMPORTANT!
// Which test program to use:
// - PROGRAM_1: first simple hello world example.
`define PROGRAM_1
// Change the previous line to try a different program,
// when available.
// ----------------------------------------------------
module rom(
PC,
inst,
clk);
parameter DATA_WIDTH= 32;
`ifdef PROGRAM_1
parameter PROG_LENGTH= 16;
`endif
//-------------Input Ports-----------------------------
input [DATA_WIDTH-1:0] PC;
input clk;
//-------------Output Ports----------------------------
output [DATA_WIDTH-1:0] inst;
reg [DATA_WIDTH-1:0] inst;
//------------Code Starts Here-------------------------
always @(posedge clk)
begin
case(PC)
`ifdef PROGRAM_1
//
// First part:
// Load values into:
// $R0 = -1
// $R1 = 0
// $R2 = 2
// Add $R0 and $R2 and get an answer in $R3:
// -1 + 2 = 1
//
// LI $R0, 0xFFFF
32'h0000_0000 : inst<= 32'b111001_00000_00000_1111111111111111;
// LUI $R0, 0xFFFF
32'h0000_0004: inst<= 32'b111010_00000_00000_1111111111111111;
// LI $R1, 0x0000
32'h0000_0008: inst<= 32'b111001_00001_00000_0000000000000000;
// LUI $R1, 0x0000
32'h0000_000c: inst<= 32'b111010_00001_00000_0000000000000000;
// LI $R2, 0x0002
32'h0000_0010: inst<= 32'b111001_00010_00000_0000000000000010;
// LUI $R2, 0x0000
32'h0000_0014: inst<= 32'b111010_00010_00000_0000000000000000;
// ADD $R3, $R0, $R2
32'h0000_0018: inst<= 32'b010010_00011_00000_00010_00000000000;
//
// Second part: store and load, should store $R3
// (contains 1) into address 5. Then load from
// address 5 into register $R1. $R1 should then
// contain 1.
//
// SWI $R3, [0x5]
32'h0000_001c: inst<= 32'b111100_00011_00000_0000000000000101;
// LWI $R1, [0x5]
32'h0000_0020: inst<= 32'b111011_00001_00000_0000000000000101;
//
// Third part: simple loop test, loop $R0 from -1 to 1
//
// ADDI $R0, $R0, 0x0001
32'h0000_0024: inst<= 32'b110010_00000_00000_0000000000000001;
// SLT $R31, $R0, $R1
32'h0000_0028: inst<= 32'b010111_11111_00000_00001_00000000000;
// BNEZ $R31, 0xFFFD
32'h0000_002c: inst<= 32'b100001_11111_00000_1111111111111101;
//
// Fourth part: test jump by _skipping_ load instructions
// at PCs 13 and 14. Contents of $R0 should still be 1.
// Afterwards 1 is subtracted with SUBI and final output
// should be 0.
//
// J 15
32'h0000_0030: inst<= 32'b000001_00000000000000000000001111;
// LI $R0, 0xFFFF
32'h0000_0034: inst<= 32'b111001_00000_00000_1111111111111111;
// LUI $R0, 0xFFFF
32'h0000_0038: inst<= 32'b111010_00000_00000_1111111111111111;
// SUBI $R0, $R0, 0x0001
32'h0000_003c: inst<= 32'b110011_00000_00000_0000000000000001;
`endif
default: inst<= 0; //NOOP
endcase
end
endmodule
|
`include "freedm_bus/fb_defines.v"
module pyhctrl (
input CLOCK_50,
// KEY
input [0: 0] KEY,
input [17: 0] SW,
output [17: 0] LEDR,
output [10: 0] GPIO,
output [8: 0] LEDG,
output [6:0]HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0,
// Ethernet 0
output ENET0_MDC,
inout ENET0_MDIO,
output ENET0_RESET_N,
output ENET0_GTX_CLK,
input ENET0_TX_CLK,
input ENET0_RX_CLK,
input [3: 0] ENET0_RX_DATA,
input ENET0_RX_DV,
output [3: 0] ENET0_TX_DATA,
output ENET0_TX_EN,
output ENET0_TX_ER,
// Ethernet 1
output ENET1_GTX_CLK,
output ENET1_MDC,
inout ENET1_MDIO,
output ENET1_RESET_N,
input ENET1_TX_CLK,
input ENET1_RX_CLK,
input [3: 0] ENET1_RX_DATA,
input ENET1_RX_DV,
output [3: 0] ENET1_TX_DATA,
output ENET1_TX_EN
);
wire rst;
assign rst = SW[17];
wire mdc;
assign ENET1_MDC = mdc;
assign ENET0_MDC = mdc;
assign ENET0_RESET_N = 1'b1;
assign ENET1_RESET_N = 1'b1;
assign GPIO[0] = ENET0_TX_DATA[0];
assign GPIO[1] = ENET0_TX_DATA[1];
assign GPIO[2] = ENET0_TX_DATA[2];
assign GPIO[3] = ENET0_TX_DATA[3];
assign GPIO[4] = ENET1_RX_DATA[0];
assign GPIO[5] = ENET1_RX_DATA[1];
assign GPIO[6] = ENET1_RX_DATA[2];
assign GPIO[7] = ENET1_RX_DATA[3];
wire clk_tx0_25;
wire clk_tx1_25;
wire clk_rx0_25;
wire clk_rx1_25;
assign clk_tx0_25 = ENET0_TX_CLK;
assign clk_tx1_25 = ENET1_TX_CLK;
assign clk_rx0_25 = ENET0_RX_CLK;
assign clk_rx1_25 = ENET1_RX_CLK;
wire TxStateSoC;
wire [1:0]RxStateDelay;
// generation of start transmitting signal
reg [31:0]TxCnt;
wire TxStartFrm;
assign TxStartFrm = & TxCnt[24:0];
always @ (posedge clk_tx0_25)
begin
if (rst) begin
TxCnt <= 31'b0;
end else if (TxStartFrm )begin
TxCnt <= 31'b0;
end
else
TxCnt <= TxCnt + 1'b1;
end
wire PHYInitEnd;
wire FrameStart;
wire ConfigOK;
wire NumbFrameReceived;
wire DistFrameReceived;
wire DelayFrameReceived;
wire DelayDistFrameReceived;
reg NumbFrameReceived_TXsyn1;
reg DistFrameReceived_TXsyn1;
reg DelayFrameReceived_TXsyn1;
reg DelayDistFrameReceived_TXsyn1;
reg NumbFrameReturned;
reg DistFrameReturned;
reg DelayFrameReturned;
reg DelayDistFrameReturned;
wire TopStateIdle;
wire TopStateNumb;
wire TopStateDist;
wire TopStateDelay;
wire TopStateDelayDist;
wire TopStateData;
wire TopStateWait;
assign LEDR[11] = TopStateIdle;
assign LEDR[12] = TopStateNumb;
assign LEDR[13] = TopStateDist;
assign LEDR[14] = TopStateDelay;
assign LEDR[15] = TopStateDelayDist;
assign LEDR[16] = TopStateData;
assign LEDR[17] = TopStateWait;
/////////////////////////////////////// fb_top state machine /////////////////
fb_topstatem fb_topstatem_INS
(
.clk_top(clk_tx0_25),
.rst(rst),
.SystemEnd(1'b0),
.SystemStart(SW[8]),
.PHYInitEnd(PHYInitEnd),
.NumbFrameReturned(NumbFrameReturned),
.DistFrameReturned(DistFrameReturned),
.DelayFrameReturned(DelayFrameReturned),
.DelayDistFrameReturned(DelayDistFrameReturned),
.ConfigEnd(ConfigOK),
.DataFrameGo(TxStartFrm),
.StateIdle(TopStateIdle),
.StateNumb(TopStateNumb),
.StateDist(TopStateDist),
.StateDelay(TopStateDelay),
.StateDelayDist(TopStateDelayDist),
.StateData(TopStateData),
.StateWait(TopStateWait)
);
//generator FrameStart signal
assign FrameStart = TopStateNumb | TopStateDist | TopStateDelay | TopStateDelayDist | TopStateData;
//synchronizing RX signals to TX clock
always @ (posedge clk_tx0_25 or posedge rst)
begin
if(rst)
begin
NumbFrameReceived_TXsyn1 <= 1'b0;
DistFrameReceived_TXsyn1 <= 1'b0;
DelayFrameReceived_TXsyn1 <= 1'b0;
DelayDistFrameReceived_TXsyn1 <= 1'b0;
NumbFrameReturned <= 1'b0;
DistFrameReturned <= 1'b0;
DelayFrameReturned <= 1'b0;
DelayDistFrameReturned <= 1'b0;
end
else
begin
NumbFrameReceived_TXsyn1 <= NumbFrameReceived;
DistFrameReceived_TXsyn1 <= DistFrameReceived;
DelayFrameReceived_TXsyn1 <= DelayFrameReceived;
DelayDistFrameReceived_TXsyn1 <= DelayDistFrameReceived;
NumbFrameReturned <= NumbFrameReceived_TXsyn1;
DistFrameReturned <= DistFrameReceived_TXsyn1;
DelayFrameReturned <= DelayFrameReceived_TXsyn1;
DelayDistFrameReturned <= DelayDistFrameReceived_TXsyn1;
end
end
/////////////////////////////////////// transmitter mac /////////////////////////////
wire [7:0] TxRamAddr;
wire [7:0] TxData;
fb_txmac fb_txmac_ins(
.MTxClk(clk_tx0_25),
.Reset(rst),
.TxUnderRun(1'b0),
.TxData(TxData),
.TxStartFrm(FrameStart),
.NumbSoC(TopStateNumb),
.DistSoC(TopStateDist),
.DelaySoC(TopStateDelay),
.DelayDistSoC(TopStateDelayDist),
.DataSoC(TopStateData),
/*
.TxStartFrm(TxStartFrm),
.NumbSoC(1'b0),
.DistSoC(1'b0),
.DelaySoC(1'b1),
.DelayDistSoC(1'b0),
.DataSoC(1'b0),
*/
.LastSlaveIDPlus1(8'd2),
.AveSlaveDelay(8'h3e),
.MTxD(ENET0_TX_DATA),
.MTxEn(ENET0_TX_EN),
.MTxErr(ENET0_TX_ER),
// .TxDone(LEDR[1]),
// .TxUsedData(LEDR[2]),
// .WillTransmit(LEDR[3]),
// .StartTxDone(LEDR[4]),
.StateIdle(LEDR[1]),
.StatePreamble(LEDR[2]),
.StateSoC(TxStateSoC),
.StateNumb(LEDR[3]),
.StateDist(LEDR[5:4]),
.StateDelay(LEDR[6]),
.StateDelayDist(LEDR[7]),
.StateData(LEDR[9:8]),
.StateCrc(LEDR[10]),
.TxRamAddr(TxRamAddr)
);
//dual port ram for tx, a port for write from higher level, b port for read from txmac
tx_dual_port_ram_8bit tx_dual_port_ram_8bit_ins(
//.data_a,
.data_b(TxData),
//.addr_a,
.addr_b(TxRamAddr),
//.we_a,
.we_b(1'b0),
.clk(clk_tx0_25),
//.q_a,
.q_b(TxData)
);
//////////////////////////////////// receiver mac /////////////////////////////
wire RxStateIdle;
wire [7:0]RxData;
wire RxValid;
wire [7:0]RxRamAddr;
wire [15:0]DelaySum;
wire [7:0]LastSlaveIDPlus1;
fb_rxmac fb_rxmac_ins
(
.MRxClk(clk_rx1_25),
.MRxDV(ENET1_RX_DV),
.MRxD(ENET1_RX_DATA),
.Reset(rst),
.inLastSlaveIDPlus1(8'd2),
.RxData(RxData),
.RxValid(RxValid),
.RxRamAddr(RxRamAddr),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
.DelaySum(DelaySum),
.NumbFrameReceived(NumbFrameReceived),
.DistFrameReceived(DistFrameReceived),
.DelayFrameReceived(DelayFrameReceived),
.DelayDistFrameReceived(DelayDistFrameReceived),
//.DataFrameReceived(DataFrameReceived),
.StateIdle(RxStateIdle),
//.StateFFS(LEDG[1]),
.StatePreamble(LEDG[1]),
.StateNumb(LEDG[3:2]),
.StateDist(LEDG[5:4]),
.StateDelay(RxStateDelay),
.StateData(LEDG[7:6]),
// .StateFrmCrc(LEDG[8])
//.debug(LEDG[8])
);
LEDnumb LED5(HEX5, LastSlaveIDPlus1[3:0]);
wire [7:0]readFromRxRam8bit;
//dual port ram for rx, a port for write from rxmac, b port for read from higher level
rx_dual_port_ram_8bit rx_dual_port_ram_8bit_ins(
.data_a(RxData),
//.data_b,
.addr_a(RxRamAddr),
.addr_b(SW[7:2]),
.we_a(RxValid),
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(readFromRxRam8bit)
);
reg [5:0]rx_ram_addr1;
always @ (posedge clk_rx1_25 )
begin
if (rst)
begin
rx_ram_addr1 <= 6'b0;
end
else
if (RxStateIdle)
rx_ram_addr1 <= 6'b0;
else
if (ENET1_RX_DV)
begin
if (rx_ram_addr1 < 6'b111110 )
rx_ram_addr1 <= rx_ram_addr1 + 1'b1;
end
end
wire [3:0]readFromRxRam;
rx_data_ram rx_data_ram_ins(
.data_a(ENET1_RX_DATA),
//.data_b,
.addr_a(rx_ram_addr1),
.addr_b(SW[7:2]),
.we_a(ENET1_RX_DV),
.we_b(1'b0),
.clk(clk_rx1_25),
//.q_a,
.q_b(readFromRxRam)
);
LEDnumb LED4(HEX4, readFromRxRam[3:0]);
//////////////////////////// Configration check ////////////////
ConfigCheck ConfigCheck_ins(
.Reset(rst),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
.AveSlaveDelay(AveSlaveDelay),
.ConfigOK(ConfigOK)
);
assign LEDG[8] = ConfigOK;
///////////////////////////////// DELAY CALCULATION //////////////////////
wire clk_100MHz;
wire [15:0] RegLoopDelay;
wire [7:0] AveTransDelay ;
wire [7:0] AveLogicDelay ;
wire [7:0] AveSlaveDelay ;
pll_25to100MHz delay_measure_clock_master
(
.inclk0(clk_rx1_25),
.areset(rst),
.c0(clk_100MHz)
);
DelayCalculator DelayCalculator_ins
(
.Clk_100MHz(clk_100MHz),
.rst(rst),
.StartCounting(ENET0_TX_EN),
.StopCounting(ENET1_RX_DV),
.DelaySum(DelaySum),
.LastSlaveIDPlus1(LastSlaveIDPlus1),
//.LastSlaveIDPlus1(SW[13:11]),
.RegLoopDelay(RegLoopDelay),
.AveTransDelay(AveTransDelay),
.AveLogicDelay(AveLogicDelay),
.AveSlaveDelay(AveSlaveDelay)
);
//// Display all kinds of delay calculation result
reg [7:0]readRxRamOrDelay;
always@ (*)
begin
if(SW[16:14]==3'b001)
readRxRamOrDelay = DelaySum[7:0];
else
if(SW[16:14]==3'b010)
readRxRamOrDelay = RegLoopDelay[7:0];
else
if(SW[16:14]==3'b011)
readRxRamOrDelay = AveTransDelay;
else
if(SW[16:14]==3'b100)
readRxRamOrDelay = AveLogicDelay;
else
if(SW[16:14]==3'b101)
readRxRamOrDelay = AveSlaveDelay;
else
readRxRamOrDelay = readFromRxRam8bit;
end
LEDnumb LED6(HEX6, readRxRamOrDelay[3:0]);
LEDnumb LED7(HEX7, readRxRamOrDelay[7:4]);
//// ///////////////////////////// End of delay calculation /////////////////////////
////////////////////////////////// MI INTERFACE ///////////////////////////////
wire [31:0] command0;
wire [15:0] command_and0;
wire [3: 0] comm_addr0;
wire [15:0] readData0;
wire [15:0] readDataRam0;
phyInital phyInital_ins0 (
.clk(CLOCK_50),
.reset(SW[0]),
.mdc(mdc),
.md_inout0(ENET0_MDIO),
.md_inout1(ENET1_MDIO),
.command(command0),
.command_and(command_and0),
.comm_addr(comm_addr0),
.ram_read_addr(SW[5:2]),
.iniStart(1'b1),
.iniEnd(PHYInitEnd),
//.stateout(LEDR[12:0]),
.readDataoutRam(readDataRam0)
//.busy(LEDG[8]),
//.WCtrlDataStartout(LEDG[7])
);
phyIniCommand0 pyhIniCommands (
.clk(CLOCK_50),
.q(command0),
.addr(comm_addr0)
);
phyIniCommand0_and pyhIniCommands_and (
.clk(CLOCK_50),
.q(command_and0),
.addr(comm_addr0)
);
wire [15:0]readDataRamOrDelay;
assign readDataRamOrDelay = SW[1] ? readDataRam0 : RegLoopDelay;
LEDnumb LED0(HEX0, readDataRamOrDelay[3:0]);
LEDnumb LED1(HEX1, readDataRamOrDelay[7:4]);
LEDnumb LED2(HEX2, readDataRamOrDelay[11:8]);
LEDnumb LED3(HEX3, readDataRamOrDelay[15:12]);
////////////////////////////////// MI INTERFACE END ///////////////////////////////
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD1_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD1_PP_SYMBOL_V
/**
* dlygate4sd1: Delay Buffer 4-stage 0.15um length inner stage gates.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__dlygate4sd1 (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD1_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:19:53 04/11/2016
// Design Name:
// Module Name: Contador_Control_de_Tiempos
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Contador_Control_de_Tiempos(
input reset,
input clk,
input PB_in,
input enable_inicio,
input enable_escribir,
input enable_leer,
input [2:0] estado_m,
output [3:0] c_5
);
reg [5:0] Cuenta_Interna = 0;
reg [3:0] Estado = 0;
reg posicion = 0;
assign c_5 = Estado;
always @(posedge clk )
if (reset)
begin
Estado = 0;
Cuenta_Interna <= 0;
end
else
begin
begin
if ((enable_escribir && PB_in) || enable_inicio || (estado_m==3'd4) )
begin
if (posicion == 1)
begin
posicion <= 0;
Estado = 0;
Cuenta_Interna <= 0;
end
else
begin
case (Estado)
4'd0: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd1;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd1: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd2;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd2: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd3;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd3: if (Cuenta_Interna == 6'd10)
begin
Estado = 4'd4;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd4: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd5;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd5: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd6;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd6: if (Cuenta_Interna == 6'd60 )
begin
Estado = 4'd7;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd7: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd8;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd8: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd9;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd9: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd10;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd10: if (Cuenta_Interna == 6'd50 )
begin
Estado = 4'd11;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd11: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd0;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
default: begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna;
end
endcase
end
end
else
if (enable_leer)
begin
if (posicion == 0)
begin
posicion <= 1;
Estado = 0;
Cuenta_Interna <= 0;
end
else
begin
case (Estado)
4'd0: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd1;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd1: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd2;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd2: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd3;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd3: if (Cuenta_Interna == 6'd10)
begin
Estado = 4'd4;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd4: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd5;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd5: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd6;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd6: if (Cuenta_Interna == 6'd60 )
begin
Estado = 4'd7;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd7: if (Cuenta_Interna == 6'd20 )
begin
Estado = 4'd8;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd8: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd9;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd9: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd10;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd10: if (Cuenta_Interna == 6'd50 )
begin
Estado = 4'd11;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
4'd11: if (Cuenta_Interna == 6'd10 )
begin
Estado = 4'd0;
Cuenta_Interna <= 6'd0;
end
else
begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna + 6'd1;
end
default: begin
Estado = Estado;
Cuenta_Interna <= Cuenta_Interna;
end
endcase
end
end
else
begin
Estado = 0;
Cuenta_Interna <= 0;
end
end
end
endmodule
|
// =============================================================================
// COPYRIGHT NOTICE
// Copyright 2006 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court 408-826-6000 (other locations)
// Hillsboro, OR 97124 web : http://www.latticesemi.com/
// U.S.A email: [email protected]
// =============================================================================/
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_trace.v
// Title : PC Trace and associated logic.
// Dependencies : lm32_include.v, lm32_functions.v
// Version : 6.1.17
// : Initial Release
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// =============================================================================
`include "lm32_include.v"
`include "system_conf.v"
`ifdef CFG_TRACE_ENABLED
module lm32_trace(
// ----- Inputs -------
clk_i,
rst_i,
stb_i,
we_i,
sel_i,
dat_i,
adr_i,
trace_pc,
trace_eid,
trace_eret,
trace_bret,
trace_pc_valid,
trace_exception,
// -- outputs
ack_o,
dat_o);
input clk_i;
input rst_i;
input stb_i;
input we_i;
input [3:0] sel_i;
input [`LM32_WORD_RNG] dat_i;
input [`LM32_WORD_RNG] adr_i;
input [`LM32_PC_RNG] trace_pc;
input [`LM32_EID_RNG] trace_eid;
input trace_eret;
input trace_bret;
input trace_pc_valid;
input trace_exception;
// -- outputs
output ack_o;
output [`LM32_WORD_RNG] dat_o;
reg ovrflw;
function integer clogb2;
input [31:0] value;
begin
for (clogb2 = 0; value > 0; clogb2 = clogb2 + 1)
value = value >> 1;
end
endfunction
// instantiate the trace memory
parameter mem_data_width = `LM32_PC_WIDTH;
parameter mem_addr_width = clogb2(`CFG_TRACE_DEPTH-1);
wire [`LM32_PC_RNG] trace_dat_o;
wire [mem_addr_width-1:0] trace_raddr;
wire [mem_addr_width-1:0] trace_waddr;
reg trace_we;
wire trace_be, trace_last;
wire rw_creg = adr_i[12];
lm32_ram #(.data_width (mem_data_width),
.address_width (mem_addr_width))
trace_mem (.read_clk (clk_i),
.write_clk (clk_i),
.reset (rst_i),
.read_address (adr_i[mem_addr_width+1:2]),
.write_address (trace_waddr),
.enable_read (`TRUE),
.enable_write ((trace_we | trace_be) & trace_pc_valid & !trace_last),
.write_enable (`TRUE),
.write_data (trace_pc),
.read_data (trace_dat_o));
// trigger type & stop type
// trig_type [0] = start capture when bret
// trig_type [1] = start capture when eret
// trig_type [2] = start capture when PC within a range
// trig_type [3] = start when an exception happens (other than breakpoint)
// trig_type [4] = start when a breakpoint exception happens
reg [4:0] trig_type; // at address 0
reg [4:0] stop_type; // at address 16
reg [`LM32_WORD_RNG] trace_len; // at address 4
reg [`LM32_WORD_RNG] pc_low; // at address 8
reg [`LM32_WORD_RNG] pc_high; // at address 12
reg trace_start,trace_stop;
reg ack_o;
reg mem_valid;
reg [`LM32_WORD_RNG] reg_dat_o;
reg started;
reg capturing;
assign dat_o = (rw_creg ? reg_dat_o : trace_dat_o);
initial begin
trig_type <= 0;
stop_type <= 0;
trace_len <= 0;
pc_low <= 0;
pc_high <= 0;
trace_start <= 0;
trace_stop <= 0;
ack_o <= 0;
reg_dat_o <= 0;
mem_valid <= 0;
started <= 0;
capturing <= 0;
end
// the host side control
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE) begin
trig_type <= 0;
trace_stop <= 0;
trace_start <= 0;
pc_low <= 0;
pc_high <= 0;
ack_o <= 0;
end else begin
if (stb_i == `TRUE && ack_o == `FALSE) begin
if (rw_creg) begin // control register access
ack_o <= `TRUE;
if (we_i == `TRUE) begin
case ({adr_i[11:2],2'b0})
// write to trig type
12'd0:
begin
if (sel_i[0]) begin
trig_type[4:0] <= dat_i[4:0];
end
if (sel_i[3]) begin
trace_start <= dat_i[31];
trace_stop <= dat_i[30];
end
end
12'd8:
begin
if (sel_i[3]) pc_low[31:24] <= dat_i[31:24];
if (sel_i[2]) pc_low[23:16] <= dat_i[23:16];
if (sel_i[1]) pc_low[15:8] <= dat_i[15:8];
if (sel_i[0]) pc_low[7:0] <= dat_i[7:0];
end
12'd12:
begin
if (sel_i[3]) pc_high[31:24] <= dat_i[31:24];
if (sel_i[2]) pc_high[23:16] <= dat_i[23:16];
if (sel_i[1]) pc_high[15:8] <= dat_i[15:8];
if (sel_i[0]) pc_high[7:0] <= dat_i[7:0];
end
12'd16:
begin
if (sel_i[0])begin
stop_type[4:0] <= dat_i[4:0];
end
end
endcase
end else begin // read control registers
case ({adr_i[11:2],2'b0})
// read the trig type
12'd0:
reg_dat_o <= {22'b1,capturing,mem_valid,ovrflw,trace_we,started,trig_type};
12'd4:
reg_dat_o <= trace_len;
12'd8:
reg_dat_o <= pc_low;
12'd12:
reg_dat_o <= pc_high;
default:
reg_dat_o <= {27'b0,stop_type};
endcase
end // else: !if(we_i == `TRUE)
end else // read / write memory
if (we_i == `FALSE) begin
ack_o <= `TRUE;
end else
ack_o <= `FALSE;
// not allowed to write to trace memory
end else begin // if (stb_i == `TRUE)
trace_start <= `FALSE;
trace_stop <= `FALSE;
ack_o <= `FALSE;
end // else: !if(stb_i == `TRUE)
end // else: !if(rst_i == `TRUE)
end
wire [`LM32_WORD_RNG] trace_pc_tmp = {trace_pc,2'b0};
// trace state machine
reg [2:0] tstate;
wire pc_in_range = {trace_pc,2'b0} >= pc_low &&
{trace_pc,2'b0} <= pc_high;
assign trace_waddr = trace_len[mem_addr_width-1:0];
wire trace_begin = ((trig_type[0] & trace_bret) ||
(trig_type[1] & trace_eret) ||
(trig_type[2] & pc_in_range & trace_pc_valid) ||
(trig_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) ||
(trig_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT))
);
wire trace_end = (trace_stop ||
(stop_type[0] & trace_bret) ||
(stop_type[1] & trace_eret) ||
(stop_type[2] & !pc_in_range & trace_pc_valid) ||
(stop_type[3] & trace_exception & (trace_eid != `LM32_EID_BREAKPOINT)) ||
(stop_type[4] & trace_exception & (trace_eid == `LM32_EID_BREAKPOINT))
);
assign trace_be = (trace_begin & (tstate == 3'd1));
assign trace_last = (trace_stop & (tstate == 3'd2));
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
if (rst_i == `TRUE) begin
tstate <= 0;
trace_we <= 0;
trace_len <= 0;
ovrflw <= `FALSE;
mem_valid <= 0;
started <= 0;
capturing <= 0;
end else begin
case (tstate)
3'd0:
// start capture
if (trace_start) begin
tstate <= 3'd1;
mem_valid <= 0;
started <= 1;
end
3'd1:
begin
// wait for trigger
if (trace_begin) begin
capturing <= 1;
tstate <= 3'd2;
trace_we <= `TRUE;
trace_len <= 0;
ovrflw <= `FALSE;
end
end // case: 3'd1
3'd2:
begin
if (trace_pc_valid) begin
if (trace_len[mem_addr_width])
trace_len <= 0;
else
trace_len <= trace_len + 1;
end
if (!ovrflw) ovrflw <= trace_len[mem_addr_width];
// wait for stop condition
if (trace_end) begin
tstate <= 3'd0;
trace_we <= 0;
mem_valid <= 1;
started <= 0;
capturing <= 0;
end
end // case: 3'd2
endcase
end // else: !if(rst_i == `TRUE)
end
endmodule
`endif
|
/***************************************************************************************************
** fpga_nes/hw/src/cpu/apu/apu_mixer.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* APU mixer.
***************************************************************************************************/
module apu_mixer
(
input wire clk_in, // system clock signal
input wire rst_in, // reset signal
input wire [3:0] mute_in, // mute specific channels
input wire [3:0] pulse0_in, // pulse 0 channel input
input wire [3:0] pulse1_in, // pulse 1 channel input
input wire [3:0] triangle_in, // triangle channel input
input wire [3:0] noise_in, // noise channel input
output wire audio_out, // mixed audio output
output wire [5:0] dac_audio_out
);
wire [3:0] pulse0;
wire [3:0] pulse1;
wire [3:0] triangle;
wire [3:0] noise;
reg [4:0] pulse_in_total;
reg [5:0] pulse_out;
reg [6:0] tnd_in_total;
reg [5:0] tnd_out;
reg [5:0] mixed_out;
always @*
begin
pulse_in_total = pulse0 + pulse1;
case (pulse_in_total)
5'h00: pulse_out = 6'h00;
5'h01: pulse_out = 6'h01;
5'h02: pulse_out = 6'h01;
5'h03: pulse_out = 6'h02;
5'h04: pulse_out = 6'h03;
5'h05: pulse_out = 6'h03;
5'h06: pulse_out = 6'h04;
5'h07: pulse_out = 6'h05;
5'h08: pulse_out = 6'h05;
5'h09: pulse_out = 6'h06;
5'h0A: pulse_out = 6'h07;
5'h0B: pulse_out = 6'h07;
5'h0C: pulse_out = 6'h08;
5'h0D: pulse_out = 6'h08;
5'h0E: pulse_out = 6'h09;
5'h0F: pulse_out = 6'h09;
5'h10: pulse_out = 6'h0A;
5'h11: pulse_out = 6'h0A;
5'h12: pulse_out = 6'h0B;
5'h13: pulse_out = 6'h0B;
5'h14: pulse_out = 6'h0C;
5'h15: pulse_out = 6'h0C;
5'h16: pulse_out = 6'h0D;
5'h17: pulse_out = 6'h0D;
5'h18: pulse_out = 6'h0E;
5'h19: pulse_out = 6'h0E;
5'h1A: pulse_out = 6'h0F;
5'h1B: pulse_out = 6'h0F;
5'h1C: pulse_out = 6'h0F;
5'h1D: pulse_out = 6'h10;
5'h1E: pulse_out = 6'h10;
default: pulse_out = 6'bxxxxxx;
endcase
tnd_in_total = { triangle, 1'b0 } + { 1'b0, triangle } + { noise, 1'b0 };
case (tnd_in_total)
7'h00: tnd_out = 6'h00;
7'h01: tnd_out = 6'h01;
7'h02: tnd_out = 6'h01;
7'h03: tnd_out = 6'h02;
7'h04: tnd_out = 6'h03;
7'h05: tnd_out = 6'h03;
7'h06: tnd_out = 6'h04;
7'h07: tnd_out = 6'h05;
7'h08: tnd_out = 6'h05;
7'h09: tnd_out = 6'h06;
7'h0A: tnd_out = 6'h07;
7'h0B: tnd_out = 6'h07;
7'h0C: tnd_out = 6'h08;
7'h0D: tnd_out = 6'h08;
7'h0E: tnd_out = 6'h09;
7'h0F: tnd_out = 6'h09;
7'h10: tnd_out = 6'h0A;
7'h11: tnd_out = 6'h0A;
7'h12: tnd_out = 6'h0B;
7'h13: tnd_out = 6'h0B;
7'h14: tnd_out = 6'h0C;
7'h15: tnd_out = 6'h0C;
7'h16: tnd_out = 6'h0D;
7'h17: tnd_out = 6'h0D;
7'h18: tnd_out = 6'h0E;
7'h19: tnd_out = 6'h0E;
7'h1A: tnd_out = 6'h0F;
7'h1B: tnd_out = 6'h0F;
7'h1C: tnd_out = 6'h0F;
7'h1D: tnd_out = 6'h10;
7'h1E: tnd_out = 6'h10;
7'h1F: tnd_out = 6'h11;
7'h20: tnd_out = 6'h11;
7'h21: tnd_out = 6'h11;
7'h22: tnd_out = 6'h12;
7'h23: tnd_out = 6'h12;
7'h24: tnd_out = 6'h12;
7'h25: tnd_out = 6'h13;
7'h26: tnd_out = 6'h13;
7'h27: tnd_out = 6'h14;
7'h28: tnd_out = 6'h14;
7'h29: tnd_out = 6'h14;
7'h2A: tnd_out = 6'h15;
7'h2B: tnd_out = 6'h15;
7'h2C: tnd_out = 6'h15;
7'h2D: tnd_out = 6'h15;
7'h2E: tnd_out = 6'h16;
7'h2F: tnd_out = 6'h16;
7'h30: tnd_out = 6'h16;
7'h31: tnd_out = 6'h17;
7'h32: tnd_out = 6'h17;
7'h33: tnd_out = 6'h17;
7'h34: tnd_out = 6'h17;
7'h35: tnd_out = 6'h18;
7'h36: tnd_out = 6'h18;
7'h37: tnd_out = 6'h18;
7'h38: tnd_out = 6'h19;
7'h39: tnd_out = 6'h19;
7'h3A: tnd_out = 6'h19;
7'h3B: tnd_out = 6'h19;
7'h3C: tnd_out = 6'h1A;
7'h3D: tnd_out = 6'h1A;
7'h3E: tnd_out = 6'h1A;
7'h3F: tnd_out = 6'h1A;
7'h40: tnd_out = 6'h1B;
7'h41: tnd_out = 6'h1B;
7'h42: tnd_out = 6'h1B;
7'h43: tnd_out = 6'h1B;
7'h44: tnd_out = 6'h1B;
7'h45: tnd_out = 6'h1C;
7'h46: tnd_out = 6'h1C;
7'h47: tnd_out = 6'h1C;
7'h48: tnd_out = 6'h1C;
7'h49: tnd_out = 6'h1C;
7'h4A: tnd_out = 6'h1D;
7'h4B: tnd_out = 6'h1D;
default: tnd_out = 6'bxxxxxx;
endcase
mixed_out = pulse_out + tnd_out;
end
//
// Pulse width modulation.
//
reg [5:0] q_pwm_cnt;
wire [5:0] d_pwm_cnt;
always @(posedge clk_in)
begin
if (rst_in)
begin
q_pwm_cnt <= 6'h0;
end
else
begin
q_pwm_cnt <= d_pwm_cnt;
end
end
assign d_pwm_cnt = q_pwm_cnt + 4'h1;
assign pulse0 = (mute_in[0]) ? 4'h0 : pulse0_in;
assign pulse1 = (mute_in[1]) ? 4'h0 : pulse1_in;
assign triangle = (mute_in[2]) ? 4'h0 : triangle_in;
assign noise = (mute_in[3]) ? 4'h0 : noise_in;
assign audio_out = mixed_out > q_pwm_cnt;
assign dac_audio_out = mixed_out;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINV_TB_V
`define SKY130_FD_SC_LP__CLKINV_TB_V
/**
* clkinv: Clock tree inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__clkinv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_lp__clkinv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINV_TB_V
|
module iop_fpga(reset_l, gclk,
spc_pcx_req_pq,
spc_pcx_atom_pq,
spc_pcx_data_pa,
pcx_spc_grant_px,
cpx_spc_data_rdy_cx2,
cpx_spc_data_cx2
);
output [4:0] spc_pcx_req_pq;
output spc_pcx_atom_pq;
output [123:0] spc_pcx_data_pa;
input [4:0] pcx_spc_grant_px;
input cpx_spc_data_rdy_cx2;
input [144:0] cpx_spc_data_cx2;
input reset_l;
input gclk;
// WIRE Definitions for unused outputs
wire spc_sscan_so;
wire spc_scanout0;
wire spc_scanout1;
wire tst_ctu_mbist_done;
wire tst_ctu_mbist_fail;
wire spc_efc_ifuse_data;
wire spc_efc_dfuse_data;
// WIRE Definitions for constraint
wire [3:0] const_cpuid = 4'b0000;
wire [7:0] const_maskid = 8'h20;
wire ctu_tck = 1'b0;
wire ctu_sscan_se = 1'b0;
wire ctu_sscan_snap = 1'b0;
wire [3:0] ctu_sscan_tid = 4'h1;
wire ctu_tst_mbist_enable = 1'b0;
wire efc_spc_fuse_clk1 = 1'b0;
wire efc_spc_fuse_clk2 = 1'b0;
wire efc_spc_ifuse_ashift = 1'b0;
wire efc_spc_ifuse_dshift = 1'b0;
wire efc_spc_ifuse_data = 1'b0;
wire efc_spc_dfuse_ashift = 1'b0;
wire efc_spc_dfuse_dshift = 1'b0;
wire efc_spc_dfuse_data = 1'b0;
wire ctu_tst_macrotest = 1'b0;
wire ctu_tst_scan_disable = 1'b0;
wire ctu_tst_short_chain = 1'b0;
wire global_shift_enable = 1'b0;
wire ctu_tst_scanmode = 1'b0;
wire spc_scanin0 = 1'b0;
wire spc_scanin1 = 1'b0;
// Reset Related Signals
wire cluster_cken;
wire cmp_grst_l;
wire cmp_arst_l;
wire ctu_tst_pre_grst_l;
wire adbginit_l;
wire gdbginit_l;
reg reset_l_int;
reg sync;
// Reset Logic
assign cmp_arst_l = reset_l_int;
assign adbginit_l = reset_l_int;
reg [7:0] reset_delay;
// Synchronize the incoming reset net into the gclk domain
always @(posedge gclk) begin
{reset_l_int, sync} <= {sync, reset_l};
end
always @(posedge gclk) begin
if(~reset_l_int) begin
reset_delay <= 8'b0;
end else
if(reset_delay != 8'hff)
reset_delay <= reset_delay + 8'b1;
end
assign cluster_cken = (reset_delay > 8'd20) ? 1'b1 : 1'b0;
assign ctu_tst_pre_grst_l = (reset_delay > 8'd60) ? 1'b1 : 1'b0;
assign gdbginit_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
assign cmp_grst_l = (reset_delay > 8'd120) ? 1'b1 : 1'b0;
sparc sparc0 (
.spc_pcx_req_pq (spc_pcx_req_pq),
.spc_pcx_atom_pq (spc_pcx_atom_pq),
.spc_pcx_data_pa (spc_pcx_data_pa),
.spc_sscan_so (spc_sscan_so),
.spc_scanout0 (spc_scanout0),
.spc_scanout1 (spc_scanout1),
.tst_ctu_mbist_done (tst_ctu_mbist_done),
.tst_ctu_mbist_fail (tst_ctu_mbist_fail),
.spc_efc_ifuse_data (spc_efc_ifuse_data),
.spc_efc_dfuse_data (spc_efc_dfuse_data),
.pcx_spc_grant_px (pcx_spc_grant_px),
.cpx_spc_data_rdy_cx2 (cpx_spc_data_rdy_cx2),
.cpx_spc_data_cx2 (cpx_spc_data_cx2),
.const_cpuid (const_cpuid),
.const_maskid (const_maskid),
.ctu_tck (ctu_tck),
.ctu_sscan_se (ctu_sscan_se),
.ctu_sscan_snap (ctu_sscan_snap),
.ctu_sscan_tid (ctu_sscan_tid),
.ctu_tst_mbist_enable (ctu_tst_mbist_enable),
.efc_spc_fuse_clk1 (efc_spc_fuse_clk1),
.efc_spc_fuse_clk2 (efc_spc_fuse_clk2),
.efc_spc_ifuse_ashift (efc_spc_ifuse_ashift),
.efc_spc_ifuse_dshift (efc_spc_ifuse_dshift),
.efc_spc_ifuse_data (efc_spc_ifuse_data),
.efc_spc_dfuse_ashift (efc_spc_dfuse_ashift),
.efc_spc_dfuse_dshift (efc_spc_dfuse_dshift),
.efc_spc_dfuse_data (efc_spc_dfuse_data),
.ctu_tst_macrotest (ctu_tst_macrotest),
.ctu_tst_scan_disable (ctu_tst_scan_disable),
.ctu_tst_short_chain (ctu_tst_short_chain),
.global_shift_enable (global_shift_enable),
.ctu_tst_scanmode (ctu_tst_scanmode),
.spc_scanin0 (spc_scanin0),
.spc_scanin1 (spc_scanin1),
.cluster_cken (cluster_cken),
.gclk (gclk),
.cmp_grst_l (cmp_grst_l),
.cmp_arst_l (cmp_arst_l),
.ctu_tst_pre_grst_l (ctu_tst_pre_grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_PP_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__or4bb (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , D_N, C_N );
or or0 (or0_out_X , B, A, nand0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4BB_BEHAVIORAL_PP_V |
// system_acl_iface_acl_kernel_interface.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire kernel_cntrl_waitrequest, // kernel_cntrl.waitrequest
output wire [31:0] kernel_cntrl_readdata, // .readdata
output wire kernel_cntrl_readdatavalid, // .readdatavalid
input wire [0:0] kernel_cntrl_burstcount, // .burstcount
input wire [31:0] kernel_cntrl_writedata, // .writedata
input wire [13:0] kernel_cntrl_address, // .address
input wire kernel_cntrl_write, // .write
input wire kernel_cntrl_read, // .read
input wire [3:0] kernel_cntrl_byteenable, // .byteenable
input wire kernel_cntrl_debugaccess, // .debugaccess
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
input wire [0:0] kernel_irq_from_kernel_irq, // kernel_irq_from_kernel.irq
output wire [1:0] acl_bsp_memorg_kernel_mode, // acl_bsp_memorg_kernel.mode
output wire [1:0] acl_bsp_memorg_host_mode, // acl_bsp_memorg_host.mode
input wire sw_reset_in_reset, // sw_reset_in.reset
input wire kernel_clk_clk, // kernel_clk.clk
output wire sw_reset_export_reset_n, // sw_reset_export.reset_n
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_irq_to_host_irq // kernel_irq_to_host.irq
);
wire reset_controller_sw_reset_out_reset; // reset_controller_sw:reset_out -> [irq_bridge_0:reset, kernel_cra:reset, mm_interconnect_0:kernel_cra_reset_reset_bridge_in_reset_reset, reset_controller_sw_reset_out_reset:in]
wire address_span_extender_0_expanded_master_waitrequest; // mm_interconnect_0:address_span_extender_0_expanded_master_waitrequest -> address_span_extender_0:avm_m0_waitrequest
wire [31:0] address_span_extender_0_expanded_master_readdata; // mm_interconnect_0:address_span_extender_0_expanded_master_readdata -> address_span_extender_0:avm_m0_readdata
wire [29:0] address_span_extender_0_expanded_master_address; // address_span_extender_0:avm_m0_address -> mm_interconnect_0:address_span_extender_0_expanded_master_address
wire address_span_extender_0_expanded_master_read; // address_span_extender_0:avm_m0_read -> mm_interconnect_0:address_span_extender_0_expanded_master_read
wire [3:0] address_span_extender_0_expanded_master_byteenable; // address_span_extender_0:avm_m0_byteenable -> mm_interconnect_0:address_span_extender_0_expanded_master_byteenable
wire address_span_extender_0_expanded_master_readdatavalid; // mm_interconnect_0:address_span_extender_0_expanded_master_readdatavalid -> address_span_extender_0:avm_m0_readdatavalid
wire address_span_extender_0_expanded_master_write; // address_span_extender_0:avm_m0_write -> mm_interconnect_0:address_span_extender_0_expanded_master_write
wire [31:0] address_span_extender_0_expanded_master_writedata; // address_span_extender_0:avm_m0_writedata -> mm_interconnect_0:address_span_extender_0_expanded_master_writedata
wire [0:0] address_span_extender_0_expanded_master_burstcount; // address_span_extender_0:avm_m0_burstcount -> mm_interconnect_0:address_span_extender_0_expanded_master_burstcount
wire [63:0] mm_interconnect_0_kernel_cra_s0_readdata; // kernel_cra:s0_readdata -> mm_interconnect_0:kernel_cra_s0_readdata
wire mm_interconnect_0_kernel_cra_s0_waitrequest; // kernel_cra:s0_waitrequest -> mm_interconnect_0:kernel_cra_s0_waitrequest
wire mm_interconnect_0_kernel_cra_s0_debugaccess; // mm_interconnect_0:kernel_cra_s0_debugaccess -> kernel_cra:s0_debugaccess
wire [29:0] mm_interconnect_0_kernel_cra_s0_address; // mm_interconnect_0:kernel_cra_s0_address -> kernel_cra:s0_address
wire mm_interconnect_0_kernel_cra_s0_read; // mm_interconnect_0:kernel_cra_s0_read -> kernel_cra:s0_read
wire [7:0] mm_interconnect_0_kernel_cra_s0_byteenable; // mm_interconnect_0:kernel_cra_s0_byteenable -> kernel_cra:s0_byteenable
wire mm_interconnect_0_kernel_cra_s0_readdatavalid; // kernel_cra:s0_readdatavalid -> mm_interconnect_0:kernel_cra_s0_readdatavalid
wire mm_interconnect_0_kernel_cra_s0_write; // mm_interconnect_0:kernel_cra_s0_write -> kernel_cra:s0_write
wire [63:0] mm_interconnect_0_kernel_cra_s0_writedata; // mm_interconnect_0:kernel_cra_s0_writedata -> kernel_cra:s0_writedata
wire [0:0] mm_interconnect_0_kernel_cra_s0_burstcount; // mm_interconnect_0:kernel_cra_s0_burstcount -> kernel_cra:s0_burstcount
wire kernel_cntrl_m0_waitrequest; // mm_interconnect_1:kernel_cntrl_m0_waitrequest -> kernel_cntrl:m0_waitrequest
wire [31:0] kernel_cntrl_m0_readdata; // mm_interconnect_1:kernel_cntrl_m0_readdata -> kernel_cntrl:m0_readdata
wire kernel_cntrl_m0_debugaccess; // kernel_cntrl:m0_debugaccess -> mm_interconnect_1:kernel_cntrl_m0_debugaccess
wire [13:0] kernel_cntrl_m0_address; // kernel_cntrl:m0_address -> mm_interconnect_1:kernel_cntrl_m0_address
wire kernel_cntrl_m0_read; // kernel_cntrl:m0_read -> mm_interconnect_1:kernel_cntrl_m0_read
wire [3:0] kernel_cntrl_m0_byteenable; // kernel_cntrl:m0_byteenable -> mm_interconnect_1:kernel_cntrl_m0_byteenable
wire kernel_cntrl_m0_readdatavalid; // mm_interconnect_1:kernel_cntrl_m0_readdatavalid -> kernel_cntrl:m0_readdatavalid
wire [31:0] kernel_cntrl_m0_writedata; // kernel_cntrl:m0_writedata -> mm_interconnect_1:kernel_cntrl_m0_writedata
wire kernel_cntrl_m0_write; // kernel_cntrl:m0_write -> mm_interconnect_1:kernel_cntrl_m0_write
wire [0:0] kernel_cntrl_m0_burstcount; // kernel_cntrl:m0_burstcount -> mm_interconnect_1:kernel_cntrl_m0_burstcount
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_readdata; // address_span_extender_0:avs_s0_readdata -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest; // address_span_extender_0:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_0_windowed_slave_waitrequest
wire [9:0] mm_interconnect_1_address_span_extender_0_windowed_slave_address; // mm_interconnect_1:address_span_extender_0_windowed_slave_address -> address_span_extender_0:avs_s0_address
wire mm_interconnect_1_address_span_extender_0_windowed_slave_read; // mm_interconnect_1:address_span_extender_0_windowed_slave_read -> address_span_extender_0:avs_s0_read
wire [3:0] mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_0_windowed_slave_byteenable -> address_span_extender_0:avs_s0_byteenable
wire mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid; // address_span_extender_0:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdatavalid
wire mm_interconnect_1_address_span_extender_0_windowed_slave_write; // mm_interconnect_1:address_span_extender_0_windowed_slave_write -> address_span_extender_0:avs_s0_write
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_0_windowed_slave_writedata -> address_span_extender_0:avs_s0_writedata
wire [0:0] mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_0_windowed_slave_burstcount -> address_span_extender_0:avs_s0_burstcount
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_readdata; // address_span_extender_0:avs_cntl_readdata -> mm_interconnect_1:address_span_extender_0_cntl_readdata
wire mm_interconnect_1_address_span_extender_0_cntl_read; // mm_interconnect_1:address_span_extender_0_cntl_read -> address_span_extender_0:avs_cntl_read
wire [7:0] mm_interconnect_1_address_span_extender_0_cntl_byteenable; // mm_interconnect_1:address_span_extender_0_cntl_byteenable -> address_span_extender_0:avs_cntl_byteenable
wire mm_interconnect_1_address_span_extender_0_cntl_write; // mm_interconnect_1:address_span_extender_0_cntl_write -> address_span_extender_0:avs_cntl_write
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_writedata; // mm_interconnect_1:address_span_extender_0_cntl_writedata -> address_span_extender_0:avs_cntl_writedata
wire mm_interconnect_1_sys_description_rom_s1_chipselect; // mm_interconnect_1:sys_description_rom_s1_chipselect -> sys_description_rom:chipselect
wire [63:0] mm_interconnect_1_sys_description_rom_s1_readdata; // sys_description_rom:readdata -> mm_interconnect_1:sys_description_rom_s1_readdata
wire mm_interconnect_1_sys_description_rom_s1_debugaccess; // mm_interconnect_1:sys_description_rom_s1_debugaccess -> sys_description_rom:debugaccess
wire [8:0] mm_interconnect_1_sys_description_rom_s1_address; // mm_interconnect_1:sys_description_rom_s1_address -> sys_description_rom:address
wire [7:0] mm_interconnect_1_sys_description_rom_s1_byteenable; // mm_interconnect_1:sys_description_rom_s1_byteenable -> sys_description_rom:byteenable
wire mm_interconnect_1_sys_description_rom_s1_write; // mm_interconnect_1:sys_description_rom_s1_write -> sys_description_rom:write
wire [63:0] mm_interconnect_1_sys_description_rom_s1_writedata; // mm_interconnect_1:sys_description_rom_s1_writedata -> sys_description_rom:writedata
wire mm_interconnect_1_sys_description_rom_s1_clken; // mm_interconnect_1:sys_description_rom_s1_clken -> sys_description_rom:clken
wire [63:0] mm_interconnect_1_sw_reset_s_readdata; // sw_reset:slave_readdata -> mm_interconnect_1:sw_reset_s_readdata
wire mm_interconnect_1_sw_reset_s_waitrequest; // sw_reset:slave_waitrequest -> mm_interconnect_1:sw_reset_s_waitrequest
wire mm_interconnect_1_sw_reset_s_read; // mm_interconnect_1:sw_reset_s_read -> sw_reset:slave_read
wire [7:0] mm_interconnect_1_sw_reset_s_byteenable; // mm_interconnect_1:sw_reset_s_byteenable -> sw_reset:slave_byteenable
wire mm_interconnect_1_sw_reset_s_write; // mm_interconnect_1:sw_reset_s_write -> sw_reset:slave_write
wire [63:0] mm_interconnect_1_sw_reset_s_writedata; // mm_interconnect_1:sw_reset_s_writedata -> sw_reset:slave_writedata
wire [31:0] mm_interconnect_1_mem_org_mode_s_readdata; // mem_org_mode:slave_readdata -> mm_interconnect_1:mem_org_mode_s_readdata
wire mm_interconnect_1_mem_org_mode_s_waitrequest; // mem_org_mode:slave_waitrequest -> mm_interconnect_1:mem_org_mode_s_waitrequest
wire mm_interconnect_1_mem_org_mode_s_read; // mm_interconnect_1:mem_org_mode_s_read -> mem_org_mode:slave_read
wire mm_interconnect_1_mem_org_mode_s_write; // mm_interconnect_1:mem_org_mode_s_write -> mem_org_mode:slave_write
wire [31:0] mm_interconnect_1_mem_org_mode_s_writedata; // mm_interconnect_1:mem_org_mode_s_writedata -> mem_org_mode:slave_writedata
wire [31:0] mm_interconnect_1_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_1:version_id_0_s_readdata
wire mm_interconnect_1_version_id_0_s_read; // mm_interconnect_1:version_id_0_s_read -> version_id_0:slave_read
wire [31:0] mm_interconnect_1_irq_ena_0_s_readdata; // irq_ena_0:slave_readdata -> mm_interconnect_1:irq_ena_0_s_readdata
wire mm_interconnect_1_irq_ena_0_s_waitrequest; // irq_ena_0:slave_waitrequest -> mm_interconnect_1:irq_ena_0_s_waitrequest
wire mm_interconnect_1_irq_ena_0_s_read; // mm_interconnect_1:irq_ena_0_s_read -> irq_ena_0:slave_read
wire [3:0] mm_interconnect_1_irq_ena_0_s_byteenable; // mm_interconnect_1:irq_ena_0_s_byteenable -> irq_ena_0:slave_byteenable
wire mm_interconnect_1_irq_ena_0_s_write; // mm_interconnect_1:irq_ena_0_s_write -> irq_ena_0:slave_write
wire [31:0] mm_interconnect_1_irq_ena_0_s_writedata; // mm_interconnect_1:irq_ena_0_s_writedata -> irq_ena_0:slave_writedata
wire irq_mapper_receiver0_irq; // irq_bridge_0:sender0_irq -> irq_mapper:receiver0_irq
wire irq_ena_0_my_irq_in_irq; // irq_mapper:sender_irq -> irq_ena_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_ena_0:resetn, kernel_cntrl:reset, mem_org_mode:resetn, mm_interconnect_1:kernel_cntrl_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sys_description_rom:reset, version_id_0:resetn]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [rst_translator:reset_req_in, sys_description_rom:reset_req]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_0:reset, mm_interconnect_0:address_span_extender_0_reset_reset_bridge_in_reset_reset, mm_interconnect_1:address_span_extender_0_reset_reset_bridge_in_reset_reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_1:sw_reset_clk_reset_reset_bridge_in_reset_reset, sw_reset:resetn]
system_acl_iface_acl_kernel_interface_sys_description_rom sys_description_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_1_sys_description_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (64),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cra (
.clk (kernel_clk_clk), // clk.clk
.reset (reset_controller_sw_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_kernel_cra_s0_address), // .address
.s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cra_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cra_readdata), // .readdata
.m0_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cra_burstcount), // .burstcount
.m0_writedata (kernel_cra_writedata), // .writedata
.m0_address (kernel_cra_address), // .address
.m0_write (kernel_cra_write), // .write
.m0_read (kernel_cra_read), // .read
.m0_byteenable (kernel_cra_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
altera_address_span_extender #(
.DATA_WIDTH (32),
.BYTEENABLE_WIDTH (4),
.MASTER_ADDRESS_WIDTH (30),
.SLAVE_ADDRESS_WIDTH (10),
.SLAVE_ADDRESS_SHIFT (2),
.BURSTCOUNT_WIDTH (1),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_0 (
.clk (kernel_clk_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_0_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_0_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_0_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.avs_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // cntl.read
.avs_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.avs_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // .write
.avs_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.avs_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.avs_cntl_address (1'b0) // (terminated)
);
sw_reset #(
.WIDTH (64),
.LOG2_RESET_CYCLES (10)
) sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (sw_reset_export_reset_n) // sw_reset.reset_n
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (14),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cntrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (kernel_cntrl_waitrequest), // s0.waitrequest
.s0_readdata (kernel_cntrl_readdata), // .readdata
.s0_readdatavalid (kernel_cntrl_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_cntrl_burstcount), // .burstcount
.s0_writedata (kernel_cntrl_writedata), // .writedata
.s0_address (kernel_cntrl_address), // .address
.s0_write (kernel_cntrl_write), // .write
.s0_read (kernel_cntrl_read), // .read
.s0_byteenable (kernel_cntrl_byteenable), // .byteenable
.s0_debugaccess (kernel_cntrl_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cntrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.m0_address (kernel_cntrl_m0_address), // .address
.m0_write (kernel_cntrl_m0_write), // .write
.m0_read (kernel_cntrl_m0_read), // .read
.m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.s0_response (), // (terminated)
.m0_response (2'b00) // (terminated)
);
mem_org_mode #(
.WIDTH (32)
) mem_org_mode (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_mem_org_mode_s_write), // s.write
.slave_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.slave_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.slave_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.mem_organization_kernel (acl_bsp_memorg_kernel_mode), // mem_organization_kernel.mode
.mem_organization_host (acl_bsp_memorg_host_mode) // mem_organization_host.mode
);
altera_irq_bridge #(
.IRQ_WIDTH (1)
) irq_bridge_0 (
.clk (kernel_clk_clk), // clk.clk
.receiver_irq (kernel_irq_from_kernel_irq), // receiver_irq.irq
.reset (reset_controller_sw_reset_out_reset), // clk_reset.reset
.sender0_irq (irq_mapper_receiver0_irq), // sender0_irq.irq
.sender1_irq (), // (terminated)
.sender2_irq (), // (terminated)
.sender3_irq (), // (terminated)
.sender4_irq (), // (terminated)
.sender5_irq (), // (terminated)
.sender6_irq (), // (terminated)
.sender7_irq (), // (terminated)
.sender8_irq (), // (terminated)
.sender9_irq (), // (terminated)
.sender10_irq (), // (terminated)
.sender11_irq (), // (terminated)
.sender12_irq (), // (terminated)
.sender13_irq (), // (terminated)
.sender14_irq (), // (terminated)
.sender15_irq (), // (terminated)
.sender16_irq (), // (terminated)
.sender17_irq (), // (terminated)
.sender18_irq (), // (terminated)
.sender19_irq (), // (terminated)
.sender20_irq (), // (terminated)
.sender21_irq (), // (terminated)
.sender22_irq (), // (terminated)
.sender23_irq (), // (terminated)
.sender24_irq (), // (terminated)
.sender25_irq (), // (terminated)
.sender26_irq (), // (terminated)
.sender27_irq (), // (terminated)
.sender28_irq (), // (terminated)
.sender29_irq (), // (terminated)
.sender30_irq (), // (terminated)
.sender31_irq () // (terminated)
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_1_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) reset_controller_sw (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~sw_reset_export_reset_n), // reset_in1.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (reset_controller_sw_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
irq_ena irq_ena_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_irq_ena_0_s_write), // s.write
.slave_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.slave_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.irq (irq_ena_0_my_irq_in_irq), // my_irq_in.irq
.irq_out (kernel_irq_to_host_irq) // my_irq_out.irq
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0 mm_interconnect_0 (
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cra_reset_reset_bridge_in_reset_reset (reset_controller_sw_reset_out_reset), // kernel_cra_reset_reset_bridge_in_reset.reset
.address_span_extender_0_expanded_master_address (address_span_extender_0_expanded_master_address), // address_span_extender_0_expanded_master.address
.address_span_extender_0_expanded_master_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.address_span_extender_0_expanded_master_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.address_span_extender_0_expanded_master_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.address_span_extender_0_expanded_master_read (address_span_extender_0_expanded_master_read), // .read
.address_span_extender_0_expanded_master_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.address_span_extender_0_expanded_master_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_0_expanded_master_write (address_span_extender_0_expanded_master_write), // .write
.address_span_extender_0_expanded_master_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.kernel_cra_s0_address (mm_interconnect_0_kernel_cra_s0_address), // kernel_cra_s0.address
.kernel_cra_s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.kernel_cra_s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.kernel_cra_s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.kernel_cra_s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.kernel_cra_s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.kernel_cra_s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.kernel_cra_s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.kernel_cra_s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // .waitrequest
.kernel_cra_s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess) // .debugaccess
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1 mm_interconnect_1 (
.clk_reset_clk_clk (clk_clk), // clk_reset_clk.clk
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cntrl_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // kernel_cntrl_reset_reset_bridge_in_reset.reset
.sw_reset_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sw_reset_clk_reset_reset_bridge_in_reset.reset
.kernel_cntrl_m0_address (kernel_cntrl_m0_address), // kernel_cntrl_m0.address
.kernel_cntrl_m0_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.kernel_cntrl_m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.kernel_cntrl_m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.kernel_cntrl_m0_read (kernel_cntrl_m0_read), // .read
.kernel_cntrl_m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.kernel_cntrl_m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.kernel_cntrl_m0_write (kernel_cntrl_m0_write), // .write
.kernel_cntrl_m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.kernel_cntrl_m0_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.address_span_extender_0_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // address_span_extender_0_cntl.write
.address_span_extender_0_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // .read
.address_span_extender_0_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.address_span_extender_0_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.address_span_extender_0_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // address_span_extender_0_windowed_slave.address
.address_span_extender_0_windowed_slave_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.address_span_extender_0_windowed_slave_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.address_span_extender_0_windowed_slave_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.address_span_extender_0_windowed_slave_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.address_span_extender_0_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.address_span_extender_0_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_0_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.irq_ena_0_s_write (mm_interconnect_1_irq_ena_0_s_write), // irq_ena_0_s.write
.irq_ena_0_s_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.irq_ena_0_s_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.irq_ena_0_s_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.irq_ena_0_s_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.irq_ena_0_s_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.mem_org_mode_s_write (mm_interconnect_1_mem_org_mode_s_write), // mem_org_mode_s.write
.mem_org_mode_s_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.mem_org_mode_s_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.mem_org_mode_s_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.mem_org_mode_s_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.sw_reset_s_write (mm_interconnect_1_sw_reset_s_write), // sw_reset_s.write
.sw_reset_s_read (mm_interconnect_1_sw_reset_s_read), // .read
.sw_reset_s_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.sw_reset_s_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.sw_reset_s_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.sw_reset_s_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sys_description_rom_s1_address (mm_interconnect_1_sys_description_rom_s1_address), // sys_description_rom_s1.address
.sys_description_rom_s1_write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.sys_description_rom_s1_readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.sys_description_rom_s1_writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.sys_description_rom_s1_byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.sys_description_rom_s1_chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.sys_description_rom_s1_clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.sys_description_rom_s1_debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.version_id_0_s_read (mm_interconnect_1_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (irq_ena_0_my_irq_in_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (sw_reset_in_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_reset_reset_n = ~reset_controller_sw_reset_out_reset;
endmodule
|
module rom8kx16 (
input [12 : 0] addr,
input clk,
output [15 : 0] dout);
//
// Generate 8 blocks of memory 8k x 2.
// Initialize memory contents from rom-init-*.v files.
//
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-a.v"
) rom_1_0 (.DO (dout[1:0]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-b.v"
) rom_3_2 (.DO (dout[3:2]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-c.v"
) rom_5_4 (.DO (dout[5:4]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-d.v"
) rom_7_6 (.DO (dout[7:6]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-e.v"
) rom_9_8 (.DO (dout[9:8]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-f.v"
) rom_11_10 (.DO (dout[11:10]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-g.v"
) rom_13_12 (.DO (dout[13:12]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
RAMB16_S2 #(.INIT (2'b00), .SRVAL (2'b00), .WRITE_MODE ("WRITE_FIRST"),
`include "rom-init-h.v"
) rom_15_14 (.DO (dout[15:14]), .ADDR (addr), .CLK (clk),
.DI (0), .EN (1), .SSR (0), .WE (0));
endmodule
|
// file: Master_Clock_Divider.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1____50.000______0.000______50.0______129.198_____89.971
// clk_out2___100.000______0.000______50.0______112.316_____89.971
// clk_out3___200.000______0.000______50.0_______98.146_____89.971
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________200.000____________0.010
`timescale 1ps/1ps
module Master_Clock_Divider_clk_wiz
(// Clock in ports
// Clock out ports
output clk_out1,
output clk_out2,
output clk_out3,
// Status and control signals
input reset,
output locked,
input clk_in1_p,
input clk_in1_n
);
// Input buffering
//------------------------------------
wire clk_in1_Master_Clock_Divider;
wire clk_in2_Master_Clock_Divider;
IBUFDS clkin1_ibufgds
(.O (clk_in1_Master_Clock_Divider),
.I (clk_in1_p),
.IB (clk_in1_n));
// Clocking PRIMITIVE
//------------------------------------
// Instantiation of the MMCM PRIMITIVE
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire clk_out1_Master_Clock_Divider;
wire clk_out2_Master_Clock_Divider;
wire clk_out3_Master_Clock_Divider;
wire clk_out4_Master_Clock_Divider;
wire clk_out5_Master_Clock_Divider;
wire clk_out6_Master_Clock_Divider;
wire clk_out7_Master_Clock_Divider;
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire locked_int;
wire clkfbout_Master_Clock_Divider;
wire clkfbout_buf_Master_Clock_Divider;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
wire reset_high;
MMCME2_ADV
#(.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (5.000),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (20.000),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (10),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (5),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5.0))
mmcm_adv_inst
// Output clocks
(
.CLKFBOUT (clkfbout_Master_Clock_Divider),
.CLKFBOUTB (clkfboutb_unused),
.CLKOUT0 (clk_out1_Master_Clock_Divider),
.CLKOUT0B (clkout0b_unused),
.CLKOUT1 (clk_out2_Master_Clock_Divider),
.CLKOUT1B (clkout1b_unused),
.CLKOUT2 (clk_out3_Master_Clock_Divider),
.CLKOUT2B (clkout2b_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT3B (clkout3b_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
.CLKOUT6 (clkout6_unused),
// Input clock control
.CLKFBIN (clkfbout_buf_Master_Clock_Divider),
.CLKIN1 (clk_in1_Master_Clock_Divider),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (psdone_unused),
// Other control and status signals
.LOCKED (locked_int),
.CLKINSTOPPED (clkinstopped_unused),
.CLKFBSTOPPED (clkfbstopped_unused),
.PWRDWN (1'b0),
.RST (reset_high));
assign reset_high = reset;
assign locked = locked_int;
// Clock Monitor clock assigning
//--------------------------------------
// Output buffering
//-----------------------------------
BUFG clkf_buf
(.O (clkfbout_buf_Master_Clock_Divider),
.I (clkfbout_Master_Clock_Divider));
BUFG clkout1_buf
(.O (clk_out1),
.I (clk_out1_Master_Clock_Divider));
BUFG clkout2_buf
(.O (clk_out2),
.I (clk_out2_Master_Clock_Divider));
BUFG clkout3_buf
(.O (clk_out3),
.I (clk_out3_Master_Clock_Divider));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10.10.2017 12:17:10
// Design Name:
// Module Name: pc_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module pc_tb();
reg clk;
reg SaltoCond;
reg [31:0] extSigno;
reg oZero;
reg reset;
//salida
wire [31:0] direinstru;
pc uut(
.clk(clk),
.SaltoCond(SaltoCond),
.extSigno(extSigno),
.oZero(oZero),
.direinstru(direinstru),
.reset(reset)
);
always
begin
clk=1'b1;
#50
clk=1'b0;
#50;
end
initial begin
//initial inputs
reset = 1'b1;
extSigno = 32'b0000_0000_0000_0000_0000_0000_0000_0000;
oZero=1'b0;
SaltoCond = 1'b0;
#100
reset = 1'b0;
#100//200
oZero=1'b0;
SaltoCond = 1'b0;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
//wait 100ns
#100 //300
oZero = 1'b1;
SaltoCond=1'b0;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100 //400
oZero=1'b0;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100//500
oZero=1'b1;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100//600
oZero=1'b1;
SaltoCond=1'b1;
extSigno=32'b0000_0000_0000_0000_0000_0000_0000_0001;
#100;
end
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
// Parameters used for fsm states
parameter WIN_UNCHANGE_START = 1'b0;
parameter WIN_UNCHANGE_CHECK = 1'b1;
//------------------------------------------------------------------------------
// SHARED CODE
//------------------------------------------------------------------------------
`ifdef OVL_SHARED_CODE
reg [width-1:0] r_test_expr;
reg r_state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
r_state <= WIN_UNCHANGE_START;
// r_test_expr deliberately not reset
end
else begin
r_test_expr <= test_expr;
case (r_state)
WIN_UNCHANGE_START: if (start_event == 1'b1) begin
r_state <= WIN_UNCHANGE_CHECK;
end
WIN_UNCHANGE_CHECK: if (end_event == 1'b1) begin
r_state <= WIN_UNCHANGE_START;
end
endcase
end
end
`endif
//------------------------------------------------------------------------------
// ASSERTION
//------------------------------------------------------------------------------
`ifdef OVL_ASSERT_ON
// 2-STATE
// =======
wire fire_2state_1;
reg fire_2state;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_2state <= 1'b0;
end
else begin
if (fire_2state_1) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression has changed value before the event window closes");
fire_2state <= ovl_fire_2state_f(property_type);
end
else begin
fire_2state <= 1'b0;
end
end
end
assign fire_2state_1 = ((r_state == WIN_UNCHANGE_CHECK) && (r_test_expr != test_expr));
// X-CHECK
// =======
`ifdef OVL_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
wire fire_xcheck = 1'b0;
`else
reg fire_xcheck_1, fire_xcheck_2, fire_xcheck_3;
reg fire_xcheck;
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_xcheck <= 1'b0;
end
else begin
if (fire_xcheck_1) begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
if (fire_xcheck_2) begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
if (fire_xcheck_3) begin
ovl_error_t(`OVL_FIRE_XCHECK,"end_event contains X or Z");
end
if (fire_xcheck_1 || fire_xcheck_2 || fire_xcheck_3) begin
fire_xcheck <= ovl_fire_xcheck_f(property_type);
end
else begin
fire_xcheck <= 1'b0;
end
end
end
wire valid_start_event = ((start_event ^ start_event) == 1'b0);
wire valid_test_expr = ((test_expr ^ test_expr) == {width{1'b0}});
wire valid_end_event = ((end_event ^ end_event) == 1'b0);
always @ (valid_start_event or r_state) begin
if (valid_start_event || (r_state != WIN_UNCHANGE_START)) begin
fire_xcheck_1 = 1'b0;
end
else begin
fire_xcheck_1 = 1'b1; // start_event X when r_state is WIN_UNCHANGE_START
end
end
always @ (valid_test_expr or r_state or start_event) begin
if (valid_test_expr || !((r_state == WIN_UNCHANGE_CHECK) || start_event)) begin
fire_xcheck_2 = 1'b0;
end
else begin
fire_xcheck_2 = 1'b1; // test_expr X when r_state is CHECK or start_event high
end
end
always @ (valid_end_event or r_state) begin
if (valid_end_event || (r_state != WIN_UNCHANGE_CHECK)) begin
fire_xcheck_3 = 1'b0;
end
else begin
fire_xcheck_3 = 1'b1; // end_event X when r_state is WIN_UNCHANGE_CHECK
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`else
wire fire_2state = 1'b0;
wire fire_xcheck = 1'b0;
`endif // OVL_ASSERT_ON
//------------------------------------------------------------------------------
// COVERAGE
//------------------------------------------------------------------------------
`ifdef OVL_COVER_ON
wire fire_cover_1, fire_cover_2;
reg fire_cover;
always @ (posedge clk) begin
if (`OVL_RESET_SIGNAL == 1'b0) begin
// OVL does not fire during reset
fire_cover <= 1'b0;
end
else begin
if (fire_cover_1) begin
ovl_cover_t("window_open covered"); // basic
end
if (fire_cover_2) begin
ovl_cover_t("window covered"); // basic
end
if (fire_cover_1 || fire_cover_2) begin
fire_cover <= 1'b1;
end
else begin
fire_cover <= 1'b0;
end
end
end
assign fire_cover_1 = ((OVL_COVER_BASIC_ON > 0) && (start_event == 1'b1) && (r_state == WIN_UNCHANGE_START));
assign fire_cover_2 = ((OVL_COVER_BASIC_ON > 0) && (end_event == 1'b1) && (r_state == WIN_UNCHANGE_CHECK));
`else
wire fire_cover = 1'b0;
`endif // OVL_COVER_ON
|
/*
Copyright (c) 2013 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* AXI4-Stream FIFO
*/
module axis_fifo #
(
parameter ADDR_WIDTH = 12,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire rst,
/*
* AXI input
*/
input wire [DATA_WIDTH-1:0] input_axis_tdata,
input wire input_axis_tvalid,
output wire input_axis_tready,
input wire input_axis_tlast,
input wire input_axis_tuser,
/*
* AXI output
*/
output wire [DATA_WIDTH-1:0] output_axis_tdata,
output wire output_axis_tvalid,
input wire output_axis_tready,
output wire output_axis_tlast,
output wire output_axis_tuser
);
reg [ADDR_WIDTH:0] wr_ptr = {ADDR_WIDTH+1{1'b0}};
reg [ADDR_WIDTH:0] rd_ptr = {ADDR_WIDTH+1{1'b0}};
reg [DATA_WIDTH+2-1:0] data_out_reg = {1'b0, 1'b0, {DATA_WIDTH{1'b0}}};
//(* RAM_STYLE="BLOCK" *)
reg [DATA_WIDTH+2-1:0] mem[(2**ADDR_WIDTH)-1:0];
reg output_read = 1'b0;
reg output_axis_tvalid_reg = 1'b0;
wire [DATA_WIDTH+2-1:0] data_in = {input_axis_tlast, input_axis_tuser, input_axis_tdata};
// full when first MSB different but rest same
wire full = ((wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &&
(wr_ptr[ADDR_WIDTH-1:0] == rd_ptr[ADDR_WIDTH-1:0]));
// empty when pointers match exactly
wire empty = wr_ptr == rd_ptr;
wire write = input_axis_tvalid & ~full;
wire read = (output_axis_tready | ~output_axis_tvalid_reg) & ~empty;
assign {output_axis_tlast, output_axis_tuser, output_axis_tdata} = data_out_reg;
assign input_axis_tready = ~full;
assign output_axis_tvalid = output_axis_tvalid_reg;
// write
always @(posedge clk or posedge rst) begin
if (rst) begin
wr_ptr <= 0;
end else if (write) begin
mem[wr_ptr[ADDR_WIDTH-1:0]] <= data_in;
wr_ptr <= wr_ptr + 1;
end
end
// read
always @(posedge clk or posedge rst) begin
if (rst) begin
rd_ptr <= 0;
end else if (read) begin
data_out_reg <= mem[rd_ptr[ADDR_WIDTH-1:0]];
rd_ptr <= rd_ptr + 1;
end
end
// source ready output
always @(posedge clk or posedge rst) begin
if (rst) begin
output_axis_tvalid_reg <= 1'b0;
end else if (output_axis_tready | ~output_axis_tvalid_reg) begin
output_axis_tvalid_reg <= ~empty;
end else begin
output_axis_tvalid_reg <= output_axis_tvalid_reg;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__FILL_8_V
`define SKY130_FD_SC_HVL__FILL_8_V
/**
* fill: Fill cell.
*
* Verilog wrapper for fill with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__fill.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__fill base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__fill_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__fill base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__FILL_8_V
|
// megafunction wizard: %altmemphy v10.0%
// GENERATION: XML
// ============================================================
// Megafunction Name(s):
// ddr3_int_phy_alt_mem_phy
// ============================================================
// Generated by altmemphy 10.0 [Altera, IP Toolbench 1.3.0 Build 262]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module ddr3_int_phy (
pll_ref_clk,
global_reset_n,
soft_reset_n,
ctl_dqs_burst,
ctl_wdata_valid,
ctl_wdata,
ctl_dm,
ctl_addr,
ctl_ba,
ctl_cas_n,
ctl_cke,
ctl_cs_n,
ctl_odt,
ctl_ras_n,
ctl_we_n,
ctl_rst_n,
ctl_mem_clk_disable,
ctl_doing_rd,
ctl_cal_req,
ctl_cal_byte_lane_sel_n,
oct_ctl_rs_value,
oct_ctl_rt_value,
dqs_offset_delay_ctrl,
dqs_delay_ctrl_import,
dbg_clk,
dbg_reset_n,
dbg_addr,
dbg_wr,
dbg_rd,
dbg_cs,
dbg_wr_data,
reset_request_n,
ctl_clk,
ctl_reset_n,
ctl_wlat,
ctl_rdata,
ctl_rdata_valid,
ctl_rlat,
ctl_cal_success,
ctl_cal_fail,
ctl_cal_warning,
mem_addr,
mem_ba,
mem_cas_n,
mem_cke,
mem_cs_n,
mem_dm,
mem_odt,
mem_ras_n,
mem_we_n,
mem_reset_n,
dqs_delay_ctrl_export,
dll_reference_clk,
dbg_rd_data,
dbg_waitrequest,
aux_half_rate_clk,
aux_full_rate_clk,
mem_clk,
mem_clk_n,
mem_dq,
mem_dqs,
mem_dqs_n);
input pll_ref_clk;
input global_reset_n;
input soft_reset_n;
input [7:0] ctl_dqs_burst;
input [7:0] ctl_wdata_valid;
input [127:0] ctl_wdata;
input [15:0] ctl_dm;
input [27:0] ctl_addr;
input [5:0] ctl_ba;
input [1:0] ctl_cas_n;
input [1:0] ctl_cke;
input [1:0] ctl_cs_n;
input [1:0] ctl_odt;
input [1:0] ctl_ras_n;
input [1:0] ctl_we_n;
input [1:0] ctl_rst_n;
input [0:0] ctl_mem_clk_disable;
input [7:0] ctl_doing_rd;
input ctl_cal_req;
input [3:0] ctl_cal_byte_lane_sel_n;
input [13:0] oct_ctl_rs_value;
input [13:0] oct_ctl_rt_value;
input [5:0] dqs_offset_delay_ctrl;
input [5:0] dqs_delay_ctrl_import;
input dbg_clk;
input dbg_reset_n;
input [12:0] dbg_addr;
input dbg_wr;
input dbg_rd;
input dbg_cs;
input [31:0] dbg_wr_data;
output reset_request_n;
output ctl_clk;
output ctl_reset_n;
output [4:0] ctl_wlat;
output [127:0] ctl_rdata;
output [1:0] ctl_rdata_valid;
output [4:0] ctl_rlat;
output ctl_cal_success;
output ctl_cal_fail;
output ctl_cal_warning;
output [13:0] mem_addr;
output [2:0] mem_ba;
output mem_cas_n;
output [0:0] mem_cke;
output [0:0] mem_cs_n;
output [3:0] mem_dm;
output [0:0] mem_odt;
output mem_ras_n;
output mem_we_n;
output mem_reset_n;
output [5:0] dqs_delay_ctrl_export;
output dll_reference_clk;
output [31:0] dbg_rd_data;
output dbg_waitrequest;
output aux_half_rate_clk;
output aux_full_rate_clk;
inout [0:0] mem_clk;
inout [0:0] mem_clk_n;
inout [31:0] mem_dq;
inout [3:0] mem_dqs;
inout [3:0] mem_dqs_n;
ddr3_int_phy_alt_mem_phy ddr3_int_phy_alt_mem_phy_inst(
.pll_ref_clk(pll_ref_clk),
.global_reset_n(global_reset_n),
.soft_reset_n(soft_reset_n),
.ctl_dqs_burst(ctl_dqs_burst),
.ctl_wdata_valid(ctl_wdata_valid),
.ctl_wdata(ctl_wdata),
.ctl_dm(ctl_dm),
.ctl_addr(ctl_addr),
.ctl_ba(ctl_ba),
.ctl_cas_n(ctl_cas_n),
.ctl_cke(ctl_cke),
.ctl_cs_n(ctl_cs_n),
.ctl_odt(ctl_odt),
.ctl_ras_n(ctl_ras_n),
.ctl_we_n(ctl_we_n),
.ctl_rst_n(ctl_rst_n),
.ctl_mem_clk_disable(ctl_mem_clk_disable),
.ctl_doing_rd(ctl_doing_rd),
.ctl_cal_req(ctl_cal_req),
.ctl_cal_byte_lane_sel_n(ctl_cal_byte_lane_sel_n),
.oct_ctl_rs_value(oct_ctl_rs_value),
.oct_ctl_rt_value(oct_ctl_rt_value),
.dqs_offset_delay_ctrl(dqs_offset_delay_ctrl),
.dqs_delay_ctrl_import(dqs_delay_ctrl_import),
.dbg_clk(dbg_clk),
.dbg_reset_n(dbg_reset_n),
.dbg_addr(dbg_addr),
.dbg_wr(dbg_wr),
.dbg_rd(dbg_rd),
.dbg_cs(dbg_cs),
.dbg_wr_data(dbg_wr_data),
.reset_request_n(reset_request_n),
.ctl_clk(ctl_clk),
.ctl_reset_n(ctl_reset_n),
.ctl_wlat(ctl_wlat),
.ctl_rdata(ctl_rdata),
.ctl_rdata_valid(ctl_rdata_valid),
.ctl_rlat(ctl_rlat),
.ctl_cal_success(ctl_cal_success),
.ctl_cal_fail(ctl_cal_fail),
.ctl_cal_warning(ctl_cal_warning),
.mem_addr(mem_addr),
.mem_ba(mem_ba),
.mem_cas_n(mem_cas_n),
.mem_cke(mem_cke),
.mem_cs_n(mem_cs_n),
.mem_dm(mem_dm),
.mem_odt(mem_odt),
.mem_ras_n(mem_ras_n),
.mem_we_n(mem_we_n),
.mem_reset_n(mem_reset_n),
.dqs_delay_ctrl_export(dqs_delay_ctrl_export),
.dll_reference_clk(dll_reference_clk),
.dbg_rd_data(dbg_rd_data),
.dbg_waitrequest(dbg_waitrequest),
.aux_half_rate_clk(aux_half_rate_clk),
.aux_full_rate_clk(aux_full_rate_clk),
.mem_clk(mem_clk),
.mem_clk_n(mem_clk_n),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dqs_n(mem_dqs_n));
defparam
ddr3_int_phy_alt_mem_phy_inst.FAMILY = "Arria II GX",
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_MEMTYPE = "DDR3",
ddr3_int_phy_alt_mem_phy_inst.DLL_DELAY_BUFFER_MODE = "HIGH",
ddr3_int_phy_alt_mem_phy_inst.DLL_DELAY_CHAIN_LENGTH = 10,
ddr3_int_phy_alt_mem_phy_inst.DQS_DELAY_CTL_WIDTH = 6,
ddr3_int_phy_alt_mem_phy_inst.DQS_OUT_MODE = "DELAY_CHAIN2",
ddr3_int_phy_alt_mem_phy_inst.DQS_PHASE = 7200,
ddr3_int_phy_alt_mem_phy_inst.DQS_PHASE_SETTING = 2,
ddr3_int_phy_alt_mem_phy_inst.DWIDTH_RATIO = 4,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_DWIDTH = 32,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_ADDR_WIDTH = 14,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_BANKADDR_WIDTH = 3,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_CS_WIDTH = 1,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_CS_PER_RANK = 1,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_DM_WIDTH = 4,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_DM_PINS_EN = 1,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_DQ_PER_DQS = 8,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_DQS_WIDTH = 4,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_OCT_EN = 0,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_CLK_PAIR_COUNT = 1,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_CLK_PS = 3333,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_CLK_PS_STR = "3333 ps",
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_MR_0 = 4673,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_MR_1 = 70,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_MR_2 = 8,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_MR_3 = 0,
ddr3_int_phy_alt_mem_phy_inst.PLL_STEPS_PER_CYCLE = 32,
ddr3_int_phy_alt_mem_phy_inst.SCAN_CLK_DIVIDE_BY = 2,
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_DQSN_EN = 1,
ddr3_int_phy_alt_mem_phy_inst.DLL_EXPORT_IMPORT = "EXPORT",
ddr3_int_phy_alt_mem_phy_inst.MEM_IF_ADDR_CMD_PHASE = 90,
ddr3_int_phy_alt_mem_phy_inst.RANK_HAS_ADDR_SWAP = 0,
ddr3_int_phy_alt_mem_phy_inst.INVERT_POSTAMBLE_CLK = "false";
endmodule
// =========================================================
// altmemphy Wizard Data
// ===============================
// DO NOT EDIT FOLLOWING DATA
// @Altera, IP Toolbench@
// Warning: If you modify this section, altmemphy Wizard may not be able to reproduce your chosen configuration.
//
// Retrieval info: <?xml version="1.0"?>
// Retrieval info: <MEGACORE title="ALTMEMPHY" version="10.0" build="198" iptb_version="1.3.0 Build 262" format_version="120" >
// Retrieval info: <NETLIST_SECTION class="altera.ipbu.flowbase.netlist.model.DDRPHYMVCModel" active_core="ddr3_int_phy_alt_mem_phy" >
// Retrieval info: <STATIC_SECTION>
// Retrieval info: <PRIVATES>
// Retrieval info: <NAMESPACE name = "parameterization">
// Retrieval info: <PRIVATE name = "pipeline_commands" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "debug_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_debug_port" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "use_generated_memory_model" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase_label" value="Dedicated memory clock phase:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_mhz" value="300.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "quartus_project_exists" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_drate" value="Half" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_v72_rsu" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_clk_mhz_label" value="150.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "new_variant" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_memtype" value="DDR3 SDRAM" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_mhz" value="25.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_ps_label" value="(3333 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "project_family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "speed_grade" value="5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_phase" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_ref_clk_ps_label" value="(40000 ps)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "avalon_burst_length" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_clk_pair_count" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_dimm" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pre_latency_label" value="Fix read latency at:" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dedicated_memory_clk_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mirror_addressing" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_bankaddr_width" value="3" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_9" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_rowaddr_width" value="14" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dyn_deskew_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "post_latency_label" value="cycles (0 cycles=minimum latency, non-deterministic)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dm_pins_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_dwidth_label" value="128" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_7" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_8" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset" value="Custom (Micron MT41J64M16LA-15E)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_pchaddr_bit" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "WIDTH_RATIO" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "vendor" value="Micron" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_3" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_4" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "chip_or_dimm" value="Discrete Device" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_5" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_6" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_fmax" value="666.666" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_0" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_size" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_1" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_2" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_11" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_10" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_width" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_preset_rlat" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_cs_per_rank" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "fast_simulation_en" value="FAST" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_15" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_14" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dwidth" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dq_per_dqs" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_coladdr_width" value="10" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_13" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "register_control_word_12" value="0000" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tiha_ps" value="240" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsh_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trfc_ns" value="110.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqh_ck" value="0.38" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tisa_ps" value="340" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdss_ck" value="0.2" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trtp_ns" value="7.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tinit_us" value="500.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trcd_ns" value="13.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twtr_ck" value="4" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_trrd_ns" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqss_ck" value="0.25" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tqhs_ps" value="300" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdsa_ps" value="180" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tac_ps" value="400" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdha_ps" value="165" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tras_ns" value="36.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_twr_ns" value="15.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsck_ps" value="255" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trp_ns" value="13.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tdqsq_ps" value="125" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_tmrd_ns" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tfaw_ns" value="30.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_trefi_us" value="7.8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_40_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_odt" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_str" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "input_period" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QH_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_QHS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_30_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_clk_select" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSQ_percent" value="0.65" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "pll_reconfig_ports_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_btype" value="Sequential" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl" value="8.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSS_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "export_bank_info" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSS_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_en" value="Yes" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ac_phase" value="90" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_oct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_60_fmax" value="400.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DSH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_if_dqsn_en" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enable_mp_calibration" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_IH_percent" value="0.6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_15_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dll_external" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_bl" value="On the fly" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_WLS_percent" value="0.7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_50_fmax" value="333.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mp_DQSCK_percent" value="0.5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_25_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_20_fmax" value="533.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_ecc_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_hrb_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ref_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "multicast_wr_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_cycles" value="0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_self_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "shared_sys_clk_source" value="XX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_latency" value="5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "tool_context" value="STANDALONE" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_addr_mapping" value="CHIP_ROW_BANK_COL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "burst_merge_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "user_refresh_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "qsys_mode" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "clk_source_sharing_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_lookahead_depth" value="8" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_autopch_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ctl_dynamic_bank_allocation" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "local_if_type_avalon" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "csr_en" value="false" type="STRING" enable="1" />
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// Retrieval info: <PRIVATE name = "ctl_auto_correct_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "auto_powerdn_en" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "phy_if_type_afi" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "controller_type" value="ddrx_ctl" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "max_local_size" value="32" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_srtr" value="Normal" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_loc" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dss_tinit_rst_us" value="200.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_90_fmax" value="666.666" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_wr" value="Dynamic ODT off" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_100_fmax" value="666.666" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_pasr" value="Full Array" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_asrm" value="Manual SR Reference (SRT)" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_mpr_oper" value="Predefined Pattern" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_80_fmax" value="533.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_drv_impedance" value="RZQ/7" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_rtt_nom" value="RZQ/6" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_tcl_70_fmax" value="533.333" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_wtcl" value="6.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_dll_pch" value="Fast exit" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "mem_atcl" value="Disabled" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_settings_valid" value="true" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH" value="0.219" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_intra_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQS" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "addr_cmd_slew_rate" value="3.47" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_tpd_inter_DIMM" value="0.05" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_addresscmd_CK_skew" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS_calculated" value="0.192" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_hold" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS" value="0.203" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "restore_default_toggle" value="false" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dqs_dqsn_slew_rate" value="4.103" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "dq_slew_rate" value="1.75" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_inter_DQS_group_skew" value="0.02" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_addresscmd_setup" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_minCK_DQS_skew" value="-0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IS_calculated" value="0.203" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "num_slots_or_devices" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_maxCK_DQS_skew" value="0.01" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "board_skew_ps" value="20" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH" value="0.164" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "ck_ckn_slew_rate" value="4.853" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "isi_DQ" value="0.0" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_IH_calculated" value="0.219" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DH_calculated" value="0.164" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "t_DS" value="0.193" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen">
// Retrieval info: <PRIVATE name = "use_alt_top" value="1" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "alt_top" value="ddr3_int_phy_alt_mem_phy_seq_wrapper" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "filename" value="ddr3_int_phy_alt_mem_phy_seq_wrapper.vo" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen2">
// Retrieval info: <PRIVATE name = "family" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "command" value="--simgen_arbitrary_blackbox=+ddr3_int_phy_alt_mem_phy_seq_wrapper;+ddr3_int_phy_alt_mem_phy_reconfig;+ddr3_int_phy_alt_mem_phy_pll;+ddr3_int_phy_alt_mem_phy_delay;+ddr3_int_phy_alt_mem_phy_dq_dqs --ini=simgen_tri_bus_opt=on" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "parameter" value="SIMGEN_INITIALIZATION_FILE=/home/u/univ_avion/max_core_2d/hdl/altera_ddr3_128/ddr3_int_phy_simgen_init.txt" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "simgen_enable">
// Retrieval info: <PRIVATE name = "language" value="Verilog HDL" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "enabled" value="0" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "qip">
// Retrieval info: <PRIVATE name = "gx_libs" value="1" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "greybox">
// Retrieval info: <PRIVATE name = "filename" value="ddr3_int_phy_syn.v" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "quartus_settings">
// Retrieval info: <PRIVATE name = "DEVICE" value="EP2AGX95EF29C5" type="STRING" enable="1" />
// Retrieval info: <PRIVATE name = "FAMILY" value="Arria II GX" type="STRING" enable="1" />
// Retrieval info: </NAMESPACE>
// Retrieval info: <NAMESPACE name = "serializer"/>
// Retrieval info: </PRIVATES>
// Retrieval info: <FILES/>
// Retrieval info: <PORTS/>
// Retrieval info: <LIBRARIES/>
// Retrieval info: </STATIC_SECTION>
// Retrieval info: </NETLIST_SECTION>
// Retrieval info: </MEGACORE>
// =========================================================
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
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//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: cmd_gen.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:41:58 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module genreates different type of commands, address,
// burst_length to mcb_flow_control module.
//Reference:
//Revision History:
// Nov14 2008. Added constraints for generating PRBS_BL when
// generated address is too close to end of address space.
// The BL will be force to 1 to avoid across other port's space.
// April 2 2009 Fixed Sequential Address Circuit to avoide generate any address
// beyond the allowed address range.
// Oct 22 2009 Fixed BRAM interface.
// Fixed run_traffic stop and go problem.
// Merged V6 and SP6 specific requirements.
// Modified syntax for VHDL Formality comparison.
//*****************************************************************************
`timescale 1ps/1ps
`define RD 3'b001;
`define RDP 3'b011;
`define WR 3'b000;
`define WRP 3'b010;
`define REFRESH 3'b100;
module cmd_gen #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 8,
parameter PORT_MODE = "BI_MODE",
parameter NUM_DQ_PINS = 8,
parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
parameter ADDR_WIDTH = 30,
parameter DWIDTH = 32,
parameter PIPE_STAGES = 0,
parameter MEM_COL_WIDTH = 10, // memory column width
parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
parameter PRBS_SADDR_MASK_POS = 32'h00002000,
parameter PRBS_EADDR = 32'h00002000,
parameter PRBS_SADDR = 32'h00002000
)
(
input clk_i,
input [9:0] rst_i,
input run_traffic_i,
// runtime parameter
input [6:0] rd_buff_avail_i,
input force_wrcmd_gen_i,
input [31:0] start_addr_i, // define the start of address
input [31:0] end_addr_i,
input [31:0] cmd_seed_i, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
input [31:0] data_seed_i,
input load_seed_i, //
// upper layer inputs to determine the command bus and data pattern
// internal traffic generator initialize the memory with
input [2:0] addr_mode_i, // "00" = bram; takes the address from bram output
// "01" = fixed address from the fixed_addr input
// "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "11" = sequential
input [3:0] data_mode_i, // 4'b0010:address as data
// 4'b0011:DGEN_HAMMER
// 4'b0100:DGEN_NEIGHBOUR
// 4'b0101:DGEN_WALKING1
// 4'b0110:DGEN_WALKING0
// 4'b0111:PRBS_DATA
// for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
// in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
input [3:0] instr_mode_i, // "0000" = bram; takes instruction from bram output
// "0001" = fixed instr from fixed instr input
// "0010" = R/W
// "0011" = RP/WP
// "0100" = R/RP/W/WP
// "0101" = R/RP/W/WP/REF
// "0110" = PRBS
input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output
// "01" = fixed , takes the burst length from the fixed_bl input
// "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
input mode_load_i,
// fixed pattern inputs interface
input [5:0] fixed_bl_i, // range from 1 to 64
input [2:0] fixed_instr_i, //RD 3'b001
//RDP 3'b011
//WR 3'b000
//WRP 3'b010
//REFRESH 3'b100
input [31:0] fixed_addr_i, // only upper 30 bits will be used
// BRAM FIFO input
input [31:0] bram_addr_i, //
input [2:0] bram_instr_i,
input [5:0] bram_bl_i,
input bram_valid_i,
output bram_rdy_o,
input reading_rd_data_i,
// mcb_flow_control interface
input rdy_i,
output [31:0] addr_o, // generated address
output [2:0] instr_o, // generated instruction
output [5:0] bl_o, // generated instruction
output reg [31:0] m_addr_o,
output cmd_o_vld // valid commands when asserted
);
localparam PRBS_ADDR_WIDTH = 32;
localparam INSTR_PRBS_WIDTH = 16;
localparam BL_PRBS_WIDTH = 16;
localparam BRAM_DATAL_MODE = 4'b0000;
localparam FIXED_DATA_MODE = 4'b0001;
localparam ADDR_DATA_MODE = 4'b0010;
localparam HAMMER_DATA_MODE = 4'b0011;
localparam NEIGHBOR_DATA_MODE = 4'b0100;
localparam WALKING1_DATA_MODE = 4'b0101;
localparam WALKING0_DATA_MODE = 4'b0110;
localparam PRBS_DATA_MODE = 4'b0111;
reg [10:0] INC_COUNTS;
reg [2:0] addr_mode_reg;
reg [1:0] bl_mode_reg;
reg [31:0] addr_counts;
reg [31:0] addr_counts_next_r;
wire [14:0] prbs_bl;
reg [2:0] instr_out;
wire [14:0] prbs_instr_a;
wire [14:0] prbs_instr_b;
reg [5:0] prbs_brlen;
wire [31:0] prbs_addr;
wire [31:0] seq_addr;
wire [31:0] fixed_addr;
reg [31:0] addr_out ;
reg [5:0] bl_out;
reg [5:0] bl_out_reg;
reg mode_load_d1;
reg mode_load_d2;
reg mode_load_pulse;
wire [41:0] pipe_data_o;
wire cmd_clk_en;
wire pipe_out_vld;
reg [15:0] end_addr_range;
reg force_bl1;
reg A0_G_E0;
reg A1_G_E1;
reg A2_G_E2;
reg A3_G_E3;
reg AC3_G_E3;
reg AC2_G_E2;
reg AC1_G_E1;
reg bl_out_clk_en;
reg [41:0] pipe_data_in;
reg instr_vld;
reg bl_out_vld;
reg pipe_data_in_vld;
reg gen_addr_larger ;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg [15:0] rd_data_received_counts_total;
reg instr_vld_dly1;
reg first_load_pulse;
reg mem_init_done;
reg refresh_cmd_en ;
reg [9:0] refresh_timer;
reg refresh_prbs;
reg cmd_vld;
reg run_traffic_r;
reg run_traffic_pulse;
always @ (posedge clk_i)
begin
run_traffic_r <= #TCQ run_traffic_i;
if ( run_traffic_i && ~run_traffic_r )
run_traffic_pulse <= #TCQ 1'b1;
else
run_traffic_pulse <= #TCQ 1'b0;
end
// commands go through pipeline inserters
assign addr_o = pipe_data_o[31:0];
assign instr_o = pipe_data_o[34:32];
assign bl_o = pipe_data_o[40:35];
assign cmd_o_vld = pipe_data_o[41] & run_traffic_r;
assign pipe_out_vld = pipe_data_o[41] & run_traffic_r;
assign pipe_data_o = pipe_data_in;
always @(posedge clk_i) begin
instr_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse));
bl_out_clk_en <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse));
bl_out_vld <= #TCQ bl_out_clk_en;
pipe_data_in_vld <= #TCQ instr_vld;
end
always @ (posedge clk_i) begin
if (rst_i[0])
first_load_pulse <= #TCQ 1'b1;
else if (mode_load_pulse)
first_load_pulse <= #TCQ 1'b0;
else
first_load_pulse <= #TCQ first_load_pulse;
end
generate
if (CMD_PATTERN == "CGEN_BRAM") begin: cv1
always @(posedge clk_i) begin
cmd_vld <= #TCQ (cmd_clk_en );
end
end endgenerate
generate
if (CMD_PATTERN != "CGEN_BRAM") begin: cv2
always @(posedge clk_i) begin
cmd_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse ));
end
end endgenerate
assign cmd_clk_en = ( rdy_i & pipe_out_vld & run_traffic_i || mode_load_pulse && (CMD_PATTERN == "CGEN_BRAM"));
integer i;
generate
if (FAMILY == "SPARTAN6") begin: pipe_in_s6
always @ (posedge clk_i) begin
if (rst_i[0])
pipe_data_in[31:0] <= #TCQ start_addr_i;
else if (instr_vld)
if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010))
if (DWIDTH == 32)
pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0};
else if (DWIDTH == 64)
pipe_data_in[31:0] <= #TCQ {end_addr_i[31:9],9'h0};
else
pipe_data_in[31:0] <= #TCQ {end_addr_i[31:10],10'h0};
else begin
if (DWIDTH == 32)
pipe_data_in[31:0] <= #TCQ {addr_out[31:2],2'b00} ;
else if (DWIDTH == 64)
pipe_data_in[31:0] <= #TCQ {addr_out[31:3],3'b000} ;
else if (DWIDTH == 128)
pipe_data_in[31:0] <= #TCQ {addr_out[31:4],4'b0000} ;
end
end
end endgenerate
generate
if (FAMILY == "VIRTEX6") begin: pipe_in_v6
always @ (posedge clk_i) begin
if (rst_i[1])
pipe_data_in[31:0] <= #TCQ start_addr_i;
else if (instr_vld)
// address
if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) //(AC3_G_E3 && AC2_G_E2 && AC1_G_E1 )
pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0};
else if ((NUM_DQ_PINS >= 128) && (NUM_DQ_PINS <= 144))
begin
if (MEM_BURST_LEN == 8)
pipe_data_in[31:0] <= #TCQ {addr_out[31:7], 7'b0000000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000000};
end
else if ((NUM_DQ_PINS >= 64) && (NUM_DQ_PINS < 128))
begin
if (MEM_BURST_LEN == 8)
pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:5], 5'b00000};
end
else if ((NUM_DQ_PINS == 32) || (NUM_DQ_PINS == 40) || (NUM_DQ_PINS == 48) || (NUM_DQ_PINS == 56))
begin
if (MEM_BURST_LEN == 8)
pipe_data_in[31:0] <= #TCQ {addr_out[31:5], 5'b00000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:4], 4'b0000};
end
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24))
if (MEM_BURST_LEN == 8)
pipe_data_in[31:0] <= #TCQ {addr_out[31:4], 4'b0000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000};
else if ((NUM_DQ_PINS == 8) )
if (MEM_BURST_LEN == 8)
pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000};
else
pipe_data_in[31:0] <= #TCQ {addr_out[31:2], 2'b00};
end
end endgenerate
generate
if (FAMILY == "VIRTEX6") begin: pipe_m_addr_o
always @ (posedge clk_i) begin
if (rst_i[1])
m_addr_o[31:0] <= #TCQ start_addr_i;
else if (instr_vld)
if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) //(AC3_G_E3 && AC2_G_E2 && AC1_G_E1 )
m_addr_o[31:0] <= #TCQ {end_addr_i[31:8],8'h0};
else if ((NUM_DQ_PINS >= 128 && NUM_DQ_PINS < 256))
m_addr_o <= #TCQ {addr_out[31:6], 6'b00000} ;
else if ((NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128))
m_addr_o <= #TCQ {addr_out[31:5], 5'b00000} ;
else if ((NUM_DQ_PINS == 32) || (NUM_DQ_PINS == 40) || (NUM_DQ_PINS == 48) || (NUM_DQ_PINS == 56))
m_addr_o[31:0] <= #TCQ {addr_out[31:4], 4'b0000};
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24))
m_addr_o[31:0] <= #TCQ {addr_out[31:3], 3'b000};
else if ((NUM_DQ_PINS == 8) )
m_addr_o[31:0] <= #TCQ {addr_out[31:2], 2'b00};
end
end endgenerate
reg force_wrcmd_gen;
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_gen <= #TCQ 1'b0;
else if (buf_avail_r == 63)
force_wrcmd_gen <= #TCQ 1'b0;
else if (instr_vld_dly1 && pipe_data_in[32]== 1 && pipe_data_in[41:35] > 16)
force_wrcmd_gen <= #TCQ 1'b1;
end
reg [3:0]instr_mode_reg;
always @ (posedge clk_i)
begin
instr_mode_reg <= #TCQ instr_mode_i;
end
reg force_smallvalue;
always @ (posedge clk_i)
begin
if (rst_i[2]) begin
pipe_data_in[40:32] <= #TCQ 'b0;
force_smallvalue <= #TCQ 1'b0;
end
else if (instr_vld) begin
if (instr_mode_reg == 0) begin
pipe_data_in[34:32] <= #TCQ instr_out;
end
else if (instr_out[2]) begin
pipe_data_in[34:32] <= #TCQ 3'b100;
end
//
else if ( FAMILY == "SPARTAN6" && PORT_MODE == "RD_MODE")
begin
pipe_data_in[34:32] <= #TCQ {instr_out[2:1],1'b1};
end
else if ((force_wrcmd_gen || buf_avail_r <= 15) && FAMILY == "SPARTAN6" && PORT_MODE != "RD_MODE")
begin
pipe_data_in[34:32] <= #TCQ {instr_out[2],2'b00};
end
else begin
pipe_data_in[34:32] <= #TCQ instr_out;
end
//********* condition the generated bl value except if TG is programmed for BRAM interface'
// if the generated address is close to end address range, the bl_out will be altered to 1.
if (bl_mode_i[1:0] == 2'b00) // if programmed BRAM interface
pipe_data_in[40:35] <= #TCQ bl_out;
else if (FAMILY == "VIRTEX6")
pipe_data_in[40:35] <= #TCQ bl_out;
else if (force_bl1 && (bl_mode_reg == 2'b10 ) && FAMILY == "SPARTAN6") //PRBS_BL
pipe_data_in[40:35] <= #TCQ 6'b000001;
else if ((buf_avail_r[5:0] >= 6'b111100 && buf_avail_r[6] == 1'b0) && pipe_data_in[32] == 1'b1 && FAMILY == "SPARTAN6") //read instructon
begin
if (bl_mode_reg == 2'b10)
force_smallvalue <= #TCQ ~force_smallvalue;
if ((buf_avail_r[6] && bl_mode_reg == 2'b10))
pipe_data_in[40:35] <= #TCQ {2'b0,bl_out[3:1],1'b1};
else
pipe_data_in[40:35] <= #TCQ bl_out;
end
else if (buf_avail_r < 64 && rd_buff_avail_i >= 0 && instr_out[0] == 1'b1 && (bl_mode_reg == 2'b10 ))
if (FAMILY == "SPARTAN6")
pipe_data_in[40:35] <= #TCQ {2'b0,bl_out[3:0] + 1};
else
pipe_data_in[40:35] <= #TCQ bl_out;
end //else instr_vld
end // always
always @ (posedge clk_i)
begin
if (rst_i[2])
pipe_data_in[41] <= #TCQ 'b0;
else if (cmd_vld)
pipe_data_in[41] <= #TCQ instr_vld;//instr_vld;
else if (rdy_i && pipe_out_vld)
pipe_data_in[41] <= #TCQ 1'b0;
end
always @ (posedge clk_i)
instr_vld_dly1 <= #TCQ instr_vld;
always @ (posedge clk_i) begin
if (rst_i[0]) begin
rd_data_counts_asked <= #TCQ 'b0;
end else if (instr_vld_dly1 && pipe_data_in[32]== 1) begin
if (pipe_data_in[40:35] == 0)
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (64) ;
else
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (pipe_data_in[40:35]) ;
end
end
always @ (posedge clk_i) begin
if (rst_i[0]) begin
rd_data_received_counts <= #TCQ 'b0;
rd_data_received_counts_total <= #TCQ 'b0;
end else if(reading_rd_data_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1;
rd_data_received_counts_total <= #TCQ rd_data_received_counts_total + 1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
buf_avail_r <= #TCQ (rd_data_received_counts + 64) - rd_data_counts_asked;
localparam BRAM_ADDR = 2'b00;
localparam FIXED_ADDR = 2'b01;
localparam PRBS_ADDR = 2'b10;
localparam SEQUENTIAL_ADDR = 2'b11;
// registered the mode settings
always @ (posedge clk_i) begin
if (rst_i[3])
if (CMD_PATTERN == "CGEN_BRAM")
addr_mode_reg <= #TCQ 3'b000;
else
addr_mode_reg <= #TCQ 3'b011;
else if (mode_load_pulse)
addr_mode_reg <= #TCQ addr_mode_i;
end
always @ (posedge clk_i) begin
if (mode_load_pulse) begin
bl_mode_reg <= #TCQ bl_mode_i ;
end
mode_load_d1 <= #TCQ mode_load_i;
mode_load_d2 <= #TCQ mode_load_d1;
end
always @ (posedge clk_i)
mode_load_pulse <= #TCQ mode_load_d1 & ~mode_load_d2;
// MUX the addr pattern out depending on the addr_mode setting
// "000" = bram; takes the address from bram output
// "001" = fixed address from the fixed_addr input
// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
// "011" = sequential
// "100" = mode that used for prbs addr , prbs bl and prbs data
//always @(addr_mode_reg,prbs_addr,seq_addr,fixed_addr,bram_addr_i,data_mode_i)
always @ (posedge clk_i) begin
if (rst_i[3])
addr_out <= #TCQ start_addr_i;
else
case({addr_mode_reg})
3'b000: addr_out <= #TCQ bram_addr_i;
3'b001: addr_out <= #TCQ fixed_addr;
3'b010: addr_out <= #TCQ prbs_addr;
3'b011: addr_out <= #TCQ {2'b0,seq_addr[29:0]};
3'b100: addr_out <= #TCQ {2'b00,seq_addr[6:2],seq_addr[23:0]};//{prbs_addr[31:6],6'b000000} ;
3'b101: addr_out <= #TCQ {prbs_addr[31:20],seq_addr[19:0]} ;
default : addr_out <= #TCQ 'b0;
endcase
end
// ADDR PRBS GENERATION
generate
if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_addr
cmd_prbs_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.ADDR_WIDTH (32),
.DWIDTH (DWIDTH),
.PRBS_WIDTH (32),
.SEED_WIDTH (32),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ),
.PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ),
.PRBS_EADDR (PRBS_EADDR),
.PRBS_SADDR (PRBS_SADDR )
)
addr_prbs_gen
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (mode_load_pulse),
.prbs_seed_i (cmd_seed_i[31:0]),
.prbs_o (prbs_addr)
);
end
endgenerate
always @ (posedge clk_i) begin
if (addr_out[31:8] >= end_addr_i[31:8])
gen_addr_larger <= 1'b1;
else
gen_addr_larger <= 1'b0;
end
generate
if (FAMILY == "SPARTAN6" ) begin : INC_COUNTS_S
always @ (posedge clk_i)
if (mem_init_done)
INC_COUNTS <= #TCQ (DWIDTH/8)*(bl_out_reg);
else begin
if (fixed_bl_i == 0)
INC_COUNTS <= #TCQ (DWIDTH/8)*(64);
else
INC_COUNTS <= #TCQ (DWIDTH/8)*(fixed_bl_i);
end
end
endgenerate
//converting string to integer
//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4;
localparam MEM_BURST_INT = MEM_BURST_LEN ;
generate
if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
always @ (posedge clk_i) begin
if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256
INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4);
else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256
INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128
INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ;
else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64
INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4);
else if ((NUM_DQ_PINS == 8) )
INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4);
end
end
endgenerate
generate
// Sequential Address pattern
// It is generated when rdy_i is valid and write command is valid and bl_cmd is valid.
reg [31:0] end_addr_r;
always @ (posedge clk_i) begin
end_addr_r <= #TCQ end_addr_i - DWIDTH/8*fixed_bl_i +1;
end
always @ (posedge clk_i) begin
if (addr_out[31:24] >= end_addr_r[31:24])
AC3_G_E3 <= #TCQ 1'b1;
else
AC3_G_E3 <= #TCQ 1'b0;
if (addr_out[23:16] >= end_addr_r[23:16])
AC2_G_E2 <= #TCQ 1'b1;
else
AC2_G_E2 <= #TCQ 1'b0;
if (addr_out[15:8] >= end_addr_r[15:8])
AC1_G_E1 <= #TCQ 1'b1;
else
AC1_G_E1 <= #TCQ 1'b0;
end
if (CMD_PATTERN == "CGEN_SEQUENTIAL" || CMD_PATTERN == "CGEN_ALL" ) begin : seq_addr_gen
assign seq_addr = addr_counts;
reg mode_load_pulse_r1;
always @ (posedge clk_i)
begin
mode_load_pulse_r1 <= #TCQ mode_load_pulse;
end
always @ (posedge clk_i)
end_addr_range <= #TCQ end_addr_i[15:0] - (DWIDTH/8 *bl_out_reg) + 1 ;
always @ (posedge clk_i)
addr_counts_next_r <= #TCQ addr_counts + INC_COUNTS ;
reg cmd_clk_en_r;
always @ (posedge clk_i)
cmd_clk_en_r <= #TCQ cmd_clk_en;
always @ (posedge clk_i) begin
if (rst_i[4]) begin
addr_counts <= #TCQ start_addr_i;
mem_init_done <= #TCQ 1'b0;
end else if (cmd_clk_en_r || mode_load_pulse_r1)
if(addr_counts_next_r>= end_addr_i) begin
addr_counts <= #TCQ start_addr_i;
mem_init_done <= #TCQ 1'b1;
end else if(addr_counts < end_addr_r) // address counts get incremented by burst_length and port size each wr command generated
addr_counts <= #TCQ addr_counts + INC_COUNTS;
end
// end begin
end
endgenerate
generate
// Fixed Address pattern
if (CMD_PATTERN == "CGEN_FIXED" || CMD_PATTERN == "CGEN_ALL" ) begin : fixed_addr_gen
assign fixed_addr = (DWIDTH == 32)? {fixed_addr_i[31:2],2'b0} :
(DWIDTH == 64)? {fixed_addr_i[31:3],3'b0}:
(DWIDTH <= 128)? {fixed_addr_i[31:4],4'b0}:
(DWIDTH <= 256)? {fixed_addr_i[31:5],5'b0}:
{fixed_addr_i[31:6],6'b0};
end
endgenerate
generate
// BRAM Address pattern
if (CMD_PATTERN == "CGEN_BRAM" || CMD_PATTERN == "CGEN_ALL" ) begin : bram_addr_gen
assign bram_rdy_o = run_traffic_i & cmd_clk_en & bram_valid_i | mode_load_pulse;
end
endgenerate
///////////////////////////////////////////////////////////////////////////
// INSTR COMMAND GENERATION
// tap points are 3,2
//`define RD 3'b001
//`define RDP 3'b011
//`define WR 3'b000
//`define WRP 3'b010
//`define REFRESH 3'b100
// use 14 stages 1 sr16; tap position 1,3,5,14
reg [9:0]force_rd_counts;
reg force_rd;
always @ (posedge clk_i) begin
if (rst_i[4])
force_rd_counts <= #TCQ 'b0;
else if (instr_vld) begin
force_rd_counts <= #TCQ force_rd_counts + 1;
end
end
always @ (posedge clk_i) begin
if (rst_i[4])
force_rd <= #TCQ 1'b0;
else if (force_rd_counts[3])
force_rd <= #TCQ 1'b1;
else
force_rd <= #TCQ 1'b0;
end
// adding refresh timer to limit the amount of issuing refresh command.
always @ (posedge clk_i) begin
if (rst_i[4])
refresh_timer <= #TCQ 'b0;
else
refresh_timer <= #TCQ refresh_timer + 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[4])
refresh_cmd_en <= #TCQ 'b0;
//else if (refresh_timer >= 12'hff0 && refresh_timer <= 12'hfff)
else if (refresh_timer == 10'h3ff)
refresh_cmd_en <= #TCQ 'b1;
else if (cmd_clk_en && refresh_cmd_en)
refresh_cmd_en <= #TCQ 'b0;
end
always @ (posedge clk_i) begin
if (FAMILY == "SPARTAN6")
refresh_prbs <= #TCQ prbs_instr_b[3] & refresh_cmd_en;
else
refresh_prbs <= #TCQ 1'b0;
end
//synthesis translate_off
always @ (instr_mode_i)
if(instr_mode_i >2 && FAMILY == "VIRTEX6") begin
$display("Error ! Not valid instruction mode");
$stop;
end
//synthesis translate_on
always @ (posedge clk_i) begin
case(instr_mode_i)
0: instr_out <= #TCQ bram_instr_i;
1: instr_out <= #TCQ fixed_instr_i;
2: instr_out <= #TCQ {2'b00,(prbs_instr_a[0] | force_rd)};
3: instr_out <= #TCQ {2'b0,prbs_instr_a[0]}; //: WP/RP
4: instr_out <= #TCQ {1'b0,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP.
// may be add another PRBS for generating REFRESH
// 5: instr_out <= #TCQ {prbs_instr_b[3],prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH
5: instr_out <= #TCQ {refresh_prbs ,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH
default : instr_out <= #TCQ {2'b00,prbs_instr_a[0]};
endcase
end
generate // PRBS INSTRUCTION generation
// use two PRBS generators and tap off 1 bit from each to create more randomness for
// generating actual read/write commands
if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_instr
cmd_prbs_gen #
(
.TCQ (TCQ),
.PRBS_CMD ("INSTR"),
.ADDR_WIDTH (32),
.SEED_WIDTH (15),
.PRBS_WIDTH (20)
)
instr_prbs_gen_a
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (load_seed_i),
.prbs_seed_i (cmd_seed_i[14:0]),
.prbs_o (prbs_instr_a)
);
cmd_prbs_gen #
(
.PRBS_CMD ("INSTR"),
.SEED_WIDTH (15),
.PRBS_WIDTH (20)
)
instr_prbs_gen_b
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (load_seed_i),
.prbs_seed_i (cmd_seed_i[16:2]),
.prbs_o (prbs_instr_b)
);
end
endgenerate
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// BURST LENGTH GENERATION
// burst length code = user burst length input - 1
// mcb_flow_control does the minus before sending out to mcb\
// when filling up the memory, need to make sure bl doesn't go beyound its upper limit boundary
//assign force_bl1 = (addr_out[31:0] >= (end_addr_i[31:0] - 4*64)) ? 1'b1: 1'b0;
// for neighbour pattern, need to limit the bl to make sure it is within column size boundary.
// check bl validity
always @ (posedge clk_i) begin
if (addr_out[31:24] >= end_addr_i[31:24])
A3_G_E3 <= #TCQ 1'b1;
else
A3_G_E3 <= #TCQ 1'b0;
if (addr_out[23:16] >= end_addr_i[23:16])
A2_G_E2 <= #TCQ 1'b1;
else
A2_G_E2 <= #TCQ 1'b0;
if (addr_out[15:8] >= end_addr_i[15:8])
A1_G_E1 <= #TCQ 1'b1;
else
A1_G_E1 <= #TCQ 1'b0;
if (addr_out[7:0] > end_addr_i[7:0] - DWIDTH/8* bl_out + 1)
A0_G_E0 <= #TCQ 1'b1;
else
A0_G_E0 <= #TCQ 1'b0;
end
always @(addr_out,bl_out,end_addr_i,rst_i,buf_avail_r) begin
if (rst_i[5])
force_bl1 = 1'b0;
else if (((addr_out + bl_out* (DWIDTH/8)) >= end_addr_i) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE"))
force_bl1 = 1'b1;
else
force_bl1 = 1'b0;
end
always @(posedge clk_i) begin
if (rst_i[6])
bl_out_reg <= #TCQ fixed_bl_i;
else if (bl_out_vld)
bl_out_reg <= #TCQ bl_out;
end
always @ (posedge clk_i) begin
if (mode_load_pulse)
bl_out <= #TCQ fixed_bl_i ;
else if (cmd_clk_en) begin
case({bl_mode_reg})
0: bl_out <= #TCQ bram_bl_i ;
1: bl_out <= #TCQ fixed_bl_i ;
2: bl_out <= #TCQ prbs_brlen;
default : bl_out <= #TCQ 6'h1;
endcase
end
end
//synthesis translate_off
always @ (bl_out)
if(bl_out >2 && FAMILY == "VIRTEX6") begin
$display("Error ! Not valid burst length");
$stop;
end
//synthesis translate_on
generate
if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_bl
cmd_prbs_gen #
(
.TCQ (TCQ),
.FAMILY (FAMILY),
.PRBS_CMD ("BLEN"),
.ADDR_WIDTH (32),
.SEED_WIDTH (15),
.PRBS_WIDTH (20)
)
bl_prbs_gen
(
.clk_i (clk_i),
.clk_en (cmd_clk_en),
.prbs_seed_init (load_seed_i),
.prbs_seed_i (cmd_seed_i[16:2]),
.prbs_o (prbs_bl)
);
end
always @ (prbs_bl)
if (FAMILY == "SPARTAN6") // supports 1 throug 64
prbs_brlen = (prbs_bl[5:0] == 6'b000000) ? 6'b000001: prbs_bl[5:0];
else // VIRTEX6 only supports 1 or 2 burst on user ports
prbs_brlen = 6'b000010;
endgenerate
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: buffer_dp.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module buffer_dp (
data,
rdaddress,
rdclock,
wraddress,
wrclock,
wren,
q);
input [7:0] data;
input [8:0] rdaddress;
input rdclock;
input [8:0] wraddress;
input wrclock;
input wren;
output [7:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 wrclock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [7:0] sub_wire0;
wire [7:0] q = sub_wire0[7:0];
altsyncram altsyncram_component (
.wren_a (wren),
.clock0 (wrclock),
.clock1 (rdclock),
.address_a (wraddress),
.address_b (rdaddress),
.data_a (data),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({8{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_reg_b = "CLOCK1",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.init_file = "buffer_dp",
altsyncram_component.intended_device_family = "Cyclone II",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.maximum_depth = 512,
altsyncram_component.numwords_a = 512,
altsyncram_component.numwords_b = 512,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.ram_block_type = "M4K",
altsyncram_component.widthad_a = 9,
altsyncram_component.widthad_b = 9,
altsyncram_component.width_a = 8,
altsyncram_component.width_b = 8,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "1"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: ECC NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "512"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "buffer_dp"
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "8"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "buffer_dp"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: MAXIMUM_DEPTH NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "512"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: RAM_BLOCK_TYPE STRING "M4K"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "9"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdaddress 0 0 9 0 INPUT NODEFVAL rdaddress[8..0]
// Retrieval info: USED_PORT: rdclock 0 0 0 0 INPUT NODEFVAL rdclock
// Retrieval info: USED_PORT: wraddress 0 0 9 0 INPUT NODEFVAL wraddress[8..0]
// Retrieval info: USED_PORT: wrclock 0 0 0 0 INPUT VCC wrclock
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
// Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q_b 0 0 8 0
// Retrieval info: CONNECT: @address_a 0 0 9 0 wraddress 0 0 9 0
// Retrieval info: CONNECT: @address_b 0 0 9 0 rdaddress 0 0 9 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 wrclock 0 0 0 0
// Retrieval info: CONNECT: @clock1 0 0 0 0 rdclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_bb.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL buffer_dp_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module ghrd_10as066n2_axi_bridge_0 #(
parameter USE_PIPELINE = 1,
parameter USE_M0_AWID = 1,
parameter USE_M0_AWREGION = 1,
parameter USE_M0_AWLEN = 1,
parameter USE_M0_AWSIZE = 1,
parameter USE_M0_AWBURST = 1,
parameter USE_M0_AWLOCK = 1,
parameter USE_M0_AWCACHE = 1,
parameter USE_M0_AWQOS = 1,
parameter USE_S0_AWREGION = 1,
parameter USE_S0_AWLOCK = 1,
parameter USE_S0_AWCACHE = 1,
parameter USE_S0_AWQOS = 1,
parameter USE_S0_AWPROT = 1,
parameter USE_M0_WSTRB = 1,
parameter USE_S0_WLAST = 1,
parameter USE_M0_BID = 1,
parameter USE_M0_BRESP = 1,
parameter USE_S0_BRESP = 1,
parameter USE_M0_ARID = 1,
parameter USE_M0_ARREGION = 1,
parameter USE_M0_ARLEN = 1,
parameter USE_M0_ARSIZE = 1,
parameter USE_M0_ARBURST = 1,
parameter USE_M0_ARLOCK = 1,
parameter USE_M0_ARCACHE = 1,
parameter USE_M0_ARQOS = 1,
parameter USE_S0_ARREGION = 1,
parameter USE_S0_ARLOCK = 1,
parameter USE_S0_ARCACHE = 1,
parameter USE_S0_ARQOS = 1,
parameter USE_S0_ARPROT = 1,
parameter USE_M0_RID = 1,
parameter USE_M0_RRESP = 1,
parameter USE_M0_RLAST = 1,
parameter USE_S0_RRESP = 1,
parameter M0_ID_WIDTH = 3,
parameter S0_ID_WIDTH = 6,
parameter DATA_WIDTH = 512,
parameter WRITE_ADDR_USER_WIDTH = 32,
parameter READ_ADDR_USER_WIDTH = 32,
parameter WRITE_DATA_USER_WIDTH = 32,
parameter WRITE_RESP_USER_WIDTH = 32,
parameter READ_DATA_USER_WIDTH = 32,
parameter ADDR_WIDTH = 32,
parameter USE_S0_AWUSER = 0,
parameter USE_S0_ARUSER = 0,
parameter USE_S0_WUSER = 0,
parameter USE_S0_RUSER = 0,
parameter USE_S0_BUSER = 0,
parameter USE_M0_AWUSER = 0,
parameter USE_M0_ARUSER = 0,
parameter USE_M0_WUSER = 0,
parameter USE_M0_RUSER = 0,
parameter USE_M0_BUSER = 0,
parameter AXI_VERSION = "AXI4"
) (
input wire aclk, // clk.clk
input wire aresetn, // clk_reset.reset_n
output wire [2:0] m0_awid, // m0.awid
output wire [31:0] m0_awaddr, // .awaddr
output wire [7:0] m0_awlen, // .awlen
output wire [2:0] m0_awsize, // .awsize
output wire [1:0] m0_awburst, // .awburst
output wire [0:0] m0_awlock, // .awlock
output wire [3:0] m0_awcache, // .awcache
output wire [2:0] m0_awprot, // .awprot
output wire [3:0] m0_awqos, // .awqos
output wire [3:0] m0_awregion, // .awregion
output wire m0_awvalid, // .awvalid
input wire m0_awready, // .awready
output wire [511:0] m0_wdata, // .wdata
output wire [63:0] m0_wstrb, // .wstrb
output wire m0_wlast, // .wlast
output wire m0_wvalid, // .wvalid
input wire m0_wready, // .wready
input wire [2:0] m0_bid, // .bid
input wire [1:0] m0_bresp, // .bresp
input wire m0_bvalid, // .bvalid
output wire m0_bready, // .bready
output wire [2:0] m0_arid, // .arid
output wire [31:0] m0_araddr, // .araddr
output wire [7:0] m0_arlen, // .arlen
output wire [2:0] m0_arsize, // .arsize
output wire [1:0] m0_arburst, // .arburst
output wire [0:0] m0_arlock, // .arlock
output wire [3:0] m0_arcache, // .arcache
output wire [2:0] m0_arprot, // .arprot
output wire [3:0] m0_arqos, // .arqos
output wire [3:0] m0_arregion, // .arregion
output wire m0_arvalid, // .arvalid
input wire m0_arready, // .arready
input wire [2:0] m0_rid, // .rid
input wire [511:0] m0_rdata, // .rdata
input wire [1:0] m0_rresp, // .rresp
input wire m0_rlast, // .rlast
input wire m0_rvalid, // .rvalid
output wire m0_rready, // .rready
input wire [5:0] s0_awid, // s0.awid
input wire [31:0] s0_awaddr, // .awaddr
input wire [7:0] s0_awlen, // .awlen
input wire [2:0] s0_awsize, // .awsize
input wire [1:0] s0_awburst, // .awburst
input wire [0:0] s0_awlock, // .awlock
input wire [3:0] s0_awcache, // .awcache
input wire [2:0] s0_awprot, // .awprot
input wire [3:0] s0_awqos, // .awqos
input wire [3:0] s0_awregion, // .awregion
input wire s0_awvalid, // .awvalid
output wire s0_awready, // .awready
input wire [511:0] s0_wdata, // .wdata
input wire [63:0] s0_wstrb, // .wstrb
input wire s0_wlast, // .wlast
input wire s0_wvalid, // .wvalid
output wire s0_wready, // .wready
output wire [5:0] s0_bid, // .bid
output wire [1:0] s0_bresp, // .bresp
output wire s0_bvalid, // .bvalid
input wire s0_bready, // .bready
input wire [5:0] s0_arid, // .arid
input wire [31:0] s0_araddr, // .araddr
input wire [7:0] s0_arlen, // .arlen
input wire [2:0] s0_arsize, // .arsize
input wire [1:0] s0_arburst, // .arburst
input wire [0:0] s0_arlock, // .arlock
input wire [3:0] s0_arcache, // .arcache
input wire [2:0] s0_arprot, // .arprot
input wire [3:0] s0_arqos, // .arqos
input wire [3:0] s0_arregion, // .arregion
input wire s0_arvalid, // .arvalid
output wire s0_arready, // .arready
output wire [5:0] s0_rid, // .rid
output wire [511:0] s0_rdata, // .rdata
output wire [1:0] s0_rresp, // .rresp
output wire s0_rlast, // .rlast
output wire s0_rvalid, // .rvalid
input wire s0_rready // .rready
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
`define SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
/**
* decaphe: Shielded Decoupling capacitance filler.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphe ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHE_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v2_0_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Dec 20 2013
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_0_ddr_phy_tempmon #
(
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter TEMP_INCDEC = 1465, // Degrees C * 100 (14.65 * 100)
parameter TEMP_HYST = 1,
parameter TEMP_MIN_LIMIT = 12'h8ac,
parameter TEMP_MAX_LIMIT = 12'hca4
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
localparam TEMP_INCDEC_OFFSET = ((TEMP_INCDEC * 4096) / 50400) ;
// Temperature sampler FSM encoding
localparam IDLE = 11'b000_0000_0001;
localparam INIT = 11'b000_0000_0010;
localparam FOUR_INC = 11'b000_0000_0100;
localparam THREE_INC = 11'b000_0000_1000;
localparam TWO_INC = 11'b000_0001_0000;
localparam ONE_INC = 11'b000_0010_0000;
localparam NEUTRAL = 11'b000_0100_0000;
localparam ONE_DEC = 11'b000_1000_0000;
localparam TWO_DEC = 11'b001_0000_0000;
localparam THREE_DEC = 11'b010_0000_0000;
localparam FOUR_DEC = 11'b100_0000_0000;
//===========================================================================
// Reg declarations
//===========================================================================
// Output port flops. Inc and dec are mutex.
reg pi_f_dec; // Flop output
reg pi_f_inc; // Flop output
reg pi_f_dec_nxt; // FSM output
reg pi_f_inc_nxt; // FSM output
// FSM state
reg [10:0] tempmon_state;
reg [10:0] tempmon_state_nxt;
// FSM output used to capture the initial device termperature
reg tempmon_state_init;
// Flag to indicate the initial device temperature is captured and normal operation can begin
reg tempmon_init_complete;
// Temperature band/state boundaries
reg [11:0] four_inc_max_limit;
reg [11:0] three_inc_max_limit;
reg [11:0] two_inc_max_limit;
reg [11:0] one_inc_max_limit;
reg [11:0] neutral_max_limit;
reg [11:0] one_dec_max_limit;
reg [11:0] two_dec_max_limit;
reg [11:0] three_dec_max_limit;
reg [11:0] three_inc_min_limit;
reg [11:0] two_inc_min_limit;
reg [11:0] one_inc_min_limit;
reg [11:0] neutral_min_limit;
reg [11:0] one_dec_min_limit;
reg [11:0] two_dec_min_limit;
reg [11:0] three_dec_min_limit;
reg [11:0] four_dec_min_limit;
reg [11:0] device_temp_init;
// Flops for capturing and storing the current device temperature
reg tempmon_sample_en_101;
reg tempmon_sample_en_102;
reg [11:0] device_temp_101;
reg [11:0] device_temp_capture_102;
reg update_temp_102;
// Flops for comparing temperature to max limits
reg temp_cmp_four_inc_max_102;
reg temp_cmp_three_inc_max_102;
reg temp_cmp_two_inc_max_102;
reg temp_cmp_one_inc_max_102;
reg temp_cmp_neutral_max_102;
reg temp_cmp_one_dec_max_102;
reg temp_cmp_two_dec_max_102;
reg temp_cmp_three_dec_max_102;
// Flops for comparing temperature to min limits
reg temp_cmp_three_inc_min_102;
reg temp_cmp_two_inc_min_102;
reg temp_cmp_one_inc_min_102;
reg temp_cmp_neutral_min_102;
reg temp_cmp_one_dec_min_102;
reg temp_cmp_two_dec_min_102;
reg temp_cmp_three_dec_min_102;
reg temp_cmp_four_dec_min_102;
//===========================================================================
// Overview and temperature band limits
//===========================================================================
// The main feature of the tempmon block is an FSM that tracks the temerature provided by the ADC and decides if the phaser needs to be adjusted. The FSM
// has nine temperature bands or states, centered around an initial device temperature. The name of each state is the net number of phaser increments or
// decrements that have been issued in getting to the state. There are two temperature boundaries or limits between adjacent states. These two boundaries are
// offset by a small amount to provide hysteresis. The max limits are the boundaries that are used to determine when to move to the next higher temperature state
// and decrement the phaser. The min limits determine when to move to the next lower temperature state and increment the phaser. The limits are calculated when
// the initial device temperature is taken, and will always be at fixed offsets from the initial device temperature. States with limits below 0C or above
// 125C will never be entered.
// Temperature lowest highest
// <------------------------------------------------------------------------------------------------------------------------------------------------>
//
// Temp four three two one neutral one two three four
// band/state inc inc inc inc dec dec dec dec
//
// Max limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|
// Min limits |<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->|<-2*TEMP_INCDEC->| |
// | | | | | | |
// | | | | | | |
// three_inc_min_limit | HYST_OFFSET--->| |<-- | four_dec_min_limit |
// | device_temp_init |
// four_inc_max_limit three_dec_max_limit
// Boundaries for moving from lower temp bands to higher temp bands.
// Note that only three_dec_max_limit can roll over, assuming device_temp_init is between 0C and 125C and TEMP_INCDEC_OFFSET is 14.65C,
// and none of the min or max limits can roll under. So three_dec_max_limit has a check for being out of the 0x0 to 0xFFF range.
wire [11:0] four_inc_max_limit_nxt = device_temp_init - 7*TEMP_INCDEC_OFFSET; // upper boundary of lowest temp band
wire [11:0] three_inc_max_limit_nxt = device_temp_init - 5*TEMP_INCDEC_OFFSET;
wire [11:0] two_inc_max_limit_nxt = device_temp_init - 3*TEMP_INCDEC_OFFSET;
wire [11:0] one_inc_max_limit_nxt = device_temp_init - TEMP_INCDEC_OFFSET;
wire [11:0] neutral_max_limit_nxt = device_temp_init + TEMP_INCDEC_OFFSET; // upper boundary of init temp band
wire [11:0] one_dec_max_limit_nxt = device_temp_init + 3*TEMP_INCDEC_OFFSET;
wire [11:0] two_dec_max_limit_nxt = device_temp_init + 5*TEMP_INCDEC_OFFSET;
wire [12:0] three_dec_max_limit_tmp = device_temp_init + 7*TEMP_INCDEC_OFFSET; // upper boundary of 2nd highest temp band
wire [11:0] three_dec_max_limit_nxt = three_dec_max_limit_tmp[12] ? 12'hFFF : three_dec_max_limit_tmp[11:0];
// Boundaries for moving from higher temp bands to lower temp bands
wire [11:0] three_inc_min_limit_nxt = four_inc_max_limit - HYST_OFFSET; // lower boundary of 2nd lowest temp band
wire [11:0] two_inc_min_limit_nxt = three_inc_max_limit - HYST_OFFSET;
wire [11:0] one_inc_min_limit_nxt = two_inc_max_limit - HYST_OFFSET;
wire [11:0] neutral_min_limit_nxt = one_inc_max_limit - HYST_OFFSET; // lower boundary of init temp band
wire [11:0] one_dec_min_limit_nxt = neutral_max_limit - HYST_OFFSET;
wire [11:0] two_dec_min_limit_nxt = one_dec_max_limit - HYST_OFFSET;
wire [11:0] three_dec_min_limit_nxt = two_dec_max_limit - HYST_OFFSET;
wire [11:0] four_dec_min_limit_nxt = three_dec_max_limit - HYST_OFFSET; // lower boundary of highest temp band
//===========================================================================
// Capture device temperature
//===========================================================================
// There is a three stage pipeline used to capture temperature, calculate the next state
// of the FSM, and update the tempmon outputs.
//
// Stage 100 Inputs device_temp and tempmon_sample_en become valid and are flopped.
// Input device_temp is compared to ADC codes for 0C and 125C and limited
// at the flop input if needed.
//
// Stage 101 The flopped version of device_temp is compared to the FSM temperature band boundaries
// to determine if a state change is needed. State changes are only enabled on the
// rising edge of the flopped tempmon_sample_en signal. If there is a state change a phaser
// increment or decrement signal is generated and flopped.
//
// Stage 102 The flopped versions of the phaser inc/dec signals drive the module outputs.
// Limit device_temp to 0C to 125C and assign it to flop input device_temp_100
// temp C = ( ( ADC CODE * 503.975 ) / 4096 ) - 273.15
wire device_temp_high = device_temp > TEMP_MAX_LIMIT;
wire device_temp_low = device_temp < TEMP_MIN_LIMIT;
wire [11:0] device_temp_100 = ( { 12 { device_temp_high } } & TEMP_MAX_LIMIT )
| ( { 12 { device_temp_low } } & TEMP_MIN_LIMIT )
| ( { 12 { ~device_temp_high & ~device_temp_low } } & device_temp );
// Capture/hold the initial temperature used in setting temperature bands and set init complete flag
// to enable normal sample operation.
wire [11:0] device_temp_init_nxt = tempmon_state_init ? device_temp_101 : device_temp_init;
wire tempmon_init_complete_nxt = tempmon_state_init ? 1'b1 : tempmon_init_complete;
// Capture/hold the current temperature on the sample enable signal rising edge after init is complete.
// The captured current temp is not used functionaly. It is just useful for debug and waveform review.
wire update_temp_101 = tempmon_init_complete & ~tempmon_sample_en_102 & tempmon_sample_en_101;
wire [11:0] device_temp_capture_101 = update_temp_101 ? device_temp_101 : device_temp_capture_102;
//===========================================================================
// Generate FSM arc signals
//===========================================================================
// Temperature comparisons for increasing temperature.
wire temp_cmp_four_inc_max_101 = device_temp_101 >= four_inc_max_limit ;
wire temp_cmp_three_inc_max_101 = device_temp_101 >= three_inc_max_limit ;
wire temp_cmp_two_inc_max_101 = device_temp_101 >= two_inc_max_limit ;
wire temp_cmp_one_inc_max_101 = device_temp_101 >= one_inc_max_limit ;
wire temp_cmp_neutral_max_101 = device_temp_101 >= neutral_max_limit ;
wire temp_cmp_one_dec_max_101 = device_temp_101 >= one_dec_max_limit ;
wire temp_cmp_two_dec_max_101 = device_temp_101 >= two_dec_max_limit ;
wire temp_cmp_three_dec_max_101 = device_temp_101 >= three_dec_max_limit ;
// Temperature comparisons for decreasing temperature.
wire temp_cmp_three_inc_min_101 = device_temp_101 < three_inc_min_limit ;
wire temp_cmp_two_inc_min_101 = device_temp_101 < two_inc_min_limit ;
wire temp_cmp_one_inc_min_101 = device_temp_101 < one_inc_min_limit ;
wire temp_cmp_neutral_min_101 = device_temp_101 < neutral_min_limit ;
wire temp_cmp_one_dec_min_101 = device_temp_101 < one_dec_min_limit ;
wire temp_cmp_two_dec_min_101 = device_temp_101 < two_dec_min_limit ;
wire temp_cmp_three_dec_min_101 = device_temp_101 < three_dec_min_limit ;
wire temp_cmp_four_dec_min_101 = device_temp_101 < four_dec_min_limit ;
// FSM arcs for increasing temperature.
wire temp_gte_four_inc_max = update_temp_102 & temp_cmp_four_inc_max_102;
wire temp_gte_three_inc_max = update_temp_102 & temp_cmp_three_inc_max_102;
wire temp_gte_two_inc_max = update_temp_102 & temp_cmp_two_inc_max_102;
wire temp_gte_one_inc_max = update_temp_102 & temp_cmp_one_inc_max_102;
wire temp_gte_neutral_max = update_temp_102 & temp_cmp_neutral_max_102;
wire temp_gte_one_dec_max = update_temp_102 & temp_cmp_one_dec_max_102;
wire temp_gte_two_dec_max = update_temp_102 & temp_cmp_two_dec_max_102;
wire temp_gte_three_dec_max = update_temp_102 & temp_cmp_three_dec_max_102;
// FSM arcs for decreasing temperature.
wire temp_lte_three_inc_min = update_temp_102 & temp_cmp_three_inc_min_102;
wire temp_lte_two_inc_min = update_temp_102 & temp_cmp_two_inc_min_102;
wire temp_lte_one_inc_min = update_temp_102 & temp_cmp_one_inc_min_102;
wire temp_lte_neutral_min = update_temp_102 & temp_cmp_neutral_min_102;
wire temp_lte_one_dec_min = update_temp_102 & temp_cmp_one_dec_min_102;
wire temp_lte_two_dec_min = update_temp_102 & temp_cmp_two_dec_min_102;
wire temp_lte_three_dec_min = update_temp_102 & temp_cmp_three_dec_min_102;
wire temp_lte_four_dec_min = update_temp_102 & temp_cmp_four_dec_min_102;
//===========================================================================
// Implement FSM
//===========================================================================
// In addition to the nine temperature states, there are also IDLE and INIT states.
// The INIT state triggers the calculation of the temperature boundaries between the
// other states. After INIT, the FSM will always go to the NEUTRAL state. There is
// no timing restriction required between calib_complete and tempmon_sample_en.
always @(*) begin
tempmon_state_nxt = tempmon_state;
tempmon_state_init = 1'b0;
pi_f_inc_nxt = 1'b0;
pi_f_dec_nxt = 1'b0;
casez (tempmon_state)
IDLE: begin
if (calib_complete) tempmon_state_nxt = INIT;
end
INIT: begin
tempmon_state_nxt = NEUTRAL;
tempmon_state_init = 1'b1;
end
FOUR_INC: begin
if (temp_gte_four_inc_max) begin
tempmon_state_nxt = THREE_INC;
pi_f_dec_nxt = 1'b1;
end
end
THREE_INC: begin
if (temp_gte_three_inc_max) begin
tempmon_state_nxt = TWO_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_inc_min) begin
tempmon_state_nxt = FOUR_INC;
pi_f_inc_nxt = 1'b1;
end
end
TWO_INC: begin
if (temp_gte_two_inc_max) begin
tempmon_state_nxt = ONE_INC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_inc_min) begin
tempmon_state_nxt = THREE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_INC: begin
if (temp_gte_one_inc_max) begin
tempmon_state_nxt = NEUTRAL;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_inc_min) begin
tempmon_state_nxt = TWO_INC;
pi_f_inc_nxt = 1'b1;
end
end
NEUTRAL: begin
if (temp_gte_neutral_max) begin
tempmon_state_nxt = ONE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_neutral_min) begin
tempmon_state_nxt = ONE_INC;
pi_f_inc_nxt = 1'b1;
end
end
ONE_DEC: begin
if (temp_gte_one_dec_max) begin
tempmon_state_nxt = TWO_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_one_dec_min) begin
tempmon_state_nxt = NEUTRAL;
pi_f_inc_nxt = 1'b1;
end
end
TWO_DEC: begin
if (temp_gte_two_dec_max) begin
tempmon_state_nxt = THREE_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_two_dec_min) begin
tempmon_state_nxt = ONE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
THREE_DEC: begin
if (temp_gte_three_dec_max) begin
tempmon_state_nxt = FOUR_DEC;
pi_f_dec_nxt = 1'b1;
end
else if (temp_lte_three_dec_min) begin
tempmon_state_nxt = TWO_DEC;
pi_f_inc_nxt = 1'b1;
end
end
FOUR_DEC: begin
if (temp_lte_four_dec_min) begin
tempmon_state_nxt = THREE_DEC;
pi_f_inc_nxt = 1'b1;
end
end
default: begin
tempmon_state_nxt = IDLE;
end
endcase
end //always
//synopsys translate_off
reg [71:0] tempmon_state_name;
always @(*) casez (tempmon_state)
IDLE : tempmon_state_name = "IDLE";
INIT : tempmon_state_name = "INIT";
FOUR_INC : tempmon_state_name = "FOUR_INC";
THREE_INC : tempmon_state_name = "THREE_INC";
TWO_INC : tempmon_state_name = "TWO_INC";
ONE_INC : tempmon_state_name = "ONE_INC";
NEUTRAL : tempmon_state_name = "NEUTRAL";
ONE_DEC : tempmon_state_name = "ONE_DEC";
TWO_DEC : tempmon_state_name = "TWO_DEC";
THREE_DEC : tempmon_state_name = "THREE_DEC";
FOUR_DEC : tempmon_state_name = "FOUR_DEC";
default : tempmon_state_name = "BAD_STATE";
endcase
//synopsys translate_on
//===========================================================================
// Generate final output and implement flops
//===========================================================================
// Generate output
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = pi_f_inc | pi_f_dec;
// Implement reset flops
always @(posedge clk) begin
if(rst) begin
tempmon_state <= #TCQ 11'b000_0000_0001;
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
four_inc_max_limit <= #TCQ 12'b0;
three_inc_max_limit <= #TCQ 12'b0;
two_inc_max_limit <= #TCQ 12'b0;
one_inc_max_limit <= #TCQ 12'b0;
neutral_max_limit <= #TCQ 12'b0;
one_dec_max_limit <= #TCQ 12'b0;
two_dec_max_limit <= #TCQ 12'b0;
three_dec_max_limit <= #TCQ 12'b0;
three_inc_min_limit <= #TCQ 12'b0;
two_inc_min_limit <= #TCQ 12'b0;
one_inc_min_limit <= #TCQ 12'b0;
neutral_min_limit <= #TCQ 12'b0;
one_dec_min_limit <= #TCQ 12'b0;
two_dec_min_limit <= #TCQ 12'b0;
three_dec_min_limit <= #TCQ 12'b0;
four_dec_min_limit <= #TCQ 12'b0;
device_temp_init <= #TCQ 12'b0;
tempmon_init_complete <= #TCQ 1'b0;
tempmon_sample_en_101 <= #TCQ 1'b0;
tempmon_sample_en_102 <= #TCQ 1'b0;
device_temp_101 <= #TCQ 12'b0;
device_temp_capture_102 <= #TCQ 12'b0;
end
else begin
tempmon_state <= #TCQ tempmon_state_nxt;
pi_f_inc <= #TCQ pi_f_inc_nxt;
pi_f_dec <= #TCQ pi_f_dec_nxt;
four_inc_max_limit <= #TCQ four_inc_max_limit_nxt;
three_inc_max_limit <= #TCQ three_inc_max_limit_nxt;
two_inc_max_limit <= #TCQ two_inc_max_limit_nxt;
one_inc_max_limit <= #TCQ one_inc_max_limit_nxt;
neutral_max_limit <= #TCQ neutral_max_limit_nxt;
one_dec_max_limit <= #TCQ one_dec_max_limit_nxt;
two_dec_max_limit <= #TCQ two_dec_max_limit_nxt;
three_dec_max_limit <= #TCQ three_dec_max_limit_nxt;
three_inc_min_limit <= #TCQ three_inc_min_limit_nxt;
two_inc_min_limit <= #TCQ two_inc_min_limit_nxt;
one_inc_min_limit <= #TCQ one_inc_min_limit_nxt;
neutral_min_limit <= #TCQ neutral_min_limit_nxt;
one_dec_min_limit <= #TCQ one_dec_min_limit_nxt;
two_dec_min_limit <= #TCQ two_dec_min_limit_nxt;
three_dec_min_limit <= #TCQ three_dec_min_limit_nxt;
four_dec_min_limit <= #TCQ four_dec_min_limit_nxt;
device_temp_init <= #TCQ device_temp_init_nxt;
tempmon_init_complete <= #TCQ tempmon_init_complete_nxt;
tempmon_sample_en_101 <= #TCQ tempmon_sample_en;
tempmon_sample_en_102 <= #TCQ tempmon_sample_en_101;
device_temp_101 <= #TCQ device_temp_100;
device_temp_capture_102 <= #TCQ device_temp_capture_101;
end
end
// Implement non-reset flops
always @(posedge clk) begin
temp_cmp_four_inc_max_102 <= #TCQ temp_cmp_four_inc_max_101;
temp_cmp_three_inc_max_102 <= #TCQ temp_cmp_three_inc_max_101;
temp_cmp_two_inc_max_102 <= #TCQ temp_cmp_two_inc_max_101;
temp_cmp_one_inc_max_102 <= #TCQ temp_cmp_one_inc_max_101;
temp_cmp_neutral_max_102 <= #TCQ temp_cmp_neutral_max_101;
temp_cmp_one_dec_max_102 <= #TCQ temp_cmp_one_dec_max_101;
temp_cmp_two_dec_max_102 <= #TCQ temp_cmp_two_dec_max_101;
temp_cmp_three_dec_max_102 <= #TCQ temp_cmp_three_dec_max_101;
temp_cmp_three_inc_min_102 <= #TCQ temp_cmp_three_inc_min_101;
temp_cmp_two_inc_min_102 <= #TCQ temp_cmp_two_inc_min_101;
temp_cmp_one_inc_min_102 <= #TCQ temp_cmp_one_inc_min_101;
temp_cmp_neutral_min_102 <= #TCQ temp_cmp_neutral_min_101;
temp_cmp_one_dec_min_102 <= #TCQ temp_cmp_one_dec_min_101;
temp_cmp_two_dec_min_102 <= #TCQ temp_cmp_two_dec_min_101;
temp_cmp_three_dec_min_102 <= #TCQ temp_cmp_three_dec_min_101;
temp_cmp_four_dec_min_102 <= #TCQ temp_cmp_four_dec_min_101;
update_temp_102 <= #TCQ update_temp_101;
end
endmodule
|
module cosrom (
input c, // clock
input [9:0] a0, a1, // angle
output reg [34:0] d0, d1);
reg [34:0] oreg0, oreg1;
(* ram_style = "block" *) reg [34:0] bram[0:1023];
always @ (posedge c) begin
oreg0 <= bram[a0];
oreg1 <= bram[a1];
d0 <= oreg0;
d1 <= oreg1;
end
initial begin
bram[0] <= 35'd34359730181;
bram[1] <= 35'd34359689231;
bram[2] <= 35'd34359566360;
bram[3] <= 35'd34359369763;
bram[4] <= 35'd34359083052;
bram[5] <= 35'd34358722615;
bram[6] <= 35'd34358272064;
bram[7] <= 35'd34357747786;
bram[8] <= 35'd34357141588;
bram[9] <= 35'd34356453469;
bram[10] <= 35'd34355691624;
bram[11] <= 35'd34354839666;
bram[12] <= 35'd34353905787;
bram[13] <= 35'd34352898181;
bram[14] <= 35'd34351808655;
bram[15] <= 35'd34350637209;
bram[16] <= 35'd34349383843;
bram[17] <= 35'd34348048557;
bram[18] <= 35'd34346631350;
bram[19] <= 35'd34345140417;
bram[20] <= 35'd34343559370;
bram[21] <= 35'd34341904596;
bram[22] <= 35'd34340167902;
bram[23] <= 35'd34338349288;
bram[24] <= 35'd34336448754;
bram[25] <= 35'd34334466299;
bram[26] <= 35'd34332410118;
bram[27] <= 35'd34330263823;
bram[28] <= 35'd34328043801;
bram[29] <= 35'd34325741860;
bram[30] <= 35'd34323349804;
bram[31] <= 35'd34320892215;
bram[32] <= 35'd34318344513;
bram[33] <= 35'd34315714890;
bram[34] <= 35'd34313011541;
bram[35] <= 35'd34310218078;
bram[36] <= 35'd34307350888;
bram[37] <= 35'd34304401778;
bram[38] <= 35'd34301370748;
bram[39] <= 35'd34298257797;
bram[40] <= 35'd34295071120;
bram[41] <= 35'd34291794329;
bram[42] <= 35'd34288443811;
bram[43] <= 35'd34285011373;
bram[44] <= 35'd34281497015;
bram[45] <= 35'd34277900737;
bram[46] <= 35'd34274222538;
bram[47] <= 35'd34270470613;
bram[48] <= 35'd34266628574;
bram[49] <= 35'd34262712808;
bram[50] <= 35'd34258715122;
bram[51] <= 35'd34254635516;
bram[52] <= 35'd34250473989;
bram[53] <= 35'd34246238736;
bram[54] <= 35'd34241913369;
bram[55] <= 35'd34237514275;
bram[56] <= 35'd34233033261;
bram[57] <= 35'd34228470327;
bram[58] <= 35'd34223825472;
bram[59] <= 35'd34219106891;
bram[60] <= 35'd34214298196;
bram[61] <= 35'd34209415774;
bram[62] <= 35'd34204451432;
bram[63] <= 35'd34199405170;
bram[64] <= 35'd34194276987;
bram[65] <= 35'd34189075078;
bram[66] <= 35'd34183783055;
bram[67] <= 35'd34178417305;
bram[68] <= 35'd34172969635;
bram[69] <= 35'd34167440044;
bram[70] <= 35'd34161836727;
bram[71] <= 35'd34156143296;
bram[72] <= 35'd34150376138;
bram[73] <= 35'd34144527060;
bram[74] <= 35'd34138596062;
bram[75] <= 35'd34132583143;
bram[76] <= 35'd34126496497;
bram[77] <= 35'd34120327932;
bram[78] <= 35'd34114069252;
bram[79] <= 35'd34107745039;
bram[80] <= 35'd34101330713;
bram[81] <= 35'd34094834466;
bram[82] <= 35'd34088264492;
bram[83] <= 35'd34081612598;
bram[84] <= 35'd34074878783;
bram[85] <= 35'd34068071242;
bram[86] <= 35'd34061173587;
bram[87] <= 35'd34054202205;
bram[88] <= 35'd34047148903;
bram[89] <= 35'd34040013680;
bram[90] <= 35'd34032804731;
bram[91] <= 35'd34025505668;
bram[92] <= 35'd34018132878;
bram[93] <= 35'd34010678167;
bram[94] <= 35'd34003149730;
bram[95] <= 35'd33995531179;
bram[96] <= 35'd33987838901;
bram[97] <= 35'd33980064703;
bram[98] <= 35'd33972208584;
bram[99] <= 35'd33964278738;
bram[100] <= 35'd33956266972;
bram[101] <= 35'd33948173286;
bram[102] <= 35'd33939997679;
bram[103] <= 35'd33931748346;
bram[104] <= 35'd33923408899;
bram[105] <= 35'd33914995724;
bram[106] <= 35'd33906508823;
bram[107] <= 35'd33897931808;
bram[108] <= 35'd33889281066;
bram[109] <= 35'd33880548404;
bram[110] <= 35'd33871733821;
bram[111] <= 35'd33862845511;
bram[112] <= 35'd33853875281;
bram[113] <= 35'd33844823130;
bram[114] <= 35'd33835697253;
bram[115] <= 35'd33826481262;
bram[116] <= 35'd33817191543;
bram[117] <= 35'd33807828098;
bram[118] <= 35'd33798374539;
bram[119] <= 35'd33788847253;
bram[120] <= 35'd33779238046;
bram[121] <= 35'd33769555112;
bram[122] <= 35'd33759790258;
bram[123] <= 35'd33749943484;
bram[124] <= 35'd33740014789;
bram[125] <= 35'd33730012367;
bram[126] <= 35'd33719928025;
bram[127] <= 35'd33709761762;
bram[128] <= 35'd33699521772;
bram[129] <= 35'd33689199862;
bram[130] <= 35'd33678796032;
bram[131] <= 35'd33668310281;
bram[132] <= 35'd33657750802;
bram[133] <= 35'd33647117597;
bram[134] <= 35'd33636394278;
bram[135] <= 35'd33625597232;
bram[136] <= 35'd33614718265;
bram[137] <= 35'd33603765571;
bram[138] <= 35'd33592730957;
bram[139] <= 35'd33581614422;
bram[140] <= 35'd33570424160;
bram[141] <= 35'd33559151978;
bram[142] <= 35'd33547797875;
bram[143] <= 35'd33536370045;
bram[144] <= 35'd33524860294;
bram[145] <= 35'd33513276816;
bram[146] <= 35'd33501611418;
bram[147] <= 35'd33489864099;
bram[148] <= 35'd33478043053;
bram[149] <= 35'd33466140087;
bram[150] <= 35'd33454155200;
bram[151] <= 35'd33442096586;
bram[152] <= 35'd33429956051;
bram[153] <= 35'd33417741789;
bram[154] <= 35'd33405445607;
bram[155] <= 35'd33393067504;
bram[156] <= 35'd33380615674;
bram[157] <= 35'd33368081923;
bram[158] <= 35'd33355474445;
bram[159] <= 35'd33342785047;
bram[160] <= 35'd33330013728;
bram[161] <= 35'd33317168682;
bram[162] <= 35'd33304241715;
bram[163] <= 35'd33291241021;
bram[164] <= 35'd33278158406;
bram[165] <= 35'd33265002064;
bram[166] <= 35'd33251763802;
bram[167] <= 35'd33238443619;
bram[168] <= 35'd33225049708;
bram[169] <= 35'd33211582070;
bram[170] <= 35'd33198032512;
bram[171] <= 35'd33184401033;
bram[172] <= 35'd33170695827;
bram[173] <= 35'd33156908700;
bram[174] <= 35'd33143047846;
bram[175] <= 35'd33129105071;
bram[176] <= 35'd33115088569;
bram[177] <= 35'd33100990146;
bram[178] <= 35'd33086817996;
bram[179] <= 35'd33072563925;
bram[180] <= 35'd33058236127;
bram[181] <= 35'd33043826408;
bram[182] <= 35'd33029342962;
bram[183] <= 35'd33014777595;
bram[184] <= 35'd33000138501;
bram[185] <= 35'd32985417486;
bram[186] <= 35'd32970622744;
bram[187] <= 35'd32955746081;
bram[188] <= 35'd32940795691;
bram[189] <= 35'd32925763380;
bram[190] <= 35'd32910657341;
bram[191] <= 35'd32895477575;
bram[192] <= 35'd32880215889;
bram[193] <= 35'd32864872282;
bram[194] <= 35'd32849454947;
bram[195] <= 35'd32833963885;
bram[196] <= 35'd32818390902;
bram[197] <= 35'd32802744191;
bram[198] <= 35'd32787023753;
bram[199] <= 35'd32771221395;
bram[200] <= 35'd32755337115;
bram[201] <= 35'd32739387302;
bram[202] <= 35'd32723347374;
bram[203] <= 35'd32707241912;
bram[204] <= 35'd32691054530;
bram[205] <= 35'd32674785226;
bram[206] <= 35'd32658450389;
bram[207] <= 35'd32642025437;
bram[208] <= 35'd32625534951;
bram[209] <= 35'd32608962544;
bram[210] <= 35'd32592316410;
bram[211] <= 35'd32575588355;
bram[212] <= 35'd32558786572;
bram[213] <= 35'd32541911062;
bram[214] <= 35'd32524953631;
bram[215] <= 35'd32507922472;
bram[216] <= 35'd32490817586;
bram[217] <= 35'd32473630779;
bram[218] <= 35'd32456370244;
bram[219] <= 35'd32439035982;
bram[220] <= 35'd32421619799;
bram[221] <= 35'd32404129888;
bram[222] <= 35'd32386566250;
bram[223] <= 35'd32368920691;
bram[224] <= 35'd32351201404;
bram[225] <= 35'd32333408390;
bram[226] <= 35'd32315533454;
bram[227] <= 35'd32297592984;
bram[228] <= 35'd32279570594;
bram[229] <= 35'd32261466282;
bram[230] <= 35'd32243296436;
bram[231] <= 35'd32225044669;
bram[232] <= 35'd32206719175;
bram[233] <= 35'd32188311759;
bram[234] <= 35'd32169838809;
bram[235] <= 35'd32151283938;
bram[236] <= 35'd32132655339;
bram[237] <= 35'd32113953013;
bram[238] <= 35'd32095168766;
bram[239] <= 35'd32076310791;
bram[240] <= 35'd32057379088;
bram[241] <= 35'd32038373657;
bram[242] <= 35'd32019294499;
bram[243] <= 35'd32000133419;
bram[244] <= 35'd31980906805;
bram[245] <= 35'd31961598270;
bram[246] <= 35'd31942216008;
bram[247] <= 35'd31922751824;
bram[248] <= 35'd31903222106;
bram[249] <= 35'd31883610467;
bram[250] <= 35'd31863925100;
bram[251] <= 35'd31844166005;
bram[252] <= 35'd31824333182;
bram[253] <= 35'd31804426631;
bram[254] <= 35'd31784446353;
bram[255] <= 35'd31764384153;
bram[256] <= 35'd31744256419;
bram[257] <= 35'd31724046764;
bram[258] <= 35'd31703763381;
bram[259] <= 35'd31683406270;
bram[260] <= 35'd31662975431;
bram[261] <= 35'd31642470864;
bram[262] <= 35'd31621892570;
bram[263] <= 35'd31601232354;
bram[264] <= 35'd31580506603;
bram[265] <= 35'd31559707125;
bram[266] <= 35'd31538825726;
bram[267] <= 35'd31517870598;
bram[268] <= 35'd31496849936;
bram[269] <= 35'd31475747353;
bram[270] <= 35'd31454571041;
bram[271] <= 35'd31433329195;
bram[272] <= 35'd31412005428;
bram[273] <= 35'd31390607933;
bram[274] <= 35'd31369136710;
bram[275] <= 35'd31347591759;
bram[276] <= 35'd31325973080;
bram[277] <= 35'd31304280672;
bram[278] <= 35'd31282522730;
bram[279] <= 35'd31260682867;
bram[280] <= 35'd31238769276;
bram[281] <= 35'd31216781957;
bram[282] <= 35'd31194720909;
bram[283] <= 35'd31172594327;
bram[284] <= 35'd31150385824;
bram[285] <= 35'd31128103592;
bram[286] <= 35'd31105755826;
bram[287] <= 35'd31083326138;
bram[288] <= 35'd31060830915;
bram[289] <= 35'd31038261965;
bram[290] <= 35'd31015611093;
bram[291] <= 35'd30992894686;
bram[292] <= 35'd30970104551;
bram[293] <= 35'd30947240688;
bram[294] <= 35'd30924303096;
bram[295] <= 35'd30901299970;
bram[296] <= 35'd30878214922;
bram[297] <= 35'd30855064340;
bram[298] <= 35'd30831831836;
bram[299] <= 35'd30808533797;
bram[300] <= 35'd30785162030;
bram[301] <= 35'd30761716535;
bram[302] <= 35'd30738197311;
bram[303] <= 35'd30714612553;
bram[304] <= 35'd30690945873;
bram[305] <= 35'd30667213658;
bram[306] <= 35'd30643407715;
bram[307] <= 35'd30619528043;
bram[308] <= 35'd30595582837;
bram[309] <= 35'd30571555709;
bram[310] <= 35'd30547463046;
bram[311] <= 35'd30523296654;
bram[312] <= 35'd30499064728;
bram[313] <= 35'd30474750880;
bram[314] <= 35'd30450371497;
bram[315] <= 35'd30425918386;
bram[316] <= 35'd30401391546;
bram[317] <= 35'd30376799171;
bram[318] <= 35'd30352133068;
bram[319] <= 35'd30327393237;
bram[320] <= 35'd30302579677;
bram[321] <= 35'd30277700582;
bram[322] <= 35'd30252747759;
bram[323] <= 35'd30227721207;
bram[324] <= 35'd30202629120;
bram[325] <= 35'd30177463305;
bram[326] <= 35'd30152223762;
bram[327] <= 35'd30126910490;
bram[328] <= 35'd30101531682;
bram[329] <= 35'd30076087340;
bram[330] <= 35'd30050561076;
bram[331] <= 35'd30024969276;
bram[332] <= 35'd29999311941;
bram[333] <= 35'd29973580878;
bram[334] <= 35'd29947776087;
bram[335] <= 35'd29921897567;
bram[336] <= 35'd29895953511;
bram[337] <= 35'd29869943920;
bram[338] <= 35'd29843860601;
bram[339] <= 35'd29817703553;
bram[340] <= 35'd29791480970;
bram[341] <= 35'd29765184659;
bram[342] <= 35'd29738814619;
bram[343] <= 35'd29712379043;
bram[344] <= 35'd29685877932;
bram[345] <= 35'd29659303093;
bram[346] <= 35'd29632654525;
bram[347] <= 35'd29605940421;
bram[348] <= 35'd29579160782;
bram[349] <= 35'd29552307415;
bram[350] <= 35'd29525380319;
bram[351] <= 35'd29498387687;
bram[352] <= 35'd29471329520;
bram[353] <= 35'd29444197625;
bram[354] <= 35'd29416992001;
bram[355] <= 35'd29389720841;
bram[356] <= 35'd29362384146;
bram[357] <= 35'd29334973722;
bram[358] <= 35'd29307497762;
bram[359] <= 35'd29279956267;
bram[360] <= 35'd29252341044;
bram[361] <= 35'd29224652092;
bram[362] <= 35'd29196897604;
bram[363] <= 35'd29169077580;
bram[364] <= 35'd29141192021;
bram[365] <= 35'd29113232734;
bram[366] <= 35'd29085199717;
bram[367] <= 35'd29057109358;
bram[368] <= 35'd29028945270;
bram[369] <= 35'd29000715647;
bram[370] <= 35'd28972412295;
bram[371] <= 35'd28944043407;
bram[372] <= 35'd28915608984;
bram[373] <= 35'd28887100832;
bram[374] <= 35'd28858527144;
bram[375] <= 35'd28829887921;
bram[376] <= 35'd28801174968;
bram[377] <= 35'd28772404673;
bram[378] <= 35'd28743560650;
bram[379] <= 35'd28714642897;
bram[380] <= 35'd28685667802;
bram[381] <= 35'd28656618978;
bram[382] <= 35'd28627504618;
bram[383] <= 35'd28598324723;
bram[384] <= 35'd28569071098;
bram[385] <= 35'd28539760131;
bram[386] <= 35'd28510375435;
bram[387] <= 35'd28480925203;
bram[388] <= 35'd28451409436;
bram[389] <= 35'd28421819939;
bram[390] <= 35'd28392173100;
bram[391] <= 35'd28362452532;
bram[392] <= 35'd28332666428;
bram[393] <= 35'd28302814788;
bram[394] <= 35'd28272897612;
bram[395] <= 35'd28242914900;
bram[396] <= 35'd28212866653;
bram[397] <= 35'd28182744676;
bram[398] <= 35'd28152565357;
bram[399] <= 35'd28122312309;
bram[400] <= 35'd28091993724;
bram[401] <= 35'd28061617797;
bram[402] <= 35'd28031168141;
bram[403] <= 35'd28000652949;
bram[404] <= 35'd27970072221;
bram[405] <= 35'd27939425957;
bram[406] <= 35'd27908714157;
bram[407] <= 35'd27877936821;
bram[408] <= 35'd27847093949;
bram[409] <= 35'd27816185541;
bram[410] <= 35'd27785211597;
bram[411] <= 35'd27754172117;
bram[412] <= 35'd27723067101;
bram[413] <= 35'd27691896549;
bram[414] <= 35'd27660660460;
bram[415] <= 35'd27629367029;
bram[416] <= 35'd27597999869;
bram[417] <= 35'd27566567173;
bram[418] <= 35'd27535068940;
bram[419] <= 35'd27503513364;
bram[420] <= 35'd27471892253;
bram[421] <= 35'd27440197412;
bram[422] <= 35'd27408445228;
bram[423] <= 35'd27376627508;
bram[424] <= 35'd27344744252;
bram[425] <= 35'd27312795459;
bram[426] <= 35'd27280789324;
bram[427] <= 35'd27248709459;
bram[428] <= 35'd27216572251;
bram[429] <= 35'd27184369507;
bram[430] <= 35'd27152101227;
bram[431] <= 35'd27119767410;
bram[432] <= 35'd27087376250;
bram[433] <= 35'd27054919555;
bram[434] <= 35'd27022389129;
bram[435] <= 35'd26989809554;
bram[436] <= 35'd26957156249;
bram[437] <= 35'd26924445601;
bram[438] <= 35'd26891669417;
bram[439] <= 35'd26858827696;
bram[440] <= 35'd26825928633;
bram[441] <= 35'd26792955840;
bram[442] <= 35'd26759925703;
bram[443] <= 35'd26726838223;
bram[444] <= 35'd26693685207;
bram[445] <= 35'd26660466655;
bram[446] <= 35'd26627182566;
bram[447] <= 35'd26593841134;
bram[448] <= 35'd26560434165;
bram[449] <= 35'd26526969854;
bram[450] <= 35'd26493431812;
bram[451] <= 35'd26459844621;
bram[452] <= 35'd26426183699;
bram[453] <= 35'd26392473628;
bram[454] <= 35'd26358689827;
bram[455] <= 35'd26324848683;
bram[456] <= 35'd26290942002;
bram[457] <= 35'd26256977978;
bram[458] <= 35'd26222948417;
bram[459] <= 35'd26188861513;
bram[460] <= 35'd26154709072;
bram[461] <= 35'd26120499288;
bram[462] <= 35'd26086223967;
bram[463] <= 35'd26051891303;
bram[464] <= 35'd26017493102;
bram[465] <= 35'd25983037558;
bram[466] <= 35'd25948516477;
bram[467] <= 35'd25913938052;
bram[468] <= 35'd25879302284;
bram[469] <= 35'd25844600980;
bram[470] <= 35'd25809834139;
bram[471] <= 35'd25775009954;
bram[472] <= 35'd25740128426;
bram[473] <= 35'd25705181361;
bram[474] <= 35'd25670176952;
bram[475] <= 35'd25635115200;
bram[476] <= 35'd25599987911;
bram[477] <= 35'd25564803279;
bram[478] <= 35'd25529553109;
bram[479] <= 35'd25494253789;
bram[480] <= 35'd25458888933;
bram[481] <= 35'd25423458540;
bram[482] <= 35'd25387970803;
bram[483] <= 35'd25352425722;
bram[484] <= 35'd25316823298;
bram[485] <= 35'd25281155337;
bram[486] <= 35'd25245430032;
bram[487] <= 35'd25209647383;
bram[488] <= 35'd25173807391;
bram[489] <= 35'd25137901861;
bram[490] <= 35'd25101947181;
bram[491] <= 35'd25065926965;
bram[492] <= 35'd25029841211;
bram[493] <= 35'd24993706307;
bram[494] <= 35'd24957505865;
bram[495] <= 35'd24921256273;
bram[496] <= 35'd24884941144;
bram[497] <= 35'd24848568672;
bram[498] <= 35'd24812130662;
bram[499] <= 35'd24775643501;
bram[500] <= 35'd24739098997;
bram[501] <= 35'd24702488956;
bram[502] <= 35'd24665821570;
bram[503] <= 35'd24629105034;
bram[504] <= 35'd24592322961;
bram[505] <= 35'd24555483544;
bram[506] <= 35'd24518586783;
bram[507] <= 35'd24481632678;
bram[508] <= 35'd24444621229;
bram[509] <= 35'd24407552436;
bram[510] <= 35'd24370426299;
bram[511] <= 35'd24333242818;
bram[512] <= 35'd24296001993;
bram[513] <= 35'd24258703824;
bram[514] <= 35'd24221348311;
bram[515] <= 35'd24183935454;
bram[516] <= 35'd24146465252;
bram[517] <= 35'd24108945900;
bram[518] <= 35'd24071361011;
bram[519] <= 35'd24033718777;
bram[520] <= 35'd23996027393;
bram[521] <= 35'd23958270471;
bram[522] <= 35'd23920464398;
bram[523] <= 35'd23882600981;
bram[524] <= 35'd23844680220;
bram[525] <= 35'd23806702115;
bram[526] <= 35'd23768666666;
bram[527] <= 35'd23730573872;
bram[528] <= 35'd23692431927;
bram[529] <= 35'd23654232638;
bram[530] <= 35'd23615976005;
bram[531] <= 35'd23577662028;
bram[532] <= 35'd23539290706;
bram[533] <= 35'd23500870233;
bram[534] <= 35'd23462392416;
bram[535] <= 35'd23423857254;
bram[536] <= 35'd23385272941;
bram[537] <= 35'd23346631284;
bram[538] <= 35'd23307932283;
bram[539] <= 35'd23269175937;
bram[540] <= 35'd23230370440;
bram[541] <= 35'd23191507599;
bram[542] <= 35'd23152587413;
bram[543] <= 35'd23113618076;
bram[544] <= 35'd23074591395;
bram[545] <= 35'd23035507369;
bram[546] <= 35'd22996374192;
bram[547] <= 35'd22957183670;
bram[548] <= 35'd22917943997;
bram[549] <= 35'd22878646980;
bram[550] <= 35'd22839292618;
bram[551] <= 35'd22799889105;
bram[552] <= 35'd22760428247;
bram[553] <= 35'd22720918237;
bram[554] <= 35'd22681359077;
bram[555] <= 35'd22641734378;
bram[556] <= 35'd22602068722;
bram[557] <= 35'd22562337527;
bram[558] <= 35'd22522565375;
bram[559] <= 35'd22482727684;
bram[560] <= 35'd22442849035;
bram[561] <= 35'd22402913042;
bram[562] <= 35'd22362919704;
bram[563] <= 35'd22322877214;
bram[564] <= 35'd22282785573;
bram[565] <= 35'd22242636587;
bram[566] <= 35'd22202438450;
bram[567] <= 35'd22162182967;
bram[568] <= 35'd22121886527;
bram[569] <= 35'd22081524548;
bram[570] <= 35'd22041121611;
bram[571] <= 35'd22000661329;
bram[572] <= 35'd21960151896;
bram[573] <= 35'd21919585118;
bram[574] <= 35'd21878969188;
bram[575] <= 35'd21838304106;
bram[576] <= 35'd21797589873;
bram[577] <= 35'd21756818295;
bram[578] <= 35'd21715997565;
bram[579] <= 35'd21675127683;
bram[580] <= 35'd21634208650;
bram[581] <= 35'd21593232272;
bram[582] <= 35'd21552206742;
bram[583] <= 35'd21511132060;
bram[584] <= 35'd21470008226;
bram[585] <= 35'd21428835241;
bram[586] <= 35'd21387604910;
bram[587] <= 35'd21346333621;
bram[588] <= 35'd21305004987;
bram[589] <= 35'd21263627201;
bram[590] <= 35'd21222200263;
bram[591] <= 35'd21180724173;
bram[592] <= 35'd21139198932;
bram[593] <= 35'd21097616345;
bram[594] <= 35'd21055992799;
bram[595] <= 35'd21014320102;
bram[596] <= 35'd20972590059;
bram[597] <= 35'd20930819057;
bram[598] <= 35'd20888998904;
bram[599] <= 35'd20847121405;
bram[600] <= 35'd20805202948;
bram[601] <= 35'd20763227145;
bram[602] <= 35'd20721210383;
bram[603] <= 35'd20679144469;
bram[604] <= 35'd20637029404;
bram[605] <= 35'd20594856993;
bram[606] <= 35'd20552643623;
bram[607] <= 35'd20510381101;
bram[608] <= 35'd20468069426;
bram[609] <= 35'd20425716793;
bram[610] <= 35'd20383306814;
bram[611] <= 35'd20340855877;
bram[612] <= 35'd20298347594;
bram[613] <= 35'd20255798352;
bram[614] <= 35'd20213199958;
bram[615] <= 35'd20170552411;
bram[616] <= 35'd20127863906;
bram[617] <= 35'd20085118055;
bram[618] <= 35'd20042331245;
bram[619] <= 35'd19999495282;
bram[620] <= 35'd19956618361;
bram[621] <= 35'd19913684094;
bram[622] <= 35'd19870708867;
bram[623] <= 35'd19827692682;
bram[624] <= 35'd19784619151;
bram[625] <= 35'd19741504661;
bram[626] <= 35'd19698341018;
bram[627] <= 35'd19655136417;
bram[628] <= 35'd19611874469;
bram[629] <= 35'd19568579756;
bram[630] <= 35'd19525227697;
bram[631] <= 35'd19481834678;
bram[632] <= 35'd19438400701;
bram[633] <= 35'd19394909377;
bram[634] <= 35'd19351385288;
bram[635] <= 35'd19307803852;
bram[636] <= 35'd19264189651;
bram[637] <= 35'd19220518104;
bram[638] <= 35'd19176805597;
bram[639] <= 35'd19133052131;
bram[640] <= 35'd19089249513;
bram[641] <= 35'd19045397741;
bram[642] <= 35'd19001513204;
bram[643] <= 35'd18957571320;
bram[644] <= 35'd18913596671;
bram[645] <= 35'd18869564675;
bram[646] <= 35'd18825499913;
bram[647] <= 35'd18781385999;
bram[648] <= 35'd18737222932;
bram[649] <= 35'd18693018905;
bram[650] <= 35'd18648773918;
bram[651] <= 35'd18604487972;
bram[652] <= 35'd18560152873;
bram[653] <= 35'd18515776815;
bram[654] <= 35'd18471351604;
bram[655] <= 35'd18426885433;
bram[656] <= 35'd18382378302;
bram[657] <= 35'd18337830212;
bram[658] <= 35'd18293232969;
bram[659] <= 35'd18248594766;
bram[660] <= 35'd18203915603;
bram[661] <= 35'd18159195481;
bram[662] <= 35'd18114426206;
bram[663] <= 35'd18069615971;
bram[664] <= 35'd18024764776;
bram[665] <= 35'd17979872621;
bram[666] <= 35'd17934939507;
bram[667] <= 35'd17889957240;
bram[668] <= 35'd17844934012;
bram[669] <= 35'd17799878018;
bram[670] <= 35'd17754772871;
bram[671] <= 35'd17709626764;
bram[672] <= 35'd17664439697;
bram[673] <= 35'd17619211671;
bram[674] <= 35'd17573934491;
bram[675] <= 35'd17528624544;
bram[676] <= 35'd17483273638;
bram[677] <= 35'd17437873578;
bram[678] <= 35'd17392440751;
bram[679] <= 35'd17346966964;
bram[680] <= 35'd17301452218;
bram[681] <= 35'd17255888318;
bram[682] <= 35'd17210291651;
bram[683] <= 35'd17164654024;
bram[684] <= 35'd17118975437;
bram[685] <= 35'd17073255890;
bram[686] <= 35'd17027495383;
bram[687] <= 35'd16981693916;
bram[688] <= 35'd16935851488;
bram[689] <= 35'd16889976294;
bram[690] <= 35'd16844051946;
bram[691] <= 35'd16798094831;
bram[692] <= 35'd16752096756;
bram[693] <= 35'd16706057720;
bram[694] <= 35'd16659985918;
bram[695] <= 35'd16613864962;
bram[696] <= 35'd16567711239;
bram[697] <= 35'd16521516556;
bram[698] <= 35'd16475280912;
bram[699] <= 35'd16429012502;
bram[700] <= 35'd16382694937;
bram[701] <= 35'd16336352799;
bram[702] <= 35'd16289961507;
bram[703] <= 35'd16243537448;
bram[704] <= 35'd16197072429;
bram[705] <= 35'd16150566449;
bram[706] <= 35'd16104027702;
bram[707] <= 35'd16057447994;
bram[708] <= 35'd16010835519;
bram[709] <= 35'd15964182084;
bram[710] <= 35'd15917487688;
bram[711] <= 35'd15870760525;
bram[712] <= 35'd15823992401;
bram[713] <= 35'd15777191510;
bram[714] <= 35'd15730349659;
bram[715] <= 35'd15683466847;
bram[716] <= 35'd15636551267;
bram[717] <= 35'd15589602920;
bram[718] <= 35'd15542613612;
bram[719] <= 35'd15495591537;
bram[720] <= 35'd15448528501;
bram[721] <= 35'd15401432698;
bram[722] <= 35'd15354295934;
bram[723] <= 35'd15307126402;
bram[724] <= 35'd15259924103;
bram[725] <= 35'd15212680843;
bram[726] <= 35'd15165404816;
bram[727] <= 35'd15118087828;
bram[728] <= 35'd15070738072;
bram[729] <= 35'd15023355548;
bram[730] <= 35'd14975940257;
bram[731] <= 35'd14928484005;
bram[732] <= 35'd14880994986;
bram[733] <= 35'd14833465005;
bram[734] <= 35'd14785910450;
bram[735] <= 35'd14738314934;
bram[736] <= 35'd14690686651;
bram[737] <= 35'd14643017406;
bram[738] <= 35'd14595323587;
bram[739] <= 35'd14547588807;
bram[740] <= 35'd14499821259;
bram[741] <= 35'd14452020943;
bram[742] <= 35'd14404187860;
bram[743] <= 35'd14356313815;
bram[744] <= 35'd14308415196;
bram[745] <= 35'd14260475616;
bram[746] <= 35'd14212503267;
bram[747] <= 35'd14164506344;
bram[748] <= 35'd14116468460;
bram[749] <= 35'd14068397808;
bram[750] <= 35'd14020294388;
bram[751] <= 35'd13972158200;
bram[752] <= 35'd13923989244;
bram[753] <= 35'd13875787520;
bram[754] <= 35'd13827553028;
bram[755] <= 35'd13779285768;
bram[756] <= 35'd13730985740;
bram[757] <= 35'd13682652944;
bram[758] <= 35'd13634287379;
bram[759] <= 35'd13585897240;
bram[760] <= 35'd13537466140;
bram[761] <= 35'd13489002271;
bram[762] <= 35'd13440513827;
bram[763] <= 35'd13391992615;
bram[764] <= 35'd13343438635;
bram[765] <= 35'd13294851887;
bram[766] <= 35'd13246232370;
bram[767] <= 35'd13197588279;
bram[768] <= 35'd13148903226;
bram[769] <= 35'd13100193598;
bram[770] <= 35'd13051451201;
bram[771] <= 35'd13002684230;
bram[772] <= 35'd12953876297;
bram[773] <= 35'd12905043789;
bram[774] <= 35'd12856178512;
bram[775] <= 35'd12807288660;
bram[776] <= 35'd12758366040;
bram[777] <= 35'd12709410651;
bram[778] <= 35'd12660430688;
bram[779] <= 35'd12611409762;
bram[780] <= 35'd12562372455;
bram[781] <= 35'd12513294186;
bram[782] <= 35'd12464191341;
bram[783] <= 35'd12415063921;
bram[784] <= 35'd12365903733;
bram[785] <= 35'd12316710776;
bram[786] <= 35'd12267493244;
bram[787] <= 35'd12218242943;
bram[788] <= 35'd12168968067;
bram[789] <= 35'd12119660422;
bram[790] <= 35'd12070328201;
bram[791] <= 35'd12020971405;
bram[792] <= 35'd11971581841;
bram[793] <= 35'd11922159508;
bram[794] <= 35'd11872712599;
bram[795] <= 35'd11823241115;
bram[796] <= 35'd11773736862;
bram[797] <= 35'd11724208034;
bram[798] <= 35'd11674646437;
bram[799] <= 35'd11625060264;
bram[800] <= 35'd11575449515;
bram[801] <= 35'd11525814191;
bram[802] <= 35'd11476146098;
bram[803] <= 35'd11426453430;
bram[804] <= 35'd11376727993;
bram[805] <= 35'd11326977979;
bram[806] <= 35'd11277211584;
bram[807] <= 35'd11227404226;
bram[808] <= 35'd11177580486;
bram[809] <= 35'd11127723977;
bram[810] <= 35'd11077842892;
bram[811] <= 35'd11027937231;
bram[812] <= 35'd10978006994;
bram[813] <= 35'd10928052181;
bram[814] <= 35'd10878072793;
bram[815] <= 35'd10828060636;
bram[816] <= 35'd10778023903;
bram[817] <= 35'd10727962593;
bram[818] <= 35'd10677884901;
bram[819] <= 35'd10627774440;
bram[820] <= 35'd10577639403;
bram[821] <= 35'd10527479790;
bram[822] <= 35'd10477295601;
bram[823] <= 35'd10427086837;
bram[824] <= 35'd10376845303;
bram[825] <= 35'd10326587386;
bram[826] <= 35'd10276304893;
bram[827] <= 35'd10225997823;
bram[828] <= 35'd10175674371;
bram[829] <= 35'd10125318150;
bram[830] <= 35'd10074937353;
bram[831] <= 35'd10024531979;
bram[832] <= 35'd9974110222;
bram[833] <= 35'd9923663890;
bram[834] <= 35'd9873184788;
bram[835] <= 35'd9822689303;
bram[836] <= 35'd9772169241;
bram[837] <= 35'd9721632797;
bram[838] <= 35'd9671063583;
bram[839] <= 35'd9620477986;
bram[840] <= 35'd9569867813;
bram[841] <= 35'd9519233063;
bram[842] <= 35'd9468581931;
bram[843] <= 35'd9417898028;
bram[844] <= 35'd9367205936;
bram[845] <= 35'd9316481074;
bram[846] <= 35'd9265739829;
bram[847] <= 35'd9214974008;
bram[848] <= 35'd9164183610;
bram[849] <= 35'd9113376829;
bram[850] <= 35'd9062545471;
bram[851] <= 35'd9011697730;
bram[852] <= 35'd8960825413;
bram[853] <= 35'd8909928519;
bram[854] <= 35'd8859015242;
bram[855] <= 35'd8808077388;
bram[856] <= 35'd8757123151;
bram[857] <= 35'd8706144337;
bram[858] <= 35'd8655149140;
bram[859] <= 35'd8604129366;
bram[860] <= 35'd8553093209;
bram[861] <= 35'd8502032475;
bram[862] <= 35'd8450955358;
bram[863] <= 35'd8399853664;
bram[864] <= 35'd8348735586;
bram[865] <= 35'd8297601125;
bram[866] <= 35'd8246442087;
bram[867] <= 35'd8195266665;
bram[868] <= 35'd8144074860;
bram[869] <= 35'd8092858478;
bram[870] <= 35'd8041625713;
bram[871] <= 35'd7990368370;
bram[872] <= 35'd7939102837;
bram[873] <= 35'd7887812728;
bram[874] <= 35'd7836498041;
bram[875] <= 35'd7785175164;
bram[876] <= 35'd7733827710;
bram[877] <= 35'd7682463872;
bram[878] <= 35'd7631083650;
bram[879] <= 35'd7579687045;
bram[880] <= 35'd7528265863;
bram[881] <= 35'd7476828297;
bram[882] <= 35'd7425374347;
bram[883] <= 35'd7373904013;
bram[884] <= 35'd7322417295;
bram[885] <= 35'd7270914193;
bram[886] <= 35'd7219394708;
bram[887] <= 35'd7167850645;
bram[888] <= 35'd7116298392;
bram[889] <= 35'd7064721561;
bram[890] <= 35'd7013136540;
bram[891] <= 35'd6961526941;
bram[892] <= 35'd6909909152;
bram[893] <= 35'd6858266785;
bram[894] <= 35'd6806616228;
bram[895] <= 35'd6754941093;
bram[896] <= 35'd6703257767;
bram[897] <= 35'd6651558058;
bram[898] <= 35'd6599833771;
bram[899] <= 35'd6548101293;
bram[900] <= 35'd6496352431;
bram[901] <= 35'd6444587184;
bram[902] <= 35'd6392813747;
bram[903] <= 35'd6341015732;
bram[904] <= 35'd6289209526;
bram[905] <= 35'd6237386936;
bram[906] <= 35'd6185547962;
bram[907] <= 35'd6133692604;
bram[908] <= 35'd6081820861;
bram[909] <= 35'd6029940927;
bram[910] <= 35'd5978044609;
bram[911] <= 35'd5926131906;
bram[912] <= 35'd5874211012;
bram[913] <= 35'd5822273734;
bram[914] <= 35'd5770320071;
bram[915] <= 35'd5718358217;
bram[916] <= 35'd5666379979;
bram[917] <= 35'd5614385356;
bram[918] <= 35'd5562382542;
bram[919] <= 35'd5510363344;
bram[920] <= 35'd5458327761;
bram[921] <= 35'd5406283986;
bram[922] <= 35'd5354232021;
bram[923] <= 35'd5302155477;
bram[924] <= 35'd5250078935;
bram[925] <= 35'd5197986009;
bram[926] <= 35'd5145876698;
bram[927] <= 35'd5093759196;
bram[928] <= 35'd5041625309;
bram[929] <= 35'd4989483230;
bram[930] <= 35'd4937332960;
bram[931] <= 35'd4885166306;
bram[932] <= 35'd4832983266;
bram[933] <= 35'd4780800229;
bram[934] <= 35'd4728592613;
bram[935] <= 35'd4676384999;
bram[936] <= 35'd4624161000;
bram[937] <= 35'd4571928809;
bram[938] <= 35'd4519688427;
bram[939] <= 35'd4467431660;
bram[940] <= 35'd4415166701;
bram[941] <= 35'd4362893551;
bram[942] <= 35'd4310604016;
bram[943] <= 35'd4258306289;
bram[944] <= 35'd4206000370;
bram[945] <= 35'd4153686259;
bram[946] <= 35'd4101363957;
bram[947] <= 35'd4049025269;
bram[948] <= 35'd3996686583;
bram[949] <= 35'd3944331512;
bram[950] <= 35'd3891968249;
bram[951] <= 35'd3839596795;
bram[952] <= 35'd3787208955;
bram[953] <= 35'd3734821116;
bram[954] <= 35'd3682425086;
bram[955] <= 35'd3630012670;
bram[956] <= 35'd3577600256;
bram[957] <= 35'd3525171456;
bram[958] <= 35'd3472742658;
bram[959] <= 35'd3420297474;
bram[960] <= 35'd3367852292;
bram[961] <= 35'd3315390724;
bram[962] <= 35'd3262929158;
bram[963] <= 35'd3210451206;
bram[964] <= 35'd3157973255;
bram[965] <= 35'd3105487112;
bram[966] <= 35'd3052992777;
bram[967] <= 35'd3000490250;
bram[968] <= 35'd2947979531;
bram[969] <= 35'd2895460619;
bram[970] <= 35'd2842941709;
bram[971] <= 35'd2790406413;
bram[972] <= 35'd2737871118;
bram[973] <= 35'd2685327630;
bram[974] <= 35'd2632784144;
bram[975] <= 35'd2580224272;
bram[976] <= 35'd2527664401;
bram[977] <= 35'd2475096337;
bram[978] <= 35'd2422528275;
bram[979] <= 35'd2369943827;
bram[980] <= 35'd2317359379;
bram[981] <= 35'd2264774933;
bram[982] <= 35'd2212174101;
bram[983] <= 35'd2159573269;
bram[984] <= 35'd2106972438;
bram[985] <= 35'd2054363415;
bram[986] <= 35'd2001746200;
bram[987] <= 35'd1949120791;
bram[988] <= 35'd1896503577;
bram[989] <= 35'd1843869977;
bram[990] <= 35'd1791236377;
bram[991] <= 35'd1738602778;
bram[992] <= 35'd1685960987;
bram[993] <= 35'd1633311003;
bram[994] <= 35'd1580661019;
bram[995] <= 35'd1528011036;
bram[996] <= 35'd1475352860;
bram[997] <= 35'd1422694685;
bram[998] <= 35'd1370028317;
bram[999] <= 35'd1317361949;
bram[1000] <= 35'd1264695582;
bram[1001] <= 35'd1212021022;
bram[1002] <= 35'd1159346463;
bram[1003] <= 35'd1106663711;
bram[1004] <= 35'd1053980959;
bram[1005] <= 35'd1001298207;
bram[1006] <= 35'd948615456;
bram[1007] <= 35'd895924512;
bram[1008] <= 35'd843233568;
bram[1009] <= 35'd790542624;
bram[1010] <= 35'd737851681;
bram[1011] <= 35'd685152545;
bram[1012] <= 35'd632453409;
bram[1013] <= 35'd579754273;
bram[1014] <= 35'd527055137;
bram[1015] <= 35'd474356001;
bram[1016] <= 35'd421656866;
bram[1017] <= 35'd368949538;
bram[1018] <= 35'd316242209;
bram[1019] <= 35'd263543074;
bram[1020] <= 35'd210835746;
bram[1021] <= 35'd158128418;
bram[1022] <= 35'd105421090;
bram[1023] <= 35'd52713762;
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Base Mixed Mode Clock Manager (MMCM)
// /___/ /\ Filename : MMCME3_BASE.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 10/22/2014 808642 - Added #1 to $finish
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MMCME3_BASE #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter BANDWIDTH = "OPTIMIZED",
parameter real CLKFBOUT_MULT_F = 5.000,
parameter real CLKFBOUT_PHASE = 0.000,
parameter real CLKIN1_PERIOD = 0.000,
parameter real CLKOUT0_DIVIDE_F = 1.000,
parameter real CLKOUT0_DUTY_CYCLE = 0.500,
parameter real CLKOUT0_PHASE = 0.000,
parameter integer CLKOUT1_DIVIDE = 1,
parameter real CLKOUT1_DUTY_CYCLE = 0.500,
parameter real CLKOUT1_PHASE = 0.000,
parameter integer CLKOUT2_DIVIDE = 1,
parameter real CLKOUT2_DUTY_CYCLE = 0.500,
parameter real CLKOUT2_PHASE = 0.000,
parameter integer CLKOUT3_DIVIDE = 1,
parameter real CLKOUT3_DUTY_CYCLE = 0.500,
parameter real CLKOUT3_PHASE = 0.000,
parameter CLKOUT4_CASCADE = "FALSE",
parameter integer CLKOUT4_DIVIDE = 1,
parameter real CLKOUT4_DUTY_CYCLE = 0.500,
parameter real CLKOUT4_PHASE = 0.000,
parameter integer CLKOUT5_DIVIDE = 1,
parameter real CLKOUT5_DUTY_CYCLE = 0.500,
parameter real CLKOUT5_PHASE = 0.000,
parameter integer CLKOUT6_DIVIDE = 1,
parameter real CLKOUT6_DUTY_CYCLE = 0.500,
parameter real CLKOUT6_PHASE = 0.000,
parameter integer DIVCLK_DIVIDE = 1,
parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0,
parameter [0:0] IS_CLKIN1_INVERTED = 1'b0,
parameter [0:0] IS_PWRDWN_INVERTED = 1'b0,
parameter [0:0] IS_RST_INVERTED = 1'b0,
parameter real REF_JITTER1 = 0.010,
parameter STARTUP_WAIT = "FALSE"
)(
output CLKFBOUT,
output CLKFBOUTB,
output CLKOUT0,
output CLKOUT0B,
output CLKOUT1,
output CLKOUT1B,
output CLKOUT2,
output CLKOUT2B,
output CLKOUT3,
output CLKOUT3B,
output CLKOUT4,
output CLKOUT5,
output CLKOUT6,
output LOCKED,
input CLKFBIN,
input CLKIN1,
input PWRDWN,
input RST
);
// define constants
localparam MODULE_NAME = "MMCME3_BASE";
reg trig_attr = 1'b0;
localparam [0:0] IS_CLKFBIN_INVERTED_REG = IS_CLKFBIN_INVERTED;
localparam [0:0] IS_CLKIN1_INVERTED_REG = IS_CLKIN1_INVERTED;
localparam [0:0] IS_PWRDWN_INVERTED_REG = IS_PWRDWN_INVERTED;
localparam [0:0] IS_RST_INVERTED_REG = IS_RST_INVERTED;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
wire CLKFBIN_in;
wire CLKIN1_in;
wire PWRDWN_in;
wire RST_in;
assign CLKFBIN_in = (CLKFBIN !== 1'bz) && (CLKFBIN ^ IS_CLKFBIN_INVERTED_REG); // rv 0
assign CLKIN1_in = (CLKIN1 !== 1'bz) && (CLKIN1 ^ IS_CLKIN1_INVERTED_REG); // rv 0
assign PWRDWN_in = (PWRDWN !== 1'bz) && (PWRDWN ^ IS_PWRDWN_INVERTED_REG); // rv 0
assign RST_in = (RST !== 1'bz) && (RST ^ IS_RST_INVERTED_REG); // rv 0
initial begin
#1;
trig_attr = ~trig_attr;
end
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((IS_CLKFBIN_INVERTED_REG !== 1'b0) && (IS_CLKFBIN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-142] IS_CLKFBIN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKFBIN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_CLKIN1_INVERTED_REG !== 1'b0) && (IS_CLKIN1_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-143] IS_CLKIN1_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_CLKIN1_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_PWRDWN_INVERTED_REG !== 1'b0) && (IS_PWRDWN_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-148] IS_PWRDWN_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_PWRDWN_INVERTED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((IS_RST_INVERTED_REG !== 1'b0) && (IS_RST_INVERTED_REG !== 1'b1))) begin
$display("Error: [Unisim %s-149] IS_RST_INVERTED attribute is set to %b. Legal values for this attribute are 1'b0 to 1'b1. Instance: %m", MODULE_NAME, IS_RST_INVERTED_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
`ifndef XIL_XECLIB
initial begin
#1;
if ($realtime == 0) begin
$display ("Error: [Unisim %s-1] Simulator resolution is set to a value greater than 1 ps. ", MODULE_NAME);
$display ("The simulator resolution must be set to 1ps or smaller. Instance %m");
#1 $finish;
end
end
`endif
wire CDDCDONE;
wire DRDY;
wire PSDONE;
wire CLKFBSTOPPED;
wire CLKINSTOPPED;
wire [15:0] DO;
MMCME3_ADV #(
.BANDWIDTH(BANDWIDTH),
.CLKFBOUT_MULT_F(CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE(CLKFBOUT_PHASE),
.CLKIN1_PERIOD(CLKIN1_PERIOD),
.CLKIN2_PERIOD(10),
.CLKOUT0_DIVIDE_F(CLKOUT0_DIVIDE_F),
.CLKOUT0_DUTY_CYCLE(CLKOUT0_DUTY_CYCLE),
.CLKOUT0_PHASE(CLKOUT0_PHASE),
.CLKOUT1_DIVIDE(CLKOUT1_DIVIDE),
.CLKOUT1_DUTY_CYCLE(CLKOUT1_DUTY_CYCLE),
.CLKOUT1_PHASE(CLKOUT1_PHASE),
.CLKOUT2_DIVIDE(CLKOUT2_DIVIDE),
.CLKOUT2_DUTY_CYCLE(CLKOUT2_DUTY_CYCLE),
.CLKOUT2_PHASE(CLKOUT2_PHASE),
.CLKOUT3_DIVIDE(CLKOUT3_DIVIDE),
.CLKOUT3_DUTY_CYCLE(CLKOUT3_DUTY_CYCLE),
.CLKOUT3_PHASE(CLKOUT3_PHASE),
.CLKOUT4_CASCADE(CLKOUT4_CASCADE),
.CLKOUT4_DIVIDE(CLKOUT4_DIVIDE),
.CLKOUT4_DUTY_CYCLE(CLKOUT4_DUTY_CYCLE),
.CLKOUT4_PHASE(CLKOUT4_PHASE),
.CLKOUT5_DIVIDE(CLKOUT5_DIVIDE),
.CLKOUT5_DUTY_CYCLE(CLKOUT5_DUTY_CYCLE),
.CLKOUT5_PHASE(CLKOUT5_PHASE),
.CLKOUT6_DIVIDE(CLKOUT6_DIVIDE),
.CLKOUT6_DUTY_CYCLE(CLKOUT6_DUTY_CYCLE),
.CLKOUT6_PHASE(CLKOUT6_PHASE),
.DIVCLK_DIVIDE(DIVCLK_DIVIDE),
.REF_JITTER1(REF_JITTER1),
.STARTUP_WAIT(STARTUP_WAIT)
) mmcm_adv_1 (
.CDDCDONE (CDDCDONE),
.CLKFBOUT (CLKFBOUT),
.CLKFBOUTB (CLKFBOUTB),
.CLKFBSTOPPED(CLKFBSTOPPED),
.CLKINSTOPPED(CLKINSTOPPED),
.CLKOUT0 (CLKOUT0),
.CLKOUT0B (CLKOUT0B),
.CLKOUT1 (CLKOUT1),
.CLKOUT1B (CLKOUT1B),
.CLKOUT2 (CLKOUT2),
.CLKOUT2B (CLKOUT2B),
.CLKOUT3 (CLKOUT3),
.CLKOUT3B (CLKOUT3B),
.CLKOUT4 (CLKOUT4),
.CLKOUT5 (CLKOUT5),
.CLKOUT6 (CLKOUT6),
.DO (DO),
.DRDY (DRDY),
.LOCKED (LOCKED),
.PSDONE(PSDONE),
.CDDCREQ (1'b0),
.CLKFBIN (CLKFBIN_in),
.CLKIN1 (CLKIN1_in),
.CLKIN2 (1'b0),
.CLKINSEL(1'b1),
.DADDR (7'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.PSCLK(1'b0),
.PSEN(1'b0),
.PSINCDEC(1'b0),
.PWRDWN(PWRDWN_in),
.RST (RST_in)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(negedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
(posedge RST => (LOCKED +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLKFBIN, 0:0:0, notifier);
$period (negedge CLKFBOUT, 0:0:0, notifier);
$period (negedge CLKFBOUTB, 0:0:0, notifier);
$period (negedge CLKIN1, 0:0:0, notifier);
$period (negedge CLKOUT0, 0:0:0, notifier);
$period (negedge CLKOUT0B, 0:0:0, notifier);
$period (negedge CLKOUT1, 0:0:0, notifier);
$period (negedge CLKOUT1B, 0:0:0, notifier);
$period (negedge CLKOUT2, 0:0:0, notifier);
$period (negedge CLKOUT2B, 0:0:0, notifier);
$period (negedge CLKOUT3, 0:0:0, notifier);
$period (negedge CLKOUT3B, 0:0:0, notifier);
$period (negedge CLKOUT4, 0:0:0, notifier);
$period (negedge CLKOUT5, 0:0:0, notifier);
$period (negedge CLKOUT6, 0:0:0, notifier);
$period (posedge CLKFBIN, 0:0:0, notifier);
$period (posedge CLKFBOUT, 0:0:0, notifier);
$period (posedge CLKFBOUTB, 0:0:0, notifier);
$period (posedge CLKIN1, 0:0:0, notifier);
$period (posedge CLKOUT0, 0:0:0, notifier);
$period (posedge CLKOUT0B, 0:0:0, notifier);
$period (posedge CLKOUT1, 0:0:0, notifier);
$period (posedge CLKOUT1B, 0:0:0, notifier);
$period (posedge CLKOUT2, 0:0:0, notifier);
$period (posedge CLKOUT2B, 0:0:0, notifier);
$period (posedge CLKOUT3, 0:0:0, notifier);
$period (posedge CLKOUT3B, 0:0:0, notifier);
$period (posedge CLKOUT4, 0:0:0, notifier);
$period (posedge CLKOUT5, 0:0:0, notifier);
$period (posedge CLKOUT6, 0:0:0, notifier);
$width (negedge CLKIN1, 0:0:0, 0, notifier);
$width (negedge PWRDWN, 0:0:0, 0, notifier);
$width (negedge RST, 0:0:0, 0, notifier);
$width (posedge CLKIN1, 0:0:0, 0, notifier);
$width (posedge PWRDWN, 0:0:0, 0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//====================================================================
// bsg_idiv_iterative_controller.v
// 11/14/2016, [email protected]
//====================================================================
//
// The controller of bsg_idiv_iterative module.
// Code refactored based on Sam Larser's work
`include "bsg_defines.v"
module bsg_idiv_iterative_controller #(parameter width_p=32)
(input clk_i
,input reset_i
,input v_i
,output ready_and_o
,input zero_divisor_i
,input signed_div_r_i
,input adder_result_is_neg_i
,input opA_is_neg_i
,input opC_is_neg_i
,output logic opA_sel_o
,output logic opA_ld_o
,output logic opA_inv_o
,output logic opA_clr_l_o
,output logic [2:0] opB_sel_o
,output logic opB_ld_o
,output logic opB_inv_o
,output logic opB_clr_l_o
,output logic [2:0] opC_sel_o
,output logic opC_ld_o
,output logic latch_signed_div_o
,output logic adder_cin_o
,output logic v_o
,input yumi_i
);
reg q_neg;
reg r_neg;
reg neg_ld;
reg add_neg_last;
typedef enum logic[5:0]
{WAIT, NEG0, NEG1, SHIFT,
CALC,
REPAIR, REMAIN,
QUOT,DONE } idiv_ctrl_stat;
idiv_ctrl_stat state, next_state;
always @(posedge clk_i) begin
add_neg_last <= adder_result_is_neg_i;
if (neg_ld) begin
// the quotient is negated if the signs of the operands differ
q_neg <= (opA_is_neg_i ^ opC_is_neg_i) & signed_div_r_i;
// the remainder is negated if the dividend is negative
r_neg <= opC_is_neg_i & signed_div_r_i;
end
end
logic [`BSG_SAFE_CLOG2(width_p+1)-1:0] calc_cnt;
wire calc_up_li = (state == CALC) && (calc_cnt < width_p);
wire calc_done = (calc_cnt == width_p);
bsg_counter_clear_up#(.max_val_p(width_p)
,.init_val_p(0)
,.disable_overflow_warning_p(1)) calc_counter
(.clk_i(clk_i)
,.reset_i(reset_i)
// We rely on natural overflow
,.clear_i(calc_done)
,.up_i(calc_up_li)
,.count_o(calc_cnt)
);
// synopsys sync_set_reset "reset_i"
always @(posedge clk_i) begin
if (reset_i) state <= WAIT;
else state <= next_state;
end
always_comb begin
opA_sel_o = 1'b0;
opA_ld_o = 1'b0;
opA_inv_o = !add_neg_last;
opA_clr_l_o = 1'b1;
opB_sel_o = 3'b001;
opB_ld_o = 1'b1;
opB_inv_o = 1'b0;
opB_clr_l_o = 1'b1;
opC_sel_o = 3'b001;
opC_ld_o = 1'b1;
adder_cin_o = !add_neg_last;
neg_ld = 1'b0;
latch_signed_div_o = 1'b0;
next_state = WAIT;
case (state)
WAIT: begin
if (v_i) begin
opA_ld_o = 1'b1;
opC_ld_o = 1'b1;
latch_signed_div_o = 1'b1;
next_state = NEG0;
end
opA_sel_o = 1'b1;
opC_sel_o = 3'b100;
end
NEG0: begin
next_state = (opC_is_neg_i & signed_div_r_i) ? NEG1 : SHIFT;
opA_inv_o = 1'b1;
opB_clr_l_o = 1'b0;
opB_sel_o = 3'b100;
opC_ld_o = 1'b0;
neg_ld = 1'b1;
adder_cin_o = 1'b1;
opA_ld_o = opA_is_neg_i & signed_div_r_i;
end
NEG1: begin
next_state = SHIFT;
opA_clr_l_o = 1'b0;
opB_inv_o = 1'b1;
opB_ld_o = 1'b0;
opC_sel_o = 3'b010;
adder_cin_o = 1'b1;
end
SHIFT: begin
next_state = CALC;
opA_clr_l_o = 1'b0;
opB_clr_l_o = 1'b0;
adder_cin_o = 1'b0;
end
CALC: begin
opB_sel_o = calc_done ? 3'b010 : 3'b001;
if (calc_done) begin
if (adder_result_is_neg_i) next_state = REPAIR;
else next_state = REMAIN;
end else
next_state = CALC;
end
REPAIR: begin
next_state = REMAIN;
opA_inv_o = 1'b0;
opB_sel_o = 3'b010;
opC_ld_o = 1'b0;
adder_cin_o = 1'b0;
end
REMAIN: begin
next_state = (zero_divisor_i | !q_neg) ? DONE: QUOT;
opA_ld_o = 1'b1;
opA_clr_l_o = 1'b0;
opB_sel_o = 3'b100;
opC_ld_o = 1'b0;
opB_inv_o = r_neg;
adder_cin_o = r_neg;
end
QUOT: begin
next_state = DONE;
opA_clr_l_o = 1'b0;
opB_inv_o = 1'b1;
opB_ld_o = 1'b0;
opC_sel_o = 3'b010;
adder_cin_o = 1'b1;
end
DONE:begin
if( yumi_i ) next_state = WAIT;
else next_state = DONE;
opA_ld_o = 1'b0;
opB_ld_o = 1'b0;
opC_ld_o = 1'b0;
end
endcase
end
assign ready_and_o = ( state == WAIT );
assign v_o = ( state == DONE );
endmodule // divide_control
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_BEHAVIORAL_V
`define SKY130_FD_SC_LP__AND3_BEHAVIORAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_BEHAVIORAL_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// Transmit HDMI, video dma data in, hdmi separate syncs data out.
module axi_hdmi_tx_core (
// hdmi interface
hdmi_clk,
hdmi_rst,
// 16-bit interface
hdmi_16_hsync,
hdmi_16_vsync,
hdmi_16_data_e,
hdmi_16_data,
hdmi_16_es_data,
// 24-bit interface
hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_data_e,
hdmi_24_data,
// 36-bit interface
hdmi_36_hsync,
hdmi_36_vsync,
hdmi_36_data_e,
hdmi_36_data,
// control signals
hdmi_fs_toggle,
hdmi_raddr_g,
hdmi_tpm_oos,
hdmi_status,
// vdma interface
vdma_clk,
vdma_wr,
vdma_waddr,
vdma_wdata,
vdma_fs_ret_toggle,
vdma_fs_waddr,
// processor interface
hdmi_full_range,
hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min);
// parameters
parameter Cr_Cb_N = 0;
parameter EMBEDDED_SYNC = 0;
// hdmi interface
input hdmi_clk;
input hdmi_rst;
// 16-bit interface
output hdmi_16_hsync;
output hdmi_16_vsync;
output hdmi_16_data_e;
output [15:0] hdmi_16_data;
output [15:0] hdmi_16_es_data;
// 24-bit interface
output hdmi_24_hsync;
output hdmi_24_vsync;
output hdmi_24_data_e;
output [23:0] hdmi_24_data;
// 36-bit interface
output hdmi_36_hsync;
output hdmi_36_vsync;
output hdmi_36_data_e;
output [35:0] hdmi_36_data;
// control signals
output hdmi_fs_toggle;
output [ 8:0] hdmi_raddr_g;
output hdmi_tpm_oos;
output hdmi_status;
// vdma interface
input vdma_clk;
input vdma_wr;
input [ 8:0] vdma_waddr;
input [47:0] vdma_wdata;
input vdma_fs_ret_toggle;
input [ 8:0] vdma_fs_waddr;
// processor interface
input hdmi_full_range;
input hdmi_csc_bypass;
input hdmi_ss_bypass;
input [ 1:0] hdmi_srcsel;
input [23:0] hdmi_const_rgb;
input [15:0] hdmi_hl_active;
input [15:0] hdmi_hl_width;
input [15:0] hdmi_hs_width;
input [15:0] hdmi_he_max;
input [15:0] hdmi_he_min;
input [15:0] hdmi_vf_active;
input [15:0] hdmi_vf_width;
input [15:0] hdmi_vs_width;
input [15:0] hdmi_ve_max;
input [15:0] hdmi_ve_min;
// internal registers
reg hdmi_status = 'd0;
reg hdmi_enable = 'd0;
reg [15:0] hdmi_hs_count = 'd0;
reg [15:0] hdmi_vs_count = 'd0;
reg hdmi_fs = 'd0;
reg hdmi_fs_toggle = 'd0;
reg hdmi_fs_ret_toggle_m1 = 'd0;
reg hdmi_fs_ret_toggle_m2 = 'd0;
reg hdmi_fs_ret_toggle_m3 = 'd0;
reg hdmi_fs_ret = 'd0;
reg [ 8:0] hdmi_fs_waddr = 'd0;
reg hdmi_hs = 'd0;
reg hdmi_vs = 'd0;
reg hdmi_hs_de = 'd0;
reg hdmi_vs_de = 'd0;
reg [ 9:0] hdmi_raddr = 'd0;
reg [ 8:0] hdmi_raddr_g = 'd0;
reg hdmi_hs_d = 'd0;
reg hdmi_vs_d = 'd0;
reg hdmi_hs_de_d = 'd0;
reg hdmi_vs_de_d = 'd0;
reg hdmi_de_d = 'd0;
reg hdmi_data_sel_d = 'd0;
reg hdmi_hs_2d = 'd0;
reg hdmi_vs_2d = 'd0;
reg hdmi_hs_de_2d = 'd0;
reg hdmi_vs_de_2d = 'd0;
reg hdmi_de_2d = 'd0;
reg hdmi_data_sel_2d = 'd0;
reg [47:0] hdmi_data_2d = 'd0;
reg [23:0] hdmi_tpm_data = 'd0;
reg hdmi_tpm_oos = 'd0;
reg hdmi_hsync = 'd0;
reg hdmi_vsync = 'd0;
reg hdmi_hsync_data_e = 'd0;
reg hdmi_vsync_data_e = 'd0;
reg hdmi_data_e = 'd0;
reg [23:0] hdmi_data = 'd0;
reg hdmi_24_hsync = 'd0;
reg hdmi_24_vsync = 'd0;
reg hdmi_24_hsync_data_e = 'd0;
reg hdmi_24_vsync_data_e = 'd0;
reg hdmi_24_data_e = 'd0;
reg [23:0] hdmi_24_data = 'd0;
reg hdmi_16_hsync = 'd0;
reg hdmi_16_vsync = 'd0;
reg hdmi_16_hsync_data_e = 'd0;
reg hdmi_16_vsync_data_e = 'd0;
reg hdmi_16_data_e = 'd0;
reg [15:0] hdmi_16_data = 'd0;
reg hdmi_es_hs_de = 'd0;
reg hdmi_es_vs_de = 'd0;
reg [15:0] hdmi_es_data = 'd0;
// internal wires
wire [15:0] hdmi_hl_width_s;
wire [15:0] hdmi_vf_width_s;
wire [15:0] hdmi_he_width_s;
wire [15:0] hdmi_ve_width_s;
wire hdmi_fs_ret_s;
wire hdmi_de_s;
wire [47:0] hdmi_rdata_s;
wire [23:0] hdmi_data_2d_s;
wire hdmi_tpm_mismatch_s;
wire [23:0] hdmi_tpg_data_s;
wire hdmi_csc_hsync_s;
wire hdmi_csc_vsync_s;
wire hdmi_csc_hsync_data_e_s;
wire hdmi_csc_vsync_data_e_s;
wire hdmi_csc_data_e_s;
wire [23:0] hdmi_csc_data_s;
wire hdmi_ss_hsync_s;
wire hdmi_ss_vsync_s;
wire hdmi_ss_hsync_data_e_s;
wire hdmi_ss_vsync_data_e_s;
wire hdmi_ss_data_e_s;
wire [15:0] hdmi_ss_data_s;
wire hdmi_es_hs_de_s;
wire hdmi_es_vs_de_s;
wire hdmi_es_de_s;
wire [15:0] hdmi_es_data_s;
// binary to grey conversion
function [8:0] b2g;
input [8:0] b;
reg [8:0] g;
begin
g[8] = b[8];
g[7] = b[8] ^ b[7];
g[6] = b[7] ^ b[6];
g[5] = b[6] ^ b[5];
g[4] = b[5] ^ b[4];
g[3] = b[4] ^ b[3];
g[2] = b[3] ^ b[2];
g[1] = b[2] ^ b[1];
g[0] = b[1] ^ b[0];
b2g = g;
end
endfunction
// status and enable
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_status <= 1'b0;
hdmi_enable <= 1'b0;
end else begin
hdmi_status <= 1'b1;
hdmi_enable <= hdmi_srcsel[1] | hdmi_srcsel[0];
end
end
// calculate useful limits
assign hdmi_hl_width_s = hdmi_hl_width - 1'b1;
assign hdmi_vf_width_s = hdmi_vf_width - 1'b1;
assign hdmi_he_width_s = hdmi_hl_width - (hdmi_hl_active + 1'b1);
assign hdmi_ve_width_s = hdmi_vf_width - (hdmi_vf_active + 1'b1);
// hdmi counters
always @(posedge hdmi_clk) begin
if (hdmi_hs_count >= hdmi_hl_width_s) begin
hdmi_hs_count <= 0;
end else begin
hdmi_hs_count <= hdmi_hs_count + 1'b1;
end
if (hdmi_hs_count >= hdmi_hl_width_s) begin
if (hdmi_vs_count >= hdmi_vf_width_s) begin
hdmi_vs_count <= 0;
end else begin
hdmi_vs_count <= hdmi_vs_count + 1'b1;
end
end
end
// hdmi start of frame
always @(posedge hdmi_clk) begin
if (EMBEDDED_SYNC == 1) begin
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_ve_width_s)) begin
hdmi_fs <= hdmi_enable;
end else begin
hdmi_fs <= 1'b0;
end
end else begin
if ((hdmi_hs_count == 1) && (hdmi_vs_count == hdmi_vs_width)) begin
hdmi_fs <= hdmi_enable;
end else begin
hdmi_fs <= 1'b0;
end
end
if (hdmi_fs == 1'b1) begin
hdmi_fs_toggle <= ~hdmi_fs_toggle;
end
end
// hdmi sof write address
assign hdmi_fs_ret_s = hdmi_fs_ret_toggle_m2 ^ hdmi_fs_ret_toggle_m3;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_fs_ret_toggle_m1 <= 1'd0;
hdmi_fs_ret_toggle_m2 <= 1'd0;
hdmi_fs_ret_toggle_m3 <= 1'd0;
end else begin
hdmi_fs_ret_toggle_m1 <= vdma_fs_ret_toggle;
hdmi_fs_ret_toggle_m2 <= hdmi_fs_ret_toggle_m1;
hdmi_fs_ret_toggle_m3 <= hdmi_fs_ret_toggle_m2;
end
hdmi_fs_ret <= hdmi_fs_ret_s;
if (hdmi_fs_ret_s == 1'b1) begin
hdmi_fs_waddr <= vdma_fs_waddr;
end
end
// hdmi sync signals
always @(posedge hdmi_clk) begin
if (EMBEDDED_SYNC == 1) begin
hdmi_hs <= 1'b0;
hdmi_vs <= 1'b0;
if (hdmi_hs_count <= hdmi_he_width_s) begin
hdmi_hs_de <= 1'b0;
end else begin
hdmi_hs_de <= hdmi_enable;
end
if (hdmi_vs_count <= hdmi_ve_width_s) begin
hdmi_vs_de <= 1'b0;
end else begin
hdmi_vs_de <= hdmi_enable;
end
end else begin
if (hdmi_hs_count < hdmi_hs_width) begin
hdmi_hs <= hdmi_enable;
end else begin
hdmi_hs <= 1'b0;
end
if (hdmi_vs_count < hdmi_vs_width) begin
hdmi_vs <= hdmi_enable;
end else begin
hdmi_vs <= 1'b0;
end
if ((hdmi_hs_count < hdmi_he_min) || (hdmi_hs_count >= hdmi_he_max)) begin
hdmi_hs_de <= 1'b0;
end else begin
hdmi_hs_de <= hdmi_enable;
end
if ((hdmi_vs_count < hdmi_ve_min) || (hdmi_vs_count >= hdmi_ve_max)) begin
hdmi_vs_de <= 1'b0;
end else begin
hdmi_vs_de <= hdmi_enable;
end
end
end
// hdmi read data
assign hdmi_de_s = hdmi_hs_de & hdmi_vs_de;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_raddr <= 10'd0;
end else if (hdmi_fs_ret == 1'b1) begin
hdmi_raddr <= {hdmi_fs_waddr, 1'b0};
end else if (hdmi_de_s == 1'b1) begin
hdmi_raddr <= hdmi_raddr + 1'b1;
end
hdmi_raddr_g <= b2g(hdmi_raddr[9:1]);
end
// control and data pipe line
always @(posedge hdmi_clk) begin
hdmi_hs_d <= hdmi_hs;
hdmi_vs_d <= hdmi_vs;
hdmi_hs_de_d <= hdmi_hs_de;
hdmi_vs_de_d <= hdmi_vs_de;
hdmi_de_d <= hdmi_de_s;
hdmi_data_sel_d <= hdmi_raddr[0];
hdmi_hs_2d <= hdmi_hs_d;
hdmi_vs_2d <= hdmi_vs_d;
hdmi_hs_de_2d <= hdmi_hs_de_d;
hdmi_vs_de_2d <= hdmi_vs_de_d;
hdmi_de_2d <= hdmi_de_d;
hdmi_data_sel_2d <= hdmi_data_sel_d;
hdmi_data_2d <= hdmi_rdata_s;
end
// hdmi data count (may be used to monitor or insert)
assign hdmi_data_2d_s = (hdmi_data_sel_2d == 1'b1) ? hdmi_data_2d[47:24] : hdmi_data_2d[23:0];
assign hdmi_tpm_mismatch_s = (hdmi_data_2d_s == hdmi_tpm_data) ? 1'b0 : hdmi_de_2d;
assign hdmi_tpg_data_s = hdmi_tpm_data;
always @(posedge hdmi_clk) begin
if ((hdmi_rst == 1'b1) || (hdmi_fs_ret == 1'b1)) begin
hdmi_tpm_data <= 'd0;
end else if (hdmi_de_2d == 1'b1) begin
hdmi_tpm_data <= hdmi_tpm_data + 1'b1;
end
hdmi_tpm_oos <= hdmi_tpm_mismatch_s;
end
// hdmi data select
always @(posedge hdmi_clk) begin
hdmi_hsync <= hdmi_hs_2d;
hdmi_vsync <= hdmi_vs_2d;
hdmi_hsync_data_e <= hdmi_hs_de_2d;
hdmi_vsync_data_e <= hdmi_vs_de_2d;
hdmi_data_e <= hdmi_de_2d;
case (hdmi_srcsel)
2'b11: hdmi_data <= hdmi_const_rgb;
2'b10: hdmi_data <= hdmi_tpg_data_s;
2'b01: hdmi_data <= hdmi_data_2d_s;
default: hdmi_data <= 24'd0;
endcase
end
// hdmi csc 16, 24 and 36 outputs
assign hdmi_36_hsync = hdmi_24_hsync;
assign hdmi_36_vsync = hdmi_24_vsync;
assign hdmi_36_data_e = hdmi_24_data_e;
assign hdmi_36_data[35:24] = {hdmi_24_data[23:16], hdmi_24_data[23:20]};
assign hdmi_36_data[23:12] = {hdmi_24_data[15: 8], hdmi_24_data[15:12]};
assign hdmi_36_data[11: 0] = {hdmi_24_data[ 7: 0], hdmi_24_data[ 7: 4]};
always @(posedge hdmi_clk) begin
if (hdmi_csc_bypass == 1'b1) begin
hdmi_24_hsync <= hdmi_hsync;
hdmi_24_vsync <= hdmi_vsync;
hdmi_24_hsync_data_e <= hdmi_hsync_data_e;
hdmi_24_vsync_data_e <= hdmi_vsync_data_e;
hdmi_24_data_e <= hdmi_data_e;
hdmi_24_data <= hdmi_data;
end else begin
hdmi_24_hsync <= hdmi_csc_hsync_s;
hdmi_24_vsync <= hdmi_csc_vsync_s;
hdmi_24_hsync_data_e <= hdmi_csc_hsync_data_e_s;
hdmi_24_vsync_data_e <= hdmi_csc_vsync_data_e_s;
hdmi_24_data_e <= hdmi_csc_data_e_s;
hdmi_24_data <= hdmi_csc_data_s;
end
if (hdmi_ss_bypass == 1'b1) begin
hdmi_16_hsync <= hdmi_24_hsync;
hdmi_16_vsync <= hdmi_24_vsync;
hdmi_16_hsync_data_e <= hdmi_24_hsync_data_e;
hdmi_16_vsync_data_e <= hdmi_24_vsync_data_e;
hdmi_16_data_e <= hdmi_24_data_e;
hdmi_16_data <= hdmi_24_data[15:0]; // Ignore the upper 8 bit
end else begin
hdmi_16_hsync <= hdmi_ss_hsync_s;
hdmi_16_vsync <= hdmi_ss_vsync_s;
hdmi_16_hsync_data_e <= hdmi_ss_hsync_data_e_s;
hdmi_16_vsync_data_e <= hdmi_ss_vsync_data_e_s;
hdmi_16_data_e <= hdmi_ss_data_e_s;
hdmi_16_data <= hdmi_ss_data_s;
end
end
// hdmi embedded sync clipping
assign hdmi_es_hs_de_s = hdmi_16_hsync_data_e;
assign hdmi_es_vs_de_s = hdmi_16_vsync_data_e;
assign hdmi_es_de_s = hdmi_16_data_e;
assign hdmi_es_data_s = hdmi_16_data;
always @(posedge hdmi_clk) begin
hdmi_es_hs_de <= hdmi_es_hs_de_s;
hdmi_es_vs_de <= hdmi_es_vs_de_s;
if (hdmi_es_de_s == 1'b0) begin
hdmi_es_data[15:8] <= 8'h80;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[15:8] > 8'heb)) begin
hdmi_es_data[15:8] <= 8'heb;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[15:8] < 8'h10)) begin
hdmi_es_data[15:8] <= 8'h10;
end else if (hdmi_es_data_s[15:8] > 8'hfe) begin
hdmi_es_data[15:8] <= 8'hfe;
end else if (hdmi_es_data_s[15:8] < 8'h01) begin
hdmi_es_data[15:8] <= 8'h01;
end else begin
hdmi_es_data[15:8] <= hdmi_es_data_s[15:8];
end
if (hdmi_es_de_s == 1'b0) begin
hdmi_es_data[7:0] <= 8'h80;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[7:0] > 8'heb)) begin
hdmi_es_data[7:0] <= 8'heb;
end else if ((hdmi_full_range == 1'b0) &&
(hdmi_es_data_s[7:0] < 8'h10)) begin
hdmi_es_data[7:0] <= 8'h10;
end else if (hdmi_es_data_s[7:0] > 8'hfe) begin
hdmi_es_data[7:0] <= 8'hfe;
end else if (hdmi_es_data_s[7:0] < 8'h01) begin
hdmi_es_data[7:0] <= 8'h01;
end else begin
hdmi_es_data[7:0] <= hdmi_es_data_s[7:0];
end
end
// data memory
ad_mem #(.DATA_WIDTH(48), .ADDR_WIDTH(9)) i_mem (
.clka (vdma_clk),
.wea (vdma_wr),
.addra (vdma_waddr),
.dina (vdma_wdata),
.clkb (hdmi_clk),
.addrb (hdmi_raddr[9:1]),
.doutb (hdmi_rdata_s));
// color space coversion, RGB to CrYCb
ad_csc_RGB2CrYCb #(.DELAY_DATA_WIDTH(5)) i_csc_RGB2CrYCb (
.clk (hdmi_clk),
.RGB_sync ({hdmi_hsync,
hdmi_vsync,
hdmi_hsync_data_e,
hdmi_vsync_data_e,
hdmi_data_e}),
.RGB_data (hdmi_data),
.CrYCb_sync ({hdmi_csc_hsync_s,
hdmi_csc_vsync_s,
hdmi_csc_hsync_data_e_s,
hdmi_csc_vsync_data_e_s,
hdmi_csc_data_e_s}),
.CrYCb_data (hdmi_csc_data_s));
// sub sampling, 444 to 422
ad_ss_444to422 #(.DELAY_DATA_WIDTH(5), .Cr_Cb_N(Cr_Cb_N)) i_ss_444to422 (
.clk (hdmi_clk),
.s444_de (hdmi_24_data_e),
.s444_sync ({hdmi_24_hsync,
hdmi_24_vsync,
hdmi_24_hsync_data_e,
hdmi_24_vsync_data_e,
hdmi_24_data_e}),
.s444_data (hdmi_24_data),
.s422_sync ({hdmi_ss_hsync_s,
hdmi_ss_vsync_s,
hdmi_ss_hsync_data_e_s,
hdmi_ss_vsync_data_e_s,
hdmi_ss_data_e_s}),
.s422_data (hdmi_ss_data_s));
// embedded sync
axi_hdmi_tx_es #(.DATA_WIDTH(16)) i_es (
.hdmi_clk (hdmi_clk),
.hdmi_hs_de (hdmi_es_hs_de),
.hdmi_vs_de (hdmi_es_vs_de),
.hdmi_data_de (hdmi_es_data),
.hdmi_data (hdmi_16_es_data));
endmodule
// ***************************************************************************
// ***************************************************************************
|
`default_nettype none
module main (input sysclk,
input clk,
input rst,
output c0,
output c1,
output c2,
output c3,
output c4,
output c5,
output c6,
output c7);
//-- Configure the pull-up resistors for clk and rst inputs
wire clk_in, clk2;
wire rst_in, rst2;
wire sw;
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin (
.PACKAGE_PIN(clk),
.D_IN_0(clk2)
);
SB_IO #(
.PIN_TYPE(6'b 1010_01),
.PULLUP(1'b 1)
) io_pin2 (
.PACKAGE_PIN(rst),
.D_IN_0(rst2)
);
//-- rst_in and clk_in are the signals from the switches, with
//-- standar logic (1 pressed, 0 not presssed)
assign rst_in = ~rst2;
assign sw = ~clk2;
debounce d1 (
.clk(sysclk),
.sw_in(sw),
.sw_out(clk_in)
);
//-- Counter with asynchronous reset
reg [7:0] counter;
always @(posedge clk_in or posedge rst_in) begin
if (rst_in==1'b1)
counter <= 7'b0;
else
counter <= counter + 1;
end
//-- Output the counter's bits
assign c0 = counter[0];
assign c1 = counter[1];
assign c2 = counter[2];
assign c3 = counter[3];
assign c4 = counter[4];
assign c5 = counter[5];
assign c6 = counter[6];
assign c7 = counter[7];
endmodule
module debounce(input wire clk,
input wire sw_in,
output wire sw_out);
//------------------------------
//-- CONTROLLER
//------------------------------
//-- fsm states
localparam STABLE_0 = 0; //-- Idle state. Button not pressed
localparam WAIT_1 = 1; //-- Waiting for the stabilization of 1. Butt pressed
localparam STABLE_1 = 2; //-- Button is pressed and stable
localparam WAIT_0 = 3; //-- Button released. Waiting for stabilization of 0
//-- Registers for storing the states
reg [1:0] state = STABLE_0;
reg [1:0] next_state;
//-- Control signals
reg out = 0;
reg timer_ena = 0;
assign sw_out = out;
//-- Transition between states
always @(posedge clk)
state <= next_state;
//-- Control signal generation and next states
always @(*) begin
//-- Default values
next_state = state; //-- Stay in the same state by default
timer_ena = 0;
out = 0;
case (state)
//-- Button not pressed
//-- Remain in this state until the botton is pressed
STABLE_0: begin
timer_ena = 0;
out = 0;
if (sw_in)
next_state = WAIT_1;
end
//-- Wait until x ms has elapsed
WAIT_1: begin
timer_ena = 1;
out = 1;
if (timer_trig)
next_state = STABLE_1;
end
STABLE_1: begin
timer_ena = 0;
out = 1;
if (sw_in == 0)
next_state = WAIT_0;
end
WAIT_0: begin
timer_ena = 1;
out = 0;
if (timer_trig)
next_state = STABLE_0;
end
default: begin
end
endcase
end
assign sw_out = out;
//-- Timer
wire timer_trig;
prescaler #(
.N(16)
) pres0 (
.clk_in(clk),
.ena(timer_ena),
.clk_out(timer_trig)
);
endmodule // debounce
//-- Prescaler N bits
module prescaler(input wire clk_in,
input wire ena,
output wire clk_out);
//-- Bits of the prescaler
parameter N = 22;
//-- N bits counter
reg [N-1:0] count = 0;
//-- The most significant bit is used as output
assign clk_out = count[N-1];
always @(posedge(clk_in)) begin
if (!ena)
count <= 0;
else
count <= count + 1;
end
endmodule /// prescaler
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_ocmc.v
*
* Date : 2012-11
*
* Description : Controller for OCM model
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_ocmc(
rstn,
sw_clk,
/* Goes to port 0 of OCM */
ocm_wr_ack_port0,
ocm_wr_dv_port0,
ocm_rd_req_port0,
ocm_rd_dv_port0,
ocm_wr_addr_port0,
ocm_wr_data_port0,
ocm_wr_bytes_port0,
ocm_rd_addr_port0,
ocm_rd_data_port0,
ocm_rd_bytes_port0,
ocm_wr_qos_port0,
ocm_rd_qos_port0,
/* Goes to port 1 of OCM */
ocm_wr_ack_port1,
ocm_wr_dv_port1,
ocm_rd_req_port1,
ocm_rd_dv_port1,
ocm_wr_addr_port1,
ocm_wr_data_port1,
ocm_wr_bytes_port1,
ocm_rd_addr_port1,
ocm_rd_data_port1,
ocm_rd_bytes_port1,
ocm_wr_qos_port1,
ocm_rd_qos_port1
);
`include "processing_system7_bfm_v2_0_local_params.v"
input rstn;
input sw_clk;
output ocm_wr_ack_port0;
input ocm_wr_dv_port0;
input ocm_rd_req_port0;
output ocm_rd_dv_port0;
input[addr_width-1:0] ocm_wr_addr_port0;
input[max_burst_bits-1:0] ocm_wr_data_port0;
input[max_burst_bytes_width:0] ocm_wr_bytes_port0;
input[addr_width-1:0] ocm_rd_addr_port0;
output[max_burst_bits-1:0] ocm_rd_data_port0;
input[max_burst_bytes_width:0] ocm_rd_bytes_port0;
input [axi_qos_width-1:0] ocm_wr_qos_port0;
input [axi_qos_width-1:0] ocm_rd_qos_port0;
output ocm_wr_ack_port1;
input ocm_wr_dv_port1;
input ocm_rd_req_port1;
output ocm_rd_dv_port1;
input[addr_width-1:0] ocm_wr_addr_port1;
input[max_burst_bits-1:0] ocm_wr_data_port1;
input[max_burst_bytes_width:0] ocm_wr_bytes_port1;
input[addr_width-1:0] ocm_rd_addr_port1;
output[max_burst_bits-1:0] ocm_rd_data_port1;
input[max_burst_bytes_width:0] ocm_rd_bytes_port1;
input[axi_qos_width-1:0] ocm_wr_qos_port1;
input[axi_qos_width-1:0] ocm_rd_qos_port1;
wire [axi_qos_width-1:0] wr_qos;
wire wr_req;
wire [max_burst_bits-1:0] wr_data;
wire [addr_width-1:0] wr_addr;
wire [max_burst_bytes_width:0] wr_bytes;
reg wr_ack;
wire [axi_qos_width-1:0] rd_qos;
reg [max_burst_bits-1:0] rd_data;
wire [addr_width-1:0] rd_addr;
wire [max_burst_bytes_width:0] rd_bytes;
reg rd_dv;
wire rd_req;
processing_system7_bfm_v2_0_arb_wr ocm_write_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_wr_qos_port0),
.qos2(ocm_wr_qos_port1),
.prt_dv1(ocm_wr_dv_port0),
.prt_dv2(ocm_wr_dv_port1),
.prt_data1(ocm_wr_data_port0),
.prt_data2(ocm_wr_data_port1),
.prt_addr1(ocm_wr_addr_port0),
.prt_addr2(ocm_wr_addr_port1),
.prt_bytes1(ocm_wr_bytes_port0),
.prt_bytes2(ocm_wr_bytes_port1),
.prt_ack1(ocm_wr_ack_port0),
.prt_ack2(ocm_wr_ack_port1),
.prt_qos(wr_qos),
.prt_req(wr_req),
.prt_data(wr_data),
.prt_addr(wr_addr),
.prt_bytes(wr_bytes),
.prt_ack(wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ocm_read_ports (
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(ocm_rd_qos_port0),
.qos2(ocm_rd_qos_port1),
.prt_req1(ocm_rd_req_port0),
.prt_req2(ocm_rd_req_port1),
.prt_data1(ocm_rd_data_port0),
.prt_data2(ocm_rd_data_port1),
.prt_addr1(ocm_rd_addr_port0),
.prt_addr2(ocm_rd_addr_port1),
.prt_bytes1(ocm_rd_bytes_port0),
.prt_bytes2(ocm_rd_bytes_port1),
.prt_dv1(ocm_rd_dv_port0),
.prt_dv2(ocm_rd_dv_port1),
.prt_qos(rd_qos),
.prt_req(rd_req),
.prt_data(rd_data),
.prt_addr(rd_addr),
.prt_bytes(rd_bytes),
.prt_dv(rd_dv)
);
processing_system7_bfm_v2_0_ocm_mem ocm();
reg [1:0] state;
always@(posedge sw_clk or negedge rstn)
begin
if(!rstn) begin
wr_ack <= 0;
rd_dv <= 0;
state <= 2'd0;
end else begin
case(state)
0:begin
state <= 0;
wr_ack <= 0;
rd_dv <= 0;
if(wr_req) begin
ocm.write_mem(wr_data , wr_addr, wr_bytes);
wr_ack <= 1;
state <= 1;
end
if(rd_req) begin
ocm.read_mem(rd_data,rd_addr, rd_bytes);
rd_dv <= 1;
state <= 1;
end
end
1:begin
wr_ack <= 0;
rd_dv <= 0;
state <= 0;
end
endcase
end /// if
end// always
endmodule
|
/*
File: debouncer.v
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013 Adapteva, Inc.
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
module debouncer (/*AUTOARG*/
// Outputs
clean_out,
// Inputs
clk, noisy_in
);
parameter N = 20; //debouncer counter width
input clk; //system clock
input noisy_in; //bouncy input (convention says it goes low when button is pressed)
output clean_out; //clean output (positive polarity)
wire expired;
wire sync_in;
reg [N-1:0] counter;
wire filtering;
synchronizer #(1) synchronizer(.out (sync_in),
.in (noisy_in),
.clk (clk),
.reset (1'b0));
//Counter that resets when sync_in is low
always @ (posedge clk)
if(sync_in)
counter[N-1:0]={(N){1'b1}};
else if(filtering)
counter[N-1:0]=counter[N-1:0]-1'b1;
assign filtering =|counter[N-1:0];
assign clean_out = filtering | sync_in;
endmodule // debouncer
|
// ghrd_10as066n2_ocm_0.v
// Generated using ACDS version 17.1 240
`timescale 1 ps / 1 ps
module ghrd_10as066n2_ocm_0 (
input wire clk, // clk1.clk
input wire reset, // reset1.reset
input wire reset_req, // .reset_req
input wire [17:0] address, // s1.address
input wire clken, // .clken
input wire chipselect, // .chipselect
input wire write, // .write
output wire [7:0] readdata, // .readdata
input wire [7:0] writedata // .writedata
);
ghrd_10as066n2_ocm_0_altera_avalon_onchip_memory2_171_ehvj5ii ocm_0 (
.clk (clk), // input, width = 1, clk1.clk
.address (address), // input, width = 18, s1.address
.clken (clken), // input, width = 1, .clken
.chipselect (chipselect), // input, width = 1, .chipselect
.write (write), // input, width = 1, .write
.readdata (readdata), // output, width = 8, .readdata
.writedata (writedata), // input, width = 8, .writedata
.reset (reset), // input, width = 1, reset1.reset
.reset_req (reset_req), // input, width = 1, .reset_req
.freeze (1'b0) // (terminated),
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
`define SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__dfstp (
Q ,
CLK ,
D ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DFSTP_BLACKBOX_V
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_ecc_decoder #
( parameter
CFG_DATA_WIDTH = 40,
CFG_ECC_CODE_WIDTH = 8,
CFG_ECC_DEC_REG = 1,
CFG_ECC_DECODER_REG = 0,
CFG_ECC_RDATA_REG = 0,
CFG_MMR_DRAM_DATA_WIDTH = 7,
CFG_MMR_LOCAL_DATA_WIDTH = 7,
CFG_PORT_WIDTH_ENABLE_ECC = 1
)
(
ctl_clk,
ctl_reset_n,
cfg_local_data_width,
cfg_dram_data_width,
cfg_enable_ecc,
input_data,
input_data_valid,
output_data,
output_data_valid,
output_ecc_code,
err_corrected,
err_detected,
err_fatal,
err_sbe
);
localparam CFG_ECC_DATA_WIDTH = (CFG_DATA_WIDTH > 8) ? (CFG_DATA_WIDTH - CFG_ECC_CODE_WIDTH) : (CFG_DATA_WIDTH);
input ctl_clk;
input ctl_reset_n;
input [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_local_data_width;
input [CFG_MMR_LOCAL_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_DATA_WIDTH - 1 : 0] input_data;
input input_data_valid;
output [CFG_DATA_WIDTH - 1 : 0] output_data;
output output_data_valid;
output [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
output err_corrected;
output err_detected;
output err_fatal;
output err_sbe;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_data;
reg [CFG_DATA_WIDTH - 1 : 0] int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] or_int_decoder_input_ecc_code;
reg [CFG_DATA_WIDTH - 1 : 0] output_data;
reg output_data_valid;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] output_ecc_code;
reg err_corrected;
reg err_detected;
reg err_fatal;
reg err_sbe;
wire int_err_corrected;
wire int_err_detected;
wire int_err_fatal;
wire int_err_sbe;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] int_output_ecc_code;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code_r;
reg [CFG_ECC_CODE_WIDTH - 1 : 0] decoder_output_ecc_code_r_r;
wire [CFG_DATA_WIDTH - 1 : 0] decoder_input;
wire [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output;
reg decoder_output_valid;
reg [CFG_ECC_DATA_WIDTH - 1 : 0] decoder_output_r;
reg decoder_output_valid_r;
reg decoder_output_valid_r_r;
reg int_err_corrected_r;
reg int_err_detected_r;
reg int_err_fatal_r;
reg int_err_sbe_r;
wire zero = 1'b0;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Common Logic
//
//--------------------------------------------------------------------------------------------------------
// Input data splitting/masking logic:
// change
// <Empty data> - <ECC code> - <Data>
// into
// <ECC code> - <Empty data> - <Data>
generate
genvar i_data;
for (i_data = 0;i_data < CFG_DATA_WIDTH;i_data = i_data + 1)
begin : decoder_input_per_data_width
always @ (*)
begin
int_decoder_input_data [i_data] = input_data [i_data];
end
end
endgenerate
generate
if (CFG_ECC_RDATA_REG)
begin
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_decoder_input <= 0;
end
else
begin
int_decoder_input <= int_decoder_input_data;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
decoder_output_valid <= 0;
decoder_output_ecc_code <= 0;
end
else
begin
decoder_output_valid <= input_data_valid;
decoder_output_ecc_code <= int_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
int_decoder_input = int_decoder_input_data;
end
always @ (*)
begin
decoder_output_valid = input_data_valid;
decoder_output_ecc_code = int_output_ecc_code;
end
end
endgenerate
// Decoder input assignment
assign decoder_input = int_decoder_input;
// Decoder output, registered
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
decoder_output_r <= {CFG_ECC_DATA_WIDTH{1'b0}};
decoder_output_valid_r <= 1'b0;
decoder_output_valid_r_r <= 1'b0;
int_err_corrected_r <= 1'b0;
int_err_detected_r <= 1'b0;
int_err_fatal_r <= 1'b0;
int_err_sbe_r <= 1'b0;
decoder_output_ecc_code_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
decoder_output_ecc_code_r_r <= {CFG_ECC_CODE_WIDTH{1'b0}};
end
else
begin
decoder_output_r <= decoder_output;
decoder_output_valid_r <= decoder_output_valid;
decoder_output_valid_r_r <= decoder_output_valid_r;
int_err_corrected_r <= int_err_corrected;
int_err_detected_r <= int_err_detected;
int_err_fatal_r <= int_err_fatal;
int_err_sbe_r <= int_err_sbe;
decoder_output_ecc_code_r <= decoder_output_ecc_code;
decoder_output_ecc_code_r_r <= decoder_output_ecc_code_r;
end
end
// Decoder output ecc code
generate
if (CFG_DATA_WIDTH <= 8)
begin
// No support for ECC case
always @ (*)
begin
int_output_ecc_code = {CFG_ECC_CODE_WIDTH{zero}};
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
int_output_ecc_code = int_decoder_input_data [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH];
else
int_output_ecc_code = 0;
end
end
endgenerate
// Decoder wrapper output assignment
generate
begin : gen_decoder_output_reg_select
if (CFG_ECC_DEC_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output_r}; // Assign '0' to ECC code portions
output_data_valid = (CFG_ECC_DECODER_REG == 1) ? decoder_output_valid_r_r : decoder_output_valid_r;
err_corrected = int_err_corrected_r;
err_detected = int_err_detected_r;
err_fatal = int_err_fatal_r;
err_sbe = int_err_sbe_r;
output_ecc_code = (CFG_ECC_DECODER_REG == 1) ? decoder_output_ecc_code_r_r : decoder_output_ecc_code_r;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = decoder_output_ecc_code;
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc)
begin
output_data = {{CFG_ECC_CODE_WIDTH{1'b0}}, decoder_output}; // Assign '0' to ECC code portions
output_data_valid = (CFG_ECC_DECODER_REG == 1) ? decoder_output_valid_r : decoder_output_valid;
err_corrected = int_err_corrected;
err_detected = int_err_detected;
err_fatal = int_err_fatal;
err_sbe = int_err_sbe;
output_ecc_code = decoder_output_ecc_code;
end
else
begin
output_data = input_data;
output_data_valid = input_data_valid;
err_corrected = 1'b0;
err_detected = 1'b0;
err_fatal = 1'b0;
err_sbe = 1'b0;
output_ecc_code = decoder_output_ecc_code;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Common Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Instantiation
//
//--------------------------------------------------------------------------------------------------------
generate
begin
if (CFG_ECC_DATA_WIDTH == 8 && CFG_DATA_WIDTH > 8) // Make sure this is an ECC case else it will cause compilation error
begin
wire [39 : 0] internal_decoder_input;
wire [31 : 0] internal_decoder_output;
// Assign decoder output
assign internal_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 24'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = internal_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (internal_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (internal_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 16)
begin
wire [39 : 0] internal_decoder_input;
wire [31 : 0] internal_decoder_output;
// Assign decoder output
assign internal_decoder_input = {decoder_input [CFG_DATA_WIDTH - 1 : CFG_ECC_DATA_WIDTH], 16'd0, decoder_input [CFG_ECC_DATA_WIDTH - 1 : 0]};
// Assign decoder output
assign decoder_output = internal_decoder_output [CFG_ECC_DATA_WIDTH - 1 : 0];
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (internal_decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (internal_decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 32)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_32
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (decoder_input [38 : 0]),
.err_corrected (int_err_corrected ),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else if (CFG_ECC_DATA_WIDTH == 64)
begin
// 32/39 bit decoder instantiation
alt_mem_ddrx_ecc_decoder_64
# (
.CFG_ECC_DECODER_REG (CFG_ECC_DECODER_REG)
)
decoder_inst
(
.clk (ctl_clk ),
.reset_n (ctl_reset_n ),
.data (decoder_input ),
.err_corrected (int_err_corrected),
.err_detected (int_err_detected ),
.err_fatal (int_err_fatal ),
.err_sbe (int_err_sbe ),
.q (decoder_output )
);
end
else
begin
assign int_err_corrected = 1'b0;
assign int_err_detected = 1'b0;
assign int_err_fatal = 1'b0;
assign int_err_sbe = 1'b0;
assign decoder_output = {CFG_ECC_DATA_WIDTH{1'b0}};
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Instantiation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (c) Copyright 1995-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:processing_system7_bfm:2.0
// IP Revision: 1
`timescale 1ns/1ps
module tutorial_processing_system7_0_0 (
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
FCLK_CLK0,
FCLK_CLK1,
FCLK_CLK2,
FCLK_RESET0_N,
FCLK_RESET1_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB
);
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1 : 0] USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11 : 0] M_AXI_GP0_ARID;
output [11 : 0] M_AXI_GP0_AWID;
output [11 : 0] M_AXI_GP0_WID;
output [1 : 0] M_AXI_GP0_ARBURST;
output [1 : 0] M_AXI_GP0_ARLOCK;
output [2 : 0] M_AXI_GP0_ARSIZE;
output [1 : 0] M_AXI_GP0_AWBURST;
output [1 : 0] M_AXI_GP0_AWLOCK;
output [2 : 0] M_AXI_GP0_AWSIZE;
output [2 : 0] M_AXI_GP0_ARPROT;
output [2 : 0] M_AXI_GP0_AWPROT;
output [31 : 0] M_AXI_GP0_ARADDR;
output [31 : 0] M_AXI_GP0_AWADDR;
output [31 : 0] M_AXI_GP0_WDATA;
output [3 : 0] M_AXI_GP0_ARCACHE;
output [3 : 0] M_AXI_GP0_ARLEN;
output [3 : 0] M_AXI_GP0_ARQOS;
output [3 : 0] M_AXI_GP0_AWCACHE;
output [3 : 0] M_AXI_GP0_AWLEN;
output [3 : 0] M_AXI_GP0_AWQOS;
output [3 : 0] M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11 : 0] M_AXI_GP0_BID;
input [11 : 0] M_AXI_GP0_RID;
input [1 : 0] M_AXI_GP0_BRESP;
input [1 : 0] M_AXI_GP0_RRESP;
input [31 : 0] M_AXI_GP0_RDATA;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1 : 0] S_AXI_HP0_BRESP;
output [1 : 0] S_AXI_HP0_RRESP;
output [5 : 0] S_AXI_HP0_BID;
output [5 : 0] S_AXI_HP0_RID;
output [63 : 0] S_AXI_HP0_RDATA;
output [7 : 0] S_AXI_HP0_RCOUNT;
output [7 : 0] S_AXI_HP0_WCOUNT;
output [2 : 0] S_AXI_HP0_RACOUNT;
output [5 : 0] S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1 : 0] S_AXI_HP0_ARBURST;
input [1 : 0] S_AXI_HP0_ARLOCK;
input [2 : 0] S_AXI_HP0_ARSIZE;
input [1 : 0] S_AXI_HP0_AWBURST;
input [1 : 0] S_AXI_HP0_AWLOCK;
input [2 : 0] S_AXI_HP0_AWSIZE;
input [2 : 0] S_AXI_HP0_ARPROT;
input [2 : 0] S_AXI_HP0_AWPROT;
input [31 : 0] S_AXI_HP0_ARADDR;
input [31 : 0] S_AXI_HP0_AWADDR;
input [3 : 0] S_AXI_HP0_ARCACHE;
input [3 : 0] S_AXI_HP0_ARLEN;
input [3 : 0] S_AXI_HP0_ARQOS;
input [3 : 0] S_AXI_HP0_AWCACHE;
input [3 : 0] S_AXI_HP0_AWLEN;
input [3 : 0] S_AXI_HP0_AWQOS;
input [5 : 0] S_AXI_HP0_ARID;
input [5 : 0] S_AXI_HP0_AWID;
input [5 : 0] S_AXI_HP0_WID;
input [63 : 0] S_AXI_HP0_WDATA;
input [7 : 0] S_AXI_HP0_WSTRB;
output FCLK_CLK0;
output FCLK_CLK1;
output FCLK_CLK2;
output FCLK_RESET0_N;
output FCLK_RESET1_N;
input [53 : 0] MIO;
input DDR_CAS_n;
input DDR_CKE;
input DDR_Clk_n;
input DDR_Clk;
input DDR_CS_n;
input DDR_DRSTB;
input DDR_ODT;
input DDR_RAS_n;
input DDR_WEB;
input [2 : 0] DDR_BankAddr;
input [14 : 0] DDR_Addr;
input DDR_VRN;
input DDR_VRP;
input [3 : 0] DDR_DM;
input [31 : 0] DDR_DQ;
input [3 : 0] DDR_DQS_n;
input [3 : 0] DDR_DQS;
input PS_SRSTB;
input PS_CLK;
input PS_PORB;
processing_system7_bfm_v2_0_processing_system7_bfm #(
.C_USE_M_AXI_GP0(1),
.C_USE_M_AXI_GP1(0),
.C_USE_S_AXI_ACP(0),
.C_USE_S_AXI_GP0(0),
.C_USE_S_AXI_GP1(0),
.C_USE_S_AXI_HP0(1),
.C_USE_S_AXI_HP1(0),
.C_USE_S_AXI_HP2(0),
.C_USE_S_AXI_HP3(0),
.C_S_AXI_HP0_DATA_WIDTH(64),
.C_S_AXI_HP1_DATA_WIDTH(64),
.C_S_AXI_HP2_DATA_WIDTH(64),
.C_S_AXI_HP3_DATA_WIDTH(64),
.C_HIGH_OCM_EN(0),
.C_FCLK_CLK0_FREQ(76),
.C_FCLK_CLK1_FREQ(142),
.C_FCLK_CLK2_FREQ(100),
.C_FCLK_CLK3_FREQ(50),
.C_M_AXI_GP0_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP1_ENABLE_STATIC_REMAP(0),
.C_M_AXI_GP0_THREAD_ID_WIDTH (12),
.C_M_AXI_GP1_THREAD_ID_WIDTH (12)
) inst (
.M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID),
.M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID),
.M_AXI_GP0_BREADY(M_AXI_GP0_BREADY),
.M_AXI_GP0_RREADY(M_AXI_GP0_RREADY),
.M_AXI_GP0_WLAST(M_AXI_GP0_WLAST),
.M_AXI_GP0_WVALID(M_AXI_GP0_WVALID),
.M_AXI_GP0_ARID(M_AXI_GP0_ARID),
.M_AXI_GP0_AWID(M_AXI_GP0_AWID),
.M_AXI_GP0_WID(M_AXI_GP0_WID),
.M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST),
.M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK),
.M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE),
.M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST),
.M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK),
.M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE),
.M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT),
.M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT),
.M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR),
.M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR),
.M_AXI_GP0_WDATA(M_AXI_GP0_WDATA),
.M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE),
.M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN),
.M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS),
.M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE),
.M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN),
.M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS),
.M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB),
.M_AXI_GP0_ACLK(M_AXI_GP0_ACLK),
.M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY),
.M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY),
.M_AXI_GP0_BVALID(M_AXI_GP0_BVALID),
.M_AXI_GP0_RLAST(M_AXI_GP0_RLAST),
.M_AXI_GP0_RVALID(M_AXI_GP0_RVALID),
.M_AXI_GP0_WREADY(M_AXI_GP0_WREADY),
.M_AXI_GP0_BID(M_AXI_GP0_BID),
.M_AXI_GP0_RID(M_AXI_GP0_RID),
.M_AXI_GP0_BRESP(M_AXI_GP0_BRESP),
.M_AXI_GP0_RRESP(M_AXI_GP0_RRESP),
.M_AXI_GP0_RDATA(M_AXI_GP0_RDATA),
.M_AXI_GP1_ARVALID(),
.M_AXI_GP1_AWVALID(),
.M_AXI_GP1_BREADY(),
.M_AXI_GP1_RREADY(),
.M_AXI_GP1_WLAST(),
.M_AXI_GP1_WVALID(),
.M_AXI_GP1_ARID(),
.M_AXI_GP1_AWID(),
.M_AXI_GP1_WID(),
.M_AXI_GP1_ARBURST(),
.M_AXI_GP1_ARLOCK(),
.M_AXI_GP1_ARSIZE(),
.M_AXI_GP1_AWBURST(),
.M_AXI_GP1_AWLOCK(),
.M_AXI_GP1_AWSIZE(),
.M_AXI_GP1_ARPROT(),
.M_AXI_GP1_AWPROT(),
.M_AXI_GP1_ARADDR(),
.M_AXI_GP1_AWADDR(),
.M_AXI_GP1_WDATA(),
.M_AXI_GP1_ARCACHE(),
.M_AXI_GP1_ARLEN(),
.M_AXI_GP1_ARQOS(),
.M_AXI_GP1_AWCACHE(),
.M_AXI_GP1_AWLEN(),
.M_AXI_GP1_AWQOS(),
.M_AXI_GP1_WSTRB(),
.M_AXI_GP1_ACLK(1'B0),
.M_AXI_GP1_ARREADY(1'B0),
.M_AXI_GP1_AWREADY(1'B0),
.M_AXI_GP1_BVALID(1'B0),
.M_AXI_GP1_RLAST(1'B0),
.M_AXI_GP1_RVALID(1'B0),
.M_AXI_GP1_WREADY(1'B0),
.M_AXI_GP1_BID(12'B0),
.M_AXI_GP1_RID(12'B0),
.M_AXI_GP1_BRESP(2'B0),
.M_AXI_GP1_RRESP(2'B0),
.M_AXI_GP1_RDATA(32'B0),
.S_AXI_GP0_ARREADY(),
.S_AXI_GP0_AWREADY(),
.S_AXI_GP0_BVALID(),
.S_AXI_GP0_RLAST(),
.S_AXI_GP0_RVALID(),
.S_AXI_GP0_WREADY(),
.S_AXI_GP0_BRESP(),
.S_AXI_GP0_RRESP(),
.S_AXI_GP0_RDATA(),
.S_AXI_GP0_BID(),
.S_AXI_GP0_RID(),
.S_AXI_GP0_ACLK(1'B0),
.S_AXI_GP0_ARVALID(1'B0),
.S_AXI_GP0_AWVALID(1'B0),
.S_AXI_GP0_BREADY(1'B0),
.S_AXI_GP0_RREADY(1'B0),
.S_AXI_GP0_WLAST(1'B0),
.S_AXI_GP0_WVALID(1'B0),
.S_AXI_GP0_ARBURST(2'B0),
.S_AXI_GP0_ARLOCK(2'B0),
.S_AXI_GP0_ARSIZE(3'B0),
.S_AXI_GP0_AWBURST(2'B0),
.S_AXI_GP0_AWLOCK(2'B0),
.S_AXI_GP0_AWSIZE(3'B0),
.S_AXI_GP0_ARPROT(3'B0),
.S_AXI_GP0_AWPROT(3'B0),
.S_AXI_GP0_ARADDR(32'B0),
.S_AXI_GP0_AWADDR(32'B0),
.S_AXI_GP0_WDATA(32'B0),
.S_AXI_GP0_ARCACHE(4'B0),
.S_AXI_GP0_ARLEN(4'B0),
.S_AXI_GP0_ARQOS(4'B0),
.S_AXI_GP0_AWCACHE(4'B0),
.S_AXI_GP0_AWLEN(4'B0),
.S_AXI_GP0_AWQOS(4'B0),
.S_AXI_GP0_WSTRB(4'B0),
.S_AXI_GP0_ARID(6'B0),
.S_AXI_GP0_AWID(6'B0),
.S_AXI_GP0_WID(6'B0),
.S_AXI_GP1_ARREADY(),
.S_AXI_GP1_AWREADY(),
.S_AXI_GP1_BVALID(),
.S_AXI_GP1_RLAST(),
.S_AXI_GP1_RVALID(),
.S_AXI_GP1_WREADY(),
.S_AXI_GP1_BRESP(),
.S_AXI_GP1_RRESP(),
.S_AXI_GP1_RDATA(),
.S_AXI_GP1_BID(),
.S_AXI_GP1_RID(),
.S_AXI_GP1_ACLK(1'B0),
.S_AXI_GP1_ARVALID(1'B0),
.S_AXI_GP1_AWVALID(1'B0),
.S_AXI_GP1_BREADY(1'B0),
.S_AXI_GP1_RREADY(1'B0),
.S_AXI_GP1_WLAST(1'B0),
.S_AXI_GP1_WVALID(1'B0),
.S_AXI_GP1_ARBURST(2'B0),
.S_AXI_GP1_ARLOCK(2'B0),
.S_AXI_GP1_ARSIZE(3'B0),
.S_AXI_GP1_AWBURST(2'B0),
.S_AXI_GP1_AWLOCK(2'B0),
.S_AXI_GP1_AWSIZE(3'B0),
.S_AXI_GP1_ARPROT(3'B0),
.S_AXI_GP1_AWPROT(3'B0),
.S_AXI_GP1_ARADDR(32'B0),
.S_AXI_GP1_AWADDR(32'B0),
.S_AXI_GP1_WDATA(32'B0),
.S_AXI_GP1_ARCACHE(4'B0),
.S_AXI_GP1_ARLEN(4'B0),
.S_AXI_GP1_ARQOS(4'B0),
.S_AXI_GP1_AWCACHE(4'B0),
.S_AXI_GP1_AWLEN(4'B0),
.S_AXI_GP1_AWQOS(4'B0),
.S_AXI_GP1_WSTRB(4'B0),
.S_AXI_GP1_ARID(6'B0),
.S_AXI_GP1_AWID(6'B0),
.S_AXI_GP1_WID(6'B0),
.S_AXI_ACP_ARREADY(),
.S_AXI_ACP_AWREADY(),
.S_AXI_ACP_BVALID(),
.S_AXI_ACP_RLAST(),
.S_AXI_ACP_RVALID(),
.S_AXI_ACP_WREADY(),
.S_AXI_ACP_BRESP(),
.S_AXI_ACP_RRESP(),
.S_AXI_ACP_BID(),
.S_AXI_ACP_RID(),
.S_AXI_ACP_RDATA(),
.S_AXI_ACP_ACLK(1'B0),
.S_AXI_ACP_ARVALID(1'B0),
.S_AXI_ACP_AWVALID(1'B0),
.S_AXI_ACP_BREADY(1'B0),
.S_AXI_ACP_RREADY(1'B0),
.S_AXI_ACP_WLAST(1'B0),
.S_AXI_ACP_WVALID(1'B0),
.S_AXI_ACP_ARID(3'B0),
.S_AXI_ACP_ARPROT(3'B0),
.S_AXI_ACP_AWID(3'B0),
.S_AXI_ACP_AWPROT(3'B0),
.S_AXI_ACP_WID(3'B0),
.S_AXI_ACP_ARADDR(32'B0),
.S_AXI_ACP_AWADDR(32'B0),
.S_AXI_ACP_ARCACHE(4'B0),
.S_AXI_ACP_ARLEN(4'B0),
.S_AXI_ACP_ARQOS(4'B0),
.S_AXI_ACP_AWCACHE(4'B0),
.S_AXI_ACP_AWLEN(4'B0),
.S_AXI_ACP_AWQOS(4'B0),
.S_AXI_ACP_ARBURST(2'B0),
.S_AXI_ACP_ARLOCK(2'B0),
.S_AXI_ACP_ARSIZE(3'B0),
.S_AXI_ACP_AWBURST(2'B0),
.S_AXI_ACP_AWLOCK(2'B0),
.S_AXI_ACP_AWSIZE(3'B0),
.S_AXI_ACP_ARUSER(5'B0),
.S_AXI_ACP_AWUSER(5'B0),
.S_AXI_ACP_WDATA(64'B0),
.S_AXI_ACP_WSTRB(8'B0),
.S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY),
.S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY),
.S_AXI_HP0_BVALID(S_AXI_HP0_BVALID),
.S_AXI_HP0_RLAST(S_AXI_HP0_RLAST),
.S_AXI_HP0_RVALID(S_AXI_HP0_RVALID),
.S_AXI_HP0_WREADY(S_AXI_HP0_WREADY),
.S_AXI_HP0_BRESP(S_AXI_HP0_BRESP),
.S_AXI_HP0_RRESP(S_AXI_HP0_RRESP),
.S_AXI_HP0_BID(S_AXI_HP0_BID),
.S_AXI_HP0_RID(S_AXI_HP0_RID),
.S_AXI_HP0_RDATA(S_AXI_HP0_RDATA),
.S_AXI_HP0_ACLK(S_AXI_HP0_ACLK),
.S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID),
.S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID),
.S_AXI_HP0_BREADY(S_AXI_HP0_BREADY),
.S_AXI_HP0_RREADY(S_AXI_HP0_RREADY),
.S_AXI_HP0_WLAST(S_AXI_HP0_WLAST),
.S_AXI_HP0_WVALID(S_AXI_HP0_WVALID),
.S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST),
.S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK),
.S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE),
.S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST),
.S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK),
.S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE),
.S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT),
.S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT),
.S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR),
.S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR),
.S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE),
.S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN),
.S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS),
.S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE),
.S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN),
.S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS),
.S_AXI_HP0_ARID(S_AXI_HP0_ARID),
.S_AXI_HP0_AWID(S_AXI_HP0_AWID),
.S_AXI_HP0_WID(S_AXI_HP0_WID),
.S_AXI_HP0_WDATA(S_AXI_HP0_WDATA),
.S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB),
.S_AXI_HP1_ARREADY(),
.S_AXI_HP1_AWREADY(),
.S_AXI_HP1_BVALID(),
.S_AXI_HP1_RLAST(),
.S_AXI_HP1_RVALID(),
.S_AXI_HP1_WREADY(),
.S_AXI_HP1_BRESP(),
.S_AXI_HP1_RRESP(),
.S_AXI_HP1_BID(),
.S_AXI_HP1_RID(),
.S_AXI_HP1_RDATA(),
.S_AXI_HP1_ACLK(1'B0),
.S_AXI_HP1_ARVALID(1'B0),
.S_AXI_HP1_AWVALID(1'B0),
.S_AXI_HP1_BREADY(1'B0),
.S_AXI_HP1_RREADY(1'B0),
.S_AXI_HP1_WLAST(1'B0),
.S_AXI_HP1_WVALID(1'B0),
.S_AXI_HP1_ARBURST(2'B0),
.S_AXI_HP1_ARLOCK(2'B0),
.S_AXI_HP1_ARSIZE(3'B0),
.S_AXI_HP1_AWBURST(2'B0),
.S_AXI_HP1_AWLOCK(2'B0),
.S_AXI_HP1_AWSIZE(3'B0),
.S_AXI_HP1_ARPROT(3'B0),
.S_AXI_HP1_AWPROT(3'B0),
.S_AXI_HP1_ARADDR(32'B0),
.S_AXI_HP1_AWADDR(32'B0),
.S_AXI_HP1_ARCACHE(4'B0),
.S_AXI_HP1_ARLEN(4'B0),
.S_AXI_HP1_ARQOS(4'B0),
.S_AXI_HP1_AWCACHE(4'B0),
.S_AXI_HP1_AWLEN(4'B0),
.S_AXI_HP1_AWQOS(4'B0),
.S_AXI_HP1_ARID(6'B0),
.S_AXI_HP1_AWID(6'B0),
.S_AXI_HP1_WID(6'B0),
.S_AXI_HP1_WDATA(64'B0),
.S_AXI_HP1_WSTRB(8'B0),
.S_AXI_HP2_ARREADY(),
.S_AXI_HP2_AWREADY(),
.S_AXI_HP2_BVALID(),
.S_AXI_HP2_RLAST(),
.S_AXI_HP2_RVALID(),
.S_AXI_HP2_WREADY(),
.S_AXI_HP2_BRESP(),
.S_AXI_HP2_RRESP(),
.S_AXI_HP2_BID(),
.S_AXI_HP2_RID(),
.S_AXI_HP2_RDATA(),
.S_AXI_HP2_ACLK(1'B0),
.S_AXI_HP2_ARVALID(1'B0),
.S_AXI_HP2_AWVALID(1'B0),
.S_AXI_HP2_BREADY(1'B0),
.S_AXI_HP2_RREADY(1'B0),
.S_AXI_HP2_WLAST(1'B0),
.S_AXI_HP2_WVALID(1'B0),
.S_AXI_HP2_ARBURST(2'B0),
.S_AXI_HP2_ARLOCK(2'B0),
.S_AXI_HP2_ARSIZE(3'B0),
.S_AXI_HP2_AWBURST(2'B0),
.S_AXI_HP2_AWLOCK(2'B0),
.S_AXI_HP2_AWSIZE(3'B0),
.S_AXI_HP2_ARPROT(3'B0),
.S_AXI_HP2_AWPROT(3'B0),
.S_AXI_HP2_ARADDR(32'B0),
.S_AXI_HP2_AWADDR(32'B0),
.S_AXI_HP2_ARCACHE(4'B0),
.S_AXI_HP2_ARLEN(4'B0),
.S_AXI_HP2_ARQOS(4'B0),
.S_AXI_HP2_AWCACHE(4'B0),
.S_AXI_HP2_AWLEN(4'B0),
.S_AXI_HP2_AWQOS(4'B0),
.S_AXI_HP2_ARID(6'B0),
.S_AXI_HP2_AWID(6'B0),
.S_AXI_HP2_WID(6'B0),
.S_AXI_HP2_WDATA(64'B0),
.S_AXI_HP2_WSTRB(8'B0),
.S_AXI_HP3_ARREADY(),
.S_AXI_HP3_AWREADY(),
.S_AXI_HP3_BVALID(),
.S_AXI_HP3_RLAST(),
.S_AXI_HP3_RVALID(),
.S_AXI_HP3_WREADY(),
.S_AXI_HP3_BRESP(),
.S_AXI_HP3_RRESP(),
.S_AXI_HP3_BID(),
.S_AXI_HP3_RID(),
.S_AXI_HP3_RDATA(),
.S_AXI_HP3_ACLK(1'B0),
.S_AXI_HP3_ARVALID(1'B0),
.S_AXI_HP3_AWVALID(1'B0),
.S_AXI_HP3_BREADY(1'B0),
.S_AXI_HP3_RREADY(1'B0),
.S_AXI_HP3_WLAST(1'B0),
.S_AXI_HP3_WVALID(1'B0),
.S_AXI_HP3_ARBURST(2'B0),
.S_AXI_HP3_ARLOCK(2'B0),
.S_AXI_HP3_ARSIZE(3'B0),
.S_AXI_HP3_AWBURST(2'B0),
.S_AXI_HP3_AWLOCK(2'B0),
.S_AXI_HP3_AWSIZE(3'B0),
.S_AXI_HP3_ARPROT(3'B0),
.S_AXI_HP3_AWPROT(3'B0),
.S_AXI_HP3_ARADDR(32'B0),
.S_AXI_HP3_AWADDR(32'B0),
.S_AXI_HP3_ARCACHE(4'B0),
.S_AXI_HP3_ARLEN(4'B0),
.S_AXI_HP3_ARQOS(4'B0),
.S_AXI_HP3_AWCACHE(4'B0),
.S_AXI_HP3_AWLEN(4'B0),
.S_AXI_HP3_AWQOS(4'B0),
.S_AXI_HP3_ARID(6'B0),
.S_AXI_HP3_AWID(6'B0),
.S_AXI_HP3_WID(6'B0),
.S_AXI_HP3_WDATA(64'B0),
.S_AXI_HP3_WSTRB(8'B0),
.FCLK_CLK0(FCLK_CLK0),
.FCLK_CLK1(FCLK_CLK1),
.FCLK_CLK2(FCLK_CLK2),
.FCLK_CLK3(),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(FCLK_RESET1_N),
.FCLK_RESET2_N(),
.FCLK_RESET3_N(),
.IRQ_F2P(16'B0),
.PS_SRSTB(PS_SRSTB),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_ls__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_ls__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFBBN_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_clk_cl_sparc_cmp.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_clk_cl_sparc_cmp(/*AUTOARG*/
// Outputs
so, rclk, dbginit_l, cluster_grst_l,
// Inputs
si, se, grst_l, gdbginit_l, gclk, cluster_cken, arst_l,
adbginit_l
);
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output cluster_grst_l; // From I0 of cluster_header.v
output dbginit_l; // From I0 of cluster_header.v
output rclk; // From I0 of cluster_header.v
output so; // From I0 of cluster_header.v
// End of automatics
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input adbginit_l; // To I0 of cluster_header.v
input arst_l; // To I0 of cluster_header.v
input cluster_cken; // To I0 of cluster_header.v
input gclk; // To I0 of cluster_header.v
input gdbginit_l; // To I0 of cluster_header.v
input grst_l; // To I0 of cluster_header.v
input se; // To I0 of cluster_header.v
input si; // To I0 of cluster_header.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
// End of automatics
cluster_header I0 (/*AUTOINST*/
// Outputs
.dbginit_l (dbginit_l),
.cluster_grst_l (cluster_grst_l),
.rclk (rclk),
.so (so),
// Inputs
.gclk (gclk),
.cluster_cken (cluster_cken),
.arst_l (arst_l),
.grst_l (grst_l),
.adbginit_l (adbginit_l),
.gdbginit_l (gdbginit_l),
.si (si),
.se (se));
//output so ;
//output dbginit_l ;
//output cluster_grst_l ;
//output rclk ;
//input si ;
//input se ;
//input adbginit_l ;
//input gdbginit_l ;
//input arst_l ;
//input grst_l ;
//input cluster_cken ;
//input gclk ;
endmodule // bw_clk_cl_sparc_cmp
// Local Variables:
// verilog-library-directories:("." "../../common/rtl")
// End:
|
`timescale 1 ns / 1 ps
module PmodAD1_v1_0 #
(
// Users to add parameters here
// 2x89KSPS with these parameters
parameter INCLUDE_DEBUG_INTERFACE = 0,
parameter AD1_CLOCKS_PER_BIT = 20,//1 bit per 200ns
parameter AD1_CLOCKS_BEFORE_DATA = 60,//600ns
parameter AD1_CLOCKS_AFTER_DATA = 500,//5us
parameter AD1_CLOCKS_BETWEEN_TRANSACTIONS = 400,//4us
// User parameters ends
// Do not modify the parameters beyond this line
// Parameters of Axi Slave Bus Interface S00_AXI
parameter integer C_S00_AXI_DATA_WIDTH = 32,
parameter integer C_S00_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
input Pmod_out_pin10_i,
output Pmod_out_pin10_o,
output Pmod_out_pin10_t,
input Pmod_out_pin1_i,
output Pmod_out_pin1_o,
output Pmod_out_pin1_t,
input Pmod_out_pin2_i,
output Pmod_out_pin2_o,
output Pmod_out_pin2_t,
input Pmod_out_pin3_i,
output Pmod_out_pin3_o,
output Pmod_out_pin3_t,
input Pmod_out_pin4_i,
output Pmod_out_pin4_o,
output Pmod_out_pin4_t,
input Pmod_out_pin7_i,
output Pmod_out_pin7_o,
output Pmod_out_pin7_t,
input Pmod_out_pin8_i,
output Pmod_out_pin8_o,
output Pmod_out_pin8_t,
input Pmod_out_pin9_i,
output Pmod_out_pin9_o,
output Pmod_out_pin9_t,
output wire [1:0] led,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXI
input wire s00_axi_aclk,
input wire s00_axi_aresetn,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
input wire [2 : 0] s00_axi_awprot,
input wire s00_axi_awvalid,
output wire s00_axi_awready,
input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
input wire s00_axi_wvalid,
output wire s00_axi_wready,
output wire [1 : 0] s00_axi_bresp,
output wire s00_axi_bvalid,
input wire s00_axi_bready,
input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
input wire [2 : 0] s00_axi_arprot,
input wire s00_axi_arvalid,
output wire s00_axi_arready,
output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
output wire [1 : 0] s00_axi_rresp,
output wire s00_axi_rvalid,
input wire s00_axi_rready
);
wire ad1_cs;
wire ad1_sdin0;
wire ad1_sdin1;
wire ad1_sclk;
// Instantiation of Axi Bus Interface S00_AXI
PmodAD1_v1_0_S00_AXI # (
.INCLUDE_DEBUG_INTERFACE(INCLUDE_DEBUG_INTERFACE),
.C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
.C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH),
.AD1_CLOCKS_PER_BIT(AD1_CLOCKS_PER_BIT),//1 bit per 200ns
.AD1_CLOCKS_BEFORE_DATA(AD1_CLOCKS_BEFORE_DATA),//600ns
.AD1_CLOCKS_AFTER_DATA(AD1_CLOCKS_AFTER_DATA),//5us
.AD1_CLOCKS_BETWEEN_TRANSACTIONS(AD1_CLOCKS_BETWEEN_TRANSACTIONS)//4us
) PmodAD1_v1_0_S00_AXI_inst (
.ad1_cs (ad1_cs ),
.ad1_sdin0 (ad1_sdin0),
.ad1_sdin1 (ad1_sdin1),
.ad1_sclk (ad1_sclk ),
.led(led),
.S_AXI_ACLK(s00_axi_aclk),
.S_AXI_ARESETN(s00_axi_aresetn),
.S_AXI_AWADDR(s00_axi_awaddr),
.S_AXI_AWPROT(s00_axi_awprot),
.S_AXI_AWVALID(s00_axi_awvalid),
.S_AXI_AWREADY(s00_axi_awready),
.S_AXI_WDATA(s00_axi_wdata),
.S_AXI_WSTRB(s00_axi_wstrb),
.S_AXI_WVALID(s00_axi_wvalid),
.S_AXI_WREADY(s00_axi_wready),
.S_AXI_BRESP(s00_axi_bresp),
.S_AXI_BVALID(s00_axi_bvalid),
.S_AXI_BREADY(s00_axi_bready),
.S_AXI_ARADDR(s00_axi_araddr),
.S_AXI_ARPROT(s00_axi_arprot),
.S_AXI_ARVALID(s00_axi_arvalid),
.S_AXI_ARREADY(s00_axi_arready),
.S_AXI_RDATA(s00_axi_rdata),
.S_AXI_RRESP(s00_axi_rresp),
.S_AXI_RVALID(s00_axi_rvalid),
.S_AXI_RREADY(s00_axi_rready)
);
pmod_bridge_0 PmodAD1_pmod_bridge_0_0
(.in0_I(),
.in0_O(ad1_cs),
.in0_T(1'b0),
.in1_I(ad1_sdin0),
.in1_O(),
.in1_T(1'b1),
.in2_I(ad1_sdin1),
.in2_O(),
.in2_T(1'b1),
.in3_I(),
.in3_O(ad1_sclk),
.in3_T(1'b0),
.out0_I(Pmod_out_pin1_i),
.out0_O(Pmod_out_pin1_o),
.out0_T(Pmod_out_pin1_t),
.out1_I(Pmod_out_pin2_i),
.out1_O(Pmod_out_pin2_o),
.out1_T(Pmod_out_pin2_t),
.out2_I(Pmod_out_pin3_i),
.out2_O(Pmod_out_pin3_o),
.out2_T(Pmod_out_pin3_t),
.out3_I(Pmod_out_pin4_i),
.out3_O(Pmod_out_pin4_o),
.out3_T(Pmod_out_pin4_t),
.out4_I(Pmod_out_pin7_i),
.out4_O(Pmod_out_pin7_o),
.out4_T(Pmod_out_pin7_t),
.out5_I(Pmod_out_pin8_i),
.out5_O(Pmod_out_pin8_o),
.out5_T(Pmod_out_pin8_t),
.out6_I(Pmod_out_pin9_i),
.out6_O(Pmod_out_pin9_o),
.out6_T(Pmod_out_pin9_t),
.out7_I(Pmod_out_pin10_i),
.out7_O(Pmod_out_pin10_o),
.out7_T(Pmod_out_pin10_t)
);
// Add user logic here
// User logic ends
endmodule
|
`timescale 1ns / 1ps
`default_nettype none //To avoid bugs involving implicit nets
////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Acknowledgements: Prof. Kyle Gilsdorf (Arizona State)
// - http://www.public.asu.edu/~kyle135/
// - [email protected]
//
//
// Author: Rushang Vinod Vandana Karia
// - Masters in Computer Science @ Arizona State
// - [email protected]
// - 4806283130
// - github.com/RushangKaria
//
//
// Module: Pulse_Width_Modulation.v
//
//
// Description : Modulate the backlight so that we can the pixels are cleary
// visible
//
// Copyright : Copyright (C) 2014 Rushang Vinod Vandana Karia
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////////
module Pulse_Width_Modulation #(
parameter
C_CLK_I_FREQUENCY = 50, //MHz
C_PWM_FREQUENCY = 20000, //KHz
C_PWM_RESOLUTION = 8
)
(
input wire CLK_I,
input wire RST_I,
input wire [C_PWM_RESOLUTION-1:0] DUTY_FACTOR_I,
output wire PWM_O
);
///////////////////////////////////////////////////////////////////////
// MODULE SPECIFIC PARAMETER DECLARATIONS
///////////////////////////////////////////////////////////////////////
parameter integer C_CLOCK_DIVIDER = C_CLK_I_FREQUENCY*1000000/C_PWM_FREQUENCY/2/2**C_PWM_RESOLUTION;
///////////////////////////////////////////////////////////////////////
// PORTS ORIGINATING IN MODULE
///////////////////////////////////////////////////////////////////////
reg [C_PWM_RESOLUTION-1:0] PWMCnt;
reg PWMCntEn;
reg int_PWM;
reg [$clog2(C_CLOCK_DIVIDER):0] PSCnt;
reg PWMCntUp;
///////////////////////////////////////////////////////////////////////////////////////
// SYNTHESIS SPECIFIC INSTRUCTIONS
///////////////////////////////////////////////////////////////////////////////////////
initial
begin
PWMCnt = 'b0;
PSCnt = 'b0;
PWMCntUp = 1'b0;
end
///////////////////////////////////////////////////////////////////////
// PRE-SCALER
///////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(PSCnt == C_CLOCK_DIVIDER)
begin
PSCnt <= 'b0;
PWMCntEn <= 1'b1;
end
else
begin
PSCnt <= PSCnt + 1;
PWMCntEn <= 1'b0;
end
///////////////////////////////////////////////////////////////////////
// Up/Down counter for mid-aligned PWM pulse
// In designs with multiple PWM chanels mid-alignment eliminates
// simultaneously
//
// switching PWM outputs, resulting in less stress on power rails
///////////////////////////////////////////////////////////////////////
always@(posedge CLK_I) //This implementation is weird....variables used in the VHDL code
begin
//{
if(RST_I)
PWMCnt <= 'b0;
else if(PWMCntEn)
if(PWMCntUp)
PWMCnt <= PWMCnt + 1;
else
PWMCnt <= PWMCnt - 1;
if(PWMCnt==0)
PWMCntUp <= 1'b1;
else if(PWMCnt == 2**C_PWM_RESOLUTION-1)
PWMCntUp <= 1'b0;
//}
end
///////////////////////////////////////////////////////////////////////
// PWM OUTPUT
///////////////////////////////////////////////////////////////////////
always@(posedge CLK_I)
if(PWMCnt < DUTY_FACTOR_I)
int_PWM <= 1'b1;
else
int_PWM <= 1'b0;
assign PWM_O = (RST_I)?'bz:int_PWM;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__dlygate4sd2 (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLYGATE4SD2_BEHAVIORAL_V |
// (C) 2001-2018 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files from any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel FPGA IP License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
/*
This block is responsible for communicating with the host processor/
descriptor prefetching master block. It uses FIFOs to buffer descriptors
to keep the read and write masters operating without intervention from a
host processor. This block is comprised of three main blocks:
1) Descriptor buffer
2) CSR
3) Response
The descriptor buffer recieves descriptors from a host/prefetcher and
registers the incoming byte lanes. When the descriptor 'go' bit has been
written, the descriptor is committed to the read/write descriptor buffers.
From there the descriptors are exposed to the read and write masters without
intervention from the host. The descriptor port is either 128 or 256 bits
wide depending on whether or not the enhanced features setting has been enabled.
Since the port is write only minimial logic will be created in the fabric
to adapt the byte enables for narrow masters connecting to this port. This
port contains a single address so address bits are exposed to the fabric.
The CSR (control-status register) block is used to provide information
back to the host as well as allow the SGDMA to be controlled on a
non-descriptor basis. The host driver should be written to mostly interact
with this port as interrupts and status information is accessible from this
block.
The optional response block is used to feed information on a per descriptor
basis back to the host or prefetching descriptor master. In most cases the
port will be used for sharing infomation about ST->MM transfers.
Communication between this block and the masters is performed using pairs
of Avalon-ST port connections. When the SGDMA is setup for MM->ST then the
write master port connections are removed and visa vera for ST->MM and the
read master. For more detailed information refer to "SGDMA_dispatcher_ug.pdf"
for more details.
Author: JCJB
Date: 08/13/2010
1.0 - Initial release
1.1 - Changed the stopped and resetting logic to correctly reflect the state
of the hardware (this block and the masters).
1.2 - Added stop descriptors logic
1.3 - Fixed the busy status so that it doesn't become ready too soon.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module dispatcher (
clk,
reset,
// 128/256 bit write only port for feeding the dispatcher descriptors, no address since it's only one word wide, blocking when too many descriptors are buffered
descriptor_writedata,
descriptor_byteenable,
descriptor_write,
descriptor_waitrequest,
// st interface for feeding the dispatcher descriptors. This interface is used if dispatcher descriptor interface is set to ST Source instead of Avalon MM Slave
snk_descriptor_data,
snk_descriptor_valid,
snk_descriptor_ready,
// control and status port, 32 bits wide with a read latency of 2 and non-blocking
csr_writedata,
csr_byteenable,
csr_write,
csr_readdata,
csr_read,
csr_address, // 4 addresses when ENHANCED_FEATURES is off (zero) otherwise 8 addresses are available
csr_irq, // only available if the response port is not an ST source (in that case the SGDMA pre-fetching block will issue interrupts)
// response slave port (when "RESPONSE_PORT" is set to 0), 32 bits wide, read only, and a read latency of 3 cycles
mm_response_readdata,
mm_response_read,
mm_response_address, // only two addresses
mm_response_byteenable, // last byte read pops the response FIFO
mm_response_waitrequest,
// response source port (when "RESPONSE_PORT" is set to 1),
src_response_data,
src_response_valid,
src_response_ready,
// write master source port (sends commands to write master)
src_write_master_data,
src_write_master_valid,
src_write_master_ready,
// write master sink port (recieves response from write master)
snk_write_master_data,
snk_write_master_valid,
snk_write_master_ready,
// read master source port (sends commands to read master)
src_read_master_data,
src_read_master_valid,
src_read_master_ready,
// read master sink port (recieves response from the read master)
snk_read_master_data,
snk_read_master_valid,
snk_read_master_ready
);
// y = log2(x)
function integer log2;
input integer x;
begin
x = x-1;
for(log2=0; x>0; log2=log2+1)
x = x>>1;
end
endfunction
parameter MODE = 0; // 0 for MM->MM, 1 for MM->ST, 2 for ST->MM
parameter RESPONSE_PORT = 0; // 0 for MM, 1 for ST, 2 for Disabled // normally disabled for all but ST->MM transfers
parameter DESCRIPTOR_FIFO_DEPTH = 128; // 16-1024 in powers of 2
parameter ENHANCED_FEATURES = 1; // 1 for Enabled, 0 for Disabled
parameter DESCRIPTOR_WIDTH = 256; // 256 when enhanced mode is on, 128 for off (needs to be controlled by callback since it influences data width)
parameter DESCRIPTOR_BYTEENABLE_WIDTH = 32; // 32 when enhanced mode is on, 16 for off (needs to be controlled by callback since it influences byte enable width)
parameter CSR_ADDRESS_WIDTH = 3; // always 3 bits wide
parameter DESCRIPTOR_INTERFACE = 0; // 0: Avalon MM Slave, 1:Avalon ST Source
localparam RESPONSE_FIFO_DEPTH = 2 * DESCRIPTOR_FIFO_DEPTH;
localparam DESCRIPTOR_FIFO_DEPTH_LOG2 = log2(DESCRIPTOR_FIFO_DEPTH);
localparam RESPONSE_FIFO_DEPTH_LOG2 = log2(RESPONSE_FIFO_DEPTH);
input clk;
input reset;
input [DESCRIPTOR_WIDTH-1:0] descriptor_writedata;
input [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable;
input descriptor_write;
output wire descriptor_waitrequest;
input [DESCRIPTOR_WIDTH-1:0] snk_descriptor_data;
input snk_descriptor_valid;
output wire snk_descriptor_ready;
input [31:0] csr_writedata;
input [3:0] csr_byteenable;
input csr_write;
output wire [31:0] csr_readdata;
input csr_read;
input [CSR_ADDRESS_WIDTH-1:0] csr_address;
output wire csr_irq;
// Used by a host with a master (like Nios II)
output wire [31:0] mm_response_readdata;
input mm_response_read;
input mm_response_address;
input [3:0] mm_response_byteenable;
output wire mm_response_waitrequest;
// Used by a pre-fetching master
output wire [255:0] src_response_data; // making wide in case we need to jam more signals in here, unnecessary bits will be grounded/optimized away
output wire src_response_valid;
input src_response_ready;
output wire [255:0] src_write_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away
output wire src_write_master_valid;
input src_write_master_ready;
input [255:0] snk_write_master_data; // might need to jam more bits in......
input snk_write_master_valid;
output wire snk_write_master_ready;
output wire [255:0] src_read_master_data; // don't know how many bits the master will use, unnecessary bits will be grounded/optimized away
output wire src_read_master_valid;
input src_read_master_ready;
input [255:0] snk_read_master_data; // might need to jam more bits in......
input snk_read_master_valid;
output wire snk_read_master_ready;
/* Internal wires and registers */
// descriptor information
wire read_command_valid;
wire read_command_ready;
wire [255:0] read_command_data;
wire read_command_empty;
wire read_command_full;
wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] read_command_used; // true used signal so extra MSB is included
wire write_command_valid;
wire write_command_ready;
wire [255:0] write_command_data;
wire write_command_empty;
wire write_command_full;
wire [DESCRIPTOR_FIFO_DEPTH_LOG2:0] write_command_used; // true used signal so extra MSB is included
wire [31:0] sequence_number;
wire transfer_complete_IRQ_mask;
wire early_termination_IRQ_mask;
wire [7:0] error_IRQ_mask;
wire descriptor_buffer_empty;
wire descriptor_buffer_full;
wire [15:0] write_descriptor_watermark;
wire [15:0] read_descriptor_watermark;
wire [31:0] descriptor_watermark;
wire busy;
reg all_transfers_done;
wire done_strobe;
wire stop_issuing_commands;
wire stop;
wire sw_reset;
wire stop_on_error;
wire stop_on_early_termination;
wire stop_descriptors;
wire reset_stalled;
wire master_stop_state;
wire descriptors_stop_state;
wire stop_state;
wire stopped_on_error;
wire stopped_on_early_termination;
wire response_fifo_full;
wire response_fifo_empty;
wire [15:0] response_watermark;
wire [7:0] response_error;
wire response_early_termination;
wire [31:0] response_actual_bytes_transferred;
wire [DESCRIPTOR_WIDTH-1:0] descriptor_writedata_int;
wire [DESCRIPTOR_BYTEENABLE_WIDTH-1:0] descriptor_byteenable_int;
wire descriptor_write_int;
wire descriptor_waitrequest_int;
/************************************************ REGISTERS *******************************************************/
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
all_transfers_done <= 1;
end
else if (((done_strobe == 1) & (read_command_empty == 1) & (write_command_empty == 1)) | (sw_reset == 1))
begin
all_transfers_done <= 1; // no more descriptors are buffered and the last transfer completed
end
else if ((read_command_empty == 0) | (write_command_empty == 0))
begin
all_transfers_done <= 0; // at least one descriptor has been buffered, this will deassert two clock cycles after the first descriptor is written into the descriptor FIFO
end
end
/********************************************** END REGISTERS *****************************************************/
/******************************************* MODULE DECLERATIONS **************************************************/
// the descriptor buffers block instantiates the descriptor FIFOs and handshaking logic with the master command ports
descriptor_buffers the_descriptor_buffers (
.clk (clk),
.reset (reset),
.writedata (descriptor_writedata_int),
.write (descriptor_write_int),
.byteenable (descriptor_byteenable_int),
.waitrequest (descriptor_waitrequest_int),
.read_command_valid (read_command_valid),
.read_command_ready (read_command_ready),
.read_command_data (read_command_data),
.read_command_empty (read_command_empty),
.read_command_full (read_command_full),
.read_command_used (read_command_used),
.write_command_valid (write_command_valid),
.write_command_ready (write_command_ready),
.write_command_data (write_command_data),
.write_command_empty (write_command_empty),
.write_command_full (write_command_full),
.write_command_used (write_command_used),
.stop_issuing_commands (stop_issuing_commands),
.stop (stop),
.sw_reset (sw_reset),
.sequence_number (sequence_number),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask)
);
defparam the_descriptor_buffers.MODE = MODE;
defparam the_descriptor_buffers.DATA_WIDTH = DESCRIPTOR_WIDTH;
defparam the_descriptor_buffers.BYTE_ENABLE_WIDTH = DESCRIPTOR_WIDTH/8;
defparam the_descriptor_buffers.FIFO_DEPTH = DESCRIPTOR_FIFO_DEPTH;
defparam the_descriptor_buffers.FIFO_DEPTH_LOG2 = DESCRIPTOR_FIFO_DEPTH_LOG2;
// Control and status registers (and interrupts when a host connects directly to this block)
csr_block the_csr_block (
.clk (clk),
.reset (reset),
.csr_writedata (csr_writedata),
.csr_write (csr_write),
.csr_byteenable (csr_byteenable),
.csr_readdata (csr_readdata),
.csr_read (csr_read),
.csr_address (csr_address),
.csr_irq (csr_irq),
.done_strobe (done_strobe),
.busy (busy),
.descriptor_buffer_empty (descriptor_buffer_empty),
.descriptor_buffer_full (descriptor_buffer_full),
.stop_state (stop_state),
.stopped_on_error (stopped_on_error),
.stopped_on_early_termination (stopped_on_early_termination),
.stop_descriptors (stop_descriptors),
.reset_stalled (reset_stalled), // from the master(s) to tell the CSR block that it's still resetting
.stop (stop),
.sw_reset (sw_reset),
.stop_on_error (stop_on_error),
.stop_on_early_termination (stop_on_early_termination),
.sequence_number (sequence_number),
.descriptor_watermark (descriptor_watermark),
.response_watermark (response_watermark),
.response_buffer_empty (response_fifo_empty),
.response_buffer_full (response_fifo_full),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.error (response_error),
.early_termination (response_early_termination)
);
defparam the_csr_block.ADDRESS_WIDTH = CSR_ADDRESS_WIDTH;
// Optional response port. When using a directly connected host it'll be a slave port and using a pre-fetching descriptor master it will be a streaming source port.
response_block the_response_block (
.clk (clk),
.reset (reset),
.mm_response_readdata (mm_response_readdata),
.mm_response_read (mm_response_read),
.mm_response_address (mm_response_address),
.mm_response_byteenable (mm_response_byteenable),
.mm_response_waitrequest (mm_response_waitrequest),
.src_response_data (src_response_data),
.src_response_valid (src_response_valid),
.src_response_ready (src_response_ready),
.sw_reset (sw_reset),
.response_watermark (response_watermark),
.response_fifo_full (response_fifo_full),
.response_fifo_empty (response_fifo_empty),
.done_strobe (done_strobe),
.actual_bytes_transferred (response_actual_bytes_transferred),
.error (response_error),
.early_termination (response_early_termination),
.transfer_complete_IRQ_mask (transfer_complete_IRQ_mask),
.error_IRQ_mask (error_IRQ_mask),
.early_termination_IRQ_mask (early_termination_IRQ_mask),
.descriptor_buffer_full (descriptor_buffer_full)
);
defparam the_response_block.RESPONSE_PORT = RESPONSE_PORT;
defparam the_response_block.FIFO_DEPTH = RESPONSE_FIFO_DEPTH;
defparam the_response_block.FIFO_DEPTH_LOG2 = RESPONSE_FIFO_DEPTH_LOG2;
/***************************************** END MODULE DECLERATIONS ************************************************/
/****************************************** COMBINATIONAL SIGNALS *************************************************/
// this block issues the commands so it's always ready for a response. The response FIFO fill level will be used to
// make sure additional ST-->MM commands are not issued if there is no room to catch the response.
assign snk_write_master_ready = 1'b1;
assign snk_read_master_ready = 1'b1;
// since the snk_read/write_master_valid is always high a completed response from the master should always be accepted in one clock cycle and so we generate the strobe based on that condition
assign done_strobe = (MODE == 1)? (snk_read_master_ready & snk_read_master_valid) : (snk_write_master_ready & snk_write_master_valid);
assign stop_issuing_commands = (response_fifo_full == 1) | (stop_descriptors == 1);
assign src_write_master_valid = write_command_valid;
assign write_command_ready = src_write_master_ready;
assign src_write_master_data = write_command_data;
assign src_read_master_valid = read_command_valid;
assign read_command_ready = src_read_master_ready;
assign src_read_master_data = read_command_data;
assign busy = (all_transfers_done == 0); // transfers are still occuring
assign descriptor_buffer_empty = (read_command_empty == 1) & (write_command_empty == 1);
assign descriptor_buffer_full = (read_command_full == 1) | (write_command_full == 1);
assign write_descriptor_watermark = 16'h0000 | write_command_used; // zero padding the upper unused bits
assign read_descriptor_watermark = 16'h0000 | read_command_used; // zero padding the upper unused bits
assign descriptor_watermark = {write_descriptor_watermark, read_descriptor_watermark};
assign reset_stalled = snk_read_master_data[0] | snk_write_master_data[32];
assign master_stop_state = ((MODE == 0)? (snk_read_master_data[1] & snk_write_master_data[33]) :
(MODE == 1)? snk_read_master_data[1] : snk_write_master_data[33]);
assign descriptors_stop_state = (stop_descriptors == 1) & ((MODE == 0)? ((src_read_master_ready == 1) & (src_write_master_ready == 1)) :
(MODE == 1)? (src_read_master_ready == 1) : (src_write_master_ready == 1));
assign stop_state = (master_stop_state == 1) | (descriptors_stop_state == 1);
assign response_actual_bytes_transferred = snk_write_master_data[31:0];
assign response_error = snk_write_master_data[41:34];
assign response_early_termination = snk_write_master_data[42];
// descriptor interface muxes
assign descriptor_writedata_int = (DESCRIPTOR_INTERFACE == 0) ? descriptor_writedata : snk_descriptor_data;
assign descriptor_byteenable_int = (DESCRIPTOR_INTERFACE == 0) ? descriptor_byteenable : {DESCRIPTOR_BYTEENABLE_WIDTH{1'b1}};
assign descriptor_write_int = (DESCRIPTOR_INTERFACE == 0) ? descriptor_write : snk_descriptor_valid;
assign descriptor_waitrequest = (DESCRIPTOR_INTERFACE == 0) ? descriptor_waitrequest_int : 1'b1;
assign snk_descriptor_ready = (DESCRIPTOR_INTERFACE == 0) ? 1'b0 : ~descriptor_waitrequest_int;
/**************************************** END COMBINATIONAL SIGNALS ***********************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V
/**
* fa: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__fa (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out ;
wire and1_out ;
wire and2_out ;
wire nor0_out ;
wire nor1_out ;
wire or1_out_COUT ;
wire pwrgood_pp0_out_COUT;
wire or2_out_SUM ;
wire pwrgood_pp1_out_SUM ;
// Name Output Other arguments
or or0 (or0_out , CIN, B );
and and0 (and0_out , or0_out, A );
and and1 (and1_out , B, CIN );
or or1 (or1_out_COUT , and1_out, and0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_COUT, or1_out_COUT, VPWR, VGND);
buf buf0 (COUT , pwrgood_pp0_out_COUT );
and and2 (and2_out , CIN, A, B );
nor nor0 (nor0_out , A, or0_out );
nor nor1 (nor1_out , nor0_out, COUT );
or or2 (or2_out_SUM , nor1_out, and2_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_SUM , or2_out_SUM, VPWR, VGND );
buf buf1 (SUM , pwrgood_pp1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__FA_BEHAVIORAL_PP_V |
/* verilator lint_off WIDTH */
/* verilator lint_off UNUSED */
module output_data(
input clock,
// meta data
input isDrawAreaVGA,
input isOsdTextArea,
input isCharPixel,
input isOsdBgArea,
input isScanline,
input [8:0] scanline_intensity,
// ...
input [23:0] data,
output reg [23:0] data_out
);
localparam ONE_TO_ONE = 9'd_256;
`ifdef OSD_BACKGROUND_ALPHA
localparam OSD_BACKGROUND_ALPHA = `OSD_BACKGROUND_ALPHA;
`else
localparam OSD_BACKGROUND_ALPHA = 9'd_64;
`endif
reg [23:0] alpha_data;
reg [8:0] alpha_alpha;
wire [23:0] alpha_out;
alpha_calc ac (
.clock(clock),
.data(alpha_data),
.alpha(alpha_alpha),
.data_out(alpha_out)
);
function [8:0] trunc_osdbg(
input[16:0] value
);
trunc_osdbg = value[16:8];
endfunction
reg [8:0] osd_alpha;
reg isCharPixel_q, isOsdTextArea_q, isOsdBgArea_q, isDrawAreaVGA_q, isScanline_q;
reg [23:0] data_q;
always @(posedge clock) begin
data_q <= data;
osd_alpha <= OSD_BACKGROUND_ALPHA * scanline_intensity;
{ isCharPixel_q, isOsdTextArea_q, isOsdBgArea_q, isDrawAreaVGA_q, isScanline_q } <= { isCharPixel, isOsdTextArea, isOsdBgArea, isDrawAreaVGA, isScanline };
case ({ isOsdTextArea_q, isOsdBgArea_q, isDrawAreaVGA_q })
3'b_001: begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? scanline_intensity : ONE_TO_ONE);
end
3'b_011: begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? trunc_osdbg(osd_alpha) : OSD_BACKGROUND_ALPHA);
end
3'b_111: begin
if (isCharPixel_q) begin
alpha_data <= 24'hFFFFFF;
alpha_alpha <= ONE_TO_ONE;
end else begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? trunc_osdbg(osd_alpha) : OSD_BACKGROUND_ALPHA);
end
end
default: begin
alpha_data <= 24'h00;
alpha_alpha <= ONE_TO_ONE;
end
endcase
data_out <= alpha_out;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__TAPVGND_SYMBOL_V
`define SKY130_FD_SC_HD__TAPVGND_SYMBOL_V
/**
* tapvgnd: Tap cell with tap to ground, isolated power connection
* 1 row down.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__tapvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__TAPVGND_SYMBOL_V
|
module asyc_add_tb;
reg reset = 1;
reg button = 0;
reg clk = 0;
wire [6:0] leds;
asyc_add add1(leds, reset, button, clk);
initial begin
$monitor($time, " reset: %b, button: %b, digit: %b, leds: %b",
reset, button, add1.digit, leds);
#0 reset = 1'b0;
#10 reset = 1'b1;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#10 reset = 1'b0;
#10 reset = 1'b1;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
#5 button = 1'b1;
#5 button = 1'b0;
end
initial forever #1 clk <= ~clk;
initial #400 $finish;
endmodule
|
// niosii.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module niosii (
input wire clk_clk, // clk.clk
output wire [7:0] pio_0_external_connection_export, // pio_0_external_connection.export
input wire reset_reset_n, // reset.reset_n
output wire [12:0] sdram_addr, // sdram.addr
output wire [1:0] sdram_ba, // .ba
output wire sdram_cas_n, // .cas_n
output wire sdram_cke, // .cke
output wire sdram_cs_n, // .cs_n
inout wire [15:0] sdram_dq, // .dq
output wire [1:0] sdram_dqm, // .dqm
output wire sdram_ras_n, // .ras_n
output wire sdram_we_n, // .we_n
output wire sdram_clk_clk // sdram_clk.clk
);
wire sys_sdram_pll_0_sys_clk_clk; // sys_sdram_pll_0:sys_clk_clk -> [irq_mapper:clk, irq_synchronizer:sender_clk, mm_interconnect_0:sys_sdram_pll_0_sys_clk_clk, nios2_gen2_0:clk, onchip_memory2_0:clk, pio_0:clk, rst_controller_001:clk, sdram_controller_0:clk]
wire [31:0] nios2_gen2_0_data_master_readdata; // mm_interconnect_0:nios2_gen2_0_data_master_readdata -> nios2_gen2_0:d_readdata
wire nios2_gen2_0_data_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_data_master_waitrequest -> nios2_gen2_0:d_waitrequest
wire nios2_gen2_0_data_master_debugaccess; // nios2_gen2_0:debug_mem_slave_debugaccess_to_roms -> mm_interconnect_0:nios2_gen2_0_data_master_debugaccess
wire [26:0] nios2_gen2_0_data_master_address; // nios2_gen2_0:d_address -> mm_interconnect_0:nios2_gen2_0_data_master_address
wire [3:0] nios2_gen2_0_data_master_byteenable; // nios2_gen2_0:d_byteenable -> mm_interconnect_0:nios2_gen2_0_data_master_byteenable
wire nios2_gen2_0_data_master_read; // nios2_gen2_0:d_read -> mm_interconnect_0:nios2_gen2_0_data_master_read
wire nios2_gen2_0_data_master_write; // nios2_gen2_0:d_write -> mm_interconnect_0:nios2_gen2_0_data_master_write
wire [31:0] nios2_gen2_0_data_master_writedata; // nios2_gen2_0:d_writedata -> mm_interconnect_0:nios2_gen2_0_data_master_writedata
wire [31:0] nios2_gen2_0_instruction_master_readdata; // mm_interconnect_0:nios2_gen2_0_instruction_master_readdata -> nios2_gen2_0:i_readdata
wire nios2_gen2_0_instruction_master_waitrequest; // mm_interconnect_0:nios2_gen2_0_instruction_master_waitrequest -> nios2_gen2_0:i_waitrequest
wire [26:0] nios2_gen2_0_instruction_master_address; // nios2_gen2_0:i_address -> mm_interconnect_0:nios2_gen2_0_instruction_master_address
wire nios2_gen2_0_instruction_master_read; // nios2_gen2_0:i_read -> mm_interconnect_0:nios2_gen2_0_instruction_master_read
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_chipselect -> jtag_uart_0:av_chipselect
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata; // jtag_uart_0:av_readdata -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_readdata
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest; // jtag_uart_0:av_waitrequest -> mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_waitrequest
wire [0:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_address -> jtag_uart_0:av_address
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_read -> jtag_uart_0:av_read_n
wire mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_write -> jtag_uart_0:av_write_n
wire [31:0] mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata; // mm_interconnect_0:jtag_uart_0_avalon_jtag_slave_writedata -> jtag_uart_0:av_writedata
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata; // nios2_gen2_0:debug_mem_slave_readdata -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_readdata
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest; // nios2_gen2_0:debug_mem_slave_waitrequest -> mm_interconnect_0:nios2_gen2_0_debug_mem_slave_waitrequest
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_debugaccess -> nios2_gen2_0:debug_mem_slave_debugaccess
wire [8:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_address -> nios2_gen2_0:debug_mem_slave_address
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_read -> nios2_gen2_0:debug_mem_slave_read
wire [3:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_byteenable -> nios2_gen2_0:debug_mem_slave_byteenable
wire mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_write -> nios2_gen2_0:debug_mem_slave_write
wire [31:0] mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata; // mm_interconnect_0:nios2_gen2_0_debug_mem_slave_writedata -> nios2_gen2_0:debug_mem_slave_writedata
wire mm_interconnect_0_onchip_memory2_0_s1_chipselect; // mm_interconnect_0:onchip_memory2_0_s1_chipselect -> onchip_memory2_0:chipselect
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_readdata; // onchip_memory2_0:readdata -> mm_interconnect_0:onchip_memory2_0_s1_readdata
wire [13:0] mm_interconnect_0_onchip_memory2_0_s1_address; // mm_interconnect_0:onchip_memory2_0_s1_address -> onchip_memory2_0:address
wire [3:0] mm_interconnect_0_onchip_memory2_0_s1_byteenable; // mm_interconnect_0:onchip_memory2_0_s1_byteenable -> onchip_memory2_0:byteenable
wire mm_interconnect_0_onchip_memory2_0_s1_write; // mm_interconnect_0:onchip_memory2_0_s1_write -> onchip_memory2_0:write
wire [31:0] mm_interconnect_0_onchip_memory2_0_s1_writedata; // mm_interconnect_0:onchip_memory2_0_s1_writedata -> onchip_memory2_0:writedata
wire mm_interconnect_0_onchip_memory2_0_s1_clken; // mm_interconnect_0:onchip_memory2_0_s1_clken -> onchip_memory2_0:clken
wire mm_interconnect_0_pio_0_s1_chipselect; // mm_interconnect_0:pio_0_s1_chipselect -> pio_0:chipselect
wire [31:0] mm_interconnect_0_pio_0_s1_readdata; // pio_0:readdata -> mm_interconnect_0:pio_0_s1_readdata
wire [1:0] mm_interconnect_0_pio_0_s1_address; // mm_interconnect_0:pio_0_s1_address -> pio_0:address
wire mm_interconnect_0_pio_0_s1_write; // mm_interconnect_0:pio_0_s1_write -> pio_0:write_n
wire [31:0] mm_interconnect_0_pio_0_s1_writedata; // mm_interconnect_0:pio_0_s1_writedata -> pio_0:writedata
wire mm_interconnect_0_sdram_controller_0_s1_chipselect; // mm_interconnect_0:sdram_controller_0_s1_chipselect -> sdram_controller_0:az_cs
wire [15:0] mm_interconnect_0_sdram_controller_0_s1_readdata; // sdram_controller_0:za_data -> mm_interconnect_0:sdram_controller_0_s1_readdata
wire mm_interconnect_0_sdram_controller_0_s1_waitrequest; // sdram_controller_0:za_waitrequest -> mm_interconnect_0:sdram_controller_0_s1_waitrequest
wire [23:0] mm_interconnect_0_sdram_controller_0_s1_address; // mm_interconnect_0:sdram_controller_0_s1_address -> sdram_controller_0:az_addr
wire mm_interconnect_0_sdram_controller_0_s1_read; // mm_interconnect_0:sdram_controller_0_s1_read -> sdram_controller_0:az_rd_n
wire [1:0] mm_interconnect_0_sdram_controller_0_s1_byteenable; // mm_interconnect_0:sdram_controller_0_s1_byteenable -> sdram_controller_0:az_be_n
wire mm_interconnect_0_sdram_controller_0_s1_readdatavalid; // sdram_controller_0:za_valid -> mm_interconnect_0:sdram_controller_0_s1_readdatavalid
wire mm_interconnect_0_sdram_controller_0_s1_write; // mm_interconnect_0:sdram_controller_0_s1_write -> sdram_controller_0:az_wr_n
wire [15:0] mm_interconnect_0_sdram_controller_0_s1_writedata; // mm_interconnect_0:sdram_controller_0_s1_writedata -> sdram_controller_0:az_data
wire [31:0] nios2_gen2_0_irq_irq; // irq_mapper:sender_irq -> nios2_gen2_0:irq
wire irq_mapper_receiver0_irq; // irq_synchronizer:sender_irq -> irq_mapper:receiver0_irq
wire [0:0] irq_synchronizer_receiver_irq; // jtag_uart_0:av_irq -> irq_synchronizer:receiver_irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_synchronizer:receiver_reset, jtag_uart_0:rst_n, mm_interconnect_0:jtag_uart_0_reset_reset_bridge_in_reset_reset, sys_sdram_pll_0:ref_reset_reset]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [irq_mapper:reset, irq_synchronizer:sender_reset, mm_interconnect_0:nios2_gen2_0_reset_reset_bridge_in_reset_reset, nios2_gen2_0:reset_n, onchip_memory2_0:reset, pio_0:reset_n, rst_translator:in_reset, sdram_controller_0:reset_n]
wire rst_controller_001_reset_out_reset_req; // rst_controller_001:reset_req -> [nios2_gen2_0:reset_req, onchip_memory2_0:reset_req, rst_translator:reset_req_in]
niosii_jtag_uart_0 jtag_uart_0 (
.clk (clk_clk), // clk.clk
.rst_n (~rst_controller_reset_out_reset), // reset.reset_n
.av_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // avalon_jtag_slave.chipselect
.av_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // .address
.av_read_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read_n
.av_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.av_write_n (~mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write_n
.av_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.av_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.av_irq (irq_synchronizer_receiver_irq) // irq.irq
);
niosii_nios2_gen2_0 nios2_gen2_0 (
.clk (sys_sdram_pll_0_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.d_address (nios2_gen2_0_data_master_address), // data_master.address
.d_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.d_read (nios2_gen2_0_data_master_read), // .read
.d_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.d_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.d_write (nios2_gen2_0_data_master_write), // .write
.d_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.debug_mem_slave_debugaccess_to_roms (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.i_address (nios2_gen2_0_instruction_master_address), // instruction_master.address
.i_read (nios2_gen2_0_instruction_master_read), // .read
.i_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.i_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.irq (nios2_gen2_0_irq_irq), // irq.irq
.debug_reset_request (), // debug_reset_request.reset
.debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.dummy_ci_port () // custom_instruction_master.readra
);
niosii_onchip_memory2_0 onchip_memory2_0 (
.clk (sys_sdram_pll_0_sys_clk_clk), // clk1.clk
.address (mm_interconnect_0_onchip_memory2_0_s1_address), // s1.address
.clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.reset (rst_controller_001_reset_out_reset), // reset1.reset
.reset_req (rst_controller_001_reset_out_reset_req) // .reset_req
);
niosii_pio_0 pio_0 (
.clk (sys_sdram_pll_0_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.address (mm_interconnect_0_pio_0_s1_address), // s1.address
.write_n (~mm_interconnect_0_pio_0_s1_write), // .write_n
.writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.out_port (pio_0_external_connection_export) // external_connection.export
);
niosii_sdram_controller_0 sdram_controller_0 (
.clk (sys_sdram_pll_0_sys_clk_clk), // clk.clk
.reset_n (~rst_controller_001_reset_out_reset), // reset.reset_n
.az_addr (mm_interconnect_0_sdram_controller_0_s1_address), // s1.address
.az_be_n (~mm_interconnect_0_sdram_controller_0_s1_byteenable), // .byteenable_n
.az_cs (mm_interconnect_0_sdram_controller_0_s1_chipselect), // .chipselect
.az_data (mm_interconnect_0_sdram_controller_0_s1_writedata), // .writedata
.az_rd_n (~mm_interconnect_0_sdram_controller_0_s1_read), // .read_n
.az_wr_n (~mm_interconnect_0_sdram_controller_0_s1_write), // .write_n
.za_data (mm_interconnect_0_sdram_controller_0_s1_readdata), // .readdata
.za_valid (mm_interconnect_0_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.za_waitrequest (mm_interconnect_0_sdram_controller_0_s1_waitrequest), // .waitrequest
.zs_addr (sdram_addr), // wire.export
.zs_ba (sdram_ba), // .export
.zs_cas_n (sdram_cas_n), // .export
.zs_cke (sdram_cke), // .export
.zs_cs_n (sdram_cs_n), // .export
.zs_dq (sdram_dq), // .export
.zs_dqm (sdram_dqm), // .export
.zs_ras_n (sdram_ras_n), // .export
.zs_we_n (sdram_we_n) // .export
);
niosii_sys_sdram_pll_0 sys_sdram_pll_0 (
.ref_clk_clk (clk_clk), // ref_clk.clk
.ref_reset_reset (rst_controller_reset_out_reset), // ref_reset.reset
.sys_clk_clk (sys_sdram_pll_0_sys_clk_clk), // sys_clk.clk
.sdram_clk_clk (sdram_clk_clk), // sdram_clk.clk
.reset_source_reset () // reset_source.reset
);
niosii_mm_interconnect_0 mm_interconnect_0 (
.clk_0_clk_clk (clk_clk), // clk_0_clk.clk
.sys_sdram_pll_0_sys_clk_clk (sys_sdram_pll_0_sys_clk_clk), // sys_sdram_pll_0_sys_clk.clk
.jtag_uart_0_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // jtag_uart_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // nios2_gen2_0_reset_reset_bridge_in_reset.reset
.nios2_gen2_0_data_master_address (nios2_gen2_0_data_master_address), // nios2_gen2_0_data_master.address
.nios2_gen2_0_data_master_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.nios2_gen2_0_data_master_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.nios2_gen2_0_data_master_read (nios2_gen2_0_data_master_read), // .read
.nios2_gen2_0_data_master_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.nios2_gen2_0_data_master_write (nios2_gen2_0_data_master_write), // .write
.nios2_gen2_0_data_master_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.nios2_gen2_0_data_master_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.nios2_gen2_0_instruction_master_address (nios2_gen2_0_instruction_master_address), // nios2_gen2_0_instruction_master.address
.nios2_gen2_0_instruction_master_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.nios2_gen2_0_instruction_master_read (nios2_gen2_0_instruction_master_read), // .read
.nios2_gen2_0_instruction_master_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_address (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_address), // jtag_uart_0_avalon_jtag_slave.address
.jtag_uart_0_avalon_jtag_slave_write (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_write), // .write
.jtag_uart_0_avalon_jtag_slave_read (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_read), // .read
.jtag_uart_0_avalon_jtag_slave_readdata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_readdata), // .readdata
.jtag_uart_0_avalon_jtag_slave_writedata (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_writedata), // .writedata
.jtag_uart_0_avalon_jtag_slave_waitrequest (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_waitrequest), // .waitrequest
.jtag_uart_0_avalon_jtag_slave_chipselect (mm_interconnect_0_jtag_uart_0_avalon_jtag_slave_chipselect), // .chipselect
.nios2_gen2_0_debug_mem_slave_address (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_address), // nios2_gen2_0_debug_mem_slave.address
.nios2_gen2_0_debug_mem_slave_write (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_write), // .write
.nios2_gen2_0_debug_mem_slave_read (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_read), // .read
.nios2_gen2_0_debug_mem_slave_readdata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.nios2_gen2_0_debug_mem_slave_writedata (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.nios2_gen2_0_debug_mem_slave_byteenable (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.nios2_gen2_0_debug_mem_slave_waitrequest (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.nios2_gen2_0_debug_mem_slave_debugaccess (mm_interconnect_0_nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.onchip_memory2_0_s1_address (mm_interconnect_0_onchip_memory2_0_s1_address), // onchip_memory2_0_s1.address
.onchip_memory2_0_s1_write (mm_interconnect_0_onchip_memory2_0_s1_write), // .write
.onchip_memory2_0_s1_readdata (mm_interconnect_0_onchip_memory2_0_s1_readdata), // .readdata
.onchip_memory2_0_s1_writedata (mm_interconnect_0_onchip_memory2_0_s1_writedata), // .writedata
.onchip_memory2_0_s1_byteenable (mm_interconnect_0_onchip_memory2_0_s1_byteenable), // .byteenable
.onchip_memory2_0_s1_chipselect (mm_interconnect_0_onchip_memory2_0_s1_chipselect), // .chipselect
.onchip_memory2_0_s1_clken (mm_interconnect_0_onchip_memory2_0_s1_clken), // .clken
.pio_0_s1_address (mm_interconnect_0_pio_0_s1_address), // pio_0_s1.address
.pio_0_s1_write (mm_interconnect_0_pio_0_s1_write), // .write
.pio_0_s1_readdata (mm_interconnect_0_pio_0_s1_readdata), // .readdata
.pio_0_s1_writedata (mm_interconnect_0_pio_0_s1_writedata), // .writedata
.pio_0_s1_chipselect (mm_interconnect_0_pio_0_s1_chipselect), // .chipselect
.sdram_controller_0_s1_address (mm_interconnect_0_sdram_controller_0_s1_address), // sdram_controller_0_s1.address
.sdram_controller_0_s1_write (mm_interconnect_0_sdram_controller_0_s1_write), // .write
.sdram_controller_0_s1_read (mm_interconnect_0_sdram_controller_0_s1_read), // .read
.sdram_controller_0_s1_readdata (mm_interconnect_0_sdram_controller_0_s1_readdata), // .readdata
.sdram_controller_0_s1_writedata (mm_interconnect_0_sdram_controller_0_s1_writedata), // .writedata
.sdram_controller_0_s1_byteenable (mm_interconnect_0_sdram_controller_0_s1_byteenable), // .byteenable
.sdram_controller_0_s1_readdatavalid (mm_interconnect_0_sdram_controller_0_s1_readdatavalid), // .readdatavalid
.sdram_controller_0_s1_waitrequest (mm_interconnect_0_sdram_controller_0_s1_waitrequest), // .waitrequest
.sdram_controller_0_s1_chipselect (mm_interconnect_0_sdram_controller_0_s1_chipselect) // .chipselect
);
niosii_irq_mapper irq_mapper (
.clk (sys_sdram_pll_0_sys_clk_clk), // clk.clk
.reset (rst_controller_001_reset_out_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (nios2_gen2_0_irq_irq) // sender.irq
);
altera_irq_clock_crosser #(
.IRQ_WIDTH (1)
) irq_synchronizer (
.receiver_clk (clk_clk), // receiver_clk.clk
.sender_clk (sys_sdram_pll_0_sys_clk_clk), // sender_clk.clk
.receiver_reset (rst_controller_reset_out_reset), // receiver_clk_reset.reset
.sender_reset (rst_controller_001_reset_out_reset), // sender_clk_reset.reset
.receiver_irq (irq_synchronizer_receiver_irq), // receiver.irq
.sender_irq (irq_mapper_receiver0_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (sys_sdram_pll_0_sys_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_001_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_2_V
`define SKY130_FD_SC_LP__A221O_2_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Verilog wrapper for a221o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_2 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a221o_2 (
X ,
A1,
A2,
B1,
B2,
C1
);
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a221o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_2_V
|
`timescale 1 ns / 1 ps
module axis_measure_pulse #
(
parameter integer AXIS_TDATA_WIDTH = 16,
parameter integer CNTR_WIDTH = 16,
parameter integer PULSE_WIDTH = 16,
parameter integer BRAM_DATA_WIDTH = 16,
parameter integer BRAM_ADDR_WIDTH = 16
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire [PULSE_WIDTH*4+95:0] cfg_data,
output wire overload,
output wire [2:0] case_id,
output wire [31:0] sts_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
input wire m_axis_tready,
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid,
output wire m_axis_tlast,
// BRAM port
output wire bram_porta_clk,
output wire bram_porta_rst,
output wire [BRAM_ADDR_WIDTH-1:0] bram_porta_addr,
input wire [BRAM_DATA_WIDTH-1:0] bram_porta_rddata
);
wire [PULSE_WIDTH-1:0] total_sweeps,ramp,width,offset_width;
wire [BRAM_ADDR_WIDTH-1:0] waveform_length, pulse_length;
wire signed [31:0] threshold, magnitude;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next, int_cntr_sweeps_reg, int_cntr_sweeps_next;
reg [2:0] int_case_reg, int_case_next;
reg signed [31:0] pulse,pulse_next,offset,offset_next,result,result_next;
reg [BRAM_ADDR_WIDTH-1:0] wfrm_start,wfrm_start_next,wfrm_point,wfrm_point_next;
reg [BRAM_ADDR_WIDTH-1:0] int_addr, int_addr_next;
reg int_enbl_reg, int_enbl_next;
reg int_last_pulse_reg, int_last_pulse_next;
wire int_comp_wire, int_tlast_wire, wfrm_point_comp;
// default cfg_data: total_sweeps[16]:ramp[16]:width[16]:unused[16]:threshold[32]:waveform_length[32]:pulse_length[32]
assign total_sweeps = cfg_data[PULSE_WIDTH-1:0];
assign ramp = cfg_data[PULSE_WIDTH*2-1:PULSE_WIDTH];
assign width = cfg_data[PULSE_WIDTH*3-1:PULSE_WIDTH*2];
assign offset_width = width[PULSE_WIDTH-2:1];
assign threshold = $signed(cfg_data[PULSE_WIDTH*4+31:PULSE_WIDTH*4]);
assign waveform_length = cfg_data[PULSE_WIDTH*4+BRAM_ADDR_WIDTH+31:PULSE_WIDTH*4+32];
assign pulse_length = cfg_data[PULSE_WIDTH*4+BRAM_ADDR_WIDTH+63:PULSE_WIDTH*4+64];
assign magnitude = $signed(pulse) - $signed(offset);
always @(posedge aclk)
begin
if(~aresetn)
begin
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_cntr_sweeps_reg <= {(CNTR_WIDTH){1'b0}};
int_case_reg <= 3'd0;
pulse <= 32'd0;
offset <= 32'd0;
result <= 32'd0;
wfrm_start <= {(BRAM_ADDR_WIDTH){1'b0}};
wfrm_point <= {(BRAM_ADDR_WIDTH){1'b0}};
int_addr <= {(BRAM_ADDR_WIDTH){1'b0}};
int_enbl_reg <= 1'b0;
int_last_pulse_reg <= 1'b0;
end
else
begin
int_cntr_reg <= int_cntr_next;
int_cntr_sweeps_reg <= int_cntr_sweeps_next;
int_case_reg <= int_case_next;
pulse <= pulse_next;
offset <= offset_next;
result <= result_next;
wfrm_start <= wfrm_start_next;
wfrm_point <= wfrm_point_next;
int_addr <= int_addr_next;
int_enbl_reg <= int_enbl_next;
int_last_pulse_reg <= int_last_pulse_next;
end
end
assign int_comp_wire = wfrm_start < waveform_length;
assign int_tlast_wire = ~int_comp_wire;
assign wfrm_point_comp = wfrm_point < pulse_length;
always @*
begin
int_cntr_next = int_cntr_reg;
int_cntr_sweeps_next = int_cntr_sweeps_reg;
int_case_next = int_case_reg;
offset_next=offset;
result_next=result;
int_addr_next = int_addr;
pulse_next = pulse;
wfrm_start_next = wfrm_start;
wfrm_point_next = wfrm_point;
int_enbl_next = int_enbl_reg;
int_last_pulse_next = int_last_pulse_reg;
if(int_case_reg < 3'd5)
begin
if(wfrm_start < ( waveform_length - pulse_length) )
int_last_pulse_next = 1'b0;
else
int_last_pulse_next = 1'b1;
if(~int_enbl_reg & int_comp_wire)
int_enbl_next = 1'b1;
if(m_axis_tready & int_enbl_reg & wfrm_point_comp)
begin
wfrm_point_next = wfrm_point + 1'b1;
int_addr_next = wfrm_start + wfrm_point;
end
if(m_axis_tready & int_enbl_reg & ~wfrm_point_comp)
begin
wfrm_point_next = 32'b0;
int_addr_next = wfrm_start + wfrm_point;
end
if(s_axis_tvalid)
begin
case(int_case_reg)
// measure signal offset front
0:
begin
if(int_cntr_reg < offset_width )
begin
offset_next = $signed(offset) + $signed(s_axis_tdata);
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// skip ramp up
1:
begin
if(int_cntr_reg < ramp )
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// measure pulse
2:
begin
if(int_cntr_reg < width )
begin
pulse_next = $signed(pulse) + $signed(s_axis_tdata);
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// skip ramp down
3:
begin
if(int_cntr_reg < ramp )
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = int_case_reg + 3'd1;
end
end
// post offset
4:
begin
if(int_cntr_reg < offset_width )
begin
offset_next = $signed(offset) + $signed(s_axis_tdata);
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = 3'd0;
result_next = magnitude; // assume 50% duty cycle
offset_next = 32'd0;
pulse_next = 32'd0;
wfrm_point_next = {(BRAM_ADDR_WIDTH){1'b0}};
int_addr_next = wfrm_start + wfrm_point;
if((magnitude < threshold) & ~int_last_pulse_reg )
begin
wfrm_start_next = wfrm_start + pulse_length + 1;
end
else
begin
wfrm_start_next = {(BRAM_ADDR_WIDTH){1'b0}};
if(int_cntr_sweeps_reg < total_sweeps )
begin
int_cntr_sweeps_next = int_cntr_sweeps_reg + 1'b1;
end
else
begin
int_enbl_next = 1'b0;
wfrm_point_next = {(BRAM_ADDR_WIDTH){1'b0}};
int_case_next = 3'd5;
end
end
end
end
5:
begin
int_enbl_next = 1'b0;
wfrm_start_next = {(BRAM_ADDR_WIDTH){1'b0}};
wfrm_point_next = {(BRAM_ADDR_WIDTH){1'b0}};
end
endcase
end
end
end
assign overload = result < threshold;
assign s_axis_tready = 1'b1;
assign m_axis_tdata = bram_porta_rddata;
assign m_axis_tvalid = int_enbl_reg;
assign m_axis_tlast = int_enbl_reg & int_tlast_wire;
// assign sts_data = result ;
assign sts_data = {result[31:8],5'b0,int_case_reg};
assign bram_porta_clk = aclk;
assign bram_porta_rst = ~aresetn;
assign bram_porta_addr = m_axis_tready & int_enbl_reg ? int_addr_next : int_addr;
assign case_id = int_case_reg;
// assign bram_porta_addr = int_addr;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFBBN_BEHAVIORAL_V
`define SKY130_FD_SC_LP__DFBBN_BEHAVIORAL_V
/**
* dfbbn: Delay flop, inverted set, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_lp__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_lp__dfbbn (
Q ,
Q_N ,
D ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire CLK_N_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
not not2 (CLK , CLK_N_delayed );
sky130_fd_sc_lp__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFBBN_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NAND3B_PP_SYMBOL_V
`define SKY130_FD_SC_HDLL__NAND3B_PP_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__nand3b (
//# {{data|Data Signals}}
input A_N ,
input B ,
input C ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NAND3B_PP_SYMBOL_V
|
//
// bsg_fifo_1r1w_pseudo_large
//
// MBT 3/11/15
//
// This fifo looks like a 1R1W fifo but actually is implemented
// with a 1RW FIFO for the bulk of its storage, and has a
// small 1R1W FIFO to help decouple reads and writes that may
// conflict. This FIFO is useful for cases where reads and writes
// each individually have a duty cycle of 50% or less.
//
// In 180 nm, the area of a 128x70 1R1W is about 1.75 the equivalent 1RW.
// The 2-element little fifo is about 0.25 the above 1RW. So the net
// savings is 1.25 versus 1.75; but that assumes the 1R1W has no overhead
// when in reality, it would probably have a 2-el fifo as well (e.g. 2.00).
// So this module does actually save area.
//
// For example, an element is written into the
// FIFO every other cycle, and an element is read from the FIFO
// every other cycle.
//
// _______________________________
// \ __________ \__|\ ____________
// \___/ 1RW FIFO \___| |__/ 1R1W FIFO \______
// \___big____/ | | \___little___/
// |/
//
// Data is inserted directly into the little fifo until
// that fifo is full. Then it is stored in
// the 1 port ram. When data is not enqued into the big fifo,
// and there is sufficient gauranteed space in the little fifo
// then data is transferred from the big fifo to the little fifo.
//
// Although both bsg_fifo_1r1w_pseudo_large and bsg_fifo_1r1w_large
// use 1RW rams, the pseudo fifo will be more area efficient for
// smaller FIFO sizes, because 1) it does not read as much data at a time
// and thus does not require as many sense amps (see your RAM compiler)
// and 2) the little FIFO is smaller than the associated "little fifo"
// serial-to-parallel registers of the 1r1w_large.
//
// * Enque Guarantees:
//
// In order to maintain the appearance of the 1R1W FIFO, this
// FIFO will always accept up to els_p data elements without saying
// that it is full. (These elements can be sent back-to-back, but this
// may starve out the little FIFO since it will not be able to
// access the 1RW FIFO.)
//
// * Deque non-guarantees and guarantees:
//
// As long as the duty cycle is <= 50 percent in any window of the input data stream
// that is twice the size of the parameter max_conflict_run_p, the FIFO will report
// that data is available when there is data available. If the user violates this
// parameter, the FIFO may be busy receiving data and potentially could report not
// having data when there is in fact data inside the FIFO.
//
// As long as you check the v_o signal, you will not lose data; but you may have periods
// where are unable to read because writes are occupying the bandwidth.
//
// On the other hand, if you have code that counts how many elements went into the FIFO,
// and then expects to deque that number of elements without checking the v_o bit, that
// code could fail.)
//
// (Another example: if the incoming data comes in bursts of N words, followed by
// a pause of at least N cycles, and the receiver reads data at most one word
// every other two cycles; then the FIFO will never report empty if it has data.)
//
// Parameters:
//
// max_conflict_run_p (N):
//
// First, the maximum # of sequential writes, N, that the FIFO can sustain before dropping
// below an average throughput of 1/2 because of structural hazards on the 1RW ram.
// This conflict run property is useful, for example, if we know that traffic comes in bursts
// of consecutive packets.
// Second, how many elements must be queued up before the FIFO starts
// using the large 1RW FIFO, which will likely consume a lot more power,
// after how many elements the effective throughput of the FIFO drops to 1/2.
// early_yumi_p: this parameter says whether the yumi signal comes in earlier
// which allows us to reduce latency between deque and the next element
// being transferred from the internal ram to the output, which in turns
// reduces how many FIFO elements are required by the setting of max_conflict_run_p
// Without early_yumi, this latency is
// 2+n cycles (yumi->BF deq->LF enq) where n is the number BF enques. early yumi
// changes this to (yumi/BF deq -> LF enq) or 1+n cycles.
// early_yumi_p can be used if the yumi signal is known early, and reduces the
// required little fifo size by 1 element to 1+n.
// [ Assertion to be formally proved: the FIFO size required for a conflict run size of n is 2+n.
// (yumi->BF deq->LF enq)+conflicts. So, your basic small FIFO should be at least 3 elements for
// enque patterns that do every-other cycle with an unknown relationship to the output, which
// is also every other cycle. The early yumi flag changes this parameter to
// (yumi/BF deq -> LF enq) +conflicts = 1+n = 2 elements ]
//
// (early_yumi_p allows the fifo to support 1/2 rate inputs and outputs with conflict runs of 1
// and only a twofer.)
// TODO: make max_conflict_run_p a parameter (and correspondingly parameterize little FIFO size
// and update control logic)
// add assertions that detect violation of the max conflict run
//
`include "bsg_defines.v"
module bsg_fifo_1r1w_pseudo_large #(parameter `BSG_INV_PARAM(width_p )
, parameter `BSG_INV_PARAM(els_p )
// Future extensions: need to add max_conflict_run_p;
// currently it is "1" and only if early_yumi_p = 1.
// to implement this, we need to parameterize the fifo
// to be of size (max_conflict_run_p+2-early_yumi_p)
// if yumi is on critical path; you can change this to 0.
// but to maintain performance, we would need to
// implement the max_conflict_run_p parameter.
, parameter early_yumi_p = 1
, parameter verbose_p = 0
)
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input v_i
, output ready_o
, output v_o
, output [width_p-1:0] data_o
, input yumi_i
);
wire big_full_lo, big_empty_lo;
wire [width_p-1:0] big_data_lo;
logic big_enq, big_deq, big_deq_r;
wire little_ready_lo, little_will_have_space;
logic little_valid, big_valid;
if (early_yumi_p)
assign little_will_have_space = little_ready_lo | yumi_i;
else
assign little_will_have_space = little_ready_lo;
// whether we dequed something on the last cycle
always_ff @(posedge clk_i)
if (reset_i)
big_deq_r <= 1'b0;
else
big_deq_r <= big_deq;
// if the big fifo is not full, then we can take more data
wire ready_o_int = ~big_full_lo;
assign ready_o = ready_o_int;
// ***** DEBUG ******
// for debugging; whether we are bypassing the big fifo
// synopsys translate_off
wire bypass_mode = v_i & ~ big_enq;
// sum up all of the storage in this fifo
wire [31:0] num_elements_debug = big1p.num_elements_debug + big_deq_r + little2p.num_elements_debug;
logic big_enq_r;
always_ff @(posedge clk_i)
if (reset_i)
big_enq_r <= 0;
else
big_enq_r <= big_enq_r | big_enq;
always_ff @(negedge clk_i)
if (verbose_p & (reset_i === 0) & (~big_enq_r & big_enq))
$display("## %L: overflowing into big fifo for the first time (%m)");
// synopsys translate_on
//
// ***** END DEBUG ******
always_comb
begin
// if we fetch an element last cycle, we need to enque
// it into the little fifo
if (big_deq_r)
begin
// we dequed last cycle, so there must be room
// in both big and little fifos
little_valid = 1'b1;
big_enq = v_i;
// if there is data in big fifo
// and we are not enqueing to the big fifo
// and the little fifo is empty
// we can grab another word
// we do not test for the yumi signal here
// because an empty little fifo cannot have a yumi.
big_deq = (~big_empty_lo & ~big_enq & ~v_o);
end
else
begin
// clean through bypass mode; skip
// big fifo and go to little fifo
if (big_empty_lo)
begin
little_valid = v_i & little_will_have_space;
big_enq = v_i & ~little_will_have_space;
big_deq = 1'b0; // big FIFO is empty, can't deque
end
else
// there is data in the big fifo
// but we did not fetch from it
// last cycle.
// we cannot enque anything into
// the little fifo this cycle.
begin
little_valid = 1'b0;
big_enq = v_i & ~big_full_lo;
big_deq = ~big_enq & little_will_have_space;
end
end // else: !if(big_deq_r)
big_valid = big_enq | big_deq;
end
// if we dequed from the big queue last cycle
// then we enque it into the little fifo
wire [width_p-1:0] little_data = big_deq_r ? big_data_lo : data_i;
bsg_fifo_1rw_large #(.width_p(width_p)
,.els_p(els_p)
,.verbose_p(verbose_p)
) big1p
(.clk_i (clk_i )
,.reset_i (reset_i )
,.data_i (data_i )
,.v_i (big_valid)
,.enq_not_deq_i(big_enq)
,.full_o (big_full_lo )
,.empty_o (big_empty_lo)
,.data_o (big_data_lo )
);
bsg_two_fifo #(.width_p(width_p)
,. verbose_p(verbose_p)
,. allow_enq_deq_on_full_p(early_yumi_p)) little2p
(.clk_i (clk_i)
,.reset_i(reset_i)
,.ready_o(little_ready_lo)
,.data_i (little_data)
,.v_i (little_valid)
,.v_o (v_o)
,.data_o (data_o)
,.yumi_i (yumi_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_fifo_1r1w_pseudo_large)
|
`include "../src/include/DISCHARGE_ctl.v"
module test_discharge # (
parameter integer C_DEFAULT_VALUE = 0,
parameter integer C_PWM_CNT_WIDTH = 16,
parameter integer C_FRACTIONAL_WIDTH = 16,
parameter integer C_NUMBER_WIDTH = 32
) (
);
reg clk;
reg resetn;
wire def_val ;
wire exe_done;
reg [C_PWM_CNT_WIDTH-1:0] denominator; // >= 3
reg [C_PWM_CNT_WIDTH-1:0] numerator0 ;
reg [C_PWM_CNT_WIDTH-1:0] numerator1 ;
reg [C_NUMBER_WIDTH-1:0] number0 ;
reg [C_NUMBER_WIDTH-1:0] number1 ;
reg [C_PWM_CNT_WIDTH+C_FRACTIONAL_WIDTH-1:0] inc0;
wire drive;
DISCHARGE_ctl # (
.C_DEFAULT_VALUE(C_DEFAULT_VALUE),
.C_PWM_CNT_WIDTH(C_PWM_CNT_WIDTH),
.C_FRACTIONAL_WIDTH(C_FRACTIONAL_WIDTH),
.C_NUMBER_WIDTH(C_NUMBER_WIDTH)
) discharge_ctl_inst (
.clk(clk),
.resetn(resetn),
.def_val(def_val),
.exe_done(exe_done),
.denominator(denominator),
.numerator0 (numerator0),
.numerator1 (numerator1),
.number0 (number0),
.number1 (number1),
.inc0 (inc0),
.drive (drive)
);
initial begin
clk <= 1'b1;
forever #2.5 clk <= ~clk;
end
initial begin
resetn <= 1'b0;
repeat (5) #5 resetn <= 1'b0;
forever #5 resetn <= 1'b1;
end
always @ (posedge clk) begin
if (resetn == 1'b0) begin
denominator <= 23;
numerator0 <= 19;
numerator1 <= 7;
number0 <= 5;
number1 <= 9;
inc0 <= (19 - 7) * 65536 / 9;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__BUFBUF_16_V
`define SKY130_FD_SC_HDLL__BUFBUF_16_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 16 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__bufbuf_16 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__bufbuf_16 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__BUFBUF_16_V
|
`timescale 1ns / 1ps
module sim_menu;
// Inputs
reg clk;
reg reset;
reg boton_arriba;
reg boton_abajo;
reg boton_izq;
reg boton_der;
reg boton_elige;
// Outputs
wire text_red;
wire text_green;
wire text_blue;
wire [9:0] char_scale;
wire es_mayuscula;
wire nuevo;
wire guardar;
wire cerrar;
wire [2:0] where_fila;
wire [2:0] where_columna;
// Instantiate the Unit Under Test (UUT)
Controlador_Menu_Editor uut (
.clk(clk),
.reset(reset),
.boton_arriba(boton_arriba),
.boton_abajo(boton_abajo),
.boton_izq(boton_izq),
.boton_der(boton_der),
.boton_elige(boton_elige),
.text_red(text_red),
.text_green(text_green),
.text_blue(text_blue),
.char_scale(char_scale),
.es_mayuscula(es_mayuscula),
.nuevo(nuevo),
.guardar(guardar),
.cerrar(cerrar),
.where_fila(where_fila),
.where_columna(where_columna)
);
always
#10 clk = ~clk;
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 1;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 1;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 1;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
#10;
boton_arriba = 0;
boton_abajo = 0;
boton_izq = 0;
boton_der = 0;
boton_elige = 0;
end
endmodule
|
/*
_______________________________________________________________________________
Copyright (c) 2012 TU Dresden, Chair for Embedded Systems
(http://www.mr.inf.tu-dresden.de) All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this software
must display the following acknowledgement: "This product includes
software developed by the TU Dresden Chair for Embedded Systems and
its contributors."
4. Neither the name of the TU Dresden Chair for Embedded Systems nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY TU DRESDEN CHAIR FOR EMBEDDED SYSTEMS AND
CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING,
BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
_______________________________________________________________________________
*/
//////////////////////////////////////////////////////////////////////////////////
// Create Date: 17:07:11 09/20/2011
// Module Name: uart_light_tx_dp
//////////////////////////////////////////////////////////////////////////////////
module uart_light_tx_dp
#(
parameter WORD_SIZE = 8,
parameter BC_SIZE = 3, //2^BC_SIZE >= WORD_SIZE
parameter FIFO_ADDR_BITS = 5
)(
input wire reset,
input wire clk_peri,
input wire clk_tx,
output wire tx,
//Interfaces zum SPMC
input wire [WORD_SIZE-1:0] word_tx,
//Interfaces zum Controller-Module, welche durch clk_tx getrieben werden
input wire transmit,
input wire clear,
input wire fifo_read_enable,
output wire frame_done,
//Interfaces zum Controller-Module, welche durch clk_peri getrieben werden
input wire fifo_write_enable,
output wire fifo_full,
output wire fifo_empty
);
wire[WORD_SIZE-1:0] fifo_out;
reg [WORD_SIZE:0] shfreg_tx;
reg [BC_SIZE:0] bit_count;
assign tx = shfreg_tx[0];
assign frame_done = (bit_count == WORD_SIZE);
always @(posedge clk_tx, posedge reset) begin
if(reset) begin
shfreg_tx <= {(WORD_SIZE+1){1'b1}};
bit_count <= {(BC_SIZE+1){1'b0}};
end
else begin
if(fifo_read_enable)
shfreg_tx <= {fifo_out,1'b0};
else if(transmit) begin
shfreg_tx <= {1'b1, shfreg_tx[WORD_SIZE:1]};
bit_count <= bit_count + 1'b1;
end
else if(clear) begin
shfreg_tx <= {(WORD_SIZE+1){1'b1}};
bit_count <= {(BC_SIZE+1){1'b0}};
end
end
end
yaf #
(
.DSIZE (WORD_SIZE),
.ASIZE (FIFO_ADDR_BITS)
)
yaf_tx0
(
.rdata( fifo_out ), //Sendedaten zum Tranceiver
.wfull( ), //Empfangs-FIFO voll mit wclk synchronisiert
.rfull( ), //Empfangs-FIFO voll mit rclk synchronisiert
.rwfull( fifo_full ), //Sende-FIFO voll = rfull | wfull
.wempty( ), //Empfangs-FIFO leer mit wclk synchronisiert
.rempty( ), //Empfangs-FIFO leer mit rclk synchronisiert
.rwempty( fifo_empty ), //Sende-FIFO leer = rempty & wempty
.fill( ), //Output wird nicht verwendet.
.wdata( word_tx ), //Sendedatem vom MC
.winc( fifo_write_enable ), //MC schreibt Daten solange write=1 ist.
.wclk( clk_peri ),
.wrst_n( ~reset ),
.rinc( fifo_read_enable ), //Transceiver liest Daten
.rclk( clk_tx ),
.rrst_n ( ~reset ),
.rptr_upd( 1'b0 ),
.rptr_rest( 1'b0 ),
.wptr_upd( 1'b0 ),
.wptr_rest( 1'b0 )
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_vuad_dpm.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_vuad_dpm
(/*AUTOARG*/
// Outputs
so, bistordiag_ua_data, bistordiag_vd_data, vuad_dp_diag_data_c7,
vuad_syndrome_c9, parity_c4,
// Inputs
rclk, si, se, diag_rd_ua_out, diag_rd_vd_out, arbctl_acc_ua_c2,
valid_rd_parity_c2, dirty_rd_parity_c2, used_rd_parity_c2,
alloc_rd_parity_c2, arbdata_wr_data_c2, bist_vuad_data_in,
sel_diag1_data_wr_c3, sel_diag0_data_wr_c3
) ;
input rclk;
input si, se;
output so;
output [25:0] bistordiag_ua_data; // Left
output [25:0] bistordiag_vd_data; // Right
input [25:0] diag_rd_ua_out ; // Left
input [25:0] diag_rd_vd_out ; // Right
input arbctl_acc_ua_c2; // TOP
output [25:0] vuad_dp_diag_data_c7;
output [3:0] vuad_syndrome_c9; // Bottom
output [3:0] parity_c4; // Top
input valid_rd_parity_c2; // Right
input dirty_rd_parity_c2; // Right
input used_rd_parity_c2; // Left
input alloc_rd_parity_c2; // Left
input [25:0] arbdata_wr_data_c2; // Top
input [7:0] bist_vuad_data_in; // Top
input sel_diag1_data_wr_c3; // Top
input sel_diag0_data_wr_c3; // Top
wire [25:0] diag_out_c2;
wire [25:0] diag_out_c3;
wire [25:0] diag_out_c4;
wire [25:0] diag_out_c5;
wire [25:0] diag_out_c6;
wire [25:0] diag_out_c7;
wire [25:0] diag_out_c8;
wire [3:0] parity_c3;
wire [3:0] parity_c5;
wire [3:0] parity_c6;
wire [3:0] vuad_syndrome_c7;
wire [3:0] vuad_syndrome_c8;
wire [25:0] bist_data_c3;
wire [25:0] arbdata_wr_data_c3;
wire [25:0] bistordiag_ua_data_in, bistordiag_vd_data_in;
//////////////////////////////
// This is a 32 bit datapath
//////////////////////////////
//////////////////////////////
// Use the 26 lfetmost dp pitches for this
//////////////////////////////
// Use a 2-1 mux flop to reduce the setup on arbctl_acc_ua_c2
mux2ds #(26) mux_diag_out_c2
( .dout (diag_out_c2[25:0]),
.in0(diag_rd_ua_out[25:0]),
.in1(diag_rd_vd_out[25:0]),
.sel0(arbctl_acc_ua_c2),
.sel1(~arbctl_acc_ua_c2)
);
dff_s #(26) ff_diag_out_c3
(.q (diag_out_c3[25:0]),
.din (diag_out_c2[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(26) ff_diag_out_c4
(.q (diag_out_c4[25:0]),
.din (diag_out_c3[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(26) ff_diag_out_c5
(.q (diag_out_c5[25:0]),
.din (diag_out_c4[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(26) ff_diag_out_c6
(.q (diag_out_c6[25:0]),
.din (diag_out_c5[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(26) ff_diag_out_c7
(.q (diag_out_c7[25:0]),
.din (diag_out_c6[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(26) ff_diag_out_c8
(.q (diag_out_c8[25:0]),
.din (diag_out_c7[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// eventhough the suffix says c7 this is actually c8 data
// sent to deccdp. THis data gets muxed with other diagnostic
// data and inval data in C8 and is transmitted to the
// requesting sparc in the next cycle.
assign vuad_dp_diag_data_c7 = diag_out_c8 ;
//////////////////////////////
// Use the 4 rightmost dp pitches for this
//////////////////////////////
dff_s #(4) ff_parity_c3
(.q (parity_c3[3:0]),
.din ({valid_rd_parity_c2, dirty_rd_parity_c2,
used_rd_parity_c2, alloc_rd_parity_c2}),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_parity_c4
(.q (parity_c4[3:0]),
.din (parity_c3[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_parity_c5
(.q (parity_c5[3:0]),
.din (parity_c4[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_parity_c6
(.q (parity_c6[3:0]),
.din (parity_c5[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_vuad_syndrome_c7
(.q (vuad_syndrome_c7[3:0]),
.din (parity_c6[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_vuad_syndrome_c8
(.q (vuad_syndrome_c8[3:0]),
.din (vuad_syndrome_c7[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
dff_s #(4) ff_vuad_syndrome_c9
(.q (vuad_syndrome_c9[3:0]),
.din (vuad_syndrome_c8[3:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// Bist data flops
// 26 bits from 8 bits.
assign bist_data_c3 = { bist_vuad_data_in[1:0],
{3{bist_vuad_data_in[7:0]}}};
//Diagnostic WR data mux
dff_s #(26) ff_arbdata_wr_data_c3
(.q (arbdata_wr_data_c3[25:0]),
.din (arbdata_wr_data_c2[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// Use a 2-1 mux flop for bistordiag_ua_data
mux2ds #(26) mux_lhs_bistordiag_data
(.dout (bistordiag_ua_data_in[25:0]),
.in0 ({arbdata_wr_data_c3[25], arbdata_wr_data_c3[23:12],
arbdata_wr_data_c3[24], arbdata_wr_data_c3[11:0]}),
.sel0 (sel_diag1_data_wr_c3),
.in1 ({bist_data_c3[25], bist_data_c3[23:12],
bist_data_c3[24], bist_data_c3[11:0]}),
.sel1 (~sel_diag1_data_wr_c3)
) ;
dff_s #(26) ff_bistordiag_ua_data
(.q (bistordiag_ua_data[25:0]),
.din (bistordiag_ua_data_in[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
// Use a 2-1 mux flop for bistordiag_vd_data
mux2ds #(26) mux_rhs_bistordiag_data
(.dout (bistordiag_vd_data_in[25:0]),
.in0 ({arbdata_wr_data_c3[25], arbdata_wr_data_c3[23:12],
arbdata_wr_data_c3[24], arbdata_wr_data_c3[11:0]}),
.sel0 (sel_diag0_data_wr_c3),
.in1 ({bist_data_c3[25], bist_data_c3[23:12],
bist_data_c3[24], bist_data_c3[11:0]}),
.sel1 (~sel_diag0_data_wr_c3)
) ;
dff_s #(26) ff_bistordiag_vd_data
(.q (bistordiag_vd_data[25:0]),
.din (bistordiag_vd_data_in[25:0]),
.clk (rclk),
.se(se), .si (), .so ()
) ;
endmodule
|
// generated by gen_VerilogEHR.py using VerilogEHR.mako
// Copyright (c) 2019 Massachusetts Institute of Technology
// Permission is hereby granted, free of charge, to any person
// obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without
// restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies
// of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be
// included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
// SOFTWARE.
module EHRU_5 (
CLK,
read_0,
write_0,
EN_write_0,
read_1,
write_1,
EN_write_1,
read_2,
write_2,
EN_write_2,
read_3,
write_3,
EN_write_3,
read_4,
write_4,
EN_write_4
);
parameter DATA_SZ = 1;
parameter RESET_VAL = 0;
input CLK;
output [DATA_SZ-1:0] read_0;
input [DATA_SZ-1:0] write_0;
input EN_write_0;
output [DATA_SZ-1:0] read_1;
input [DATA_SZ-1:0] write_1;
input EN_write_1;
output [DATA_SZ-1:0] read_2;
input [DATA_SZ-1:0] write_2;
input EN_write_2;
output [DATA_SZ-1:0] read_3;
input [DATA_SZ-1:0] write_3;
input EN_write_3;
output [DATA_SZ-1:0] read_4;
input [DATA_SZ-1:0] write_4;
input EN_write_4;
reg [DATA_SZ-1:0] r;
wire [DATA_SZ-1:0] wire_0;
wire [DATA_SZ-1:0] wire_1;
wire [DATA_SZ-1:0] wire_2;
wire [DATA_SZ-1:0] wire_3;
wire [DATA_SZ-1:0] wire_4;
wire [DATA_SZ-1:0] wire_5;
assign wire_0 = r;
assign wire_1 = EN_write_0 ? write_0 : wire_0;
assign wire_2 = EN_write_1 ? write_1 : wire_1;
assign wire_3 = EN_write_2 ? write_2 : wire_2;
assign wire_4 = EN_write_3 ? write_3 : wire_3;
assign wire_5 = EN_write_4 ? write_4 : wire_4;
assign read_0 = wire_0;
assign read_1 = wire_1;
assign read_2 = wire_2;
assign read_3 = wire_3;
assign read_4 = wire_4;
always @(posedge CLK) begin
r <= wire_5;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_gpio(
input clock,
input reset,
output io_interrupts_0_0,
output io_interrupts_0_1,
output io_interrupts_0_2,
output io_interrupts_0_3,
output io_interrupts_0_4,
output io_interrupts_0_5,
output io_interrupts_0_6,
output io_interrupts_0_7,
output io_interrupts_0_8,
output io_interrupts_0_9,
output io_interrupts_0_10,
output io_interrupts_0_11,
output io_interrupts_0_12,
output io_interrupts_0_13,
output io_interrupts_0_14,
output io_interrupts_0_15,
output io_interrupts_0_16,
output io_interrupts_0_17,
output io_interrupts_0_18,
output io_interrupts_0_19,
output io_interrupts_0_20,
output io_interrupts_0_21,
output io_interrupts_0_22,
output io_interrupts_0_23,
output io_interrupts_0_24,
output io_interrupts_0_25,
output io_interrupts_0_26,
output io_interrupts_0_27,
output io_interrupts_0_28,
output io_interrupts_0_29,
output io_interrupts_0_30,
output io_interrupts_0_31,
output io_in_0_a_ready,
input io_in_0_a_valid,
input [2:0] io_in_0_a_bits_opcode,
input [2:0] io_in_0_a_bits_param,
input [2:0] io_in_0_a_bits_size,
input [4:0] io_in_0_a_bits_source,
input [28:0] io_in_0_a_bits_address,
input [3:0] io_in_0_a_bits_mask,
input [31:0] io_in_0_a_bits_data,
input io_in_0_b_ready,
output io_in_0_b_valid,
output [2:0] io_in_0_b_bits_opcode,
output [1:0] io_in_0_b_bits_param,
output [2:0] io_in_0_b_bits_size,
output [4:0] io_in_0_b_bits_source,
output [28:0] io_in_0_b_bits_address,
output [3:0] io_in_0_b_bits_mask,
output [31:0] io_in_0_b_bits_data,
output io_in_0_c_ready,
input io_in_0_c_valid,
input [2:0] io_in_0_c_bits_opcode,
input [2:0] io_in_0_c_bits_param,
input [2:0] io_in_0_c_bits_size,
input [4:0] io_in_0_c_bits_source,
input [28:0] io_in_0_c_bits_address,
input [31:0] io_in_0_c_bits_data,
input io_in_0_c_bits_error,
input io_in_0_d_ready,
output io_in_0_d_valid,
output [2:0] io_in_0_d_bits_opcode,
output [1:0] io_in_0_d_bits_param,
output [2:0] io_in_0_d_bits_size,
output [4:0] io_in_0_d_bits_source,
output io_in_0_d_bits_sink,
output [1:0] io_in_0_d_bits_addr_lo,
output [31:0] io_in_0_d_bits_data,
output io_in_0_d_bits_error,
output io_in_0_e_ready,
input io_in_0_e_valid,
input io_in_0_e_bits_sink,
input io_port_pins_0_i_ival,
output io_port_pins_0_o_oval,
output io_port_pins_0_o_oe,
output io_port_pins_0_o_ie,
output io_port_pins_0_o_pue,
output io_port_pins_0_o_ds,
input io_port_pins_1_i_ival,
output io_port_pins_1_o_oval,
output io_port_pins_1_o_oe,
output io_port_pins_1_o_ie,
output io_port_pins_1_o_pue,
output io_port_pins_1_o_ds,
input io_port_pins_2_i_ival,
output io_port_pins_2_o_oval,
output io_port_pins_2_o_oe,
output io_port_pins_2_o_ie,
output io_port_pins_2_o_pue,
output io_port_pins_2_o_ds,
input io_port_pins_3_i_ival,
output io_port_pins_3_o_oval,
output io_port_pins_3_o_oe,
output io_port_pins_3_o_ie,
output io_port_pins_3_o_pue,
output io_port_pins_3_o_ds,
input io_port_pins_4_i_ival,
output io_port_pins_4_o_oval,
output io_port_pins_4_o_oe,
output io_port_pins_4_o_ie,
output io_port_pins_4_o_pue,
output io_port_pins_4_o_ds,
input io_port_pins_5_i_ival,
output io_port_pins_5_o_oval,
output io_port_pins_5_o_oe,
output io_port_pins_5_o_ie,
output io_port_pins_5_o_pue,
output io_port_pins_5_o_ds,
input io_port_pins_6_i_ival,
output io_port_pins_6_o_oval,
output io_port_pins_6_o_oe,
output io_port_pins_6_o_ie,
output io_port_pins_6_o_pue,
output io_port_pins_6_o_ds,
input io_port_pins_7_i_ival,
output io_port_pins_7_o_oval,
output io_port_pins_7_o_oe,
output io_port_pins_7_o_ie,
output io_port_pins_7_o_pue,
output io_port_pins_7_o_ds,
input io_port_pins_8_i_ival,
output io_port_pins_8_o_oval,
output io_port_pins_8_o_oe,
output io_port_pins_8_o_ie,
output io_port_pins_8_o_pue,
output io_port_pins_8_o_ds,
input io_port_pins_9_i_ival,
output io_port_pins_9_o_oval,
output io_port_pins_9_o_oe,
output io_port_pins_9_o_ie,
output io_port_pins_9_o_pue,
output io_port_pins_9_o_ds,
input io_port_pins_10_i_ival,
output io_port_pins_10_o_oval,
output io_port_pins_10_o_oe,
output io_port_pins_10_o_ie,
output io_port_pins_10_o_pue,
output io_port_pins_10_o_ds,
input io_port_pins_11_i_ival,
output io_port_pins_11_o_oval,
output io_port_pins_11_o_oe,
output io_port_pins_11_o_ie,
output io_port_pins_11_o_pue,
output io_port_pins_11_o_ds,
input io_port_pins_12_i_ival,
output io_port_pins_12_o_oval,
output io_port_pins_12_o_oe,
output io_port_pins_12_o_ie,
output io_port_pins_12_o_pue,
output io_port_pins_12_o_ds,
input io_port_pins_13_i_ival,
output io_port_pins_13_o_oval,
output io_port_pins_13_o_oe,
output io_port_pins_13_o_ie,
output io_port_pins_13_o_pue,
output io_port_pins_13_o_ds,
input io_port_pins_14_i_ival,
output io_port_pins_14_o_oval,
output io_port_pins_14_o_oe,
output io_port_pins_14_o_ie,
output io_port_pins_14_o_pue,
output io_port_pins_14_o_ds,
input io_port_pins_15_i_ival,
output io_port_pins_15_o_oval,
output io_port_pins_15_o_oe,
output io_port_pins_15_o_ie,
output io_port_pins_15_o_pue,
output io_port_pins_15_o_ds,
input io_port_pins_16_i_ival,
output io_port_pins_16_o_oval,
output io_port_pins_16_o_oe,
output io_port_pins_16_o_ie,
output io_port_pins_16_o_pue,
output io_port_pins_16_o_ds,
input io_port_pins_17_i_ival,
output io_port_pins_17_o_oval,
output io_port_pins_17_o_oe,
output io_port_pins_17_o_ie,
output io_port_pins_17_o_pue,
output io_port_pins_17_o_ds,
input io_port_pins_18_i_ival,
output io_port_pins_18_o_oval,
output io_port_pins_18_o_oe,
output io_port_pins_18_o_ie,
output io_port_pins_18_o_pue,
output io_port_pins_18_o_ds,
input io_port_pins_19_i_ival,
output io_port_pins_19_o_oval,
output io_port_pins_19_o_oe,
output io_port_pins_19_o_ie,
output io_port_pins_19_o_pue,
output io_port_pins_19_o_ds,
input io_port_pins_20_i_ival,
output io_port_pins_20_o_oval,
output io_port_pins_20_o_oe,
output io_port_pins_20_o_ie,
output io_port_pins_20_o_pue,
output io_port_pins_20_o_ds,
input io_port_pins_21_i_ival,
output io_port_pins_21_o_oval,
output io_port_pins_21_o_oe,
output io_port_pins_21_o_ie,
output io_port_pins_21_o_pue,
output io_port_pins_21_o_ds,
input io_port_pins_22_i_ival,
output io_port_pins_22_o_oval,
output io_port_pins_22_o_oe,
output io_port_pins_22_o_ie,
output io_port_pins_22_o_pue,
output io_port_pins_22_o_ds,
input io_port_pins_23_i_ival,
output io_port_pins_23_o_oval,
output io_port_pins_23_o_oe,
output io_port_pins_23_o_ie,
output io_port_pins_23_o_pue,
output io_port_pins_23_o_ds,
input io_port_pins_24_i_ival,
output io_port_pins_24_o_oval,
output io_port_pins_24_o_oe,
output io_port_pins_24_o_ie,
output io_port_pins_24_o_pue,
output io_port_pins_24_o_ds,
input io_port_pins_25_i_ival,
output io_port_pins_25_o_oval,
output io_port_pins_25_o_oe,
output io_port_pins_25_o_ie,
output io_port_pins_25_o_pue,
output io_port_pins_25_o_ds,
input io_port_pins_26_i_ival,
output io_port_pins_26_o_oval,
output io_port_pins_26_o_oe,
output io_port_pins_26_o_ie,
output io_port_pins_26_o_pue,
output io_port_pins_26_o_ds,
input io_port_pins_27_i_ival,
output io_port_pins_27_o_oval,
output io_port_pins_27_o_oe,
output io_port_pins_27_o_ie,
output io_port_pins_27_o_pue,
output io_port_pins_27_o_ds,
input io_port_pins_28_i_ival,
output io_port_pins_28_o_oval,
output io_port_pins_28_o_oe,
output io_port_pins_28_o_ie,
output io_port_pins_28_o_pue,
output io_port_pins_28_o_ds,
input io_port_pins_29_i_ival,
output io_port_pins_29_o_oval,
output io_port_pins_29_o_oe,
output io_port_pins_29_o_ie,
output io_port_pins_29_o_pue,
output io_port_pins_29_o_ds,
input io_port_pins_30_i_ival,
output io_port_pins_30_o_oval,
output io_port_pins_30_o_oe,
output io_port_pins_30_o_ie,
output io_port_pins_30_o_pue,
output io_port_pins_30_o_ds,
input io_port_pins_31_i_ival,
output io_port_pins_31_o_oval,
output io_port_pins_31_o_oe,
output io_port_pins_31_o_ie,
output io_port_pins_31_o_pue,
output io_port_pins_31_o_ds,
output io_port_iof_0_0_i_ival,
input io_port_iof_0_0_o_oval,
input io_port_iof_0_0_o_oe,
input io_port_iof_0_0_o_ie,
input io_port_iof_0_0_o_valid,
output io_port_iof_0_1_i_ival,
input io_port_iof_0_1_o_oval,
input io_port_iof_0_1_o_oe,
input io_port_iof_0_1_o_ie,
input io_port_iof_0_1_o_valid,
output io_port_iof_0_2_i_ival,
input io_port_iof_0_2_o_oval,
input io_port_iof_0_2_o_oe,
input io_port_iof_0_2_o_ie,
input io_port_iof_0_2_o_valid,
output io_port_iof_0_3_i_ival,
input io_port_iof_0_3_o_oval,
input io_port_iof_0_3_o_oe,
input io_port_iof_0_3_o_ie,
input io_port_iof_0_3_o_valid,
output io_port_iof_0_4_i_ival,
input io_port_iof_0_4_o_oval,
input io_port_iof_0_4_o_oe,
input io_port_iof_0_4_o_ie,
input io_port_iof_0_4_o_valid,
output io_port_iof_0_5_i_ival,
input io_port_iof_0_5_o_oval,
input io_port_iof_0_5_o_oe,
input io_port_iof_0_5_o_ie,
input io_port_iof_0_5_o_valid,
output io_port_iof_0_6_i_ival,
input io_port_iof_0_6_o_oval,
input io_port_iof_0_6_o_oe,
input io_port_iof_0_6_o_ie,
input io_port_iof_0_6_o_valid,
output io_port_iof_0_7_i_ival,
input io_port_iof_0_7_o_oval,
input io_port_iof_0_7_o_oe,
input io_port_iof_0_7_o_ie,
input io_port_iof_0_7_o_valid,
output io_port_iof_0_8_i_ival,
input io_port_iof_0_8_o_oval,
input io_port_iof_0_8_o_oe,
input io_port_iof_0_8_o_ie,
input io_port_iof_0_8_o_valid,
output io_port_iof_0_9_i_ival,
input io_port_iof_0_9_o_oval,
input io_port_iof_0_9_o_oe,
input io_port_iof_0_9_o_ie,
input io_port_iof_0_9_o_valid,
output io_port_iof_0_10_i_ival,
input io_port_iof_0_10_o_oval,
input io_port_iof_0_10_o_oe,
input io_port_iof_0_10_o_ie,
input io_port_iof_0_10_o_valid,
output io_port_iof_0_11_i_ival,
input io_port_iof_0_11_o_oval,
input io_port_iof_0_11_o_oe,
input io_port_iof_0_11_o_ie,
input io_port_iof_0_11_o_valid,
output io_port_iof_0_12_i_ival,
input io_port_iof_0_12_o_oval,
input io_port_iof_0_12_o_oe,
input io_port_iof_0_12_o_ie,
input io_port_iof_0_12_o_valid,
output io_port_iof_0_13_i_ival,
input io_port_iof_0_13_o_oval,
input io_port_iof_0_13_o_oe,
input io_port_iof_0_13_o_ie,
input io_port_iof_0_13_o_valid,
output io_port_iof_0_14_i_ival,
input io_port_iof_0_14_o_oval,
input io_port_iof_0_14_o_oe,
input io_port_iof_0_14_o_ie,
input io_port_iof_0_14_o_valid,
output io_port_iof_0_15_i_ival,
input io_port_iof_0_15_o_oval,
input io_port_iof_0_15_o_oe,
input io_port_iof_0_15_o_ie,
input io_port_iof_0_15_o_valid,
output io_port_iof_0_16_i_ival,
input io_port_iof_0_16_o_oval,
input io_port_iof_0_16_o_oe,
input io_port_iof_0_16_o_ie,
input io_port_iof_0_16_o_valid,
output io_port_iof_0_17_i_ival,
input io_port_iof_0_17_o_oval,
input io_port_iof_0_17_o_oe,
input io_port_iof_0_17_o_ie,
input io_port_iof_0_17_o_valid,
output io_port_iof_0_18_i_ival,
input io_port_iof_0_18_o_oval,
input io_port_iof_0_18_o_oe,
input io_port_iof_0_18_o_ie,
input io_port_iof_0_18_o_valid,
output io_port_iof_0_19_i_ival,
input io_port_iof_0_19_o_oval,
input io_port_iof_0_19_o_oe,
input io_port_iof_0_19_o_ie,
input io_port_iof_0_19_o_valid,
output io_port_iof_0_20_i_ival,
input io_port_iof_0_20_o_oval,
input io_port_iof_0_20_o_oe,
input io_port_iof_0_20_o_ie,
input io_port_iof_0_20_o_valid,
output io_port_iof_0_21_i_ival,
input io_port_iof_0_21_o_oval,
input io_port_iof_0_21_o_oe,
input io_port_iof_0_21_o_ie,
input io_port_iof_0_21_o_valid,
output io_port_iof_0_22_i_ival,
input io_port_iof_0_22_o_oval,
input io_port_iof_0_22_o_oe,
input io_port_iof_0_22_o_ie,
input io_port_iof_0_22_o_valid,
output io_port_iof_0_23_i_ival,
input io_port_iof_0_23_o_oval,
input io_port_iof_0_23_o_oe,
input io_port_iof_0_23_o_ie,
input io_port_iof_0_23_o_valid,
output io_port_iof_0_24_i_ival,
input io_port_iof_0_24_o_oval,
input io_port_iof_0_24_o_oe,
input io_port_iof_0_24_o_ie,
input io_port_iof_0_24_o_valid,
output io_port_iof_0_25_i_ival,
input io_port_iof_0_25_o_oval,
input io_port_iof_0_25_o_oe,
input io_port_iof_0_25_o_ie,
input io_port_iof_0_25_o_valid,
output io_port_iof_0_26_i_ival,
input io_port_iof_0_26_o_oval,
input io_port_iof_0_26_o_oe,
input io_port_iof_0_26_o_ie,
input io_port_iof_0_26_o_valid,
output io_port_iof_0_27_i_ival,
input io_port_iof_0_27_o_oval,
input io_port_iof_0_27_o_oe,
input io_port_iof_0_27_o_ie,
input io_port_iof_0_27_o_valid,
output io_port_iof_0_28_i_ival,
input io_port_iof_0_28_o_oval,
input io_port_iof_0_28_o_oe,
input io_port_iof_0_28_o_ie,
input io_port_iof_0_28_o_valid,
output io_port_iof_0_29_i_ival,
input io_port_iof_0_29_o_oval,
input io_port_iof_0_29_o_oe,
input io_port_iof_0_29_o_ie,
input io_port_iof_0_29_o_valid,
output io_port_iof_0_30_i_ival,
input io_port_iof_0_30_o_oval,
input io_port_iof_0_30_o_oe,
input io_port_iof_0_30_o_ie,
input io_port_iof_0_30_o_valid,
output io_port_iof_0_31_i_ival,
input io_port_iof_0_31_o_oval,
input io_port_iof_0_31_o_oe,
input io_port_iof_0_31_o_ie,
input io_port_iof_0_31_o_valid,
output io_port_iof_1_0_i_ival,
input io_port_iof_1_0_o_oval,
input io_port_iof_1_0_o_oe,
input io_port_iof_1_0_o_ie,
input io_port_iof_1_0_o_valid,
output io_port_iof_1_1_i_ival,
input io_port_iof_1_1_o_oval,
input io_port_iof_1_1_o_oe,
input io_port_iof_1_1_o_ie,
input io_port_iof_1_1_o_valid,
output io_port_iof_1_2_i_ival,
input io_port_iof_1_2_o_oval,
input io_port_iof_1_2_o_oe,
input io_port_iof_1_2_o_ie,
input io_port_iof_1_2_o_valid,
output io_port_iof_1_3_i_ival,
input io_port_iof_1_3_o_oval,
input io_port_iof_1_3_o_oe,
input io_port_iof_1_3_o_ie,
input io_port_iof_1_3_o_valid,
output io_port_iof_1_4_i_ival,
input io_port_iof_1_4_o_oval,
input io_port_iof_1_4_o_oe,
input io_port_iof_1_4_o_ie,
input io_port_iof_1_4_o_valid,
output io_port_iof_1_5_i_ival,
input io_port_iof_1_5_o_oval,
input io_port_iof_1_5_o_oe,
input io_port_iof_1_5_o_ie,
input io_port_iof_1_5_o_valid,
output io_port_iof_1_6_i_ival,
input io_port_iof_1_6_o_oval,
input io_port_iof_1_6_o_oe,
input io_port_iof_1_6_o_ie,
input io_port_iof_1_6_o_valid,
output io_port_iof_1_7_i_ival,
input io_port_iof_1_7_o_oval,
input io_port_iof_1_7_o_oe,
input io_port_iof_1_7_o_ie,
input io_port_iof_1_7_o_valid,
output io_port_iof_1_8_i_ival,
input io_port_iof_1_8_o_oval,
input io_port_iof_1_8_o_oe,
input io_port_iof_1_8_o_ie,
input io_port_iof_1_8_o_valid,
output io_port_iof_1_9_i_ival,
input io_port_iof_1_9_o_oval,
input io_port_iof_1_9_o_oe,
input io_port_iof_1_9_o_ie,
input io_port_iof_1_9_o_valid,
output io_port_iof_1_10_i_ival,
input io_port_iof_1_10_o_oval,
input io_port_iof_1_10_o_oe,
input io_port_iof_1_10_o_ie,
input io_port_iof_1_10_o_valid,
output io_port_iof_1_11_i_ival,
input io_port_iof_1_11_o_oval,
input io_port_iof_1_11_o_oe,
input io_port_iof_1_11_o_ie,
input io_port_iof_1_11_o_valid,
output io_port_iof_1_12_i_ival,
input io_port_iof_1_12_o_oval,
input io_port_iof_1_12_o_oe,
input io_port_iof_1_12_o_ie,
input io_port_iof_1_12_o_valid,
output io_port_iof_1_13_i_ival,
input io_port_iof_1_13_o_oval,
input io_port_iof_1_13_o_oe,
input io_port_iof_1_13_o_ie,
input io_port_iof_1_13_o_valid,
output io_port_iof_1_14_i_ival,
input io_port_iof_1_14_o_oval,
input io_port_iof_1_14_o_oe,
input io_port_iof_1_14_o_ie,
input io_port_iof_1_14_o_valid,
output io_port_iof_1_15_i_ival,
input io_port_iof_1_15_o_oval,
input io_port_iof_1_15_o_oe,
input io_port_iof_1_15_o_ie,
input io_port_iof_1_15_o_valid,
output io_port_iof_1_16_i_ival,
input io_port_iof_1_16_o_oval,
input io_port_iof_1_16_o_oe,
input io_port_iof_1_16_o_ie,
input io_port_iof_1_16_o_valid,
output io_port_iof_1_17_i_ival,
input io_port_iof_1_17_o_oval,
input io_port_iof_1_17_o_oe,
input io_port_iof_1_17_o_ie,
input io_port_iof_1_17_o_valid,
output io_port_iof_1_18_i_ival,
input io_port_iof_1_18_o_oval,
input io_port_iof_1_18_o_oe,
input io_port_iof_1_18_o_ie,
input io_port_iof_1_18_o_valid,
output io_port_iof_1_19_i_ival,
input io_port_iof_1_19_o_oval,
input io_port_iof_1_19_o_oe,
input io_port_iof_1_19_o_ie,
input io_port_iof_1_19_o_valid,
output io_port_iof_1_20_i_ival,
input io_port_iof_1_20_o_oval,
input io_port_iof_1_20_o_oe,
input io_port_iof_1_20_o_ie,
input io_port_iof_1_20_o_valid,
output io_port_iof_1_21_i_ival,
input io_port_iof_1_21_o_oval,
input io_port_iof_1_21_o_oe,
input io_port_iof_1_21_o_ie,
input io_port_iof_1_21_o_valid,
output io_port_iof_1_22_i_ival,
input io_port_iof_1_22_o_oval,
input io_port_iof_1_22_o_oe,
input io_port_iof_1_22_o_ie,
input io_port_iof_1_22_o_valid,
output io_port_iof_1_23_i_ival,
input io_port_iof_1_23_o_oval,
input io_port_iof_1_23_o_oe,
input io_port_iof_1_23_o_ie,
input io_port_iof_1_23_o_valid,
output io_port_iof_1_24_i_ival,
input io_port_iof_1_24_o_oval,
input io_port_iof_1_24_o_oe,
input io_port_iof_1_24_o_ie,
input io_port_iof_1_24_o_valid,
output io_port_iof_1_25_i_ival,
input io_port_iof_1_25_o_oval,
input io_port_iof_1_25_o_oe,
input io_port_iof_1_25_o_ie,
input io_port_iof_1_25_o_valid,
output io_port_iof_1_26_i_ival,
input io_port_iof_1_26_o_oval,
input io_port_iof_1_26_o_oe,
input io_port_iof_1_26_o_ie,
input io_port_iof_1_26_o_valid,
output io_port_iof_1_27_i_ival,
input io_port_iof_1_27_o_oval,
input io_port_iof_1_27_o_oe,
input io_port_iof_1_27_o_ie,
input io_port_iof_1_27_o_valid,
output io_port_iof_1_28_i_ival,
input io_port_iof_1_28_o_oval,
input io_port_iof_1_28_o_oe,
input io_port_iof_1_28_o_ie,
input io_port_iof_1_28_o_valid,
output io_port_iof_1_29_i_ival,
input io_port_iof_1_29_o_oval,
input io_port_iof_1_29_o_oe,
input io_port_iof_1_29_o_ie,
input io_port_iof_1_29_o_valid,
output io_port_iof_1_30_i_ival,
input io_port_iof_1_30_o_oval,
input io_port_iof_1_30_o_oe,
input io_port_iof_1_30_o_ie,
input io_port_iof_1_30_o_valid,
output io_port_iof_1_31_i_ival,
input io_port_iof_1_31_o_oval,
input io_port_iof_1_31_o_oe,
input io_port_iof_1_31_o_ie,
input io_port_iof_1_31_o_valid
);
reg [31:0] portReg;
reg [31:0] GEN_399;
wire oeReg_clock;
wire oeReg_reset;
wire [31:0] oeReg_io_d;
wire [31:0] oeReg_io_q;
wire oeReg_io_en;
wire pueReg_clock;
wire pueReg_reset;
wire [31:0] pueReg_io_d;
wire [31:0] pueReg_io_q;
wire pueReg_io_en;
reg [31:0] dsReg;
reg [31:0] GEN_400;
wire ieReg_clock;
wire ieReg_reset;
wire [31:0] ieReg_io_d;
wire [31:0] ieReg_io_q;
wire ieReg_io_en;
wire [31:0] inVal;
wire T_3188_0;
wire T_3188_1;
wire T_3188_2;
wire T_3188_3;
wire T_3188_4;
wire T_3188_5;
wire T_3188_6;
wire T_3188_7;
wire T_3188_8;
wire T_3188_9;
wire T_3188_10;
wire T_3188_11;
wire T_3188_12;
wire T_3188_13;
wire T_3188_14;
wire T_3188_15;
wire T_3188_16;
wire T_3188_17;
wire T_3188_18;
wire T_3188_19;
wire T_3188_20;
wire T_3188_21;
wire T_3188_22;
wire T_3188_23;
wire T_3188_24;
wire T_3188_25;
wire T_3188_26;
wire T_3188_27;
wire T_3188_28;
wire T_3188_29;
wire T_3188_30;
wire T_3188_31;
wire [1:0] T_3223;
wire [1:0] T_3224;
wire [3:0] T_3225;
wire [1:0] T_3226;
wire [1:0] T_3227;
wire [3:0] T_3228;
wire [7:0] T_3229;
wire [1:0] T_3230;
wire [1:0] T_3231;
wire [3:0] T_3232;
wire [1:0] T_3233;
wire [1:0] T_3234;
wire [3:0] T_3235;
wire [7:0] T_3236;
wire [15:0] T_3237;
wire [1:0] T_3238;
wire [1:0] T_3239;
wire [3:0] T_3240;
wire [1:0] T_3241;
wire [1:0] T_3242;
wire [3:0] T_3243;
wire [7:0] T_3244;
wire [1:0] T_3245;
wire [1:0] T_3246;
wire [3:0] T_3247;
wire [1:0] T_3248;
wire [1:0] T_3249;
wire [3:0] T_3250;
wire [7:0] T_3251;
wire [15:0] T_3252;
wire [31:0] T_3253;
reg [31:0] T_3256;
reg [31:0] GEN_401;
reg [31:0] T_3257;
reg [31:0] GEN_402;
reg [31:0] inSyncReg;
reg [31:0] GEN_403;
reg [31:0] valueReg;
reg [31:0] GEN_404;
reg [31:0] highIeReg;
reg [31:0] GEN_405;
reg [31:0] lowIeReg;
reg [31:0] GEN_406;
reg [31:0] riseIeReg;
reg [31:0] GEN_407;
reg [31:0] fallIeReg;
reg [31:0] GEN_408;
reg [31:0] highIpReg;
reg [31:0] GEN_409;
reg [31:0] lowIpReg;
reg [31:0] GEN_410;
reg [31:0] riseIpReg;
reg [31:0] GEN_411;
reg [31:0] fallIpReg;
reg [31:0] GEN_412;
wire iofEnReg_clock;
wire iofEnReg_reset;
wire [31:0] iofEnReg_io_d;
wire [31:0] iofEnReg_io_q;
wire iofEnReg_io_en;
reg [31:0] iofSelReg;
reg [31:0] GEN_413;
reg [31:0] xorReg;
reg [31:0] GEN_414;
wire [31:0] T_3269;
wire [31:0] rise;
wire [31:0] T_3270;
wire [31:0] fall;
wire T_3295_ready;
wire T_3295_valid;
wire T_3295_bits_read;
wire [9:0] T_3295_bits_index;
wire [31:0] T_3295_bits_data;
wire [3:0] T_3295_bits_mask;
wire [9:0] T_3295_bits_extra;
wire T_3312;
wire [26:0] T_3313;
wire [1:0] T_3314;
wire [6:0] T_3315;
wire [9:0] T_3316;
wire T_3334_ready;
wire T_3334_valid;
wire T_3334_bits_read;
wire [31:0] T_3334_bits_data;
wire [9:0] T_3334_bits_extra;
wire T_3370_ready;
wire T_3370_valid;
wire T_3370_bits_read;
wire [9:0] T_3370_bits_index;
wire [31:0] T_3370_bits_data;
wire [3:0] T_3370_bits_mask;
wire [9:0] T_3370_bits_extra;
wire [9:0] T_3455;
wire T_3457;
wire [9:0] T_3463;
wire [9:0] T_3464;
wire T_3466;
wire [9:0] T_3472;
wire [9:0] T_3473;
wire T_3475;
wire [9:0] T_3481;
wire [9:0] T_3482;
wire T_3484;
wire [9:0] T_3490;
wire [9:0] T_3491;
wire T_3493;
wire [9:0] T_3499;
wire [9:0] T_3500;
wire T_3502;
wire [9:0] T_3508;
wire [9:0] T_3509;
wire T_3511;
wire [9:0] T_3517;
wire [9:0] T_3518;
wire T_3520;
wire [9:0] T_3526;
wire [9:0] T_3527;
wire T_3529;
wire [9:0] T_3535;
wire [9:0] T_3536;
wire T_3538;
wire [9:0] T_3544;
wire [9:0] T_3545;
wire T_3547;
wire [9:0] T_3553;
wire [9:0] T_3554;
wire T_3556;
wire [9:0] T_3562;
wire [9:0] T_3563;
wire T_3565;
wire [9:0] T_3571;
wire [9:0] T_3572;
wire T_3574;
wire [9:0] T_3580;
wire [9:0] T_3581;
wire T_3583;
wire [9:0] T_3589;
wire [9:0] T_3590;
wire T_3592;
wire [9:0] T_3598;
wire [9:0] T_3599;
wire T_3601;
wire T_3609_0;
wire T_3609_1;
wire T_3609_2;
wire T_3609_3;
wire T_3609_4;
wire T_3609_5;
wire T_3609_6;
wire T_3609_7;
wire T_3609_8;
wire T_3609_9;
wire T_3609_10;
wire T_3609_11;
wire T_3609_12;
wire T_3609_13;
wire T_3609_14;
wire T_3609_15;
wire T_3609_16;
wire T_3614_0;
wire T_3614_1;
wire T_3614_2;
wire T_3614_3;
wire T_3614_4;
wire T_3614_5;
wire T_3614_6;
wire T_3614_7;
wire T_3614_8;
wire T_3614_9;
wire T_3614_10;
wire T_3614_11;
wire T_3614_12;
wire T_3614_13;
wire T_3614_14;
wire T_3614_15;
wire T_3614_16;
wire T_3619_0;
wire T_3619_1;
wire T_3619_2;
wire T_3619_3;
wire T_3619_4;
wire T_3619_5;
wire T_3619_6;
wire T_3619_7;
wire T_3619_8;
wire T_3619_9;
wire T_3619_10;
wire T_3619_11;
wire T_3619_12;
wire T_3619_13;
wire T_3619_14;
wire T_3619_15;
wire T_3619_16;
wire T_3624_0;
wire T_3624_1;
wire T_3624_2;
wire T_3624_3;
wire T_3624_4;
wire T_3624_5;
wire T_3624_6;
wire T_3624_7;
wire T_3624_8;
wire T_3624_9;
wire T_3624_10;
wire T_3624_11;
wire T_3624_12;
wire T_3624_13;
wire T_3624_14;
wire T_3624_15;
wire T_3624_16;
wire T_3629_0;
wire T_3629_1;
wire T_3629_2;
wire T_3629_3;
wire T_3629_4;
wire T_3629_5;
wire T_3629_6;
wire T_3629_7;
wire T_3629_8;
wire T_3629_9;
wire T_3629_10;
wire T_3629_11;
wire T_3629_12;
wire T_3629_13;
wire T_3629_14;
wire T_3629_15;
wire T_3629_16;
wire T_3634_0;
wire T_3634_1;
wire T_3634_2;
wire T_3634_3;
wire T_3634_4;
wire T_3634_5;
wire T_3634_6;
wire T_3634_7;
wire T_3634_8;
wire T_3634_9;
wire T_3634_10;
wire T_3634_11;
wire T_3634_12;
wire T_3634_13;
wire T_3634_14;
wire T_3634_15;
wire T_3634_16;
wire T_3639_0;
wire T_3639_1;
wire T_3639_2;
wire T_3639_3;
wire T_3639_4;
wire T_3639_5;
wire T_3639_6;
wire T_3639_7;
wire T_3639_8;
wire T_3639_9;
wire T_3639_10;
wire T_3639_11;
wire T_3639_12;
wire T_3639_13;
wire T_3639_14;
wire T_3639_15;
wire T_3639_16;
wire T_3644_0;
wire T_3644_1;
wire T_3644_2;
wire T_3644_3;
wire T_3644_4;
wire T_3644_5;
wire T_3644_6;
wire T_3644_7;
wire T_3644_8;
wire T_3644_9;
wire T_3644_10;
wire T_3644_11;
wire T_3644_12;
wire T_3644_13;
wire T_3644_14;
wire T_3644_15;
wire T_3644_16;
wire T_3806;
wire T_3807;
wire T_3808;
wire T_3809;
wire [7:0] T_3813;
wire [7:0] T_3817;
wire [7:0] T_3821;
wire [7:0] T_3825;
wire [15:0] T_3826;
wire [15:0] T_3827;
wire [31:0] T_3828;
wire [31:0] T_3856;
wire T_3858;
wire T_3911;
wire [31:0] GEN_7;
wire T_3951;
wire [31:0] GEN_8;
wire T_3991;
wire [31:0] T_4007;
wire T_4031;
wire [31:0] T_4047;
wire T_4071;
wire [31:0] GEN_9;
wire T_4111;
wire [31:0] T_4114;
wire [31:0] T_4116;
wire [31:0] T_4117;
wire [31:0] T_4118;
wire [31:0] T_4119;
wire T_4157;
wire [31:0] T_4160;
wire [31:0] T_4162;
wire [31:0] T_4163;
wire [31:0] T_4164;
wire [31:0] T_4165;
wire T_4203;
wire [31:0] T_4219;
wire T_4243;
wire [31:0] GEN_10;
wire T_4283;
wire [31:0] T_4286;
wire [31:0] T_4288;
wire [31:0] T_4289;
wire [31:0] T_4290;
wire [31:0] T_4291;
wire T_4329;
wire [31:0] GEN_11;
wire T_4369;
wire [31:0] GEN_12;
wire T_4409;
wire [31:0] T_4412;
wire [31:0] T_4414;
wire [31:0] T_4415;
wire [31:0] T_4416;
wire [31:0] T_4417;
wire T_4455;
wire [31:0] GEN_13;
wire T_4495;
wire [31:0] T_4511;
wire T_4535;
wire [31:0] GEN_14;
wire T_4557;
wire T_4559;
wire T_4561;
wire T_4563;
wire T_4565;
wire T_4567;
wire T_4569;
wire T_4571;
wire T_4573;
wire T_4575;
wire T_4577;
wire T_4579;
wire T_4581;
wire T_4583;
wire T_4585;
wire T_4587;
wire T_4589;
wire T_4591;
wire T_4593;
wire T_4595;
wire T_4597;
wire T_4599;
wire T_4601;
wire T_4603;
wire T_4605;
wire T_4607;
wire T_4609;
wire T_4611;
wire T_4613;
wire T_4615;
wire T_4617;
wire T_4619;
wire T_4621;
wire T_4623;
wire T_4704_0;
wire T_4704_1;
wire T_4704_2;
wire T_4704_3;
wire T_4704_4;
wire T_4704_5;
wire T_4704_6;
wire T_4704_7;
wire T_4704_8;
wire T_4704_9;
wire T_4704_10;
wire T_4704_11;
wire T_4704_12;
wire T_4704_13;
wire T_4704_14;
wire T_4704_15;
wire T_4704_16;
wire T_4704_17;
wire T_4704_18;
wire T_4704_19;
wire T_4704_20;
wire T_4704_21;
wire T_4704_22;
wire T_4704_23;
wire T_4704_24;
wire T_4704_25;
wire T_4704_26;
wire T_4704_27;
wire T_4704_28;
wire T_4704_29;
wire T_4704_30;
wire T_4704_31;
wire T_4742;
wire T_4746;
wire T_4750;
wire T_4754;
wire T_4758;
wire T_4762;
wire T_4766;
wire T_4770;
wire T_4774;
wire T_4778;
wire T_4782;
wire T_4786;
wire T_4790;
wire T_4794;
wire T_4798;
wire T_4802;
wire T_4806;
wire T_4887_0;
wire T_4887_1;
wire T_4887_2;
wire T_4887_3;
wire T_4887_4;
wire T_4887_5;
wire T_4887_6;
wire T_4887_7;
wire T_4887_8;
wire T_4887_9;
wire T_4887_10;
wire T_4887_11;
wire T_4887_12;
wire T_4887_13;
wire T_4887_14;
wire T_4887_15;
wire T_4887_16;
wire T_4887_17;
wire T_4887_18;
wire T_4887_19;
wire T_4887_20;
wire T_4887_21;
wire T_4887_22;
wire T_4887_23;
wire T_4887_24;
wire T_4887_25;
wire T_4887_26;
wire T_4887_27;
wire T_4887_28;
wire T_4887_29;
wire T_4887_30;
wire T_4887_31;
wire T_4925;
wire T_4929;
wire T_4933;
wire T_4937;
wire T_4941;
wire T_4945;
wire T_4949;
wire T_4953;
wire T_4957;
wire T_4961;
wire T_4965;
wire T_4969;
wire T_4973;
wire T_4977;
wire T_4981;
wire T_4985;
wire T_4989;
wire T_5070_0;
wire T_5070_1;
wire T_5070_2;
wire T_5070_3;
wire T_5070_4;
wire T_5070_5;
wire T_5070_6;
wire T_5070_7;
wire T_5070_8;
wire T_5070_9;
wire T_5070_10;
wire T_5070_11;
wire T_5070_12;
wire T_5070_13;
wire T_5070_14;
wire T_5070_15;
wire T_5070_16;
wire T_5070_17;
wire T_5070_18;
wire T_5070_19;
wire T_5070_20;
wire T_5070_21;
wire T_5070_22;
wire T_5070_23;
wire T_5070_24;
wire T_5070_25;
wire T_5070_26;
wire T_5070_27;
wire T_5070_28;
wire T_5070_29;
wire T_5070_30;
wire T_5070_31;
wire T_5108;
wire T_5112;
wire T_5116;
wire T_5120;
wire T_5124;
wire T_5128;
wire T_5132;
wire T_5136;
wire T_5140;
wire T_5144;
wire T_5148;
wire T_5152;
wire T_5156;
wire T_5160;
wire T_5164;
wire T_5168;
wire T_5172;
wire T_5253_0;
wire T_5253_1;
wire T_5253_2;
wire T_5253_3;
wire T_5253_4;
wire T_5253_5;
wire T_5253_6;
wire T_5253_7;
wire T_5253_8;
wire T_5253_9;
wire T_5253_10;
wire T_5253_11;
wire T_5253_12;
wire T_5253_13;
wire T_5253_14;
wire T_5253_15;
wire T_5253_16;
wire T_5253_17;
wire T_5253_18;
wire T_5253_19;
wire T_5253_20;
wire T_5253_21;
wire T_5253_22;
wire T_5253_23;
wire T_5253_24;
wire T_5253_25;
wire T_5253_26;
wire T_5253_27;
wire T_5253_28;
wire T_5253_29;
wire T_5253_30;
wire T_5253_31;
wire T_5288;
wire T_5289;
wire T_5290;
wire T_5291;
wire T_5292;
wire [1:0] T_5298;
wire [1:0] T_5299;
wire [2:0] T_5300;
wire [4:0] T_5301;
wire GEN_0;
wire GEN_15;
wire GEN_16;
wire GEN_17;
wire GEN_18;
wire GEN_19;
wire GEN_20;
wire GEN_21;
wire GEN_22;
wire GEN_23;
wire GEN_24;
wire GEN_25;
wire GEN_26;
wire GEN_27;
wire GEN_28;
wire GEN_29;
wire GEN_30;
wire GEN_31;
wire GEN_32;
wire GEN_33;
wire GEN_34;
wire GEN_35;
wire GEN_36;
wire GEN_37;
wire GEN_38;
wire GEN_39;
wire GEN_40;
wire GEN_41;
wire GEN_42;
wire GEN_43;
wire GEN_44;
wire GEN_45;
wire GEN_1;
wire GEN_46;
wire GEN_47;
wire GEN_48;
wire GEN_49;
wire GEN_50;
wire GEN_51;
wire GEN_52;
wire GEN_53;
wire GEN_54;
wire GEN_55;
wire GEN_56;
wire GEN_57;
wire GEN_58;
wire GEN_59;
wire GEN_60;
wire GEN_61;
wire GEN_62;
wire GEN_63;
wire GEN_64;
wire GEN_65;
wire GEN_66;
wire GEN_67;
wire GEN_68;
wire GEN_69;
wire GEN_70;
wire GEN_71;
wire GEN_72;
wire GEN_73;
wire GEN_74;
wire GEN_75;
wire GEN_76;
wire T_5318;
wire GEN_2;
wire GEN_77;
wire GEN_78;
wire GEN_79;
wire GEN_80;
wire GEN_81;
wire GEN_82;
wire GEN_83;
wire GEN_84;
wire GEN_85;
wire GEN_86;
wire GEN_87;
wire GEN_88;
wire GEN_89;
wire GEN_90;
wire GEN_91;
wire GEN_92;
wire GEN_93;
wire GEN_94;
wire GEN_95;
wire GEN_96;
wire GEN_97;
wire GEN_98;
wire GEN_99;
wire GEN_100;
wire GEN_101;
wire GEN_102;
wire GEN_103;
wire GEN_104;
wire GEN_105;
wire GEN_106;
wire GEN_107;
wire GEN_3;
wire GEN_108;
wire GEN_109;
wire GEN_110;
wire GEN_111;
wire GEN_112;
wire GEN_113;
wire GEN_114;
wire GEN_115;
wire GEN_116;
wire GEN_117;
wire GEN_118;
wire GEN_119;
wire GEN_120;
wire GEN_121;
wire GEN_122;
wire GEN_123;
wire GEN_124;
wire GEN_125;
wire GEN_126;
wire GEN_127;
wire GEN_128;
wire GEN_129;
wire GEN_130;
wire GEN_131;
wire GEN_132;
wire GEN_133;
wire GEN_134;
wire GEN_135;
wire GEN_136;
wire GEN_137;
wire GEN_138;
wire T_5321;
wire T_5322;
wire T_5323;
wire T_5324;
wire T_5325;
wire [31:0] T_5327;
wire [1:0] T_5328;
wire [1:0] T_5329;
wire [3:0] T_5330;
wire [1:0] T_5331;
wire [1:0] T_5332;
wire [3:0] T_5333;
wire [7:0] T_5334;
wire [1:0] T_5335;
wire [1:0] T_5336;
wire [3:0] T_5337;
wire [1:0] T_5338;
wire [1:0] T_5339;
wire [3:0] T_5340;
wire [7:0] T_5341;
wire [15:0] T_5342;
wire [1:0] T_5343;
wire [3:0] T_5345;
wire [7:0] T_5349;
wire [15:0] T_5357;
wire [31:0] T_5358;
wire [31:0] T_5359;
wire T_5394;
wire T_5395;
wire T_5396;
wire T_5397;
wire T_5400;
wire T_5401;
wire T_5403;
wire T_5404;
wire T_5405;
wire T_5407;
wire T_5411;
wire T_5413;
wire T_5416;
wire T_5417;
wire T_5423;
wire T_5427;
wire T_5433;
wire T_5436;
wire T_5437;
wire T_5443;
wire T_5447;
wire T_5453;
wire T_5456;
wire T_5457;
wire T_5463;
wire T_5467;
wire T_5473;
wire T_5476;
wire T_5477;
wire T_5483;
wire T_5487;
wire T_5493;
wire T_5496;
wire T_5497;
wire T_5503;
wire T_5507;
wire T_5513;
wire T_5516;
wire T_5517;
wire T_5523;
wire T_5527;
wire T_5533;
wire T_5536;
wire T_5537;
wire T_5543;
wire T_5547;
wire T_5553;
wire T_5556;
wire T_5557;
wire T_5563;
wire T_5567;
wire T_5573;
wire T_5576;
wire T_5577;
wire T_5583;
wire T_5587;
wire T_5593;
wire T_5596;
wire T_5597;
wire T_5603;
wire T_5607;
wire T_5613;
wire T_5616;
wire T_5617;
wire T_5623;
wire T_5627;
wire T_5633;
wire T_5636;
wire T_5637;
wire T_5643;
wire T_5647;
wire T_5653;
wire T_5656;
wire T_5657;
wire T_5663;
wire T_5667;
wire T_5673;
wire T_5676;
wire T_5677;
wire T_5683;
wire T_5687;
wire T_5693;
wire T_5696;
wire T_5697;
wire T_5703;
wire T_5707;
wire T_5713;
wire T_5716;
wire T_5717;
wire T_5723;
wire T_5727;
wire T_5733;
wire T_6137_0;
wire T_6137_1;
wire T_6137_2;
wire T_6137_3;
wire T_6137_4;
wire T_6137_5;
wire T_6137_6;
wire T_6137_7;
wire T_6137_8;
wire T_6137_9;
wire T_6137_10;
wire T_6137_11;
wire T_6137_12;
wire T_6137_13;
wire T_6137_14;
wire T_6137_15;
wire T_6137_16;
wire T_6137_17;
wire T_6137_18;
wire T_6137_19;
wire T_6137_20;
wire T_6137_21;
wire T_6137_22;
wire T_6137_23;
wire T_6137_24;
wire T_6137_25;
wire T_6137_26;
wire T_6137_27;
wire T_6137_28;
wire T_6137_29;
wire T_6137_30;
wire T_6137_31;
wire [31:0] T_6208_0;
wire [31:0] T_6208_1;
wire [31:0] T_6208_2;
wire [31:0] T_6208_3;
wire [31:0] T_6208_4;
wire [31:0] T_6208_5;
wire [31:0] T_6208_6;
wire [31:0] T_6208_7;
wire [31:0] T_6208_8;
wire [31:0] T_6208_9;
wire [31:0] T_6208_10;
wire [31:0] T_6208_11;
wire [31:0] T_6208_12;
wire [31:0] T_6208_13;
wire [31:0] T_6208_14;
wire [31:0] T_6208_15;
wire [31:0] T_6208_16;
wire [31:0] T_6208_17;
wire [31:0] T_6208_18;
wire [31:0] T_6208_19;
wire [31:0] T_6208_20;
wire [31:0] T_6208_21;
wire [31:0] T_6208_22;
wire [31:0] T_6208_23;
wire [31:0] T_6208_24;
wire [31:0] T_6208_25;
wire [31:0] T_6208_26;
wire [31:0] T_6208_27;
wire [31:0] T_6208_28;
wire [31:0] T_6208_29;
wire [31:0] T_6208_30;
wire [31:0] T_6208_31;
wire GEN_4;
wire GEN_139;
wire GEN_140;
wire GEN_141;
wire GEN_142;
wire GEN_143;
wire GEN_144;
wire GEN_145;
wire GEN_146;
wire GEN_147;
wire GEN_148;
wire GEN_149;
wire GEN_150;
wire GEN_151;
wire GEN_152;
wire GEN_153;
wire GEN_154;
wire GEN_155;
wire GEN_156;
wire GEN_157;
wire GEN_158;
wire GEN_159;
wire GEN_160;
wire GEN_161;
wire GEN_162;
wire GEN_163;
wire GEN_164;
wire GEN_165;
wire GEN_166;
wire GEN_167;
wire GEN_168;
wire GEN_169;
wire [31:0] GEN_5;
wire [31:0] GEN_170;
wire [31:0] GEN_171;
wire [31:0] GEN_172;
wire [31:0] GEN_173;
wire [31:0] GEN_174;
wire [31:0] GEN_175;
wire [31:0] GEN_176;
wire [31:0] GEN_177;
wire [31:0] GEN_178;
wire [31:0] GEN_179;
wire [31:0] GEN_180;
wire [31:0] GEN_181;
wire [31:0] GEN_182;
wire [31:0] GEN_183;
wire [31:0] GEN_184;
wire [31:0] GEN_185;
wire [31:0] GEN_186;
wire [31:0] GEN_187;
wire [31:0] GEN_188;
wire [31:0] GEN_189;
wire [31:0] GEN_190;
wire [31:0] GEN_191;
wire [31:0] GEN_192;
wire [31:0] GEN_193;
wire [31:0] GEN_194;
wire [31:0] GEN_195;
wire [31:0] GEN_196;
wire [31:0] GEN_197;
wire [31:0] GEN_198;
wire [31:0] GEN_199;
wire [31:0] GEN_200;
wire [31:0] T_6245;
wire [1:0] T_6246;
wire [4:0] T_6248;
wire [2:0] T_6249;
wire [2:0] T_6260_opcode;
wire [1:0] T_6260_param;
wire [2:0] T_6260_size;
wire [4:0] T_6260_source;
wire T_6260_sink;
wire [1:0] T_6260_addr_lo;
wire [31:0] T_6260_data;
wire T_6260_error;
wire swPinCtrl_0_oval;
wire swPinCtrl_0_oe;
wire swPinCtrl_0_ie;
wire swPinCtrl_0_pue;
wire swPinCtrl_0_ds;
wire swPinCtrl_1_oval;
wire swPinCtrl_1_oe;
wire swPinCtrl_1_ie;
wire swPinCtrl_1_pue;
wire swPinCtrl_1_ds;
wire swPinCtrl_2_oval;
wire swPinCtrl_2_oe;
wire swPinCtrl_2_ie;
wire swPinCtrl_2_pue;
wire swPinCtrl_2_ds;
wire swPinCtrl_3_oval;
wire swPinCtrl_3_oe;
wire swPinCtrl_3_ie;
wire swPinCtrl_3_pue;
wire swPinCtrl_3_ds;
wire swPinCtrl_4_oval;
wire swPinCtrl_4_oe;
wire swPinCtrl_4_ie;
wire swPinCtrl_4_pue;
wire swPinCtrl_4_ds;
wire swPinCtrl_5_oval;
wire swPinCtrl_5_oe;
wire swPinCtrl_5_ie;
wire swPinCtrl_5_pue;
wire swPinCtrl_5_ds;
wire swPinCtrl_6_oval;
wire swPinCtrl_6_oe;
wire swPinCtrl_6_ie;
wire swPinCtrl_6_pue;
wire swPinCtrl_6_ds;
wire swPinCtrl_7_oval;
wire swPinCtrl_7_oe;
wire swPinCtrl_7_ie;
wire swPinCtrl_7_pue;
wire swPinCtrl_7_ds;
wire swPinCtrl_8_oval;
wire swPinCtrl_8_oe;
wire swPinCtrl_8_ie;
wire swPinCtrl_8_pue;
wire swPinCtrl_8_ds;
wire swPinCtrl_9_oval;
wire swPinCtrl_9_oe;
wire swPinCtrl_9_ie;
wire swPinCtrl_9_pue;
wire swPinCtrl_9_ds;
wire swPinCtrl_10_oval;
wire swPinCtrl_10_oe;
wire swPinCtrl_10_ie;
wire swPinCtrl_10_pue;
wire swPinCtrl_10_ds;
wire swPinCtrl_11_oval;
wire swPinCtrl_11_oe;
wire swPinCtrl_11_ie;
wire swPinCtrl_11_pue;
wire swPinCtrl_11_ds;
wire swPinCtrl_12_oval;
wire swPinCtrl_12_oe;
wire swPinCtrl_12_ie;
wire swPinCtrl_12_pue;
wire swPinCtrl_12_ds;
wire swPinCtrl_13_oval;
wire swPinCtrl_13_oe;
wire swPinCtrl_13_ie;
wire swPinCtrl_13_pue;
wire swPinCtrl_13_ds;
wire swPinCtrl_14_oval;
wire swPinCtrl_14_oe;
wire swPinCtrl_14_ie;
wire swPinCtrl_14_pue;
wire swPinCtrl_14_ds;
wire swPinCtrl_15_oval;
wire swPinCtrl_15_oe;
wire swPinCtrl_15_ie;
wire swPinCtrl_15_pue;
wire swPinCtrl_15_ds;
wire swPinCtrl_16_oval;
wire swPinCtrl_16_oe;
wire swPinCtrl_16_ie;
wire swPinCtrl_16_pue;
wire swPinCtrl_16_ds;
wire swPinCtrl_17_oval;
wire swPinCtrl_17_oe;
wire swPinCtrl_17_ie;
wire swPinCtrl_17_pue;
wire swPinCtrl_17_ds;
wire swPinCtrl_18_oval;
wire swPinCtrl_18_oe;
wire swPinCtrl_18_ie;
wire swPinCtrl_18_pue;
wire swPinCtrl_18_ds;
wire swPinCtrl_19_oval;
wire swPinCtrl_19_oe;
wire swPinCtrl_19_ie;
wire swPinCtrl_19_pue;
wire swPinCtrl_19_ds;
wire swPinCtrl_20_oval;
wire swPinCtrl_20_oe;
wire swPinCtrl_20_ie;
wire swPinCtrl_20_pue;
wire swPinCtrl_20_ds;
wire swPinCtrl_21_oval;
wire swPinCtrl_21_oe;
wire swPinCtrl_21_ie;
wire swPinCtrl_21_pue;
wire swPinCtrl_21_ds;
wire swPinCtrl_22_oval;
wire swPinCtrl_22_oe;
wire swPinCtrl_22_ie;
wire swPinCtrl_22_pue;
wire swPinCtrl_22_ds;
wire swPinCtrl_23_oval;
wire swPinCtrl_23_oe;
wire swPinCtrl_23_ie;
wire swPinCtrl_23_pue;
wire swPinCtrl_23_ds;
wire swPinCtrl_24_oval;
wire swPinCtrl_24_oe;
wire swPinCtrl_24_ie;
wire swPinCtrl_24_pue;
wire swPinCtrl_24_ds;
wire swPinCtrl_25_oval;
wire swPinCtrl_25_oe;
wire swPinCtrl_25_ie;
wire swPinCtrl_25_pue;
wire swPinCtrl_25_ds;
wire swPinCtrl_26_oval;
wire swPinCtrl_26_oe;
wire swPinCtrl_26_ie;
wire swPinCtrl_26_pue;
wire swPinCtrl_26_ds;
wire swPinCtrl_27_oval;
wire swPinCtrl_27_oe;
wire swPinCtrl_27_ie;
wire swPinCtrl_27_pue;
wire swPinCtrl_27_ds;
wire swPinCtrl_28_oval;
wire swPinCtrl_28_oe;
wire swPinCtrl_28_ie;
wire swPinCtrl_28_pue;
wire swPinCtrl_28_ds;
wire swPinCtrl_29_oval;
wire swPinCtrl_29_oe;
wire swPinCtrl_29_ie;
wire swPinCtrl_29_pue;
wire swPinCtrl_29_ds;
wire swPinCtrl_30_oval;
wire swPinCtrl_30_oe;
wire swPinCtrl_30_ie;
wire swPinCtrl_30_pue;
wire swPinCtrl_30_ds;
wire swPinCtrl_31_oval;
wire swPinCtrl_31_oe;
wire swPinCtrl_31_ie;
wire swPinCtrl_31_pue;
wire swPinCtrl_31_ds;
wire iof0Ctrl_0_oval;
wire iof0Ctrl_0_oe;
wire iof0Ctrl_0_ie;
wire iof0Ctrl_1_oval;
wire iof0Ctrl_1_oe;
wire iof0Ctrl_1_ie;
wire iof0Ctrl_2_oval;
wire iof0Ctrl_2_oe;
wire iof0Ctrl_2_ie;
wire iof0Ctrl_3_oval;
wire iof0Ctrl_3_oe;
wire iof0Ctrl_3_ie;
wire iof0Ctrl_4_oval;
wire iof0Ctrl_4_oe;
wire iof0Ctrl_4_ie;
wire iof0Ctrl_5_oval;
wire iof0Ctrl_5_oe;
wire iof0Ctrl_5_ie;
wire iof0Ctrl_6_oval;
wire iof0Ctrl_6_oe;
wire iof0Ctrl_6_ie;
wire iof0Ctrl_7_oval;
wire iof0Ctrl_7_oe;
wire iof0Ctrl_7_ie;
wire iof0Ctrl_8_oval;
wire iof0Ctrl_8_oe;
wire iof0Ctrl_8_ie;
wire iof0Ctrl_9_oval;
wire iof0Ctrl_9_oe;
wire iof0Ctrl_9_ie;
wire iof0Ctrl_10_oval;
wire iof0Ctrl_10_oe;
wire iof0Ctrl_10_ie;
wire iof0Ctrl_11_oval;
wire iof0Ctrl_11_oe;
wire iof0Ctrl_11_ie;
wire iof0Ctrl_12_oval;
wire iof0Ctrl_12_oe;
wire iof0Ctrl_12_ie;
wire iof0Ctrl_13_oval;
wire iof0Ctrl_13_oe;
wire iof0Ctrl_13_ie;
wire iof0Ctrl_14_oval;
wire iof0Ctrl_14_oe;
wire iof0Ctrl_14_ie;
wire iof0Ctrl_15_oval;
wire iof0Ctrl_15_oe;
wire iof0Ctrl_15_ie;
wire iof0Ctrl_16_oval;
wire iof0Ctrl_16_oe;
wire iof0Ctrl_16_ie;
wire iof0Ctrl_17_oval;
wire iof0Ctrl_17_oe;
wire iof0Ctrl_17_ie;
wire iof0Ctrl_18_oval;
wire iof0Ctrl_18_oe;
wire iof0Ctrl_18_ie;
wire iof0Ctrl_19_oval;
wire iof0Ctrl_19_oe;
wire iof0Ctrl_19_ie;
wire iof0Ctrl_20_oval;
wire iof0Ctrl_20_oe;
wire iof0Ctrl_20_ie;
wire iof0Ctrl_21_oval;
wire iof0Ctrl_21_oe;
wire iof0Ctrl_21_ie;
wire iof0Ctrl_22_oval;
wire iof0Ctrl_22_oe;
wire iof0Ctrl_22_ie;
wire iof0Ctrl_23_oval;
wire iof0Ctrl_23_oe;
wire iof0Ctrl_23_ie;
wire iof0Ctrl_24_oval;
wire iof0Ctrl_24_oe;
wire iof0Ctrl_24_ie;
wire iof0Ctrl_25_oval;
wire iof0Ctrl_25_oe;
wire iof0Ctrl_25_ie;
wire iof0Ctrl_26_oval;
wire iof0Ctrl_26_oe;
wire iof0Ctrl_26_ie;
wire iof0Ctrl_27_oval;
wire iof0Ctrl_27_oe;
wire iof0Ctrl_27_ie;
wire iof0Ctrl_28_oval;
wire iof0Ctrl_28_oe;
wire iof0Ctrl_28_ie;
wire iof0Ctrl_29_oval;
wire iof0Ctrl_29_oe;
wire iof0Ctrl_29_ie;
wire iof0Ctrl_30_oval;
wire iof0Ctrl_30_oe;
wire iof0Ctrl_30_ie;
wire iof0Ctrl_31_oval;
wire iof0Ctrl_31_oe;
wire iof0Ctrl_31_ie;
wire iof1Ctrl_0_oval;
wire iof1Ctrl_0_oe;
wire iof1Ctrl_0_ie;
wire iof1Ctrl_1_oval;
wire iof1Ctrl_1_oe;
wire iof1Ctrl_1_ie;
wire iof1Ctrl_2_oval;
wire iof1Ctrl_2_oe;
wire iof1Ctrl_2_ie;
wire iof1Ctrl_3_oval;
wire iof1Ctrl_3_oe;
wire iof1Ctrl_3_ie;
wire iof1Ctrl_4_oval;
wire iof1Ctrl_4_oe;
wire iof1Ctrl_4_ie;
wire iof1Ctrl_5_oval;
wire iof1Ctrl_5_oe;
wire iof1Ctrl_5_ie;
wire iof1Ctrl_6_oval;
wire iof1Ctrl_6_oe;
wire iof1Ctrl_6_ie;
wire iof1Ctrl_7_oval;
wire iof1Ctrl_7_oe;
wire iof1Ctrl_7_ie;
wire iof1Ctrl_8_oval;
wire iof1Ctrl_8_oe;
wire iof1Ctrl_8_ie;
wire iof1Ctrl_9_oval;
wire iof1Ctrl_9_oe;
wire iof1Ctrl_9_ie;
wire iof1Ctrl_10_oval;
wire iof1Ctrl_10_oe;
wire iof1Ctrl_10_ie;
wire iof1Ctrl_11_oval;
wire iof1Ctrl_11_oe;
wire iof1Ctrl_11_ie;
wire iof1Ctrl_12_oval;
wire iof1Ctrl_12_oe;
wire iof1Ctrl_12_ie;
wire iof1Ctrl_13_oval;
wire iof1Ctrl_13_oe;
wire iof1Ctrl_13_ie;
wire iof1Ctrl_14_oval;
wire iof1Ctrl_14_oe;
wire iof1Ctrl_14_ie;
wire iof1Ctrl_15_oval;
wire iof1Ctrl_15_oe;
wire iof1Ctrl_15_ie;
wire iof1Ctrl_16_oval;
wire iof1Ctrl_16_oe;
wire iof1Ctrl_16_ie;
wire iof1Ctrl_17_oval;
wire iof1Ctrl_17_oe;
wire iof1Ctrl_17_ie;
wire iof1Ctrl_18_oval;
wire iof1Ctrl_18_oe;
wire iof1Ctrl_18_ie;
wire iof1Ctrl_19_oval;
wire iof1Ctrl_19_oe;
wire iof1Ctrl_19_ie;
wire iof1Ctrl_20_oval;
wire iof1Ctrl_20_oe;
wire iof1Ctrl_20_ie;
wire iof1Ctrl_21_oval;
wire iof1Ctrl_21_oe;
wire iof1Ctrl_21_ie;
wire iof1Ctrl_22_oval;
wire iof1Ctrl_22_oe;
wire iof1Ctrl_22_ie;
wire iof1Ctrl_23_oval;
wire iof1Ctrl_23_oe;
wire iof1Ctrl_23_ie;
wire iof1Ctrl_24_oval;
wire iof1Ctrl_24_oe;
wire iof1Ctrl_24_ie;
wire iof1Ctrl_25_oval;
wire iof1Ctrl_25_oe;
wire iof1Ctrl_25_ie;
wire iof1Ctrl_26_oval;
wire iof1Ctrl_26_oe;
wire iof1Ctrl_26_ie;
wire iof1Ctrl_27_oval;
wire iof1Ctrl_27_oe;
wire iof1Ctrl_27_ie;
wire iof1Ctrl_28_oval;
wire iof1Ctrl_28_oe;
wire iof1Ctrl_28_ie;
wire iof1Ctrl_29_oval;
wire iof1Ctrl_29_oe;
wire iof1Ctrl_29_ie;
wire iof1Ctrl_30_oval;
wire iof1Ctrl_30_oe;
wire iof1Ctrl_30_ie;
wire iof1Ctrl_31_oval;
wire iof1Ctrl_31_oe;
wire iof1Ctrl_31_ie;
wire iofCtrl_0_oval;
wire iofCtrl_0_oe;
wire iofCtrl_0_ie;
wire iofCtrl_1_oval;
wire iofCtrl_1_oe;
wire iofCtrl_1_ie;
wire iofCtrl_2_oval;
wire iofCtrl_2_oe;
wire iofCtrl_2_ie;
wire iofCtrl_3_oval;
wire iofCtrl_3_oe;
wire iofCtrl_3_ie;
wire iofCtrl_4_oval;
wire iofCtrl_4_oe;
wire iofCtrl_4_ie;
wire iofCtrl_5_oval;
wire iofCtrl_5_oe;
wire iofCtrl_5_ie;
wire iofCtrl_6_oval;
wire iofCtrl_6_oe;
wire iofCtrl_6_ie;
wire iofCtrl_7_oval;
wire iofCtrl_7_oe;
wire iofCtrl_7_ie;
wire iofCtrl_8_oval;
wire iofCtrl_8_oe;
wire iofCtrl_8_ie;
wire iofCtrl_9_oval;
wire iofCtrl_9_oe;
wire iofCtrl_9_ie;
wire iofCtrl_10_oval;
wire iofCtrl_10_oe;
wire iofCtrl_10_ie;
wire iofCtrl_11_oval;
wire iofCtrl_11_oe;
wire iofCtrl_11_ie;
wire iofCtrl_12_oval;
wire iofCtrl_12_oe;
wire iofCtrl_12_ie;
wire iofCtrl_13_oval;
wire iofCtrl_13_oe;
wire iofCtrl_13_ie;
wire iofCtrl_14_oval;
wire iofCtrl_14_oe;
wire iofCtrl_14_ie;
wire iofCtrl_15_oval;
wire iofCtrl_15_oe;
wire iofCtrl_15_ie;
wire iofCtrl_16_oval;
wire iofCtrl_16_oe;
wire iofCtrl_16_ie;
wire iofCtrl_17_oval;
wire iofCtrl_17_oe;
wire iofCtrl_17_ie;
wire iofCtrl_18_oval;
wire iofCtrl_18_oe;
wire iofCtrl_18_ie;
wire iofCtrl_19_oval;
wire iofCtrl_19_oe;
wire iofCtrl_19_ie;
wire iofCtrl_20_oval;
wire iofCtrl_20_oe;
wire iofCtrl_20_ie;
wire iofCtrl_21_oval;
wire iofCtrl_21_oe;
wire iofCtrl_21_ie;
wire iofCtrl_22_oval;
wire iofCtrl_22_oe;
wire iofCtrl_22_ie;
wire iofCtrl_23_oval;
wire iofCtrl_23_oe;
wire iofCtrl_23_ie;
wire iofCtrl_24_oval;
wire iofCtrl_24_oe;
wire iofCtrl_24_ie;
wire iofCtrl_25_oval;
wire iofCtrl_25_oe;
wire iofCtrl_25_ie;
wire iofCtrl_26_oval;
wire iofCtrl_26_oe;
wire iofCtrl_26_ie;
wire iofCtrl_27_oval;
wire iofCtrl_27_oe;
wire iofCtrl_27_ie;
wire iofCtrl_28_oval;
wire iofCtrl_28_oe;
wire iofCtrl_28_ie;
wire iofCtrl_29_oval;
wire iofCtrl_29_oe;
wire iofCtrl_29_ie;
wire iofCtrl_30_oval;
wire iofCtrl_30_oe;
wire iofCtrl_30_ie;
wire iofCtrl_31_oval;
wire iofCtrl_31_oe;
wire iofCtrl_31_ie;
wire iofPlusSwPinCtrl_0_oval;
wire iofPlusSwPinCtrl_0_oe;
wire iofPlusSwPinCtrl_0_ie;
wire iofPlusSwPinCtrl_0_pue;
wire iofPlusSwPinCtrl_0_ds;
wire iofPlusSwPinCtrl_1_oval;
wire iofPlusSwPinCtrl_1_oe;
wire iofPlusSwPinCtrl_1_ie;
wire iofPlusSwPinCtrl_1_pue;
wire iofPlusSwPinCtrl_1_ds;
wire iofPlusSwPinCtrl_2_oval;
wire iofPlusSwPinCtrl_2_oe;
wire iofPlusSwPinCtrl_2_ie;
wire iofPlusSwPinCtrl_2_pue;
wire iofPlusSwPinCtrl_2_ds;
wire iofPlusSwPinCtrl_3_oval;
wire iofPlusSwPinCtrl_3_oe;
wire iofPlusSwPinCtrl_3_ie;
wire iofPlusSwPinCtrl_3_pue;
wire iofPlusSwPinCtrl_3_ds;
wire iofPlusSwPinCtrl_4_oval;
wire iofPlusSwPinCtrl_4_oe;
wire iofPlusSwPinCtrl_4_ie;
wire iofPlusSwPinCtrl_4_pue;
wire iofPlusSwPinCtrl_4_ds;
wire iofPlusSwPinCtrl_5_oval;
wire iofPlusSwPinCtrl_5_oe;
wire iofPlusSwPinCtrl_5_ie;
wire iofPlusSwPinCtrl_5_pue;
wire iofPlusSwPinCtrl_5_ds;
wire iofPlusSwPinCtrl_6_oval;
wire iofPlusSwPinCtrl_6_oe;
wire iofPlusSwPinCtrl_6_ie;
wire iofPlusSwPinCtrl_6_pue;
wire iofPlusSwPinCtrl_6_ds;
wire iofPlusSwPinCtrl_7_oval;
wire iofPlusSwPinCtrl_7_oe;
wire iofPlusSwPinCtrl_7_ie;
wire iofPlusSwPinCtrl_7_pue;
wire iofPlusSwPinCtrl_7_ds;
wire iofPlusSwPinCtrl_8_oval;
wire iofPlusSwPinCtrl_8_oe;
wire iofPlusSwPinCtrl_8_ie;
wire iofPlusSwPinCtrl_8_pue;
wire iofPlusSwPinCtrl_8_ds;
wire iofPlusSwPinCtrl_9_oval;
wire iofPlusSwPinCtrl_9_oe;
wire iofPlusSwPinCtrl_9_ie;
wire iofPlusSwPinCtrl_9_pue;
wire iofPlusSwPinCtrl_9_ds;
wire iofPlusSwPinCtrl_10_oval;
wire iofPlusSwPinCtrl_10_oe;
wire iofPlusSwPinCtrl_10_ie;
wire iofPlusSwPinCtrl_10_pue;
wire iofPlusSwPinCtrl_10_ds;
wire iofPlusSwPinCtrl_11_oval;
wire iofPlusSwPinCtrl_11_oe;
wire iofPlusSwPinCtrl_11_ie;
wire iofPlusSwPinCtrl_11_pue;
wire iofPlusSwPinCtrl_11_ds;
wire iofPlusSwPinCtrl_12_oval;
wire iofPlusSwPinCtrl_12_oe;
wire iofPlusSwPinCtrl_12_ie;
wire iofPlusSwPinCtrl_12_pue;
wire iofPlusSwPinCtrl_12_ds;
wire iofPlusSwPinCtrl_13_oval;
wire iofPlusSwPinCtrl_13_oe;
wire iofPlusSwPinCtrl_13_ie;
wire iofPlusSwPinCtrl_13_pue;
wire iofPlusSwPinCtrl_13_ds;
wire iofPlusSwPinCtrl_14_oval;
wire iofPlusSwPinCtrl_14_oe;
wire iofPlusSwPinCtrl_14_ie;
wire iofPlusSwPinCtrl_14_pue;
wire iofPlusSwPinCtrl_14_ds;
wire iofPlusSwPinCtrl_15_oval;
wire iofPlusSwPinCtrl_15_oe;
wire iofPlusSwPinCtrl_15_ie;
wire iofPlusSwPinCtrl_15_pue;
wire iofPlusSwPinCtrl_15_ds;
wire iofPlusSwPinCtrl_16_oval;
wire iofPlusSwPinCtrl_16_oe;
wire iofPlusSwPinCtrl_16_ie;
wire iofPlusSwPinCtrl_16_pue;
wire iofPlusSwPinCtrl_16_ds;
wire iofPlusSwPinCtrl_17_oval;
wire iofPlusSwPinCtrl_17_oe;
wire iofPlusSwPinCtrl_17_ie;
wire iofPlusSwPinCtrl_17_pue;
wire iofPlusSwPinCtrl_17_ds;
wire iofPlusSwPinCtrl_18_oval;
wire iofPlusSwPinCtrl_18_oe;
wire iofPlusSwPinCtrl_18_ie;
wire iofPlusSwPinCtrl_18_pue;
wire iofPlusSwPinCtrl_18_ds;
wire iofPlusSwPinCtrl_19_oval;
wire iofPlusSwPinCtrl_19_oe;
wire iofPlusSwPinCtrl_19_ie;
wire iofPlusSwPinCtrl_19_pue;
wire iofPlusSwPinCtrl_19_ds;
wire iofPlusSwPinCtrl_20_oval;
wire iofPlusSwPinCtrl_20_oe;
wire iofPlusSwPinCtrl_20_ie;
wire iofPlusSwPinCtrl_20_pue;
wire iofPlusSwPinCtrl_20_ds;
wire iofPlusSwPinCtrl_21_oval;
wire iofPlusSwPinCtrl_21_oe;
wire iofPlusSwPinCtrl_21_ie;
wire iofPlusSwPinCtrl_21_pue;
wire iofPlusSwPinCtrl_21_ds;
wire iofPlusSwPinCtrl_22_oval;
wire iofPlusSwPinCtrl_22_oe;
wire iofPlusSwPinCtrl_22_ie;
wire iofPlusSwPinCtrl_22_pue;
wire iofPlusSwPinCtrl_22_ds;
wire iofPlusSwPinCtrl_23_oval;
wire iofPlusSwPinCtrl_23_oe;
wire iofPlusSwPinCtrl_23_ie;
wire iofPlusSwPinCtrl_23_pue;
wire iofPlusSwPinCtrl_23_ds;
wire iofPlusSwPinCtrl_24_oval;
wire iofPlusSwPinCtrl_24_oe;
wire iofPlusSwPinCtrl_24_ie;
wire iofPlusSwPinCtrl_24_pue;
wire iofPlusSwPinCtrl_24_ds;
wire iofPlusSwPinCtrl_25_oval;
wire iofPlusSwPinCtrl_25_oe;
wire iofPlusSwPinCtrl_25_ie;
wire iofPlusSwPinCtrl_25_pue;
wire iofPlusSwPinCtrl_25_ds;
wire iofPlusSwPinCtrl_26_oval;
wire iofPlusSwPinCtrl_26_oe;
wire iofPlusSwPinCtrl_26_ie;
wire iofPlusSwPinCtrl_26_pue;
wire iofPlusSwPinCtrl_26_ds;
wire iofPlusSwPinCtrl_27_oval;
wire iofPlusSwPinCtrl_27_oe;
wire iofPlusSwPinCtrl_27_ie;
wire iofPlusSwPinCtrl_27_pue;
wire iofPlusSwPinCtrl_27_ds;
wire iofPlusSwPinCtrl_28_oval;
wire iofPlusSwPinCtrl_28_oe;
wire iofPlusSwPinCtrl_28_ie;
wire iofPlusSwPinCtrl_28_pue;
wire iofPlusSwPinCtrl_28_ds;
wire iofPlusSwPinCtrl_29_oval;
wire iofPlusSwPinCtrl_29_oe;
wire iofPlusSwPinCtrl_29_ie;
wire iofPlusSwPinCtrl_29_pue;
wire iofPlusSwPinCtrl_29_ds;
wire iofPlusSwPinCtrl_30_oval;
wire iofPlusSwPinCtrl_30_oe;
wire iofPlusSwPinCtrl_30_ie;
wire iofPlusSwPinCtrl_30_pue;
wire iofPlusSwPinCtrl_30_ds;
wire iofPlusSwPinCtrl_31_oval;
wire iofPlusSwPinCtrl_31_oe;
wire iofPlusSwPinCtrl_31_ie;
wire iofPlusSwPinCtrl_31_pue;
wire iofPlusSwPinCtrl_31_ds;
wire T_7569;
wire T_7570;
wire T_7571;
wire T_7572;
wire T_7573;
wire GEN_201;
wire GEN_202;
wire GEN_203;
wire GEN_204;
wire GEN_205;
wire GEN_206;
wire T_7574;
wire T_7575_oval;
wire T_7575_oe;
wire T_7575_ie;
wire T_7579;
wire T_7580_oval;
wire T_7580_oe;
wire T_7580_ie;
wire T_7580_pue;
wire T_7580_ds;
wire T_7586;
wire T_7587;
wire T_7588;
wire T_7589;
wire T_7590;
wire T_7591;
wire T_7592;
wire T_7593;
wire T_7594;
wire T_7595;
wire T_7596;
wire T_7597;
wire T_7598;
wire T_7599;
wire T_7600;
wire T_7601;
wire T_7602;
wire T_7603;
wire T_7605;
wire T_7606;
wire T_7607;
wire T_7608;
wire T_7609;
wire GEN_207;
wire GEN_208;
wire GEN_209;
wire GEN_210;
wire GEN_211;
wire GEN_212;
wire T_7610;
wire T_7611_oval;
wire T_7611_oe;
wire T_7611_ie;
wire T_7615;
wire T_7616_oval;
wire T_7616_oe;
wire T_7616_ie;
wire T_7616_pue;
wire T_7616_ds;
wire T_7622;
wire T_7623;
wire T_7624;
wire T_7625;
wire T_7626;
wire T_7627;
wire T_7628;
wire T_7629;
wire T_7630;
wire T_7631;
wire T_7632;
wire T_7633;
wire T_7634;
wire T_7635;
wire T_7636;
wire T_7637;
wire T_7638;
wire T_7639;
wire T_7641;
wire T_7642;
wire T_7643;
wire T_7644;
wire T_7645;
wire GEN_213;
wire GEN_214;
wire GEN_215;
wire GEN_216;
wire GEN_217;
wire GEN_218;
wire T_7646;
wire T_7647_oval;
wire T_7647_oe;
wire T_7647_ie;
wire T_7651;
wire T_7652_oval;
wire T_7652_oe;
wire T_7652_ie;
wire T_7652_pue;
wire T_7652_ds;
wire T_7658;
wire T_7659;
wire T_7660;
wire T_7661;
wire T_7662;
wire T_7663;
wire T_7664;
wire T_7665;
wire T_7666;
wire T_7667;
wire T_7668;
wire T_7669;
wire T_7670;
wire T_7671;
wire T_7672;
wire T_7673;
wire T_7674;
wire T_7675;
wire T_7677;
wire T_7678;
wire T_7679;
wire T_7680;
wire T_7681;
wire GEN_219;
wire GEN_220;
wire GEN_221;
wire GEN_222;
wire GEN_223;
wire GEN_224;
wire T_7682;
wire T_7683_oval;
wire T_7683_oe;
wire T_7683_ie;
wire T_7687;
wire T_7688_oval;
wire T_7688_oe;
wire T_7688_ie;
wire T_7688_pue;
wire T_7688_ds;
wire T_7694;
wire T_7695;
wire T_7696;
wire T_7697;
wire T_7698;
wire T_7699;
wire T_7700;
wire T_7701;
wire T_7702;
wire T_7703;
wire T_7704;
wire T_7705;
wire T_7706;
wire T_7707;
wire T_7708;
wire T_7709;
wire T_7710;
wire T_7711;
wire T_7713;
wire T_7714;
wire T_7715;
wire T_7716;
wire T_7717;
wire GEN_225;
wire GEN_226;
wire GEN_227;
wire GEN_228;
wire GEN_229;
wire GEN_230;
wire T_7718;
wire T_7719_oval;
wire T_7719_oe;
wire T_7719_ie;
wire T_7723;
wire T_7724_oval;
wire T_7724_oe;
wire T_7724_ie;
wire T_7724_pue;
wire T_7724_ds;
wire T_7730;
wire T_7731;
wire T_7732;
wire T_7733;
wire T_7734;
wire T_7735;
wire T_7736;
wire T_7737;
wire T_7738;
wire T_7739;
wire T_7740;
wire T_7741;
wire T_7742;
wire T_7743;
wire T_7744;
wire T_7745;
wire T_7746;
wire T_7747;
wire T_7749;
wire T_7750;
wire T_7751;
wire T_7752;
wire T_7753;
wire GEN_231;
wire GEN_232;
wire GEN_233;
wire GEN_234;
wire GEN_235;
wire GEN_236;
wire T_7754;
wire T_7755_oval;
wire T_7755_oe;
wire T_7755_ie;
wire T_7759;
wire T_7760_oval;
wire T_7760_oe;
wire T_7760_ie;
wire T_7760_pue;
wire T_7760_ds;
wire T_7766;
wire T_7767;
wire T_7768;
wire T_7769;
wire T_7770;
wire T_7771;
wire T_7772;
wire T_7773;
wire T_7774;
wire T_7775;
wire T_7776;
wire T_7777;
wire T_7778;
wire T_7779;
wire T_7780;
wire T_7781;
wire T_7782;
wire T_7783;
wire T_7785;
wire T_7786;
wire T_7787;
wire T_7788;
wire T_7789;
wire GEN_237;
wire GEN_238;
wire GEN_239;
wire GEN_240;
wire GEN_241;
wire GEN_242;
wire T_7790;
wire T_7791_oval;
wire T_7791_oe;
wire T_7791_ie;
wire T_7795;
wire T_7796_oval;
wire T_7796_oe;
wire T_7796_ie;
wire T_7796_pue;
wire T_7796_ds;
wire T_7802;
wire T_7803;
wire T_7804;
wire T_7805;
wire T_7806;
wire T_7807;
wire T_7808;
wire T_7809;
wire T_7810;
wire T_7811;
wire T_7812;
wire T_7813;
wire T_7814;
wire T_7815;
wire T_7816;
wire T_7817;
wire T_7818;
wire T_7819;
wire T_7821;
wire T_7822;
wire T_7823;
wire T_7824;
wire T_7825;
wire GEN_243;
wire GEN_244;
wire GEN_245;
wire GEN_246;
wire GEN_247;
wire GEN_248;
wire T_7826;
wire T_7827_oval;
wire T_7827_oe;
wire T_7827_ie;
wire T_7831;
wire T_7832_oval;
wire T_7832_oe;
wire T_7832_ie;
wire T_7832_pue;
wire T_7832_ds;
wire T_7838;
wire T_7839;
wire T_7840;
wire T_7841;
wire T_7842;
wire T_7843;
wire T_7844;
wire T_7845;
wire T_7846;
wire T_7847;
wire T_7848;
wire T_7849;
wire T_7850;
wire T_7851;
wire T_7852;
wire T_7853;
wire T_7854;
wire T_7855;
wire T_7857;
wire T_7858;
wire T_7859;
wire T_7860;
wire T_7861;
wire GEN_249;
wire GEN_250;
wire GEN_251;
wire GEN_252;
wire GEN_253;
wire GEN_254;
wire T_7862;
wire T_7863_oval;
wire T_7863_oe;
wire T_7863_ie;
wire T_7867;
wire T_7868_oval;
wire T_7868_oe;
wire T_7868_ie;
wire T_7868_pue;
wire T_7868_ds;
wire T_7874;
wire T_7875;
wire T_7876;
wire T_7877;
wire T_7878;
wire T_7879;
wire T_7880;
wire T_7881;
wire T_7882;
wire T_7883;
wire T_7884;
wire T_7885;
wire T_7886;
wire T_7887;
wire T_7888;
wire T_7889;
wire T_7890;
wire T_7891;
wire T_7893;
wire T_7894;
wire T_7895;
wire T_7896;
wire T_7897;
wire GEN_255;
wire GEN_256;
wire GEN_257;
wire GEN_258;
wire GEN_259;
wire GEN_260;
wire T_7898;
wire T_7899_oval;
wire T_7899_oe;
wire T_7899_ie;
wire T_7903;
wire T_7904_oval;
wire T_7904_oe;
wire T_7904_ie;
wire T_7904_pue;
wire T_7904_ds;
wire T_7910;
wire T_7911;
wire T_7912;
wire T_7913;
wire T_7914;
wire T_7915;
wire T_7916;
wire T_7917;
wire T_7918;
wire T_7919;
wire T_7920;
wire T_7921;
wire T_7922;
wire T_7923;
wire T_7924;
wire T_7925;
wire T_7926;
wire T_7927;
wire T_7929;
wire T_7930;
wire T_7931;
wire T_7932;
wire T_7933;
wire GEN_261;
wire GEN_262;
wire GEN_263;
wire GEN_264;
wire GEN_265;
wire GEN_266;
wire T_7934;
wire T_7935_oval;
wire T_7935_oe;
wire T_7935_ie;
wire T_7939;
wire T_7940_oval;
wire T_7940_oe;
wire T_7940_ie;
wire T_7940_pue;
wire T_7940_ds;
wire T_7946;
wire T_7947;
wire T_7948;
wire T_7949;
wire T_7950;
wire T_7951;
wire T_7952;
wire T_7953;
wire T_7954;
wire T_7955;
wire T_7956;
wire T_7957;
wire T_7958;
wire T_7959;
wire T_7960;
wire T_7961;
wire T_7962;
wire T_7963;
wire T_7965;
wire T_7966;
wire T_7967;
wire T_7968;
wire T_7969;
wire GEN_267;
wire GEN_268;
wire GEN_269;
wire GEN_270;
wire GEN_271;
wire GEN_272;
wire T_7970;
wire T_7971_oval;
wire T_7971_oe;
wire T_7971_ie;
wire T_7975;
wire T_7976_oval;
wire T_7976_oe;
wire T_7976_ie;
wire T_7976_pue;
wire T_7976_ds;
wire T_7982;
wire T_7983;
wire T_7984;
wire T_7985;
wire T_7986;
wire T_7987;
wire T_7988;
wire T_7989;
wire T_7990;
wire T_7991;
wire T_7992;
wire T_7993;
wire T_7994;
wire T_7995;
wire T_7996;
wire T_7997;
wire T_7998;
wire T_7999;
wire T_8001;
wire T_8002;
wire T_8003;
wire T_8004;
wire T_8005;
wire GEN_273;
wire GEN_274;
wire GEN_275;
wire GEN_276;
wire GEN_277;
wire GEN_278;
wire T_8006;
wire T_8007_oval;
wire T_8007_oe;
wire T_8007_ie;
wire T_8011;
wire T_8012_oval;
wire T_8012_oe;
wire T_8012_ie;
wire T_8012_pue;
wire T_8012_ds;
wire T_8018;
wire T_8019;
wire T_8020;
wire T_8021;
wire T_8022;
wire T_8023;
wire T_8024;
wire T_8025;
wire T_8026;
wire T_8027;
wire T_8028;
wire T_8029;
wire T_8030;
wire T_8031;
wire T_8032;
wire T_8033;
wire T_8034;
wire T_8035;
wire T_8037;
wire T_8038;
wire T_8039;
wire T_8040;
wire T_8041;
wire GEN_279;
wire GEN_280;
wire GEN_281;
wire GEN_282;
wire GEN_283;
wire GEN_284;
wire T_8042;
wire T_8043_oval;
wire T_8043_oe;
wire T_8043_ie;
wire T_8047;
wire T_8048_oval;
wire T_8048_oe;
wire T_8048_ie;
wire T_8048_pue;
wire T_8048_ds;
wire T_8054;
wire T_8055;
wire T_8056;
wire T_8057;
wire T_8058;
wire T_8059;
wire T_8060;
wire T_8061;
wire T_8062;
wire T_8063;
wire T_8064;
wire T_8065;
wire T_8066;
wire T_8067;
wire T_8068;
wire T_8069;
wire T_8070;
wire T_8071;
wire T_8073;
wire T_8074;
wire T_8075;
wire T_8076;
wire T_8077;
wire GEN_285;
wire GEN_286;
wire GEN_287;
wire GEN_288;
wire GEN_289;
wire GEN_290;
wire T_8078;
wire T_8079_oval;
wire T_8079_oe;
wire T_8079_ie;
wire T_8083;
wire T_8084_oval;
wire T_8084_oe;
wire T_8084_ie;
wire T_8084_pue;
wire T_8084_ds;
wire T_8090;
wire T_8091;
wire T_8092;
wire T_8093;
wire T_8094;
wire T_8095;
wire T_8096;
wire T_8097;
wire T_8098;
wire T_8099;
wire T_8100;
wire T_8101;
wire T_8102;
wire T_8103;
wire T_8104;
wire T_8105;
wire T_8106;
wire T_8107;
wire T_8109;
wire T_8110;
wire T_8111;
wire T_8112;
wire T_8113;
wire GEN_291;
wire GEN_292;
wire GEN_293;
wire GEN_294;
wire GEN_295;
wire GEN_296;
wire T_8114;
wire T_8115_oval;
wire T_8115_oe;
wire T_8115_ie;
wire T_8119;
wire T_8120_oval;
wire T_8120_oe;
wire T_8120_ie;
wire T_8120_pue;
wire T_8120_ds;
wire T_8126;
wire T_8127;
wire T_8128;
wire T_8129;
wire T_8130;
wire T_8131;
wire T_8132;
wire T_8133;
wire T_8134;
wire T_8135;
wire T_8136;
wire T_8137;
wire T_8138;
wire T_8139;
wire T_8140;
wire T_8141;
wire T_8142;
wire T_8143;
wire T_8145;
wire T_8146;
wire T_8147;
wire T_8148;
wire T_8149;
wire GEN_297;
wire GEN_298;
wire GEN_299;
wire GEN_300;
wire GEN_301;
wire GEN_302;
wire T_8150;
wire T_8151_oval;
wire T_8151_oe;
wire T_8151_ie;
wire T_8155;
wire T_8156_oval;
wire T_8156_oe;
wire T_8156_ie;
wire T_8156_pue;
wire T_8156_ds;
wire T_8162;
wire T_8163;
wire T_8164;
wire T_8165;
wire T_8166;
wire T_8167;
wire T_8168;
wire T_8169;
wire T_8170;
wire T_8171;
wire T_8172;
wire T_8173;
wire T_8174;
wire T_8175;
wire T_8176;
wire T_8177;
wire T_8178;
wire T_8179;
wire T_8181;
wire T_8182;
wire T_8183;
wire T_8184;
wire T_8185;
wire GEN_303;
wire GEN_304;
wire GEN_305;
wire GEN_306;
wire GEN_307;
wire GEN_308;
wire T_8186;
wire T_8187_oval;
wire T_8187_oe;
wire T_8187_ie;
wire T_8191;
wire T_8192_oval;
wire T_8192_oe;
wire T_8192_ie;
wire T_8192_pue;
wire T_8192_ds;
wire T_8198;
wire T_8199;
wire T_8200;
wire T_8201;
wire T_8202;
wire T_8203;
wire T_8204;
wire T_8205;
wire T_8206;
wire T_8207;
wire T_8208;
wire T_8209;
wire T_8210;
wire T_8211;
wire T_8212;
wire T_8213;
wire T_8214;
wire T_8215;
wire T_8217;
wire T_8218;
wire T_8219;
wire T_8220;
wire T_8221;
wire GEN_309;
wire GEN_310;
wire GEN_311;
wire GEN_312;
wire GEN_313;
wire GEN_314;
wire T_8222;
wire T_8223_oval;
wire T_8223_oe;
wire T_8223_ie;
wire T_8227;
wire T_8228_oval;
wire T_8228_oe;
wire T_8228_ie;
wire T_8228_pue;
wire T_8228_ds;
wire T_8234;
wire T_8235;
wire T_8236;
wire T_8237;
wire T_8238;
wire T_8239;
wire T_8240;
wire T_8241;
wire T_8242;
wire T_8243;
wire T_8244;
wire T_8245;
wire T_8246;
wire T_8247;
wire T_8248;
wire T_8249;
wire T_8250;
wire T_8251;
wire T_8253;
wire T_8254;
wire T_8255;
wire T_8256;
wire T_8257;
wire GEN_315;
wire GEN_316;
wire GEN_317;
wire GEN_318;
wire GEN_319;
wire GEN_320;
wire T_8258;
wire T_8259_oval;
wire T_8259_oe;
wire T_8259_ie;
wire T_8263;
wire T_8264_oval;
wire T_8264_oe;
wire T_8264_ie;
wire T_8264_pue;
wire T_8264_ds;
wire T_8270;
wire T_8271;
wire T_8272;
wire T_8273;
wire T_8274;
wire T_8275;
wire T_8276;
wire T_8277;
wire T_8278;
wire T_8279;
wire T_8280;
wire T_8281;
wire T_8282;
wire T_8283;
wire T_8284;
wire T_8285;
wire T_8286;
wire T_8287;
wire T_8289;
wire T_8290;
wire T_8291;
wire T_8292;
wire T_8293;
wire GEN_321;
wire GEN_322;
wire GEN_323;
wire GEN_324;
wire GEN_325;
wire GEN_326;
wire T_8294;
wire T_8295_oval;
wire T_8295_oe;
wire T_8295_ie;
wire T_8299;
wire T_8300_oval;
wire T_8300_oe;
wire T_8300_ie;
wire T_8300_pue;
wire T_8300_ds;
wire T_8306;
wire T_8307;
wire T_8308;
wire T_8309;
wire T_8310;
wire T_8311;
wire T_8312;
wire T_8313;
wire T_8314;
wire T_8315;
wire T_8316;
wire T_8317;
wire T_8318;
wire T_8319;
wire T_8320;
wire T_8321;
wire T_8322;
wire T_8323;
wire T_8325;
wire T_8326;
wire T_8327;
wire T_8328;
wire T_8329;
wire GEN_327;
wire GEN_328;
wire GEN_329;
wire GEN_330;
wire GEN_331;
wire GEN_332;
wire T_8330;
wire T_8331_oval;
wire T_8331_oe;
wire T_8331_ie;
wire T_8335;
wire T_8336_oval;
wire T_8336_oe;
wire T_8336_ie;
wire T_8336_pue;
wire T_8336_ds;
wire T_8342;
wire T_8343;
wire T_8344;
wire T_8345;
wire T_8346;
wire T_8347;
wire T_8348;
wire T_8349;
wire T_8350;
wire T_8351;
wire T_8352;
wire T_8353;
wire T_8354;
wire T_8355;
wire T_8356;
wire T_8357;
wire T_8358;
wire T_8359;
wire T_8361;
wire T_8362;
wire T_8363;
wire T_8364;
wire T_8365;
wire GEN_333;
wire GEN_334;
wire GEN_335;
wire GEN_336;
wire GEN_337;
wire GEN_338;
wire T_8366;
wire T_8367_oval;
wire T_8367_oe;
wire T_8367_ie;
wire T_8371;
wire T_8372_oval;
wire T_8372_oe;
wire T_8372_ie;
wire T_8372_pue;
wire T_8372_ds;
wire T_8378;
wire T_8379;
wire T_8380;
wire T_8381;
wire T_8382;
wire T_8383;
wire T_8384;
wire T_8385;
wire T_8386;
wire T_8387;
wire T_8388;
wire T_8389;
wire T_8390;
wire T_8391;
wire T_8392;
wire T_8393;
wire T_8394;
wire T_8395;
wire T_8397;
wire T_8398;
wire T_8399;
wire T_8400;
wire T_8401;
wire GEN_339;
wire GEN_340;
wire GEN_341;
wire GEN_342;
wire GEN_343;
wire GEN_344;
wire T_8402;
wire T_8403_oval;
wire T_8403_oe;
wire T_8403_ie;
wire T_8407;
wire T_8408_oval;
wire T_8408_oe;
wire T_8408_ie;
wire T_8408_pue;
wire T_8408_ds;
wire T_8414;
wire T_8415;
wire T_8416;
wire T_8417;
wire T_8418;
wire T_8419;
wire T_8420;
wire T_8421;
wire T_8422;
wire T_8423;
wire T_8424;
wire T_8425;
wire T_8426;
wire T_8427;
wire T_8428;
wire T_8429;
wire T_8430;
wire T_8431;
wire T_8433;
wire T_8434;
wire T_8435;
wire T_8436;
wire T_8437;
wire GEN_345;
wire GEN_346;
wire GEN_347;
wire GEN_348;
wire GEN_349;
wire GEN_350;
wire T_8438;
wire T_8439_oval;
wire T_8439_oe;
wire T_8439_ie;
wire T_8443;
wire T_8444_oval;
wire T_8444_oe;
wire T_8444_ie;
wire T_8444_pue;
wire T_8444_ds;
wire T_8450;
wire T_8451;
wire T_8452;
wire T_8453;
wire T_8454;
wire T_8455;
wire T_8456;
wire T_8457;
wire T_8458;
wire T_8459;
wire T_8460;
wire T_8461;
wire T_8462;
wire T_8463;
wire T_8464;
wire T_8465;
wire T_8466;
wire T_8467;
wire T_8469;
wire T_8470;
wire T_8471;
wire T_8472;
wire T_8473;
wire GEN_351;
wire GEN_352;
wire GEN_353;
wire GEN_354;
wire GEN_355;
wire GEN_356;
wire T_8474;
wire T_8475_oval;
wire T_8475_oe;
wire T_8475_ie;
wire T_8479;
wire T_8480_oval;
wire T_8480_oe;
wire T_8480_ie;
wire T_8480_pue;
wire T_8480_ds;
wire T_8486;
wire T_8487;
wire T_8488;
wire T_8489;
wire T_8490;
wire T_8491;
wire T_8492;
wire T_8493;
wire T_8494;
wire T_8495;
wire T_8496;
wire T_8497;
wire T_8498;
wire T_8499;
wire T_8500;
wire T_8501;
wire T_8502;
wire T_8503;
wire T_8505;
wire T_8506;
wire T_8507;
wire T_8508;
wire T_8509;
wire GEN_357;
wire GEN_358;
wire GEN_359;
wire GEN_360;
wire GEN_361;
wire GEN_362;
wire T_8510;
wire T_8511_oval;
wire T_8511_oe;
wire T_8511_ie;
wire T_8515;
wire T_8516_oval;
wire T_8516_oe;
wire T_8516_ie;
wire T_8516_pue;
wire T_8516_ds;
wire T_8522;
wire T_8523;
wire T_8524;
wire T_8525;
wire T_8526;
wire T_8527;
wire T_8528;
wire T_8529;
wire T_8530;
wire T_8531;
wire T_8532;
wire T_8533;
wire T_8534;
wire T_8535;
wire T_8536;
wire T_8537;
wire T_8538;
wire T_8539;
wire T_8541;
wire T_8542;
wire T_8543;
wire T_8544;
wire T_8545;
wire GEN_363;
wire GEN_364;
wire GEN_365;
wire GEN_366;
wire GEN_367;
wire GEN_368;
wire T_8546;
wire T_8547_oval;
wire T_8547_oe;
wire T_8547_ie;
wire T_8551;
wire T_8552_oval;
wire T_8552_oe;
wire T_8552_ie;
wire T_8552_pue;
wire T_8552_ds;
wire T_8558;
wire T_8559;
wire T_8560;
wire T_8561;
wire T_8562;
wire T_8563;
wire T_8564;
wire T_8565;
wire T_8566;
wire T_8567;
wire T_8568;
wire T_8569;
wire T_8570;
wire T_8571;
wire T_8572;
wire T_8573;
wire T_8574;
wire T_8575;
wire T_8577;
wire T_8578;
wire T_8579;
wire T_8580;
wire T_8581;
wire GEN_369;
wire GEN_370;
wire GEN_371;
wire GEN_372;
wire GEN_373;
wire GEN_374;
wire T_8582;
wire T_8583_oval;
wire T_8583_oe;
wire T_8583_ie;
wire T_8587;
wire T_8588_oval;
wire T_8588_oe;
wire T_8588_ie;
wire T_8588_pue;
wire T_8588_ds;
wire T_8594;
wire T_8595;
wire T_8596;
wire T_8597;
wire T_8598;
wire T_8599;
wire T_8600;
wire T_8601;
wire T_8602;
wire T_8603;
wire T_8604;
wire T_8605;
wire T_8606;
wire T_8607;
wire T_8608;
wire T_8609;
wire T_8610;
wire T_8611;
wire T_8613;
wire T_8614;
wire T_8615;
wire T_8616;
wire T_8617;
wire GEN_375;
wire GEN_376;
wire GEN_377;
wire GEN_378;
wire GEN_379;
wire GEN_380;
wire T_8618;
wire T_8619_oval;
wire T_8619_oe;
wire T_8619_ie;
wire T_8623;
wire T_8624_oval;
wire T_8624_oe;
wire T_8624_ie;
wire T_8624_pue;
wire T_8624_ds;
wire T_8630;
wire T_8631;
wire T_8632;
wire T_8633;
wire T_8634;
wire T_8635;
wire T_8636;
wire T_8637;
wire T_8638;
wire T_8639;
wire T_8640;
wire T_8641;
wire T_8642;
wire T_8643;
wire T_8644;
wire T_8645;
wire T_8646;
wire T_8647;
wire T_8649;
wire T_8650;
wire T_8651;
wire T_8652;
wire T_8653;
wire GEN_381;
wire GEN_382;
wire GEN_383;
wire GEN_384;
wire GEN_385;
wire GEN_386;
wire T_8654;
wire T_8655_oval;
wire T_8655_oe;
wire T_8655_ie;
wire T_8659;
wire T_8660_oval;
wire T_8660_oe;
wire T_8660_ie;
wire T_8660_pue;
wire T_8660_ds;
wire T_8666;
wire T_8667;
wire T_8668;
wire T_8669;
wire T_8670;
wire T_8671;
wire T_8672;
wire T_8673;
wire T_8674;
wire T_8675;
wire T_8676;
wire T_8677;
wire T_8678;
wire T_8679;
wire T_8680;
wire T_8681;
wire T_8682;
wire T_8683;
wire T_8685;
wire T_8686;
wire T_8687;
wire T_8688;
wire T_8689;
wire GEN_387;
wire GEN_388;
wire GEN_389;
wire GEN_390;
wire GEN_391;
wire GEN_392;
wire T_8690;
wire T_8691_oval;
wire T_8691_oe;
wire T_8691_ie;
wire T_8695;
wire T_8696_oval;
wire T_8696_oe;
wire T_8696_ie;
wire T_8696_pue;
wire T_8696_ds;
wire T_8702;
wire T_8703;
wire T_8704;
wire T_8705;
wire T_8706;
wire T_8707;
wire T_8708;
wire T_8709;
wire T_8710;
wire T_8711;
wire T_8712;
wire T_8713;
wire T_8714;
wire T_8715;
wire T_8716;
wire T_8717;
wire T_8718;
wire T_8719;
wire [2:0] GEN_6 = 3'b0;
wire [1:0] GEN_393 = 2'b0;
wire [2:0] GEN_394 = 3'b0;
wire [4:0] GEN_395 = 5'b0;
wire [28:0] GEN_396 = 29'b0;
wire [3:0] GEN_397 = 4'b0;
wire [31:0] GEN_398 = 32'b0;
sirv_AsyncResetRegVec_67 u_oeReg (
.clock(oeReg_clock),
.reset(oeReg_reset),
.io_d(oeReg_io_d),
.io_q(oeReg_io_q),
.io_en(oeReg_io_en)
);
sirv_AsyncResetRegVec_67 u_pueReg (
.clock(pueReg_clock),
.reset(pueReg_reset),
.io_d(pueReg_io_d),
.io_q(pueReg_io_q),
.io_en(pueReg_io_en)
);
sirv_AsyncResetRegVec_67 u_ieReg (
.clock(ieReg_clock),
.reset(ieReg_reset),
.io_d(ieReg_io_d),
.io_q(ieReg_io_q),
.io_en(ieReg_io_en)
);
sirv_AsyncResetRegVec_67 u_iofEnReg (
.clock(iofEnReg_clock),
.reset(iofEnReg_reset),
.io_d(iofEnReg_io_d),
.io_q(iofEnReg_io_q),
.io_en(iofEnReg_io_en)
);
assign io_interrupts_0_0 = T_7602;
assign io_interrupts_0_1 = T_7638;
assign io_interrupts_0_2 = T_7674;
assign io_interrupts_0_3 = T_7710;
assign io_interrupts_0_4 = T_7746;
assign io_interrupts_0_5 = T_7782;
assign io_interrupts_0_6 = T_7818;
assign io_interrupts_0_7 = T_7854;
assign io_interrupts_0_8 = T_7890;
assign io_interrupts_0_9 = T_7926;
assign io_interrupts_0_10 = T_7962;
assign io_interrupts_0_11 = T_7998;
assign io_interrupts_0_12 = T_8034;
assign io_interrupts_0_13 = T_8070;
assign io_interrupts_0_14 = T_8106;
assign io_interrupts_0_15 = T_8142;
assign io_interrupts_0_16 = T_8178;
assign io_interrupts_0_17 = T_8214;
assign io_interrupts_0_18 = T_8250;
assign io_interrupts_0_19 = T_8286;
assign io_interrupts_0_20 = T_8322;
assign io_interrupts_0_21 = T_8358;
assign io_interrupts_0_22 = T_8394;
assign io_interrupts_0_23 = T_8430;
assign io_interrupts_0_24 = T_8466;
assign io_interrupts_0_25 = T_8502;
assign io_interrupts_0_26 = T_8538;
assign io_interrupts_0_27 = T_8574;
assign io_interrupts_0_28 = T_8610;
assign io_interrupts_0_29 = T_8646;
assign io_interrupts_0_30 = T_8682;
assign io_interrupts_0_31 = T_8718;
assign io_in_0_a_ready = T_3295_ready;
assign io_in_0_b_valid = 1'h0;
assign io_in_0_b_bits_opcode = GEN_6;
assign io_in_0_b_bits_param = GEN_393;
assign io_in_0_b_bits_size = GEN_394;
assign io_in_0_b_bits_source = GEN_395;
assign io_in_0_b_bits_address = GEN_396;
assign io_in_0_b_bits_mask = GEN_397;
assign io_in_0_b_bits_data = GEN_398;
assign io_in_0_c_ready = 1'h1;
assign io_in_0_d_valid = T_3334_valid;
assign io_in_0_d_bits_opcode = {{2'd0}, T_3334_bits_read};
assign io_in_0_d_bits_param = T_6260_param;
assign io_in_0_d_bits_size = T_6260_size;
assign io_in_0_d_bits_source = T_6260_source;
assign io_in_0_d_bits_sink = T_6260_sink;
assign io_in_0_d_bits_addr_lo = T_6260_addr_lo;
assign io_in_0_d_bits_data = T_3334_bits_data;
assign io_in_0_d_bits_error = T_6260_error;
assign io_in_0_e_ready = 1'h1;
assign io_port_pins_0_o_oval = T_7587;
assign io_port_pins_0_o_oe = T_7580_oe;
assign io_port_pins_0_o_ie = T_7580_ie;
assign io_port_pins_0_o_pue = T_7580_pue;
assign io_port_pins_0_o_ds = T_7580_ds;
assign io_port_pins_1_o_oval = T_7623;
assign io_port_pins_1_o_oe = T_7616_oe;
assign io_port_pins_1_o_ie = T_7616_ie;
assign io_port_pins_1_o_pue = T_7616_pue;
assign io_port_pins_1_o_ds = T_7616_ds;
assign io_port_pins_2_o_oval = T_7659;
assign io_port_pins_2_o_oe = T_7652_oe;
assign io_port_pins_2_o_ie = T_7652_ie;
assign io_port_pins_2_o_pue = T_7652_pue;
assign io_port_pins_2_o_ds = T_7652_ds;
assign io_port_pins_3_o_oval = T_7695;
assign io_port_pins_3_o_oe = T_7688_oe;
assign io_port_pins_3_o_ie = T_7688_ie;
assign io_port_pins_3_o_pue = T_7688_pue;
assign io_port_pins_3_o_ds = T_7688_ds;
assign io_port_pins_4_o_oval = T_7731;
assign io_port_pins_4_o_oe = T_7724_oe;
assign io_port_pins_4_o_ie = T_7724_ie;
assign io_port_pins_4_o_pue = T_7724_pue;
assign io_port_pins_4_o_ds = T_7724_ds;
assign io_port_pins_5_o_oval = T_7767;
assign io_port_pins_5_o_oe = T_7760_oe;
assign io_port_pins_5_o_ie = T_7760_ie;
assign io_port_pins_5_o_pue = T_7760_pue;
assign io_port_pins_5_o_ds = T_7760_ds;
assign io_port_pins_6_o_oval = T_7803;
assign io_port_pins_6_o_oe = T_7796_oe;
assign io_port_pins_6_o_ie = T_7796_ie;
assign io_port_pins_6_o_pue = T_7796_pue;
assign io_port_pins_6_o_ds = T_7796_ds;
assign io_port_pins_7_o_oval = T_7839;
assign io_port_pins_7_o_oe = T_7832_oe;
assign io_port_pins_7_o_ie = T_7832_ie;
assign io_port_pins_7_o_pue = T_7832_pue;
assign io_port_pins_7_o_ds = T_7832_ds;
assign io_port_pins_8_o_oval = T_7875;
assign io_port_pins_8_o_oe = T_7868_oe;
assign io_port_pins_8_o_ie = T_7868_ie;
assign io_port_pins_8_o_pue = T_7868_pue;
assign io_port_pins_8_o_ds = T_7868_ds;
assign io_port_pins_9_o_oval = T_7911;
assign io_port_pins_9_o_oe = T_7904_oe;
assign io_port_pins_9_o_ie = T_7904_ie;
assign io_port_pins_9_o_pue = T_7904_pue;
assign io_port_pins_9_o_ds = T_7904_ds;
assign io_port_pins_10_o_oval = T_7947;
assign io_port_pins_10_o_oe = T_7940_oe;
assign io_port_pins_10_o_ie = T_7940_ie;
assign io_port_pins_10_o_pue = T_7940_pue;
assign io_port_pins_10_o_ds = T_7940_ds;
assign io_port_pins_11_o_oval = T_7983;
assign io_port_pins_11_o_oe = T_7976_oe;
assign io_port_pins_11_o_ie = T_7976_ie;
assign io_port_pins_11_o_pue = T_7976_pue;
assign io_port_pins_11_o_ds = T_7976_ds;
assign io_port_pins_12_o_oval = T_8019;
assign io_port_pins_12_o_oe = T_8012_oe;
assign io_port_pins_12_o_ie = T_8012_ie;
assign io_port_pins_12_o_pue = T_8012_pue;
assign io_port_pins_12_o_ds = T_8012_ds;
assign io_port_pins_13_o_oval = T_8055;
assign io_port_pins_13_o_oe = T_8048_oe;
assign io_port_pins_13_o_ie = T_8048_ie;
assign io_port_pins_13_o_pue = T_8048_pue;
assign io_port_pins_13_o_ds = T_8048_ds;
assign io_port_pins_14_o_oval = T_8091;
assign io_port_pins_14_o_oe = T_8084_oe;
assign io_port_pins_14_o_ie = T_8084_ie;
assign io_port_pins_14_o_pue = T_8084_pue;
assign io_port_pins_14_o_ds = T_8084_ds;
assign io_port_pins_15_o_oval = T_8127;
assign io_port_pins_15_o_oe = T_8120_oe;
assign io_port_pins_15_o_ie = T_8120_ie;
assign io_port_pins_15_o_pue = T_8120_pue;
assign io_port_pins_15_o_ds = T_8120_ds;
assign io_port_pins_16_o_oval = T_8163;
assign io_port_pins_16_o_oe = T_8156_oe;
assign io_port_pins_16_o_ie = T_8156_ie;
assign io_port_pins_16_o_pue = T_8156_pue;
assign io_port_pins_16_o_ds = T_8156_ds;
assign io_port_pins_17_o_oval = T_8199;
assign io_port_pins_17_o_oe = T_8192_oe;
assign io_port_pins_17_o_ie = T_8192_ie;
assign io_port_pins_17_o_pue = T_8192_pue;
assign io_port_pins_17_o_ds = T_8192_ds;
assign io_port_pins_18_o_oval = T_8235;
assign io_port_pins_18_o_oe = T_8228_oe;
assign io_port_pins_18_o_ie = T_8228_ie;
assign io_port_pins_18_o_pue = T_8228_pue;
assign io_port_pins_18_o_ds = T_8228_ds;
assign io_port_pins_19_o_oval = T_8271;
assign io_port_pins_19_o_oe = T_8264_oe;
assign io_port_pins_19_o_ie = T_8264_ie;
assign io_port_pins_19_o_pue = T_8264_pue;
assign io_port_pins_19_o_ds = T_8264_ds;
assign io_port_pins_20_o_oval = T_8307;
assign io_port_pins_20_o_oe = T_8300_oe;
assign io_port_pins_20_o_ie = T_8300_ie;
assign io_port_pins_20_o_pue = T_8300_pue;
assign io_port_pins_20_o_ds = T_8300_ds;
assign io_port_pins_21_o_oval = T_8343;
assign io_port_pins_21_o_oe = T_8336_oe;
assign io_port_pins_21_o_ie = T_8336_ie;
assign io_port_pins_21_o_pue = T_8336_pue;
assign io_port_pins_21_o_ds = T_8336_ds;
assign io_port_pins_22_o_oval = T_8379;
assign io_port_pins_22_o_oe = T_8372_oe;
assign io_port_pins_22_o_ie = T_8372_ie;
assign io_port_pins_22_o_pue = T_8372_pue;
assign io_port_pins_22_o_ds = T_8372_ds;
assign io_port_pins_23_o_oval = T_8415;
assign io_port_pins_23_o_oe = T_8408_oe;
assign io_port_pins_23_o_ie = T_8408_ie;
assign io_port_pins_23_o_pue = T_8408_pue;
assign io_port_pins_23_o_ds = T_8408_ds;
assign io_port_pins_24_o_oval = T_8451;
assign io_port_pins_24_o_oe = T_8444_oe;
assign io_port_pins_24_o_ie = T_8444_ie;
assign io_port_pins_24_o_pue = T_8444_pue;
assign io_port_pins_24_o_ds = T_8444_ds;
assign io_port_pins_25_o_oval = T_8487;
assign io_port_pins_25_o_oe = T_8480_oe;
assign io_port_pins_25_o_ie = T_8480_ie;
assign io_port_pins_25_o_pue = T_8480_pue;
assign io_port_pins_25_o_ds = T_8480_ds;
assign io_port_pins_26_o_oval = T_8523;
assign io_port_pins_26_o_oe = T_8516_oe;
assign io_port_pins_26_o_ie = T_8516_ie;
assign io_port_pins_26_o_pue = T_8516_pue;
assign io_port_pins_26_o_ds = T_8516_ds;
assign io_port_pins_27_o_oval = T_8559;
assign io_port_pins_27_o_oe = T_8552_oe;
assign io_port_pins_27_o_ie = T_8552_ie;
assign io_port_pins_27_o_pue = T_8552_pue;
assign io_port_pins_27_o_ds = T_8552_ds;
assign io_port_pins_28_o_oval = T_8595;
assign io_port_pins_28_o_oe = T_8588_oe;
assign io_port_pins_28_o_ie = T_8588_ie;
assign io_port_pins_28_o_pue = T_8588_pue;
assign io_port_pins_28_o_ds = T_8588_ds;
assign io_port_pins_29_o_oval = T_8631;
assign io_port_pins_29_o_oe = T_8624_oe;
assign io_port_pins_29_o_ie = T_8624_ie;
assign io_port_pins_29_o_pue = T_8624_pue;
assign io_port_pins_29_o_ds = T_8624_ds;
assign io_port_pins_30_o_oval = T_8667;
assign io_port_pins_30_o_oe = T_8660_oe;
assign io_port_pins_30_o_ie = T_8660_ie;
assign io_port_pins_30_o_pue = T_8660_pue;
assign io_port_pins_30_o_ds = T_8660_ds;
assign io_port_pins_31_o_oval = T_8703;
assign io_port_pins_31_o_oe = T_8696_oe;
assign io_port_pins_31_o_ie = T_8696_ie;
assign io_port_pins_31_o_pue = T_8696_pue;
assign io_port_pins_31_o_ds = T_8696_ds;
assign io_port_iof_0_0_i_ival = T_7603;
assign io_port_iof_0_1_i_ival = T_7639;
assign io_port_iof_0_2_i_ival = T_7675;
assign io_port_iof_0_3_i_ival = T_7711;
assign io_port_iof_0_4_i_ival = T_7747;
assign io_port_iof_0_5_i_ival = T_7783;
assign io_port_iof_0_6_i_ival = T_7819;
assign io_port_iof_0_7_i_ival = T_7855;
assign io_port_iof_0_8_i_ival = T_7891;
assign io_port_iof_0_9_i_ival = T_7927;
assign io_port_iof_0_10_i_ival = T_7963;
assign io_port_iof_0_11_i_ival = T_7999;
assign io_port_iof_0_12_i_ival = T_8035;
assign io_port_iof_0_13_i_ival = T_8071;
assign io_port_iof_0_14_i_ival = T_8107;
assign io_port_iof_0_15_i_ival = T_8143;
assign io_port_iof_0_16_i_ival = T_8179;
assign io_port_iof_0_17_i_ival = T_8215;
assign io_port_iof_0_18_i_ival = T_8251;
assign io_port_iof_0_19_i_ival = T_8287;
assign io_port_iof_0_20_i_ival = T_8323;
assign io_port_iof_0_21_i_ival = T_8359;
assign io_port_iof_0_22_i_ival = T_8395;
assign io_port_iof_0_23_i_ival = T_8431;
assign io_port_iof_0_24_i_ival = T_8467;
assign io_port_iof_0_25_i_ival = T_8503;
assign io_port_iof_0_26_i_ival = T_8539;
assign io_port_iof_0_27_i_ival = T_8575;
assign io_port_iof_0_28_i_ival = T_8611;
assign io_port_iof_0_29_i_ival = T_8647;
assign io_port_iof_0_30_i_ival = T_8683;
assign io_port_iof_0_31_i_ival = T_8719;
assign io_port_iof_1_0_i_ival = T_7603;
assign io_port_iof_1_1_i_ival = T_7639;
assign io_port_iof_1_2_i_ival = T_7675;
assign io_port_iof_1_3_i_ival = T_7711;
assign io_port_iof_1_4_i_ival = T_7747;
assign io_port_iof_1_5_i_ival = T_7783;
assign io_port_iof_1_6_i_ival = T_7819;
assign io_port_iof_1_7_i_ival = T_7855;
assign io_port_iof_1_8_i_ival = T_7891;
assign io_port_iof_1_9_i_ival = T_7927;
assign io_port_iof_1_10_i_ival = T_7963;
assign io_port_iof_1_11_i_ival = T_7999;
assign io_port_iof_1_12_i_ival = T_8035;
assign io_port_iof_1_13_i_ival = T_8071;
assign io_port_iof_1_14_i_ival = T_8107;
assign io_port_iof_1_15_i_ival = T_8143;
assign io_port_iof_1_16_i_ival = T_8179;
assign io_port_iof_1_17_i_ival = T_8215;
assign io_port_iof_1_18_i_ival = T_8251;
assign io_port_iof_1_19_i_ival = T_8287;
assign io_port_iof_1_20_i_ival = T_8323;
assign io_port_iof_1_21_i_ival = T_8359;
assign io_port_iof_1_22_i_ival = T_8395;
assign io_port_iof_1_23_i_ival = T_8431;
assign io_port_iof_1_24_i_ival = T_8467;
assign io_port_iof_1_25_i_ival = T_8503;
assign io_port_iof_1_26_i_ival = T_8539;
assign io_port_iof_1_27_i_ival = T_8575;
assign io_port_iof_1_28_i_ival = T_8611;
assign io_port_iof_1_29_i_ival = T_8647;
assign io_port_iof_1_30_i_ival = T_8683;
assign io_port_iof_1_31_i_ival = T_8719;
assign oeReg_clock = clock;
assign oeReg_reset = reset;
assign oeReg_io_d = T_3370_bits_data;
assign oeReg_io_en = T_4203;
assign pueReg_clock = clock;
assign pueReg_reset = reset;
assign pueReg_io_d = T_3370_bits_data;
assign pueReg_io_en = T_4495;
assign ieReg_clock = clock;
assign ieReg_reset = reset;
assign ieReg_io_d = T_3370_bits_data;
assign ieReg_io_en = T_4031;
assign inVal = T_3253;
assign T_3188_0 = io_port_pins_0_i_ival;
assign T_3188_1 = io_port_pins_1_i_ival;
assign T_3188_2 = io_port_pins_2_i_ival;
assign T_3188_3 = io_port_pins_3_i_ival;
assign T_3188_4 = io_port_pins_4_i_ival;
assign T_3188_5 = io_port_pins_5_i_ival;
assign T_3188_6 = io_port_pins_6_i_ival;
assign T_3188_7 = io_port_pins_7_i_ival;
assign T_3188_8 = io_port_pins_8_i_ival;
assign T_3188_9 = io_port_pins_9_i_ival;
assign T_3188_10 = io_port_pins_10_i_ival;
assign T_3188_11 = io_port_pins_11_i_ival;
assign T_3188_12 = io_port_pins_12_i_ival;
assign T_3188_13 = io_port_pins_13_i_ival;
assign T_3188_14 = io_port_pins_14_i_ival;
assign T_3188_15 = io_port_pins_15_i_ival;
assign T_3188_16 = io_port_pins_16_i_ival;
assign T_3188_17 = io_port_pins_17_i_ival;
assign T_3188_18 = io_port_pins_18_i_ival;
assign T_3188_19 = io_port_pins_19_i_ival;
assign T_3188_20 = io_port_pins_20_i_ival;
assign T_3188_21 = io_port_pins_21_i_ival;
assign T_3188_22 = io_port_pins_22_i_ival;
assign T_3188_23 = io_port_pins_23_i_ival;
assign T_3188_24 = io_port_pins_24_i_ival;
assign T_3188_25 = io_port_pins_25_i_ival;
assign T_3188_26 = io_port_pins_26_i_ival;
assign T_3188_27 = io_port_pins_27_i_ival;
assign T_3188_28 = io_port_pins_28_i_ival;
assign T_3188_29 = io_port_pins_29_i_ival;
assign T_3188_30 = io_port_pins_30_i_ival;
assign T_3188_31 = io_port_pins_31_i_ival;
assign T_3223 = {T_3188_1,T_3188_0};
assign T_3224 = {T_3188_3,T_3188_2};
assign T_3225 = {T_3224,T_3223};
assign T_3226 = {T_3188_5,T_3188_4};
assign T_3227 = {T_3188_7,T_3188_6};
assign T_3228 = {T_3227,T_3226};
assign T_3229 = {T_3228,T_3225};
assign T_3230 = {T_3188_9,T_3188_8};
assign T_3231 = {T_3188_11,T_3188_10};
assign T_3232 = {T_3231,T_3230};
assign T_3233 = {T_3188_13,T_3188_12};
assign T_3234 = {T_3188_15,T_3188_14};
assign T_3235 = {T_3234,T_3233};
assign T_3236 = {T_3235,T_3232};
assign T_3237 = {T_3236,T_3229};
assign T_3238 = {T_3188_17,T_3188_16};
assign T_3239 = {T_3188_19,T_3188_18};
assign T_3240 = {T_3239,T_3238};
assign T_3241 = {T_3188_21,T_3188_20};
assign T_3242 = {T_3188_23,T_3188_22};
assign T_3243 = {T_3242,T_3241};
assign T_3244 = {T_3243,T_3240};
assign T_3245 = {T_3188_25,T_3188_24};
assign T_3246 = {T_3188_27,T_3188_26};
assign T_3247 = {T_3246,T_3245};
assign T_3248 = {T_3188_29,T_3188_28};
assign T_3249 = {T_3188_31,T_3188_30};
assign T_3250 = {T_3249,T_3248};
assign T_3251 = {T_3250,T_3247};
assign T_3252 = {T_3251,T_3244};
assign T_3253 = {T_3252,T_3237};
assign iofEnReg_clock = clock;
assign iofEnReg_reset = reset;
assign iofEnReg_io_d = T_3370_bits_data;
assign iofEnReg_io_en = T_3991;
assign T_3269 = ~ valueReg;
assign rise = T_3269 & inSyncReg;
assign T_3270 = ~ inSyncReg;
assign fall = valueReg & T_3270;
assign T_3295_ready = T_5322;
assign T_3295_valid = io_in_0_a_valid;
assign T_3295_bits_read = T_3312;
assign T_3295_bits_index = T_3313[9:0];
assign T_3295_bits_data = io_in_0_a_bits_data;
assign T_3295_bits_mask = io_in_0_a_bits_mask;
assign T_3295_bits_extra = T_3316;
assign T_3312 = io_in_0_a_bits_opcode == 3'h4;
assign T_3313 = io_in_0_a_bits_address[28:2];
assign T_3314 = io_in_0_a_bits_address[1:0];
assign T_3315 = {T_3314,io_in_0_a_bits_source};
assign T_3316 = {T_3315,io_in_0_a_bits_size};
assign T_3334_ready = io_in_0_d_ready;
assign T_3334_valid = T_5325;
assign T_3334_bits_read = T_3370_bits_read;
assign T_3334_bits_data = T_6245;
assign T_3334_bits_extra = T_3370_bits_extra;
assign T_3370_ready = T_5324;
assign T_3370_valid = T_5323;
assign T_3370_bits_read = T_3295_bits_read;
assign T_3370_bits_index = T_3295_bits_index;
assign T_3370_bits_data = T_3295_bits_data;
assign T_3370_bits_mask = T_3295_bits_mask;
assign T_3370_bits_extra = T_3295_bits_extra;
assign T_3455 = T_3370_bits_index & 10'h3e0;
assign T_3457 = T_3455 == 10'h0;
assign T_3463 = T_3370_bits_index ^ 10'h5;
assign T_3464 = T_3463 & 10'h3e0;
assign T_3466 = T_3464 == 10'h0;
assign T_3472 = T_3370_bits_index ^ 10'ha;
assign T_3473 = T_3472 & 10'h3e0;
assign T_3475 = T_3473 == 10'h0;
assign T_3481 = T_3370_bits_index ^ 10'he;
assign T_3482 = T_3481 & 10'h3e0;
assign T_3484 = T_3482 == 10'h0;
assign T_3490 = T_3370_bits_index ^ 10'h1;
assign T_3491 = T_3490 & 10'h3e0;
assign T_3493 = T_3491 == 10'h0;
assign T_3499 = T_3370_bits_index ^ 10'h6;
assign T_3500 = T_3499 & 10'h3e0;
assign T_3502 = T_3500 == 10'h0;
assign T_3508 = T_3370_bits_index ^ 10'h9;
assign T_3509 = T_3508 & 10'h3e0;
assign T_3511 = T_3509 == 10'h0;
assign T_3517 = T_3370_bits_index ^ 10'hd;
assign T_3518 = T_3517 & 10'h3e0;
assign T_3520 = T_3518 == 10'h0;
assign T_3526 = T_3370_bits_index ^ 10'h2;
assign T_3527 = T_3526 & 10'h3e0;
assign T_3529 = T_3527 == 10'h0;
assign T_3535 = T_3370_bits_index ^ 10'hc;
assign T_3536 = T_3535 & 10'h3e0;
assign T_3538 = T_3536 == 10'h0;
assign T_3544 = T_3370_bits_index ^ 10'h7;
assign T_3545 = T_3544 & 10'h3e0;
assign T_3547 = T_3545 == 10'h0;
assign T_3553 = T_3370_bits_index ^ 10'h3;
assign T_3554 = T_3553 & 10'h3e0;
assign T_3556 = T_3554 == 10'h0;
assign T_3562 = T_3370_bits_index ^ 10'h10;
assign T_3563 = T_3562 & 10'h3e0;
assign T_3565 = T_3563 == 10'h0;
assign T_3571 = T_3370_bits_index ^ 10'hb;
assign T_3572 = T_3571 & 10'h3e0;
assign T_3574 = T_3572 == 10'h0;
assign T_3580 = T_3370_bits_index ^ 10'h8;
assign T_3581 = T_3580 & 10'h3e0;
assign T_3583 = T_3581 == 10'h0;
assign T_3589 = T_3370_bits_index ^ 10'h4;
assign T_3590 = T_3589 & 10'h3e0;
assign T_3592 = T_3590 == 10'h0;
assign T_3598 = T_3370_bits_index ^ 10'hf;
assign T_3599 = T_3598 & 10'h3e0;
assign T_3601 = T_3599 == 10'h0;
assign T_3609_0 = T_5397;
assign T_3609_1 = T_5497;
assign T_3609_2 = T_5597;
assign T_3609_3 = T_5677;
assign T_3609_4 = T_5417;
assign T_3609_5 = T_5517;
assign T_3609_6 = T_5577;
assign T_3609_7 = T_5657;
assign T_3609_8 = T_5437;
assign T_3609_9 = T_5637;
assign T_3609_10 = T_5537;
assign T_3609_11 = T_5457;
assign T_3609_12 = T_5717;
assign T_3609_13 = T_5617;
assign T_3609_14 = T_5557;
assign T_3609_15 = T_5477;
assign T_3609_16 = T_5697;
assign T_3614_0 = T_5403;
assign T_3614_1 = T_5503;
assign T_3614_2 = T_5603;
assign T_3614_3 = T_5683;
assign T_3614_4 = T_5423;
assign T_3614_5 = T_5523;
assign T_3614_6 = T_5583;
assign T_3614_7 = T_5663;
assign T_3614_8 = T_5443;
assign T_3614_9 = T_5643;
assign T_3614_10 = T_5543;
assign T_3614_11 = T_5463;
assign T_3614_12 = T_5723;
assign T_3614_13 = T_5623;
assign T_3614_14 = T_5563;
assign T_3614_15 = T_5483;
assign T_3614_16 = T_5703;
assign T_3619_0 = 1'h1;
assign T_3619_1 = 1'h1;
assign T_3619_2 = 1'h1;
assign T_3619_3 = 1'h1;
assign T_3619_4 = 1'h1;
assign T_3619_5 = 1'h1;
assign T_3619_6 = 1'h1;
assign T_3619_7 = 1'h1;
assign T_3619_8 = 1'h1;
assign T_3619_9 = 1'h1;
assign T_3619_10 = 1'h1;
assign T_3619_11 = 1'h1;
assign T_3619_12 = 1'h1;
assign T_3619_13 = 1'h1;
assign T_3619_14 = 1'h1;
assign T_3619_15 = 1'h1;
assign T_3619_16 = 1'h1;
assign T_3624_0 = 1'h1;
assign T_3624_1 = 1'h1;
assign T_3624_2 = 1'h1;
assign T_3624_3 = 1'h1;
assign T_3624_4 = 1'h1;
assign T_3624_5 = 1'h1;
assign T_3624_6 = 1'h1;
assign T_3624_7 = 1'h1;
assign T_3624_8 = 1'h1;
assign T_3624_9 = 1'h1;
assign T_3624_10 = 1'h1;
assign T_3624_11 = 1'h1;
assign T_3624_12 = 1'h1;
assign T_3624_13 = 1'h1;
assign T_3624_14 = 1'h1;
assign T_3624_15 = 1'h1;
assign T_3624_16 = 1'h1;
assign T_3629_0 = 1'h1;
assign T_3629_1 = 1'h1;
assign T_3629_2 = 1'h1;
assign T_3629_3 = 1'h1;
assign T_3629_4 = 1'h1;
assign T_3629_5 = 1'h1;
assign T_3629_6 = 1'h1;
assign T_3629_7 = 1'h1;
assign T_3629_8 = 1'h1;
assign T_3629_9 = 1'h1;
assign T_3629_10 = 1'h1;
assign T_3629_11 = 1'h1;
assign T_3629_12 = 1'h1;
assign T_3629_13 = 1'h1;
assign T_3629_14 = 1'h1;
assign T_3629_15 = 1'h1;
assign T_3629_16 = 1'h1;
assign T_3634_0 = 1'h1;
assign T_3634_1 = 1'h1;
assign T_3634_2 = 1'h1;
assign T_3634_3 = 1'h1;
assign T_3634_4 = 1'h1;
assign T_3634_5 = 1'h1;
assign T_3634_6 = 1'h1;
assign T_3634_7 = 1'h1;
assign T_3634_8 = 1'h1;
assign T_3634_9 = 1'h1;
assign T_3634_10 = 1'h1;
assign T_3634_11 = 1'h1;
assign T_3634_12 = 1'h1;
assign T_3634_13 = 1'h1;
assign T_3634_14 = 1'h1;
assign T_3634_15 = 1'h1;
assign T_3634_16 = 1'h1;
assign T_3639_0 = T_5407;
assign T_3639_1 = T_5507;
assign T_3639_2 = T_5607;
assign T_3639_3 = T_5687;
assign T_3639_4 = T_5427;
assign T_3639_5 = T_5527;
assign T_3639_6 = T_5587;
assign T_3639_7 = T_5667;
assign T_3639_8 = T_5447;
assign T_3639_9 = T_5647;
assign T_3639_10 = T_5547;
assign T_3639_11 = T_5467;
assign T_3639_12 = T_5727;
assign T_3639_13 = T_5627;
assign T_3639_14 = T_5567;
assign T_3639_15 = T_5487;
assign T_3639_16 = T_5707;
assign T_3644_0 = T_5413;
assign T_3644_1 = T_5513;
assign T_3644_2 = T_5613;
assign T_3644_3 = T_5693;
assign T_3644_4 = T_5433;
assign T_3644_5 = T_5533;
assign T_3644_6 = T_5593;
assign T_3644_7 = T_5673;
assign T_3644_8 = T_5453;
assign T_3644_9 = T_5653;
assign T_3644_10 = T_5553;
assign T_3644_11 = T_5473;
assign T_3644_12 = T_5733;
assign T_3644_13 = T_5633;
assign T_3644_14 = T_5573;
assign T_3644_15 = T_5493;
assign T_3644_16 = T_5713;
assign T_3806 = T_3370_bits_mask[0];
assign T_3807 = T_3370_bits_mask[1];
assign T_3808 = T_3370_bits_mask[2];
assign T_3809 = T_3370_bits_mask[3];
assign T_3813 = T_3806 ? 8'hff : 8'h0;
assign T_3817 = T_3807 ? 8'hff : 8'h0;
assign T_3821 = T_3808 ? 8'hff : 8'h0;
assign T_3825 = T_3809 ? 8'hff : 8'h0;
assign T_3826 = {T_3817,T_3813};
assign T_3827 = {T_3825,T_3821};
assign T_3828 = {T_3827,T_3826};
assign T_3856 = ~ T_3828;
assign T_3858 = T_3856 == 32'h0;
assign T_3911 = T_3644_1 & T_3858;
assign GEN_7 = T_3911 ? T_3370_bits_data : dsReg;
assign T_3951 = T_3644_2 & T_3858;
assign GEN_8 = T_3951 ? T_3370_bits_data : highIeReg;
assign T_3991 = T_3644_3 & T_3858;
assign T_4007 = iofEnReg_io_q;
assign T_4031 = T_3644_4 & T_3858;
assign T_4047 = ieReg_io_q;
assign T_4071 = T_3644_5 & T_3858;
assign GEN_9 = T_4071 ? T_3370_bits_data : riseIeReg;
assign T_4111 = T_3644_6 & T_3858;
assign T_4114 = ~ fallIpReg;
assign T_4116 = T_4111 ? T_3370_bits_data : 32'h0;
assign T_4117 = T_4114 | T_4116;
assign T_4118 = ~ T_4117;
assign T_4119 = T_4118 | fall;
assign T_4157 = T_3644_7 & T_3858;
assign T_4160 = ~ lowIpReg;
assign T_4162 = T_4157 ? T_3370_bits_data : 32'h0;
assign T_4163 = T_4160 | T_4162;
assign T_4164 = ~ T_4163;
assign T_4165 = T_4164 | T_3269;
assign T_4203 = T_3644_8 & T_3858;
assign T_4219 = oeReg_io_q;
assign T_4243 = T_3644_9 & T_3858;
assign GEN_10 = T_4243 ? T_3370_bits_data : lowIeReg;
assign T_4283 = T_3644_10 & T_3858;
assign T_4286 = ~ riseIpReg;
assign T_4288 = T_4283 ? T_3370_bits_data : 32'h0;
assign T_4289 = T_4286 | T_4288;
assign T_4290 = ~ T_4289;
assign T_4291 = T_4290 | rise;
assign T_4329 = T_3644_11 & T_3858;
assign GEN_11 = T_4329 ? T_3370_bits_data : portReg;
assign T_4369 = T_3644_12 & T_3858;
assign GEN_12 = T_4369 ? T_3370_bits_data : xorReg;
assign T_4409 = T_3644_13 & T_3858;
assign T_4412 = ~ highIpReg;
assign T_4414 = T_4409 ? T_3370_bits_data : 32'h0;
assign T_4415 = T_4412 | T_4414;
assign T_4416 = ~ T_4415;
assign T_4417 = T_4416 | valueReg;
assign T_4455 = T_3644_14 & T_3858;
assign GEN_13 = T_4455 ? T_3370_bits_data : fallIeReg;
assign T_4495 = T_3644_15 & T_3858;
assign T_4511 = pueReg_io_q;
assign T_4535 = T_3644_16 & T_3858;
assign GEN_14 = T_4535 ? T_3370_bits_data : iofSelReg;
assign T_4557 = T_3457 == 1'h0;
assign T_4559 = T_4557 | T_3619_0;
assign T_4561 = T_3493 == 1'h0;
assign T_4563 = T_4561 | T_3619_4;
assign T_4565 = T_3529 == 1'h0;
assign T_4567 = T_4565 | T_3619_8;
assign T_4569 = T_3556 == 1'h0;
assign T_4571 = T_4569 | T_3619_11;
assign T_4573 = T_3592 == 1'h0;
assign T_4575 = T_4573 | T_3619_15;
assign T_4577 = T_3466 == 1'h0;
assign T_4579 = T_4577 | T_3619_1;
assign T_4581 = T_3502 == 1'h0;
assign T_4583 = T_4581 | T_3619_5;
assign T_4585 = T_3547 == 1'h0;
assign T_4587 = T_4585 | T_3619_10;
assign T_4589 = T_3583 == 1'h0;
assign T_4591 = T_4589 | T_3619_14;
assign T_4593 = T_3511 == 1'h0;
assign T_4595 = T_4593 | T_3619_6;
assign T_4597 = T_3475 == 1'h0;
assign T_4599 = T_4597 | T_3619_2;
assign T_4601 = T_3574 == 1'h0;
assign T_4603 = T_4601 | T_3619_13;
assign T_4605 = T_3538 == 1'h0;
assign T_4607 = T_4605 | T_3619_9;
assign T_4609 = T_3520 == 1'h0;
assign T_4611 = T_4609 | T_3619_7;
assign T_4613 = T_3484 == 1'h0;
assign T_4615 = T_4613 | T_3619_3;
assign T_4617 = T_3601 == 1'h0;
assign T_4619 = T_4617 | T_3619_16;
assign T_4621 = T_3565 == 1'h0;
assign T_4623 = T_4621 | T_3619_12;
assign T_4704_0 = T_4559;
assign T_4704_1 = T_4563;
assign T_4704_2 = T_4567;
assign T_4704_3 = T_4571;
assign T_4704_4 = T_4575;
assign T_4704_5 = T_4579;
assign T_4704_6 = T_4583;
assign T_4704_7 = T_4587;
assign T_4704_8 = T_4591;
assign T_4704_9 = T_4595;
assign T_4704_10 = T_4599;
assign T_4704_11 = T_4603;
assign T_4704_12 = T_4607;
assign T_4704_13 = T_4611;
assign T_4704_14 = T_4615;
assign T_4704_15 = T_4619;
assign T_4704_16 = T_4623;
assign T_4704_17 = 1'h1;
assign T_4704_18 = 1'h1;
assign T_4704_19 = 1'h1;
assign T_4704_20 = 1'h1;
assign T_4704_21 = 1'h1;
assign T_4704_22 = 1'h1;
assign T_4704_23 = 1'h1;
assign T_4704_24 = 1'h1;
assign T_4704_25 = 1'h1;
assign T_4704_26 = 1'h1;
assign T_4704_27 = 1'h1;
assign T_4704_28 = 1'h1;
assign T_4704_29 = 1'h1;
assign T_4704_30 = 1'h1;
assign T_4704_31 = 1'h1;
assign T_4742 = T_4557 | T_3624_0;
assign T_4746 = T_4561 | T_3624_4;
assign T_4750 = T_4565 | T_3624_8;
assign T_4754 = T_4569 | T_3624_11;
assign T_4758 = T_4573 | T_3624_15;
assign T_4762 = T_4577 | T_3624_1;
assign T_4766 = T_4581 | T_3624_5;
assign T_4770 = T_4585 | T_3624_10;
assign T_4774 = T_4589 | T_3624_14;
assign T_4778 = T_4593 | T_3624_6;
assign T_4782 = T_4597 | T_3624_2;
assign T_4786 = T_4601 | T_3624_13;
assign T_4790 = T_4605 | T_3624_9;
assign T_4794 = T_4609 | T_3624_7;
assign T_4798 = T_4613 | T_3624_3;
assign T_4802 = T_4617 | T_3624_16;
assign T_4806 = T_4621 | T_3624_12;
assign T_4887_0 = T_4742;
assign T_4887_1 = T_4746;
assign T_4887_2 = T_4750;
assign T_4887_3 = T_4754;
assign T_4887_4 = T_4758;
assign T_4887_5 = T_4762;
assign T_4887_6 = T_4766;
assign T_4887_7 = T_4770;
assign T_4887_8 = T_4774;
assign T_4887_9 = T_4778;
assign T_4887_10 = T_4782;
assign T_4887_11 = T_4786;
assign T_4887_12 = T_4790;
assign T_4887_13 = T_4794;
assign T_4887_14 = T_4798;
assign T_4887_15 = T_4802;
assign T_4887_16 = T_4806;
assign T_4887_17 = 1'h1;
assign T_4887_18 = 1'h1;
assign T_4887_19 = 1'h1;
assign T_4887_20 = 1'h1;
assign T_4887_21 = 1'h1;
assign T_4887_22 = 1'h1;
assign T_4887_23 = 1'h1;
assign T_4887_24 = 1'h1;
assign T_4887_25 = 1'h1;
assign T_4887_26 = 1'h1;
assign T_4887_27 = 1'h1;
assign T_4887_28 = 1'h1;
assign T_4887_29 = 1'h1;
assign T_4887_30 = 1'h1;
assign T_4887_31 = 1'h1;
assign T_4925 = T_4557 | T_3629_0;
assign T_4929 = T_4561 | T_3629_4;
assign T_4933 = T_4565 | T_3629_8;
assign T_4937 = T_4569 | T_3629_11;
assign T_4941 = T_4573 | T_3629_15;
assign T_4945 = T_4577 | T_3629_1;
assign T_4949 = T_4581 | T_3629_5;
assign T_4953 = T_4585 | T_3629_10;
assign T_4957 = T_4589 | T_3629_14;
assign T_4961 = T_4593 | T_3629_6;
assign T_4965 = T_4597 | T_3629_2;
assign T_4969 = T_4601 | T_3629_13;
assign T_4973 = T_4605 | T_3629_9;
assign T_4977 = T_4609 | T_3629_7;
assign T_4981 = T_4613 | T_3629_3;
assign T_4985 = T_4617 | T_3629_16;
assign T_4989 = T_4621 | T_3629_12;
assign T_5070_0 = T_4925;
assign T_5070_1 = T_4929;
assign T_5070_2 = T_4933;
assign T_5070_3 = T_4937;
assign T_5070_4 = T_4941;
assign T_5070_5 = T_4945;
assign T_5070_6 = T_4949;
assign T_5070_7 = T_4953;
assign T_5070_8 = T_4957;
assign T_5070_9 = T_4961;
assign T_5070_10 = T_4965;
assign T_5070_11 = T_4969;
assign T_5070_12 = T_4973;
assign T_5070_13 = T_4977;
assign T_5070_14 = T_4981;
assign T_5070_15 = T_4985;
assign T_5070_16 = T_4989;
assign T_5070_17 = 1'h1;
assign T_5070_18 = 1'h1;
assign T_5070_19 = 1'h1;
assign T_5070_20 = 1'h1;
assign T_5070_21 = 1'h1;
assign T_5070_22 = 1'h1;
assign T_5070_23 = 1'h1;
assign T_5070_24 = 1'h1;
assign T_5070_25 = 1'h1;
assign T_5070_26 = 1'h1;
assign T_5070_27 = 1'h1;
assign T_5070_28 = 1'h1;
assign T_5070_29 = 1'h1;
assign T_5070_30 = 1'h1;
assign T_5070_31 = 1'h1;
assign T_5108 = T_4557 | T_3634_0;
assign T_5112 = T_4561 | T_3634_4;
assign T_5116 = T_4565 | T_3634_8;
assign T_5120 = T_4569 | T_3634_11;
assign T_5124 = T_4573 | T_3634_15;
assign T_5128 = T_4577 | T_3634_1;
assign T_5132 = T_4581 | T_3634_5;
assign T_5136 = T_4585 | T_3634_10;
assign T_5140 = T_4589 | T_3634_14;
assign T_5144 = T_4593 | T_3634_6;
assign T_5148 = T_4597 | T_3634_2;
assign T_5152 = T_4601 | T_3634_13;
assign T_5156 = T_4605 | T_3634_9;
assign T_5160 = T_4609 | T_3634_7;
assign T_5164 = T_4613 | T_3634_3;
assign T_5168 = T_4617 | T_3634_16;
assign T_5172 = T_4621 | T_3634_12;
assign T_5253_0 = T_5108;
assign T_5253_1 = T_5112;
assign T_5253_2 = T_5116;
assign T_5253_3 = T_5120;
assign T_5253_4 = T_5124;
assign T_5253_5 = T_5128;
assign T_5253_6 = T_5132;
assign T_5253_7 = T_5136;
assign T_5253_8 = T_5140;
assign T_5253_9 = T_5144;
assign T_5253_10 = T_5148;
assign T_5253_11 = T_5152;
assign T_5253_12 = T_5156;
assign T_5253_13 = T_5160;
assign T_5253_14 = T_5164;
assign T_5253_15 = T_5168;
assign T_5253_16 = T_5172;
assign T_5253_17 = 1'h1;
assign T_5253_18 = 1'h1;
assign T_5253_19 = 1'h1;
assign T_5253_20 = 1'h1;
assign T_5253_21 = 1'h1;
assign T_5253_22 = 1'h1;
assign T_5253_23 = 1'h1;
assign T_5253_24 = 1'h1;
assign T_5253_25 = 1'h1;
assign T_5253_26 = 1'h1;
assign T_5253_27 = 1'h1;
assign T_5253_28 = 1'h1;
assign T_5253_29 = 1'h1;
assign T_5253_30 = 1'h1;
assign T_5253_31 = 1'h1;
assign T_5288 = T_3370_bits_index[0];
assign T_5289 = T_3370_bits_index[1];
assign T_5290 = T_3370_bits_index[2];
assign T_5291 = T_3370_bits_index[3];
assign T_5292 = T_3370_bits_index[4];
assign T_5298 = {T_5289,T_5288};
assign T_5299 = {T_5292,T_5291};
assign T_5300 = {T_5299,T_5290};
assign T_5301 = {T_5300,T_5298};
assign GEN_0 = GEN_45;
assign GEN_15 = 5'h1 == T_5301 ? T_4704_1 : T_4704_0;
assign GEN_16 = 5'h2 == T_5301 ? T_4704_2 : GEN_15;
assign GEN_17 = 5'h3 == T_5301 ? T_4704_3 : GEN_16;
assign GEN_18 = 5'h4 == T_5301 ? T_4704_4 : GEN_17;
assign GEN_19 = 5'h5 == T_5301 ? T_4704_5 : GEN_18;
assign GEN_20 = 5'h6 == T_5301 ? T_4704_6 : GEN_19;
assign GEN_21 = 5'h7 == T_5301 ? T_4704_7 : GEN_20;
assign GEN_22 = 5'h8 == T_5301 ? T_4704_8 : GEN_21;
assign GEN_23 = 5'h9 == T_5301 ? T_4704_9 : GEN_22;
assign GEN_24 = 5'ha == T_5301 ? T_4704_10 : GEN_23;
assign GEN_25 = 5'hb == T_5301 ? T_4704_11 : GEN_24;
assign GEN_26 = 5'hc == T_5301 ? T_4704_12 : GEN_25;
assign GEN_27 = 5'hd == T_5301 ? T_4704_13 : GEN_26;
assign GEN_28 = 5'he == T_5301 ? T_4704_14 : GEN_27;
assign GEN_29 = 5'hf == T_5301 ? T_4704_15 : GEN_28;
assign GEN_30 = 5'h10 == T_5301 ? T_4704_16 : GEN_29;
assign GEN_31 = 5'h11 == T_5301 ? T_4704_17 : GEN_30;
assign GEN_32 = 5'h12 == T_5301 ? T_4704_18 : GEN_31;
assign GEN_33 = 5'h13 == T_5301 ? T_4704_19 : GEN_32;
assign GEN_34 = 5'h14 == T_5301 ? T_4704_20 : GEN_33;
assign GEN_35 = 5'h15 == T_5301 ? T_4704_21 : GEN_34;
assign GEN_36 = 5'h16 == T_5301 ? T_4704_22 : GEN_35;
assign GEN_37 = 5'h17 == T_5301 ? T_4704_23 : GEN_36;
assign GEN_38 = 5'h18 == T_5301 ? T_4704_24 : GEN_37;
assign GEN_39 = 5'h19 == T_5301 ? T_4704_25 : GEN_38;
assign GEN_40 = 5'h1a == T_5301 ? T_4704_26 : GEN_39;
assign GEN_41 = 5'h1b == T_5301 ? T_4704_27 : GEN_40;
assign GEN_42 = 5'h1c == T_5301 ? T_4704_28 : GEN_41;
assign GEN_43 = 5'h1d == T_5301 ? T_4704_29 : GEN_42;
assign GEN_44 = 5'h1e == T_5301 ? T_4704_30 : GEN_43;
assign GEN_45 = 5'h1f == T_5301 ? T_4704_31 : GEN_44;
assign GEN_1 = GEN_76;
assign GEN_46 = 5'h1 == T_5301 ? T_4887_1 : T_4887_0;
assign GEN_47 = 5'h2 == T_5301 ? T_4887_2 : GEN_46;
assign GEN_48 = 5'h3 == T_5301 ? T_4887_3 : GEN_47;
assign GEN_49 = 5'h4 == T_5301 ? T_4887_4 : GEN_48;
assign GEN_50 = 5'h5 == T_5301 ? T_4887_5 : GEN_49;
assign GEN_51 = 5'h6 == T_5301 ? T_4887_6 : GEN_50;
assign GEN_52 = 5'h7 == T_5301 ? T_4887_7 : GEN_51;
assign GEN_53 = 5'h8 == T_5301 ? T_4887_8 : GEN_52;
assign GEN_54 = 5'h9 == T_5301 ? T_4887_9 : GEN_53;
assign GEN_55 = 5'ha == T_5301 ? T_4887_10 : GEN_54;
assign GEN_56 = 5'hb == T_5301 ? T_4887_11 : GEN_55;
assign GEN_57 = 5'hc == T_5301 ? T_4887_12 : GEN_56;
assign GEN_58 = 5'hd == T_5301 ? T_4887_13 : GEN_57;
assign GEN_59 = 5'he == T_5301 ? T_4887_14 : GEN_58;
assign GEN_60 = 5'hf == T_5301 ? T_4887_15 : GEN_59;
assign GEN_61 = 5'h10 == T_5301 ? T_4887_16 : GEN_60;
assign GEN_62 = 5'h11 == T_5301 ? T_4887_17 : GEN_61;
assign GEN_63 = 5'h12 == T_5301 ? T_4887_18 : GEN_62;
assign GEN_64 = 5'h13 == T_5301 ? T_4887_19 : GEN_63;
assign GEN_65 = 5'h14 == T_5301 ? T_4887_20 : GEN_64;
assign GEN_66 = 5'h15 == T_5301 ? T_4887_21 : GEN_65;
assign GEN_67 = 5'h16 == T_5301 ? T_4887_22 : GEN_66;
assign GEN_68 = 5'h17 == T_5301 ? T_4887_23 : GEN_67;
assign GEN_69 = 5'h18 == T_5301 ? T_4887_24 : GEN_68;
assign GEN_70 = 5'h19 == T_5301 ? T_4887_25 : GEN_69;
assign GEN_71 = 5'h1a == T_5301 ? T_4887_26 : GEN_70;
assign GEN_72 = 5'h1b == T_5301 ? T_4887_27 : GEN_71;
assign GEN_73 = 5'h1c == T_5301 ? T_4887_28 : GEN_72;
assign GEN_74 = 5'h1d == T_5301 ? T_4887_29 : GEN_73;
assign GEN_75 = 5'h1e == T_5301 ? T_4887_30 : GEN_74;
assign GEN_76 = 5'h1f == T_5301 ? T_4887_31 : GEN_75;
assign T_5318 = T_3370_bits_read ? GEN_0 : GEN_1;
assign GEN_2 = GEN_107;
assign GEN_77 = 5'h1 == T_5301 ? T_5070_1 : T_5070_0;
assign GEN_78 = 5'h2 == T_5301 ? T_5070_2 : GEN_77;
assign GEN_79 = 5'h3 == T_5301 ? T_5070_3 : GEN_78;
assign GEN_80 = 5'h4 == T_5301 ? T_5070_4 : GEN_79;
assign GEN_81 = 5'h5 == T_5301 ? T_5070_5 : GEN_80;
assign GEN_82 = 5'h6 == T_5301 ? T_5070_6 : GEN_81;
assign GEN_83 = 5'h7 == T_5301 ? T_5070_7 : GEN_82;
assign GEN_84 = 5'h8 == T_5301 ? T_5070_8 : GEN_83;
assign GEN_85 = 5'h9 == T_5301 ? T_5070_9 : GEN_84;
assign GEN_86 = 5'ha == T_5301 ? T_5070_10 : GEN_85;
assign GEN_87 = 5'hb == T_5301 ? T_5070_11 : GEN_86;
assign GEN_88 = 5'hc == T_5301 ? T_5070_12 : GEN_87;
assign GEN_89 = 5'hd == T_5301 ? T_5070_13 : GEN_88;
assign GEN_90 = 5'he == T_5301 ? T_5070_14 : GEN_89;
assign GEN_91 = 5'hf == T_5301 ? T_5070_15 : GEN_90;
assign GEN_92 = 5'h10 == T_5301 ? T_5070_16 : GEN_91;
assign GEN_93 = 5'h11 == T_5301 ? T_5070_17 : GEN_92;
assign GEN_94 = 5'h12 == T_5301 ? T_5070_18 : GEN_93;
assign GEN_95 = 5'h13 == T_5301 ? T_5070_19 : GEN_94;
assign GEN_96 = 5'h14 == T_5301 ? T_5070_20 : GEN_95;
assign GEN_97 = 5'h15 == T_5301 ? T_5070_21 : GEN_96;
assign GEN_98 = 5'h16 == T_5301 ? T_5070_22 : GEN_97;
assign GEN_99 = 5'h17 == T_5301 ? T_5070_23 : GEN_98;
assign GEN_100 = 5'h18 == T_5301 ? T_5070_24 : GEN_99;
assign GEN_101 = 5'h19 == T_5301 ? T_5070_25 : GEN_100;
assign GEN_102 = 5'h1a == T_5301 ? T_5070_26 : GEN_101;
assign GEN_103 = 5'h1b == T_5301 ? T_5070_27 : GEN_102;
assign GEN_104 = 5'h1c == T_5301 ? T_5070_28 : GEN_103;
assign GEN_105 = 5'h1d == T_5301 ? T_5070_29 : GEN_104;
assign GEN_106 = 5'h1e == T_5301 ? T_5070_30 : GEN_105;
assign GEN_107 = 5'h1f == T_5301 ? T_5070_31 : GEN_106;
assign GEN_3 = GEN_138;
assign GEN_108 = 5'h1 == T_5301 ? T_5253_1 : T_5253_0;
assign GEN_109 = 5'h2 == T_5301 ? T_5253_2 : GEN_108;
assign GEN_110 = 5'h3 == T_5301 ? T_5253_3 : GEN_109;
assign GEN_111 = 5'h4 == T_5301 ? T_5253_4 : GEN_110;
assign GEN_112 = 5'h5 == T_5301 ? T_5253_5 : GEN_111;
assign GEN_113 = 5'h6 == T_5301 ? T_5253_6 : GEN_112;
assign GEN_114 = 5'h7 == T_5301 ? T_5253_7 : GEN_113;
assign GEN_115 = 5'h8 == T_5301 ? T_5253_8 : GEN_114;
assign GEN_116 = 5'h9 == T_5301 ? T_5253_9 : GEN_115;
assign GEN_117 = 5'ha == T_5301 ? T_5253_10 : GEN_116;
assign GEN_118 = 5'hb == T_5301 ? T_5253_11 : GEN_117;
assign GEN_119 = 5'hc == T_5301 ? T_5253_12 : GEN_118;
assign GEN_120 = 5'hd == T_5301 ? T_5253_13 : GEN_119;
assign GEN_121 = 5'he == T_5301 ? T_5253_14 : GEN_120;
assign GEN_122 = 5'hf == T_5301 ? T_5253_15 : GEN_121;
assign GEN_123 = 5'h10 == T_5301 ? T_5253_16 : GEN_122;
assign GEN_124 = 5'h11 == T_5301 ? T_5253_17 : GEN_123;
assign GEN_125 = 5'h12 == T_5301 ? T_5253_18 : GEN_124;
assign GEN_126 = 5'h13 == T_5301 ? T_5253_19 : GEN_125;
assign GEN_127 = 5'h14 == T_5301 ? T_5253_20 : GEN_126;
assign GEN_128 = 5'h15 == T_5301 ? T_5253_21 : GEN_127;
assign GEN_129 = 5'h16 == T_5301 ? T_5253_22 : GEN_128;
assign GEN_130 = 5'h17 == T_5301 ? T_5253_23 : GEN_129;
assign GEN_131 = 5'h18 == T_5301 ? T_5253_24 : GEN_130;
assign GEN_132 = 5'h19 == T_5301 ? T_5253_25 : GEN_131;
assign GEN_133 = 5'h1a == T_5301 ? T_5253_26 : GEN_132;
assign GEN_134 = 5'h1b == T_5301 ? T_5253_27 : GEN_133;
assign GEN_135 = 5'h1c == T_5301 ? T_5253_28 : GEN_134;
assign GEN_136 = 5'h1d == T_5301 ? T_5253_29 : GEN_135;
assign GEN_137 = 5'h1e == T_5301 ? T_5253_30 : GEN_136;
assign GEN_138 = 5'h1f == T_5301 ? T_5253_31 : GEN_137;
assign T_5321 = T_3370_bits_read ? GEN_2 : GEN_3;
assign T_5322 = T_3370_ready & T_5318;
assign T_5323 = T_3295_valid & T_5318;
assign T_5324 = T_3334_ready & T_5321;
assign T_5325 = T_3370_valid & T_5321;
assign T_5327 = 32'h1 << T_5301;
assign T_5328 = {T_3493,T_3457};
assign T_5329 = {T_3556,T_3529};
assign T_5330 = {T_5329,T_5328};
assign T_5331 = {T_3466,T_3592};
assign T_5332 = {T_3547,T_3502};
assign T_5333 = {T_5332,T_5331};
assign T_5334 = {T_5333,T_5330};
assign T_5335 = {T_3511,T_3583};
assign T_5336 = {T_3574,T_3475};
assign T_5337 = {T_5336,T_5335};
assign T_5338 = {T_3520,T_3538};
assign T_5339 = {T_3601,T_3484};
assign T_5340 = {T_5339,T_5338};
assign T_5341 = {T_5340,T_5337};
assign T_5342 = {T_5341,T_5334};
assign T_5343 = {1'h1,T_3565};
assign T_5345 = {2'h3,T_5343};
assign T_5349 = {4'hf,T_5345};
assign T_5357 = {8'hff,T_5349};
assign T_5358 = {T_5357,T_5342};
assign T_5359 = T_5327 & T_5358;
assign T_5394 = T_3295_valid & T_3370_ready;
assign T_5395 = T_5394 & T_3370_bits_read;
assign T_5396 = T_5359[0];
assign T_5397 = T_5395 & T_5396;
assign T_5400 = T_3370_bits_read == 1'h0;
assign T_5401 = T_5394 & T_5400;
assign T_5403 = T_5401 & T_5396;
assign T_5404 = T_3370_valid & T_3334_ready;
assign T_5405 = T_5404 & T_3370_bits_read;
assign T_5407 = T_5405 & T_5396;
assign T_5411 = T_5404 & T_5400;
assign T_5413 = T_5411 & T_5396;
assign T_5416 = T_5359[1];
assign T_5417 = T_5395 & T_5416;
assign T_5423 = T_5401 & T_5416;
assign T_5427 = T_5405 & T_5416;
assign T_5433 = T_5411 & T_5416;
assign T_5436 = T_5359[2];
assign T_5437 = T_5395 & T_5436;
assign T_5443 = T_5401 & T_5436;
assign T_5447 = T_5405 & T_5436;
assign T_5453 = T_5411 & T_5436;
assign T_5456 = T_5359[3];
assign T_5457 = T_5395 & T_5456;
assign T_5463 = T_5401 & T_5456;
assign T_5467 = T_5405 & T_5456;
assign T_5473 = T_5411 & T_5456;
assign T_5476 = T_5359[4];
assign T_5477 = T_5395 & T_5476;
assign T_5483 = T_5401 & T_5476;
assign T_5487 = T_5405 & T_5476;
assign T_5493 = T_5411 & T_5476;
assign T_5496 = T_5359[5];
assign T_5497 = T_5395 & T_5496;
assign T_5503 = T_5401 & T_5496;
assign T_5507 = T_5405 & T_5496;
assign T_5513 = T_5411 & T_5496;
assign T_5516 = T_5359[6];
assign T_5517 = T_5395 & T_5516;
assign T_5523 = T_5401 & T_5516;
assign T_5527 = T_5405 & T_5516;
assign T_5533 = T_5411 & T_5516;
assign T_5536 = T_5359[7];
assign T_5537 = T_5395 & T_5536;
assign T_5543 = T_5401 & T_5536;
assign T_5547 = T_5405 & T_5536;
assign T_5553 = T_5411 & T_5536;
assign T_5556 = T_5359[8];
assign T_5557 = T_5395 & T_5556;
assign T_5563 = T_5401 & T_5556;
assign T_5567 = T_5405 & T_5556;
assign T_5573 = T_5411 & T_5556;
assign T_5576 = T_5359[9];
assign T_5577 = T_5395 & T_5576;
assign T_5583 = T_5401 & T_5576;
assign T_5587 = T_5405 & T_5576;
assign T_5593 = T_5411 & T_5576;
assign T_5596 = T_5359[10];
assign T_5597 = T_5395 & T_5596;
assign T_5603 = T_5401 & T_5596;
assign T_5607 = T_5405 & T_5596;
assign T_5613 = T_5411 & T_5596;
assign T_5616 = T_5359[11];
assign T_5617 = T_5395 & T_5616;
assign T_5623 = T_5401 & T_5616;
assign T_5627 = T_5405 & T_5616;
assign T_5633 = T_5411 & T_5616;
assign T_5636 = T_5359[12];
assign T_5637 = T_5395 & T_5636;
assign T_5643 = T_5401 & T_5636;
assign T_5647 = T_5405 & T_5636;
assign T_5653 = T_5411 & T_5636;
assign T_5656 = T_5359[13];
assign T_5657 = T_5395 & T_5656;
assign T_5663 = T_5401 & T_5656;
assign T_5667 = T_5405 & T_5656;
assign T_5673 = T_5411 & T_5656;
assign T_5676 = T_5359[14];
assign T_5677 = T_5395 & T_5676;
assign T_5683 = T_5401 & T_5676;
assign T_5687 = T_5405 & T_5676;
assign T_5693 = T_5411 & T_5676;
assign T_5696 = T_5359[15];
assign T_5697 = T_5395 & T_5696;
assign T_5703 = T_5401 & T_5696;
assign T_5707 = T_5405 & T_5696;
assign T_5713 = T_5411 & T_5696;
assign T_5716 = T_5359[16];
assign T_5717 = T_5395 & T_5716;
assign T_5723 = T_5401 & T_5716;
assign T_5727 = T_5405 & T_5716;
assign T_5733 = T_5411 & T_5716;
assign T_6137_0 = T_3457;
assign T_6137_1 = T_3493;
assign T_6137_2 = T_3529;
assign T_6137_3 = T_3556;
assign T_6137_4 = T_3592;
assign T_6137_5 = T_3466;
assign T_6137_6 = T_3502;
assign T_6137_7 = T_3547;
assign T_6137_8 = T_3583;
assign T_6137_9 = T_3511;
assign T_6137_10 = T_3475;
assign T_6137_11 = T_3574;
assign T_6137_12 = T_3538;
assign T_6137_13 = T_3520;
assign T_6137_14 = T_3484;
assign T_6137_15 = T_3601;
assign T_6137_16 = T_3565;
assign T_6137_17 = 1'h1;
assign T_6137_18 = 1'h1;
assign T_6137_19 = 1'h1;
assign T_6137_20 = 1'h1;
assign T_6137_21 = 1'h1;
assign T_6137_22 = 1'h1;
assign T_6137_23 = 1'h1;
assign T_6137_24 = 1'h1;
assign T_6137_25 = 1'h1;
assign T_6137_26 = 1'h1;
assign T_6137_27 = 1'h1;
assign T_6137_28 = 1'h1;
assign T_6137_29 = 1'h1;
assign T_6137_30 = 1'h1;
assign T_6137_31 = 1'h1;
assign T_6208_0 = valueReg;
assign T_6208_1 = T_4047;
assign T_6208_2 = T_4219;
assign T_6208_3 = portReg;
assign T_6208_4 = T_4511;
assign T_6208_5 = dsReg;
assign T_6208_6 = riseIeReg;
assign T_6208_7 = riseIpReg;
assign T_6208_8 = fallIeReg;
assign T_6208_9 = fallIpReg;
assign T_6208_10 = highIeReg;
assign T_6208_11 = highIpReg;
assign T_6208_12 = lowIeReg;
assign T_6208_13 = lowIpReg;
assign T_6208_14 = T_4007;
assign T_6208_15 = iofSelReg;
assign T_6208_16 = xorReg;
assign T_6208_17 = 32'h0;
assign T_6208_18 = 32'h0;
assign T_6208_19 = 32'h0;
assign T_6208_20 = 32'h0;
assign T_6208_21 = 32'h0;
assign T_6208_22 = 32'h0;
assign T_6208_23 = 32'h0;
assign T_6208_24 = 32'h0;
assign T_6208_25 = 32'h0;
assign T_6208_26 = 32'h0;
assign T_6208_27 = 32'h0;
assign T_6208_28 = 32'h0;
assign T_6208_29 = 32'h0;
assign T_6208_30 = 32'h0;
assign T_6208_31 = 32'h0;
assign GEN_4 = GEN_169;
assign GEN_139 = 5'h1 == T_5301 ? T_6137_1 : T_6137_0;
assign GEN_140 = 5'h2 == T_5301 ? T_6137_2 : GEN_139;
assign GEN_141 = 5'h3 == T_5301 ? T_6137_3 : GEN_140;
assign GEN_142 = 5'h4 == T_5301 ? T_6137_4 : GEN_141;
assign GEN_143 = 5'h5 == T_5301 ? T_6137_5 : GEN_142;
assign GEN_144 = 5'h6 == T_5301 ? T_6137_6 : GEN_143;
assign GEN_145 = 5'h7 == T_5301 ? T_6137_7 : GEN_144;
assign GEN_146 = 5'h8 == T_5301 ? T_6137_8 : GEN_145;
assign GEN_147 = 5'h9 == T_5301 ? T_6137_9 : GEN_146;
assign GEN_148 = 5'ha == T_5301 ? T_6137_10 : GEN_147;
assign GEN_149 = 5'hb == T_5301 ? T_6137_11 : GEN_148;
assign GEN_150 = 5'hc == T_5301 ? T_6137_12 : GEN_149;
assign GEN_151 = 5'hd == T_5301 ? T_6137_13 : GEN_150;
assign GEN_152 = 5'he == T_5301 ? T_6137_14 : GEN_151;
assign GEN_153 = 5'hf == T_5301 ? T_6137_15 : GEN_152;
assign GEN_154 = 5'h10 == T_5301 ? T_6137_16 : GEN_153;
assign GEN_155 = 5'h11 == T_5301 ? T_6137_17 : GEN_154;
assign GEN_156 = 5'h12 == T_5301 ? T_6137_18 : GEN_155;
assign GEN_157 = 5'h13 == T_5301 ? T_6137_19 : GEN_156;
assign GEN_158 = 5'h14 == T_5301 ? T_6137_20 : GEN_157;
assign GEN_159 = 5'h15 == T_5301 ? T_6137_21 : GEN_158;
assign GEN_160 = 5'h16 == T_5301 ? T_6137_22 : GEN_159;
assign GEN_161 = 5'h17 == T_5301 ? T_6137_23 : GEN_160;
assign GEN_162 = 5'h18 == T_5301 ? T_6137_24 : GEN_161;
assign GEN_163 = 5'h19 == T_5301 ? T_6137_25 : GEN_162;
assign GEN_164 = 5'h1a == T_5301 ? T_6137_26 : GEN_163;
assign GEN_165 = 5'h1b == T_5301 ? T_6137_27 : GEN_164;
assign GEN_166 = 5'h1c == T_5301 ? T_6137_28 : GEN_165;
assign GEN_167 = 5'h1d == T_5301 ? T_6137_29 : GEN_166;
assign GEN_168 = 5'h1e == T_5301 ? T_6137_30 : GEN_167;
assign GEN_169 = 5'h1f == T_5301 ? T_6137_31 : GEN_168;
assign GEN_5 = GEN_200;
assign GEN_170 = 5'h1 == T_5301 ? T_6208_1 : T_6208_0;
assign GEN_171 = 5'h2 == T_5301 ? T_6208_2 : GEN_170;
assign GEN_172 = 5'h3 == T_5301 ? T_6208_3 : GEN_171;
assign GEN_173 = 5'h4 == T_5301 ? T_6208_4 : GEN_172;
assign GEN_174 = 5'h5 == T_5301 ? T_6208_5 : GEN_173;
assign GEN_175 = 5'h6 == T_5301 ? T_6208_6 : GEN_174;
assign GEN_176 = 5'h7 == T_5301 ? T_6208_7 : GEN_175;
assign GEN_177 = 5'h8 == T_5301 ? T_6208_8 : GEN_176;
assign GEN_178 = 5'h9 == T_5301 ? T_6208_9 : GEN_177;
assign GEN_179 = 5'ha == T_5301 ? T_6208_10 : GEN_178;
assign GEN_180 = 5'hb == T_5301 ? T_6208_11 : GEN_179;
assign GEN_181 = 5'hc == T_5301 ? T_6208_12 : GEN_180;
assign GEN_182 = 5'hd == T_5301 ? T_6208_13 : GEN_181;
assign GEN_183 = 5'he == T_5301 ? T_6208_14 : GEN_182;
assign GEN_184 = 5'hf == T_5301 ? T_6208_15 : GEN_183;
assign GEN_185 = 5'h10 == T_5301 ? T_6208_16 : GEN_184;
assign GEN_186 = 5'h11 == T_5301 ? T_6208_17 : GEN_185;
assign GEN_187 = 5'h12 == T_5301 ? T_6208_18 : GEN_186;
assign GEN_188 = 5'h13 == T_5301 ? T_6208_19 : GEN_187;
assign GEN_189 = 5'h14 == T_5301 ? T_6208_20 : GEN_188;
assign GEN_190 = 5'h15 == T_5301 ? T_6208_21 : GEN_189;
assign GEN_191 = 5'h16 == T_5301 ? T_6208_22 : GEN_190;
assign GEN_192 = 5'h17 == T_5301 ? T_6208_23 : GEN_191;
assign GEN_193 = 5'h18 == T_5301 ? T_6208_24 : GEN_192;
assign GEN_194 = 5'h19 == T_5301 ? T_6208_25 : GEN_193;
assign GEN_195 = 5'h1a == T_5301 ? T_6208_26 : GEN_194;
assign GEN_196 = 5'h1b == T_5301 ? T_6208_27 : GEN_195;
assign GEN_197 = 5'h1c == T_5301 ? T_6208_28 : GEN_196;
assign GEN_198 = 5'h1d == T_5301 ? T_6208_29 : GEN_197;
assign GEN_199 = 5'h1e == T_5301 ? T_6208_30 : GEN_198;
assign GEN_200 = 5'h1f == T_5301 ? T_6208_31 : GEN_199;
assign T_6245 = GEN_4 ? GEN_5 : 32'h0;
assign T_6246 = T_3334_bits_extra[9:8];
assign T_6248 = T_3334_bits_extra[7:3];
assign T_6249 = T_3334_bits_extra[2:0];
assign T_6260_opcode = 3'h0;
assign T_6260_param = 2'h0;
assign T_6260_size = T_6249;
assign T_6260_source = T_6248;
assign T_6260_sink = 1'h0;
assign T_6260_addr_lo = T_6246;
assign T_6260_data = 32'h0;
assign T_6260_error = 1'h0;
assign swPinCtrl_0_oval = T_7570;
assign swPinCtrl_0_oe = T_7571;
assign swPinCtrl_0_ie = T_7573;
assign swPinCtrl_0_pue = T_7569;
assign swPinCtrl_0_ds = T_7572;
assign swPinCtrl_1_oval = T_7606;
assign swPinCtrl_1_oe = T_7607;
assign swPinCtrl_1_ie = T_7609;
assign swPinCtrl_1_pue = T_7605;
assign swPinCtrl_1_ds = T_7608;
assign swPinCtrl_2_oval = T_7642;
assign swPinCtrl_2_oe = T_7643;
assign swPinCtrl_2_ie = T_7645;
assign swPinCtrl_2_pue = T_7641;
assign swPinCtrl_2_ds = T_7644;
assign swPinCtrl_3_oval = T_7678;
assign swPinCtrl_3_oe = T_7679;
assign swPinCtrl_3_ie = T_7681;
assign swPinCtrl_3_pue = T_7677;
assign swPinCtrl_3_ds = T_7680;
assign swPinCtrl_4_oval = T_7714;
assign swPinCtrl_4_oe = T_7715;
assign swPinCtrl_4_ie = T_7717;
assign swPinCtrl_4_pue = T_7713;
assign swPinCtrl_4_ds = T_7716;
assign swPinCtrl_5_oval = T_7750;
assign swPinCtrl_5_oe = T_7751;
assign swPinCtrl_5_ie = T_7753;
assign swPinCtrl_5_pue = T_7749;
assign swPinCtrl_5_ds = T_7752;
assign swPinCtrl_6_oval = T_7786;
assign swPinCtrl_6_oe = T_7787;
assign swPinCtrl_6_ie = T_7789;
assign swPinCtrl_6_pue = T_7785;
assign swPinCtrl_6_ds = T_7788;
assign swPinCtrl_7_oval = T_7822;
assign swPinCtrl_7_oe = T_7823;
assign swPinCtrl_7_ie = T_7825;
assign swPinCtrl_7_pue = T_7821;
assign swPinCtrl_7_ds = T_7824;
assign swPinCtrl_8_oval = T_7858;
assign swPinCtrl_8_oe = T_7859;
assign swPinCtrl_8_ie = T_7861;
assign swPinCtrl_8_pue = T_7857;
assign swPinCtrl_8_ds = T_7860;
assign swPinCtrl_9_oval = T_7894;
assign swPinCtrl_9_oe = T_7895;
assign swPinCtrl_9_ie = T_7897;
assign swPinCtrl_9_pue = T_7893;
assign swPinCtrl_9_ds = T_7896;
assign swPinCtrl_10_oval = T_7930;
assign swPinCtrl_10_oe = T_7931;
assign swPinCtrl_10_ie = T_7933;
assign swPinCtrl_10_pue = T_7929;
assign swPinCtrl_10_ds = T_7932;
assign swPinCtrl_11_oval = T_7966;
assign swPinCtrl_11_oe = T_7967;
assign swPinCtrl_11_ie = T_7969;
assign swPinCtrl_11_pue = T_7965;
assign swPinCtrl_11_ds = T_7968;
assign swPinCtrl_12_oval = T_8002;
assign swPinCtrl_12_oe = T_8003;
assign swPinCtrl_12_ie = T_8005;
assign swPinCtrl_12_pue = T_8001;
assign swPinCtrl_12_ds = T_8004;
assign swPinCtrl_13_oval = T_8038;
assign swPinCtrl_13_oe = T_8039;
assign swPinCtrl_13_ie = T_8041;
assign swPinCtrl_13_pue = T_8037;
assign swPinCtrl_13_ds = T_8040;
assign swPinCtrl_14_oval = T_8074;
assign swPinCtrl_14_oe = T_8075;
assign swPinCtrl_14_ie = T_8077;
assign swPinCtrl_14_pue = T_8073;
assign swPinCtrl_14_ds = T_8076;
assign swPinCtrl_15_oval = T_8110;
assign swPinCtrl_15_oe = T_8111;
assign swPinCtrl_15_ie = T_8113;
assign swPinCtrl_15_pue = T_8109;
assign swPinCtrl_15_ds = T_8112;
assign swPinCtrl_16_oval = T_8146;
assign swPinCtrl_16_oe = T_8147;
assign swPinCtrl_16_ie = T_8149;
assign swPinCtrl_16_pue = T_8145;
assign swPinCtrl_16_ds = T_8148;
assign swPinCtrl_17_oval = T_8182;
assign swPinCtrl_17_oe = T_8183;
assign swPinCtrl_17_ie = T_8185;
assign swPinCtrl_17_pue = T_8181;
assign swPinCtrl_17_ds = T_8184;
assign swPinCtrl_18_oval = T_8218;
assign swPinCtrl_18_oe = T_8219;
assign swPinCtrl_18_ie = T_8221;
assign swPinCtrl_18_pue = T_8217;
assign swPinCtrl_18_ds = T_8220;
assign swPinCtrl_19_oval = T_8254;
assign swPinCtrl_19_oe = T_8255;
assign swPinCtrl_19_ie = T_8257;
assign swPinCtrl_19_pue = T_8253;
assign swPinCtrl_19_ds = T_8256;
assign swPinCtrl_20_oval = T_8290;
assign swPinCtrl_20_oe = T_8291;
assign swPinCtrl_20_ie = T_8293;
assign swPinCtrl_20_pue = T_8289;
assign swPinCtrl_20_ds = T_8292;
assign swPinCtrl_21_oval = T_8326;
assign swPinCtrl_21_oe = T_8327;
assign swPinCtrl_21_ie = T_8329;
assign swPinCtrl_21_pue = T_8325;
assign swPinCtrl_21_ds = T_8328;
assign swPinCtrl_22_oval = T_8362;
assign swPinCtrl_22_oe = T_8363;
assign swPinCtrl_22_ie = T_8365;
assign swPinCtrl_22_pue = T_8361;
assign swPinCtrl_22_ds = T_8364;
assign swPinCtrl_23_oval = T_8398;
assign swPinCtrl_23_oe = T_8399;
assign swPinCtrl_23_ie = T_8401;
assign swPinCtrl_23_pue = T_8397;
assign swPinCtrl_23_ds = T_8400;
assign swPinCtrl_24_oval = T_8434;
assign swPinCtrl_24_oe = T_8435;
assign swPinCtrl_24_ie = T_8437;
assign swPinCtrl_24_pue = T_8433;
assign swPinCtrl_24_ds = T_8436;
assign swPinCtrl_25_oval = T_8470;
assign swPinCtrl_25_oe = T_8471;
assign swPinCtrl_25_ie = T_8473;
assign swPinCtrl_25_pue = T_8469;
assign swPinCtrl_25_ds = T_8472;
assign swPinCtrl_26_oval = T_8506;
assign swPinCtrl_26_oe = T_8507;
assign swPinCtrl_26_ie = T_8509;
assign swPinCtrl_26_pue = T_8505;
assign swPinCtrl_26_ds = T_8508;
assign swPinCtrl_27_oval = T_8542;
assign swPinCtrl_27_oe = T_8543;
assign swPinCtrl_27_ie = T_8545;
assign swPinCtrl_27_pue = T_8541;
assign swPinCtrl_27_ds = T_8544;
assign swPinCtrl_28_oval = T_8578;
assign swPinCtrl_28_oe = T_8579;
assign swPinCtrl_28_ie = T_8581;
assign swPinCtrl_28_pue = T_8577;
assign swPinCtrl_28_ds = T_8580;
assign swPinCtrl_29_oval = T_8614;
assign swPinCtrl_29_oe = T_8615;
assign swPinCtrl_29_ie = T_8617;
assign swPinCtrl_29_pue = T_8613;
assign swPinCtrl_29_ds = T_8616;
assign swPinCtrl_30_oval = T_8650;
assign swPinCtrl_30_oe = T_8651;
assign swPinCtrl_30_ie = T_8653;
assign swPinCtrl_30_pue = T_8649;
assign swPinCtrl_30_ds = T_8652;
assign swPinCtrl_31_oval = T_8686;
assign swPinCtrl_31_oe = T_8687;
assign swPinCtrl_31_ie = T_8689;
assign swPinCtrl_31_pue = T_8685;
assign swPinCtrl_31_ds = T_8688;
assign iof0Ctrl_0_oval = GEN_201;
assign iof0Ctrl_0_oe = GEN_202;
assign iof0Ctrl_0_ie = GEN_203;
assign iof0Ctrl_1_oval = GEN_207;
assign iof0Ctrl_1_oe = GEN_208;
assign iof0Ctrl_1_ie = GEN_209;
assign iof0Ctrl_2_oval = GEN_213;
assign iof0Ctrl_2_oe = GEN_214;
assign iof0Ctrl_2_ie = GEN_215;
assign iof0Ctrl_3_oval = GEN_219;
assign iof0Ctrl_3_oe = GEN_220;
assign iof0Ctrl_3_ie = GEN_221;
assign iof0Ctrl_4_oval = GEN_225;
assign iof0Ctrl_4_oe = GEN_226;
assign iof0Ctrl_4_ie = GEN_227;
assign iof0Ctrl_5_oval = GEN_231;
assign iof0Ctrl_5_oe = GEN_232;
assign iof0Ctrl_5_ie = GEN_233;
assign iof0Ctrl_6_oval = GEN_237;
assign iof0Ctrl_6_oe = GEN_238;
assign iof0Ctrl_6_ie = GEN_239;
assign iof0Ctrl_7_oval = GEN_243;
assign iof0Ctrl_7_oe = GEN_244;
assign iof0Ctrl_7_ie = GEN_245;
assign iof0Ctrl_8_oval = GEN_249;
assign iof0Ctrl_8_oe = GEN_250;
assign iof0Ctrl_8_ie = GEN_251;
assign iof0Ctrl_9_oval = GEN_255;
assign iof0Ctrl_9_oe = GEN_256;
assign iof0Ctrl_9_ie = GEN_257;
assign iof0Ctrl_10_oval = GEN_261;
assign iof0Ctrl_10_oe = GEN_262;
assign iof0Ctrl_10_ie = GEN_263;
assign iof0Ctrl_11_oval = GEN_267;
assign iof0Ctrl_11_oe = GEN_268;
assign iof0Ctrl_11_ie = GEN_269;
assign iof0Ctrl_12_oval = GEN_273;
assign iof0Ctrl_12_oe = GEN_274;
assign iof0Ctrl_12_ie = GEN_275;
assign iof0Ctrl_13_oval = GEN_279;
assign iof0Ctrl_13_oe = GEN_280;
assign iof0Ctrl_13_ie = GEN_281;
assign iof0Ctrl_14_oval = GEN_285;
assign iof0Ctrl_14_oe = GEN_286;
assign iof0Ctrl_14_ie = GEN_287;
assign iof0Ctrl_15_oval = GEN_291;
assign iof0Ctrl_15_oe = GEN_292;
assign iof0Ctrl_15_ie = GEN_293;
assign iof0Ctrl_16_oval = GEN_297;
assign iof0Ctrl_16_oe = GEN_298;
assign iof0Ctrl_16_ie = GEN_299;
assign iof0Ctrl_17_oval = GEN_303;
assign iof0Ctrl_17_oe = GEN_304;
assign iof0Ctrl_17_ie = GEN_305;
assign iof0Ctrl_18_oval = GEN_309;
assign iof0Ctrl_18_oe = GEN_310;
assign iof0Ctrl_18_ie = GEN_311;
assign iof0Ctrl_19_oval = GEN_315;
assign iof0Ctrl_19_oe = GEN_316;
assign iof0Ctrl_19_ie = GEN_317;
assign iof0Ctrl_20_oval = GEN_321;
assign iof0Ctrl_20_oe = GEN_322;
assign iof0Ctrl_20_ie = GEN_323;
assign iof0Ctrl_21_oval = GEN_327;
assign iof0Ctrl_21_oe = GEN_328;
assign iof0Ctrl_21_ie = GEN_329;
assign iof0Ctrl_22_oval = GEN_333;
assign iof0Ctrl_22_oe = GEN_334;
assign iof0Ctrl_22_ie = GEN_335;
assign iof0Ctrl_23_oval = GEN_339;
assign iof0Ctrl_23_oe = GEN_340;
assign iof0Ctrl_23_ie = GEN_341;
assign iof0Ctrl_24_oval = GEN_345;
assign iof0Ctrl_24_oe = GEN_346;
assign iof0Ctrl_24_ie = GEN_347;
assign iof0Ctrl_25_oval = GEN_351;
assign iof0Ctrl_25_oe = GEN_352;
assign iof0Ctrl_25_ie = GEN_353;
assign iof0Ctrl_26_oval = GEN_357;
assign iof0Ctrl_26_oe = GEN_358;
assign iof0Ctrl_26_ie = GEN_359;
assign iof0Ctrl_27_oval = GEN_363;
assign iof0Ctrl_27_oe = GEN_364;
assign iof0Ctrl_27_ie = GEN_365;
assign iof0Ctrl_28_oval = GEN_369;
assign iof0Ctrl_28_oe = GEN_370;
assign iof0Ctrl_28_ie = GEN_371;
assign iof0Ctrl_29_oval = GEN_375;
assign iof0Ctrl_29_oe = GEN_376;
assign iof0Ctrl_29_ie = GEN_377;
assign iof0Ctrl_30_oval = GEN_381;
assign iof0Ctrl_30_oe = GEN_382;
assign iof0Ctrl_30_ie = GEN_383;
assign iof0Ctrl_31_oval = GEN_387;
assign iof0Ctrl_31_oe = GEN_388;
assign iof0Ctrl_31_ie = GEN_389;
assign iof1Ctrl_0_oval = GEN_204;
assign iof1Ctrl_0_oe = GEN_205;
assign iof1Ctrl_0_ie = GEN_206;
assign iof1Ctrl_1_oval = GEN_210;
assign iof1Ctrl_1_oe = GEN_211;
assign iof1Ctrl_1_ie = GEN_212;
assign iof1Ctrl_2_oval = GEN_216;
assign iof1Ctrl_2_oe = GEN_217;
assign iof1Ctrl_2_ie = GEN_218;
assign iof1Ctrl_3_oval = GEN_222;
assign iof1Ctrl_3_oe = GEN_223;
assign iof1Ctrl_3_ie = GEN_224;
assign iof1Ctrl_4_oval = GEN_228;
assign iof1Ctrl_4_oe = GEN_229;
assign iof1Ctrl_4_ie = GEN_230;
assign iof1Ctrl_5_oval = GEN_234;
assign iof1Ctrl_5_oe = GEN_235;
assign iof1Ctrl_5_ie = GEN_236;
assign iof1Ctrl_6_oval = GEN_240;
assign iof1Ctrl_6_oe = GEN_241;
assign iof1Ctrl_6_ie = GEN_242;
assign iof1Ctrl_7_oval = GEN_246;
assign iof1Ctrl_7_oe = GEN_247;
assign iof1Ctrl_7_ie = GEN_248;
assign iof1Ctrl_8_oval = GEN_252;
assign iof1Ctrl_8_oe = GEN_253;
assign iof1Ctrl_8_ie = GEN_254;
assign iof1Ctrl_9_oval = GEN_258;
assign iof1Ctrl_9_oe = GEN_259;
assign iof1Ctrl_9_ie = GEN_260;
assign iof1Ctrl_10_oval = GEN_264;
assign iof1Ctrl_10_oe = GEN_265;
assign iof1Ctrl_10_ie = GEN_266;
assign iof1Ctrl_11_oval = GEN_270;
assign iof1Ctrl_11_oe = GEN_271;
assign iof1Ctrl_11_ie = GEN_272;
assign iof1Ctrl_12_oval = GEN_276;
assign iof1Ctrl_12_oe = GEN_277;
assign iof1Ctrl_12_ie = GEN_278;
assign iof1Ctrl_13_oval = GEN_282;
assign iof1Ctrl_13_oe = GEN_283;
assign iof1Ctrl_13_ie = GEN_284;
assign iof1Ctrl_14_oval = GEN_288;
assign iof1Ctrl_14_oe = GEN_289;
assign iof1Ctrl_14_ie = GEN_290;
assign iof1Ctrl_15_oval = GEN_294;
assign iof1Ctrl_15_oe = GEN_295;
assign iof1Ctrl_15_ie = GEN_296;
assign iof1Ctrl_16_oval = GEN_300;
assign iof1Ctrl_16_oe = GEN_301;
assign iof1Ctrl_16_ie = GEN_302;
assign iof1Ctrl_17_oval = GEN_306;
assign iof1Ctrl_17_oe = GEN_307;
assign iof1Ctrl_17_ie = GEN_308;
assign iof1Ctrl_18_oval = GEN_312;
assign iof1Ctrl_18_oe = GEN_313;
assign iof1Ctrl_18_ie = GEN_314;
assign iof1Ctrl_19_oval = GEN_318;
assign iof1Ctrl_19_oe = GEN_319;
assign iof1Ctrl_19_ie = GEN_320;
assign iof1Ctrl_20_oval = GEN_324;
assign iof1Ctrl_20_oe = GEN_325;
assign iof1Ctrl_20_ie = GEN_326;
assign iof1Ctrl_21_oval = GEN_330;
assign iof1Ctrl_21_oe = GEN_331;
assign iof1Ctrl_21_ie = GEN_332;
assign iof1Ctrl_22_oval = GEN_336;
assign iof1Ctrl_22_oe = GEN_337;
assign iof1Ctrl_22_ie = GEN_338;
assign iof1Ctrl_23_oval = GEN_342;
assign iof1Ctrl_23_oe = GEN_343;
assign iof1Ctrl_23_ie = GEN_344;
assign iof1Ctrl_24_oval = GEN_348;
assign iof1Ctrl_24_oe = GEN_349;
assign iof1Ctrl_24_ie = GEN_350;
assign iof1Ctrl_25_oval = GEN_354;
assign iof1Ctrl_25_oe = GEN_355;
assign iof1Ctrl_25_ie = GEN_356;
assign iof1Ctrl_26_oval = GEN_360;
assign iof1Ctrl_26_oe = GEN_361;
assign iof1Ctrl_26_ie = GEN_362;
assign iof1Ctrl_27_oval = GEN_366;
assign iof1Ctrl_27_oe = GEN_367;
assign iof1Ctrl_27_ie = GEN_368;
assign iof1Ctrl_28_oval = GEN_372;
assign iof1Ctrl_28_oe = GEN_373;
assign iof1Ctrl_28_ie = GEN_374;
assign iof1Ctrl_29_oval = GEN_378;
assign iof1Ctrl_29_oe = GEN_379;
assign iof1Ctrl_29_ie = GEN_380;
assign iof1Ctrl_30_oval = GEN_384;
assign iof1Ctrl_30_oe = GEN_385;
assign iof1Ctrl_30_ie = GEN_386;
assign iof1Ctrl_31_oval = GEN_390;
assign iof1Ctrl_31_oe = GEN_391;
assign iof1Ctrl_31_ie = GEN_392;
assign iofCtrl_0_oval = T_7575_oval;
assign iofCtrl_0_oe = T_7575_oe;
assign iofCtrl_0_ie = T_7575_ie;
assign iofCtrl_1_oval = T_7611_oval;
assign iofCtrl_1_oe = T_7611_oe;
assign iofCtrl_1_ie = T_7611_ie;
assign iofCtrl_2_oval = T_7647_oval;
assign iofCtrl_2_oe = T_7647_oe;
assign iofCtrl_2_ie = T_7647_ie;
assign iofCtrl_3_oval = T_7683_oval;
assign iofCtrl_3_oe = T_7683_oe;
assign iofCtrl_3_ie = T_7683_ie;
assign iofCtrl_4_oval = T_7719_oval;
assign iofCtrl_4_oe = T_7719_oe;
assign iofCtrl_4_ie = T_7719_ie;
assign iofCtrl_5_oval = T_7755_oval;
assign iofCtrl_5_oe = T_7755_oe;
assign iofCtrl_5_ie = T_7755_ie;
assign iofCtrl_6_oval = T_7791_oval;
assign iofCtrl_6_oe = T_7791_oe;
assign iofCtrl_6_ie = T_7791_ie;
assign iofCtrl_7_oval = T_7827_oval;
assign iofCtrl_7_oe = T_7827_oe;
assign iofCtrl_7_ie = T_7827_ie;
assign iofCtrl_8_oval = T_7863_oval;
assign iofCtrl_8_oe = T_7863_oe;
assign iofCtrl_8_ie = T_7863_ie;
assign iofCtrl_9_oval = T_7899_oval;
assign iofCtrl_9_oe = T_7899_oe;
assign iofCtrl_9_ie = T_7899_ie;
assign iofCtrl_10_oval = T_7935_oval;
assign iofCtrl_10_oe = T_7935_oe;
assign iofCtrl_10_ie = T_7935_ie;
assign iofCtrl_11_oval = T_7971_oval;
assign iofCtrl_11_oe = T_7971_oe;
assign iofCtrl_11_ie = T_7971_ie;
assign iofCtrl_12_oval = T_8007_oval;
assign iofCtrl_12_oe = T_8007_oe;
assign iofCtrl_12_ie = T_8007_ie;
assign iofCtrl_13_oval = T_8043_oval;
assign iofCtrl_13_oe = T_8043_oe;
assign iofCtrl_13_ie = T_8043_ie;
assign iofCtrl_14_oval = T_8079_oval;
assign iofCtrl_14_oe = T_8079_oe;
assign iofCtrl_14_ie = T_8079_ie;
assign iofCtrl_15_oval = T_8115_oval;
assign iofCtrl_15_oe = T_8115_oe;
assign iofCtrl_15_ie = T_8115_ie;
assign iofCtrl_16_oval = T_8151_oval;
assign iofCtrl_16_oe = T_8151_oe;
assign iofCtrl_16_ie = T_8151_ie;
assign iofCtrl_17_oval = T_8187_oval;
assign iofCtrl_17_oe = T_8187_oe;
assign iofCtrl_17_ie = T_8187_ie;
assign iofCtrl_18_oval = T_8223_oval;
assign iofCtrl_18_oe = T_8223_oe;
assign iofCtrl_18_ie = T_8223_ie;
assign iofCtrl_19_oval = T_8259_oval;
assign iofCtrl_19_oe = T_8259_oe;
assign iofCtrl_19_ie = T_8259_ie;
assign iofCtrl_20_oval = T_8295_oval;
assign iofCtrl_20_oe = T_8295_oe;
assign iofCtrl_20_ie = T_8295_ie;
assign iofCtrl_21_oval = T_8331_oval;
assign iofCtrl_21_oe = T_8331_oe;
assign iofCtrl_21_ie = T_8331_ie;
assign iofCtrl_22_oval = T_8367_oval;
assign iofCtrl_22_oe = T_8367_oe;
assign iofCtrl_22_ie = T_8367_ie;
assign iofCtrl_23_oval = T_8403_oval;
assign iofCtrl_23_oe = T_8403_oe;
assign iofCtrl_23_ie = T_8403_ie;
assign iofCtrl_24_oval = T_8439_oval;
assign iofCtrl_24_oe = T_8439_oe;
assign iofCtrl_24_ie = T_8439_ie;
assign iofCtrl_25_oval = T_8475_oval;
assign iofCtrl_25_oe = T_8475_oe;
assign iofCtrl_25_ie = T_8475_ie;
assign iofCtrl_26_oval = T_8511_oval;
assign iofCtrl_26_oe = T_8511_oe;
assign iofCtrl_26_ie = T_8511_ie;
assign iofCtrl_27_oval = T_8547_oval;
assign iofCtrl_27_oe = T_8547_oe;
assign iofCtrl_27_ie = T_8547_ie;
assign iofCtrl_28_oval = T_8583_oval;
assign iofCtrl_28_oe = T_8583_oe;
assign iofCtrl_28_ie = T_8583_ie;
assign iofCtrl_29_oval = T_8619_oval;
assign iofCtrl_29_oe = T_8619_oe;
assign iofCtrl_29_ie = T_8619_ie;
assign iofCtrl_30_oval = T_8655_oval;
assign iofCtrl_30_oe = T_8655_oe;
assign iofCtrl_30_ie = T_8655_ie;
assign iofCtrl_31_oval = T_8691_oval;
assign iofCtrl_31_oe = T_8691_oe;
assign iofCtrl_31_ie = T_8691_ie;
assign iofPlusSwPinCtrl_0_oval = iofCtrl_0_oval;
assign iofPlusSwPinCtrl_0_oe = iofCtrl_0_oe;
assign iofPlusSwPinCtrl_0_ie = iofCtrl_0_ie;
assign iofPlusSwPinCtrl_0_pue = swPinCtrl_0_pue;
assign iofPlusSwPinCtrl_0_ds = swPinCtrl_0_ds;
assign iofPlusSwPinCtrl_1_oval = iofCtrl_1_oval;
assign iofPlusSwPinCtrl_1_oe = iofCtrl_1_oe;
assign iofPlusSwPinCtrl_1_ie = iofCtrl_1_ie;
assign iofPlusSwPinCtrl_1_pue = swPinCtrl_1_pue;
assign iofPlusSwPinCtrl_1_ds = swPinCtrl_1_ds;
assign iofPlusSwPinCtrl_2_oval = iofCtrl_2_oval;
assign iofPlusSwPinCtrl_2_oe = iofCtrl_2_oe;
assign iofPlusSwPinCtrl_2_ie = iofCtrl_2_ie;
assign iofPlusSwPinCtrl_2_pue = swPinCtrl_2_pue;
assign iofPlusSwPinCtrl_2_ds = swPinCtrl_2_ds;
assign iofPlusSwPinCtrl_3_oval = iofCtrl_3_oval;
assign iofPlusSwPinCtrl_3_oe = iofCtrl_3_oe;
assign iofPlusSwPinCtrl_3_ie = iofCtrl_3_ie;
assign iofPlusSwPinCtrl_3_pue = swPinCtrl_3_pue;
assign iofPlusSwPinCtrl_3_ds = swPinCtrl_3_ds;
assign iofPlusSwPinCtrl_4_oval = iofCtrl_4_oval;
assign iofPlusSwPinCtrl_4_oe = iofCtrl_4_oe;
assign iofPlusSwPinCtrl_4_ie = iofCtrl_4_ie;
assign iofPlusSwPinCtrl_4_pue = swPinCtrl_4_pue;
assign iofPlusSwPinCtrl_4_ds = swPinCtrl_4_ds;
assign iofPlusSwPinCtrl_5_oval = iofCtrl_5_oval;
assign iofPlusSwPinCtrl_5_oe = iofCtrl_5_oe;
assign iofPlusSwPinCtrl_5_ie = iofCtrl_5_ie;
assign iofPlusSwPinCtrl_5_pue = swPinCtrl_5_pue;
assign iofPlusSwPinCtrl_5_ds = swPinCtrl_5_ds;
assign iofPlusSwPinCtrl_6_oval = iofCtrl_6_oval;
assign iofPlusSwPinCtrl_6_oe = iofCtrl_6_oe;
assign iofPlusSwPinCtrl_6_ie = iofCtrl_6_ie;
assign iofPlusSwPinCtrl_6_pue = swPinCtrl_6_pue;
assign iofPlusSwPinCtrl_6_ds = swPinCtrl_6_ds;
assign iofPlusSwPinCtrl_7_oval = iofCtrl_7_oval;
assign iofPlusSwPinCtrl_7_oe = iofCtrl_7_oe;
assign iofPlusSwPinCtrl_7_ie = iofCtrl_7_ie;
assign iofPlusSwPinCtrl_7_pue = swPinCtrl_7_pue;
assign iofPlusSwPinCtrl_7_ds = swPinCtrl_7_ds;
assign iofPlusSwPinCtrl_8_oval = iofCtrl_8_oval;
assign iofPlusSwPinCtrl_8_oe = iofCtrl_8_oe;
assign iofPlusSwPinCtrl_8_ie = iofCtrl_8_ie;
assign iofPlusSwPinCtrl_8_pue = swPinCtrl_8_pue;
assign iofPlusSwPinCtrl_8_ds = swPinCtrl_8_ds;
assign iofPlusSwPinCtrl_9_oval = iofCtrl_9_oval;
assign iofPlusSwPinCtrl_9_oe = iofCtrl_9_oe;
assign iofPlusSwPinCtrl_9_ie = iofCtrl_9_ie;
assign iofPlusSwPinCtrl_9_pue = swPinCtrl_9_pue;
assign iofPlusSwPinCtrl_9_ds = swPinCtrl_9_ds;
assign iofPlusSwPinCtrl_10_oval = iofCtrl_10_oval;
assign iofPlusSwPinCtrl_10_oe = iofCtrl_10_oe;
assign iofPlusSwPinCtrl_10_ie = iofCtrl_10_ie;
assign iofPlusSwPinCtrl_10_pue = swPinCtrl_10_pue;
assign iofPlusSwPinCtrl_10_ds = swPinCtrl_10_ds;
assign iofPlusSwPinCtrl_11_oval = iofCtrl_11_oval;
assign iofPlusSwPinCtrl_11_oe = iofCtrl_11_oe;
assign iofPlusSwPinCtrl_11_ie = iofCtrl_11_ie;
assign iofPlusSwPinCtrl_11_pue = swPinCtrl_11_pue;
assign iofPlusSwPinCtrl_11_ds = swPinCtrl_11_ds;
assign iofPlusSwPinCtrl_12_oval = iofCtrl_12_oval;
assign iofPlusSwPinCtrl_12_oe = iofCtrl_12_oe;
assign iofPlusSwPinCtrl_12_ie = iofCtrl_12_ie;
assign iofPlusSwPinCtrl_12_pue = swPinCtrl_12_pue;
assign iofPlusSwPinCtrl_12_ds = swPinCtrl_12_ds;
assign iofPlusSwPinCtrl_13_oval = iofCtrl_13_oval;
assign iofPlusSwPinCtrl_13_oe = iofCtrl_13_oe;
assign iofPlusSwPinCtrl_13_ie = iofCtrl_13_ie;
assign iofPlusSwPinCtrl_13_pue = swPinCtrl_13_pue;
assign iofPlusSwPinCtrl_13_ds = swPinCtrl_13_ds;
assign iofPlusSwPinCtrl_14_oval = iofCtrl_14_oval;
assign iofPlusSwPinCtrl_14_oe = iofCtrl_14_oe;
assign iofPlusSwPinCtrl_14_ie = iofCtrl_14_ie;
assign iofPlusSwPinCtrl_14_pue = swPinCtrl_14_pue;
assign iofPlusSwPinCtrl_14_ds = swPinCtrl_14_ds;
assign iofPlusSwPinCtrl_15_oval = iofCtrl_15_oval;
assign iofPlusSwPinCtrl_15_oe = iofCtrl_15_oe;
assign iofPlusSwPinCtrl_15_ie = iofCtrl_15_ie;
assign iofPlusSwPinCtrl_15_pue = swPinCtrl_15_pue;
assign iofPlusSwPinCtrl_15_ds = swPinCtrl_15_ds;
assign iofPlusSwPinCtrl_16_oval = iofCtrl_16_oval;
assign iofPlusSwPinCtrl_16_oe = iofCtrl_16_oe;
assign iofPlusSwPinCtrl_16_ie = iofCtrl_16_ie;
assign iofPlusSwPinCtrl_16_pue = swPinCtrl_16_pue;
assign iofPlusSwPinCtrl_16_ds = swPinCtrl_16_ds;
assign iofPlusSwPinCtrl_17_oval = iofCtrl_17_oval;
assign iofPlusSwPinCtrl_17_oe = iofCtrl_17_oe;
assign iofPlusSwPinCtrl_17_ie = iofCtrl_17_ie;
assign iofPlusSwPinCtrl_17_pue = swPinCtrl_17_pue;
assign iofPlusSwPinCtrl_17_ds = swPinCtrl_17_ds;
assign iofPlusSwPinCtrl_18_oval = iofCtrl_18_oval;
assign iofPlusSwPinCtrl_18_oe = iofCtrl_18_oe;
assign iofPlusSwPinCtrl_18_ie = iofCtrl_18_ie;
assign iofPlusSwPinCtrl_18_pue = swPinCtrl_18_pue;
assign iofPlusSwPinCtrl_18_ds = swPinCtrl_18_ds;
assign iofPlusSwPinCtrl_19_oval = iofCtrl_19_oval;
assign iofPlusSwPinCtrl_19_oe = iofCtrl_19_oe;
assign iofPlusSwPinCtrl_19_ie = iofCtrl_19_ie;
assign iofPlusSwPinCtrl_19_pue = swPinCtrl_19_pue;
assign iofPlusSwPinCtrl_19_ds = swPinCtrl_19_ds;
assign iofPlusSwPinCtrl_20_oval = iofCtrl_20_oval;
assign iofPlusSwPinCtrl_20_oe = iofCtrl_20_oe;
assign iofPlusSwPinCtrl_20_ie = iofCtrl_20_ie;
assign iofPlusSwPinCtrl_20_pue = swPinCtrl_20_pue;
assign iofPlusSwPinCtrl_20_ds = swPinCtrl_20_ds;
assign iofPlusSwPinCtrl_21_oval = iofCtrl_21_oval;
assign iofPlusSwPinCtrl_21_oe = iofCtrl_21_oe;
assign iofPlusSwPinCtrl_21_ie = iofCtrl_21_ie;
assign iofPlusSwPinCtrl_21_pue = swPinCtrl_21_pue;
assign iofPlusSwPinCtrl_21_ds = swPinCtrl_21_ds;
assign iofPlusSwPinCtrl_22_oval = iofCtrl_22_oval;
assign iofPlusSwPinCtrl_22_oe = iofCtrl_22_oe;
assign iofPlusSwPinCtrl_22_ie = iofCtrl_22_ie;
assign iofPlusSwPinCtrl_22_pue = swPinCtrl_22_pue;
assign iofPlusSwPinCtrl_22_ds = swPinCtrl_22_ds;
assign iofPlusSwPinCtrl_23_oval = iofCtrl_23_oval;
assign iofPlusSwPinCtrl_23_oe = iofCtrl_23_oe;
assign iofPlusSwPinCtrl_23_ie = iofCtrl_23_ie;
assign iofPlusSwPinCtrl_23_pue = swPinCtrl_23_pue;
assign iofPlusSwPinCtrl_23_ds = swPinCtrl_23_ds;
assign iofPlusSwPinCtrl_24_oval = iofCtrl_24_oval;
assign iofPlusSwPinCtrl_24_oe = iofCtrl_24_oe;
assign iofPlusSwPinCtrl_24_ie = iofCtrl_24_ie;
assign iofPlusSwPinCtrl_24_pue = swPinCtrl_24_pue;
assign iofPlusSwPinCtrl_24_ds = swPinCtrl_24_ds;
assign iofPlusSwPinCtrl_25_oval = iofCtrl_25_oval;
assign iofPlusSwPinCtrl_25_oe = iofCtrl_25_oe;
assign iofPlusSwPinCtrl_25_ie = iofCtrl_25_ie;
assign iofPlusSwPinCtrl_25_pue = swPinCtrl_25_pue;
assign iofPlusSwPinCtrl_25_ds = swPinCtrl_25_ds;
assign iofPlusSwPinCtrl_26_oval = iofCtrl_26_oval;
assign iofPlusSwPinCtrl_26_oe = iofCtrl_26_oe;
assign iofPlusSwPinCtrl_26_ie = iofCtrl_26_ie;
assign iofPlusSwPinCtrl_26_pue = swPinCtrl_26_pue;
assign iofPlusSwPinCtrl_26_ds = swPinCtrl_26_ds;
assign iofPlusSwPinCtrl_27_oval = iofCtrl_27_oval;
assign iofPlusSwPinCtrl_27_oe = iofCtrl_27_oe;
assign iofPlusSwPinCtrl_27_ie = iofCtrl_27_ie;
assign iofPlusSwPinCtrl_27_pue = swPinCtrl_27_pue;
assign iofPlusSwPinCtrl_27_ds = swPinCtrl_27_ds;
assign iofPlusSwPinCtrl_28_oval = iofCtrl_28_oval;
assign iofPlusSwPinCtrl_28_oe = iofCtrl_28_oe;
assign iofPlusSwPinCtrl_28_ie = iofCtrl_28_ie;
assign iofPlusSwPinCtrl_28_pue = swPinCtrl_28_pue;
assign iofPlusSwPinCtrl_28_ds = swPinCtrl_28_ds;
assign iofPlusSwPinCtrl_29_oval = iofCtrl_29_oval;
assign iofPlusSwPinCtrl_29_oe = iofCtrl_29_oe;
assign iofPlusSwPinCtrl_29_ie = iofCtrl_29_ie;
assign iofPlusSwPinCtrl_29_pue = swPinCtrl_29_pue;
assign iofPlusSwPinCtrl_29_ds = swPinCtrl_29_ds;
assign iofPlusSwPinCtrl_30_oval = iofCtrl_30_oval;
assign iofPlusSwPinCtrl_30_oe = iofCtrl_30_oe;
assign iofPlusSwPinCtrl_30_ie = iofCtrl_30_ie;
assign iofPlusSwPinCtrl_30_pue = swPinCtrl_30_pue;
assign iofPlusSwPinCtrl_30_ds = swPinCtrl_30_ds;
assign iofPlusSwPinCtrl_31_oval = iofCtrl_31_oval;
assign iofPlusSwPinCtrl_31_oe = iofCtrl_31_oe;
assign iofPlusSwPinCtrl_31_ie = iofCtrl_31_ie;
assign iofPlusSwPinCtrl_31_pue = swPinCtrl_31_pue;
assign iofPlusSwPinCtrl_31_ds = swPinCtrl_31_ds;
assign T_7569 = pueReg_io_q[0];
assign T_7570 = portReg[0];
assign T_7571 = oeReg_io_q[0];
assign T_7572 = dsReg[0];
assign T_7573 = ieReg_io_q[0];
assign GEN_201 = io_port_iof_0_0_o_valid ? io_port_iof_0_0_o_oval : swPinCtrl_0_oval;
assign GEN_202 = io_port_iof_0_0_o_valid ? io_port_iof_0_0_o_oe : swPinCtrl_0_oe;
assign GEN_203 = io_port_iof_0_0_o_valid ? io_port_iof_0_0_o_ie : swPinCtrl_0_ie;
assign GEN_204 = io_port_iof_1_0_o_valid ? io_port_iof_1_0_o_oval : swPinCtrl_0_oval;
assign GEN_205 = io_port_iof_1_0_o_valid ? io_port_iof_1_0_o_oe : swPinCtrl_0_oe;
assign GEN_206 = io_port_iof_1_0_o_valid ? io_port_iof_1_0_o_ie : swPinCtrl_0_ie;
assign T_7574 = iofSelReg[0];
assign T_7575_oval = T_7574 ? iof1Ctrl_0_oval : iof0Ctrl_0_oval;
assign T_7575_oe = T_7574 ? iof1Ctrl_0_oe : iof0Ctrl_0_oe;
assign T_7575_ie = T_7574 ? iof1Ctrl_0_ie : iof0Ctrl_0_ie;
assign T_7579 = iofEnReg_io_q[0];
assign T_7580_oval = T_7579 ? iofPlusSwPinCtrl_0_oval : swPinCtrl_0_oval;
assign T_7580_oe = T_7579 ? iofPlusSwPinCtrl_0_oe : swPinCtrl_0_oe;
assign T_7580_ie = T_7579 ? iofPlusSwPinCtrl_0_ie : swPinCtrl_0_ie;
assign T_7580_pue = T_7579 ? iofPlusSwPinCtrl_0_pue : swPinCtrl_0_pue;
assign T_7580_ds = T_7579 ? iofPlusSwPinCtrl_0_ds : swPinCtrl_0_ds;
assign T_7586 = xorReg[0];
assign T_7587 = T_7580_oval ^ T_7586;
assign T_7588 = riseIpReg[0];
assign T_7589 = riseIeReg[0];
assign T_7590 = T_7588 & T_7589;
assign T_7591 = fallIpReg[0];
assign T_7592 = fallIeReg[0];
assign T_7593 = T_7591 & T_7592;
assign T_7594 = T_7590 | T_7593;
assign T_7595 = highIpReg[0];
assign T_7596 = highIeReg[0];
assign T_7597 = T_7595 & T_7596;
assign T_7598 = T_7594 | T_7597;
assign T_7599 = lowIpReg[0];
assign T_7600 = lowIeReg[0];
assign T_7601 = T_7599 & T_7600;
assign T_7602 = T_7598 | T_7601;
assign T_7603 = inSyncReg[0];
assign T_7605 = pueReg_io_q[1];
assign T_7606 = portReg[1];
assign T_7607 = oeReg_io_q[1];
assign T_7608 = dsReg[1];
assign T_7609 = ieReg_io_q[1];
assign GEN_207 = io_port_iof_0_1_o_valid ? io_port_iof_0_1_o_oval : swPinCtrl_1_oval;
assign GEN_208 = io_port_iof_0_1_o_valid ? io_port_iof_0_1_o_oe : swPinCtrl_1_oe;
assign GEN_209 = io_port_iof_0_1_o_valid ? io_port_iof_0_1_o_ie : swPinCtrl_1_ie;
assign GEN_210 = io_port_iof_1_1_o_valid ? io_port_iof_1_1_o_oval : swPinCtrl_1_oval;
assign GEN_211 = io_port_iof_1_1_o_valid ? io_port_iof_1_1_o_oe : swPinCtrl_1_oe;
assign GEN_212 = io_port_iof_1_1_o_valid ? io_port_iof_1_1_o_ie : swPinCtrl_1_ie;
assign T_7610 = iofSelReg[1];
assign T_7611_oval = T_7610 ? iof1Ctrl_1_oval : iof0Ctrl_1_oval;
assign T_7611_oe = T_7610 ? iof1Ctrl_1_oe : iof0Ctrl_1_oe;
assign T_7611_ie = T_7610 ? iof1Ctrl_1_ie : iof0Ctrl_1_ie;
assign T_7615 = iofEnReg_io_q[1];
assign T_7616_oval = T_7615 ? iofPlusSwPinCtrl_1_oval : swPinCtrl_1_oval;
assign T_7616_oe = T_7615 ? iofPlusSwPinCtrl_1_oe : swPinCtrl_1_oe;
assign T_7616_ie = T_7615 ? iofPlusSwPinCtrl_1_ie : swPinCtrl_1_ie;
assign T_7616_pue = T_7615 ? iofPlusSwPinCtrl_1_pue : swPinCtrl_1_pue;
assign T_7616_ds = T_7615 ? iofPlusSwPinCtrl_1_ds : swPinCtrl_1_ds;
assign T_7622 = xorReg[1];
assign T_7623 = T_7616_oval ^ T_7622;
assign T_7624 = riseIpReg[1];
assign T_7625 = riseIeReg[1];
assign T_7626 = T_7624 & T_7625;
assign T_7627 = fallIpReg[1];
assign T_7628 = fallIeReg[1];
assign T_7629 = T_7627 & T_7628;
assign T_7630 = T_7626 | T_7629;
assign T_7631 = highIpReg[1];
assign T_7632 = highIeReg[1];
assign T_7633 = T_7631 & T_7632;
assign T_7634 = T_7630 | T_7633;
assign T_7635 = lowIpReg[1];
assign T_7636 = lowIeReg[1];
assign T_7637 = T_7635 & T_7636;
assign T_7638 = T_7634 | T_7637;
assign T_7639 = inSyncReg[1];
assign T_7641 = pueReg_io_q[2];
assign T_7642 = portReg[2];
assign T_7643 = oeReg_io_q[2];
assign T_7644 = dsReg[2];
assign T_7645 = ieReg_io_q[2];
assign GEN_213 = io_port_iof_0_2_o_valid ? io_port_iof_0_2_o_oval : swPinCtrl_2_oval;
assign GEN_214 = io_port_iof_0_2_o_valid ? io_port_iof_0_2_o_oe : swPinCtrl_2_oe;
assign GEN_215 = io_port_iof_0_2_o_valid ? io_port_iof_0_2_o_ie : swPinCtrl_2_ie;
assign GEN_216 = io_port_iof_1_2_o_valid ? io_port_iof_1_2_o_oval : swPinCtrl_2_oval;
assign GEN_217 = io_port_iof_1_2_o_valid ? io_port_iof_1_2_o_oe : swPinCtrl_2_oe;
assign GEN_218 = io_port_iof_1_2_o_valid ? io_port_iof_1_2_o_ie : swPinCtrl_2_ie;
assign T_7646 = iofSelReg[2];
assign T_7647_oval = T_7646 ? iof1Ctrl_2_oval : iof0Ctrl_2_oval;
assign T_7647_oe = T_7646 ? iof1Ctrl_2_oe : iof0Ctrl_2_oe;
assign T_7647_ie = T_7646 ? iof1Ctrl_2_ie : iof0Ctrl_2_ie;
assign T_7651 = iofEnReg_io_q[2];
assign T_7652_oval = T_7651 ? iofPlusSwPinCtrl_2_oval : swPinCtrl_2_oval;
assign T_7652_oe = T_7651 ? iofPlusSwPinCtrl_2_oe : swPinCtrl_2_oe;
assign T_7652_ie = T_7651 ? iofPlusSwPinCtrl_2_ie : swPinCtrl_2_ie;
assign T_7652_pue = T_7651 ? iofPlusSwPinCtrl_2_pue : swPinCtrl_2_pue;
assign T_7652_ds = T_7651 ? iofPlusSwPinCtrl_2_ds : swPinCtrl_2_ds;
assign T_7658 = xorReg[2];
assign T_7659 = T_7652_oval ^ T_7658;
assign T_7660 = riseIpReg[2];
assign T_7661 = riseIeReg[2];
assign T_7662 = T_7660 & T_7661;
assign T_7663 = fallIpReg[2];
assign T_7664 = fallIeReg[2];
assign T_7665 = T_7663 & T_7664;
assign T_7666 = T_7662 | T_7665;
assign T_7667 = highIpReg[2];
assign T_7668 = highIeReg[2];
assign T_7669 = T_7667 & T_7668;
assign T_7670 = T_7666 | T_7669;
assign T_7671 = lowIpReg[2];
assign T_7672 = lowIeReg[2];
assign T_7673 = T_7671 & T_7672;
assign T_7674 = T_7670 | T_7673;
assign T_7675 = inSyncReg[2];
assign T_7677 = pueReg_io_q[3];
assign T_7678 = portReg[3];
assign T_7679 = oeReg_io_q[3];
assign T_7680 = dsReg[3];
assign T_7681 = ieReg_io_q[3];
assign GEN_219 = io_port_iof_0_3_o_valid ? io_port_iof_0_3_o_oval : swPinCtrl_3_oval;
assign GEN_220 = io_port_iof_0_3_o_valid ? io_port_iof_0_3_o_oe : swPinCtrl_3_oe;
assign GEN_221 = io_port_iof_0_3_o_valid ? io_port_iof_0_3_o_ie : swPinCtrl_3_ie;
assign GEN_222 = io_port_iof_1_3_o_valid ? io_port_iof_1_3_o_oval : swPinCtrl_3_oval;
assign GEN_223 = io_port_iof_1_3_o_valid ? io_port_iof_1_3_o_oe : swPinCtrl_3_oe;
assign GEN_224 = io_port_iof_1_3_o_valid ? io_port_iof_1_3_o_ie : swPinCtrl_3_ie;
assign T_7682 = iofSelReg[3];
assign T_7683_oval = T_7682 ? iof1Ctrl_3_oval : iof0Ctrl_3_oval;
assign T_7683_oe = T_7682 ? iof1Ctrl_3_oe : iof0Ctrl_3_oe;
assign T_7683_ie = T_7682 ? iof1Ctrl_3_ie : iof0Ctrl_3_ie;
assign T_7687 = iofEnReg_io_q[3];
assign T_7688_oval = T_7687 ? iofPlusSwPinCtrl_3_oval : swPinCtrl_3_oval;
assign T_7688_oe = T_7687 ? iofPlusSwPinCtrl_3_oe : swPinCtrl_3_oe;
assign T_7688_ie = T_7687 ? iofPlusSwPinCtrl_3_ie : swPinCtrl_3_ie;
assign T_7688_pue = T_7687 ? iofPlusSwPinCtrl_3_pue : swPinCtrl_3_pue;
assign T_7688_ds = T_7687 ? iofPlusSwPinCtrl_3_ds : swPinCtrl_3_ds;
assign T_7694 = xorReg[3];
assign T_7695 = T_7688_oval ^ T_7694;
assign T_7696 = riseIpReg[3];
assign T_7697 = riseIeReg[3];
assign T_7698 = T_7696 & T_7697;
assign T_7699 = fallIpReg[3];
assign T_7700 = fallIeReg[3];
assign T_7701 = T_7699 & T_7700;
assign T_7702 = T_7698 | T_7701;
assign T_7703 = highIpReg[3];
assign T_7704 = highIeReg[3];
assign T_7705 = T_7703 & T_7704;
assign T_7706 = T_7702 | T_7705;
assign T_7707 = lowIpReg[3];
assign T_7708 = lowIeReg[3];
assign T_7709 = T_7707 & T_7708;
assign T_7710 = T_7706 | T_7709;
assign T_7711 = inSyncReg[3];
assign T_7713 = pueReg_io_q[4];
assign T_7714 = portReg[4];
assign T_7715 = oeReg_io_q[4];
assign T_7716 = dsReg[4];
assign T_7717 = ieReg_io_q[4];
assign GEN_225 = io_port_iof_0_4_o_valid ? io_port_iof_0_4_o_oval : swPinCtrl_4_oval;
assign GEN_226 = io_port_iof_0_4_o_valid ? io_port_iof_0_4_o_oe : swPinCtrl_4_oe;
assign GEN_227 = io_port_iof_0_4_o_valid ? io_port_iof_0_4_o_ie : swPinCtrl_4_ie;
assign GEN_228 = io_port_iof_1_4_o_valid ? io_port_iof_1_4_o_oval : swPinCtrl_4_oval;
assign GEN_229 = io_port_iof_1_4_o_valid ? io_port_iof_1_4_o_oe : swPinCtrl_4_oe;
assign GEN_230 = io_port_iof_1_4_o_valid ? io_port_iof_1_4_o_ie : swPinCtrl_4_ie;
assign T_7718 = iofSelReg[4];
assign T_7719_oval = T_7718 ? iof1Ctrl_4_oval : iof0Ctrl_4_oval;
assign T_7719_oe = T_7718 ? iof1Ctrl_4_oe : iof0Ctrl_4_oe;
assign T_7719_ie = T_7718 ? iof1Ctrl_4_ie : iof0Ctrl_4_ie;
assign T_7723 = iofEnReg_io_q[4];
assign T_7724_oval = T_7723 ? iofPlusSwPinCtrl_4_oval : swPinCtrl_4_oval;
assign T_7724_oe = T_7723 ? iofPlusSwPinCtrl_4_oe : swPinCtrl_4_oe;
assign T_7724_ie = T_7723 ? iofPlusSwPinCtrl_4_ie : swPinCtrl_4_ie;
assign T_7724_pue = T_7723 ? iofPlusSwPinCtrl_4_pue : swPinCtrl_4_pue;
assign T_7724_ds = T_7723 ? iofPlusSwPinCtrl_4_ds : swPinCtrl_4_ds;
assign T_7730 = xorReg[4];
assign T_7731 = T_7724_oval ^ T_7730;
assign T_7732 = riseIpReg[4];
assign T_7733 = riseIeReg[4];
assign T_7734 = T_7732 & T_7733;
assign T_7735 = fallIpReg[4];
assign T_7736 = fallIeReg[4];
assign T_7737 = T_7735 & T_7736;
assign T_7738 = T_7734 | T_7737;
assign T_7739 = highIpReg[4];
assign T_7740 = highIeReg[4];
assign T_7741 = T_7739 & T_7740;
assign T_7742 = T_7738 | T_7741;
assign T_7743 = lowIpReg[4];
assign T_7744 = lowIeReg[4];
assign T_7745 = T_7743 & T_7744;
assign T_7746 = T_7742 | T_7745;
assign T_7747 = inSyncReg[4];
assign T_7749 = pueReg_io_q[5];
assign T_7750 = portReg[5];
assign T_7751 = oeReg_io_q[5];
assign T_7752 = dsReg[5];
assign T_7753 = ieReg_io_q[5];
assign GEN_231 = io_port_iof_0_5_o_valid ? io_port_iof_0_5_o_oval : swPinCtrl_5_oval;
assign GEN_232 = io_port_iof_0_5_o_valid ? io_port_iof_0_5_o_oe : swPinCtrl_5_oe;
assign GEN_233 = io_port_iof_0_5_o_valid ? io_port_iof_0_5_o_ie : swPinCtrl_5_ie;
assign GEN_234 = io_port_iof_1_5_o_valid ? io_port_iof_1_5_o_oval : swPinCtrl_5_oval;
assign GEN_235 = io_port_iof_1_5_o_valid ? io_port_iof_1_5_o_oe : swPinCtrl_5_oe;
assign GEN_236 = io_port_iof_1_5_o_valid ? io_port_iof_1_5_o_ie : swPinCtrl_5_ie;
assign T_7754 = iofSelReg[5];
assign T_7755_oval = T_7754 ? iof1Ctrl_5_oval : iof0Ctrl_5_oval;
assign T_7755_oe = T_7754 ? iof1Ctrl_5_oe : iof0Ctrl_5_oe;
assign T_7755_ie = T_7754 ? iof1Ctrl_5_ie : iof0Ctrl_5_ie;
assign T_7759 = iofEnReg_io_q[5];
assign T_7760_oval = T_7759 ? iofPlusSwPinCtrl_5_oval : swPinCtrl_5_oval;
assign T_7760_oe = T_7759 ? iofPlusSwPinCtrl_5_oe : swPinCtrl_5_oe;
assign T_7760_ie = T_7759 ? iofPlusSwPinCtrl_5_ie : swPinCtrl_5_ie;
assign T_7760_pue = T_7759 ? iofPlusSwPinCtrl_5_pue : swPinCtrl_5_pue;
assign T_7760_ds = T_7759 ? iofPlusSwPinCtrl_5_ds : swPinCtrl_5_ds;
assign T_7766 = xorReg[5];
assign T_7767 = T_7760_oval ^ T_7766;
assign T_7768 = riseIpReg[5];
assign T_7769 = riseIeReg[5];
assign T_7770 = T_7768 & T_7769;
assign T_7771 = fallIpReg[5];
assign T_7772 = fallIeReg[5];
assign T_7773 = T_7771 & T_7772;
assign T_7774 = T_7770 | T_7773;
assign T_7775 = highIpReg[5];
assign T_7776 = highIeReg[5];
assign T_7777 = T_7775 & T_7776;
assign T_7778 = T_7774 | T_7777;
assign T_7779 = lowIpReg[5];
assign T_7780 = lowIeReg[5];
assign T_7781 = T_7779 & T_7780;
assign T_7782 = T_7778 | T_7781;
assign T_7783 = inSyncReg[5];
assign T_7785 = pueReg_io_q[6];
assign T_7786 = portReg[6];
assign T_7787 = oeReg_io_q[6];
assign T_7788 = dsReg[6];
assign T_7789 = ieReg_io_q[6];
assign GEN_237 = io_port_iof_0_6_o_valid ? io_port_iof_0_6_o_oval : swPinCtrl_6_oval;
assign GEN_238 = io_port_iof_0_6_o_valid ? io_port_iof_0_6_o_oe : swPinCtrl_6_oe;
assign GEN_239 = io_port_iof_0_6_o_valid ? io_port_iof_0_6_o_ie : swPinCtrl_6_ie;
assign GEN_240 = io_port_iof_1_6_o_valid ? io_port_iof_1_6_o_oval : swPinCtrl_6_oval;
assign GEN_241 = io_port_iof_1_6_o_valid ? io_port_iof_1_6_o_oe : swPinCtrl_6_oe;
assign GEN_242 = io_port_iof_1_6_o_valid ? io_port_iof_1_6_o_ie : swPinCtrl_6_ie;
assign T_7790 = iofSelReg[6];
assign T_7791_oval = T_7790 ? iof1Ctrl_6_oval : iof0Ctrl_6_oval;
assign T_7791_oe = T_7790 ? iof1Ctrl_6_oe : iof0Ctrl_6_oe;
assign T_7791_ie = T_7790 ? iof1Ctrl_6_ie : iof0Ctrl_6_ie;
assign T_7795 = iofEnReg_io_q[6];
assign T_7796_oval = T_7795 ? iofPlusSwPinCtrl_6_oval : swPinCtrl_6_oval;
assign T_7796_oe = T_7795 ? iofPlusSwPinCtrl_6_oe : swPinCtrl_6_oe;
assign T_7796_ie = T_7795 ? iofPlusSwPinCtrl_6_ie : swPinCtrl_6_ie;
assign T_7796_pue = T_7795 ? iofPlusSwPinCtrl_6_pue : swPinCtrl_6_pue;
assign T_7796_ds = T_7795 ? iofPlusSwPinCtrl_6_ds : swPinCtrl_6_ds;
assign T_7802 = xorReg[6];
assign T_7803 = T_7796_oval ^ T_7802;
assign T_7804 = riseIpReg[6];
assign T_7805 = riseIeReg[6];
assign T_7806 = T_7804 & T_7805;
assign T_7807 = fallIpReg[6];
assign T_7808 = fallIeReg[6];
assign T_7809 = T_7807 & T_7808;
assign T_7810 = T_7806 | T_7809;
assign T_7811 = highIpReg[6];
assign T_7812 = highIeReg[6];
assign T_7813 = T_7811 & T_7812;
assign T_7814 = T_7810 | T_7813;
assign T_7815 = lowIpReg[6];
assign T_7816 = lowIeReg[6];
assign T_7817 = T_7815 & T_7816;
assign T_7818 = T_7814 | T_7817;
assign T_7819 = inSyncReg[6];
assign T_7821 = pueReg_io_q[7];
assign T_7822 = portReg[7];
assign T_7823 = oeReg_io_q[7];
assign T_7824 = dsReg[7];
assign T_7825 = ieReg_io_q[7];
assign GEN_243 = io_port_iof_0_7_o_valid ? io_port_iof_0_7_o_oval : swPinCtrl_7_oval;
assign GEN_244 = io_port_iof_0_7_o_valid ? io_port_iof_0_7_o_oe : swPinCtrl_7_oe;
assign GEN_245 = io_port_iof_0_7_o_valid ? io_port_iof_0_7_o_ie : swPinCtrl_7_ie;
assign GEN_246 = io_port_iof_1_7_o_valid ? io_port_iof_1_7_o_oval : swPinCtrl_7_oval;
assign GEN_247 = io_port_iof_1_7_o_valid ? io_port_iof_1_7_o_oe : swPinCtrl_7_oe;
assign GEN_248 = io_port_iof_1_7_o_valid ? io_port_iof_1_7_o_ie : swPinCtrl_7_ie;
assign T_7826 = iofSelReg[7];
assign T_7827_oval = T_7826 ? iof1Ctrl_7_oval : iof0Ctrl_7_oval;
assign T_7827_oe = T_7826 ? iof1Ctrl_7_oe : iof0Ctrl_7_oe;
assign T_7827_ie = T_7826 ? iof1Ctrl_7_ie : iof0Ctrl_7_ie;
assign T_7831 = iofEnReg_io_q[7];
assign T_7832_oval = T_7831 ? iofPlusSwPinCtrl_7_oval : swPinCtrl_7_oval;
assign T_7832_oe = T_7831 ? iofPlusSwPinCtrl_7_oe : swPinCtrl_7_oe;
assign T_7832_ie = T_7831 ? iofPlusSwPinCtrl_7_ie : swPinCtrl_7_ie;
assign T_7832_pue = T_7831 ? iofPlusSwPinCtrl_7_pue : swPinCtrl_7_pue;
assign T_7832_ds = T_7831 ? iofPlusSwPinCtrl_7_ds : swPinCtrl_7_ds;
assign T_7838 = xorReg[7];
assign T_7839 = T_7832_oval ^ T_7838;
assign T_7840 = riseIpReg[7];
assign T_7841 = riseIeReg[7];
assign T_7842 = T_7840 & T_7841;
assign T_7843 = fallIpReg[7];
assign T_7844 = fallIeReg[7];
assign T_7845 = T_7843 & T_7844;
assign T_7846 = T_7842 | T_7845;
assign T_7847 = highIpReg[7];
assign T_7848 = highIeReg[7];
assign T_7849 = T_7847 & T_7848;
assign T_7850 = T_7846 | T_7849;
assign T_7851 = lowIpReg[7];
assign T_7852 = lowIeReg[7];
assign T_7853 = T_7851 & T_7852;
assign T_7854 = T_7850 | T_7853;
assign T_7855 = inSyncReg[7];
assign T_7857 = pueReg_io_q[8];
assign T_7858 = portReg[8];
assign T_7859 = oeReg_io_q[8];
assign T_7860 = dsReg[8];
assign T_7861 = ieReg_io_q[8];
assign GEN_249 = io_port_iof_0_8_o_valid ? io_port_iof_0_8_o_oval : swPinCtrl_8_oval;
assign GEN_250 = io_port_iof_0_8_o_valid ? io_port_iof_0_8_o_oe : swPinCtrl_8_oe;
assign GEN_251 = io_port_iof_0_8_o_valid ? io_port_iof_0_8_o_ie : swPinCtrl_8_ie;
assign GEN_252 = io_port_iof_1_8_o_valid ? io_port_iof_1_8_o_oval : swPinCtrl_8_oval;
assign GEN_253 = io_port_iof_1_8_o_valid ? io_port_iof_1_8_o_oe : swPinCtrl_8_oe;
assign GEN_254 = io_port_iof_1_8_o_valid ? io_port_iof_1_8_o_ie : swPinCtrl_8_ie;
assign T_7862 = iofSelReg[8];
assign T_7863_oval = T_7862 ? iof1Ctrl_8_oval : iof0Ctrl_8_oval;
assign T_7863_oe = T_7862 ? iof1Ctrl_8_oe : iof0Ctrl_8_oe;
assign T_7863_ie = T_7862 ? iof1Ctrl_8_ie : iof0Ctrl_8_ie;
assign T_7867 = iofEnReg_io_q[8];
assign T_7868_oval = T_7867 ? iofPlusSwPinCtrl_8_oval : swPinCtrl_8_oval;
assign T_7868_oe = T_7867 ? iofPlusSwPinCtrl_8_oe : swPinCtrl_8_oe;
assign T_7868_ie = T_7867 ? iofPlusSwPinCtrl_8_ie : swPinCtrl_8_ie;
assign T_7868_pue = T_7867 ? iofPlusSwPinCtrl_8_pue : swPinCtrl_8_pue;
assign T_7868_ds = T_7867 ? iofPlusSwPinCtrl_8_ds : swPinCtrl_8_ds;
assign T_7874 = xorReg[8];
assign T_7875 = T_7868_oval ^ T_7874;
assign T_7876 = riseIpReg[8];
assign T_7877 = riseIeReg[8];
assign T_7878 = T_7876 & T_7877;
assign T_7879 = fallIpReg[8];
assign T_7880 = fallIeReg[8];
assign T_7881 = T_7879 & T_7880;
assign T_7882 = T_7878 | T_7881;
assign T_7883 = highIpReg[8];
assign T_7884 = highIeReg[8];
assign T_7885 = T_7883 & T_7884;
assign T_7886 = T_7882 | T_7885;
assign T_7887 = lowIpReg[8];
assign T_7888 = lowIeReg[8];
assign T_7889 = T_7887 & T_7888;
assign T_7890 = T_7886 | T_7889;
assign T_7891 = inSyncReg[8];
assign T_7893 = pueReg_io_q[9];
assign T_7894 = portReg[9];
assign T_7895 = oeReg_io_q[9];
assign T_7896 = dsReg[9];
assign T_7897 = ieReg_io_q[9];
assign GEN_255 = io_port_iof_0_9_o_valid ? io_port_iof_0_9_o_oval : swPinCtrl_9_oval;
assign GEN_256 = io_port_iof_0_9_o_valid ? io_port_iof_0_9_o_oe : swPinCtrl_9_oe;
assign GEN_257 = io_port_iof_0_9_o_valid ? io_port_iof_0_9_o_ie : swPinCtrl_9_ie;
assign GEN_258 = io_port_iof_1_9_o_valid ? io_port_iof_1_9_o_oval : swPinCtrl_9_oval;
assign GEN_259 = io_port_iof_1_9_o_valid ? io_port_iof_1_9_o_oe : swPinCtrl_9_oe;
assign GEN_260 = io_port_iof_1_9_o_valid ? io_port_iof_1_9_o_ie : swPinCtrl_9_ie;
assign T_7898 = iofSelReg[9];
assign T_7899_oval = T_7898 ? iof1Ctrl_9_oval : iof0Ctrl_9_oval;
assign T_7899_oe = T_7898 ? iof1Ctrl_9_oe : iof0Ctrl_9_oe;
assign T_7899_ie = T_7898 ? iof1Ctrl_9_ie : iof0Ctrl_9_ie;
assign T_7903 = iofEnReg_io_q[9];
assign T_7904_oval = T_7903 ? iofPlusSwPinCtrl_9_oval : swPinCtrl_9_oval;
assign T_7904_oe = T_7903 ? iofPlusSwPinCtrl_9_oe : swPinCtrl_9_oe;
assign T_7904_ie = T_7903 ? iofPlusSwPinCtrl_9_ie : swPinCtrl_9_ie;
assign T_7904_pue = T_7903 ? iofPlusSwPinCtrl_9_pue : swPinCtrl_9_pue;
assign T_7904_ds = T_7903 ? iofPlusSwPinCtrl_9_ds : swPinCtrl_9_ds;
assign T_7910 = xorReg[9];
assign T_7911 = T_7904_oval ^ T_7910;
assign T_7912 = riseIpReg[9];
assign T_7913 = riseIeReg[9];
assign T_7914 = T_7912 & T_7913;
assign T_7915 = fallIpReg[9];
assign T_7916 = fallIeReg[9];
assign T_7917 = T_7915 & T_7916;
assign T_7918 = T_7914 | T_7917;
assign T_7919 = highIpReg[9];
assign T_7920 = highIeReg[9];
assign T_7921 = T_7919 & T_7920;
assign T_7922 = T_7918 | T_7921;
assign T_7923 = lowIpReg[9];
assign T_7924 = lowIeReg[9];
assign T_7925 = T_7923 & T_7924;
assign T_7926 = T_7922 | T_7925;
assign T_7927 = inSyncReg[9];
assign T_7929 = pueReg_io_q[10];
assign T_7930 = portReg[10];
assign T_7931 = oeReg_io_q[10];
assign T_7932 = dsReg[10];
assign T_7933 = ieReg_io_q[10];
assign GEN_261 = io_port_iof_0_10_o_valid ? io_port_iof_0_10_o_oval : swPinCtrl_10_oval;
assign GEN_262 = io_port_iof_0_10_o_valid ? io_port_iof_0_10_o_oe : swPinCtrl_10_oe;
assign GEN_263 = io_port_iof_0_10_o_valid ? io_port_iof_0_10_o_ie : swPinCtrl_10_ie;
assign GEN_264 = io_port_iof_1_10_o_valid ? io_port_iof_1_10_o_oval : swPinCtrl_10_oval;
assign GEN_265 = io_port_iof_1_10_o_valid ? io_port_iof_1_10_o_oe : swPinCtrl_10_oe;
assign GEN_266 = io_port_iof_1_10_o_valid ? io_port_iof_1_10_o_ie : swPinCtrl_10_ie;
assign T_7934 = iofSelReg[10];
assign T_7935_oval = T_7934 ? iof1Ctrl_10_oval : iof0Ctrl_10_oval;
assign T_7935_oe = T_7934 ? iof1Ctrl_10_oe : iof0Ctrl_10_oe;
assign T_7935_ie = T_7934 ? iof1Ctrl_10_ie : iof0Ctrl_10_ie;
assign T_7939 = iofEnReg_io_q[10];
assign T_7940_oval = T_7939 ? iofPlusSwPinCtrl_10_oval : swPinCtrl_10_oval;
assign T_7940_oe = T_7939 ? iofPlusSwPinCtrl_10_oe : swPinCtrl_10_oe;
assign T_7940_ie = T_7939 ? iofPlusSwPinCtrl_10_ie : swPinCtrl_10_ie;
assign T_7940_pue = T_7939 ? iofPlusSwPinCtrl_10_pue : swPinCtrl_10_pue;
assign T_7940_ds = T_7939 ? iofPlusSwPinCtrl_10_ds : swPinCtrl_10_ds;
assign T_7946 = xorReg[10];
assign T_7947 = T_7940_oval ^ T_7946;
assign T_7948 = riseIpReg[10];
assign T_7949 = riseIeReg[10];
assign T_7950 = T_7948 & T_7949;
assign T_7951 = fallIpReg[10];
assign T_7952 = fallIeReg[10];
assign T_7953 = T_7951 & T_7952;
assign T_7954 = T_7950 | T_7953;
assign T_7955 = highIpReg[10];
assign T_7956 = highIeReg[10];
assign T_7957 = T_7955 & T_7956;
assign T_7958 = T_7954 | T_7957;
assign T_7959 = lowIpReg[10];
assign T_7960 = lowIeReg[10];
assign T_7961 = T_7959 & T_7960;
assign T_7962 = T_7958 | T_7961;
assign T_7963 = inSyncReg[10];
assign T_7965 = pueReg_io_q[11];
assign T_7966 = portReg[11];
assign T_7967 = oeReg_io_q[11];
assign T_7968 = dsReg[11];
assign T_7969 = ieReg_io_q[11];
assign GEN_267 = io_port_iof_0_11_o_valid ? io_port_iof_0_11_o_oval : swPinCtrl_11_oval;
assign GEN_268 = io_port_iof_0_11_o_valid ? io_port_iof_0_11_o_oe : swPinCtrl_11_oe;
assign GEN_269 = io_port_iof_0_11_o_valid ? io_port_iof_0_11_o_ie : swPinCtrl_11_ie;
assign GEN_270 = io_port_iof_1_11_o_valid ? io_port_iof_1_11_o_oval : swPinCtrl_11_oval;
assign GEN_271 = io_port_iof_1_11_o_valid ? io_port_iof_1_11_o_oe : swPinCtrl_11_oe;
assign GEN_272 = io_port_iof_1_11_o_valid ? io_port_iof_1_11_o_ie : swPinCtrl_11_ie;
assign T_7970 = iofSelReg[11];
assign T_7971_oval = T_7970 ? iof1Ctrl_11_oval : iof0Ctrl_11_oval;
assign T_7971_oe = T_7970 ? iof1Ctrl_11_oe : iof0Ctrl_11_oe;
assign T_7971_ie = T_7970 ? iof1Ctrl_11_ie : iof0Ctrl_11_ie;
assign T_7975 = iofEnReg_io_q[11];
assign T_7976_oval = T_7975 ? iofPlusSwPinCtrl_11_oval : swPinCtrl_11_oval;
assign T_7976_oe = T_7975 ? iofPlusSwPinCtrl_11_oe : swPinCtrl_11_oe;
assign T_7976_ie = T_7975 ? iofPlusSwPinCtrl_11_ie : swPinCtrl_11_ie;
assign T_7976_pue = T_7975 ? iofPlusSwPinCtrl_11_pue : swPinCtrl_11_pue;
assign T_7976_ds = T_7975 ? iofPlusSwPinCtrl_11_ds : swPinCtrl_11_ds;
assign T_7982 = xorReg[11];
assign T_7983 = T_7976_oval ^ T_7982;
assign T_7984 = riseIpReg[11];
assign T_7985 = riseIeReg[11];
assign T_7986 = T_7984 & T_7985;
assign T_7987 = fallIpReg[11];
assign T_7988 = fallIeReg[11];
assign T_7989 = T_7987 & T_7988;
assign T_7990 = T_7986 | T_7989;
assign T_7991 = highIpReg[11];
assign T_7992 = highIeReg[11];
assign T_7993 = T_7991 & T_7992;
assign T_7994 = T_7990 | T_7993;
assign T_7995 = lowIpReg[11];
assign T_7996 = lowIeReg[11];
assign T_7997 = T_7995 & T_7996;
assign T_7998 = T_7994 | T_7997;
assign T_7999 = inSyncReg[11];
assign T_8001 = pueReg_io_q[12];
assign T_8002 = portReg[12];
assign T_8003 = oeReg_io_q[12];
assign T_8004 = dsReg[12];
assign T_8005 = ieReg_io_q[12];
assign GEN_273 = io_port_iof_0_12_o_valid ? io_port_iof_0_12_o_oval : swPinCtrl_12_oval;
assign GEN_274 = io_port_iof_0_12_o_valid ? io_port_iof_0_12_o_oe : swPinCtrl_12_oe;
assign GEN_275 = io_port_iof_0_12_o_valid ? io_port_iof_0_12_o_ie : swPinCtrl_12_ie;
assign GEN_276 = io_port_iof_1_12_o_valid ? io_port_iof_1_12_o_oval : swPinCtrl_12_oval;
assign GEN_277 = io_port_iof_1_12_o_valid ? io_port_iof_1_12_o_oe : swPinCtrl_12_oe;
assign GEN_278 = io_port_iof_1_12_o_valid ? io_port_iof_1_12_o_ie : swPinCtrl_12_ie;
assign T_8006 = iofSelReg[12];
assign T_8007_oval = T_8006 ? iof1Ctrl_12_oval : iof0Ctrl_12_oval;
assign T_8007_oe = T_8006 ? iof1Ctrl_12_oe : iof0Ctrl_12_oe;
assign T_8007_ie = T_8006 ? iof1Ctrl_12_ie : iof0Ctrl_12_ie;
assign T_8011 = iofEnReg_io_q[12];
assign T_8012_oval = T_8011 ? iofPlusSwPinCtrl_12_oval : swPinCtrl_12_oval;
assign T_8012_oe = T_8011 ? iofPlusSwPinCtrl_12_oe : swPinCtrl_12_oe;
assign T_8012_ie = T_8011 ? iofPlusSwPinCtrl_12_ie : swPinCtrl_12_ie;
assign T_8012_pue = T_8011 ? iofPlusSwPinCtrl_12_pue : swPinCtrl_12_pue;
assign T_8012_ds = T_8011 ? iofPlusSwPinCtrl_12_ds : swPinCtrl_12_ds;
assign T_8018 = xorReg[12];
assign T_8019 = T_8012_oval ^ T_8018;
assign T_8020 = riseIpReg[12];
assign T_8021 = riseIeReg[12];
assign T_8022 = T_8020 & T_8021;
assign T_8023 = fallIpReg[12];
assign T_8024 = fallIeReg[12];
assign T_8025 = T_8023 & T_8024;
assign T_8026 = T_8022 | T_8025;
assign T_8027 = highIpReg[12];
assign T_8028 = highIeReg[12];
assign T_8029 = T_8027 & T_8028;
assign T_8030 = T_8026 | T_8029;
assign T_8031 = lowIpReg[12];
assign T_8032 = lowIeReg[12];
assign T_8033 = T_8031 & T_8032;
assign T_8034 = T_8030 | T_8033;
assign T_8035 = inSyncReg[12];
assign T_8037 = pueReg_io_q[13];
assign T_8038 = portReg[13];
assign T_8039 = oeReg_io_q[13];
assign T_8040 = dsReg[13];
assign T_8041 = ieReg_io_q[13];
assign GEN_279 = io_port_iof_0_13_o_valid ? io_port_iof_0_13_o_oval : swPinCtrl_13_oval;
assign GEN_280 = io_port_iof_0_13_o_valid ? io_port_iof_0_13_o_oe : swPinCtrl_13_oe;
assign GEN_281 = io_port_iof_0_13_o_valid ? io_port_iof_0_13_o_ie : swPinCtrl_13_ie;
assign GEN_282 = io_port_iof_1_13_o_valid ? io_port_iof_1_13_o_oval : swPinCtrl_13_oval;
assign GEN_283 = io_port_iof_1_13_o_valid ? io_port_iof_1_13_o_oe : swPinCtrl_13_oe;
assign GEN_284 = io_port_iof_1_13_o_valid ? io_port_iof_1_13_o_ie : swPinCtrl_13_ie;
assign T_8042 = iofSelReg[13];
assign T_8043_oval = T_8042 ? iof1Ctrl_13_oval : iof0Ctrl_13_oval;
assign T_8043_oe = T_8042 ? iof1Ctrl_13_oe : iof0Ctrl_13_oe;
assign T_8043_ie = T_8042 ? iof1Ctrl_13_ie : iof0Ctrl_13_ie;
assign T_8047 = iofEnReg_io_q[13];
assign T_8048_oval = T_8047 ? iofPlusSwPinCtrl_13_oval : swPinCtrl_13_oval;
assign T_8048_oe = T_8047 ? iofPlusSwPinCtrl_13_oe : swPinCtrl_13_oe;
assign T_8048_ie = T_8047 ? iofPlusSwPinCtrl_13_ie : swPinCtrl_13_ie;
assign T_8048_pue = T_8047 ? iofPlusSwPinCtrl_13_pue : swPinCtrl_13_pue;
assign T_8048_ds = T_8047 ? iofPlusSwPinCtrl_13_ds : swPinCtrl_13_ds;
assign T_8054 = xorReg[13];
assign T_8055 = T_8048_oval ^ T_8054;
assign T_8056 = riseIpReg[13];
assign T_8057 = riseIeReg[13];
assign T_8058 = T_8056 & T_8057;
assign T_8059 = fallIpReg[13];
assign T_8060 = fallIeReg[13];
assign T_8061 = T_8059 & T_8060;
assign T_8062 = T_8058 | T_8061;
assign T_8063 = highIpReg[13];
assign T_8064 = highIeReg[13];
assign T_8065 = T_8063 & T_8064;
assign T_8066 = T_8062 | T_8065;
assign T_8067 = lowIpReg[13];
assign T_8068 = lowIeReg[13];
assign T_8069 = T_8067 & T_8068;
assign T_8070 = T_8066 | T_8069;
assign T_8071 = inSyncReg[13];
assign T_8073 = pueReg_io_q[14];
assign T_8074 = portReg[14];
assign T_8075 = oeReg_io_q[14];
assign T_8076 = dsReg[14];
assign T_8077 = ieReg_io_q[14];
assign GEN_285 = io_port_iof_0_14_o_valid ? io_port_iof_0_14_o_oval : swPinCtrl_14_oval;
assign GEN_286 = io_port_iof_0_14_o_valid ? io_port_iof_0_14_o_oe : swPinCtrl_14_oe;
assign GEN_287 = io_port_iof_0_14_o_valid ? io_port_iof_0_14_o_ie : swPinCtrl_14_ie;
assign GEN_288 = io_port_iof_1_14_o_valid ? io_port_iof_1_14_o_oval : swPinCtrl_14_oval;
assign GEN_289 = io_port_iof_1_14_o_valid ? io_port_iof_1_14_o_oe : swPinCtrl_14_oe;
assign GEN_290 = io_port_iof_1_14_o_valid ? io_port_iof_1_14_o_ie : swPinCtrl_14_ie;
assign T_8078 = iofSelReg[14];
assign T_8079_oval = T_8078 ? iof1Ctrl_14_oval : iof0Ctrl_14_oval;
assign T_8079_oe = T_8078 ? iof1Ctrl_14_oe : iof0Ctrl_14_oe;
assign T_8079_ie = T_8078 ? iof1Ctrl_14_ie : iof0Ctrl_14_ie;
assign T_8083 = iofEnReg_io_q[14];
assign T_8084_oval = T_8083 ? iofPlusSwPinCtrl_14_oval : swPinCtrl_14_oval;
assign T_8084_oe = T_8083 ? iofPlusSwPinCtrl_14_oe : swPinCtrl_14_oe;
assign T_8084_ie = T_8083 ? iofPlusSwPinCtrl_14_ie : swPinCtrl_14_ie;
assign T_8084_pue = T_8083 ? iofPlusSwPinCtrl_14_pue : swPinCtrl_14_pue;
assign T_8084_ds = T_8083 ? iofPlusSwPinCtrl_14_ds : swPinCtrl_14_ds;
assign T_8090 = xorReg[14];
assign T_8091 = T_8084_oval ^ T_8090;
assign T_8092 = riseIpReg[14];
assign T_8093 = riseIeReg[14];
assign T_8094 = T_8092 & T_8093;
assign T_8095 = fallIpReg[14];
assign T_8096 = fallIeReg[14];
assign T_8097 = T_8095 & T_8096;
assign T_8098 = T_8094 | T_8097;
assign T_8099 = highIpReg[14];
assign T_8100 = highIeReg[14];
assign T_8101 = T_8099 & T_8100;
assign T_8102 = T_8098 | T_8101;
assign T_8103 = lowIpReg[14];
assign T_8104 = lowIeReg[14];
assign T_8105 = T_8103 & T_8104;
assign T_8106 = T_8102 | T_8105;
assign T_8107 = inSyncReg[14];
assign T_8109 = pueReg_io_q[15];
assign T_8110 = portReg[15];
assign T_8111 = oeReg_io_q[15];
assign T_8112 = dsReg[15];
assign T_8113 = ieReg_io_q[15];
assign GEN_291 = io_port_iof_0_15_o_valid ? io_port_iof_0_15_o_oval : swPinCtrl_15_oval;
assign GEN_292 = io_port_iof_0_15_o_valid ? io_port_iof_0_15_o_oe : swPinCtrl_15_oe;
assign GEN_293 = io_port_iof_0_15_o_valid ? io_port_iof_0_15_o_ie : swPinCtrl_15_ie;
assign GEN_294 = io_port_iof_1_15_o_valid ? io_port_iof_1_15_o_oval : swPinCtrl_15_oval;
assign GEN_295 = io_port_iof_1_15_o_valid ? io_port_iof_1_15_o_oe : swPinCtrl_15_oe;
assign GEN_296 = io_port_iof_1_15_o_valid ? io_port_iof_1_15_o_ie : swPinCtrl_15_ie;
assign T_8114 = iofSelReg[15];
assign T_8115_oval = T_8114 ? iof1Ctrl_15_oval : iof0Ctrl_15_oval;
assign T_8115_oe = T_8114 ? iof1Ctrl_15_oe : iof0Ctrl_15_oe;
assign T_8115_ie = T_8114 ? iof1Ctrl_15_ie : iof0Ctrl_15_ie;
assign T_8119 = iofEnReg_io_q[15];
assign T_8120_oval = T_8119 ? iofPlusSwPinCtrl_15_oval : swPinCtrl_15_oval;
assign T_8120_oe = T_8119 ? iofPlusSwPinCtrl_15_oe : swPinCtrl_15_oe;
assign T_8120_ie = T_8119 ? iofPlusSwPinCtrl_15_ie : swPinCtrl_15_ie;
assign T_8120_pue = T_8119 ? iofPlusSwPinCtrl_15_pue : swPinCtrl_15_pue;
assign T_8120_ds = T_8119 ? iofPlusSwPinCtrl_15_ds : swPinCtrl_15_ds;
assign T_8126 = xorReg[15];
assign T_8127 = T_8120_oval ^ T_8126;
assign T_8128 = riseIpReg[15];
assign T_8129 = riseIeReg[15];
assign T_8130 = T_8128 & T_8129;
assign T_8131 = fallIpReg[15];
assign T_8132 = fallIeReg[15];
assign T_8133 = T_8131 & T_8132;
assign T_8134 = T_8130 | T_8133;
assign T_8135 = highIpReg[15];
assign T_8136 = highIeReg[15];
assign T_8137 = T_8135 & T_8136;
assign T_8138 = T_8134 | T_8137;
assign T_8139 = lowIpReg[15];
assign T_8140 = lowIeReg[15];
assign T_8141 = T_8139 & T_8140;
assign T_8142 = T_8138 | T_8141;
assign T_8143 = inSyncReg[15];
assign T_8145 = pueReg_io_q[16];
assign T_8146 = portReg[16];
assign T_8147 = oeReg_io_q[16];
assign T_8148 = dsReg[16];
assign T_8149 = ieReg_io_q[16];
assign GEN_297 = io_port_iof_0_16_o_valid ? io_port_iof_0_16_o_oval : swPinCtrl_16_oval;
assign GEN_298 = io_port_iof_0_16_o_valid ? io_port_iof_0_16_o_oe : swPinCtrl_16_oe;
assign GEN_299 = io_port_iof_0_16_o_valid ? io_port_iof_0_16_o_ie : swPinCtrl_16_ie;
assign GEN_300 = io_port_iof_1_16_o_valid ? io_port_iof_1_16_o_oval : swPinCtrl_16_oval;
assign GEN_301 = io_port_iof_1_16_o_valid ? io_port_iof_1_16_o_oe : swPinCtrl_16_oe;
assign GEN_302 = io_port_iof_1_16_o_valid ? io_port_iof_1_16_o_ie : swPinCtrl_16_ie;
assign T_8150 = iofSelReg[16];
assign T_8151_oval = T_8150 ? iof1Ctrl_16_oval : iof0Ctrl_16_oval;
assign T_8151_oe = T_8150 ? iof1Ctrl_16_oe : iof0Ctrl_16_oe;
assign T_8151_ie = T_8150 ? iof1Ctrl_16_ie : iof0Ctrl_16_ie;
assign T_8155 = iofEnReg_io_q[16];
assign T_8156_oval = T_8155 ? iofPlusSwPinCtrl_16_oval : swPinCtrl_16_oval;
assign T_8156_oe = T_8155 ? iofPlusSwPinCtrl_16_oe : swPinCtrl_16_oe;
assign T_8156_ie = T_8155 ? iofPlusSwPinCtrl_16_ie : swPinCtrl_16_ie;
assign T_8156_pue = T_8155 ? iofPlusSwPinCtrl_16_pue : swPinCtrl_16_pue;
assign T_8156_ds = T_8155 ? iofPlusSwPinCtrl_16_ds : swPinCtrl_16_ds;
assign T_8162 = xorReg[16];
assign T_8163 = T_8156_oval ^ T_8162;
assign T_8164 = riseIpReg[16];
assign T_8165 = riseIeReg[16];
assign T_8166 = T_8164 & T_8165;
assign T_8167 = fallIpReg[16];
assign T_8168 = fallIeReg[16];
assign T_8169 = T_8167 & T_8168;
assign T_8170 = T_8166 | T_8169;
assign T_8171 = highIpReg[16];
assign T_8172 = highIeReg[16];
assign T_8173 = T_8171 & T_8172;
assign T_8174 = T_8170 | T_8173;
assign T_8175 = lowIpReg[16];
assign T_8176 = lowIeReg[16];
assign T_8177 = T_8175 & T_8176;
assign T_8178 = T_8174 | T_8177;
assign T_8179 = inSyncReg[16];
assign T_8181 = pueReg_io_q[17];
assign T_8182 = portReg[17];
assign T_8183 = oeReg_io_q[17];
assign T_8184 = dsReg[17];
assign T_8185 = ieReg_io_q[17];
assign GEN_303 = io_port_iof_0_17_o_valid ? io_port_iof_0_17_o_oval : swPinCtrl_17_oval;
assign GEN_304 = io_port_iof_0_17_o_valid ? io_port_iof_0_17_o_oe : swPinCtrl_17_oe;
assign GEN_305 = io_port_iof_0_17_o_valid ? io_port_iof_0_17_o_ie : swPinCtrl_17_ie;
assign GEN_306 = io_port_iof_1_17_o_valid ? io_port_iof_1_17_o_oval : swPinCtrl_17_oval;
assign GEN_307 = io_port_iof_1_17_o_valid ? io_port_iof_1_17_o_oe : swPinCtrl_17_oe;
assign GEN_308 = io_port_iof_1_17_o_valid ? io_port_iof_1_17_o_ie : swPinCtrl_17_ie;
assign T_8186 = iofSelReg[17];
assign T_8187_oval = T_8186 ? iof1Ctrl_17_oval : iof0Ctrl_17_oval;
assign T_8187_oe = T_8186 ? iof1Ctrl_17_oe : iof0Ctrl_17_oe;
assign T_8187_ie = T_8186 ? iof1Ctrl_17_ie : iof0Ctrl_17_ie;
assign T_8191 = iofEnReg_io_q[17];
assign T_8192_oval = T_8191 ? iofPlusSwPinCtrl_17_oval : swPinCtrl_17_oval;
assign T_8192_oe = T_8191 ? iofPlusSwPinCtrl_17_oe : swPinCtrl_17_oe;
assign T_8192_ie = T_8191 ? iofPlusSwPinCtrl_17_ie : swPinCtrl_17_ie;
assign T_8192_pue = T_8191 ? iofPlusSwPinCtrl_17_pue : swPinCtrl_17_pue;
assign T_8192_ds = T_8191 ? iofPlusSwPinCtrl_17_ds : swPinCtrl_17_ds;
assign T_8198 = xorReg[17];
assign T_8199 = T_8192_oval ^ T_8198;
assign T_8200 = riseIpReg[17];
assign T_8201 = riseIeReg[17];
assign T_8202 = T_8200 & T_8201;
assign T_8203 = fallIpReg[17];
assign T_8204 = fallIeReg[17];
assign T_8205 = T_8203 & T_8204;
assign T_8206 = T_8202 | T_8205;
assign T_8207 = highIpReg[17];
assign T_8208 = highIeReg[17];
assign T_8209 = T_8207 & T_8208;
assign T_8210 = T_8206 | T_8209;
assign T_8211 = lowIpReg[17];
assign T_8212 = lowIeReg[17];
assign T_8213 = T_8211 & T_8212;
assign T_8214 = T_8210 | T_8213;
assign T_8215 = inSyncReg[17];
assign T_8217 = pueReg_io_q[18];
assign T_8218 = portReg[18];
assign T_8219 = oeReg_io_q[18];
assign T_8220 = dsReg[18];
assign T_8221 = ieReg_io_q[18];
assign GEN_309 = io_port_iof_0_18_o_valid ? io_port_iof_0_18_o_oval : swPinCtrl_18_oval;
assign GEN_310 = io_port_iof_0_18_o_valid ? io_port_iof_0_18_o_oe : swPinCtrl_18_oe;
assign GEN_311 = io_port_iof_0_18_o_valid ? io_port_iof_0_18_o_ie : swPinCtrl_18_ie;
assign GEN_312 = io_port_iof_1_18_o_valid ? io_port_iof_1_18_o_oval : swPinCtrl_18_oval;
assign GEN_313 = io_port_iof_1_18_o_valid ? io_port_iof_1_18_o_oe : swPinCtrl_18_oe;
assign GEN_314 = io_port_iof_1_18_o_valid ? io_port_iof_1_18_o_ie : swPinCtrl_18_ie;
assign T_8222 = iofSelReg[18];
assign T_8223_oval = T_8222 ? iof1Ctrl_18_oval : iof0Ctrl_18_oval;
assign T_8223_oe = T_8222 ? iof1Ctrl_18_oe : iof0Ctrl_18_oe;
assign T_8223_ie = T_8222 ? iof1Ctrl_18_ie : iof0Ctrl_18_ie;
assign T_8227 = iofEnReg_io_q[18];
assign T_8228_oval = T_8227 ? iofPlusSwPinCtrl_18_oval : swPinCtrl_18_oval;
assign T_8228_oe = T_8227 ? iofPlusSwPinCtrl_18_oe : swPinCtrl_18_oe;
assign T_8228_ie = T_8227 ? iofPlusSwPinCtrl_18_ie : swPinCtrl_18_ie;
assign T_8228_pue = T_8227 ? iofPlusSwPinCtrl_18_pue : swPinCtrl_18_pue;
assign T_8228_ds = T_8227 ? iofPlusSwPinCtrl_18_ds : swPinCtrl_18_ds;
assign T_8234 = xorReg[18];
assign T_8235 = T_8228_oval ^ T_8234;
assign T_8236 = riseIpReg[18];
assign T_8237 = riseIeReg[18];
assign T_8238 = T_8236 & T_8237;
assign T_8239 = fallIpReg[18];
assign T_8240 = fallIeReg[18];
assign T_8241 = T_8239 & T_8240;
assign T_8242 = T_8238 | T_8241;
assign T_8243 = highIpReg[18];
assign T_8244 = highIeReg[18];
assign T_8245 = T_8243 & T_8244;
assign T_8246 = T_8242 | T_8245;
assign T_8247 = lowIpReg[18];
assign T_8248 = lowIeReg[18];
assign T_8249 = T_8247 & T_8248;
assign T_8250 = T_8246 | T_8249;
assign T_8251 = inSyncReg[18];
assign T_8253 = pueReg_io_q[19];
assign T_8254 = portReg[19];
assign T_8255 = oeReg_io_q[19];
assign T_8256 = dsReg[19];
assign T_8257 = ieReg_io_q[19];
assign GEN_315 = io_port_iof_0_19_o_valid ? io_port_iof_0_19_o_oval : swPinCtrl_19_oval;
assign GEN_316 = io_port_iof_0_19_o_valid ? io_port_iof_0_19_o_oe : swPinCtrl_19_oe;
assign GEN_317 = io_port_iof_0_19_o_valid ? io_port_iof_0_19_o_ie : swPinCtrl_19_ie;
assign GEN_318 = io_port_iof_1_19_o_valid ? io_port_iof_1_19_o_oval : swPinCtrl_19_oval;
assign GEN_319 = io_port_iof_1_19_o_valid ? io_port_iof_1_19_o_oe : swPinCtrl_19_oe;
assign GEN_320 = io_port_iof_1_19_o_valid ? io_port_iof_1_19_o_ie : swPinCtrl_19_ie;
assign T_8258 = iofSelReg[19];
assign T_8259_oval = T_8258 ? iof1Ctrl_19_oval : iof0Ctrl_19_oval;
assign T_8259_oe = T_8258 ? iof1Ctrl_19_oe : iof0Ctrl_19_oe;
assign T_8259_ie = T_8258 ? iof1Ctrl_19_ie : iof0Ctrl_19_ie;
assign T_8263 = iofEnReg_io_q[19];
assign T_8264_oval = T_8263 ? iofPlusSwPinCtrl_19_oval : swPinCtrl_19_oval;
assign T_8264_oe = T_8263 ? iofPlusSwPinCtrl_19_oe : swPinCtrl_19_oe;
assign T_8264_ie = T_8263 ? iofPlusSwPinCtrl_19_ie : swPinCtrl_19_ie;
assign T_8264_pue = T_8263 ? iofPlusSwPinCtrl_19_pue : swPinCtrl_19_pue;
assign T_8264_ds = T_8263 ? iofPlusSwPinCtrl_19_ds : swPinCtrl_19_ds;
assign T_8270 = xorReg[19];
assign T_8271 = T_8264_oval ^ T_8270;
assign T_8272 = riseIpReg[19];
assign T_8273 = riseIeReg[19];
assign T_8274 = T_8272 & T_8273;
assign T_8275 = fallIpReg[19];
assign T_8276 = fallIeReg[19];
assign T_8277 = T_8275 & T_8276;
assign T_8278 = T_8274 | T_8277;
assign T_8279 = highIpReg[19];
assign T_8280 = highIeReg[19];
assign T_8281 = T_8279 & T_8280;
assign T_8282 = T_8278 | T_8281;
assign T_8283 = lowIpReg[19];
assign T_8284 = lowIeReg[19];
assign T_8285 = T_8283 & T_8284;
assign T_8286 = T_8282 | T_8285;
assign T_8287 = inSyncReg[19];
assign T_8289 = pueReg_io_q[20];
assign T_8290 = portReg[20];
assign T_8291 = oeReg_io_q[20];
assign T_8292 = dsReg[20];
assign T_8293 = ieReg_io_q[20];
assign GEN_321 = io_port_iof_0_20_o_valid ? io_port_iof_0_20_o_oval : swPinCtrl_20_oval;
assign GEN_322 = io_port_iof_0_20_o_valid ? io_port_iof_0_20_o_oe : swPinCtrl_20_oe;
assign GEN_323 = io_port_iof_0_20_o_valid ? io_port_iof_0_20_o_ie : swPinCtrl_20_ie;
assign GEN_324 = io_port_iof_1_20_o_valid ? io_port_iof_1_20_o_oval : swPinCtrl_20_oval;
assign GEN_325 = io_port_iof_1_20_o_valid ? io_port_iof_1_20_o_oe : swPinCtrl_20_oe;
assign GEN_326 = io_port_iof_1_20_o_valid ? io_port_iof_1_20_o_ie : swPinCtrl_20_ie;
assign T_8294 = iofSelReg[20];
assign T_8295_oval = T_8294 ? iof1Ctrl_20_oval : iof0Ctrl_20_oval;
assign T_8295_oe = T_8294 ? iof1Ctrl_20_oe : iof0Ctrl_20_oe;
assign T_8295_ie = T_8294 ? iof1Ctrl_20_ie : iof0Ctrl_20_ie;
assign T_8299 = iofEnReg_io_q[20];
assign T_8300_oval = T_8299 ? iofPlusSwPinCtrl_20_oval : swPinCtrl_20_oval;
assign T_8300_oe = T_8299 ? iofPlusSwPinCtrl_20_oe : swPinCtrl_20_oe;
assign T_8300_ie = T_8299 ? iofPlusSwPinCtrl_20_ie : swPinCtrl_20_ie;
assign T_8300_pue = T_8299 ? iofPlusSwPinCtrl_20_pue : swPinCtrl_20_pue;
assign T_8300_ds = T_8299 ? iofPlusSwPinCtrl_20_ds : swPinCtrl_20_ds;
assign T_8306 = xorReg[20];
assign T_8307 = T_8300_oval ^ T_8306;
assign T_8308 = riseIpReg[20];
assign T_8309 = riseIeReg[20];
assign T_8310 = T_8308 & T_8309;
assign T_8311 = fallIpReg[20];
assign T_8312 = fallIeReg[20];
assign T_8313 = T_8311 & T_8312;
assign T_8314 = T_8310 | T_8313;
assign T_8315 = highIpReg[20];
assign T_8316 = highIeReg[20];
assign T_8317 = T_8315 & T_8316;
assign T_8318 = T_8314 | T_8317;
assign T_8319 = lowIpReg[20];
assign T_8320 = lowIeReg[20];
assign T_8321 = T_8319 & T_8320;
assign T_8322 = T_8318 | T_8321;
assign T_8323 = inSyncReg[20];
assign T_8325 = pueReg_io_q[21];
assign T_8326 = portReg[21];
assign T_8327 = oeReg_io_q[21];
assign T_8328 = dsReg[21];
assign T_8329 = ieReg_io_q[21];
assign GEN_327 = io_port_iof_0_21_o_valid ? io_port_iof_0_21_o_oval : swPinCtrl_21_oval;
assign GEN_328 = io_port_iof_0_21_o_valid ? io_port_iof_0_21_o_oe : swPinCtrl_21_oe;
assign GEN_329 = io_port_iof_0_21_o_valid ? io_port_iof_0_21_o_ie : swPinCtrl_21_ie;
assign GEN_330 = io_port_iof_1_21_o_valid ? io_port_iof_1_21_o_oval : swPinCtrl_21_oval;
assign GEN_331 = io_port_iof_1_21_o_valid ? io_port_iof_1_21_o_oe : swPinCtrl_21_oe;
assign GEN_332 = io_port_iof_1_21_o_valid ? io_port_iof_1_21_o_ie : swPinCtrl_21_ie;
assign T_8330 = iofSelReg[21];
assign T_8331_oval = T_8330 ? iof1Ctrl_21_oval : iof0Ctrl_21_oval;
assign T_8331_oe = T_8330 ? iof1Ctrl_21_oe : iof0Ctrl_21_oe;
assign T_8331_ie = T_8330 ? iof1Ctrl_21_ie : iof0Ctrl_21_ie;
assign T_8335 = iofEnReg_io_q[21];
assign T_8336_oval = T_8335 ? iofPlusSwPinCtrl_21_oval : swPinCtrl_21_oval;
assign T_8336_oe = T_8335 ? iofPlusSwPinCtrl_21_oe : swPinCtrl_21_oe;
assign T_8336_ie = T_8335 ? iofPlusSwPinCtrl_21_ie : swPinCtrl_21_ie;
assign T_8336_pue = T_8335 ? iofPlusSwPinCtrl_21_pue : swPinCtrl_21_pue;
assign T_8336_ds = T_8335 ? iofPlusSwPinCtrl_21_ds : swPinCtrl_21_ds;
assign T_8342 = xorReg[21];
assign T_8343 = T_8336_oval ^ T_8342;
assign T_8344 = riseIpReg[21];
assign T_8345 = riseIeReg[21];
assign T_8346 = T_8344 & T_8345;
assign T_8347 = fallIpReg[21];
assign T_8348 = fallIeReg[21];
assign T_8349 = T_8347 & T_8348;
assign T_8350 = T_8346 | T_8349;
assign T_8351 = highIpReg[21];
assign T_8352 = highIeReg[21];
assign T_8353 = T_8351 & T_8352;
assign T_8354 = T_8350 | T_8353;
assign T_8355 = lowIpReg[21];
assign T_8356 = lowIeReg[21];
assign T_8357 = T_8355 & T_8356;
assign T_8358 = T_8354 | T_8357;
assign T_8359 = inSyncReg[21];
assign T_8361 = pueReg_io_q[22];
assign T_8362 = portReg[22];
assign T_8363 = oeReg_io_q[22];
assign T_8364 = dsReg[22];
assign T_8365 = ieReg_io_q[22];
assign GEN_333 = io_port_iof_0_22_o_valid ? io_port_iof_0_22_o_oval : swPinCtrl_22_oval;
assign GEN_334 = io_port_iof_0_22_o_valid ? io_port_iof_0_22_o_oe : swPinCtrl_22_oe;
assign GEN_335 = io_port_iof_0_22_o_valid ? io_port_iof_0_22_o_ie : swPinCtrl_22_ie;
assign GEN_336 = io_port_iof_1_22_o_valid ? io_port_iof_1_22_o_oval : swPinCtrl_22_oval;
assign GEN_337 = io_port_iof_1_22_o_valid ? io_port_iof_1_22_o_oe : swPinCtrl_22_oe;
assign GEN_338 = io_port_iof_1_22_o_valid ? io_port_iof_1_22_o_ie : swPinCtrl_22_ie;
assign T_8366 = iofSelReg[22];
assign T_8367_oval = T_8366 ? iof1Ctrl_22_oval : iof0Ctrl_22_oval;
assign T_8367_oe = T_8366 ? iof1Ctrl_22_oe : iof0Ctrl_22_oe;
assign T_8367_ie = T_8366 ? iof1Ctrl_22_ie : iof0Ctrl_22_ie;
assign T_8371 = iofEnReg_io_q[22];
assign T_8372_oval = T_8371 ? iofPlusSwPinCtrl_22_oval : swPinCtrl_22_oval;
assign T_8372_oe = T_8371 ? iofPlusSwPinCtrl_22_oe : swPinCtrl_22_oe;
assign T_8372_ie = T_8371 ? iofPlusSwPinCtrl_22_ie : swPinCtrl_22_ie;
assign T_8372_pue = T_8371 ? iofPlusSwPinCtrl_22_pue : swPinCtrl_22_pue;
assign T_8372_ds = T_8371 ? iofPlusSwPinCtrl_22_ds : swPinCtrl_22_ds;
assign T_8378 = xorReg[22];
assign T_8379 = T_8372_oval ^ T_8378;
assign T_8380 = riseIpReg[22];
assign T_8381 = riseIeReg[22];
assign T_8382 = T_8380 & T_8381;
assign T_8383 = fallIpReg[22];
assign T_8384 = fallIeReg[22];
assign T_8385 = T_8383 & T_8384;
assign T_8386 = T_8382 | T_8385;
assign T_8387 = highIpReg[22];
assign T_8388 = highIeReg[22];
assign T_8389 = T_8387 & T_8388;
assign T_8390 = T_8386 | T_8389;
assign T_8391 = lowIpReg[22];
assign T_8392 = lowIeReg[22];
assign T_8393 = T_8391 & T_8392;
assign T_8394 = T_8390 | T_8393;
assign T_8395 = inSyncReg[22];
assign T_8397 = pueReg_io_q[23];
assign T_8398 = portReg[23];
assign T_8399 = oeReg_io_q[23];
assign T_8400 = dsReg[23];
assign T_8401 = ieReg_io_q[23];
assign GEN_339 = io_port_iof_0_23_o_valid ? io_port_iof_0_23_o_oval : swPinCtrl_23_oval;
assign GEN_340 = io_port_iof_0_23_o_valid ? io_port_iof_0_23_o_oe : swPinCtrl_23_oe;
assign GEN_341 = io_port_iof_0_23_o_valid ? io_port_iof_0_23_o_ie : swPinCtrl_23_ie;
assign GEN_342 = io_port_iof_1_23_o_valid ? io_port_iof_1_23_o_oval : swPinCtrl_23_oval;
assign GEN_343 = io_port_iof_1_23_o_valid ? io_port_iof_1_23_o_oe : swPinCtrl_23_oe;
assign GEN_344 = io_port_iof_1_23_o_valid ? io_port_iof_1_23_o_ie : swPinCtrl_23_ie;
assign T_8402 = iofSelReg[23];
assign T_8403_oval = T_8402 ? iof1Ctrl_23_oval : iof0Ctrl_23_oval;
assign T_8403_oe = T_8402 ? iof1Ctrl_23_oe : iof0Ctrl_23_oe;
assign T_8403_ie = T_8402 ? iof1Ctrl_23_ie : iof0Ctrl_23_ie;
assign T_8407 = iofEnReg_io_q[23];
assign T_8408_oval = T_8407 ? iofPlusSwPinCtrl_23_oval : swPinCtrl_23_oval;
assign T_8408_oe = T_8407 ? iofPlusSwPinCtrl_23_oe : swPinCtrl_23_oe;
assign T_8408_ie = T_8407 ? iofPlusSwPinCtrl_23_ie : swPinCtrl_23_ie;
assign T_8408_pue = T_8407 ? iofPlusSwPinCtrl_23_pue : swPinCtrl_23_pue;
assign T_8408_ds = T_8407 ? iofPlusSwPinCtrl_23_ds : swPinCtrl_23_ds;
assign T_8414 = xorReg[23];
assign T_8415 = T_8408_oval ^ T_8414;
assign T_8416 = riseIpReg[23];
assign T_8417 = riseIeReg[23];
assign T_8418 = T_8416 & T_8417;
assign T_8419 = fallIpReg[23];
assign T_8420 = fallIeReg[23];
assign T_8421 = T_8419 & T_8420;
assign T_8422 = T_8418 | T_8421;
assign T_8423 = highIpReg[23];
assign T_8424 = highIeReg[23];
assign T_8425 = T_8423 & T_8424;
assign T_8426 = T_8422 | T_8425;
assign T_8427 = lowIpReg[23];
assign T_8428 = lowIeReg[23];
assign T_8429 = T_8427 & T_8428;
assign T_8430 = T_8426 | T_8429;
assign T_8431 = inSyncReg[23];
assign T_8433 = pueReg_io_q[24];
assign T_8434 = portReg[24];
assign T_8435 = oeReg_io_q[24];
assign T_8436 = dsReg[24];
assign T_8437 = ieReg_io_q[24];
assign GEN_345 = io_port_iof_0_24_o_valid ? io_port_iof_0_24_o_oval : swPinCtrl_24_oval;
assign GEN_346 = io_port_iof_0_24_o_valid ? io_port_iof_0_24_o_oe : swPinCtrl_24_oe;
assign GEN_347 = io_port_iof_0_24_o_valid ? io_port_iof_0_24_o_ie : swPinCtrl_24_ie;
assign GEN_348 = io_port_iof_1_24_o_valid ? io_port_iof_1_24_o_oval : swPinCtrl_24_oval;
assign GEN_349 = io_port_iof_1_24_o_valid ? io_port_iof_1_24_o_oe : swPinCtrl_24_oe;
assign GEN_350 = io_port_iof_1_24_o_valid ? io_port_iof_1_24_o_ie : swPinCtrl_24_ie;
assign T_8438 = iofSelReg[24];
assign T_8439_oval = T_8438 ? iof1Ctrl_24_oval : iof0Ctrl_24_oval;
assign T_8439_oe = T_8438 ? iof1Ctrl_24_oe : iof0Ctrl_24_oe;
assign T_8439_ie = T_8438 ? iof1Ctrl_24_ie : iof0Ctrl_24_ie;
assign T_8443 = iofEnReg_io_q[24];
assign T_8444_oval = T_8443 ? iofPlusSwPinCtrl_24_oval : swPinCtrl_24_oval;
assign T_8444_oe = T_8443 ? iofPlusSwPinCtrl_24_oe : swPinCtrl_24_oe;
assign T_8444_ie = T_8443 ? iofPlusSwPinCtrl_24_ie : swPinCtrl_24_ie;
assign T_8444_pue = T_8443 ? iofPlusSwPinCtrl_24_pue : swPinCtrl_24_pue;
assign T_8444_ds = T_8443 ? iofPlusSwPinCtrl_24_ds : swPinCtrl_24_ds;
assign T_8450 = xorReg[24];
assign T_8451 = T_8444_oval ^ T_8450;
assign T_8452 = riseIpReg[24];
assign T_8453 = riseIeReg[24];
assign T_8454 = T_8452 & T_8453;
assign T_8455 = fallIpReg[24];
assign T_8456 = fallIeReg[24];
assign T_8457 = T_8455 & T_8456;
assign T_8458 = T_8454 | T_8457;
assign T_8459 = highIpReg[24];
assign T_8460 = highIeReg[24];
assign T_8461 = T_8459 & T_8460;
assign T_8462 = T_8458 | T_8461;
assign T_8463 = lowIpReg[24];
assign T_8464 = lowIeReg[24];
assign T_8465 = T_8463 & T_8464;
assign T_8466 = T_8462 | T_8465;
assign T_8467 = inSyncReg[24];
assign T_8469 = pueReg_io_q[25];
assign T_8470 = portReg[25];
assign T_8471 = oeReg_io_q[25];
assign T_8472 = dsReg[25];
assign T_8473 = ieReg_io_q[25];
assign GEN_351 = io_port_iof_0_25_o_valid ? io_port_iof_0_25_o_oval : swPinCtrl_25_oval;
assign GEN_352 = io_port_iof_0_25_o_valid ? io_port_iof_0_25_o_oe : swPinCtrl_25_oe;
assign GEN_353 = io_port_iof_0_25_o_valid ? io_port_iof_0_25_o_ie : swPinCtrl_25_ie;
assign GEN_354 = io_port_iof_1_25_o_valid ? io_port_iof_1_25_o_oval : swPinCtrl_25_oval;
assign GEN_355 = io_port_iof_1_25_o_valid ? io_port_iof_1_25_o_oe : swPinCtrl_25_oe;
assign GEN_356 = io_port_iof_1_25_o_valid ? io_port_iof_1_25_o_ie : swPinCtrl_25_ie;
assign T_8474 = iofSelReg[25];
assign T_8475_oval = T_8474 ? iof1Ctrl_25_oval : iof0Ctrl_25_oval;
assign T_8475_oe = T_8474 ? iof1Ctrl_25_oe : iof0Ctrl_25_oe;
assign T_8475_ie = T_8474 ? iof1Ctrl_25_ie : iof0Ctrl_25_ie;
assign T_8479 = iofEnReg_io_q[25];
assign T_8480_oval = T_8479 ? iofPlusSwPinCtrl_25_oval : swPinCtrl_25_oval;
assign T_8480_oe = T_8479 ? iofPlusSwPinCtrl_25_oe : swPinCtrl_25_oe;
assign T_8480_ie = T_8479 ? iofPlusSwPinCtrl_25_ie : swPinCtrl_25_ie;
assign T_8480_pue = T_8479 ? iofPlusSwPinCtrl_25_pue : swPinCtrl_25_pue;
assign T_8480_ds = T_8479 ? iofPlusSwPinCtrl_25_ds : swPinCtrl_25_ds;
assign T_8486 = xorReg[25];
assign T_8487 = T_8480_oval ^ T_8486;
assign T_8488 = riseIpReg[25];
assign T_8489 = riseIeReg[25];
assign T_8490 = T_8488 & T_8489;
assign T_8491 = fallIpReg[25];
assign T_8492 = fallIeReg[25];
assign T_8493 = T_8491 & T_8492;
assign T_8494 = T_8490 | T_8493;
assign T_8495 = highIpReg[25];
assign T_8496 = highIeReg[25];
assign T_8497 = T_8495 & T_8496;
assign T_8498 = T_8494 | T_8497;
assign T_8499 = lowIpReg[25];
assign T_8500 = lowIeReg[25];
assign T_8501 = T_8499 & T_8500;
assign T_8502 = T_8498 | T_8501;
assign T_8503 = inSyncReg[25];
assign T_8505 = pueReg_io_q[26];
assign T_8506 = portReg[26];
assign T_8507 = oeReg_io_q[26];
assign T_8508 = dsReg[26];
assign T_8509 = ieReg_io_q[26];
assign GEN_357 = io_port_iof_0_26_o_valid ? io_port_iof_0_26_o_oval : swPinCtrl_26_oval;
assign GEN_358 = io_port_iof_0_26_o_valid ? io_port_iof_0_26_o_oe : swPinCtrl_26_oe;
assign GEN_359 = io_port_iof_0_26_o_valid ? io_port_iof_0_26_o_ie : swPinCtrl_26_ie;
assign GEN_360 = io_port_iof_1_26_o_valid ? io_port_iof_1_26_o_oval : swPinCtrl_26_oval;
assign GEN_361 = io_port_iof_1_26_o_valid ? io_port_iof_1_26_o_oe : swPinCtrl_26_oe;
assign GEN_362 = io_port_iof_1_26_o_valid ? io_port_iof_1_26_o_ie : swPinCtrl_26_ie;
assign T_8510 = iofSelReg[26];
assign T_8511_oval = T_8510 ? iof1Ctrl_26_oval : iof0Ctrl_26_oval;
assign T_8511_oe = T_8510 ? iof1Ctrl_26_oe : iof0Ctrl_26_oe;
assign T_8511_ie = T_8510 ? iof1Ctrl_26_ie : iof0Ctrl_26_ie;
assign T_8515 = iofEnReg_io_q[26];
assign T_8516_oval = T_8515 ? iofPlusSwPinCtrl_26_oval : swPinCtrl_26_oval;
assign T_8516_oe = T_8515 ? iofPlusSwPinCtrl_26_oe : swPinCtrl_26_oe;
assign T_8516_ie = T_8515 ? iofPlusSwPinCtrl_26_ie : swPinCtrl_26_ie;
assign T_8516_pue = T_8515 ? iofPlusSwPinCtrl_26_pue : swPinCtrl_26_pue;
assign T_8516_ds = T_8515 ? iofPlusSwPinCtrl_26_ds : swPinCtrl_26_ds;
assign T_8522 = xorReg[26];
assign T_8523 = T_8516_oval ^ T_8522;
assign T_8524 = riseIpReg[26];
assign T_8525 = riseIeReg[26];
assign T_8526 = T_8524 & T_8525;
assign T_8527 = fallIpReg[26];
assign T_8528 = fallIeReg[26];
assign T_8529 = T_8527 & T_8528;
assign T_8530 = T_8526 | T_8529;
assign T_8531 = highIpReg[26];
assign T_8532 = highIeReg[26];
assign T_8533 = T_8531 & T_8532;
assign T_8534 = T_8530 | T_8533;
assign T_8535 = lowIpReg[26];
assign T_8536 = lowIeReg[26];
assign T_8537 = T_8535 & T_8536;
assign T_8538 = T_8534 | T_8537;
assign T_8539 = inSyncReg[26];
assign T_8541 = pueReg_io_q[27];
assign T_8542 = portReg[27];
assign T_8543 = oeReg_io_q[27];
assign T_8544 = dsReg[27];
assign T_8545 = ieReg_io_q[27];
assign GEN_363 = io_port_iof_0_27_o_valid ? io_port_iof_0_27_o_oval : swPinCtrl_27_oval;
assign GEN_364 = io_port_iof_0_27_o_valid ? io_port_iof_0_27_o_oe : swPinCtrl_27_oe;
assign GEN_365 = io_port_iof_0_27_o_valid ? io_port_iof_0_27_o_ie : swPinCtrl_27_ie;
assign GEN_366 = io_port_iof_1_27_o_valid ? io_port_iof_1_27_o_oval : swPinCtrl_27_oval;
assign GEN_367 = io_port_iof_1_27_o_valid ? io_port_iof_1_27_o_oe : swPinCtrl_27_oe;
assign GEN_368 = io_port_iof_1_27_o_valid ? io_port_iof_1_27_o_ie : swPinCtrl_27_ie;
assign T_8546 = iofSelReg[27];
assign T_8547_oval = T_8546 ? iof1Ctrl_27_oval : iof0Ctrl_27_oval;
assign T_8547_oe = T_8546 ? iof1Ctrl_27_oe : iof0Ctrl_27_oe;
assign T_8547_ie = T_8546 ? iof1Ctrl_27_ie : iof0Ctrl_27_ie;
assign T_8551 = iofEnReg_io_q[27];
assign T_8552_oval = T_8551 ? iofPlusSwPinCtrl_27_oval : swPinCtrl_27_oval;
assign T_8552_oe = T_8551 ? iofPlusSwPinCtrl_27_oe : swPinCtrl_27_oe;
assign T_8552_ie = T_8551 ? iofPlusSwPinCtrl_27_ie : swPinCtrl_27_ie;
assign T_8552_pue = T_8551 ? iofPlusSwPinCtrl_27_pue : swPinCtrl_27_pue;
assign T_8552_ds = T_8551 ? iofPlusSwPinCtrl_27_ds : swPinCtrl_27_ds;
assign T_8558 = xorReg[27];
assign T_8559 = T_8552_oval ^ T_8558;
assign T_8560 = riseIpReg[27];
assign T_8561 = riseIeReg[27];
assign T_8562 = T_8560 & T_8561;
assign T_8563 = fallIpReg[27];
assign T_8564 = fallIeReg[27];
assign T_8565 = T_8563 & T_8564;
assign T_8566 = T_8562 | T_8565;
assign T_8567 = highIpReg[27];
assign T_8568 = highIeReg[27];
assign T_8569 = T_8567 & T_8568;
assign T_8570 = T_8566 | T_8569;
assign T_8571 = lowIpReg[27];
assign T_8572 = lowIeReg[27];
assign T_8573 = T_8571 & T_8572;
assign T_8574 = T_8570 | T_8573;
assign T_8575 = inSyncReg[27];
assign T_8577 = pueReg_io_q[28];
assign T_8578 = portReg[28];
assign T_8579 = oeReg_io_q[28];
assign T_8580 = dsReg[28];
assign T_8581 = ieReg_io_q[28];
assign GEN_369 = io_port_iof_0_28_o_valid ? io_port_iof_0_28_o_oval : swPinCtrl_28_oval;
assign GEN_370 = io_port_iof_0_28_o_valid ? io_port_iof_0_28_o_oe : swPinCtrl_28_oe;
assign GEN_371 = io_port_iof_0_28_o_valid ? io_port_iof_0_28_o_ie : swPinCtrl_28_ie;
assign GEN_372 = io_port_iof_1_28_o_valid ? io_port_iof_1_28_o_oval : swPinCtrl_28_oval;
assign GEN_373 = io_port_iof_1_28_o_valid ? io_port_iof_1_28_o_oe : swPinCtrl_28_oe;
assign GEN_374 = io_port_iof_1_28_o_valid ? io_port_iof_1_28_o_ie : swPinCtrl_28_ie;
assign T_8582 = iofSelReg[28];
assign T_8583_oval = T_8582 ? iof1Ctrl_28_oval : iof0Ctrl_28_oval;
assign T_8583_oe = T_8582 ? iof1Ctrl_28_oe : iof0Ctrl_28_oe;
assign T_8583_ie = T_8582 ? iof1Ctrl_28_ie : iof0Ctrl_28_ie;
assign T_8587 = iofEnReg_io_q[28];
assign T_8588_oval = T_8587 ? iofPlusSwPinCtrl_28_oval : swPinCtrl_28_oval;
assign T_8588_oe = T_8587 ? iofPlusSwPinCtrl_28_oe : swPinCtrl_28_oe;
assign T_8588_ie = T_8587 ? iofPlusSwPinCtrl_28_ie : swPinCtrl_28_ie;
assign T_8588_pue = T_8587 ? iofPlusSwPinCtrl_28_pue : swPinCtrl_28_pue;
assign T_8588_ds = T_8587 ? iofPlusSwPinCtrl_28_ds : swPinCtrl_28_ds;
assign T_8594 = xorReg[28];
assign T_8595 = T_8588_oval ^ T_8594;
assign T_8596 = riseIpReg[28];
assign T_8597 = riseIeReg[28];
assign T_8598 = T_8596 & T_8597;
assign T_8599 = fallIpReg[28];
assign T_8600 = fallIeReg[28];
assign T_8601 = T_8599 & T_8600;
assign T_8602 = T_8598 | T_8601;
assign T_8603 = highIpReg[28];
assign T_8604 = highIeReg[28];
assign T_8605 = T_8603 & T_8604;
assign T_8606 = T_8602 | T_8605;
assign T_8607 = lowIpReg[28];
assign T_8608 = lowIeReg[28];
assign T_8609 = T_8607 & T_8608;
assign T_8610 = T_8606 | T_8609;
assign T_8611 = inSyncReg[28];
assign T_8613 = pueReg_io_q[29];
assign T_8614 = portReg[29];
assign T_8615 = oeReg_io_q[29];
assign T_8616 = dsReg[29];
assign T_8617 = ieReg_io_q[29];
assign GEN_375 = io_port_iof_0_29_o_valid ? io_port_iof_0_29_o_oval : swPinCtrl_29_oval;
assign GEN_376 = io_port_iof_0_29_o_valid ? io_port_iof_0_29_o_oe : swPinCtrl_29_oe;
assign GEN_377 = io_port_iof_0_29_o_valid ? io_port_iof_0_29_o_ie : swPinCtrl_29_ie;
assign GEN_378 = io_port_iof_1_29_o_valid ? io_port_iof_1_29_o_oval : swPinCtrl_29_oval;
assign GEN_379 = io_port_iof_1_29_o_valid ? io_port_iof_1_29_o_oe : swPinCtrl_29_oe;
assign GEN_380 = io_port_iof_1_29_o_valid ? io_port_iof_1_29_o_ie : swPinCtrl_29_ie;
assign T_8618 = iofSelReg[29];
assign T_8619_oval = T_8618 ? iof1Ctrl_29_oval : iof0Ctrl_29_oval;
assign T_8619_oe = T_8618 ? iof1Ctrl_29_oe : iof0Ctrl_29_oe;
assign T_8619_ie = T_8618 ? iof1Ctrl_29_ie : iof0Ctrl_29_ie;
assign T_8623 = iofEnReg_io_q[29];
assign T_8624_oval = T_8623 ? iofPlusSwPinCtrl_29_oval : swPinCtrl_29_oval;
assign T_8624_oe = T_8623 ? iofPlusSwPinCtrl_29_oe : swPinCtrl_29_oe;
assign T_8624_ie = T_8623 ? iofPlusSwPinCtrl_29_ie : swPinCtrl_29_ie;
assign T_8624_pue = T_8623 ? iofPlusSwPinCtrl_29_pue : swPinCtrl_29_pue;
assign T_8624_ds = T_8623 ? iofPlusSwPinCtrl_29_ds : swPinCtrl_29_ds;
assign T_8630 = xorReg[29];
assign T_8631 = T_8624_oval ^ T_8630;
assign T_8632 = riseIpReg[29];
assign T_8633 = riseIeReg[29];
assign T_8634 = T_8632 & T_8633;
assign T_8635 = fallIpReg[29];
assign T_8636 = fallIeReg[29];
assign T_8637 = T_8635 & T_8636;
assign T_8638 = T_8634 | T_8637;
assign T_8639 = highIpReg[29];
assign T_8640 = highIeReg[29];
assign T_8641 = T_8639 & T_8640;
assign T_8642 = T_8638 | T_8641;
assign T_8643 = lowIpReg[29];
assign T_8644 = lowIeReg[29];
assign T_8645 = T_8643 & T_8644;
assign T_8646 = T_8642 | T_8645;
assign T_8647 = inSyncReg[29];
assign T_8649 = pueReg_io_q[30];
assign T_8650 = portReg[30];
assign T_8651 = oeReg_io_q[30];
assign T_8652 = dsReg[30];
assign T_8653 = ieReg_io_q[30];
assign GEN_381 = io_port_iof_0_30_o_valid ? io_port_iof_0_30_o_oval : swPinCtrl_30_oval;
assign GEN_382 = io_port_iof_0_30_o_valid ? io_port_iof_0_30_o_oe : swPinCtrl_30_oe;
assign GEN_383 = io_port_iof_0_30_o_valid ? io_port_iof_0_30_o_ie : swPinCtrl_30_ie;
assign GEN_384 = io_port_iof_1_30_o_valid ? io_port_iof_1_30_o_oval : swPinCtrl_30_oval;
assign GEN_385 = io_port_iof_1_30_o_valid ? io_port_iof_1_30_o_oe : swPinCtrl_30_oe;
assign GEN_386 = io_port_iof_1_30_o_valid ? io_port_iof_1_30_o_ie : swPinCtrl_30_ie;
assign T_8654 = iofSelReg[30];
assign T_8655_oval = T_8654 ? iof1Ctrl_30_oval : iof0Ctrl_30_oval;
assign T_8655_oe = T_8654 ? iof1Ctrl_30_oe : iof0Ctrl_30_oe;
assign T_8655_ie = T_8654 ? iof1Ctrl_30_ie : iof0Ctrl_30_ie;
assign T_8659 = iofEnReg_io_q[30];
assign T_8660_oval = T_8659 ? iofPlusSwPinCtrl_30_oval : swPinCtrl_30_oval;
assign T_8660_oe = T_8659 ? iofPlusSwPinCtrl_30_oe : swPinCtrl_30_oe;
assign T_8660_ie = T_8659 ? iofPlusSwPinCtrl_30_ie : swPinCtrl_30_ie;
assign T_8660_pue = T_8659 ? iofPlusSwPinCtrl_30_pue : swPinCtrl_30_pue;
assign T_8660_ds = T_8659 ? iofPlusSwPinCtrl_30_ds : swPinCtrl_30_ds;
assign T_8666 = xorReg[30];
assign T_8667 = T_8660_oval ^ T_8666;
assign T_8668 = riseIpReg[30];
assign T_8669 = riseIeReg[30];
assign T_8670 = T_8668 & T_8669;
assign T_8671 = fallIpReg[30];
assign T_8672 = fallIeReg[30];
assign T_8673 = T_8671 & T_8672;
assign T_8674 = T_8670 | T_8673;
assign T_8675 = highIpReg[30];
assign T_8676 = highIeReg[30];
assign T_8677 = T_8675 & T_8676;
assign T_8678 = T_8674 | T_8677;
assign T_8679 = lowIpReg[30];
assign T_8680 = lowIeReg[30];
assign T_8681 = T_8679 & T_8680;
assign T_8682 = T_8678 | T_8681;
assign T_8683 = inSyncReg[30];
assign T_8685 = pueReg_io_q[31];
assign T_8686 = portReg[31];
assign T_8687 = oeReg_io_q[31];
assign T_8688 = dsReg[31];
assign T_8689 = ieReg_io_q[31];
assign GEN_387 = io_port_iof_0_31_o_valid ? io_port_iof_0_31_o_oval : swPinCtrl_31_oval;
assign GEN_388 = io_port_iof_0_31_o_valid ? io_port_iof_0_31_o_oe : swPinCtrl_31_oe;
assign GEN_389 = io_port_iof_0_31_o_valid ? io_port_iof_0_31_o_ie : swPinCtrl_31_ie;
assign GEN_390 = io_port_iof_1_31_o_valid ? io_port_iof_1_31_o_oval : swPinCtrl_31_oval;
assign GEN_391 = io_port_iof_1_31_o_valid ? io_port_iof_1_31_o_oe : swPinCtrl_31_oe;
assign GEN_392 = io_port_iof_1_31_o_valid ? io_port_iof_1_31_o_ie : swPinCtrl_31_ie;
assign T_8690 = iofSelReg[31];
assign T_8691_oval = T_8690 ? iof1Ctrl_31_oval : iof0Ctrl_31_oval;
assign T_8691_oe = T_8690 ? iof1Ctrl_31_oe : iof0Ctrl_31_oe;
assign T_8691_ie = T_8690 ? iof1Ctrl_31_ie : iof0Ctrl_31_ie;
assign T_8695 = iofEnReg_io_q[31];
assign T_8696_oval = T_8695 ? iofPlusSwPinCtrl_31_oval : swPinCtrl_31_oval;
assign T_8696_oe = T_8695 ? iofPlusSwPinCtrl_31_oe : swPinCtrl_31_oe;
assign T_8696_ie = T_8695 ? iofPlusSwPinCtrl_31_ie : swPinCtrl_31_ie;
assign T_8696_pue = T_8695 ? iofPlusSwPinCtrl_31_pue : swPinCtrl_31_pue;
assign T_8696_ds = T_8695 ? iofPlusSwPinCtrl_31_ds : swPinCtrl_31_ds;
assign T_8702 = xorReg[31];
assign T_8703 = T_8696_oval ^ T_8702;
assign T_8704 = riseIpReg[31];
assign T_8705 = riseIeReg[31];
assign T_8706 = T_8704 & T_8705;
assign T_8707 = fallIpReg[31];
assign T_8708 = fallIeReg[31];
assign T_8709 = T_8707 & T_8708;
assign T_8710 = T_8706 | T_8709;
assign T_8711 = highIpReg[31];
assign T_8712 = highIeReg[31];
assign T_8713 = T_8711 & T_8712;
assign T_8714 = T_8710 | T_8713;
assign T_8715 = lowIpReg[31];
assign T_8716 = lowIeReg[31];
assign T_8717 = T_8715 & T_8716;
assign T_8718 = T_8714 | T_8717;
assign T_8719 = inSyncReg[31];
always @(posedge clock or posedge reset)
if(reset) begin
T_3256 <= 32'b0;
T_3257 <= 32'b0;
inSyncReg <= 32'b0;
end
else begin
T_3256 <= inVal;
T_3257 <= T_3256;
inSyncReg <= T_3257;
end
always @(posedge clock or posedge reset)
if (reset) begin
portReg <= 32'h0;
end else begin
if (T_4329) begin
portReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
dsReg <= 32'h0;
end else begin
if (T_3911) begin
dsReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
valueReg <= 32'h0;
end else begin
valueReg <= inSyncReg;
end
always @(posedge clock or posedge reset)
if (reset) begin
highIeReg <= 32'h0;
end else begin
if (T_3951) begin
highIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
lowIeReg <= 32'h0;
end else begin
if (T_4243) begin
lowIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
riseIeReg <= 32'h0;
end else begin
if (T_4071) begin
riseIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
fallIeReg <= 32'h0;
end else begin
if (T_4455) begin
fallIeReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
highIpReg <= 32'h0;
end else begin
highIpReg <= T_4417;
end
always @(posedge clock or posedge reset)
if (reset) begin
lowIpReg <= 32'h0;
end else begin
lowIpReg <= T_4165;
end
always @(posedge clock or posedge reset)
if (reset) begin
riseIpReg <= 32'h0;
end else begin
riseIpReg <= T_4291;
end
always @(posedge clock or posedge reset)
if (reset) begin
fallIpReg <= 32'h0;
end else begin
fallIpReg <= T_4119;
end
always @(posedge clock or posedge reset)
if (reset) begin
iofSelReg <= 32'h0;
end else begin
if (T_4535) begin
iofSelReg <= T_3370_bits_data;
end
end
always @(posedge clock or posedge reset)
if (reset) begin
xorReg <= 32'h0;
end else begin
if (T_4369) begin
xorReg <= T_3370_bits_data;
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
`define SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A221OI_BEHAVIORAL_V |
/*
* Copyright (c) 2015-2016 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Testbench for micro UART
*/
`include "common.vh"
`include "ocp_const.vh"
`ifndef TRACE_FILE
`define TRACE_FILE "trace.vcd"
`endif
module tb_micro_uart();
localparam HCLK = 5;
localparam PCLK = 2*HCLK; /* Clock period */
/* Micro UART register offsets */
localparam [`ADDR_WIDTH-1:0] CHARREG = 32'h000; /* Character register */
reg clk;
reg nrst;
reg [`ADDR_WIDTH-1:0] MAddr;
reg [2:0] MCmd;
reg [`DATA_WIDTH-1:0] MData;
reg [`BEN_WIDTH-1:0] MByteEn;
wire SCmdAccept;
wire [`DATA_WIDTH-1:0] SData;
wire [1:0] SResp;
always
#HCLK clk = !clk;
/* Issue bus read */
task bus_read;
input [`ADDR_WIDTH-1:0] addr;
begin
@(posedge clk)
begin
MAddr <= addr;
MByteEn <= 4'hf;
MCmd <= `OCP_CMD_READ;
end
@(posedge clk)
begin
MAddr <= 0;
MByteEn <= 4'h0;
MCmd <= `OCP_CMD_IDLE;
end
end
endtask
/* Issue bus write */
task bus_write;
input [`ADDR_WIDTH-1:0] addr;
input [`DATA_WIDTH-1:0] data;
begin
@(posedge clk)
begin
MAddr <= addr;
MData <= data;
MByteEn <= 4'hf;
MCmd <= `OCP_CMD_WRITE;
end
@(posedge clk)
begin
MAddr <= 0;
MData <= 0;
MByteEn <= 4'h0;
MCmd <= `OCP_CMD_IDLE;
end
end
endtask
initial
begin
/* Set tracing */
$dumpfile(`TRACE_FILE);
$dumpvars(0, tb_micro_uart);
clk = 1;
nrst = 0;
MAddr = 0;
MData = 0;
MByteEn = 0;
MCmd = 0;
#(10*PCLK) nrst = 1;
#(2*PCLK)
/* Read char register */
bus_read(CHARREG);
/* Write char register */
bus_write(CHARREG, "H");
bus_write(CHARREG, "e");
bus_write(CHARREG, "l");
bus_write(CHARREG, "l");
bus_write(CHARREG, "o");
bus_write(CHARREG, "\n");
#500 $finish;
end
/* Instantiate micro UART */
micro_uart uart(
.clk(clk),
.nrst(nrst),
.i_MAddr(MAddr),
.i_MCmd(MCmd),
.i_MData(MData),
.i_MByteEn(MByteEn),
.o_SCmdAccept(SCmdAccept),
.o_SData(SData),
.o_SResp(SResp)
);
endmodule /* tb_micro_uart */
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