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`include "../rtl/uart_rx.v"
`default_nettype none
`timescale 1ns/1ps
module tb_uart_rx;
reg clk;
reg rst_n;
reg rx_in;
wire [7:0] rx_data;
wire rx_rdy;
uart_rx
_uart_rx
(
.clk ( clk ),
.rst_n ( rst_n ),
.rx_in ( rx_in ),
.rx_data ( rx_data ),
.rx_rdy ( rx_rdy )
);
parameter CLK_PERIOD = 10.0;
always #(CLK_PERIOD/2) clk = ~clk;
initial begin
$dumpfile("tb_uart_rx.vcd");
$dumpvars(0, tb_uart_rx);
#1 rst_n<=1'bx;clk<=1'bx;rx_in<=1'bx;
#(CLK_PERIOD) rst_n<=1;
#(CLK_PERIOD*3) rst_n<=0;clk<=0;rx_in<=1;
repeat(5) @(posedge clk);
rst_n<=1;
@(posedge clk);
rx_in<=0;
@(posedge clk);
rx_in<=1;
@(posedge clk);
rx_in<=1;
@(posedge clk);
rx_in<=0;
@(posedge clk);
rx_in<=0;
@(posedge clk);
rx_in<=1;
@(posedge clk);
rx_in<=0;
@(posedge clk);
rx_in<=1;
@(posedge clk);
rx_in<=1;
@(posedge clk);
rx_in<=1;
@(posedge clk);
if (rx_data !== 8'b11010011)
$display("result == %b, expected but %b", rx_data, 8'b11010011);
repeat(5) @(posedge clk);
$finish(2);
end
endmodule
`default_nettype wire
|
module ALU(opcode,funct,in1,in2,result,rw,clk);
input clk;
input [5:0] opcode, funct;
input [31:0] in1, in2;
output [31:0] result; //result of instruction
reg [31:0] result;
output rw;
reg rw; //0 means a read instruction, 1 means a write to register instruction
wire [31:0] sum, diff, product, sum_or;
thirtytwobitadder ADD(in1,in2,carryout,sum,1'b0);
thirtytwobitsubtractor SUBTRACT(in1,in2,carry,diff,1'b0);
AND prod(in1,in2,product);
OR orop(in1,in2,sum_or);
always @(*)
begin
if(opcode==6'b000000)
begin
if(funct==6'b100000) //funct for add
begin
rw=1'b0;
result=sum;
rw=1'b1;
end
if(funct==6'b100010) //funct for subtract
begin
rw=1'b0;
result=diff;
rw=1'b1;
end
if(funct==6'b100100) //funct for multiply
begin
rw=1'b0;
result=product;
rw=1'b1;
end
if(funct==6'b100101)
begin
rw=1'b0;
result=sum_or;
rw=1'b1;
end
end
if(opcode==6'b100011)
begin
rw=1'b0;
result=sum;
rw=1'b1;
end
if(opcode==6'b101011)
begin
rw=1'b0;
result=sum;
end
if(opcode==6'b000100)
begin
rw=1'b0;
if(diff==32'b00000000000000000000000000000000)
begin
result=diff;
end
end
end
endmodule
|
`include "constants.vh"
/*
size:
sb,lb->0
sh,lh->1
sw,lw->2
*/
`define SIZE_REQ_BYTE 0
`define SIZE_REQ_HALF 1
`define SIZE_REQ_WORD 2
module memory(
input clk,
input [`ADDR_LEN-1:0] iraddr1,
input [`ADDR_LEN-1:0] iraddr2,
input [`ADDR_LEN-1:0] draddr1,
input [`ADDR_LEN-1:0] draddr2,
output [`DATA_LEN-1:0] irdata1,
output [`DATA_LEN-1:0] irdata2,
output [`DATA_LEN-1:0] drdata1,
output [`DATA_LEN-1:0] drdata2,
input [1:0] drsize1,
input [1:0] drsize2,
input [`ADDR_LEN-1:0] dwaddr1,
input [`ADDR_LEN-1:0] dwaddr2,
input [`DATA_LEN-1:0] dwdata1,
input [`DATA_LEN-1:0] dwdata2,
input dwe1,
input dwe2,
input [1:0] dwsize1,
input [1:0] dwsize2
);
wire [`DATA_LEN-1:0] drdata1_ram;
wire [`DATA_LEN-1:0] drdata2_ram;
wire [`DATA_LEN-1:0] dwdata1_ram;
wire [`DATA_LEN-1:0] dwdata2_ram;
assign drdata1 =
(drsize1 == `SIZE_REQ_WORD) ? drdata1_ram :
(drsize1 == `SIZE_REQ_HALF) ?
(drdata1_ram >> (`DATA_LEN>>1)*draddr1[1]) :
(drsize1 == `SIZE_REQ_BYTE) ?
(drdata1_ram >> (`DATA_LEN>>2)*draddr1[1:0]) : 32'h0;
assign drdata2 =
(drsize2 == `SIZE_REQ_WORD) ? drdata2_ram :
(drsize2 == `SIZE_REQ_HALF) ?
(drdata2_ram >> (`DATA_LEN>>1)*draddr2[1]) :
(drsize2 == `SIZE_REQ_BYTE) ?
(drdata2_ram >> (`DATA_LEN>>2)*draddr2[1:0]) : 32'h0;
assign dwdata1_ram =
(dwsize1 == `SIZE_REQ_WORD) ? dwdata1 :
(dwsize1 == `SIZE_REQ_HALF) ?
(
(dwaddr1[1] == 1'b0) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:16], dwdata1[15:0]} :
{dwdata1[15:0], mainmemory.mem0.mem[dwaddr1>>2][31:16]}
) :
(dwsize1 == `SIZE_REQ_BYTE) ?
(
(dwaddr1[1:0] == 2'b00) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:8], dwdata1[7:0]} :
(dwaddr1[1:0] == 2'b01) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:16], dwdata1[7:0],
mainmemory.mem0.mem[dwaddr1>>2][7:0]} :
(dwaddr1[1:0] == 2'b10) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:24], dwdata1[7:0],
mainmemory.mem0.mem[dwaddr1>>2][15:0]} :
{dwdata1[7:0], mainmemory.mem0.mem[dwaddr1>>2][23:0]}
) : 32'h0;
assign dwdata2_ram =
(dwsize2 == `SIZE_REQ_WORD) ? dwdata2 :
(dwsize2 == `SIZE_REQ_HALF) ?
(
(dwaddr2[1] == 1'b0) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:16], dwdata2[15:0]} :
{dwdata2[15:0], mainmemory.mem0.mem[dwaddr2>>2][31:16]}
) :
(dwsize2 == `SIZE_REQ_BYTE) ?
(
(dwaddr2[1:0] == 2'b00) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:8], dwdata2[7:0]} :
(dwaddr2[1:0] == 2'b01) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:16], dwdata2[7:0],
mainmemory.mem0.mem[dwaddr2>>2][7:0]} :
(dwaddr2[1:0] == 2'b10) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:24], dwdata2[7:0],
mainmemory.mem0.mem[dwaddr2>>2][15:0]} :
{dwdata2[7:0], mainmemory.mem0.mem[dwaddr2>>2][23:0]}
) : 32'h0;
//512KB 4READ-2WRITE RAM
ram_sync_4r2w #(`ADDR_LEN, `DATA_LEN, 131072)
mainmemory(
.clk(clk),
.raddr1(iraddr1>>2),
.raddr2(iraddr2>>2),
.raddr3(draddr1>>2),
.raddr4(draddr2>>2),
.rdata1(irdata1),
.rdata2(irdata2),
.rdata3(drdata1_ram),
.rdata4(drdata2_ram),
.waddr1(dwaddr1>>2),
.waddr2(dwaddr2>>2),
.wdata1(dwdata1_ram),
.wdata2(dwdata2_ram),
.we1(dwe1),
.we2(dwe2)
);
endmodule // memory
module memory_nolatch(
input clk,
input [`ADDR_LEN-1:0] iraddr1,
input [`ADDR_LEN-1:0] iraddr2,
input [`ADDR_LEN-1:0] draddr1,
input [`ADDR_LEN-1:0] draddr2,
output [`DATA_LEN-1:0] irdata1,
output [`DATA_LEN-1:0] irdata2,
output [`DATA_LEN-1:0] drdata1,
output [`DATA_LEN-1:0] drdata2,
input [1:0] drsize1,
input [1:0] drsize2,
input [`ADDR_LEN-1:0] dwaddr1,
input [`ADDR_LEN-1:0] dwaddr2,
input [`DATA_LEN-1:0] dwdata1,
input [`DATA_LEN-1:0] dwdata2,
input dwe1,
input dwe2,
input [1:0] dwsize1,
input [1:0] dwsize2
);
wire [`DATA_LEN-1:0] drdata1_ram;
wire [`DATA_LEN-1:0] drdata2_ram;
wire [`DATA_LEN-1:0] dwdata1_ram;
wire [`DATA_LEN-1:0] dwdata2_ram;
assign drdata1 =
(drsize1 == `SIZE_REQ_WORD) ? drdata1_ram :
(drsize1 == `SIZE_REQ_HALF) ?
(drdata1_ram >> (`DATA_LEN>>1)*draddr1[1]) :
(drsize1 == `SIZE_REQ_BYTE) ?
(drdata1_ram >> (`DATA_LEN>>2)*draddr1[1:0]) : 32'h0;
assign drdata2 =
(drsize2 == `SIZE_REQ_WORD) ? drdata2_ram :
(drsize2 == `SIZE_REQ_HALF) ?
(drdata2_ram >> (`DATA_LEN>>1)*draddr2[1]) :
(drsize2 == `SIZE_REQ_BYTE) ?
(drdata2_ram >> (`DATA_LEN>>2)*draddr2[1:0]) : 32'h0;
assign dwdata1_ram =
(dwsize1 == `SIZE_REQ_WORD) ? dwdata1 :
(dwsize1 == `SIZE_REQ_HALF) ?
(
(dwaddr1[1] == 1'b0) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:16], dwdata1[15:0]} :
{dwdata1[15:0], mainmemory.mem0.mem[dwaddr1>>2][31:16]}
) :
(dwsize1 == `SIZE_REQ_BYTE) ?
(
(dwaddr1[1:0] == 2'b00) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:8], dwdata1[7:0]} :
(dwaddr1[1:0] == 2'b01) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:16], dwdata1[7:0],
mainmemory.mem0.mem[dwaddr1>>2][7:0]} :
(dwaddr1[1:0] == 2'b10) ?
{mainmemory.mem0.mem[dwaddr1>>2][31:24], dwdata1[7:0],
mainmemory.mem0.mem[dwaddr1>>2][15:0]} :
{dwdata1[7:0], mainmemory.mem0.mem[dwaddr1>>2][23:0]}
) : 32'h0;
assign dwdata2_ram =
(dwsize2 == `SIZE_REQ_WORD) ? dwdata2 :
(dwsize2 == `SIZE_REQ_HALF) ?
(
(dwaddr2[1] == 1'b0) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:16], dwdata2[15:0]} :
{dwdata2[15:0], mainmemory.mem0.mem[dwaddr2>>2][31:16]}
) :
(dwsize2 == `SIZE_REQ_BYTE) ?
(
(dwaddr2[1:0] == 2'b00) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:8], dwdata2[7:0]} :
(dwaddr2[1:0] == 2'b01) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:16], dwdata2[7:0],
mainmemory.mem0.mem[dwaddr2>>2][7:0]} :
(dwaddr2[1:0] == 2'b10) ?
{mainmemory.mem0.mem[dwaddr2>>2][31:24], dwdata2[7:0],
mainmemory.mem0.mem[dwaddr2>>2][15:0]} :
{dwdata2[7:0], mainmemory.mem0.mem[dwaddr2>>2][23:0]}
) : 32'h0;
//512KB 4READ-2WRITE RAM
ram_sync_nolatch_4r2w #(`ADDR_LEN, `DATA_LEN, 131072)
mainmemory(
.clk(clk),
.raddr1(iraddr1>>2),
.raddr2(iraddr2>>2),
.raddr3(draddr1>>2),
.raddr4(draddr2>>2),
.rdata1(irdata1),
.rdata2(irdata2),
.rdata3(drdata1_ram),
.rdata4(drdata2_ram),
.waddr1(dwaddr1>>2),
.waddr2(dwaddr2>>2),
.wdata1(dwdata1_ram),
.wdata2(dwdata2_ram),
.we1(dwe1),
.we2(dwe2)
);
endmodule // memory_nolatch
|
(** * References: Typing Mutable References *)
(** Up to this point, we have considered a variety of _pure_
language features, including functional abstraction, basic types
such as numbers and booleans, and structured types such as records
and variants. These features form the backbone of most
programming languages -- including purely functional languages
such as Haskell and "mostly functional" languages such as ML, as
well as imperative languages such as C and object-oriented
languages such as Java, C[#], and Scala.
However, most practical languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, computation in these languages may assign to mutable
variables (reference cells, arrays, mutable record fields, etc.);
perform input and output to files, displays, or network
connections; make non-local transfers of control via exceptions,
jumps, or continuations; engage in inter-process synchronization
and communication; and so on. In the literature on programming
languages, such "side effects" of computation are collectively
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational effect --
mutable references -- can be added to the calculi we have studied.
The main extension will be dealing explicitly with a _store_ (or
_heap_) and _pointers_ that name store locations. This extension
is fairly straightforward to define; the most interesting part is
the refinement we need to make to the statement of the type
preservation theorem. *)
Require Import Coq.Arith.Arith.
Require Import Coq.omega.Omega.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import Maps.
Require Import Smallstep.
(* ################################################################# *)
(** * Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language Gallina is a
rare exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] to assign a new value to the
cell that it points to (by writing [y:=84]), but we cannot use [y]
directly as an argument to an operation like [+]. Instead, we
must explicitly _dereference_ it, writing [!y] to obtain its
current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a
mutable cell, and the operation of dereferencing a variable to
obtain its current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit. *)
(* ################################################################# *)
(** * Syntax *)
(** In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and reduces to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] reduces
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. *)
(* ----------------------------------------------------------------- *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. Besides the base natural number type and arrow
types, we need to add two more types to deal with
references. First, we need the _unit type_, which we will use as
the result type of an assignment operation. We then add
_reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references to
cells holding values of type [T].
T ::= Nat
| Unit
| T -> T
| Ref T
*)
Inductive ty : Type :=
| TNat : ty
| TUnit : ty
| TArrow : ty -> ty -> ty
| TRef : ty -> ty.
(* ----------------------------------------------------------------- *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* New terms: *)
| tunit : tm
| tref : tm -> tm
| tderef : tm -> tm
| tassign : tm -> tm -> tm
| tloc : nat -> tm.
(** Intuitively:
- [ref t] (formally, [tref t]) allocates a new reference cell
with the value [t] and reduces to the location of the newly
allocated cell;
- [!t] (formally, [tderef t]) reduces to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [tassign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [tloc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. (It
would be easy to do so, since there are no very interesting
interactions between those features and references.) *)
(* ----------------------------------------------------------------- *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T11
--------------------- (T_Deref)
Gamma |- !t1 : T11
Gamma |- t1 : Ref T11
Gamma |- t2 : T11
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ----------------------------------------------------------------- *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall n,
value (tnat n)
| v_unit :
value tunit
| v_loc : forall l,
value (tloc l).
Hint Constructors value.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if beq_id x x' then s else t
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tabs x' T t1 =>
if beq_id x x' then t else tabs x' T (subst x s t1)
| tnat n =>
t
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
t
| tref t1 =>
tref (subst x s t1)
| tderef t1 =>
tderef (subst x s t1)
| tassign t1 t2 =>
tassign (subst x s t1) (subst x s t2)
| tloc _ =>
t
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################################################# *)
(** * Pragmatics *)
(* ================================================================= *)
(** ** Side Effects and Sequencing *)
(** The fact that we've chosen the result of an assignment
expression to be the trivial value [unit] allows a nice
abbreviation for _sequencing_. For example, we can write
r:=succ(!r); !r
as an abbreviation for
(\x:Unit. !r) (r:=succ(!r)).
This has the effect of reducing two expressions in order and
returning the value of the second. Restricting the type of the
first expression to [Unit] helps the typechecker to catch some
silly errors by permitting us to throw away the first value only
if it is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
*)
(** Formally, we introduce sequencing as a _derived form_
[tseq] that expands into an abstraction and an application. *)
Definition tseq t1 t2 :=
tapp (tabs (Id "x") TUnit t2) t1.
(* ================================================================= *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to some variable [r] and the _cell_
in the store that is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after reducing
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
r := 5; r := !s
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
r := !s
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ================================================================= *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
*)
(** Note that, since their argument types are [Unit], the
arguments to the abstractions in the definitions of [incc] and
[decc] are not providing any useful information to the bodies of
these functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose of these
abstractions is to "slow down" the execution of the function
bodies. Since function abstractions are values, the two [let]s are
executed simply by binding these functions to the names [incc] and
[decc], rather than by actually incrementing or decrementing [c].
Later, each caddll to one of these functions results in its body
being executed once and performing the appropriate mutation on
[c]. Such functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(* ================================================================= *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
*)
(** **** Exercise: 1 star (store_draw) *)
(** Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give an (inefficient) implementation of arrays
of numbers, as follows. Write [NatArray] for the type
[Ref (Nat->Nat)].
Recall the [equal] function from the [MoreStlc] chapter:
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
To build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
newarray = \_:Unit. ref (\n:Nat.0)
To look up an element of an array, we simply apply
the function to the desired index.
lookup = \a:NatArray. \n:Nat. (!a) n
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], while on all other indices it passes the
lookup to the function that was previously stored in the reference.
update = \a:NatArray. \m:Nat. \v:Nat.
let oldf = !a in
a := (\n:Nat. if equal m n then v else oldf n);
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars, recommended (compact_update) *)
(** If we defined [update] more compactly like this
update = \a:NatArray. \m:Nat. \v:Nat.
a := (\n:Nat. if equal m n then v else (!a) n)
would it behave the same? *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Null References *)
(** There is one final significant difference between our
references and C-style mutable variables: in C-like languages,
variables holding pointers into the heap may sometimes have the
value [NULL]. Dereferencing such a "null pointer" is an error,
and results either in a clean exception (Java and C[#]) or in
arbitrary and possibly insecure behavior (C and relatives like
C++). Null pointers cause significant trouble in C-like
languages: the fact that any pointer might be null means that any
dereference operation in the program can potentially fail.
Even in ML-like languages, there are occasionally situations where
we may or may not have a valid pointer in our hands. Fortunately,
there is no need to extend the basic mechanisms of references to
represent such situations: the sum types introduced in the
[MoreStlc] chapter already give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter. Define [Option T] to be an
abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ================================================================= *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, automatically identifying and reusing cells that can
no longer be reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. One reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Nat] and the
other with type [Ref Bool]. *)
(** **** Exercise: 1 star (type_safety_violation) *)
(** Show how this can lead to a violation of type safety. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Operational Semantics *)
(* ================================================================= *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that reduci a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming-language implementations is
essentially just a big array of bytes. The run-time system keeps
track of which parts of this array are currently in use; when we
need to allocate a new reference cell, we allocate a large enough
segment from the free region of the store (4 bytes for integer
cells, 8 bytes for cells storing [Float]s, etc.), record somewhere
that it is being used, and return the index (typically, a 32- or
64-bit integer) of the start of the newly allocated region. These
indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is convenient to use
numbers.) We use the word _location_ instead of _reference_ or
_pointer_ to emphasize this abstract quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type-safety violations. *)
(* ================================================================= *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
IMP, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in IMP, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we didn't use this representation
before is that, in IMP, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [tref t1], which puts the value of [t1]
in a new reference cell and reduces to the location of the newly
created reference cell. When reducing such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
that we don't will require a bit of work.) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st tunit.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** As might be expected, we will also need some technical
lemmas about [replace]; they are straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x nil = nil.
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
- (* st = [] *)
inversion Hlen.
- (* st = t' :: st' *)
destruct l; simpl...
apply IHst'. simpl in Hlen. omega.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
- (* l1 = 0 *)
destruct st.
+ (* st = [] *) rewrite replace_nil...
+ (* st = _ :: _ *) destruct l2... contradict Hneq...
- (* l1 = S l1' *)
destruct st as [|t2 st2].
+ (* st = [] *) destruct l2...
+ (* st = t2 :: st2 *)
destruct l2...
simpl; apply IHl1'...
Qed.
(* ================================================================= *)
(** ** Reduction *)
(** Next, we need to extend the operational semantics to take
stores into account. Since the result of reducing an expression
will in general depend on the contents of the store in which it is
reduced, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the reduction of a
term can cause side effects on the store, and these may affect the
reduction of other terms in the future, the reduction rules need
to return a new store. Thus, the shape of the single-step
reduction relation needs to change from [t ==> t'] to [t / st ==> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing reduction rules with stores:
value v2
-------------------------------------- (ST_AppAbs)
(\x:T.t12) v2 / st ==> [x:=v2]t12 / st
t1 / st ==> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st ==> t1' t2 / st'
value v1 t2 / st ==> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st ==> v1 t2' / st'
Note that the first rule here returns the store unchanged, since
function application, in itself, has no side effects. The other
two rules simply propagate side effects from premise to
conclusion.
Now, the result of reducing a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values. It is crucial to note that making this
extension to the syntax of terms does not mean that we intend
_programmers_ to write terms involving explicit, concrete locations:
such terms will arise only as intermediate results during reduction.
This may seem odd, but it follows naturally from our design decision
to represent the result of every reduction step by a modified _term_.
If we had chosen a more "machine-like" model, e.g., with an explicit
stack to contain values of bound identifiers, then the idea of adding
locations to the set of allowed values might seem more obvious.
In terms of this expanded syntax, we can state reduction rules
for the new constructs that manipulate locations and the store.
First, to reduce a dereferencing expression [!t1], we must first
reduce [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------- (ST_Deref)
!t1 / st ==> !t1' / st'
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to dereference a
location that is larger than the size [|st|] of the currently
allocated store; the reduction rules simply get stuck in this
case. The type-safety properties established below assure us
that well-typed terms will never misbehave in this way.)
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st ==> lookup l st / st
Next, to reduce an assignment expression [t1:=t2], we must first
reduce [t1] until it becomes a value (a location), and then
reduce [t2] until it becomes a value (of any sort):
t1 / st ==> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st ==> t1' := t2 / st'
t2 / st ==> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st ==> v1 := t2' / st'
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v2], which we execute by updating the store to make
location [l] contain [v2]:
l < |st|
------------------------------------- (ST_Assign)
loc l := v2 / st ==> unit / [l:=v2]st
The notation [[l:=v2]st] means "the store that maps [l] to [v2]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this reduction step is just [unit];
the interesting result is the updated store.
Finally, to reduct an expression of the form [ref t1], we first
reduce [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------------- (ST_Ref)
ref t1 / st ==> ref t1' / st'
Then, to reduce the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v1].
-------------------------------- (ST_RefValue)
ref v1 / st ==> loc |st| / st,v1
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v1] means [st ++ v1::nil] -- i.e., to add
a new reference cell to the store, we append it to the end.)
Note that these reduction rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as reduction proceeds. This does not affect the
correctness of the results of reduction (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
reduction), but it means that a naive implementation of our
evaluator might run out of memory where a more sophisticated
evaluator would be able to continue by reusing locations whose
contents have become garbage.
Here are the rules again, formally: *)
Reserved Notation "t1 '/' st1 '==>' t2 '/' st2"
(at level 40, st1 at level 39, t2 at level 39).
Import ListNotations.
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T t12 v2 st,
value v2 ->
tapp (tabs x T t12) v2 / st ==> [x:=v2]t12 / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tapp t1 t2 / st ==> tapp t1' t2 / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tapp v1 t2 / st ==> tapp v1 t2'/ st'
| ST_SuccNat : forall n st,
tsucc (tnat n) / st ==> tnat (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tsucc t1 / st ==> tsucc t1' / st'
| ST_PredNat : forall n st,
tpred (tnat n) / st ==> tnat (pred n) / st
| ST_Pred : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tpred t1 / st ==> tpred t1' / st'
| ST_MultNats : forall n1 n2 st,
tmult (tnat n1) (tnat n2) / st ==> tnat (mult n1 n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st ==> t1' / st' ->
tmult t1 t2 / st ==> tmult t1' t2 / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tmult v1 t2 / st ==> tmult v1 t2' / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st ==> t1' / st' ->
tif0 t1 t2 t3 / st ==> tif0 t1' t2 t3 / st'
| ST_If0_Zero : forall t2 t3 st,
tif0 (tnat 0) t2 t3 / st ==> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
tif0 (tnat (S n)) t2 t3 / st ==> t3 / st
| ST_RefValue : forall v1 st,
value v1 ->
tref v1 / st ==> tloc (length st) / (st ++ v1::nil)
| ST_Ref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tref t1 / st ==> tref t1' / st'
| ST_DerefLoc : forall st l,
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
| ST_Deref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tderef t1 / st ==> tderef t1' / st'
| ST_Assign : forall v2 l st,
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tassign t1 t2 / st ==> tassign t1' t2 / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tassign v1 t2 / st ==> tassign v1 t2' / st'
where "t1 '/' st1 '==>' t2 '/' st2" := (step (t1,st1) (t2,st2)).
(** One slightly ugly point should be noted here: In the [ST_RefValue]
rule, we extend the state by writing [st ++ v1::nil] rather than
the more natural [st ++ [v1]]. The reason for this is that the
notation we've defined for substitution uses square brackets,
which clash with the standard library's notation for lists. *)
Hint Constructors step.
Definition multistep := (multi step).
Notation "t1 '/' st '==>*' t2 '/' st'" :=
(multistep (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(* ################################################################# *)
(** * Typing *)
(** The contexts assigning types to free variables are exactly the
same as for the STLC: partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ================================================================= *)
(** ** Store typings *)
(** Having extended our syntax and reduction rules to accommodate
references, our last job is to write down typing rules for the new
constructs (and, of course, to check that these rules are sound!).
Naturally, the key question is, "What is the type of a location?"
First of all, notice that this question doesn't arise when
typechecking terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of reduction; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of a reduction
sequence, e.g., trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we reduce a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we reduce the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we reduce the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
and all the rest of the typing rules in the system are extended
similarly with stores. (The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.)
However, this rule will not quite do. For one thing, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear. Worse yet, the
proposed typing rule for locations may not allow us to derive
anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
*)
(** **** Exercise: 2 stars (cyclic_store) *)
(** Can you find a term whose reduction will create this particular
cyclic store? *)
(** [] *)
(** These problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ -- a finite function
mapping locations to types.
As with the other type systems we've seen, this conservative typing
restriction on allowed updates means that we will rule out as
ill-typed some programs that could reduce perfectly well without
getting stuck.
Just as we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
values that we expect to be stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_Tlookup] function retrieves the type at a particular
index. *)
Definition store_Tlookup (n:nat) (ST:store_ty) :=
nth n ST TUnit.
(** Suppose we are given a store typing [ST] describing the store
[st] in which some term [t] will be reduced. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we can immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
That is, as long as [l] is a valid location, we can compute the
type of [l] just by looking it up in [ST]. Typing is again a
four-place relation, but it is parameterized on a store _typing_
rather than a concrete store. The rest of the typing rules are
analogously augmented with store typings. *)
(* ================================================================= *)
(** ** The Typing Relation *)
(** We can now formalize the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T11
------------------------- (T_Deref)
Gamma; ST |- !t1 : T11
Gamma; ST |- t1 : Ref T11
Gamma; ST |- t2 : T11
----------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
*)
Reserved Notation "Gamma ';' ST '|-' t '\in' T" (at level 40).
Inductive has_type : context -> store_ty -> tm -> ty -> Prop :=
| T_Var : forall Gamma ST x T,
Gamma x = Some T ->
Gamma; ST |- (tvar x) \in T
| T_Abs : forall Gamma ST x T11 T12 t12,
(update Gamma x T11); ST |- t12 \in T12 ->
Gamma; ST |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma ST t1 t2,
Gamma; ST |- t1 \in (TArrow T1 T2) ->
Gamma; ST |- t2 \in T1 ->
Gamma; ST |- (tapp t1 t2) \in T2
| T_Nat : forall Gamma ST n,
Gamma; ST |- (tnat n) \in TNat
| T_Succ : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tsucc t1) \in TNat
| T_Pred : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tpred t1) \in TNat
| T_Mult : forall Gamma ST t1 t2,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in TNat ->
Gamma; ST |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma ST t1 t2 t3 T,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in T ->
Gamma; ST |- t3 \in T ->
Gamma; ST |- (tif0 t1 t2 t3) \in T
| T_Unit : forall Gamma ST,
Gamma; ST |- tunit \in TUnit
| T_Loc : forall Gamma ST l,
l < length ST ->
Gamma; ST |- (tloc l) \in (TRef (store_Tlookup l ST))
| T_Ref : forall Gamma ST t1 T1,
Gamma; ST |- t1 \in T1 ->
Gamma; ST |- (tref t1) \in (TRef T1)
| T_Deref : forall Gamma ST t1 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- (tderef t1) \in T11
| T_Assign : forall Gamma ST t1 t2 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- t2 \in T11 ->
Gamma; ST |- (tassign t1 t2) \in TUnit
where "Gamma ';' ST '|-' t '\in' T" := (has_type Gamma ST t T).
Hint Constructors has_type.
(** Of course, these typing rules will accurately predict the results
of reduction only if the concrete store used during reduction
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the basic STLC: the substitution lemma
promises that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will reduce to a final result of type [T] if it yields
any result at all. We will see below how to formalize an
analogous intuition for stores and store typings.
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Concrete locations arise only in
terms that are the intermediate results of reduction; they are
not in the language that programmers write. Thus, we can simply
typecheck the programmer's terms with respect to the _empty_ store
typing. As reduction proceeds and new locations are created, we
will always be able to see how to extend the store typing by
looking at the type of the initial values being placed in newly
allocated cells; this intuition is formalized in the statement of
the type preservation theorem below. *)
(* ################################################################# *)
(** * Properties *)
(** Our final task is to check that standard type safety
properties continue to hold for the STLC with references. The
progress theorem ("well-typed terms are not stuck") can be stated
and proved almost as for the STLC; we just need to add a few
straightforward cases to the proof to deal with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ================================================================= *)
(** ** Well-Typed Stores *)
(** Since we have extended both the reduction relation (with
initial and final stores) and the typing relation (with a store
typing), we need to change the statement of preservation to
include these parameters. But clearly we cannot just add stores
and store typings without saying anything about how they are
related -- i.e., this is wrong: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
empty; ST |- t' \in T.
Abort.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then reduce with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
empty; ST |- (store_lookup l st) \in (store_Tlookup l ST)).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation. This allows us to type circular
stores like the one we saw above. *)
(** **** Exercise: 2 stars (store_not_unique) *)
(** Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
(* FILL IN HERE *)
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Theorem preservation_wrong2 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
empty; ST |- t' \in T.
Abort.
(** This statement is fine for all of the reduction rules except
the allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st'] includes
a binding for a fresh location [l], then [l] cannot be in the
domain of [ST], and it will not be the case that [t'] (which
definitely mentions [l]) is typable under [ST]. *)
(* ================================================================= *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during reduction,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_Tlookup l ST' = store_Tlookup l ST.
Proof with auto.
intros l ST ST' Hlen H.
generalize dependent ST'. generalize dependent l.
induction ST as [|a ST2]; intros l Hlen ST' HST'.
- (* nil *) inversion Hlen.
- (* cons *) unfold store_Tlookup in *.
destruct ST'.
+ (* ST' = nil *) inversion HST'.
+ (* ST' = a' :: ST'2 *)
inversion HST'; subst.
destruct l as [|l'].
* (* l = 0 *) auto.
* (* l = S l' *) simpl. apply IHST2...
simpl in Hlen; omega.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
inversion Hlen.
simpl in *.
destruct l; try omega.
apply lt_n_S. apply IHextends. omega.
Qed.
(** Finally, [ST ++ T] extends [ST], and [extends] is reflexive. *)
Lemma extends_app : forall ST T,
extends (ST ++ T) ST.
Proof with auto.
induction ST; intros T...
simpl...
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ================================================================= *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else exactly [ST ++ T1::nil], where
[T1] is the type of the value [v1] in the extended store [st ++
v1::nil], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of reduction steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ================================================================= *)
(** ** Substitution Lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_succ : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tsucc t1)
| afi_pred : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tpred t1)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_ref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tref t1)
| afi_deref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tderef t1)
| afi_assign1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tassign t1 t2)
| afi_assign2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tassign t1 t2).
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma ST,
appears_free_in x t ->
Gamma; ST |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros. generalize dependent Gamma. generalize dependent T.
induction H;
intros; (try solve [ inversion H0; subst; eauto ]).
- (* afi_abs *)
inversion H1; subst.
apply IHappears_free_in in H8.
rewrite update_neq in H8; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' ST t T,
Gamma; ST |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma'; ST |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros...
- (* T_Var *)
apply T_Var. symmetry. rewrite <- H...
- (* T_Abs *)
apply T_Abs. apply IHhas_type; intros.
unfold update, t_update.
destruct (beq_idP x x0)...
- (* T_App *)
eapply T_App.
apply IHhas_type1...
apply IHhas_type2...
- (* T_Mult *)
eapply T_Mult.
apply IHhas_type1...
apply IHhas_type2...
- (* T_If0 *)
eapply T_If0.
apply IHhas_type1...
apply IHhas_type2...
apply IHhas_type3...
- (* T_Assign *)
eapply T_Assign.
apply IHhas_type1...
apply IHhas_type2...
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x s S t T,
empty; ST |- s \in S ->
(update Gamma x S); ST |- t \in T ->
Gamma; ST |- ([x:=s]t) \in T.
Proof with eauto.
intros Gamma ST x s S t T Hs Ht.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
inversion H; subst; simpl...
- (* tvar *)
rename i into y.
destruct (beq_idP x y).
+ (* x = y *)
subst.
rewrite update_eq in H3.
inversion H3; subst.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ _ _ _ Hcontra Hs)
as [T' HT'].
inversion HT'.
+ (* x <> y *)
apply T_Var.
rewrite update_neq in H3...
- (* tabs *) subst.
rename i into y.
destruct (beq_idP x y).
+ (* x = y *)
subst.
apply T_Abs. eapply context_invariance...
intros. rewrite update_shadow. reflexivity.
+ (* x <> x0 *)
apply T_Abs. apply IHt.
eapply context_invariance...
intros. unfold update, t_update.
destruct (beq_idP y x0)...
subst.
rewrite false_beq_id...
Qed.
(* ================================================================= *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
empty; ST |- t \in (store_Tlookup l ST) ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
destruct (beq_nat l' l) eqn: Heqll'.
- (* l' = l *)
apply beq_nat_true in Heqll'; subst.
rewrite lookup_replace_eq...
- (* l' <> l *)
apply beq_nat_false in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ================================================================= *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
Gamma; ST |- t \in T ->
Gamma; ST' |- t \in T.
Proof with eauto.
intros. induction H0; eauto.
- (* T_Loc *)
erewrite <- extends_lookup...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well typed with respect to a store typing, then the store extended
with a new term [t] will still be well typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_app : forall ST st t1 T1,
store_well_typed ST st ->
empty; ST |- t1 \in T1 ->
store_well_typed (ST ++ T1::nil) (st ++ t1::nil).
Proof with auto.
intros.
unfold store_well_typed in *.
inversion H as [Hlen Hmatch]; clear H.
rewrite app_length, plus_comm. simpl.
rewrite app_length, plus_comm. simpl.
split...
- (* types match. *)
intros l Hl.
unfold store_lookup, store_Tlookup.
apply le_lt_eq_dec in Hl; inversion Hl as [Hlt | Heq].
+ (* l < length st *)
apply lt_S_n in Hlt.
rewrite !app_nth1...
* apply store_weakening with ST. apply extends_app.
apply Hmatch...
* rewrite Hlen...
+ (* l = length st *)
inversion Heq.
rewrite app_nth2; try omega.
rewrite <- Hlen.
rewrite minus_diag. simpl.
apply store_weakening with ST...
{ apply extends_app. }
rewrite app_nth2; try omega.
rewrite minus_diag. simpl. trivial.
Qed.
(* ================================================================= *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
(** Begin with one technical lemma: *)
Lemma nth_eq_last : forall A (l:list A) x d,
nth (length l) (l ++ x::nil) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** And here, at last, is the preservation theorem and proof: *)
Theorem preservation : forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
Proof with eauto using store_weakening, extends_refl.
remember (@empty ty) as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
induction Ht; intros t' HST Hstep;
subst; try solve_by_invert; inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
(* T_App *)
- (* ST_AppAbs *) exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
- (* ST_App1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_App2 *)
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_Succ *)
+ (* ST_Succ *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_Pred *)
+ (* ST_Pred *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Mult *)
- (* ST_Mult1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_Mult2 *)
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_If0 *)
+ (* ST_If0_1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... split...
(* T_Ref *)
- (* ST_RefValue *)
exists (ST ++ T1::nil).
inversion HST; subst.
split.
apply extends_app.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (ST ++ T1::nil))).
apply T_Loc.
rewrite <- H. rewrite app_length, plus_comm. simpl. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_last.
reflexivity.
apply store_well_typed_app; assumption.
- (* ST_Ref *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Deref *)
- (* ST_DerefLoc *)
exists ST. split; try split...
inversion HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst...
- (* ST_Deref *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Assign *)
- (* ST_Assign *)
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
- (* ST_Assign1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_Assign2 *)
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
(** **** Exercise: 3 stars (preservation_informal) *)
(** Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
(* FILL IN HERE *)
[] *)
(* ================================================================= *)
(** ** Progress *)
(** As we've said, progress for this system is pretty easy to prove;
the proof is very similar to the proof of progress for the STLC,
with a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
empty; ST |- t \in T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst; try solve_by_invert...
- (* T_App *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve_by_invert.
destruct IHHt2 as [Ht2p | Ht2p]...
* (* t2 steps *)
inversion Ht2p as [t2' [st' Hstep]].
exists (tapp (tabs x T t) t2'). exists st'...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tapp t1' t2). exists st'...
- (* T_Succ *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [ inversion Ht ].
* (* t1 is a tnat *)
exists (tnat (S n)). exists st...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tsucc t1'). exists st'...
- (* T_Pred *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht ].
* (* t1 is a tnat *)
exists (tnat (pred n)). exists st...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tpred t1'). exists st'...
- (* T_Mult *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
* (* t2 is a value *)
inversion Ht2p; subst; try solve [inversion Ht2].
exists (tnat (mult n n0)). exists st...
* (* t2 steps *)
inversion Ht2p as [t2' [st' Hstep]].
exists (tmult (tnat n) t2'). exists st'...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tmult t1' t2). exists st'...
- (* T_If0 *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
* (* n = 0 *) exists t2. exists st...
* (* n = S n' *) exists t3. exists st...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tif0 t1' t2 t3). exists st'...
- (* T_Ref *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tref t1'). exists st'...
- (* T_Deref *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve_by_invert.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tderef t1'). exists st'...
- (* T_Assign *)
right. destruct IHHt1 as [Ht1p|Ht1p]...
+ (* t1 is a value *)
destruct IHHt2 as [Ht2p|Ht2p]...
* (* t2 is a value *)
inversion Ht1p; subst; try solve_by_invert.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H5...
* (* t2 steps *)
inversion Ht2p as [t2' [st' Hstep]].
exists (tassign t1 t2'). exists st'...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tassign t1' t2). exists st'...
Qed.
(* ################################################################# *)
(** * References and Nontermination *)
(** An important fact about the STLC (proved in chapter [Norm]) is
that it is is _normalizing_ -- that is, every well-typed term can
be reduced to a value in a finite number of steps.
What about STLC + references? Surprisingly, adding references
causes us to lose the normalization property: there exist
well-typed terms in the STLC + references which can continue to
reduce forever, without ever reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function [\x:Unit.(!r) unit] -- that is, the function which ignores
its argument and calls the function stored in [r] on the argument
[unit]; but of course, that function is itself! To start the
divergent loop, we execute the function stored in the cell by
evaluating [(!r) unit].
Here is the divergent term in Coq: *)
Module ExampleVariables.
Definition x := Id "x".
Definition y := Id "y".
Definition r := Id "r".
Definition s := Id "s".
End ExampleVariables.
Module RefsAndNontermination.
Import ExampleVariables.
Definition loop_fun :=
tabs x TUnit (tapp (tderef (tvar r)) tunit).
Definition loop :=
tapp
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit)))
(tref (tabs x TUnit tunit)).
(** This term is well typed: *)
Lemma loop_typeable : exists T, empty; nil |- loop \in T.
Proof with eauto.
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
unfold update, t_update. simpl. reflexivity. auto.
eapply T_Assign.
eapply T_Var. unfold update, t_update. simpl. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[==>+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [==>*]), except
that it is not reflexive: [t ==>+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition multistep1 := (step_closure step).
Notation "t1 '/' st '==>+' t2 '/' st'" :=
(multistep1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store
[[r:=(loc 0)]loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[multi_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply multi_refl]).
(** Next, we use [reduce] to show that [loop] steps to
[!(loc 0) unit], starting from the empty store. *)
Lemma loop_steps_to_loop_fun :
loop / nil ==>*
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof.
unfold loop.
reduce.
Qed.
(** Finally, we show that the latter expression reduces in
two steps to itself! *)
Lemma loop_fun_step_self :
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil ==>+
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
(** **** Exercise: 4 stars (factorial_ref) *)
(** Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just uncomment the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition factorial : tm
(* REPLACE THIS LINE WITH ":= _your_definition_ ." *). Admitted.
Lemma factorial_type : empty; nil |- factorial \in (TArrow TNat TNat).
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
(*
Lemma factorial_4 : exists st,
tapp factorial (tnat 4) / nil ==>* tnat 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
*)
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, optional (garabage_collector) *)
(** Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(** [] *)
End RefsAndNontermination.
End STLCRef.
(** $Date: 2016-10-11 11:45:39 -0400 (Tue, 11 Oct 2016) $ *)
|
// megafunction wizard: %LPM_FF%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_ff
// ============================================================
// File Name: lpm_ff_v1.v
// Megafunction Name(s):
// lpm_ff
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 8.1 Build 163 10/28/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module lpm_ff_v1 (
clock,
data,
q);
input clock;
input [63:0] data;
output [63:0] q;
wire [63:0] sub_wire0;
wire [63:0] q = sub_wire0[63:0];
lpm_ff lpm_ff_component (
.clock (clock),
.data (data),
.q (sub_wire0)
// synopsys translate_off
,
.aclr (),
.aload (),
.aset (),
.enable (),
.sclr (),
.sload (),
.sset ()
// synopsys translate_on
);
defparam
lpm_ff_component.lpm_fftype = "DFF",
lpm_ff_component.lpm_type = "LPM_FF",
lpm_ff_component.lpm_width = 64;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACLR NUMERIC "0"
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
// Retrieval info: PRIVATE: ASET NUMERIC "0"
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
// Retrieval info: PRIVATE: DFF NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
// Retrieval info: PRIVATE: SSET NUMERIC "0"
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "64"
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "64"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 64 0 INPUT NODEFVAL data[63..0]
// Retrieval info: USED_PORT: q 0 0 64 0 OUTPUT NODEFVAL q[63..0]
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 64 0 @q 0 0 64 0
// Retrieval info: CONNECT: @data 0 0 64 0 data 0 0 64 0
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL lpm_ff_v1_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:27:32 06/14/2012
// Design Name:
// Module Name: reorder_queue
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Reorders downstream TLPs to output in increasing tag sequence. Input packets
// are stored in RAM and then read out when all previous sequence numbers have
// arrived and been read out. This module also provides the next available tag
// for the TX engine to use when sending memory request TLPs.
//
// Dependencies:
// reorder_queue_input.v
// reorder_queue_output.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "trellis.vh"
`timescale 1ns / 1ps
module reorder_queue
#(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_COUNT_WIDTH = clog2(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH,
parameter C_DW_PER_TAG = C_MAX_READ_REQ_BYTES/4,
parameter C_TAG_DW_COUNT_WIDTH = clog2s(C_DW_PER_TAG+1),
parameter C_DATA_ADDR_STRIDE_WIDTH = clog2s(C_DW_PER_TAG/C_PCI_DATA_WORD), // div by C_PCI_DATA_WORD b/c there are C_PCI_DATA_WORD RAMs
parameter C_DATA_ADDR_WIDTH = C_TAG_WIDTH + C_DATA_ADDR_STRIDE_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
input [5:0] INT_TAG, // Internal tag to exchange with external
input INT_TAG_VALID, // High to signal tag exchange
output [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
output EXT_TAG_VALID, // High to signal external tag is valid
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
`include "functions.vh"
wire [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] wWrDataAddr;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
wire [C_PCI_DATA_WORD-1:0] wWrDataEn;
wire [C_TAG_WIDTH-1:0] wWrPktTag;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wWrPktWords;
wire wWrPktWordsLTE1;
wire wWrPktWordsLTE2;
wire wWrPktValid;
wire wWrPktDone;
wire wWrPktErr;
wire [C_DATA_ADDR_WIDTH-1:0] wRdDataAddr;
wire [C_PCI_DATA_WIDTH-1:0] wRdData;
wire [C_TAG_WIDTH-1:0] wRdPktTag;
wire [(1+1+1+1+C_TAG_DW_COUNT_WIDTH)-1:0] wRdPktInfo;
wire [5:0] wRdTagMap;
wire [C_NUM_TAGS-1:0] wFinish;
wire [C_NUM_TAGS-1:0] wClear;
reg [C_TAG_WIDTH-1:0] rPos=0;
reg rValid=0;
reg [C_NUM_TAGS-1:0] rFinished=0;
reg [C_NUM_TAGS-1:0] rUse=0;
reg [C_NUM_TAGS-1:0] rUsing=0;
assign EXT_TAG = rPos;
assign EXT_TAG_VALID = rValid;
// Move through tag/slot/bucket space.
always @ (posedge CLK) begin
if (RST) begin
rPos <= #1 0;
rUse <= #1 0;
rValid <= #1 0;
end
else begin
if (INT_TAG_VALID & EXT_TAG_VALID) begin
rPos <= #1 rPos + 1'd1;
rUse <= #1 1<<rPos;
rValid <= #1 !rUsing[rPos + 1'd1];
end
else begin
rUse <= #1 0;
rValid <= #1 !rUsing[rPos];
end
end
end
// Update tag/slot/bucket status.
always @ (posedge CLK) begin
if (RST) begin
rUsing <= #1 0;
rFinished <= #1 0;
end
else begin
rUsing <= #1 (rUsing | rUse) & ~wClear;
rFinished <= #1 (rFinished | wFinish) & ~wClear;
end
end
genvar r;
generate
for (r = 0; r < C_PCI_DATA_WORD; r = r + 1) begin : rams
// RAMs for packet reordering.
(* RAM_STYLE="BLOCK" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(32),
.C_RAM_DEPTH(C_NUM_TAGS*C_DW_PER_TAG/C_PCI_DATA_WORD)
)
ram
(
.CLK(CLK),
.ADDRA(wWrDataAddr[C_DATA_ADDR_WIDTH*r +:C_DATA_ADDR_WIDTH]),
.WEA(wWrDataEn[r]),
.DINA(wWrData[32*r +:32]),
.ADDRB(wRdDataAddr),
.DOUTB(wRdData[32*r +:32])
);
end
endgenerate
// RAM for bucket done, err, final DW count
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(1 + 1 + 1 + 1 + C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
pktRam
(
.CLK(CLK),
.ADDRA(wWrPktTag),
.WEA((wWrPktDone | wWrPktErr) & wWrPktValid),
.DINA({wWrPktDone, wWrPktErr, wWrPktWordsLTE2, wWrPktWordsLTE1, wWrPktWords}),
.ADDRB(wRdPktTag),
.DOUTB(wRdPktInfo)
);
// RAM for tag map
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(6),
.C_RAM_DEPTH(C_NUM_TAGS))
mapRam
(
.CLK(CLK),
.ADDRA(rPos),
.WEA(INT_TAG_VALID & EXT_TAG_VALID),
.DINA(INT_TAG),
.ADDRB(wRdPktTag),
.DOUTB(wRdTagMap)
);
// Demux input data into the correct slot/bucket.
reorder_queue_input
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
.C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
)
data_input
(
.CLK(CLK),
.RST(RST),
.VALID(VALID),
.DATA_START_FLAG (DATA_START_FLAG),
.DATA_START_OFFSET (DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (DATA_END_FLAG),
.DATA_END_OFFSET (DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (DATA),
.DATA_EN (DATA_EN),
.DONE(DONE),
.ERR(ERR),
.TAG(TAG),
.TAG_FINISH(wFinish),
.TAG_CLEAR(wClear),
.STORED_DATA_ADDR(wWrDataAddr),
.STORED_DATA(wWrData),
.STORED_DATA_EN(wWrDataEn),
.PKT_VALID(wWrPktValid),
.PKT_TAG(wWrPktTag),
.PKT_WORDS(wWrPktWords),
.PKT_WORDS_LTE1(wWrPktWordsLTE1),
.PKT_WORDS_LTE2(wWrPktWordsLTE2),
.PKT_DONE(wWrPktDone),
.PKT_ERR(wWrPktErr)
);
// Output packets in increasing tag order.
reorder_queue_output
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
.C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
)
data_output
(
.CLK(CLK),
.RST(RST),
.DATA_ADDR(wRdDataAddr),
.DATA(wRdData),
.TAG_FINISHED(rFinished),
.TAG_CLEAR(wClear),
.TAG(wRdPktTag),
.TAG_MAPPED(wRdTagMap),
.PKT_WORDS(wRdPktInfo[0 +:C_TAG_DW_COUNT_WIDTH]),
.PKT_WORDS_LTE1(wRdPktInfo[C_TAG_DW_COUNT_WIDTH]),
.PKT_WORDS_LTE2(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+1]),
.PKT_ERR(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+2]),
.PKT_DONE(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+3]),
.ENG_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N
);
// Module ports
output Y ;
input A ;
input B ;
input C_N;
// Local signals
wire nor0_out ;
wire and0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y, C_N, nor0_out );
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_V |
// ======================================================================
// Lticker.v generated from TopDesign.cysch
// 11/07/2014 at 22:00
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// Component: WS2812driver
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "..\WS2812driver"
`include "..\WS2812driver\WS2812driver.v"
`else
`define CY_BLK_DIR "C:\Users\Tsubasa Maruyama\Documents\PSoC Creator\Lticker\Lticker.cydsn\WS2812driver"
`include "C:\Users\Tsubasa Maruyama\Documents\PSoC Creator\Lticker\Lticker.cydsn\WS2812driver\WS2812driver.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: B_Counter_v2_40
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40\B_Counter_v2_40.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\B_Counter_v2_40\B_Counter_v2_40.v"
`endif
// Counter_v2_40(CaptureMode=0, CaptureModeSoftware=0, ClockMode=3, CompareMode=1, CompareModeSoftware=0, CompareStatusEdgeSense=true, CompareValue=128, CONTROL3=0, ControlRegRemoved=1, CtlModeReplacementString=SyncCtl, CyGetRegReplacementString=CY_GET_REG8, CySetRegReplacementString=CY_SET_REG8, EnableMode=1, FF16=false, FF8=false, FixedFunction=false, FixedFunctionUsed=0, InitCounterValue=249, InterruptOnCapture=false, InterruptOnCompare=false, InterruptOnOverUnderFlow=true, InterruptOnTC=false, Period=249, RegDefReplacementString=reg8, RegSizeReplacementString=uint8, ReloadOnCapture=false, ReloadOnCompare=false, ReloadOnOverUnder=false, ReloadOnReset=true, Resolution=8, RstStatusReplacementString=sSTSReg_rstSts, RunMode=1, UDB16=false, UDB24=false, UDB32=false, UDB8=true, UDBControlReg=false, UseInterrupt=true, VerilogSectionReplacementString=sC8, CY_COMPONENT_NAME=Counter_v2_40, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=Counter_reset_gen, CY_INSTANCE_SHORT_NAME=Counter_reset_gen, CY_MAJOR_VERSION=2, CY_MINOR_VERSION=40, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=Counter_reset_gen, )
module Counter_v2_40_0 (
clock,
comp,
tc,
reset,
interrupt,
enable,
capture,
upCnt,
downCnt,
up_ndown,
count);
input clock;
output comp;
output tc;
input reset;
output interrupt;
input enable;
input capture;
input upCnt;
input downCnt;
input up_ndown;
input count;
parameter CaptureMode = 0;
parameter ClockMode = 3;
parameter CompareMode = 1;
parameter CompareStatusEdgeSense = 1;
parameter EnableMode = 1;
parameter ReloadOnCapture = 0;
parameter ReloadOnCompare = 0;
parameter ReloadOnOverUnder = 0;
parameter ReloadOnReset = 1;
parameter Resolution = 8;
parameter RunMode = 1;
parameter UseInterrupt = 1;
wire Net_95;
wire Net_89;
// VirtualMux_1 (cy_virtualmux_v1_0)
assign Net_89 = Net_95;
ZeroTerminal ZeroTerminal_2 (
.z(Net_95));
B_Counter_v2_40 CounterUDB (
.reset(reset),
.tc_out(tc),
.cmp_out(comp),
.clock(clock),
.irq_out(interrupt),
.up_ndown(Net_89),
.upcnt(upCnt),
.dwncnt(downCnt),
.enable(enable),
.capture(capture),
.count(count));
defparam CounterUDB.CaptureMode = 0;
defparam CounterUDB.ClockMode = 3;
defparam CounterUDB.CompareMode = 1;
defparam CounterUDB.CompareStatusEdgeSense = 1;
defparam CounterUDB.EnableMode = 1;
defparam CounterUDB.ReloadOnCapture = 0;
defparam CounterUDB.ReloadOnCompare = 0;
defparam CounterUDB.ReloadOnOverUnder = 0;
defparam CounterUDB.ReloadOnReset = 1;
defparam CounterUDB.Resolution = 8;
defparam CounterUDB.RunMode = 1;
defparam CounterUDB.UseInterrupt = 1;
endmodule
// Component: cy_constant_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_constant_v1_0\cy_constant_v1_0.v"
`endif
// top
module top ;
wire Net_350;
wire Net_300;
wire Net_299;
wire Net_298;
wire Net_297;
wire Net_296;
wire Net_295;
wire Net_76;
wire Net_187;
electrical Net_307;
electrical Net_314;
electrical Net_311;
electrical Net_308;
wire Net_286;
wire Net_243;
wire Net_189;
wire Net_242;
wire Net_186;
wire Net_188;
wire [0:0] tmpOE__Pin_1_net;
wire [0:0] tmpFB_0__Pin_1_net;
wire [0:0] tmpIO_0__Pin_1_net;
wire [0:0] tmpINTERRUPT_0__Pin_1_net;
electrical [0:0] tmpSIOVREF__Pin_1_net;
cy_psoc3_pins_v1_10
#(.id("3dba336a-f6a5-43fb-aed3-de1e0b7bf362"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b1),
.vtrip(2'b10),
.width(1))
Pin_1
(.oe(tmpOE__Pin_1_net),
.y({Net_187}),
.fb({tmpFB_0__Pin_1_net[0:0]}),
.io({tmpIO_0__Pin_1_net[0:0]}),
.siovref(tmpSIOVREF__Pin_1_net),
.interrupt({tmpINTERRUPT_0__Pin_1_net[0:0]}),
.annotation({Net_307}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Pin_1_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_clock_v1_0
#(.id("f7e617de-451d-41ac-a469-e1d8f1d87445"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(2),
.period("0"),
.is_direct(0),
.is_digital(1))
Clock_1
(.clock_out(Net_186));
wire [0:0] tmpOE__Pin_2_net;
wire [0:0] tmpFB_0__Pin_2_net;
wire [0:0] tmpIO_0__Pin_2_net;
wire [0:0] tmpINTERRUPT_0__Pin_2_net;
electrical [0:0] tmpSIOVREF__Pin_2_net;
cy_psoc3_pins_v1_10
#(.id("51010087-04dc-4e24-97b0-b1201a8c8de6"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Pin_2
(.oe(tmpOE__Pin_2_net),
.y({Net_188}),
.fb({tmpFB_0__Pin_2_net[0:0]}),
.io({tmpIO_0__Pin_2_net[0:0]}),
.siovref(tmpSIOVREF__Pin_2_net),
.interrupt({tmpINTERRUPT_0__Pin_2_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Pin_2_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__Pin_3_net;
wire [0:0] tmpFB_0__Pin_3_net;
wire [0:0] tmpIO_0__Pin_3_net;
wire [0:0] tmpINTERRUPT_0__Pin_3_net;
electrical [0:0] tmpSIOVREF__Pin_3_net;
cy_psoc3_pins_v1_10
#(.id("89175cc8-82f4-43f8-81c9-e7745da2d3af"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
Pin_3
(.oe(tmpOE__Pin_3_net),
.y({Net_189}),
.fb({tmpFB_0__Pin_3_net[0:0]}),
.io({tmpIO_0__Pin_3_net[0:0]}),
.siovref(tmpSIOVREF__Pin_3_net),
.interrupt({tmpINTERRUPT_0__Pin_3_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__Pin_3_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
WS2812driver WS2812driver_1 (
.CLK(Net_186),
.PulseOut(Net_187),
.BUSY(Net_188),
.FIFO_EMPTY(Net_189));
Counter_v2_40_0 Counter_reset_gen (
.reset(Net_188),
.tc(Net_295),
.comp(Net_296),
.clock(Net_242),
.interrupt(Net_243),
.enable(Net_286),
.capture(1'b0),
.upCnt(1'b0),
.downCnt(1'b0),
.up_ndown(1'b1),
.count(Net_286));
defparam Counter_reset_gen.CaptureMode = 0;
defparam Counter_reset_gen.ClockMode = 3;
defparam Counter_reset_gen.CompareMode = 1;
defparam Counter_reset_gen.CompareStatusEdgeSense = 1;
defparam Counter_reset_gen.EnableMode = 1;
defparam Counter_reset_gen.ReloadOnCapture = 0;
defparam Counter_reset_gen.ReloadOnCompare = 0;
defparam Counter_reset_gen.ReloadOnOverUnder = 0;
defparam Counter_reset_gen.ReloadOnReset = 1;
defparam Counter_reset_gen.Resolution = 8;
defparam Counter_reset_gen.RunMode = 1;
defparam Counter_reset_gen.UseInterrupt = 1;
cy_clock_v1_0
#(.id("117aede7-d730-428e-9e64-f2e7716138bc"),
.source_clock_id("413DE2EF-D9F2-4233-A808-DFAF137FD877"),
.divisor(8),
.period("0"),
.is_direct(0),
.is_digital(1))
Clock_2
(.clock_out(Net_242));
cy_isr_v1_0
#(.int_type(2'b00))
isr_fifo_empty
(.int_signal(Net_189));
cy_isr_v1_0
#(.int_type(2'b10))
isr_reset_done
(.int_signal(Net_243));
assign Net_286 = 1'h1;
cy_annotation_universal_v1_0 D_1 (
.connect({
Net_307,
Net_308
})
);
defparam D_1.comp_name = "LED_v1_0";
defparam D_1.port_names = "A, K";
defparam D_1.width = 2;
cy_annotation_universal_v1_0 D_2 (
.connect({
Net_308,
Net_311
})
);
defparam D_2.comp_name = "LED_v1_0";
defparam D_2.port_names = "A, K";
defparam D_2.width = 2;
cy_annotation_universal_v1_0 D_3 (
.connect({
Net_311,
Net_314
})
);
defparam D_3.comp_name = "LED_v1_0";
defparam D_3.port_names = "A, K";
defparam D_3.width = 2;
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_fwft_96x512.v
// /___/ /\ Timestamp: Thu Nov 8 19:02:12 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_fwft_96x512.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_fwft_96x512.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_fwft_96x512.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_fwft_96x512.v
// # of Modules : 1
// Design Name : fifo_fwft_96x512
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_fwft_96x512 (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [95 : 0] dout;
input [95 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire N4;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_6 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_7 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_29 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000_30 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_35 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_37 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_39 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_41 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_43 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_45 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_47 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_95 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_96 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_100 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_102 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_104 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_106 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_108 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_110 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_112 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_114 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
wire [95 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i ;
wire [95 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_7 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_96 ,
dout[95] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [95],
dout[94] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [94],
dout[93] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [93],
dout[92] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [92],
dout[91] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [91],
dout[90] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [90],
dout[89] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [89],
dout[88] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [88],
dout[87] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [87],
dout[86] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [86],
dout[85] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [85],
dout[84] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [84],
dout[83] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [83],
dout[82] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [82],
dout[81] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [81],
dout[80] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [80],
dout[79] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [79],
dout[78] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [78],
dout[77] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [77],
dout[76] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [76],
dout[75] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [75],
dout[74] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [74],
dout[73] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [73],
dout[72] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [72],
dout[71] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [71],
dout[70] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [70],
dout[69] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [69],
dout[68] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [68],
dout[67] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [67],
dout[66] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [66],
dout[65] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [65],
dout[64] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [64],
dout[63] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [63],
dout[62] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [62],
dout[61] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [61],
dout[60] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [60],
dout[59] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [59],
dout[58] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [58],
dout[57] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [57],
dout[56] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [56],
dout[55] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [55],
dout[54] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [54],
dout[53] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [53],
dout[52] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [52],
dout[51] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [51],
dout[50] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [50],
dout[49] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [49],
dout[48] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [48],
dout[47] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [47],
dout[46] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [46],
dout[45] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [45],
dout[44] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [44],
dout[43] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [43],
dout[42] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [42],
dout[41] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [41],
dout[40] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40],
dout[39] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39],
dout[38] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38],
dout[37] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37],
dout[36] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36],
dout[35] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35],
dout[34] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34],
dout[33] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33],
dout[32] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32],
dout[31] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31],
dout[30] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30],
dout[29] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29],
dout[28] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28],
dout[27] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27],
dout[26] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26],
dout[25] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25],
dout[24] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24],
dout[23] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23],
dout[22] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22],
dout[21] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21],
dout[20] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20],
dout[19] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19],
dout[18] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18],
dout[17] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17],
dout[16] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16],
dout[15] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15],
dout[14] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14],
dout[13] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13],
dout[12] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12],
dout[11] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11],
dout[10] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10],
dout[9] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9],
dout[8] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8],
dout[7] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7],
dout[6] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6],
dout[5] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5],
dout[4] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4],
dout[3] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3],
dout[2] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2],
dout[1] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1],
dout[0] = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0];
GND XST_GND (
.G(N0)
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VCC XST_VCC (
.P(N1)
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FD #(
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
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);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
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FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
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MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
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XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
FDR #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1 (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In ),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_7 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_6 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_114 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_112 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_112 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_110 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_110 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_108 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_108 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_95 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [95]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [95])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_94 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [94]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [94])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_93 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [93]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [93])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_92 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [92]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [92])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_91 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [91]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [91])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_90 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [90]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [90])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_89 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [89]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [89])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_88 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [88]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [88])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_87 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [87]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [87])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_86 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [86]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [86])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_85 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [85]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [85])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_84 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [84]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [84])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_83 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [83]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [83])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_82 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [82]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [82])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_81 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [81]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [81])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_80 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [80]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [80])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_79 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [79]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [79])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_78 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [78]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [78])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_77 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [77]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [77])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_76 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [76]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [76])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_75 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [75]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [75])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_74 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [74]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [74])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_73 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [73]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [73])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_72 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [72]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [72])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_71 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [71]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [71])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_70 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [70]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [70])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_69 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [69]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [69])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_68 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [68]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [68])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_67 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [67]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [67])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_66 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [66]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [66])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_65 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [65]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [65])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_64 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [64]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [64])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_63 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [63]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [63])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_62 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [62]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [62])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_61 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [61]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [61])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_60 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [60]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [60])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_59 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [59]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [59])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_58 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [58]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [58])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_57 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [57]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [57])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_56 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [56]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [56])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_55 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [55]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [55])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_54 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [54]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [54])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_53 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [53]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [53])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_52 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [52]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [52])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_51 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [51]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [51])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_50 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [50]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [50])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_49 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [49]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [49])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_48 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [48]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [48])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_47 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [47]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [47])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_46 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [46]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [46])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_45 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [45]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [45])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_44 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [44]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [44])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_43 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [43]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [43])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_42 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [42]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [42])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_41 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [41]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [41])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_40 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [40]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [40])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_39 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [39]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [39])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_38 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [38]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [38])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_37 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [37]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [37])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_36 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [36]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [36])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_35 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [35]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [35])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_34 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [34]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [34])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_33 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [33]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [33])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_32 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [32]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [32])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_31 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [31]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [31])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_30 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [30]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [30])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_29 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [29]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [29])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_28 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [28]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [28])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_27 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [27]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [27])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_26 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [26]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [26])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_25 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [25]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [25])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_24 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [24]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [24])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_23 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [23]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [23])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_22 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [22]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [22])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_21 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [21]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [21])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_20 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [20]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [20])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_19 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [19]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [19])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_18 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [18]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [18])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_17 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [17]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [17])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_16 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [16]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [16])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_15 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [15]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [15])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_14 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [14]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [14])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_13 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [13]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [13])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_12 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [12]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [12])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_11 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [11]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [11])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_10 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [10]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [10])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_9 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [9]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [9])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_i [0])
);
LUT4 #(
.INIT ( 16'h5D55 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_29 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 ),
.I2(rd_en),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1-In )
);
LUT5 #(
.INIT ( 32'hFFFFB2A2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb_6 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 ),
.I3(rd_en),
.I4(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i_mux0000 )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_95 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT3 #(
.INIT ( 8'hA2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_REGOUT_EN1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 ),
.I2(rd_en),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_regout_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_95 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT4 #(
.INIT ( 16'h2333 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/RAM_RD_EN_FWFT1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_29 ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT2 #(
.INIT ( 4'hD ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000_SW0 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_95 ),
.O(N4)
);
LUT6 #(
.INIT ( 64'hFAEAEAEAFEEEEEEE ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_29 ),
.I2(N4),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000_30 )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
FDRSE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2 (
.C(clk),
.CE(rd_en),
.D(N0),
.R(srst),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_45 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_43 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_41 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_39 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_37 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_35 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_33 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_112 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_110 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_108 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_106 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_104 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_102 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_100 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_47 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_114 )
);
LUT5 #(
.INIT ( 32'hFFFF5515 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_29 ),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd2_5 ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/curr_fwft_state_FSM_FFd1_3 ),
.I3(rd_en),
.I4(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({N0, din[95], din[94], din[93], din[92], din[91], din[90], din[89], din[88], din[87], din[86], din[85], din[84], din[83], din[82], din[81], N0
, din[80], din[79], din[78], din[77], din[76], din[75], din[74], din[73], din[72], din[71], din[70], din[69], din[68], din[67], din[66], N0, din[65],
din[64], din[63], din[62], din[61], din[60], din[59], din[58], din[57], din[56], din[55], din[54], din[53], din[52], din[51], N0, din[50], din[49],
din[48], din[47], din[46], din[45], din[44], din[43], din[42], din[41], din[40], din[39], din[38], din[37], din[36]}),
.DIP({N0, N0, N0, N0, N0, N0, N0, N0}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<63>_UNCONNECTED
, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [95],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [94],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [93],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [92],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [91],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [90],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [89],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [88],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [87],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [86],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [85],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [84],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [83],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [82],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [81],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<47>_UNCONNECTED
, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [80],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [79],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [78],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [77],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [76],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [75],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [74],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [73],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [72],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [71],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [70],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [69],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [68],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [67],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [66],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<31>_UNCONNECTED
, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [65],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [64],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [63],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [62],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [61],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [60],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [59],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [58],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [57],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [56],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [55],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [54],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [53],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [52],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [51],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DO<15>_UNCONNECTED
, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [50],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [49],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [48],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [47],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [46],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [45],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [44],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [43],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [42],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [41],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [40],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [39],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [38],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [37],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [36]}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED
}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
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\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
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\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
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\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM18.TDP (
.RDCLK(clk),
.WRCLK(clk),
.RDEN(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WREN(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.REGCE(N0),
.SSR(srst),
.RDADDR({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]}),
.WRADDR({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]}),
.DI({din[34], din[33], din[32], din[31], din[30], din[29], din[28], din[27], din[25], din[24], din[23], din[22], din[21], din[20], din[19],
din[18], din[16], din[15], din[14], din[13], din[12], din[11], din[10], din[9], din[7], din[6], din[5], din[4], din[3], din[2], din[1], din[0]}),
.DIP({din[35], din[26], din[17], din[8]}),
.DO({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [34],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [33],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [32],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [31],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [30],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [29],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [28],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [27],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [25],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [24],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [23],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [22],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [21],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [20],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [19],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [18],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [16],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [15],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [14],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [13],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [12],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [11],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [10],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [9],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [0]}),
.DOP({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [35],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [26],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [17],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/dout_mem [8]}),
.WE({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en })
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_ddr_cntrl (
// ddr interface
ddr_clk,
ddr_rst,
ddr_start,
ddr_stream,
ddr_count,
ddr_ovf,
ddr_unf,
ddr_status,
ddr_bw,
ddr_ready,
// dma interface
dma_clk,
dma_rst,
dma_start,
dma_stream,
dma_count,
dma_ovf,
dma_unf,
dma_status,
dma_bw,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// ddr interface
input ddr_clk;
output ddr_rst;
output ddr_start;
output ddr_stream;
output [31:0] ddr_count;
input ddr_ovf;
input ddr_unf;
input ddr_status;
input [31:0] ddr_bw;
input ddr_ready;
// dma interface
input dma_clk;
output dma_rst;
output dma_start;
output dma_stream;
output [31:0] dma_count;
input dma_ovf;
input dma_unf;
input dma_status;
input [31:0] dma_bw;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg up_resetn = 'd0;
reg up_ddr_stream = 'd0;
reg up_ddr_start = 'd0;
reg [31:0] up_ddr_count = 'd0;
reg up_dma_stream = 'd0;
reg up_dma_start = 'd0;
reg [31:0] up_dma_count = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg ddr_start_m1 = 'd0;
reg ddr_start_m2 = 'd0;
reg ddr_start_m3 = 'd0;
reg ddr_start = 'd0;
reg ddr_stream = 'd0;
reg [31:0] ddr_count = 'd0;
reg [ 5:0] ddr_xfer_cnt = 'd0;
reg ddr_xfer_toggle = 'd0;
reg ddr_xfer_ovf = 'd0;
reg ddr_xfer_unf = 'd0;
reg ddr_acc_ovf = 'd0;
reg ddr_acc_unf = 'd0;
reg up_ddr_xfer_toggle_m1 = 'd0;
reg up_ddr_xfer_toggle_m2 = 'd0;
reg up_ddr_xfer_toggle_m3 = 'd0;
reg up_ddr_xfer_ovf = 'd0;
reg up_ddr_xfer_unf = 'd0;
reg up_ddr_ovf = 'd0;
reg up_ddr_unf = 'd0;
reg up_ddr_status_m1 = 'd0;
reg up_ddr_status = 'd0;
reg up_ddr_ready_m1 = 'd0;
reg up_ddr_ready = 'd0;
reg dma_start_m1 = 'd0;
reg dma_start_m2 = 'd0;
reg dma_start_m3 = 'd0;
reg dma_start = 'd0;
reg dma_stream = 'd0;
reg [31:0] dma_count = 'd0;
reg [ 5:0] dma_xfer_cnt = 'd0;
reg dma_xfer_toggle = 'd0;
reg dma_xfer_ovf = 'd0;
reg dma_xfer_unf = 'd0;
reg dma_acc_ovf = 'd0;
reg dma_acc_unf = 'd0;
reg up_dma_xfer_toggle_m1 = 'd0;
reg up_dma_xfer_toggle_m2 = 'd0;
reg up_dma_xfer_toggle_m3 = 'd0;
reg up_dma_xfer_ovf = 'd0;
reg up_dma_xfer_unf = 'd0;
reg up_dma_ovf = 'd0;
reg up_dma_unf = 'd0;
reg up_dma_status_m1 = 'd0;
reg up_dma_status = 'd0;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire up_preset_s;
wire up_ddr_xfer_toggle_s;
wire up_dma_xfer_toggle_s;
// decode block select
assign up_sel_s = ((up_addr[13:4] == 10'h001) || (up_addr[13:4] == 10'h002)) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_resetn <= 'd0;
up_ddr_stream <= 'd0;
up_ddr_start <= 'd0;
up_ddr_count <= 'd0;
up_dma_stream <= 'd0;
up_dma_start <= 'd0;
up_dma_count <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h10)) begin
up_resetn <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h18)) begin
up_ddr_stream <= up_wdata[1];
up_ddr_start <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h19)) begin
up_ddr_count <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h20)) begin
up_dma_stream <= up_wdata[1];
up_dma_start <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h21)) begin
up_dma_count <= up_wdata;
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[5:0])
6'h10: up_rdata <= {31'd0, up_resetn};
6'h17: up_rdata <= {31'd0, up_ddr_ready};
6'h18: up_rdata <= {30'd0, up_ddr_stream, up_ddr_start};
6'h19: up_rdata <= up_ddr_count;
6'h1a: up_rdata <= {29'd0, up_ddr_ovf, up_ddr_unf, up_ddr_status};
6'h1b: up_rdata <= ddr_bw;
6'h20: up_rdata <= {30'd0, up_dma_stream, up_dma_start};
6'h21: up_rdata <= up_dma_count;
6'h22: up_rdata <= {29'd0, up_dma_ovf, up_dma_unf, up_dma_status};
6'h23: up_rdata <= dma_bw;
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// DDR CONTROL
FDPE #(.INIT(1'b1)) i_ddr_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (ddr_clk),
.Q (ddr_rst));
// ddr control transfer
always @(posedge ddr_clk) begin
if (ddr_rst == 1'b1) begin
ddr_start_m1 <= 'd0;
ddr_start_m2 <= 'd0;
ddr_start_m3 <= 'd0;
end else begin
ddr_start_m1 <= up_ddr_start;
ddr_start_m2 <= ddr_start_m1;
ddr_start_m3 <= ddr_start_m2;
end
ddr_start <= ddr_start_m2 & ~ddr_start_m3;
if ((ddr_start_m2 == 1'b1) && (ddr_start_m3 == 1'b0)) begin
ddr_stream <= up_ddr_stream;
ddr_count <= up_ddr_count;
end
end
// ddr status transfer
always @(posedge ddr_clk) begin
ddr_xfer_cnt <= ddr_xfer_cnt + 1'b1;
if (ddr_xfer_cnt == 6'd0) begin
ddr_xfer_toggle <= ~ddr_xfer_toggle;
ddr_xfer_ovf <= ddr_acc_ovf;
ddr_xfer_unf <= ddr_acc_unf;
end
if (ddr_xfer_cnt == 6'd0) begin
ddr_acc_ovf <= ddr_ovf;
ddr_acc_unf <= ddr_unf;
end else begin
ddr_acc_ovf <= ddr_acc_ovf | ddr_ovf;
ddr_acc_unf <= ddr_acc_unf | ddr_unf;
end
end
assign up_ddr_xfer_toggle_s = up_ddr_xfer_toggle_m2 ^ up_ddr_xfer_toggle_m3;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ddr_xfer_toggle_m1 <= 'd0;
up_ddr_xfer_toggle_m2 <= 'd0;
up_ddr_xfer_toggle_m3 <= 'd0;
up_ddr_xfer_ovf <= 'd0;
up_ddr_xfer_unf <= 'd0;
up_ddr_ovf <= 'd0;
up_ddr_unf <= 'd0;
end else begin
up_ddr_xfer_toggle_m1 <= ddr_xfer_toggle;
up_ddr_xfer_toggle_m2 <= up_ddr_xfer_toggle_m1;
up_ddr_xfer_toggle_m3 <= up_ddr_xfer_toggle_m2;
if (up_ddr_xfer_toggle_s == 1'b1) begin
up_ddr_xfer_ovf <= ddr_xfer_ovf;
up_ddr_xfer_unf <= ddr_xfer_unf;
end
if (up_ddr_xfer_ovf == 1'b1) begin
up_ddr_ovf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h1a)) begin
up_ddr_ovf <= up_ddr_ovf & ~up_wdata[2];
end
if (up_ddr_xfer_unf == 1'b1) begin
up_ddr_unf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h1a)) begin
up_ddr_unf <= up_ddr_unf & ~up_wdata[1];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ddr_status_m1 <= 'd0;
up_ddr_status <= 'd0;
end else begin
up_ddr_status_m1 <= ddr_status;
up_ddr_status <= up_ddr_status_m1;
end
end
// ddr interface ready
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ddr_ready_m1 <= 'd0;
up_ddr_ready <= 'd0;
end else begin
up_ddr_ready_m1 <= ddr_ready;
up_ddr_ready <= up_ddr_ready_m1;
end
end
// DMA CONTROL
FDPE #(.INIT(1'b1)) i_dma_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (dma_clk),
.Q (dma_rst));
// dma control transfer
always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin
dma_start_m1 <= 'd0;
dma_start_m2 <= 'd0;
dma_start_m3 <= 'd0;
end else begin
dma_start_m1 <= up_dma_start;
dma_start_m2 <= dma_start_m1;
dma_start_m3 <= dma_start_m2;
end
dma_start <= dma_start_m2 & ~dma_start_m3;
if ((dma_start_m2 == 1'b1) && (dma_start_m3 == 1'b0)) begin
dma_stream <= up_dma_stream;
dma_count <= up_dma_count;
end
end
// dma status transfer
always @(posedge dma_clk) begin
dma_xfer_cnt <= dma_xfer_cnt + 1'b1;
if (dma_xfer_cnt == 6'd0) begin
dma_xfer_toggle <= ~dma_xfer_toggle;
dma_xfer_ovf <= dma_acc_ovf;
dma_xfer_unf <= dma_acc_unf;
end
if (dma_xfer_cnt == 6'd0) begin
dma_acc_ovf <= dma_ovf;
dma_acc_unf <= dma_unf;
end else begin
dma_acc_ovf <= dma_acc_ovf | dma_ovf;
dma_acc_unf <= dma_acc_unf | dma_unf;
end
end
assign up_dma_xfer_toggle_s = up_dma_xfer_toggle_m2 ^ up_dma_xfer_toggle_m3;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_xfer_toggle_m1 <= 'd0;
up_dma_xfer_toggle_m2 <= 'd0;
up_dma_xfer_toggle_m3 <= 'd0;
up_dma_xfer_ovf <= 'd0;
up_dma_xfer_unf <= 'd0;
up_dma_ovf <= 'd0;
up_dma_unf <= 'd0;
end else begin
up_dma_xfer_toggle_m1 <= dma_xfer_toggle;
up_dma_xfer_toggle_m2 <= up_dma_xfer_toggle_m1;
up_dma_xfer_toggle_m3 <= up_dma_xfer_toggle_m2;
if (up_dma_xfer_toggle_s == 1'b1) begin
up_dma_xfer_ovf <= dma_xfer_ovf;
up_dma_xfer_unf <= dma_xfer_unf;
end
if (up_dma_xfer_ovf == 1'b1) begin
up_dma_ovf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h22)) begin
up_dma_ovf <= up_dma_ovf & ~up_wdata[2];
end
if (up_dma_xfer_unf == 1'b1) begin
up_dma_unf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[5:0] == 6'h22)) begin
up_dma_unf <= up_dma_unf & ~up_wdata[1];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_dma_status_m1 <= 'd0;
up_dma_status <= 'd0;
end else begin
up_dma_status_m1 <= dma_status;
up_dma_status <= up_dma_status_m1;
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DECAP_BLACKBOX_V
`define SKY130_FD_SC_MS__DECAP_BLACKBOX_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__decap ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DECAP_BLACKBOX_V
|
module midi_in(CLK, RES, MIDI_IN,
CH_MESSAGE,
CHAN, NOTE, VELOCITY, LSB, MSB //параметры сообщений
);
input wire CLK; // 50 MHz clock
input wire RES; // reset
input wire MIDI_IN; // MIDI in data
//note control
output reg [3:0] CHAN; // номер канала, в который отправляется нота. в ПО считаются от 1 до 16. тут считаются с 0. То есть барабаны - 10й, тут будет 9.
output reg [6:0] NOTE; // номер ноты 0 - это С-1, 12 - С0, 24 - С1
output reg [6:0] VELOCITY;
output reg [6:0] LSB;
output reg [6:0] MSB;
output reg [3:0] CH_MESSAGE;
reg [23:0] midi_command; //миди команда 3 байта
reg [7:0] rcv_state;
//состояние приемника
//0 - ожидаем любой байт
//1 - принят первый байт сообщения канала nnnn одно из сообщений ниже, и ждем еще двух байт данных, у которых старший бит = 0, иначе это реалтайм сообщения
// 1000nnnn - Note Off (Номер ноты(NOTE); Динамика(VELOCITY))
// 1001nnnn - Note On (Номер ноты(NOTE); Динамика(VELOCITY))
// 1010nnnn - Polyphonic Key Pressure (Номер ноты(NOTE); Давление(VELOCITY))
// 1011nnnn - Control Change (Номер контроллера(LSB); Значение контроллера(MSB))
// 1100nnnn - Program Change (Номер программы(LSB); -)
// 1101nnnn - Channel Pressure (Давление(LSB); -)
// 1110nnnn - Pitch Wheel Change (LSB;MSB)
//2 - принят второй байт сообщения канала
//3 - принят третий байт сообщения канала и переход в 0
reg [7:0] byte1;
reg [7:0] byte2;
reg [7:0] byte3;
initial begin
CHAN <= 4'b0000;
NOTE <= 7'd0;
VELOCITY <= 7'd0;
LSB <= 7'd0;
MSB <= 7'd0;
CH_MESSAGE <= 4'd0;
rcv_state <= 8'b00000000;
byte1 <= 8'd0;
byte2 <= 8'd0;
byte3 <= 8'd0;
end
//midi rx
//бодген - модуль для генерации клока UART
// first register:
// baud_freq = 16*baud_rate / gcd(global_clock_freq, 16*baud_rate)
//Greatest Common Divisor - наибольший общий делитель. http://www.alcula.com/calculators/math/gcd/
//baud_freq = 16*31250 / gcd(50000000, 50000) = 500000 / 500000 = 1
// second register:
// baud_limit = (global_clock_freq / gcd(global_clock_freq, 16*baud_rate)) - baud_freq
//baud_limit = (50000000 / gcd(50000000, 500000)) - 1
// = ( 50000000 / 500000) - 1 = 99
wire port_clk;
wire [7:0] uart_command;
wire ucom_ready;
baud_gen BG( CLK, RES, port_clk, 1, 99);
uart_rx URX( CLK, RES, port_clk, MIDI_IN, uart_command, ucom_ready );
always @ (posedge CLK) begin
if (ucom_ready==1) begin
//Ожидаем сообщение
if (rcv_state==8'd0) begin
//если старший бит = 1, то это сообщение
//запоминаем байт
if (uart_command[7:7]==1'b1) byte1 <= uart_command;
//в любом случае сбрасываем выходы NOTE_ON, NOTE_OFF, NOTE, VELOCITY
CH_MESSAGE <= 4'd0;
CHAN <= 4'b0000;
NOTE <= 7'd0;
LSB <= 7'd00;
MSB <= 7'd00;
VELOCITY <= 7'd0;
//смена стейта
rcv_state <= ((uart_command[7:4]>=4'b1000)&&(uart_command[7:4]<=4'b1110)) ? 8'd01 : rcv_state;
end else if (rcv_state==8'd01) begin //ждем первый байт данных
//если старший бит = 0, то это данные
if (uart_command[7:7]==1'b0) byte2 <= uart_command;
//сменf стейта
rcv_state <= (uart_command[7:7]==1'b0) ? 8'd2 : rcv_state;
end else if (rcv_state==8'd02) begin //ждем второй байт данных
//если старший бит = 0, то это данные
if (uart_command[7:7]==1'b0) begin
byte3 = uart_command; // = вместо <= для присвоения сразу. чтобы все данные были сразу в byte1, 2, 3
//Обрабатываем три принятых байта
//номер канала (в первом байте, 4 младших бита)
CHAN <= byte1[3:0];
//декодируем сообщение
if ((byte1[7:4]==4'b1000)||(byte1[7:4]==4'b1001)||(byte1[7:4]==4'b1010)) begin //note off, note on, poly key pressure
CH_MESSAGE <= byte1[7:4];
//нота
NOTE <= byte2[6:0];
//значение velocity или pressure
VELOCITY <= byte3[6:0];
end else if ((byte1[7:4]==4'b1100)||(byte1[7:4]==4'b1101)) begin // Program change, Channel pressure
CH_MESSAGE <= byte1[7:4];
LSB <= byte2[6:0];
MSB <= 0;
end else if ((byte1[7:4]==4'b1011)||(byte1[7:4]==4'b1110)) begin
CH_MESSAGE <= byte1[7:4];
LSB <= byte2[6:0];
MSB <= byte3[6:0];
end
end
//смена стейта
rcv_state <= (uart_command[7:7]==1'b0) ? 8'd0 : rcv_state;
end
end //ucom_ready
end
endmodule |
Require Import List.
Require Import Ascii.
Require Import Omega.
Require Import Stream.
Require Import Charset.
Import INSTREAM.
Set Implicit Arguments.
Section CHARSET.
Variable charset : Charset.
Definition char := char charset.
(* We describe the syntax of grammars using Adam's approach from ltamer *)
Section VARS.
Variable var : Set -> Type.
Inductive term: Set -> Type :=
| GVar : forall t:Set, var t -> term t
| GEpsilon : forall t:Set, t -> term t
| GSatisfy : (char -> bool) -> term char
| GCat : forall (t1 t2:Set), term t1 -> term t2 -> term (t1 * t2)
| GAlt : forall t, term t -> term t -> term t
| GTry : forall t, term t -> term t
| GRec : forall t:Set, (var t -> term t) -> term t
| GMap : forall (t1 t2:Set), (t1 -> t2) -> term t1 -> term t2.
(* A relational definition of substitution for terms -- used in the definition
* of the semantics below, in particular for the rec case *)
Inductive Subst :
forall (t1 t2:Set), (var t1->term t2)->(term t1)->(term t2)->Type :=
| SEpsilon : forall (t1 t2:Set) (v:t2) (e:term t1),
Subst (fun _ => GEpsilon v) e (GEpsilon v)
| SSatisfy : forall t1 (f:char->bool) (e:term t1),
Subst (fun _ => GSatisfy f) e (GSatisfy f)
| SCat :
forall t1 t2 t3 (f1:var t1 -> term t2) (f2:var t1 -> term t3) (e:term t1)
(e1:term t2)(e2:term t3),
Subst f1 e e1 -> Subst f2 e e2 ->
Subst (fun v => GCat (f1 v) (f2 v)) e (GCat e1 e2)
| SAlt :
forall t1 t2 (f1 f2:var t1 -> term t2) (e:term t1)(e1 e2:term t2),
Subst f1 e e1 -> Subst f2 e e2 ->
Subst (fun v => GAlt (f1 v) (f2 v)) e (GAlt e1 e2)
| SMap :
forall (t1 t2 t3:Set)
(f:var t1 -> term t2) (e:term t1) (g:t2->t3) (e1:term t2),
Subst f e e1 ->
Subst (fun v => GMap g (f v)) e (GMap g e1)
| STry :
forall t1 t2 (f1:var t1 -> term t2) (e : term t1) (e1:term t2),
Subst f1 e e1 -> Subst (fun v => GTry (f1 v)) e (GTry e1)
| SVarEq :
forall t (e:term t), Subst (@GVar t) e e
| SVarNeq :
forall t1 t2 (v:var t2) (e:term t1), Subst (fun _ => GVar v) e (GVar v)
| SRec :
forall t1 t2 (f1:var t1->var t2->term t2) (f2:var t2->term t2)(e:term t1),
(forall v', Subst (fun v => f1 v v') e (f2 v')) ->
Subst (fun v => GRec (f1 v)) e (GRec f2).
End VARS.
Definition Term t := forall V, term V t.
Implicit Arguments GVar [var t].
Implicit Arguments GEpsilon [var t].
Implicit Arguments GSatisfy [var].
Implicit Arguments GCat [var t1 t2].
Implicit Arguments GAlt [var t].
Implicit Arguments GTry [var t].
Implicit Arguments GRec [var t].
Implicit Arguments GMap [var t1 t2].
Fixpoint flatten(V:Set->Type)(t:Set)(e: term (term V) t) {struct e} : term V t :=
match e in (term _ t) return (term V t) with
| GVar _ v => v
| GEpsilon t v => GEpsilon v
| GSatisfy f => GSatisfy f
| GCat t1 t2 e1 e2 => GCat (flatten e1) (flatten e2)
| GAlt t e1 e2 => GAlt (flatten e1) (flatten e2)
| GMap t1 t2 f e => GMap f (flatten e)
| GTry t e => GTry (flatten e)
| GRec t f => GRec (fun (v:V t) => flatten (f (GVar v)))
end.
Definition unroll(t:Set)(f:forall V, V t -> term V t) : Term t :=
fun V => flatten (f (term V) (GRec (f V))).
Definition empvar := (fun _:Set => Empty_set).
(* It would be nice if we could prove the following axiom so that the definition
* of Gfix was simpler:
Axiom Unroll : forall (t:Set)(f:forall var, var t -> term var t),
Subst (f empvar) (GRec (f empvar)) (unroll f empvar).
*)
Inductive consumed_t : Set := Consumed | NotConsumed.
Inductive reply_t(a:Set) : Set :=
| Okay : consumed_t -> a -> list char -> reply_t a
| Error : consumed_t -> reply_t a.
Implicit Arguments Error [a].
Definition join_cons (nc1 nc2 : consumed_t) : consumed_t :=
match (nc1, nc2) with
| (Consumed, _) => Consumed
| (_, Consumed) => Consumed
| (_, _) => NotConsumed
end.
(* We give meaning to grammars here, following the style of Parsec combinators.
* In particular, note that we only try the second grammar of an alternation when
* the first one does not consume input. The presentation here is slightly di fferent
* from Parsec in that (a) we don't worry about space leaks since this is intended
* for specification only, and (b) instead of representing concatenation with a
* bind-like construct, we simply return a pair of the results. We have a separate
* operation GMap that allows us to transform a t1 grammar to a t2 grammar. The
* intention here is that grammars should use a minimum of meta-level stuff in
* revealing their structure, so that we can potentially analyze and transform them.
*)
(* What I'm doing here is defining a denotational semantics that maps grammar terms
* down to a simpler language with a monadic structure. Then we give an operational
* semantics to the monadic structure. Note that I've instantiated the var in the
* phoas so that it always yields an empty set. This ensures that the term does not
* have a free variable. *)
Inductive M: Set -> Type :=
| MReturn : forall t, reply_t t -> M t
| MBind : forall t1 t2, M t1 -> (reply_t t1 -> M t2) -> M t2
| MFix : forall t (f:empvar t -> term empvar t), list char -> M t.
Notation "'Return' x" := (MReturn x) (at level 75) : gdenote_scope.
Notation "x <- c1 ; c2" := (MBind c1 (fun x => c2))
(right associativity, at level 84, c1 at next level) : gdenote_scope.
Definition wfCoerce (t:Set)(v:empvar t) : M t := match v with end.
Open Local Scope gdenote_scope.
(* here we map a term e to a computation over lists of characters -- this is
* essentially the same as with Parsec-style combinators, though I've chosen
* slightly different combinators that are closer to arrows than the monadic
* interpretation. *)
Fixpoint denote(t:Set)(e:term empvar t)(s:list char) {struct e} : M t :=
match e in term _ t return M t with
| GVar _ v => wfCoerce v
| GEpsilon _ x => Return Okay NotConsumed x s
| GSatisfy test =>
Return match s with
| c :: cs => if (test c) then Okay Consumed c cs else
Error NotConsumed
| nil => Error NotConsumed
end
| GMap t1 t2 f e =>
r <- denote e s ;
Return match r with
| Okay nc v s2 => Okay nc (f v) s2
| Error nc => Error nc
end
| GTry t e =>
r <- denote e s ;
Return match r with
| Error Consumed => Error NotConsumed
| Okay Consumed v s2 => Okay NotConsumed v s2
| _ => r
end
| GCat t1 t2 e1 e2 =>
r1 <- denote e1 s ;
match r1 with
| Error nc => Return Error nc
| Okay nc1 v1 s1 =>
r2 <- denote e2 s1 ;
Return match r2 with
| Error nc2 => Error (join_cons nc1 nc2)
| Okay nc2 v2 s2 => Okay (join_cons nc1 nc2) (v1,v2) s2
end
end
| GAlt t e1 e2 =>
r1 <- denote e1 s ;
match r1 with
| Error Consumed => Return Error Consumed
| Error NotConsumed => denote e2 s
| Okay NotConsumed v s2 =>
r2 <- denote e2 s ;
Return match r2 with
| Error NotConsumed => Okay NotConsumed v s2
| Okay NotConsumed _ _ => Okay NotConsumed v s2
| r2 => r2
end
| Okay Consumed v s2 => Return Okay Consumed v s2
end
| GRec t f => MFix f s
end.
(* We now give an operational semantics to the monadic terms generated by the
* denotation function. Note that in essence, we just delay unrolling the
* fix operator. *)
Inductive evals : forall t, M t -> reply_t t -> Prop :=
| eMReturn : forall t (r:reply_t t), evals (MReturn r) r
| eMBind : forall t1 t2 (c:M t1) (r1:reply_t t1) (f:reply_t t1 -> M t2) r2,
evals c r1 -> evals (f r1) r2 -> evals (MBind c f) r2
| eMFix :
forall t (f:empvar t -> term empvar t) (s:list char) (e:term empvar t) (r:reply_t t),
Subst f (GRec f) e -> evals (denote e s) r -> evals (MFix f s) r.
(* Then we say that a term t parses string s yielding result r if the following
* if evaluating the denotation of e, when applied to s yields r. *)
Definition parses(t:Set)(e:Term t)(s:list char)(r:reply_t t) :=
evals (denote (e empvar) s) r.
Inductive parse_reply_t(t:Set) : Set :=
| OKAY : consumed_t -> nat -> t -> parse_reply_t t
| ERROR : consumed_t -> list ascii -> parse_reply_t t.
Fixpoint nthtail(A:Type)(cs:list A)(n:nat) {struct n} : list A :=
match (n,cs) with
| (0,cs) => cs
| (S n, c::cs) => nthtail cs n
| (S n, nil) => nil
end.
Require Import Ynot.
Definition okay(t:Set)(n: [nat])(i:instream_t char)(e:Term t)(c:consumed_t)(m:nat)(v:t) :=
(n ~~ let elts := stream_elts i in
elts ~~ [parses e (nthtail elts n) (Okay c v (nthtail elts (m+n)))])%hprop.
Definition okaystr(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t)(m:nat)(v:t) :=
(okay n i e c m v * (n ~~ rep i (m+n)))%hprop.
Definition error(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t) :=
(n ~~ let elts := stream_elts i in
elts ~~ [parses e (nthtail elts n) (Error c)])%hprop.
Definition errorstr(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(c:consumed_t) :=
(error n i e c * (Exists m :@ nat, rep i m))%hprop.
Definition ans_correct(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(ans:parse_reply_t t) :=
match ans with
| OKAY c m v => okay n i e c m v
| ERROR c _ => error n i e c
end.
Definition ans_str_correct(t:Set)(n:[nat])(i:instream_t char)(e:Term t)(ans:parse_reply_t t) :=
match ans with
| OKAY c m v => okaystr n i e c m v
| ERROR c _ => errorstr n i e c
end.
Definition parser_t(t:Set)(e:Term t) :=
forall (ins:instream_t char)(n:[nat]), STsep (n ~~ rep ins n) (ans_str_correct n ins e).
Implicit Arguments parser_t [t].
Open Local Scope stsep_scope.
Lemma EmpImpInj(P:Prop) :
P -> __ ==> [P].
Proof.
intros. sep fail auto.
Qed.
Lemma NthErrorNoneNthTail(A:Type)(i:nat) : forall (vs:list A),
nth_error vs i = None -> nthtail vs i = nil.
Proof.
induction i ; destruct vs ; auto ; simpl ; intros. unfold value in H. congruence.
apply IHi. auto.
Qed.
Lemma NthErrorSomeNthTail(A:Type)(i:nat) : forall (vs:list A)(v:A),
nth_error vs i = Some v ->
exists vs1, exists vs2, vs = vs1 ++ v::vs2 /\ nthtail vs i = v::vs2.
Proof.
induction i ; destruct vs ; auto ; simpl ; intros. unfold Specif.error in H. congruence.
unfold value in H. inversion H. subst. exists (nil(A:=A)). simpl. eauto.
unfold Specif.error in H. congruence. pose (IHi _ _ H). destruct e as [vs1 [vs2 [H1 H2]]].
exists (a::vs1). exists vs2. split. rewrite H1. simpl. auto. auto.
Qed.
Lemma NthTailSucc(A:Type)(i:nat) : forall (vs vs2:list A)(v:A),
nthtail vs i = v::vs2 -> nthtail vs (S i) = vs2.
Proof.
induction i ; simpl ; intros. rewrite H. auto. destruct vs. congruence.
pose (IHi _ _ _ H). apply e.
Qed.
Lemma PlusAssoc(n m p:nat) : n + (m + p) = n + m + p. intros ; omega.
Qed.
Ltac mysep :=
match goal with
| [ |- (__ ==> [ _ ])%hprop ] => apply EmpImpInj
| [ |- evals (MReturn ?r) ?r ] => constructor
| [ |- evals (MBind _ _) _] => econstructor
| [ |- context[?n + (?m + ?p)]] => rewrite (PlusAssoc n m p)
| [ |- context[if (?f ?c) then _ else _] ] =>
let H := fresh "H" in
assert (H: f c = true \/ f c = false) ; [ destruct (f c) ; tauto |
destruct H ; [ rewrite H ; simpl | rewrite H ; simpl ]]
| _ => auto
end.
Definition lower (P : char -> Prop) (v : forall c : char, {P c} + {~P c}) : char -> bool := fun c => if v c then true else false.
Definition gsatisfy(f:char -> bool) vars := GSatisfy (var:=vars) f.
Definition gclass(cl:CharClass charset) vars := GSatisfy (var:=vars) (@lower (DenoteClass cl) (In_CharClass_dec cl)).
Definition gepsilon(t:Set)(v:t) vars := GEpsilon (var:=vars) v.
Definition galt(t:Set)(e1 e2:Term t) vars := GAlt (e1 vars) (e2 vars).
Definition gmap(t1 t2:Set)(f:t1 -> t2)(e:Term t1) vars := GMap f (e vars).
Definition gcat(t1 t2:Set)(e1:Term t1)(e2:Term t2) vars := GCat (e1 vars) (e2 vars).
Definition gtry(t:Set)(e:Term t) vars := GTry (e vars).
Definition grec(t:Set)(f:forall (var:Set->Type), var t -> term var t)(var:Set -> Type) := GRec (f var).
Ltac myunfold := unfold ans_str_correct, ans_correct, okaystr, okay, errorstr, error,
parses, gsatisfy, gepsilon, galt, gmap, gcat, gtry, grec.
Ltac psimp := (myunfold ; sep fail auto ; mysep ; simpl ; eauto).
Ltac rsimp := psimp ;
match goal with
| [ |- context[match ?a with | OKAY c m v => _ | ERROR c _ => _ end] ] => destruct a
| [ |- context[match ?c with | Consumed => _ | NotConsumed => _ end] ] => destruct c
| _ => idtac
end.
Lemma NthError(x:list char)(n:nat) :
(nth_error x n = None \/ exists c, nth_error x n = Some c).
Proof. intros. destruct (nth_error x n). right. eauto. left. eauto.
Qed.
Lemma EvalsMReturn(t:Set)(r1 r2:reply_t t) : r1 = r2 -> evals (MReturn r1) r2.
Proof. intros. rewrite <- H. constructor. Qed.
Open Scope char_scope.
Definition bad_character := "b"::"a"::"d"::" "::"c"::"h"::"a"::"r"::"a"::"c"::"t"::"e"::"r"::nil.
(* the parser for a single character *)
Definition satisfy(f:char -> bool) : parser_t (gsatisfy f).
intros instream n.
refine (copt <- next instream n ;
Return (match copt with
| None => ERROR char NotConsumed bad_character
| Some c => if f c then OKAY Consumed 1 c
else ERROR char NotConsumed bad_character
end) <@>
match copt with
| None => errorstr n instream (gsatisfy f) NotConsumed
| Some c => if f c then okaystr n instream (gsatisfy f) Consumed 1 c
else errorstr n instream (gsatisfy f) NotConsumed
end @> _);
psimp ; solve [ sep fail auto |
match goal with
[ |- _ ==> match nth_error ?x ?n with | Some c => _ | None => _ end] =>
let H := fresh in pose (H := NthError x n) ; destruct H ; [ rewrite H ; psimp ;
rewrite (NthErrorNoneNthTail _ _ H) ; psimp | destruct H ; rewrite H ; psimp ; psimp ;
let H1 := fresh in let v1 := fresh in let v2 := fresh in
let H2 := fresh in let H3 := fresh in
pose (H1 := NthErrorSomeNthTail _ _ H) ; destruct H1 as [v1 [v2 [H1 H2]]] ;
rewrite H2 ; psimp ; pose (H3 := (NthTailSucc _ _ H2)) ;
simpl in H3 ; eapply EvalsMReturn ; congruence]
| [ |- match ?copt with | Some c => _ | None => _ end ==> _] => destruct copt ;
repeat psimp
end ].
Qed.
Definition class(cl:CharClass charset) : parser_t (gsatisfy (@lower (DenoteClass cl) (In_CharClass_dec cl))) := satisfy (@lower (DenoteClass cl) (In_CharClass_dec cl)).
(* the parser for the empty string *)
Definition epsilon(t:Set)(v:t) : parser_t (gepsilon v).
intros instream n.
refine ({{Return (OKAY NotConsumed 0 v) <@> (n ~~ rep instream n)}}) ;
repeat psimp.
Qed.
(* left-biased alternation -- need to fix error message propagation here *)
Definition alt(t:Set)(e1 e2:Term t)(p1:parser_t e1)(p2:parser_t e2) : parser_t (galt e1 e2).
intros instream n. unfold galt.
refine (n0 <- position instream n @> (fun n0 => n ~~ rep instream n * [n0=n])%hprop ;
ans1 <- p1 instream n <@> (n ~~ [n0=n])%hprop @>
(fun ans1 => ans_str_correct n instream e1 ans1 * (n ~~ [n0=n]))%hprop ;
let frame := fun ans => ((n ~~ [n0=n]) * ans_correct n instream e1 ans)%hprop in
match ans1 as ans1'
return STsep (ans_str_correct n instream e1 ans1' * (n ~~ [n0=n]))%hprop
(ans_str_correct n instream (galt e1 e2))
with
| ERROR NotConsumed msg1 =>
seek instream n0 <@> frame (ERROR t NotConsumed msg1) ;;
p2 instream n <@> frame (ERROR t NotConsumed msg1) @> _
| OKAY NotConsumed m1 v1 =>
seek instream n0 <@> frame (OKAY NotConsumed m1 v1) ;;
ans2 <- p2 instream n <@> frame (OKAY NotConsumed m1 v1) ;
match ans2 as ans2'
return STsep (frame (OKAY NotConsumed m1 v1) *
ans_str_correct n instream e2 ans2')
(ans_str_correct n instream (galt e1 e2))
with
| ERROR NotConsumed msg2 =>
(* interestingly, I forgot to do the seek here and in the next
case and then got stuck doing the proof! *)
seek instream (m1 + n0) <@>
frame (OKAY NotConsumed m1 v1) *
ans_correct n instream e2 (ERROR t NotConsumed msg2) ;;
Return OKAY NotConsumed m1 v1 <@>
frame (OKAY NotConsumed m1 v1) *
rep instream (m1 + n0) *
ans_correct n instream e2 (ERROR t NotConsumed msg2) @> _
| OKAY NotConsumed m2 v2 =>
seek instream (m1 + n0) <@>
frame (OKAY NotConsumed m1 v1) *
ans_correct n instream e2 (OKAY NotConsumed m2 v2) ;;
Return OKAY NotConsumed m1 v1 <@>
frame (OKAY NotConsumed m1 v1) *
rep instream (m1 + n0) *
ans_correct n instream e2 (OKAY NotConsumed m2 v2) @> _
| ans =>
{{Return ans <@>
frame (OKAY NotConsumed m1 v1) * ans_str_correct n instream e2 ans}}
end
| ans =>
{{Return ans <@>
((n ~~ [n0=n]) * ans_str_correct n instream e1 ans)%hprop}}
end) ;
(try unfold frame) ; repeat rsimp.
Qed.
(* the parser for (gmap f e) given f and a parser p for e *)
Definition map(t1 t2:Set)(f:t1->t2)(e:Term t1)(p:parser_t e) : parser_t (gmap f e).
intros instream n.
refine (ans <- p instream n;
Return (match ans with
| OKAY c m v => OKAY c m (f v)
| ERROR c msg => ERROR t2 c msg
end) <@> ans_str_correct n instream e ans @> _) ; psimp.
destruct ans ; repeat psimp.
Qed.
(* parser for concatenation *)
Definition cat(t1 t2:Set)(e1:Term t1)(e2:Term t2)(p1:parser_t e1)(p2:parser_t e2) :
parser_t (gcat e1 e2).
intros instream n.
refine (n0 <- position instream n ;
ans1 <- p1 instream n <@> (n ~~ [n0 = n])%hprop ;
match ans1 as ans1' return
STsep (ans_str_correct n instream e1 ans1' * (n ~~ [n0 = n])%hprop)
(ans_str_correct n instream (gcat e1 e2))
with
| OKAY c1 m1 v1 =>
ans2 <- p2 instream (inhabits (m1+n0))<@>
(ans_correct n instream e1 (OKAY c1 m1 v1) * (n ~~ [n0=n]))%hprop;
Return match ans2 with
| OKAY c2 m2 v2 => OKAY (join_cons c1 c2) (m2 + m1) (v1,v2)
| ERROR c2 msg => ERROR (t1*t2)%type (join_cons c1 c2) msg
end <@>
(ans_correct n instream e1 (OKAY c1 m1 v1) * (n ~~ [n0=n]) *
ans_str_correct (inhabits (m1+n0)) instream e2 ans2)%hprop @> _
| ERROR c1 msg =>
{{Return ERROR (t1*t2) c1 msg <@>
(ans_str_correct n instream e1 (ERROR t1 c1 msg) * (n ~~ [n0 = n]))%hprop}}
end) ; repeat rsimp.
Qed.
(* try combinator *)
Definition try(t:Set)(e:Term t)(p:parser_t e) : parser_t (gtry e).
intros instream n.
refine (ans <- p instream n ;
Return match ans with
| ERROR Consumed msg => ERROR t NotConsumed msg
| OKAY Consumed m v => OKAY NotConsumed m v
| ans => ans
end <@> ans_str_correct n instream e ans @> _) ; psimp.
destruct ans ; destruct c ; repeat psimp.
Qed.
(* used in construction of fixed-point *)
Definition coerce_parse_fn(t:Set)(f:forall var, var t -> term var t)(e:Term t)
(H1:Subst (f empvar) (GRec (f empvar)) (e empvar))
(F:parser_t (grec f) -> parser_t e) :
parser_t (grec f) -> parser_t (grec f).
intros p instream n.
refine ((F p instream n) @> _). sep fail auto. sep fail auto. destruct v ; psimp ; econstructor ; eauto.
Qed.
Definition parser_t'(t:Set)(e:Term t)(p:(instream_t char * [nat])) :=
let ins := fst p in
let n := snd p in
STsep (n ~~ rep ins n) (ans_str_correct n ins e).
Open Local Scope stsepi_scope.
(* Alas, note that we need H here -- can't easily prove this once and for all *)
Definition Gfix(t:Set)(f:forall V, V t -> term V t)
(F:parser_t (grec f) -> parser_t (unroll f))
(H: Subst (f empvar) (GRec (f empvar)) (unroll f empvar)) :
parser_t (grec f) :=
(* coerce F so that its result is re-rolled *)
let Fc : parser_t (grec f) -> parser_t (grec f) := coerce_parse_fn H F in
Fix2 _ _ Fc.
Implicit Arguments Gfix [t f].
End CHARSET.
Module ParsecNotation.
Delimit Scope grammar_scope with grammar.
Notation "!!!! v" := (@GVar _ _ _ v) (at level 1) : grammar_scope.
Notation "# c" := (@GSatisfy AsciiCharset _
(fun c2 => if ascii_dec (c)%char c2 then true else false)) (at level 1) : grammar_scope.
Notation "e1 ^ e2" := (GCat e1 e2)
(right associativity, at level 30) : grammar_scope.
Notation "e @ f" := (GMap f e)
(left associativity, at level 78) : grammar_scope.
Notation "e1 '|||' e2" := (GAlt e1 e2)
(right associativity, at level 79) : grammar_scope.
Notation "% v" := (@GEpsilon _ _ _ v) (at level 1) : grammar_scope.
Delimit Scope parser_scope with parser.
Notation "e1 ^ e2" := (cat e1 e2)
(right associativity, at level 30) : parser_scope.
Notation "e @ f" := (map f e)
(left associativity, at level 78) : parser_scope.
Notation "e1 '|||' e2" := (alt e1 e2)
(right associativity, at level 79) : parser_scope.
Notation "# c" := (satisfy AsciiCharset (fun c2 => if ascii_dec (c%char) c2 then true else false))
(at level 1) : parser_scope.
Notation "% v" := (epsilon _ v) : parser_scope.
Notation "'gfix' e" := (Gfix e _) (at level 70).
Ltac gtac := unfold unroll, gclass, grec ; simpl ; repeat (progress constructor).
End ParsecNotation.
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:41:24 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_system_ila_0_stub.v
// Design : zynq_design_1_system_ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "bd_350b,Vivado 2017.2" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, SLOT_0_AXI_awaddr, SLOT_0_AXI_awvalid,
SLOT_0_AXI_awready, SLOT_0_AXI_wdata, SLOT_0_AXI_wstrb, SLOT_0_AXI_wvalid,
SLOT_0_AXI_wready, SLOT_0_AXI_bresp, SLOT_0_AXI_bvalid, SLOT_0_AXI_bready,
SLOT_0_AXI_araddr, SLOT_0_AXI_arvalid, SLOT_0_AXI_arready, SLOT_0_AXI_rdata,
SLOT_0_AXI_rresp, SLOT_0_AXI_rvalid, SLOT_0_AXI_rready, SLOT_1_GPIO_tri_o,
SLOT_2_AXI_awid, SLOT_2_AXI_awaddr, SLOT_2_AXI_awlen, SLOT_2_AXI_awsize,
SLOT_2_AXI_awburst, SLOT_2_AXI_awlock, SLOT_2_AXI_awcache, SLOT_2_AXI_awprot,
SLOT_2_AXI_awqos, SLOT_2_AXI_awvalid, SLOT_2_AXI_awready, SLOT_2_AXI_wdata,
SLOT_2_AXI_wstrb, SLOT_2_AXI_wlast, SLOT_2_AXI_wvalid, SLOT_2_AXI_wready, SLOT_2_AXI_bid,
SLOT_2_AXI_bresp, SLOT_2_AXI_bvalid, SLOT_2_AXI_bready, SLOT_2_AXI_arid,
SLOT_2_AXI_araddr, SLOT_2_AXI_arlen, SLOT_2_AXI_arsize, SLOT_2_AXI_arburst,
SLOT_2_AXI_arlock, SLOT_2_AXI_arcache, SLOT_2_AXI_arprot, SLOT_2_AXI_arqos,
SLOT_2_AXI_arvalid, SLOT_2_AXI_arready, SLOT_2_AXI_rid, SLOT_2_AXI_rdata,
SLOT_2_AXI_rresp, SLOT_2_AXI_rlast, SLOT_2_AXI_rvalid, SLOT_2_AXI_rready, resetn,
TRIG_IN_trig, TRIG_IN_ack, TRIG_OUT_trig, TRIG_OUT_ack)
/* synthesis syn_black_box black_box_pad_pin="clk,SLOT_0_AXI_awaddr[8:0],SLOT_0_AXI_awvalid,SLOT_0_AXI_awready,SLOT_0_AXI_wdata[31:0],SLOT_0_AXI_wstrb[3:0],SLOT_0_AXI_wvalid,SLOT_0_AXI_wready,SLOT_0_AXI_bresp[1:0],SLOT_0_AXI_bvalid,SLOT_0_AXI_bready,SLOT_0_AXI_araddr[8:0],SLOT_0_AXI_arvalid,SLOT_0_AXI_arready,SLOT_0_AXI_rdata[31:0],SLOT_0_AXI_rresp[1:0],SLOT_0_AXI_rvalid,SLOT_0_AXI_rready,SLOT_1_GPIO_tri_o[7:0],SLOT_2_AXI_awid[11:0],SLOT_2_AXI_awaddr[15:0],SLOT_2_AXI_awlen[7:0],SLOT_2_AXI_awsize[2:0],SLOT_2_AXI_awburst[1:0],SLOT_2_AXI_awlock[0:0],SLOT_2_AXI_awcache[3:0],SLOT_2_AXI_awprot[2:0],SLOT_2_AXI_awqos[3:0],SLOT_2_AXI_awvalid,SLOT_2_AXI_awready,SLOT_2_AXI_wdata[31:0],SLOT_2_AXI_wstrb[3:0],SLOT_2_AXI_wlast,SLOT_2_AXI_wvalid,SLOT_2_AXI_wready,SLOT_2_AXI_bid[11:0],SLOT_2_AXI_bresp[1:0],SLOT_2_AXI_bvalid,SLOT_2_AXI_bready,SLOT_2_AXI_arid[11:0],SLOT_2_AXI_araddr[15:0],SLOT_2_AXI_arlen[7:0],SLOT_2_AXI_arsize[2:0],SLOT_2_AXI_arburst[1:0],SLOT_2_AXI_arlock[0:0],SLOT_2_AXI_arcache[3:0],SLOT_2_AXI_arprot[2:0],SLOT_2_AXI_arqos[3:0],SLOT_2_AXI_arvalid,SLOT_2_AXI_arready,SLOT_2_AXI_rid[11:0],SLOT_2_AXI_rdata[31:0],SLOT_2_AXI_rresp[1:0],SLOT_2_AXI_rlast,SLOT_2_AXI_rvalid,SLOT_2_AXI_rready,resetn,TRIG_IN_trig[0:0],TRIG_IN_ack[0:0],TRIG_OUT_trig[0:0],TRIG_OUT_ack[0:0]" */;
input clk;
input [8:0]SLOT_0_AXI_awaddr;
input SLOT_0_AXI_awvalid;
input SLOT_0_AXI_awready;
input [31:0]SLOT_0_AXI_wdata;
input [3:0]SLOT_0_AXI_wstrb;
input SLOT_0_AXI_wvalid;
input SLOT_0_AXI_wready;
input [1:0]SLOT_0_AXI_bresp;
input SLOT_0_AXI_bvalid;
input SLOT_0_AXI_bready;
input [8:0]SLOT_0_AXI_araddr;
input SLOT_0_AXI_arvalid;
input SLOT_0_AXI_arready;
input [31:0]SLOT_0_AXI_rdata;
input [1:0]SLOT_0_AXI_rresp;
input SLOT_0_AXI_rvalid;
input SLOT_0_AXI_rready;
input [7:0]SLOT_1_GPIO_tri_o;
input [11:0]SLOT_2_AXI_awid;
input [15:0]SLOT_2_AXI_awaddr;
input [7:0]SLOT_2_AXI_awlen;
input [2:0]SLOT_2_AXI_awsize;
input [1:0]SLOT_2_AXI_awburst;
input [0:0]SLOT_2_AXI_awlock;
input [3:0]SLOT_2_AXI_awcache;
input [2:0]SLOT_2_AXI_awprot;
input [3:0]SLOT_2_AXI_awqos;
input SLOT_2_AXI_awvalid;
input SLOT_2_AXI_awready;
input [31:0]SLOT_2_AXI_wdata;
input [3:0]SLOT_2_AXI_wstrb;
input SLOT_2_AXI_wlast;
input SLOT_2_AXI_wvalid;
input SLOT_2_AXI_wready;
input [11:0]SLOT_2_AXI_bid;
input [1:0]SLOT_2_AXI_bresp;
input SLOT_2_AXI_bvalid;
input SLOT_2_AXI_bready;
input [11:0]SLOT_2_AXI_arid;
input [15:0]SLOT_2_AXI_araddr;
input [7:0]SLOT_2_AXI_arlen;
input [2:0]SLOT_2_AXI_arsize;
input [1:0]SLOT_2_AXI_arburst;
input [0:0]SLOT_2_AXI_arlock;
input [3:0]SLOT_2_AXI_arcache;
input [2:0]SLOT_2_AXI_arprot;
input [3:0]SLOT_2_AXI_arqos;
input SLOT_2_AXI_arvalid;
input SLOT_2_AXI_arready;
input [11:0]SLOT_2_AXI_rid;
input [31:0]SLOT_2_AXI_rdata;
input [1:0]SLOT_2_AXI_rresp;
input SLOT_2_AXI_rlast;
input SLOT_2_AXI_rvalid;
input SLOT_2_AXI_rready;
input resetn;
input [0:0]TRIG_IN_trig;
output [0:0]TRIG_IN_ack;
output [0:0]TRIG_OUT_trig;
input [0:0]TRIG_OUT_ack;
endmodule
|
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module alt_mem_ddrx_rank_timer #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
CFG_MEM_IF_CHIP = 1,
CFG_MEM_IF_CS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 4,
CFG_AFI_INTF_PHASE_NUM = 2,
CFG_REG_GRANT = 0,
CFG_RANK_TIMER_OUTPUT_REG = 0,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 0,
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 0,
T_PARAM_WR_TO_WR_WIDTH = 0,
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 0,
T_PARAM_WR_TO_RD_WIDTH = 0,
T_PARAM_WR_TO_RD_BC_WIDTH = 0,
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_RD_WIDTH = 0,
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 0,
T_PARAM_RD_TO_WR_WIDTH = 0,
T_PARAM_RD_TO_WR_BC_WIDTH = 0,
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 0
)
(
ctl_clk,
ctl_reset_n,
// MMR Configurations
cfg_burst_length,
// Timing parameters
t_param_four_act_to_act,
t_param_act_to_act_diff_bank,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
// Arbiter Interface
bg_do_write,
bg_do_read,
bg_do_burst_chop,
bg_do_burst_terminate,
bg_do_activate,
bg_do_precharge,
bg_to_chip,
bg_effective_size,
bg_interrupt_ready,
// Command Generator Interface
cmd_gen_chipsel,
// TBP Interface
tbp_chipsel,
tbp_load,
// Sideband Interface
stall_chip,
can_activate,
can_precharge,
can_read,
can_write
);
input ctl_clk;
input ctl_reset_n;
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
input [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
input [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
input [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
input [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
input [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
input [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
input [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
input [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
input [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
input [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
input [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_write;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_read;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_chop;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_burst_terminate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_activate;
input [CFG_AFI_INTF_PHASE_NUM - 1 : 0] bg_do_precharge;
input [(CFG_AFI_INTF_PHASE_NUM * CFG_MEM_IF_CHIP) - 1 : 0] bg_to_chip;
input [CFG_INT_SIZE_WIDTH - 1 : 0] bg_effective_size;
input bg_interrupt_ready;
input [CFG_MEM_IF_CS_WIDTH - 1 : 0] cmd_gen_chipsel;
input [(CFG_CTL_TBP_NUM * CFG_MEM_IF_CS_WIDTH) - 1 : 0] tbp_chipsel;
input [CFG_CTL_TBP_NUM - 1 : 0] tbp_load;
input [CFG_MEM_IF_CHIP - 1 : 0] stall_chip;
output [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
output [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
output [CFG_CTL_TBP_NUM - 1 : 0] can_read;
output [CFG_CTL_TBP_NUM - 1 : 0] can_write;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// General
localparam RANK_TIMER_COUNTER_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 4 : 3) : ((CFG_REG_GRANT) ? 3 : 2);
localparam RANK_TIMER_TFAW_OFFSET = (CFG_RANK_TIMER_OUTPUT_REG) ? ((CFG_REG_GRANT) ? 2 : 1) : ((CFG_REG_GRANT) ? 1 : 0);
localparam ENABLE_BETTER_TRRD_EFFICIENCY = 1; // ONLY set to '1' when CFG_RANK_TIMER_OUTPUT_REG is enabled, else it will fail
wire one = 1'b1;
wire zero = 1'b0;
// Timing Parameter Comparison Logic
reg less_than_1_act_to_act_diff_bank;
reg less_than_2_act_to_act_diff_bank;
reg less_than_3_act_to_act_diff_bank;
reg less_than_4_act_to_act_diff_bank;
reg less_than_4_four_act_to_act;
reg less_than_1_rd_to_rd;
reg less_than_1_rd_to_wr;
reg less_than_1_wr_to_wr;
reg less_than_1_wr_to_rd;
reg less_than_1_rd_to_wr_bc;
reg less_than_1_wr_to_rd_bc;
reg less_than_1_rd_to_rd_diff_chip;
reg less_than_1_rd_to_wr_diff_chip;
reg less_than_1_wr_to_wr_diff_chip;
reg less_than_1_wr_to_rd_diff_chip;
reg less_than_2_rd_to_rd;
reg less_than_2_rd_to_wr;
reg less_than_2_wr_to_wr;
reg less_than_2_wr_to_rd;
reg less_than_2_rd_to_wr_bc;
reg less_than_2_wr_to_rd_bc;
reg less_than_2_rd_to_rd_diff_chip;
reg less_than_2_rd_to_wr_diff_chip;
reg less_than_2_wr_to_wr_diff_chip;
reg less_than_2_wr_to_rd_diff_chip;
reg less_than_3_rd_to_rd;
reg less_than_3_rd_to_wr;
reg less_than_3_wr_to_wr;
reg less_than_3_wr_to_rd;
reg less_than_3_rd_to_wr_bc;
reg less_than_3_wr_to_rd_bc;
reg less_than_3_rd_to_rd_diff_chip;
reg less_than_3_rd_to_wr_diff_chip;
reg less_than_3_wr_to_wr_diff_chip;
reg less_than_3_wr_to_rd_diff_chip;
reg less_than_4_rd_to_rd;
reg less_than_4_rd_to_wr;
reg less_than_4_wr_to_wr;
reg less_than_4_wr_to_rd;
reg less_than_4_rd_to_wr_bc;
reg less_than_4_wr_to_rd_bc;
reg less_than_4_rd_to_rd_diff_chip;
reg less_than_4_rd_to_wr_diff_chip;
reg less_than_4_wr_to_wr_diff_chip;
reg less_than_4_wr_to_rd_diff_chip;
reg more_than_3_rd_to_rd;
reg more_than_3_rd_to_wr;
reg more_than_3_wr_to_wr;
reg more_than_3_wr_to_rd;
reg more_than_3_rd_to_wr_bc;
reg more_than_3_wr_to_rd_bc;
reg more_than_3_rd_to_rd_diff_chip;
reg more_than_3_rd_to_wr_diff_chip;
reg more_than_3_wr_to_wr_diff_chip;
reg more_than_3_wr_to_rd_diff_chip;
reg less_than_xn1_act_to_act_diff_bank;
reg less_than_xn1_rd_to_rd;
reg less_than_xn1_rd_to_wr;
reg less_than_xn1_wr_to_wr;
reg less_than_xn1_wr_to_rd;
reg less_than_xn1_rd_to_wr_bc;
reg less_than_xn1_wr_to_rd_bc;
reg less_than_xn1_rd_to_rd_diff_chip;
reg less_than_xn1_rd_to_wr_diff_chip;
reg less_than_xn1_wr_to_wr_diff_chip;
reg less_than_xn1_wr_to_rd_diff_chip;
reg less_than_x0_act_to_act_diff_bank;
reg less_than_x0_rd_to_rd;
reg less_than_x0_rd_to_wr;
reg less_than_x0_wr_to_wr;
reg less_than_x0_wr_to_rd;
reg less_than_x0_rd_to_wr_bc;
reg less_than_x0_wr_to_rd_bc;
reg less_than_x0_rd_to_rd_diff_chip;
reg less_than_x0_rd_to_wr_diff_chip;
reg less_than_x0_wr_to_wr_diff_chip;
reg less_than_x0_wr_to_rd_diff_chip;
reg less_than_x1_act_to_act_diff_bank;
reg less_than_x1_rd_to_rd;
reg less_than_x1_rd_to_wr;
reg less_than_x1_wr_to_wr;
reg less_than_x1_wr_to_rd;
reg less_than_x1_rd_to_wr_bc;
reg less_than_x1_wr_to_rd_bc;
reg less_than_x1_rd_to_rd_diff_chip;
reg less_than_x1_rd_to_wr_diff_chip;
reg less_than_x1_wr_to_wr_diff_chip;
reg less_than_x1_wr_to_rd_diff_chip;
// Input
reg int_do_activate;
reg int_do_precharge;
reg int_do_burst_chop;
reg int_do_burst_terminate;
reg int_do_write;
reg int_do_read;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_r;
reg [CFG_MEM_IF_CHIP - 1 : 0] int_to_chip_c;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] int_effective_size;
reg int_interrupt_ready;
// Activate Monitor
localparam ACTIVATE_COUNTER_WIDTH = T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH;
localparam ACTIVATE_COMMAND_WIDTH = 3;
localparam NUM_OF_TFAW_SHIFT_REG = 2 ** T_PARAM_FOUR_ACT_TO_ACT_WIDTH;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_tfaw_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_trrd_ready_combi;
reg [CFG_MEM_IF_CHIP - 1 : 0] act_ready;
wire [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_count [CFG_MEM_IF_CHIP - 1 : 0];
// Read/Write Monitor
localparam IDLE = 32'h49444C45;
localparam WR = 32'h20205752;
localparam RD = 32'h20205244;
localparam RDWR_COUNTER_WIDTH = (T_PARAM_RD_TO_WR_WIDTH > T_PARAM_WR_TO_RD_WIDTH) ? T_PARAM_RD_TO_WR_WIDTH : T_PARAM_WR_TO_RD_WIDTH;
reg [CFG_INT_SIZE_WIDTH - 1 : 0] max_local_burst_size;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr_combi;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip_combi;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd_combi;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip_combi;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] effective_rd_to_wr;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] effective_rd_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] effective_wr_to_rd;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] effective_wr_to_rd_diff_chip;
reg [CFG_MEM_IF_CHIP - 1 : 0] read_ready;
reg [CFG_MEM_IF_CHIP - 1 : 0] write_ready;
// Precharge Monitor
reg [CFG_MEM_IF_CHIP - 1 : 0] pch_ready;
// Output
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] int_can_write;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_activate;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_precharge;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_read;
reg [CFG_CTL_TBP_NUM - 1 : 0] can_write;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] sel_act_tfaw_shift_out_point;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Input
//
//--------------------------------------------------------------------------------------------------------
// Do activate
always @ (*)
begin
int_do_activate = |bg_do_activate;
end
// Do precharge
always @ (*)
begin
int_do_precharge = |bg_do_precharge;
end
//Do burst chop
always @ (*)
begin
int_do_burst_chop = |bg_do_burst_chop;
end
//Do burst terminate
always @ (*)
begin
int_do_burst_terminate = |bg_do_burst_terminate;
end
// Do write
always @ (*)
begin
int_do_write = |bg_do_write;
end
// Do read
always @ (*)
begin
int_do_read = |bg_do_read;
end
// To chip
always @ (*)
begin
// _r for row command and _c for column command
if (CFG_CTL_ARBITER_TYPE == "COLROW")
begin
int_to_chip_c = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_r = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
else if (CFG_CTL_ARBITER_TYPE == "ROWCOL")
begin
int_to_chip_r = bg_to_chip [CFG_MEM_IF_CHIP - 1 : 0 ];
int_to_chip_c = bg_to_chip [2 * CFG_MEM_IF_CHIP - 1 : CFG_MEM_IF_CHIP];
end
end
// Effective size
always @ (*)
begin
int_effective_size = bg_effective_size;
end
// Interrupt ready
always @ (*)
begin
int_interrupt_ready = bg_interrupt_ready;
end
//--------------------------------------------------------------------------------------------------------
//
// [END] Input
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Output
//
//--------------------------------------------------------------------------------------------------------
generate
genvar x_cs;
for (x_cs = 0; x_cs < CFG_CTL_TBP_NUM;x_cs = x_cs + 1)
begin : can_logic_per_chip
reg [CFG_MEM_IF_CS_WIDTH - 1 : 0] chip_addr;
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG && tbp_load [x_cs])
begin
chip_addr = cmd_gen_chipsel;
end
else
begin
chip_addr = tbp_chipsel [(x_cs + 1) * CFG_MEM_IF_CS_WIDTH - 1 : x_cs * CFG_MEM_IF_CS_WIDTH];
end
end
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
always @ (*)
begin
can_activate [x_cs] = int_can_activate [x_cs] ;
can_precharge [x_cs] = int_can_precharge [x_cs] ;
can_read [x_cs] = int_can_read [x_cs] & int_interrupt_ready;
can_write [x_cs] = int_can_write [x_cs] & int_interrupt_ready;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_activate [x_cs] <= 1'b0;
end
else if (int_do_activate && int_to_chip_r [chip_addr] && !ENABLE_BETTER_TRRD_EFFICIENCY)
begin
int_can_activate [x_cs] <= 1'b0;
end
else
begin
int_can_activate [x_cs] <= act_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_precharge [x_cs] <= 1'b0;
end
else
begin
int_can_precharge [x_cs] <= pch_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_read [x_cs] <= 1'b0;
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_wr_to_rd_bc)
begin
int_can_read [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_wr_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_rd_to_rd)
begin
int_can_read [x_cs] <= 1'b0;
end
else
begin
int_can_read [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_read [x_cs] <= 1'b0;
end
end
else
begin
int_can_read [x_cs] <= read_ready [chip_addr];
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
if (stall_chip [chip_addr])
begin
int_can_write [x_cs] <= 1'b0;
end
else if (int_do_read)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (int_do_burst_chop && more_than_3_rd_to_wr_bc)
begin
int_can_write [x_cs] <= 1'b0;
end
else if (!int_do_burst_chop && more_than_3_rd_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else if (int_do_write)
begin
if (int_to_chip_c [chip_addr]) // to same chip addr as compared to current TBP
begin
if (more_than_3_wr_to_wr)
begin
int_can_write [x_cs] <= 1'b0;
end
else
begin
int_can_write [x_cs] <= 1'b1;
end
end
else // to other chip addr as compared to current TBP
begin
int_can_write [x_cs] <= 1'b0;
end
end
else
begin
int_can_write [x_cs] <= write_ready [chip_addr];
end
end
end
end
else
begin
// Can activate
always @ (*)
begin
can_activate [x_cs] = act_ready [chip_addr];
end
// Can precharge
always @ (*)
begin
can_precharge [x_cs] = pch_ready [chip_addr];
end
// Can read
always @ (*)
begin
can_read [x_cs] = read_ready [chip_addr];
end
// Can write
always @ (*)
begin
can_write [x_cs] = write_ready [chip_addr];
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Output
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 1)
less_than_1_act_to_act_diff_bank <= 1'b1;
else
less_than_1_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 2)
less_than_2_act_to_act_diff_bank <= 1'b1;
else
less_than_2_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 3)
less_than_3_act_to_act_diff_bank <= 1'b1;
else
less_than_3_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_act_to_act_diff_bank <= 1'b0;
end
else
begin
if (t_param_act_to_act_diff_bank <= 4)
less_than_4_act_to_act_diff_bank <= 1'b1;
else
less_than_4_act_to_act_diff_bank <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_four_act_to_act <= 1'b0;
end
else
begin
if (t_param_four_act_to_act <= 4)
less_than_4_four_act_to_act <= 1'b1;
else
less_than_4_four_act_to_act <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 1)
less_than_1_rd_to_rd <= 1'b1;
else
less_than_1_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 1)
less_than_1_rd_to_wr <= 1'b1;
else
less_than_1_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 1)
less_than_1_wr_to_wr <= 1'b1;
else
less_than_1_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 1)
less_than_1_wr_to_rd <= 1'b1;
else
less_than_1_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 1)
less_than_1_rd_to_wr_bc <= 1'b1;
else
less_than_1_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 1)
less_than_1_wr_to_rd_bc <= 1'b1;
else
less_than_1_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 1)
less_than_1_rd_to_rd_diff_chip <= 1'b1;
else
less_than_1_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 1)
less_than_1_rd_to_wr_diff_chip <= 1'b1;
else
less_than_1_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 1)
less_than_1_wr_to_wr_diff_chip <= 1'b1;
else
less_than_1_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 1)
less_than_1_wr_to_rd_diff_chip <= 1'b1;
else
less_than_1_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 2)
less_than_2_rd_to_rd <= 1'b1;
else
less_than_2_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 2)
less_than_2_rd_to_wr <= 1'b1;
else
less_than_2_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 2)
less_than_2_wr_to_wr <= 1'b1;
else
less_than_2_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 2)
less_than_2_wr_to_rd <= 1'b1;
else
less_than_2_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 2)
less_than_2_rd_to_wr_bc <= 1'b1;
else
less_than_2_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 2)
less_than_2_wr_to_rd_bc <= 1'b1;
else
less_than_2_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 2)
less_than_2_rd_to_rd_diff_chip <= 1'b1;
else
less_than_2_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 2)
less_than_2_rd_to_wr_diff_chip <= 1'b1;
else
less_than_2_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 2)
less_than_2_wr_to_wr_diff_chip <= 1'b1;
else
less_than_2_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 2)
less_than_2_wr_to_rd_diff_chip <= 1'b1;
else
less_than_2_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 3)
less_than_3_rd_to_rd <= 1'b1;
else
less_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 3)
less_than_3_rd_to_wr <= 1'b1;
else
less_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 3)
less_than_3_wr_to_wr <= 1'b1;
else
less_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 3)
less_than_3_wr_to_rd <= 1'b1;
else
less_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 3)
less_than_3_rd_to_wr_bc <= 1'b1;
else
less_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 3)
less_than_3_wr_to_rd_bc <= 1'b1;
else
less_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 3)
less_than_3_rd_to_rd_diff_chip <= 1'b1;
else
less_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 3)
less_than_3_rd_to_wr_diff_chip <= 1'b1;
else
less_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 3)
less_than_3_wr_to_wr_diff_chip <= 1'b1;
else
less_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 3)
less_than_3_wr_to_rd_diff_chip <= 1'b1;
else
less_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd <= 4)
less_than_4_rd_to_rd <= 1'b1;
else
less_than_4_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr <= 4)
less_than_4_rd_to_wr <= 1'b1;
else
less_than_4_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr <= 4)
less_than_4_wr_to_wr <= 1'b1;
else
less_than_4_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd <= 4)
less_than_4_wr_to_rd <= 1'b1;
else
less_than_4_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc <= 4)
less_than_4_rd_to_wr_bc <= 1'b1;
else
less_than_4_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc <= 4)
less_than_4_wr_to_rd_bc <= 1'b1;
else
less_than_4_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip <= 4)
less_than_4_rd_to_rd_diff_chip <= 1'b1;
else
less_than_4_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip <= 4)
less_than_4_rd_to_wr_diff_chip <= 1'b1;
else
less_than_4_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip <= 4)
less_than_4_wr_to_wr_diff_chip <= 1'b1;
else
less_than_4_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip <= 4)
less_than_4_wr_to_rd_diff_chip <= 1'b1;
else
less_than_4_wr_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd <= 1'b0;
end
else
begin
if (t_param_rd_to_rd >= 3)
more_than_3_rd_to_rd <= 1'b1;
else
more_than_3_rd_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr <= 1'b0;
end
else
begin
if (t_param_rd_to_wr >= 3)
more_than_3_rd_to_wr <= 1'b1;
else
more_than_3_rd_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr <= 1'b0;
end
else
begin
if (t_param_wr_to_wr >= 3)
more_than_3_wr_to_wr <= 1'b1;
else
more_than_3_wr_to_wr <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd <= 1'b0;
end
else
begin
if (t_param_wr_to_rd >= 3)
more_than_3_wr_to_rd <= 1'b1;
else
more_than_3_wr_to_rd <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_bc <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_bc >= 3)
more_than_3_rd_to_wr_bc <= 1'b1;
else
more_than_3_rd_to_wr_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_bc <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_bc >= 3)
more_than_3_wr_to_rd_bc <= 1'b1;
else
more_than_3_wr_to_rd_bc <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_rd_diff_chip >= 3)
more_than_3_rd_to_rd_diff_chip <= 1'b1;
else
more_than_3_rd_to_rd_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_rd_to_wr_diff_chip >= 3)
more_than_3_rd_to_wr_diff_chip <= 1'b1;
else
more_than_3_rd_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_wr_diff_chip >= 3)
more_than_3_wr_to_wr_diff_chip <= 1'b1;
else
more_than_3_wr_to_wr_diff_chip <= 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
if (t_param_wr_to_rd_diff_chip >= 3)
more_than_3_wr_to_rd_diff_chip <= 1'b1;
else
more_than_3_wr_to_rd_diff_chip <= 1'b0;
end
end
generate
begin
if (CFG_REG_GRANT)
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_3_rd_to_rd;
less_than_x0_rd_to_wr = less_than_3_rd_to_wr;
less_than_x0_wr_to_wr = less_than_3_wr_to_wr;
less_than_x0_wr_to_rd = less_than_3_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_4_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_4_rd_to_rd;
less_than_x1_rd_to_wr = less_than_4_rd_to_wr;
less_than_x1_wr_to_wr = less_than_4_wr_to_wr;
less_than_x1_wr_to_rd = less_than_4_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_4_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_4_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_4_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_4_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_4_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_4_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_2_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_2_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_2_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_2_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
end
end
else
begin
always @ (*)
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_2_rd_to_rd;
less_than_x0_rd_to_wr = less_than_2_rd_to_wr;
less_than_x0_wr_to_wr = less_than_2_wr_to_wr;
less_than_x0_wr_to_rd = less_than_2_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_3_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_3_rd_to_rd;
less_than_x1_rd_to_wr = less_than_3_rd_to_wr;
less_than_x1_wr_to_wr = less_than_3_wr_to_wr;
less_than_x1_wr_to_rd = less_than_3_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_3_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_3_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_3_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_3_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_3_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_3_wr_to_rd_diff_chip;
end
else
begin
// Doesn't matter for less_than_xn1_* if CFG_RANK_TIMER_OUTPUT_REG is '0'
less_than_xn1_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_xn1_rd_to_rd = less_than_1_rd_to_rd;
less_than_xn1_rd_to_wr = less_than_1_rd_to_wr;
less_than_xn1_wr_to_wr = less_than_1_wr_to_wr;
less_than_xn1_wr_to_rd = less_than_1_wr_to_rd;
less_than_xn1_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_xn1_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_xn1_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_xn1_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_xn1_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_xn1_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x0_act_to_act_diff_bank = less_than_1_act_to_act_diff_bank;
less_than_x0_rd_to_rd = less_than_1_rd_to_rd;
less_than_x0_rd_to_wr = less_than_1_rd_to_wr;
less_than_x0_wr_to_wr = less_than_1_wr_to_wr;
less_than_x0_wr_to_rd = less_than_1_wr_to_rd;
less_than_x0_rd_to_wr_bc = less_than_1_rd_to_wr_bc;
less_than_x0_wr_to_rd_bc = less_than_1_wr_to_rd_bc;
less_than_x0_rd_to_rd_diff_chip = less_than_1_rd_to_rd_diff_chip;
less_than_x0_rd_to_wr_diff_chip = less_than_1_rd_to_wr_diff_chip;
less_than_x0_wr_to_wr_diff_chip = less_than_1_wr_to_wr_diff_chip;
less_than_x0_wr_to_rd_diff_chip = less_than_1_wr_to_rd_diff_chip;
less_than_x1_act_to_act_diff_bank = less_than_2_act_to_act_diff_bank;
less_than_x1_rd_to_rd = less_than_2_rd_to_rd;
less_than_x1_rd_to_wr = less_than_2_rd_to_wr;
less_than_x1_wr_to_wr = less_than_2_wr_to_wr;
less_than_x1_wr_to_rd = less_than_2_wr_to_rd;
less_than_x1_rd_to_wr_bc = less_than_2_rd_to_wr_bc;
less_than_x1_wr_to_rd_bc = less_than_2_wr_to_rd_bc;
less_than_x1_rd_to_rd_diff_chip = less_than_2_rd_to_rd_diff_chip;
less_than_x1_rd_to_wr_diff_chip = less_than_2_rd_to_wr_diff_chip;
less_than_x1_wr_to_wr_diff_chip = less_than_2_wr_to_wr_diff_chip;
less_than_x1_wr_to_rd_diff_chip = less_than_2_wr_to_rd_diff_chip;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Comparison Logic
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Activate Monitor
//
// Monitors the following rank timing parameters:
//
// - tFAW, four activate window, only four activate is allowed in a specific timing window
// - tRRD, activate to activate different bank
//
//--------------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
sel_act_tfaw_shift_out_point <= 0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET + 1;
end
else
begin
sel_act_tfaw_shift_out_point <= t_param_four_act_to_act - RANK_TIMER_TFAW_OFFSET;
end
end
end
generate
genvar t_cs;
genvar t_tfaw;
for (t_cs = 0;t_cs < CFG_MEM_IF_CHIP;t_cs = t_cs + 1)
begin : act_monitor_per_chip
//----------------------------------------------------------------------------------------------------
// tFAW Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COMMAND_WIDTH - 1 : 0] act_tfaw_cmd_cnt;
reg [NUM_OF_TFAW_SHIFT_REG - 1 : 0] act_tfaw_shift_reg;
assign act_tfaw_cmd_count [t_cs] = act_tfaw_cmd_cnt;
// Shift register to keep track of tFAW
// Shift in -> n, n-1, n-2, n-3.......4, 3 -> Shift out
// Shift in '1' when there is an activate else shift in '0'
// Shift out every clock cycles
// Shift register [3]
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [3] <= 1'b0;
end
else
begin
// Shift in '1' if there is an activate
// else shift in '0'
if (int_do_activate && int_to_chip_r [t_cs])
act_tfaw_shift_reg [3] <= 1'b1;
else
act_tfaw_shift_reg [3] <= 1'b0;
end
end
// Shift register [n : 3]
for (t_tfaw = 4;t_tfaw < NUM_OF_TFAW_SHIFT_REG;t_tfaw = t_tfaw + 1)
begin : tfaw_shift_register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_shift_reg [t_tfaw] <= 1'b0;
end
else
begin
act_tfaw_shift_reg [t_tfaw] <= act_tfaw_shift_reg [t_tfaw - 1];
end
end
end
// Activate command counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_cmd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt;
else
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt + 1'b1;
end
else if (act_tfaw_shift_reg [sel_act_tfaw_shift_out_point]) // Shift out when activate reaches tFAW point in shift register
act_tfaw_cmd_cnt <= act_tfaw_cmd_cnt - 1'b1;
end
end
// tFAW ready signal
always @ (*)
begin
// If tFAW is lesser than 4, this means we can do back-to-back activate without tFAW constraint
if (less_than_4_four_act_to_act)
begin
act_tfaw_ready_combi [t_cs] = 1'b1;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs] && act_tfaw_cmd_cnt == 3'd3)
act_tfaw_ready_combi [t_cs] = 1'b0;
else if (act_tfaw_cmd_cnt < 3'd4)
act_tfaw_ready_combi [t_cs] = 1'b1;
else
act_tfaw_ready_combi [t_cs] = 1'b0;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_tfaw_ready [t_cs] <= 1'b0;
end
else
begin
act_tfaw_ready [t_cs] <= act_tfaw_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// tRRD Monitor
//----------------------------------------------------------------------------------------------------
reg [ACTIVATE_COUNTER_WIDTH - 1 : 0] act_trrd_cnt;
// tRRD counter
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_cnt <= 0;
end
else
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET - 1;
end
else
begin
act_trrd_cnt <= RANK_TIMER_COUNTER_OFFSET;
end
end
else if (act_trrd_cnt != {ACTIVATE_COUNTER_WIDTH{1'b1}})
begin
act_trrd_cnt <= act_trrd_cnt + 1'b1;
end
end
end
// tRRD monitor
always @ (*)
begin
if (int_do_activate && int_to_chip_r [t_cs])
begin
if (!ENABLE_BETTER_TRRD_EFFICIENCY && less_than_x0_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else if (ENABLE_BETTER_TRRD_EFFICIENCY && less_than_xn1_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
else if (act_trrd_cnt >= t_param_act_to_act_diff_bank)
act_trrd_ready_combi [t_cs] = 1'b1;
else
act_trrd_ready_combi [t_cs] = 1'b0;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
act_trrd_ready [t_cs] <= 1'b0;
end
else
begin
act_trrd_ready [t_cs] <= act_trrd_ready_combi [t_cs];
end
end
//----------------------------------------------------------------------------------------------------
// Overall activate ready
//----------------------------------------------------------------------------------------------------
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [t_cs])
begin
act_ready [t_cs] = 1'b0;
end
else
begin
if (ENABLE_BETTER_TRRD_EFFICIENCY)
begin
act_ready [t_cs] = act_trrd_ready_combi [t_cs] & act_tfaw_ready_combi [t_cs];
end
else
begin
act_ready [t_cs] = act_trrd_ready [t_cs] & act_tfaw_ready [t_cs];
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Activate Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Read/Write Monitor
//
// Monitors the following rank timing parameters:
//
// - Write to read timing parameter (tWTR)
// - Read to write timing parameter
//
// Missing Features:
//
// - Burst interrupt
// - Burst terminate
//
//--------------------------------------------------------------------------------------------------------
//----------------------------------------------------------------------------------------------------
// Effective Timing Parameters
// Only when burst interrupt option is enabled
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
max_local_burst_size <= 0;
end
else
begin
max_local_burst_size <= cfg_burst_length / CFG_DWIDTH_RATIO;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
effective_rd_to_wr <= 0;
effective_rd_to_wr_diff_chip <= 0;
effective_wr_to_rd <= 0;
effective_wr_to_rd_diff_chip <= 0;
end
else
begin
if (int_do_burst_chop)
begin
effective_rd_to_wr <= t_param_rd_to_wr_bc;
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip;
effective_wr_to_rd <= t_param_wr_to_rd_bc;
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip;
end
else if (int_do_burst_terminate)
begin
if (t_param_rd_to_wr > (max_local_burst_size - int_effective_size))
effective_rd_to_wr <= t_param_rd_to_wr - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr <= 1'b1;
if (t_param_rd_to_wr_diff_chip > (max_local_burst_size - int_effective_size))
effective_rd_to_wr_diff_chip <= t_param_rd_to_wr_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_rd_to_wr_diff_chip <= 1'b1;
if (t_param_wr_to_rd > (max_local_burst_size - int_effective_size))
effective_wr_to_rd <= t_param_wr_to_rd - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd <= 1'b1;
if (t_param_wr_to_rd_diff_chip > (max_local_burst_size - int_effective_size))
effective_wr_to_rd_diff_chip <= t_param_wr_to_rd_diff_chip - (max_local_burst_size - int_effective_size);
else
effective_wr_to_rd_diff_chip <= 1'b1;
end
end
end
//----------------------------------------------------------------------------------------------------
// Read / Write State Machine
//----------------------------------------------------------------------------------------------------
generate
genvar s_cs;
for (s_cs = 0;s_cs < CFG_MEM_IF_CHIP;s_cs = s_cs + 1)
begin : rdwr_monitor_per_chip
reg [31 : 0] rdwr_state;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_this_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] read_cnt_diff_chip;
reg [RDWR_COUNTER_WIDTH - 1 : 0] write_cnt_diff_chip;
reg int_do_read_this_chip;
reg int_do_write_this_chip;
reg int_do_read_diff_chip;
reg int_do_write_diff_chip;
reg doing_burst_chop;
reg doing_burst_terminate;
reg int_read_ready;
reg int_write_ready;
// Do read/write to this/different chip
always @ (*)
begin
if (int_do_read)
begin
if (int_to_chip_c [s_cs])
begin
int_do_read_this_chip = 1'b1;
int_do_read_diff_chip = 1'b0;
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b1;
end
end
else
begin
int_do_read_this_chip = 1'b0;
int_do_read_diff_chip = 1'b0;
end
end
always @ (*)
begin
if (int_do_write)
begin
if (int_to_chip_c [s_cs])
begin
int_do_write_this_chip = 1'b1;
int_do_write_diff_chip = 1'b0;
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b1;
end
end
else
begin
int_do_write_this_chip = 1'b0;
int_do_write_diff_chip = 1'b0;
end
end
// Read write counter to this chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_this_chip <= 0;
write_cnt_this_chip <= 0;
end
else
begin
if (int_do_read_this_chip)
read_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_this_chip <= read_cnt_this_chip + 1'b1;
if (int_do_write_this_chip)
write_cnt_this_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_this_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_this_chip <= write_cnt_this_chip + 1'b1;
end
end
// Read write counter to different chip address
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
read_cnt_diff_chip <= 0;
write_cnt_diff_chip <= 0;
end
else
begin
if (int_do_read_diff_chip)
read_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (read_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
read_cnt_diff_chip <= read_cnt_diff_chip + 1'b1;
if (int_do_write_diff_chip)
write_cnt_diff_chip <= RANK_TIMER_COUNTER_OFFSET;
else if (write_cnt_diff_chip != {RDWR_COUNTER_WIDTH{1'b1}})
write_cnt_diff_chip <= write_cnt_diff_chip + 1'b1;
end
end
// Doing burst chop signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_chop <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
begin
if (int_do_burst_chop)
doing_burst_chop <= 1'b1;
else
doing_burst_chop <= 1'b0;
end
end
end
// Doing burst terminate signal
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
doing_burst_terminate <= 1'b0;
end
else
begin
if (int_do_read || int_do_write)
doing_burst_terminate <= 1'b0;
else if (int_do_burst_terminate)
doing_burst_terminate <= 1'b1;
end
end
// Register comparison logic for better fMAX
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip;
reg compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr;
reg compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip;
reg compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd;
reg compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (less_than_x1_rd_to_rd)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (less_than_x1_rd_to_wr)
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (t_param_rd_to_rd - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd <= 1'b0;
end
if (read_cnt_this_chip >= (t_param_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (less_than_x1_rd_to_rd_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (less_than_x1_rd_to_wr_diff_chip)
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (t_param_rd_to_rd_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip <= 1'b0;
end
if (read_cnt_diff_chip >= (t_param_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (less_than_x1_wr_to_wr)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (less_than_x1_wr_to_rd)
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (t_param_wr_to_wr - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr <= 1'b0;
end
if (write_cnt_this_chip >= (t_param_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (less_than_x1_wr_to_wr_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (less_than_x1_wr_to_rd_diff_chip)
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (t_param_wr_to_wr_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip <= 1'b0;
end
if (write_cnt_diff_chip >= (t_param_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
else
begin
// Read to this chip comparison
if (int_do_read_this_chip)
begin
if (t_param_rd_to_wr <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
else
begin
if (read_cnt_this_chip >= (effective_rd_to_wr - 1'b1))
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b1;
end
else
begin
compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr <= 1'b0;
end
end
// Read to different chip comparison
if (int_do_read_diff_chip)
begin
if (t_param_rd_to_wr_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
else
begin
if (read_cnt_diff_chip >= (effective_rd_to_wr_diff_chip - 1'b1))
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b1;
end
else
begin
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip <= 1'b0;
end
end
// Write to this chip comparison
if (int_do_write_this_chip)
begin
if (t_param_wr_to_rd <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
else
begin
if (write_cnt_this_chip >= (effective_wr_to_rd - 1'b1))
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b1;
end
else
begin
compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd <= 1'b0;
end
end
// Write to different chip comparison
if (int_do_write_diff_chip)
begin
if (t_param_wr_to_rd_diff_chip <= RANK_TIMER_COUNTER_OFFSET)
// We're not comparing against effective_timing_param because it is not loaded yet!
// It'll take one clock cycle to load, therefore we'r taking the worst case parameter (to be safe on all scenario)
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
else
begin
if (write_cnt_diff_chip >= (effective_wr_to_rd_diff_chip - 1'b1))
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b1;
end
else
begin
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip <= 1'b0;
end
end
end
end
// Read write monitor state machine
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b0;
int_write_ready <= 1'b0;
end
else
begin
case (rdwr_state)
IDLE :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
rdwr_state <= IDLE;
int_read_ready <= 1'b1;
int_write_ready <= 1'b1;
end
end
WR :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr &&
compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip && compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
RD :
begin
if (int_do_write_this_chip)
begin
rdwr_state <= WR;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_wr_to_rd_bc)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
else
begin
if (less_than_x0_wr_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
end
if (less_than_x0_wr_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_write_diff_chip)
begin
rdwr_state <= WR;
if (less_than_x0_wr_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_wr_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else if (int_do_read_this_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd)
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (int_do_burst_chop) // burst chop
begin
if (less_than_x0_rd_to_wr_bc)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (less_than_x0_rd_to_wr)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
else if (int_do_read_diff_chip)
begin
rdwr_state <= RD;
if (less_than_x0_rd_to_rd_diff_chip && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd) // making sure previous write timing is satisfied
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (less_than_x0_rd_to_wr_diff_chip && compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr) // making sure previous read timing is satisfied
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (doing_burst_chop || doing_burst_terminate) // burst chop or burst terminate
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_effective_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_effective_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_effective_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_effective_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip )
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
else
begin
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_rd && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_rd &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_rd_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_rd_diff_chip )
int_read_ready <= 1'b1;
else
int_read_ready <= 1'b0;
if (compare_rd_cnt_this_chip_greater_eq_than_t_param_rd_to_wr && compare_wr_cnt_this_chip_greater_eq_than_t_param_wr_to_wr &&
compare_rd_cnt_diff_chip_greater_eq_than_t_param_rd_to_wr_diff_chip && compare_wr_cnt_diff_chip_greater_eq_than_t_param_wr_to_wr_diff_chip)
int_write_ready <= 1'b1;
else
int_write_ready <= 1'b0;
end
end
end
default :
rdwr_state <= IDLE;
endcase
end
end
// Assign read/write ready signal to top
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [s_cs])
begin
read_ready [s_cs] = 1'b0;
write_ready [s_cs] = 1'b0;
end
else
begin
if (CFG_RANK_TIMER_OUTPUT_REG)
begin
read_ready [s_cs] = int_read_ready;
write_ready [s_cs] = int_write_ready;
end
else
begin
read_ready [s_cs] = int_read_ready & int_interrupt_ready;
write_ready [s_cs] = int_write_ready & int_interrupt_ready;
end
end
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Read/Write Monitor
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
generate
genvar u_cs;
for (u_cs = 0;u_cs < CFG_MEM_IF_CHIP;u_cs = u_cs + 1)
begin : pch_monitor_per_chip
always @ (*)
begin
if (!CFG_RANK_TIMER_OUTPUT_REG && stall_chip [u_cs])
pch_ready [u_cs] = 1'b0;
else
pch_ready [u_cs] = one;
end
end
endgenerate
//--------------------------------------------------------------------------------------------------------
//
// [END] Precharge Monitor
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module rw_manager_read_datapath(
ck,
reset_n,
check_do,
check_dm,
check_do_lfsr,
check_dm_lfsr,
check_pattern_push,
clear_error,
read_data,
read_data_valid,
error_word,
enable_ap_mode
);
parameter DATA_WIDTH = "";
parameter AFI_RATIO = "";
localparam NUMBER_OF_WORDS = 2 * AFI_RATIO;
localparam DATA_BUS_SIZE = DATA_WIDTH * NUMBER_OF_WORDS;
input ck;
input reset_n;
input [3:0] check_do;
input [2:0] check_dm;
input check_do_lfsr;
input check_dm_lfsr;
input check_pattern_push;
input enable_ap_mode;
input clear_error;
input [DATA_BUS_SIZE - 1 : 0] read_data;
input read_data_valid;
output [DATA_WIDTH - 1 : 0] error_word;
reg [4:0] pattern_radd;
reg [4:0] pattern_wadd;
wire [4:0] pattern_radd_next;
wire [8:0] check_word_write = { check_do, check_dm, check_do_lfsr, check_dm_lfsr };
wire [8:0] check_word_read;
wire [3:0] check_do_read = check_word_read[8:5];
wire [2:0] check_dm_read = check_word_read[4:2];
wire check_do_lfsr_read = check_word_read[1];
wire check_dm_lfsr_read = check_word_read[0];
wire [DATA_BUS_SIZE - 1 : 0] do_data;
wire [NUMBER_OF_WORDS - 1 : 0] dm_data;
wire do_lfsr_step = check_do_lfsr_read & read_data_valid;
wire dm_lfsr_step = check_dm_lfsr_read & read_data_valid;
reg h_data_valid;
reg h_data_valid_r;
always @(posedge ck)
begin
if (~reset_n)
begin
h_data_valid <= 1'b0;
h_data_valid_r <= 1'b0;
end
else
begin
if (h_data_valid)
h_data_valid <= 1'b0;
else if (read_data_valid & ~h_data_valid)
h_data_valid <= 1'b1;
h_data_valid_r <= h_data_valid;
end
end
wire [DATA_BUS_SIZE - 1 : 0] h_do_data;
assign h_do_data = (h_data_valid_r & enable_ap_mode)? {DATA_BUS_SIZE {1'b0}} : do_data;
rw_manager_bitcheck bitcheck_i(
.ck(ck),
.reset_n(reset_n),
.clear(clear_error),
.enable(read_data_valid),
.read_data(read_data),
.reference_data(h_do_data),
.mask(dm_data),
.error_word(error_word)
);
defparam bitcheck_i.DATA_WIDTH = DATA_WIDTH;
defparam bitcheck_i.AFI_RATIO = AFI_RATIO;
rw_manager_write_decoder write_decoder_i(
.ck(ck),
.reset_n(reset_n),
.do_lfsr(check_do_lfsr_read),
.dm_lfsr(check_dm_lfsr_read),
.do_lfsr_step(do_lfsr_step),
.dm_lfsr_step(dm_lfsr_step),
.do_code(check_do_read),
.dm_code(check_dm_read),
.do_data(do_data),
.dm_data(dm_data)
);
defparam write_decoder_i.DATA_WIDTH = DATA_WIDTH;
defparam write_decoder_i.AFI_RATIO = AFI_RATIO;
rw_manager_pattern_fifo pattern_fifo_i(
.clock(ck),
.data(check_word_write),
.rdaddress(pattern_radd_next),
.wraddress(pattern_wadd),
.wren(check_pattern_push),
.q(check_word_read)
);
assign pattern_radd_next = pattern_radd + (read_data_valid ? 1'b1 : 1'b0);
always @(posedge ck or negedge reset_n) begin
if(~reset_n) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end
else begin
if (clear_error) begin
pattern_radd <= 5'b00000;
pattern_wadd <= 5'b00000;
end else begin
if(read_data_valid) begin
pattern_radd <= pattern_radd + 1'b1;
end
if(check_pattern_push) begin
pattern_wadd <= pattern_wadd + 1'b1;
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBP_TB_V
`define SKY130_FD_SC_LS__SDFBBP_TB_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfbbp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SCD = 1'b0;
#80 SCE = 1'b0;
#100 SET_B = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 D = 1'b1;
#220 RESET_B = 1'b1;
#240 SCD = 1'b1;
#260 SCE = 1'b1;
#280 SET_B = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 D = 1'b0;
#400 RESET_B = 1'b0;
#420 SCD = 1'b0;
#440 SCE = 1'b0;
#460 SET_B = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 SET_B = 1'b1;
#660 SCE = 1'b1;
#680 SCD = 1'b1;
#700 RESET_B = 1'b1;
#720 D = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 SET_B = 1'bx;
#840 SCE = 1'bx;
#860 SCD = 1'bx;
#880 RESET_B = 1'bx;
#900 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ls__sdfbbp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBP_TB_V
|
//-----------------------------------------------------------------------------
// processing_system7
// processor sub system wrapper
//-----------------------------------------------------------------------------
//
// ************************************************************************
// ** DISCLAIMER OF LIABILITY **
// ** **
// ** This file contains proprietary and confidential information of **
// ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
// ** from Xilinx, and may be used, copied and/or diSCLosed only **
// ** pursuant to the terms of a valid license agreement with Xilinx. **
// ** **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
// ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
// ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
// ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
// ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
// ** does not warrant that functions included in the Materials will **
// ** meet the requirements of Licensee, or that the operation of the **
// ** Materials will be uninterrupted or error-free, or that defects **
// ** in the Materials will be corrected. Furthermore, Xilinx does **
// ** not warrant or make any representations regarding use, or the **
// ** results of the use, of the Materials in terms of correctness, **
// ** accuracy, reliability or otherwise. **
// ** **
// ** Xilinx products are not designed or intended to be fail-safe, **
// ** or for use in any application requiring fail-safe performance, **
// ** such as life-support or safety devices or systems, Class III **
// ** medical devices, nuclear facilities, applications related to **
// ** the deployment of airbags, or any other applications that could **
// ** lead to death, personal injury or severe property or **
// ** environmental damage (individually and collectively, "critical **
// ** applications"). Customer assumes the sole risk and liability **
// ** of any use of Xilinx products in critical applications, **
// ** subject only to applicable laws and regulations governing **
// ** limitations on product liability. **
// ** **
// ** Copyright 2010 Xilinx, Inc. **
// ** All rights reserved. **
// ** **
// ** This disclaimer and copyright notice must be retained as part **
// ** of this file at all times. **
// ************************************************************************
//
//-----------------------------------------------------------------------------
// Filename: processing_system7_v5_5_processing_system7.v
// Version: v1.00.a
// Description: This is the wrapper file for PSS.
//-----------------------------------------------------------------------------
// Structure: This section shows the hierarchical structure of
// pss_wrapper.
//
// --processing_system7_v5_5_processing_system7.v
// --PS7.v - Unisim component
//-----------------------------------------------------------------------------
// Author: SD
//
// History:
//
// SD 09/20/11 -- First version
// ~~~~~~
// Created the first version v2.00.a
// ^^^^^^
//------------------------------------------------------------------------------
// ^^^^^^
// SR 11/25/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// 1. Changed all clock, reset and clktrig ports to be individual
// signals instead of vectors. This is required for modeling of tools.
// 2. Interrupts are now defined as individual signals as well.
// 3. Added Clk buffer logic for FCLK_CLK
// 4. Includes the ACP related changes done
//
// TODO:
// 1. C_NUM_F2P_INTR_INPUTS needs to have control on the
// number of interrupt ports connected for IRQ_F2P.
//
//------------------------------------------------------------------------------
// ^^^^^^
// KP 12/07/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_NUM_F2P_INTR_INPUTS taken into account for IRQ_F2P
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/09/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// C_FCLK_CLK0_BUF to C_FCLK_CLK3_BUF parameters were updated
// to STRING and fix for CR 640523
//------------------------------------------------------------------------------
// ^^^^^^
// NR 12/13/11 -- v3.00.a version
// ~~~~~~~
// Key changes are
// Updated IRQ_F2P logic to address CR 641523.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/01/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Updated SDIO logic to address CR 636210.
// |
// Added C_PS7_SI_REV parameter to track SI Rev
// Removed compress/decompress logic to address CR 642527.
//------------------------------------------------------------------------------
// ^^^^^^
// NR 02/27/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// TTC(0,1)_WAVE_OUT and TTC(0,1)_CLK_IN vector signals are made as individual
// ports as fix for CR 646379
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/05/12 -- v3.01.a version
// ~~~~~~~
// Key changes are
// Added/updated compress/decompress logic to address 648393
//------------------------------------------------------------------------------
// ^^^^^^
// NR 03/14/12 -- v4.00.a version
// ~~~~~~~
// Unused parameters deleted CR 651120
// Addressed CR 651751
//------------------------------------------------------------------------------
// ^^^^^^
// NR 04/17/12 -- v4.01.a version
// ~~~~~~~
// Added FTM trace buffer functionality
// Added support for ACP AxUSER ports local update
//------------------------------------------------------------------------------
// ^^^^^^
// VR 05/18/12 -- v4.01.a version
// ~~~~~~~
// Fixed CR#659157
//------------------------------------------------------------------------------
// ^^^^^^
// VR 07/25/12 -- v4.01.a version
// ~~~~~~~
// Changed S_AXI_HP{1,2}_WACOUNT port's width to 6 from 8 to match unisim model
// Changed fclk_clktrig_gnd width to 4 from 16 to match unisim model
//------------------------------------------------------------------------------
// ^^^^^^
// VR 11/06/12 -- v5.00 version
// ~~~~~~~
// CR #682573
// Added BIBUF to fixed IO ports and IBUF to fixed input ports
//------------------------------------------------------------------------------
(*POWER= "<PROCESSOR name={system} numA9Cores={2} clockFreq={650.000000} load={0.5} /><MEMORY name={code} memType={DDR3} dataWidth={32} clockFreq={525.000000} readRate={0.5} writeRate={0.5} /><IO interface={I2C} ioStandard={} bidis={1} ioBank={} clockFreq={108.333336} usageRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={7} ioBank={Vcco_p1} clockFreq={50.000000} usageRate={0.5} /><IO interface={USB} ioStandard={LVCMOS18} bidis={12} ioBank={Vcco_p1} clockFreq={60} usageRate={0.5} /><IO interface={GigE} ioStandard={HSTL_I_18} bidis={14} ioBank={Vcco_p1} clockFreq={125.000000} usageRate={0.5} /><IO interface={QSPI} ioStandard={LVCMOS33} bidis={6} ioBank={Vcco_p0} clockFreq={200} usageRate={0.5} /><PLL domain={Processor} vco={1300.000} /><PLL domain={Memory} vco={1050.000} /><PLL domain={IO} vco={1000.000} /><AXI interface={M_AXI_GP0} dataWidth={32} clockFreq={100} usageRate={0.5} />/>" *)
(* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=525.000000, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=14, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.034, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=-0.03, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=-0.082, PCW_UIPARAM_DDR_BOARD_DELAY0=0.176, PCW_UIPARAM_DDR_BOARD_DELAY1=0.159, PCW_UIPARAM_DDR_BOARD_DELAY2=0.162, PCW_UIPARAM_DDR_BOARD_DELAY3=0.187, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=27.85, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=22.87, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=22.9, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=29.9, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=27, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=22.8, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=24, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=30.45, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=20.6, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=20.6, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=180, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=165, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=165, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=50.000000, PCW_APU_PERIPHERAL_FREQMHZ=650.000000, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=50, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100.000000, PCW_FPGA1_PERIPHERAL_FREQMHZ=150, PCW_FPGA2_PERIPHERAL_FREQMHZ=12.288, PCW_FPGA3_PERIPHERAL_FREQMHZ=100.000000, PCW_OVERRIDE_BASIC_CLOCK=0, PCW_ARMPLL_CTRL_FBDIV=26, PCW_IOPLL_CTRL_FBDIV=20, PCW_DDRPLL_CTRL_FBDIV=21, PCW_CPU_CPU_PLL_FREQMHZ=1300.000, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1050.000, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=0, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=100, PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=150, PCW_S_AXI_HP1_FREQMHZ=100, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K128M16 JT-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=2048 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=0, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 47, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=EMIO, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=0, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=0, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=0, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=DDR PLL, PCW_FCLK2_PERIPHERAL_CLKSRC=ARM PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=1, PCW_FPGA_FCLK2_ENABLE=1, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=2, PCW_NOR_SRAM_CS0_T_RC=2, PCW_NOR_SRAM_CS0_WE_TIME=2, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=2, PCW_NOR_SRAM_CS1_T_RC=2, PCW_NOR_SRAM_CS1_WE_TIME=2, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=2, PCW_NOR_CS0_T_RC=2, PCW_NOR_CS0_WE_TIME=2, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=2, PCW_NOR_CS1_T_RC=2, PCW_NOR_CS1_WE_TIME=2, PCW_NAND_CYCLES_T_RR=0, PCW_NAND_CYCLES_T_AR=0, PCW_NAND_CYCLES_T_CLR=0, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=2, PCW_NAND_CYCLES_T_RC=2 }" *)
module processing_system7_v5_5_processing_system7
#(
parameter integer C_USE_DEFAULT_ACP_USER_VAL = 1,
parameter integer C_S_AXI_ACP_ARUSER_VAL = 31,
parameter integer C_S_AXI_ACP_AWUSER_VAL = 31,
parameter integer C_M_AXI_GP0_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_THREAD_ID_WIDTH = 12,
parameter integer C_M_AXI_GP0_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP1_ENABLE_STATIC_REMAP = 1,
parameter integer C_M_AXI_GP0_ID_WIDTH = 12,
parameter integer C_M_AXI_GP1_ID_WIDTH = 12,
parameter integer C_S_AXI_GP0_ID_WIDTH = 6,
parameter integer C_S_AXI_GP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP0_ID_WIDTH = 6,
parameter integer C_S_AXI_HP1_ID_WIDTH = 6,
parameter integer C_S_AXI_HP2_ID_WIDTH = 6,
parameter integer C_S_AXI_HP3_ID_WIDTH = 6,
parameter integer C_S_AXI_ACP_ID_WIDTH = 3,
parameter integer C_S_AXI_HP0_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP1_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP2_DATA_WIDTH = 64,
parameter integer C_S_AXI_HP3_DATA_WIDTH = 64,
parameter integer C_INCLUDE_ACP_TRANS_CHECK = 0,
parameter integer C_NUM_F2P_INTR_INPUTS = 1,
parameter C_FCLK_CLK0_BUF = "TRUE",
parameter C_FCLK_CLK1_BUF = "TRUE",
parameter C_FCLK_CLK2_BUF = "TRUE",
parameter C_FCLK_CLK3_BUF = "TRUE",
parameter integer C_EMIO_GPIO_WIDTH = 64,
parameter integer C_INCLUDE_TRACE_BUFFER = 0,
parameter integer C_TRACE_BUFFER_FIFO_SIZE = 128,
parameter integer C_TRACE_BUFFER_CLOCK_DELAY = 12,
parameter integer USE_TRACE_DATA_EDGE_DETECTOR = 0,
parameter integer C_TRACE_PIPELINE_WIDTH = 8,
parameter C_PS7_SI_REV = "PRODUCTION",
parameter integer C_EN_EMIO_ENET0 = 0,
parameter integer C_EN_EMIO_ENET1 = 0,
parameter integer C_EN_EMIO_TRACE = 0,
parameter integer C_DQ_WIDTH = 32,
parameter integer C_DQS_WIDTH = 4,
parameter integer C_DM_WIDTH = 4,
parameter integer C_MIO_PRIMITIVE = 54,
parameter C_PACKAGE_NAME = "clg484",
parameter C_IRQ_F2P_MODE = "DIRECT",
parameter C_TRACE_INTERNAL_WIDTH = 32,
parameter integer C_EN_EMIO_PJTAG = 0
)
(
//FMIO =========================================
//FMIO CAN0
output CAN0_PHY_TX,
input CAN0_PHY_RX,
//FMIO CAN1
output CAN1_PHY_TX,
input CAN1_PHY_RX,
//FMIO ENET0
output reg ENET0_GMII_TX_EN,
output reg ENET0_GMII_TX_ER,
output ENET0_MDIO_MDC,
output ENET0_MDIO_O,
output ENET0_MDIO_T,
output ENET0_PTP_DELAY_REQ_RX,
output ENET0_PTP_DELAY_REQ_TX,
output ENET0_PTP_PDELAY_REQ_RX,
output ENET0_PTP_PDELAY_REQ_TX,
output ENET0_PTP_PDELAY_RESP_RX,
output ENET0_PTP_PDELAY_RESP_TX,
output ENET0_PTP_SYNC_FRAME_RX,
output ENET0_PTP_SYNC_FRAME_TX,
output ENET0_SOF_RX,
output ENET0_SOF_TX,
output reg [7:0] ENET0_GMII_TXD,
input ENET0_GMII_COL,
input ENET0_GMII_CRS,
input ENET0_GMII_RX_CLK,
input ENET0_GMII_RX_DV,
input ENET0_GMII_RX_ER,
input ENET0_GMII_TX_CLK,
input ENET0_MDIO_I,
input ENET0_EXT_INTIN,
input [7:0] ENET0_GMII_RXD,
//FMIO ENET1
output reg ENET1_GMII_TX_EN,
output reg ENET1_GMII_TX_ER,
output ENET1_MDIO_MDC,
output ENET1_MDIO_O,
output ENET1_MDIO_T,
output ENET1_PTP_DELAY_REQ_RX,
output ENET1_PTP_DELAY_REQ_TX,
output ENET1_PTP_PDELAY_REQ_RX,
output ENET1_PTP_PDELAY_REQ_TX,
output ENET1_PTP_PDELAY_RESP_RX,
output ENET1_PTP_PDELAY_RESP_TX,
output ENET1_PTP_SYNC_FRAME_RX,
output ENET1_PTP_SYNC_FRAME_TX,
output ENET1_SOF_RX,
output ENET1_SOF_TX,
output reg [7:0] ENET1_GMII_TXD,
input ENET1_GMII_COL,
input ENET1_GMII_CRS,
input ENET1_GMII_RX_CLK,
input ENET1_GMII_RX_DV,
input ENET1_GMII_RX_ER,
input ENET1_GMII_TX_CLK,
input ENET1_MDIO_I,
input ENET1_EXT_INTIN,
input [7:0] ENET1_GMII_RXD,
//FMIO GPIO
input [(C_EMIO_GPIO_WIDTH-1):0] GPIO_I,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_O,
output [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T,
//FMIO I2C0
input I2C0_SDA_I,
output I2C0_SDA_O,
output I2C0_SDA_T,
input I2C0_SCL_I,
output I2C0_SCL_O,
output I2C0_SCL_T,
//FMIO I2C1
input I2C1_SDA_I,
output I2C1_SDA_O,
output I2C1_SDA_T,
input I2C1_SCL_I,
output I2C1_SCL_O,
output I2C1_SCL_T,
//FMIO PJTAG
input PJTAG_TCK,
input PJTAG_TMS,
input PJTAG_TDI,
output PJTAG_TDO,
//FMIO SDIO0
output SDIO0_CLK,
input SDIO0_CLK_FB,
output SDIO0_CMD_O,
input SDIO0_CMD_I,
output SDIO0_CMD_T,
input [3:0] SDIO0_DATA_I,
output [3:0] SDIO0_DATA_O,
output [3:0] SDIO0_DATA_T,
output SDIO0_LED,
input SDIO0_CDN,
input SDIO0_WP,
output SDIO0_BUSPOW,
output [2:0] SDIO0_BUSVOLT,
//FMIO SDIO1
output SDIO1_CLK,
input SDIO1_CLK_FB,
output SDIO1_CMD_O,
input SDIO1_CMD_I,
output SDIO1_CMD_T,
input [3:0] SDIO1_DATA_I,
output [3:0] SDIO1_DATA_O,
output [3:0] SDIO1_DATA_T,
output SDIO1_LED,
input SDIO1_CDN,
input SDIO1_WP,
output SDIO1_BUSPOW,
output [2:0] SDIO1_BUSVOLT,
//FMIO SPI0
input SPI0_SCLK_I,
output SPI0_SCLK_O,
output SPI0_SCLK_T,
input SPI0_MOSI_I,
output SPI0_MOSI_O,
output SPI0_MOSI_T,
input SPI0_MISO_I,
output SPI0_MISO_O,
output SPI0_MISO_T,
input SPI0_SS_I,
output SPI0_SS_O,
output SPI0_SS1_O,
output SPI0_SS2_O,
output SPI0_SS_T,
//FMIO SPI1
input SPI1_SCLK_I,
output SPI1_SCLK_O,
output SPI1_SCLK_T,
input SPI1_MOSI_I,
output SPI1_MOSI_O,
output SPI1_MOSI_T,
input SPI1_MISO_I,
output SPI1_MISO_O,
output SPI1_MISO_T,
input SPI1_SS_I,
output SPI1_SS_O,
output SPI1_SS1_O,
output SPI1_SS2_O,
output SPI1_SS_T,
//FMIO UART0
output UART0_DTRN,
output UART0_RTSN,
output UART0_TX,
input UART0_CTSN,
input UART0_DCDN,
input UART0_DSRN,
input UART0_RIN,
input UART0_RX,
//FMIO UART1
output UART1_DTRN,
output UART1_RTSN,
output UART1_TX,
input UART1_CTSN,
input UART1_DCDN,
input UART1_DSRN,
input UART1_RIN,
input UART1_RX,
//FMIO TTC0
output TTC0_WAVE0_OUT,
output TTC0_WAVE1_OUT,
output TTC0_WAVE2_OUT,
input TTC0_CLK0_IN,
input TTC0_CLK1_IN,
input TTC0_CLK2_IN,
//FMIO TTC1
output TTC1_WAVE0_OUT,
output TTC1_WAVE1_OUT,
output TTC1_WAVE2_OUT,
input TTC1_CLK0_IN,
input TTC1_CLK1_IN,
input TTC1_CLK2_IN,
//WDT
input WDT_CLK_IN,
output WDT_RST_OUT,
//FTPORT
input TRACE_CLK,
output TRACE_CTL,
output [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA,
output reg TRACE_CLK_OUT,
// USB
output [1:0] USB0_PORT_INDCTL,
output USB0_VBUS_PWRSELECT,
input USB0_VBUS_PWRFAULT,
output [1:0] USB1_PORT_INDCTL,
output USB1_VBUS_PWRSELECT,
input USB1_VBUS_PWRFAULT,
input SRAM_INTIN,
//AIO ===================================================
//M_AXI_GP0
// -- Output
output M_AXI_GP0_ARESETN,
output M_AXI_GP0_ARVALID,
output M_AXI_GP0_AWVALID,
output M_AXI_GP0_BREADY,
output M_AXI_GP0_RREADY,
output M_AXI_GP0_WLAST,
output M_AXI_GP0_WVALID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_ARID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_AWID,
output [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_WID,
output [1:0] M_AXI_GP0_ARBURST,
output [1:0] M_AXI_GP0_ARLOCK,
output [2:0] M_AXI_GP0_ARSIZE,
output [1:0] M_AXI_GP0_AWBURST,
output [1:0] M_AXI_GP0_AWLOCK,
output [2:0] M_AXI_GP0_AWSIZE,
output [2:0] M_AXI_GP0_ARPROT,
output [2:0] M_AXI_GP0_AWPROT,
output [31:0] M_AXI_GP0_ARADDR,
output [31:0] M_AXI_GP0_AWADDR,
output [31:0] M_AXI_GP0_WDATA,
output [3:0] M_AXI_GP0_ARCACHE,
output [3:0] M_AXI_GP0_ARLEN,
output [3:0] M_AXI_GP0_ARQOS,
output [3:0] M_AXI_GP0_AWCACHE,
output [3:0] M_AXI_GP0_AWLEN,
output [3:0] M_AXI_GP0_AWQOS,
output [3:0] M_AXI_GP0_WSTRB,
// -- Input
input M_AXI_GP0_ACLK,
input M_AXI_GP0_ARREADY,
input M_AXI_GP0_AWREADY,
input M_AXI_GP0_BVALID,
input M_AXI_GP0_RLAST,
input M_AXI_GP0_RVALID,
input M_AXI_GP0_WREADY,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_BID,
input [(C_M_AXI_GP0_THREAD_ID_WIDTH - 1):0] M_AXI_GP0_RID,
input [1:0] M_AXI_GP0_BRESP,
input [1:0] M_AXI_GP0_RRESP,
input [31:0] M_AXI_GP0_RDATA,
//M_AXI_GP1
// -- Output
output M_AXI_GP1_ARESETN,
output M_AXI_GP1_ARVALID,
output M_AXI_GP1_AWVALID,
output M_AXI_GP1_BREADY,
output M_AXI_GP1_RREADY,
output M_AXI_GP1_WLAST,
output M_AXI_GP1_WVALID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_ARID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_AWID,
output [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_WID,
output [1:0] M_AXI_GP1_ARBURST,
output [1:0] M_AXI_GP1_ARLOCK,
output [2:0] M_AXI_GP1_ARSIZE,
output [1:0] M_AXI_GP1_AWBURST,
output [1:0] M_AXI_GP1_AWLOCK,
output [2:0] M_AXI_GP1_AWSIZE,
output [2:0] M_AXI_GP1_ARPROT,
output [2:0] M_AXI_GP1_AWPROT,
output [31:0] M_AXI_GP1_ARADDR,
output [31:0] M_AXI_GP1_AWADDR,
output [31:0] M_AXI_GP1_WDATA,
output [3:0] M_AXI_GP1_ARCACHE,
output [3:0] M_AXI_GP1_ARLEN,
output [3:0] M_AXI_GP1_ARQOS,
output [3:0] M_AXI_GP1_AWCACHE,
output [3:0] M_AXI_GP1_AWLEN,
output [3:0] M_AXI_GP1_AWQOS,
output [3:0] M_AXI_GP1_WSTRB,
// -- Input
input M_AXI_GP1_ACLK,
input M_AXI_GP1_ARREADY,
input M_AXI_GP1_AWREADY,
input M_AXI_GP1_BVALID,
input M_AXI_GP1_RLAST,
input M_AXI_GP1_RVALID,
input M_AXI_GP1_WREADY,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_BID,
input [(C_M_AXI_GP1_THREAD_ID_WIDTH - 1):0] M_AXI_GP1_RID,
input [1:0] M_AXI_GP1_BRESP,
input [1:0] M_AXI_GP1_RRESP,
input [31:0] M_AXI_GP1_RDATA,
// S_AXI_GP0
// -- Output
output S_AXI_GP0_ARESETN,
output S_AXI_GP0_ARREADY,
output S_AXI_GP0_AWREADY,
output S_AXI_GP0_BVALID,
output S_AXI_GP0_RLAST,
output S_AXI_GP0_RVALID,
output S_AXI_GP0_WREADY,
output [1:0] S_AXI_GP0_BRESP,
output [1:0] S_AXI_GP0_RRESP,
output [31:0] S_AXI_GP0_RDATA,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_BID,
output [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_RID,
// -- Input
input S_AXI_GP0_ACLK,
input S_AXI_GP0_ARVALID,
input S_AXI_GP0_AWVALID,
input S_AXI_GP0_BREADY,
input S_AXI_GP0_RREADY,
input S_AXI_GP0_WLAST,
input S_AXI_GP0_WVALID,
input [1:0] S_AXI_GP0_ARBURST,
input [1:0] S_AXI_GP0_ARLOCK,
input [2:0] S_AXI_GP0_ARSIZE,
input [1:0] S_AXI_GP0_AWBURST,
input [1:0] S_AXI_GP0_AWLOCK,
input [2:0] S_AXI_GP0_AWSIZE,
input [2:0] S_AXI_GP0_ARPROT,
input [2:0] S_AXI_GP0_AWPROT,
input [31:0] S_AXI_GP0_ARADDR,
input [31:0] S_AXI_GP0_AWADDR,
input [31:0] S_AXI_GP0_WDATA,
input [3:0] S_AXI_GP0_ARCACHE,
input [3:0] S_AXI_GP0_ARLEN,
input [3:0] S_AXI_GP0_ARQOS,
input [3:0] S_AXI_GP0_AWCACHE,
input [3:0] S_AXI_GP0_AWLEN,
input [3:0] S_AXI_GP0_AWQOS,
input [3:0] S_AXI_GP0_WSTRB,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_ARID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_AWID,
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] S_AXI_GP0_WID,
// S_AXI_GP1
// -- Output
output S_AXI_GP1_ARESETN,
output S_AXI_GP1_ARREADY,
output S_AXI_GP1_AWREADY,
output S_AXI_GP1_BVALID,
output S_AXI_GP1_RLAST,
output S_AXI_GP1_RVALID,
output S_AXI_GP1_WREADY,
output [1:0] S_AXI_GP1_BRESP,
output [1:0] S_AXI_GP1_RRESP,
output [31:0] S_AXI_GP1_RDATA,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_BID,
output [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_RID,
// -- Input
input S_AXI_GP1_ACLK,
input S_AXI_GP1_ARVALID,
input S_AXI_GP1_AWVALID,
input S_AXI_GP1_BREADY,
input S_AXI_GP1_RREADY,
input S_AXI_GP1_WLAST,
input S_AXI_GP1_WVALID,
input [1:0] S_AXI_GP1_ARBURST,
input [1:0] S_AXI_GP1_ARLOCK,
input [2:0] S_AXI_GP1_ARSIZE,
input [1:0] S_AXI_GP1_AWBURST,
input [1:0] S_AXI_GP1_AWLOCK,
input [2:0] S_AXI_GP1_AWSIZE,
input [2:0] S_AXI_GP1_ARPROT,
input [2:0] S_AXI_GP1_AWPROT,
input [31:0] S_AXI_GP1_ARADDR,
input [31:0] S_AXI_GP1_AWADDR,
input [31:0] S_AXI_GP1_WDATA,
input [3:0] S_AXI_GP1_ARCACHE,
input [3:0] S_AXI_GP1_ARLEN,
input [3:0] S_AXI_GP1_ARQOS,
input [3:0] S_AXI_GP1_AWCACHE,
input [3:0] S_AXI_GP1_AWLEN,
input [3:0] S_AXI_GP1_AWQOS,
input [3:0] S_AXI_GP1_WSTRB,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_ARID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_AWID,
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] S_AXI_GP1_WID,
//S_AXI_ACP
// -- Output
output S_AXI_ACP_ARESETN,
output S_AXI_ACP_ARREADY,
output S_AXI_ACP_AWREADY,
output S_AXI_ACP_BVALID,
output S_AXI_ACP_RLAST,
output S_AXI_ACP_RVALID,
output S_AXI_ACP_WREADY,
output [1:0] S_AXI_ACP_BRESP,
output [1:0] S_AXI_ACP_RRESP,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_BID,
output [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_RID,
output [63:0] S_AXI_ACP_RDATA,
// -- Input
input S_AXI_ACP_ACLK,
input S_AXI_ACP_ARVALID,
input S_AXI_ACP_AWVALID,
input S_AXI_ACP_BREADY,
input S_AXI_ACP_RREADY,
input S_AXI_ACP_WLAST,
input S_AXI_ACP_WVALID,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_ARID,
input [2:0] S_AXI_ACP_ARPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_AWID,
input [2:0] S_AXI_ACP_AWPROT,
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ACP_WID,
input [31:0] S_AXI_ACP_ARADDR,
input [31:0] S_AXI_ACP_AWADDR,
input [3:0] S_AXI_ACP_ARCACHE,
input [3:0] S_AXI_ACP_ARLEN,
input [3:0] S_AXI_ACP_ARQOS,
input [3:0] S_AXI_ACP_AWCACHE,
input [3:0] S_AXI_ACP_AWLEN,
input [3:0] S_AXI_ACP_AWQOS,
input [1:0] S_AXI_ACP_ARBURST,
input [1:0] S_AXI_ACP_ARLOCK,
input [2:0] S_AXI_ACP_ARSIZE,
input [1:0] S_AXI_ACP_AWBURST,
input [1:0] S_AXI_ACP_AWLOCK,
input [2:0] S_AXI_ACP_AWSIZE,
input [4:0] S_AXI_ACP_ARUSER,
input [4:0] S_AXI_ACP_AWUSER,
input [63:0] S_AXI_ACP_WDATA,
input [7:0] S_AXI_ACP_WSTRB,
// S_AXI_HP_0
// -- Output
output S_AXI_HP0_ARESETN,
output S_AXI_HP0_ARREADY,
output S_AXI_HP0_AWREADY,
output S_AXI_HP0_BVALID,
output S_AXI_HP0_RLAST,
output S_AXI_HP0_RVALID,
output S_AXI_HP0_WREADY,
output [1:0] S_AXI_HP0_BRESP,
output [1:0] S_AXI_HP0_RRESP,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_BID,
output [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_RID,
output [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_RDATA,
output [7:0] S_AXI_HP0_RCOUNT,
output [7:0] S_AXI_HP0_WCOUNT,
output [2:0] S_AXI_HP0_RACOUNT,
output [5:0] S_AXI_HP0_WACOUNT,
// -- Input
input S_AXI_HP0_ACLK,
input S_AXI_HP0_ARVALID,
input S_AXI_HP0_AWVALID,
input S_AXI_HP0_BREADY,
input S_AXI_HP0_RDISSUECAP1_EN,
input S_AXI_HP0_RREADY,
input S_AXI_HP0_WLAST,
input S_AXI_HP0_WRISSUECAP1_EN,
input S_AXI_HP0_WVALID,
input [1:0] S_AXI_HP0_ARBURST,
input [1:0] S_AXI_HP0_ARLOCK,
input [2:0] S_AXI_HP0_ARSIZE,
input [1:0] S_AXI_HP0_AWBURST,
input [1:0] S_AXI_HP0_AWLOCK,
input [2:0] S_AXI_HP0_AWSIZE,
input [2:0] S_AXI_HP0_ARPROT,
input [2:0] S_AXI_HP0_AWPROT,
input [31:0] S_AXI_HP0_ARADDR,
input [31:0] S_AXI_HP0_AWADDR,
input [3:0] S_AXI_HP0_ARCACHE,
input [3:0] S_AXI_HP0_ARLEN,
input [3:0] S_AXI_HP0_ARQOS,
input [3:0] S_AXI_HP0_AWCACHE,
input [3:0] S_AXI_HP0_AWLEN,
input [3:0] S_AXI_HP0_AWQOS,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_ARID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_AWID,
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] S_AXI_HP0_WID,
input [(C_S_AXI_HP0_DATA_WIDTH - 1) :0] S_AXI_HP0_WDATA,
input [((C_S_AXI_HP0_DATA_WIDTH/8)-1):0] S_AXI_HP0_WSTRB,
// S_AXI_HP1
// -- Output
output S_AXI_HP1_ARESETN,
output S_AXI_HP1_ARREADY,
output S_AXI_HP1_AWREADY,
output S_AXI_HP1_BVALID,
output S_AXI_HP1_RLAST,
output S_AXI_HP1_RVALID,
output S_AXI_HP1_WREADY,
output [1:0] S_AXI_HP1_BRESP,
output [1:0] S_AXI_HP1_RRESP,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_BID,
output [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_RID,
output [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_RDATA,
output [7:0] S_AXI_HP1_RCOUNT,
output [7:0] S_AXI_HP1_WCOUNT,
output [2:0] S_AXI_HP1_RACOUNT,
output [5:0] S_AXI_HP1_WACOUNT,
// -- Input
input S_AXI_HP1_ACLK,
input S_AXI_HP1_ARVALID,
input S_AXI_HP1_AWVALID,
input S_AXI_HP1_BREADY,
input S_AXI_HP1_RDISSUECAP1_EN,
input S_AXI_HP1_RREADY,
input S_AXI_HP1_WLAST,
input S_AXI_HP1_WRISSUECAP1_EN,
input S_AXI_HP1_WVALID,
input [1:0] S_AXI_HP1_ARBURST,
input [1:0] S_AXI_HP1_ARLOCK,
input [2:0] S_AXI_HP1_ARSIZE,
input [1:0] S_AXI_HP1_AWBURST,
input [1:0] S_AXI_HP1_AWLOCK,
input [2:0] S_AXI_HP1_AWSIZE,
input [2:0] S_AXI_HP1_ARPROT,
input [2:0] S_AXI_HP1_AWPROT,
input [31:0] S_AXI_HP1_ARADDR,
input [31:0] S_AXI_HP1_AWADDR,
input [3:0] S_AXI_HP1_ARCACHE,
input [3:0] S_AXI_HP1_ARLEN,
input [3:0] S_AXI_HP1_ARQOS,
input [3:0] S_AXI_HP1_AWCACHE,
input [3:0] S_AXI_HP1_AWLEN,
input [3:0] S_AXI_HP1_AWQOS,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_ARID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_AWID,
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] S_AXI_HP1_WID,
input [(C_S_AXI_HP1_DATA_WIDTH - 1) :0] S_AXI_HP1_WDATA,
input [((C_S_AXI_HP1_DATA_WIDTH/8)-1):0] S_AXI_HP1_WSTRB,
// S_AXI_HP2
// -- Output
output S_AXI_HP2_ARESETN,
output S_AXI_HP2_ARREADY,
output S_AXI_HP2_AWREADY,
output S_AXI_HP2_BVALID,
output S_AXI_HP2_RLAST,
output S_AXI_HP2_RVALID,
output S_AXI_HP2_WREADY,
output [1:0] S_AXI_HP2_BRESP,
output [1:0] S_AXI_HP2_RRESP,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_BID,
output [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_RID,
output [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_RDATA,
output [7:0] S_AXI_HP2_RCOUNT,
output [7:0] S_AXI_HP2_WCOUNT,
output [2:0] S_AXI_HP2_RACOUNT,
output [5:0] S_AXI_HP2_WACOUNT,
// -- Input
input S_AXI_HP2_ACLK,
input S_AXI_HP2_ARVALID,
input S_AXI_HP2_AWVALID,
input S_AXI_HP2_BREADY,
input S_AXI_HP2_RDISSUECAP1_EN,
input S_AXI_HP2_RREADY,
input S_AXI_HP2_WLAST,
input S_AXI_HP2_WRISSUECAP1_EN,
input S_AXI_HP2_WVALID,
input [1:0] S_AXI_HP2_ARBURST,
input [1:0] S_AXI_HP2_ARLOCK,
input [2:0] S_AXI_HP2_ARSIZE,
input [1:0] S_AXI_HP2_AWBURST,
input [1:0] S_AXI_HP2_AWLOCK,
input [2:0] S_AXI_HP2_AWSIZE,
input [2:0] S_AXI_HP2_ARPROT,
input [2:0] S_AXI_HP2_AWPROT,
input [31:0] S_AXI_HP2_ARADDR,
input [31:0] S_AXI_HP2_AWADDR,
input [3:0] S_AXI_HP2_ARCACHE,
input [3:0] S_AXI_HP2_ARLEN,
input [3:0] S_AXI_HP2_ARQOS,
input [3:0] S_AXI_HP2_AWCACHE,
input [3:0] S_AXI_HP2_AWLEN,
input [3:0] S_AXI_HP2_AWQOS,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_ARID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_AWID,
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] S_AXI_HP2_WID,
input [(C_S_AXI_HP2_DATA_WIDTH - 1) :0] S_AXI_HP2_WDATA,
input [((C_S_AXI_HP2_DATA_WIDTH/8)-1):0] S_AXI_HP2_WSTRB,
// S_AXI_HP_3
// -- Output
output S_AXI_HP3_ARESETN,
output S_AXI_HP3_ARREADY,
output S_AXI_HP3_AWREADY,
output S_AXI_HP3_BVALID,
output S_AXI_HP3_RLAST,
output S_AXI_HP3_RVALID,
output S_AXI_HP3_WREADY,
output [1:0] S_AXI_HP3_BRESP,
output [1:0] S_AXI_HP3_RRESP,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_BID,
output [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_RID,
output [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_RDATA,
output [7:0] S_AXI_HP3_RCOUNT,
output [7:0] S_AXI_HP3_WCOUNT,
output [2:0] S_AXI_HP3_RACOUNT,
output [5:0] S_AXI_HP3_WACOUNT,
// -- Input
input S_AXI_HP3_ACLK,
input S_AXI_HP3_ARVALID,
input S_AXI_HP3_AWVALID,
input S_AXI_HP3_BREADY,
input S_AXI_HP3_RDISSUECAP1_EN,
input S_AXI_HP3_RREADY,
input S_AXI_HP3_WLAST,
input S_AXI_HP3_WRISSUECAP1_EN,
input S_AXI_HP3_WVALID,
input [1:0] S_AXI_HP3_ARBURST,
input [1:0] S_AXI_HP3_ARLOCK,
input [2:0] S_AXI_HP3_ARSIZE,
input [1:0] S_AXI_HP3_AWBURST,
input [1:0] S_AXI_HP3_AWLOCK,
input [2:0] S_AXI_HP3_AWSIZE,
input [2:0] S_AXI_HP3_ARPROT,
input [2:0] S_AXI_HP3_AWPROT,
input [31:0] S_AXI_HP3_ARADDR,
input [31:0] S_AXI_HP3_AWADDR,
input [3:0] S_AXI_HP3_ARCACHE,
input [3:0] S_AXI_HP3_ARLEN,
input [3:0] S_AXI_HP3_ARQOS,
input [3:0] S_AXI_HP3_AWCACHE,
input [3:0] S_AXI_HP3_AWLEN,
input [3:0] S_AXI_HP3_AWQOS,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_ARID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_AWID,
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] S_AXI_HP3_WID,
input [(C_S_AXI_HP3_DATA_WIDTH - 1) :0] S_AXI_HP3_WDATA,
input [((C_S_AXI_HP3_DATA_WIDTH/8)-1):0] S_AXI_HP3_WSTRB,
//FIO ========================================
//IRQ
//output [28:0] IRQ_P2F,
output IRQ_P2F_DMAC_ABORT ,
output IRQ_P2F_DMAC0,
output IRQ_P2F_DMAC1,
output IRQ_P2F_DMAC2,
output IRQ_P2F_DMAC3,
output IRQ_P2F_DMAC4,
output IRQ_P2F_DMAC5,
output IRQ_P2F_DMAC6,
output IRQ_P2F_DMAC7,
output IRQ_P2F_SMC,
output IRQ_P2F_QSPI,
output IRQ_P2F_CTI,
output IRQ_P2F_GPIO,
output IRQ_P2F_USB0,
output IRQ_P2F_ENET0,
output IRQ_P2F_ENET_WAKE0,
output IRQ_P2F_SDIO0,
output IRQ_P2F_I2C0,
output IRQ_P2F_SPI0,
output IRQ_P2F_UART0,
output IRQ_P2F_CAN0,
output IRQ_P2F_USB1,
output IRQ_P2F_ENET1,
output IRQ_P2F_ENET_WAKE1,
output IRQ_P2F_SDIO1,
output IRQ_P2F_I2C1,
output IRQ_P2F_SPI1,
output IRQ_P2F_UART1,
output IRQ_P2F_CAN1,
input [(C_NUM_F2P_INTR_INPUTS-1):0] IRQ_F2P,
input Core0_nFIQ,
input Core0_nIRQ,
input Core1_nFIQ,
input Core1_nIRQ,
//DMA
output [1:0] DMA0_DATYPE,
output DMA0_DAVALID,
output DMA0_DRREADY,
output DMA0_RSTN,
output [1:0] DMA1_DATYPE,
output DMA1_DAVALID,
output DMA1_DRREADY,
output DMA1_RSTN,
output [1:0] DMA2_DATYPE,
output DMA2_DAVALID,
output DMA2_DRREADY,
output DMA2_RSTN,
output [1:0] DMA3_DATYPE,
output DMA3_DAVALID,
output DMA3_DRREADY,
output DMA3_RSTN,
input DMA0_ACLK,
input DMA0_DAREADY,
input DMA0_DRLAST,
input DMA0_DRVALID,
input DMA1_ACLK,
input DMA1_DAREADY,
input DMA1_DRLAST,
input DMA1_DRVALID,
input DMA2_ACLK,
input DMA2_DAREADY,
input DMA2_DRLAST,
input DMA2_DRVALID,
input DMA3_ACLK,
input DMA3_DAREADY,
input DMA3_DRLAST,
input DMA3_DRVALID,
input [1:0] DMA0_DRTYPE,
input [1:0] DMA1_DRTYPE,
input [1:0] DMA2_DRTYPE,
input [1:0] DMA3_DRTYPE,
//FCLK
output FCLK_CLK3,
output FCLK_CLK2,
output FCLK_CLK1,
output FCLK_CLK0,
input FCLK_CLKTRIG3_N,
input FCLK_CLKTRIG2_N,
input FCLK_CLKTRIG1_N,
input FCLK_CLKTRIG0_N,
output FCLK_RESET3_N,
output FCLK_RESET2_N,
output FCLK_RESET1_N,
output FCLK_RESET0_N,
//FTMD
input [31:0] FTMD_TRACEIN_DATA,
input FTMD_TRACEIN_VALID,
input FTMD_TRACEIN_CLK,
input [3:0] FTMD_TRACEIN_ATID,
//FTMT
input FTMT_F2P_TRIG_0,
output FTMT_F2P_TRIGACK_0,
input FTMT_F2P_TRIG_1,
output FTMT_F2P_TRIGACK_1,
input FTMT_F2P_TRIG_2,
output FTMT_F2P_TRIGACK_2,
input FTMT_F2P_TRIG_3,
output FTMT_F2P_TRIGACK_3,
input [31:0] FTMT_F2P_DEBUG,
input FTMT_P2F_TRIGACK_0,
output FTMT_P2F_TRIG_0,
input FTMT_P2F_TRIGACK_1,
output FTMT_P2F_TRIG_1,
input FTMT_P2F_TRIGACK_2,
output FTMT_P2F_TRIG_2,
input FTMT_P2F_TRIGACK_3,
output FTMT_P2F_TRIG_3,
output [31:0] FTMT_P2F_DEBUG,
//FIDLE
input FPGA_IDLE_N,
//EVENT
output EVENT_EVENTO,
output [1:0] EVENT_STANDBYWFE,
output [1:0] EVENT_STANDBYWFI,
input EVENT_EVENTI,
//DARB
input [3:0] DDR_ARB,
inout [C_MIO_PRIMITIVE - 1:0] MIO,
//DDR
inout DDR_CAS_n, // CASB
inout DDR_CKE, // CKE
inout DDR_Clk_n, // CKN
inout DDR_Clk, // CKP
inout DDR_CS_n, // CSB
inout DDR_DRSTB, // DDR_DRSTB
inout DDR_ODT, // ODT
inout DDR_RAS_n, // RASB
inout DDR_WEB,
inout [2:0] DDR_BankAddr, // BA
inout [14:0] DDR_Addr, // A
inout DDR_VRN,
inout DDR_VRP,
inout [C_DM_WIDTH - 1:0] DDR_DM, // DM
inout [C_DQ_WIDTH - 1:0] DDR_DQ, // DQ
inout [C_DQS_WIDTH -1:0] DDR_DQS_n, // DQSN
inout [C_DQS_WIDTH - 1:0] DDR_DQS, // DQSP
inout PS_SRSTB, // SRSTB
inout PS_CLK, // CLK
inout PS_PORB // PORB
);
wire [11:0] M_AXI_GP0_AWID_FULL;
wire [11:0] M_AXI_GP0_WID_FULL;
wire [11:0] M_AXI_GP0_ARID_FULL;
wire [11:0] M_AXI_GP0_BID_FULL;
wire [11:0] M_AXI_GP0_RID_FULL;
wire [11:0] M_AXI_GP1_AWID_FULL;
wire [11:0] M_AXI_GP1_WID_FULL;
wire [11:0] M_AXI_GP1_ARID_FULL;
wire [11:0] M_AXI_GP1_BID_FULL;
wire [11:0] M_AXI_GP1_RID_FULL;
wire ENET0_GMII_TX_EN_i;
wire ENET0_GMII_TX_ER_i;
reg ENET0_GMII_COL_i;
reg ENET0_GMII_CRS_i;
reg ENET0_GMII_RX_DV_i;
reg ENET0_GMII_RX_ER_i;
reg [7:0] ENET0_GMII_RXD_i;
wire [7:0] ENET0_GMII_TXD_i;
wire ENET1_GMII_TX_EN_i;
wire ENET1_GMII_TX_ER_i;
reg ENET1_GMII_COL_i;
reg ENET1_GMII_CRS_i;
reg ENET1_GMII_RX_DV_i;
reg ENET1_GMII_RX_ER_i;
reg [7:0] ENET1_GMII_RXD_i;
wire [7:0] ENET1_GMII_TXD_i;
reg [31:0] FTMD_TRACEIN_DATA_notracebuf;
reg FTMD_TRACEIN_VALID_notracebuf;
reg [3:0] FTMD_TRACEIN_ATID_notracebuf;
wire [31:0] FTMD_TRACEIN_DATA_i;
wire FTMD_TRACEIN_VALID_i;
wire [3:0] FTMD_TRACEIN_ATID_i;
wire [31:0] FTMD_TRACEIN_DATA_tracebuf;
wire FTMD_TRACEIN_VALID_tracebuf;
wire [3:0] FTMD_TRACEIN_ATID_tracebuf;
wire [5:0] S_AXI_GP0_BID_out;
wire [5:0] S_AXI_GP0_RID_out;
wire [5:0] S_AXI_GP0_ARID_in;
wire [5:0] S_AXI_GP0_AWID_in;
wire [5:0] S_AXI_GP0_WID_in;
wire [5:0] S_AXI_GP1_BID_out;
wire [5:0] S_AXI_GP1_RID_out;
wire [5:0] S_AXI_GP1_ARID_in;
wire [5:0] S_AXI_GP1_AWID_in;
wire [5:0] S_AXI_GP1_WID_in;
wire [5:0] S_AXI_HP0_BID_out;
wire [5:0] S_AXI_HP0_RID_out;
wire [5:0] S_AXI_HP0_ARID_in;
wire [5:0] S_AXI_HP0_AWID_in;
wire [5:0] S_AXI_HP0_WID_in;
wire [5:0] S_AXI_HP1_BID_out;
wire [5:0] S_AXI_HP1_RID_out;
wire [5:0] S_AXI_HP1_ARID_in;
wire [5:0] S_AXI_HP1_AWID_in;
wire [5:0] S_AXI_HP1_WID_in;
wire [5:0] S_AXI_HP2_BID_out;
wire [5:0] S_AXI_HP2_RID_out;
wire [5:0] S_AXI_HP2_ARID_in;
wire [5:0] S_AXI_HP2_AWID_in;
wire [5:0] S_AXI_HP2_WID_in;
wire [5:0] S_AXI_HP3_BID_out;
wire [5:0] S_AXI_HP3_RID_out;
wire [5:0] S_AXI_HP3_ARID_in;
wire [5:0] S_AXI_HP3_AWID_in;
wire [5:0] S_AXI_HP3_WID_in;
wire [2:0] S_AXI_ACP_BID_out;
wire [2:0] S_AXI_ACP_RID_out;
wire [2:0] S_AXI_ACP_ARID_in;
wire [2:0] S_AXI_ACP_AWID_in;
wire [2:0] S_AXI_ACP_WID_in;
wire [63:0] S_AXI_HP0_WDATA_in;
wire [7:0] S_AXI_HP0_WSTRB_in;
wire [63:0] S_AXI_HP0_RDATA_out;
wire [63:0] S_AXI_HP1_WDATA_in;
wire [7:0] S_AXI_HP1_WSTRB_in;
wire [63:0] S_AXI_HP1_RDATA_out;
wire [63:0] S_AXI_HP2_WDATA_in;
wire [7:0] S_AXI_HP2_WSTRB_in;
wire [63:0] S_AXI_HP2_RDATA_out;
wire [63:0] S_AXI_HP3_WDATA_in;
wire [7:0] S_AXI_HP3_WSTRB_in;
wire [63:0] S_AXI_HP3_RDATA_out;
wire [1:0] M_AXI_GP0_ARSIZE_i;
wire [1:0] M_AXI_GP0_AWSIZE_i;
wire [1:0] M_AXI_GP1_ARSIZE_i;
wire [1:0] M_AXI_GP1_AWSIZE_i;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPBID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPRID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPARID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPAWID_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] SAXIACPWID_W;
wire SAXIACPARREADY_W;
wire SAXIACPAWREADY_W;
wire SAXIACPBVALID_W;
wire SAXIACPRLAST_W;
wire SAXIACPRVALID_W;
wire SAXIACPWREADY_W;
wire [1:0] SAXIACPBRESP_W;
wire [1:0] SAXIACPRRESP_W;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_BID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_RID;
wire [63:0] SAXIACPRDATA_W;
wire S_AXI_ATC_ARVALID;
wire S_AXI_ATC_AWVALID;
wire S_AXI_ATC_BREADY;
wire S_AXI_ATC_RREADY;
wire S_AXI_ATC_WLAST;
wire S_AXI_ATC_WVALID;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_ARID;
wire [2:0] S_AXI_ATC_ARPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_AWID;
wire [2:0] S_AXI_ATC_AWPROT;
wire [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] S_AXI_ATC_WID;
wire [31:0] S_AXI_ATC_ARADDR;
wire [31:0] S_AXI_ATC_AWADDR;
wire [3:0] S_AXI_ATC_ARCACHE;
wire [3:0] S_AXI_ATC_ARLEN;
wire [3:0] S_AXI_ATC_ARQOS;
wire [3:0] S_AXI_ATC_AWCACHE;
wire [3:0] S_AXI_ATC_AWLEN;
wire [3:0] S_AXI_ATC_AWQOS;
wire [1:0] S_AXI_ATC_ARBURST;
wire [1:0] S_AXI_ATC_ARLOCK;
wire [2:0] S_AXI_ATC_ARSIZE;
wire [1:0] S_AXI_ATC_AWBURST;
wire [1:0] S_AXI_ATC_AWLOCK;
wire [2:0] S_AXI_ATC_AWSIZE;
wire [4:0] S_AXI_ATC_ARUSER;
wire [4:0] S_AXI_ATC_AWUSER;
wire [63:0] S_AXI_ATC_WDATA;
wire [7:0] S_AXI_ATC_WSTRB;
wire SAXIACPARVALID_W;
wire SAXIACPAWVALID_W;
wire SAXIACPBREADY_W;
wire SAXIACPRREADY_W;
wire SAXIACPWLAST_W;
wire SAXIACPWVALID_W;
wire [2:0] SAXIACPARPROT_W;
wire [2:0] SAXIACPAWPROT_W;
wire [31:0] SAXIACPARADDR_W;
wire [31:0] SAXIACPAWADDR_W;
wire [3:0] SAXIACPARCACHE_W;
wire [3:0] SAXIACPARLEN_W;
wire [3:0] SAXIACPARQOS_W;
wire [3:0] SAXIACPAWCACHE_W;
wire [3:0] SAXIACPAWLEN_W;
wire [3:0] SAXIACPAWQOS_W;
wire [1:0] SAXIACPARBURST_W;
wire [1:0] SAXIACPARLOCK_W;
wire [2:0] SAXIACPARSIZE_W;
wire [1:0] SAXIACPAWBURST_W;
wire [1:0] SAXIACPAWLOCK_W;
wire [2:0] SAXIACPAWSIZE_W;
wire [4:0] SAXIACPARUSER_W;
wire [4:0] SAXIACPAWUSER_W;
wire [63:0] SAXIACPWDATA_W;
wire [7:0] SAXIACPWSTRB_W;
// AxUSER signal update
wire [4:0] param_aruser;
wire [4:0] param_awuser;
// Added to address CR 651751
wire [3:0] fclk_clktrig_gnd = 4'h0;
wire [19:0] irq_f2p_i;
wire [15:0] irq_f2p_null = 16'h0000;
// EMIO I2C0
wire I2C0_SDA_T_n;
wire I2C0_SCL_T_n;
// EMIO I2C1
wire I2C1_SDA_T_n;
wire I2C1_SCL_T_n;
// EMIO SPI0
wire SPI0_SCLK_T_n;
wire SPI0_MOSI_T_n;
wire SPI0_MISO_T_n;
wire SPI0_SS_T_n;
// EMIO SPI1
wire SPI1_SCLK_T_n;
wire SPI1_MOSI_T_n;
wire SPI1_MISO_T_n;
wire SPI1_SS_T_n;
// EMIO GEM0
wire ENET0_MDIO_T_n;
// EMIO GEM1
wire ENET1_MDIO_T_n;
// EMIO GPIO
wire [(C_EMIO_GPIO_WIDTH-1):0] GPIO_T_n;
wire [63:0] gpio_out_t_n;
wire [63:0] gpio_out;
wire [63:0] gpio_in63_0;
//For Clock buffering
wire [3:0] FCLK_CLK_unbuffered;
wire [3:0] FCLK_CLK_buffered;
// EMIO PJTAG
wire PJTAG_TDO_O;
wire PJTAG_TDO_T;
wire PJTAG_TDO_T_n;
// EMIO SDIO0
wire SDIO0_CMD_T_n;
wire [3:0] SDIO0_DATA_T_n;
// EMIO SDIO1
wire SDIO1_CMD_T_n;
wire [3:0] SDIO1_DATA_T_n;
// buffered IO
wire [C_MIO_PRIMITIVE - 1:0] buffered_MIO;
wire buffered_DDR_WEB;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_Clk_n;
wire buffered_DDR_Clk;
wire buffered_DDR_CS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire [2:0] buffered_DDR_BankAddr;
wire [14:0] buffered_DDR_Addr;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire [C_DM_WIDTH - 1:0] buffered_DDR_DM;
wire [C_DQ_WIDTH - 1:0] buffered_DDR_DQ;
wire [C_DQS_WIDTH -1:0] buffered_DDR_DQS_n;
wire [C_DQS_WIDTH - 1:0] buffered_DDR_DQS;
wire buffered_PS_SRSTB;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire [31:0] TRACE_DATA_i;
wire TRACE_CTL_i;
reg TRACE_CTL_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
reg [(C_TRACE_INTERNAL_WIDTH)-1:0] TRACE_DATA_PIPE [(C_TRACE_PIPELINE_WIDTH - 1):0];
// fixed CR #665394
integer j;
generate
if (C_EN_EMIO_TRACE == 1) begin
always @(posedge TRACE_CLK)
begin
TRACE_CTL_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_CTL_i;
TRACE_DATA_PIPE[C_TRACE_PIPELINE_WIDTH - 1] <= TRACE_DATA_i[(C_TRACE_INTERNAL_WIDTH-1):0];
for (j=(C_TRACE_PIPELINE_WIDTH-1); j>0; j=j-1) begin
TRACE_CTL_PIPE[j-1] <= TRACE_CTL_PIPE[j];
TRACE_DATA_PIPE[j-1] <= TRACE_DATA_PIPE[j];
end
TRACE_CLK_OUT <= ~TRACE_CLK_OUT;
end
end
endgenerate
assign TRACE_CTL = TRACE_CTL_PIPE[0];
assign TRACE_DATA = TRACE_DATA_PIPE[0];
//irq_p2f
// Updated IRQ_F2P logic to address CR 641523
generate
if(C_NUM_F2P_INTR_INPUTS == 0) begin : irq_f2p_select_null
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,irq_f2p_null[15:0]};
end else if(C_NUM_F2P_INTR_INPUTS == 16) begin : irq_f2p_select_all
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,IRQ_F2P[15:0]};
end else begin : irq_f2p_select
if (C_IRQ_F2P_MODE == "DIRECT") begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0],
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0]};
end else begin
assign irq_f2p_i[19:0] = {Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,
IRQ_F2P[(C_NUM_F2P_INTR_INPUTS-1):0],
irq_f2p_null[(15-C_NUM_F2P_INTR_INPUTS):0]};
end
end
endgenerate
assign M_AXI_GP0_ARSIZE[2:0] = {1'b0, M_AXI_GP0_ARSIZE_i[1:0]};
assign M_AXI_GP0_AWSIZE[2:0] = {1'b0, M_AXI_GP0_AWSIZE_i[1:0]};
assign M_AXI_GP1_ARSIZE[2:0] = {1'b0, M_AXI_GP1_ARSIZE_i[1:0]};
assign M_AXI_GP1_AWSIZE[2:0] = {1'b0, M_AXI_GP1_AWSIZE_i[1:0]};
// Compress Function
// Modified as per CR 631955
//function [11:0] uncompress_id;
// input [5:0] id;
// begin
// case (id[5:0])
// // dmac0
// 6'd1 : uncompress_id = 12'b010000_1000_00 ;
// 6'd2 : uncompress_id = 12'b010000_0000_00 ;
// 6'd3 : uncompress_id = 12'b010000_0001_00 ;
// 6'd4 : uncompress_id = 12'b010000_0010_00 ;
// 6'd5 : uncompress_id = 12'b010000_0011_00 ;
// 6'd6 : uncompress_id = 12'b010000_0100_00 ;
// 6'd7 : uncompress_id = 12'b010000_0101_00 ;
// 6'd8 : uncompress_id = 12'b010000_0110_00 ;
// 6'd9 : uncompress_id = 12'b010000_0111_00 ;
// // ioum
// 6'd10 : uncompress_id = 12'b0100000_000_01 ;
// 6'd11 : uncompress_id = 12'b0100000_001_01 ;
// 6'd12 : uncompress_id = 12'b0100000_010_01 ;
// 6'd13 : uncompress_id = 12'b0100000_011_01 ;
// 6'd14 : uncompress_id = 12'b0100000_100_01 ;
// 6'd15 : uncompress_id = 12'b0100000_101_01 ;
// // devci
// 6'd16 : uncompress_id = 12'b1000_0000_0000 ;
// // dap
// 6'd17 : uncompress_id = 12'b1000_0000_0001 ;
// // l2m1 (CPU000)
// 6'd18 : uncompress_id = 12'b11_000_000_00_00 ;
// 6'd19 : uncompress_id = 12'b11_010_000_00_00 ;
// 6'd20 : uncompress_id = 12'b11_011_000_00_00 ;
// 6'd21 : uncompress_id = 12'b11_100_000_00_00 ;
// 6'd22 : uncompress_id = 12'b11_101_000_00_00 ;
// 6'd23 : uncompress_id = 12'b11_110_000_00_00 ;
// 6'd24 : uncompress_id = 12'b11_111_000_00_00 ;
// // l2m1 (CPU001)
// 6'd25 : uncompress_id = 12'b11_000_001_00_00 ;
// 6'd26 : uncompress_id = 12'b11_010_001_00_00 ;
// 6'd27 : uncompress_id = 12'b11_011_001_00_00 ;
// 6'd28 : uncompress_id = 12'b11_100_001_00_00 ;
// 6'd29 : uncompress_id = 12'b11_101_001_00_00 ;
// 6'd30 : uncompress_id = 12'b11_110_001_00_00 ;
// 6'd31 : uncompress_id = 12'b11_111_001_00_00 ;
// // l2m1 (L2CC)
// 6'd32 : uncompress_id = 12'b11_000_00101_00 ;
// 6'd33 : uncompress_id = 12'b11_000_01001_00 ;
// 6'd34 : uncompress_id = 12'b11_000_01101_00 ;
// 6'd35 : uncompress_id = 12'b11_000_10011_00 ;
// 6'd36 : uncompress_id = 12'b11_000_10111_00 ;
// 6'd37 : uncompress_id = 12'b11_000_11011_00 ;
// 6'd38 : uncompress_id = 12'b11_000_11111_00 ;
// 6'd39 : uncompress_id = 12'b11_000_00011_00 ;
// 6'd40 : uncompress_id = 12'b11_000_00111_00 ;
// 6'd41 : uncompress_id = 12'b11_000_01011_00 ;
// 6'd42 : uncompress_id = 12'b11_000_01111_00 ;
// 6'd43 : uncompress_id = 12'b11_000_00001_00 ;
// // l2m1 (ACP)
// 6'd44 : uncompress_id = 12'b11_000_10000_00 ;
// 6'd45 : uncompress_id = 12'b11_001_10000_00 ;
// 6'd46 : uncompress_id = 12'b11_010_10000_00 ;
// 6'd47 : uncompress_id = 12'b11_011_10000_00 ;
// 6'd48 : uncompress_id = 12'b11_100_10000_00 ;
// 6'd49 : uncompress_id = 12'b11_101_10000_00 ;
// 6'd50 : uncompress_id = 12'b11_110_10000_00 ;
// 6'd51 : uncompress_id = 12'b11_111_10000_00 ;
// default : uncompress_id = ~0;
// endcase
// end
//endfunction
//
//function [5:0] compress_id;
// input [11:0] id;
// begin
// case (id[11:0])
// // dmac0
// 12'b010000_1000_00 : compress_id = 'd1 ;
// 12'b010000_0000_00 : compress_id = 'd2 ;
// 12'b010000_0001_00 : compress_id = 'd3 ;
// 12'b010000_0010_00 : compress_id = 'd4 ;
// 12'b010000_0011_00 : compress_id = 'd5 ;
// 12'b010000_0100_00 : compress_id = 'd6 ;
// 12'b010000_0101_00 : compress_id = 'd7 ;
// 12'b010000_0110_00 : compress_id = 'd8 ;
// 12'b010000_0111_00 : compress_id = 'd9 ;
// // ioum
// 12'b0100000_000_01 : compress_id = 'd10 ;
// 12'b0100000_001_01 : compress_id = 'd11 ;
// 12'b0100000_010_01 : compress_id = 'd12 ;
// 12'b0100000_011_01 : compress_id = 'd13 ;
// 12'b0100000_100_01 : compress_id = 'd14 ;
// 12'b0100000_101_01 : compress_id = 'd15 ;
// // devci
// 12'b1000_0000_0000 : compress_id = 'd16 ;
// // dap
// 12'b1000_0000_0001 : compress_id = 'd17 ;
// // l2m1 (CPU000)
// 12'b11_000_000_00_00 : compress_id = 'd18 ;
// 12'b11_010_000_00_00 : compress_id = 'd19 ;
// 12'b11_011_000_00_00 : compress_id = 'd20 ;
// 12'b11_100_000_00_00 : compress_id = 'd21 ;
// 12'b11_101_000_00_00 : compress_id = 'd22 ;
// 12'b11_110_000_00_00 : compress_id = 'd23 ;
// 12'b11_111_000_00_00 : compress_id = 'd24 ;
// // l2m1 (CPU001)
// 12'b11_000_001_00_00 : compress_id = 'd25 ;
// 12'b11_010_001_00_00 : compress_id = 'd26 ;
// 12'b11_011_001_00_00 : compress_id = 'd27 ;
// 12'b11_100_001_00_00 : compress_id = 'd28 ;
// 12'b11_101_001_00_00 : compress_id = 'd29 ;
// 12'b11_110_001_00_00 : compress_id = 'd30 ;
// 12'b11_111_001_00_00 : compress_id = 'd31 ;
// // l2m1 (L2CC)
// 12'b11_000_00101_00 : compress_id = 'd32 ;
// 12'b11_000_01001_00 : compress_id = 'd33 ;
// 12'b11_000_01101_00 : compress_id = 'd34 ;
// 12'b11_000_10011_00 : compress_id = 'd35 ;
// 12'b11_000_10111_00 : compress_id = 'd36 ;
// 12'b11_000_11011_00 : compress_id = 'd37 ;
// 12'b11_000_11111_00 : compress_id = 'd38 ;
// 12'b11_000_00011_00 : compress_id = 'd39 ;
// 12'b11_000_00111_00 : compress_id = 'd40 ;
// 12'b11_000_01011_00 : compress_id = 'd41 ;
// 12'b11_000_01111_00 : compress_id = 'd42 ;
// 12'b11_000_00001_00 : compress_id = 'd43 ;
// // l2m1 (ACP)
// 12'b11_000_10000_00 : compress_id = 'd44 ;
// 12'b11_001_10000_00 : compress_id = 'd45 ;
// 12'b11_010_10000_00 : compress_id = 'd46 ;
// 12'b11_011_10000_00 : compress_id = 'd47 ;
// 12'b11_100_10000_00 : compress_id = 'd48 ;
// 12'b11_101_10000_00 : compress_id = 'd49 ;
// 12'b11_110_10000_00 : compress_id = 'd50 ;
// 12'b11_111_10000_00 : compress_id = 'd51 ;
// default: compress_id = ~0;
// endcase
// end
//endfunction
// Modified as per CR 648393
function [5:0] compress_id;
input [11:0] id;
begin
compress_id[0] = id[7] | (id[4] & id[2]) | (~id[11] & id[2]) | (id[11] & id[0]);
compress_id[1] = id[8] | id[5] | (~id[11] & id[3]);
compress_id[2] = id[9] | (id[6] & id[3] & id[2]) | (~id[11] & id[4]);
compress_id[3] = (id[11] & id[10] & id[4]) | (id[11] & id[10] & id[2]) | (~id[11] & id[10] & ~id[5] & ~id[0]);
compress_id[4] = (id[11] & id[3]) | (id[10] & id[0]) | (id[11] & id[10] & ~id[2] &~id[6]);
compress_id[5] = id[11] & id[10] & ~id[3];
end
endfunction
function [11:0] uncompress_id;
input [5:0] id;
begin
case (id[5:0])
// dmac0
6'b000_010 : uncompress_id = 12'b010000_1000_00 ;
6'b001_000 : uncompress_id = 12'b010000_0000_00 ;
6'b001_001 : uncompress_id = 12'b010000_0001_00 ;
6'b001_010 : uncompress_id = 12'b010000_0010_00 ;
6'b001_011 : uncompress_id = 12'b010000_0011_00 ;
6'b001_100 : uncompress_id = 12'b010000_0100_00 ;
6'b001_101 : uncompress_id = 12'b010000_0101_00 ;
6'b001_110 : uncompress_id = 12'b010000_0110_00 ;
6'b001_111 : uncompress_id = 12'b010000_0111_00 ;
// ioum
6'b010_000 : uncompress_id = 12'b0100000_000_01 ;
6'b010_001 : uncompress_id = 12'b0100000_001_01 ;
6'b010_010 : uncompress_id = 12'b0100000_010_01 ;
6'b010_011 : uncompress_id = 12'b0100000_011_01 ;
6'b010_100 : uncompress_id = 12'b0100000_100_01 ;
6'b010_101 : uncompress_id = 12'b0100000_101_01 ;
// devci
6'b000_000 : uncompress_id = 12'b1000_0000_0000 ;
// dap
6'b000_001 : uncompress_id = 12'b1000_0000_0001 ;
// l2m1 (CPU000)
6'b110_000 : uncompress_id = 12'b11_000_000_00_00 ;
6'b110_010 : uncompress_id = 12'b11_010_000_00_00 ;
6'b110_011 : uncompress_id = 12'b11_011_000_00_00 ;
6'b110_100 : uncompress_id = 12'b11_100_000_00_00 ;
6'b110_101 : uncompress_id = 12'b11_101_000_00_00 ;
6'b110_110 : uncompress_id = 12'b11_110_000_00_00 ;
6'b110_111 : uncompress_id = 12'b11_111_000_00_00 ;
// l2m1 (CPU001)
6'b111_000 : uncompress_id = 12'b11_000_001_00_00 ;
6'b111_010 : uncompress_id = 12'b11_010_001_00_00 ;
6'b111_011 : uncompress_id = 12'b11_011_001_00_00 ;
6'b111_100 : uncompress_id = 12'b11_100_001_00_00 ;
6'b111_101 : uncompress_id = 12'b11_101_001_00_00 ;
6'b111_110 : uncompress_id = 12'b11_110_001_00_00 ;
6'b111_111 : uncompress_id = 12'b11_111_001_00_00 ;
// l2m1 (L2CC)
6'b101_001 : uncompress_id = 12'b11_000_00101_00 ;
6'b101_010 : uncompress_id = 12'b11_000_01001_00 ;
6'b101_011 : uncompress_id = 12'b11_000_01101_00 ;
6'b011_100 : uncompress_id = 12'b11_000_10011_00 ;
6'b011_101 : uncompress_id = 12'b11_000_10111_00 ;
6'b011_110 : uncompress_id = 12'b11_000_11011_00 ;
6'b011_111 : uncompress_id = 12'b11_000_11111_00 ;
6'b011_000 : uncompress_id = 12'b11_000_00011_00 ;
6'b011_001 : uncompress_id = 12'b11_000_00111_00 ;
6'b011_010 : uncompress_id = 12'b11_000_01011_00 ;
6'b011_011 : uncompress_id = 12'b11_000_01111_00 ;
6'b101_000 : uncompress_id = 12'b11_000_00001_00 ;
// l2m1 (ACP)
6'b100_000 : uncompress_id = 12'b11_000_10000_00 ;
6'b100_001 : uncompress_id = 12'b11_001_10000_00 ;
6'b100_010 : uncompress_id = 12'b11_010_10000_00 ;
6'b100_011 : uncompress_id = 12'b11_011_10000_00 ;
6'b100_100 : uncompress_id = 12'b11_100_10000_00 ;
6'b100_101 : uncompress_id = 12'b11_101_10000_00 ;
6'b100_110 : uncompress_id = 12'b11_110_10000_00 ;
6'b100_111 : uncompress_id = 12'b11_111_10000_00 ;
default : uncompress_id = 12'hx ;
endcase
end
endfunction
// Static Remap logic Enablement and Disablement for C_M_AXI0 port
assign M_AXI_GP0_AWID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_AWID_FULL) : M_AXI_GP0_AWID_FULL;
assign M_AXI_GP0_WID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_WID_FULL) : M_AXI_GP0_WID_FULL;
assign M_AXI_GP0_ARID = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP0_ARID_FULL) : M_AXI_GP0_ARID_FULL;
assign M_AXI_GP0_BID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_BID) : M_AXI_GP0_BID;
assign M_AXI_GP0_RID_FULL = (C_M_AXI_GP0_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP0_RID) : M_AXI_GP0_RID;
// Static Remap logic Enablement and Disablement for C_M_AXI1 port
assign M_AXI_GP1_AWID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_AWID_FULL) : M_AXI_GP1_AWID_FULL;
assign M_AXI_GP1_WID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_WID_FULL) : M_AXI_GP1_WID_FULL;
assign M_AXI_GP1_ARID = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? compress_id(M_AXI_GP1_ARID_FULL) : M_AXI_GP1_ARID_FULL;
assign M_AXI_GP1_BID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_BID) : M_AXI_GP1_BID;
assign M_AXI_GP1_RID_FULL = (C_M_AXI_GP1_ENABLE_STATIC_REMAP == 1) ? uncompress_id(M_AXI_GP1_RID) : M_AXI_GP1_RID;
//// Compress_id and uncompress_id has been removed to address CR 642527
//// AXI interconnect v1.05.a and beyond implements dynamic ID compression/decompression.
// assign M_AXI_GP0_AWID = M_AXI_GP0_AWID_FULL;
// assign M_AXI_GP0_WID = M_AXI_GP0_WID_FULL;
// assign M_AXI_GP0_ARID = M_AXI_GP0_ARID_FULL;
// assign M_AXI_GP0_BID_FULL = M_AXI_GP0_BID;
// assign M_AXI_GP0_RID_FULL = M_AXI_GP0_RID;
//
// assign M_AXI_GP1_AWID = M_AXI_GP1_AWID_FULL;
// assign M_AXI_GP1_WID = M_AXI_GP1_WID_FULL;
// assign M_AXI_GP1_ARID = M_AXI_GP1_ARID_FULL;
// assign M_AXI_GP1_BID_FULL = M_AXI_GP1_BID;
// assign M_AXI_GP1_RID_FULL = M_AXI_GP1_RID;
// Pipeline Stage for ENET0
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_TX_CLK)
begin
ENET0_GMII_TXD <= ENET0_GMII_TXD_i;
ENET0_GMII_TX_EN <= ENET0_GMII_TX_EN_i;
ENET0_GMII_TX_ER <= ENET0_GMII_TX_ER_i;
ENET0_GMII_COL_i <= ENET0_GMII_COL;
ENET0_GMII_CRS_i <= ENET0_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET0 == 1) begin
always @(posedge ENET0_GMII_RX_CLK)
begin
ENET0_GMII_RXD_i <= ENET0_GMII_RXD;
ENET0_GMII_RX_DV_i <= ENET0_GMII_RX_DV;
ENET0_GMII_RX_ER_i <= ENET0_GMII_RX_ER;
end
end
endgenerate
// Pipeline Stage for ENET1
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_TX_CLK)
begin
ENET1_GMII_TXD <= ENET1_GMII_TXD_i;
ENET1_GMII_TX_EN <= ENET1_GMII_TX_EN_i;
ENET1_GMII_TX_ER <= ENET1_GMII_TX_ER_i;
ENET1_GMII_COL_i <= ENET1_GMII_COL;
ENET1_GMII_CRS_i <= ENET1_GMII_CRS;
end
end
endgenerate
generate
if (C_EN_EMIO_ENET1 == 1) begin
always @(posedge ENET1_GMII_RX_CLK)
begin
ENET1_GMII_RXD_i <= ENET1_GMII_RXD;
ENET1_GMII_RX_DV_i <= ENET1_GMII_RX_DV;
ENET1_GMII_RX_ER_i <= ENET1_GMII_RX_ER;
end
end
endgenerate
// Trace buffer instantiated when C_INCLUDE_TRACE_BUFFER is 1.
generate
if (C_EN_EMIO_TRACE == 1) begin
if (C_INCLUDE_TRACE_BUFFER == 0) begin : gen_no_trace_buffer
// Pipeline Stage for Traceport ATID
always @(posedge FTMD_TRACEIN_CLK)
begin
FTMD_TRACEIN_DATA_notracebuf <= FTMD_TRACEIN_DATA;
FTMD_TRACEIN_VALID_notracebuf <= FTMD_TRACEIN_VALID;
FTMD_TRACEIN_ATID_notracebuf <= FTMD_TRACEIN_ATID;
end
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_notracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_notracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_notracebuf;
end else begin : gen_trace_buffer
processing_system7_v5_5_trace_buffer #(.FIFO_SIZE (C_TRACE_BUFFER_FIFO_SIZE),
.USE_TRACE_DATA_EDGE_DETECTOR(USE_TRACE_DATA_EDGE_DETECTOR),
.C_DELAY_CLKS(C_TRACE_BUFFER_CLOCK_DELAY)
)
trace_buffer_i (
.TRACE_CLK(FTMD_TRACEIN_CLK),
.RST(~FCLK_RESET0_N),
.TRACE_VALID_IN(FTMD_TRACEIN_VALID),
.TRACE_DATA_IN(FTMD_TRACEIN_DATA),
.TRACE_ATID_IN(FTMD_TRACEIN_ATID),
.TRACE_ATID_OUT(FTMD_TRACEIN_ATID_tracebuf),
.TRACE_VALID_OUT(FTMD_TRACEIN_VALID_tracebuf),
.TRACE_DATA_OUT(FTMD_TRACEIN_DATA_tracebuf)
);
assign FTMD_TRACEIN_DATA_i = FTMD_TRACEIN_DATA_tracebuf;
assign FTMD_TRACEIN_VALID_i = FTMD_TRACEIN_VALID_tracebuf;
assign FTMD_TRACEIN_ATID_i = FTMD_TRACEIN_ATID_tracebuf;
end
end
endgenerate
// ID Width Control on AXI Slave ports
// S_AXI_GP0
function [5:0] id_in_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_in;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_in_gp0 = {5'b0, axi_id_gp0_in};
2: id_in_gp0 = {4'b0, axi_id_gp0_in};
3: id_in_gp0 = {3'b0, axi_id_gp0_in};
4: id_in_gp0 = {2'b0, axi_id_gp0_in};
5: id_in_gp0 = {1'b0, axi_id_gp0_in};
6: id_in_gp0 = axi_id_gp0_in;
default : id_in_gp0 = axi_id_gp0_in;
endcase
end
endfunction
assign S_AXI_GP0_ARID_in = id_in_gp0(S_AXI_GP0_ARID);
assign S_AXI_GP0_AWID_in = id_in_gp0(S_AXI_GP0_AWID);
assign S_AXI_GP0_WID_in = id_in_gp0(S_AXI_GP0_WID);
function [5:0] id_out_gp0;
input [(C_S_AXI_GP0_ID_WIDTH - 1) : 0] axi_id_gp0_out;
begin
case (C_S_AXI_GP0_ID_WIDTH)
1: id_out_gp0 = axi_id_gp0_out[0];
2: id_out_gp0 = axi_id_gp0_out[1:0];
3: id_out_gp0 = axi_id_gp0_out[2:0];
4: id_out_gp0 = axi_id_gp0_out[3:0];
5: id_out_gp0 = axi_id_gp0_out[4:0];
6: id_out_gp0 = axi_id_gp0_out;
default : id_out_gp0 = axi_id_gp0_out;
endcase
end
endfunction
assign S_AXI_GP0_BID = id_out_gp0(S_AXI_GP0_BID_out);
assign S_AXI_GP0_RID = id_out_gp0(S_AXI_GP0_RID_out);
// S_AXI_GP1
function [5:0] id_in_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_in;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_in_gp1 = {5'b0, axi_id_gp1_in};
2: id_in_gp1 = {4'b0, axi_id_gp1_in};
3: id_in_gp1 = {3'b0, axi_id_gp1_in};
4: id_in_gp1 = {2'b0, axi_id_gp1_in};
5: id_in_gp1 = {1'b0, axi_id_gp1_in};
6: id_in_gp1 = axi_id_gp1_in;
default : id_in_gp1 = axi_id_gp1_in;
endcase
end
endfunction
assign S_AXI_GP1_ARID_in = id_in_gp1(S_AXI_GP1_ARID);
assign S_AXI_GP1_AWID_in = id_in_gp1(S_AXI_GP1_AWID);
assign S_AXI_GP1_WID_in = id_in_gp1(S_AXI_GP1_WID);
function [5:0] id_out_gp1;
input [(C_S_AXI_GP1_ID_WIDTH - 1) : 0] axi_id_gp1_out;
begin
case (C_S_AXI_GP1_ID_WIDTH)
1: id_out_gp1 = axi_id_gp1_out[0];
2: id_out_gp1 = axi_id_gp1_out[1:0];
3: id_out_gp1 = axi_id_gp1_out[2:0];
4: id_out_gp1 = axi_id_gp1_out[3:0];
5: id_out_gp1 = axi_id_gp1_out[4:0];
6: id_out_gp1 = axi_id_gp1_out;
default : id_out_gp1 = axi_id_gp1_out;
endcase
end
endfunction
assign S_AXI_GP1_BID = id_out_gp1(S_AXI_GP1_BID_out);
assign S_AXI_GP1_RID = id_out_gp1(S_AXI_GP1_RID_out);
// S_AXI_HP0
function [5:0] id_in_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_in;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_in_hp0 = {5'b0, axi_id_hp0_in};
2: id_in_hp0 = {4'b0, axi_id_hp0_in};
3: id_in_hp0 = {3'b0, axi_id_hp0_in};
4: id_in_hp0 = {2'b0, axi_id_hp0_in};
5: id_in_hp0 = {1'b0, axi_id_hp0_in};
6: id_in_hp0 = axi_id_hp0_in;
default : id_in_hp0 = axi_id_hp0_in;
endcase
end
endfunction
assign S_AXI_HP0_ARID_in = id_in_hp0(S_AXI_HP0_ARID);
assign S_AXI_HP0_AWID_in = id_in_hp0(S_AXI_HP0_AWID);
assign S_AXI_HP0_WID_in = id_in_hp0(S_AXI_HP0_WID);
function [5:0] id_out_hp0;
input [(C_S_AXI_HP0_ID_WIDTH - 1) : 0] axi_id_hp0_out;
begin
case (C_S_AXI_HP0_ID_WIDTH)
1: id_out_hp0 = axi_id_hp0_out[0];
2: id_out_hp0 = axi_id_hp0_out[1:0];
3: id_out_hp0 = axi_id_hp0_out[2:0];
4: id_out_hp0 = axi_id_hp0_out[3:0];
5: id_out_hp0 = axi_id_hp0_out[4:0];
6: id_out_hp0 = axi_id_hp0_out;
default : id_out_hp0 = axi_id_hp0_out;
endcase
end
endfunction
assign S_AXI_HP0_BID = id_out_hp0(S_AXI_HP0_BID_out);
assign S_AXI_HP0_RID = id_out_hp0(S_AXI_HP0_RID_out);
assign S_AXI_HP0_WDATA_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WDATA : {32'b0,S_AXI_HP0_WDATA};
assign S_AXI_HP0_WSTRB_in = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_WSTRB : {4'b0,S_AXI_HP0_WSTRB};
assign S_AXI_HP0_RDATA = (C_S_AXI_HP0_DATA_WIDTH == 64) ? S_AXI_HP0_RDATA_out : S_AXI_HP0_RDATA_out[31:0];
// S_AXI_HP1
function [5:0] id_in_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_in;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_in_hp1 = {5'b0, axi_id_hp1_in};
2: id_in_hp1 = {4'b0, axi_id_hp1_in};
3: id_in_hp1 = {3'b0, axi_id_hp1_in};
4: id_in_hp1 = {2'b0, axi_id_hp1_in};
5: id_in_hp1 = {1'b0, axi_id_hp1_in};
6: id_in_hp1 = axi_id_hp1_in;
default : id_in_hp1 = axi_id_hp1_in;
endcase
end
endfunction
assign S_AXI_HP1_ARID_in = id_in_hp1(S_AXI_HP1_ARID);
assign S_AXI_HP1_AWID_in = id_in_hp1(S_AXI_HP1_AWID);
assign S_AXI_HP1_WID_in = id_in_hp1(S_AXI_HP1_WID);
function [5:0] id_out_hp1;
input [(C_S_AXI_HP1_ID_WIDTH - 1) : 0] axi_id_hp1_out;
begin
case (C_S_AXI_HP1_ID_WIDTH)
1: id_out_hp1 = axi_id_hp1_out[0];
2: id_out_hp1 = axi_id_hp1_out[1:0];
3: id_out_hp1 = axi_id_hp1_out[2:0];
4: id_out_hp1 = axi_id_hp1_out[3:0];
5: id_out_hp1 = axi_id_hp1_out[4:0];
6: id_out_hp1 = axi_id_hp1_out;
default : id_out_hp1 = axi_id_hp1_out;
endcase
end
endfunction
assign S_AXI_HP1_BID = id_out_hp1(S_AXI_HP1_BID_out);
assign S_AXI_HP1_RID = id_out_hp1(S_AXI_HP1_RID_out);
assign S_AXI_HP1_WDATA_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WDATA : {32'b0,S_AXI_HP1_WDATA};
assign S_AXI_HP1_WSTRB_in = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_WSTRB : {4'b0,S_AXI_HP1_WSTRB};
assign S_AXI_HP1_RDATA = (C_S_AXI_HP1_DATA_WIDTH == 64) ? S_AXI_HP1_RDATA_out : S_AXI_HP1_RDATA_out[31:0];
// S_AXI_HP2
function [5:0] id_in_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_in;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_in_hp2 = {5'b0, axi_id_hp2_in};
2: id_in_hp2 = {4'b0, axi_id_hp2_in};
3: id_in_hp2 = {3'b0, axi_id_hp2_in};
4: id_in_hp2 = {2'b0, axi_id_hp2_in};
5: id_in_hp2 = {1'b0, axi_id_hp2_in};
6: id_in_hp2 = axi_id_hp2_in;
default : id_in_hp2 = axi_id_hp2_in;
endcase
end
endfunction
assign S_AXI_HP2_ARID_in = id_in_hp2(S_AXI_HP2_ARID);
assign S_AXI_HP2_AWID_in = id_in_hp2(S_AXI_HP2_AWID);
assign S_AXI_HP2_WID_in = id_in_hp2(S_AXI_HP2_WID);
function [5:0] id_out_hp2;
input [(C_S_AXI_HP2_ID_WIDTH - 1) : 0] axi_id_hp2_out;
begin
case (C_S_AXI_HP2_ID_WIDTH)
1: id_out_hp2 = axi_id_hp2_out[0];
2: id_out_hp2 = axi_id_hp2_out[1:0];
3: id_out_hp2 = axi_id_hp2_out[2:0];
4: id_out_hp2 = axi_id_hp2_out[3:0];
5: id_out_hp2 = axi_id_hp2_out[4:0];
6: id_out_hp2 = axi_id_hp2_out;
default : id_out_hp2 = axi_id_hp2_out;
endcase
end
endfunction
assign S_AXI_HP2_BID = id_out_hp2(S_AXI_HP2_BID_out);
assign S_AXI_HP2_RID = id_out_hp2(S_AXI_HP2_RID_out);
assign S_AXI_HP2_WDATA_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WDATA : {32'b0,S_AXI_HP2_WDATA};
assign S_AXI_HP2_WSTRB_in = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_WSTRB : {4'b0,S_AXI_HP2_WSTRB};
assign S_AXI_HP2_RDATA = (C_S_AXI_HP2_DATA_WIDTH == 64) ? S_AXI_HP2_RDATA_out : S_AXI_HP2_RDATA_out[31:0];
// S_AXI_HP3
function [5:0] id_in_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_in;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_in_hp3 = {5'b0, axi_id_hp3_in};
2: id_in_hp3 = {4'b0, axi_id_hp3_in};
3: id_in_hp3 = {3'b0, axi_id_hp3_in};
4: id_in_hp3 = {2'b0, axi_id_hp3_in};
5: id_in_hp3 = {1'b0, axi_id_hp3_in};
6: id_in_hp3 = axi_id_hp3_in;
default : id_in_hp3 = axi_id_hp3_in;
endcase
end
endfunction
assign S_AXI_HP3_ARID_in = id_in_hp3(S_AXI_HP3_ARID);
assign S_AXI_HP3_AWID_in = id_in_hp3(S_AXI_HP3_AWID);
assign S_AXI_HP3_WID_in = id_in_hp3(S_AXI_HP3_WID);
function [5:0] id_out_hp3;
input [(C_S_AXI_HP3_ID_WIDTH - 1) : 0] axi_id_hp3_out;
begin
case (C_S_AXI_HP3_ID_WIDTH)
1: id_out_hp3 = axi_id_hp3_out[0];
2: id_out_hp3 = axi_id_hp3_out[1:0];
3: id_out_hp3 = axi_id_hp3_out[2:0];
4: id_out_hp3 = axi_id_hp3_out[3:0];
5: id_out_hp3 = axi_id_hp3_out[4:0];
6: id_out_hp3 = axi_id_hp3_out;
default : id_out_hp3 = axi_id_hp3_out;
endcase
end
endfunction
assign S_AXI_HP3_BID = id_out_hp3(S_AXI_HP3_BID_out);
assign S_AXI_HP3_RID = id_out_hp3(S_AXI_HP3_RID_out);
assign S_AXI_HP3_WDATA_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WDATA : {32'b0,S_AXI_HP3_WDATA};
assign S_AXI_HP3_WSTRB_in = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_WSTRB : {4'b0,S_AXI_HP3_WSTRB};
assign S_AXI_HP3_RDATA = (C_S_AXI_HP3_DATA_WIDTH == 64) ? S_AXI_HP3_RDATA_out : S_AXI_HP3_RDATA_out[31:0];
// S_AXI_ACP
function [2:0] id_in_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_in;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_in_acp = {2'b0, axi_id_acp_in};
2: id_in_acp = {1'b0, axi_id_acp_in};
3: id_in_acp = axi_id_acp_in;
default : id_in_acp = axi_id_acp_in;
endcase
end
endfunction
assign S_AXI_ACP_ARID_in = id_in_acp(SAXIACPARID_W);
assign S_AXI_ACP_AWID_in = id_in_acp(SAXIACPAWID_W);
assign S_AXI_ACP_WID_in = id_in_acp(SAXIACPWID_W);
function [2:0] id_out_acp;
input [(C_S_AXI_ACP_ID_WIDTH - 1) : 0] axi_id_acp_out;
begin
case (C_S_AXI_ACP_ID_WIDTH)
1: id_out_acp = axi_id_acp_out[0];
2: id_out_acp = axi_id_acp_out[1:0];
3: id_out_acp = axi_id_acp_out;
default : id_out_acp = axi_id_acp_out;
endcase
end
endfunction
assign SAXIACPBID_W = id_out_acp(S_AXI_ACP_BID_out);
assign SAXIACPRID_W = id_out_acp(S_AXI_ACP_RID_out);
// FMIO Tristate Inversion logic
//FMIO I2C0
assign I2C0_SDA_T = ~ I2C0_SDA_T_n;
assign I2C0_SCL_T = ~ I2C0_SCL_T_n;
//FMIO I2C1
assign I2C1_SDA_T = ~ I2C1_SDA_T_n;
assign I2C1_SCL_T = ~ I2C1_SCL_T_n;
//FMIO SPI0
assign SPI0_SCLK_T = ~ SPI0_SCLK_T_n;
assign SPI0_MOSI_T = ~ SPI0_MOSI_T_n;
assign SPI0_MISO_T = ~ SPI0_MISO_T_n;
assign SPI0_SS_T = ~ SPI0_SS_T_n;
//FMIO SPI1
assign SPI1_SCLK_T = ~ SPI1_SCLK_T_n;
assign SPI1_MOSI_T = ~ SPI1_MOSI_T_n;
assign SPI1_MISO_T = ~ SPI1_MISO_T_n;
assign SPI1_SS_T = ~ SPI1_SS_T_n;
// EMIO GEM0 MDIO
assign ENET0_MDIO_T = ~ ENET0_MDIO_T_n;
// EMIO GEM1 MDIO
assign ENET1_MDIO_T = ~ ENET1_MDIO_T_n;
// EMIO GPIO
assign GPIO_T = ~ GPIO_T_n;
// EMIO GPIO Width Control
function [63:0] gpio_width_adjust_in;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_in;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_in = {63'b0, gpio_in};
2: gpio_width_adjust_in = {62'b0, gpio_in};
3: gpio_width_adjust_in = {61'b0, gpio_in};
4: gpio_width_adjust_in = {60'b0, gpio_in};
5: gpio_width_adjust_in = {59'b0, gpio_in};
6: gpio_width_adjust_in = {58'b0, gpio_in};
7: gpio_width_adjust_in = {57'b0, gpio_in};
8: gpio_width_adjust_in = {56'b0, gpio_in};
9: gpio_width_adjust_in = {55'b0, gpio_in};
10: gpio_width_adjust_in = {54'b0, gpio_in};
11: gpio_width_adjust_in = {53'b0, gpio_in};
12: gpio_width_adjust_in = {52'b0, gpio_in};
13: gpio_width_adjust_in = {51'b0, gpio_in};
14: gpio_width_adjust_in = {50'b0, gpio_in};
15: gpio_width_adjust_in = {49'b0, gpio_in};
16: gpio_width_adjust_in = {48'b0, gpio_in};
17: gpio_width_adjust_in = {47'b0, gpio_in};
18: gpio_width_adjust_in = {46'b0, gpio_in};
19: gpio_width_adjust_in = {45'b0, gpio_in};
20: gpio_width_adjust_in = {44'b0, gpio_in};
21: gpio_width_adjust_in = {43'b0, gpio_in};
22: gpio_width_adjust_in = {42'b0, gpio_in};
23: gpio_width_adjust_in = {41'b0, gpio_in};
24: gpio_width_adjust_in = {40'b0, gpio_in};
25: gpio_width_adjust_in = {39'b0, gpio_in};
26: gpio_width_adjust_in = {38'b0, gpio_in};
27: gpio_width_adjust_in = {37'b0, gpio_in};
28: gpio_width_adjust_in = {36'b0, gpio_in};
29: gpio_width_adjust_in = {35'b0, gpio_in};
30: gpio_width_adjust_in = {34'b0, gpio_in};
31: gpio_width_adjust_in = {33'b0, gpio_in};
32: gpio_width_adjust_in = {32'b0, gpio_in};
33: gpio_width_adjust_in = {31'b0, gpio_in};
34: gpio_width_adjust_in = {30'b0, gpio_in};
35: gpio_width_adjust_in = {29'b0, gpio_in};
36: gpio_width_adjust_in = {28'b0, gpio_in};
37: gpio_width_adjust_in = {27'b0, gpio_in};
38: gpio_width_adjust_in = {26'b0, gpio_in};
39: gpio_width_adjust_in = {25'b0, gpio_in};
40: gpio_width_adjust_in = {24'b0, gpio_in};
41: gpio_width_adjust_in = {23'b0, gpio_in};
42: gpio_width_adjust_in = {22'b0, gpio_in};
43: gpio_width_adjust_in = {21'b0, gpio_in};
44: gpio_width_adjust_in = {20'b0, gpio_in};
45: gpio_width_adjust_in = {19'b0, gpio_in};
46: gpio_width_adjust_in = {18'b0, gpio_in};
47: gpio_width_adjust_in = {17'b0, gpio_in};
48: gpio_width_adjust_in = {16'b0, gpio_in};
49: gpio_width_adjust_in = {15'b0, gpio_in};
50: gpio_width_adjust_in = {14'b0, gpio_in};
51: gpio_width_adjust_in = {13'b0, gpio_in};
52: gpio_width_adjust_in = {12'b0, gpio_in};
53: gpio_width_adjust_in = {11'b0, gpio_in};
54: gpio_width_adjust_in = {10'b0, gpio_in};
55: gpio_width_adjust_in = {9'b0, gpio_in};
56: gpio_width_adjust_in = {8'b0, gpio_in};
57: gpio_width_adjust_in = {7'b0, gpio_in};
58: gpio_width_adjust_in = {6'b0, gpio_in};
59: gpio_width_adjust_in = {5'b0, gpio_in};
60: gpio_width_adjust_in = {4'b0, gpio_in};
61: gpio_width_adjust_in = {3'b0, gpio_in};
62: gpio_width_adjust_in = {2'b0, gpio_in};
63: gpio_width_adjust_in = {1'b0, gpio_in};
64: gpio_width_adjust_in = gpio_in;
default : gpio_width_adjust_in = gpio_in;
endcase
end
endfunction
assign gpio_in63_0 = gpio_width_adjust_in(GPIO_I);
function [63:0] gpio_width_adjust_out;
input [(C_EMIO_GPIO_WIDTH - 1) : 0] gpio_o;
begin
case (C_EMIO_GPIO_WIDTH)
1: gpio_width_adjust_out = gpio_o[0];
2: gpio_width_adjust_out = gpio_o[1:0];
3: gpio_width_adjust_out = gpio_o[2:0];
4: gpio_width_adjust_out = gpio_o[3:0];
5: gpio_width_adjust_out = gpio_o[4:0];
6: gpio_width_adjust_out = gpio_o[5:0];
7: gpio_width_adjust_out = gpio_o[6:0];
8: gpio_width_adjust_out = gpio_o[7:0];
9: gpio_width_adjust_out = gpio_o[8:0];
10: gpio_width_adjust_out = gpio_o[9:0];
11: gpio_width_adjust_out = gpio_o[10:0];
12: gpio_width_adjust_out = gpio_o[11:0];
13: gpio_width_adjust_out = gpio_o[12:0];
14: gpio_width_adjust_out = gpio_o[13:0];
15: gpio_width_adjust_out = gpio_o[14:0];
16: gpio_width_adjust_out = gpio_o[15:0];
17: gpio_width_adjust_out = gpio_o[16:0];
18: gpio_width_adjust_out = gpio_o[17:0];
19: gpio_width_adjust_out = gpio_o[18:0];
20: gpio_width_adjust_out = gpio_o[19:0];
21: gpio_width_adjust_out = gpio_o[20:0];
22: gpio_width_adjust_out = gpio_o[21:0];
23: gpio_width_adjust_out = gpio_o[22:0];
24: gpio_width_adjust_out = gpio_o[23:0];
25: gpio_width_adjust_out = gpio_o[24:0];
26: gpio_width_adjust_out = gpio_o[25:0];
27: gpio_width_adjust_out = gpio_o[26:0];
28: gpio_width_adjust_out = gpio_o[27:0];
29: gpio_width_adjust_out = gpio_o[28:0];
30: gpio_width_adjust_out = gpio_o[29:0];
31: gpio_width_adjust_out = gpio_o[30:0];
32: gpio_width_adjust_out = gpio_o[31:0];
33: gpio_width_adjust_out = gpio_o[32:0];
34: gpio_width_adjust_out = gpio_o[33:0];
35: gpio_width_adjust_out = gpio_o[34:0];
36: gpio_width_adjust_out = gpio_o[35:0];
37: gpio_width_adjust_out = gpio_o[36:0];
38: gpio_width_adjust_out = gpio_o[37:0];
39: gpio_width_adjust_out = gpio_o[38:0];
40: gpio_width_adjust_out = gpio_o[39:0];
41: gpio_width_adjust_out = gpio_o[40:0];
42: gpio_width_adjust_out = gpio_o[41:0];
43: gpio_width_adjust_out = gpio_o[42:0];
44: gpio_width_adjust_out = gpio_o[43:0];
45: gpio_width_adjust_out = gpio_o[44:0];
46: gpio_width_adjust_out = gpio_o[45:0];
47: gpio_width_adjust_out = gpio_o[46:0];
48: gpio_width_adjust_out = gpio_o[47:0];
49: gpio_width_adjust_out = gpio_o[48:0];
50: gpio_width_adjust_out = gpio_o[49:0];
51: gpio_width_adjust_out = gpio_o[50:0];
52: gpio_width_adjust_out = gpio_o[51:0];
53: gpio_width_adjust_out = gpio_o[52:0];
54: gpio_width_adjust_out = gpio_o[53:0];
55: gpio_width_adjust_out = gpio_o[54:0];
56: gpio_width_adjust_out = gpio_o[55:0];
57: gpio_width_adjust_out = gpio_o[56:0];
58: gpio_width_adjust_out = gpio_o[57:0];
59: gpio_width_adjust_out = gpio_o[58:0];
60: gpio_width_adjust_out = gpio_o[59:0];
61: gpio_width_adjust_out = gpio_o[60:0];
62: gpio_width_adjust_out = gpio_o[61:0];
63: gpio_width_adjust_out = gpio_o[62:0];
64: gpio_width_adjust_out = gpio_o;
default : gpio_width_adjust_out = gpio_o;
endcase
end
endfunction
assign GPIO_O[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out);
assign GPIO_T_n[(C_EMIO_GPIO_WIDTH - 1) : 0] = gpio_width_adjust_out(gpio_out_t_n);
// Adding OBUFT to JTAG out port
generate
if ( C_EN_EMIO_PJTAG == 1 ) begin : PJTAG_OBUFT_TRUE
OBUFT jtag_obuft_inst (
.O(PJTAG_TDO),
.I(PJTAG_TDO_O),
.T(PJTAG_TDO_T)
);
end
endgenerate
// -------
// EMIO PJTAG
assign PJTAG_TDO_T = ~ PJTAG_TDO_T_n;
// EMIO SDIO0 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO0_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO0_CMD_T_n) : (~ SDIO0_CMD_T_n);
assign SDIO0_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO0_DATA_T_n[3:0]) : (~ SDIO0_DATA_T_n[3:0]);
// EMIO SDIO1 : No negation required as per CR#636210 for 1.0 version of Silicon,
// FOR Other SI REV, inversion is required
assign SDIO1_CMD_T = (C_PS7_SI_REV == "1.0") ? (SDIO1_CMD_T_n) : (~ SDIO1_CMD_T_n);
assign SDIO1_DATA_T[3:0] = (C_PS7_SI_REV == "1.0") ? (SDIO1_DATA_T_n[3:0]) : (~ SDIO1_DATA_T_n[3:0]);
// FCLK_CLK optional clock buffers
generate
if (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") begin : buffer_fclk_clk_0
BUFG FCLK_CLK_0_BUFG (.I(FCLK_CLK_unbuffered[0]), .O(FCLK_CLK_buffered[0]));
end
if (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") begin : buffer_fclk_clk_1
BUFG FCLK_CLK_1_BUFG (.I(FCLK_CLK_unbuffered[1]), .O(FCLK_CLK_buffered[1]));
end
if (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") begin : buffer_fclk_clk_2
BUFG FCLK_CLK_2_BUFG (.I(FCLK_CLK_unbuffered[2]), .O(FCLK_CLK_buffered[2]));
end
if (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") begin : buffer_fclk_clk_3
BUFG FCLK_CLK_3_BUFG (.I(FCLK_CLK_unbuffered[3]), .O(FCLK_CLK_buffered[3]));
end
endgenerate
assign FCLK_CLK0 = (C_FCLK_CLK0_BUF == "TRUE" | C_FCLK_CLK0_BUF == "true") ? FCLK_CLK_buffered[0] : FCLK_CLK_unbuffered[0];
assign FCLK_CLK1 = (C_FCLK_CLK1_BUF == "TRUE" | C_FCLK_CLK1_BUF == "true") ? FCLK_CLK_buffered[1] : FCLK_CLK_unbuffered[1];
assign FCLK_CLK2 = (C_FCLK_CLK2_BUF == "TRUE" | C_FCLK_CLK2_BUF == "true") ? FCLK_CLK_buffered[2] : FCLK_CLK_unbuffered[2];
assign FCLK_CLK3 = (C_FCLK_CLK3_BUF == "TRUE" | C_FCLK_CLK3_BUF == "true") ? FCLK_CLK_buffered[3] : FCLK_CLK_unbuffered[3];
// Adding BIBUF for fixed IO Ports and IBUF for fixed Input Ports
BIBUF DDR_CAS_n_BIBUF (.PAD(DDR_CAS_n), .IO(buffered_DDR_CAS_n));
BIBUF DDR_CKE_BIBUF (.PAD(DDR_CKE), .IO(buffered_DDR_CKE));
BIBUF DDR_Clk_n_BIBUF (.PAD(DDR_Clk_n), .IO(buffered_DDR_Clk_n));
BIBUF DDR_Clk_BIBUF (.PAD(DDR_Clk), .IO(buffered_DDR_Clk));
BIBUF DDR_CS_n_BIBUF (.PAD(DDR_CS_n), .IO(buffered_DDR_CS_n));
BIBUF DDR_DRSTB_BIBUF (.PAD(DDR_DRSTB), .IO(buffered_DDR_DRSTB));
BIBUF DDR_ODT_BIBUF (.PAD(DDR_ODT), .IO(buffered_DDR_ODT));
BIBUF DDR_RAS_n_BIBUF (.PAD(DDR_RAS_n), .IO(buffered_DDR_RAS_n));
BIBUF DDR_WEB_BIBUF (.PAD(DDR_WEB), .IO(buffered_DDR_WEB));
BIBUF DDR_VRN_BIBUF (.PAD(DDR_VRN), .IO(buffered_DDR_VRN));
BIBUF DDR_VRP_BIBUF (.PAD(DDR_VRP), .IO(buffered_DDR_VRP));
BIBUF PS_SRSTB_BIBUF (.PAD(PS_SRSTB), .IO(buffered_PS_SRSTB));
BIBUF PS_CLK_BIBUF (.PAD(PS_CLK), .IO(buffered_PS_CLK));
BIBUF PS_PORB_BIBUF (.PAD(PS_PORB), .IO(buffered_PS_PORB));
genvar i;
generate
for (i=0; i < C_MIO_PRIMITIVE; i=i+1) begin
BIBUF MIO_BIBUF (.PAD(MIO[i]), .IO(buffered_MIO[i]));
end
endgenerate
generate
for (i=0; i < 3; i=i+1) begin
BIBUF DDR_BankAddr_BIBUF (.PAD(DDR_BankAddr[i]), .IO(buffered_DDR_BankAddr[i]));
end
endgenerate
generate
for (i=0; i < 15; i=i+1) begin
BIBUF DDR_Addr_BIBUF (.PAD(DDR_Addr[i]), .IO(buffered_DDR_Addr[i]));
end
endgenerate
generate
for (i=0; i < C_DM_WIDTH; i=i+1) begin
BIBUF DDR_DM_BIBUF (.PAD(DDR_DM[i]), .IO(buffered_DDR_DM[i]));
end
endgenerate
generate
for (i=0; i < C_DQ_WIDTH; i=i+1) begin
BIBUF DDR_DQ_BIBUF (.PAD(DDR_DQ[i]), .IO(buffered_DDR_DQ[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_n_BIBUF (.PAD(DDR_DQS_n[i]), .IO(buffered_DDR_DQS_n[i]));
end
endgenerate
generate
for (i=0; i < C_DQS_WIDTH; i=i+1) begin
BIBUF DDR_DQS_BIBUF (.PAD(DDR_DQS[i]), .IO(buffered_DDR_DQS[i]));
end
endgenerate
//====================
//PSS TOP
//====================
generate
if (C_PACKAGE_NAME == "clg225" ) begin
wire [21:0] dummy;
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO ({buffered_MIO[31:30],dummy[21:20],buffered_MIO[29:28],dummy[19:12],buffered_MIO[27:16],dummy[11:0],buffered_MIO[15:0]}),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
else begin
PS7 PS7_i (
.DMA0DATYPE (DMA0_DATYPE ),
.DMA0DAVALID (DMA0_DAVALID),
.DMA0DRREADY (DMA0_DRREADY),
.DMA0RSTN (DMA0_RSTN ),
.DMA1DATYPE (DMA1_DATYPE ),
.DMA1DAVALID (DMA1_DAVALID),
.DMA1DRREADY (DMA1_DRREADY),
.DMA1RSTN (DMA1_RSTN ),
.DMA2DATYPE (DMA2_DATYPE ),
.DMA2DAVALID (DMA2_DAVALID),
.DMA2DRREADY (DMA2_DRREADY),
.DMA2RSTN (DMA2_RSTN ),
.DMA3DATYPE (DMA3_DATYPE ),
.DMA3DAVALID (DMA3_DAVALID),
.DMA3DRREADY (DMA3_DRREADY),
.DMA3RSTN (DMA3_RSTN ),
.EMIOCAN0PHYTX (CAN0_PHY_TX ),
.EMIOCAN1PHYTX (CAN1_PHY_TX ),
.EMIOENET0GMIITXD (ENET0_GMII_TXD_i ),
.EMIOENET0GMIITXEN (ENET0_GMII_TX_EN_i),
.EMIOENET0GMIITXER (ENET0_GMII_TX_ER_i),
.EMIOENET0MDIOMDC (ENET0_MDIO_MDC),
.EMIOENET0MDIOO (ENET0_MDIO_O ),
.EMIOENET0MDIOTN (ENET0_MDIO_T_n ),
.EMIOENET0PTPDELAYREQRX (ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX (ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX (ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX (ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX (ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX (ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX (ENET0_SOF_RX),
.EMIOENET0SOFTX (ENET0_SOF_TX),
.EMIOENET1GMIITXD (ENET1_GMII_TXD_i),
.EMIOENET1GMIITXEN (ENET1_GMII_TX_EN_i),
.EMIOENET1GMIITXER (ENET1_GMII_TX_ER_i),
.EMIOENET1MDIOMDC (ENET1_MDIO_MDC),
.EMIOENET1MDIOO (ENET1_MDIO_O ),
.EMIOENET1MDIOTN (ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX (ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX (ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX (ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX (ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX (ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX (ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX (ENET1_SOF_RX),
.EMIOENET1SOFTX (ENET1_SOF_TX),
.EMIOGPIOO (gpio_out),
.EMIOGPIOTN (gpio_out_t_n),
.EMIOI2C0SCLO (I2C0_SCL_O),
.EMIOI2C0SCLTN (I2C0_SCL_T_n),
.EMIOI2C0SDAO (I2C0_SDA_O),
.EMIOI2C0SDATN (I2C0_SDA_T_n),
.EMIOI2C1SCLO (I2C1_SCL_O),
.EMIOI2C1SCLTN (I2C1_SCL_T_n),
.EMIOI2C1SDAO (I2C1_SDA_O),
.EMIOI2C1SDATN (I2C1_SDA_T_n),
.EMIOPJTAGTDO (PJTAG_TDO_O),
.EMIOPJTAGTDTN (PJTAG_TDO_T_n),
.EMIOSDIO0BUSPOW (SDIO0_BUSPOW),
.EMIOSDIO0CLK (SDIO0_CLK ),
.EMIOSDIO0CMDO (SDIO0_CMD_O ),
.EMIOSDIO0CMDTN (SDIO0_CMD_T_n ),
.EMIOSDIO0DATAO (SDIO0_DATA_O),
.EMIOSDIO0DATATN (SDIO0_DATA_T_n),
.EMIOSDIO0LED (SDIO0_LED),
.EMIOSDIO1BUSPOW (SDIO1_BUSPOW),
.EMIOSDIO1CLK (SDIO1_CLK ),
.EMIOSDIO1CMDO (SDIO1_CMD_O ),
.EMIOSDIO1CMDTN (SDIO1_CMD_T_n ),
.EMIOSDIO1DATAO (SDIO1_DATA_O),
.EMIOSDIO1DATATN (SDIO1_DATA_T_n),
.EMIOSDIO1LED (SDIO1_LED),
.EMIOSPI0MO (SPI0_MOSI_O),
.EMIOSPI0MOTN (SPI0_MOSI_T_n),
.EMIOSPI0SCLKO (SPI0_SCLK_O),
.EMIOSPI0SCLKTN (SPI0_SCLK_T_n),
.EMIOSPI0SO (SPI0_MISO_O),
.EMIOSPI0STN (SPI0_MISO_T_n),
.EMIOSPI0SSON ({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0SSNTN (SPI0_SS_T_n),
.EMIOSPI1MO (SPI1_MOSI_O),
.EMIOSPI1MOTN (SPI1_MOSI_T_n),
.EMIOSPI1SCLKO (SPI1_SCLK_O),
.EMIOSPI1SCLKTN (SPI1_SCLK_T_n),
.EMIOSPI1SO (SPI1_MISO_O),
.EMIOSPI1STN (SPI1_MISO_T_n),
.EMIOSPI1SSON ({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1SSNTN (SPI1_SS_T_n),
.EMIOTRACECTL (TRACE_CTL_i),
.EMIOTRACEDATA (TRACE_DATA_i),
.EMIOTTC0WAVEO ({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1WAVEO ({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0DTRN (UART0_DTRN),
.EMIOUART0RTSN (UART0_RTSN),
.EMIOUART0TX (UART0_TX ),
.EMIOUART1DTRN (UART1_DTRN),
.EMIOUART1RTSN (UART1_RTSN),
.EMIOUART1TX (UART1_TX ),
.EMIOUSB0PORTINDCTL (USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRSELECT (USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL (USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRSELECT (USB1_VBUS_PWRSELECT),
.EMIOWDTRSTO (WDT_RST_OUT),
.EVENTEVENTO (EVENT_EVENTO),
.EVENTSTANDBYWFE (EVENT_STANDBYWFE),
.EVENTSTANDBYWFI (EVENT_STANDBYWFI),
.FCLKCLK (FCLK_CLK_unbuffered),
.FCLKRESETN ({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.EMIOSDIO0BUSVOLT (SDIO0_BUSVOLT),
.EMIOSDIO1BUSVOLT (SDIO1_BUSVOLT),
.FTMTF2PTRIGACK ({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG (FTMT_P2F_DEBUG ),
.FTMTP2FTRIG ({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.IRQP2F ({IRQ_P2F_DMAC_ABORT, IRQ_P2F_DMAC7, IRQ_P2F_DMAC6, IRQ_P2F_DMAC5, IRQ_P2F_DMAC4, IRQ_P2F_DMAC3, IRQ_P2F_DMAC2, IRQ_P2F_DMAC1, IRQ_P2F_DMAC0, IRQ_P2F_SMC, IRQ_P2F_QSPI, IRQ_P2F_CTI, IRQ_P2F_GPIO, IRQ_P2F_USB0, IRQ_P2F_ENET0, IRQ_P2F_ENET_WAKE0, IRQ_P2F_SDIO0, IRQ_P2F_I2C0, IRQ_P2F_SPI0, IRQ_P2F_UART0, IRQ_P2F_CAN0, IRQ_P2F_USB1, IRQ_P2F_ENET1, IRQ_P2F_ENET_WAKE1, IRQ_P2F_SDIO1, IRQ_P2F_I2C1, IRQ_P2F_SPI1, IRQ_P2F_UART1, IRQ_P2F_CAN1}),
.MAXIGP0ARADDR (M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST (M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE (M_AXI_GP0_ARCACHE),
.MAXIGP0ARESETN (M_AXI_GP0_ARESETN),
.MAXIGP0ARID (M_AXI_GP0_ARID_FULL ),
.MAXIGP0ARLEN (M_AXI_GP0_ARLEN ),
.MAXIGP0ARLOCK (M_AXI_GP0_ARLOCK ),
.MAXIGP0ARPROT (M_AXI_GP0_ARPROT ),
.MAXIGP0ARQOS (M_AXI_GP0_ARQOS ),
.MAXIGP0ARSIZE (M_AXI_GP0_ARSIZE_i ),
.MAXIGP0ARVALID (M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR (M_AXI_GP0_AWADDR ),
.MAXIGP0AWBURST (M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE (M_AXI_GP0_AWCACHE),
.MAXIGP0AWID (M_AXI_GP0_AWID_FULL ),
.MAXIGP0AWLEN (M_AXI_GP0_AWLEN ),
.MAXIGP0AWLOCK (M_AXI_GP0_AWLOCK ),
.MAXIGP0AWPROT (M_AXI_GP0_AWPROT ),
.MAXIGP0AWQOS (M_AXI_GP0_AWQOS ),
.MAXIGP0AWSIZE (M_AXI_GP0_AWSIZE_i ),
.MAXIGP0AWVALID (M_AXI_GP0_AWVALID),
.MAXIGP0BREADY (M_AXI_GP0_BREADY ),
.MAXIGP0RREADY (M_AXI_GP0_RREADY ),
.MAXIGP0WDATA (M_AXI_GP0_WDATA ),
.MAXIGP0WID (M_AXI_GP0_WID_FULL ),
.MAXIGP0WLAST (M_AXI_GP0_WLAST ),
.MAXIGP0WSTRB (M_AXI_GP0_WSTRB ),
.MAXIGP0WVALID (M_AXI_GP0_WVALID ),
.MAXIGP1ARADDR (M_AXI_GP1_ARADDR ),
.MAXIGP1ARBURST (M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE (M_AXI_GP1_ARCACHE),
.MAXIGP1ARESETN (M_AXI_GP1_ARESETN),
.MAXIGP1ARID (M_AXI_GP1_ARID_FULL ),
.MAXIGP1ARLEN (M_AXI_GP1_ARLEN ),
.MAXIGP1ARLOCK (M_AXI_GP1_ARLOCK ),
.MAXIGP1ARPROT (M_AXI_GP1_ARPROT ),
.MAXIGP1ARQOS (M_AXI_GP1_ARQOS ),
.MAXIGP1ARSIZE (M_AXI_GP1_ARSIZE_i ),
.MAXIGP1ARVALID (M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR (M_AXI_GP1_AWADDR ),
.MAXIGP1AWBURST (M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE (M_AXI_GP1_AWCACHE),
.MAXIGP1AWID (M_AXI_GP1_AWID_FULL ),
.MAXIGP1AWLEN (M_AXI_GP1_AWLEN ),
.MAXIGP1AWLOCK (M_AXI_GP1_AWLOCK ),
.MAXIGP1AWPROT (M_AXI_GP1_AWPROT ),
.MAXIGP1AWQOS (M_AXI_GP1_AWQOS ),
.MAXIGP1AWSIZE (M_AXI_GP1_AWSIZE_i ),
.MAXIGP1AWVALID (M_AXI_GP1_AWVALID),
.MAXIGP1BREADY (M_AXI_GP1_BREADY ),
.MAXIGP1RREADY (M_AXI_GP1_RREADY ),
.MAXIGP1WDATA (M_AXI_GP1_WDATA ),
.MAXIGP1WID (M_AXI_GP1_WID_FULL ),
.MAXIGP1WLAST (M_AXI_GP1_WLAST ),
.MAXIGP1WSTRB (M_AXI_GP1_WSTRB ),
.MAXIGP1WVALID (M_AXI_GP1_WVALID ),
.SAXIACPARESETN (S_AXI_ACP_ARESETN),
.SAXIACPARREADY (SAXIACPARREADY_W),
.SAXIACPAWREADY (SAXIACPAWREADY_W),
.SAXIACPBID (S_AXI_ACP_BID_out ),
.SAXIACPBRESP (SAXIACPBRESP_W ),
.SAXIACPBVALID (SAXIACPBVALID_W ),
.SAXIACPRDATA (SAXIACPRDATA_W ),
.SAXIACPRID (S_AXI_ACP_RID_out),
.SAXIACPRLAST (SAXIACPRLAST_W ),
.SAXIACPRRESP (SAXIACPRRESP_W ),
.SAXIACPRVALID (SAXIACPRVALID_W ),
.SAXIACPWREADY (SAXIACPWREADY_W ),
.SAXIGP0ARESETN (S_AXI_GP0_ARESETN),
.SAXIGP0ARREADY (S_AXI_GP0_ARREADY),
.SAXIGP0AWREADY (S_AXI_GP0_AWREADY),
.SAXIGP0BID (S_AXI_GP0_BID_out),
.SAXIGP0BRESP (S_AXI_GP0_BRESP ),
.SAXIGP0BVALID (S_AXI_GP0_BVALID ),
.SAXIGP0RDATA (S_AXI_GP0_RDATA ),
.SAXIGP0RID (S_AXI_GP0_RID_out ),
.SAXIGP0RLAST (S_AXI_GP0_RLAST ),
.SAXIGP0RRESP (S_AXI_GP0_RRESP ),
.SAXIGP0RVALID (S_AXI_GP0_RVALID ),
.SAXIGP0WREADY (S_AXI_GP0_WREADY ),
.SAXIGP1ARESETN (S_AXI_GP1_ARESETN),
.SAXIGP1ARREADY (S_AXI_GP1_ARREADY),
.SAXIGP1AWREADY (S_AXI_GP1_AWREADY),
.SAXIGP1BID (S_AXI_GP1_BID_out ),
.SAXIGP1BRESP (S_AXI_GP1_BRESP ),
.SAXIGP1BVALID (S_AXI_GP1_BVALID ),
.SAXIGP1RDATA (S_AXI_GP1_RDATA ),
.SAXIGP1RID (S_AXI_GP1_RID_out ),
.SAXIGP1RLAST (S_AXI_GP1_RLAST ),
.SAXIGP1RRESP (S_AXI_GP1_RRESP ),
.SAXIGP1RVALID (S_AXI_GP1_RVALID ),
.SAXIGP1WREADY (S_AXI_GP1_WREADY ),
.SAXIHP0ARESETN (S_AXI_HP0_ARESETN),
.SAXIHP0ARREADY (S_AXI_HP0_ARREADY),
.SAXIHP0AWREADY (S_AXI_HP0_AWREADY),
.SAXIHP0BID (S_AXI_HP0_BID_out ),
.SAXIHP0BRESP (S_AXI_HP0_BRESP ),
.SAXIHP0BVALID (S_AXI_HP0_BVALID ),
.SAXIHP0RACOUNT (S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT (S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA (S_AXI_HP0_RDATA_out),
.SAXIHP0RID (S_AXI_HP0_RID_out ),
.SAXIHP0RLAST (S_AXI_HP0_RLAST),
.SAXIHP0RRESP (S_AXI_HP0_RRESP),
.SAXIHP0RVALID (S_AXI_HP0_RVALID),
.SAXIHP0WCOUNT (S_AXI_HP0_WCOUNT),
.SAXIHP0WACOUNT (S_AXI_HP0_WACOUNT),
.SAXIHP0WREADY (S_AXI_HP0_WREADY),
.SAXIHP1ARESETN (S_AXI_HP1_ARESETN),
.SAXIHP1ARREADY (S_AXI_HP1_ARREADY),
.SAXIHP1AWREADY (S_AXI_HP1_AWREADY),
.SAXIHP1BID (S_AXI_HP1_BID_out ),
.SAXIHP1BRESP (S_AXI_HP1_BRESP ),
.SAXIHP1BVALID (S_AXI_HP1_BVALID ),
.SAXIHP1RACOUNT (S_AXI_HP1_RACOUNT ),
.SAXIHP1RCOUNT (S_AXI_HP1_RCOUNT ),
.SAXIHP1RDATA (S_AXI_HP1_RDATA_out),
.SAXIHP1RID (S_AXI_HP1_RID_out ),
.SAXIHP1RLAST (S_AXI_HP1_RLAST ),
.SAXIHP1RRESP (S_AXI_HP1_RRESP ),
.SAXIHP1RVALID (S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT (S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT (S_AXI_HP1_WCOUNT),
.SAXIHP1WREADY (S_AXI_HP1_WREADY),
.SAXIHP2ARESETN (S_AXI_HP2_ARESETN),
.SAXIHP2ARREADY (S_AXI_HP2_ARREADY),
.SAXIHP2AWREADY (S_AXI_HP2_AWREADY),
.SAXIHP2BID (S_AXI_HP2_BID_out ),
.SAXIHP2BRESP (S_AXI_HP2_BRESP),
.SAXIHP2BVALID (S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT (S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT (S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA (S_AXI_HP2_RDATA_out),
.SAXIHP2RID (S_AXI_HP2_RID_out ),
.SAXIHP2RLAST (S_AXI_HP2_RLAST),
.SAXIHP2RRESP (S_AXI_HP2_RRESP),
.SAXIHP2RVALID (S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT (S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT (S_AXI_HP2_WCOUNT),
.SAXIHP2WREADY (S_AXI_HP2_WREADY),
.SAXIHP3ARESETN (S_AXI_HP3_ARESETN),
.SAXIHP3ARREADY (S_AXI_HP3_ARREADY),
.SAXIHP3AWREADY (S_AXI_HP3_AWREADY),
.SAXIHP3BID (S_AXI_HP3_BID_out),
.SAXIHP3BRESP (S_AXI_HP3_BRESP),
.SAXIHP3BVALID (S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT (S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT (S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA (S_AXI_HP3_RDATA_out),
.SAXIHP3RID (S_AXI_HP3_RID_out),
.SAXIHP3RLAST (S_AXI_HP3_RLAST),
.SAXIHP3RRESP (S_AXI_HP3_RRESP),
.SAXIHP3RVALID (S_AXI_HP3_RVALID),
.SAXIHP3WCOUNT (S_AXI_HP3_WCOUNT),
.SAXIHP3WACOUNT (S_AXI_HP3_WACOUNT),
.SAXIHP3WREADY (S_AXI_HP3_WREADY),
.DDRARB (DDR_ARB),
.DMA0ACLK (DMA0_ACLK ),
.DMA0DAREADY (DMA0_DAREADY),
.DMA0DRLAST (DMA0_DRLAST ),
.DMA0DRTYPE (DMA0_DRTYPE),
.DMA0DRVALID (DMA0_DRVALID),
.DMA1ACLK (DMA1_ACLK ),
.DMA1DAREADY (DMA1_DAREADY),
.DMA1DRLAST (DMA1_DRLAST ),
.DMA1DRTYPE (DMA1_DRTYPE),
.DMA1DRVALID (DMA1_DRVALID),
.DMA2ACLK (DMA2_ACLK ),
.DMA2DAREADY (DMA2_DAREADY),
.DMA2DRLAST (DMA2_DRLAST ),
.DMA2DRTYPE (DMA2_DRTYPE),
.DMA2DRVALID (DMA2_DRVALID),
.DMA3ACLK (DMA3_ACLK ),
.DMA3DAREADY (DMA3_DAREADY),
.DMA3DRLAST (DMA3_DRLAST ),
.DMA3DRTYPE (DMA3_DRTYPE),
.DMA3DRVALID (DMA3_DRVALID),
.EMIOCAN0PHYRX (CAN0_PHY_RX),
.EMIOCAN1PHYRX (CAN1_PHY_RX),
.EMIOENET0EXTINTIN (ENET0_EXT_INTIN),
.EMIOENET0GMIICOL (ENET0_GMII_COL_i),
.EMIOENET0GMIICRS (ENET0_GMII_CRS_i),
.EMIOENET0GMIIRXCLK (ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD (ENET0_GMII_RXD_i),
.EMIOENET0GMIIRXDV (ENET0_GMII_RX_DV_i),
.EMIOENET0GMIIRXER (ENET0_GMII_RX_ER_i),
.EMIOENET0GMIITXCLK (ENET0_GMII_TX_CLK),
.EMIOENET0MDIOI (ENET0_MDIO_I),
.EMIOENET1EXTINTIN (ENET1_EXT_INTIN),
.EMIOENET1GMIICOL (ENET1_GMII_COL_i),
.EMIOENET1GMIICRS (ENET1_GMII_CRS_i),
.EMIOENET1GMIIRXCLK (ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD (ENET1_GMII_RXD_i),
.EMIOENET1GMIIRXDV (ENET1_GMII_RX_DV_i),
.EMIOENET1GMIIRXER (ENET1_GMII_RX_ER_i),
.EMIOENET1GMIITXCLK (ENET1_GMII_TX_CLK),
.EMIOENET1MDIOI (ENET1_MDIO_I),
.EMIOGPIOI (gpio_in63_0 ),
.EMIOI2C0SCLI (I2C0_SCL_I),
.EMIOI2C0SDAI (I2C0_SDA_I),
.EMIOI2C1SCLI (I2C1_SCL_I),
.EMIOI2C1SDAI (I2C1_SDA_I),
.EMIOPJTAGTCK (PJTAG_TCK),
.EMIOPJTAGTDI (PJTAG_TDI),
.EMIOPJTAGTMS (PJTAG_TMS),
.EMIOSDIO0CDN (SDIO0_CDN),
.EMIOSDIO0CLKFB (SDIO0_CLK_FB ),
.EMIOSDIO0CMDI (SDIO0_CMD_I ),
.EMIOSDIO0DATAI (SDIO0_DATA_I ),
.EMIOSDIO0WP (SDIO0_WP),
.EMIOSDIO1CDN (SDIO1_CDN),
.EMIOSDIO1CLKFB (SDIO1_CLK_FB ),
.EMIOSDIO1CMDI (SDIO1_CMD_I ),
.EMIOSDIO1DATAI (SDIO1_DATA_I ),
.EMIOSDIO1WP (SDIO1_WP),
.EMIOSPI0MI (SPI0_MISO_I),
.EMIOSPI0SCLKI (SPI0_SCLK_I),
.EMIOSPI0SI (SPI0_MOSI_I),
.EMIOSPI0SSIN (SPI0_SS_I),
.EMIOSPI1MI (SPI1_MISO_I),
.EMIOSPI1SCLKI (SPI1_SCLK_I),
.EMIOSPI1SI (SPI1_MOSI_I),
.EMIOSPI1SSIN (SPI1_SS_I),
.EMIOSRAMINTIN (SRAM_INTIN),
.EMIOTRACECLK (TRACE_CLK),
.EMIOTTC0CLKI ({TTC0_CLK2_IN, TTC0_CLK1_IN, TTC0_CLK0_IN}),
.EMIOTTC1CLKI ({TTC1_CLK2_IN, TTC1_CLK1_IN, TTC1_CLK0_IN}),
.EMIOUART0CTSN (UART0_CTSN),
.EMIOUART0DCDN (UART0_DCDN),
.EMIOUART0DSRN (UART0_DSRN),
.EMIOUART0RIN (UART0_RIN ),
.EMIOUART0RX (UART0_RX ),
.EMIOUART1CTSN (UART1_CTSN),
.EMIOUART1DCDN (UART1_DCDN),
.EMIOUART1DSRN (UART1_DSRN),
.EMIOUART1RIN (UART1_RIN ),
.EMIOUART1RX (UART1_RX ),
.EMIOUSB0VBUSPWRFAULT (USB0_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRFAULT (USB1_VBUS_PWRFAULT),
.EMIOWDTCLKI (WDT_CLK_IN),
.EVENTEVENTI (EVENT_EVENTI),
.FCLKCLKTRIGN (fclk_clktrig_gnd),
.FPGAIDLEN (FPGA_IDLE_N),
.FTMDTRACEINATID (FTMD_TRACEIN_ATID_i),
.FTMDTRACEINCLOCK (FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA (FTMD_TRACEIN_DATA_i),
.FTMDTRACEINVALID (FTMD_TRACEIN_VALID_i),
.FTMTF2PDEBUG (FTMT_F2P_DEBUG ),
.FTMTF2PTRIG ({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTP2FTRIGACK ({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P (irq_f2p_i),
.MAXIGP0ACLK (M_AXI_GP0_ACLK),
.MAXIGP0ARREADY (M_AXI_GP0_ARREADY),
.MAXIGP0AWREADY (M_AXI_GP0_AWREADY),
.MAXIGP0BID (M_AXI_GP0_BID_FULL ),
.MAXIGP0BRESP (M_AXI_GP0_BRESP ),
.MAXIGP0BVALID (M_AXI_GP0_BVALID ),
.MAXIGP0RDATA (M_AXI_GP0_RDATA ),
.MAXIGP0RID (M_AXI_GP0_RID_FULL ),
.MAXIGP0RLAST (M_AXI_GP0_RLAST ),
.MAXIGP0RRESP (M_AXI_GP0_RRESP ),
.MAXIGP0RVALID (M_AXI_GP0_RVALID ),
.MAXIGP0WREADY (M_AXI_GP0_WREADY ),
.MAXIGP1ACLK (M_AXI_GP1_ACLK ),
.MAXIGP1ARREADY (M_AXI_GP1_ARREADY),
.MAXIGP1AWREADY (M_AXI_GP1_AWREADY),
.MAXIGP1BID (M_AXI_GP1_BID_FULL ),
.MAXIGP1BRESP (M_AXI_GP1_BRESP ),
.MAXIGP1BVALID (M_AXI_GP1_BVALID ),
.MAXIGP1RDATA (M_AXI_GP1_RDATA ),
.MAXIGP1RID (M_AXI_GP1_RID_FULL ),
.MAXIGP1RLAST (M_AXI_GP1_RLAST ),
.MAXIGP1RRESP (M_AXI_GP1_RRESP ),
.MAXIGP1RVALID (M_AXI_GP1_RVALID ),
.MAXIGP1WREADY (M_AXI_GP1_WREADY ),
.SAXIACPACLK (S_AXI_ACP_ACLK ),
.SAXIACPARADDR (SAXIACPARADDR_W ),
.SAXIACPARBURST (SAXIACPARBURST_W),
.SAXIACPARCACHE (SAXIACPARCACHE_W),
.SAXIACPARID (S_AXI_ACP_ARID_in ),
.SAXIACPARLEN (SAXIACPARLEN_W ),
.SAXIACPARLOCK (SAXIACPARLOCK_W ),
.SAXIACPARPROT (SAXIACPARPROT_W ),
.SAXIACPARQOS (S_AXI_ACP_ARQOS ),
.SAXIACPARSIZE (SAXIACPARSIZE_W[1:0] ),
.SAXIACPARUSER (SAXIACPARUSER_W ),
.SAXIACPARVALID (SAXIACPARVALID_W),
.SAXIACPAWADDR (SAXIACPAWADDR_W ),
.SAXIACPAWBURST (SAXIACPAWBURST_W),
.SAXIACPAWCACHE (SAXIACPAWCACHE_W),
.SAXIACPAWID (S_AXI_ACP_AWID_in ),
.SAXIACPAWLEN (SAXIACPAWLEN_W ),
.SAXIACPAWLOCK (SAXIACPAWLOCK_W ),
.SAXIACPAWPROT (SAXIACPAWPROT_W ),
.SAXIACPAWQOS (S_AXI_ACP_AWQOS ),
.SAXIACPAWSIZE (SAXIACPAWSIZE_W[1:0] ),
.SAXIACPAWUSER (SAXIACPAWUSER_W ),
.SAXIACPAWVALID (SAXIACPAWVALID_W),
.SAXIACPBREADY (SAXIACPBREADY_W ),
.SAXIACPRREADY (SAXIACPRREADY_W ),
.SAXIACPWDATA (SAXIACPWDATA_W ),
.SAXIACPWID (S_AXI_ACP_WID_in ),
.SAXIACPWLAST (SAXIACPWLAST_W ),
.SAXIACPWSTRB (SAXIACPWSTRB_W ),
.SAXIACPWVALID (SAXIACPWVALID_W ),
.SAXIGP0ACLK (S_AXI_GP0_ACLK ),
.SAXIGP0ARADDR (S_AXI_GP0_ARADDR ),
.SAXIGP0ARBURST (S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE (S_AXI_GP0_ARCACHE),
.SAXIGP0ARID (S_AXI_GP0_ARID_in ),
.SAXIGP0ARLEN (S_AXI_GP0_ARLEN ),
.SAXIGP0ARLOCK (S_AXI_GP0_ARLOCK ),
.SAXIGP0ARPROT (S_AXI_GP0_ARPROT ),
.SAXIGP0ARQOS (S_AXI_GP0_ARQOS ),
.SAXIGP0ARSIZE (S_AXI_GP0_ARSIZE[1:0] ),
.SAXIGP0ARVALID (S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR (S_AXI_GP0_AWADDR ),
.SAXIGP0AWBURST (S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE (S_AXI_GP0_AWCACHE),
.SAXIGP0AWID (S_AXI_GP0_AWID_in ),
.SAXIGP0AWLEN (S_AXI_GP0_AWLEN ),
.SAXIGP0AWLOCK (S_AXI_GP0_AWLOCK ),
.SAXIGP0AWPROT (S_AXI_GP0_AWPROT ),
.SAXIGP0AWQOS (S_AXI_GP0_AWQOS ),
.SAXIGP0AWSIZE (S_AXI_GP0_AWSIZE[1:0] ),
.SAXIGP0AWVALID (S_AXI_GP0_AWVALID),
.SAXIGP0BREADY (S_AXI_GP0_BREADY ),
.SAXIGP0RREADY (S_AXI_GP0_RREADY ),
.SAXIGP0WDATA (S_AXI_GP0_WDATA ),
.SAXIGP0WID (S_AXI_GP0_WID_in ),
.SAXIGP0WLAST (S_AXI_GP0_WLAST ),
.SAXIGP0WSTRB (S_AXI_GP0_WSTRB ),
.SAXIGP0WVALID (S_AXI_GP0_WVALID ),
.SAXIGP1ACLK (S_AXI_GP1_ACLK ),
.SAXIGP1ARADDR (S_AXI_GP1_ARADDR ),
.SAXIGP1ARBURST (S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE (S_AXI_GP1_ARCACHE),
.SAXIGP1ARID (S_AXI_GP1_ARID_in ),
.SAXIGP1ARLEN (S_AXI_GP1_ARLEN ),
.SAXIGP1ARLOCK (S_AXI_GP1_ARLOCK ),
.SAXIGP1ARPROT (S_AXI_GP1_ARPROT ),
.SAXIGP1ARQOS (S_AXI_GP1_ARQOS ),
.SAXIGP1ARSIZE (S_AXI_GP1_ARSIZE[1:0] ),
.SAXIGP1ARVALID (S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR (S_AXI_GP1_AWADDR ),
.SAXIGP1AWBURST (S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE (S_AXI_GP1_AWCACHE),
.SAXIGP1AWID (S_AXI_GP1_AWID_in ),
.SAXIGP1AWLEN (S_AXI_GP1_AWLEN ),
.SAXIGP1AWLOCK (S_AXI_GP1_AWLOCK ),
.SAXIGP1AWPROT (S_AXI_GP1_AWPROT ),
.SAXIGP1AWQOS (S_AXI_GP1_AWQOS ),
.SAXIGP1AWSIZE (S_AXI_GP1_AWSIZE[1:0] ),
.SAXIGP1AWVALID (S_AXI_GP1_AWVALID),
.SAXIGP1BREADY (S_AXI_GP1_BREADY ),
.SAXIGP1RREADY (S_AXI_GP1_RREADY ),
.SAXIGP1WDATA (S_AXI_GP1_WDATA ),
.SAXIGP1WID (S_AXI_GP1_WID_in ),
.SAXIGP1WLAST (S_AXI_GP1_WLAST ),
.SAXIGP1WSTRB (S_AXI_GP1_WSTRB ),
.SAXIGP1WVALID (S_AXI_GP1_WVALID ),
.SAXIHP0ACLK (S_AXI_HP0_ACLK ),
.SAXIHP0ARADDR (S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST (S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE (S_AXI_HP0_ARCACHE),
.SAXIHP0ARID (S_AXI_HP0_ARID_in),
.SAXIHP0ARLEN (S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK (S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT (S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS (S_AXI_HP0_ARQOS),
.SAXIHP0ARSIZE (S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID (S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR (S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST (S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE (S_AXI_HP0_AWCACHE),
.SAXIHP0AWID (S_AXI_HP0_AWID_in),
.SAXIHP0AWLEN (S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK (S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT (S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS (S_AXI_HP0_AWQOS),
.SAXIHP0AWSIZE (S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID (S_AXI_HP0_AWVALID),
.SAXIHP0BREADY (S_AXI_HP0_BREADY),
.SAXIHP0RDISSUECAP1EN (S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RREADY (S_AXI_HP0_RREADY),
.SAXIHP0WDATA (S_AXI_HP0_WDATA_in),
.SAXIHP0WID (S_AXI_HP0_WID_in),
.SAXIHP0WLAST (S_AXI_HP0_WLAST),
.SAXIHP0WRISSUECAP1EN (S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB (S_AXI_HP0_WSTRB_in),
.SAXIHP0WVALID (S_AXI_HP0_WVALID),
.SAXIHP1ACLK (S_AXI_HP1_ACLK),
.SAXIHP1ARADDR (S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST (S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE (S_AXI_HP1_ARCACHE),
.SAXIHP1ARID (S_AXI_HP1_ARID_in),
.SAXIHP1ARLEN (S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK (S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT (S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS (S_AXI_HP1_ARQOS),
.SAXIHP1ARSIZE (S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID (S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR (S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST (S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE (S_AXI_HP1_AWCACHE),
.SAXIHP1AWID (S_AXI_HP1_AWID_in),
.SAXIHP1AWLEN (S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK (S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT (S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS (S_AXI_HP1_AWQOS),
.SAXIHP1AWSIZE (S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID (S_AXI_HP1_AWVALID),
.SAXIHP1BREADY (S_AXI_HP1_BREADY),
.SAXIHP1RDISSUECAP1EN (S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RREADY (S_AXI_HP1_RREADY),
.SAXIHP1WDATA (S_AXI_HP1_WDATA_in),
.SAXIHP1WID (S_AXI_HP1_WID_in),
.SAXIHP1WLAST (S_AXI_HP1_WLAST),
.SAXIHP1WRISSUECAP1EN (S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB (S_AXI_HP1_WSTRB_in),
.SAXIHP1WVALID (S_AXI_HP1_WVALID),
.SAXIHP2ACLK (S_AXI_HP2_ACLK),
.SAXIHP2ARADDR (S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST (S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE (S_AXI_HP2_ARCACHE),
.SAXIHP2ARID (S_AXI_HP2_ARID_in),
.SAXIHP2ARLEN (S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK (S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT (S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS (S_AXI_HP2_ARQOS),
.SAXIHP2ARSIZE (S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID (S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR (S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST (S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE (S_AXI_HP2_AWCACHE),
.SAXIHP2AWID (S_AXI_HP2_AWID_in),
.SAXIHP2AWLEN (S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK (S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT (S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS (S_AXI_HP2_AWQOS),
.SAXIHP2AWSIZE (S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID (S_AXI_HP2_AWVALID),
.SAXIHP2BREADY (S_AXI_HP2_BREADY),
.SAXIHP2RDISSUECAP1EN (S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RREADY (S_AXI_HP2_RREADY),
.SAXIHP2WDATA (S_AXI_HP2_WDATA_in),
.SAXIHP2WID (S_AXI_HP2_WID_in),
.SAXIHP2WLAST (S_AXI_HP2_WLAST),
.SAXIHP2WRISSUECAP1EN (S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB (S_AXI_HP2_WSTRB_in),
.SAXIHP2WVALID (S_AXI_HP2_WVALID),
.SAXIHP3ACLK (S_AXI_HP3_ACLK),
.SAXIHP3ARADDR (S_AXI_HP3_ARADDR ),
.SAXIHP3ARBURST (S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE (S_AXI_HP3_ARCACHE),
.SAXIHP3ARID (S_AXI_HP3_ARID_in ),
.SAXIHP3ARLEN (S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK (S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT (S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS (S_AXI_HP3_ARQOS),
.SAXIHP3ARSIZE (S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID (S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR (S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST (S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE (S_AXI_HP3_AWCACHE),
.SAXIHP3AWID (S_AXI_HP3_AWID_in),
.SAXIHP3AWLEN (S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK (S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT (S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS (S_AXI_HP3_AWQOS),
.SAXIHP3AWSIZE (S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID (S_AXI_HP3_AWVALID),
.SAXIHP3BREADY (S_AXI_HP3_BREADY),
.SAXIHP3RDISSUECAP1EN (S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RREADY (S_AXI_HP3_RREADY),
.SAXIHP3WDATA (S_AXI_HP3_WDATA_in),
.SAXIHP3WID (S_AXI_HP3_WID_in),
.SAXIHP3WLAST (S_AXI_HP3_WLAST),
.SAXIHP3WRISSUECAP1EN (S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB (S_AXI_HP3_WSTRB_in),
.SAXIHP3WVALID (S_AXI_HP3_WVALID),
.DDRA (buffered_DDR_Addr),
.DDRBA (buffered_DDR_BankAddr),
.DDRCASB (buffered_DDR_CAS_n),
.DDRCKE (buffered_DDR_CKE),
.DDRCKN (buffered_DDR_Clk_n),
.DDRCKP (buffered_DDR_Clk),
.DDRCSB (buffered_DDR_CS_n),
.DDRDM (buffered_DDR_DM),
.DDRDQ (buffered_DDR_DQ),
.DDRDQSN (buffered_DDR_DQS_n),
.DDRDQSP (buffered_DDR_DQS),
.DDRDRSTB (buffered_DDR_DRSTB),
.DDRODT (buffered_DDR_ODT),
.DDRRASB (buffered_DDR_RAS_n),
.DDRVRN (buffered_DDR_VRN),
.DDRVRP (buffered_DDR_VRP),
.DDRWEB (buffered_DDR_WEB),
.MIO (buffered_MIO),
.PSCLK (buffered_PS_CLK),
.PSPORB (buffered_PS_PORB),
.PSSRSTB (buffered_PS_SRSTB)
);
end
endgenerate
// Generating the AxUSER Values locally when the C_USE_DEFAULT_ACP_USER_VAL is enabled.
// Otherwise a master connected to the ACP port will drive the AxUSER Ports
assign param_aruser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_ARUSER_VAL : S_AXI_ACP_ARUSER;
assign param_awuser = C_USE_DEFAULT_ACP_USER_VAL? C_S_AXI_ACP_AWUSER_VAL : S_AXI_ACP_AWUSER;
assign SAXIACPARADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARADDR : S_AXI_ACP_ARADDR;
assign SAXIACPARBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARBURST : S_AXI_ACP_ARBURST;
assign SAXIACPARCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARCACHE : S_AXI_ACP_ARCACHE;
assign SAXIACPARLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLEN : S_AXI_ACP_ARLEN;
assign SAXIACPARLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARLOCK : S_AXI_ACP_ARLOCK;
assign SAXIACPARPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARPROT : S_AXI_ACP_ARPROT;
assign SAXIACPARSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARSIZE : S_AXI_ACP_ARSIZE;
//assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : S_AXI_ACP_ARUSER;
assign SAXIACPARUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARUSER : param_aruser;
assign SAXIACPARVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARVALID : S_AXI_ACP_ARVALID ;
assign SAXIACPAWADDR_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWADDR : S_AXI_ACP_AWADDR;
assign SAXIACPAWBURST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWBURST : S_AXI_ACP_AWBURST;
assign SAXIACPAWCACHE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWCACHE : S_AXI_ACP_AWCACHE;
assign SAXIACPAWLEN_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLEN : S_AXI_ACP_AWLEN;
assign SAXIACPAWLOCK_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWLOCK : S_AXI_ACP_AWLOCK;
assign SAXIACPAWPROT_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWPROT : S_AXI_ACP_AWPROT;
assign SAXIACPAWSIZE_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWSIZE : S_AXI_ACP_AWSIZE;
//assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : S_AXI_ACP_AWUSER;
assign SAXIACPAWUSER_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWUSER : param_awuser;
assign SAXIACPAWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWVALID : S_AXI_ACP_AWVALID;
assign SAXIACPBREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_BREADY : S_AXI_ACP_BREADY;
assign SAXIACPRREADY_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_RREADY : S_AXI_ACP_RREADY;
assign SAXIACPWDATA_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WDATA : S_AXI_ACP_WDATA;
assign SAXIACPWLAST_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WLAST : S_AXI_ACP_WLAST;
assign SAXIACPWSTRB_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WSTRB : S_AXI_ACP_WSTRB;
assign SAXIACPWVALID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WVALID : S_AXI_ACP_WVALID;
assign SAXIACPARID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_ARID : S_AXI_ACP_ARID;
assign SAXIACPAWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_AWID : S_AXI_ACP_AWID;
assign SAXIACPWID_W = (C_INCLUDE_ACP_TRANS_CHECK == 1) ? S_AXI_ATC_WID : S_AXI_ACP_WID;
generate
if (C_INCLUDE_ACP_TRANS_CHECK == 0) begin : gen_no_atc
assign S_AXI_ACP_AWREADY = SAXIACPAWREADY_W;
assign S_AXI_ACP_WREADY = SAXIACPWREADY_W;
assign S_AXI_ACP_BID = SAXIACPBID_W;
assign S_AXI_ACP_BRESP = SAXIACPBRESP_W;
assign S_AXI_ACP_BVALID = SAXIACPBVALID_W;
assign S_AXI_ACP_RDATA = SAXIACPRDATA_W;
assign S_AXI_ACP_RID = SAXIACPRID_W;
assign S_AXI_ACP_RLAST = SAXIACPRLAST_W;
assign S_AXI_ACP_RRESP = SAXIACPRRESP_W;
assign S_AXI_ACP_RVALID = SAXIACPRVALID_W;
assign S_AXI_ACP_ARREADY = SAXIACPARREADY_W;
end else begin : gen_atc
processing_system7_v5_5_atc #(
.C_AXI_ID_WIDTH (C_S_AXI_ACP_ID_WIDTH),
.C_AXI_AWUSER_WIDTH (5),
.C_AXI_ARUSER_WIDTH (5)
)
atc_i (
// Global Signals
.ACLK (S_AXI_ACP_ACLK),
.ARESETN (S_AXI_ACP_ARESETN),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_ACP_AWID),
.S_AXI_AWADDR (S_AXI_ACP_AWADDR),
.S_AXI_AWLEN (S_AXI_ACP_AWLEN),
.S_AXI_AWSIZE (S_AXI_ACP_AWSIZE),
.S_AXI_AWBURST (S_AXI_ACP_AWBURST),
.S_AXI_AWLOCK (S_AXI_ACP_AWLOCK),
.S_AXI_AWCACHE (S_AXI_ACP_AWCACHE),
.S_AXI_AWPROT (S_AXI_ACP_AWPROT),
//.S_AXI_AWUSER (S_AXI_ACP_AWUSER),
.S_AXI_AWUSER (param_awuser),
.S_AXI_AWVALID (S_AXI_ACP_AWVALID),
.S_AXI_AWREADY (S_AXI_ACP_AWREADY),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_ACP_WID),
.S_AXI_WDATA (S_AXI_ACP_WDATA),
.S_AXI_WSTRB (S_AXI_ACP_WSTRB),
.S_AXI_WLAST (S_AXI_ACP_WLAST),
.S_AXI_WUSER (),
.S_AXI_WVALID (S_AXI_ACP_WVALID),
.S_AXI_WREADY (S_AXI_ACP_WREADY),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_ACP_BID),
.S_AXI_BRESP (S_AXI_ACP_BRESP),
.S_AXI_BUSER (),
.S_AXI_BVALID (S_AXI_ACP_BVALID),
.S_AXI_BREADY (S_AXI_ACP_BREADY),
// Slave Interface Read Address Ports
.S_AXI_ARID (S_AXI_ACP_ARID),
.S_AXI_ARADDR (S_AXI_ACP_ARADDR),
.S_AXI_ARLEN (S_AXI_ACP_ARLEN),
.S_AXI_ARSIZE (S_AXI_ACP_ARSIZE),
.S_AXI_ARBURST (S_AXI_ACP_ARBURST),
.S_AXI_ARLOCK (S_AXI_ACP_ARLOCK),
.S_AXI_ARCACHE (S_AXI_ACP_ARCACHE),
.S_AXI_ARPROT (S_AXI_ACP_ARPROT),
//.S_AXI_ARUSER (S_AXI_ACP_ARUSER),
.S_AXI_ARUSER (param_aruser),
.S_AXI_ARVALID (S_AXI_ACP_ARVALID),
.S_AXI_ARREADY (S_AXI_ACP_ARREADY),
// Slave Interface Read Data Ports
.S_AXI_RID (S_AXI_ACP_RID),
.S_AXI_RDATA (S_AXI_ACP_RDATA),
.S_AXI_RRESP (S_AXI_ACP_RRESP),
.S_AXI_RLAST (S_AXI_ACP_RLAST),
.S_AXI_RUSER (),
.S_AXI_RVALID (S_AXI_ACP_RVALID),
.S_AXI_RREADY (S_AXI_ACP_RREADY),
// Slave Interface Write Address Ports
.M_AXI_AWID (S_AXI_ATC_AWID),
.M_AXI_AWADDR (S_AXI_ATC_AWADDR),
.M_AXI_AWLEN (S_AXI_ATC_AWLEN),
.M_AXI_AWSIZE (S_AXI_ATC_AWSIZE),
.M_AXI_AWBURST (S_AXI_ATC_AWBURST),
.M_AXI_AWLOCK (S_AXI_ATC_AWLOCK),
.M_AXI_AWCACHE (S_AXI_ATC_AWCACHE),
.M_AXI_AWPROT (S_AXI_ATC_AWPROT),
.M_AXI_AWUSER (S_AXI_ATC_AWUSER),
.M_AXI_AWVALID (S_AXI_ATC_AWVALID),
.M_AXI_AWREADY (SAXIACPAWREADY_W),
// Slave Interface Write Data Ports
.M_AXI_WID (S_AXI_ATC_WID),
.M_AXI_WDATA (S_AXI_ATC_WDATA),
.M_AXI_WSTRB (S_AXI_ATC_WSTRB),
.M_AXI_WLAST (S_AXI_ATC_WLAST),
.M_AXI_WUSER (),
.M_AXI_WVALID (S_AXI_ATC_WVALID),
.M_AXI_WREADY (SAXIACPWREADY_W),
// Slave Interface Write Response Ports
.M_AXI_BID (SAXIACPBID_W),
.M_AXI_BRESP (SAXIACPBRESP_W),
.M_AXI_BUSER (),
.M_AXI_BVALID (SAXIACPBVALID_W),
.M_AXI_BREADY (S_AXI_ATC_BREADY),
// Slave Interface Read Address Ports
.M_AXI_ARID (S_AXI_ATC_ARID),
.M_AXI_ARADDR (S_AXI_ATC_ARADDR),
.M_AXI_ARLEN (S_AXI_ATC_ARLEN),
.M_AXI_ARSIZE (S_AXI_ATC_ARSIZE),
.M_AXI_ARBURST (S_AXI_ATC_ARBURST),
.M_AXI_ARLOCK (S_AXI_ATC_ARLOCK),
.M_AXI_ARCACHE (S_AXI_ATC_ARCACHE),
.M_AXI_ARPROT (S_AXI_ATC_ARPROT),
.M_AXI_ARUSER (S_AXI_ATC_ARUSER),
.M_AXI_ARVALID (S_AXI_ATC_ARVALID),
.M_AXI_ARREADY (SAXIACPARREADY_W),
// Slave Interface Read Data Ports
.M_AXI_RID (SAXIACPRID_W),
.M_AXI_RDATA (SAXIACPRDATA_W),
.M_AXI_RRESP (SAXIACPRRESP_W),
.M_AXI_RLAST (SAXIACPRLAST_W),
.M_AXI_RUSER (),
.M_AXI_RVALID (SAXIACPRVALID_W),
.M_AXI_RREADY (S_AXI_ATC_RREADY),
.ERROR_TRIGGER(),
.ERROR_TRANSACTION_ID()
);
end
endgenerate
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 10:20:39 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_Mux4x1_8_0_1/RAT_Mux4x1_8_0_1_stub.v
// Design : RAT_Mux4x1_8_0_1
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "Mux4x1_8,Vivado 2016.4" *)
module RAT_Mux4x1_8_0_1(A, B, C, D, SEL, X)
/* synthesis syn_black_box black_box_pad_pin="A[7:0],B[7:0],C[7:0],D[7:0],SEL[1:0],X[7:0]" */;
input [7:0]A;
input [7:0]B;
input [7:0]C;
input [7:0]D;
input [1:0]SEL;
output [7:0]X;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
`define SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__bufinv (
Y,
A
);
// Module ports
output Y;
input A;
// Local signals
wire not0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y, A );
buf buf0 (Y , not0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFINV_FUNCTIONAL_V |
//---------------------------------------------------------------------------
//-- Copyright 2015 - 2017 Systems Group, ETH Zurich
//--
//-- This hardware module is free software: you can redistribute it and/or
//-- modify it under the terms of the GNU General Public License as published
//-- by the Free Software Foundation, either version 3 of the License, or
//-- (at your option) any later version.
//--
//-- This program is distributed in the hope that it will be useful,
//-- but WITHOUT ANY WARRANTY; without even the implied warranty of
//-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
//-- GNU General Public License for more details.
//--
//-- You should have received a copy of the GNU General Public License
//-- along with this program. If not, see <http://www.gnu.org/licenses/>.
//---------------------------------------------------------------------------
module rem_top_ff #(parameter CHAR_COUNT=32, DELIMITER=0, STATE_COUNT=4)
(
clk,
rst, //active high
softRst,
input_valid,
input_data,
input_ready,
output_valid,
output_match,
output_index
);
input clk;
input rst;
input softRst;
input input_valid;
input [511:0] input_data;
output reg input_ready;
output reg output_valid;
output reg output_match;
output reg [15:0] output_index;
reg scan_mode;
reg input_wasvalid;
reg input_wasready;
reg input_hasdata;
reg [511:0] input_datareg;
reg config_valid;
reg [CHAR_COUNT*8-1:0] config_chars;
reg [CHAR_COUNT/2-1:0] config_ranges;
reg [CHAR_COUNT-1:0] config_conds;
reg [STATE_COUNT*(CHAR_COUNT)-1:0] config_state_pred;
reg [STATE_COUNT*STATE_COUNT-1:0] config_state_act;
reg restart;
reg wait_new;
reg wait_conf;
wire pred_valid;
wire [CHAR_COUNT-1:0] pred_bits;
wire [15:0] pred_index;
wire pred_last;
reg need_purge;
reg pred_valid_D;
reg pred_last_D;
reg [15:0] pred_index_D;
reg [STATE_COUNT*(CHAR_COUNT)-1:0] state_pred_masks;
reg [STATE_COUNT*STATE_COUNT-1:0] state_act_masks;
wire [STATE_COUNT-1:0] state_match_bits;
wire [STATE_COUNT-1:0] state_inact_bits;
wire [STATE_COUNT-1:0] state_outact_bits;
reg [STATE_COUNT*4-1:0] state_inact_delays;
reg [STATE_COUNT-1:0] always_activated;
reg [STATE_COUNT-1:0] state_act_sticky;
reg [15:0] string_length;
reg [7:0] length_remaining ;
reg [5:0] byte_addr;
reg waiting_pred;
reg dec_valid;
reg dec_last;
reg [7:0] dec_char;
reg rstBuf;
localparam STATE_ACT_SIZE = (STATE_COUNT*STATE_COUNT % 8 ==0) ? STATE_COUNT*STATE_COUNT : STATE_COUNT*STATE_COUNT+8-(STATE_COUNT*STATE_COUNT%8);
rem_decoder #(
.CHAR_COUNT(CHAR_COUNT),
.DELIMITER(DELIMITER)
) decoder_inst (
.clk(clk),
.rst(rstBuf),
.config_valid(config_valid),
.config_chars(config_chars),
.config_ranges(config_ranges),
.config_conds(config_conds),
.input_valid(dec_valid),
.input_last(dec_last),
.input_char(dec_char),
.index_rewind(wait_new),
.output_valid(pred_valid),
.output_data(pred_bits),
.output_index(pred_index),
.output_last(pred_last)
);
genvar X;
generate
for (X=0; X<STATE_COUNT; X=X+1)
begin: gen_states
rem_onestate onestate_inst (
.clk(clk),
.rst(rstBuf | wait_new),
.is_sticky(state_act_sticky),
.delay_valid(config_valid),
.delay_cycles(state_inact_delays[X*4 +: 4]),
.pred_valid(pred_valid),
.pred_match(state_match_bits[X]),
.act_input(state_inact_bits[X]),
.act_output(state_outact_bits[X])
);
assign state_match_bits[X] = ((state_pred_masks[(X+1)*(CHAR_COUNT)-1:X*(CHAR_COUNT)] & pred_bits) == 0 && state_pred_masks[(X+1)*(CHAR_COUNT)-1:X*(CHAR_COUNT)]!=0) ? 0 : 1;
assign state_inact_bits[X] = ((state_act_masks[(X+1)*STATE_COUNT-1:X*STATE_COUNT] & state_outact_bits) != 0) ? 1 : always_activated[X];
end
endgenerate
integer ind;
always @(posedge clk) begin
pred_valid_D <= pred_valid;
pred_last_D <= pred_last;
pred_index_D <= pred_index;
rstBuf <= rst;
if (rst) begin
output_valid <= 0;
always_activated <= 0;
string_length <= 0;
wait_new <= 1;
wait_conf <= 1;
restart <= 0;
need_purge <= 0;
input_ready <= 1;
config_valid <= 0;
dec_valid <= 0;
dec_last <= 0;
input_wasready <= input_ready;
input_wasvalid <= input_valid;
input_hasdata <= 0;
state_inact_delays <= 0;
waiting_pred <= 0;
scan_mode <= 0;
end
else begin
if (restart) begin
wait_conf <= 1 & (~scan_mode);
wait_new <= 1;
restart <= 0;
end
if (softRst) begin
wait_conf <= 1;
wait_new <= 1;
restart <= 0;
end
input_wasvalid <= input_valid;
input_wasready <= input_ready;
output_valid <= 0;
config_valid <= 0;
dec_valid <= 0;
dec_last <= 0;
if (input_valid==1) begin
input_ready <= 0;
end
input_hasdata <= input_ready==1 ? 0 : input_hasdata;
if (input_ready && input_valid) begin
input_datareg <= input_data;
input_hasdata <= 1;
end
if (input_hasdata==1 && wait_conf==1) begin
config_valid <= 1;
config_chars <= input_datareg[CHAR_COUNT*8-1:0];
config_ranges <= input_datareg[CHAR_COUNT/2 + CHAR_COUNT*8-1 : CHAR_COUNT*8];
config_conds <= input_datareg[CHAR_COUNT-1+CHAR_COUNT/2 + CHAR_COUNT*8:CHAR_COUNT/2 + CHAR_COUNT*8];
config_state_pred <= input_datareg[STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:CHAR_COUNT/2 + CHAR_COUNT*8+CHAR_COUNT];
config_state_act <= input_datareg[STATE_COUNT*STATE_COUNT+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
state_pred_masks <= input_datareg[STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:CHAR_COUNT/2 + CHAR_COUNT*8+CHAR_COUNT];
state_act_masks <= input_datareg[STATE_COUNT*STATE_COUNT+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8-1:STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
state_inact_delays <= input_datareg[STATE_COUNT*4-1+STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8 : STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
state_act_sticky <= input_datareg[STATE_COUNT-1+STATE_COUNT*4+STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8 : STATE_COUNT*4+STATE_ACT_SIZE+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8];
for (ind=0; ind<STATE_COUNT; ind=ind+1) begin
always_activated[ind]=0;
if (input_datareg[(ind)*STATE_COUNT+STATE_COUNT*CHAR_COUNT+CHAR_COUNT+CHAR_COUNT/2 + CHAR_COUNT*8 +: STATE_COUNT]==0) always_activated[ind]=1;
end
wait_conf <= 0;
input_ready <= 1;
scan_mode <= input_datareg[511];
end
if (restart==0 && wait_conf==0) begin
if (!input_ready && input_hasdata==1 && wait_new==1) begin
byte_addr <= 2;
string_length <= input_datareg[15:0];
length_remaining <= (input_datareg[15:0]+63)/64;
wait_new <= 0;
if (input_datareg[15:0]==0) begin
wait_new <=1;
input_ready <= 1;
end
end
if (!input_ready && input_hasdata==1 && wait_new==0) begin
if (byte_addr<=63) begin
dec_valid <= 1;
dec_char <= input_datareg[byte_addr[5:0]*8 +: 8];
byte_addr <= byte_addr+1;
if (byte_addr==63 && length_remaining==1) begin
dec_last <= 1;
end else begin
dec_last <= 0;
end
end
if (byte_addr==63 && length_remaining>1) begin
byte_addr <= 0;
input_ready <= 1;
length_remaining <= length_remaining-1;
end
else if (byte_addr==63 && length_remaining==1 && !need_purge) begin
byte_addr <= 0;
input_hasdata <= 0;
waiting_pred <= 1;
length_remaining <= 0;
end
if (need_purge==1) begin
if (length_remaining>1) begin
byte_addr <= 64;
length_remaining <= length_remaining-1;
input_ready <= 1;
end
else begin
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
end
end
if (!need_purge && !wait_new && pred_valid_D==1 && (state_outact_bits[STATE_COUNT-1]==1 || pred_last_D==1)) begin
output_valid <= 1;
output_match <= state_outact_bits[STATE_COUNT-1]==1;
output_index <= pred_index_D;
if (!waiting_pred) begin
need_purge<=1;
end
else begin
waiting_pred <= 0;
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
end
if (!input_hasdata && output_valid==1 && waiting_pred==1) begin
waiting_pred <= 0;
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
if (!need_purge && waiting_pred==1 && pred_valid_D==0 && length_remaining==0) begin
output_valid <= 1;
output_match <= 0;
output_index <= 0;
waiting_pred <= 0;
byte_addr <= 0;
restart <= 1;
input_ready <= 1;
need_purge <= 0;
end
end
end
end
endmodule |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Oct 27 19:58:51 2016
/////////////////////////////////////////////////////////////
module Simple_KOA_SW24 ( clk, rst, load_b_i, Data_A_i, Data_B_i, sgf_result_o
);
input [23:0] Data_A_i;
input [23:0] Data_B_i;
output [47:0] sgf_result_o;
input clk, rst, load_b_i;
wire n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64,
n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78,
n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92,
n93, n94, n96, n98, n100, n102, n103, n104, n105, n106, n107, n108,
n109, n110, n111, n112, n113, n114, n115, n116, n117, n118, n119,
n120, n121, n122, n123, n124, n125, n126, n127, n128, n129, n130,
n131, n132, n133, n134, n135, n136, n137, n139, n141, n142, n143,
n144, n145, n146, n147, n148, n149, n150, n151, n152, n153, n154,
n155, n156, n157, n158, n159, n160, n161, n162, n163, n164, n165,
n166, n167, n168, n169, n170, n171, n172, n173, n174, n175, n176,
n177, n178, n179, n180, n181, n182, n183, n184, n185, n186, n187,
n188, n189, n190, n191, n192, n193, n194, n195, n196, n197, n198,
n199, n200, n201, n202, n203, n204, n205, n206, n207, n208, n209,
n210, n211, n212, n213, n214, n215, n216, n217, n218, n219, n220,
n221, n222, n223, n224, n225, n226, n227, n228, n229, n230, n231,
n232, n233, n234, n235, n236, n237, n238, n239, n240, n241, n242,
n243, n244, n245, n246, n247, n248, n249, n250, n251, n252, n253,
n254, n255, n256, n257, n258, n259, n260, n261, n262, n263, n264,
n265, n266, n267, n268, n269, n270, n271, n272, n273, n274, n275,
n276, n277, n278, n279, n280, n281, n282, n283, n284, n285, n286,
n287, n288, n289, n290, n291, n292, n293, n294, n295, n296, n297,
n298, n299, n300, n301, n302, n303, n304, n305, n306, n307, n308,
n309, n310, n311, n312, n313, n314, n315, n316, n317, n318, n319,
n320, n321, n322, n323, n324, n325, n326, n327, n328, n329, n330,
n331, n332, n333, n334, n335, n336, n337, n338, n339, n340, n341,
n342, n343, n344, n345, n346, n347, n348, n349, n350, n351, n352,
n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374,
n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407,
n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418,
n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429,
n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, n440,
n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451,
n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462,
n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473,
n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484,
n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506,
n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614, n615, n616,
n617, n618, n619, n620, n621, n622, n623, n624, n625, n626, n627,
n628, n629, n630, n631, n632, n633, n634, n635, n636, n637, n638,
n639, n640, n641, n642, n643, n644, n645, n646, n647, n648, n649,
n650, n651, n652, n653, n654, n655, n656, n657, n658, n659, n660,
n661, n662, n663, n664, n665, n666, n667, n668, n669, n670, n671,
n672, n673, n674, n675, n676, n677, n678, n679, n680, n681, n682,
n683, n684, n685, n686, n687, n688, n689, n690, n691, n692, n693,
n694, n695, n696, n697, n698, n699, n700, n701, n702, n703, n704,
n705, n706, n707, n708, n709, n710, n711, n712, n713, n714, n715,
n716, n717, n718, n719, n720, n721, n722, n723, n724, n725, n726,
n727, n728, n729, n730, n731, n732, n733, n734, n735, n736, n737,
n738, n739, n740, n741, n742, n743, n744, n745, n746, n747, n748,
n749, n750, n751, n752, n753, n754, n755, n756, n757, n758, n759,
n760, n761, n762, n763, n764, n765, n766, n767, n768, n769, n770,
n771, n772, n773, n774, n775, n776, n777, n778, n779, n780, n781,
n782, n783, n784, n785, n786, n787, n788, n789, n790, n791, n792,
n793, n794, n795, n796, n797, n798, n799, n800, n801, n802, n803,
n804, n805, n806, n807, n808, n809, n810, n811, n812, n813, n814,
n815, n816, n817, n818, n819, n820, n821, n822, n823, n824, n825,
n826, n827, n828, n829, n830, n831, n832, n833, n834, n835, n836,
n837, n838, n839, n840, n841, n842, n843, n844, n845, n846, n847,
n848, n849, n850, n851, n852, n853, n854, n855, n856, n857, n858,
n859, n860, n861, n862, n863, n864, n865, n866, n867, n868, n869,
n870, n871, n872, n873, n874, n875, n876, n877, n878, n879, n880,
n881, n882, n883, n884, n885, n886, n887, n888, n889, n890, n891,
n892, n893, n894, n895, n896, n897, n898, n899, n900, n901, n902,
n903, n904, n905, n906, n907, n908, n909, n910, n911, n912, n913,
n914, n915, n916, n917, n918, n919, n920, n921, n922, n923, n924,
n925, n926, n927, n928, n929, n930, n931, n932, n933, n934, n935,
n936, n937, n938, n939, n940, n941, n942, n943, n944, n945, n946,
n947, n948, n949, n950, n951, n952, n953, n954, n955, n956, n957,
n958, n959, n960, n961, n962, n963, n964, n965, n966, n967, n968,
n969, n970, n971, n972, n973, n974, n975, n976, n977, n978, n979,
n980, n981, n982, n983, n984, n985, n986, n987, n988, n989, n990,
n991, n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001,
n1002, n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011,
n1012, n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021,
n1022, n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031,
n1032, n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041,
n1042, n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051,
n1052, n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061,
n1062, n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071,
n1072, n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081,
n1082, n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091,
n1092, n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101,
n1102, n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111,
n1112, n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121,
n1122, n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131,
n1132, n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141,
n1142, n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151,
n1152, n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161,
n1162, n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171,
n1172, n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181,
n1182, n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191,
n1192, n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201,
n1202, n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211,
n1212, n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221,
n1222, n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231,
n1232, n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241,
n1242, n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251,
n1252, n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261,
n1262, n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271,
n1272, n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281,
n1282, n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291,
n1292, n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301,
n1302, n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311,
n1312, n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321,
n1322, n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331,
n1332, n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341,
n1342, n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351,
n1352, n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361,
n1362, n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371,
n1372, n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381,
n1382, n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391,
n1392, n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401,
n1402, n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411,
n1412, n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421,
n1422, n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431,
n1432, n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441,
n1442, n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451,
n1452, n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461,
n1462, n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471,
n1472, n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481,
n1482, n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491,
n1492, n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501,
n1502, n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511,
n1512, n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521,
n1522, n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531,
n1532, n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541,
n1542, n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551,
n1552, n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561,
n1562, n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571,
n1572, n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581,
n1582, n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591,
n1592, n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601,
n1602, n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611,
n1612, n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621,
n1622, n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631,
n1632, n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641,
n1642, n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651,
n1652, n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661,
n1662, n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671,
n1672, n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681,
n1682, n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691,
n1692, n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701,
n1702, n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711,
n1712, n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721,
n1722, n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731,
n1732, n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741,
n1742, n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751,
n1752, n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761,
n1762, n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771,
n1772, n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781,
n1782, n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791,
n1792, n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801,
n1802, n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811,
n1812, n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821,
n1822, n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831,
n1832, n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841,
n1842, n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851,
n1852, n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861,
n1862, n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871,
n1872, n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881,
n1882, n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891,
n1892, n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901,
n1902, n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911,
n1912, n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921,
n1922, n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931,
n1932, n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941,
n1942, n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951,
n1952, n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961,
n1962, n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971,
n1972, n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981,
n1982, n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991,
n1992, n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001,
n2002, n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011,
n2012, n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021,
n2022, n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031,
n2032, n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041,
n2042, n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051,
n2052, n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061,
n2062, n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071,
n2072, n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081,
n2082, n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091,
n2092, n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101,
n2102, n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111,
n2112, n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121,
n2122, n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131,
n2132, n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141,
n2142, n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151,
n2152, n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161,
n2162, n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171,
n2172, n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181,
n2182, n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191,
n2192, n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201,
n2202, n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211,
n2212, n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221,
n2222, n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231,
n2232, n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241,
n2242, n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251,
n2252, n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261,
n2262, n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271,
n2272, n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281,
n2282, n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291,
n2292, n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301,
n2302, n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311,
n2312, n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321,
n2322, n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331,
n2332, n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341,
n2342, n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351,
n2352, n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361,
n2362, n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371,
n2372, n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381,
n2382, n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391,
n2392, n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401,
n2402, n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411,
n2412, n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421,
n2422, n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431,
n2432, n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441,
n2442, n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451,
n2452, n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461,
n2462, n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471,
n2472, n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481,
n2482, n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491,
n2492, n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501,
n2502, n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511,
n2512, n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521,
n2522, n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531,
n2532, n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541,
n2542, n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551,
n2552, n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561,
n2562, n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571,
n2572, n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581,
n2582, n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591,
n2592, n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601,
n2602, n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611,
n2612, n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621,
n2622, n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631,
n2632, n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641,
n2642, n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651,
n2652, n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661,
n2662, n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671,
n2672, n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681,
n2682, n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691,
n2692, n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701,
n2702, n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711,
n2712, n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721,
n2722, n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731,
n2732, n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741,
n2742, n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751,
n2752, n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761,
n2762, n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771,
n2772, n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781,
n2782, n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791,
n2792, n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801,
n2802, n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811,
n2812, n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821,
n2822, n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831,
n2832, n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841,
n2842, n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851,
n2852, n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861,
n2862, n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871,
n2872, n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881,
n2882, n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891,
n2892, n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901,
n2902, n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911,
n2912, n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921,
n2922, n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931,
n2932, n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941,
n2942, n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951,
n2952, n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961,
n2962, n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971,
n2972, n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981,
n2982, n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991,
n2992, n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001,
n3002, n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011,
n3012, n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021,
n3022, n3023, n3024, n3025, n3026, n3028, n3029, n3030;
DFFRXLTS EVEN1_finalreg_Q_reg_26_ ( .D(n24), .CK(clk), .RN(n3029), .Q(
sgf_result_o[26]) );
DFFRXLTS EVEN1_finalreg_Q_reg_20_ ( .D(n30), .CK(clk), .RN(n212), .Q(
sgf_result_o[20]) );
DFFRXLTS EVEN1_finalreg_Q_reg_24_ ( .D(n26), .CK(clk), .RN(n211), .Q(
sgf_result_o[24]) );
DFFRXLTS EVEN1_finalreg_Q_reg_25_ ( .D(n25), .CK(clk), .RN(n211), .Q(
sgf_result_o[25]) );
DFFRXLTS EVEN1_finalreg_Q_reg_27_ ( .D(n23), .CK(clk), .RN(n3028), .Q(
sgf_result_o[27]) );
DFFRXLTS EVEN1_finalreg_Q_reg_28_ ( .D(n22), .CK(clk), .RN(n3028), .Q(
sgf_result_o[28]) );
DFFRXLTS EVEN1_finalreg_Q_reg_22_ ( .D(n28), .CK(clk), .RN(n3030), .Q(
sgf_result_o[22]) );
DFFRXLTS EVEN1_finalreg_Q_reg_23_ ( .D(n27), .CK(clk), .RN(n3030), .Q(
sgf_result_o[23]) );
DFFSX1TS EVEN1_finalreg_Q_reg_29_ ( .D(n3026), .CK(clk), .SN(n212), .QN(
sgf_result_o[29]) );
DFFSX1TS EVEN1_finalreg_Q_reg_31_ ( .D(n3025), .CK(clk), .SN(n211), .QN(
sgf_result_o[31]) );
DFFSX1TS EVEN1_finalreg_Q_reg_32_ ( .D(n3024), .CK(clk), .SN(n3030), .QN(
sgf_result_o[32]) );
DFFSX1TS EVEN1_finalreg_Q_reg_34_ ( .D(n3023), .CK(clk), .SN(n212), .Q(n127),
.QN(sgf_result_o[34]) );
DFFSX1TS EVEN1_finalreg_Q_reg_33_ ( .D(n3022), .CK(clk), .SN(n211), .QN(
sgf_result_o[33]) );
DFFSX1TS EVEN1_finalreg_Q_reg_30_ ( .D(n3020), .CK(clk), .SN(n212), .QN(
sgf_result_o[30]) );
DFFSX1TS EVEN1_finalreg_Q_reg_35_ ( .D(n3019), .CK(clk), .SN(n211), .QN(
sgf_result_o[35]) );
DFFSX1TS EVEN1_finalreg_Q_reg_36_ ( .D(n3018), .CK(clk), .SN(n3030), .QN(
sgf_result_o[36]) );
DFFSX1TS EVEN1_finalreg_Q_reg_47_ ( .D(n3016), .CK(clk), .SN(n211), .QN(
sgf_result_o[47]) );
DFFSX1TS EVEN1_finalreg_Q_reg_44_ ( .D(n3014), .CK(clk), .SN(n212), .QN(
sgf_result_o[44]) );
DFFSX1TS EVEN1_finalreg_Q_reg_39_ ( .D(n3010), .CK(clk), .SN(n211), .QN(
sgf_result_o[39]) );
DFFSX1TS EVEN1_finalreg_Q_reg_41_ ( .D(n3009), .CK(clk), .SN(n3030), .QN(
sgf_result_o[41]) );
DFFSX1TS EVEN1_finalreg_Q_reg_38_ ( .D(n3008), .CK(clk), .SN(n212), .QN(
sgf_result_o[38]) );
DFFRXLTS EVEN1_finalreg_Q_reg_10_ ( .D(n40), .CK(clk), .RN(n3028), .Q(
sgf_result_o[10]) );
DFFRHQX1TS EVEN1_finalreg_Q_reg_19_ ( .D(n31), .CK(clk), .RN(n211), .Q(
sgf_result_o[19]) );
DFFSRHQX2TS EVEN1_finalreg_Q_reg_18_ ( .D(n32), .CK(clk), .SN(1'b1), .RN(
n3030), .Q(sgf_result_o[18]) );
DFFRXLTS EVEN1_finalreg_Q_reg_0_ ( .D(n50), .CK(clk), .RN(n3029), .Q(
sgf_result_o[0]) );
DFFRXLTS EVEN1_finalreg_Q_reg_1_ ( .D(n49), .CK(clk), .RN(n3029), .Q(
sgf_result_o[1]) );
DFFRXLTS EVEN1_finalreg_Q_reg_3_ ( .D(n47), .CK(clk), .RN(n3029), .Q(
sgf_result_o[3]) );
DFFRXLTS EVEN1_finalreg_Q_reg_5_ ( .D(n45), .CK(clk), .RN(n3029), .Q(
sgf_result_o[5]) );
DFFRXLTS EVEN1_finalreg_Q_reg_8_ ( .D(n42), .CK(clk), .RN(n211), .Q(
sgf_result_o[8]) );
DFFRXLTS EVEN1_finalreg_Q_reg_9_ ( .D(n41), .CK(clk), .RN(n3028), .Q(
sgf_result_o[9]) );
DFFRXLTS EVEN1_finalreg_Q_reg_12_ ( .D(n38), .CK(clk), .RN(n3028), .Q(
sgf_result_o[12]) );
DFFRXLTS EVEN1_finalreg_Q_reg_13_ ( .D(n37), .CK(clk), .RN(n3028), .Q(
sgf_result_o[13]) );
DFFRXLTS EVEN1_finalreg_Q_reg_16_ ( .D(n34), .CK(clk), .RN(n3028), .Q(
sgf_result_o[16]) );
DFFRXLTS EVEN1_finalreg_Q_reg_2_ ( .D(n48), .CK(clk), .RN(n3029), .Q(
sgf_result_o[2]) );
DFFRXLTS EVEN1_finalreg_Q_reg_4_ ( .D(n46), .CK(clk), .RN(n3029), .Q(
sgf_result_o[4]) );
DFFRXLTS EVEN1_finalreg_Q_reg_6_ ( .D(n44), .CK(clk), .RN(n3029), .Q(
sgf_result_o[6]) );
DFFRXLTS EVEN1_finalreg_Q_reg_7_ ( .D(n43), .CK(clk), .RN(n3029), .Q(
sgf_result_o[7]) );
DFFRXLTS EVEN1_finalreg_Q_reg_11_ ( .D(n39), .CK(clk), .RN(n3028), .Q(
sgf_result_o[11]) );
DFFRXLTS EVEN1_finalreg_Q_reg_14_ ( .D(n36), .CK(clk), .RN(n3028), .Q(
sgf_result_o[14]) );
DFFRXLTS EVEN1_finalreg_Q_reg_15_ ( .D(n35), .CK(clk), .RN(n3028), .Q(
sgf_result_o[15]) );
DFFRXLTS EVEN1_finalreg_Q_reg_17_ ( .D(n33), .CK(clk), .RN(n3029), .Q(
sgf_result_o[17]) );
DFFRXLTS EVEN1_finalreg_Q_reg_21_ ( .D(n29), .CK(clk), .RN(n212), .Q(
sgf_result_o[21]) );
DFFSHQX8TS EVEN1_finalreg_Q_reg_43_ ( .D(n3013), .CK(clk), .SN(n211), .Q(
n100) );
DFFSHQX8TS EVEN1_finalreg_Q_reg_40_ ( .D(n3011), .CK(clk), .SN(n212), .Q(n98) );
DFFSHQX8TS EVEN1_finalreg_Q_reg_42_ ( .D(n3012), .CK(clk), .SN(n3030), .Q(
n137) );
DFFSHQX8TS EVEN1_finalreg_Q_reg_46_ ( .D(n3015), .CK(clk), .SN(n3030), .Q(
n96) );
DFFSHQX8TS EVEN1_finalreg_Q_reg_45_ ( .D(n3021), .CK(clk), .SN(n3030), .Q(
n139) );
DFFSHQX2TS EVEN1_finalreg_Q_reg_37_ ( .D(n3017), .CK(clk), .SN(n212), .Q(n94) );
OAI2BB1X1TS U53 ( .A0N(n747), .A1N(n2830), .B0(n2829), .Y(n29) );
OAI2BB1X1TS U54 ( .A0N(n478), .A1N(n2850), .B0(n2849), .Y(n22) );
OAI2BB1X1TS U55 ( .A0N(n478), .A1N(n2840), .B0(n2839), .Y(n23) );
OAI2BB1X1TS U56 ( .A0N(n478), .A1N(n2875), .B0(n2874), .Y(n25) );
OAI2BB1X1TS U57 ( .A0N(n478), .A1N(n2836), .B0(n2835), .Y(n26) );
AOI21X1TS U58 ( .A0(n815), .A1(n2967), .B0(n123), .Y(n3010) );
AOI21X1TS U59 ( .A0(n819), .A1(n2967), .B0(n125), .Y(n3009) );
AOI21X1TS U60 ( .A0(n577), .A1(n2782), .B0(n112), .Y(n3014) );
XOR2XLTS U61 ( .A(n826), .B(n887), .Y(n825) );
INVX1TS U62 ( .A(n2967), .Y(n2929) );
INVX2TS U63 ( .A(load_b_i), .Y(n2892) );
CLKINVX2TS U64 ( .A(n2782), .Y(n3005) );
CLKBUFX2TS U65 ( .A(load_b_i), .Y(n2967) );
CLKBUFX2TS U66 ( .A(load_b_i), .Y(n2782) );
NOR2X1TS U67 ( .A(n850), .B(n2584), .Y(n2780) );
NAND2X1TS U68 ( .A(n2530), .B(n2529), .Y(n2845) );
NOR2X4TS U69 ( .A(n2750), .B(n2755), .Y(n2590) );
NAND2X2TS U70 ( .A(n2695), .B(n2694), .Y(n2767) );
NOR2X1TS U71 ( .A(n463), .B(n476), .Y(n2876) );
NAND2X2TS U72 ( .A(n2587), .B(n2586), .Y(n2756) );
XOR2X2TS U73 ( .A(n2274), .B(n2273), .Y(n2530) );
NOR2X4TS U74 ( .A(n2677), .B(n887), .Y(n2695) );
XNOR2X1TS U75 ( .A(n2516), .B(n2515), .Y(n463) );
BUFX3TS U76 ( .A(n861), .Y(n605) );
NAND2BXLTS U77 ( .AN(n2513), .B(n2514), .Y(n2515) );
XNOR2X2TS U78 ( .A(n428), .B(n427), .Y(n2523) );
NOR2X6TS U79 ( .A(n806), .B(n2473), .Y(n2858) );
OAI21X2TS U80 ( .A0(n2516), .A1(n2513), .B0(n2514), .Y(n428) );
NOR2X2TS U81 ( .A(n2166), .B(n2220), .Y(n2168) );
INVX2TS U82 ( .A(n711), .Y(n2516) );
CLKXOR2X2TS U83 ( .A(n2353), .B(n2352), .Y(n2473) );
XOR2X1TS U84 ( .A(n2356), .B(n2355), .Y(n805) );
NAND2X1TS U85 ( .A(n2289), .B(n2290), .Y(n2291) );
NOR2X2TS U86 ( .A(n2222), .B(n2212), .Y(n2097) );
NOR2X2TS U87 ( .A(n844), .B(n2534), .Y(n2223) );
NOR2X4TS U88 ( .A(n495), .B(n2092), .Y(n2534) );
NAND2X1TS U89 ( .A(n2637), .B(n700), .Y(n2687) );
NAND2X2TS U90 ( .A(n1904), .B(n1905), .Y(n2555) );
NOR2X2TS U91 ( .A(n2091), .B(n2090), .Y(n844) );
OAI21X1TS U92 ( .A0(n2227), .A1(n2226), .B0(n2225), .Y(n590) );
OAI2BB1X2TS U93 ( .A0N(n2006), .A1N(n556), .B0(n827), .Y(n2094) );
OAI2BB1X2TS U94 ( .A0N(n1959), .A1N(n373), .B0(n371), .Y(n2092) );
NAND2BXLTS U95 ( .AN(n2376), .B(n378), .Y(n2378) );
OAI2BB1X2TS U96 ( .A0N(n2102), .A1N(n2101), .B0(n655), .Y(n2134) );
OAI21X1TS U97 ( .A0(n2006), .A1(n556), .B0(n2005), .Y(n827) );
OAI21X2TS U98 ( .A0(n2101), .A1(n2102), .B0(n2100), .Y(n655) );
OAI2BB1X2TS U99 ( .A0N(n1765), .A1N(n1766), .B0(n321), .Y(n1767) );
OAI2BB1X2TS U100 ( .A0N(n1788), .A1N(n1787), .B0(n1786), .Y(n1844) );
ADDFHX2TS U101 ( .A(n1848), .B(n1847), .CI(n1846), .CO(n1906), .S(n1845) );
OAI21X1TS U102 ( .A0(n2209), .A1(n2161), .B0(n2160), .Y(n2265) );
INVX1TS U103 ( .A(n1745), .Y(n471) );
NAND2X1TS U104 ( .A(n2429), .B(n2329), .Y(n2330) );
OAI21X1TS U105 ( .A0(n2004), .A1(n414), .B0(n2003), .Y(n413) );
OAI21X1TS U106 ( .A0(n1762), .A1(n1763), .B0(n1761), .Y(n213) );
NOR2X2TS U107 ( .A(n1693), .B(n1692), .Y(n2463) );
CMPR32X2TS U108 ( .A(n2188), .B(n2736), .C(n2187), .CO(n2247), .S(n2190) );
OAI2BB1X2TS U109 ( .A0N(n1877), .A1N(n650), .B0(n649), .Y(n1917) );
INVX2TS U110 ( .A(n2405), .Y(n2960) );
OAI2BB1X2TS U111 ( .A0N(n1834), .A1N(n1832), .B0(n591), .Y(n1850) );
NAND2X2TS U112 ( .A(n1671), .B(n1672), .Y(n378) );
XOR2X1TS U113 ( .A(n2104), .B(n2103), .Y(n869) );
OAI21X1TS U114 ( .A0(n1741), .A1(n537), .B0(n1740), .Y(n536) );
ADDFHX2TS U115 ( .A(n2012), .B(n2011), .CI(n2010), .CO(n2089), .S(n2048) );
OAI2BB1X1TS U116 ( .A0N(n1670), .A1N(n658), .B0(n657), .Y(n1671) );
AND2X2TS U117 ( .A(n715), .B(n521), .Y(n1913) );
XOR2X2TS U118 ( .A(n1994), .B(n1993), .Y(n417) );
ADDFHX1TS U119 ( .A(n1998), .B(n1999), .CI(n1997), .CO(n2008), .S(n1962) );
ADDFHX1TS U120 ( .A(n2044), .B(n2045), .CI(n2043), .CO(n2052), .S(n2007) );
CMPR32X2TS U121 ( .A(n1911), .B(n1910), .C(n1909), .CO(n1997), .S(n1914) );
INVX2TS U122 ( .A(n2267), .Y(n1341) );
NAND2XLTS U123 ( .A(n1894), .B(n1895), .Y(n521) );
OAI2BB1X2TS U124 ( .A0N(n1731), .A1N(n1730), .B0(n542), .Y(n1702) );
OAI2BB1X2TS U125 ( .A0N(n1679), .A1N(n1680), .B0(n707), .Y(n1688) );
CLKINVX2TS U126 ( .A(n2332), .Y(n1900) );
OAI2BB1X1TS U127 ( .A0N(n2034), .A1N(n2033), .B0(n837), .Y(n2344) );
OAI21XLTS U128 ( .A0(n1894), .A1(n1895), .B0(n1893), .Y(n715) );
AO21X2TS U129 ( .A0(n164), .A1(n181), .B0(n204), .Y(n2177) );
OAI21XLTS U130 ( .A0(n658), .A1(n1670), .B0(n1669), .Y(n657) );
OAI2BB1X2TS U131 ( .A0N(n1223), .A1N(n840), .B0(n872), .Y(n2617) );
XOR2X1TS U132 ( .A(n1853), .B(n1854), .Y(n284) );
ADDFX2TS U133 ( .A(n1784), .B(n1785), .CI(n1783), .CO(n1899), .S(n1776) );
CLKINVX6TS U134 ( .A(n2674), .Y(n761) );
INVX2TS U135 ( .A(n2335), .Y(n1996) );
OAI2BB1X1TS U136 ( .A0N(n1871), .A1N(n1870), .B0(n680), .Y(n2334) );
OAI2BB1X1TS U137 ( .A0N(n1677), .A1N(n540), .B0(n539), .Y(n1690) );
OAI2BB1X2TS U138 ( .A0N(n1298), .A1N(n527), .B0(n525), .Y(n1274) );
BUFX2TS U139 ( .A(n2320), .Y(n618) );
INVX2TS U140 ( .A(n681), .Y(n594) );
OAI2BB1X2TS U141 ( .A0N(n1725), .A1N(n1724), .B0(n664), .Y(n1720) );
OAI21XLTS U142 ( .A0(n2033), .A1(n2034), .B0(n2032), .Y(n837) );
OAI21X2TS U143 ( .A0(n320), .A1(n1348), .B0(n319), .Y(n299) );
OAI2BB1X1TS U144 ( .A0N(n2083), .A1N(n2082), .B0(n870), .Y(n2721) );
XOR2X2TS U145 ( .A(n2036), .B(n2037), .Y(n499) );
OAI21X1TS U146 ( .A0(n1351), .A1(n1350), .B0(n1349), .Y(n309) );
OAI22X1TS U147 ( .A0(n1856), .A1(n202), .B0(n1908), .B1(n162), .Y(n1920) );
OAI22X1TS U148 ( .A0(n1855), .A1(n192), .B0(n1924), .B1(n185), .Y(n1921) );
XOR2X1TS U149 ( .A(n236), .B(n1779), .Y(n235) );
CMPR32X2TS U150 ( .A(n2064), .B(n2063), .C(n2062), .CO(n2115), .S(n2079) );
NOR2X1TS U151 ( .A(n2309), .B(n2308), .Y(n2935) );
INVX2TS U152 ( .A(n2308), .Y(n1414) );
OAI2BB1X2TS U153 ( .A0N(n2321), .A1N(n526), .B0(n1297), .Y(n525) );
NAND2X1TS U154 ( .A(n1989), .B(n829), .Y(n830) );
NOR2X1TS U155 ( .A(n509), .B(n508), .Y(n2395) );
OAI2BB1X2TS U156 ( .A0N(n217), .A1N(n2162), .B0(n1723), .Y(n664) );
OAI22X1TS U157 ( .A0(n1809), .A1(n205), .B0(n383), .B1(n61), .Y(n1897) );
XOR2X2TS U158 ( .A(n1670), .B(n660), .Y(n659) );
XOR2X2TS U159 ( .A(n2033), .B(n839), .Y(n838) );
OAI21X1TS U160 ( .A0(n1986), .A1(n1988), .B0(n1987), .Y(n239) );
ADDFHX2TS U161 ( .A(n1951), .B(n1950), .CI(n1949), .CO(n2674), .S(n2660) );
CMPR32X2TS U162 ( .A(n2069), .B(n2068), .C(n2067), .CO(n2106), .S(n2082) );
INVX2TS U163 ( .A(n2306), .Y(n1534) );
OAI2BB1X2TS U164 ( .A0N(n1344), .A1N(n1343), .B0(n607), .Y(n2319) );
OAI2BB1X2TS U165 ( .A0N(n1292), .A1N(n1293), .B0(n627), .Y(n2321) );
INVX2TS U166 ( .A(n2163), .Y(n1723) );
INVX2TS U167 ( .A(n2324), .Y(n1167) );
OAI2BB1X2TS U168 ( .A0N(n1207), .A1N(n1206), .B0(n555), .Y(n1782) );
OAI2BB1X2TS U169 ( .A0N(n1115), .A1N(n616), .B0(n615), .Y(n1110) );
INVX2TS U170 ( .A(n179), .Y(n180) );
OAI2BB1X2TS U171 ( .A0N(n1337), .A1N(n1338), .B0(n298), .Y(n2201) );
OAI21X2TS U172 ( .A0(n533), .A1(n531), .B0(n530), .Y(n1987) );
OAI2BB1X2TS U173 ( .A0N(n257), .A1N(n256), .B0(n776), .Y(n355) );
OAI21X2TS U174 ( .A0(n2312), .A1(n801), .B0(n800), .Y(n1728) );
OAI2BB1X1TS U175 ( .A0N(n874), .A1N(n1228), .B0(n873), .Y(n1779) );
OAI22X1TS U176 ( .A0(n1577), .A1(n168), .B0(n1538), .B1(n184), .Y(n1656) );
XOR2X2TS U177 ( .A(n327), .B(n323), .Y(n326) );
NOR2BX1TS U178 ( .AN(n1644), .B(n510), .Y(n509) );
NOR2X1TS U179 ( .A(n1939), .B(n1940), .Y(n531) );
NAND2X1TS U180 ( .A(n1437), .B(n1438), .Y(n800) );
OAI2BB1X1TS U181 ( .A0N(n1190), .A1N(n1191), .B0(n597), .Y(n1225) );
INVX2TS U182 ( .A(n737), .Y(n669) );
INVX2TS U183 ( .A(n2323), .Y(n59) );
OAI21X2TS U184 ( .A0(n1860), .A1(n1861), .B0(n1859), .Y(n647) );
NOR2BX1TS U185 ( .AN(n107), .B(n1643), .Y(n510) );
OAI21X1TS U186 ( .A0(n1343), .A1(n1344), .B0(n608), .Y(n607) );
AO21X2TS U187 ( .A0(n913), .A1(n1607), .B0(n358), .Y(n1806) );
OAI2BB1X2TS U188 ( .A0N(n1476), .A1N(n1475), .B0(n689), .Y(n1467) );
OAI21X2TS U189 ( .A0(n1337), .A1(n1338), .B0(n1336), .Y(n298) );
INVX2TS U190 ( .A(n2596), .Y(n85) );
XOR2X2TS U191 ( .A(n1827), .B(n1828), .Y(n679) );
OAI22X1TS U192 ( .A0(n261), .A1(n1982), .B0(n575), .B1(n2020), .Y(n2021) );
XOR2X1TS U193 ( .A(n1206), .B(n328), .Y(n327) );
XOR2X1TS U194 ( .A(n1668), .B(n2305), .Y(n380) );
OAI2BB1X1TS U195 ( .A0N(n1967), .A1N(n1968), .B0(n548), .Y(n2034) );
AO21X2TS U196 ( .A0(n206), .A1(n175), .B0(n429), .Y(n1973) );
OAI2BB1X2TS U197 ( .A0N(n316), .A1N(n315), .B0(n1439), .Y(n314) );
NAND2X1TS U198 ( .A(n600), .B(n602), .Y(n229) );
OAI22X1TS U199 ( .A0(n164), .A1(n1941), .B0(n181), .B1(n1971), .Y(n1974) );
XOR2X1TS U200 ( .A(n2125), .B(n358), .Y(n958) );
XOR2X1TS U201 ( .A(n151), .B(n1583), .Y(n1542) );
XNOR2X1TS U202 ( .A(n1553), .B(n2142), .Y(n504) );
XOR2X2TS U203 ( .A(n1171), .B(n602), .Y(n601) );
XNOR2X1TS U204 ( .A(n550), .B(n549), .Y(n1972) );
ADDFHX1TS U205 ( .A(n1634), .B(n1633), .CI(n1632), .CO(n1626), .S(n1645) );
XNOR2X1TS U206 ( .A(n1583), .B(n2000), .Y(n1251) );
CMPR32X2TS U207 ( .A(n2518), .B(n1623), .C(n1622), .CO(n1632), .S(n1635) );
INVX2TS U208 ( .A(n1172), .Y(n602) );
BUFX2TS U209 ( .A(n467), .Y(n291) );
INVX2TS U210 ( .A(n674), .Y(n192) );
OAI21X2TS U211 ( .A0(n1271), .A1(n490), .B0(n1270), .Y(n488) );
OAI2BB1X1TS U212 ( .A0N(n746), .A1N(n111), .B0(n744), .Y(n1207) );
CLKINVX2TS U213 ( .A(n1171), .Y(n600) );
XOR2X1TS U214 ( .A(n1229), .B(n1230), .Y(n876) );
OAI2BB1X1TS U215 ( .A0N(n1540), .A1N(n1541), .B0(n569), .Y(n2147) );
XNOR2X2TS U216 ( .A(n1422), .B(n1423), .Y(n544) );
XNOR2X2TS U217 ( .A(n237), .B(n1062), .Y(n1293) );
OAI22X1TS U218 ( .A0(n261), .A1(n1925), .B0(n575), .B1(n1982), .Y(n1985) );
XNOR2X1TS U219 ( .A(n153), .B(n1616), .Y(n1590) );
XOR2X2TS U220 ( .A(n1874), .B(n2000), .Y(n856) );
XNOR2X1TS U221 ( .A(n1874), .B(n177), .Y(n1092) );
INVX2TS U222 ( .A(n341), .Y(n187) );
OAI2BB1X2TS U223 ( .A0N(n1055), .A1N(n1056), .B0(n793), .Y(n1112) );
OAI2BB1X2TS U224 ( .A0N(n1132), .A1N(n1131), .B0(n693), .Y(n1171) );
OAI2BB1X2TS U225 ( .A0N(n1326), .A1N(n708), .B0(n491), .Y(n490) );
INVX2TS U226 ( .A(n519), .Y(n1464) );
OAI21X1TS U227 ( .A0(n1290), .A1(n1291), .B0(n1289), .Y(n606) );
BUFX3TS U228 ( .A(n1030), .Y(n177) );
BUFX3TS U229 ( .A(n913), .Y(n571) );
OAI2BB1X1TS U230 ( .A0N(n1143), .A1N(n286), .B0(n285), .Y(n1189) );
XOR2X2TS U231 ( .A(n1333), .B(n1334), .Y(n668) );
XOR2X2TS U232 ( .A(n745), .B(n111), .Y(n1193) );
XOR2X2TS U233 ( .A(n709), .B(n708), .Y(n1444) );
ADDFHX2TS U234 ( .A(n1420), .B(n1419), .CI(n1418), .CO(n2308), .S(n2306) );
XOR2X1TS U235 ( .A(n1190), .B(n224), .Y(n598) );
XOR2X2TS U236 ( .A(n1554), .B(n1555), .Y(n2141) );
XNOR2X1TS U237 ( .A(n190), .B(Data_A_i[23]), .Y(n1981) );
BUFX3TS U238 ( .A(n1591), .Y(n302) );
INVX4TS U239 ( .A(n576), .Y(n1807) );
CLKINVX2TS U240 ( .A(n61), .Y(n182) );
BUFX3TS U241 ( .A(n1117), .Y(n290) );
NAND2X1TS U242 ( .A(n1608), .B(n1619), .Y(n2888) );
NOR2BX1TS U243 ( .AN(n210), .B(n2175), .Y(n1118) );
OAI2BB1X1TS U244 ( .A0N(n1135), .A1N(n1133), .B0(n593), .Y(n1194) );
XOR2X2TS U245 ( .A(n1487), .B(n392), .Y(n1508) );
XNOR2X2TS U246 ( .A(n66), .B(Data_A_i[11]), .Y(n1212) );
XNOR2X1TS U247 ( .A(n1143), .B(n287), .Y(n1127) );
CLKINVX6TS U248 ( .A(n341), .Y(n1607) );
BUFX6TS U249 ( .A(n1872), .Y(n383) );
INVX2TS U250 ( .A(n1221), .Y(n62) );
BUFX4TS U251 ( .A(n2000), .Y(n772) );
AND2X2TS U252 ( .A(n158), .B(n645), .Y(n1454) );
NAND2BXLTS U253 ( .AN(n1488), .B(n391), .Y(n390) );
OAI22X1TS U254 ( .A0(n2026), .A1(n2024), .B0(n2025), .B1(n1281), .Y(n1316)
);
OAI22X2TS U255 ( .A0(n1825), .A1(n1823), .B0(n63), .B1(n1427), .Y(n1485) );
CLKINVX2TS U256 ( .A(n151), .Y(n152) );
XOR2X2TS U257 ( .A(n1144), .B(n1221), .Y(n287) );
NAND2BXLTS U258 ( .AN(Data_A_i[0]), .B(n186), .Y(n1608) );
NAND2BXLTS U259 ( .AN(Data_A_i[12]), .B(n133), .Y(n1558) );
XNOR2X1TS U260 ( .A(n210), .B(n2070), .Y(n1089) );
XOR2X1TS U261 ( .A(n1003), .B(n1002), .Y(n1277) );
INVX3TS U262 ( .A(n359), .Y(n1872) );
INVX2TS U263 ( .A(n520), .Y(n1799) );
OAI22X1TS U264 ( .A0(n2026), .A1(n1001), .B0(n2025), .B1(n1000), .Y(n1278)
);
OAI22X1TS U265 ( .A0(n172), .A1(n999), .B0(n63), .B1(n998), .Y(n1279) );
NAND2BXLTS U266 ( .AN(n171), .B(n65), .Y(n1560) );
XNOR2X2TS U267 ( .A(n131), .B(Data_A_i[9]), .Y(n1280) );
XOR2X2TS U268 ( .A(n1135), .B(n1133), .Y(n332) );
INVX6TS U269 ( .A(n420), .Y(n2070) );
BUFX6TS U270 ( .A(n2026), .Y(n573) );
NAND2X1TS U271 ( .A(n971), .B(n966), .Y(n704) );
INVX2TS U272 ( .A(n883), .Y(n189) );
NOR2X1TS U273 ( .A(n900), .B(n899), .Y(n901) );
BUFX8TS U274 ( .A(n529), .Y(n497) );
INVX2TS U275 ( .A(n421), .Y(n57) );
BUFX8TS U276 ( .A(n2110), .Y(n575) );
BUFX4TS U277 ( .A(n981), .Y(n181) );
CLKAND2X2TS U278 ( .A(n374), .B(n1023), .Y(n445) );
NAND2BX2TS U279 ( .AN(n343), .B(n973), .Y(n342) );
ADDHX1TS U280 ( .A(n1384), .B(n1383), .CO(n1407), .S(n1420) );
OAI22X2TS U281 ( .A0(n1825), .A1(n1388), .B0(n203), .B1(n1387), .Y(n1405) );
XNOR2X1TS U282 ( .A(n2000), .B(n1642), .Y(n1256) );
NAND2X1TS U283 ( .A(Data_A_i[8]), .B(Data_A_i[20]), .Y(n904) );
INVX1TS U284 ( .A(Data_A_i[1]), .Y(n1052) );
XNOR2X1TS U285 ( .A(n66), .B(Data_A_i[7]), .Y(n998) );
XNOR2X1TS U286 ( .A(n188), .B(Data_A_i[1]), .Y(n997) );
XNOR2X1TS U287 ( .A(Data_B_i[5]), .B(Data_A_i[6]), .Y(n999) );
INVX2TS U288 ( .A(n2000), .Y(n2057) );
NOR2BX1TS U289 ( .AN(n171), .B(n421), .Y(n1050) );
NAND2X2TS U290 ( .A(n346), .B(n802), .Y(n345) );
XNOR2X2TS U291 ( .A(n133), .B(Data_A_i[17]), .Y(n1430) );
XNOR2X1TS U292 ( .A(Data_B_i[13]), .B(Data_A_i[19]), .Y(n1369) );
XNOR2X1TS U293 ( .A(n136), .B(Data_A_i[13]), .Y(n1395) );
XNOR2X1TS U294 ( .A(n170), .B(Data_A_i[15]), .Y(n1397) );
BUFX6TS U295 ( .A(n2018), .Y(n496) );
NAND2X1TS U296 ( .A(n1008), .B(n1013), .Y(n613) );
INVX2TS U297 ( .A(n541), .Y(n275) );
INVX4TS U298 ( .A(n1867), .Y(n136) );
INVX2TS U299 ( .A(n134), .Y(n135) );
NAND2BX2TS U300 ( .AN(n967), .B(n968), .Y(n367) );
NOR2X2TS U301 ( .A(n424), .B(n369), .Y(n423) );
XNOR2X2TS U302 ( .A(n131), .B(Data_A_i[6]), .Y(n1385) );
INVX4TS U303 ( .A(Data_B_i[11]), .Y(n204) );
XNOR2X1TS U304 ( .A(n190), .B(Data_A_i[14]), .Y(n944) );
XNOR2X1TS U305 ( .A(n520), .B(Data_A_i[18]), .Y(n942) );
INVX2TS U306 ( .A(Data_B_i[12]), .Y(n974) );
INVX6TS U307 ( .A(n1561), .Y(n65) );
BUFX6TS U308 ( .A(Data_B_i[15]), .Y(n279) );
BUFX3TS U309 ( .A(n1011), .Y(n645) );
INVX3TS U310 ( .A(n429), .Y(n132) );
BUFX8TS U311 ( .A(Data_B_i[17]), .Y(n520) );
INVX3TS U312 ( .A(Data_B_i[8]), .Y(n836) );
XNOR2X1TS U313 ( .A(n1012), .B(n721), .Y(n1010) );
NOR2X1TS U314 ( .A(Data_A_i[20]), .B(Data_A_i[8]), .Y(n902) );
OAI21X1TS U315 ( .A0(Data_B_i[4]), .A1(Data_B_i[16]), .B0(Data_B_i[3]), .Y(
n397) );
NAND2XLTS U316 ( .A(Data_B_i[16]), .B(Data_B_i[4]), .Y(n446) );
NAND2X6TS U317 ( .A(n2018), .B(n498), .Y(n529) );
NOR2X1TS U318 ( .A(Data_B_i[7]), .B(Data_B_i[19]), .Y(n721) );
OAI21X2TS U319 ( .A0(Data_B_i[20]), .A1(Data_B_i[8]), .B0(Data_B_i[7]), .Y(
n752) );
XNOR2X2TS U320 ( .A(n581), .B(Data_A_i[14]), .Y(n1065) );
XNOR2X1TS U321 ( .A(n190), .B(Data_A_i[15]), .Y(n943) );
XNOR2X1TS U322 ( .A(Data_B_i[17]), .B(Data_A_i[20]), .Y(n1071) );
BUFX6TS U323 ( .A(Data_B_i[23]), .Y(n581) );
INVX12TS U324 ( .A(Data_B_i[9]), .Y(n883) );
CLKINVX3TS U325 ( .A(n551), .Y(n438) );
NAND2X1TS U326 ( .A(Data_A_i[18]), .B(Data_A_i[6]), .Y(n1040) );
NOR2X4TS U327 ( .A(Data_B_i[16]), .B(Data_B_i[15]), .Y(n402) );
BUFX8TS U328 ( .A(Data_B_i[15]), .Y(n624) );
INVX3TS U329 ( .A(Data_B_i[23]), .Y(n220) );
INVX2TS U330 ( .A(n1025), .Y(n64) );
CLKINVX6TS U331 ( .A(Data_B_i[12]), .Y(n1640) );
CLKINVX3TS U332 ( .A(Data_B_i[0]), .Y(n1639) );
NOR2X6TS U333 ( .A(Data_A_i[17]), .B(Data_A_i[5]), .Y(n1025) );
NAND2X2TS U334 ( .A(Data_A_i[3]), .B(Data_A_i[15]), .Y(n964) );
INVX2TS U335 ( .A(n970), .Y(n788) );
NAND2X1TS U336 ( .A(n401), .B(n163), .Y(n448) );
NOR2X1TS U337 ( .A(Data_A_i[21]), .B(Data_A_i[9]), .Y(n905) );
INVX2TS U338 ( .A(n205), .Y(n77) );
OAI21X2TS U339 ( .A0(n1015), .A1(n1039), .B0(n1040), .Y(n1016) );
NAND2X2TS U340 ( .A(Data_A_i[13]), .B(Data_A_i[1]), .Y(n960) );
INVX2TS U341 ( .A(n1976), .Y(n759) );
XNOR2X2TS U342 ( .A(n1807), .B(n623), .Y(n1242) );
OAI22X2TS U343 ( .A0(n571), .A1(n1145), .B0(n187), .B1(n358), .Y(n1156) );
NAND2X6TS U344 ( .A(n2185), .B(n786), .Y(n2186) );
NOR2X2TS U345 ( .A(n204), .B(n1052), .Y(n1221) );
OAI22X1TS U346 ( .A0(n1243), .A1(n205), .B0(n1809), .B1(n156), .Y(n1784) );
OAI21X2TS U347 ( .A0(n353), .A1(n2266), .B0(n352), .Y(n1276) );
NAND2X2TS U348 ( .A(n400), .B(n401), .Y(n399) );
OAI22X1TS U349 ( .A0(n194), .A1(n924), .B0(n921), .B1(n974), .Y(n946) );
XNOR2X1TS U350 ( .A(n190), .B(Data_A_i[13]), .Y(n1267) );
ADDFHX2TS U351 ( .A(n1153), .B(n1152), .CI(n1154), .CO(n1166), .S(n1168) );
OAI2BB1X2TS U352 ( .A0N(n1348), .A1N(n320), .B0(n299), .Y(n1339) );
OAI21X1TS U353 ( .A0(n1055), .A1(n1056), .B0(n1054), .Y(n793) );
XNOR2X1TS U354 ( .A(Data_B_i[9]), .B(Data_A_i[1]), .Y(n1286) );
OAI2BB1X1TS U355 ( .A0N(n200), .A1N(n1926), .B0(n136), .Y(n1984) );
OAI22X1TS U356 ( .A0(n595), .A1(n1367), .B0(n208), .B1(n1327), .Y(n1373) );
XNOR2X2TS U357 ( .A(n1478), .B(n1479), .Y(n848) );
INVX4TS U358 ( .A(n581), .Y(n89) );
ADDFHX2TS U359 ( .A(n2009), .B(n2008), .CI(n2007), .CO(n2051), .S(n2046) );
OAI22X2TS U360 ( .A0(n595), .A1(n1548), .B0(n208), .B1(n1547), .Y(n1554) );
ADDFHX2TS U361 ( .A(n1974), .B(n1973), .CI(n1972), .CO(n2032), .S(n1986) );
XOR3X1TS U362 ( .A(n2255), .B(n2254), .C(n2253), .Y(n2256) );
OAI21X1TS U363 ( .A0(n2036), .A1(n2037), .B0(n2035), .Y(n878) );
INVX2TS U364 ( .A(n2429), .Y(n2430) );
INVX2TS U365 ( .A(n2402), .Y(n1644) );
NOR2XLTS U366 ( .A(n2334), .B(n2333), .Y(n2369) );
OAI2BB1X2TS U367 ( .A0N(n1444), .A1N(n1443), .B0(n753), .Y(n2162) );
NOR2XLTS U368 ( .A(n2477), .B(n2480), .Y(n2483) );
OR2X1TS U369 ( .A(n2257), .B(n2256), .Y(n108) );
XOR2X2TS U370 ( .A(Data_A_i[3]), .B(n802), .Y(n1543) );
INVX2TS U371 ( .A(n2406), .Y(n2408) );
OAI2BB1X1TS U372 ( .A0N(n1779), .A1N(n236), .B0(n234), .Y(n2637) );
INVX2TS U373 ( .A(n2559), .Y(n2561) );
INVX2TS U374 ( .A(n2275), .Y(n2277) );
INVX2TS U375 ( .A(n2358), .Y(n2467) );
AND2X2TS U376 ( .A(n108), .B(n2258), .Y(n110) );
INVX2TS U377 ( .A(n2713), .Y(n2702) );
NOR2XLTS U378 ( .A(n2661), .B(n2660), .Y(n2671) );
INVX2TS U379 ( .A(n2885), .Y(n2413) );
NAND2X1TS U380 ( .A(n2555), .B(n2556), .Y(n2557) );
OAI21XLTS U381 ( .A0(n2509), .A1(n2519), .B0(n2510), .Y(n2285) );
INVX2TS U382 ( .A(n2671), .Y(n2680) );
XNOR2X1TS U383 ( .A(n186), .B(Data_A_i[1]), .Y(n1618) );
INVX4TS U384 ( .A(n2768), .Y(n2727) );
NAND2X1TS U385 ( .A(n2737), .B(n2736), .Y(n2738) );
NOR2X2TS U386 ( .A(n2856), .B(n2858), .Y(n804) );
INVX2TS U387 ( .A(n451), .Y(n2744) );
NOR2X2TS U388 ( .A(n2415), .B(n2414), .Y(n2404) );
OAI21XLTS U389 ( .A0(n2934), .A1(n2933), .B0(n2932), .Y(n2939) );
INVX2TS U390 ( .A(n2942), .Y(n2949) );
OAI21XLTS U391 ( .A0(n2735), .A1(n2734), .B0(n2733), .Y(n2741) );
NAND2BX1TS U392 ( .AN(n2521), .B(n463), .Y(n2877) );
INVX2TS U393 ( .A(n2782), .Y(n2982) );
INVX2TS U394 ( .A(n3005), .Y(n478) );
AOI21X1TS U395 ( .A0(n795), .A1(n2967), .B0(n121), .Y(n3017) );
AOI21X1TS U396 ( .A0(n817), .A1(n2967), .B0(n124), .Y(n3008) );
INVX2TS U397 ( .A(n2811), .Y(n3026) );
NAND2X1TS U398 ( .A(n2768), .B(n2744), .Y(n52) );
AND2X4TS U399 ( .A(n714), .B(n713), .Y(n53) );
INVX2TS U400 ( .A(n216), .Y(n1376) );
OR2X2TS U401 ( .A(Data_A_i[12]), .B(Data_A_i[0]), .Y(n54) );
NOR2X1TS U402 ( .A(n2324), .B(n2323), .Y(n2387) );
XNOR2X4TS U403 ( .A(n572), .B(n1780), .Y(n55) );
XNOR2X4TS U404 ( .A(n1031), .B(n1032), .Y(n56) );
XNOR2X2TS U405 ( .A(n973), .B(n972), .Y(n1620) );
BUFX6TS U406 ( .A(n2070), .Y(n623) );
INVX2TS U407 ( .A(n1413), .Y(n456) );
INVX2TS U408 ( .A(n2742), .Y(n191) );
AOI21X1TS U409 ( .A0(n825), .A1(n2967), .B0(n120), .Y(n3013) );
CLKINVX2TS U410 ( .A(n2654), .Y(n2622) );
INVX4TS U411 ( .A(n2744), .Y(n2771) );
NOR2X4TS U412 ( .A(n2727), .B(n2621), .Y(n2652) );
INVX2TS U413 ( .A(n2784), .Y(n2785) );
NOR2BX4TS U414 ( .AN(n2591), .B(n453), .Y(n451) );
INVX1TS U415 ( .A(n2780), .Y(n2786) );
INVX1TS U416 ( .A(n2844), .Y(n2846) );
NAND2X2TS U417 ( .A(n2495), .B(n2494), .Y(n2866) );
CLKINVX2TS U418 ( .A(n2233), .Y(n671) );
INVX2TS U419 ( .A(n1746), .Y(n473) );
INVX2TS U420 ( .A(n2222), .Y(n2206) );
CLKINVX2TS U421 ( .A(n2644), .Y(n2645) );
XOR2X1TS U422 ( .A(n2741), .B(n2740), .Y(n886) );
XNOR2X2TS U423 ( .A(n2676), .B(n2675), .Y(n887) );
XOR2X1TS U424 ( .A(n2442), .B(n2441), .Y(n2454) );
NAND2X1TS U425 ( .A(n2464), .B(n144), .Y(n2465) );
INVX2TS U426 ( .A(n1694), .Y(n713) );
NOR2X6TS U427 ( .A(n2134), .B(n2133), .Y(n2220) );
XOR2X2TS U428 ( .A(n2452), .B(n506), .Y(n2455) );
OAI2BB1X2TS U429 ( .A0N(n414), .A1N(n2004), .B0(n413), .Y(n2005) );
INVX1TS U430 ( .A(n2484), .Y(n2359) );
CLKINVX1TS U431 ( .A(n2633), .Y(n2612) );
INVX2TS U432 ( .A(n2265), .Y(n2200) );
CLKINVX1TS U433 ( .A(n2627), .Y(n2611) );
OAI21X2TS U434 ( .A0(n1688), .A1(n1689), .B0(n1687), .Y(n362) );
INVX1TS U435 ( .A(n2443), .Y(n2445) );
CLKINVX1TS U436 ( .A(n2604), .Y(n2594) );
INVX1TS U437 ( .A(n2369), .Y(n2382) );
INVX2TS U438 ( .A(n1852), .Y(n2331) );
OAI2BB1X1TS U439 ( .A0N(n1900), .A1N(n254), .B0(n253), .Y(n1955) );
CLKINVX1TS U440 ( .A(n2630), .Y(n2618) );
XOR2X1TS U441 ( .A(n2934), .B(n2928), .Y(n2931) );
OAI21X1TS U442 ( .A0(n1915), .A1(n222), .B0(n1914), .Y(n221) );
CLKINVX1TS U443 ( .A(n2682), .Y(n2685) );
CLKINVX1TS U444 ( .A(n2262), .Y(n2203) );
NAND2X2TS U445 ( .A(n229), .B(n1170), .Y(n599) );
INVX1TS U446 ( .A(n2321), .Y(n527) );
CLKINVX1TS U447 ( .A(n2466), .Y(n2346) );
CLKINVX1TS U448 ( .A(n2259), .Y(n2164) );
OAI21X1TS U449 ( .A0(n254), .A1(n1900), .B0(n1899), .Y(n253) );
INVX2TS U450 ( .A(n2341), .Y(n2014) );
INVX3TS U451 ( .A(n2342), .Y(n2041) );
CLKINVX2TS U452 ( .A(n2522), .Y(n670) );
OAI21X2TS U453 ( .A0(n1112), .A1(n1113), .B0(n1111), .Y(n858) );
INVX1TS U454 ( .A(n1500), .Y(n780) );
XOR2X2TS U455 ( .A(n2045), .B(n760), .Y(n1993) );
NOR2X1TS U456 ( .A(n2704), .B(n2703), .Y(n2715) );
XOR2X1TS U457 ( .A(n2910), .B(n2909), .Y(n2912) );
OR2X2TS U458 ( .A(n2157), .B(n2158), .Y(n104) );
AND2X2TS U459 ( .A(n337), .B(n2283), .Y(n2278) );
CLKINVX1TS U460 ( .A(n2734), .Y(n2722) );
INVX2TS U461 ( .A(n2042), .Y(n2689) );
INVX3TS U462 ( .A(n2147), .Y(n1535) );
OAI2BB1X2TS U463 ( .A0N(n1828), .A1N(n1827), .B0(n682), .Y(n681) );
INVX1TS U464 ( .A(n1710), .Y(n561) );
INVX1TS U465 ( .A(n1292), .Y(n306) );
INVX1TS U466 ( .A(n2309), .Y(n781) );
OAI21X2TS U467 ( .A0(n1207), .A1(n1206), .B0(n1205), .Y(n555) );
OR2X2TS U468 ( .A(n2737), .B(n2736), .Y(n2739) );
INVX1TS U469 ( .A(n1645), .Y(n507) );
OAI2BB1X2TS U470 ( .A0N(n1985), .A1N(n1984), .B0(n762), .Y(n2035) );
XOR2X1TS U471 ( .A(n1933), .B(n523), .Y(n1949) );
OAI21X2TS U472 ( .A0(n1470), .A1(n1471), .B0(n1469), .Y(n278) );
INVX2TS U473 ( .A(n2736), .Y(n2249) );
XOR2X1TS U474 ( .A(n1935), .B(n1934), .Y(n523) );
XOR2X2TS U475 ( .A(n1936), .B(n1937), .Y(n589) );
INVX1TS U476 ( .A(n1366), .Y(n71) );
INVX1TS U477 ( .A(n1984), .Y(n764) );
INVX4TS U478 ( .A(n2296), .Y(n1594) );
XOR2X1TS U479 ( .A(n1326), .B(n1325), .Y(n709) );
INVX1TS U480 ( .A(n1828), .Y(n683) );
NAND2BX1TS U481 ( .AN(n1642), .B(n56), .Y(n1435) );
CLKINVX1TS U482 ( .A(n2517), .Y(n1622) );
INVX2TS U483 ( .A(n1616), .Y(n1125) );
CLKINVX2TS U484 ( .A(n2518), .Y(n1614) );
AO21X1TS U485 ( .A0(n529), .A1(n2018), .B0(n2017), .Y(n2083) );
INVX1TS U486 ( .A(n954), .Y(n915) );
CLKINVX2TS U487 ( .A(n1979), .Y(n1932) );
CLKINVX1TS U488 ( .A(n1220), .Y(n264) );
NAND2X2TS U489 ( .A(n54), .B(n961), .Y(n1086) );
NAND2X1TS U490 ( .A(n2982), .B(sgf_result_o[14]), .Y(n2983) );
NAND2X1TS U491 ( .A(n2982), .B(sgf_result_o[11]), .Y(n2961) );
NAND2X1TS U492 ( .A(n2982), .B(sgf_result_o[10]), .Y(n2954) );
INVX2TS U493 ( .A(n96), .Y(sgf_result_o[46]) );
INVX2TS U494 ( .A(n960), .Y(n424) );
INVX2TS U495 ( .A(n964), .Y(n334) );
INVX2TS U496 ( .A(n2782), .Y(n2779) );
AOI21X1TS U497 ( .A0(n442), .A1(n2967), .B0(n117), .Y(n3012) );
AOI21X2TS U498 ( .A0(n821), .A1(n747), .B0(n118), .Y(n3016) );
OAI21X2TS U499 ( .A0(n191), .A1(n2710), .B0(n2709), .Y(n2711) );
OAI21X1TS U500 ( .A0(n2774), .A1(n2668), .B0(n2667), .Y(n2669) );
OAI21X1TS U501 ( .A0(n2747), .A1(n2755), .B0(n2756), .Y(n2748) );
XOR2X1TS U502 ( .A(n726), .B(n2798), .Y(n725) );
NOR2X1TS U503 ( .A(n2745), .B(n2755), .Y(n2749) );
CLKINVX2TS U504 ( .A(n2755), .Y(n2757) );
NAND2X1TS U505 ( .A(n2751), .B(n2752), .Y(n2753) );
NAND2BX1TS U506 ( .AN(n3005), .B(n2883), .Y(n2884) );
XOR2X1TS U507 ( .A(n2882), .B(n2881), .Y(n2883) );
NAND2BX1TS U508 ( .AN(n2975), .B(n2863), .Y(n2864) );
NAND2BX1TS U509 ( .AN(n2975), .B(n2870), .Y(n2871) );
XOR2X1TS U510 ( .A(n2869), .B(n146), .Y(n2870) );
OAI21X1TS U511 ( .A0(n2857), .A1(n2856), .B0(n720), .Y(n2862) );
NAND2BX1TS U512 ( .AN(n3005), .B(n3004), .Y(n3006) );
XOR2X1TS U513 ( .A(n2857), .B(n2828), .Y(n2830) );
XOR2X1TS U514 ( .A(n2817), .B(n2816), .Y(n2819) );
NOR2X1TS U515 ( .A(n882), .B(n2222), .Y(n881) );
XOR2X1TS U516 ( .A(n2823), .B(n141), .Y(n2825) );
NAND2BX1TS U517 ( .AN(n3005), .B(n2994), .Y(n2995) );
XOR2X1TS U518 ( .A(n2998), .B(n2853), .Y(n2855) );
INVX1TS U519 ( .A(n2865), .Y(n2867) );
INVX4TS U520 ( .A(n1771), .Y(n678) );
INVX3TS U521 ( .A(n2269), .Y(n857) );
INVX3TS U522 ( .A(n2271), .Y(n58) );
INVX1TS U523 ( .A(n2856), .Y(n2827) );
NAND2X4TS U524 ( .A(n474), .B(n473), .Y(n2500) );
INVX2TS U525 ( .A(n2677), .Y(n2666) );
INVX1TS U526 ( .A(n720), .Y(n719) );
NAND2X2TS U527 ( .A(n2472), .B(n805), .Y(n720) );
NAND2BX1TS U528 ( .AN(n2975), .B(n2974), .Y(n2976) );
INVX1TS U529 ( .A(n2820), .Y(n2822) );
NAND2BX2TS U530 ( .AN(n888), .B(n336), .Y(n2677) );
NOR2BX2TS U531 ( .AN(n2665), .B(n2664), .Y(n336) );
NAND2X2TS U532 ( .A(n2229), .B(n2221), .Y(n2232) );
XOR2X1TS U533 ( .A(n2493), .B(n2492), .Y(n2494) );
XOR2X1TS U534 ( .A(n2469), .B(n2468), .Y(n2470) );
INVX1TS U535 ( .A(n2591), .Y(n452) );
XOR2X1TS U536 ( .A(n2735), .B(n2723), .Y(n2725) );
XNOR2X1TS U537 ( .A(n2620), .B(n2619), .Y(n889) );
INVX1TS U538 ( .A(n1843), .Y(n1839) );
XOR2X1TS U539 ( .A(n2610), .B(n2609), .Y(n2644) );
XNOR2X1TS U540 ( .A(n2719), .B(n2638), .Y(n2653) );
OAI21X1TS U541 ( .A0(n2359), .A1(n2477), .B0(n2481), .Y(n2347) );
OAI21X1TS U542 ( .A0(n2359), .A1(n2358), .B0(n2466), .Y(n2360) );
OAI21X1TS U543 ( .A0(n2716), .A1(n2715), .B0(n2714), .Y(n2717) );
INVX1TS U544 ( .A(n2716), .Y(n2701) );
NOR2X1TS U545 ( .A(n2357), .B(n2477), .Y(n2348) );
OAI21X1TS U546 ( .A0(n2612), .A1(n2626), .B0(n2629), .Y(n2613) );
XOR2X1TS U547 ( .A(n2219), .B(n2218), .Y(n2585) );
INVX1TS U548 ( .A(n2431), .Y(n2434) );
NAND2X4TS U549 ( .A(n465), .B(n464), .Y(n1714) );
OAI2BB1X2TS U550 ( .A0N(n1689), .A1N(n1688), .B0(n362), .Y(n1694) );
AOI21X2TS U551 ( .A0(n2265), .A1(n2264), .B0(n2263), .Y(n2635) );
NAND2X2TS U552 ( .A(n86), .B(n87), .Y(n267) );
INVX1TS U553 ( .A(n2478), .Y(n2357) );
INVX1TS U554 ( .A(n2433), .Y(n2419) );
OAI21X1TS U555 ( .A0(n2688), .A1(n2687), .B0(n2686), .Y(n2700) );
INVX1TS U556 ( .A(n2605), .Y(n2598) );
NAND2BX1TS U557 ( .AN(n2975), .B(n2940), .Y(n2941) );
INVX1TS U558 ( .A(n2379), .Y(n2449) );
NOR2X1TS U559 ( .A(n2681), .B(n2688), .Y(n2696) );
NAND2BX1TS U560 ( .AN(n2975), .B(n2945), .Y(n2946) );
NAND2X2TS U561 ( .A(n2323), .B(n85), .Y(n86) );
XOR2X1TS U562 ( .A(n2953), .B(n2952), .Y(n2955) );
OAI21X1TS U563 ( .A0(n2448), .A1(n2369), .B0(n2381), .Y(n2370) );
INVX1TS U564 ( .A(n2209), .Y(n2216) );
OAI21X1TS U565 ( .A0(n2550), .A1(n2546), .B0(n2547), .Y(n2543) );
NOR2X1TS U566 ( .A(n2605), .B(n2602), .Y(n2627) );
NAND2X1TS U567 ( .A(n2440), .B(n2439), .Y(n2441) );
NAND2X2TS U568 ( .A(n309), .B(n308), .Y(n1755) );
NAND2X2TS U569 ( .A(n456), .B(n291), .Y(n466) );
OAI21X1TS U570 ( .A0(n2481), .A1(n2480), .B0(n2479), .Y(n2482) );
INVX1TS U571 ( .A(n2387), .Y(n2389) );
OAI21X1TS U572 ( .A0(n2630), .A1(n2629), .B0(n2628), .Y(n2631) );
INVX1TS U573 ( .A(n2626), .Y(n2608) );
NOR2X1TS U574 ( .A(n2626), .B(n2630), .Y(n2632) );
INVX1TS U575 ( .A(n2602), .Y(n2595) );
INVX1TS U576 ( .A(n2438), .Y(n2440) );
INVX1TS U577 ( .A(n1650), .Y(n349) );
OAI21X1TS U578 ( .A0(n2262), .A1(n2261), .B0(n2260), .Y(n2263) );
INVX1TS U579 ( .A(n2950), .Y(n2315) );
XOR2X2TS U580 ( .A(n869), .B(n2105), .Y(n2130) );
OAI21X1TS U581 ( .A0(n2687), .A1(n2671), .B0(n2682), .Y(n2672) );
CLKINVX1TS U582 ( .A(n2381), .Y(n2338) );
INVX1TS U583 ( .A(n2956), .Y(n2958) );
INVX1TS U584 ( .A(n2372), .Y(n2337) );
NAND2BX1TS U585 ( .AN(n3005), .B(n2917), .Y(n2918) );
INVX1TS U586 ( .A(n2687), .Y(n2658) );
INVX4TS U587 ( .A(n147), .Y(n2326) );
XOR2X1TS U588 ( .A(n2396), .B(n2395), .Y(n2417) );
INVX1TS U589 ( .A(n2681), .Y(n2659) );
OAI21X1TS U590 ( .A0(n2105), .A1(n2104), .B0(n2103), .Y(n868) );
INVX1TS U591 ( .A(n2362), .Y(n2345) );
OAI21X1TS U592 ( .A0(n2539), .A1(n2547), .B0(n2540), .Y(n2153) );
OAI2BB1X2TS U593 ( .A0N(n1225), .A1N(n1224), .B0(n325), .Y(n2327) );
INVX1TS U594 ( .A(n2539), .Y(n2541) );
XOR2X1TS U595 ( .A(n2279), .B(n2278), .Y(n2529) );
INVX1TS U596 ( .A(n1532), .Y(n365) );
INVX1TS U597 ( .A(n2715), .Y(n2705) );
OAI21X2TS U598 ( .A0(n2395), .A1(n2392), .B0(n2393), .Y(n2424) );
INVX2TS U599 ( .A(n1913), .Y(n2661) );
XOR2X2TS U600 ( .A(n1532), .B(n1531), .Y(n661) );
CLKINVX2TS U601 ( .A(n2210), .Y(n2215) );
XOR2X1TS U602 ( .A(n2403), .B(n2402), .Y(n2414) );
NOR2X1TS U603 ( .A(n2637), .B(n700), .Y(n2681) );
INVX1TS U604 ( .A(n2697), .Y(n2698) );
INVX1TS U605 ( .A(n2217), .Y(n2159) );
OAI21X1TS U606 ( .A0(n2275), .A1(n2278), .B0(n2276), .Y(n2573) );
INVX2TS U607 ( .A(n2319), .Y(n1351) );
INVX1TS U608 ( .A(n2683), .Y(n2684) );
OR2X2TS U609 ( .A(n2690), .B(n2689), .Y(n2699) );
OR2X2TS U610 ( .A(n2344), .B(n2343), .Y(n106) );
INVX1TS U611 ( .A(n2546), .Y(n2548) );
INVX1TS U612 ( .A(n1531), .Y(n366) );
ADDFHX2TS U613 ( .A(n1537), .B(n1535), .CI(n1536), .CO(n1532), .S(n1657) );
XOR2X1TS U614 ( .A(n572), .B(n1780), .Y(n149) );
OAI21X2TS U615 ( .A0(n1224), .A1(n1225), .B0(n326), .Y(n325) );
OAI2BB1X1TS U616 ( .A0N(n1628), .A1N(n312), .B0(n310), .Y(n1604) );
ADDFHX2TS U617 ( .A(n1157), .B(n1156), .CI(n1155), .CO(n1830), .S(n1165) );
CLKINVX2TS U618 ( .A(n2690), .Y(n2040) );
INVX2TS U619 ( .A(n2400), .Y(n508) );
INVX1TS U620 ( .A(n2913), .Y(n2303) );
INVX1TS U621 ( .A(n2480), .Y(n2351) );
NAND2X4TS U622 ( .A(n790), .B(n789), .Y(n840) );
INVX1TS U623 ( .A(n2660), .Y(n222) );
OAI21X1TS U624 ( .A0(n1628), .A1(n312), .B0(n1627), .Y(n310) );
OAI2BB1X2TS U625 ( .A0N(n1991), .A1N(n1990), .B0(n830), .Y(n2690) );
INVX1TS U626 ( .A(n2919), .Y(n2921) );
XNOR2X1TS U627 ( .A(n1975), .B(n1976), .Y(n760) );
INVX2TS U628 ( .A(n2157), .Y(n1726) );
INVX1TS U629 ( .A(n2933), .Y(n2927) );
INVX1TS U630 ( .A(n2571), .Y(n2146) );
NAND2BX1TS U631 ( .AN(n2975), .B(n2904), .Y(n2905) );
NOR2X1TS U632 ( .A(n2350), .B(n2349), .Y(n2480) );
INVX1TS U633 ( .A(n2305), .Y(n396) );
INVX3TS U634 ( .A(n2307), .Y(n1506) );
INVX3TS U635 ( .A(n2301), .Y(n732) );
OAI2BB1X2TS U636 ( .A0N(n1227), .A1N(n1226), .B0(n675), .Y(n236) );
NAND2BX1TS U637 ( .AN(n2142), .B(n1553), .Y(n502) );
OAI2BB1X2TS U638 ( .A0N(n1935), .A1N(n1934), .B0(n522), .Y(n1989) );
INVX2TS U639 ( .A(n1475), .Y(n691) );
OR2X2TS U640 ( .A(n2489), .B(n2488), .Y(n2491) );
INVX1TS U641 ( .A(n1626), .Y(n514) );
NAND2X2TS U642 ( .A(n841), .B(n842), .Y(n791) );
NAND2XLTS U643 ( .A(n2890), .B(n2967), .Y(n2891) );
CLKINVX1TS U644 ( .A(n2509), .Y(n2511) );
INVX2TS U645 ( .A(n1827), .Y(n684) );
INVX1TS U646 ( .A(n1440), .Y(n315) );
INVX1TS U647 ( .A(n1118), .Y(n642) );
INVX3TS U648 ( .A(n2141), .Y(n60) );
INVX2TS U649 ( .A(n2184), .Y(n2241) );
INVX1TS U650 ( .A(n2900), .Y(n2298) );
NAND2BX1TS U651 ( .AN(n1229), .B(n875), .Y(n874) );
NAND2X2TS U652 ( .A(n1075), .B(n933), .Y(n937) );
INVX1TS U653 ( .A(n1441), .Y(n316) );
ADDFHX2TS U654 ( .A(n1279), .B(n1278), .CI(n1277), .CO(n1054), .S(n1344) );
INVX1TS U655 ( .A(n2893), .Y(n2895) );
OAI2BB1X2TS U656 ( .A0N(n1236), .A1N(n1235), .B0(n248), .Y(n1802) );
XNOR2X2TS U657 ( .A(n1174), .B(n1175), .Y(n247) );
NAND2BX1TS U658 ( .AN(n1566), .B(n274), .Y(n271) );
INVX2TS U659 ( .A(n2295), .Y(n1615) );
INVX1TS U660 ( .A(n1476), .Y(n690) );
INVX1TS U661 ( .A(n1985), .Y(n763) );
INVX1TS U662 ( .A(n1075), .Y(n935) );
INVX1TS U663 ( .A(n1230), .Y(n875) );
ADDFHX2TS U664 ( .A(n2183), .B(n2182), .CI(n2181), .CO(n2184), .S(n2736) );
AND2X2TS U665 ( .A(n2520), .B(n2519), .Y(n2521) );
INVX6TS U666 ( .A(n702), .Y(n2175) );
ADDFHX2TS U667 ( .A(n1820), .B(n1819), .CI(n1818), .CO(n1891), .S(n1828) );
CLKINVX1TS U668 ( .A(n1365), .Y(n70) );
NAND2BX1TS U669 ( .AN(n3005), .B(n2885), .Y(n2886) );
INVX4TS U670 ( .A(n56), .Y(n61) );
AND2X2TS U671 ( .A(n2982), .B(sgf_result_o[37]), .Y(n121) );
AND2X2TS U672 ( .A(n2929), .B(sgf_result_o[42]), .Y(n117) );
AND2X2TS U673 ( .A(n2929), .B(sgf_result_o[45]), .Y(n2778) );
NAND2X4TS U674 ( .A(n1579), .B(n923), .Y(n1565) );
XNOR2X1TS U675 ( .A(n1968), .B(n1967), .Y(n549) );
AND2X2TS U676 ( .A(n2779), .B(sgf_result_o[33]), .Y(n115) );
NAND2XLTS U677 ( .A(n2929), .B(sgf_result_o[7]), .Y(n2930) );
NAND2XLTS U678 ( .A(n2929), .B(sgf_result_o[6]), .Y(n2924) );
AND2X2TS U679 ( .A(n2982), .B(sgf_result_o[35]), .Y(n122) );
INVX1TS U680 ( .A(n2064), .Y(n2031) );
NAND2XLTS U681 ( .A(n2929), .B(sgf_result_o[4]), .Y(n2911) );
AND2X2TS U682 ( .A(n2779), .B(sgf_result_o[32]), .Y(n114) );
NAND2XLTS U683 ( .A(n2929), .B(sgf_result_o[2]), .Y(n2898) );
CLKINVX2TS U684 ( .A(n2179), .Y(n2117) );
AND2X2TS U685 ( .A(n2779), .B(sgf_result_o[31]), .Y(n113) );
OAI21X2TS U686 ( .A0(n1018), .A1(n1040), .B0(n1019), .Y(n450) );
NOR2X1TS U687 ( .A(n204), .B(n2112), .Y(n2178) );
NAND2X2TS U688 ( .A(n446), .B(n397), .Y(n1031) );
INVX8TS U689 ( .A(n1011), .Y(n2018) );
INVX2TS U690 ( .A(n343), .Y(n972) );
INVX8TS U691 ( .A(n1824), .Y(n63) );
NOR2X1TS U692 ( .A(n204), .B(n2060), .Y(n2179) );
NOR2X2TS U693 ( .A(n204), .B(n1944), .Y(n1967) );
NOR2X2TS U694 ( .A(n204), .B(n1888), .Y(n1968) );
INVX6TS U695 ( .A(n163), .Y(n66) );
INVX6TS U696 ( .A(n883), .Y(n67) );
INVX12TS U697 ( .A(Data_B_i[11]), .Y(n421) );
XOR2X4TS U698 ( .A(n447), .B(n68), .Y(n109) );
AND2X4TS U699 ( .A(n1031), .B(n1032), .Y(n68) );
OAI21XLTS U700 ( .A0(n1381), .A1(n568), .B0(n1380), .Y(n567) );
XNOR2X2TS U701 ( .A(Data_B_i[17]), .B(Data_A_i[23]), .Y(n1232) );
NAND2X4TS U702 ( .A(n348), .B(n347), .Y(n2451) );
OAI2BB1X2TS U703 ( .A0N(n1525), .A1N(n1526), .B0(n630), .Y(n1696) );
OAI2BB1X4TS U704 ( .A0N(n1476), .A1N(n1475), .B0(n689), .Y(n69) );
OAI21X2TS U705 ( .A0(n1497), .A1(n1498), .B0(n1496), .Y(n846) );
NOR2X6TS U706 ( .A(n67), .B(Data_B_i[21]), .Y(n481) );
OAI2BB1X2TS U707 ( .A0N(n1532), .A1N(n1531), .B0(n364), .Y(n1527) );
OAI2BB1X4TS U708 ( .A0N(n1736), .A1N(n1734), .B0(n304), .Y(n1741) );
NOR2X8TS U709 ( .A(n53), .B(n2288), .Y(n1699) );
XNOR2X2TS U710 ( .A(n1616), .B(n56), .Y(n1517) );
OAI22X2TS U711 ( .A0(n573), .A1(n1196), .B0(n609), .B1(n1217), .Y(n1216) );
XOR2X2TS U712 ( .A(n2421), .B(n2420), .Y(n2427) );
OAI22X1TS U713 ( .A0(n2038), .A1(n202), .B0(n162), .B1(n2057), .Y(n2085) );
NOR2X4TS U714 ( .A(n1039), .B(n1018), .Y(n891) );
XOR2X2TS U715 ( .A(n1250), .B(n357), .Y(n356) );
XOR2X4TS U716 ( .A(n1275), .B(n1276), .Y(n584) );
AND2X4TS U717 ( .A(n897), .B(n893), .Y(n948) );
INVX2TS U718 ( .A(n905), .Y(n893) );
NAND2X1TS U719 ( .A(n1365), .B(n71), .Y(n72) );
NAND2X1TS U720 ( .A(n70), .B(n1366), .Y(n73) );
NAND2X2TS U721 ( .A(n72), .B(n73), .Y(n612) );
OAI22X2TS U722 ( .A0(n1432), .A1(n1368), .B0(n242), .B1(n1269), .Y(n1365) );
OAI21X1TS U723 ( .A0(n289), .A1(n1323), .B0(n1324), .Y(n288) );
XNOR2X1TS U724 ( .A(n2055), .B(n182), .Y(n1093) );
XNOR2X2TS U725 ( .A(n2055), .B(n350), .Y(n1120) );
INVX4TS U726 ( .A(n656), .Y(n161) );
OAI21X2TS U727 ( .A0(n1734), .A1(n1736), .B0(n1735), .Y(n304) );
AND2X2TS U728 ( .A(n788), .B(n74), .Y(n787) );
XNOR2X1TS U729 ( .A(n190), .B(Data_B_i[22]), .Y(n74) );
XOR2X1TS U730 ( .A(n746), .B(n1195), .Y(n745) );
OAI22X2TS U731 ( .A0(n63), .A1(n1197), .B0(n173), .B1(n1137), .Y(n746) );
INVX4TS U732 ( .A(n962), .Y(n969) );
NAND2X2TS U733 ( .A(n2097), .B(n2223), .Y(n2166) );
XNOR2X2TS U734 ( .A(n1591), .B(n2070), .Y(n1087) );
XNOR2X2TS U735 ( .A(n1804), .B(n632), .Y(n1831) );
NAND2X1TS U736 ( .A(n1076), .B(n1075), .Y(n1079) );
XOR2X4TS U737 ( .A(n1337), .B(n1338), .Y(n244) );
OAI22X4TS U738 ( .A0(n1267), .A1(n496), .B0(n1268), .B1(n497), .Y(n611) );
INVX2TS U739 ( .A(n331), .Y(n75) );
XNOR2X1TS U740 ( .A(n57), .B(Data_A_i[7]), .Y(n1883) );
OAI22X2TS U741 ( .A0(n1102), .A1(n529), .B0(n2018), .B1(n1181), .Y(n1180) );
NAND2X4TS U742 ( .A(n910), .B(n908), .Y(n360) );
XOR2X2TS U743 ( .A(n1708), .B(n563), .Y(n1717) );
OAI21X2TS U744 ( .A0(n1168), .A1(n1169), .B0(n1167), .Y(n485) );
XOR2X1TS U745 ( .A(n2465), .B(n696), .Y(n2471) );
OAI21X2TS U746 ( .A0(n2960), .A1(n2956), .B0(n2957), .Y(n2410) );
OAI22X1TS U747 ( .A0(n1908), .A1(n202), .B0(n2001), .B1(n162), .Y(n1998) );
CLKINVX1TS U748 ( .A(n963), .Y(n965) );
ADDFHX4TS U749 ( .A(n1702), .B(n1701), .CI(n1700), .CO(n1758), .S(n1766) );
INVX4TS U750 ( .A(n421), .Y(n169) );
OAI21X2TS U751 ( .A0(n1854), .A1(n1853), .B0(n1852), .Y(n283) );
OAI22X4TS U752 ( .A0(n2059), .A1(n1257), .B0(n771), .B1(n1254), .Y(n568) );
NAND2BX2TS U753 ( .AN(n1744), .B(n471), .Y(n2497) );
OAI22X2TS U754 ( .A0(n1092), .A1(n192), .B0(n1123), .B1(n185), .Y(n1114) );
NAND2X1TS U755 ( .A(n76), .B(n77), .Y(n78) );
NAND2X2TS U756 ( .A(n78), .B(n385), .Y(n1295) );
CLKINVX1TS U757 ( .A(n1311), .Y(n76) );
XOR2X2TS U758 ( .A(n1965), .B(n61), .Y(n1022) );
NAND2X4TS U759 ( .A(n461), .B(n1872), .Y(n205) );
OAI22X2TS U760 ( .A0(n1473), .A1(n571), .B0(n1472), .B1(n187), .Y(n1500) );
XNOR2X1TS U761 ( .A(n1874), .B(n350), .Y(n1472) );
OAI21X2TS U762 ( .A0(n1525), .A1(n1526), .B0(n1524), .Y(n630) );
OAI2BB1X2TS U763 ( .A0N(n366), .A1N(n365), .B0(n1530), .Y(n364) );
NAND2X2TS U764 ( .A(n466), .B(n468), .Y(n465) );
INVX4TS U765 ( .A(n1926), .Y(n783) );
XOR2X4TS U766 ( .A(n79), .B(n1348), .Y(n1701) );
XOR2X4TS U767 ( .A(n2202), .B(n2201), .Y(n79) );
NAND2X2TS U768 ( .A(n374), .B(n64), .Y(n1014) );
NAND3X8TS U769 ( .A(n437), .B(n891), .C(n1038), .Y(n419) );
XNOR2X4TS U770 ( .A(n596), .B(n177), .Y(n449) );
XOR2X1TS U771 ( .A(n1709), .B(n1710), .Y(n563) );
OAI2BB1X2TS U772 ( .A0N(n1710), .A1N(n1709), .B0(n560), .Y(n1722) );
INVX12TS U773 ( .A(n130), .Y(n131) );
OAI21X4TS U774 ( .A0(n1246), .A1(n1245), .B0(n1244), .Y(n735) );
XNOR2X2TS U775 ( .A(n520), .B(Data_A_i[21]), .Y(n1103) );
OAI22X2TS U776 ( .A0(n174), .A1(n1887), .B0(n1942), .B1(n429), .Y(n1938) );
OAI2BB1X2TS U777 ( .A0N(Data_B_i[18]), .A1N(Data_B_i[6]), .B0(n430), .Y(
n1029) );
XNOR2X4TS U778 ( .A(n274), .B(n1566), .Y(n273) );
XNOR2X2TS U779 ( .A(n1965), .B(n177), .Y(n1151) );
XNOR2X1TS U780 ( .A(n621), .B(n1030), .Y(n1448) );
AO21X1TS U781 ( .A0(n1964), .A1(n185), .B0(n718), .Y(n2016) );
NOR2X1TS U782 ( .A(n785), .B(n1033), .Y(n1035) );
XOR2X4TS U783 ( .A(n230), .B(n1161), .Y(n1303) );
NOR2X4TS U784 ( .A(Data_A_i[18]), .B(Data_A_i[6]), .Y(n1039) );
INVX2TS U785 ( .A(n1039), .Y(n1041) );
XOR2X4TS U786 ( .A(n718), .B(n1583), .Y(n1447) );
INVX6TS U787 ( .A(n346), .Y(n919) );
OAI22X2TS U788 ( .A0(n200), .A1(n1233), .B0(n784), .B1(n1793), .Y(n1794) );
XNOR2X2TS U789 ( .A(n136), .B(Data_A_i[22]), .Y(n1793) );
OAI21X1TS U790 ( .A0(n558), .A1(n1913), .B0(n1912), .Y(n557) );
XOR2X4TS U791 ( .A(n80), .B(n1714), .Y(n483) );
XOR2X4TS U792 ( .A(n1716), .B(n1715), .Y(n80) );
INVX12TS U793 ( .A(Data_B_i[7]), .Y(n429) );
OAI21X4TS U794 ( .A0(n2554), .A1(n2568), .B0(n2555), .Y(n409) );
INVX2TS U795 ( .A(n2554), .Y(n2556) );
NOR2X8TS U796 ( .A(n1904), .B(n1905), .Y(n2554) );
NAND2X4TS U797 ( .A(n936), .B(n937), .Y(n1074) );
XOR2X4TS U798 ( .A(n1437), .B(n1438), .Y(n432) );
OAI22X1TS U799 ( .A0(n1873), .A1(n1482), .B0(n1382), .B1(n383), .Y(n1415) );
XNOR2X2TS U800 ( .A(n1583), .B(n56), .Y(n1482) );
XNOR2X4TS U801 ( .A(n574), .B(n1234), .Y(n1226) );
OAI22X2TS U802 ( .A0(n261), .A1(n1104), .B0(n575), .B1(n1183), .Y(n1179) );
CLKINVX1TS U803 ( .A(n2906), .Y(n2908) );
NAND2X2TS U804 ( .A(n2460), .B(n2459), .Y(n2996) );
OAI21X2TS U805 ( .A0(n2909), .A1(n2906), .B0(n2907), .Y(n2915) );
XOR2X4TS U806 ( .A(n1162), .B(n1163), .Y(n230) );
OAI21X2TS U807 ( .A0(n1223), .A1(n840), .B0(n1222), .Y(n872) );
XOR2X4TS U808 ( .A(n1226), .B(n1227), .Y(n677) );
XOR2X4TS U809 ( .A(n1303), .B(n1304), .Y(n81) );
XOR2X4TS U810 ( .A(n1302), .B(n81), .Y(n1305) );
NAND2X2TS U811 ( .A(n1303), .B(n1302), .Y(n82) );
NAND2X2TS U812 ( .A(n1304), .B(n1302), .Y(n83) );
NAND2X1TS U813 ( .A(n1304), .B(n1303), .Y(n84) );
NAND3X4TS U814 ( .A(n83), .B(n82), .C(n84), .Y(n1838) );
NAND2X2TS U815 ( .A(n59), .B(n2596), .Y(n87) );
OAI2BB1X2TS U816 ( .A0N(n1276), .A1N(n1275), .B0(n634), .Y(n1304) );
OAI21X1TS U817 ( .A0(n2082), .A1(n2083), .B0(n2081), .Y(n870) );
NAND2X1TS U818 ( .A(Data_A_i[8]), .B(Data_A_i[20]), .Y(n88) );
OAI22X2TS U819 ( .A0(n1810), .A1(n180), .B0(n1875), .B1(n209), .Y(n1896) );
OAI21X2TS U820 ( .A0(n1478), .A1(n1479), .B0(n1477), .Y(n847) );
XOR2X2TS U821 ( .A(n1466), .B(n1468), .Y(n673) );
OAI22X2TS U822 ( .A0(n194), .A1(n1393), .B0(n1369), .B1(n974), .Y(n1392) );
INVX4TS U823 ( .A(n193), .Y(n194) );
OAI21X1TS U824 ( .A0(n1936), .A1(n1937), .B0(n1938), .Y(n588) );
ADDFHX2TS U825 ( .A(n2089), .B(n2088), .CI(n2087), .CO(n2100), .S(n2050) );
ADDFHX2TS U826 ( .A(n2054), .B(n2053), .CI(n2052), .CO(n2102), .S(n2087) );
OAI22X2TS U827 ( .A0(n913), .A1(n1578), .B0(n1607), .B1(n1542), .Y(n1586) );
NAND2X4TS U828 ( .A(n276), .B(n275), .Y(n274) );
NAND2X2TS U829 ( .A(n270), .B(n268), .Y(n2301) );
OAI2BB1X4TS U830 ( .A0N(n1245), .A1N(n1246), .B0(n735), .Y(n318) );
XNOR2X4TS U831 ( .A(n520), .B(Data_A_i[22]), .Y(n1182) );
OAI22X2TS U832 ( .A0(n1090), .A1(n209), .B0(n2186), .B1(n1089), .Y(n1252) );
XNOR2X2TS U833 ( .A(n1616), .B(n2070), .Y(n1090) );
XOR2X4TS U834 ( .A(n787), .B(n971), .Y(n786) );
OAI22X2TS U835 ( .A0(n1929), .A1(n497), .B0(n1981), .B1(n496), .Y(n1977) );
OAI22X2TS U836 ( .A0(n1516), .A1(n1873), .B0(n1517), .B1(n383), .Y(n1575) );
XNOR2X4TS U837 ( .A(n380), .B(n1667), .Y(n1676) );
XOR2X4TS U838 ( .A(n467), .B(n455), .Y(n454) );
BUFX8TS U839 ( .A(n2111), .Y(n261) );
OAI2BB1X4TS U840 ( .A0N(n1074), .A1N(n1073), .B0(n662), .Y(n1248) );
OAI21X4TS U841 ( .A0(n1074), .A1(n1073), .B0(n1072), .Y(n662) );
NAND2X2TS U842 ( .A(n1029), .B(n1034), .Y(n1009) );
CLKINVX1TS U843 ( .A(n2799), .Y(n2792) );
OAI2BB1X4TS U844 ( .A0N(n1845), .A1N(n1844), .B0(n851), .Y(n1905) );
OAI2BB1X4TS U845 ( .A0N(n1850), .A1N(n1851), .B0(n743), .Y(n742) );
NAND2X6TS U846 ( .A(n862), .B(n860), .Y(n861) );
XOR2X2TS U847 ( .A(n596), .B(n1147), .Y(n1446) );
NOR2X4TS U848 ( .A(Data_A_i[19]), .B(Data_A_i[7]), .Y(n1018) );
OAI2BB1X4TS U849 ( .A0N(n1988), .A1N(n1986), .B0(n239), .Y(n2342) );
OAI22X2TS U850 ( .A0(n1342), .A1(n571), .B0(n1120), .B1(n187), .Y(n1323) );
XOR2X2TS U851 ( .A(n1985), .B(n1984), .Y(n765) );
OAI21X2TS U852 ( .A0(n1844), .A1(n1845), .B0(n852), .Y(n851) );
OAI2BB1X2TS U853 ( .A0N(n2048), .A1N(n2047), .B0(n653), .Y(n2049) );
OAI21X1TS U854 ( .A0(n2048), .A1(n2047), .B0(n2046), .Y(n653) );
OAI22X2TS U855 ( .A0(n200), .A1(n1793), .B0(n784), .B1(n1868), .Y(n1863) );
INVX6TS U856 ( .A(n783), .Y(n784) );
OAI22X2TS U857 ( .A0(n1450), .A1(n205), .B0(n1449), .B1(n156), .Y(n1704) );
OAI2BB1X2TS U858 ( .A0N(n1763), .A1N(n1762), .B0(n213), .Y(n1769) );
OAI2BB1X2TS U859 ( .A0N(n2037), .A1N(n2036), .B0(n878), .Y(n2704) );
NAND2X2TS U860 ( .A(n2090), .B(n2091), .Y(n2544) );
INVX4TS U861 ( .A(n2300), .Y(n1572) );
NOR2X2TS U862 ( .A(n2471), .B(n2470), .Y(n2820) );
NOR2X2TS U863 ( .A(n2767), .B(n2777), .Y(n2726) );
OAI21X1TS U864 ( .A0(n2605), .A1(n2604), .B0(n2603), .Y(n2633) );
NOR2X1TS U865 ( .A(n2597), .B(n2596), .Y(n2605) );
OAI21X2TS U866 ( .A0(n2544), .A1(n2534), .B0(n2535), .Y(n712) );
NAND2X1TS U867 ( .A(n495), .B(n2092), .Y(n2535) );
NOR2X2TS U868 ( .A(n2495), .B(n2494), .Y(n2865) );
OAI2BB1X2TS U869 ( .A0N(n1757), .A1N(n1756), .B0(n433), .Y(n1762) );
OAI21X1TS U870 ( .A0(n1757), .A1(n1756), .B0(n434), .Y(n433) );
ADDFHX2TS U871 ( .A(n1722), .B(n1721), .CI(n1720), .CO(n1760), .S(n1756) );
NOR2X2TS U872 ( .A(n2997), .B(n2999), .Y(n808) );
NOR2X4TS U873 ( .A(n2462), .B(n2461), .Y(n2999) );
AOI21X2TS U874 ( .A0(n2329), .A1(n2431), .B0(n2328), .Y(n722) );
OAI21X1TS U875 ( .A0(n2438), .A1(n2432), .B0(n2439), .Y(n2328) );
OAI21X1TS U876 ( .A0(n1191), .A1(n1190), .B0(n1189), .Y(n597) );
NAND2BX2TS U877 ( .AN(n354), .B(n1250), .Y(n352) );
CLKINVX1TS U878 ( .A(n1724), .Y(n217) );
OAI21XLTS U879 ( .A0(n1968), .A1(n1967), .B0(n550), .Y(n548) );
XOR2X4TS U880 ( .A(n1166), .B(n1164), .Y(n90) );
XOR2X4TS U881 ( .A(n1165), .B(n90), .Y(n1246) );
NAND2X1TS U882 ( .A(n1166), .B(n1165), .Y(n91) );
NAND2X1TS U883 ( .A(n1164), .B(n1165), .Y(n92) );
NAND2X1TS U884 ( .A(n1164), .B(n1166), .Y(n93) );
NAND3X2TS U885 ( .A(n92), .B(n91), .C(n93), .Y(n1833) );
OAI22X2TS U886 ( .A0(n1964), .A1(n1462), .B0(n1447), .B1(n1963), .Y(n1438)
);
OAI2BB1X4TS U887 ( .A0N(n1733), .A1N(n436), .B0(n435), .Y(n434) );
INVX2TS U888 ( .A(n94), .Y(sgf_result_o[37]) );
BUFX8TS U889 ( .A(n511), .Y(n375) );
NOR2X1TS U890 ( .A(n2566), .B(n1773), .Y(n2553) );
NAND2X2TS U891 ( .A(n2523), .B(n2522), .Y(n2879) );
AOI21X4TS U892 ( .A0(n486), .A1(n2782), .B0(n2778), .Y(n3021) );
AOI21X2TS U893 ( .A0(n129), .A1(n2732), .B0(n2731), .Y(n695) );
XOR2X4TS U894 ( .A(n796), .B(n52), .Y(n795) );
XOR2X4TS U895 ( .A(n2049), .B(n2051), .Y(n770) );
AOI21X2TS U896 ( .A0(n861), .A1(n2099), .B0(n2098), .Y(n2137) );
NAND2X6TS U897 ( .A(n845), .B(n678), .Y(n394) );
BUFX6TS U898 ( .A(n511), .Y(n129) );
AOI21X2TS U899 ( .A0(n129), .A1(n809), .B0(n767), .Y(n766) );
XOR2X4TS U900 ( .A(n487), .B(n2777), .Y(n486) );
INVX2TS U901 ( .A(n98), .Y(sgf_result_o[40]) );
INVX2TS U902 ( .A(n100), .Y(sgf_result_o[43]) );
XNOR2X2TS U903 ( .A(n2071), .B(n1620), .Y(n1119) );
OAI2BB1X4TS U904 ( .A0N(Data_B_i[22]), .A1N(Data_B_i[10]), .B0(n422), .Y(
n966) );
OAI21X4TS U905 ( .A0(Data_B_i[10]), .A1(Data_B_i[22]), .B0(Data_B_i[9]), .Y(
n422) );
NOR2X4TS U906 ( .A(n1902), .B(n1901), .Y(n2269) );
OAI21X1TS U907 ( .A0(n1275), .A1(n1276), .B0(n1274), .Y(n634) );
OAI21X4TS U908 ( .A0(n2980), .A1(n2977), .B0(n2978), .Y(n2988) );
NOR2BX2TS U909 ( .AN(n733), .B(n2298), .Y(n2909) );
OAI22X2TS U910 ( .A0(n1562), .A1(n1545), .B0(n1580), .B1(n1544), .Y(n1581)
);
OAI22X4TS U911 ( .A0(n497), .A1(n1981), .B0(n496), .B1(n2017), .Y(n2022) );
OAI2BB1X1TS U912 ( .A0N(n1854), .A1N(n1853), .B0(n283), .Y(n1954) );
OAI22X2TS U913 ( .A0(n609), .A1(n1970), .B0(n573), .B1(n1945), .Y(n550) );
OAI22X2TS U914 ( .A0(n573), .A1(n1970), .B0(n609), .B1(n2024), .Y(n2030) );
ADDFHX2TS U915 ( .A(n2042), .B(n2041), .CI(n2040), .CO(n2053), .S(n2010) );
XNOR2X2TS U916 ( .A(n1323), .B(n1324), .Y(n260) );
OAI22X2TS U917 ( .A0(n1335), .A1(n168), .B0(n184), .B1(n1119), .Y(n1324) );
NAND2X2TS U918 ( .A(n2094), .B(n2093), .Y(n2231) );
NOR2X4TS U919 ( .A(n2093), .B(n2094), .Y(n2222) );
XOR2X1TS U920 ( .A(n177), .B(n2244), .Y(n1924) );
AOI21X4TS U921 ( .A0(n500), .A1(n2532), .B0(n2531), .Y(n2759) );
OAI21X2TS U922 ( .A0(n2844), .A1(n2841), .B0(n2845), .Y(n2531) );
OAI2BB1X2TS U923 ( .A0N(n143), .A1N(n2287), .B0(n2354), .Y(n2292) );
OAI21X2TS U924 ( .A0(n373), .A1(n1959), .B0(n1958), .Y(n371) );
OAI21X4TS U925 ( .A0(n2762), .A1(n2805), .B0(n2763), .Y(n2799) );
OAI21X2TS U926 ( .A0(n915), .A1(n75), .B0(n951), .Y(n329) );
OAI22X2TS U927 ( .A0(n1093), .A1(n205), .B0(n156), .B1(n1243), .Y(n406) );
XNOR2X4TS U928 ( .A(n426), .B(n1758), .Y(n1761) );
ADDFHX2TS U929 ( .A(n2086), .B(n2085), .CI(n2084), .CO(n2103), .S(n2054) );
NOR2X1TS U930 ( .A(n2769), .B(n2656), .Y(n2657) );
OAI21X1TS U931 ( .A0(n2656), .A1(n2774), .B0(n2655), .Y(n444) );
OAI2BB1X2TS U932 ( .A0N(n1752), .A1N(n1751), .B0(n582), .Y(n1901) );
NAND2X4TS U933 ( .A(n857), .B(n58), .Y(n1773) );
OAI22X2TS U934 ( .A0(n958), .A1(n571), .B0(n1145), .B1(n187), .Y(n1046) );
OAI21X4TS U935 ( .A0(n2756), .A1(n2750), .B0(n2751), .Y(n2589) );
NOR2X6TS U936 ( .A(n459), .B(n2588), .Y(n2750) );
OAI22X2TS U937 ( .A0(n573), .A1(n1889), .B0(n609), .B1(n1945), .Y(n1936) );
BUFX8TS U938 ( .A(n2025), .Y(n609) );
INVX4TS U939 ( .A(n1695), .Y(n714) );
OAI21X2TS U940 ( .A0(n1480), .A1(n977), .B0(n457), .Y(n1413) );
NAND2X2TS U941 ( .A(n458), .B(n975), .Y(n457) );
AOI21X2TS U942 ( .A0(n2743), .A1(n129), .B0(n2742), .Y(n796) );
OAI21X2TS U943 ( .A0(n2212), .A1(n2231), .B0(n2224), .Y(n877) );
AOI21X2TS U944 ( .A0(n861), .A1(n881), .B0(n879), .Y(n2214) );
NAND2X4TS U945 ( .A(n2754), .B(n2590), .Y(n155) );
OAI2BB1X2TS U946 ( .A0N(n1843), .A1N(n1842), .B0(n1841), .Y(n1903) );
CLKINVX1TS U947 ( .A(n2754), .Y(n2745) );
AOI21X2TS U948 ( .A0(n823), .A1(n2967), .B0(n119), .Y(n3011) );
XOR2X2TS U949 ( .A(n824), .B(n889), .Y(n823) );
AOI21X1TS U950 ( .A0(n129), .A1(n2651), .B0(n2650), .Y(n824) );
XOR2X4TS U951 ( .A(n770), .B(n2050), .Y(n2093) );
AOI21X1TS U952 ( .A0(n375), .A1(n2670), .B0(n2669), .Y(n826) );
NAND2BX1TS U953 ( .AN(n759), .B(n1975), .Y(n757) );
NOR2BX1TS U954 ( .AN(n759), .B(n1975), .Y(n758) );
NOR2X4TS U955 ( .A(n440), .B(n2585), .Y(n2787) );
NOR2BX2TS U956 ( .AN(n354), .B(n1250), .Y(n353) );
XOR2X4TS U957 ( .A(n583), .B(n1750), .Y(n1770) );
XOR2X4TS U958 ( .A(n1751), .B(n1752), .Y(n583) );
XNOR2X2TS U959 ( .A(n621), .B(n2070), .Y(n1149) );
OAI22X2TS U960 ( .A0(n1149), .A1(n2185), .B0(n2186), .B1(n1126), .Y(n1146)
);
OAI22X1TS U961 ( .A0(n1448), .A1(n1963), .B0(n1447), .B1(n1964), .Y(n1705)
);
NOR2X2TS U962 ( .A(n2321), .B(n2322), .Y(n2385) );
NOR2XLTS U963 ( .A(n2262), .B(n2259), .Y(n2264) );
NAND2X6TS U964 ( .A(n730), .B(n729), .Y(n2436) );
NAND2X2TS U965 ( .A(n2652), .B(n2653), .Y(n2656) );
NAND2BX2TS U966 ( .AN(n2059), .B(n856), .Y(n855) );
XNOR2X2TS U967 ( .A(n1922), .B(n772), .Y(n1150) );
INVX2TS U968 ( .A(n290), .Y(n643) );
NAND2X4TS U969 ( .A(Data_A_i[16]), .B(Data_A_i[4]), .Y(n1023) );
OAI22X1TS U970 ( .A0(n1966), .A1(n2243), .B0(n2039), .B1(n176), .Y(n2015) );
INVX2TS U971 ( .A(n2606), .Y(n1777) );
INVX2TS U972 ( .A(n2336), .Y(n1995) );
XNOR2X1TS U973 ( .A(n1807), .B(n350), .Y(n1473) );
XNOR2X1TS U974 ( .A(n621), .B(n350), .Y(n1436) );
NOR2X1TS U975 ( .A(n204), .B(n1201), .Y(n1220) );
INVX2TS U976 ( .A(Data_A_i[3]), .Y(n1201) );
INVX2TS U977 ( .A(n1191), .Y(n224) );
ADDFHX2TS U978 ( .A(n2124), .B(n2123), .CI(n2122), .CO(n2174), .S(n2120) );
INVX2TS U979 ( .A(n2349), .Y(n2123) );
INVX2TS U980 ( .A(n2304), .Y(n1536) );
INVX2TS U981 ( .A(n1444), .Y(n754) );
NOR2XLTS U982 ( .A(n2162), .B(n2163), .Y(n2259) );
INVX1TS U983 ( .A(n2538), .Y(n2550) );
NAND2X1TS U984 ( .A(n2284), .B(n2285), .Y(n337) );
INVX2TS U985 ( .A(n2436), .Y(n564) );
NOR2X2TS U986 ( .A(n2744), .B(n2621), .Y(n2654) );
OAI21X2TS U987 ( .A0(n2635), .A1(n2636), .B0(n2634), .Y(n2719) );
NAND2X2TS U988 ( .A(n884), .B(n2815), .Y(n2458) );
AOI21X2TS U989 ( .A0(n2947), .A1(n2951), .B0(n2315), .Y(n731) );
NOR2XLTS U990 ( .A(n2295), .B(n2294), .Y(n2893) );
XNOR2X1TS U991 ( .A(n2125), .B(n177), .Y(n1855) );
INVX4TS U992 ( .A(n1591), .Y(n717) );
XNOR2X2TS U993 ( .A(n1807), .B(n772), .Y(n1124) );
XOR2X1TS U994 ( .A(n2125), .B(n1147), .Y(n1335) );
NOR2X4TS U995 ( .A(n645), .B(n1012), .Y(n774) );
INVX2TS U996 ( .A(n2244), .Y(n2071) );
ADDFHX2TS U997 ( .A(n1831), .B(n1829), .CI(n1830), .CO(n1876), .S(n1834) );
INVX2TS U998 ( .A(n1805), .Y(n633) );
INVX4TS U999 ( .A(n386), .Y(n156) );
CLKINVX3TS U1000 ( .A(n2155), .Y(n1468) );
NOR2X2TS U1001 ( .A(n209), .B(n1086), .Y(n1381) );
XNOR2X1TS U1002 ( .A(n1922), .B(n182), .Y(n1311) );
INVX4TS U1003 ( .A(n2317), .Y(n1708) );
INVX2TS U1004 ( .A(n2202), .Y(n319) );
NAND2X1TS U1005 ( .A(n264), .B(n62), .Y(n263) );
NAND2X4TS U1006 ( .A(Data_B_i[16]), .B(Data_B_i[15]), .Y(n400) );
OAI22X1TS U1007 ( .A0(n1432), .A1(n1103), .B0(n1800), .B1(n1182), .Y(n637)
);
NAND2BX1TS U1008 ( .AN(Data_A_i[12]), .B(n581), .Y(n920) );
OAI22X1TS U1009 ( .A0(n1565), .A1(n1327), .B0(n207), .B1(n929), .Y(n1325) );
INVX2TS U1010 ( .A(n2333), .Y(n558) );
NAND2BX1TS U1011 ( .AN(n61), .B(n384), .Y(n1911) );
OAI22X1TS U1012 ( .A0(n1875), .A1(n180), .B0(n1907), .B1(n2185), .Y(n1909)
);
CLKINVX3TS U1013 ( .A(n2334), .Y(n1915) );
XNOR2X2TS U1014 ( .A(n133), .B(Data_A_i[18]), .Y(n1393) );
INVX6TS U1015 ( .A(n785), .Y(n1926) );
ADDFHX2TS U1016 ( .A(n1575), .B(n1576), .CI(n1574), .CO(n1667), .S(n1664) );
INVX2TS U1017 ( .A(n2302), .Y(n1574) );
OAI2BB1X2TS U1018 ( .A0N(n1552), .A1N(n503), .B0(n502), .Y(n1585) );
NAND2BXLTS U1019 ( .AN(n1144), .B(n1221), .Y(n286) );
XOR2X1TS U1020 ( .A(n1147), .B(n1583), .Y(n1592) );
OAI2BB1X2TS U1021 ( .A0N(n684), .A1N(n683), .B0(n1826), .Y(n682) );
NAND2X1TS U1022 ( .A(n935), .B(n934), .Y(n936) );
OAI22X1TS U1023 ( .A0(n1565), .A1(n928), .B0(n207), .B1(n1082), .Y(n1066) );
NAND2X6TS U1024 ( .A(n2175), .B(n166), .Y(n2243) );
INVX2TS U1025 ( .A(n1850), .Y(n231) );
INVX2TS U1026 ( .A(n1851), .Y(n219) );
XOR2X2TS U1027 ( .A(n255), .B(n1899), .Y(n1846) );
OAI21X2TS U1028 ( .A0(n250), .A1(n1777), .B0(n1776), .Y(n249) );
INVX2TS U1029 ( .A(n456), .Y(n455) );
OAI2BB1X1TS U1030 ( .A0N(n2305), .A1N(n2148), .B0(n1667), .Y(n395) );
ADDFHX2TS U1031 ( .A(n1507), .B(n1506), .CI(n1505), .CO(n1501), .S(n1674) );
OAI22X1TS U1032 ( .A0(n1481), .A1(n205), .B0(n383), .B1(n1482), .Y(n1507) );
XOR2X1TS U1033 ( .A(n1220), .B(n1221), .Y(n265) );
XOR2X1TS U1034 ( .A(n302), .B(n1147), .Y(n1617) );
OAI22X1TS U1035 ( .A0(n1592), .A1(n1641), .B0(n168), .B1(n1617), .Y(n312) );
XOR2X2TS U1036 ( .A(n504), .B(n1552), .Y(n1601) );
OAI22X1TS U1037 ( .A0(n1565), .A1(n1564), .B0(n208), .B1(n1563), .Y(n2140)
);
CLKAND2X2TS U1038 ( .A(n2478), .B(n2483), .Y(n2486) );
INVX2TS U1039 ( .A(n2034), .Y(n839) );
XOR2X1TS U1040 ( .A(n311), .B(n1627), .Y(n1647) );
XOR2X1TS U1041 ( .A(n1628), .B(n312), .Y(n311) );
XNOR2X2TS U1042 ( .A(n66), .B(Data_A_i[5]), .Y(n1288) );
NOR2XLTS U1043 ( .A(n2266), .B(n2267), .Y(n2602) );
OAI2BB1X1TS U1044 ( .A0N(n1858), .A1N(n865), .B0(n864), .Y(n1951) );
OAI22X1TS U1045 ( .A0(n261), .A1(n2020), .B0(n2066), .B1(n575), .Y(n2067) );
AOI21X1TS U1046 ( .A0(n2487), .A1(n2449), .B0(n2380), .Y(n2384) );
INVX1TS U1047 ( .A(n2448), .Y(n2380) );
INVX2TS U1048 ( .A(n1727), .Y(n2314) );
NOR2XLTS U1049 ( .A(n2611), .B(n2626), .Y(n2615) );
NOR2XLTS U1050 ( .A(n2617), .B(n2616), .Y(n2630) );
INVX1TS U1051 ( .A(n2646), .Y(n2647) );
NAND2BX1TS U1052 ( .AN(n2045), .B(n2674), .Y(n2683) );
NOR2XLTS U1053 ( .A(n2681), .B(n2671), .Y(n2673) );
NOR2XLTS U1054 ( .A(n2713), .B(n2715), .Y(n2718) );
INVX2TS U1055 ( .A(n2774), .Y(n2742) );
NOR2X4TS U1056 ( .A(n2578), .B(n2577), .Y(n2762) );
OR2X1TS U1057 ( .A(n2518), .B(n2517), .Y(n2520) );
XOR2X1TS U1058 ( .A(n2502), .B(n2501), .Y(n2505) );
NOR2X2TS U1059 ( .A(n805), .B(n2472), .Y(n2856) );
NAND2X1TS U1060 ( .A(n2389), .B(n2388), .Y(n2390) );
INVX1TS U1061 ( .A(n2392), .Y(n2394) );
NOR2X2TS U1062 ( .A(n2418), .B(n2417), .Y(n2977) );
NAND2X1TS U1063 ( .A(n2398), .B(n2397), .Y(n2399) );
INVX2TS U1064 ( .A(n510), .Y(n2401) );
NAND2X1TS U1065 ( .A(n271), .B(n272), .Y(n270) );
NOR2XLTS U1066 ( .A(n2299), .B(n2300), .Y(n2906) );
OAI21XLTS U1067 ( .A0(n2998), .A1(n2997), .B0(n2996), .Y(n3003) );
OAI21X2TS U1068 ( .A0(n388), .A1(n2820), .B0(n2821), .Y(n2826) );
AOI21X2TS U1069 ( .A0(n2851), .A1(n808), .B0(n807), .Y(n388) );
INVX2TS U1070 ( .A(n2521), .Y(n476) );
INVX2TS U1071 ( .A(n2977), .Y(n2979) );
INVX1TS U1072 ( .A(n2926), .Y(n2934) );
NAND2X4TS U1073 ( .A(n625), .B(n670), .Y(n2880) );
CLKINVX3TS U1074 ( .A(n2523), .Y(n625) );
XNOR2X1TS U1075 ( .A(n2410), .B(n2409), .Y(n2964) );
NOR2BX2TS U1076 ( .AN(n1411), .B(n2312), .Y(n2293) );
NAND2BX1TS U1077 ( .AN(n2302), .B(n732), .Y(n2914) );
NAND2BX1TS U1078 ( .AN(n2296), .B(n734), .Y(n2901) );
INVX2TS U1079 ( .A(n88), .Y(n892) );
OAI22X1TS U1080 ( .A0(n1923), .A1(n2243), .B0(n176), .B1(n1966), .Y(n1976)
);
OAI2BB1X1TS U1081 ( .A0N(n1806), .A1N(n1805), .B0(n631), .Y(n1879) );
OAI21XLTS U1082 ( .A0(n1805), .A1(n1806), .B0(n1804), .Y(n631) );
INVX2TS U1083 ( .A(n902), .Y(n897) );
XOR2X2TS U1084 ( .A(n429), .B(Data_B_i[19]), .Y(n1034) );
XOR2X1TS U1085 ( .A(Data_B_i[6]), .B(Data_B_i[18]), .Y(n1033) );
NOR2X4TS U1086 ( .A(Data_A_i[14]), .B(Data_A_i[2]), .Y(n967) );
NAND2BX1TS U1087 ( .AN(n210), .B(n623), .Y(n1088) );
INVX2TS U1088 ( .A(n383), .Y(n386) );
NAND2BX1TS U1089 ( .AN(n161), .B(n856), .Y(n854) );
XOR2X2TS U1090 ( .A(n1148), .B(n1147), .Y(n431) );
XNOR2X2TS U1091 ( .A(n1583), .B(n2070), .Y(n1126) );
OAI22X2TS U1092 ( .A0(n1087), .A1(n2185), .B0(n2186), .B1(n1090), .Y(n1117)
);
NOR2X2TS U1093 ( .A(n65), .B(n279), .Y(n896) );
XNOR2X1TS U1094 ( .A(n166), .B(Data_A_i[16]), .Y(n1183) );
INVX2TS U1095 ( .A(n1007), .Y(n374) );
NOR2X4TS U1096 ( .A(Data_A_i[15]), .B(Data_A_i[3]), .Y(n963) );
NAND2X4TS U1097 ( .A(Data_A_i[14]), .B(Data_A_i[2]), .Y(n968) );
NOR2X2TS U1098 ( .A(n967), .B(n963), .Y(n412) );
NOR2BX1TS U1099 ( .AN(n331), .B(n914), .Y(n330) );
INVX2TS U1100 ( .A(n948), .Y(n914) );
XNOR2X1TS U1101 ( .A(Data_B_i[13]), .B(Data_A_i[22]), .Y(n924) );
XNOR2X1TS U1102 ( .A(Data_B_i[13]), .B(Data_A_i[21]), .Y(n1261) );
OAI22X1TS U1103 ( .A0(n1924), .A1(n192), .B0(n185), .B1(n718), .Y(n1975) );
XNOR2X1TS U1104 ( .A(n1922), .B(n623), .Y(n1875) );
NAND2X1TS U1105 ( .A(n1873), .B(n383), .Y(n384) );
NAND2BXLTS U1106 ( .AN(n1879), .B(n1919), .Y(n699) );
INVX2TS U1107 ( .A(n2637), .Y(n254) );
XOR2X1TS U1108 ( .A(n2244), .B(n182), .Y(n1809) );
XOR2X1TS U1109 ( .A(n2125), .B(n61), .Y(n1243) );
ADDFHX2TS U1110 ( .A(n1160), .B(n1159), .CI(n1158), .CO(n1829), .S(n1164) );
OAI21X2TS U1111 ( .A0(n1150), .A1(n162), .B0(n855), .Y(n1159) );
OAI22X1TS U1112 ( .A0(n449), .A1(n185), .B0(n192), .B1(n1151), .Y(n1158) );
OAI2BB1X1TS U1113 ( .A0N(n1148), .A1N(n1147), .B0(n646), .Y(n1155) );
XNOR2X2TS U1114 ( .A(n2071), .B(n350), .Y(n1145) );
INVX2TS U1115 ( .A(n1446), .Y(n458) );
XNOR2X1TS U1116 ( .A(n1807), .B(n182), .Y(n1450) );
XOR2X1TS U1117 ( .A(n1030), .B(n717), .Y(n1462) );
BUFX3TS U1118 ( .A(n152), .Y(n350) );
INVX2TS U1119 ( .A(n1037), .Y(n1015) );
XNOR2X1TS U1120 ( .A(n189), .B(Data_A_i[10]), .Y(n1945) );
NAND2X1TS U1121 ( .A(n387), .B(n386), .Y(n385) );
INVX2TS U1122 ( .A(n1022), .Y(n387) );
XNOR2X1TS U1123 ( .A(n617), .B(n616), .Y(n1300) );
INVX2TS U1124 ( .A(n2322), .Y(n1301) );
OAI22X1TS U1125 ( .A0(n1445), .A1(n168), .B0(n1335), .B1(n1641), .Y(n1724)
);
OAI2BB1X2TS U1126 ( .A0N(n562), .A1N(n561), .B0(n1708), .Y(n560) );
INVX2TS U1127 ( .A(n2201), .Y(n320) );
INVX4TS U1128 ( .A(n1588), .Y(n151) );
XNOR2X1TS U1129 ( .A(n66), .B(Data_A_i[9]), .Y(n1137) );
XNOR2X1TS U1130 ( .A(n132), .B(Data_A_i[10]), .Y(n1817) );
XOR2X1TS U1131 ( .A(n1076), .B(n1077), .Y(n934) );
XNOR2X1TS U1132 ( .A(n136), .B(Data_A_i[16]), .Y(n926) );
XNOR2X1TS U1133 ( .A(n166), .B(n619), .Y(n927) );
XNOR2X1TS U1134 ( .A(Data_B_i[13]), .B(Data_A_i[23]), .Y(n921) );
XNOR2X1TS U1135 ( .A(n624), .B(Data_A_i[22]), .Y(n1082) );
NAND2X1TS U1136 ( .A(n1926), .B(n918), .Y(n1927) );
XNOR2X1TS U1137 ( .A(n190), .B(Data_A_i[16]), .Y(n1070) );
XNOR2X1TS U1138 ( .A(n166), .B(Data_A_i[17]), .Y(n1238) );
XNOR2X1TS U1139 ( .A(n166), .B(Data_A_i[20]), .Y(n1925) );
INVX2TS U1140 ( .A(n1014), .Y(n1038) );
NOR2X1TS U1141 ( .A(Data_A_i[22]), .B(Data_A_i[10]), .Y(n947) );
NAND2X1TS U1142 ( .A(Data_A_i[22]), .B(Data_A_i[10]), .Y(n951) );
NAND2X1TS U1143 ( .A(Data_A_i[23]), .B(Data_A_i[11]), .Y(n950) );
NOR2XLTS U1144 ( .A(Data_A_i[23]), .B(Data_A_i[11]), .Y(n952) );
NAND2X1TS U1145 ( .A(Data_A_i[21]), .B(Data_A_i[9]), .Y(n903) );
INVX2TS U1146 ( .A(n2616), .Y(n250) );
XNOR2X2TS U1147 ( .A(n2637), .B(n1900), .Y(n255) );
ADDFHX2TS U1148 ( .A(n2075), .B(n2074), .CI(n2073), .CO(n2131), .S(n2088) );
XNOR2X1TS U1149 ( .A(Data_B_i[13]), .B(Data_A_i[20]), .Y(n1330) );
BUFX3TS U1150 ( .A(n1432), .Y(n201) );
OAI21X2TS U1151 ( .A0(n1162), .A1(n1163), .B0(n1161), .Y(n792) );
INVX2TS U1152 ( .A(n297), .Y(n295) );
OAI2BB1X2TS U1153 ( .A0N(n1415), .A1N(n545), .B0(n469), .Y(n468) );
NAND2BX1TS U1154 ( .AN(n2308), .B(n470), .Y(n469) );
NAND2BX1TS U1155 ( .AN(n1415), .B(n2151), .Y(n470) );
INVX2TS U1156 ( .A(n109), .Y(n1963) );
XNOR2X1TS U1157 ( .A(n302), .B(n56), .Y(n1481) );
XNOR2X1TS U1158 ( .A(n189), .B(Data_A_i[11]), .Y(n1970) );
CMPR22X2TS U1159 ( .A(n732), .B(n1570), .CO(n1662), .S(n1666) );
OAI22X1TS U1160 ( .A0(n1446), .A1(n977), .B0(n1445), .B1(n184), .Y(n1713) );
OAI2BB1X1TS U1161 ( .A0N(n568), .A1N(n1381), .B0(n567), .Y(n1345) );
INVX2TS U1162 ( .A(n665), .Y(n436) );
OAI22X1TS U1163 ( .A0(n174), .A1(n1139), .B0(n206), .B1(n1202), .Y(n1191) );
INVX2TS U1164 ( .A(n154), .Y(n358) );
INVX2TS U1165 ( .A(n151), .Y(n154) );
XNOR2X2TS U1166 ( .A(n302), .B(n153), .Y(n1578) );
INVX2TS U1167 ( .A(n2143), .Y(n1571) );
NOR2BX2TS U1168 ( .AN(n1003), .B(n983), .Y(n1063) );
NAND2X2TS U1169 ( .A(Data_B_i[0]), .B(Data_B_i[12]), .Y(n343) );
INVX2TS U1170 ( .A(n421), .Y(n188) );
XNOR2X2TS U1171 ( .A(n131), .B(Data_A_i[11]), .Y(n984) );
OAI22X1TS U1172 ( .A0(n2114), .A1(n1218), .B0(n181), .B1(n1821), .Y(n1814)
);
OAI2BB1X1TS U1173 ( .A0N(n263), .A1N(n1219), .B0(n262), .Y(n1813) );
OAI22X1TS U1174 ( .A0(n573), .A1(n1217), .B0(n609), .B1(n1822), .Y(n1815) );
NAND2X2TS U1175 ( .A(n931), .B(n930), .Y(n1075) );
OR2X2TS U1176 ( .A(n1432), .B(n941), .Y(n931) );
XNOR2X2TS U1177 ( .A(n636), .B(n1179), .Y(n1177) );
XNOR2X1TS U1178 ( .A(n1180), .B(n637), .Y(n636) );
INVX2TS U1179 ( .A(n1178), .Y(n841) );
OAI22X1TS U1180 ( .A0(n1927), .A1(n1105), .B0(n784), .B1(n1188), .Y(n1175)
);
XNOR2X1TS U1181 ( .A(n166), .B(Data_A_i[19]), .Y(n1862) );
XNOR2X1TS U1182 ( .A(n581), .B(Data_A_i[18]), .Y(n1798) );
XNOR2X1TS U1183 ( .A(n1236), .B(n1235), .Y(n574) );
OAI2BB1X1TS U1184 ( .A0N(n1180), .A1N(n637), .B0(n635), .Y(n1227) );
OAI21XLTS U1185 ( .A0(n1180), .A1(n637), .B0(n1179), .Y(n635) );
XNOR2X1TS U1186 ( .A(n166), .B(Data_A_i[21]), .Y(n1982) );
INVX2TS U1187 ( .A(Data_B_i[22]), .Y(n778) );
ADDFHX2TS U1188 ( .A(n2121), .B(n2120), .CI(n2119), .CO(n2193), .S(n2132) );
NOR2XLTS U1189 ( .A(n947), .B(n952), .Y(n955) );
OAI21XLTS U1190 ( .A0(n952), .A1(n951), .B0(n950), .Y(n953) );
OAI21X1TS U1191 ( .A0(n905), .A1(n904), .B0(n903), .Y(n954) );
ADDFHX2TS U1192 ( .A(n2129), .B(n2128), .CI(n2127), .CO(n2172), .S(n2104) );
XNOR2X1TS U1193 ( .A(n1260), .B(n1259), .Y(n639) );
OAI2BB1X2TS U1194 ( .A0N(n1334), .A1N(n1333), .B0(n667), .Y(n1337) );
OAI21X1TS U1195 ( .A0(n1333), .A1(n1334), .B0(n1332), .Y(n667) );
OAI2BB1X1TS U1196 ( .A0N(n1915), .A1N(n222), .B0(n221), .Y(n1960) );
OAI2BB1X2TS U1197 ( .A0N(n1906), .A1N(n742), .B0(n408), .Y(n2091) );
NAND2BXLTS U1198 ( .AN(Data_A_i[12]), .B(n520), .Y(n1431) );
NAND2BXLTS U1199 ( .AN(Data_A_i[12]), .B(Data_B_i[19]), .Y(n1370) );
NAND2X1TS U1200 ( .A(n1204), .B(n1203), .Y(n565) );
XNOR2X1TS U1201 ( .A(n919), .B(Data_A_i[16]), .Y(n1514) );
INVX2TS U1202 ( .A(n624), .Y(n1564) );
XNOR2X1TS U1203 ( .A(n188), .B(Data_A_i[11]), .Y(n2061) );
OAI2BB1X1TS U1204 ( .A0N(n1937), .A1N(n1936), .B0(n588), .Y(n1988) );
ADDFHX2TS U1205 ( .A(n1660), .B(n1659), .CI(n1658), .CO(n1682), .S(n1669) );
INVX2TS U1206 ( .A(n1194), .Y(n228) );
INVX2TS U1207 ( .A(n2138), .Y(n1606) );
INVX2TS U1208 ( .A(n2294), .Y(n1605) );
XNOR2X1TS U1209 ( .A(Data_B_i[1]), .B(Data_A_i[10]), .Y(n986) );
BUFX3TS U1210 ( .A(n981), .Y(n2113) );
INVX2TS U1211 ( .A(n922), .Y(n1579) );
XNOR2X1TS U1212 ( .A(Data_A_i[14]), .B(n919), .Y(n1559) );
INVX2TS U1213 ( .A(n1205), .Y(n323) );
INVX2TS U1214 ( .A(n1207), .Y(n328) );
INVX2TS U1215 ( .A(n189), .Y(n2024) );
ADDFHX2TS U1216 ( .A(n1979), .B(n1978), .CI(n1977), .CO(n2037), .S(n1983) );
OAI2BB1X2TS U1217 ( .A0N(n764), .A1N(n763), .B0(n1983), .Y(n762) );
INVX2TS U1218 ( .A(n660), .Y(n658) );
XOR2X2TS U1219 ( .A(n1939), .B(n1940), .Y(n532) );
OAI21X1TS U1220 ( .A0(n1871), .A1(n1870), .B0(n681), .Y(n680) );
OAI21XLTS U1221 ( .A0(n1858), .A1(n865), .B0(n1857), .Y(n864) );
NAND2X1TS U1222 ( .A(n1230), .B(n1229), .Y(n873) );
OAI22X1TS U1223 ( .A0(n497), .A1(n1869), .B0(n2018), .B1(n1929), .Y(n1930)
);
BUFX4TS U1224 ( .A(Data_B_i[23]), .Y(n166) );
NOR2XLTS U1225 ( .A(n220), .B(n1980), .Y(n2069) );
XNOR2X1TS U1226 ( .A(n166), .B(Data_A_i[22]), .Y(n2020) );
NOR2X1TS U1227 ( .A(n2232), .B(n2222), .Y(n2234) );
OAI2BB1X2TS U1228 ( .A0N(n2051), .A1N(n2050), .B0(n769), .Y(n2096) );
OAI21X1TS U1229 ( .A0(n2050), .A1(n2051), .B0(n2049), .Y(n769) );
NOR2X4TS U1230 ( .A(n2095), .B(n2096), .Y(n2212) );
OAI2BB1X2TS U1231 ( .A0N(n1479), .A1N(n1478), .B0(n847), .Y(n2155) );
AOI21X1TS U1232 ( .A0(n2538), .A1(n2154), .B0(n2153), .Y(n2209) );
NOR2XLTS U1233 ( .A(n2539), .B(n2546), .Y(n2154) );
INVX4TS U1234 ( .A(n1773), .Y(n2565) );
OR2X1TS U1235 ( .A(n2145), .B(n2144), .Y(n2572) );
ADDFHX2TS U1236 ( .A(n2080), .B(n2079), .CI(n2078), .CO(n2350), .S(n2343) );
AO21X1TS U1237 ( .A0(n573), .A1(n609), .B0(n2024), .Y(n2080) );
OAI21X2TS U1238 ( .A0(n1307), .A1(n1306), .B0(n1305), .Y(n686) );
AND2X4TS U1239 ( .A(n1554), .B(n1555), .Y(n2142) );
INVX2TS U1240 ( .A(n1307), .Y(n688) );
NOR2X2TS U1241 ( .A(n2513), .B(n2507), .Y(n1772) );
BUFX3TS U1242 ( .A(Data_A_i[12]), .Y(n619) );
NAND2X6TS U1243 ( .A(n919), .B(n1640), .Y(n1610) );
OAI2BB1X2TS U1244 ( .A0N(n1741), .A1N(n537), .B0(n536), .Y(n1746) );
OAI21X1TS U1245 ( .A0(n1679), .A1(n1680), .B0(n1678), .Y(n707) );
OAI2BB1X1TS U1246 ( .A0N(n1668), .A1N(n396), .B0(n395), .Y(n1673) );
OAI2BB1X2TS U1247 ( .A0N(n1782), .A1N(n1781), .B0(n750), .Y(n2332) );
OAI21X1TS U1248 ( .A0(n1781), .A1(n1782), .B0(n1780), .Y(n750) );
OAI2BB1X1TS U1249 ( .A0N(n515), .A1N(n514), .B0(n1624), .Y(n513) );
INVX2TS U1250 ( .A(n1625), .Y(n515) );
INVX2TS U1251 ( .A(n2887), .Y(n1637) );
NAND2X1TS U1252 ( .A(n1621), .B(n977), .Y(n1636) );
NAND2BXLTS U1253 ( .AN(n1642), .B(n1620), .Y(n1621) );
OAI22X1TS U1254 ( .A0(n173), .A1(n1359), .B0(n203), .B1(n1288), .Y(n1355) );
OAI22X2TS U1255 ( .A0(n2026), .A1(n1287), .B0(n2025), .B1(n1286), .Y(n1356)
);
XNOR2X1TS U1256 ( .A(n65), .B(Data_A_i[5]), .Y(n1386) );
XNOR2X1TS U1257 ( .A(Data_A_i[3]), .B(Data_B_i[5]), .Y(n1387) );
NAND2X1TS U1258 ( .A(n1141), .B(n985), .Y(n198) );
INVX4TS U1259 ( .A(Data_B_i[5]), .Y(n163) );
XOR2X1TS U1260 ( .A(n802), .B(Data_A_i[4]), .Y(n1433) );
XNOR2X1TS U1261 ( .A(n131), .B(Data_A_i[5]), .Y(n1426) );
INVX2TS U1262 ( .A(n66), .Y(n1823) );
NOR2X4TS U1263 ( .A(n1672), .B(n1671), .Y(n2376) );
OR2X1TS U1264 ( .A(n2335), .B(n2336), .Y(n2373) );
NOR2XLTS U1265 ( .A(n2379), .B(n2369), .Y(n2371) );
NAND2BX2TS U1266 ( .AN(n1991), .B(n831), .Y(n829) );
INVX2TS U1267 ( .A(n1990), .Y(n831) );
XNOR2X1TS U1268 ( .A(n166), .B(Data_A_i[23]), .Y(n2066) );
INVX4TS U1269 ( .A(Data_B_i[23]), .Y(n705) );
OAI21X1TS U1270 ( .A0(n2551), .A1(n2566), .B0(n2568), .Y(n2552) );
AOI21X1TS U1271 ( .A0(n2572), .A1(n2573), .B0(n2146), .Y(n2562) );
NOR2XLTS U1272 ( .A(n2148), .B(n2147), .Y(n2559) );
CLKBUFX2TS U1273 ( .A(n712), .Y(n640) );
INVX2TS U1274 ( .A(n2223), .Y(n882) );
NAND2X1TS U1275 ( .A(n880), .B(n2231), .Y(n879) );
NAND2BX1TS U1276 ( .AN(n2222), .B(n712), .Y(n880) );
INVX2TS U1277 ( .A(n2544), .Y(n2533) );
NAND2X2TS U1278 ( .A(n1694), .B(n1695), .Y(n2354) );
INVX2TS U1279 ( .A(n2280), .Y(n2270) );
NOR2X1TS U1280 ( .A(n2142), .B(n2143), .Y(n2275) );
NAND2X1TS U1281 ( .A(n60), .B(n338), .Y(n2284) );
NOR2XLTS U1282 ( .A(n2357), .B(n2358), .Y(n2361) );
INVX2TS U1283 ( .A(n1652), .Y(n347) );
CLKINVX3TS U1284 ( .A(n1653), .Y(n348) );
NAND2X1TS U1285 ( .A(n1648), .B(n1647), .Y(n2422) );
INVX2TS U1286 ( .A(n1647), .Y(n547) );
INVX2TS U1287 ( .A(n2397), .Y(n2386) );
NOR2X1TS U1288 ( .A(n1646), .B(n1645), .Y(n2392) );
NAND2BX1TS U1289 ( .AN(n507), .B(n1646), .Y(n2393) );
OAI22X2TS U1290 ( .A0(n172), .A1(n1288), .B0(n203), .B1(n999), .Y(n1314) );
NOR2X4TS U1291 ( .A(n1770), .B(n1769), .Y(n2507) );
NAND2X2TS U1292 ( .A(n1770), .B(n1769), .Y(n2508) );
NOR2XLTS U1293 ( .A(n2139), .B(n2138), .Y(n2509) );
NOR2X1TS U1294 ( .A(n2327), .B(n149), .Y(n2438) );
NOR2XLTS U1295 ( .A(n2430), .B(n2433), .Y(n2437) );
INVX2TS U1296 ( .A(n2385), .Y(n2398) );
NAND2BX1TS U1297 ( .AN(n107), .B(n1643), .Y(n2400) );
NAND2BXLTS U1298 ( .AN(Data_A_i[0]), .B(n132), .Y(n1361) );
INVX2TS U1299 ( .A(n63), .Y(n276) );
OAI22X2TS U1300 ( .A0(n160), .A1(n1543), .B0(n1433), .B1(n195), .Y(n1566) );
OAI22X2TS U1301 ( .A0(n128), .A1(n1434), .B0(n198), .B1(n1544), .Y(n272) );
XNOR2X1TS U1302 ( .A(n65), .B(Data_A_i[3]), .Y(n1484) );
XNOR2X2TS U1303 ( .A(n131), .B(Data_A_i[2]), .Y(n1557) );
XNOR2X1TS U1304 ( .A(Data_B_i[3]), .B(Data_A_i[1]), .Y(n1544) );
INVX6TS U1305 ( .A(Data_B_i[3]), .Y(n1561) );
BUFX6TS U1306 ( .A(n1141), .Y(n1580) );
INVX2TS U1307 ( .A(n2767), .Y(n2770) );
INVX2TS U1308 ( .A(n2226), .Y(n2197) );
OAI21XLTS U1309 ( .A0(n2200), .A1(n2259), .B0(n2261), .Y(n2205) );
NAND2X1TS U1310 ( .A(n866), .B(n2544), .Y(n2545) );
NAND2X1TS U1311 ( .A(n2419), .B(n2432), .Y(n2420) );
INVX2TS U1312 ( .A(n802), .Y(n186) );
XOR2X1TS U1313 ( .A(n2707), .B(n2706), .Y(n2708) );
NAND2X1TS U1314 ( .A(n2598), .B(n2603), .Y(n2599) );
NAND2X1TS U1315 ( .A(n2608), .B(n2629), .Y(n2609) );
OAI21XLTS U1316 ( .A0(n2774), .A1(n2649), .B0(n2648), .Y(n2650) );
INVX2TS U1317 ( .A(n2750), .Y(n2752) );
INVX2TS U1318 ( .A(n2503), .Y(n2832) );
NAND2X1TS U1319 ( .A(n2505), .B(n2504), .Y(n2831) );
XOR2X1TS U1320 ( .A(n443), .B(n888), .Y(n442) );
AOI21X1TS U1321 ( .A0(n375), .A1(n2657), .B0(n444), .Y(n443) );
AOI21X1TS U1322 ( .A0(n797), .A1(n478), .B0(n122), .Y(n3019) );
XOR2X1TS U1323 ( .A(n798), .B(n2758), .Y(n797) );
AOI22X1TS U1324 ( .A0(n748), .A1(n747), .B0(n3007), .B1(sgf_result_o[30]),
.Y(n3020) );
XOR2X1TS U1325 ( .A(n2766), .B(n2765), .Y(n748) );
NAND2X1TS U1326 ( .A(n2763), .B(n2764), .Y(n2765) );
AOI2BB2X1TS U1327 ( .B0(n479), .B1(n478), .A0N(load_b_i), .A1N(n127), .Y(
n3023) );
AOI21X1TS U1328 ( .A0(n723), .A1(n478), .B0(n113), .Y(n3025) );
XOR2X1TS U1329 ( .A(n724), .B(n2804), .Y(n723) );
NAND2X1TS U1330 ( .A(n2803), .B(n2802), .Y(n2804) );
OAI2BB1X1TS U1331 ( .A0N(sgf_result_o[29]), .A1N(n3007), .B0(n2810), .Y(
n2811) );
NAND2BX1TS U1332 ( .AN(n3005), .B(n2809), .Y(n2810) );
NAND2X1TS U1333 ( .A(n2846), .B(n2845), .Y(n2847) );
XOR2XLTS U1334 ( .A(n2843), .B(n2838), .Y(n2840) );
NAND2X1TS U1335 ( .A(n2837), .B(n2841), .Y(n2838) );
NAND2BX1TS U1336 ( .AN(n2876), .B(n2877), .Y(n2873) );
NAND2BX1TS U1337 ( .AN(n719), .B(n2827), .Y(n2828) );
XOR2XLTS U1338 ( .A(n2981), .B(n2980), .Y(n2984) );
XOR2XLTS U1339 ( .A(n2960), .B(n2959), .Y(n2962) );
XOR2XLTS U1340 ( .A(n2923), .B(n2922), .Y(n2925) );
XOR2XLTS U1341 ( .A(n2897), .B(n2896), .Y(n2899) );
CLKAND2X2TS U1342 ( .A(n2965), .B(n2966), .Y(n2968) );
CLKAND2X2TS U1343 ( .A(n2889), .B(n2896), .Y(n2890) );
OR2X1TS U1344 ( .A(n2888), .B(n2887), .Y(n2889) );
INVX2TS U1345 ( .A(n2162), .Y(n1725) );
ADDFHX2TS U1346 ( .A(n1615), .B(n1614), .CI(n1613), .CO(n1611), .S(n1631) );
OAI22X1TS U1347 ( .A0(n175), .A1(n429), .B0(n1942), .B1(n1361), .Y(n1383) );
OAI2BB1X2TS U1348 ( .A0N(n1064), .A1N(n1063), .B0(n238), .Y(n1130) );
INVX6TS U1349 ( .A(n751), .Y(n2185) );
INVX3TS U1350 ( .A(n751), .Y(n209) );
OAI21X2TS U1351 ( .A0(n1132), .A1(n1131), .B0(n1130), .Y(n693) );
CLKBUFX2TS U1352 ( .A(n2607), .Y(n102) );
INVX4TS U1353 ( .A(n2158), .Y(n1707) );
XNOR2X4TS U1354 ( .A(n1357), .B(n1356), .Y(n233) );
INVX6TS U1355 ( .A(n313), .Y(n1583) );
XOR2X4TS U1356 ( .A(n103), .B(n1524), .Y(n1695) );
XOR2X4TS U1357 ( .A(n1525), .B(n1526), .Y(n103) );
OAI2BB1X2TS U1358 ( .A0N(n754), .A1N(n755), .B0(n1442), .Y(n753) );
OAI2BB1X4TS U1359 ( .A0N(n259), .A1N(n665), .B0(n1732), .Y(n435) );
OAI21X2TS U1360 ( .A0(n1110), .A1(n59), .B0(n2596), .Y(n266) );
INVX8TS U1361 ( .A(Data_B_i[13]), .Y(n346) );
OAI22X4TS U1362 ( .A0(n1242), .A1(n209), .B0(n1149), .B1(n2186), .Y(n1160)
);
OAI21X1TS U1363 ( .A0(n746), .A1(n111), .B0(n1195), .Y(n744) );
ADDFHX2TS U1364 ( .A(n1957), .B(n1956), .CI(n1955), .CO(n2003), .S(n1916) );
OAI21X1TS U1365 ( .A0(n1752), .A1(n1751), .B0(n1750), .Y(n582) );
AO21X1TS U1366 ( .A0(n1562), .A1(n1141), .B0(n1561), .Y(n1214) );
OAI21X1TS U1367 ( .A0(n1147), .A1(n1148), .B0(n1146), .Y(n646) );
OAI22X4TS U1368 ( .A0(n1360), .A1(n160), .B0(n1318), .B1(n196), .Y(n1402) );
NOR2X6TS U1369 ( .A(n2795), .B(n2801), .Y(n368) );
XOR2X2TS U1370 ( .A(n480), .B(n2790), .Y(n479) );
AND2X4TS U1371 ( .A(n1653), .B(n1652), .Y(n1654) );
NAND3X6TS U1372 ( .A(n394), .B(n849), .C(n2565), .Y(n860) );
OAI2BB1X4TS U1373 ( .A0N(n1423), .A1N(n1422), .B0(n462), .Y(n2151) );
NOR2BX1TS U1374 ( .AN(n619), .B(n2110), .Y(n1265) );
OAI22X2TS U1375 ( .A0(n2111), .A1(n89), .B0(n920), .B1(n2110), .Y(n945) );
XOR2X2TS U1376 ( .A(n1033), .B(n448), .Y(n447) );
XOR2X4TS U1377 ( .A(n883), .B(Data_B_i[21]), .Y(n1013) );
INVX2TS U1378 ( .A(n1030), .Y(n718) );
INVX2TS U1379 ( .A(Data_A_i[12]), .Y(n157) );
NAND2X4TS U1380 ( .A(n980), .B(n981), .Y(n164) );
OR2X1TS U1381 ( .A(n2155), .B(n2156), .Y(n105) );
INVX2TS U1382 ( .A(n1619), .Y(n159) );
OA22X2TS U1383 ( .A0(n1638), .A1(n1641), .B0(n210), .B1(n168), .Y(n107) );
OAI21X2TS U1384 ( .A0(n720), .A1(n2858), .B0(n2859), .Y(n803) );
INVX2TS U1385 ( .A(n2475), .Y(n2496) );
INVX4TS U1386 ( .A(n159), .Y(n160) );
OAI22X1TS U1387 ( .A0(n2026), .A1(n1136), .B0(n2025), .B1(n1196), .Y(n111)
);
INVX2TS U1388 ( .A(Data_A_i[0]), .Y(n541) );
BUFX3TS U1389 ( .A(n1800), .Y(n242) );
NAND2X6TS U1390 ( .A(Data_A_i[0]), .B(Data_A_i[12]), .Y(n961) );
INVX4TS U1391 ( .A(Data_B_i[19]), .Y(n1867) );
INVX2TS U1392 ( .A(n1177), .Y(n842) );
INVX2TS U1393 ( .A(n1580), .Y(n178) );
NOR2X4TS U1394 ( .A(Data_A_i[16]), .B(Data_A_i[4]), .Y(n1007) );
INVX2TS U1395 ( .A(n947), .Y(n331) );
INVX2TS U1396 ( .A(n2151), .Y(n545) );
INVX2TS U1397 ( .A(n2148), .Y(n1668) );
AND2X2TS U1398 ( .A(n2929), .B(sgf_result_o[44]), .Y(n112) );
AND2X2TS U1399 ( .A(n2929), .B(sgf_result_o[46]), .Y(n116) );
AND2X2TS U1400 ( .A(n2929), .B(sgf_result_o[47]), .Y(n118) );
AND2X2TS U1401 ( .A(n2982), .B(sgf_result_o[40]), .Y(n119) );
AND2X2TS U1402 ( .A(n2929), .B(sgf_result_o[43]), .Y(n120) );
AND2X2TS U1403 ( .A(n2982), .B(sgf_result_o[39]), .Y(n123) );
AND2X2TS U1404 ( .A(n2982), .B(sgf_result_o[38]), .Y(n124) );
AND2X2TS U1405 ( .A(n2982), .B(sgf_result_o[41]), .Y(n125) );
AND2X2TS U1406 ( .A(n2982), .B(sgf_result_o[36]), .Y(n126) );
INVX2TS U1407 ( .A(n3005), .Y(n747) );
NOR2X2TS U1408 ( .A(n2318), .B(n2317), .Y(n2956) );
INVX2TS U1409 ( .A(n1730), .Y(n2318) );
AOI21X1TS U1410 ( .A0(n799), .A1(n478), .B0(n126), .Y(n3018) );
XOR2X2TS U1411 ( .A(n512), .B(n2753), .Y(n799) );
OAI22X2TS U1412 ( .A0(n200), .A1(n1396), .B0(n784), .B1(n1395), .Y(n1456) );
OAI22X2TS U1413 ( .A0(n200), .A1(n1081), .B0(n784), .B1(n1105), .Y(n1101) );
OAI21X1TS U1414 ( .A0(n2679), .A1(n2774), .B0(n2678), .Y(n767) );
INVX2TS U1415 ( .A(n178), .Y(n128) );
INVX2TS U1416 ( .A(n541), .Y(n171) );
INVX12TS U1417 ( .A(Data_B_i[1]), .Y(n130) );
INVX2TS U1418 ( .A(n346), .Y(n133) );
INVX2TS U1419 ( .A(Data_B_i[21]), .Y(n134) );
INVX2TS U1420 ( .A(n137), .Y(sgf_result_o[42]) );
INVX2TS U1421 ( .A(n155), .Y(n2743) );
INVX2TS U1422 ( .A(n139), .Y(sgf_result_o[45]) );
AOI21X1TS U1423 ( .A0(n2851), .A1(n808), .B0(n807), .Y(n141) );
NAND2X2TS U1424 ( .A(n2473), .B(n806), .Y(n2859) );
XOR2X4TS U1425 ( .A(n665), .B(n1733), .Y(n794) );
XOR2X4TS U1426 ( .A(n142), .B(n1222), .Y(n2607) );
XOR2X4TS U1427 ( .A(n840), .B(n1223), .Y(n142) );
INVX2TS U1428 ( .A(n1113), .Y(n592) );
NOR2XLTS U1429 ( .A(n2791), .B(n2801), .Y(n2794) );
OAI21XLTS U1430 ( .A0(n2792), .A1(n2801), .B0(n2802), .Y(n2793) );
OAI21X1TS U1431 ( .A0(n1541), .A1(n1540), .B0(n1539), .Y(n569) );
XOR2X1TS U1432 ( .A(n570), .B(n1539), .Y(n2145) );
AOI21X4TS U1433 ( .A0(n2813), .A1(n2815), .B0(n2456), .Y(n2457) );
XOR2X4TS U1434 ( .A(n2487), .B(n2450), .Y(n749) );
INVX6TS U1435 ( .A(n978), .Y(n1942) );
XNOR2X2TS U1436 ( .A(n861), .B(n2545), .Y(n2580) );
AOI21X2TS U1437 ( .A0(n861), .A1(n2223), .B0(n640), .Y(n2208) );
NOR2X4TS U1438 ( .A(n2587), .B(n2586), .Y(n2755) );
OAI22X2TS U1439 ( .A0(n1610), .A1(n1369), .B0(n1330), .B1(n1640), .Y(n1453)
);
OAI22X2TS U1440 ( .A0(n959), .A1(n156), .B0(n205), .B1(n1022), .Y(n1250) );
OAI2BB1X2TS U1441 ( .A0N(n306), .A1N(n305), .B0(n628), .Y(n627) );
NAND2X1TS U1442 ( .A(n714), .B(n713), .Y(n143) );
INVX2TS U1443 ( .A(n652), .Y(n650) );
OAI22X1TS U1444 ( .A0(n1432), .A1(n1182), .B0(n1800), .B1(n1232), .Y(n1235)
);
OAI22X4TS U1445 ( .A0(n595), .A1(n1394), .B0(n207), .B1(n1367), .Y(n1460) );
OR2X2TS U1446 ( .A(n1693), .B(n1692), .Y(n144) );
OAI2BB1X1TS U1447 ( .A0N(n1690), .A1N(n1691), .B0(n603), .Y(n1692) );
INVX4TS U1448 ( .A(n2617), .Y(n1775) );
XNOR2X2TS U1449 ( .A(n1624), .B(n516), .Y(n1648) );
OAI2BB1X1TS U1450 ( .A0N(n1299), .A1N(n1300), .B0(n517), .Y(n1308) );
NAND2X2TS U1451 ( .A(n1926), .B(n918), .Y(n199) );
OAI22X2TS U1452 ( .A0(n959), .A1(n205), .B0(n1093), .B1(n156), .Y(n1045) );
XOR2X4TS U1453 ( .A(n772), .B(n717), .Y(n1254) );
XOR2X2TS U1454 ( .A(n1725), .B(n1724), .Y(n666) );
OR2X4TS U1455 ( .A(n1666), .B(n1665), .Y(n145) );
NAND2X4TS U1456 ( .A(n145), .B(n1664), .Y(n382) );
AOI21X1TS U1457 ( .A0(n2826), .A1(n804), .B0(n803), .Y(n146) );
INVX2TS U1458 ( .A(n1249), .Y(n552) );
OAI21XLTS U1459 ( .A0(n2843), .A1(n2842), .B0(n2841), .Y(n2848) );
NAND2X4TS U1460 ( .A(n1607), .B(n912), .Y(n913) );
XOR2X2TS U1461 ( .A(n1117), .B(n1118), .Y(n644) );
OAI22X2TS U1462 ( .A0(n496), .A1(n943), .B0(n529), .B1(n944), .Y(n1259) );
OAI22X2TS U1463 ( .A0(n529), .A1(n1070), .B0(n2018), .B1(n1102), .Y(n1109)
);
ADDFHX4TS U1464 ( .A(n1573), .B(n1572), .CI(n1571), .CO(n1665), .S(n1599) );
ADDFHX2TS U1465 ( .A(n1962), .B(n1961), .CI(n1960), .CO(n2006), .S(n1959) );
OAI2BB1X1TS U1466 ( .A0N(n1913), .A1N(n558), .B0(n557), .Y(n1961) );
OAI21X2TS U1467 ( .A0(n1326), .A1(n708), .B0(n1325), .Y(n491) );
OAI22X2TS U1468 ( .A0(n201), .A1(n1269), .B0(n242), .B1(n942), .Y(n1326) );
XNOR2X4TS U1469 ( .A(n324), .B(n326), .Y(n147) );
OAI21X2TS U1470 ( .A0(n1534), .A1(n587), .B0(n1533), .Y(n585) );
OAI2BB1X4TS U1471 ( .A0N(n1174), .A1N(n1175), .B0(n246), .Y(n1223) );
OAI22X2TS U1472 ( .A0(n194), .A1(n1514), .B0(n1430), .B1(n974), .Y(n1492) );
OAI21X2TS U1473 ( .A0(n1122), .A1(n1121), .B0(n737), .Y(n407) );
AOI21X2TS U1474 ( .A0(n957), .A1(n948), .B0(n954), .Y(n907) );
ADDFHX2TS U1475 ( .A(n1295), .B(n1296), .CI(n1294), .CO(n1297), .S(n1349) );
OAI22X2TS U1476 ( .A0(n1559), .A1(n1610), .B0(n1546), .B1(n1640), .Y(n1555)
);
NOR2X4TS U1477 ( .A(n2554), .B(n2566), .Y(n849) );
OAI22X2TS U1478 ( .A0(n1546), .A1(n1610), .B0(n1514), .B1(n1640), .Y(n1568)
);
XOR2X4TS U1479 ( .A(n148), .B(n1857), .Y(n1859) );
XOR2X4TS U1480 ( .A(n1858), .B(n865), .Y(n148) );
AOI21X4TS U1481 ( .A0(n2876), .A1(n2880), .B0(n2524), .Y(n2525) );
NAND2X2TS U1482 ( .A(n440), .B(n2585), .Y(n2789) );
ADDFHX2TS U1483 ( .A(n2117), .B(n2116), .CI(n2115), .CO(n2489), .S(n2349) );
AOI21X1TS U1484 ( .A0(n375), .A1(n2786), .B0(n2785), .Y(n480) );
AOI21X1TS U1485 ( .A0(n375), .A1(n2749), .B0(n2748), .Y(n512) );
AOI21X1TS U1486 ( .A0(n725), .A1(n478), .B0(n114), .Y(n3024) );
NAND2X2TS U1487 ( .A(n2877), .B(n2880), .Y(n2526) );
INVX2TS U1488 ( .A(n2407), .Y(n727) );
NOR2X4TS U1489 ( .A(n2319), .B(n618), .Y(n2406) );
NAND2X2TS U1490 ( .A(n368), .B(n2800), .Y(n377) );
NAND2X4TS U1491 ( .A(n2405), .B(n728), .Y(n730) );
NAND2X1TS U1492 ( .A(n2768), .B(n2695), .Y(n2679) );
AOI21X2TS U1493 ( .A0(n2228), .A1(n2229), .B0(n590), .Y(n2230) );
OAI21X4TS U1494 ( .A0(n2795), .A1(n2802), .B0(n2796), .Y(n2583) );
OAI22X2TS U1495 ( .A0(n2114), .A1(n997), .B0(n181), .B1(n1047), .Y(n1059) );
ADDFHX2TS U1496 ( .A(n1636), .B(n1637), .CI(n1635), .CO(n1629), .S(n1643) );
XNOR2X2TS U1497 ( .A(n2368), .B(n2367), .Y(n2462) );
NAND2X1TS U1498 ( .A(n2366), .B(n2365), .Y(n2368) );
OAI2BB1X1TS U1499 ( .A0N(n2104), .A1N(n2105), .B0(n868), .Y(n2171) );
ADDFHX4TS U1500 ( .A(n2132), .B(n2131), .CI(n2130), .CO(n2169), .S(n2101) );
ADDFHX2TS U1501 ( .A(n2077), .B(n2703), .CI(n2076), .CO(n2105), .S(n2073) );
XNOR2X1TS U1502 ( .A(n2498), .B(n2476), .Y(n2495) );
NAND2X4TS U1503 ( .A(n833), .B(n836), .Y(n834) );
XNOR2X1TS U1504 ( .A(n1874), .B(n56), .Y(n1449) );
XNOR2X1TS U1505 ( .A(n1114), .B(n1115), .Y(n617) );
OAI22X2TS U1506 ( .A0(n1124), .A1(n771), .B0(n1091), .B1(n202), .Y(n1115) );
INVX2TS U1507 ( .A(n1865), .Y(n1796) );
OAI22X2TS U1508 ( .A0(n1610), .A1(n1430), .B0(n1393), .B1(n974), .Y(n1494)
);
NOR2X1TS U1509 ( .A(n909), .B(n922), .Y(n911) );
NOR2X2TS U1510 ( .A(n1437), .B(n1438), .Y(n801) );
INVX2TS U1511 ( .A(n406), .Y(n301) );
NAND2X2TS U1512 ( .A(n2606), .B(n406), .Y(n403) );
NAND2X4TS U1513 ( .A(n453), .B(n452), .Y(n2768) );
INVX2TS U1514 ( .A(n621), .Y(n1808) );
XNOR2X1TS U1515 ( .A(n772), .B(n621), .Y(n1091) );
XNOR2X2TS U1516 ( .A(n621), .B(n56), .Y(n1382) );
OAI21X2TS U1517 ( .A0(n1993), .A1(n1994), .B0(n1992), .Y(n614) );
OAI21X2TS U1518 ( .A0(n1227), .A1(n1226), .B0(n676), .Y(n675) );
ADDFHX4TS U1519 ( .A(n1598), .B(n1597), .CI(n1596), .CO(n1659), .S(n1603) );
OAI22X2TS U1520 ( .A0(n1943), .A1(n1060), .B0(n1942), .B1(n1139), .Y(n1135)
);
OAI21X2TS U1521 ( .A0(n1755), .A1(n1754), .B0(n1753), .Y(n811) );
XNOR2X1TS U1522 ( .A(n1965), .B(n2070), .Y(n1907) );
XOR2X4TS U1523 ( .A(n150), .B(n1501), .Y(n1550) );
XOR2X4TS U1524 ( .A(n1502), .B(n1503), .Y(n150) );
OAI22X2TS U1525 ( .A0(n2114), .A1(n1821), .B0(n2113), .B1(n1883), .Y(n1882)
);
ADDFHX2TS U1526 ( .A(n1896), .B(n1898), .CI(n1897), .CO(n1912), .S(n1878) );
AOI21X1TS U1527 ( .A0(n2361), .A1(n2487), .B0(n2360), .Y(n2364) );
OAI21X2TS U1528 ( .A0(n2387), .A1(n2397), .B0(n2388), .Y(n2431) );
NAND2X2TS U1529 ( .A(n1141), .B(n985), .Y(n1562) );
OAI22X4TS U1530 ( .A0(n161), .A1(n1255), .B0(n2059), .B1(n2057), .Y(n1400)
);
OAI22X2TS U1531 ( .A0(n383), .A1(n1435), .B0(n1873), .B1(n61), .Y(n1570) );
NAND2XLTS U1532 ( .A(n2497), .B(n2475), .Y(n2476) );
ADDFHX2TS U1533 ( .A(n996), .B(n995), .CI(n994), .CO(n1056), .S(n1289) );
INVX4TS U1534 ( .A(n2607), .Y(n1203) );
XOR2X4TS U1535 ( .A(n1475), .B(n1476), .Y(n692) );
NAND2BX1TS U1536 ( .AN(n2507), .B(n2508), .Y(n427) );
OAI2BB1X2TS U1537 ( .A0N(n1323), .A1N(n289), .B0(n288), .Y(n1299) );
AOI21X1TS U1538 ( .A0(n2497), .A1(n2498), .B0(n2496), .Y(n2502) );
XNOR2X1TS U1539 ( .A(n596), .B(n623), .Y(n2002) );
XNOR2X1TS U1540 ( .A(n596), .B(n350), .Y(n1342) );
XNOR2X1TS U1541 ( .A(n596), .B(n182), .Y(n959) );
XNOR2X1TS U1542 ( .A(n596), .B(n2000), .Y(n1856) );
INVX2TS U1543 ( .A(n1415), .Y(n460) );
INVX2TS U1544 ( .A(n1732), .Y(n538) );
OAI21X1TS U1545 ( .A0(n1765), .A1(n1766), .B0(n1764), .Y(n321) );
NAND2X2TS U1546 ( .A(n1903), .B(n411), .Y(n2568) );
NOR2X4TS U1547 ( .A(n1903), .B(n411), .Y(n2566) );
OAI22X1TS U1548 ( .A0(n2111), .A1(n1183), .B0(n575), .B1(n1238), .Y(n1230)
);
OAI22X2TS U1549 ( .A0(n2110), .A1(n932), .B0(n2111), .B1(n927), .Y(n939) );
OAI22X2TS U1550 ( .A0(n2110), .A1(n1862), .B0(n2111), .B1(n1798), .Y(n865)
);
CLKINVX1TS U1551 ( .A(n1842), .Y(n1840) );
ADDFHX4TS U1552 ( .A(n1341), .B(n1340), .CI(n1339), .CO(n1354), .S(n1759) );
NAND2X4TS U1553 ( .A(n777), .B(n280), .Y(n2111) );
BUFX20TS U1554 ( .A(Data_B_i[21]), .Y(n190) );
OAI21X2TS U1555 ( .A0(n705), .A1(Data_B_i[21]), .B0(n778), .Y(n777) );
INVX2TS U1556 ( .A(n151), .Y(n153) );
NOR2X1TS U1557 ( .A(n2730), .B(n155), .Y(n2732) );
NOR2X1TS U1558 ( .A(n2679), .B(n155), .Y(n809) );
NOR2X1TS U1559 ( .A(n155), .B(n2773), .Y(n2776) );
NAND2X1TS U1560 ( .A(n2754), .B(n2590), .Y(n2769) );
NAND2X4TS U1561 ( .A(n461), .B(n1872), .Y(n1873) );
INVX2TS U1562 ( .A(n157), .Y(n158) );
INVX2TS U1563 ( .A(n2058), .Y(n656) );
INVX2TS U1564 ( .A(n656), .Y(n162) );
OAI22X1TS U1565 ( .A0(n1091), .A1(n162), .B0(n1251), .B1(n202), .Y(n1296) );
NAND2BX2TS U1566 ( .AN(n171), .B(n188), .Y(n982) );
XOR2X4TS U1567 ( .A(n169), .B(Data_B_i[10]), .Y(n980) );
NAND2X2TS U1568 ( .A(n980), .B(n981), .Y(n2114) );
CLKBUFX2TS U1569 ( .A(n2243), .Y(n165) );
NOR2XLTS U1570 ( .A(n165), .B(n2244), .Y(n2245) );
NAND2X4TS U1571 ( .A(Data_B_i[1]), .B(n1639), .Y(n1619) );
AOI21X1TS U1572 ( .A0(n2776), .A1(n511), .B0(n2775), .Y(n487) );
INVX2TS U1573 ( .A(n977), .Y(n167) );
INVX2TS U1574 ( .A(n167), .Y(n168) );
OAI22X2TS U1575 ( .A0(n199), .A1(n1868), .B0(n1867), .B1(n784), .Y(n1931) );
INVX2TS U1576 ( .A(n401), .Y(n170) );
NAND2X4TS U1577 ( .A(n988), .B(n987), .Y(n172) );
NAND2X4TS U1578 ( .A(n988), .B(n987), .Y(n173) );
OAI22X2TS U1579 ( .A0(n172), .A1(n1197), .B0(n203), .B1(n1212), .Y(n1215) );
NAND2X2TS U1580 ( .A(n988), .B(n987), .Y(n1825) );
OAI22X2TS U1581 ( .A0(n164), .A1(n989), .B0(n2113), .B1(n997), .Y(n996) );
NAND2X4TS U1582 ( .A(n1942), .B(n979), .Y(n174) );
NAND2X4TS U1583 ( .A(n1942), .B(n979), .Y(n175) );
OAI22X2TS U1584 ( .A0(n174), .A1(n1319), .B0(n206), .B1(n1285), .Y(n1357) );
OAI22X1TS U1585 ( .A0(n175), .A1(n1389), .B0(n206), .B1(n1319), .Y(n1401) );
OAI22X2TS U1586 ( .A0(n1943), .A1(n991), .B0(n206), .B1(n990), .Y(n995) );
OAI22X1TS U1587 ( .A0(n175), .A1(n1817), .B0(n1942), .B1(n1887), .Y(n1884)
);
NAND2X2TS U1588 ( .A(n1942), .B(n979), .Y(n1943) );
INVX2TS U1589 ( .A(n702), .Y(n176) );
OAI22X2TS U1590 ( .A0(n2243), .A1(n313), .B0(n1808), .B1(n2175), .Y(n1805)
);
NOR2X4TS U1591 ( .A(n429), .B(Data_B_i[9]), .Y(n835) );
NAND2X4TS U1592 ( .A(n429), .B(Data_B_i[9]), .Y(n833) );
INVX2TS U1593 ( .A(n2186), .Y(n179) );
OAI22X1TS U1594 ( .A0(n164), .A1(n2028), .B0(n181), .B1(n2061), .Y(n2062) );
OAI22X2TS U1595 ( .A0(n1138), .A1(n2114), .B0(n2113), .B1(n1198), .Y(n1195)
);
INVX2TS U1596 ( .A(n1641), .Y(n183) );
INVX2TS U1597 ( .A(n183), .Y(n184) );
INVX2TS U1598 ( .A(n109), .Y(n185) );
XNOR2X2TS U1599 ( .A(Data_B_i[1]), .B(Data_A_i[8]), .Y(n1318) );
OAI21X2TS U1600 ( .A0(Data_B_i[2]), .A1(Data_B_i[14]), .B0(n131), .Y(n379)
);
OAI22X2TS U1601 ( .A0(n1120), .A1(n571), .B0(n187), .B1(n958), .Y(n357) );
OAI21X1TS U1602 ( .A0(Data_B_i[6]), .A1(Data_B_i[18]), .B0(Data_B_i[5]), .Y(
n430) );
NOR2X1TS U1603 ( .A(Data_B_i[11]), .B(Data_B_i[23]), .Y(n703) );
XNOR2X1TS U1604 ( .A(Data_B_i[19]), .B(Data_A_i[18]), .Y(n1081) );
XNOR2X1TS U1605 ( .A(n619), .B(n136), .Y(n1396) );
OAI21XLTS U1606 ( .A0(n2773), .A1(n2774), .B0(n2772), .Y(n2775) );
INVX2TS U1607 ( .A(n1964), .Y(n674) );
OAI22X1TS U1608 ( .A0(n449), .A1(n192), .B0(n185), .B1(n1812), .Y(n1783) );
OAI22X1TS U1609 ( .A0(n1123), .A1(n192), .B0(n1151), .B1(n185), .Y(n1154) );
XNOR2X1TS U1610 ( .A(n1616), .B(n1620), .Y(n1638) );
INVX2TS U1611 ( .A(n1620), .Y(n1147) );
XNOR2X1TS U1612 ( .A(n2781), .B(n511), .Y(n2783) );
INVX2TS U1613 ( .A(n1610), .Y(n193) );
INVX2TS U1614 ( .A(Data_B_i[0]), .Y(n195) );
INVX2TS U1615 ( .A(Data_B_i[0]), .Y(n196) );
NAND2X2TS U1616 ( .A(n1141), .B(n985), .Y(n197) );
OAI22X1TS U1617 ( .A0(n197), .A1(n1061), .B0(n1580), .B1(n1142), .Y(n1134)
);
OAI22X1TS U1618 ( .A0(n1562), .A1(n992), .B0(n1580), .B1(n1061), .Y(n1048)
);
OAI22X1TS U1619 ( .A0(n1562), .A1(n1561), .B0(n1580), .B1(n1560), .Y(n2297)
);
OAI22X1TS U1620 ( .A0(n197), .A1(n1142), .B0(n1580), .B1(n1561), .Y(n1199)
);
OAI22X2TS U1621 ( .A0(n198), .A1(n1483), .B0(n1580), .B1(n1386), .Y(n1406)
);
NAND2X4TS U1622 ( .A(n1926), .B(n918), .Y(n200) );
OAI22X1TS U1623 ( .A0(n200), .A1(n1395), .B0(n1926), .B1(n1331), .Y(n1452)
);
OAI22X1TS U1624 ( .A0(n925), .A1(n200), .B0(n784), .B1(n1081), .Y(n1085) );
OAI22X1TS U1625 ( .A0(n199), .A1(n1867), .B0(n1370), .B1(n1926), .Y(n1391)
);
OAI22X2TS U1626 ( .A0(n200), .A1(n926), .B0(n784), .B1(n925), .Y(n940) );
OAI22X2TS U1627 ( .A0(n784), .A1(n926), .B0(n1927), .B1(n1266), .Y(n708) );
INVX4TS U1628 ( .A(Data_B_i[17]), .Y(n401) );
NAND2X2TS U1629 ( .A(n2058), .B(n773), .Y(n202) );
NAND2X4TS U1630 ( .A(n2058), .B(n773), .Y(n2059) );
INVX6TS U1631 ( .A(n988), .Y(n1824) );
INVX4TS U1632 ( .A(n1824), .Y(n203) );
AO21X2TS U1633 ( .A0(n261), .A1(n575), .B0(n705), .Y(n2181) );
NOR2X1TS U1634 ( .A(n705), .B(n1866), .Y(n1979) );
NOR2X1TS U1635 ( .A(n220), .B(n1069), .Y(n1241) );
NOR2X1TS U1636 ( .A(n220), .B(n1231), .Y(n1865) );
OAI22X1TS U1637 ( .A0(n164), .A1(n2061), .B0(n181), .B1(n204), .Y(n2116) );
OAI22X2TS U1638 ( .A0(n164), .A1(n204), .B0(n2113), .B1(n982), .Y(n1003) );
NOR2XLTS U1639 ( .A(n421), .B(n1969), .Y(n2064) );
OAI22X1TS U1640 ( .A0(n1449), .A1(n205), .B0(n156), .B1(n1311), .Y(n1709) );
OAI22X1TS U1641 ( .A0(n1481), .A1(n383), .B0(n1517), .B1(n1873), .Y(n1663)
);
INVX2TS U1642 ( .A(n978), .Y(n206) );
NOR2X2TS U1643 ( .A(n541), .B(n1942), .Y(n393) );
INVX2TS U1644 ( .A(n922), .Y(n207) );
INVX2TS U1645 ( .A(n922), .Y(n208) );
OAI22X1TS U1646 ( .A0(n595), .A1(n1547), .B0(n208), .B1(n1515), .Y(n1567) );
OAI22X1TS U1647 ( .A0(n1565), .A1(n1082), .B0(n208), .B1(n1107), .Y(n1100)
);
OAI22X2TS U1648 ( .A0(n2186), .A1(n420), .B0(n209), .B1(n1088), .Y(n1253) );
INVX2TS U1649 ( .A(n1086), .Y(n210) );
NAND2BX1TS U1650 ( .AN(n1642), .B(n152), .Y(n1556) );
INVX2TS U1651 ( .A(rst), .Y(n211) );
INVX2TS U1652 ( .A(rst), .Y(n212) );
XNOR2X4TS U1653 ( .A(n214), .B(n1761), .Y(n1768) );
XNOR2X4TS U1654 ( .A(n1762), .B(n1763), .Y(n214) );
XNOR2X4TS U1655 ( .A(n1861), .B(n1860), .Y(n648) );
OAI2BB1X1TS U1656 ( .A0N(n1357), .A1N(n1356), .B0(n232), .Y(n1320) );
XNOR2X4TS U1657 ( .A(n215), .B(n608), .Y(n1730) );
XOR2X4TS U1658 ( .A(n1343), .B(n1344), .Y(n215) );
XOR2X4TS U1659 ( .A(n233), .B(n1355), .Y(n216) );
OAI2BB1X2TS U1660 ( .A0N(n1366), .A1N(n611), .B0(n610), .Y(n1332) );
XOR2X4TS U1661 ( .A(n218), .B(n2101), .Y(n2095) );
XOR2X4TS U1662 ( .A(n2100), .B(n2102), .Y(n218) );
INVX2TS U1663 ( .A(n1733), .Y(n259) );
OAI2BB1X4TS U1664 ( .A0N(n231), .A1N(n219), .B0(n1849), .Y(n743) );
XOR2X4TS U1665 ( .A(n651), .B(n1877), .Y(n1851) );
INVX4TS U1666 ( .A(n2320), .Y(n1350) );
OAI2BB1X4TS U1667 ( .A0N(Data_B_i[21]), .A1N(n220), .B0(Data_B_i[22]), .Y(
n280) );
XOR2X4TS U1668 ( .A(n895), .B(n894), .Y(n596) );
XOR2X4TS U1669 ( .A(n1054), .B(n1056), .Y(n258) );
INVX4TS U1670 ( .A(n1747), .Y(n474) );
XOR2X1TS U1671 ( .A(n973), .B(n974), .Y(n976) );
XOR2X4TS U1672 ( .A(n802), .B(Data_B_i[13]), .Y(n973) );
XNOR2X4TS U1673 ( .A(n223), .B(n1914), .Y(n1952) );
XOR2X4TS U1674 ( .A(n1915), .B(n2660), .Y(n223) );
OAI22X2TS U1675 ( .A0(n1617), .A1(n1641), .B0(n1638), .B1(n168), .Y(n1630)
);
XNOR2X4TS U1676 ( .A(n1439), .B(n317), .Y(n1727) );
XOR2X4TS U1677 ( .A(n484), .B(n147), .Y(n1244) );
XOR2X4TS U1678 ( .A(n225), .B(n1737), .Y(n1740) );
XOR2X4TS U1679 ( .A(n1739), .B(n1738), .Y(n225) );
OAI2BB1X4TS U1680 ( .A0N(n1193), .A1N(n1194), .B0(n226), .Y(n1224) );
OAI21X2TS U1681 ( .A0(n1194), .A1(n1193), .B0(n1192), .Y(n226) );
XNOR2X4TS U1682 ( .A(n1192), .B(n227), .Y(n1170) );
XOR2X4TS U1683 ( .A(n1193), .B(n228), .Y(n227) );
AOI21X4TS U1684 ( .A0(n813), .A1(load_b_i), .B0(n116), .Y(n3015) );
OAI2BB1X2TS U1685 ( .A0N(n1290), .A1N(n1291), .B0(n606), .Y(n1292) );
NOR2BX2TS U1686 ( .AN(n210), .B(n1963), .Y(n1537) );
OAI21X1TS U1687 ( .A0(n1356), .A1(n1357), .B0(n1355), .Y(n232) );
XOR2X4TS U1688 ( .A(n1375), .B(n1376), .Y(n252) );
NAND2X4TS U1689 ( .A(n1176), .B(n791), .Y(n790) );
NAND2X1TS U1690 ( .A(n2299), .B(n2142), .Y(n503) );
OAI21X4TS U1691 ( .A0(n2812), .A1(n2458), .B0(n2457), .Y(n2851) );
AOI21X4TS U1692 ( .A0(n2988), .A1(n2986), .B0(n2428), .Y(n2812) );
ADDFHX2TS U1693 ( .A(n1412), .B(n1411), .CI(n1410), .CO(n1716), .S(n1523) );
XOR2X4TS U1694 ( .A(n1146), .B(n431), .Y(n1152) );
OAI21X1TS U1695 ( .A0(n1779), .A1(n236), .B0(n1778), .Y(n234) );
XOR2X4TS U1696 ( .A(n235), .B(n1778), .Y(n2616) );
OAI2BB1X2TS U1697 ( .A0N(n587), .A1N(n1534), .B0(n585), .Y(n1528) );
INVX2TS U1698 ( .A(n274), .Y(n269) );
INVX2TS U1699 ( .A(n1503), .Y(n2152) );
XOR2X4TS U1700 ( .A(n848), .B(n1477), .Y(n1503) );
NAND2X4TS U1701 ( .A(n1902), .B(n1901), .Y(n2280) );
OAI2BB1X2TS U1702 ( .A0N(n1309), .A1N(n295), .B0(n293), .Y(n1302) );
INVX2TS U1703 ( .A(n1309), .Y(n294) );
OAI2BB1X4TS U1704 ( .A0N(n1113), .A1N(n1112), .B0(n858), .Y(n2323) );
XNOR2X4TS U1705 ( .A(n1064), .B(n1063), .Y(n237) );
OAI21X1TS U1706 ( .A0(n1063), .A1(n1064), .B0(n1062), .Y(n238) );
XOR2X4TS U1707 ( .A(n679), .B(n1826), .Y(n1780) );
ADDFHX4TS U1708 ( .A(n1354), .B(n1353), .CI(n1352), .CO(n1306), .S(n1750) );
ADDFHX4TS U1709 ( .A(n1996), .B(n761), .CI(n1995), .CO(n2009), .S(n1992) );
XNOR2X4TS U1710 ( .A(n240), .B(n1987), .Y(n2335) );
XOR2X4TS U1711 ( .A(n1986), .B(n241), .Y(n240) );
INVX2TS U1712 ( .A(n1988), .Y(n241) );
INVX2TS U1713 ( .A(n1272), .Y(n257) );
XOR2X4TS U1714 ( .A(n243), .B(n1764), .Y(n1747) );
XOR2X4TS U1715 ( .A(n322), .B(n434), .Y(n1764) );
XOR2X4TS U1716 ( .A(n1766), .B(n1765), .Y(n243) );
XOR2X4TS U1717 ( .A(n244), .B(n1336), .Y(n2163) );
XOR2X4TS U1718 ( .A(n1270), .B(n489), .Y(n1336) );
INVX2TS U1719 ( .A(n1293), .Y(n305) );
XOR2X4TS U1720 ( .A(n245), .B(n917), .Y(n2125) );
AOI21X4TS U1721 ( .A0(n957), .A1(n330), .B0(n329), .Y(n245) );
OAI22X4TS U1722 ( .A0(n1800), .A1(n1799), .B0(n1432), .B1(n1232), .Y(n1795)
);
XNOR2X2TS U1723 ( .A(n135), .B(Data_A_i[17]), .Y(n1102) );
OAI21X1TS U1724 ( .A0(n1175), .A1(n1174), .B0(n1173), .Y(n246) );
XNOR2X4TS U1725 ( .A(n247), .B(n1173), .Y(n1176) );
OAI21X1TS U1726 ( .A0(n1235), .A1(n1236), .B0(n1234), .Y(n248) );
OAI2BB1X4TS U1727 ( .A0N(n1777), .A1N(n250), .B0(n249), .Y(n1847) );
XNOR2X4TS U1728 ( .A(n251), .B(n1776), .Y(n1835) );
XOR2X4TS U1729 ( .A(n1777), .B(n2616), .Y(n251) );
XNOR2X4TS U1730 ( .A(n252), .B(n1374), .Y(n1411) );
OAI21X2TS U1731 ( .A0(n1422), .A1(n1423), .B0(n1421), .Y(n462) );
INVX2TS U1732 ( .A(n1443), .Y(n755) );
XNOR2X2TS U1733 ( .A(n279), .B(Data_A_i[17]), .Y(n1394) );
XOR2X4TS U1734 ( .A(n432), .B(n2312), .Y(n467) );
XNOR2X4TS U1735 ( .A(n687), .B(n1305), .Y(n1902) );
INVX2TS U1736 ( .A(n1273), .Y(n256) );
XOR2X4TS U1737 ( .A(n258), .B(n1055), .Y(n628) );
ADDFHX2TS U1738 ( .A(n1568), .B(n1569), .CI(n1567), .CO(n2144), .S(n2143) );
XNOR2X4TS U1739 ( .A(n260), .B(n289), .Y(n1721) );
XOR2X4TS U1740 ( .A(n381), .B(n1676), .Y(n1681) );
OAI21X4TS U1741 ( .A0(n2280), .A1(n2271), .B0(n2272), .Y(n2564) );
NOR2X8TS U1742 ( .A(n410), .B(n398), .Y(n2271) );
CMPR22X2TS U1743 ( .A(n945), .B(n946), .CO(n1084), .S(n1258) );
XOR2X4TS U1744 ( .A(n1844), .B(n1845), .Y(n853) );
NAND2X1TS U1745 ( .A(n1220), .B(n1221), .Y(n262) );
XOR2X1TS U1746 ( .A(n1219), .B(n265), .Y(n1208) );
OAI2BB1X4TS U1747 ( .A0N(n59), .A1N(n1110), .B0(n266), .Y(n1162) );
XNOR2X4TS U1748 ( .A(n267), .B(n1110), .Y(n1309) );
OAI21X2TS U1749 ( .A0(n1918), .A1(n1917), .B0(n1916), .Y(n867) );
NAND2X1TS U1750 ( .A(n269), .B(n1566), .Y(n268) );
XOR2X4TS U1751 ( .A(n273), .B(n272), .Y(n2300) );
XOR2X4TS U1752 ( .A(n363), .B(n1687), .Y(n1693) );
XNOR2X4TS U1753 ( .A(n1469), .B(n277), .Y(n2309) );
XNOR2X4TS U1754 ( .A(n1470), .B(n1471), .Y(n277) );
OAI2BB1X4TS U1755 ( .A0N(n1471), .A1N(n1470), .B0(n278), .Y(n2312) );
ADDFHX2TS U1756 ( .A(n1186), .B(n1185), .CI(n1184), .CO(n1229), .S(n1174) );
XNOR2X2TS U1757 ( .A(n1965), .B(n772), .Y(n1811) );
NAND2X1TS U1758 ( .A(n1076), .B(n1077), .Y(n1078) );
OAI22X2TS U1759 ( .A0(n1963), .A1(n1461), .B0(n1964), .B1(n1417), .Y(n1463)
);
XOR2X4TS U1760 ( .A(n580), .B(n1706), .Y(n579) );
XOR2X4TS U1761 ( .A(n492), .B(n1380), .Y(n1706) );
ADDFHX2TS U1762 ( .A(n1453), .B(n1454), .CI(n1452), .CO(n1371), .S(n1479) );
INVX8TS U1763 ( .A(n281), .Y(n595) );
CLKINVX6TS U1764 ( .A(n1565), .Y(n281) );
NOR2X4TS U1765 ( .A(n2220), .B(n2226), .Y(n2229) );
XOR2X4TS U1766 ( .A(n2046), .B(n654), .Y(n556) );
XNOR2X4TS U1767 ( .A(n282), .B(n2081), .Y(n2703) );
XNOR2X4TS U1768 ( .A(n2083), .B(n2082), .Y(n282) );
INVX2TS U1769 ( .A(n1248), .Y(n553) );
CMPR22X2TS U1770 ( .A(n1485), .B(n1486), .CO(n1509), .S(n1518) );
XOR2X4TS U1771 ( .A(n828), .B(n2005), .Y(n495) );
INVX2TS U1772 ( .A(n2759), .Y(n2808) );
XOR2X4TS U1773 ( .A(n1852), .B(n284), .Y(n1877) );
XOR2X4TS U1774 ( .A(n685), .B(n594), .Y(n1852) );
ADDFHX2TS U1775 ( .A(n1815), .B(n1814), .CI(n1813), .CO(n1871), .S(n1826) );
NAND2BX1TS U1776 ( .AN(n1221), .B(n1144), .Y(n285) );
AOI21X4TS U1777 ( .A0(n2746), .A1(n2590), .B0(n2589), .Y(n2774) );
OAI2BB1X4TS U1778 ( .A0N(n1168), .A1N(n1169), .B0(n485), .Y(n1245) );
NAND2X4TS U1779 ( .A(n962), .B(n412), .Y(n439) );
OAI22X2TS U1780 ( .A0(n164), .A1(n1883), .B0(n181), .B1(n1941), .Y(n1940) );
XOR2X4TS U1781 ( .A(n1116), .B(n644), .Y(n289) );
ADDFHX4TS U1782 ( .A(n1551), .B(n1550), .CI(n1549), .CO(n1525), .S(n1687) );
OAI21X4TS U1783 ( .A0(n968), .A1(n963), .B0(n964), .Y(n551) );
INVX2TS U1784 ( .A(n2150), .Y(n1533) );
XNOR2X4TS U1785 ( .A(n2309), .B(n1500), .Y(n782) );
XOR2X4TS U1786 ( .A(n1399), .B(n1400), .Y(n1437) );
OAI22X4TS U1787 ( .A0(n1257), .A1(n161), .B0(n1256), .B1(n2059), .Y(n1399)
);
OAI21X4TS U1788 ( .A0(n2784), .A1(n2787), .B0(n2789), .Y(n2746) );
XOR2X4TS U1789 ( .A(n292), .B(n1290), .Y(n608) );
XOR2X4TS U1790 ( .A(n1289), .B(n1291), .Y(n292) );
OAI2BB1X2TS U1791 ( .A0N(n297), .A1N(n294), .B0(n1308), .Y(n293) );
XNOR2X4TS U1792 ( .A(n296), .B(n1308), .Y(n1752) );
XOR2X4TS U1793 ( .A(n297), .B(n1309), .Y(n296) );
XOR2X4TS U1794 ( .A(n620), .B(n1167), .Y(n297) );
XOR2X4TS U1795 ( .A(n300), .B(n2606), .Y(n1161) );
XOR2X4TS U1796 ( .A(n2596), .B(n301), .Y(n300) );
XNOR2X4TS U1797 ( .A(n1498), .B(n1497), .Y(n524) );
XNOR2X4TS U1798 ( .A(n303), .B(n1735), .Y(n1742) );
XNOR2X4TS U1799 ( .A(n1734), .B(n1736), .Y(n303) );
XOR2X4TS U1800 ( .A(n537), .B(n1741), .Y(n472) );
XOR2X4TS U1801 ( .A(n794), .B(n538), .Y(n537) );
XNOR2X4TS U1802 ( .A(n307), .B(n1349), .Y(n1700) );
XOR2X4TS U1803 ( .A(n1350), .B(n2319), .Y(n307) );
XNOR2X4TS U1804 ( .A(n1755), .B(n1754), .Y(n812) );
XNOR2X4TS U1805 ( .A(n528), .B(n1297), .Y(n1754) );
NAND2X1TS U1806 ( .A(n1350), .B(n1351), .Y(n308) );
ADDFHX4TS U1807 ( .A(n1683), .B(n1682), .CI(n1681), .CO(n1684), .S(n1672) );
ADDFHX2TS U1808 ( .A(n1520), .B(n1519), .CI(n1518), .CO(n2304), .S(n2302) );
OAI22X4TS U1809 ( .A0(n2243), .A1(n1125), .B0(n717), .B1(n2175), .Y(n1148)
);
XNOR2X4TS U1810 ( .A(n335), .B(n333), .Y(n313) );
OAI21X4TS U1811 ( .A0(n2377), .A1(n2376), .B0(n378), .Y(n2367) );
AOI21X4TS U1812 ( .A0(n505), .A1(n2451), .B0(n1654), .Y(n2377) );
OAI2BB1X4TS U1813 ( .A0N(n1440), .A1N(n1441), .B0(n314), .Y(n2317) );
XOR2X4TS U1814 ( .A(n1440), .B(n1441), .Y(n317) );
AOI21X4TS U1815 ( .A0(n861), .A1(n2168), .B0(n535), .Y(n2199) );
OAI21X2TS U1816 ( .A0(n1787), .A1(n1788), .B0(n318), .Y(n1786) );
XOR2X4TS U1817 ( .A(n318), .B(n1788), .Y(n710) );
XOR2X4TS U1818 ( .A(n776), .B(n706), .Y(n2202) );
XOR2X4TS U1819 ( .A(n1756), .B(n1757), .Y(n322) );
XOR2X4TS U1820 ( .A(n1224), .B(n1225), .Y(n324) );
NAND2X8TS U1821 ( .A(n419), .B(n418), .Y(n957) );
XOR2X4TS U1822 ( .A(n1132), .B(n1131), .Y(n694) );
XOR2X4TS U1823 ( .A(n1134), .B(n332), .Y(n1131) );
NOR2BX4TS U1824 ( .AN(n965), .B(n334), .Y(n333) );
OAI21X4TS U1825 ( .A0(n969), .A1(n967), .B0(n968), .Y(n335) );
XNOR2X4TS U1826 ( .A(n910), .B(n908), .Y(n1588) );
XOR2X4TS U1827 ( .A(n1561), .B(Data_B_i[15]), .Y(n910) );
INVX2TS U1828 ( .A(n2140), .Y(n338) );
NAND2BX4TS U1829 ( .AN(n1684), .B(n339), .Y(n2366) );
INVX4TS U1830 ( .A(n1685), .Y(n339) );
XOR2X4TS U1831 ( .A(n604), .B(n351), .Y(n1685) );
XOR2X4TS U1832 ( .A(n340), .B(n1678), .Y(n351) );
XOR2X4TS U1833 ( .A(n1680), .B(n1679), .Y(n340) );
XNOR2X4TS U1834 ( .A(n344), .B(n342), .Y(n341) );
XOR2X4TS U1835 ( .A(n909), .B(n345), .Y(n344) );
XOR2X4TS U1836 ( .A(Data_B_i[14]), .B(Data_B_i[2]), .Y(n909) );
OAI21X4TS U1837 ( .A0(n2443), .A1(n2446), .B0(n2444), .Y(n505) );
NAND2BX2TS U1838 ( .AN(n349), .B(n1651), .Y(n2444) );
AOI21X4TS U1839 ( .A0(n2424), .A1(n2423), .B0(n1649), .Y(n2446) );
NOR2X4TS U1840 ( .A(n1651), .B(n1650), .Y(n2443) );
OAI22X4TS U1841 ( .A0(n913), .A1(n1590), .B0(n1607), .B1(n1578), .Y(n1598)
);
OAI21X1TS U1842 ( .A0(n1690), .A1(n1691), .B0(n351), .Y(n603) );
INVX2TS U1843 ( .A(n357), .Y(n354) );
XNOR2X4TS U1844 ( .A(n356), .B(n2266), .Y(n1340) );
OAI2BB1X4TS U1845 ( .A0N(n1273), .A1N(n1272), .B0(n355), .Y(n2266) );
XNOR2X4TS U1846 ( .A(n361), .B(n360), .Y(n359) );
XNOR2X4TS U1847 ( .A(n896), .B(n899), .Y(n361) );
XOR2X4TS U1848 ( .A(n1689), .B(n1688), .Y(n363) );
OAI21X4TS U1849 ( .A0(n369), .A1(n961), .B0(n960), .Y(n962) );
XOR2X4TS U1850 ( .A(n163), .B(Data_B_i[17]), .Y(n1032) );
XOR2X4TS U1851 ( .A(n969), .B(n367), .Y(n1591) );
AOI21X4TS U1852 ( .A0(n2799), .A1(n368), .B0(n2583), .Y(n376) );
NOR2X8TS U1853 ( .A(Data_A_i[13]), .B(Data_A_i[1]), .Y(n369) );
XOR2X4TS U1854 ( .A(n370), .B(n1021), .Y(n1922) );
AOI21X4TS U1855 ( .A0(n1017), .A1(n437), .B0(n1016), .Y(n370) );
XOR2X4TS U1856 ( .A(n372), .B(n1958), .Y(n2090) );
XOR2X4TS U1857 ( .A(n373), .B(n1959), .Y(n372) );
OAI2BB1X4TS U1858 ( .A0N(n1917), .A1N(n1918), .B0(n867), .Y(n373) );
INVX2TS U1859 ( .A(n1922), .Y(n1966) );
OAI21X4TS U1860 ( .A0(n2759), .A1(n377), .B0(n376), .Y(n511) );
OAI2BB1X4TS U1861 ( .A0N(Data_B_i[14]), .A1N(Data_B_i[2]), .B0(n379), .Y(
n908) );
XOR2X4TS U1862 ( .A(n540), .B(n1677), .Y(n381) );
OAI2BB1X4TS U1863 ( .A0N(n1665), .A1N(n1666), .B0(n382), .Y(n540) );
OAI2BB1X4TS U1864 ( .A0N(n390), .A1N(n1487), .B0(n389), .Y(n1419) );
NAND2BX1TS U1865 ( .AN(n391), .B(n1488), .Y(n389) );
INVX2TS U1866 ( .A(n393), .Y(n391) );
XOR2X4TS U1867 ( .A(n1488), .B(n393), .Y(n392) );
CLKINVX1TS U1868 ( .A(n2965), .Y(n2972) );
XOR2X4TS U1869 ( .A(n2391), .B(n2390), .Y(n2418) );
AOI2BB1X4TS U1870 ( .A0N(n2965), .A1N(n2404), .B0(n2416), .Y(n2980) );
OAI21X2TS U1871 ( .A0(n2922), .A1(n2919), .B0(n2920), .Y(n2926) );
NAND2X1TS U1872 ( .A(n2305), .B(n2304), .Y(n2920) );
NOR2X1TS U1873 ( .A(n2305), .B(n2304), .Y(n2919) );
AOI21X2TS U1874 ( .A0(n2281), .A1(n394), .B0(n2270), .Y(n2274) );
AOI21X1TS U1875 ( .A0(n2565), .A1(n394), .B0(n2564), .Y(n2570) );
AOI21X1TS U1876 ( .A0(n2553), .A1(n394), .B0(n2552), .Y(n2558) );
XNOR2X1TS U1877 ( .A(n2282), .B(n394), .Y(n2528) );
NAND2X2TS U1878 ( .A(n398), .B(n410), .Y(n2272) );
XOR2X4TS U1879 ( .A(n863), .B(n1838), .Y(n398) );
NAND2BX4TS U1880 ( .AN(n402), .B(n400), .Y(n1800) );
OAI21X4TS U1881 ( .A0(n402), .A1(n401), .B0(n399), .Y(n1432) );
OAI21X4TS U1882 ( .A0(n404), .A1(n2596), .B0(n403), .Y(n1832) );
NOR2X4TS U1883 ( .A(n2606), .B(n406), .Y(n404) );
OAI2BB1X4TS U1884 ( .A0N(n1249), .A1N(n1248), .B0(n405), .Y(n2596) );
OAI2BB1X4TS U1885 ( .A0N(n552), .A1N(n553), .B0(n1247), .Y(n405) );
OAI2BB1X4TS U1886 ( .A0N(n1122), .A1N(n1121), .B0(n407), .Y(n2606) );
XOR2X4TS U1887 ( .A(n843), .B(n1176), .Y(n737) );
OAI21X1TS U1888 ( .A0(n1906), .A1(n742), .B0(n739), .Y(n408) );
AOI21X4TS U1889 ( .A0(n849), .A1(n2564), .B0(n409), .Y(n862) );
OAI2BB1X4TS U1890 ( .A0N(n1306), .A1N(n1307), .B0(n686), .Y(n410) );
XOR2X4TS U1891 ( .A(n853), .B(n852), .Y(n411) );
INVX2TS U1892 ( .A(n416), .Y(n414) );
XNOR2X4TS U1893 ( .A(n415), .B(n2003), .Y(n1958) );
XOR2X4TS U1894 ( .A(n2004), .B(n416), .Y(n415) );
XNOR2X4TS U1895 ( .A(n417), .B(n1992), .Y(n416) );
AOI21X4TS U1896 ( .A0(n1037), .A1(n891), .B0(n450), .Y(n418) );
XOR2X4TS U1897 ( .A(n971), .B(n966), .Y(n420) );
XOR2X4TS U1898 ( .A(n421), .B(Data_B_i[23]), .Y(n971) );
XNOR2X4TS U1899 ( .A(n423), .B(n961), .Y(n1616) );
OAI2BB1X4TS U1900 ( .A0N(n1760), .A1N(n1759), .B0(n425), .Y(n1751) );
OAI21X2TS U1901 ( .A0(n1759), .A1(n1760), .B0(n1758), .Y(n425) );
XNOR2X4TS U1902 ( .A(n1759), .B(n1760), .Y(n426) );
XOR2X4TS U1903 ( .A(n437), .B(n445), .Y(n621) );
NAND2X8TS U1904 ( .A(n439), .B(n438), .Y(n437) );
XOR2X4TS U1905 ( .A(n543), .B(n1729), .Y(n1732) );
AOI21X4TS U1906 ( .A0(n437), .A1(n1038), .B0(n1037), .Y(n1043) );
XOR2X4TS U1907 ( .A(n2214), .B(n2213), .Y(n440) );
XOR2X4TS U1908 ( .A(n441), .B(n1833), .Y(n1787) );
XOR2X4TS U1909 ( .A(n1834), .B(n1832), .Y(n441) );
XOR2X4TS U1910 ( .A(n1743), .B(n483), .Y(n622) );
NAND2BX4TS U1911 ( .AN(n109), .B(n1036), .Y(n1964) );
AOI21X4TS U1912 ( .A0(n957), .A1(n897), .B0(n892), .Y(n895) );
XOR2X4TS U1913 ( .A(n768), .B(n110), .Y(n453) );
XNOR2X4TS U1914 ( .A(n454), .B(n468), .Y(n1522) );
NAND2X2TS U1915 ( .A(n459), .B(n2588), .Y(n2751) );
XOR2X4TS U1916 ( .A(n2199), .B(n2198), .Y(n459) );
XOR2X4TS U1917 ( .A(n2151), .B(n460), .Y(n546) );
XOR2X4TS U1918 ( .A(n901), .B(n1032), .Y(n461) );
NAND2BX4TS U1919 ( .AN(n291), .B(n455), .Y(n464) );
NAND2X4TS U1920 ( .A(n2500), .B(n2497), .Y(n1749) );
XOR2X4TS U1921 ( .A(n472), .B(n1740), .Y(n1745) );
NAND2X1TS U1922 ( .A(n475), .B(n2312), .Y(n2943) );
CLKINVX1TS U1923 ( .A(n1411), .Y(n475) );
OAI2BB1X4TS U1924 ( .A0N(n1716), .A1N(n1715), .B0(n477), .Y(n1737) );
OAI21X4TS U1925 ( .A0(n1716), .A1(n1715), .B0(n1714), .Y(n477) );
XOR2X4TS U1926 ( .A(n970), .B(n481), .Y(n534) );
XOR2X4TS U1927 ( .A(Data_B_i[22]), .B(Data_B_i[10]), .Y(n970) );
OAI2BB1X1TS U1928 ( .A0N(n1743), .A1N(n483), .B0(n482), .Y(n1744) );
OAI21X1TS U1929 ( .A0(n1743), .A1(n483), .B0(n1742), .Y(n482) );
INVX2TS U1930 ( .A(n2325), .Y(n1204) );
XOR2X4TS U1931 ( .A(n2607), .B(n2325), .Y(n484) );
XOR2X4TS U1932 ( .A(n738), .B(n669), .Y(n1169) );
XOR2X4TS U1933 ( .A(n836), .B(Data_B_i[7]), .Y(n2025) );
OAI2BB1X4TS U1934 ( .A0N(n1271), .A1N(n490), .B0(n488), .Y(n1272) );
XOR2X4TS U1935 ( .A(n1271), .B(n490), .Y(n489) );
INVX2TS U1936 ( .A(n580), .Y(n2313) );
XOR2X4TS U1937 ( .A(n568), .B(n1381), .Y(n492) );
AND2X4TS U1938 ( .A(n1399), .B(n1400), .Y(n1380) );
AOI21X4TS U1939 ( .A0(n1374), .A1(n494), .B0(n493), .Y(n580) );
AND2X4TS U1940 ( .A(n1376), .B(n1375), .Y(n493) );
NAND2BX4TS U1941 ( .AN(n1375), .B(n216), .Y(n494) );
XOR2X4TS U1942 ( .A(Data_B_i[20]), .B(Data_B_i[21]), .Y(n498) );
XNOR2X4TS U1943 ( .A(n2035), .B(n499), .Y(n2042) );
INVX2TS U1944 ( .A(n500), .Y(n2843) );
OAI21X4TS U1945 ( .A0(n2872), .A1(n2526), .B0(n2525), .Y(n500) );
NAND2X2TS U1946 ( .A(n2451), .B(n501), .Y(n2452) );
INVX2TS U1947 ( .A(n1654), .Y(n501) );
INVX2TS U1948 ( .A(n505), .Y(n506) );
INVX4TS U1949 ( .A(n975), .Y(n1641) );
OAI2BB1X1TS U1950 ( .A0N(n1626), .A1N(n1625), .B0(n513), .Y(n1650) );
XNOR2X4TS U1951 ( .A(n1626), .B(n1625), .Y(n516) );
OAI21X1TS U1952 ( .A0(n1299), .A1(n1300), .B0(n1301), .Y(n517) );
XOR2X4TS U1953 ( .A(n518), .B(n1301), .Y(n1753) );
XOR2X4TS U1954 ( .A(n1300), .B(n1299), .Y(n518) );
OA22X4TS U1955 ( .A0(n1964), .A1(n718), .B0(n1963), .B1(n1416), .Y(n519) );
OAI22X2TS U1956 ( .A0(n1504), .A1(n168), .B0(n1480), .B1(n184), .Y(n1502) );
OAI21X1TS U1957 ( .A0(n1934), .A1(n1935), .B0(n1933), .Y(n522) );
XNOR2X4TS U1958 ( .A(n524), .B(n1496), .Y(n1526) );
AO21X2TS U1959 ( .A0(n207), .A1(n1565), .B0(n1564), .Y(n1234) );
XOR2X4TS U1960 ( .A(n1474), .B(n692), .Y(n1499) );
CLKINVX1TS U1961 ( .A(n1298), .Y(n526) );
XOR2X4TS U1962 ( .A(n2321), .B(n1298), .Y(n528) );
NOR2X2TS U1963 ( .A(n2387), .B(n2385), .Y(n2429) );
NAND2X2TS U1964 ( .A(n2454), .B(n2453), .Y(n2991) );
ADDFHX2TS U1965 ( .A(n1045), .B(n1046), .CI(n1044), .CO(n1163), .S(n1275) );
NOR2X4TS U1966 ( .A(n2195), .B(n2196), .Y(n2226) );
NAND2X1TS U1967 ( .A(n1939), .B(n1940), .Y(n530) );
XNOR2X4TS U1968 ( .A(n533), .B(n532), .Y(n1947) );
XNOR2X4TS U1969 ( .A(n589), .B(n1938), .Y(n533) );
XOR2X4TS U1970 ( .A(n613), .B(n534), .Y(n751) );
OAI21X4TS U1971 ( .A0(n2167), .A1(n2220), .B0(n2227), .Y(n535) );
OAI2BB1X4TS U1972 ( .A0N(n643), .A1N(n642), .B0(n1116), .Y(n641) );
NAND2X2TS U1973 ( .A(n2095), .B(n2096), .Y(n2224) );
OAI21X2TS U1974 ( .A0(n1115), .A1(n616), .B0(n1114), .Y(n615) );
ADDFHX2TS U1975 ( .A(n1006), .B(n1005), .CI(n1004), .CO(n1044), .S(n1298) );
ADDFHX2TS U1976 ( .A(n1865), .B(n1864), .CI(n1863), .CO(n1934), .S(n1861) );
OAI21X1TS U1977 ( .A0(n1677), .A1(n540), .B0(n1676), .Y(n539) );
OAI22X2TS U1978 ( .A0(n1619), .A1(n984), .B0(n1133), .B1(n195), .Y(n1049) );
CMPR22X2TS U1979 ( .A(n734), .B(n338), .CO(n1573), .S(n1593) );
OAI21X2TS U1980 ( .A0(n1731), .A1(n1730), .B0(n1729), .Y(n542) );
XOR2X4TS U1981 ( .A(n1731), .B(n1730), .Y(n543) );
NOR2X2TS U1982 ( .A(n1203), .B(n1204), .Y(n566) );
XNOR2X4TS U1983 ( .A(n544), .B(n1421), .Y(n2150) );
XOR2X4TS U1984 ( .A(n546), .B(n1414), .Y(n1529) );
CMPR22X2TS U1985 ( .A(n1253), .B(n1252), .CO(n1116), .S(n1346) );
OAI2BB1X4TS U1986 ( .A0N(n691), .A1N(n690), .B0(n1474), .Y(n689) );
XNOR2X4TS U1987 ( .A(n666), .B(n1723), .Y(n665) );
NAND2X2TS U1988 ( .A(n1693), .B(n1692), .Y(n2464) );
NAND2BX4TS U1989 ( .AN(n1648), .B(n547), .Y(n2423) );
XOR2X2TS U1990 ( .A(n2375), .B(n2374), .Y(n2461) );
OAI22X2TS U1991 ( .A0(n1618), .A1(n160), .B0(n1557), .B1(n196), .Y(n2295) );
XNOR2X2TS U1992 ( .A(Data_B_i[1]), .B(Data_A_i[7]), .Y(n1360) );
OAI22X2TS U1993 ( .A0(n529), .A1(n1797), .B0(n496), .B1(n1869), .Y(n1858) );
OAI21X2TS U1994 ( .A0(n1502), .A1(n1503), .B0(n1501), .Y(n626) );
OAI22X2TS U1995 ( .A0(n1619), .A1(n1280), .B0(n986), .B1(n196), .Y(n1283) );
OAI22X2TS U1996 ( .A0(n1425), .A1(n173), .B0(n63), .B1(n1424), .Y(n1519) );
XOR2X4TS U1997 ( .A(n2048), .B(n2047), .Y(n654) );
OAI22X2TS U1998 ( .A0(n921), .A1(n1610), .B0(n974), .B1(n346), .Y(n1067) );
XNOR2X4TS U1999 ( .A(n1247), .B(n554), .Y(n2267) );
XNOR2X4TS U2000 ( .A(n1248), .B(n1249), .Y(n554) );
INVX2TS U2001 ( .A(n2287), .Y(n2356) );
XOR2X4TS U2002 ( .A(n1782), .B(n1781), .Y(n572) );
AND2X4TS U2003 ( .A(n1463), .B(n1464), .Y(n1474) );
XOR2X4TS U2004 ( .A(n559), .B(n1913), .Y(n1956) );
XNOR2X4TS U2005 ( .A(n1912), .B(n2333), .Y(n559) );
CLKINVX1TS U2006 ( .A(n1709), .Y(n562) );
ADDFHX2TS U2007 ( .A(n1886), .B(n1885), .CI(n1884), .CO(n1939), .S(n1892) );
OAI22X2TS U2008 ( .A0(n160), .A1(n1318), .B0(n1280), .B1(n195), .Y(n1317) );
ADDFHX2TS U2009 ( .A(n1059), .B(n1058), .CI(n1057), .CO(n1132), .S(n1055) );
XOR2X2TS U2010 ( .A(n2384), .B(n2383), .Y(n2459) );
OAI21X4TS U2011 ( .A0(n2330), .A1(n564), .B0(n722), .Y(n2487) );
NOR2X2TS U2012 ( .A(n2325), .B(n2326), .Y(n2433) );
OAI21X4TS U2013 ( .A0(n566), .A1(n2326), .B0(n565), .Y(n1837) );
OAI21X4TS U2014 ( .A0(n2514), .A1(n2507), .B0(n2508), .Y(n1771) );
OR2X4TS U2015 ( .A(n2427), .B(n2426), .Y(n2986) );
OAI22X2TS U2016 ( .A0(n1565), .A1(n1489), .B0(n208), .B1(n1394), .Y(n1457)
);
NOR2X2TS U2017 ( .A(n2406), .B(n2956), .Y(n728) );
NAND2X4TS U2018 ( .A(n711), .B(n1772), .Y(n845) );
OAI21X4TS U2019 ( .A0(n1749), .A1(n2474), .B0(n663), .Y(n711) );
XOR2X1TS U2020 ( .A(n1541), .B(n1540), .Y(n570) );
OAI21X2TS U2021 ( .A0(n1834), .A1(n1832), .B0(n1833), .Y(n591) );
ADDFHX2TS U2022 ( .A(n346), .B(n1101), .CI(n1100), .CO(n1178), .S(n1098) );
NOR2BX2TS U2023 ( .AN(n158), .B(n242), .Y(n1569) );
CMPR22X2TS U2024 ( .A(n1329), .B(n1328), .CO(n1334), .S(n1372) );
NOR2X2TS U2025 ( .A(n2460), .B(n2459), .Y(n2997) );
ADDFHX4TS U2026 ( .A(n1595), .B(n1594), .CI(n1593), .CO(n1597), .S(n1627) );
ADDFHX2TS U2027 ( .A(n940), .B(n939), .CI(n938), .CO(n1073), .S(n1270) );
ADDFHX2TS U2028 ( .A(n1409), .B(n1408), .CI(n1407), .CO(n1375), .S(n1469) );
NOR2BX2TS U2029 ( .AN(n275), .B(n1580), .Y(n2294) );
OAI22X2TS U2030 ( .A0(n1310), .A1(n185), .B0(n1448), .B1(n1964), .Y(n1710)
);
XNOR2X4TS U2031 ( .A(n1028), .B(n1027), .Y(n576) );
XOR2X4TS U2032 ( .A(Data_B_i[12]), .B(Data_B_i[0]), .Y(n975) );
XOR2X4TS U2033 ( .A(n766), .B(n2693), .Y(n577) );
NAND2X4TS U2034 ( .A(n1767), .B(n1768), .Y(n2514) );
OAI2BB1X4TS U2035 ( .A0N(n580), .A1N(n1707), .B0(n578), .Y(n1718) );
OAI21X4TS U2036 ( .A0(n1707), .A1(n580), .B0(n1706), .Y(n578) );
XOR2X4TS U2037 ( .A(n579), .B(n1707), .Y(n1715) );
NOR2BX2TS U2038 ( .AN(n275), .B(n2025), .Y(n1403) );
AOI21X4TS U2039 ( .A0(n861), .A1(n866), .B0(n2533), .Y(n822) );
XOR2X4TS U2040 ( .A(n584), .B(n1274), .Y(n1353) );
XOR2X4TS U2041 ( .A(n586), .B(n1534), .Y(n1679) );
XOR2X4TS U2042 ( .A(n1533), .B(n587), .Y(n586) );
XOR2X4TS U2043 ( .A(n1463), .B(n1464), .Y(n587) );
XOR2X4TS U2044 ( .A(n1851), .B(n1850), .Y(n871) );
XOR2X4TS U2045 ( .A(n782), .B(n1499), .Y(n1551) );
XOR2X4TS U2046 ( .A(n1111), .B(n592), .Y(n859) );
XOR2X4TS U2047 ( .A(n694), .B(n1130), .Y(n1111) );
OAI22X2TS U2048 ( .A0(n1150), .A1(n202), .B0(n1811), .B1(n162), .Y(n1804) );
XOR2X4TS U2049 ( .A(n1073), .B(n1072), .Y(n775) );
XNOR2X4TS U2050 ( .A(n716), .B(n1893), .Y(n1919) );
OAI21X1TS U2051 ( .A0(n1135), .A1(n1133), .B0(n1134), .Y(n593) );
OAI22X2TS U2052 ( .A0(n497), .A1(n1237), .B0(n2018), .B1(n1797), .Y(n1791)
);
OAI22X2TS U2053 ( .A0(n172), .A1(n1387), .B0(n63), .B1(n1359), .Y(n1408) );
OAI21X2TS U2054 ( .A0(n1467), .A1(n1468), .B0(n1466), .Y(n672) );
ADDFHX2TS U2055 ( .A(n1067), .B(n1068), .CI(n1066), .CO(n1095), .S(n1083) );
XNOR2X4TS U2056 ( .A(n1169), .B(n1168), .Y(n620) );
NOR2X8TS U2057 ( .A(n1697), .B(n1696), .Y(n2288) );
NAND2X2TS U2058 ( .A(Data_A_i[17]), .B(Data_A_i[5]), .Y(n1026) );
OAI21X4TS U2059 ( .A0(n1025), .A1(n1023), .B0(n1026), .Y(n1037) );
XNOR2X4TS U2060 ( .A(n598), .B(n1189), .Y(n1192) );
OAI2BB1X4TS U2061 ( .A0N(n1171), .A1N(n1172), .B0(n599), .Y(n2325) );
XNOR2X4TS U2062 ( .A(n601), .B(n1170), .Y(n2324) );
OAI21X2TS U2063 ( .A0(n1124), .A1(n202), .B0(n854), .Y(n1153) );
OAI2BB1X4TS U2064 ( .A0N(n1738), .A1N(n1739), .B0(n697), .Y(n1765) );
XOR2X4TS U2065 ( .A(n1690), .B(n1691), .Y(n604) );
OAI21X1TS U2066 ( .A0(n611), .A1(n1366), .B0(n1365), .Y(n610) );
XOR2X4TS U2067 ( .A(n612), .B(n611), .Y(n1379) );
AO21X4TS U2068 ( .A0(n955), .A1(n954), .B0(n953), .Y(n890) );
OAI21X4TS U2069 ( .A0(n2942), .A1(n2316), .B0(n731), .Y(n2405) );
AOI21X4TS U2070 ( .A0(n2436), .A1(n2398), .B0(n2386), .Y(n2391) );
OAI22X2TS U2071 ( .A0(n529), .A1(n943), .B0(n2018), .B1(n1070), .Y(n1076) );
ADDFHX2TS U2072 ( .A(n1948), .B(n1947), .CI(n1946), .CO(n2336), .S(n2333) );
OAI2BB1X4TS U2073 ( .A0N(n1994), .A1N(n1993), .B0(n614), .Y(n2047) );
OAI2BB1X4TS U2074 ( .A0N(n1118), .A1N(n290), .B0(n641), .Y(n616) );
OR2X4TS U2075 ( .A(n2454), .B(n2453), .Y(n884) );
INVX2TS U2076 ( .A(n934), .Y(n933) );
NOR2BX4TS U2077 ( .AN(n275), .B(n2113), .Y(n1284) );
XOR2X4TS U2078 ( .A(n622), .B(n1742), .Y(n1697) );
OAI21X2TS U2079 ( .A0(n2996), .A1(n2999), .B0(n3000), .Y(n807) );
AND2X4TS U2080 ( .A(n2223), .B(n2234), .Y(n2236) );
XNOR2X4TS U2081 ( .A(n957), .B(n898), .Y(n1965) );
OAI2BB1X4TS U2082 ( .A0N(n1503), .A1N(n1502), .B0(n626), .Y(n1496) );
XNOR2X4TS U2083 ( .A(n629), .B(n628), .Y(n2320) );
XOR2X4TS U2084 ( .A(n1292), .B(n305), .Y(n629) );
NAND2X2TS U2085 ( .A(n1747), .B(n1746), .Y(n2499) );
OAI22X2TS U2086 ( .A0(n1610), .A1(n1261), .B0(n924), .B1(n974), .Y(n1264) );
XNOR2X2TS U2087 ( .A(Data_A_i[3]), .B(n132), .Y(n1285) );
ADDFHX2TS U2088 ( .A(n1523), .B(n1522), .CI(n1521), .CO(n1743), .S(n1524) );
OR2X4TS U2089 ( .A(n1606), .B(n1605), .Y(n1595) );
OAI22X2TS U2090 ( .A0(n160), .A1(n1426), .B0(n1385), .B1(n196), .Y(n1488) );
XOR2X4TS U2091 ( .A(n1806), .B(n633), .Y(n632) );
XNOR2X4TS U2092 ( .A(n652), .B(n1876), .Y(n651) );
ADDFHX2TS U2093 ( .A(n1241), .B(n1240), .CI(n1239), .CO(n1789), .S(n1228) );
XNOR2X4TS U2094 ( .A(n2292), .B(n2291), .Y(n806) );
OAI2BB1X2TS U2095 ( .A0N(n1260), .A1N(n1259), .B0(n638), .Y(n1072) );
OAI21X1TS U2096 ( .A0(n1259), .A1(n1260), .B0(n1258), .Y(n638) );
XNOR2X2TS U2097 ( .A(n639), .B(n1258), .Y(n1338) );
ADDFHX2TS U2098 ( .A(n1932), .B(n1931), .CI(n1930), .CO(n1990), .S(n1933) );
ADDFHX4TS U2099 ( .A(n1837), .B(n1836), .CI(n1835), .CO(n1849), .S(n1843) );
OAI2BB1X4TS U2100 ( .A0N(n1861), .A1N(n1860), .B0(n647), .Y(n1950) );
XOR2X4TS U2101 ( .A(n1894), .B(n1895), .Y(n716) );
XNOR2X4TS U2102 ( .A(n648), .B(n1859), .Y(n1894) );
OAI21X2TS U2103 ( .A0(n1877), .A1(n650), .B0(n1876), .Y(n649) );
XOR2X4TS U2104 ( .A(n701), .B(n1878), .Y(n652) );
XOR2X4TS U2105 ( .A(n661), .B(n1530), .Y(n1680) );
NAND2X2TS U2106 ( .A(n1745), .B(n1744), .Y(n2475) );
ADDFHX2TS U2107 ( .A(n1403), .B(n1402), .CI(n1401), .CO(n1362), .S(n1471) );
XOR2X4TS U2108 ( .A(n556), .B(n2006), .Y(n828) );
OAI21X4TS U2109 ( .A0(n2868), .A1(n2865), .B0(n2866), .Y(n2833) );
XOR2X4TS U2110 ( .A(n814), .B(n2724), .Y(n813) );
XOR2X4TS U2111 ( .A(n816), .B(n2645), .Y(n815) );
XOR2X4TS U2112 ( .A(n818), .B(n2601), .Y(n817) );
INVX2TS U2113 ( .A(n2814), .Y(n2456) );
NOR2X2TS U2114 ( .A(n2433), .B(n2438), .Y(n2329) );
INVX2TS U2115 ( .A(n2224), .Y(n2228) );
OAI22X2TS U2116 ( .A0(n2026), .A1(n1051), .B0(n2025), .B1(n1136), .Y(n1144)
);
NOR2X8TS U2117 ( .A(n2582), .B(n2581), .Y(n2795) );
AOI21X4TS U2118 ( .A0(n2287), .A1(n1699), .B0(n1698), .Y(n2474) );
OAI21X4TS U2119 ( .A0(n696), .A1(n2463), .B0(n2464), .Y(n2287) );
AOI21X4TS U2120 ( .A0(n2833), .A1(n2832), .B0(n2506), .Y(n2872) );
XOR2X4TS U2121 ( .A(Data_B_i[3]), .B(Data_B_i[2]), .Y(n985) );
XNOR2X4TS U2122 ( .A(n659), .B(n1669), .Y(n1653) );
XNOR2X4TS U2123 ( .A(n1664), .B(n810), .Y(n660) );
XNOR2X2TS U2124 ( .A(n136), .B(Data_A_i[23]), .Y(n1868) );
OAI21X2TS U2125 ( .A0(n2232), .A1(n2231), .B0(n2230), .Y(n2233) );
AOI21X4TS U2126 ( .A0(n2500), .A1(n2496), .B0(n1748), .Y(n663) );
XOR2X4TS U2127 ( .A(n668), .B(n1332), .Y(n1442) );
CLKINVX1TS U2128 ( .A(n1169), .Y(n2597) );
OAI21X4TS U2129 ( .A0(n2288), .A1(n2354), .B0(n2289), .Y(n1698) );
OAI22X2TS U2130 ( .A0(n173), .A1(n998), .B0(n63), .B1(n1053), .Y(n1058) );
NOR2X1TS U2131 ( .A(n421), .B(n1140), .Y(n1200) );
OAI2BB1X4TS U2132 ( .A0N(n2234), .A1N(n640), .B0(n671), .Y(n2235) );
XOR2X4TS U2133 ( .A(n820), .B(n2664), .Y(n819) );
INVX2TS U2134 ( .A(n2422), .Y(n1649) );
INVX2TS U2135 ( .A(n2652), .Y(n2623) );
ADDFHX2TS U2136 ( .A(n1631), .B(n1630), .CI(n1629), .CO(n1624), .S(n1646) );
INVX2TS U2137 ( .A(n2288), .Y(n2290) );
OAI2BB1X4TS U2138 ( .A0N(n1468), .A1N(n69), .B0(n672), .Y(n1711) );
XOR2X4TS U2139 ( .A(n673), .B(n69), .Y(n1498) );
XOR2X4TS U2140 ( .A(n677), .B(n676), .Y(n1222) );
XOR2X4TS U2141 ( .A(n876), .B(n1228), .Y(n676) );
OAI21X4TS U2142 ( .A0(n1739), .A1(n1738), .B0(n1737), .Y(n697) );
NAND2X2TS U2143 ( .A(n2580), .B(n2579), .Y(n2802) );
AOI21X2TS U2144 ( .A0(n2926), .A1(n2311), .B0(n2310), .Y(n2942) );
NAND2X2TS U2145 ( .A(n2964), .B(n2963), .Y(n2965) );
OR2X4TS U2146 ( .A(n2727), .B(n2728), .Y(n2730) );
INVX2TS U2147 ( .A(n844), .Y(n866) );
XOR2X4TS U2148 ( .A(n1870), .B(n1871), .Y(n685) );
OAI22X2TS U2149 ( .A0(n174), .A1(n1285), .B0(n1942), .B1(n991), .Y(n1313) );
NAND2X2TS U2150 ( .A(n2578), .B(n2577), .Y(n2763) );
XOR2X4TS U2151 ( .A(n1306), .B(n688), .Y(n687) );
AOI21X4TS U2152 ( .A0(n437), .A1(n374), .B0(n1024), .Y(n1028) );
NAND2BX2TS U2153 ( .AN(n2455), .B(n749), .Y(n2815) );
XNOR2X4TS U2154 ( .A(n1034), .B(n1029), .Y(n1030) );
XOR2X4TS U2155 ( .A(n695), .B(n886), .Y(n821) );
AOI21X2TS U2156 ( .A0(n129), .A1(n2593), .B0(n2592), .Y(n818) );
AOI21X2TS U2157 ( .A0(n129), .A1(n2625), .B0(n2624), .Y(n820) );
AOI21X2TS U2158 ( .A0(n129), .A1(n2712), .B0(n2711), .Y(n814) );
AOI21X2TS U2159 ( .A0(n129), .A1(n2643), .B0(n2642), .Y(n816) );
AOI21X1TS U2160 ( .A0(n2783), .A1(n478), .B0(n115), .Y(n3022) );
OAI22X2TS U2161 ( .A0(n1126), .A1(n2185), .B0(n2186), .B1(n1087), .Y(n1005)
);
AOI21X4TS U2162 ( .A0(n712), .A1(n2097), .B0(n877), .Y(n2167) );
AOI21X4TS U2163 ( .A0(n2367), .A1(n2366), .B0(n1686), .Y(n696) );
NOR2X4TS U2164 ( .A(n1768), .B(n1767), .Y(n2513) );
OAI2BB1X2TS U2165 ( .A0N(n1878), .A1N(n699), .B0(n698), .Y(n1957) );
NAND2X1TS U2166 ( .A(n700), .B(n1879), .Y(n698) );
INVX2TS U2167 ( .A(n1919), .Y(n700) );
XOR2X4TS U2168 ( .A(n1919), .B(n1879), .Y(n701) );
XOR2X4TS U2169 ( .A(n704), .B(n703), .Y(n702) );
XOR2X4TS U2170 ( .A(n1272), .B(n1273), .Y(n706) );
XOR2X4TS U2171 ( .A(n1842), .B(n1843), .Y(n863) );
XOR2X4TS U2172 ( .A(n710), .B(n1787), .Y(n1842) );
OAI22X4TS U2173 ( .A0(n497), .A1(n2017), .B0(n1262), .B1(n496), .Y(n1328) );
XOR2X4TS U2174 ( .A(Data_B_i[19]), .B(Data_B_i[20]), .Y(n1011) );
NAND2BX4TS U2175 ( .AN(n2314), .B(n580), .Y(n2951) );
XOR2X4TS U2176 ( .A(Data_B_i[20]), .B(Data_B_i[8]), .Y(n1012) );
AOI21X1TS U2177 ( .A0(n2808), .A1(n2800), .B0(n2799), .Y(n724) );
AOI21X1TS U2178 ( .A0(n2808), .A1(n2794), .B0(n2793), .Y(n726) );
AOI2BB1X4TS U2179 ( .A0N(n2406), .A1N(n2957), .B0(n727), .Y(n729) );
AOI21X2TS U2180 ( .A0(n2915), .A1(n2914), .B0(n2303), .Y(n2922) );
NAND2X1TS U2181 ( .A(n2901), .B(n2902), .Y(n733) );
INVX2TS U2182 ( .A(n2297), .Y(n734) );
XNOR2X4TS U2183 ( .A(n736), .B(n1245), .Y(n1307) );
XNOR2X4TS U2184 ( .A(n1244), .B(n1246), .Y(n736) );
XOR2X4TS U2185 ( .A(n1121), .B(n1122), .Y(n738) );
XOR2X4TS U2186 ( .A(n741), .B(n739), .Y(n1904) );
XOR2X4TS U2187 ( .A(n740), .B(n1916), .Y(n739) );
XOR2X4TS U2188 ( .A(n1918), .B(n1917), .Y(n740) );
XOR2X4TS U2189 ( .A(n742), .B(n1906), .Y(n741) );
NAND2BX2TS U2190 ( .AN(n749), .B(n2455), .Y(n2814) );
OAI2BB1X4TS U2191 ( .A0N(Data_B_i[8]), .A1N(Data_B_i[20]), .B0(n752), .Y(
n1008) );
XOR2X4TS U2192 ( .A(n756), .B(n1442), .Y(n2157) );
XOR2X4TS U2193 ( .A(n1443), .B(n1444), .Y(n756) );
OAI21X4TS U2194 ( .A0(n2045), .A1(n758), .B0(n757), .Y(n2011) );
NAND2X1TS U2195 ( .A(n761), .B(n2045), .Y(n885) );
XNOR2X4TS U2196 ( .A(n832), .B(n1989), .Y(n2045) );
XOR2X4TS U2197 ( .A(n1983), .B(n765), .Y(n1991) );
AOI21X4TS U2198 ( .A0(n2236), .A1(n605), .B0(n2235), .Y(n768) );
CLKBUFX3TS U2199 ( .A(n2058), .Y(n771) );
XOR2X4TS U2200 ( .A(n1013), .B(n774), .Y(n773) );
XOR2X4TS U2201 ( .A(n1010), .B(n1009), .Y(n2058) );
XOR2X4TS U2202 ( .A(n2057), .B(n1616), .Y(n1257) );
XNOR2X4TS U2203 ( .A(n1013), .B(n1008), .Y(n2000) );
XOR2X4TS U2204 ( .A(n775), .B(n1074), .Y(n776) );
XOR2X4TS U2205 ( .A(n778), .B(Data_B_i[21]), .Y(n2110) );
OAI2BB1X4TS U2206 ( .A0N(n1500), .A1N(n781), .B0(n779), .Y(n1497) );
OAI2BB1X4TS U2207 ( .A0N(n2309), .A1N(n780), .B0(n1499), .Y(n779) );
XOR2X4TS U2208 ( .A(Data_B_i[17]), .B(Data_B_i[18]), .Y(n785) );
NAND2X2TS U2209 ( .A(n1177), .B(n1178), .Y(n789) );
OAI2BB1X4TS U2210 ( .A0N(n1163), .A1N(n1162), .B0(n792), .Y(n1788) );
AOI21X1TS U2211 ( .A0(n511), .A1(n2754), .B0(n2746), .Y(n798) );
INVX12TS U2212 ( .A(Data_B_i[1]), .Y(n802) );
AOI21X4TS U2213 ( .A0(n2826), .A1(n804), .B0(n803), .Y(n2868) );
XOR2X4TS U2214 ( .A(n1665), .B(n1666), .Y(n810) );
OAI2BB1X4TS U2215 ( .A0N(n1755), .A1N(n1754), .B0(n811), .Y(n1352) );
XNOR2X4TS U2216 ( .A(n812), .B(n1753), .Y(n1763) );
XOR2X4TS U2217 ( .A(n822), .B(n2537), .Y(n2582) );
ADDHX1TS U2218 ( .A(n1492), .B(n1491), .CO(n1512), .S(n1539) );
INVX2TS U2219 ( .A(n2145), .Y(n1587) );
OAI22X2TS U2220 ( .A0(n1462), .A1(n1963), .B0(n1461), .B1(n1964), .Y(n1475)
);
OAI22X2TS U2221 ( .A0(n932), .A1(n2111), .B0(n2110), .B1(n1065), .Y(n1077)
);
OAI22X2TS U2222 ( .A0(n200), .A1(n1331), .B0(n784), .B1(n1266), .Y(n1366) );
OAI22X2TS U2223 ( .A0(n913), .A1(n358), .B0(n1556), .B1(n1607), .Y(n1612) );
ADDFHX2TS U2224 ( .A(n1892), .B(n1891), .CI(n1890), .CO(n1946), .S(n1870) );
OAI22X4TS U2225 ( .A0(n172), .A1(n1212), .B0(n1823), .B1(n63), .Y(n1819) );
NAND2X2TS U2226 ( .A(n2576), .B(n2575), .Y(n2805) );
INVX2TS U2227 ( .A(n2564), .Y(n2551) );
NAND2X2TS U2228 ( .A(n1685), .B(n1684), .Y(n2365) );
XOR2X4TS U2229 ( .A(n871), .B(n1849), .Y(n852) );
INVX2TS U2230 ( .A(n2474), .Y(n2498) );
NOR2X4TS U2231 ( .A(n2580), .B(n2579), .Y(n2801) );
XOR2X4TS U2232 ( .A(n1991), .B(n1990), .Y(n832) );
OAI21X4TS U2233 ( .A0(n835), .A1(n836), .B0(n834), .Y(n2026) );
XNOR2X4TS U2234 ( .A(n838), .B(n2032), .Y(n2341) );
XOR2X4TS U2235 ( .A(n1178), .B(n1177), .Y(n843) );
NAND2X2TS U2236 ( .A(n1697), .B(n1696), .Y(n2289) );
OAI2BB1X4TS U2237 ( .A0N(n1498), .A1N(n1497), .B0(n846), .Y(n1734) );
NAND2X4TS U2238 ( .A(n850), .B(n2584), .Y(n2784) );
XOR2X4TS U2239 ( .A(n2208), .B(n2207), .Y(n850) );
AOI21X4TS U2240 ( .A0(n957), .A1(n956), .B0(n890), .Y(n2244) );
XNOR2X4TS U2241 ( .A(n859), .B(n1112), .Y(n2322) );
NOR2X2TS U2242 ( .A(n2505), .B(n2504), .Y(n2503) );
ADDFHX2TS U2243 ( .A(n1210), .B(n1209), .CI(n1208), .CO(n1781), .S(n1205) );
ADDFHX2TS U2244 ( .A(n1200), .B(n62), .CI(n1199), .CO(n1209), .S(n1190) );
CLKINVX1TS U2245 ( .A(n2826), .Y(n2857) );
ADDFHX2TS U2246 ( .A(n2194), .B(n2193), .CI(n2192), .CO(n2237), .S(n2170) );
ADDFHX2TS U2247 ( .A(n2191), .B(n2190), .CI(n2189), .CO(n2250), .S(n2194) );
ADDFHX2TS U2248 ( .A(n1129), .B(n1128), .CI(n1127), .CO(n1172), .S(n1113) );
ADDFHX4TS U2249 ( .A(n1379), .B(n1378), .CI(n1377), .CO(n2158), .S(n2156) );
ADDFHX2TS U2250 ( .A(n1096), .B(n1095), .CI(n1094), .CO(n1122), .S(n1249) );
ADDFHX2TS U2251 ( .A(n1215), .B(n1216), .CI(n1214), .CO(n1827), .S(n1206) );
XNOR2X4TS U2252 ( .A(n2436), .B(n2399), .Y(n2415) );
CLKINVX3TS U2253 ( .A(n2156), .Y(n1410) );
ADDFHX2TS U2254 ( .A(n1657), .B(n1656), .CI(n1655), .CO(n1678), .S(n1683) );
ADDFHX2TS U2255 ( .A(n1586), .B(n1585), .CI(n1587), .CO(n1655), .S(n1658) );
ADDFHX2TS U2256 ( .A(n2023), .B(n2022), .CI(n2021), .CO(n2081), .S(n2036) );
ADDFHX2TS U2257 ( .A(n1459), .B(n1460), .CI(n1458), .CO(n1378), .S(n1477) );
ADDFHX2TS U2258 ( .A(n1529), .B(n1528), .CI(n1527), .CO(n1521), .S(n1689) );
ADDFHX2TS U2259 ( .A(n1803), .B(n1802), .CI(n1801), .CO(n1893), .S(n1778) );
ADDFHX2TS U2260 ( .A(n1663), .B(n1662), .CI(n1661), .CO(n1530), .S(n1677) );
ADDFHX2TS U2261 ( .A(n1347), .B(n1346), .CI(n1345), .CO(n1348), .S(n1729) );
ADDFHX2TS U2262 ( .A(n1728), .B(n1727), .CI(n1726), .CO(n1733), .S(n1736) );
XOR2X4TS U2263 ( .A(n907), .B(n906), .Y(n2055) );
ADDFHX2TS U2264 ( .A(n1601), .B(n1600), .CI(n1599), .CO(n1670), .S(n1602) );
ADDFHX2TS U2265 ( .A(n1457), .B(n1456), .CI(n1455), .CO(n1478), .S(n1421) );
NOR2X1TS U2266 ( .A(n2307), .B(n2306), .Y(n2933) );
ADDFHX2TS U2267 ( .A(n1510), .B(n1509), .CI(n1508), .CO(n2307), .S(n2305) );
ADDFHX2TS U2268 ( .A(n2016), .B(n2015), .CI(n2014), .CO(n2074), .S(n2012) );
OAI22X2TS U2269 ( .A0(n160), .A1(n986), .B0(n984), .B1(n196), .Y(n1002) );
ADDFHX2TS U2270 ( .A(n1675), .B(n1674), .CI(n1673), .CO(n1549), .S(n1691) );
ADDFHX2TS U2271 ( .A(n2239), .B(n2237), .CI(n2238), .CO(n2257), .S(n2195) );
ADDFHX2TS U2272 ( .A(n2252), .B(n2250), .CI(n2251), .CO(n2253), .S(n2238) );
ADDFHX2TS U2273 ( .A(n1604), .B(n1603), .CI(n1602), .CO(n1652), .S(n1651) );
ADDFHX2TS U2274 ( .A(n60), .B(n1612), .CI(n1611), .CO(n1600), .S(n1625) );
XOR2X4TS U2275 ( .A(Data_B_i[16]), .B(Data_B_i[4]), .Y(n899) );
NAND2X2TS U2276 ( .A(n2134), .B(n2133), .Y(n2227) );
ADDFHX2TS U2277 ( .A(n1920), .B(n1921), .CI(n1919), .CO(n1994), .S(n1953) );
ADDFHX2TS U2278 ( .A(n2171), .B(n2169), .CI(n2170), .CO(n2196), .S(n2133) );
ADDFHX2TS U2279 ( .A(n1099), .B(n1098), .CI(n1097), .CO(n1121), .S(n1247) );
ADDFHX2TS U2280 ( .A(n1085), .B(n1084), .CI(n1083), .CO(n1097), .S(n1273) );
ADDFHX2TS U2281 ( .A(n1373), .B(n1372), .CI(n1371), .CO(n1443), .S(n1377) );
ADDFHX2TS U2282 ( .A(n1954), .B(n1953), .CI(n1952), .CO(n2004), .S(n1918) );
ADDFHX2TS U2283 ( .A(n1265), .B(n1264), .CI(n1263), .CO(n1271), .S(n1333) );
ADDFHX2TS U2284 ( .A(n1322), .B(n1321), .CI(n1320), .CO(n1343), .S(n1439) );
ADDFHX2TS U2285 ( .A(n1049), .B(n1050), .CI(n1048), .CO(n1128), .S(n1062) );
ADDFHX2TS U2286 ( .A(n1513), .B(n1512), .CI(n1511), .CO(n2149), .S(n2148) );
ADDFHX2TS U2287 ( .A(n1495), .B(n1494), .CI(n1493), .CO(n1422), .S(n1511) );
ADDFHX4TS U2288 ( .A(n1713), .B(n1711), .CI(n1712), .CO(n1738), .S(n1735) );
ADDFHX2TS U2289 ( .A(n1705), .B(n1704), .CI(n1703), .CO(n1719), .S(n1712) );
ADDFHX2TS U2290 ( .A(n1185), .B(n1109), .CI(n1108), .CO(n1173), .S(n1094) );
XOR2X4TS U2291 ( .A(n624), .B(Data_B_i[14]), .Y(n923) );
ADDFHX2TS U2292 ( .A(n1406), .B(n1405), .CI(n1404), .CO(n1470), .S(n1418) );
AO21X4TS U2293 ( .A0(n173), .A1(n63), .B0(n1823), .Y(n1880) );
ADDFHX2TS U2294 ( .A(n1283), .B(n1284), .CI(n1282), .CO(n1291), .S(n1321) );
ADDFHX2TS U2295 ( .A(n1364), .B(n1363), .CI(n1362), .CO(n1440), .S(n1374) );
ADDFHX2TS U2296 ( .A(n1796), .B(n1795), .CI(n1794), .CO(n1860), .S(n1803) );
ADDFHX2TS U2297 ( .A(n1882), .B(n1880), .CI(n1881), .CO(n1948), .S(n1890) );
ADDFHX2TS U2298 ( .A(n2031), .B(n2030), .CI(n2029), .CO(n2078), .S(n2033) );
XNOR2X4TS U2299 ( .A(Data_B_i[3]), .B(Data_B_i[4]), .Y(n988) );
OR2X2TS U2300 ( .A(n1800), .B(n1071), .Y(n930) );
AO21X2TS U2301 ( .A0(n201), .A1(n242), .B0(n1799), .Y(n1857) );
XOR2X4TS U2302 ( .A(Data_B_i[5]), .B(Data_B_i[4]), .Y(n987) );
XOR2X4TS U2303 ( .A(Data_B_i[7]), .B(Data_B_i[6]), .Y(n979) );
XOR2X4TS U2304 ( .A(Data_B_i[19]), .B(Data_B_i[18]), .Y(n918) );
XNOR2X4TS U2305 ( .A(Data_B_i[9]), .B(Data_B_i[10]), .Y(n981) );
XOR2X4TS U2306 ( .A(n1043), .B(n1042), .Y(n1874) );
ADDFHX2TS U2307 ( .A(n1314), .B(n1313), .CI(n1312), .CO(n1290), .S(n1441) );
XNOR2X1TS U2308 ( .A(n2663), .B(n2662), .Y(n888) );
NOR2XLTS U2309 ( .A(n2721), .B(n2720), .Y(n2734) );
OR2X1TS U2310 ( .A(n2964), .B(n2963), .Y(n2966) );
NAND2X1TS U2311 ( .A(Data_A_i[19]), .B(Data_A_i[7]), .Y(n1019) );
NAND2X1TS U2312 ( .A(n893), .B(n903), .Y(n894) );
NAND2X1TS U2313 ( .A(n897), .B(n88), .Y(n898) );
XOR2X1TS U2314 ( .A(n279), .B(Data_B_i[16]), .Y(n900) );
NAND2X1TS U2315 ( .A(n331), .B(n951), .Y(n906) );
XOR2X4TS U2316 ( .A(Data_B_i[13]), .B(Data_B_i[14]), .Y(n922) );
XOR2X1TS U2317 ( .A(n911), .B(n910), .Y(n912) );
INVX1TS U2318 ( .A(n952), .Y(n916) );
NAND2X1TS U2319 ( .A(n916), .B(n950), .Y(n917) );
XNOR2X1TS U2320 ( .A(Data_B_i[19]), .B(Data_A_i[17]), .Y(n925) );
NOR2BX1TS U2321 ( .AN(Data_A_i[12]), .B(n89), .Y(n1068) );
XNOR2X1TS U2322 ( .A(n279), .B(Data_A_i[21]), .Y(n928) );
OAI22X1TS U2323 ( .A0(n529), .A1(n1267), .B0(n2018), .B1(n944), .Y(n1263) );
XNOR2X1TS U2324 ( .A(Data_B_i[19]), .B(Data_A_i[15]), .Y(n1266) );
XNOR2X1TS U2325 ( .A(Data_B_i[17]), .B(Data_A_i[17]), .Y(n1269) );
XNOR2X1TS U2326 ( .A(n279), .B(Data_A_i[19]), .Y(n1327) );
XNOR2X1TS U2327 ( .A(n624), .B(Data_A_i[20]), .Y(n929) );
XNOR2X1TS U2328 ( .A(Data_B_i[23]), .B(Data_A_i[13]), .Y(n932) );
OAI22X1TS U2329 ( .A0(n595), .A1(n929), .B0(n207), .B1(n928), .Y(n938) );
XNOR2X1TS U2330 ( .A(Data_B_i[17]), .B(Data_A_i[19]), .Y(n941) );
OAI22X1TS U2331 ( .A0(n942), .A1(n1432), .B0(n1800), .B1(n941), .Y(n1260) );
NAND2X1TS U2332 ( .A(n948), .B(n955), .Y(n949) );
INVX2TS U2333 ( .A(n949), .Y(n956) );
OAI22X1TS U2334 ( .A0(n1125), .A1(n176), .B0(n2243), .B1(n1086), .Y(n1006)
);
NAND2X1TS U2335 ( .A(n976), .B(n184), .Y(n977) );
OAI22X1TS U2336 ( .A0(n1119), .A1(n168), .B0(n1147), .B1(n184), .Y(n1004) );
XOR2X4TS U2337 ( .A(Data_B_i[5]), .B(Data_B_i[6]), .Y(n978) );
XNOR2X1TS U2338 ( .A(Data_B_i[7]), .B(Data_A_i[5]), .Y(n990) );
XNOR2X1TS U2339 ( .A(n132), .B(Data_A_i[6]), .Y(n1060) );
OAI22X1TS U2340 ( .A0(n174), .A1(n990), .B0(n206), .B1(n1060), .Y(n1064) );
INVX2TS U2341 ( .A(n1002), .Y(n983) );
INVX2TS U2342 ( .A(n186), .Y(n1133) );
XNOR2X4TS U2343 ( .A(Data_B_i[1]), .B(Data_B_i[2]), .Y(n1141) );
XNOR2X1TS U2344 ( .A(n65), .B(Data_A_i[9]), .Y(n992) );
XNOR2X1TS U2345 ( .A(n65), .B(Data_A_i[10]), .Y(n1061) );
XNOR2X1TS U2346 ( .A(Data_B_i[9]), .B(Data_A_i[2]), .Y(n1001) );
OAI22X1TS U2347 ( .A0(n2026), .A1(n1286), .B0(n2025), .B1(n1001), .Y(n1282)
);
XNOR2X1TS U2348 ( .A(Data_B_i[7]), .B(Data_A_i[4]), .Y(n991) );
XNOR2X1TS U2349 ( .A(Data_B_i[3]), .B(Data_A_i[7]), .Y(n1315) );
XNOR2X1TS U2350 ( .A(n65), .B(Data_A_i[8]), .Y(n993) );
OAI22X1TS U2351 ( .A0(n197), .A1(n1315), .B0(n128), .B1(n993), .Y(n1312) );
XNOR2X1TS U2352 ( .A(Data_B_i[11]), .B(Data_A_i[0]), .Y(n989) );
OAI22X1TS U2353 ( .A0(n197), .A1(n993), .B0(n128), .B1(n992), .Y(n994) );
XNOR2X1TS U2354 ( .A(Data_B_i[11]), .B(Data_A_i[2]), .Y(n1047) );
XNOR2X1TS U2355 ( .A(n66), .B(Data_A_i[8]), .Y(n1053) );
XNOR2X1TS U2356 ( .A(n67), .B(Data_A_i[3]), .Y(n1000) );
XNOR2X1TS U2357 ( .A(n67), .B(Data_A_i[4]), .Y(n1051) );
OAI22X1TS U2358 ( .A0(n573), .A1(n1000), .B0(n609), .B1(n1051), .Y(n1057) );
NOR2X1TS U2359 ( .A(n1014), .B(n1039), .Y(n1017) );
INVX2TS U2360 ( .A(n1018), .Y(n1020) );
NAND2X1TS U2361 ( .A(n1020), .B(n1019), .Y(n1021) );
INVX2TS U2362 ( .A(n1023), .Y(n1024) );
NAND2X1TS U2363 ( .A(n64), .B(n1026), .Y(n1027) );
XNOR2X1TS U2364 ( .A(n1807), .B(n1030), .Y(n1310) );
XOR2X1TS U2365 ( .A(n1035), .B(n1034), .Y(n1036) );
NAND2X1TS U2366 ( .A(n1041), .B(n1040), .Y(n1042) );
OAI22X1TS U2367 ( .A0(n1310), .A1(n192), .B0(n1092), .B1(n185), .Y(n1294) );
XNOR2X1TS U2368 ( .A(Data_A_i[3]), .B(n57), .Y(n1138) );
OAI22X1TS U2369 ( .A0(n164), .A1(n1047), .B0(n181), .B1(n1138), .Y(n1129) );
XNOR2X1TS U2370 ( .A(Data_B_i[9]), .B(Data_A_i[5]), .Y(n1136) );
OAI22X1TS U2371 ( .A0(n1825), .A1(n1053), .B0(n203), .B1(n1137), .Y(n1143)
);
XNOR2X1TS U2372 ( .A(Data_B_i[7]), .B(Data_A_i[7]), .Y(n1139) );
XNOR2X1TS U2373 ( .A(Data_B_i[3]), .B(Data_A_i[11]), .Y(n1142) );
XNOR2X1TS U2374 ( .A(n166), .B(Data_A_i[15]), .Y(n1104) );
OAI22X1TS U2375 ( .A0(n261), .A1(n1065), .B0(n575), .B1(n1104), .Y(n1096) );
INVX2TS U2376 ( .A(Data_A_i[13]), .Y(n1069) );
INVX2TS U2377 ( .A(n1241), .Y(n1185) );
OAI22X1TS U2378 ( .A0(n1432), .A1(n1071), .B0(n1800), .B1(n1103), .Y(n1108)
);
NAND2X1TS U2379 ( .A(n1077), .B(n1075), .Y(n1080) );
NAND3X1TS U2380 ( .A(n1080), .B(n1078), .C(n1079), .Y(n1099) );
XNOR2X1TS U2381 ( .A(Data_B_i[19]), .B(Data_A_i[19]), .Y(n1105) );
XNOR2X1TS U2382 ( .A(Data_B_i[15]), .B(Data_A_i[23]), .Y(n1107) );
INVX2TS U2383 ( .A(n1086), .Y(n1642) );
XNOR2X1TS U2384 ( .A(n1922), .B(n1030), .Y(n1123) );
XNOR2X1TS U2385 ( .A(n135), .B(Data_A_i[18]), .Y(n1181) );
XNOR2X1TS U2386 ( .A(n136), .B(Data_A_i[20]), .Y(n1188) );
INVX2TS U2387 ( .A(Data_A_i[14]), .Y(n1106) );
NOR2X1TS U2388 ( .A(n705), .B(n1106), .Y(n1186) );
OAI22X2TS U2389 ( .A0(n1565), .A1(n1107), .B0(n208), .B1(n1564), .Y(n1184)
);
XNOR2X1TS U2390 ( .A(Data_B_i[9]), .B(Data_A_i[6]), .Y(n1196) );
XNOR2X1TS U2391 ( .A(Data_B_i[5]), .B(Data_A_i[10]), .Y(n1197) );
XNOR2X1TS U2392 ( .A(Data_B_i[11]), .B(Data_A_i[4]), .Y(n1198) );
XNOR2X1TS U2393 ( .A(n132), .B(Data_A_i[8]), .Y(n1202) );
INVX2TS U2394 ( .A(Data_A_i[2]), .Y(n1140) );
OAI22X1TS U2395 ( .A0(n313), .A1(n176), .B0(n717), .B1(n2243), .Y(n1157) );
XNOR2X1TS U2396 ( .A(Data_B_i[21]), .B(Data_A_i[19]), .Y(n1237) );
OAI22X1TS U2397 ( .A0(n529), .A1(n1181), .B0(n2018), .B1(n1237), .Y(n1236)
);
INVX2TS U2398 ( .A(Data_A_i[15]), .Y(n1187) );
NOR2X1TS U2399 ( .A(n89), .B(n1187), .Y(n1240) );
XNOR2X1TS U2400 ( .A(n136), .B(Data_A_i[21]), .Y(n1233) );
OAI22X1TS U2401 ( .A0(n200), .A1(n1188), .B0(n1926), .B1(n1233), .Y(n1239)
);
XNOR2X1TS U2402 ( .A(n189), .B(Data_A_i[7]), .Y(n1217) );
XNOR2X1TS U2403 ( .A(Data_B_i[11]), .B(Data_A_i[5]), .Y(n1218) );
OAI22X1TS U2404 ( .A0(n164), .A1(n1198), .B0(n181), .B1(n1218), .Y(n1210) );
XNOR2X1TS U2405 ( .A(n132), .B(Data_A_i[9]), .Y(n1213) );
OAI22X1TS U2406 ( .A0(n175), .A1(n1202), .B0(n1942), .B1(n1213), .Y(n1219)
);
INVX2TS U2407 ( .A(Data_A_i[4]), .Y(n1211) );
NOR2X1TS U2408 ( .A(n421), .B(n1211), .Y(n1886) );
INVX1TS U2409 ( .A(n1886), .Y(n1820) );
OAI22X1TS U2410 ( .A0(n175), .A1(n1213), .B0(n206), .B1(n1817), .Y(n1818) );
XNOR2X1TS U2411 ( .A(n67), .B(Data_A_i[8]), .Y(n1822) );
XNOR2X1TS U2412 ( .A(Data_B_i[11]), .B(Data_A_i[6]), .Y(n1821) );
INVX2TS U2413 ( .A(n2327), .Y(n1774) );
INVX2TS U2414 ( .A(Data_A_i[16]), .Y(n1231) );
XNOR2X1TS U2415 ( .A(n190), .B(Data_A_i[20]), .Y(n1797) );
OAI22X1TS U2416 ( .A0(n2111), .A1(n1238), .B0(n2110), .B1(n1798), .Y(n1790)
);
XNOR2X1TS U2417 ( .A(n1874), .B(n623), .Y(n1810) );
OAI22X1TS U2418 ( .A0(n1242), .A1(n180), .B0(n1810), .B1(n209), .Y(n1785) );
XNOR2X1TS U2419 ( .A(n2055), .B(n177), .Y(n1812) );
OAI22X1TS U2420 ( .A0(n1251), .A1(n162), .B0(n1254), .B1(n202), .Y(n1347) );
NAND2BX1TS U2421 ( .AN(n1642), .B(n2000), .Y(n1255) );
OAI22X1TS U2422 ( .A0(n1610), .A1(n1330), .B0(n1261), .B1(n1640), .Y(n1329)
);
INVX2TS U2423 ( .A(n190), .Y(n2017) );
NAND2BX1TS U2424 ( .AN(n619), .B(n190), .Y(n1262) );
XNOR2X1TS U2425 ( .A(n136), .B(Data_A_i[14]), .Y(n1331) );
XNOR2X1TS U2426 ( .A(n190), .B(n619), .Y(n1268) );
XNOR2X1TS U2427 ( .A(Data_B_i[17]), .B(Data_A_i[16]), .Y(n1368) );
NAND2BX1TS U2428 ( .AN(Data_A_i[0]), .B(n189), .Y(n1281) );
XNOR2X1TS U2429 ( .A(Data_B_i[7]), .B(Data_A_i[2]), .Y(n1319) );
XNOR2X1TS U2430 ( .A(n67), .B(Data_A_i[0]), .Y(n1287) );
XNOR2X1TS U2431 ( .A(Data_B_i[5]), .B(Data_A_i[4]), .Y(n1359) );
XNOR2X1TS U2432 ( .A(Data_B_i[3]), .B(Data_A_i[6]), .Y(n1358) );
OAI22X1TS U2433 ( .A0(n197), .A1(n1358), .B0(n1580), .B1(n1315), .Y(n1364)
);
ADDHX1TS U2434 ( .A(n1317), .B(n1316), .CO(n1322), .S(n1363) );
XNOR2X1TS U2435 ( .A(n132), .B(Data_A_i[1]), .Y(n1389) );
XNOR2X1TS U2436 ( .A(n624), .B(Data_A_i[18]), .Y(n1367) );
XNOR2X1TS U2437 ( .A(n2055), .B(n1620), .Y(n1445) );
XNOR2X1TS U2438 ( .A(n153), .B(n1965), .Y(n1451) );
OAI22X1TS U2439 ( .A0(n1342), .A1(n187), .B0(n1451), .B1(n571), .Y(n1731) );
OAI22X1TS U2440 ( .A0(n1450), .A1(n156), .B0(n1382), .B1(n205), .Y(n1412) );
OAI22X1TS U2441 ( .A0(n1562), .A1(n1386), .B0(n1141), .B1(n1358), .Y(n1409)
);
OAI22X1TS U2442 ( .A0(n1385), .A1(n1619), .B0(n1360), .B1(n195), .Y(n1384)
);
OAI22X1TS U2443 ( .A0(n1432), .A1(n1397), .B0(n1800), .B1(n1368), .Y(n1459)
);
XNOR2X1TS U2444 ( .A(n1965), .B(n1620), .Y(n1480) );
XNOR2X1TS U2445 ( .A(n66), .B(Data_A_i[1]), .Y(n1424) );
XNOR2X1TS U2446 ( .A(Data_B_i[5]), .B(Data_A_i[2]), .Y(n1388) );
OAI22X1TS U2447 ( .A0(n173), .A1(n1424), .B0(n63), .B1(n1388), .Y(n1487) );
XNOR2X1TS U2448 ( .A(Data_B_i[3]), .B(Data_A_i[4]), .Y(n1483) );
XNOR2X1TS U2449 ( .A(n132), .B(n275), .Y(n1390) );
OAI22X1TS U2450 ( .A0(n175), .A1(n1390), .B0(n206), .B1(n1389), .Y(n1404) );
ADDHX1TS U2451 ( .A(n1392), .B(n1391), .CO(n1458), .S(n1423) );
NOR2BX1TS U2452 ( .AN(n619), .B(n1926), .Y(n1495) );
XNOR2X1TS U2453 ( .A(n520), .B(Data_A_i[13]), .Y(n1428) );
XNOR2X1TS U2454 ( .A(n520), .B(Data_A_i[14]), .Y(n1398) );
OAI22X1TS U2455 ( .A0(n201), .A1(n1428), .B0(n242), .B1(n1398), .Y(n1493) );
XNOR2X1TS U2456 ( .A(n279), .B(Data_A_i[16]), .Y(n1489) );
OAI22X1TS U2457 ( .A0(n201), .A1(n1398), .B0(n242), .B1(n1397), .Y(n1455) );
NAND2BX1TS U2458 ( .AN(n1642), .B(n1030), .Y(n1416) );
XNOR2X1TS U2459 ( .A(n1616), .B(n1030), .Y(n1461) );
XNOR2X1TS U2460 ( .A(n210), .B(n1030), .Y(n1417) );
XNOR2X1TS U2461 ( .A(Data_B_i[3]), .B(Data_A_i[2]), .Y(n1434) );
OAI22X1TS U2462 ( .A0(n197), .A1(n1434), .B0(n1580), .B1(n1484), .Y(n1520)
);
XNOR2X1TS U2463 ( .A(n66), .B(n275), .Y(n1425) );
OAI22X1TS U2464 ( .A0(n1619), .A1(n1433), .B0(n1426), .B1(n195), .Y(n1486)
);
NAND2BX1TS U2465 ( .AN(Data_A_i[0]), .B(n66), .Y(n1427) );
XNOR2X1TS U2466 ( .A(n624), .B(Data_A_i[14]), .Y(n1515) );
XNOR2X1TS U2467 ( .A(n624), .B(Data_A_i[15]), .Y(n1490) );
OAI22X1TS U2468 ( .A0(n595), .A1(n1515), .B0(n207), .B1(n1490), .Y(n1541) );
XNOR2X1TS U2469 ( .A(n520), .B(n158), .Y(n1429) );
OAI22X1TS U2470 ( .A0(n201), .A1(n1429), .B0(n1800), .B1(n1428), .Y(n1540)
);
OAI22X1TS U2471 ( .A0(n1432), .A1(n1799), .B0(n1800), .B1(n1431), .Y(n1491)
);
OAI22X1TS U2472 ( .A0(n1473), .A1(n1607), .B0(n1436), .B1(n571), .Y(n1531)
);
OAI22X1TS U2473 ( .A0(n1436), .A1(n187), .B0(n1542), .B1(n571), .Y(n1661) );
XNOR2X1TS U2474 ( .A(n1922), .B(n350), .Y(n1465) );
OAI22X1TS U2475 ( .A0(n1465), .A1(n571), .B0(n1451), .B1(n187), .Y(n1703) );
NOR2BX1TS U2476 ( .AN(n210), .B(n2058), .Y(n1476) );
OAI22X1TS U2477 ( .A0(n1472), .A1(n571), .B0(n1465), .B1(n187), .Y(n1466) );
XNOR2X1TS U2478 ( .A(n1922), .B(n1620), .Y(n1504) );
OAI22X1TS U2479 ( .A0(n1562), .A1(n1484), .B0(n128), .B1(n1483), .Y(n1510)
);
OAI22X1TS U2480 ( .A0(n595), .A1(n1490), .B0(n207), .B1(n1489), .Y(n1513) );
INVX2TS U2481 ( .A(n2149), .Y(n1505) );
XNOR2X1TS U2482 ( .A(n1874), .B(n1620), .Y(n1538) );
OAI22X1TS U2483 ( .A0(n1538), .A1(n977), .B0(n1504), .B1(n184), .Y(n1675) );
XNOR2X1TS U2484 ( .A(Data_B_i[13]), .B(Data_A_i[15]), .Y(n1546) );
XNOR2X1TS U2485 ( .A(n624), .B(Data_A_i[13]), .Y(n1547) );
INVX2TS U2486 ( .A(n2144), .Y(n1576) );
XNOR2X1TS U2487 ( .A(n1642), .B(n56), .Y(n1516) );
XNOR2X1TS U2488 ( .A(n1807), .B(n1620), .Y(n1577) );
OAI22X1TS U2489 ( .A0(n1619), .A1(n1557), .B0(n1543), .B1(n195), .Y(n1582)
);
XNOR2X1TS U2490 ( .A(n65), .B(Data_A_i[0]), .Y(n1545) );
INVX2TS U2491 ( .A(n2299), .Y(n1553) );
XNOR2X1TS U2492 ( .A(n624), .B(n158), .Y(n1548) );
NOR2BX1TS U2493 ( .AN(n210), .B(n1872), .Y(n1552) );
NAND2X1TS U2494 ( .A(n1558), .B(n1610), .Y(n2518) );
XNOR2X1TS U2495 ( .A(Data_B_i[13]), .B(Data_A_i[13]), .Y(n1609) );
OAI22X1TS U2496 ( .A0(n194), .A1(n1609), .B0(n1559), .B1(n1640), .Y(n2139)
);
INVX1TS U2497 ( .A(n2139), .Y(n1613) );
NAND2BX1TS U2498 ( .AN(Data_A_i[12]), .B(n624), .Y(n1563) );
XNOR2X1TS U2499 ( .A(n621), .B(n1620), .Y(n1584) );
OAI22X1TS U2500 ( .A0(n1577), .A1(n1641), .B0(n1584), .B1(n168), .Y(n1660)
);
NOR2BX1TS U2501 ( .AN(n619), .B(n1579), .Y(n2138) );
ADDHX1TS U2502 ( .A(n1582), .B(n1581), .CO(n2299), .S(n2296) );
OAI22X1TS U2503 ( .A0(n1584), .A1(n1641), .B0(n1592), .B1(n168), .Y(n1596)
);
XNOR2X1TS U2504 ( .A(n1642), .B(n152), .Y(n1589) );
OAI22X1TS U2505 ( .A0(n1590), .A1(n1607), .B0(n913), .B1(n1589), .Y(n1628)
);
XNOR2X1TS U2506 ( .A(n1606), .B(n1605), .Y(n1634) );
NOR2BX1TS U2507 ( .AN(n1642), .B(n1607), .Y(n1633) );
INVX2TS U2508 ( .A(n2888), .Y(n1623) );
OAI22X1TS U2509 ( .A0(n1610), .A1(n619), .B0(n1609), .B1(n1640), .Y(n2517)
);
OAI22X1TS U2510 ( .A0(n1619), .A1(n275), .B0(n1618), .B1(n196), .Y(n2887) );
NOR2BX1TS U2511 ( .AN(n275), .B(n195), .Y(n2885) );
NOR2BX1TS U2512 ( .AN(n158), .B(n1640), .Y(n2504) );
INVX2TS U2513 ( .A(n2504), .Y(n2412) );
NOR2BX1TS U2514 ( .AN(n210), .B(n184), .Y(n2411) );
INVX2TS U2515 ( .A(n2365), .Y(n1686) );
ADDFHX4TS U2516 ( .A(n1719), .B(n1718), .CI(n1717), .CO(n1757), .S(n1739) );
INVX2TS U2517 ( .A(n2499), .Y(n1748) );
ADDFHX4TS U2518 ( .A(n1775), .B(n55), .CI(n1774), .CO(n1848), .S(n1836) );
ADDFHX2TS U2519 ( .A(n1790), .B(n1791), .CI(n1789), .CO(n1895), .S(n1801) );
INVX2TS U2520 ( .A(Data_A_i[17]), .Y(n1792) );
NOR2X1TS U2521 ( .A(n220), .B(n1792), .Y(n1864) );
XNOR2X1TS U2522 ( .A(n135), .B(Data_A_i[21]), .Y(n1869) );
OAI22X1TS U2523 ( .A0(n576), .A1(n176), .B0(n1808), .B1(n2243), .Y(n1898) );
OAI22X1TS U2524 ( .A0(n1856), .A1(n162), .B0(n1811), .B1(n202), .Y(n1854) );
OAI22X1TS U2525 ( .A0(n1812), .A1(n192), .B0(n1855), .B1(n185), .Y(n1853) );
INVX2TS U2526 ( .A(Data_A_i[5]), .Y(n1816) );
NOR2X1TS U2527 ( .A(n421), .B(n1816), .Y(n1885) );
XNOR2X1TS U2528 ( .A(Data_B_i[7]), .B(Data_A_i[11]), .Y(n1887) );
XNOR2X1TS U2529 ( .A(n189), .B(Data_A_i[9]), .Y(n1889) );
OAI22X1TS U2530 ( .A0(n573), .A1(n1822), .B0(n2025), .B1(n1889), .Y(n1881)
);
OAI2BB1X2TS U2531 ( .A0N(n1840), .A1N(n1839), .B0(n1838), .Y(n1841) );
XNOR2X1TS U2532 ( .A(n2055), .B(n772), .Y(n1908) );
OAI22X1TS U2533 ( .A0(n261), .A1(n1862), .B0(n575), .B1(n1925), .Y(n1935) );
INVX2TS U2534 ( .A(Data_A_i[18]), .Y(n1866) );
XNOR2X1TS U2535 ( .A(Data_A_i[22]), .B(n135), .Y(n1929) );
INVX2TS U2536 ( .A(n1874), .Y(n1923) );
OAI22X1TS U2537 ( .A0(n576), .A1(n2243), .B0(n1923), .B1(n176), .Y(n1910) );
XNOR2X1TS U2538 ( .A(n57), .B(Data_A_i[8]), .Y(n1941) );
INVX2TS U2539 ( .A(Data_A_i[6]), .Y(n1888) );
INVX2TS U2540 ( .A(n1968), .Y(n1937) );
OAI22X1TS U2541 ( .A0(n2002), .A1(n2185), .B0(n1907), .B1(n180), .Y(n1999)
);
XNOR2X1TS U2542 ( .A(n2125), .B(n772), .Y(n2001) );
INVX2TS U2543 ( .A(Data_A_i[19]), .Y(n1928) );
NOR2X1TS U2544 ( .A(n705), .B(n1928), .Y(n1978) );
XNOR2X1TS U2545 ( .A(n57), .B(Data_A_i[9]), .Y(n1971) );
INVX2TS U2546 ( .A(Data_A_i[7]), .Y(n1944) );
INVX2TS U2547 ( .A(n1965), .Y(n2039) );
INVX2TS U2548 ( .A(Data_A_i[8]), .Y(n1969) );
XNOR2X1TS U2549 ( .A(n188), .B(Data_A_i[10]), .Y(n2028) );
OAI22X1TS U2550 ( .A0(n164), .A1(n1971), .B0(n2028), .B1(n181), .Y(n2029) );
INVX2TS U2551 ( .A(Data_A_i[20]), .Y(n1980) );
INVX1TS U2552 ( .A(n2069), .Y(n2023) );
XNOR2X1TS U2553 ( .A(n2071), .B(n772), .Y(n2038) );
OAI22X1TS U2554 ( .A0(n2001), .A1(n202), .B0(n2038), .B1(n162), .Y(n2044) );
XNOR2X1TS U2555 ( .A(n2055), .B(n623), .Y(n2013) );
OAI22X1TS U2556 ( .A0(n2002), .A1(n180), .B0(n2013), .B1(n209), .Y(n2043) );
XNOR2X1TS U2557 ( .A(n623), .B(n2125), .Y(n2072) );
OAI22X1TS U2558 ( .A0(n2013), .A1(n180), .B0(n2072), .B1(n209), .Y(n2075) );
INVX2TS U2559 ( .A(Data_A_i[21]), .Y(n2019) );
NOR2X1TS U2560 ( .A(n89), .B(n2019), .Y(n2068) );
INVX2TS U2561 ( .A(Data_A_i[9]), .Y(n2027) );
NOR2X1TS U2562 ( .A(n204), .B(n2027), .Y(n2063) );
INVX2TS U2563 ( .A(n2343), .Y(n2077) );
INVX2TS U2564 ( .A(n2344), .Y(n2076) );
INVX2TS U2565 ( .A(n2704), .Y(n2086) );
CLKINVX1TS U2566 ( .A(n596), .Y(n2056) );
OAI22X1TS U2567 ( .A0(n2056), .A1(n176), .B0(n2039), .B1(n2243), .Y(n2084)
);
CLKINVX1TS U2568 ( .A(n2055), .Y(n2126) );
OAI22X1TS U2569 ( .A0(n2056), .A1(n165), .B0(n2126), .B1(n176), .Y(n2121) );
AO21X1TS U2570 ( .A0(n2059), .A1(n771), .B0(n2057), .Y(n2124) );
INVX2TS U2571 ( .A(Data_A_i[10]), .Y(n2060) );
INVX2TS U2572 ( .A(Data_A_i[22]), .Y(n2065) );
NOR2X1TS U2573 ( .A(n705), .B(n2065), .Y(n2183) );
INVX1TS U2574 ( .A(n2183), .Y(n2108) );
OAI22X1TS U2575 ( .A0(n261), .A1(n2066), .B0(n575), .B1(n705), .Y(n2107) );
INVX2TS U2576 ( .A(n2720), .Y(n2122) );
XNOR2X1TS U2577 ( .A(n2071), .B(n623), .Y(n2118) );
OAI22X1TS U2578 ( .A0(n2072), .A1(n180), .B0(n2118), .B1(n2185), .Y(n2119)
);
INVX2TS U2579 ( .A(n2350), .Y(n2129) );
INVX2TS U2580 ( .A(n2721), .Y(n2128) );
INVX2TS U2581 ( .A(n2703), .Y(n2127) );
INVX2TS U2582 ( .A(n2166), .Y(n2099) );
INVX2TS U2583 ( .A(n2167), .Y(n2098) );
CMPR32X2TS U2584 ( .A(n2108), .B(n2107), .C(n2106), .CO(n2737), .S(n2720) );
INVX2TS U2585 ( .A(n2737), .Y(n2191) );
INVX2TS U2586 ( .A(Data_A_i[23]), .Y(n2109) );
NOR2X1TS U2587 ( .A(n705), .B(n2109), .Y(n2182) );
INVX2TS U2588 ( .A(Data_A_i[11]), .Y(n2112) );
INVX2TS U2589 ( .A(n2488), .Y(n2188) );
INVX2TS U2590 ( .A(n2489), .Y(n2187) );
OAI22X1TS U2591 ( .A0(n2118), .A1(n180), .B0(n2185), .B1(n420), .Y(n2189) );
CLKINVX1TS U2592 ( .A(n2125), .Y(n2176) );
OAI22X1TS U2593 ( .A0(n2126), .A1(n165), .B0(n2176), .B1(n176), .Y(n2173) );
INVX2TS U2594 ( .A(n2220), .Y(n2135) );
NAND2X1TS U2595 ( .A(n2135), .B(n2227), .Y(n2136) );
XOR2X4TS U2596 ( .A(n2137), .B(n2136), .Y(n2587) );
NAND2X1TS U2597 ( .A(n104), .B(n105), .Y(n2161) );
NOR2X1TS U2598 ( .A(n2152), .B(n2151), .Y(n2539) );
NOR2X1TS U2599 ( .A(n2150), .B(n2149), .Y(n2546) );
NAND2X1TS U2600 ( .A(n2518), .B(n2517), .Y(n2519) );
NAND2X1TS U2601 ( .A(n2139), .B(n2138), .Y(n2510) );
NAND2X1TS U2602 ( .A(n2140), .B(n2141), .Y(n2283) );
NAND2X1TS U2603 ( .A(n2143), .B(n2142), .Y(n2276) );
NAND2X1TS U2604 ( .A(n2145), .B(n2144), .Y(n2571) );
NAND2X1TS U2605 ( .A(n2147), .B(n2148), .Y(n2560) );
OAI21X1TS U2606 ( .A0(n2562), .A1(n2559), .B0(n2560), .Y(n2538) );
NAND2X1TS U2607 ( .A(n2150), .B(n2149), .Y(n2547) );
NAND2X1TS U2608 ( .A(n2151), .B(n2152), .Y(n2540) );
NAND2X1TS U2609 ( .A(n2156), .B(n2155), .Y(n2210) );
NAND2X1TS U2610 ( .A(n2158), .B(n2157), .Y(n2217) );
AOI21X1TS U2611 ( .A0(n104), .A1(n2215), .B0(n2159), .Y(n2160) );
NAND2X1TS U2612 ( .A(n2163), .B(n2162), .Y(n2261) );
NAND2X1TS U2613 ( .A(n2164), .B(n2261), .Y(n2165) );
XOR2X1TS U2614 ( .A(n2200), .B(n2165), .Y(n2586) );
CMPR32X2TS U2615 ( .A(n2174), .B(n2173), .C(n2172), .CO(n2239), .S(n2192) );
OAI22X1TS U2616 ( .A0(n2176), .A1(n165), .B0(n176), .B1(n2244), .Y(n2252) );
CMPR32X2TS U2617 ( .A(n2179), .B(n2178), .C(n2177), .CO(n2180), .S(n2488) );
INVX2TS U2618 ( .A(n2180), .Y(n2242) );
AO21X1TS U2619 ( .A0(n2186), .A1(n2185), .B0(n420), .Y(n2240) );
NAND2X1TS U2620 ( .A(n2196), .B(n2195), .Y(n2225) );
NAND2X1TS U2621 ( .A(n2197), .B(n2225), .Y(n2198) );
NOR2X1TS U2622 ( .A(n2201), .B(n2202), .Y(n2262) );
NAND2X1TS U2623 ( .A(n2202), .B(n2201), .Y(n2260) );
NAND2X1TS U2624 ( .A(n2203), .B(n2260), .Y(n2204) );
XNOR2X1TS U2625 ( .A(n2205), .B(n2204), .Y(n2588) );
NAND2X1TS U2626 ( .A(n2206), .B(n2231), .Y(n2207) );
NAND2X1TS U2627 ( .A(n105), .B(n2210), .Y(n2211) );
XNOR2X1TS U2628 ( .A(n2216), .B(n2211), .Y(n2584) );
INVX2TS U2629 ( .A(n2212), .Y(n2221) );
NAND2X1TS U2630 ( .A(n2221), .B(n2224), .Y(n2213) );
AOI21X1TS U2631 ( .A0(n2216), .A1(n105), .B0(n2215), .Y(n2219) );
NAND2X1TS U2632 ( .A(n104), .B(n2217), .Y(n2218) );
NOR2X2TS U2633 ( .A(n2780), .B(n2787), .Y(n2754) );
CMPR32X2TS U2634 ( .A(n2242), .B(n2241), .C(n2240), .CO(n2246), .S(n2248) );
XNOR2X1TS U2635 ( .A(n2246), .B(n2245), .Y(n2255) );
CMPR32X2TS U2636 ( .A(n2249), .B(n2248), .C(n2247), .CO(n2254), .S(n2251) );
NAND2X1TS U2637 ( .A(n2257), .B(n2256), .Y(n2258) );
INVX2TS U2638 ( .A(n2635), .Y(n2614) );
NAND2X1TS U2639 ( .A(n2266), .B(n2267), .Y(n2604) );
NAND2X1TS U2640 ( .A(n2595), .B(n2604), .Y(n2268) );
XNOR2X1TS U2641 ( .A(n2614), .B(n2268), .Y(n2591) );
NOR2X1TS U2642 ( .A(n155), .B(n2727), .Y(n2593) );
CLKINVX1TS U2643 ( .A(n2269), .Y(n2281) );
NAND2X1TS U2644 ( .A(n58), .B(n2272), .Y(n2273) );
NAND2X1TS U2645 ( .A(n2277), .B(n2276), .Y(n2279) );
NOR2X2TS U2646 ( .A(n2530), .B(n2529), .Y(n2844) );
NAND2X1TS U2647 ( .A(n2280), .B(n2281), .Y(n2282) );
NAND2X1TS U2648 ( .A(n2284), .B(n2283), .Y(n2286) );
XNOR2X1TS U2649 ( .A(n2286), .B(n2285), .Y(n2527) );
NOR2X1TS U2650 ( .A(n2528), .B(n2527), .Y(n2842) );
NOR2X1TS U2651 ( .A(n2844), .B(n2842), .Y(n2532) );
INVX2TS U2652 ( .A(n2293), .Y(n2948) );
NAND2X1TS U2653 ( .A(n2951), .B(n2948), .Y(n2316) );
NOR2X1TS U2654 ( .A(n2935), .B(n2933), .Y(n2311) );
NAND2X1TS U2655 ( .A(n2888), .B(n2887), .Y(n2896) );
NAND2X1TS U2656 ( .A(n2295), .B(n2294), .Y(n2894) );
OAI21X1TS U2657 ( .A0(n2893), .A1(n2896), .B0(n2894), .Y(n2902) );
NAND2X1TS U2658 ( .A(n2297), .B(n2296), .Y(n2900) );
NAND2X1TS U2659 ( .A(n2300), .B(n2299), .Y(n2907) );
NAND2X1TS U2660 ( .A(n2302), .B(n2301), .Y(n2913) );
NAND2X1TS U2661 ( .A(n2306), .B(n2307), .Y(n2932) );
NAND2X1TS U2662 ( .A(n2309), .B(n2308), .Y(n2936) );
OAI21X1TS U2663 ( .A0(n2935), .A1(n2932), .B0(n2936), .Y(n2310) );
INVX2TS U2664 ( .A(n2943), .Y(n2947) );
NAND2X1TS U2665 ( .A(n2314), .B(n2313), .Y(n2950) );
NAND2X1TS U2666 ( .A(n2317), .B(n2318), .Y(n2957) );
NAND2X1TS U2667 ( .A(n618), .B(n2319), .Y(n2407) );
NAND2X1TS U2668 ( .A(n2322), .B(n2321), .Y(n2397) );
NAND2X1TS U2669 ( .A(n2324), .B(n2323), .Y(n2388) );
NAND2X1TS U2670 ( .A(n2326), .B(n2325), .Y(n2432) );
NAND2X1TS U2671 ( .A(n149), .B(n2327), .Y(n2439) );
NOR2X1TS U2672 ( .A(n2332), .B(n2331), .Y(n2379) );
NAND2X1TS U2673 ( .A(n2382), .B(n2373), .Y(n2340) );
NOR2X1TS U2674 ( .A(n2379), .B(n2340), .Y(n2478) );
NOR2X1TS U2675 ( .A(n2341), .B(n2342), .Y(n2358) );
NAND2X1TS U2676 ( .A(n2467), .B(n106), .Y(n2477) );
NAND2X1TS U2677 ( .A(n2332), .B(n2331), .Y(n2448) );
NAND2X1TS U2678 ( .A(n2333), .B(n2334), .Y(n2381) );
NAND2X1TS U2679 ( .A(n2335), .B(n2336), .Y(n2372) );
AOI21X1TS U2680 ( .A0(n2373), .A1(n2338), .B0(n2337), .Y(n2339) );
OAI21X1TS U2681 ( .A0(n2340), .A1(n2448), .B0(n2339), .Y(n2484) );
NAND2X1TS U2682 ( .A(n2342), .B(n2341), .Y(n2466) );
NAND2X1TS U2683 ( .A(n2343), .B(n2344), .Y(n2362) );
AOI21X1TS U2684 ( .A0(n2346), .A1(n106), .B0(n2345), .Y(n2481) );
AOI21X1TS U2685 ( .A0(n2487), .A1(n2348), .B0(n2347), .Y(n2353) );
NAND2X1TS U2686 ( .A(n2350), .B(n2349), .Y(n2479) );
NAND2X1TS U2687 ( .A(n2351), .B(n2479), .Y(n2352) );
NAND2X1TS U2688 ( .A(n2354), .B(n143), .Y(n2355) );
NAND2X1TS U2689 ( .A(n106), .B(n2362), .Y(n2363) );
XOR2X1TS U2690 ( .A(n2364), .B(n2363), .Y(n2472) );
AOI21X1TS U2691 ( .A0(n2487), .A1(n2371), .B0(n2370), .Y(n2375) );
NAND2X1TS U2692 ( .A(n2373), .B(n2372), .Y(n2374) );
XOR2X1TS U2693 ( .A(n2378), .B(n2377), .Y(n2460) );
NAND2X1TS U2694 ( .A(n2382), .B(n2381), .Y(n2383) );
NAND2X1TS U2695 ( .A(n2394), .B(n2393), .Y(n2396) );
NAND2X1TS U2696 ( .A(n2401), .B(n2400), .Y(n2403) );
INVX2TS U2697 ( .A(n2404), .Y(n2971) );
NAND2XLTS U2698 ( .A(n2408), .B(n2407), .Y(n2409) );
AFHCONX2TS U2699 ( .A(n2413), .B(n2412), .CI(n2411), .CON(n2402), .S(n2963)
);
NAND2X1TS U2700 ( .A(n2415), .B(n2414), .Y(n2970) );
INVX2TS U2701 ( .A(n2970), .Y(n2416) );
NAND2X1TS U2702 ( .A(n2418), .B(n2417), .Y(n2978) );
AOI21X1TS U2703 ( .A0(n2436), .A1(n2429), .B0(n2431), .Y(n2421) );
NAND2X1TS U2704 ( .A(n2423), .B(n2422), .Y(n2425) );
XNOR2X1TS U2705 ( .A(n2425), .B(n2424), .Y(n2426) );
NAND2X1TS U2706 ( .A(n2427), .B(n2426), .Y(n2985) );
INVX2TS U2707 ( .A(n2985), .Y(n2428) );
OAI21X1TS U2708 ( .A0(n2434), .A1(n2433), .B0(n2432), .Y(n2435) );
AOI21X1TS U2709 ( .A0(n2437), .A1(n2436), .B0(n2435), .Y(n2442) );
NAND2X1TS U2710 ( .A(n2444), .B(n2445), .Y(n2447) );
XOR2X1TS U2711 ( .A(n2447), .B(n2446), .Y(n2453) );
NAND2X1TS U2712 ( .A(n2449), .B(n2448), .Y(n2450) );
INVX2TS U2713 ( .A(n2991), .Y(n2813) );
NAND2X1TS U2714 ( .A(n2462), .B(n2461), .Y(n3000) );
AOI21X1TS U2715 ( .A0(n2487), .A1(n2478), .B0(n2484), .Y(n2469) );
NAND2X1TS U2716 ( .A(n2467), .B(n2466), .Y(n2468) );
NAND2X1TS U2717 ( .A(n2471), .B(n2470), .Y(n2821) );
AO21X1TS U2718 ( .A0(n2484), .A1(n2483), .B0(n2482), .Y(n2485) );
AOI21X1TS U2719 ( .A0(n2487), .A1(n2486), .B0(n2485), .Y(n2493) );
NAND2X1TS U2720 ( .A(n2489), .B(n2488), .Y(n2490) );
NAND2X1TS U2721 ( .A(n2491), .B(n2490), .Y(n2492) );
NAND2X1TS U2722 ( .A(n2499), .B(n2500), .Y(n2501) );
INVX2TS U2723 ( .A(n2831), .Y(n2506) );
NAND2X1TS U2724 ( .A(n2511), .B(n2510), .Y(n2512) );
XOR2X1TS U2725 ( .A(n2512), .B(n2519), .Y(n2522) );
INVX2TS U2726 ( .A(n2879), .Y(n2524) );
NAND2X1TS U2727 ( .A(n2528), .B(n2527), .Y(n2841) );
CLKINVX1TS U2728 ( .A(n2534), .Y(n2536) );
NAND2X1TS U2729 ( .A(n2536), .B(n2535), .Y(n2537) );
NAND2X1TS U2730 ( .A(n2541), .B(n2540), .Y(n2542) );
XNOR2X1TS U2731 ( .A(n2543), .B(n2542), .Y(n2581) );
NAND2X1TS U2732 ( .A(n2548), .B(n2547), .Y(n2549) );
XOR2X1TS U2733 ( .A(n2550), .B(n2549), .Y(n2579) );
XOR2X4TS U2734 ( .A(n2558), .B(n2557), .Y(n2578) );
NAND2X1TS U2735 ( .A(n2561), .B(n2560), .Y(n2563) );
XOR2X1TS U2736 ( .A(n2563), .B(n2562), .Y(n2577) );
CLKINVX1TS U2737 ( .A(n2566), .Y(n2567) );
NAND2X1TS U2738 ( .A(n2568), .B(n2567), .Y(n2569) );
XOR2X1TS U2739 ( .A(n2570), .B(n2569), .Y(n2576) );
NAND2X1TS U2740 ( .A(n2572), .B(n2571), .Y(n2574) );
XNOR2X1TS U2741 ( .A(n2574), .B(n2573), .Y(n2575) );
NOR2X1TS U2742 ( .A(n2576), .B(n2575), .Y(n2760) );
NOR2X2TS U2743 ( .A(n2762), .B(n2760), .Y(n2800) );
NAND2X2TS U2744 ( .A(n2582), .B(n2581), .Y(n2796) );
OAI21X1TS U2745 ( .A0(n2774), .A1(n2727), .B0(n2744), .Y(n2592) );
AOI21X1TS U2746 ( .A0(n2614), .A1(n2595), .B0(n2594), .Y(n2600) );
NAND2X1TS U2747 ( .A(n2597), .B(n2596), .Y(n2603) );
XOR2X1TS U2748 ( .A(n2600), .B(n2599), .Y(n2639) );
INVX1TS U2749 ( .A(n2639), .Y(n2601) );
AOI21X1TS U2750 ( .A0(n2614), .A1(n2627), .B0(n2633), .Y(n2610) );
NOR2X1TS U2751 ( .A(n2606), .B(n102), .Y(n2626) );
NAND2X1TS U2752 ( .A(n102), .B(n2606), .Y(n2629) );
NAND2X1TS U2753 ( .A(n2644), .B(n2639), .Y(n2646) );
AOI21X1TS U2754 ( .A0(n2615), .A1(n2614), .B0(n2613), .Y(n2620) );
NAND2X1TS U2755 ( .A(n2617), .B(n2616), .Y(n2628) );
NAND2X1TS U2756 ( .A(n2618), .B(n2628), .Y(n2619) );
NOR2X1TS U2757 ( .A(n2646), .B(n889), .Y(n2665) );
INVX1TS U2758 ( .A(n2665), .Y(n2621) );
NOR2X1TS U2759 ( .A(n155), .B(n2623), .Y(n2625) );
OAI21X1TS U2760 ( .A0(n2774), .A1(n2623), .B0(n2622), .Y(n2624) );
NAND2X1TS U2761 ( .A(n2627), .B(n2632), .Y(n2636) );
AOI21X1TS U2762 ( .A0(n2633), .A1(n2632), .B0(n2631), .Y(n2634) );
NAND2X1TS U2763 ( .A(n2659), .B(n2687), .Y(n2638) );
INVX2TS U2764 ( .A(n2653), .Y(n2664) );
NAND2X1TS U2765 ( .A(n2768), .B(n2639), .Y(n2641) );
NOR2X1TS U2766 ( .A(n155), .B(n2641), .Y(n2643) );
NAND2X1TS U2767 ( .A(n2771), .B(n2639), .Y(n2640) );
OAI21X1TS U2768 ( .A0(n2774), .A1(n2641), .B0(n2640), .Y(n2642) );
NAND2X1TS U2769 ( .A(n2768), .B(n2647), .Y(n2649) );
NOR2X1TS U2770 ( .A(n155), .B(n2649), .Y(n2651) );
NAND2X1TS U2771 ( .A(n2771), .B(n2647), .Y(n2648) );
NAND2X1TS U2772 ( .A(n2654), .B(n2653), .Y(n2655) );
AOI21X1TS U2773 ( .A0(n2719), .A1(n2659), .B0(n2658), .Y(n2663) );
NAND2X1TS U2774 ( .A(n2661), .B(n2660), .Y(n2682) );
NAND2X1TS U2775 ( .A(n2680), .B(n2682), .Y(n2662) );
NAND2X1TS U2776 ( .A(n2768), .B(n2666), .Y(n2668) );
NOR2X1TS U2777 ( .A(n155), .B(n2668), .Y(n2670) );
NAND2X1TS U2778 ( .A(n2771), .B(n2666), .Y(n2667) );
AOI21X1TS U2779 ( .A0(n2719), .A1(n2673), .B0(n2672), .Y(n2676) );
NAND2X1TS U2780 ( .A(n885), .B(n2683), .Y(n2675) );
NAND2X1TS U2781 ( .A(n2771), .B(n2695), .Y(n2678) );
NAND2X1TS U2782 ( .A(n2680), .B(n885), .Y(n2688) );
AOI21X1TS U2783 ( .A0(n885), .A1(n2685), .B0(n2684), .Y(n2686) );
AOI21X1TS U2784 ( .A0(n2719), .A1(n2696), .B0(n2700), .Y(n2692) );
NAND2X1TS U2785 ( .A(n2690), .B(n2689), .Y(n2697) );
NAND2X1TS U2786 ( .A(n2699), .B(n2697), .Y(n2691) );
XOR2X1TS U2787 ( .A(n2692), .B(n2691), .Y(n2694) );
INVX2TS U2788 ( .A(n2694), .Y(n2693) );
NAND2X1TS U2789 ( .A(n2696), .B(n2699), .Y(n2713) );
AOI21X1TS U2790 ( .A0(n2700), .A1(n2699), .B0(n2698), .Y(n2716) );
AOI21X1TS U2791 ( .A0(n2719), .A1(n2702), .B0(n2701), .Y(n2707) );
NAND2X1TS U2792 ( .A(n2704), .B(n2703), .Y(n2714) );
NAND2X1TS U2793 ( .A(n2705), .B(n2714), .Y(n2706) );
INVX2TS U2794 ( .A(n2708), .Y(n2777) );
NAND2X1TS U2795 ( .A(n2768), .B(n2726), .Y(n2710) );
NOR2X1TS U2796 ( .A(n155), .B(n2710), .Y(n2712) );
NAND2X1TS U2797 ( .A(n2771), .B(n2726), .Y(n2709) );
AOI21X1TS U2798 ( .A0(n2719), .A1(n2718), .B0(n2717), .Y(n2735) );
NAND2X1TS U2799 ( .A(n2721), .B(n2720), .Y(n2733) );
NAND2X1TS U2800 ( .A(n2722), .B(n2733), .Y(n2723) );
INVX2TS U2801 ( .A(n2725), .Y(n2724) );
NAND2X1TS U2802 ( .A(n2726), .B(n2725), .Y(n2728) );
OR2X2TS U2803 ( .A(n2744), .B(n2728), .Y(n2729) );
OAI21X1TS U2804 ( .A0(n2774), .A1(n2730), .B0(n2729), .Y(n2731) );
NAND2X1TS U2805 ( .A(n2739), .B(n2738), .Y(n2740) );
INVX2TS U2806 ( .A(n2746), .Y(n2747) );
NAND2X1TS U2807 ( .A(n2757), .B(n2756), .Y(n2758) );
INVX2TS U2808 ( .A(load_b_i), .Y(n3007) );
CLKINVX1TS U2809 ( .A(n2760), .Y(n2806) );
CLKINVX1TS U2810 ( .A(n2805), .Y(n2761) );
AOI21X1TS U2811 ( .A0(n2808), .A1(n2806), .B0(n2761), .Y(n2766) );
CLKINVX1TS U2812 ( .A(n2762), .Y(n2764) );
NAND2X1TS U2813 ( .A(n2768), .B(n2770), .Y(n2773) );
NAND2X1TS U2814 ( .A(n2771), .B(n2770), .Y(n2772) );
NAND2X1TS U2815 ( .A(n2786), .B(n2784), .Y(n2781) );
INVX2TS U2816 ( .A(load_b_i), .Y(n2975) );
CLKINVX1TS U2817 ( .A(n2787), .Y(n2788) );
NAND2X1TS U2818 ( .A(n2789), .B(n2788), .Y(n2790) );
CLKINVX1TS U2819 ( .A(n2800), .Y(n2791) );
CLKINVX1TS U2820 ( .A(n2795), .Y(n2797) );
NAND2X1TS U2821 ( .A(n2796), .B(n2797), .Y(n2798) );
CLKINVX1TS U2822 ( .A(n2801), .Y(n2803) );
NAND2XLTS U2823 ( .A(n2806), .B(n2805), .Y(n2807) );
XNOR2X1TS U2824 ( .A(n2808), .B(n2807), .Y(n2809) );
INVX2TS U2826 ( .A(n2812), .Y(n2993) );
AOI21X1TS U2827 ( .A0(n2993), .A1(n884), .B0(n2813), .Y(n2817) );
NAND2X1TS U2828 ( .A(n2815), .B(n2814), .Y(n2816) );
NAND2X1TS U2829 ( .A(n2892), .B(sgf_result_o[17]), .Y(n2818) );
OAI2BB1X1TS U2830 ( .A0N(n747), .A1N(n2819), .B0(n2818), .Y(n33) );
NAND2X1TS U2831 ( .A(n2821), .B(n2822), .Y(n2823) );
NAND2X1TS U2832 ( .A(n2892), .B(sgf_result_o[20]), .Y(n2824) );
OAI2BB1X1TS U2833 ( .A0N(load_b_i), .A1N(n2825), .B0(n2824), .Y(n30) );
NAND2X1TS U2834 ( .A(n2892), .B(sgf_result_o[21]), .Y(n2829) );
NAND2X1TS U2835 ( .A(n2832), .B(n2831), .Y(n2834) );
XNOR2X1TS U2836 ( .A(n2834), .B(n2833), .Y(n2836) );
NAND2X1TS U2837 ( .A(n3005), .B(sgf_result_o[24]), .Y(n2835) );
CLKINVX1TS U2838 ( .A(n2842), .Y(n2837) );
NAND2X1TS U2839 ( .A(n2892), .B(sgf_result_o[27]), .Y(n2839) );
XNOR2X1TS U2840 ( .A(n2848), .B(n2847), .Y(n2850) );
NAND2X1TS U2841 ( .A(n2892), .B(sgf_result_o[28]), .Y(n2849) );
INVX2TS U2842 ( .A(n2851), .Y(n2998) );
CLKINVX1TS U2843 ( .A(n2997), .Y(n2852) );
NAND2X1TS U2844 ( .A(n2852), .B(n2996), .Y(n2853) );
NAND2X1TS U2845 ( .A(n2779), .B(sgf_result_o[18]), .Y(n2854) );
OAI2BB1X1TS U2846 ( .A0N(n747), .A1N(n2855), .B0(n2854), .Y(n32) );
INVX2TS U2847 ( .A(rst), .Y(n3030) );
CLKBUFX2TS U2848 ( .A(n3030), .Y(n3028) );
CLKBUFX2TS U2849 ( .A(n212), .Y(n3029) );
CLKINVX1TS U2850 ( .A(n2858), .Y(n2860) );
NAND2X1TS U2851 ( .A(n2859), .B(n2860), .Y(n2861) );
XNOR2X1TS U2852 ( .A(n2862), .B(n2861), .Y(n2863) );
OAI2BB1X1TS U2853 ( .A0N(sgf_result_o[22]), .A1N(n2975), .B0(n2864), .Y(n28)
);
NAND2X1TS U2854 ( .A(n2867), .B(n2866), .Y(n2869) );
OAI2BB1X1TS U2855 ( .A0N(sgf_result_o[23]), .A1N(n2975), .B0(n2871), .Y(n27)
);
CLKINVX1TS U2856 ( .A(n2872), .Y(n2878) );
XNOR2X1TS U2857 ( .A(n2878), .B(n2873), .Y(n2875) );
NAND2X1TS U2858 ( .A(n3005), .B(sgf_result_o[25]), .Y(n2874) );
AOI21X1TS U2859 ( .A0(n2878), .A1(n2877), .B0(n2876), .Y(n2882) );
NAND2X1TS U2860 ( .A(n2880), .B(n2879), .Y(n2881) );
OAI2BB1X1TS U2861 ( .A0N(sgf_result_o[26]), .A1N(n2975), .B0(n2884), .Y(n24)
);
OAI2BB1X1TS U2862 ( .A0N(sgf_result_o[0]), .A1N(n2892), .B0(n2886), .Y(n50)
);
OAI2BB1X1TS U2863 ( .A0N(sgf_result_o[1]), .A1N(n2892), .B0(n2891), .Y(n49)
);
NAND2X1TS U2864 ( .A(n2895), .B(n2894), .Y(n2897) );
OAI2BB1X1TS U2865 ( .A0N(load_b_i), .A1N(n2899), .B0(n2898), .Y(n48) );
NAND2X1TS U2866 ( .A(n2901), .B(n2900), .Y(n2903) );
XNOR2X1TS U2867 ( .A(n2903), .B(n2902), .Y(n2904) );
OAI2BB1X1TS U2868 ( .A0N(sgf_result_o[3]), .A1N(n3007), .B0(n2905), .Y(n47)
);
NAND2X1TS U2869 ( .A(n2908), .B(n2907), .Y(n2910) );
OAI2BB1X1TS U2870 ( .A0N(load_b_i), .A1N(n2912), .B0(n2911), .Y(n46) );
NAND2X1TS U2871 ( .A(n2914), .B(n2913), .Y(n2916) );
XNOR2X1TS U2872 ( .A(n2916), .B(n2915), .Y(n2917) );
OAI2BB1X1TS U2873 ( .A0N(sgf_result_o[5]), .A1N(n3007), .B0(n2918), .Y(n45)
);
NAND2X1TS U2874 ( .A(n2921), .B(n2920), .Y(n2923) );
OAI2BB1X1TS U2875 ( .A0N(n747), .A1N(n2925), .B0(n2924), .Y(n44) );
NAND2X1TS U2876 ( .A(n2927), .B(n2932), .Y(n2928) );
OAI2BB1X1TS U2877 ( .A0N(n747), .A1N(n2931), .B0(n2930), .Y(n43) );
INVX1TS U2878 ( .A(n2935), .Y(n2937) );
NAND2X1TS U2879 ( .A(n2937), .B(n2936), .Y(n2938) );
XNOR2X1TS U2880 ( .A(n2939), .B(n2938), .Y(n2940) );
OAI2BB1X1TS U2881 ( .A0N(sgf_result_o[8]), .A1N(n3007), .B0(n2941), .Y(n42)
);
NAND2X1TS U2882 ( .A(n2943), .B(n2948), .Y(n2944) );
XNOR2X1TS U2883 ( .A(n2949), .B(n2944), .Y(n2945) );
OAI2BB1X1TS U2884 ( .A0N(sgf_result_o[9]), .A1N(n3007), .B0(n2946), .Y(n41)
);
AOI21X1TS U2885 ( .A0(n2949), .A1(n2948), .B0(n2947), .Y(n2953) );
NAND2X1TS U2886 ( .A(n2951), .B(n2950), .Y(n2952) );
OAI2BB1X1TS U2887 ( .A0N(n2782), .A1N(n2955), .B0(n2954), .Y(n40) );
NAND2X1TS U2888 ( .A(n2958), .B(n2957), .Y(n2959) );
OAI2BB1X1TS U2889 ( .A0N(n747), .A1N(n2962), .B0(n2961), .Y(n39) );
NAND2X1TS U2890 ( .A(n2968), .B(n2967), .Y(n2969) );
OAI2BB1X1TS U2891 ( .A0N(sgf_result_o[12]), .A1N(n3007), .B0(n2969), .Y(n38)
);
NAND2X1TS U2892 ( .A(n2971), .B(n2970), .Y(n2973) );
XNOR2X1TS U2893 ( .A(n2973), .B(n2972), .Y(n2974) );
OAI2BB1X1TS U2894 ( .A0N(sgf_result_o[13]), .A1N(n3007), .B0(n2976), .Y(n37)
);
NAND2X1TS U2895 ( .A(n2978), .B(n2979), .Y(n2981) );
OAI2BB1X1TS U2896 ( .A0N(n747), .A1N(n2984), .B0(n2983), .Y(n36) );
NAND2X1TS U2897 ( .A(n2986), .B(n2985), .Y(n2987) );
XNOR2X1TS U2898 ( .A(n2988), .B(n2987), .Y(n2990) );
NAND2X1TS U2899 ( .A(n2892), .B(sgf_result_o[15]), .Y(n2989) );
OAI2BB1X1TS U2900 ( .A0N(n747), .A1N(n2990), .B0(n2989), .Y(n35) );
NAND2X1TS U2901 ( .A(n884), .B(n2991), .Y(n2992) );
XNOR2X1TS U2902 ( .A(n2993), .B(n2992), .Y(n2994) );
OAI2BB1X1TS U2903 ( .A0N(sgf_result_o[16]), .A1N(n3007), .B0(n2995), .Y(n34)
);
CLKINVX1TS U2904 ( .A(n2999), .Y(n3001) );
NAND2X1TS U2905 ( .A(n3001), .B(n3000), .Y(n3002) );
XNOR2X1TS U2906 ( .A(n3003), .B(n3002), .Y(n3004) );
OAI2BB1X1TS U2907 ( .A0N(sgf_result_o[19]), .A1N(n3007), .B0(n3006), .Y(n31)
);
initial $sdf_annotate("Simple_KOA_syn.sdf");
endmodule
|
module microfono_TB;
reg reset, clk, micData,rd,wr;
microfono uut(.reset(reset),.micData(micData),.clk(clk),.rd(rd),.wr(wr));
always
begin
clk =1'b1;
#2;
clk=1'b0;
#2;
end
initial
begin
reset =1'b1;
#10;
reset =1'b0;
end
initial
begin
rd = 1'b0;
wr = 1'b0;
#100 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 wr = 1'b1;
#150 wr = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
#150 rd = 1'b0;
#150 rd = 1'b1;
end
initial begin
micData = 1'b0;
#100 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b0;
#150 micData = 1'b1;
#150 micData = 1'b0;
#150 micData = 1'b1;
end
initial begin: TEST_CASE
$dumpfile("microfono_TB.vcd");
$dumpvars(-1, uut);
#(10000) $finish;
end
endmodule //
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module SerialTransmitterTest;
reg clk;
reg rst_x;
reg [7:0] r_data;
reg r_valid;
wire w_error;
wire w_busy;
wire w_tx2rx;
wire [7:0] w_data;
wire w_valid;
wire w_nostop;
always #4 clk = ~clk;
always @ (posedge w_valid) begin
$display("receive: $%02x", w_data);
end
always @ (posedge w_nostop) begin
$display("receive: can not detect stop bit");
end
always @ (posedge w_error) begin
$display("transmit: unexpected request on a busy cycle");
end
SerialTransmitter dut(
.clk_x4 (clk ),
.rst_x (rst_x ),
.i_data (r_data ),
.i_valid(r_valid ),
.o_tx (w_tx2rx ),
.o_busy (w_busy ),
.o_error(w_error ));
SerialReceiver rx(
.clk_x4 (clk ),
.rst_x (rst_x ),
.i_rx (w_tx2rx ),
.o_data (w_data ),
.o_valid(w_valid ),
.o_error(w_nostop));
initial begin
$dumpfile("SerialTransmitter.vcd");
$dumpvars(0, dut);
clk <= 1'b0;
rst_x <= 1'b1;
r_valid <= 1'b0;
#32
rst_x <= 1'b0;
#32
rst_x <= 1'b1;
#20
// Transmit a data.
r_data <= 8'hde;
r_valid <= 1'b1;
#8
r_valid <= 1'b0;
#312
// Transmit another data immediately.
r_data <= 8'had;
r_valid <= 1'b1;
#8
r_valid <= 1'b0;
#308
// Error due to request on busy cycle.
r_valid <= 1'b1;
#4
$finish;
end
endmodule // SerialTransmitterTest
|
// See LICENSE.SiFive for license details.
//VCS coverage exclude_file
import "DPI-C" function int jtag_tick
(
output bit jtag_TCK,
output bit jtag_TMS,
output bit jtag_TDI,
output bit jtag_TRSTn,
output bit sysrstn,
input bit jtag_TDO
);
module SimJTAG #(
parameter TICK_DELAY = 50
)(
input clock,
input reset,
input enable,
input init_done,
output jtag_TCK,
output jtag_TMS,
output jtag_TDI,
output jtag_TRSTn,
output srstn,
input jtag_TDO_data,
input jtag_TDO_driven,
output [31:0] exit
);
reg [31:0] tickCounterReg;
wire [31:0] tickCounterNxt;
assign tickCounterNxt = (tickCounterReg == 0) ? TICK_DELAY : (tickCounterReg - 1);
bit r_reset;
wire [31:0] random_bits = $random;
wire #0.1 __jtag_TDO = jtag_TDO_driven ?
jtag_TDO_data : random_bits[0];
bit __jtag_TCK;
bit __jtag_TMS;
bit __jtag_TDI;
bit __jtag_TRSTn;
int __exit;
bit sysrstn=1;
reg init_done_sticky;
assign #0.1 jtag_TCK = __jtag_TCK;
assign #0.1 jtag_TMS = __jtag_TMS;
assign #0.1 jtag_TDI = __jtag_TDI;
assign #0.1 jtag_TRSTn = __jtag_TRSTn;
assign srstn = sysrstn;
assign #0.1 exit = __exit;
always @(posedge clock) begin
r_reset <= reset;
if (reset || r_reset) begin
__exit = 0;
tickCounterReg <= TICK_DELAY;
init_done_sticky <= 1'b0;
__jtag_TCK = !__jtag_TCK;
end else begin
init_done_sticky <= init_done | init_done_sticky;
if (enable && init_done_sticky) begin
tickCounterReg <= tickCounterNxt;
if (tickCounterReg == 0) begin
__exit = jtag_tick(
__jtag_TCK,
__jtag_TMS,
__jtag_TDI,
__jtag_TRSTn,
sysrstn,
__jtag_TDO);
end
end // if (enable && init_done_sticky)
end // else: !if(reset || r_reset)
end // always @ (posedge clock)
endmodule
|
// Constructs a frame given the data to transmit. Saves writing this
// assignment in three separate places.
//
function [10:0] framed;
input [7:0] data;
// One START bit, LOW. 8 data bits and two STOP bits, HIGH. LSB on RHS
framed = {2'b11, data, 1'b0};
endfunction
module UART (
clk,
reset, // To reset, this should be HIGH when clk RISES
tx_line, // The external line between devices driven by this UART
tx_data, // The data to be transmitted
tx_request, // RISING edge while tx_state is IDLE causes transmission to be initiated
);
input clk;
input reset;
output tx_line;
input [7:0] tx_data;
input tx_request;
parameter TX_STATE_IDLE = 0;
parameter TX_STATE_TRANSMITTING = 1;
parameter CLK_RATE = 12*1000*1000;
parameter BAUD_RATE = 9600;
// For baud rates lower than 9600, check that `tx_countdown` has enough bits
// to store CLK_DIV.
// When `clk` is 12 MHz, dividing by 1250 yields exactly 9600 bps
parameter CLK_DIV = CLK_RATE / BAUD_RATE;
// The frame currently being transmitted. If this is changed during a
// transmission then it will screw up the transmission but that's OK because
// the driver should *not* do that.
reg [10:0] frame = framed (8'h00);
// The bit position in `frame` that is being driven on tx_line right now
reg [3:0] frame_bit_id = 0;
reg tx_state = TX_STATE_IDLE;
reg [11:0] tx_countdown = CLK_DIV;
assign tx_line = frame [frame_bit_id];
always @ (posedge clk) begin
if (reset) begin
frame = framed (8'h00);
frame_bit_id = 0;
tx_state = TX_STATE_IDLE;
end
case (tx_state)
// If the transmitter is not currently transmitting a frame..
TX_STATE_IDLE: begin
// If a request to send a frame has been received..
// FIXME: This is a bit poo. The frame will be sent multiple times if
// `tx_request` is not driven low before the frame is sent
if (tx_request) begin
frame = framed (tx_data);
frame_bit_id = 0;
tx_countdown = CLK_DIV;
tx_state = TX_STATE_TRANSMITTING;
end
end
TX_STATE_TRANSMITTING: begin
tx_countdown = tx_countdown - 1;
// `tx_line` has been driven for a whole bit period when `tx_countdown`
// reaches zero. `frame_bit_id` therefore indicates the bit position
// within frame that has *been* transmitted.
if (tx_countdown == 0) begin
if (frame_bit_id != 10) begin
frame_bit_id = frame_bit_id + 1;
tx_countdown = CLK_DIV;
end else begin
tx_state = TX_STATE_IDLE;
end
end
end // TX_STATE_TRANSMITTING
endcase // tx_state
end // posedge clk
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2017 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2017.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Gigabit Transceiver for UltraScale+ devices
// /___/ /\ Filename : GTYE4_CHANNEL.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module GTYE4_CHANNEL #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0,
parameter [0:0] ACJTAG_MODE = 1'b0,
parameter [0:0] ACJTAG_RESET = 1'b0,
parameter [15:0] ADAPT_CFG0 = 16'h9200,
parameter [15:0] ADAPT_CFG1 = 16'h801C,
parameter [15:0] ADAPT_CFG2 = 16'h0000,
parameter ALIGN_COMMA_DOUBLE = "FALSE",
parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111,
parameter integer ALIGN_COMMA_WORD = 1,
parameter ALIGN_MCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011,
parameter ALIGN_PCOMMA_DET = "TRUE",
parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100,
parameter [0:0] A_RXOSCALRESET = 1'b0,
parameter [0:0] A_RXPROGDIVRESET = 1'b0,
parameter [0:0] A_RXTERMINATION = 1'b1,
parameter [4:0] A_TXDIFFCTRL = 5'b01100,
parameter [0:0] A_TXPROGDIVRESET = 1'b0,
parameter CBCC_DATA_SOURCE_SEL = "DECODED",
parameter [0:0] CDR_SWAP_MODE_EN = 1'b0,
parameter [0:0] CFOK_PWRSVE_EN = 1'b1,
parameter CHAN_BOND_KEEP_ALIGN = "FALSE",
parameter integer CHAN_BOND_MAX_SKEW = 7,
parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100,
parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111,
parameter CHAN_BOND_SEQ_2_USE = "FALSE",
parameter integer CHAN_BOND_SEQ_LEN = 2,
parameter [15:0] CH_HSPMUX = 16'h2424,
parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000,
parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000,
parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000,
parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000,
parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000,
parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000,
parameter CLK_CORRECT_USE = "TRUE",
parameter CLK_COR_KEEP_IDLE = "FALSE",
parameter integer CLK_COR_MAX_LAT = 20,
parameter integer CLK_COR_MIN_LAT = 18,
parameter CLK_COR_PRECEDENCE = "TRUE",
parameter integer CLK_COR_REPEAT_WAIT = 0,
parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100,
parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000,
parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000,
parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111,
parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000,
parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000,
parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111,
parameter CLK_COR_SEQ_2_USE = "FALSE",
parameter integer CLK_COR_SEQ_LEN = 2,
parameter [15:0] CPLL_CFG0 = 16'h01FA,
parameter [15:0] CPLL_CFG1 = 16'h24A9,
parameter [15:0] CPLL_CFG2 = 16'h6807,
parameter [15:0] CPLL_CFG3 = 16'h0000,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 4,
parameter [15:0] CPLL_INIT_CFG0 = 16'h001E,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000,
parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0,
parameter [1:0] DDI_CTRL = 2'b00,
parameter integer DDI_REALIGN_WAIT = 15,
parameter DEC_MCOMMA_DETECT = "TRUE",
parameter DEC_PCOMMA_DETECT = "TRUE",
parameter DEC_VALID_COMMA_ONLY = "TRUE",
parameter [0:0] DELAY_ELEC = 1'b0,
parameter [9:0] DMONITOR_CFG0 = 10'h000,
parameter [7:0] DMONITOR_CFG1 = 8'h00,
parameter [0:0] ES_CLK_PHASE_SEL = 1'b0,
parameter [5:0] ES_CONTROL = 6'b000000,
parameter ES_ERRDET_EN = "FALSE",
parameter ES_EYE_SCAN_EN = "FALSE",
parameter [11:0] ES_HORZ_OFFSET = 12'h800,
parameter [4:0] ES_PRESCALE = 5'b00000,
parameter [15:0] ES_QUALIFIER0 = 16'h0000,
parameter [15:0] ES_QUALIFIER1 = 16'h0000,
parameter [15:0] ES_QUALIFIER2 = 16'h0000,
parameter [15:0] ES_QUALIFIER3 = 16'h0000,
parameter [15:0] ES_QUALIFIER4 = 16'h0000,
parameter [15:0] ES_QUALIFIER5 = 16'h0000,
parameter [15:0] ES_QUALIFIER6 = 16'h0000,
parameter [15:0] ES_QUALIFIER7 = 16'h0000,
parameter [15:0] ES_QUALIFIER8 = 16'h0000,
parameter [15:0] ES_QUALIFIER9 = 16'h0000,
parameter [15:0] ES_QUAL_MASK0 = 16'h0000,
parameter [15:0] ES_QUAL_MASK1 = 16'h0000,
parameter [15:0] ES_QUAL_MASK2 = 16'h0000,
parameter [15:0] ES_QUAL_MASK3 = 16'h0000,
parameter [15:0] ES_QUAL_MASK4 = 16'h0000,
parameter [15:0] ES_QUAL_MASK5 = 16'h0000,
parameter [15:0] ES_QUAL_MASK6 = 16'h0000,
parameter [15:0] ES_QUAL_MASK7 = 16'h0000,
parameter [15:0] ES_QUAL_MASK8 = 16'h0000,
parameter [15:0] ES_QUAL_MASK9 = 16'h0000,
parameter [15:0] ES_SDATA_MASK0 = 16'h0000,
parameter [15:0] ES_SDATA_MASK1 = 16'h0000,
parameter [15:0] ES_SDATA_MASK2 = 16'h0000,
parameter [15:0] ES_SDATA_MASK3 = 16'h0000,
parameter [15:0] ES_SDATA_MASK4 = 16'h0000,
parameter [15:0] ES_SDATA_MASK5 = 16'h0000,
parameter [15:0] ES_SDATA_MASK6 = 16'h0000,
parameter [15:0] ES_SDATA_MASK7 = 16'h0000,
parameter [15:0] ES_SDATA_MASK8 = 16'h0000,
parameter [15:0] ES_SDATA_MASK9 = 16'h0000,
parameter integer EYESCAN_VP_RANGE = 0,
parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0,
parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111,
parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111,
parameter FTS_LANE_DESKEW_EN = "FALSE",
parameter [4:0] GEARBOX_MODE = 5'b00000,
parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0,
parameter [0:0] LOCAL_MASTER = 1'b0,
parameter integer LPBK_BIAS_CTRL = 4,
parameter [0:0] LPBK_EN_RCAL_B = 1'b0,
parameter [3:0] LPBK_EXT_RCAL = 4'b0000,
parameter integer LPBK_IND_CTRL0 = 5,
parameter integer LPBK_IND_CTRL1 = 5,
parameter integer LPBK_IND_CTRL2 = 5,
parameter integer LPBK_RG_CTRL = 2,
parameter [1:0] OOBDIVCTL = 2'b00,
parameter [0:0] OOB_PWRUP = 1'b0,
parameter PCI3_AUTO_REALIGN = "FRST_SMPL",
parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1,
parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00,
parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0,
parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000,
parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000,
parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000,
parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0,
parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0,
parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000,
parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000,
parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000,
parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100,
parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000,
parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE",
parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000,
parameter PCIE_GEN4_64BIT_INT_EN = "FALSE",
parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0,
parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0,
parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0,
parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_RXPMA_CFG = 16'h0000,
parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000,
parameter [15:0] PCIE_TXPMA_CFG = 16'h0000,
parameter PCS_PCIE_EN = "FALSE",
parameter [15:0] PCS_RSVD0 = 16'h0000,
parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C,
parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19,
parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64,
parameter integer PREIQ_FREQ_BST = 0,
parameter [0:0] RATE_SW_USE_DRP = 1'b0,
parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0,
parameter [0:0] RCLK_SIPO_INV_EN = 1'b0,
parameter [2:0] RTX_BUF_CML_CTRL = 3'b010,
parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00,
parameter [4:0] RXBUFRESET_TIME = 5'b00001,
parameter RXBUF_ADDR_MODE = "FULL",
parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000,
parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000,
parameter RXBUF_EN = "TRUE",
parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE",
parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE",
parameter RXBUF_RESET_ON_EIDLE = "FALSE",
parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE",
parameter integer RXBUF_THRESH_OVFLW = 0,
parameter RXBUF_THRESH_OVRD = "FALSE",
parameter integer RXBUF_THRESH_UNDFLW = 4,
parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000,
parameter [4:0] RXCDRPHRESET_TIME = 5'b00001,
parameter [15:0] RXCDR_CFG0 = 16'h0003,
parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003,
parameter [15:0] RXCDR_CFG1 = 16'h0000,
parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000,
parameter [15:0] RXCDR_CFG2 = 16'h0164,
parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164,
parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034,
parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034,
parameter [15:0] RXCDR_CFG3 = 16'h0024,
parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24,
parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024,
parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024,
parameter [15:0] RXCDR_CFG4 = 16'h5CF6,
parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6,
parameter [15:0] RXCDR_CFG5 = 16'hB46B,
parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B,
parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0,
parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0,
parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040,
parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000,
parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000,
parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000,
parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0,
parameter [15:0] RXCFOK_CFG0 = 16'h0000,
parameter [15:0] RXCFOK_CFG1 = 16'h0002,
parameter [15:0] RXCFOK_CFG2 = 16'h002D,
parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000,
parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000,
parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111,
parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000,
parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022,
parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100,
parameter [15:0] RXDFE_CFG0 = 16'h4000,
parameter [15:0] RXDFE_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG1 = 16'h0000,
parameter [15:0] RXDFE_GC_CFG2 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H2_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H3_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H3_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H4_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H4_CFG1 = 16'h0003,
parameter [15:0] RXDFE_H5_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H5_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H6_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H6_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H7_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H7_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H8_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H8_CFG1 = 16'h0002,
parameter [15:0] RXDFE_H9_CFG0 = 16'h0000,
parameter [15:0] RXDFE_H9_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HA_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HA_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HB_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HB_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HC_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HC_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HD_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HD_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HE_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HE_CFG1 = 16'h0002,
parameter [15:0] RXDFE_HF_CFG0 = 16'h0000,
parameter [15:0] RXDFE_HF_CFG1 = 16'h0002,
parameter [15:0] RXDFE_KH_CFG0 = 16'h0000,
parameter [15:0] RXDFE_KH_CFG1 = 16'h0000,
parameter [15:0] RXDFE_KH_CFG2 = 16'h0000,
parameter [15:0] RXDFE_KH_CFG3 = 16'h2000,
parameter [15:0] RXDFE_OS_CFG0 = 16'h0000,
parameter [15:0] RXDFE_OS_CFG1 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG0 = 16'h0000,
parameter [15:0] RXDFE_UT_CFG1 = 16'h0002,
parameter [15:0] RXDFE_UT_CFG2 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG0 = 16'h0000,
parameter [15:0] RXDFE_VP_CFG1 = 16'h0022,
parameter [15:0] RXDLY_CFG = 16'h0010,
parameter [15:0] RXDLY_LCFG = 16'h0030,
parameter RXELECIDLE_CFG = "SIGCFG_4",
parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter RXGEARBOX_EN = "FALSE",
parameter [4:0] RXISCANRESET_TIME = 5'b00001,
parameter [15:0] RXLPM_CFG = 16'h0000,
parameter [15:0] RXLPM_GC_CFG = 16'h1000,
parameter [15:0] RXLPM_KH_CFG0 = 16'h0000,
parameter [15:0] RXLPM_KH_CFG1 = 16'h0002,
parameter [15:0] RXLPM_OS_CFG0 = 16'h0000,
parameter [15:0] RXLPM_OS_CFG1 = 16'h0000,
parameter [8:0] RXOOB_CFG = 9'b000110000,
parameter RXOOB_CLK_CFG = "PMA",
parameter [4:0] RXOSCALRESET_TIME = 5'b00011,
parameter integer RXOUT_DIV = 4,
parameter [4:0] RXPCSRESET_TIME = 5'b00001,
parameter [15:0] RXPHBEACON_CFG = 16'h0000,
parameter [15:0] RXPHDLY_CFG = 16'h2020,
parameter [15:0] RXPHSAMP_CFG = 16'h2100,
parameter [15:0] RXPHSLIP_CFG = 16'h9933,
parameter [4:0] RXPH_MONITOR_SEL = 5'b00000,
parameter [15:0] RXPI_CFG0 = 16'h0102,
parameter [15:0] RXPI_CFG1 = 16'b0000000001010100,
parameter RXPMACLK_SEL = "DATA",
parameter [4:0] RXPMARESET_TIME = 5'b00001,
parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0,
parameter integer RXPRBS_LINKACQ_CNT = 15,
parameter [0:0] RXREFCLKDIV2_SEL = 1'b0,
parameter integer RXSLIDE_AUTO_WAIT = 7,
parameter RXSLIDE_MODE = "OFF",
parameter [0:0] RXSYNC_MULTILANE = 1'b0,
parameter [0:0] RXSYNC_OVRD = 1'b0,
parameter [0:0] RXSYNC_SKIP_DA = 1'b0,
parameter [0:0] RX_AFE_CM_EN = 1'b0,
parameter [15:0] RX_BIAS_CFG0 = 16'h12B0,
parameter [5:0] RX_BUFFER_CFG = 6'b000000,
parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0,
parameter integer RX_CLK25_DIV = 8,
parameter [0:0] RX_CLKMUX_EN = 1'b1,
parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000,
parameter [3:0] RX_CM_BUF_CFG = 4'b1010,
parameter [0:0] RX_CM_BUF_PD = 1'b0,
parameter integer RX_CM_SEL = 2,
parameter integer RX_CM_TRIM = 12,
parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0,
parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000,
parameter integer RX_DATA_WIDTH = 20,
parameter [5:0] RX_DDI_SEL = 6'b000000,
parameter RX_DEFER_RESET_BUF_EN = "TRUE",
parameter [2:0] RX_DEGEN_CTRL = 3'b100,
parameter integer RX_DFELPM_CFG0 = 10,
parameter [0:0] RX_DFELPM_CFG1 = 1'b1,
parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1,
parameter integer RX_DFE_AGC_CFG1 = 4,
parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1,
parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2,
parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01,
parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4,
parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0,
parameter RX_DISPERR_SEQ_MATCH = "TRUE",
parameter [4:0] RX_DIVRESET_TIME = 5'b00001,
parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0,
parameter integer RX_EN_SUM_RCAL_B = 0,
parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000,
parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0,
parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10,
parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0,
parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] RX_I2V_FILTER_EN = 1'b1,
parameter integer RX_INT_DATAWIDTH = 1,
parameter [0:0] RX_PMA_POWER_SAVE = 1'b0,
parameter [15:0] RX_PMA_RSV0 = 16'h002F,
parameter real RX_PROGDIV_CFG = 0.0,
parameter [15:0] RX_PROGDIV_RATE = 16'h0001,
parameter [3:0] RX_RESLOAD_CTRL = 4'b0000,
parameter [0:0] RX_RESLOAD_OVRD = 1'b0,
parameter [2:0] RX_SAMPLE_PERIOD = 3'b101,
parameter integer RX_SIG_VALID_DLY = 11,
parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0,
parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0,
parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000,
parameter integer RX_SUM_PWR_SAVING = 0,
parameter [3:0] RX_SUM_RES_CTRL = 4'b0000,
parameter [3:0] RX_SUM_VCMTUNE = 4'b0011,
parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1,
parameter [0:0] RX_SUM_VCM_OVWR = 1'b0,
parameter [2:0] RX_SUM_VREF_TUNE = 3'b100,
parameter [1:0] RX_TUNE_AFE_OS = 2'b00,
parameter [2:0] RX_VREG_CTRL = 3'b010,
parameter [0:0] RX_VREG_PDB = 1'b1,
parameter [1:0] RX_WIDEMODE_CDR = 2'b01,
parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01,
parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01,
parameter RX_XCLK_SEL = "RXDES",
parameter [0:0] RX_XMODE_SEL = 1'b0,
parameter [0:0] SAMPLE_CLK_PHASE = 1'b0,
parameter [0:0] SAS_12G_MODE = 1'b0,
parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111,
parameter [2:0] SATA_BURST_VAL = 3'b100,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [2:0] SATA_EIDLE_VAL = 3'b100,
parameter SHOW_REALIGN_COMMA = "TRUE",
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter SIM_MODE = "FAST",
parameter SIM_RECEIVER_DETECT_PASS = "TRUE",
parameter SIM_RESET_SPEEDUP = "TRUE",
parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z",
parameter [0:0] SRSTMODE = 1'b0,
parameter [1:0] TAPDLY_SET_TX = 2'h0,
parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000,
parameter [2:0] TERM_RCAL_OVRD = 3'b000,
parameter [7:0] TRANS_TIME_RATE = 8'h0E,
parameter [7:0] TST_RSV0 = 8'h00,
parameter [7:0] TST_RSV1 = 8'h00,
parameter TXBUF_EN = "TRUE",
parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE",
parameter [15:0] TXDLY_CFG = 16'h0010,
parameter [15:0] TXDLY_LCFG = 16'h0030,
parameter integer TXDRV_FREQBAND = 0,
parameter [15:0] TXFE_CFG0 = 16'b0000000000000000,
parameter [15:0] TXFE_CFG1 = 16'b0000000000000000,
parameter [15:0] TXFE_CFG2 = 16'b0000000000000000,
parameter [15:0] TXFE_CFG3 = 16'b0000000000000000,
parameter TXFIFO_ADDR_CFG = "LOW",
parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4,
parameter TXGEARBOX_EN = "FALSE",
parameter integer TXOUT_DIV = 4,
parameter [4:0] TXPCSRESET_TIME = 5'b00001,
parameter [15:0] TXPHDLY_CFG0 = 16'h6020,
parameter [15:0] TXPHDLY_CFG1 = 16'h0002,
parameter [15:0] TXPH_CFG = 16'h0123,
parameter [15:0] TXPH_CFG2 = 16'h0000,
parameter [4:0] TXPH_MONITOR_SEL = 5'b00000,
parameter [15:0] TXPI_CFG0 = 16'b0000000100000000,
parameter [15:0] TXPI_CFG1 = 16'b0000000000000000,
parameter [0:0] TXPI_GRAY_SEL = 1'b0,
parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0,
parameter [0:0] TXPI_PPM = 1'b0,
parameter [7:0] TXPI_PPM_CFG = 8'b00000000,
parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000,
parameter [4:0] TXPMARESET_TIME = 5'b00001,
parameter [0:0] TXREFCLKDIV2_SEL = 1'b0,
parameter integer TXSWBST_BST = 1,
parameter integer TXSWBST_EN = 0,
parameter integer TXSWBST_MAG = 6,
parameter [0:0] TXSYNC_MULTILANE = 1'b0,
parameter [0:0] TXSYNC_OVRD = 1'b0,
parameter [0:0] TXSYNC_SKIP_DA = 1'b0,
parameter integer TX_CLK25_DIV = 8,
parameter [0:0] TX_CLKMUX_EN = 1'b1,
parameter integer TX_DATA_WIDTH = 20,
parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000,
parameter [5:0] TX_DEEMPH0 = 6'b000000,
parameter [5:0] TX_DEEMPH1 = 6'b000000,
parameter [5:0] TX_DEEMPH2 = 6'b000000,
parameter [5:0] TX_DEEMPH3 = 6'b000000,
parameter [4:0] TX_DIVRESET_TIME = 5'b00001,
parameter TX_DRIVE_MODE = "DIRECT",
parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110,
parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100,
parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0,
parameter [0:0] TX_FIFO_BYP_EN = 1'b0,
parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0,
parameter integer TX_INT_DATAWIDTH = 1,
parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE",
parameter [0:0] TX_MAINCURSOR_SEL = 1'b0,
parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110,
parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001,
parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101,
parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010,
parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110,
parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100,
parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010,
parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000,
parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000,
parameter [15:0] TX_PHICAL_CFG0 = 16'h0000,
parameter [15:0] TX_PHICAL_CFG1 = 16'h003F,
parameter integer TX_PI_BIASSET = 0,
parameter [0:0] TX_PMADATA_OPT = 1'b0,
parameter [0:0] TX_PMA_POWER_SAVE = 1'b0,
parameter [15:0] TX_PMA_RSV0 = 16'h0000,
parameter [15:0] TX_PMA_RSV1 = 16'h0000,
parameter TX_PROGCLK_SEL = "POSTPI",
parameter real TX_PROGDIV_CFG = 0.0,
parameter [15:0] TX_PROGDIV_RATE = 16'h0001,
parameter [13:0] TX_RXDETECT_CFG = 14'h0032,
parameter integer TX_RXDETECT_REF = 3,
parameter [2:0] TX_SAMPLE_PERIOD = 3'b101,
parameter [1:0] TX_SW_MEAS = 2'b00,
parameter [2:0] TX_VREG_CTRL = 3'b000,
parameter [0:0] TX_VREG_PDB = 1'b0,
parameter [1:0] TX_VREG_VREFSEL = 2'b00,
parameter TX_XCLK_SEL = "TXOUT",
parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0,
parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111,
parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011,
parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0,
parameter [0:0] USB_EXT_CNTL = 1'b1,
parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011,
parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011,
parameter [8:0] USB_LFPSPING_BURST = 9'b000000101,
parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001,
parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100,
parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101,
parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011,
parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011,
parameter [3:0] USB_LFPS_TPERIOD = 4'b0011,
parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1,
parameter [0:0] USB_MODE = 1'b0,
parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0,
parameter integer USB_PING_SATA_MAX_INIT = 21,
parameter integer USB_PING_SATA_MIN_INIT = 12,
parameter integer USB_POLL_SATA_MAX_BURST = 8,
parameter integer USB_POLL_SATA_MIN_BURST = 4,
parameter [0:0] USB_RAW_ELEC = 1'b0,
parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1,
parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1,
parameter integer USB_U1_SATA_MAX_WAKE = 7,
parameter integer USB_U1_SATA_MIN_WAKE = 4,
parameter integer USB_U2_SAS_MAX_COM = 64,
parameter integer USB_U2_SAS_MIN_COM = 36,
parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0,
parameter [0:0] Y_ALL_MODE = 1'b0
)(
output BUFGTCE,
output [2:0] BUFGTCEMASK,
output [8:0] BUFGTDIV,
output BUFGTRESET,
output [2:0] BUFGTRSTMASK,
output CPLLFBCLKLOST,
output CPLLLOCK,
output CPLLREFCLKLOST,
output [15:0] DMONITOROUT,
output DMONITOROUTCLK,
output [15:0] DRPDO,
output DRPRDY,
output EYESCANDATAERROR,
output GTPOWERGOOD,
output GTREFCLKMONITOR,
output GTYTXN,
output GTYTXP,
output PCIERATEGEN3,
output PCIERATEIDLE,
output [1:0] PCIERATEQPLLPD,
output [1:0] PCIERATEQPLLRESET,
output PCIESYNCTXSYNCDONE,
output PCIEUSERGEN3RDY,
output PCIEUSERPHYSTATUSRST,
output PCIEUSERRATESTART,
output [15:0] PCSRSVDOUT,
output PHYSTATUS,
output [15:0] PINRSRVDAS,
output POWERPRESENT,
output RESETEXCEPTION,
output [2:0] RXBUFSTATUS,
output RXBYTEISALIGNED,
output RXBYTEREALIGN,
output RXCDRLOCK,
output RXCDRPHDONE,
output RXCHANBONDSEQ,
output RXCHANISALIGNED,
output RXCHANREALIGN,
output [4:0] RXCHBONDO,
output RXCKCALDONE,
output [1:0] RXCLKCORCNT,
output RXCOMINITDET,
output RXCOMMADET,
output RXCOMSASDET,
output RXCOMWAKEDET,
output [15:0] RXCTRL0,
output [15:0] RXCTRL1,
output [7:0] RXCTRL2,
output [7:0] RXCTRL3,
output [127:0] RXDATA,
output [7:0] RXDATAEXTENDRSVD,
output [1:0] RXDATAVALID,
output RXDLYSRESETDONE,
output RXELECIDLE,
output [5:0] RXHEADER,
output [1:0] RXHEADERVALID,
output RXLFPSTRESETDET,
output RXLFPSU2LPEXITDET,
output RXLFPSU3WAKEDET,
output [7:0] RXMONITOROUT,
output RXOSINTDONE,
output RXOSINTSTARTED,
output RXOSINTSTROBEDONE,
output RXOSINTSTROBESTARTED,
output RXOUTCLK,
output RXOUTCLKFABRIC,
output RXOUTCLKPCS,
output RXPHALIGNDONE,
output RXPHALIGNERR,
output RXPMARESETDONE,
output RXPRBSERR,
output RXPRBSLOCKED,
output RXPRGDIVRESETDONE,
output RXRATEDONE,
output RXRECCLKOUT,
output RXRESETDONE,
output RXSLIDERDY,
output RXSLIPDONE,
output RXSLIPOUTCLKRDY,
output RXSLIPPMARDY,
output [1:0] RXSTARTOFSEQ,
output [2:0] RXSTATUS,
output RXSYNCDONE,
output RXSYNCOUT,
output RXVALID,
output [1:0] TXBUFSTATUS,
output TXCOMFINISH,
output TXDCCDONE,
output TXDLYSRESETDONE,
output TXOUTCLK,
output TXOUTCLKFABRIC,
output TXOUTCLKPCS,
output TXPHALIGNDONE,
output TXPHINITDONE,
output TXPMARESETDONE,
output TXPRGDIVRESETDONE,
output TXRATEDONE,
output TXRESETDONE,
output TXSYNCDONE,
output TXSYNCOUT,
input CDRSTEPDIR,
input CDRSTEPSQ,
input CDRSTEPSX,
input CFGRESET,
input CLKRSVD0,
input CLKRSVD1,
input CPLLFREQLOCK,
input CPLLLOCKDETCLK,
input CPLLLOCKEN,
input CPLLPD,
input [2:0] CPLLREFCLKSEL,
input CPLLRESET,
input DMONFIFORESET,
input DMONITORCLK,
input [9:0] DRPADDR,
input DRPCLK,
input [15:0] DRPDI,
input DRPEN,
input DRPRST,
input DRPWE,
input EYESCANRESET,
input EYESCANTRIGGER,
input FREQOS,
input GTGREFCLK,
input GTNORTHREFCLK0,
input GTNORTHREFCLK1,
input GTREFCLK0,
input GTREFCLK1,
input [15:0] GTRSVD,
input GTRXRESET,
input GTRXRESETSEL,
input GTSOUTHREFCLK0,
input GTSOUTHREFCLK1,
input GTTXRESET,
input GTTXRESETSEL,
input GTYRXN,
input GTYRXP,
input INCPCTRL,
input [2:0] LOOPBACK,
input PCIEEQRXEQADAPTDONE,
input PCIERSTIDLE,
input PCIERSTTXSYNCSTART,
input PCIEUSERRATEDONE,
input [15:0] PCSRSVDIN,
input QPLL0CLK,
input QPLL0FREQLOCK,
input QPLL0REFCLK,
input QPLL1CLK,
input QPLL1FREQLOCK,
input QPLL1REFCLK,
input RESETOVRD,
input RX8B10BEN,
input RXAFECFOKEN,
input RXBUFRESET,
input RXCDRFREQRESET,
input RXCDRHOLD,
input RXCDROVRDEN,
input RXCDRRESET,
input RXCHBONDEN,
input [4:0] RXCHBONDI,
input [2:0] RXCHBONDLEVEL,
input RXCHBONDMASTER,
input RXCHBONDSLAVE,
input RXCKCALRESET,
input [6:0] RXCKCALSTART,
input RXCOMMADETEN,
input RXDFEAGCHOLD,
input RXDFEAGCOVRDEN,
input [3:0] RXDFECFOKFCNUM,
input RXDFECFOKFEN,
input RXDFECFOKFPULSE,
input RXDFECFOKHOLD,
input RXDFECFOKOVREN,
input RXDFEKHHOLD,
input RXDFEKHOVRDEN,
input RXDFELFHOLD,
input RXDFELFOVRDEN,
input RXDFELPMRESET,
input RXDFETAP10HOLD,
input RXDFETAP10OVRDEN,
input RXDFETAP11HOLD,
input RXDFETAP11OVRDEN,
input RXDFETAP12HOLD,
input RXDFETAP12OVRDEN,
input RXDFETAP13HOLD,
input RXDFETAP13OVRDEN,
input RXDFETAP14HOLD,
input RXDFETAP14OVRDEN,
input RXDFETAP15HOLD,
input RXDFETAP15OVRDEN,
input RXDFETAP2HOLD,
input RXDFETAP2OVRDEN,
input RXDFETAP3HOLD,
input RXDFETAP3OVRDEN,
input RXDFETAP4HOLD,
input RXDFETAP4OVRDEN,
input RXDFETAP5HOLD,
input RXDFETAP5OVRDEN,
input RXDFETAP6HOLD,
input RXDFETAP6OVRDEN,
input RXDFETAP7HOLD,
input RXDFETAP7OVRDEN,
input RXDFETAP8HOLD,
input RXDFETAP8OVRDEN,
input RXDFETAP9HOLD,
input RXDFETAP9OVRDEN,
input RXDFEUTHOLD,
input RXDFEUTOVRDEN,
input RXDFEVPHOLD,
input RXDFEVPOVRDEN,
input RXDFEXYDEN,
input RXDLYBYPASS,
input RXDLYEN,
input RXDLYOVRDEN,
input RXDLYSRESET,
input [1:0] RXELECIDLEMODE,
input RXEQTRAINING,
input RXGEARBOXSLIP,
input RXLATCLK,
input RXLPMEN,
input RXLPMGCHOLD,
input RXLPMGCOVRDEN,
input RXLPMHFHOLD,
input RXLPMHFOVRDEN,
input RXLPMLFHOLD,
input RXLPMLFKLOVRDEN,
input RXLPMOSHOLD,
input RXLPMOSOVRDEN,
input RXMCOMMAALIGNEN,
input [1:0] RXMONITORSEL,
input RXOOBRESET,
input RXOSCALRESET,
input RXOSHOLD,
input RXOSOVRDEN,
input [2:0] RXOUTCLKSEL,
input RXPCOMMAALIGNEN,
input RXPCSRESET,
input [1:0] RXPD,
input RXPHALIGN,
input RXPHALIGNEN,
input RXPHDLYPD,
input RXPHDLYRESET,
input [1:0] RXPLLCLKSEL,
input RXPMARESET,
input RXPOLARITY,
input RXPRBSCNTRESET,
input [3:0] RXPRBSSEL,
input RXPROGDIVRESET,
input [2:0] RXRATE,
input RXRATEMODE,
input RXSLIDE,
input RXSLIPOUTCLK,
input RXSLIPPMA,
input RXSYNCALLIN,
input RXSYNCIN,
input RXSYNCMODE,
input [1:0] RXSYSCLKSEL,
input RXTERMINATION,
input RXUSERRDY,
input RXUSRCLK,
input RXUSRCLK2,
input SIGVALIDCLK,
input [19:0] TSTIN,
input [7:0] TX8B10BBYPASS,
input TX8B10BEN,
input TXCOMINIT,
input TXCOMSAS,
input TXCOMWAKE,
input [15:0] TXCTRL0,
input [15:0] TXCTRL1,
input [7:0] TXCTRL2,
input [127:0] TXDATA,
input [7:0] TXDATAEXTENDRSVD,
input TXDCCFORCESTART,
input TXDCCRESET,
input [1:0] TXDEEMPH,
input TXDETECTRX,
input [4:0] TXDIFFCTRL,
input TXDLYBYPASS,
input TXDLYEN,
input TXDLYHOLD,
input TXDLYOVRDEN,
input TXDLYSRESET,
input TXDLYUPDOWN,
input TXELECIDLE,
input [5:0] TXHEADER,
input TXINHIBIT,
input TXLATCLK,
input TXLFPSTRESET,
input TXLFPSU2LPEXIT,
input TXLFPSU3WAKE,
input [6:0] TXMAINCURSOR,
input [2:0] TXMARGIN,
input TXMUXDCDEXHOLD,
input TXMUXDCDORWREN,
input TXONESZEROS,
input [2:0] TXOUTCLKSEL,
input TXPCSRESET,
input [1:0] TXPD,
input TXPDELECIDLEMODE,
input TXPHALIGN,
input TXPHALIGNEN,
input TXPHDLYPD,
input TXPHDLYRESET,
input TXPHDLYTSTCLK,
input TXPHINIT,
input TXPHOVRDEN,
input TXPIPPMEN,
input TXPIPPMOVRDEN,
input TXPIPPMPD,
input TXPIPPMSEL,
input [4:0] TXPIPPMSTEPSIZE,
input TXPISOPD,
input [1:0] TXPLLCLKSEL,
input TXPMARESET,
input TXPOLARITY,
input [4:0] TXPOSTCURSOR,
input TXPRBSFORCEERR,
input [3:0] TXPRBSSEL,
input [4:0] TXPRECURSOR,
input TXPROGDIVRESET,
input [2:0] TXRATE,
input TXRATEMODE,
input [6:0] TXSEQUENCE,
input TXSWING,
input TXSYNCALLIN,
input TXSYNCIN,
input TXSYNCMODE,
input [1:0] TXSYSCLKSEL,
input TXUSERRDY,
input TXUSRCLK,
input TXUSRCLK2
);
// define constants
localparam MODULE_NAME = "GTYE4_CHANNEL";
reg trig_attr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "GTYE4_CHANNEL_dr.v"
`else
reg [0:0] ACJTAG_DEBUG_MODE_REG = ACJTAG_DEBUG_MODE;
reg [0:0] ACJTAG_MODE_REG = ACJTAG_MODE;
reg [0:0] ACJTAG_RESET_REG = ACJTAG_RESET;
reg [15:0] ADAPT_CFG0_REG = ADAPT_CFG0;
reg [15:0] ADAPT_CFG1_REG = ADAPT_CFG1;
reg [15:0] ADAPT_CFG2_REG = ADAPT_CFG2;
reg [40:1] ALIGN_COMMA_DOUBLE_REG = ALIGN_COMMA_DOUBLE;
reg [9:0] ALIGN_COMMA_ENABLE_REG = ALIGN_COMMA_ENABLE;
reg [2:0] ALIGN_COMMA_WORD_REG = ALIGN_COMMA_WORD;
reg [40:1] ALIGN_MCOMMA_DET_REG = ALIGN_MCOMMA_DET;
reg [9:0] ALIGN_MCOMMA_VALUE_REG = ALIGN_MCOMMA_VALUE;
reg [40:1] ALIGN_PCOMMA_DET_REG = ALIGN_PCOMMA_DET;
reg [9:0] ALIGN_PCOMMA_VALUE_REG = ALIGN_PCOMMA_VALUE;
reg [0:0] A_RXOSCALRESET_REG = A_RXOSCALRESET;
reg [0:0] A_RXPROGDIVRESET_REG = A_RXPROGDIVRESET;
reg [0:0] A_RXTERMINATION_REG = A_RXTERMINATION;
reg [4:0] A_TXDIFFCTRL_REG = A_TXDIFFCTRL;
reg [0:0] A_TXPROGDIVRESET_REG = A_TXPROGDIVRESET;
reg [56:1] CBCC_DATA_SOURCE_SEL_REG = CBCC_DATA_SOURCE_SEL;
reg [0:0] CDR_SWAP_MODE_EN_REG = CDR_SWAP_MODE_EN;
reg [0:0] CFOK_PWRSVE_EN_REG = CFOK_PWRSVE_EN;
reg [40:1] CHAN_BOND_KEEP_ALIGN_REG = CHAN_BOND_KEEP_ALIGN;
reg [3:0] CHAN_BOND_MAX_SKEW_REG = CHAN_BOND_MAX_SKEW;
reg [9:0] CHAN_BOND_SEQ_1_1_REG = CHAN_BOND_SEQ_1_1;
reg [9:0] CHAN_BOND_SEQ_1_2_REG = CHAN_BOND_SEQ_1_2;
reg [9:0] CHAN_BOND_SEQ_1_3_REG = CHAN_BOND_SEQ_1_3;
reg [9:0] CHAN_BOND_SEQ_1_4_REG = CHAN_BOND_SEQ_1_4;
reg [3:0] CHAN_BOND_SEQ_1_ENABLE_REG = CHAN_BOND_SEQ_1_ENABLE;
reg [9:0] CHAN_BOND_SEQ_2_1_REG = CHAN_BOND_SEQ_2_1;
reg [9:0] CHAN_BOND_SEQ_2_2_REG = CHAN_BOND_SEQ_2_2;
reg [9:0] CHAN_BOND_SEQ_2_3_REG = CHAN_BOND_SEQ_2_3;
reg [9:0] CHAN_BOND_SEQ_2_4_REG = CHAN_BOND_SEQ_2_4;
reg [3:0] CHAN_BOND_SEQ_2_ENABLE_REG = CHAN_BOND_SEQ_2_ENABLE;
reg [40:1] CHAN_BOND_SEQ_2_USE_REG = CHAN_BOND_SEQ_2_USE;
reg [2:0] CHAN_BOND_SEQ_LEN_REG = CHAN_BOND_SEQ_LEN;
reg [15:0] CH_HSPMUX_REG = CH_HSPMUX;
reg [15:0] CKCAL1_CFG_0_REG = CKCAL1_CFG_0;
reg [15:0] CKCAL1_CFG_1_REG = CKCAL1_CFG_1;
reg [15:0] CKCAL1_CFG_2_REG = CKCAL1_CFG_2;
reg [15:0] CKCAL1_CFG_3_REG = CKCAL1_CFG_3;
reg [15:0] CKCAL2_CFG_0_REG = CKCAL2_CFG_0;
reg [15:0] CKCAL2_CFG_1_REG = CKCAL2_CFG_1;
reg [15:0] CKCAL2_CFG_2_REG = CKCAL2_CFG_2;
reg [15:0] CKCAL2_CFG_3_REG = CKCAL2_CFG_3;
reg [15:0] CKCAL2_CFG_4_REG = CKCAL2_CFG_4;
reg [40:1] CLK_CORRECT_USE_REG = CLK_CORRECT_USE;
reg [40:1] CLK_COR_KEEP_IDLE_REG = CLK_COR_KEEP_IDLE;
reg [5:0] CLK_COR_MAX_LAT_REG = CLK_COR_MAX_LAT;
reg [5:0] CLK_COR_MIN_LAT_REG = CLK_COR_MIN_LAT;
reg [40:1] CLK_COR_PRECEDENCE_REG = CLK_COR_PRECEDENCE;
reg [4:0] CLK_COR_REPEAT_WAIT_REG = CLK_COR_REPEAT_WAIT;
reg [9:0] CLK_COR_SEQ_1_1_REG = CLK_COR_SEQ_1_1;
reg [9:0] CLK_COR_SEQ_1_2_REG = CLK_COR_SEQ_1_2;
reg [9:0] CLK_COR_SEQ_1_3_REG = CLK_COR_SEQ_1_3;
reg [9:0] CLK_COR_SEQ_1_4_REG = CLK_COR_SEQ_1_4;
reg [3:0] CLK_COR_SEQ_1_ENABLE_REG = CLK_COR_SEQ_1_ENABLE;
reg [9:0] CLK_COR_SEQ_2_1_REG = CLK_COR_SEQ_2_1;
reg [9:0] CLK_COR_SEQ_2_2_REG = CLK_COR_SEQ_2_2;
reg [9:0] CLK_COR_SEQ_2_3_REG = CLK_COR_SEQ_2_3;
reg [9:0] CLK_COR_SEQ_2_4_REG = CLK_COR_SEQ_2_4;
reg [3:0] CLK_COR_SEQ_2_ENABLE_REG = CLK_COR_SEQ_2_ENABLE;
reg [40:1] CLK_COR_SEQ_2_USE_REG = CLK_COR_SEQ_2_USE;
reg [2:0] CLK_COR_SEQ_LEN_REG = CLK_COR_SEQ_LEN;
reg [15:0] CPLL_CFG0_REG = CPLL_CFG0;
reg [15:0] CPLL_CFG1_REG = CPLL_CFG1;
reg [15:0] CPLL_CFG2_REG = CPLL_CFG2;
reg [15:0] CPLL_CFG3_REG = CPLL_CFG3;
reg [4:0] CPLL_FBDIV_REG = CPLL_FBDIV;
reg [2:0] CPLL_FBDIV_45_REG = CPLL_FBDIV_45;
reg [15:0] CPLL_INIT_CFG0_REG = CPLL_INIT_CFG0;
reg [15:0] CPLL_LOCK_CFG_REG = CPLL_LOCK_CFG;
reg [4:0] CPLL_REFCLK_DIV_REG = CPLL_REFCLK_DIV;
reg [2:0] CTLE3_OCAP_EXT_CTRL_REG = CTLE3_OCAP_EXT_CTRL;
reg [0:0] CTLE3_OCAP_EXT_EN_REG = CTLE3_OCAP_EXT_EN;
reg [1:0] DDI_CTRL_REG = DDI_CTRL;
reg [4:0] DDI_REALIGN_WAIT_REG = DDI_REALIGN_WAIT;
reg [40:1] DEC_MCOMMA_DETECT_REG = DEC_MCOMMA_DETECT;
reg [40:1] DEC_PCOMMA_DETECT_REG = DEC_PCOMMA_DETECT;
reg [40:1] DEC_VALID_COMMA_ONLY_REG = DEC_VALID_COMMA_ONLY;
reg [0:0] DELAY_ELEC_REG = DELAY_ELEC;
reg [9:0] DMONITOR_CFG0_REG = DMONITOR_CFG0;
reg [7:0] DMONITOR_CFG1_REG = DMONITOR_CFG1;
reg [0:0] ES_CLK_PHASE_SEL_REG = ES_CLK_PHASE_SEL;
reg [5:0] ES_CONTROL_REG = ES_CONTROL;
reg [40:1] ES_ERRDET_EN_REG = ES_ERRDET_EN;
reg [40:1] ES_EYE_SCAN_EN_REG = ES_EYE_SCAN_EN;
reg [11:0] ES_HORZ_OFFSET_REG = ES_HORZ_OFFSET;
reg [4:0] ES_PRESCALE_REG = ES_PRESCALE;
reg [15:0] ES_QUALIFIER0_REG = ES_QUALIFIER0;
reg [15:0] ES_QUALIFIER1_REG = ES_QUALIFIER1;
reg [15:0] ES_QUALIFIER2_REG = ES_QUALIFIER2;
reg [15:0] ES_QUALIFIER3_REG = ES_QUALIFIER3;
reg [15:0] ES_QUALIFIER4_REG = ES_QUALIFIER4;
reg [15:0] ES_QUALIFIER5_REG = ES_QUALIFIER5;
reg [15:0] ES_QUALIFIER6_REG = ES_QUALIFIER6;
reg [15:0] ES_QUALIFIER7_REG = ES_QUALIFIER7;
reg [15:0] ES_QUALIFIER8_REG = ES_QUALIFIER8;
reg [15:0] ES_QUALIFIER9_REG = ES_QUALIFIER9;
reg [15:0] ES_QUAL_MASK0_REG = ES_QUAL_MASK0;
reg [15:0] ES_QUAL_MASK1_REG = ES_QUAL_MASK1;
reg [15:0] ES_QUAL_MASK2_REG = ES_QUAL_MASK2;
reg [15:0] ES_QUAL_MASK3_REG = ES_QUAL_MASK3;
reg [15:0] ES_QUAL_MASK4_REG = ES_QUAL_MASK4;
reg [15:0] ES_QUAL_MASK5_REG = ES_QUAL_MASK5;
reg [15:0] ES_QUAL_MASK6_REG = ES_QUAL_MASK6;
reg [15:0] ES_QUAL_MASK7_REG = ES_QUAL_MASK7;
reg [15:0] ES_QUAL_MASK8_REG = ES_QUAL_MASK8;
reg [15:0] ES_QUAL_MASK9_REG = ES_QUAL_MASK9;
reg [15:0] ES_SDATA_MASK0_REG = ES_SDATA_MASK0;
reg [15:0] ES_SDATA_MASK1_REG = ES_SDATA_MASK1;
reg [15:0] ES_SDATA_MASK2_REG = ES_SDATA_MASK2;
reg [15:0] ES_SDATA_MASK3_REG = ES_SDATA_MASK3;
reg [15:0] ES_SDATA_MASK4_REG = ES_SDATA_MASK4;
reg [15:0] ES_SDATA_MASK5_REG = ES_SDATA_MASK5;
reg [15:0] ES_SDATA_MASK6_REG = ES_SDATA_MASK6;
reg [15:0] ES_SDATA_MASK7_REG = ES_SDATA_MASK7;
reg [15:0] ES_SDATA_MASK8_REG = ES_SDATA_MASK8;
reg [15:0] ES_SDATA_MASK9_REG = ES_SDATA_MASK9;
reg [1:0] EYESCAN_VP_RANGE_REG = EYESCAN_VP_RANGE;
reg [0:0] EYE_SCAN_SWAP_EN_REG = EYE_SCAN_SWAP_EN;
reg [3:0] FTS_DESKEW_SEQ_ENABLE_REG = FTS_DESKEW_SEQ_ENABLE;
reg [3:0] FTS_LANE_DESKEW_CFG_REG = FTS_LANE_DESKEW_CFG;
reg [40:1] FTS_LANE_DESKEW_EN_REG = FTS_LANE_DESKEW_EN;
reg [4:0] GEARBOX_MODE_REG = GEARBOX_MODE;
reg [0:0] ISCAN_CK_PH_SEL2_REG = ISCAN_CK_PH_SEL2;
reg [0:0] LOCAL_MASTER_REG = LOCAL_MASTER;
reg [2:0] LPBK_BIAS_CTRL_REG = LPBK_BIAS_CTRL;
reg [0:0] LPBK_EN_RCAL_B_REG = LPBK_EN_RCAL_B;
reg [3:0] LPBK_EXT_RCAL_REG = LPBK_EXT_RCAL;
reg [2:0] LPBK_IND_CTRL0_REG = LPBK_IND_CTRL0;
reg [2:0] LPBK_IND_CTRL1_REG = LPBK_IND_CTRL1;
reg [2:0] LPBK_IND_CTRL2_REG = LPBK_IND_CTRL2;
reg [1:0] LPBK_RG_CTRL_REG = LPBK_RG_CTRL;
reg [1:0] OOBDIVCTL_REG = OOBDIVCTL;
reg [0:0] OOB_PWRUP_REG = OOB_PWRUP;
reg [80:1] PCI3_AUTO_REALIGN_REG = PCI3_AUTO_REALIGN;
reg [0:0] PCI3_PIPE_RX_ELECIDLE_REG = PCI3_PIPE_RX_ELECIDLE;
reg [1:0] PCI3_RX_ASYNC_EBUF_BYPASS_REG = PCI3_RX_ASYNC_EBUF_BYPASS;
reg [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE_REG = PCI3_RX_ELECIDLE_EI2_ENABLE;
reg [5:0] PCI3_RX_ELECIDLE_H2L_COUNT_REG = PCI3_RX_ELECIDLE_H2L_COUNT;
reg [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE_REG = PCI3_RX_ELECIDLE_H2L_DISABLE;
reg [5:0] PCI3_RX_ELECIDLE_HI_COUNT_REG = PCI3_RX_ELECIDLE_HI_COUNT;
reg [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE_REG = PCI3_RX_ELECIDLE_LP4_DISABLE;
reg [0:0] PCI3_RX_FIFO_DISABLE_REG = PCI3_RX_FIFO_DISABLE;
reg [4:0] PCIE3_CLK_COR_EMPTY_THRSH_REG = PCIE3_CLK_COR_EMPTY_THRSH;
reg [5:0] PCIE3_CLK_COR_FULL_THRSH_REG = PCIE3_CLK_COR_FULL_THRSH;
reg [4:0] PCIE3_CLK_COR_MAX_LAT_REG = PCIE3_CLK_COR_MAX_LAT;
reg [4:0] PCIE3_CLK_COR_MIN_LAT_REG = PCIE3_CLK_COR_MIN_LAT;
reg [5:0] PCIE3_CLK_COR_THRSH_TIMER_REG = PCIE3_CLK_COR_THRSH_TIMER;
reg [40:1] PCIE_64B_DYN_CLKSW_DIS_REG = PCIE_64B_DYN_CLKSW_DIS;
reg [15:0] PCIE_BUFG_DIV_CTRL_REG = PCIE_BUFG_DIV_CTRL;
reg [40:1] PCIE_GEN4_64BIT_INT_EN_REG = PCIE_GEN4_64BIT_INT_EN;
reg [1:0] PCIE_PLL_SEL_MODE_GEN12_REG = PCIE_PLL_SEL_MODE_GEN12;
reg [1:0] PCIE_PLL_SEL_MODE_GEN3_REG = PCIE_PLL_SEL_MODE_GEN3;
reg [1:0] PCIE_PLL_SEL_MODE_GEN4_REG = PCIE_PLL_SEL_MODE_GEN4;
reg [15:0] PCIE_RXPCS_CFG_GEN3_REG = PCIE_RXPCS_CFG_GEN3;
reg [15:0] PCIE_RXPMA_CFG_REG = PCIE_RXPMA_CFG;
reg [15:0] PCIE_TXPCS_CFG_GEN3_REG = PCIE_TXPCS_CFG_GEN3;
reg [15:0] PCIE_TXPMA_CFG_REG = PCIE_TXPMA_CFG;
reg [40:1] PCS_PCIE_EN_REG = PCS_PCIE_EN;
reg [15:0] PCS_RSVD0_REG = PCS_RSVD0;
reg [11:0] PD_TRANS_TIME_FROM_P2_REG = PD_TRANS_TIME_FROM_P2;
reg [7:0] PD_TRANS_TIME_NONE_P2_REG = PD_TRANS_TIME_NONE_P2;
reg [7:0] PD_TRANS_TIME_TO_P2_REG = PD_TRANS_TIME_TO_P2;
reg [1:0] PREIQ_FREQ_BST_REG = PREIQ_FREQ_BST;
reg [0:0] RATE_SW_USE_DRP_REG = RATE_SW_USE_DRP;
reg [0:0] RCLK_SIPO_DLY_ENB_REG = RCLK_SIPO_DLY_ENB;
reg [0:0] RCLK_SIPO_INV_EN_REG = RCLK_SIPO_INV_EN;
reg [2:0] RTX_BUF_CML_CTRL_REG = RTX_BUF_CML_CTRL;
reg [1:0] RTX_BUF_TERM_CTRL_REG = RTX_BUF_TERM_CTRL;
reg [4:0] RXBUFRESET_TIME_REG = RXBUFRESET_TIME;
reg [32:1] RXBUF_ADDR_MODE_REG = RXBUF_ADDR_MODE;
reg [3:0] RXBUF_EIDLE_HI_CNT_REG = RXBUF_EIDLE_HI_CNT;
reg [3:0] RXBUF_EIDLE_LO_CNT_REG = RXBUF_EIDLE_LO_CNT;
reg [40:1] RXBUF_EN_REG = RXBUF_EN;
reg [40:1] RXBUF_RESET_ON_CB_CHANGE_REG = RXBUF_RESET_ON_CB_CHANGE;
reg [40:1] RXBUF_RESET_ON_COMMAALIGN_REG = RXBUF_RESET_ON_COMMAALIGN;
reg [40:1] RXBUF_RESET_ON_EIDLE_REG = RXBUF_RESET_ON_EIDLE;
reg [40:1] RXBUF_RESET_ON_RATE_CHANGE_REG = RXBUF_RESET_ON_RATE_CHANGE;
reg [5:0] RXBUF_THRESH_OVFLW_REG = RXBUF_THRESH_OVFLW;
reg [40:1] RXBUF_THRESH_OVRD_REG = RXBUF_THRESH_OVRD;
reg [5:0] RXBUF_THRESH_UNDFLW_REG = RXBUF_THRESH_UNDFLW;
reg [4:0] RXCDRFREQRESET_TIME_REG = RXCDRFREQRESET_TIME;
reg [4:0] RXCDRPHRESET_TIME_REG = RXCDRPHRESET_TIME;
reg [15:0] RXCDR_CFG0_REG = RXCDR_CFG0;
reg [15:0] RXCDR_CFG0_GEN3_REG = RXCDR_CFG0_GEN3;
reg [15:0] RXCDR_CFG1_REG = RXCDR_CFG1;
reg [15:0] RXCDR_CFG1_GEN3_REG = RXCDR_CFG1_GEN3;
reg [15:0] RXCDR_CFG2_REG = RXCDR_CFG2;
reg [9:0] RXCDR_CFG2_GEN2_REG = RXCDR_CFG2_GEN2;
reg [15:0] RXCDR_CFG2_GEN3_REG = RXCDR_CFG2_GEN3;
reg [15:0] RXCDR_CFG2_GEN4_REG = RXCDR_CFG2_GEN4;
reg [15:0] RXCDR_CFG3_REG = RXCDR_CFG3;
reg [5:0] RXCDR_CFG3_GEN2_REG = RXCDR_CFG3_GEN2;
reg [15:0] RXCDR_CFG3_GEN3_REG = RXCDR_CFG3_GEN3;
reg [15:0] RXCDR_CFG3_GEN4_REG = RXCDR_CFG3_GEN4;
reg [15:0] RXCDR_CFG4_REG = RXCDR_CFG4;
reg [15:0] RXCDR_CFG4_GEN3_REG = RXCDR_CFG4_GEN3;
reg [15:0] RXCDR_CFG5_REG = RXCDR_CFG5;
reg [15:0] RXCDR_CFG5_GEN3_REG = RXCDR_CFG5_GEN3;
reg [0:0] RXCDR_FR_RESET_ON_EIDLE_REG = RXCDR_FR_RESET_ON_EIDLE;
reg [0:0] RXCDR_HOLD_DURING_EIDLE_REG = RXCDR_HOLD_DURING_EIDLE;
reg [15:0] RXCDR_LOCK_CFG0_REG = RXCDR_LOCK_CFG0;
reg [15:0] RXCDR_LOCK_CFG1_REG = RXCDR_LOCK_CFG1;
reg [15:0] RXCDR_LOCK_CFG2_REG = RXCDR_LOCK_CFG2;
reg [15:0] RXCDR_LOCK_CFG3_REG = RXCDR_LOCK_CFG3;
reg [15:0] RXCDR_LOCK_CFG4_REG = RXCDR_LOCK_CFG4;
reg [0:0] RXCDR_PH_RESET_ON_EIDLE_REG = RXCDR_PH_RESET_ON_EIDLE;
reg [15:0] RXCFOK_CFG0_REG = RXCFOK_CFG0;
reg [15:0] RXCFOK_CFG1_REG = RXCFOK_CFG1;
reg [15:0] RXCFOK_CFG2_REG = RXCFOK_CFG2;
reg [15:0] RXCKCAL1_IQ_LOOP_RST_CFG_REG = RXCKCAL1_IQ_LOOP_RST_CFG;
reg [15:0] RXCKCAL1_I_LOOP_RST_CFG_REG = RXCKCAL1_I_LOOP_RST_CFG;
reg [15:0] RXCKCAL1_Q_LOOP_RST_CFG_REG = RXCKCAL1_Q_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_DX_LOOP_RST_CFG_REG = RXCKCAL2_DX_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_D_LOOP_RST_CFG_REG = RXCKCAL2_D_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_S_LOOP_RST_CFG_REG = RXCKCAL2_S_LOOP_RST_CFG;
reg [15:0] RXCKCAL2_X_LOOP_RST_CFG_REG = RXCKCAL2_X_LOOP_RST_CFG;
reg [6:0] RXDFELPMRESET_TIME_REG = RXDFELPMRESET_TIME;
reg [15:0] RXDFELPM_KL_CFG0_REG = RXDFELPM_KL_CFG0;
reg [15:0] RXDFELPM_KL_CFG1_REG = RXDFELPM_KL_CFG1;
reg [15:0] RXDFELPM_KL_CFG2_REG = RXDFELPM_KL_CFG2;
reg [15:0] RXDFE_CFG0_REG = RXDFE_CFG0;
reg [15:0] RXDFE_CFG1_REG = RXDFE_CFG1;
reg [15:0] RXDFE_GC_CFG0_REG = RXDFE_GC_CFG0;
reg [15:0] RXDFE_GC_CFG1_REG = RXDFE_GC_CFG1;
reg [15:0] RXDFE_GC_CFG2_REG = RXDFE_GC_CFG2;
reg [15:0] RXDFE_H2_CFG0_REG = RXDFE_H2_CFG0;
reg [15:0] RXDFE_H2_CFG1_REG = RXDFE_H2_CFG1;
reg [15:0] RXDFE_H3_CFG0_REG = RXDFE_H3_CFG0;
reg [15:0] RXDFE_H3_CFG1_REG = RXDFE_H3_CFG1;
reg [15:0] RXDFE_H4_CFG0_REG = RXDFE_H4_CFG0;
reg [15:0] RXDFE_H4_CFG1_REG = RXDFE_H4_CFG1;
reg [15:0] RXDFE_H5_CFG0_REG = RXDFE_H5_CFG0;
reg [15:0] RXDFE_H5_CFG1_REG = RXDFE_H5_CFG1;
reg [15:0] RXDFE_H6_CFG0_REG = RXDFE_H6_CFG0;
reg [15:0] RXDFE_H6_CFG1_REG = RXDFE_H6_CFG1;
reg [15:0] RXDFE_H7_CFG0_REG = RXDFE_H7_CFG0;
reg [15:0] RXDFE_H7_CFG1_REG = RXDFE_H7_CFG1;
reg [15:0] RXDFE_H8_CFG0_REG = RXDFE_H8_CFG0;
reg [15:0] RXDFE_H8_CFG1_REG = RXDFE_H8_CFG1;
reg [15:0] RXDFE_H9_CFG0_REG = RXDFE_H9_CFG0;
reg [15:0] RXDFE_H9_CFG1_REG = RXDFE_H9_CFG1;
reg [15:0] RXDFE_HA_CFG0_REG = RXDFE_HA_CFG0;
reg [15:0] RXDFE_HA_CFG1_REG = RXDFE_HA_CFG1;
reg [15:0] RXDFE_HB_CFG0_REG = RXDFE_HB_CFG0;
reg [15:0] RXDFE_HB_CFG1_REG = RXDFE_HB_CFG1;
reg [15:0] RXDFE_HC_CFG0_REG = RXDFE_HC_CFG0;
reg [15:0] RXDFE_HC_CFG1_REG = RXDFE_HC_CFG1;
reg [15:0] RXDFE_HD_CFG0_REG = RXDFE_HD_CFG0;
reg [15:0] RXDFE_HD_CFG1_REG = RXDFE_HD_CFG1;
reg [15:0] RXDFE_HE_CFG0_REG = RXDFE_HE_CFG0;
reg [15:0] RXDFE_HE_CFG1_REG = RXDFE_HE_CFG1;
reg [15:0] RXDFE_HF_CFG0_REG = RXDFE_HF_CFG0;
reg [15:0] RXDFE_HF_CFG1_REG = RXDFE_HF_CFG1;
reg [15:0] RXDFE_KH_CFG0_REG = RXDFE_KH_CFG0;
reg [15:0] RXDFE_KH_CFG1_REG = RXDFE_KH_CFG1;
reg [15:0] RXDFE_KH_CFG2_REG = RXDFE_KH_CFG2;
reg [15:0] RXDFE_KH_CFG3_REG = RXDFE_KH_CFG3;
reg [15:0] RXDFE_OS_CFG0_REG = RXDFE_OS_CFG0;
reg [15:0] RXDFE_OS_CFG1_REG = RXDFE_OS_CFG1;
reg [15:0] RXDFE_UT_CFG0_REG = RXDFE_UT_CFG0;
reg [15:0] RXDFE_UT_CFG1_REG = RXDFE_UT_CFG1;
reg [15:0] RXDFE_UT_CFG2_REG = RXDFE_UT_CFG2;
reg [15:0] RXDFE_VP_CFG0_REG = RXDFE_VP_CFG0;
reg [15:0] RXDFE_VP_CFG1_REG = RXDFE_VP_CFG1;
reg [15:0] RXDLY_CFG_REG = RXDLY_CFG;
reg [15:0] RXDLY_LCFG_REG = RXDLY_LCFG;
reg [72:1] RXELECIDLE_CFG_REG = RXELECIDLE_CFG;
reg [2:0] RXGBOX_FIFO_INIT_RD_ADDR_REG = RXGBOX_FIFO_INIT_RD_ADDR;
reg [40:1] RXGEARBOX_EN_REG = RXGEARBOX_EN;
reg [4:0] RXISCANRESET_TIME_REG = RXISCANRESET_TIME;
reg [15:0] RXLPM_CFG_REG = RXLPM_CFG;
reg [15:0] RXLPM_GC_CFG_REG = RXLPM_GC_CFG;
reg [15:0] RXLPM_KH_CFG0_REG = RXLPM_KH_CFG0;
reg [15:0] RXLPM_KH_CFG1_REG = RXLPM_KH_CFG1;
reg [15:0] RXLPM_OS_CFG0_REG = RXLPM_OS_CFG0;
reg [15:0] RXLPM_OS_CFG1_REG = RXLPM_OS_CFG1;
reg [8:0] RXOOB_CFG_REG = RXOOB_CFG;
reg [48:1] RXOOB_CLK_CFG_REG = RXOOB_CLK_CFG;
reg [4:0] RXOSCALRESET_TIME_REG = RXOSCALRESET_TIME;
reg [5:0] RXOUT_DIV_REG = RXOUT_DIV;
reg [4:0] RXPCSRESET_TIME_REG = RXPCSRESET_TIME;
reg [15:0] RXPHBEACON_CFG_REG = RXPHBEACON_CFG;
reg [15:0] RXPHDLY_CFG_REG = RXPHDLY_CFG;
reg [15:0] RXPHSAMP_CFG_REG = RXPHSAMP_CFG;
reg [15:0] RXPHSLIP_CFG_REG = RXPHSLIP_CFG;
reg [4:0] RXPH_MONITOR_SEL_REG = RXPH_MONITOR_SEL;
reg [15:0] RXPI_CFG0_REG = RXPI_CFG0;
reg [15:0] RXPI_CFG1_REG = RXPI_CFG1;
reg [64:1] RXPMACLK_SEL_REG = RXPMACLK_SEL;
reg [4:0] RXPMARESET_TIME_REG = RXPMARESET_TIME;
reg [0:0] RXPRBS_ERR_LOOPBACK_REG = RXPRBS_ERR_LOOPBACK;
reg [7:0] RXPRBS_LINKACQ_CNT_REG = RXPRBS_LINKACQ_CNT;
reg [0:0] RXREFCLKDIV2_SEL_REG = RXREFCLKDIV2_SEL;
reg [3:0] RXSLIDE_AUTO_WAIT_REG = RXSLIDE_AUTO_WAIT;
reg [32:1] RXSLIDE_MODE_REG = RXSLIDE_MODE;
reg [0:0] RXSYNC_MULTILANE_REG = RXSYNC_MULTILANE;
reg [0:0] RXSYNC_OVRD_REG = RXSYNC_OVRD;
reg [0:0] RXSYNC_SKIP_DA_REG = RXSYNC_SKIP_DA;
reg [0:0] RX_AFE_CM_EN_REG = RX_AFE_CM_EN;
reg [15:0] RX_BIAS_CFG0_REG = RX_BIAS_CFG0;
reg [5:0] RX_BUFFER_CFG_REG = RX_BUFFER_CFG;
reg [0:0] RX_CAPFF_SARC_ENB_REG = RX_CAPFF_SARC_ENB;
reg [5:0] RX_CLK25_DIV_REG = RX_CLK25_DIV;
reg [0:0] RX_CLKMUX_EN_REG = RX_CLKMUX_EN;
reg [4:0] RX_CLK_SLIP_OVRD_REG = RX_CLK_SLIP_OVRD;
reg [3:0] RX_CM_BUF_CFG_REG = RX_CM_BUF_CFG;
reg [0:0] RX_CM_BUF_PD_REG = RX_CM_BUF_PD;
reg [1:0] RX_CM_SEL_REG = RX_CM_SEL;
reg [3:0] RX_CM_TRIM_REG = RX_CM_TRIM;
reg [0:0] RX_CTLE_PWR_SAVING_REG = RX_CTLE_PWR_SAVING;
reg [3:0] RX_CTLE_RES_CTRL_REG = RX_CTLE_RES_CTRL;
reg [7:0] RX_DATA_WIDTH_REG = RX_DATA_WIDTH;
reg [5:0] RX_DDI_SEL_REG = RX_DDI_SEL;
reg [40:1] RX_DEFER_RESET_BUF_EN_REG = RX_DEFER_RESET_BUF_EN;
reg [2:0] RX_DEGEN_CTRL_REG = RX_DEGEN_CTRL;
reg [3:0] RX_DFELPM_CFG0_REG = RX_DFELPM_CFG0;
reg [0:0] RX_DFELPM_CFG1_REG = RX_DFELPM_CFG1;
reg [0:0] RX_DFELPM_KLKH_AGC_STUP_EN_REG = RX_DFELPM_KLKH_AGC_STUP_EN;
reg [2:0] RX_DFE_AGC_CFG1_REG = RX_DFE_AGC_CFG1;
reg [1:0] RX_DFE_KL_LPM_KH_CFG0_REG = RX_DFE_KL_LPM_KH_CFG0;
reg [2:0] RX_DFE_KL_LPM_KH_CFG1_REG = RX_DFE_KL_LPM_KH_CFG1;
reg [1:0] RX_DFE_KL_LPM_KL_CFG0_REG = RX_DFE_KL_LPM_KL_CFG0;
reg [2:0] RX_DFE_KL_LPM_KL_CFG1_REG = RX_DFE_KL_LPM_KL_CFG1;
reg [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE_REG = RX_DFE_LPM_HOLD_DURING_EIDLE;
reg [40:1] RX_DISPERR_SEQ_MATCH_REG = RX_DISPERR_SEQ_MATCH;
reg [4:0] RX_DIVRESET_TIME_REG = RX_DIVRESET_TIME;
reg [0:0] RX_EN_CTLE_RCAL_B_REG = RX_EN_CTLE_RCAL_B;
reg [0:0] RX_EN_SUM_RCAL_B_REG = RX_EN_SUM_RCAL_B;
reg [6:0] RX_EYESCAN_VS_CODE_REG = RX_EYESCAN_VS_CODE;
reg [0:0] RX_EYESCAN_VS_NEG_DIR_REG = RX_EYESCAN_VS_NEG_DIR;
reg [1:0] RX_EYESCAN_VS_RANGE_REG = RX_EYESCAN_VS_RANGE;
reg [0:0] RX_EYESCAN_VS_UT_SIGN_REG = RX_EYESCAN_VS_UT_SIGN;
reg [0:0] RX_FABINT_USRCLK_FLOP_REG = RX_FABINT_USRCLK_FLOP;
reg [0:0] RX_I2V_FILTER_EN_REG = RX_I2V_FILTER_EN;
reg [1:0] RX_INT_DATAWIDTH_REG = RX_INT_DATAWIDTH;
reg [0:0] RX_PMA_POWER_SAVE_REG = RX_PMA_POWER_SAVE;
reg [15:0] RX_PMA_RSV0_REG = RX_PMA_RSV0;
real RX_PROGDIV_CFG_REG = RX_PROGDIV_CFG;
reg [15:0] RX_PROGDIV_RATE_REG = RX_PROGDIV_RATE;
reg [3:0] RX_RESLOAD_CTRL_REG = RX_RESLOAD_CTRL;
reg [0:0] RX_RESLOAD_OVRD_REG = RX_RESLOAD_OVRD;
reg [2:0] RX_SAMPLE_PERIOD_REG = RX_SAMPLE_PERIOD;
reg [5:0] RX_SIG_VALID_DLY_REG = RX_SIG_VALID_DLY;
reg [0:0] RX_SUM_DEGEN_AVTT_OVERITE_REG = RX_SUM_DEGEN_AVTT_OVERITE;
reg [0:0] RX_SUM_DFETAPREP_EN_REG = RX_SUM_DFETAPREP_EN;
reg [3:0] RX_SUM_IREF_TUNE_REG = RX_SUM_IREF_TUNE;
reg [0:0] RX_SUM_PWR_SAVING_REG = RX_SUM_PWR_SAVING;
reg [3:0] RX_SUM_RES_CTRL_REG = RX_SUM_RES_CTRL;
reg [3:0] RX_SUM_VCMTUNE_REG = RX_SUM_VCMTUNE;
reg [0:0] RX_SUM_VCM_BIAS_TUNE_EN_REG = RX_SUM_VCM_BIAS_TUNE_EN;
reg [0:0] RX_SUM_VCM_OVWR_REG = RX_SUM_VCM_OVWR;
reg [2:0] RX_SUM_VREF_TUNE_REG = RX_SUM_VREF_TUNE;
reg [1:0] RX_TUNE_AFE_OS_REG = RX_TUNE_AFE_OS;
reg [2:0] RX_VREG_CTRL_REG = RX_VREG_CTRL;
reg [0:0] RX_VREG_PDB_REG = RX_VREG_PDB;
reg [1:0] RX_WIDEMODE_CDR_REG = RX_WIDEMODE_CDR;
reg [1:0] RX_WIDEMODE_CDR_GEN3_REG = RX_WIDEMODE_CDR_GEN3;
reg [1:0] RX_WIDEMODE_CDR_GEN4_REG = RX_WIDEMODE_CDR_GEN4;
reg [40:1] RX_XCLK_SEL_REG = RX_XCLK_SEL;
reg [0:0] RX_XMODE_SEL_REG = RX_XMODE_SEL;
reg [0:0] SAMPLE_CLK_PHASE_REG = SAMPLE_CLK_PHASE;
reg [0:0] SAS_12G_MODE_REG = SAS_12G_MODE;
reg [3:0] SATA_BURST_SEQ_LEN_REG = SATA_BURST_SEQ_LEN;
reg [2:0] SATA_BURST_VAL_REG = SATA_BURST_VAL;
reg [88:1] SATA_CPLL_CFG_REG = SATA_CPLL_CFG;
reg [2:0] SATA_EIDLE_VAL_REG = SATA_EIDLE_VAL;
reg [40:1] SHOW_REALIGN_COMMA_REG = SHOW_REALIGN_COMMA;
reg [160:1] SIM_DEVICE_REG = SIM_DEVICE;
reg [48:1] SIM_MODE_REG = SIM_MODE;
reg [40:1] SIM_RECEIVER_DETECT_PASS_REG = SIM_RECEIVER_DETECT_PASS;
reg [40:1] SIM_RESET_SPEEDUP_REG = SIM_RESET_SPEEDUP;
reg [32:1] SIM_TX_EIDLE_DRIVE_LEVEL_REG = SIM_TX_EIDLE_DRIVE_LEVEL;
reg [0:0] SRSTMODE_REG = SRSTMODE;
reg [1:0] TAPDLY_SET_TX_REG = TAPDLY_SET_TX;
reg [14:0] TERM_RCAL_CFG_REG = TERM_RCAL_CFG;
reg [2:0] TERM_RCAL_OVRD_REG = TERM_RCAL_OVRD;
reg [7:0] TRANS_TIME_RATE_REG = TRANS_TIME_RATE;
reg [7:0] TST_RSV0_REG = TST_RSV0;
reg [7:0] TST_RSV1_REG = TST_RSV1;
reg [40:1] TXBUF_EN_REG = TXBUF_EN;
reg [40:1] TXBUF_RESET_ON_RATE_CHANGE_REG = TXBUF_RESET_ON_RATE_CHANGE;
reg [15:0] TXDLY_CFG_REG = TXDLY_CFG;
reg [15:0] TXDLY_LCFG_REG = TXDLY_LCFG;
reg [1:0] TXDRV_FREQBAND_REG = TXDRV_FREQBAND;
reg [15:0] TXFE_CFG0_REG = TXFE_CFG0;
reg [15:0] TXFE_CFG1_REG = TXFE_CFG1;
reg [15:0] TXFE_CFG2_REG = TXFE_CFG2;
reg [15:0] TXFE_CFG3_REG = TXFE_CFG3;
reg [32:1] TXFIFO_ADDR_CFG_REG = TXFIFO_ADDR_CFG;
reg [2:0] TXGBOX_FIFO_INIT_RD_ADDR_REG = TXGBOX_FIFO_INIT_RD_ADDR;
reg [40:1] TXGEARBOX_EN_REG = TXGEARBOX_EN;
reg [5:0] TXOUT_DIV_REG = TXOUT_DIV;
reg [4:0] TXPCSRESET_TIME_REG = TXPCSRESET_TIME;
reg [15:0] TXPHDLY_CFG0_REG = TXPHDLY_CFG0;
reg [15:0] TXPHDLY_CFG1_REG = TXPHDLY_CFG1;
reg [15:0] TXPH_CFG_REG = TXPH_CFG;
reg [15:0] TXPH_CFG2_REG = TXPH_CFG2;
reg [4:0] TXPH_MONITOR_SEL_REG = TXPH_MONITOR_SEL;
reg [15:0] TXPI_CFG0_REG = TXPI_CFG0;
reg [15:0] TXPI_CFG1_REG = TXPI_CFG1;
reg [0:0] TXPI_GRAY_SEL_REG = TXPI_GRAY_SEL;
reg [0:0] TXPI_INVSTROBE_SEL_REG = TXPI_INVSTROBE_SEL;
reg [0:0] TXPI_PPM_REG = TXPI_PPM;
reg [7:0] TXPI_PPM_CFG_REG = TXPI_PPM_CFG;
reg [2:0] TXPI_SYNFREQ_PPM_REG = TXPI_SYNFREQ_PPM;
reg [4:0] TXPMARESET_TIME_REG = TXPMARESET_TIME;
reg [0:0] TXREFCLKDIV2_SEL_REG = TXREFCLKDIV2_SEL;
reg [1:0] TXSWBST_BST_REG = TXSWBST_BST;
reg [0:0] TXSWBST_EN_REG = TXSWBST_EN;
reg [2:0] TXSWBST_MAG_REG = TXSWBST_MAG;
reg [0:0] TXSYNC_MULTILANE_REG = TXSYNC_MULTILANE;
reg [0:0] TXSYNC_OVRD_REG = TXSYNC_OVRD;
reg [0:0] TXSYNC_SKIP_DA_REG = TXSYNC_SKIP_DA;
reg [5:0] TX_CLK25_DIV_REG = TX_CLK25_DIV;
reg [0:0] TX_CLKMUX_EN_REG = TX_CLKMUX_EN;
reg [7:0] TX_DATA_WIDTH_REG = TX_DATA_WIDTH;
reg [15:0] TX_DCC_LOOP_RST_CFG_REG = TX_DCC_LOOP_RST_CFG;
reg [5:0] TX_DEEMPH0_REG = TX_DEEMPH0;
reg [5:0] TX_DEEMPH1_REG = TX_DEEMPH1;
reg [5:0] TX_DEEMPH2_REG = TX_DEEMPH2;
reg [5:0] TX_DEEMPH3_REG = TX_DEEMPH3;
reg [4:0] TX_DIVRESET_TIME_REG = TX_DIVRESET_TIME;
reg [64:1] TX_DRIVE_MODE_REG = TX_DRIVE_MODE;
reg [2:0] TX_EIDLE_ASSERT_DELAY_REG = TX_EIDLE_ASSERT_DELAY;
reg [2:0] TX_EIDLE_DEASSERT_DELAY_REG = TX_EIDLE_DEASSERT_DELAY;
reg [0:0] TX_FABINT_USRCLK_FLOP_REG = TX_FABINT_USRCLK_FLOP;
reg [0:0] TX_FIFO_BYP_EN_REG = TX_FIFO_BYP_EN;
reg [0:0] TX_IDLE_DATA_ZERO_REG = TX_IDLE_DATA_ZERO;
reg [1:0] TX_INT_DATAWIDTH_REG = TX_INT_DATAWIDTH;
reg [40:1] TX_LOOPBACK_DRIVE_HIZ_REG = TX_LOOPBACK_DRIVE_HIZ;
reg [0:0] TX_MAINCURSOR_SEL_REG = TX_MAINCURSOR_SEL;
reg [6:0] TX_MARGIN_FULL_0_REG = TX_MARGIN_FULL_0;
reg [6:0] TX_MARGIN_FULL_1_REG = TX_MARGIN_FULL_1;
reg [6:0] TX_MARGIN_FULL_2_REG = TX_MARGIN_FULL_2;
reg [6:0] TX_MARGIN_FULL_3_REG = TX_MARGIN_FULL_3;
reg [6:0] TX_MARGIN_FULL_4_REG = TX_MARGIN_FULL_4;
reg [6:0] TX_MARGIN_LOW_0_REG = TX_MARGIN_LOW_0;
reg [6:0] TX_MARGIN_LOW_1_REG = TX_MARGIN_LOW_1;
reg [6:0] TX_MARGIN_LOW_2_REG = TX_MARGIN_LOW_2;
reg [6:0] TX_MARGIN_LOW_3_REG = TX_MARGIN_LOW_3;
reg [6:0] TX_MARGIN_LOW_4_REG = TX_MARGIN_LOW_4;
reg [15:0] TX_PHICAL_CFG0_REG = TX_PHICAL_CFG0;
reg [15:0] TX_PHICAL_CFG1_REG = TX_PHICAL_CFG1;
reg [1:0] TX_PI_BIASSET_REG = TX_PI_BIASSET;
reg [0:0] TX_PMADATA_OPT_REG = TX_PMADATA_OPT;
reg [0:0] TX_PMA_POWER_SAVE_REG = TX_PMA_POWER_SAVE;
reg [15:0] TX_PMA_RSV0_REG = TX_PMA_RSV0;
reg [15:0] TX_PMA_RSV1_REG = TX_PMA_RSV1;
reg [48:1] TX_PROGCLK_SEL_REG = TX_PROGCLK_SEL;
real TX_PROGDIV_CFG_REG = TX_PROGDIV_CFG;
reg [15:0] TX_PROGDIV_RATE_REG = TX_PROGDIV_RATE;
reg [13:0] TX_RXDETECT_CFG_REG = TX_RXDETECT_CFG;
reg [2:0] TX_RXDETECT_REF_REG = TX_RXDETECT_REF;
reg [2:0] TX_SAMPLE_PERIOD_REG = TX_SAMPLE_PERIOD;
reg [1:0] TX_SW_MEAS_REG = TX_SW_MEAS;
reg [2:0] TX_VREG_CTRL_REG = TX_VREG_CTRL;
reg [0:0] TX_VREG_PDB_REG = TX_VREG_PDB;
reg [1:0] TX_VREG_VREFSEL_REG = TX_VREG_VREFSEL;
reg [40:1] TX_XCLK_SEL_REG = TX_XCLK_SEL;
reg [0:0] USB_BOTH_BURST_IDLE_REG = USB_BOTH_BURST_IDLE;
reg [6:0] USB_BURSTMAX_U3WAKE_REG = USB_BURSTMAX_U3WAKE;
reg [6:0] USB_BURSTMIN_U3WAKE_REG = USB_BURSTMIN_U3WAKE;
reg [0:0] USB_CLK_COR_EQ_EN_REG = USB_CLK_COR_EQ_EN;
reg [0:0] USB_EXT_CNTL_REG = USB_EXT_CNTL;
reg [9:0] USB_IDLEMAX_POLLING_REG = USB_IDLEMAX_POLLING;
reg [9:0] USB_IDLEMIN_POLLING_REG = USB_IDLEMIN_POLLING;
reg [8:0] USB_LFPSPING_BURST_REG = USB_LFPSPING_BURST;
reg [8:0] USB_LFPSPOLLING_BURST_REG = USB_LFPSPOLLING_BURST;
reg [8:0] USB_LFPSPOLLING_IDLE_MS_REG = USB_LFPSPOLLING_IDLE_MS;
reg [8:0] USB_LFPSU1EXIT_BURST_REG = USB_LFPSU1EXIT_BURST;
reg [8:0] USB_LFPSU2LPEXIT_BURST_MS_REG = USB_LFPSU2LPEXIT_BURST_MS;
reg [8:0] USB_LFPSU3WAKE_BURST_MS_REG = USB_LFPSU3WAKE_BURST_MS;
reg [3:0] USB_LFPS_TPERIOD_REG = USB_LFPS_TPERIOD;
reg [0:0] USB_LFPS_TPERIOD_ACCURATE_REG = USB_LFPS_TPERIOD_ACCURATE;
reg [0:0] USB_MODE_REG = USB_MODE;
reg [0:0] USB_PCIE_ERR_REP_DIS_REG = USB_PCIE_ERR_REP_DIS;
reg [5:0] USB_PING_SATA_MAX_INIT_REG = USB_PING_SATA_MAX_INIT;
reg [5:0] USB_PING_SATA_MIN_INIT_REG = USB_PING_SATA_MIN_INIT;
reg [5:0] USB_POLL_SATA_MAX_BURST_REG = USB_POLL_SATA_MAX_BURST;
reg [5:0] USB_POLL_SATA_MIN_BURST_REG = USB_POLL_SATA_MIN_BURST;
reg [0:0] USB_RAW_ELEC_REG = USB_RAW_ELEC;
reg [0:0] USB_RXIDLE_P0_CTRL_REG = USB_RXIDLE_P0_CTRL;
reg [0:0] USB_TXIDLE_TUNE_ENABLE_REG = USB_TXIDLE_TUNE_ENABLE;
reg [5:0] USB_U1_SATA_MAX_WAKE_REG = USB_U1_SATA_MAX_WAKE;
reg [5:0] USB_U1_SATA_MIN_WAKE_REG = USB_U1_SATA_MIN_WAKE;
reg [6:0] USB_U2_SAS_MAX_COM_REG = USB_U2_SAS_MAX_COM;
reg [5:0] USB_U2_SAS_MIN_COM_REG = USB_U2_SAS_MIN_COM;
reg [0:0] USE_PCS_CLK_PHASE_SEL_REG = USE_PCS_CLK_PHASE_SEL;
reg [0:0] Y_ALL_MODE_REG = Y_ALL_MODE;
`endif
reg [0:0] AEN_CDRSTEPSEL_REG = 1'b0;
reg [0:0] AEN_CPLL_REG = 1'b0;
reg [0:0] AEN_LOOPBACK_REG = 1'b0;
reg [0:0] AEN_MASTER_REG = 1'b0;
reg [0:0] AEN_PD_AND_EIDLE_REG = 1'b0;
reg [0:0] AEN_POLARITY_REG = 1'b0;
reg [0:0] AEN_PRBS_REG = 1'b0;
reg [0:0] AEN_RESET_REG = 1'b0;
reg [0:0] AEN_RXCDR_REG = 1'b0;
reg [0:0] AEN_RXDFE_REG = 1'b0;
reg [0:0] AEN_RXDFELPM_REG = 1'b0;
reg [0:0] AEN_RXOUTCLK_SEL_REG = 1'b0;
reg [0:0] AEN_RXPHDLY_REG = 1'b0;
reg [0:0] AEN_RXPLLCLK_SEL_REG = 1'b0;
reg [0:0] AEN_RXSYSCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TXMUXDCD_REG = 1'b0;
reg [0:0] AEN_TXOUTCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TXPHDLY_REG = 1'b0;
reg [0:0] AEN_TXPI_PPM_REG = 1'b0;
reg [0:0] AEN_TXPLLCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TXSYSCLK_SEL_REG = 1'b0;
reg [0:0] AEN_TX_DRIVE_MODE_REG = 1'b0;
reg [15:0] AMONITOR_CFG_REG = 16'h0FC0;
reg [0:0] A_CPLLLOCKEN_REG = 1'b0;
reg [0:0] A_CPLLPD_REG = 1'b0;
reg [0:0] A_CPLLRESET_REG = 1'b0;
reg [0:0] A_EYESCANRESET_REG = 1'b0;
reg [0:0] A_GTRESETSEL_REG = 1'b0;
reg [0:0] A_GTRXRESET_REG = 1'b0;
reg [0:0] A_GTTXRESET_REG = 1'b0;
reg [80:1] A_LOOPBACK_REG = "NOLOOPBACK";
reg [0:0] A_RXAFECFOKEN_REG = 1'b1;
reg [0:0] A_RXBUFRESET_REG = 1'b0;
reg [0:0] A_RXCDRFREQRESET_REG = 1'b0;
reg [0:0] A_RXCDRHOLD_REG = 1'b0;
reg [0:0] A_RXCDROVRDEN_REG = 1'b0;
reg [0:0] A_RXCDRRESET_REG = 1'b0;
reg [0:0] A_RXCKCALRESET_REG = 1'b0;
reg [0:0] A_RXDFEAGCHOLD_REG = 1'b0;
reg [0:0] A_RXDFEAGCOVRDEN_REG = 1'b0;
reg [3:0] A_RXDFECFOKFCNUM_REG = 4'b0000;
reg [0:0] A_RXDFECFOKFEN_REG = 1'b0;
reg [0:0] A_RXDFECFOKFPULSE_REG = 1'b0;
reg [0:0] A_RXDFECFOKHOLD_REG = 1'b0;
reg [0:0] A_RXDFECFOKOVREN_REG = 1'b0;
reg [0:0] A_RXDFEKHHOLD_REG = 0;
reg [0:0] A_RXDFEKHOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFELFHOLD_REG = 1'b0;
reg [0:0] A_RXDFELFOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFELPMRESET_REG = 1'b0;
reg [0:0] A_RXDFETAP10HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP10OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP11HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP11OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP12HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP12OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP13HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP13OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP14HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP14OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP15HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP15OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP2HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP2OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP3HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP3OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP4HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP4OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP5HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP5OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP6HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP6OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP7HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP7OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP8HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP8OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFETAP9HOLD_REG = 1'b0;
reg [0:0] A_RXDFETAP9OVRDEN_REG = 1'b0;
reg [0:0] A_RXDFEUTHOLD_REG = 1'b0;
reg [0:0] A_RXDFEUTOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFEVPHOLD_REG = 1'b0;
reg [0:0] A_RXDFEVPOVRDEN_REG = 1'b0;
reg [0:0] A_RXDFEXYDEN_REG = 1'b0;
reg [0:0] A_RXDLYBYPASS_REG = 1'b0;
reg [0:0] A_RXDLYEN_REG = 1'b0;
reg [0:0] A_RXDLYOVRDEN_REG = 1'b0;
reg [0:0] A_RXDLYSRESET_REG = 1'b0;
reg [0:0] A_RXLPMEN_REG = 1'b0;
reg [0:0] A_RXLPMGCHOLD_REG = 1'b0;
reg [0:0] A_RXLPMGCOVRDEN_REG = 1'b0;
reg [0:0] A_RXLPMHFHOLD_REG = 1'b0;
reg [0:0] A_RXLPMHFOVRDEN_REG = 1'b0;
reg [0:0] A_RXLPMLFHOLD_REG = 1'b0;
reg [0:0] A_RXLPMLFKLOVRDEN_REG = 1'b0;
reg [0:0] A_RXLPMOSHOLD_REG = 1'b0;
reg [0:0] A_RXLPMOSOVRDEN_REG = 1'b0;
reg [1:0] A_RXMONITORSEL_REG = 2'b00;
reg [0:0] A_RXOOBRESET_REG = 1'b0;
reg [0:0] A_RXOSHOLD_REG = 1'b0;
reg [0:0] A_RXOSOVRDEN_REG = 1'b0;
reg [128:1] A_RXOUTCLKSEL_REG = "DISABLED";
reg [0:0] A_RXPCSRESET_REG = 1'b0;
reg [24:1] A_RXPD_REG = "P0";
reg [0:0] A_RXPHALIGN_REG = 1'b0;
reg [0:0] A_RXPHALIGNEN_REG = 1'b0;
reg [0:0] A_RXPHDLYPD_REG = 1'b0;
reg [0:0] A_RXPHDLYRESET_REG = 1'b0;
reg [64:1] A_RXPLLCLKSEL_REG = "QPLLCLK1";
reg [0:0] A_RXPMARESET_REG = 1'b0;
reg [0:0] A_RXPOLARITY_REG = 1'b0;
reg [0:0] A_RXPRBSCNTRESET_REG = 1'b0;
reg [48:1] A_RXPRBSSEL_REG = "PRBS7";
reg [88:1] A_RXSYSCLKSEL_REG = "CPLLREFCLK";
reg [2:0] A_TXBUFDIFFCTRL_REG = 3'b100;
reg [0:0] A_TXDCCRESET_REG = 1'b0;
reg [1:0] A_TXDEEMPH_REG = 2'b00;
reg [0:0] A_TXDLYBYPASS_REG = 1'b0;
reg [0:0] A_TXDLYEN_REG = 1'b0;
reg [0:0] A_TXDLYOVRDEN_REG = 1'b0;
reg [0:0] A_TXDLYSRESET_REG = 1'b0;
reg [0:0] A_TXELECIDLE_REG = 1'b0;
reg [0:0] A_TXINHIBIT_REG = 1'b0;
reg [6:0] A_TXMAINCURSOR_REG = 7'b0000000;
reg [2:0] A_TXMARGIN_REG = 3'b000;
reg [0:0] A_TXMUXDCDEXHOLD_REG = 1'b0;
reg [0:0] A_TXMUXDCDORWREN_REG = 1'b0;
reg [128:1] A_TXOUTCLKSEL_REG = "DISABLED";
reg [0:0] A_TXPCSRESET_REG = 1'b0;
reg [24:1] A_TXPD_REG = "P0";
reg [0:0] A_TXPHALIGN_REG = 1'b0;
reg [0:0] A_TXPHALIGNEN_REG = 1'b0;
reg [0:0] A_TXPHDLYPD_REG = 1'b0;
reg [0:0] A_TXPHDLYRESET_REG = 1'b0;
reg [0:0] A_TXPHINIT_REG = 1'b0;
reg [0:0] A_TXPHOVRDEN_REG = 1'b0;
reg [0:0] A_TXPIPPMOVRDEN_REG = 1'b0;
reg [0:0] A_TXPIPPMPD_REG = 1'b0;
reg [0:0] A_TXPIPPMSEL_REG = 1'b0;
reg [64:1] A_TXPLLCLKSEL_REG = "QPLLCLK1";
reg [0:0] A_TXPMARESET_REG = 1'b0;
reg [0:0] A_TXPOLARITY_REG = 1'b0;
reg [4:0] A_TXPOSTCURSOR_REG = 5'b00000;
reg [0:0] A_TXPRBSFORCEERR_REG = 1'b0;
reg [96:1] A_TXPRBSSEL_REG = "PRBS7";
reg [4:0] A_TXPRECURSOR_REG = 5'b00000;
reg [0:0] A_TXRESETSEL_REG = 1'b0;
reg [0:0] A_TXSWING_REG = 1'b0;
reg [88:1] A_TXSYSCLKSEL_REG = "CPLLREFCLK";
reg [1:0] BSR_ENABLE_REG = 2'b00;
reg [15:0] CSSD_CLK_MASK0_REG = 16'b0000000000000000;
reg [15:0] CSSD_CLK_MASK1_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG0_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG1_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG10_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG2_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG3_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG4_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG5_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG6_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG7_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG8_REG = 16'b0000000000000000;
reg [15:0] CSSD_REG9_REG = 16'b0000000000000000;
reg [40:1] GEN_RXUSRCLK_REG = "TRUE";
reg [40:1] GEN_TXUSRCLK_REG = "TRUE";
reg [0:0] GT_INSTANTIATED_REG = 1'b1;
reg [15:0] INT_MASK_CFG0_REG = 16'b0000000000000000;
reg [15:0] INT_MASK_CFG1_REG = 16'b0000000000000000;
reg [5:0] RX_DFECFOKFCDAC_REG = 6'b000000;
reg [1:0] RX_VREG_VREFSEL_REG = 2'b01;
reg [0:0] TXOUTCLKPCS_SEL_REG = 1'b0;
reg [9:0] TX_USERPATTERN_DATA0_REG = 10'b0101111100;
reg [9:0] TX_USERPATTERN_DATA1_REG = 10'b0101010101;
reg [9:0] TX_USERPATTERN_DATA2_REG = 10'b1010000011;
reg [9:0] TX_USERPATTERN_DATA3_REG = 10'b1010101010;
reg [9:0] TX_USERPATTERN_DATA4_REG = 10'b0101111100;
reg [9:0] TX_USERPATTERN_DATA5_REG = 10'b0101010101;
reg [9:0] TX_USERPATTERN_DATA6_REG = 10'b1010000011;
reg [9:0] TX_USERPATTERN_DATA7_REG = 10'b1010101010;
`ifdef XIL_XECLIB
wire [63:0] RX_PROGDIV_CFG_BIN;
wire [63:0] TX_PROGDIV_CFG_BIN;
`else
reg [63:0] RX_PROGDIV_CFG_BIN;
reg [63:0] TX_PROGDIV_CFG_BIN;
`endif
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire BUFGTCE_out;
wire BUFGTRESET_out;
wire CPLLFBCLKLOST_out;
wire CPLLLOCK_out;
wire CPLLREFCLKLOST_out;
wire CSSDSTOPCLKDONE_out;
wire DMONITOROUTCLK_out;
wire DRPRDY_out;
wire EYESCANDATAERROR_out;
wire GTPOWERGOOD_out;
wire GTREFCLKMONITOR_out;
wire GTYTXN_out;
wire GTYTXP_out;
wire PCIERATEGEN3_out;
wire PCIERATEIDLE_out;
wire PCIESYNCTXSYNCDONE_out;
wire PCIEUSERGEN3RDY_out;
wire PCIEUSERPHYSTATUSRST_out;
wire PCIEUSERRATESTART_out;
wire PHYSTATUS_out;
wire POWERPRESENT_out;
wire RESETEXCEPTION_out;
wire RXBYTEISALIGNED_out;
wire RXBYTEREALIGN_out;
wire RXCDRLOCK_out;
wire RXCDRPHDONE_out;
wire RXCHANBONDSEQ_out;
wire RXCHANISALIGNED_out;
wire RXCHANREALIGN_out;
wire RXCKCALDONE_out;
wire RXCOMINITDET_out;
wire RXCOMMADET_out;
wire RXCOMSASDET_out;
wire RXCOMWAKEDET_out;
wire RXDLYSRESETDONE_out;
wire RXELECIDLE_out;
wire RXLFPSTRESETDET_out;
wire RXLFPSU2LPEXITDET_out;
wire RXLFPSU3WAKEDET_out;
wire RXOSINTDONE_out;
wire RXOSINTSTARTED_out;
wire RXOSINTSTROBEDONE_out;
wire RXOSINTSTROBESTARTED_out;
wire RXOUTCLKFABRIC_out;
wire RXOUTCLKPCS_out;
wire RXOUTCLK_out;
wire RXPHALIGNDONE_out;
wire RXPHALIGNERR_out;
wire RXPMARESETDONE_out;
wire RXPRBSERR_out;
wire RXPRBSLOCKED_out;
wire RXPRGDIVRESETDONE_out;
wire RXRATEDONE_out;
wire RXRECCLKOUT_out;
wire RXRESETDONE_out;
wire RXSLIDERDY_out;
wire RXSLIPDONE_out;
wire RXSLIPOUTCLKRDY_out;
wire RXSLIPPMARDY_out;
wire RXSYNCDONE_out;
wire RXSYNCOUT_out;
wire RXVALID_out;
wire TXCOMFINISH_out;
wire TXDCCDONE_out;
wire TXDLYSRESETDONE_out;
wire TXOUTCLKFABRIC_out;
wire TXOUTCLKPCS_out;
wire TXOUTCLK_out;
wire TXPHALIGNDONE_out;
wire TXPHINITDONE_out;
wire TXPMARESETDONE_out;
wire TXPRGDIVRESETDONE_out;
wire TXRATEDONE_out;
wire TXRESETDONE_out;
wire TXSYNCDONE_out;
wire TXSYNCOUT_out;
wire [127:0] RXDATA_out;
wire [15:0] DMONITOROUT_out;
wire [15:0] DRPDO_out;
wire [15:0] PCSRSVDOUT_out;
wire [15:0] PINRSRVDAS_out;
wire [15:0] RXCTRL0_out;
wire [15:0] RXCTRL1_out;
wire [17:0] PMASCANOUT_out;
wire [18:0] SCANOUT_out;
wire [1:0] PCIERATEQPLLPD_out;
wire [1:0] PCIERATEQPLLRESET_out;
wire [1:0] RXCLKCORCNT_out;
wire [1:0] RXDATAVALID_out;
wire [1:0] RXHEADERVALID_out;
wire [1:0] RXSTARTOFSEQ_out;
wire [1:0] TXBUFSTATUS_out;
wire [2:0] BUFGTCEMASK_out;
wire [2:0] BUFGTRSTMASK_out;
wire [2:0] RXBUFSTATUS_out;
wire [2:0] RXSTATUS_out;
wire [4:0] RXCHBONDO_out;
wire [5:0] RXHEADER_out;
wire [7:0] RXCTRL2_out;
wire [7:0] RXCTRL3_out;
wire [7:0] RXDATAEXTENDRSVD_out;
wire [7:0] RXMONITOROUT_out;
wire [8:0] BUFGTDIV_out;
wire BSR_SERIAL_in;
wire CDRSTEPDIR_in;
wire CDRSTEPSQ_in;
wire CDRSTEPSX_in;
wire CFGRESET_in;
wire CLKRSVD0_in;
wire CLKRSVD1_in;
wire CPLLFREQLOCK_in;
wire CPLLLOCKDETCLK_in;
wire CPLLLOCKEN_in;
wire CPLLPD_in;
wire CPLLRESET_in;
wire CSSDRSTB_in;
wire CSSDSTOPCLK_in;
wire DMONFIFORESET_in;
wire DMONITORCLK_in;
wire DRPCLK_in;
wire DRPEN_in;
wire DRPRST_in;
wire DRPWE_in;
wire EYESCANRESET_in;
wire EYESCANTRIGGER_in;
wire FREQOS_in;
wire GTGREFCLK_in;
wire GTNORTHREFCLK0_in;
wire GTNORTHREFCLK1_in;
wire GTREFCLK0_in;
wire GTREFCLK1_in;
wire GTRXRESETSEL_in;
wire GTRXRESET_in;
wire GTSOUTHREFCLK0_in;
wire GTSOUTHREFCLK1_in;
wire GTTXRESETSEL_in;
wire GTTXRESET_in;
wire GTYRXN_in;
wire GTYRXP_in;
wire INCPCTRL_in;
wire PCIEEQRXEQADAPTDONE_in;
wire PCIERSTIDLE_in;
wire PCIERSTTXSYNCSTART_in;
wire PCIEUSERRATEDONE_in;
wire PMASCANCLK0_in;
wire PMASCANCLK1_in;
wire PMASCANCLK2_in;
wire PMASCANCLK3_in;
wire PMASCANCLK4_in;
wire PMASCANCLK5_in;
wire PMASCANCLK6_in;
wire PMASCANCLK7_in;
wire PMASCANCLK8_in;
wire PMASCANENB_in;
wire PMASCANMODEB_in;
wire PMASCANRSTEN_in;
wire QPLL0CLK_in;
wire QPLL0FREQLOCK_in;
wire QPLL0REFCLK_in;
wire QPLL1CLK_in;
wire QPLL1FREQLOCK_in;
wire QPLL1REFCLK_in;
wire RESETOVRD_in;
wire RX8B10BEN_in;
wire RXAFECFOKEN_in;
wire RXBUFRESET_in;
wire RXCDRFREQRESET_in;
wire RXCDRHOLD_in;
wire RXCDROVRDEN_in;
wire RXCDRRESET_in;
wire RXCHBONDEN_in;
wire RXCHBONDMASTER_in;
wire RXCHBONDSLAVE_in;
wire RXCKCALRESET_in;
wire RXCOMMADETEN_in;
wire RXDFEAGCHOLD_in;
wire RXDFEAGCOVRDEN_in;
wire RXDFECFOKFEN_in;
wire RXDFECFOKFPULSE_in;
wire RXDFECFOKHOLD_in;
wire RXDFECFOKOVREN_in;
wire RXDFEKHHOLD_in;
wire RXDFEKHOVRDEN_in;
wire RXDFELFHOLD_in;
wire RXDFELFOVRDEN_in;
wire RXDFELPMRESET_in;
wire RXDFETAP10HOLD_in;
wire RXDFETAP10OVRDEN_in;
wire RXDFETAP11HOLD_in;
wire RXDFETAP11OVRDEN_in;
wire RXDFETAP12HOLD_in;
wire RXDFETAP12OVRDEN_in;
wire RXDFETAP13HOLD_in;
wire RXDFETAP13OVRDEN_in;
wire RXDFETAP14HOLD_in;
wire RXDFETAP14OVRDEN_in;
wire RXDFETAP15HOLD_in;
wire RXDFETAP15OVRDEN_in;
wire RXDFETAP2HOLD_in;
wire RXDFETAP2OVRDEN_in;
wire RXDFETAP3HOLD_in;
wire RXDFETAP3OVRDEN_in;
wire RXDFETAP4HOLD_in;
wire RXDFETAP4OVRDEN_in;
wire RXDFETAP5HOLD_in;
wire RXDFETAP5OVRDEN_in;
wire RXDFETAP6HOLD_in;
wire RXDFETAP6OVRDEN_in;
wire RXDFETAP7HOLD_in;
wire RXDFETAP7OVRDEN_in;
wire RXDFETAP8HOLD_in;
wire RXDFETAP8OVRDEN_in;
wire RXDFETAP9HOLD_in;
wire RXDFETAP9OVRDEN_in;
wire RXDFEUTHOLD_in;
wire RXDFEUTOVRDEN_in;
wire RXDFEVPHOLD_in;
wire RXDFEVPOVRDEN_in;
wire RXDFEXYDEN_in;
wire RXDLYBYPASS_in;
wire RXDLYEN_in;
wire RXDLYOVRDEN_in;
wire RXDLYSRESET_in;
wire RXEQTRAINING_in;
wire RXGEARBOXSLIP_in;
wire RXLATCLK_in;
wire RXLPMEN_in;
wire RXLPMGCHOLD_in;
wire RXLPMGCOVRDEN_in;
wire RXLPMHFHOLD_in;
wire RXLPMHFOVRDEN_in;
wire RXLPMLFHOLD_in;
wire RXLPMLFKLOVRDEN_in;
wire RXLPMOSHOLD_in;
wire RXLPMOSOVRDEN_in;
wire RXMCOMMAALIGNEN_in;
wire RXOOBRESET_in;
wire RXOSCALRESET_in;
wire RXOSHOLD_in;
wire RXOSOVRDEN_in;
wire RXPCOMMAALIGNEN_in;
wire RXPCSRESET_in;
wire RXPHALIGNEN_in;
wire RXPHALIGN_in;
wire RXPHDLYPD_in;
wire RXPHDLYRESET_in;
wire RXPMARESET_in;
wire RXPOLARITY_in;
wire RXPRBSCNTRESET_in;
wire RXPROGDIVRESET_in;
wire RXRATEMODE_in;
wire RXSLIDE_in;
wire RXSLIPOUTCLK_in;
wire RXSLIPPMA_in;
wire RXSYNCALLIN_in;
wire RXSYNCIN_in;
wire RXSYNCMODE_in;
wire RXTERMINATION_in;
wire RXUSERRDY_in;
wire RXUSRCLK2_in;
wire RXUSRCLK_in;
wire SARCCLK_in;
wire SCANCLK_in;
wire SCANENB_in;
wire SCANMODEB_in;
wire SCANRSTB_in;
wire SCANRSTEN_in;
wire SIGVALIDCLK_in;
wire TSTCLK0_in;
wire TSTCLK1_in;
wire TSTPDOVRDB_in;
wire TX8B10BEN_in;
wire TXCOMINIT_in;
wire TXCOMSAS_in;
wire TXCOMWAKE_in;
wire TXDCCFORCESTART_in;
wire TXDCCRESET_in;
wire TXDETECTRX_in;
wire TXDLYBYPASS_in;
wire TXDLYEN_in;
wire TXDLYHOLD_in;
wire TXDLYOVRDEN_in;
wire TXDLYSRESET_in;
wire TXDLYUPDOWN_in;
wire TXELECIDLE_in;
wire TXINHIBIT_in;
wire TXLATCLK_in;
wire TXLFPSTRESET_in;
wire TXLFPSU2LPEXIT_in;
wire TXLFPSU3WAKE_in;
wire TXMUXDCDEXHOLD_in;
wire TXMUXDCDORWREN_in;
wire TXONESZEROS_in;
wire TXPCSRESET_in;
wire TXPDELECIDLEMODE_in;
wire TXPHALIGNEN_in;
wire TXPHALIGN_in;
wire TXPHDLYPD_in;
wire TXPHDLYRESET_in;
wire TXPHDLYTSTCLK_in;
wire TXPHINIT_in;
wire TXPHOVRDEN_in;
wire TXPIPPMEN_in;
wire TXPIPPMOVRDEN_in;
wire TXPIPPMPD_in;
wire TXPIPPMSEL_in;
wire TXPISOPD_in;
wire TXPMARESET_in;
wire TXPOLARITY_in;
wire TXPRBSFORCEERR_in;
wire TXPROGDIVRESET_in;
wire TXRATEMODE_in;
wire TXSWING_in;
wire TXSYNCALLIN_in;
wire TXSYNCIN_in;
wire TXSYNCMODE_in;
wire TXUSERRDY_in;
wire TXUSRCLK2_in;
wire TXUSRCLK_in;
wire [127:0] TXDATA_in;
wire [15:0] DRPDI_in;
wire [15:0] GTRSVD_in;
wire [15:0] PCSRSVDIN_in;
wire [15:0] TXCTRL0_in;
wire [15:0] TXCTRL1_in;
wire [17:0] PMASCANIN_in;
wire [18:0] SCANIN_in;
wire [19:0] TSTIN_in;
wire [1:0] RXELECIDLEMODE_in;
wire [1:0] RXMONITORSEL_in;
wire [1:0] RXPD_in;
wire [1:0] RXPLLCLKSEL_in;
wire [1:0] RXSYSCLKSEL_in;
wire [1:0] TXDEEMPH_in;
wire [1:0] TXPD_in;
wire [1:0] TXPLLCLKSEL_in;
wire [1:0] TXSYSCLKSEL_in;
wire [2:0] CPLLREFCLKSEL_in;
wire [2:0] LOOPBACK_in;
wire [2:0] RXCHBONDLEVEL_in;
wire [2:0] RXOUTCLKSEL_in;
wire [2:0] RXRATE_in;
wire [2:0] TXMARGIN_in;
wire [2:0] TXOUTCLKSEL_in;
wire [2:0] TXRATE_in;
wire [3:0] RXDFECFOKFCNUM_in;
wire [3:0] RXPRBSSEL_in;
wire [3:0] TXPRBSSEL_in;
wire [4:0] RXCHBONDI_in;
wire [4:0] TSTPD_in;
wire [4:0] TXDIFFCTRL_in;
wire [4:0] TXPIPPMSTEPSIZE_in;
wire [4:0] TXPOSTCURSOR_in;
wire [4:0] TXPRECURSOR_in;
wire [5:0] TXHEADER_in;
wire [6:0] RXCKCALSTART_in;
wire [6:0] TXMAINCURSOR_in;
wire [6:0] TXSEQUENCE_in;
wire [7:0] TX8B10BBYPASS_in;
wire [7:0] TXCTRL2_in;
wire [7:0] TXDATAEXTENDRSVD_in;
wire [9:0] DRPADDR_in;
wire gt_intclk;
reg gt_clk_int;
`ifdef XIL_TIMING
wire DRPCLK_delay;
wire DRPEN_delay;
wire DRPWE_delay;
wire RX8B10BEN_delay;
wire RXCHBONDEN_delay;
wire RXCHBONDMASTER_delay;
wire RXCHBONDSLAVE_delay;
wire RXCOMMADETEN_delay;
wire RXGEARBOXSLIP_delay;
wire RXMCOMMAALIGNEN_delay;
wire RXPCOMMAALIGNEN_delay;
wire RXPOLARITY_delay;
wire RXPRBSCNTRESET_delay;
wire RXSLIDE_delay;
wire RXSLIPOUTCLK_delay;
wire RXSLIPPMA_delay;
wire RXUSRCLK2_delay;
wire RXUSRCLK_delay;
wire TX8B10BEN_delay;
wire TXCOMINIT_delay;
wire TXCOMSAS_delay;
wire TXCOMWAKE_delay;
wire TXDETECTRX_delay;
wire TXELECIDLE_delay;
wire TXINHIBIT_delay;
wire TXPOLARITY_delay;
wire TXPRBSFORCEERR_delay;
wire TXUSRCLK2_delay;
wire [127:0] TXDATA_delay;
wire [15:0] DRPDI_delay;
wire [15:0] TXCTRL0_delay;
wire [15:0] TXCTRL1_delay;
wire [1:0] TXPD_delay;
wire [2:0] RXCHBONDLEVEL_delay;
wire [2:0] RXRATE_delay;
wire [2:0] TXRATE_delay;
wire [3:0] RXPRBSSEL_delay;
wire [3:0] TXPRBSSEL_delay;
wire [4:0] RXCHBONDI_delay;
wire [5:0] TXHEADER_delay;
wire [6:0] TXSEQUENCE_delay;
wire [7:0] TX8B10BBYPASS_delay;
wire [7:0] TXCTRL2_delay;
wire [9:0] DRPADDR_delay;
`endif
assign BUFGTCE = BUFGTCE_out;
assign BUFGTCEMASK = BUFGTCEMASK_out;
assign BUFGTDIV = BUFGTDIV_out;
assign BUFGTRESET = BUFGTRESET_out;
assign BUFGTRSTMASK = BUFGTRSTMASK_out;
assign CPLLFBCLKLOST = CPLLFBCLKLOST_out;
assign CPLLLOCK = CPLLLOCK_out;
assign CPLLREFCLKLOST = CPLLREFCLKLOST_out;
assign DMONITOROUT = DMONITOROUT_out;
assign DMONITOROUTCLK = DMONITOROUTCLK_out;
assign DRPDO = DRPDO_out;
assign DRPRDY = DRPRDY_out;
assign EYESCANDATAERROR = EYESCANDATAERROR_out;
assign GTPOWERGOOD = GTPOWERGOOD_out;
assign GTREFCLKMONITOR = GTREFCLKMONITOR_out;
assign GTYTXN = GTYTXN_out;
assign GTYTXP = GTYTXP_out;
assign PCIERATEGEN3 = PCIERATEGEN3_out;
assign PCIERATEIDLE = PCIERATEIDLE_out;
assign PCIERATEQPLLPD = PCIERATEQPLLPD_out;
assign PCIERATEQPLLRESET = PCIERATEQPLLRESET_out;
assign PCIESYNCTXSYNCDONE = PCIESYNCTXSYNCDONE_out;
assign PCIEUSERGEN3RDY = PCIEUSERGEN3RDY_out;
assign PCIEUSERPHYSTATUSRST = PCIEUSERPHYSTATUSRST_out;
assign PCIEUSERRATESTART = PCIEUSERRATESTART_out;
assign PCSRSVDOUT = PCSRSVDOUT_out;
assign PHYSTATUS = PHYSTATUS_out;
assign PINRSRVDAS = PINRSRVDAS_out;
assign POWERPRESENT = POWERPRESENT_out;
assign RESETEXCEPTION = RESETEXCEPTION_out;
assign RXBUFSTATUS = RXBUFSTATUS_out;
assign RXBYTEISALIGNED = RXBYTEISALIGNED_out;
assign RXBYTEREALIGN = RXBYTEREALIGN_out;
assign RXCDRLOCK = RXCDRLOCK_out;
assign RXCDRPHDONE = RXCDRPHDONE_out;
assign RXCHANBONDSEQ = RXCHANBONDSEQ_out;
assign RXCHANISALIGNED = RXCHANISALIGNED_out;
assign RXCHANREALIGN = RXCHANREALIGN_out;
assign RXCHBONDO = RXCHBONDO_out;
assign RXCKCALDONE = RXCKCALDONE_out;
assign RXCLKCORCNT = RXCLKCORCNT_out;
assign RXCOMINITDET = RXCOMINITDET_out;
assign RXCOMMADET = RXCOMMADET_out;
assign RXCOMSASDET = RXCOMSASDET_out;
assign RXCOMWAKEDET = RXCOMWAKEDET_out;
assign RXCTRL0 = RXCTRL0_out;
assign RXCTRL1 = RXCTRL1_out;
assign RXCTRL2 = RXCTRL2_out;
assign RXCTRL3 = RXCTRL3_out;
assign RXDATA = RXDATA_out;
assign RXDATAEXTENDRSVD = RXDATAEXTENDRSVD_out;
assign RXDATAVALID = RXDATAVALID_out;
assign RXDLYSRESETDONE = RXDLYSRESETDONE_out;
assign RXELECIDLE = RXELECIDLE_out;
assign RXHEADER = RXHEADER_out;
assign RXHEADERVALID = RXHEADERVALID_out;
assign RXLFPSTRESETDET = RXLFPSTRESETDET_out;
assign RXLFPSU2LPEXITDET = RXLFPSU2LPEXITDET_out;
assign RXLFPSU3WAKEDET = RXLFPSU3WAKEDET_out;
assign RXMONITOROUT = RXMONITOROUT_out;
assign RXOSINTDONE = RXOSINTDONE_out;
assign RXOSINTSTARTED = RXOSINTSTARTED_out;
assign RXOSINTSTROBEDONE = RXOSINTSTROBEDONE_out;
assign RXOSINTSTROBESTARTED = RXOSINTSTROBESTARTED_out;
assign RXOUTCLK = RXOUTCLK_out;
assign RXOUTCLKFABRIC = RXOUTCLKFABRIC_out;
//EL
//assign RXOUTCLKPCS = RXOUTCLKPCS_out;
assign RXOUTCLKPCS = (RXPD_in == 2'b11) ? gt_intclk : RXOUTCLKPCS_out;
assign RXPHALIGNDONE = RXPHALIGNDONE_out;
assign RXPHALIGNERR = RXPHALIGNERR_out;
assign RXPMARESETDONE = RXPMARESETDONE_out;
assign RXPRBSERR = RXPRBSERR_out;
assign RXPRBSLOCKED = RXPRBSLOCKED_out;
assign RXPRGDIVRESETDONE = RXPRGDIVRESETDONE_out;
assign RXRATEDONE = RXRATEDONE_out;
assign RXRECCLKOUT = RXRECCLKOUT_out;
assign RXRESETDONE = RXRESETDONE_out;
assign RXSLIDERDY = RXSLIDERDY_out;
assign RXSLIPDONE = RXSLIPDONE_out;
assign RXSLIPOUTCLKRDY = RXSLIPOUTCLKRDY_out;
assign RXSLIPPMARDY = RXSLIPPMARDY_out;
assign RXSTARTOFSEQ = RXSTARTOFSEQ_out;
assign RXSTATUS = RXSTATUS_out;
assign RXSYNCDONE = RXSYNCDONE_out;
assign RXSYNCOUT = RXSYNCOUT_out;
assign RXVALID = RXVALID_out;
assign TXBUFSTATUS = TXBUFSTATUS_out;
assign TXCOMFINISH = TXCOMFINISH_out;
assign TXDCCDONE = TXDCCDONE_out;
assign TXDLYSRESETDONE = TXDLYSRESETDONE_out;
//EL
//assign TXOUTCLK = TXOUTCLK_out;
assign TXOUTCLK = (TXPISOPD_in && TXOUTCLKSEL_in == 3'b101) ? gt_intclk : TXOUTCLK_out;
assign TXOUTCLKFABRIC = TXOUTCLKFABRIC_out;
assign TXOUTCLKPCS = TXPISOPD_in ? gt_intclk : TXOUTCLKPCS_out;
assign TXPHALIGNDONE = TXPHALIGNDONE_out;
assign TXPHINITDONE = TXPHINITDONE_out;
assign TXPMARESETDONE = TXPMARESETDONE_out;
assign TXPRGDIVRESETDONE = TXPRGDIVRESETDONE_out;
assign TXRATEDONE = TXRATEDONE_out;
assign TXRESETDONE = TXRESETDONE_out;
assign TXSYNCDONE = TXSYNCDONE_out;
assign TXSYNCOUT = TXSYNCOUT_out;
`ifdef XIL_TIMING
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR_delay[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR_delay[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR_delay[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR_delay[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR_delay[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR_delay[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR_delay[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR_delay[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR_delay[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR_delay[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK_delay; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI_delay[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI_delay[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI_delay[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI_delay[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI_delay[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI_delay[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI_delay[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI_delay[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI_delay[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI_delay[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI_delay[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI_delay[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI_delay[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI_delay[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI_delay[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI_delay[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN_delay; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE_delay; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN_delay; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN_delay; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI_delay[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI_delay[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI_delay[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI_delay[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI_delay[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL_delay[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL_delay[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL_delay[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER_delay; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE_delay; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN_delay; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP_delay; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN_delay; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN_delay; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY_delay; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET_delay; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL_delay[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL_delay[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL_delay[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL_delay[3]; // rv 0
assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE_delay[0]; // rv 0
assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE_delay[1]; // rv 0
assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE_delay[2]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE_delay; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK_delay; // rv 0
assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA_delay; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2_delay; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK_delay; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS_delay[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS_delay[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS_delay[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS_delay[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS_delay[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS_delay[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS_delay[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS_delay[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN_delay; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT_delay; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS_delay; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE_delay; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0_delay[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0_delay[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0_delay[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0_delay[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0_delay[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0_delay[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0_delay[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0_delay[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0_delay[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0_delay[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0_delay[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0_delay[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0_delay[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0_delay[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0_delay[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0_delay[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1_delay[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1_delay[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1_delay[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1_delay[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1_delay[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1_delay[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1_delay[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1_delay[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1_delay[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1_delay[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1_delay[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1_delay[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1_delay[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1_delay[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1_delay[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1_delay[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2_delay[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2_delay[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2_delay[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2_delay[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2_delay[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2_delay[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2_delay[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2_delay[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA_delay[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA_delay[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA_delay[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA_delay[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA_delay[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA_delay[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA_delay[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA_delay[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA_delay[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA_delay[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA_delay[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA_delay[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA_delay[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA_delay[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA_delay[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA_delay[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA_delay[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA_delay[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA_delay[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA_delay[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA_delay[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA_delay[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA_delay[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA_delay[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA_delay[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA_delay[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA_delay[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA_delay[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA_delay[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA_delay[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA_delay[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA_delay[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA_delay[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA_delay[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA_delay[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA_delay[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA_delay[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA_delay[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA_delay[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA_delay[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA_delay[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA_delay[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA_delay[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA_delay[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA_delay[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA_delay[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA_delay[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA_delay[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA_delay[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA_delay[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA_delay[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA_delay[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA_delay[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA_delay[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA_delay[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA_delay[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA_delay[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA_delay[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA_delay[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA_delay[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA_delay[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA_delay[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA_delay[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA_delay[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA_delay[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA_delay[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA_delay[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA_delay[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA_delay[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA_delay[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA_delay[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA_delay[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA_delay[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA_delay[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA_delay[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA_delay[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA_delay[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA_delay[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA_delay[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA_delay[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA_delay[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA_delay[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA_delay[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA_delay[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA_delay[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA_delay[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA_delay[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA_delay[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA_delay[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA_delay[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA_delay[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA_delay[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA_delay[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA_delay[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA_delay[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA_delay[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA_delay[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA_delay[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA_delay[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA_delay[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA_delay[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA_delay[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA_delay[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA_delay[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA_delay[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA_delay[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA_delay[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA_delay[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA_delay[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA_delay[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA_delay[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA_delay[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA_delay[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA_delay[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA_delay[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA_delay[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA_delay[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA_delay[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA_delay[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA_delay[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA_delay[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA_delay[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA_delay[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA_delay[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA_delay[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA_delay[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA_delay[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA_delay[9]; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX_delay; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE_delay; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER_delay[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER_delay[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER_delay[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER_delay[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER_delay[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER_delay[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT_delay; // rv 0
assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD_delay[0]; // rv 0
assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD_delay[1]; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY_delay; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR_delay; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL_delay[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL_delay[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL_delay[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL_delay[3]; // rv 0
assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE_delay[0]; // rv 0
assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE_delay[1]; // rv 0
assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE_delay[2]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE_delay[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE_delay[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE_delay[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE_delay[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE_delay[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE_delay[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE_delay[6]; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2_delay; // rv 0
`else
assign DRPADDR_in[0] = (DRPADDR[0] !== 1'bz) && DRPADDR[0]; // rv 0
assign DRPADDR_in[1] = (DRPADDR[1] !== 1'bz) && DRPADDR[1]; // rv 0
assign DRPADDR_in[2] = (DRPADDR[2] !== 1'bz) && DRPADDR[2]; // rv 0
assign DRPADDR_in[3] = (DRPADDR[3] !== 1'bz) && DRPADDR[3]; // rv 0
assign DRPADDR_in[4] = (DRPADDR[4] !== 1'bz) && DRPADDR[4]; // rv 0
assign DRPADDR_in[5] = (DRPADDR[5] !== 1'bz) && DRPADDR[5]; // rv 0
assign DRPADDR_in[6] = (DRPADDR[6] !== 1'bz) && DRPADDR[6]; // rv 0
assign DRPADDR_in[7] = (DRPADDR[7] !== 1'bz) && DRPADDR[7]; // rv 0
assign DRPADDR_in[8] = (DRPADDR[8] !== 1'bz) && DRPADDR[8]; // rv 0
assign DRPADDR_in[9] = (DRPADDR[9] !== 1'bz) && DRPADDR[9]; // rv 0
assign DRPCLK_in = (DRPCLK !== 1'bz) && DRPCLK; // rv 0
assign DRPDI_in[0] = (DRPDI[0] !== 1'bz) && DRPDI[0]; // rv 0
assign DRPDI_in[10] = (DRPDI[10] !== 1'bz) && DRPDI[10]; // rv 0
assign DRPDI_in[11] = (DRPDI[11] !== 1'bz) && DRPDI[11]; // rv 0
assign DRPDI_in[12] = (DRPDI[12] !== 1'bz) && DRPDI[12]; // rv 0
assign DRPDI_in[13] = (DRPDI[13] !== 1'bz) && DRPDI[13]; // rv 0
assign DRPDI_in[14] = (DRPDI[14] !== 1'bz) && DRPDI[14]; // rv 0
assign DRPDI_in[15] = (DRPDI[15] !== 1'bz) && DRPDI[15]; // rv 0
assign DRPDI_in[1] = (DRPDI[1] !== 1'bz) && DRPDI[1]; // rv 0
assign DRPDI_in[2] = (DRPDI[2] !== 1'bz) && DRPDI[2]; // rv 0
assign DRPDI_in[3] = (DRPDI[3] !== 1'bz) && DRPDI[3]; // rv 0
assign DRPDI_in[4] = (DRPDI[4] !== 1'bz) && DRPDI[4]; // rv 0
assign DRPDI_in[5] = (DRPDI[5] !== 1'bz) && DRPDI[5]; // rv 0
assign DRPDI_in[6] = (DRPDI[6] !== 1'bz) && DRPDI[6]; // rv 0
assign DRPDI_in[7] = (DRPDI[7] !== 1'bz) && DRPDI[7]; // rv 0
assign DRPDI_in[8] = (DRPDI[8] !== 1'bz) && DRPDI[8]; // rv 0
assign DRPDI_in[9] = (DRPDI[9] !== 1'bz) && DRPDI[9]; // rv 0
assign DRPEN_in = (DRPEN !== 1'bz) && DRPEN; // rv 0
assign DRPWE_in = (DRPWE !== 1'bz) && DRPWE; // rv 0
assign RX8B10BEN_in = (RX8B10BEN !== 1'bz) && RX8B10BEN; // rv 0
assign RXCHBONDEN_in = (RXCHBONDEN !== 1'bz) && RXCHBONDEN; // rv 0
assign RXCHBONDI_in[0] = (RXCHBONDI[0] !== 1'bz) && RXCHBONDI[0]; // rv 0
assign RXCHBONDI_in[1] = (RXCHBONDI[1] !== 1'bz) && RXCHBONDI[1]; // rv 0
assign RXCHBONDI_in[2] = (RXCHBONDI[2] !== 1'bz) && RXCHBONDI[2]; // rv 0
assign RXCHBONDI_in[3] = (RXCHBONDI[3] !== 1'bz) && RXCHBONDI[3]; // rv 0
assign RXCHBONDI_in[4] = (RXCHBONDI[4] !== 1'bz) && RXCHBONDI[4]; // rv 0
assign RXCHBONDLEVEL_in[0] = (RXCHBONDLEVEL[0] !== 1'bz) && RXCHBONDLEVEL[0]; // rv 0
assign RXCHBONDLEVEL_in[1] = (RXCHBONDLEVEL[1] !== 1'bz) && RXCHBONDLEVEL[1]; // rv 0
assign RXCHBONDLEVEL_in[2] = (RXCHBONDLEVEL[2] !== 1'bz) && RXCHBONDLEVEL[2]; // rv 0
assign RXCHBONDMASTER_in = (RXCHBONDMASTER !== 1'bz) && RXCHBONDMASTER; // rv 0
assign RXCHBONDSLAVE_in = (RXCHBONDSLAVE !== 1'bz) && RXCHBONDSLAVE; // rv 0
assign RXCOMMADETEN_in = (RXCOMMADETEN !== 1'bz) && RXCOMMADETEN; // rv 0
assign RXGEARBOXSLIP_in = (RXGEARBOXSLIP !== 1'bz) && RXGEARBOXSLIP; // rv 0
assign RXMCOMMAALIGNEN_in = (RXMCOMMAALIGNEN !== 1'bz) && RXMCOMMAALIGNEN; // rv 0
assign RXPCOMMAALIGNEN_in = (RXPCOMMAALIGNEN !== 1'bz) && RXPCOMMAALIGNEN; // rv 0
assign RXPOLARITY_in = (RXPOLARITY !== 1'bz) && RXPOLARITY; // rv 0
assign RXPRBSCNTRESET_in = (RXPRBSCNTRESET !== 1'bz) && RXPRBSCNTRESET; // rv 0
assign RXPRBSSEL_in[0] = (RXPRBSSEL[0] !== 1'bz) && RXPRBSSEL[0]; // rv 0
assign RXPRBSSEL_in[1] = (RXPRBSSEL[1] !== 1'bz) && RXPRBSSEL[1]; // rv 0
assign RXPRBSSEL_in[2] = (RXPRBSSEL[2] !== 1'bz) && RXPRBSSEL[2]; // rv 0
assign RXPRBSSEL_in[3] = (RXPRBSSEL[3] !== 1'bz) && RXPRBSSEL[3]; // rv 0
assign RXRATE_in[0] = (RXRATE[0] !== 1'bz) && RXRATE[0]; // rv 0
assign RXRATE_in[1] = (RXRATE[1] !== 1'bz) && RXRATE[1]; // rv 0
assign RXRATE_in[2] = (RXRATE[2] !== 1'bz) && RXRATE[2]; // rv 0
assign RXSLIDE_in = (RXSLIDE !== 1'bz) && RXSLIDE; // rv 0
assign RXSLIPOUTCLK_in = (RXSLIPOUTCLK !== 1'bz) && RXSLIPOUTCLK; // rv 0
assign RXSLIPPMA_in = (RXSLIPPMA !== 1'bz) && RXSLIPPMA; // rv 0
assign RXUSRCLK2_in = (RXUSRCLK2 !== 1'bz) && RXUSRCLK2; // rv 0
assign RXUSRCLK_in = (RXUSRCLK !== 1'bz) && RXUSRCLK; // rv 0
assign TX8B10BBYPASS_in[0] = (TX8B10BBYPASS[0] !== 1'bz) && TX8B10BBYPASS[0]; // rv 0
assign TX8B10BBYPASS_in[1] = (TX8B10BBYPASS[1] !== 1'bz) && TX8B10BBYPASS[1]; // rv 0
assign TX8B10BBYPASS_in[2] = (TX8B10BBYPASS[2] !== 1'bz) && TX8B10BBYPASS[2]; // rv 0
assign TX8B10BBYPASS_in[3] = (TX8B10BBYPASS[3] !== 1'bz) && TX8B10BBYPASS[3]; // rv 0
assign TX8B10BBYPASS_in[4] = (TX8B10BBYPASS[4] !== 1'bz) && TX8B10BBYPASS[4]; // rv 0
assign TX8B10BBYPASS_in[5] = (TX8B10BBYPASS[5] !== 1'bz) && TX8B10BBYPASS[5]; // rv 0
assign TX8B10BBYPASS_in[6] = (TX8B10BBYPASS[6] !== 1'bz) && TX8B10BBYPASS[6]; // rv 0
assign TX8B10BBYPASS_in[7] = (TX8B10BBYPASS[7] !== 1'bz) && TX8B10BBYPASS[7]; // rv 0
assign TX8B10BEN_in = (TX8B10BEN !== 1'bz) && TX8B10BEN; // rv 0
assign TXCOMINIT_in = (TXCOMINIT !== 1'bz) && TXCOMINIT; // rv 0
assign TXCOMSAS_in = (TXCOMSAS !== 1'bz) && TXCOMSAS; // rv 0
assign TXCOMWAKE_in = (TXCOMWAKE !== 1'bz) && TXCOMWAKE; // rv 0
assign TXCTRL0_in[0] = (TXCTRL0[0] !== 1'bz) && TXCTRL0[0]; // rv 0
assign TXCTRL0_in[10] = (TXCTRL0[10] !== 1'bz) && TXCTRL0[10]; // rv 0
assign TXCTRL0_in[11] = (TXCTRL0[11] !== 1'bz) && TXCTRL0[11]; // rv 0
assign TXCTRL0_in[12] = (TXCTRL0[12] !== 1'bz) && TXCTRL0[12]; // rv 0
assign TXCTRL0_in[13] = (TXCTRL0[13] !== 1'bz) && TXCTRL0[13]; // rv 0
assign TXCTRL0_in[14] = (TXCTRL0[14] !== 1'bz) && TXCTRL0[14]; // rv 0
assign TXCTRL0_in[15] = (TXCTRL0[15] !== 1'bz) && TXCTRL0[15]; // rv 0
assign TXCTRL0_in[1] = (TXCTRL0[1] !== 1'bz) && TXCTRL0[1]; // rv 0
assign TXCTRL0_in[2] = (TXCTRL0[2] !== 1'bz) && TXCTRL0[2]; // rv 0
assign TXCTRL0_in[3] = (TXCTRL0[3] !== 1'bz) && TXCTRL0[3]; // rv 0
assign TXCTRL0_in[4] = (TXCTRL0[4] !== 1'bz) && TXCTRL0[4]; // rv 0
assign TXCTRL0_in[5] = (TXCTRL0[5] !== 1'bz) && TXCTRL0[5]; // rv 0
assign TXCTRL0_in[6] = (TXCTRL0[6] !== 1'bz) && TXCTRL0[6]; // rv 0
assign TXCTRL0_in[7] = (TXCTRL0[7] !== 1'bz) && TXCTRL0[7]; // rv 0
assign TXCTRL0_in[8] = (TXCTRL0[8] !== 1'bz) && TXCTRL0[8]; // rv 0
assign TXCTRL0_in[9] = (TXCTRL0[9] !== 1'bz) && TXCTRL0[9]; // rv 0
assign TXCTRL1_in[0] = (TXCTRL1[0] !== 1'bz) && TXCTRL1[0]; // rv 0
assign TXCTRL1_in[10] = (TXCTRL1[10] !== 1'bz) && TXCTRL1[10]; // rv 0
assign TXCTRL1_in[11] = (TXCTRL1[11] !== 1'bz) && TXCTRL1[11]; // rv 0
assign TXCTRL1_in[12] = (TXCTRL1[12] !== 1'bz) && TXCTRL1[12]; // rv 0
assign TXCTRL1_in[13] = (TXCTRL1[13] !== 1'bz) && TXCTRL1[13]; // rv 0
assign TXCTRL1_in[14] = (TXCTRL1[14] !== 1'bz) && TXCTRL1[14]; // rv 0
assign TXCTRL1_in[15] = (TXCTRL1[15] !== 1'bz) && TXCTRL1[15]; // rv 0
assign TXCTRL1_in[1] = (TXCTRL1[1] !== 1'bz) && TXCTRL1[1]; // rv 0
assign TXCTRL1_in[2] = (TXCTRL1[2] !== 1'bz) && TXCTRL1[2]; // rv 0
assign TXCTRL1_in[3] = (TXCTRL1[3] !== 1'bz) && TXCTRL1[3]; // rv 0
assign TXCTRL1_in[4] = (TXCTRL1[4] !== 1'bz) && TXCTRL1[4]; // rv 0
assign TXCTRL1_in[5] = (TXCTRL1[5] !== 1'bz) && TXCTRL1[5]; // rv 0
assign TXCTRL1_in[6] = (TXCTRL1[6] !== 1'bz) && TXCTRL1[6]; // rv 0
assign TXCTRL1_in[7] = (TXCTRL1[7] !== 1'bz) && TXCTRL1[7]; // rv 0
assign TXCTRL1_in[8] = (TXCTRL1[8] !== 1'bz) && TXCTRL1[8]; // rv 0
assign TXCTRL1_in[9] = (TXCTRL1[9] !== 1'bz) && TXCTRL1[9]; // rv 0
assign TXCTRL2_in[0] = (TXCTRL2[0] !== 1'bz) && TXCTRL2[0]; // rv 0
assign TXCTRL2_in[1] = (TXCTRL2[1] !== 1'bz) && TXCTRL2[1]; // rv 0
assign TXCTRL2_in[2] = (TXCTRL2[2] !== 1'bz) && TXCTRL2[2]; // rv 0
assign TXCTRL2_in[3] = (TXCTRL2[3] !== 1'bz) && TXCTRL2[3]; // rv 0
assign TXCTRL2_in[4] = (TXCTRL2[4] !== 1'bz) && TXCTRL2[4]; // rv 0
assign TXCTRL2_in[5] = (TXCTRL2[5] !== 1'bz) && TXCTRL2[5]; // rv 0
assign TXCTRL2_in[6] = (TXCTRL2[6] !== 1'bz) && TXCTRL2[6]; // rv 0
assign TXCTRL2_in[7] = (TXCTRL2[7] !== 1'bz) && TXCTRL2[7]; // rv 0
assign TXDATA_in[0] = (TXDATA[0] !== 1'bz) && TXDATA[0]; // rv 0
assign TXDATA_in[100] = (TXDATA[100] !== 1'bz) && TXDATA[100]; // rv 0
assign TXDATA_in[101] = (TXDATA[101] !== 1'bz) && TXDATA[101]; // rv 0
assign TXDATA_in[102] = (TXDATA[102] !== 1'bz) && TXDATA[102]; // rv 0
assign TXDATA_in[103] = (TXDATA[103] !== 1'bz) && TXDATA[103]; // rv 0
assign TXDATA_in[104] = (TXDATA[104] !== 1'bz) && TXDATA[104]; // rv 0
assign TXDATA_in[105] = (TXDATA[105] !== 1'bz) && TXDATA[105]; // rv 0
assign TXDATA_in[106] = (TXDATA[106] !== 1'bz) && TXDATA[106]; // rv 0
assign TXDATA_in[107] = (TXDATA[107] !== 1'bz) && TXDATA[107]; // rv 0
assign TXDATA_in[108] = (TXDATA[108] !== 1'bz) && TXDATA[108]; // rv 0
assign TXDATA_in[109] = (TXDATA[109] !== 1'bz) && TXDATA[109]; // rv 0
assign TXDATA_in[10] = (TXDATA[10] !== 1'bz) && TXDATA[10]; // rv 0
assign TXDATA_in[110] = (TXDATA[110] !== 1'bz) && TXDATA[110]; // rv 0
assign TXDATA_in[111] = (TXDATA[111] !== 1'bz) && TXDATA[111]; // rv 0
assign TXDATA_in[112] = (TXDATA[112] !== 1'bz) && TXDATA[112]; // rv 0
assign TXDATA_in[113] = (TXDATA[113] !== 1'bz) && TXDATA[113]; // rv 0
assign TXDATA_in[114] = (TXDATA[114] !== 1'bz) && TXDATA[114]; // rv 0
assign TXDATA_in[115] = (TXDATA[115] !== 1'bz) && TXDATA[115]; // rv 0
assign TXDATA_in[116] = (TXDATA[116] !== 1'bz) && TXDATA[116]; // rv 0
assign TXDATA_in[117] = (TXDATA[117] !== 1'bz) && TXDATA[117]; // rv 0
assign TXDATA_in[118] = (TXDATA[118] !== 1'bz) && TXDATA[118]; // rv 0
assign TXDATA_in[119] = (TXDATA[119] !== 1'bz) && TXDATA[119]; // rv 0
assign TXDATA_in[11] = (TXDATA[11] !== 1'bz) && TXDATA[11]; // rv 0
assign TXDATA_in[120] = (TXDATA[120] !== 1'bz) && TXDATA[120]; // rv 0
assign TXDATA_in[121] = (TXDATA[121] !== 1'bz) && TXDATA[121]; // rv 0
assign TXDATA_in[122] = (TXDATA[122] !== 1'bz) && TXDATA[122]; // rv 0
assign TXDATA_in[123] = (TXDATA[123] !== 1'bz) && TXDATA[123]; // rv 0
assign TXDATA_in[124] = (TXDATA[124] !== 1'bz) && TXDATA[124]; // rv 0
assign TXDATA_in[125] = (TXDATA[125] !== 1'bz) && TXDATA[125]; // rv 0
assign TXDATA_in[126] = (TXDATA[126] !== 1'bz) && TXDATA[126]; // rv 0
assign TXDATA_in[127] = (TXDATA[127] !== 1'bz) && TXDATA[127]; // rv 0
assign TXDATA_in[12] = (TXDATA[12] !== 1'bz) && TXDATA[12]; // rv 0
assign TXDATA_in[13] = (TXDATA[13] !== 1'bz) && TXDATA[13]; // rv 0
assign TXDATA_in[14] = (TXDATA[14] !== 1'bz) && TXDATA[14]; // rv 0
assign TXDATA_in[15] = (TXDATA[15] !== 1'bz) && TXDATA[15]; // rv 0
assign TXDATA_in[16] = (TXDATA[16] !== 1'bz) && TXDATA[16]; // rv 0
assign TXDATA_in[17] = (TXDATA[17] !== 1'bz) && TXDATA[17]; // rv 0
assign TXDATA_in[18] = (TXDATA[18] !== 1'bz) && TXDATA[18]; // rv 0
assign TXDATA_in[19] = (TXDATA[19] !== 1'bz) && TXDATA[19]; // rv 0
assign TXDATA_in[1] = (TXDATA[1] !== 1'bz) && TXDATA[1]; // rv 0
assign TXDATA_in[20] = (TXDATA[20] !== 1'bz) && TXDATA[20]; // rv 0
assign TXDATA_in[21] = (TXDATA[21] !== 1'bz) && TXDATA[21]; // rv 0
assign TXDATA_in[22] = (TXDATA[22] !== 1'bz) && TXDATA[22]; // rv 0
assign TXDATA_in[23] = (TXDATA[23] !== 1'bz) && TXDATA[23]; // rv 0
assign TXDATA_in[24] = (TXDATA[24] !== 1'bz) && TXDATA[24]; // rv 0
assign TXDATA_in[25] = (TXDATA[25] !== 1'bz) && TXDATA[25]; // rv 0
assign TXDATA_in[26] = (TXDATA[26] !== 1'bz) && TXDATA[26]; // rv 0
assign TXDATA_in[27] = (TXDATA[27] !== 1'bz) && TXDATA[27]; // rv 0
assign TXDATA_in[28] = (TXDATA[28] !== 1'bz) && TXDATA[28]; // rv 0
assign TXDATA_in[29] = (TXDATA[29] !== 1'bz) && TXDATA[29]; // rv 0
assign TXDATA_in[2] = (TXDATA[2] !== 1'bz) && TXDATA[2]; // rv 0
assign TXDATA_in[30] = (TXDATA[30] !== 1'bz) && TXDATA[30]; // rv 0
assign TXDATA_in[31] = (TXDATA[31] !== 1'bz) && TXDATA[31]; // rv 0
assign TXDATA_in[32] = (TXDATA[32] !== 1'bz) && TXDATA[32]; // rv 0
assign TXDATA_in[33] = (TXDATA[33] !== 1'bz) && TXDATA[33]; // rv 0
assign TXDATA_in[34] = (TXDATA[34] !== 1'bz) && TXDATA[34]; // rv 0
assign TXDATA_in[35] = (TXDATA[35] !== 1'bz) && TXDATA[35]; // rv 0
assign TXDATA_in[36] = (TXDATA[36] !== 1'bz) && TXDATA[36]; // rv 0
assign TXDATA_in[37] = (TXDATA[37] !== 1'bz) && TXDATA[37]; // rv 0
assign TXDATA_in[38] = (TXDATA[38] !== 1'bz) && TXDATA[38]; // rv 0
assign TXDATA_in[39] = (TXDATA[39] !== 1'bz) && TXDATA[39]; // rv 0
assign TXDATA_in[3] = (TXDATA[3] !== 1'bz) && TXDATA[3]; // rv 0
assign TXDATA_in[40] = (TXDATA[40] !== 1'bz) && TXDATA[40]; // rv 0
assign TXDATA_in[41] = (TXDATA[41] !== 1'bz) && TXDATA[41]; // rv 0
assign TXDATA_in[42] = (TXDATA[42] !== 1'bz) && TXDATA[42]; // rv 0
assign TXDATA_in[43] = (TXDATA[43] !== 1'bz) && TXDATA[43]; // rv 0
assign TXDATA_in[44] = (TXDATA[44] !== 1'bz) && TXDATA[44]; // rv 0
assign TXDATA_in[45] = (TXDATA[45] !== 1'bz) && TXDATA[45]; // rv 0
assign TXDATA_in[46] = (TXDATA[46] !== 1'bz) && TXDATA[46]; // rv 0
assign TXDATA_in[47] = (TXDATA[47] !== 1'bz) && TXDATA[47]; // rv 0
assign TXDATA_in[48] = (TXDATA[48] !== 1'bz) && TXDATA[48]; // rv 0
assign TXDATA_in[49] = (TXDATA[49] !== 1'bz) && TXDATA[49]; // rv 0
assign TXDATA_in[4] = (TXDATA[4] !== 1'bz) && TXDATA[4]; // rv 0
assign TXDATA_in[50] = (TXDATA[50] !== 1'bz) && TXDATA[50]; // rv 0
assign TXDATA_in[51] = (TXDATA[51] !== 1'bz) && TXDATA[51]; // rv 0
assign TXDATA_in[52] = (TXDATA[52] !== 1'bz) && TXDATA[52]; // rv 0
assign TXDATA_in[53] = (TXDATA[53] !== 1'bz) && TXDATA[53]; // rv 0
assign TXDATA_in[54] = (TXDATA[54] !== 1'bz) && TXDATA[54]; // rv 0
assign TXDATA_in[55] = (TXDATA[55] !== 1'bz) && TXDATA[55]; // rv 0
assign TXDATA_in[56] = (TXDATA[56] !== 1'bz) && TXDATA[56]; // rv 0
assign TXDATA_in[57] = (TXDATA[57] !== 1'bz) && TXDATA[57]; // rv 0
assign TXDATA_in[58] = (TXDATA[58] !== 1'bz) && TXDATA[58]; // rv 0
assign TXDATA_in[59] = (TXDATA[59] !== 1'bz) && TXDATA[59]; // rv 0
assign TXDATA_in[5] = (TXDATA[5] !== 1'bz) && TXDATA[5]; // rv 0
assign TXDATA_in[60] = (TXDATA[60] !== 1'bz) && TXDATA[60]; // rv 0
assign TXDATA_in[61] = (TXDATA[61] !== 1'bz) && TXDATA[61]; // rv 0
assign TXDATA_in[62] = (TXDATA[62] !== 1'bz) && TXDATA[62]; // rv 0
assign TXDATA_in[63] = (TXDATA[63] !== 1'bz) && TXDATA[63]; // rv 0
assign TXDATA_in[64] = (TXDATA[64] !== 1'bz) && TXDATA[64]; // rv 0
assign TXDATA_in[65] = (TXDATA[65] !== 1'bz) && TXDATA[65]; // rv 0
assign TXDATA_in[66] = (TXDATA[66] !== 1'bz) && TXDATA[66]; // rv 0
assign TXDATA_in[67] = (TXDATA[67] !== 1'bz) && TXDATA[67]; // rv 0
assign TXDATA_in[68] = (TXDATA[68] !== 1'bz) && TXDATA[68]; // rv 0
assign TXDATA_in[69] = (TXDATA[69] !== 1'bz) && TXDATA[69]; // rv 0
assign TXDATA_in[6] = (TXDATA[6] !== 1'bz) && TXDATA[6]; // rv 0
assign TXDATA_in[70] = (TXDATA[70] !== 1'bz) && TXDATA[70]; // rv 0
assign TXDATA_in[71] = (TXDATA[71] !== 1'bz) && TXDATA[71]; // rv 0
assign TXDATA_in[72] = (TXDATA[72] !== 1'bz) && TXDATA[72]; // rv 0
assign TXDATA_in[73] = (TXDATA[73] !== 1'bz) && TXDATA[73]; // rv 0
assign TXDATA_in[74] = (TXDATA[74] !== 1'bz) && TXDATA[74]; // rv 0
assign TXDATA_in[75] = (TXDATA[75] !== 1'bz) && TXDATA[75]; // rv 0
assign TXDATA_in[76] = (TXDATA[76] !== 1'bz) && TXDATA[76]; // rv 0
assign TXDATA_in[77] = (TXDATA[77] !== 1'bz) && TXDATA[77]; // rv 0
assign TXDATA_in[78] = (TXDATA[78] !== 1'bz) && TXDATA[78]; // rv 0
assign TXDATA_in[79] = (TXDATA[79] !== 1'bz) && TXDATA[79]; // rv 0
assign TXDATA_in[7] = (TXDATA[7] !== 1'bz) && TXDATA[7]; // rv 0
assign TXDATA_in[80] = (TXDATA[80] !== 1'bz) && TXDATA[80]; // rv 0
assign TXDATA_in[81] = (TXDATA[81] !== 1'bz) && TXDATA[81]; // rv 0
assign TXDATA_in[82] = (TXDATA[82] !== 1'bz) && TXDATA[82]; // rv 0
assign TXDATA_in[83] = (TXDATA[83] !== 1'bz) && TXDATA[83]; // rv 0
assign TXDATA_in[84] = (TXDATA[84] !== 1'bz) && TXDATA[84]; // rv 0
assign TXDATA_in[85] = (TXDATA[85] !== 1'bz) && TXDATA[85]; // rv 0
assign TXDATA_in[86] = (TXDATA[86] !== 1'bz) && TXDATA[86]; // rv 0
assign TXDATA_in[87] = (TXDATA[87] !== 1'bz) && TXDATA[87]; // rv 0
assign TXDATA_in[88] = (TXDATA[88] !== 1'bz) && TXDATA[88]; // rv 0
assign TXDATA_in[89] = (TXDATA[89] !== 1'bz) && TXDATA[89]; // rv 0
assign TXDATA_in[8] = (TXDATA[8] !== 1'bz) && TXDATA[8]; // rv 0
assign TXDATA_in[90] = (TXDATA[90] !== 1'bz) && TXDATA[90]; // rv 0
assign TXDATA_in[91] = (TXDATA[91] !== 1'bz) && TXDATA[91]; // rv 0
assign TXDATA_in[92] = (TXDATA[92] !== 1'bz) && TXDATA[92]; // rv 0
assign TXDATA_in[93] = (TXDATA[93] !== 1'bz) && TXDATA[93]; // rv 0
assign TXDATA_in[94] = (TXDATA[94] !== 1'bz) && TXDATA[94]; // rv 0
assign TXDATA_in[95] = (TXDATA[95] !== 1'bz) && TXDATA[95]; // rv 0
assign TXDATA_in[96] = (TXDATA[96] !== 1'bz) && TXDATA[96]; // rv 0
assign TXDATA_in[97] = (TXDATA[97] !== 1'bz) && TXDATA[97]; // rv 0
assign TXDATA_in[98] = (TXDATA[98] !== 1'bz) && TXDATA[98]; // rv 0
assign TXDATA_in[99] = (TXDATA[99] !== 1'bz) && TXDATA[99]; // rv 0
assign TXDATA_in[9] = (TXDATA[9] !== 1'bz) && TXDATA[9]; // rv 0
assign TXDETECTRX_in = (TXDETECTRX !== 1'bz) && TXDETECTRX; // rv 0
assign TXELECIDLE_in = (TXELECIDLE !== 1'bz) && TXELECIDLE; // rv 0
assign TXHEADER_in[0] = (TXHEADER[0] !== 1'bz) && TXHEADER[0]; // rv 0
assign TXHEADER_in[1] = (TXHEADER[1] !== 1'bz) && TXHEADER[1]; // rv 0
assign TXHEADER_in[2] = (TXHEADER[2] !== 1'bz) && TXHEADER[2]; // rv 0
assign TXHEADER_in[3] = (TXHEADER[3] !== 1'bz) && TXHEADER[3]; // rv 0
assign TXHEADER_in[4] = (TXHEADER[4] !== 1'bz) && TXHEADER[4]; // rv 0
assign TXHEADER_in[5] = (TXHEADER[5] !== 1'bz) && TXHEADER[5]; // rv 0
assign TXINHIBIT_in = (TXINHIBIT !== 1'bz) && TXINHIBIT; // rv 0
assign TXPD_in[0] = (TXPD[0] !== 1'bz) && TXPD[0]; // rv 0
assign TXPD_in[1] = (TXPD[1] !== 1'bz) && TXPD[1]; // rv 0
assign TXPOLARITY_in = (TXPOLARITY !== 1'bz) && TXPOLARITY; // rv 0
assign TXPRBSFORCEERR_in = (TXPRBSFORCEERR !== 1'bz) && TXPRBSFORCEERR; // rv 0
assign TXPRBSSEL_in[0] = (TXPRBSSEL[0] !== 1'bz) && TXPRBSSEL[0]; // rv 0
assign TXPRBSSEL_in[1] = (TXPRBSSEL[1] !== 1'bz) && TXPRBSSEL[1]; // rv 0
assign TXPRBSSEL_in[2] = (TXPRBSSEL[2] !== 1'bz) && TXPRBSSEL[2]; // rv 0
assign TXPRBSSEL_in[3] = (TXPRBSSEL[3] !== 1'bz) && TXPRBSSEL[3]; // rv 0
assign TXRATE_in[0] = (TXRATE[0] !== 1'bz) && TXRATE[0]; // rv 0
assign TXRATE_in[1] = (TXRATE[1] !== 1'bz) && TXRATE[1]; // rv 0
assign TXRATE_in[2] = (TXRATE[2] !== 1'bz) && TXRATE[2]; // rv 0
assign TXSEQUENCE_in[0] = (TXSEQUENCE[0] !== 1'bz) && TXSEQUENCE[0]; // rv 0
assign TXSEQUENCE_in[1] = (TXSEQUENCE[1] !== 1'bz) && TXSEQUENCE[1]; // rv 0
assign TXSEQUENCE_in[2] = (TXSEQUENCE[2] !== 1'bz) && TXSEQUENCE[2]; // rv 0
assign TXSEQUENCE_in[3] = (TXSEQUENCE[3] !== 1'bz) && TXSEQUENCE[3]; // rv 0
assign TXSEQUENCE_in[4] = (TXSEQUENCE[4] !== 1'bz) && TXSEQUENCE[4]; // rv 0
assign TXSEQUENCE_in[5] = (TXSEQUENCE[5] !== 1'bz) && TXSEQUENCE[5]; // rv 0
assign TXSEQUENCE_in[6] = (TXSEQUENCE[6] !== 1'bz) && TXSEQUENCE[6]; // rv 0
assign TXUSRCLK2_in = (TXUSRCLK2 !== 1'bz) && TXUSRCLK2; // rv 0
`endif
assign CDRSTEPDIR_in = (CDRSTEPDIR !== 1'bz) && CDRSTEPDIR; // rv 0
assign CDRSTEPSQ_in = (CDRSTEPSQ !== 1'bz) && CDRSTEPSQ; // rv 0
assign CDRSTEPSX_in = (CDRSTEPSX !== 1'bz) && CDRSTEPSX; // rv 0
assign CFGRESET_in = (CFGRESET !== 1'bz) && CFGRESET; // rv 0
assign CLKRSVD0_in = (CLKRSVD0 !== 1'bz) && CLKRSVD0; // rv 0
assign CLKRSVD1_in = (CLKRSVD1 !== 1'bz) && CLKRSVD1; // rv 0
assign CPLLFREQLOCK_in = (CPLLFREQLOCK !== 1'bz) && CPLLFREQLOCK; // rv 0
assign CPLLLOCKDETCLK_in = (CPLLLOCKDETCLK !== 1'bz) && CPLLLOCKDETCLK; // rv 0
assign CPLLLOCKEN_in = (CPLLLOCKEN !== 1'bz) && CPLLLOCKEN; // rv 0
assign CPLLPD_in = (CPLLPD !== 1'bz) && CPLLPD; // rv 0
assign CPLLREFCLKSEL_in[0] = (CPLLREFCLKSEL[0] === 1'bz) || CPLLREFCLKSEL[0]; // rv 1
assign CPLLREFCLKSEL_in[1] = (CPLLREFCLKSEL[1] !== 1'bz) && CPLLREFCLKSEL[1]; // rv 0
assign CPLLREFCLKSEL_in[2] = (CPLLREFCLKSEL[2] !== 1'bz) && CPLLREFCLKSEL[2]; // rv 0
assign CPLLRESET_in = (CPLLRESET !== 1'bz) && CPLLRESET; // rv 0
assign DMONFIFORESET_in = (DMONFIFORESET !== 1'bz) && DMONFIFORESET; // rv 0
assign DMONITORCLK_in = (DMONITORCLK !== 1'bz) && DMONITORCLK; // rv 0
assign DRPRST_in = (DRPRST === 1'bz) || DRPRST; // rv 1
assign EYESCANRESET_in = (EYESCANRESET !== 1'bz) && EYESCANRESET; // rv 0
assign EYESCANTRIGGER_in = (EYESCANTRIGGER !== 1'bz) && EYESCANTRIGGER; // rv 0
assign FREQOS_in = (FREQOS !== 1'bz) && FREQOS; // rv 0
assign GTGREFCLK_in = GTGREFCLK;
assign GTNORTHREFCLK0_in = GTNORTHREFCLK0;
assign GTNORTHREFCLK1_in = GTNORTHREFCLK1;
assign GTREFCLK0_in = GTREFCLK0;
assign GTREFCLK1_in = GTREFCLK1;
assign GTRSVD_in[0] = (GTRSVD[0] !== 1'bz) && GTRSVD[0]; // rv 0
assign GTRSVD_in[10] = (GTRSVD[10] !== 1'bz) && GTRSVD[10]; // rv 0
assign GTRSVD_in[11] = (GTRSVD[11] !== 1'bz) && GTRSVD[11]; // rv 0
assign GTRSVD_in[12] = (GTRSVD[12] !== 1'bz) && GTRSVD[12]; // rv 0
assign GTRSVD_in[13] = (GTRSVD[13] !== 1'bz) && GTRSVD[13]; // rv 0
assign GTRSVD_in[14] = (GTRSVD[14] !== 1'bz) && GTRSVD[14]; // rv 0
assign GTRSVD_in[15] = (GTRSVD[15] !== 1'bz) && GTRSVD[15]; // rv 0
assign GTRSVD_in[1] = (GTRSVD[1] !== 1'bz) && GTRSVD[1]; // rv 0
assign GTRSVD_in[2] = (GTRSVD[2] !== 1'bz) && GTRSVD[2]; // rv 0
assign GTRSVD_in[3] = (GTRSVD[3] !== 1'bz) && GTRSVD[3]; // rv 0
assign GTRSVD_in[4] = (GTRSVD[4] !== 1'bz) && GTRSVD[4]; // rv 0
assign GTRSVD_in[5] = (GTRSVD[5] !== 1'bz) && GTRSVD[5]; // rv 0
assign GTRSVD_in[6] = (GTRSVD[6] !== 1'bz) && GTRSVD[6]; // rv 0
assign GTRSVD_in[7] = (GTRSVD[7] !== 1'bz) && GTRSVD[7]; // rv 0
assign GTRSVD_in[8] = (GTRSVD[8] !== 1'bz) && GTRSVD[8]; // rv 0
assign GTRSVD_in[9] = (GTRSVD[9] !== 1'bz) && GTRSVD[9]; // rv 0
assign GTRXRESETSEL_in = (GTRXRESETSEL !== 1'bz) && GTRXRESETSEL; // rv 0
assign GTRXRESET_in = (GTRXRESET !== 1'bz) && GTRXRESET; // rv 0
assign GTSOUTHREFCLK0_in = GTSOUTHREFCLK0;
assign GTSOUTHREFCLK1_in = GTSOUTHREFCLK1;
assign GTTXRESETSEL_in = (GTTXRESETSEL !== 1'bz) && GTTXRESETSEL; // rv 0
assign GTTXRESET_in = (GTTXRESET !== 1'bz) && GTTXRESET; // rv 0
assign GTYRXN_in = GTYRXN;
assign GTYRXP_in = GTYRXP;
assign INCPCTRL_in = (INCPCTRL !== 1'bz) && INCPCTRL; // rv 0
assign LOOPBACK_in[0] = (LOOPBACK[0] !== 1'bz) && LOOPBACK[0]; // rv 0
assign LOOPBACK_in[1] = (LOOPBACK[1] !== 1'bz) && LOOPBACK[1]; // rv 0
assign LOOPBACK_in[2] = (LOOPBACK[2] !== 1'bz) && LOOPBACK[2]; // rv 0
assign PCIEEQRXEQADAPTDONE_in = (PCIEEQRXEQADAPTDONE !== 1'bz) && PCIEEQRXEQADAPTDONE; // rv 0
assign PCIERSTIDLE_in = (PCIERSTIDLE !== 1'bz) && PCIERSTIDLE; // rv 0
assign PCIERSTTXSYNCSTART_in = (PCIERSTTXSYNCSTART !== 1'bz) && PCIERSTTXSYNCSTART; // rv 0
assign PCIEUSERRATEDONE_in = (PCIEUSERRATEDONE !== 1'bz) && PCIEUSERRATEDONE; // rv 0
assign PCSRSVDIN_in[0] = (PCSRSVDIN[0] === 1'bz) || PCSRSVDIN[0]; // rv 1
assign PCSRSVDIN_in[10] = (PCSRSVDIN[10] !== 1'bz) && PCSRSVDIN[10]; // rv 0
assign PCSRSVDIN_in[11] = (PCSRSVDIN[11] !== 1'bz) && PCSRSVDIN[11]; // rv 0
assign PCSRSVDIN_in[12] = (PCSRSVDIN[12] !== 1'bz) && PCSRSVDIN[12]; // rv 0
assign PCSRSVDIN_in[13] = (PCSRSVDIN[13] !== 1'bz) && PCSRSVDIN[13]; // rv 0
assign PCSRSVDIN_in[14] = (PCSRSVDIN[14] !== 1'bz) && PCSRSVDIN[14]; // rv 0
assign PCSRSVDIN_in[15] = (PCSRSVDIN[15] !== 1'bz) && PCSRSVDIN[15]; // rv 0
assign PCSRSVDIN_in[1] = (PCSRSVDIN[1] !== 1'bz) && PCSRSVDIN[1]; // rv 0
assign PCSRSVDIN_in[2] = (PCSRSVDIN[2] !== 1'bz) && PCSRSVDIN[2]; // rv 0
assign PCSRSVDIN_in[3] = (PCSRSVDIN[3] !== 1'bz) && PCSRSVDIN[3]; // rv 0
assign PCSRSVDIN_in[4] = (PCSRSVDIN[4] !== 1'bz) && PCSRSVDIN[4]; // rv 0
assign PCSRSVDIN_in[5] = (PCSRSVDIN[5] !== 1'bz) && PCSRSVDIN[5]; // rv 0
assign PCSRSVDIN_in[6] = (PCSRSVDIN[6] !== 1'bz) && PCSRSVDIN[6]; // rv 0
assign PCSRSVDIN_in[7] = (PCSRSVDIN[7] !== 1'bz) && PCSRSVDIN[7]; // rv 0
assign PCSRSVDIN_in[8] = (PCSRSVDIN[8] !== 1'bz) && PCSRSVDIN[8]; // rv 0
assign PCSRSVDIN_in[9] = (PCSRSVDIN[9] !== 1'bz) && PCSRSVDIN[9]; // rv 0
assign QPLL0CLK_in = QPLL0CLK;
assign QPLL0FREQLOCK_in = (QPLL0FREQLOCK !== 1'bz) && QPLL0FREQLOCK; // rv 0
assign QPLL0REFCLK_in = QPLL0REFCLK;
assign QPLL1CLK_in = QPLL1CLK;
assign QPLL1FREQLOCK_in = (QPLL1FREQLOCK !== 1'bz) && QPLL1FREQLOCK; // rv 0
assign QPLL1REFCLK_in = QPLL1REFCLK;
assign RESETOVRD_in = (RESETOVRD !== 1'bz) && RESETOVRD; // rv 0
assign RXAFECFOKEN_in = (RXAFECFOKEN === 1'bz) || RXAFECFOKEN; // rv 1
assign RXBUFRESET_in = (RXBUFRESET !== 1'bz) && RXBUFRESET; // rv 0
assign RXCDRFREQRESET_in = (RXCDRFREQRESET !== 1'bz) && RXCDRFREQRESET; // rv 0
assign RXCDRHOLD_in = (RXCDRHOLD !== 1'bz) && RXCDRHOLD; // rv 0
assign RXCDROVRDEN_in = (RXCDROVRDEN !== 1'bz) && RXCDROVRDEN; // rv 0
assign RXCDRRESET_in = (RXCDRRESET !== 1'bz) && RXCDRRESET; // rv 0
assign RXCKCALRESET_in = (RXCKCALRESET !== 1'bz) && RXCKCALRESET; // rv 0
assign RXCKCALSTART_in[0] = (RXCKCALSTART[0] !== 1'bz) && RXCKCALSTART[0]; // rv 0
assign RXCKCALSTART_in[1] = (RXCKCALSTART[1] !== 1'bz) && RXCKCALSTART[1]; // rv 0
assign RXCKCALSTART_in[2] = (RXCKCALSTART[2] !== 1'bz) && RXCKCALSTART[2]; // rv 0
assign RXCKCALSTART_in[3] = (RXCKCALSTART[3] !== 1'bz) && RXCKCALSTART[3]; // rv 0
assign RXCKCALSTART_in[4] = (RXCKCALSTART[4] !== 1'bz) && RXCKCALSTART[4]; // rv 0
assign RXCKCALSTART_in[5] = (RXCKCALSTART[5] !== 1'bz) && RXCKCALSTART[5]; // rv 0
assign RXCKCALSTART_in[6] = (RXCKCALSTART[6] !== 1'bz) && RXCKCALSTART[6]; // rv 0
assign RXDFEAGCHOLD_in = (RXDFEAGCHOLD !== 1'bz) && RXDFEAGCHOLD; // rv 0
assign RXDFEAGCOVRDEN_in = (RXDFEAGCOVRDEN !== 1'bz) && RXDFEAGCOVRDEN; // rv 0
assign RXDFECFOKFCNUM_in[0] = (RXDFECFOKFCNUM[0] !== 1'bz) && RXDFECFOKFCNUM[0]; // rv 0
assign RXDFECFOKFCNUM_in[1] = (RXDFECFOKFCNUM[1] === 1'bz) || RXDFECFOKFCNUM[1]; // rv 1
assign RXDFECFOKFCNUM_in[2] = (RXDFECFOKFCNUM[2] === 1'bz) || RXDFECFOKFCNUM[2]; // rv 1
assign RXDFECFOKFCNUM_in[3] = (RXDFECFOKFCNUM[3] !== 1'bz) && RXDFECFOKFCNUM[3]; // rv 0
assign RXDFECFOKFEN_in = (RXDFECFOKFEN !== 1'bz) && RXDFECFOKFEN; // rv 0
assign RXDFECFOKFPULSE_in = (RXDFECFOKFPULSE !== 1'bz) && RXDFECFOKFPULSE; // rv 0
assign RXDFECFOKHOLD_in = (RXDFECFOKHOLD !== 1'bz) && RXDFECFOKHOLD; // rv 0
assign RXDFECFOKOVREN_in = (RXDFECFOKOVREN !== 1'bz) && RXDFECFOKOVREN; // rv 0
assign RXDFEKHHOLD_in = (RXDFEKHHOLD !== 1'bz) && RXDFEKHHOLD; // rv 0
assign RXDFEKHOVRDEN_in = (RXDFEKHOVRDEN !== 1'bz) && RXDFEKHOVRDEN; // rv 0
assign RXDFELFHOLD_in = (RXDFELFHOLD !== 1'bz) && RXDFELFHOLD; // rv 0
assign RXDFELFOVRDEN_in = (RXDFELFOVRDEN !== 1'bz) && RXDFELFOVRDEN; // rv 0
assign RXDFELPMRESET_in = (RXDFELPMRESET !== 1'bz) && RXDFELPMRESET; // rv 0
assign RXDFETAP10HOLD_in = (RXDFETAP10HOLD !== 1'bz) && RXDFETAP10HOLD; // rv 0
assign RXDFETAP10OVRDEN_in = (RXDFETAP10OVRDEN !== 1'bz) && RXDFETAP10OVRDEN; // rv 0
assign RXDFETAP11HOLD_in = (RXDFETAP11HOLD !== 1'bz) && RXDFETAP11HOLD; // rv 0
assign RXDFETAP11OVRDEN_in = (RXDFETAP11OVRDEN !== 1'bz) && RXDFETAP11OVRDEN; // rv 0
assign RXDFETAP12HOLD_in = (RXDFETAP12HOLD !== 1'bz) && RXDFETAP12HOLD; // rv 0
assign RXDFETAP12OVRDEN_in = (RXDFETAP12OVRDEN !== 1'bz) && RXDFETAP12OVRDEN; // rv 0
assign RXDFETAP13HOLD_in = (RXDFETAP13HOLD !== 1'bz) && RXDFETAP13HOLD; // rv 0
assign RXDFETAP13OVRDEN_in = (RXDFETAP13OVRDEN !== 1'bz) && RXDFETAP13OVRDEN; // rv 0
assign RXDFETAP14HOLD_in = (RXDFETAP14HOLD !== 1'bz) && RXDFETAP14HOLD; // rv 0
assign RXDFETAP14OVRDEN_in = (RXDFETAP14OVRDEN !== 1'bz) && RXDFETAP14OVRDEN; // rv 0
assign RXDFETAP15HOLD_in = (RXDFETAP15HOLD !== 1'bz) && RXDFETAP15HOLD; // rv 0
assign RXDFETAP15OVRDEN_in = (RXDFETAP15OVRDEN !== 1'bz) && RXDFETAP15OVRDEN; // rv 0
assign RXDFETAP2HOLD_in = (RXDFETAP2HOLD !== 1'bz) && RXDFETAP2HOLD; // rv 0
assign RXDFETAP2OVRDEN_in = (RXDFETAP2OVRDEN !== 1'bz) && RXDFETAP2OVRDEN; // rv 0
assign RXDFETAP3HOLD_in = (RXDFETAP3HOLD !== 1'bz) && RXDFETAP3HOLD; // rv 0
assign RXDFETAP3OVRDEN_in = (RXDFETAP3OVRDEN !== 1'bz) && RXDFETAP3OVRDEN; // rv 0
assign RXDFETAP4HOLD_in = (RXDFETAP4HOLD !== 1'bz) && RXDFETAP4HOLD; // rv 0
assign RXDFETAP4OVRDEN_in = (RXDFETAP4OVRDEN !== 1'bz) && RXDFETAP4OVRDEN; // rv 0
assign RXDFETAP5HOLD_in = (RXDFETAP5HOLD !== 1'bz) && RXDFETAP5HOLD; // rv 0
assign RXDFETAP5OVRDEN_in = (RXDFETAP5OVRDEN !== 1'bz) && RXDFETAP5OVRDEN; // rv 0
assign RXDFETAP6HOLD_in = (RXDFETAP6HOLD !== 1'bz) && RXDFETAP6HOLD; // rv 0
assign RXDFETAP6OVRDEN_in = (RXDFETAP6OVRDEN !== 1'bz) && RXDFETAP6OVRDEN; // rv 0
assign RXDFETAP7HOLD_in = (RXDFETAP7HOLD !== 1'bz) && RXDFETAP7HOLD; // rv 0
assign RXDFETAP7OVRDEN_in = (RXDFETAP7OVRDEN !== 1'bz) && RXDFETAP7OVRDEN; // rv 0
assign RXDFETAP8HOLD_in = (RXDFETAP8HOLD !== 1'bz) && RXDFETAP8HOLD; // rv 0
assign RXDFETAP8OVRDEN_in = (RXDFETAP8OVRDEN !== 1'bz) && RXDFETAP8OVRDEN; // rv 0
assign RXDFETAP9HOLD_in = (RXDFETAP9HOLD !== 1'bz) && RXDFETAP9HOLD; // rv 0
assign RXDFETAP9OVRDEN_in = (RXDFETAP9OVRDEN !== 1'bz) && RXDFETAP9OVRDEN; // rv 0
assign RXDFEUTHOLD_in = (RXDFEUTHOLD !== 1'bz) && RXDFEUTHOLD; // rv 0
assign RXDFEUTOVRDEN_in = (RXDFEUTOVRDEN !== 1'bz) && RXDFEUTOVRDEN; // rv 0
assign RXDFEVPHOLD_in = (RXDFEVPHOLD !== 1'bz) && RXDFEVPHOLD; // rv 0
assign RXDFEVPOVRDEN_in = (RXDFEVPOVRDEN !== 1'bz) && RXDFEVPOVRDEN; // rv 0
assign RXDFEXYDEN_in = (RXDFEXYDEN !== 1'bz) && RXDFEXYDEN; // rv 0
assign RXDLYBYPASS_in = (RXDLYBYPASS !== 1'bz) && RXDLYBYPASS; // rv 0
assign RXDLYEN_in = (RXDLYEN !== 1'bz) && RXDLYEN; // rv 0
assign RXDLYOVRDEN_in = (RXDLYOVRDEN !== 1'bz) && RXDLYOVRDEN; // rv 0
assign RXDLYSRESET_in = (RXDLYSRESET !== 1'bz) && RXDLYSRESET; // rv 0
assign RXELECIDLEMODE_in[0] = (RXELECIDLEMODE[0] !== 1'bz) && RXELECIDLEMODE[0]; // rv 0
assign RXELECIDLEMODE_in[1] = (RXELECIDLEMODE[1] !== 1'bz) && RXELECIDLEMODE[1]; // rv 0
assign RXEQTRAINING_in = (RXEQTRAINING !== 1'bz) && RXEQTRAINING; // rv 0
assign RXLATCLK_in = (RXLATCLK !== 1'bz) && RXLATCLK; // rv 0
assign RXLPMEN_in = (RXLPMEN !== 1'bz) && RXLPMEN; // rv 0
assign RXLPMGCHOLD_in = (RXLPMGCHOLD !== 1'bz) && RXLPMGCHOLD; // rv 0
assign RXLPMGCOVRDEN_in = (RXLPMGCOVRDEN !== 1'bz) && RXLPMGCOVRDEN; // rv 0
assign RXLPMHFHOLD_in = (RXLPMHFHOLD !== 1'bz) && RXLPMHFHOLD; // rv 0
assign RXLPMHFOVRDEN_in = (RXLPMHFOVRDEN !== 1'bz) && RXLPMHFOVRDEN; // rv 0
assign RXLPMLFHOLD_in = (RXLPMLFHOLD !== 1'bz) && RXLPMLFHOLD; // rv 0
assign RXLPMLFKLOVRDEN_in = (RXLPMLFKLOVRDEN !== 1'bz) && RXLPMLFKLOVRDEN; // rv 0
assign RXLPMOSHOLD_in = (RXLPMOSHOLD !== 1'bz) && RXLPMOSHOLD; // rv 0
assign RXLPMOSOVRDEN_in = (RXLPMOSOVRDEN !== 1'bz) && RXLPMOSOVRDEN; // rv 0
assign RXMONITORSEL_in[0] = (RXMONITORSEL[0] !== 1'bz) && RXMONITORSEL[0]; // rv 0
assign RXMONITORSEL_in[1] = (RXMONITORSEL[1] !== 1'bz) && RXMONITORSEL[1]; // rv 0
assign RXOOBRESET_in = (RXOOBRESET !== 1'bz) && RXOOBRESET; // rv 0
assign RXOSCALRESET_in = (RXOSCALRESET !== 1'bz) && RXOSCALRESET; // rv 0
assign RXOSHOLD_in = (RXOSHOLD !== 1'bz) && RXOSHOLD; // rv 0
assign RXOSOVRDEN_in = (RXOSOVRDEN !== 1'bz) && RXOSOVRDEN; // rv 0
assign RXOUTCLKSEL_in[0] = (RXOUTCLKSEL[0] !== 1'bz) && RXOUTCLKSEL[0]; // rv 0
assign RXOUTCLKSEL_in[1] = (RXOUTCLKSEL[1] !== 1'bz) && RXOUTCLKSEL[1]; // rv 0
assign RXOUTCLKSEL_in[2] = (RXOUTCLKSEL[2] !== 1'bz) && RXOUTCLKSEL[2]; // rv 0
assign RXPCSRESET_in = (RXPCSRESET !== 1'bz) && RXPCSRESET; // rv 0
assign RXPD_in[0] = (RXPD[0] !== 1'bz) && RXPD[0]; // rv 0
assign RXPD_in[1] = (RXPD[1] !== 1'bz) && RXPD[1]; // rv 0
assign RXPHALIGNEN_in = (RXPHALIGNEN !== 1'bz) && RXPHALIGNEN; // rv 0
assign RXPHALIGN_in = (RXPHALIGN !== 1'bz) && RXPHALIGN; // rv 0
assign RXPHDLYPD_in = (RXPHDLYPD !== 1'bz) && RXPHDLYPD; // rv 0
assign RXPHDLYRESET_in = (RXPHDLYRESET !== 1'bz) && RXPHDLYRESET; // rv 0
assign RXPLLCLKSEL_in[0] = (RXPLLCLKSEL[0] !== 1'bz) && RXPLLCLKSEL[0]; // rv 0
assign RXPLLCLKSEL_in[1] = (RXPLLCLKSEL[1] !== 1'bz) && RXPLLCLKSEL[1]; // rv 0
assign RXPMARESET_in = (RXPMARESET !== 1'bz) && RXPMARESET; // rv 0
assign RXPROGDIVRESET_in = (RXPROGDIVRESET !== 1'bz) && RXPROGDIVRESET; // rv 0
assign RXRATEMODE_in = (RXRATEMODE !== 1'bz) && RXRATEMODE; // rv 0
assign RXSYNCALLIN_in = (RXSYNCALLIN !== 1'bz) && RXSYNCALLIN; // rv 0
assign RXSYNCIN_in = (RXSYNCIN !== 1'bz) && RXSYNCIN; // rv 0
assign RXSYNCMODE_in = (RXSYNCMODE === 1'bz) || RXSYNCMODE; // rv 1
assign RXSYSCLKSEL_in[0] = (RXSYSCLKSEL[0] !== 1'bz) && RXSYSCLKSEL[0]; // rv 0
assign RXSYSCLKSEL_in[1] = (RXSYSCLKSEL[1] !== 1'bz) && RXSYSCLKSEL[1]; // rv 0
assign RXTERMINATION_in = (RXTERMINATION !== 1'bz) && RXTERMINATION; // rv 0
assign RXUSERRDY_in = (RXUSERRDY !== 1'bz) && RXUSERRDY; // rv 0
assign SIGVALIDCLK_in = (SIGVALIDCLK !== 1'bz) && SIGVALIDCLK; // rv 0
assign TSTIN_in[0] = (TSTIN[0] !== 1'bz) && TSTIN[0]; // rv 0
assign TSTIN_in[10] = (TSTIN[10] !== 1'bz) && TSTIN[10]; // rv 0
assign TSTIN_in[11] = (TSTIN[11] !== 1'bz) && TSTIN[11]; // rv 0
assign TSTIN_in[12] = (TSTIN[12] !== 1'bz) && TSTIN[12]; // rv 0
assign TSTIN_in[13] = (TSTIN[13] !== 1'bz) && TSTIN[13]; // rv 0
assign TSTIN_in[14] = (TSTIN[14] !== 1'bz) && TSTIN[14]; // rv 0
assign TSTIN_in[15] = (TSTIN[15] !== 1'bz) && TSTIN[15]; // rv 0
assign TSTIN_in[16] = (TSTIN[16] !== 1'bz) && TSTIN[16]; // rv 0
assign TSTIN_in[17] = (TSTIN[17] !== 1'bz) && TSTIN[17]; // rv 0
assign TSTIN_in[18] = (TSTIN[18] !== 1'bz) && TSTIN[18]; // rv 0
assign TSTIN_in[19] = (TSTIN[19] !== 1'bz) && TSTIN[19]; // rv 0
assign TSTIN_in[1] = (TSTIN[1] !== 1'bz) && TSTIN[1]; // rv 0
assign TSTIN_in[2] = (TSTIN[2] !== 1'bz) && TSTIN[2]; // rv 0
assign TSTIN_in[3] = (TSTIN[3] !== 1'bz) && TSTIN[3]; // rv 0
assign TSTIN_in[4] = (TSTIN[4] !== 1'bz) && TSTIN[4]; // rv 0
assign TSTIN_in[5] = (TSTIN[5] !== 1'bz) && TSTIN[5]; // rv 0
assign TSTIN_in[6] = (TSTIN[6] !== 1'bz) && TSTIN[6]; // rv 0
assign TSTIN_in[7] = (TSTIN[7] !== 1'bz) && TSTIN[7]; // rv 0
assign TSTIN_in[8] = (TSTIN[8] !== 1'bz) && TSTIN[8]; // rv 0
assign TSTIN_in[9] = (TSTIN[9] !== 1'bz) && TSTIN[9]; // rv 0
assign TXDATAEXTENDRSVD_in[0] = (TXDATAEXTENDRSVD[0] !== 1'bz) && TXDATAEXTENDRSVD[0]; // rv 0
assign TXDATAEXTENDRSVD_in[1] = (TXDATAEXTENDRSVD[1] !== 1'bz) && TXDATAEXTENDRSVD[1]; // rv 0
assign TXDATAEXTENDRSVD_in[2] = (TXDATAEXTENDRSVD[2] !== 1'bz) && TXDATAEXTENDRSVD[2]; // rv 0
assign TXDATAEXTENDRSVD_in[3] = (TXDATAEXTENDRSVD[3] !== 1'bz) && TXDATAEXTENDRSVD[3]; // rv 0
assign TXDATAEXTENDRSVD_in[4] = (TXDATAEXTENDRSVD[4] !== 1'bz) && TXDATAEXTENDRSVD[4]; // rv 0
assign TXDATAEXTENDRSVD_in[5] = (TXDATAEXTENDRSVD[5] !== 1'bz) && TXDATAEXTENDRSVD[5]; // rv 0
assign TXDATAEXTENDRSVD_in[6] = (TXDATAEXTENDRSVD[6] !== 1'bz) && TXDATAEXTENDRSVD[6]; // rv 0
assign TXDATAEXTENDRSVD_in[7] = (TXDATAEXTENDRSVD[7] !== 1'bz) && TXDATAEXTENDRSVD[7]; // rv 0
assign TXDCCFORCESTART_in = (TXDCCFORCESTART !== 1'bz) && TXDCCFORCESTART; // rv 0
assign TXDCCRESET_in = (TXDCCRESET !== 1'bz) && TXDCCRESET; // rv 0
assign TXDEEMPH_in[0] = (TXDEEMPH[0] !== 1'bz) && TXDEEMPH[0]; // rv 0
assign TXDEEMPH_in[1] = (TXDEEMPH[1] !== 1'bz) && TXDEEMPH[1]; // rv 0
assign TXDIFFCTRL_in[0] = (TXDIFFCTRL[0] !== 1'bz) && TXDIFFCTRL[0]; // rv 0
assign TXDIFFCTRL_in[1] = (TXDIFFCTRL[1] !== 1'bz) && TXDIFFCTRL[1]; // rv 0
assign TXDIFFCTRL_in[2] = (TXDIFFCTRL[2] !== 1'bz) && TXDIFFCTRL[2]; // rv 0
assign TXDIFFCTRL_in[3] = (TXDIFFCTRL[3] !== 1'bz) && TXDIFFCTRL[3]; // rv 0
assign TXDIFFCTRL_in[4] = (TXDIFFCTRL[4] !== 1'bz) && TXDIFFCTRL[4]; // rv 0
assign TXDLYBYPASS_in = (TXDLYBYPASS !== 1'bz) && TXDLYBYPASS; // rv 0
assign TXDLYEN_in = (TXDLYEN !== 1'bz) && TXDLYEN; // rv 0
assign TXDLYHOLD_in = (TXDLYHOLD !== 1'bz) && TXDLYHOLD; // rv 0
assign TXDLYOVRDEN_in = (TXDLYOVRDEN !== 1'bz) && TXDLYOVRDEN; // rv 0
assign TXDLYSRESET_in = (TXDLYSRESET !== 1'bz) && TXDLYSRESET; // rv 0
assign TXDLYUPDOWN_in = (TXDLYUPDOWN !== 1'bz) && TXDLYUPDOWN; // rv 0
assign TXLATCLK_in = (TXLATCLK !== 1'bz) && TXLATCLK; // rv 0
assign TXLFPSTRESET_in = (TXLFPSTRESET !== 1'bz) && TXLFPSTRESET; // rv 0
assign TXLFPSU2LPEXIT_in = (TXLFPSU2LPEXIT !== 1'bz) && TXLFPSU2LPEXIT; // rv 0
assign TXLFPSU3WAKE_in = (TXLFPSU3WAKE !== 1'bz) && TXLFPSU3WAKE; // rv 0
assign TXMAINCURSOR_in[0] = (TXMAINCURSOR[0] !== 1'bz) && TXMAINCURSOR[0]; // rv 0
assign TXMAINCURSOR_in[1] = (TXMAINCURSOR[1] !== 1'bz) && TXMAINCURSOR[1]; // rv 0
assign TXMAINCURSOR_in[2] = (TXMAINCURSOR[2] !== 1'bz) && TXMAINCURSOR[2]; // rv 0
assign TXMAINCURSOR_in[3] = (TXMAINCURSOR[3] !== 1'bz) && TXMAINCURSOR[3]; // rv 0
assign TXMAINCURSOR_in[4] = (TXMAINCURSOR[4] !== 1'bz) && TXMAINCURSOR[4]; // rv 0
assign TXMAINCURSOR_in[5] = (TXMAINCURSOR[5] !== 1'bz) && TXMAINCURSOR[5]; // rv 0
assign TXMAINCURSOR_in[6] = (TXMAINCURSOR[6] !== 1'bz) && TXMAINCURSOR[6]; // rv 0
assign TXMARGIN_in[0] = (TXMARGIN[0] !== 1'bz) && TXMARGIN[0]; // rv 0
assign TXMARGIN_in[1] = (TXMARGIN[1] !== 1'bz) && TXMARGIN[1]; // rv 0
assign TXMARGIN_in[2] = (TXMARGIN[2] !== 1'bz) && TXMARGIN[2]; // rv 0
assign TXMUXDCDEXHOLD_in = (TXMUXDCDEXHOLD !== 1'bz) && TXMUXDCDEXHOLD; // rv 0
assign TXMUXDCDORWREN_in = (TXMUXDCDORWREN !== 1'bz) && TXMUXDCDORWREN; // rv 0
assign TXONESZEROS_in = (TXONESZEROS !== 1'bz) && TXONESZEROS; // rv 0
assign TXOUTCLKSEL_in[0] = (TXOUTCLKSEL[0] !== 1'bz) && TXOUTCLKSEL[0]; // rv 0
assign TXOUTCLKSEL_in[1] = (TXOUTCLKSEL[1] !== 1'bz) && TXOUTCLKSEL[1]; // rv 0
assign TXOUTCLKSEL_in[2] = (TXOUTCLKSEL[2] !== 1'bz) && TXOUTCLKSEL[2]; // rv 0
assign TXPCSRESET_in = (TXPCSRESET !== 1'bz) && TXPCSRESET; // rv 0
assign TXPDELECIDLEMODE_in = (TXPDELECIDLEMODE !== 1'bz) && TXPDELECIDLEMODE; // rv 0
assign TXPHALIGNEN_in = (TXPHALIGNEN !== 1'bz) && TXPHALIGNEN; // rv 0
assign TXPHALIGN_in = (TXPHALIGN !== 1'bz) && TXPHALIGN; // rv 0
assign TXPHDLYPD_in = (TXPHDLYPD !== 1'bz) && TXPHDLYPD; // rv 0
assign TXPHDLYRESET_in = (TXPHDLYRESET !== 1'bz) && TXPHDLYRESET; // rv 0
assign TXPHDLYTSTCLK_in = (TXPHDLYTSTCLK !== 1'bz) && TXPHDLYTSTCLK; // rv 0
assign TXPHINIT_in = (TXPHINIT !== 1'bz) && TXPHINIT; // rv 0
assign TXPHOVRDEN_in = (TXPHOVRDEN !== 1'bz) && TXPHOVRDEN; // rv 0
assign TXPIPPMEN_in = (TXPIPPMEN !== 1'bz) && TXPIPPMEN; // rv 0
assign TXPIPPMOVRDEN_in = (TXPIPPMOVRDEN !== 1'bz) && TXPIPPMOVRDEN; // rv 0
assign TXPIPPMPD_in = (TXPIPPMPD !== 1'bz) && TXPIPPMPD; // rv 0
assign TXPIPPMSEL_in = (TXPIPPMSEL !== 1'bz) && TXPIPPMSEL; // rv 0
assign TXPIPPMSTEPSIZE_in[0] = (TXPIPPMSTEPSIZE[0] !== 1'bz) && TXPIPPMSTEPSIZE[0]; // rv 0
assign TXPIPPMSTEPSIZE_in[1] = (TXPIPPMSTEPSIZE[1] !== 1'bz) && TXPIPPMSTEPSIZE[1]; // rv 0
assign TXPIPPMSTEPSIZE_in[2] = (TXPIPPMSTEPSIZE[2] !== 1'bz) && TXPIPPMSTEPSIZE[2]; // rv 0
assign TXPIPPMSTEPSIZE_in[3] = (TXPIPPMSTEPSIZE[3] !== 1'bz) && TXPIPPMSTEPSIZE[3]; // rv 0
assign TXPIPPMSTEPSIZE_in[4] = (TXPIPPMSTEPSIZE[4] !== 1'bz) && TXPIPPMSTEPSIZE[4]; // rv 0
assign TXPISOPD_in = (TXPISOPD !== 1'bz) && TXPISOPD; // rv 0
assign TXPLLCLKSEL_in[0] = (TXPLLCLKSEL[0] !== 1'bz) && TXPLLCLKSEL[0]; // rv 0
assign TXPLLCLKSEL_in[1] = (TXPLLCLKSEL[1] !== 1'bz) && TXPLLCLKSEL[1]; // rv 0
assign TXPMARESET_in = (TXPMARESET !== 1'bz) && TXPMARESET; // rv 0
assign TXPOSTCURSOR_in[0] = (TXPOSTCURSOR[0] !== 1'bz) && TXPOSTCURSOR[0]; // rv 0
assign TXPOSTCURSOR_in[1] = (TXPOSTCURSOR[1] !== 1'bz) && TXPOSTCURSOR[1]; // rv 0
assign TXPOSTCURSOR_in[2] = (TXPOSTCURSOR[2] !== 1'bz) && TXPOSTCURSOR[2]; // rv 0
assign TXPOSTCURSOR_in[3] = (TXPOSTCURSOR[3] !== 1'bz) && TXPOSTCURSOR[3]; // rv 0
assign TXPOSTCURSOR_in[4] = (TXPOSTCURSOR[4] !== 1'bz) && TXPOSTCURSOR[4]; // rv 0
assign TXPRECURSOR_in[0] = (TXPRECURSOR[0] !== 1'bz) && TXPRECURSOR[0]; // rv 0
assign TXPRECURSOR_in[1] = (TXPRECURSOR[1] !== 1'bz) && TXPRECURSOR[1]; // rv 0
assign TXPRECURSOR_in[2] = (TXPRECURSOR[2] !== 1'bz) && TXPRECURSOR[2]; // rv 0
assign TXPRECURSOR_in[3] = (TXPRECURSOR[3] !== 1'bz) && TXPRECURSOR[3]; // rv 0
assign TXPRECURSOR_in[4] = (TXPRECURSOR[4] !== 1'bz) && TXPRECURSOR[4]; // rv 0
assign TXPROGDIVRESET_in = (TXPROGDIVRESET !== 1'bz) && TXPROGDIVRESET; // rv 0
assign TXRATEMODE_in = (TXRATEMODE !== 1'bz) && TXRATEMODE; // rv 0
assign TXSWING_in = (TXSWING !== 1'bz) && TXSWING; // rv 0
assign TXSYNCALLIN_in = (TXSYNCALLIN !== 1'bz) && TXSYNCALLIN; // rv 0
assign TXSYNCIN_in = (TXSYNCIN !== 1'bz) && TXSYNCIN; // rv 0
assign TXSYNCMODE_in = (TXSYNCMODE === 1'bz) || TXSYNCMODE; // rv 1
assign TXSYSCLKSEL_in[0] = (TXSYSCLKSEL[0] !== 1'bz) && TXSYSCLKSEL[0]; // rv 0
assign TXSYSCLKSEL_in[1] = (TXSYSCLKSEL[1] !== 1'bz) && TXSYSCLKSEL[1]; // rv 0
assign TXUSERRDY_in = (TXUSERRDY !== 1'bz) && TXUSERRDY; // rv 0
assign TXUSRCLK_in = (TXUSRCLK !== 1'bz) && TXUSRCLK; // rv 0
assign gt_intclk = gt_clk_int;
initial begin
#1;
trig_attr = ~trig_attr;
gt_clk_int = 1'b0;
forever #10000 gt_clk_int = ~gt_clk_int;
end
`ifdef XIL_XECLIB
assign RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
assign TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
`else
always @ (trig_attr) begin
#1;
RX_PROGDIV_CFG_BIN = RX_PROGDIV_CFG_REG * 1000;
TX_PROGDIV_CFG_BIN = TX_PROGDIV_CFG_REG * 1000;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_DOUBLE_REG != "FALSE") &&
(ALIGN_COMMA_DOUBLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-129] ALIGN_COMMA_DOUBLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ALIGN_COMMA_DOUBLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_COMMA_WORD_REG != 1) &&
(ALIGN_COMMA_WORD_REG != 2) &&
(ALIGN_COMMA_WORD_REG != 4))) begin
$display("Error: [Unisim %s-131] ALIGN_COMMA_WORD attribute is set to %d. Legal values for this attribute are 1, 2 or 4. Instance: %m", MODULE_NAME, ALIGN_COMMA_WORD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_MCOMMA_DET_REG != "TRUE") &&
(ALIGN_MCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-132] ALIGN_MCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_MCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ALIGN_PCOMMA_DET_REG != "TRUE") &&
(ALIGN_PCOMMA_DET_REG != "FALSE"))) begin
$display("Error: [Unisim %s-134] ALIGN_PCOMMA_DET attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, ALIGN_PCOMMA_DET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CBCC_DATA_SOURCE_SEL_REG != "DECODED") &&
(CBCC_DATA_SOURCE_SEL_REG != "ENCODED"))) begin
$display("Error: [Unisim %s-268] CBCC_DATA_SOURCE_SEL attribute is set to %s. Legal values for this attribute are DECODED or ENCODED. Instance: %m", MODULE_NAME, CBCC_DATA_SOURCE_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_KEEP_ALIGN_REG != "FALSE") &&
(CHAN_BOND_KEEP_ALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-271] CHAN_BOND_KEEP_ALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_KEEP_ALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_MAX_SKEW_REG != 7) &&
(CHAN_BOND_MAX_SKEW_REG != 1) &&
(CHAN_BOND_MAX_SKEW_REG != 2) &&
(CHAN_BOND_MAX_SKEW_REG != 3) &&
(CHAN_BOND_MAX_SKEW_REG != 4) &&
(CHAN_BOND_MAX_SKEW_REG != 5) &&
(CHAN_BOND_MAX_SKEW_REG != 6) &&
(CHAN_BOND_MAX_SKEW_REG != 8) &&
(CHAN_BOND_MAX_SKEW_REG != 9) &&
(CHAN_BOND_MAX_SKEW_REG != 10) &&
(CHAN_BOND_MAX_SKEW_REG != 11) &&
(CHAN_BOND_MAX_SKEW_REG != 12) &&
(CHAN_BOND_MAX_SKEW_REG != 13) &&
(CHAN_BOND_MAX_SKEW_REG != 14))) begin
$display("Error: [Unisim %s-272] CHAN_BOND_MAX_SKEW attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13 or 14. Instance: %m", MODULE_NAME, CHAN_BOND_MAX_SKEW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_2_USE_REG != "FALSE") &&
(CHAN_BOND_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-283] CHAN_BOND_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CHAN_BOND_SEQ_LEN_REG != 2) &&
(CHAN_BOND_SEQ_LEN_REG != 1) &&
(CHAN_BOND_SEQ_LEN_REG != 3) &&
(CHAN_BOND_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-284] CHAN_BOND_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CHAN_BOND_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_CORRECT_USE_REG != "TRUE") &&
(CLK_CORRECT_USE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-295] CLK_CORRECT_USE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_CORRECT_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_KEEP_IDLE_REG != "FALSE") &&
(CLK_COR_KEEP_IDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-296] CLK_COR_KEEP_IDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_KEEP_IDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MAX_LAT_REG < 3) || (CLK_COR_MAX_LAT_REG > 60))) begin
$display("Error: [Unisim %s-297] CLK_COR_MAX_LAT attribute is set to %d. Legal values for this attribute are 3 to 60. Instance: %m", MODULE_NAME, CLK_COR_MAX_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_MIN_LAT_REG < 3) || (CLK_COR_MIN_LAT_REG > 63))) begin
$display("Error: [Unisim %s-298] CLK_COR_MIN_LAT attribute is set to %d. Legal values for this attribute are 3 to 63. Instance: %m", MODULE_NAME, CLK_COR_MIN_LAT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_PRECEDENCE_REG != "TRUE") &&
(CLK_COR_PRECEDENCE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-299] CLK_COR_PRECEDENCE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, CLK_COR_PRECEDENCE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_REPEAT_WAIT_REG < 0) || (CLK_COR_REPEAT_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-300] CLK_COR_REPEAT_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, CLK_COR_REPEAT_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_2_USE_REG != "FALSE") &&
(CLK_COR_SEQ_2_USE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-311] CLK_COR_SEQ_2_USE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, CLK_COR_SEQ_2_USE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CLK_COR_SEQ_LEN_REG != 2) &&
(CLK_COR_SEQ_LEN_REG != 1) &&
(CLK_COR_SEQ_LEN_REG != 3) &&
(CLK_COR_SEQ_LEN_REG != 4))) begin
$display("Error: [Unisim %s-312] CLK_COR_SEQ_LEN attribute is set to %d. Legal values for this attribute are 2, 1, 3 or 4. Instance: %m", MODULE_NAME, CLK_COR_SEQ_LEN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_REG != 4) &&
(CPLL_FBDIV_REG != 1) &&
(CPLL_FBDIV_REG != 2) &&
(CPLL_FBDIV_REG != 3) &&
(CPLL_FBDIV_REG != 5) &&
(CPLL_FBDIV_REG != 6) &&
(CPLL_FBDIV_REG != 8) &&
(CPLL_FBDIV_REG != 10) &&
(CPLL_FBDIV_REG != 12) &&
(CPLL_FBDIV_REG != 16) &&
(CPLL_FBDIV_REG != 20))) begin
$display("Error: [Unisim %s-317] CPLL_FBDIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 3, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_FBDIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_FBDIV_45_REG != 4) &&
(CPLL_FBDIV_45_REG != 5))) begin
$display("Error: [Unisim %s-318] CPLL_FBDIV_45 attribute is set to %d. Legal values for this attribute are 4 or 5. Instance: %m", MODULE_NAME, CPLL_FBDIV_45_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((CPLL_REFCLK_DIV_REG != 1) &&
(CPLL_REFCLK_DIV_REG != 2) &&
(CPLL_REFCLK_DIV_REG != 3) &&
(CPLL_REFCLK_DIV_REG != 4) &&
(CPLL_REFCLK_DIV_REG != 5) &&
(CPLL_REFCLK_DIV_REG != 6) &&
(CPLL_REFCLK_DIV_REG != 8) &&
(CPLL_REFCLK_DIV_REG != 10) &&
(CPLL_REFCLK_DIV_REG != 12) &&
(CPLL_REFCLK_DIV_REG != 16) &&
(CPLL_REFCLK_DIV_REG != 20))) begin
$display("Error: [Unisim %s-321] CPLL_REFCLK_DIV attribute is set to %d. Legal values for this attribute are 1, 2, 3, 4, 5, 6, 8, 10, 12, 16 or 20. Instance: %m", MODULE_NAME, CPLL_REFCLK_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DDI_REALIGN_WAIT_REG < 0) || (DDI_REALIGN_WAIT_REG > 31))) begin
$display("Error: [Unisim %s-338] DDI_REALIGN_WAIT attribute is set to %d. Legal values for this attribute are 0 to 31. Instance: %m", MODULE_NAME, DDI_REALIGN_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_MCOMMA_DETECT_REG != "TRUE") &&
(DEC_MCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-339] DEC_MCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_MCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_PCOMMA_DETECT_REG != "TRUE") &&
(DEC_PCOMMA_DETECT_REG != "FALSE"))) begin
$display("Error: [Unisim %s-340] DEC_PCOMMA_DETECT attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_PCOMMA_DETECT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((DEC_VALID_COMMA_ONLY_REG != "TRUE") &&
(DEC_VALID_COMMA_ONLY_REG != "FALSE"))) begin
$display("Error: [Unisim %s-341] DEC_VALID_COMMA_ONLY attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, DEC_VALID_COMMA_ONLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_ERRDET_EN_REG != "FALSE") &&
(ES_ERRDET_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-347] ES_ERRDET_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_ERRDET_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((ES_EYE_SCAN_EN_REG != "FALSE") &&
(ES_EYE_SCAN_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-348] ES_EYE_SCAN_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, ES_EYE_SCAN_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((EYESCAN_VP_RANGE_REG != 0) &&
(EYESCAN_VP_RANGE_REG != 1) &&
(EYESCAN_VP_RANGE_REG != 2) &&
(EYESCAN_VP_RANGE_REG != 3))) begin
$display("Error: [Unisim %s-381] EYESCAN_VP_RANGE attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, EYESCAN_VP_RANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((FTS_LANE_DESKEW_EN_REG != "FALSE") &&
(FTS_LANE_DESKEW_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-385] FTS_LANE_DESKEW_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, FTS_LANE_DESKEW_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_BIAS_CTRL_REG != 4) &&
(LPBK_BIAS_CTRL_REG != 0) &&
(LPBK_BIAS_CTRL_REG != 1) &&
(LPBK_BIAS_CTRL_REG != 2) &&
(LPBK_BIAS_CTRL_REG != 3) &&
(LPBK_BIAS_CTRL_REG != 5) &&
(LPBK_BIAS_CTRL_REG != 6) &&
(LPBK_BIAS_CTRL_REG != 7))) begin
$display("Error: [Unisim %s-394] LPBK_BIAS_CTRL attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, LPBK_BIAS_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_IND_CTRL0_REG != 5) &&
(LPBK_IND_CTRL0_REG != 0) &&
(LPBK_IND_CTRL0_REG != 1) &&
(LPBK_IND_CTRL0_REG != 2) &&
(LPBK_IND_CTRL0_REG != 3) &&
(LPBK_IND_CTRL0_REG != 4) &&
(LPBK_IND_CTRL0_REG != 6) &&
(LPBK_IND_CTRL0_REG != 7))) begin
$display("Error: [Unisim %s-397] LPBK_IND_CTRL0 attribute is set to %d. Legal values for this attribute are 5, 0, 1, 2, 3, 4, 6 or 7. Instance: %m", MODULE_NAME, LPBK_IND_CTRL0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_IND_CTRL1_REG != 5) &&
(LPBK_IND_CTRL1_REG != 0) &&
(LPBK_IND_CTRL1_REG != 1) &&
(LPBK_IND_CTRL1_REG != 2) &&
(LPBK_IND_CTRL1_REG != 3) &&
(LPBK_IND_CTRL1_REG != 4) &&
(LPBK_IND_CTRL1_REG != 6) &&
(LPBK_IND_CTRL1_REG != 7))) begin
$display("Error: [Unisim %s-398] LPBK_IND_CTRL1 attribute is set to %d. Legal values for this attribute are 5, 0, 1, 2, 3, 4, 6 or 7. Instance: %m", MODULE_NAME, LPBK_IND_CTRL1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_IND_CTRL2_REG != 5) &&
(LPBK_IND_CTRL2_REG != 0) &&
(LPBK_IND_CTRL2_REG != 1) &&
(LPBK_IND_CTRL2_REG != 2) &&
(LPBK_IND_CTRL2_REG != 3) &&
(LPBK_IND_CTRL2_REG != 4) &&
(LPBK_IND_CTRL2_REG != 6) &&
(LPBK_IND_CTRL2_REG != 7))) begin
$display("Error: [Unisim %s-399] LPBK_IND_CTRL2 attribute is set to %d. Legal values for this attribute are 5, 0, 1, 2, 3, 4, 6 or 7. Instance: %m", MODULE_NAME, LPBK_IND_CTRL2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((LPBK_RG_CTRL_REG != 2) &&
(LPBK_RG_CTRL_REG != 0) &&
(LPBK_RG_CTRL_REG != 1) &&
(LPBK_RG_CTRL_REG != 3))) begin
$display("Error: [Unisim %s-400] LPBK_RG_CTRL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, LPBK_RG_CTRL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCI3_AUTO_REALIGN_REG != "FRST_SMPL") &&
(PCI3_AUTO_REALIGN_REG != "OVR_1K_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_8_BLK") &&
(PCI3_AUTO_REALIGN_REG != "OVR_64_BLK"))) begin
$display("Error: [Unisim %s-403] PCI3_AUTO_REALIGN attribute is set to %s. Legal values for this attribute are FRST_SMPL, OVR_1K_BLK, OVR_8_BLK or OVR_64_BLK. Instance: %m", MODULE_NAME, PCI3_AUTO_REALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_64B_DYN_CLKSW_DIS_REG != "FALSE") &&
(PCIE_64B_DYN_CLKSW_DIS_REG != "TRUE"))) begin
$display("Error: [Unisim %s-417] PCIE_64B_DYN_CLKSW_DIS attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCIE_64B_DYN_CLKSW_DIS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCIE_GEN4_64BIT_INT_EN_REG != "FALSE") &&
(PCIE_GEN4_64BIT_INT_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-419] PCIE_GEN4_64BIT_INT_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCIE_GEN4_64BIT_INT_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PCS_PCIE_EN_REG != "FALSE") &&
(PCS_PCIE_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-427] PCS_PCIE_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, PCS_PCIE_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((PREIQ_FREQ_BST_REG != 0) &&
(PREIQ_FREQ_BST_REG != 1) &&
(PREIQ_FREQ_BST_REG != 2) &&
(PREIQ_FREQ_BST_REG != 3))) begin
$display("Error: [Unisim %s-432] PREIQ_FREQ_BST attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, PREIQ_FREQ_BST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_ADDR_MODE_REG != "FULL") &&
(RXBUF_ADDR_MODE_REG != "FAST"))) begin
$display("Error: [Unisim %s-439] RXBUF_ADDR_MODE attribute is set to %s. Legal values for this attribute are FULL or FAST. Instance: %m", MODULE_NAME, RXBUF_ADDR_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_EN_REG != "TRUE") &&
(RXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-442] RXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_CB_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_CB_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-443] RXBUF_RESET_ON_CB_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_CB_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_COMMAALIGN_REG != "FALSE") &&
(RXBUF_RESET_ON_COMMAALIGN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-444] RXBUF_RESET_ON_COMMAALIGN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_COMMAALIGN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_EIDLE_REG != "FALSE") &&
(RXBUF_RESET_ON_EIDLE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-445] RXBUF_RESET_ON_EIDLE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_EIDLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE") &&
(RXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE"))) begin
$display("Error: [Unisim %s-446] RXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVFLW_REG < 0) || (RXBUF_THRESH_OVFLW_REG > 63))) begin
$display("Error: [Unisim %s-447] RXBUF_THRESH_OVFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_OVRD_REG != "FALSE") &&
(RXBUF_THRESH_OVRD_REG != "TRUE"))) begin
$display("Error: [Unisim %s-448] RXBUF_THRESH_OVRD attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXBUF_THRESH_OVRD_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXBUF_THRESH_UNDFLW_REG < 0) || (RXBUF_THRESH_UNDFLW_REG > 63))) begin
$display("Error: [Unisim %s-449] RXBUF_THRESH_UNDFLW attribute is set to %d. Legal values for this attribute are 0 to 63. Instance: %m", MODULE_NAME, RXBUF_THRESH_UNDFLW_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXELECIDLE_CFG_REG != "SIGCFG_4") &&
(RXELECIDLE_CFG_REG != "SIGCFG_1") &&
(RXELECIDLE_CFG_REG != "SIGCFG_2") &&
(RXELECIDLE_CFG_REG != "SIGCFG_3") &&
(RXELECIDLE_CFG_REG != "SIGCFG_6") &&
(RXELECIDLE_CFG_REG != "SIGCFG_8") &&
(RXELECIDLE_CFG_REG != "SIGCFG_12") &&
(RXELECIDLE_CFG_REG != "SIGCFG_16"))) begin
$display("Error: [Unisim %s-536] RXELECIDLE_CFG attribute is set to %s. Legal values for this attribute are SIGCFG_4, SIGCFG_1, SIGCFG_2, SIGCFG_3, SIGCFG_6, SIGCFG_8, SIGCFG_12 or SIGCFG_16. Instance: %m", MODULE_NAME, RXELECIDLE_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(RXGBOX_FIFO_INIT_RD_ADDR_REG != 5))) begin
$display("Error: [Unisim %s-537] RXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3 or 5. Instance: %m", MODULE_NAME, RXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXGEARBOX_EN_REG != "FALSE") &&
(RXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-538] RXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, RXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOOB_CLK_CFG_REG != "PMA") &&
(RXOOB_CLK_CFG_REG != "FABRIC"))) begin
$display("Error: [Unisim %s-547] RXOOB_CLK_CFG attribute is set to %s. Legal values for this attribute are PMA or FABRIC. Instance: %m", MODULE_NAME, RXOOB_CLK_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXOUT_DIV_REG != 4) &&
(RXOUT_DIV_REG != 1) &&
(RXOUT_DIV_REG != 2) &&
(RXOUT_DIV_REG != 8) &&
(RXOUT_DIV_REG != 16) &&
(RXOUT_DIV_REG != 32))) begin
$display("Error: [Unisim %s-549] RXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, RXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPMACLK_SEL_REG != "DATA") &&
(RXPMACLK_SEL_REG != "CROSSING") &&
(RXPMACLK_SEL_REG != "EYESCAN"))) begin
$display("Error: [Unisim %s-558] RXPMACLK_SEL attribute is set to %s. Legal values for this attribute are DATA, CROSSING or EYESCAN. Instance: %m", MODULE_NAME, RXPMACLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXPRBS_LINKACQ_CNT_REG < 15) || (RXPRBS_LINKACQ_CNT_REG > 255))) begin
$display("Error: [Unisim %s-561] RXPRBS_LINKACQ_CNT attribute is set to %d. Legal values for this attribute are 15 to 255. Instance: %m", MODULE_NAME, RXPRBS_LINKACQ_CNT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_AUTO_WAIT_REG != 7) &&
(RXSLIDE_AUTO_WAIT_REG != 1) &&
(RXSLIDE_AUTO_WAIT_REG != 2) &&
(RXSLIDE_AUTO_WAIT_REG != 3) &&
(RXSLIDE_AUTO_WAIT_REG != 4) &&
(RXSLIDE_AUTO_WAIT_REG != 5) &&
(RXSLIDE_AUTO_WAIT_REG != 6) &&
(RXSLIDE_AUTO_WAIT_REG != 8) &&
(RXSLIDE_AUTO_WAIT_REG != 9) &&
(RXSLIDE_AUTO_WAIT_REG != 10) &&
(RXSLIDE_AUTO_WAIT_REG != 11) &&
(RXSLIDE_AUTO_WAIT_REG != 12) &&
(RXSLIDE_AUTO_WAIT_REG != 13) &&
(RXSLIDE_AUTO_WAIT_REG != 14) &&
(RXSLIDE_AUTO_WAIT_REG != 15))) begin
$display("Error: [Unisim %s-563] RXSLIDE_AUTO_WAIT attribute is set to %d. Legal values for this attribute are 7, 1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RXSLIDE_AUTO_WAIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RXSLIDE_MODE_REG != "OFF") &&
(RXSLIDE_MODE_REG != "AUTO") &&
(RXSLIDE_MODE_REG != "PCS") &&
(RXSLIDE_MODE_REG != "PMA"))) begin
$display("Error: [Unisim %s-564] RXSLIDE_MODE attribute is set to %s. Legal values for this attribute are OFF, AUTO, PCS or PMA. Instance: %m", MODULE_NAME, RXSLIDE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CLK25_DIV_REG < 1) || (RX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-572] RX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_SEL_REG != 2) &&
(RX_CM_SEL_REG != 0) &&
(RX_CM_SEL_REG != 1) &&
(RX_CM_SEL_REG != 3))) begin
$display("Error: [Unisim %s-577] RX_CM_SEL attribute is set to %d. Legal values for this attribute are 2, 0, 1 or 3. Instance: %m", MODULE_NAME, RX_CM_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_CM_TRIM_REG != 12) &&
(RX_CM_TRIM_REG != 0) &&
(RX_CM_TRIM_REG != 1) &&
(RX_CM_TRIM_REG != 2) &&
(RX_CM_TRIM_REG != 3) &&
(RX_CM_TRIM_REG != 4) &&
(RX_CM_TRIM_REG != 5) &&
(RX_CM_TRIM_REG != 6) &&
(RX_CM_TRIM_REG != 7) &&
(RX_CM_TRIM_REG != 8) &&
(RX_CM_TRIM_REG != 9) &&
(RX_CM_TRIM_REG != 10) &&
(RX_CM_TRIM_REG != 11) &&
(RX_CM_TRIM_REG != 13) &&
(RX_CM_TRIM_REG != 14) &&
(RX_CM_TRIM_REG != 15))) begin
$display("Error: [Unisim %s-578] RX_CM_TRIM attribute is set to %d. Legal values for this attribute are 12, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_CM_TRIM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DATA_WIDTH_REG != 20) &&
(RX_DATA_WIDTH_REG != 16) &&
(RX_DATA_WIDTH_REG != 32) &&
(RX_DATA_WIDTH_REG != 40) &&
(RX_DATA_WIDTH_REG != 64) &&
(RX_DATA_WIDTH_REG != 80) &&
(RX_DATA_WIDTH_REG != 128) &&
(RX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-581] RX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, RX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DEFER_RESET_BUF_EN_REG != "TRUE") &&
(RX_DEFER_RESET_BUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-583] RX_DEFER_RESET_BUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DEFER_RESET_BUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFELPM_CFG0_REG != 10) &&
(RX_DFELPM_CFG0_REG != 0) &&
(RX_DFELPM_CFG0_REG != 1) &&
(RX_DFELPM_CFG0_REG != 11) &&
(RX_DFELPM_CFG0_REG != 12) &&
(RX_DFELPM_CFG0_REG != 13) &&
(RX_DFELPM_CFG0_REG != 14) &&
(RX_DFELPM_CFG0_REG != 15))) begin
$display("Error: [Unisim %s-586] RX_DFELPM_CFG0 attribute is set to %d. Legal values for this attribute are 10, 0, 1, 11, 12, 13, 14 or 15. Instance: %m", MODULE_NAME, RX_DFELPM_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_AGC_CFG1_REG != 4) &&
(RX_DFE_AGC_CFG1_REG != 0) &&
(RX_DFE_AGC_CFG1_REG != 1) &&
(RX_DFE_AGC_CFG1_REG != 2) &&
(RX_DFE_AGC_CFG1_REG != 3) &&
(RX_DFE_AGC_CFG1_REG != 5) &&
(RX_DFE_AGC_CFG1_REG != 6) &&
(RX_DFE_AGC_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-589] RX_DFE_AGC_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_AGC_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG0_REG != 1) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 0) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 2) &&
(RX_DFE_KL_LPM_KH_CFG0_REG != 3))) begin
$display("Error: [Unisim %s-590] RX_DFE_KL_LPM_KH_CFG0 attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KH_CFG1_REG != 2) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 0) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 1) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 3) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 4) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 5) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 6) &&
(RX_DFE_KL_LPM_KH_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-591] RX_DFE_KL_LPM_KH_CFG1 attribute is set to %d. Legal values for this attribute are 2, 0, 1, 3, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KH_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DFE_KL_LPM_KL_CFG1_REG != 4) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 0) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 1) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 2) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 3) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 5) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 6) &&
(RX_DFE_KL_LPM_KL_CFG1_REG != 7))) begin
$display("Error: [Unisim %s-593] RX_DFE_KL_LPM_KL_CFG1 attribute is set to %d. Legal values for this attribute are 4, 0, 1, 2, 3, 5, 6 or 7. Instance: %m", MODULE_NAME, RX_DFE_KL_LPM_KL_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_DISPERR_SEQ_MATCH_REG != "TRUE") &&
(RX_DISPERR_SEQ_MATCH_REG != "FALSE"))) begin
$display("Error: [Unisim %s-595] RX_DISPERR_SEQ_MATCH attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, RX_DISPERR_SEQ_MATCH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_EN_SUM_RCAL_B_REG != 0) &&
(RX_EN_SUM_RCAL_B_REG != 1))) begin
$display("Error: [Unisim %s-598] RX_EN_SUM_RCAL_B attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, RX_EN_SUM_RCAL_B_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_INT_DATAWIDTH_REG != 1) &&
(RX_INT_DATAWIDTH_REG != 0) &&
(RX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-605] RX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, RX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_PROGDIV_CFG_REG != 0.0) &&
(RX_PROGDIV_CFG_REG != 4.0) &&
(RX_PROGDIV_CFG_REG != 5.0) &&
(RX_PROGDIV_CFG_REG != 8.0) &&
(RX_PROGDIV_CFG_REG != 10.0) &&
(RX_PROGDIV_CFG_REG != 16.0) &&
(RX_PROGDIV_CFG_REG != 16.5) &&
(RX_PROGDIV_CFG_REG != 20.0) &&
(RX_PROGDIV_CFG_REG != 32.0) &&
(RX_PROGDIV_CFG_REG != 33.0) &&
(RX_PROGDIV_CFG_REG != 40.0) &&
(RX_PROGDIV_CFG_REG != 64.0) &&
(RX_PROGDIV_CFG_REG != 66.0) &&
(RX_PROGDIV_CFG_REG != 80.0) &&
(RX_PROGDIV_CFG_REG != 100.0) &&
(RX_PROGDIV_CFG_REG != 128.0) &&
(RX_PROGDIV_CFG_REG != 132.0))) begin
$display("Error: [Unisim %s-608] RX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, RX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SIG_VALID_DLY_REG < 1) || (RX_SIG_VALID_DLY_REG > 32))) begin
$display("Error: [Unisim %s-613] RX_SIG_VALID_DLY attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, RX_SIG_VALID_DLY_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_DEGEN_AVTT_OVERITE_REG != 0) &&
(RX_SUM_DEGEN_AVTT_OVERITE_REG != 1))) begin
$display("Error: [Unisim %s-614] RX_SUM_DEGEN_AVTT_OVERITE attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, RX_SUM_DEGEN_AVTT_OVERITE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_SUM_PWR_SAVING_REG != 0) &&
(RX_SUM_PWR_SAVING_REG != 1))) begin
$display("Error: [Unisim %s-617] RX_SUM_PWR_SAVING attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, RX_SUM_PWR_SAVING_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((RX_XCLK_SEL_REG != "RXDES") &&
(RX_XCLK_SEL_REG != "RXPMA") &&
(RX_XCLK_SEL_REG != "RXUSR"))) begin
$display("Error: [Unisim %s-630] RX_XCLK_SEL attribute is set to %s. Legal values for this attribute are RXDES, RXPMA or RXUSR. Instance: %m", MODULE_NAME, RX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SATA_CPLL_CFG_REG != "VCO_3000MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_750MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_1500MHZ") &&
(SATA_CPLL_CFG_REG != "VCO_6000MHZ"))) begin
$display("Error: [Unisim %s-636] SATA_CPLL_CFG attribute is set to %s. Legal values for this attribute are VCO_3000MHZ, VCO_750MHZ, VCO_1500MHZ or VCO_6000MHZ. Instance: %m", MODULE_NAME, SATA_CPLL_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SHOW_REALIGN_COMMA_REG != "TRUE") &&
(SHOW_REALIGN_COMMA_REG != "FALSE"))) begin
$display("Error: [Unisim %s-638] SHOW_REALIGN_COMMA attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SHOW_REALIGN_COMMA_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1p") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-639] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES1p or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_MODE_REG != "FAST") &&
(SIM_MODE_REG != "LEGACY"))) begin
$display("Error: [Unisim %s-640] SIM_MODE attribute is set to %s. Legal values for this attribute are FAST or LEGACY. Instance: %m", MODULE_NAME, SIM_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RECEIVER_DETECT_PASS_REG != "TRUE") &&
(SIM_RECEIVER_DETECT_PASS_REG != "FALSE"))) begin
$display("Error: [Unisim %s-641] SIM_RECEIVER_DETECT_PASS attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RECEIVER_DETECT_PASS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_RESET_SPEEDUP_REG != "TRUE") &&
(SIM_RESET_SPEEDUP_REG != "FALSE"))) begin
$display("Error: [Unisim %s-642] SIM_RESET_SPEEDUP attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, SIM_RESET_SPEEDUP_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_TX_EIDLE_DRIVE_LEVEL_REG != "Z") &&
(SIM_TX_EIDLE_DRIVE_LEVEL_REG != "HIGH") &&
(SIM_TX_EIDLE_DRIVE_LEVEL_REG != "LOW") &&
(SIM_TX_EIDLE_DRIVE_LEVEL_REG != "X"))) begin
$display("Error: [Unisim %s-643] SIM_TX_EIDLE_DRIVE_LEVEL attribute is set to %s. Legal values for this attribute are Z, HIGH, LOW or X. Instance: %m", MODULE_NAME, SIM_TX_EIDLE_DRIVE_LEVEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_EN_REG != "TRUE") &&
(TXBUF_EN_REG != "FALSE"))) begin
$display("Error: [Unisim %s-651] TXBUF_EN attribute is set to %s. Legal values for this attribute are TRUE or FALSE. Instance: %m", MODULE_NAME, TXBUF_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXBUF_RESET_ON_RATE_CHANGE_REG != "FALSE") &&
(TXBUF_RESET_ON_RATE_CHANGE_REG != "TRUE"))) begin
$display("Error: [Unisim %s-652] TXBUF_RESET_ON_RATE_CHANGE attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXBUF_RESET_ON_RATE_CHANGE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXDRV_FREQBAND_REG != 0) &&
(TXDRV_FREQBAND_REG != 1) &&
(TXDRV_FREQBAND_REG != 2) &&
(TXDRV_FREQBAND_REG != 3))) begin
$display("Error: [Unisim %s-655] TXDRV_FREQBAND attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TXDRV_FREQBAND_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXFIFO_ADDR_CFG_REG != "LOW") &&
(TXFIFO_ADDR_CFG_REG != "HIGH"))) begin
$display("Error: [Unisim %s-660] TXFIFO_ADDR_CFG attribute is set to %s. Legal values for this attribute are LOW or HIGH. Instance: %m", MODULE_NAME, TXFIFO_ADDR_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGBOX_FIFO_INIT_RD_ADDR_REG != 4) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 2) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 3) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 5) &&
(TXGBOX_FIFO_INIT_RD_ADDR_REG != 6))) begin
$display("Error: [Unisim %s-661] TXGBOX_FIFO_INIT_RD_ADDR attribute is set to %d. Legal values for this attribute are 4, 2, 3, 5 or 6. Instance: %m", MODULE_NAME, TXGBOX_FIFO_INIT_RD_ADDR_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXGEARBOX_EN_REG != "FALSE") &&
(TXGEARBOX_EN_REG != "TRUE"))) begin
$display("Error: [Unisim %s-662] TXGEARBOX_EN attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TXGEARBOX_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXOUT_DIV_REG != 4) &&
(TXOUT_DIV_REG != 1) &&
(TXOUT_DIV_REG != 2) &&
(TXOUT_DIV_REG != 8) &&
(TXOUT_DIV_REG != 16) &&
(TXOUT_DIV_REG != 32))) begin
$display("Error: [Unisim %s-664] TXOUT_DIV attribute is set to %d. Legal values for this attribute are 4, 1, 2, 8, 16 or 32. Instance: %m", MODULE_NAME, TXOUT_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSWBST_BST_REG != 1) &&
(TXSWBST_BST_REG != 0) &&
(TXSWBST_BST_REG != 2) &&
(TXSWBST_BST_REG != 3))) begin
$display("Error: [Unisim %s-680] TXSWBST_BST attribute is set to %d. Legal values for this attribute are 1, 0, 2 or 3. Instance: %m", MODULE_NAME, TXSWBST_BST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSWBST_EN_REG != 0) &&
(TXSWBST_EN_REG != 1))) begin
$display("Error: [Unisim %s-681] TXSWBST_EN attribute is set to %d. Legal values for this attribute are 0 or 1. Instance: %m", MODULE_NAME, TXSWBST_EN_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TXSWBST_MAG_REG != 6) &&
(TXSWBST_MAG_REG != 0) &&
(TXSWBST_MAG_REG != 1) &&
(TXSWBST_MAG_REG != 2) &&
(TXSWBST_MAG_REG != 3) &&
(TXSWBST_MAG_REG != 4) &&
(TXSWBST_MAG_REG != 5) &&
(TXSWBST_MAG_REG != 7))) begin
$display("Error: [Unisim %s-682] TXSWBST_MAG attribute is set to %d. Legal values for this attribute are 6, 0, 1, 2, 3, 4, 5 or 7. Instance: %m", MODULE_NAME, TXSWBST_MAG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_CLK25_DIV_REG < 1) || (TX_CLK25_DIV_REG > 32))) begin
$display("Error: [Unisim %s-686] TX_CLK25_DIV attribute is set to %d. Legal values for this attribute are 1 to 32. Instance: %m", MODULE_NAME, TX_CLK25_DIV_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DATA_WIDTH_REG != 20) &&
(TX_DATA_WIDTH_REG != 16) &&
(TX_DATA_WIDTH_REG != 32) &&
(TX_DATA_WIDTH_REG != 40) &&
(TX_DATA_WIDTH_REG != 64) &&
(TX_DATA_WIDTH_REG != 80) &&
(TX_DATA_WIDTH_REG != 128) &&
(TX_DATA_WIDTH_REG != 160))) begin
$display("Error: [Unisim %s-688] TX_DATA_WIDTH attribute is set to %d. Legal values for this attribute are 20, 16, 32, 40, 64, 80, 128 or 160. Instance: %m", MODULE_NAME, TX_DATA_WIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_DRIVE_MODE_REG != "DIRECT") &&
(TX_DRIVE_MODE_REG != "PIPE") &&
(TX_DRIVE_MODE_REG != "PIPEGEN3"))) begin
$display("Error: [Unisim %s-695] TX_DRIVE_MODE attribute is set to %s. Legal values for this attribute are DIRECT, PIPE or PIPEGEN3. Instance: %m", MODULE_NAME, TX_DRIVE_MODE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_INT_DATAWIDTH_REG != 1) &&
(TX_INT_DATAWIDTH_REG != 0) &&
(TX_INT_DATAWIDTH_REG != 2))) begin
$display("Error: [Unisim %s-701] TX_INT_DATAWIDTH attribute is set to %d. Legal values for this attribute are 1, 0 or 2. Instance: %m", MODULE_NAME, TX_INT_DATAWIDTH_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_LOOPBACK_DRIVE_HIZ_REG != "FALSE") &&
(TX_LOOPBACK_DRIVE_HIZ_REG != "TRUE"))) begin
$display("Error: [Unisim %s-702] TX_LOOPBACK_DRIVE_HIZ attribute is set to %s. Legal values for this attribute are FALSE or TRUE. Instance: %m", MODULE_NAME, TX_LOOPBACK_DRIVE_HIZ_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PI_BIASSET_REG != 0) &&
(TX_PI_BIASSET_REG != 1) &&
(TX_PI_BIASSET_REG != 2) &&
(TX_PI_BIASSET_REG != 3))) begin
$display("Error: [Unisim %s-716] TX_PI_BIASSET attribute is set to %d. Legal values for this attribute are 0, 1, 2 or 3. Instance: %m", MODULE_NAME, TX_PI_BIASSET_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGCLK_SEL_REG != "POSTPI") &&
(TX_PROGCLK_SEL_REG != "CPLL") &&
(TX_PROGCLK_SEL_REG != "PREPI"))) begin
$display("Error: [Unisim %s-721] TX_PROGCLK_SEL attribute is set to %s. Legal values for this attribute are POSTPI, CPLL or PREPI. Instance: %m", MODULE_NAME, TX_PROGCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_PROGDIV_CFG_REG != 0.0) &&
(TX_PROGDIV_CFG_REG != 4.0) &&
(TX_PROGDIV_CFG_REG != 5.0) &&
(TX_PROGDIV_CFG_REG != 8.0) &&
(TX_PROGDIV_CFG_REG != 10.0) &&
(TX_PROGDIV_CFG_REG != 16.0) &&
(TX_PROGDIV_CFG_REG != 16.5) &&
(TX_PROGDIV_CFG_REG != 20.0) &&
(TX_PROGDIV_CFG_REG != 32.0) &&
(TX_PROGDIV_CFG_REG != 33.0) &&
(TX_PROGDIV_CFG_REG != 40.0) &&
(TX_PROGDIV_CFG_REG != 64.0) &&
(TX_PROGDIV_CFG_REG != 66.0) &&
(TX_PROGDIV_CFG_REG != 80.0) &&
(TX_PROGDIV_CFG_REG != 100.0) &&
(TX_PROGDIV_CFG_REG != 128.0) &&
(TX_PROGDIV_CFG_REG != 132.0))) begin
$display("Error: [Unisim %s-722] TX_PROGDIV_CFG attribute is set to %f. Legal values for this attribute are 0.0, 4.0, 5.0, 8.0, 10.0, 16.0, 16.5, 20.0, 32.0, 33.0, 40.0, 64.0, 66.0, 80.0, 100.0, 128.0 or 132.0. Instance: %m", MODULE_NAME, TX_PROGDIV_CFG_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_RXDETECT_REF_REG != 3) &&
(TX_RXDETECT_REF_REG != 0) &&
(TX_RXDETECT_REF_REG != 1) &&
(TX_RXDETECT_REF_REG != 2) &&
(TX_RXDETECT_REF_REG != 4) &&
(TX_RXDETECT_REF_REG != 5) &&
(TX_RXDETECT_REF_REG != 6) &&
(TX_RXDETECT_REF_REG != 7))) begin
$display("Error: [Unisim %s-725] TX_RXDETECT_REF attribute is set to %d. Legal values for this attribute are 3, 0, 1, 2, 4, 5, 6 or 7. Instance: %m", MODULE_NAME, TX_RXDETECT_REF_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((TX_XCLK_SEL_REG != "TXOUT") &&
(TX_XCLK_SEL_REG != "TXUSR"))) begin
$display("Error: [Unisim %s-739] TX_XCLK_SEL attribute is set to %s. Legal values for this attribute are TXOUT or TXUSR. Instance: %m", MODULE_NAME, TX_XCLK_SEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_PING_SATA_MAX_INIT_REG < 1) || (USB_PING_SATA_MAX_INIT_REG > 63))) begin
$display("Error: [Unisim %s-757] USB_PING_SATA_MAX_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MAX_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_PING_SATA_MIN_INIT_REG < 1) || (USB_PING_SATA_MIN_INIT_REG > 63))) begin
$display("Error: [Unisim %s-758] USB_PING_SATA_MIN_INIT attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_PING_SATA_MIN_INIT_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_POLL_SATA_MAX_BURST_REG < 1) || (USB_POLL_SATA_MAX_BURST_REG > 63))) begin
$display("Error: [Unisim %s-759] USB_POLL_SATA_MAX_BURST attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_POLL_SATA_MAX_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_POLL_SATA_MIN_BURST_REG < 1) || (USB_POLL_SATA_MIN_BURST_REG > 61))) begin
$display("Error: [Unisim %s-760] USB_POLL_SATA_MIN_BURST attribute is set to %d. Legal values for this attribute are 1 to 61. Instance: %m", MODULE_NAME, USB_POLL_SATA_MIN_BURST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U1_SATA_MAX_WAKE_REG < 1) || (USB_U1_SATA_MAX_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-764] USB_U1_SATA_MAX_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MAX_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U1_SATA_MIN_WAKE_REG < 1) || (USB_U1_SATA_MIN_WAKE_REG > 63))) begin
$display("Error: [Unisim %s-765] USB_U1_SATA_MIN_WAKE attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U1_SATA_MIN_WAKE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U2_SAS_MAX_COM_REG < 1) || (USB_U2_SAS_MAX_COM_REG > 127))) begin
$display("Error: [Unisim %s-766] USB_U2_SAS_MAX_COM attribute is set to %d. Legal values for this attribute are 1 to 127. Instance: %m", MODULE_NAME, USB_U2_SAS_MAX_COM_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USB_U2_SAS_MIN_COM_REG < 1) || (USB_U2_SAS_MIN_COM_REG > 63))) begin
$display("Error: [Unisim %s-767] USB_U2_SAS_MIN_COM attribute is set to %d. Legal values for this attribute are 1 to 63. Instance: %m", MODULE_NAME, USB_U2_SAS_MIN_COM_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
assign PMASCANCLK0_in = 1'b1; // tie off
assign PMASCANCLK1_in = 1'b1; // tie off
assign PMASCANCLK2_in = 1'b1; // tie off
assign PMASCANCLK3_in = 1'b1; // tie off
assign PMASCANCLK4_in = 1'b1; // tie off
assign PMASCANCLK5_in = 1'b1; // tie off
assign PMASCANCLK6_in = 1'b1; // tie off
assign PMASCANCLK7_in = 1'b1; // tie off
assign PMASCANCLK8_in = 1'b1; // tie off
assign SCANCLK_in = 1'b1; // tie off
assign TSTCLK0_in = 1'b1; // tie off
assign TSTCLK1_in = 1'b1; // tie off
assign BSR_SERIAL_in = 1'b1; // tie off
assign CSSDRSTB_in = 1'b1; // tie off
assign CSSDSTOPCLK_in = 1'b1; // tie off
assign PMASCANENB_in = 1'b1; // tie off
assign PMASCANIN_in = 18'b111111111111111111; // tie off
assign PMASCANMODEB_in = 1'b1; // tie off
assign PMASCANRSTEN_in = 1'b1; // tie off
assign SARCCLK_in = 1'b1; // tie off
assign SCANENB_in = 1'b1; // tie off
assign SCANIN_in = 19'b1111111111111111111; // tie off
assign SCANMODEB_in = 1'b1; // tie off
assign SCANRSTB_in = 1'b1; // tie off
assign SCANRSTEN_in = 1'b1; // tie off
assign TSTPDOVRDB_in = 1'b1; // tie off
assign TSTPD_in = 5'b11111; // tie off
SIP_GTYE4_CHANNEL SIP_GTYE4_CHANNEL_INST (
.ACJTAG_DEBUG_MODE (ACJTAG_DEBUG_MODE_REG),
.ACJTAG_MODE (ACJTAG_MODE_REG),
.ACJTAG_RESET (ACJTAG_RESET_REG),
.ADAPT_CFG0 (ADAPT_CFG0_REG),
.ADAPT_CFG1 (ADAPT_CFG1_REG),
.ADAPT_CFG2 (ADAPT_CFG2_REG),
.AEN_CDRSTEPSEL (AEN_CDRSTEPSEL_REG),
.AEN_CPLL (AEN_CPLL_REG),
.AEN_LOOPBACK (AEN_LOOPBACK_REG),
.AEN_MASTER (AEN_MASTER_REG),
.AEN_PD_AND_EIDLE (AEN_PD_AND_EIDLE_REG),
.AEN_POLARITY (AEN_POLARITY_REG),
.AEN_PRBS (AEN_PRBS_REG),
.AEN_RESET (AEN_RESET_REG),
.AEN_RXCDR (AEN_RXCDR_REG),
.AEN_RXDFE (AEN_RXDFE_REG),
.AEN_RXDFELPM (AEN_RXDFELPM_REG),
.AEN_RXOUTCLK_SEL (AEN_RXOUTCLK_SEL_REG),
.AEN_RXPHDLY (AEN_RXPHDLY_REG),
.AEN_RXPLLCLK_SEL (AEN_RXPLLCLK_SEL_REG),
.AEN_RXSYSCLK_SEL (AEN_RXSYSCLK_SEL_REG),
.AEN_TXMUXDCD (AEN_TXMUXDCD_REG),
.AEN_TXOUTCLK_SEL (AEN_TXOUTCLK_SEL_REG),
.AEN_TXPHDLY (AEN_TXPHDLY_REG),
.AEN_TXPI_PPM (AEN_TXPI_PPM_REG),
.AEN_TXPLLCLK_SEL (AEN_TXPLLCLK_SEL_REG),
.AEN_TXSYSCLK_SEL (AEN_TXSYSCLK_SEL_REG),
.AEN_TX_DRIVE_MODE (AEN_TX_DRIVE_MODE_REG),
.ALIGN_COMMA_DOUBLE (ALIGN_COMMA_DOUBLE_REG),
.ALIGN_COMMA_ENABLE (ALIGN_COMMA_ENABLE_REG),
.ALIGN_COMMA_WORD (ALIGN_COMMA_WORD_REG),
.ALIGN_MCOMMA_DET (ALIGN_MCOMMA_DET_REG),
.ALIGN_MCOMMA_VALUE (ALIGN_MCOMMA_VALUE_REG),
.ALIGN_PCOMMA_DET (ALIGN_PCOMMA_DET_REG),
.ALIGN_PCOMMA_VALUE (ALIGN_PCOMMA_VALUE_REG),
.AMONITOR_CFG (AMONITOR_CFG_REG),
.A_CPLLLOCKEN (A_CPLLLOCKEN_REG),
.A_CPLLPD (A_CPLLPD_REG),
.A_CPLLRESET (A_CPLLRESET_REG),
.A_EYESCANRESET (A_EYESCANRESET_REG),
.A_GTRESETSEL (A_GTRESETSEL_REG),
.A_GTRXRESET (A_GTRXRESET_REG),
.A_GTTXRESET (A_GTTXRESET_REG),
.A_LOOPBACK (A_LOOPBACK_REG),
.A_RXAFECFOKEN (A_RXAFECFOKEN_REG),
.A_RXBUFRESET (A_RXBUFRESET_REG),
.A_RXCDRFREQRESET (A_RXCDRFREQRESET_REG),
.A_RXCDRHOLD (A_RXCDRHOLD_REG),
.A_RXCDROVRDEN (A_RXCDROVRDEN_REG),
.A_RXCDRRESET (A_RXCDRRESET_REG),
.A_RXCKCALRESET (A_RXCKCALRESET_REG),
.A_RXDFEAGCHOLD (A_RXDFEAGCHOLD_REG),
.A_RXDFEAGCOVRDEN (A_RXDFEAGCOVRDEN_REG),
.A_RXDFECFOKFCNUM (A_RXDFECFOKFCNUM_REG),
.A_RXDFECFOKFEN (A_RXDFECFOKFEN_REG),
.A_RXDFECFOKFPULSE (A_RXDFECFOKFPULSE_REG),
.A_RXDFECFOKHOLD (A_RXDFECFOKHOLD_REG),
.A_RXDFECFOKOVREN (A_RXDFECFOKOVREN_REG),
.A_RXDFEKHHOLD (A_RXDFEKHHOLD_REG),
.A_RXDFEKHOVRDEN (A_RXDFEKHOVRDEN_REG),
.A_RXDFELFHOLD (A_RXDFELFHOLD_REG),
.A_RXDFELFOVRDEN (A_RXDFELFOVRDEN_REG),
.A_RXDFELPMRESET (A_RXDFELPMRESET_REG),
.A_RXDFETAP10HOLD (A_RXDFETAP10HOLD_REG),
.A_RXDFETAP10OVRDEN (A_RXDFETAP10OVRDEN_REG),
.A_RXDFETAP11HOLD (A_RXDFETAP11HOLD_REG),
.A_RXDFETAP11OVRDEN (A_RXDFETAP11OVRDEN_REG),
.A_RXDFETAP12HOLD (A_RXDFETAP12HOLD_REG),
.A_RXDFETAP12OVRDEN (A_RXDFETAP12OVRDEN_REG),
.A_RXDFETAP13HOLD (A_RXDFETAP13HOLD_REG),
.A_RXDFETAP13OVRDEN (A_RXDFETAP13OVRDEN_REG),
.A_RXDFETAP14HOLD (A_RXDFETAP14HOLD_REG),
.A_RXDFETAP14OVRDEN (A_RXDFETAP14OVRDEN_REG),
.A_RXDFETAP15HOLD (A_RXDFETAP15HOLD_REG),
.A_RXDFETAP15OVRDEN (A_RXDFETAP15OVRDEN_REG),
.A_RXDFETAP2HOLD (A_RXDFETAP2HOLD_REG),
.A_RXDFETAP2OVRDEN (A_RXDFETAP2OVRDEN_REG),
.A_RXDFETAP3HOLD (A_RXDFETAP3HOLD_REG),
.A_RXDFETAP3OVRDEN (A_RXDFETAP3OVRDEN_REG),
.A_RXDFETAP4HOLD (A_RXDFETAP4HOLD_REG),
.A_RXDFETAP4OVRDEN (A_RXDFETAP4OVRDEN_REG),
.A_RXDFETAP5HOLD (A_RXDFETAP5HOLD_REG),
.A_RXDFETAP5OVRDEN (A_RXDFETAP5OVRDEN_REG),
.A_RXDFETAP6HOLD (A_RXDFETAP6HOLD_REG),
.A_RXDFETAP6OVRDEN (A_RXDFETAP6OVRDEN_REG),
.A_RXDFETAP7HOLD (A_RXDFETAP7HOLD_REG),
.A_RXDFETAP7OVRDEN (A_RXDFETAP7OVRDEN_REG),
.A_RXDFETAP8HOLD (A_RXDFETAP8HOLD_REG),
.A_RXDFETAP8OVRDEN (A_RXDFETAP8OVRDEN_REG),
.A_RXDFETAP9HOLD (A_RXDFETAP9HOLD_REG),
.A_RXDFETAP9OVRDEN (A_RXDFETAP9OVRDEN_REG),
.A_RXDFEUTHOLD (A_RXDFEUTHOLD_REG),
.A_RXDFEUTOVRDEN (A_RXDFEUTOVRDEN_REG),
.A_RXDFEVPHOLD (A_RXDFEVPHOLD_REG),
.A_RXDFEVPOVRDEN (A_RXDFEVPOVRDEN_REG),
.A_RXDFEXYDEN (A_RXDFEXYDEN_REG),
.A_RXDLYBYPASS (A_RXDLYBYPASS_REG),
.A_RXDLYEN (A_RXDLYEN_REG),
.A_RXDLYOVRDEN (A_RXDLYOVRDEN_REG),
.A_RXDLYSRESET (A_RXDLYSRESET_REG),
.A_RXLPMEN (A_RXLPMEN_REG),
.A_RXLPMGCHOLD (A_RXLPMGCHOLD_REG),
.A_RXLPMGCOVRDEN (A_RXLPMGCOVRDEN_REG),
.A_RXLPMHFHOLD (A_RXLPMHFHOLD_REG),
.A_RXLPMHFOVRDEN (A_RXLPMHFOVRDEN_REG),
.A_RXLPMLFHOLD (A_RXLPMLFHOLD_REG),
.A_RXLPMLFKLOVRDEN (A_RXLPMLFKLOVRDEN_REG),
.A_RXLPMOSHOLD (A_RXLPMOSHOLD_REG),
.A_RXLPMOSOVRDEN (A_RXLPMOSOVRDEN_REG),
.A_RXMONITORSEL (A_RXMONITORSEL_REG),
.A_RXOOBRESET (A_RXOOBRESET_REG),
.A_RXOSCALRESET (A_RXOSCALRESET_REG),
.A_RXOSHOLD (A_RXOSHOLD_REG),
.A_RXOSOVRDEN (A_RXOSOVRDEN_REG),
.A_RXOUTCLKSEL (A_RXOUTCLKSEL_REG),
.A_RXPCSRESET (A_RXPCSRESET_REG),
.A_RXPD (A_RXPD_REG),
.A_RXPHALIGN (A_RXPHALIGN_REG),
.A_RXPHALIGNEN (A_RXPHALIGNEN_REG),
.A_RXPHDLYPD (A_RXPHDLYPD_REG),
.A_RXPHDLYRESET (A_RXPHDLYRESET_REG),
.A_RXPLLCLKSEL (A_RXPLLCLKSEL_REG),
.A_RXPMARESET (A_RXPMARESET_REG),
.A_RXPOLARITY (A_RXPOLARITY_REG),
.A_RXPRBSCNTRESET (A_RXPRBSCNTRESET_REG),
.A_RXPRBSSEL (A_RXPRBSSEL_REG),
.A_RXPROGDIVRESET (A_RXPROGDIVRESET_REG),
.A_RXSYSCLKSEL (A_RXSYSCLKSEL_REG),
.A_RXTERMINATION (A_RXTERMINATION_REG),
.A_TXBUFDIFFCTRL (A_TXBUFDIFFCTRL_REG),
.A_TXDCCRESET (A_TXDCCRESET_REG),
.A_TXDEEMPH (A_TXDEEMPH_REG),
.A_TXDIFFCTRL (A_TXDIFFCTRL_REG),
.A_TXDLYBYPASS (A_TXDLYBYPASS_REG),
.A_TXDLYEN (A_TXDLYEN_REG),
.A_TXDLYOVRDEN (A_TXDLYOVRDEN_REG),
.A_TXDLYSRESET (A_TXDLYSRESET_REG),
.A_TXELECIDLE (A_TXELECIDLE_REG),
.A_TXINHIBIT (A_TXINHIBIT_REG),
.A_TXMAINCURSOR (A_TXMAINCURSOR_REG),
.A_TXMARGIN (A_TXMARGIN_REG),
.A_TXMUXDCDEXHOLD (A_TXMUXDCDEXHOLD_REG),
.A_TXMUXDCDORWREN (A_TXMUXDCDORWREN_REG),
.A_TXOUTCLKSEL (A_TXOUTCLKSEL_REG),
.A_TXPCSRESET (A_TXPCSRESET_REG),
.A_TXPD (A_TXPD_REG),
.A_TXPHALIGN (A_TXPHALIGN_REG),
.A_TXPHALIGNEN (A_TXPHALIGNEN_REG),
.A_TXPHDLYPD (A_TXPHDLYPD_REG),
.A_TXPHDLYRESET (A_TXPHDLYRESET_REG),
.A_TXPHINIT (A_TXPHINIT_REG),
.A_TXPHOVRDEN (A_TXPHOVRDEN_REG),
.A_TXPIPPMOVRDEN (A_TXPIPPMOVRDEN_REG),
.A_TXPIPPMPD (A_TXPIPPMPD_REG),
.A_TXPIPPMSEL (A_TXPIPPMSEL_REG),
.A_TXPLLCLKSEL (A_TXPLLCLKSEL_REG),
.A_TXPMARESET (A_TXPMARESET_REG),
.A_TXPOLARITY (A_TXPOLARITY_REG),
.A_TXPOSTCURSOR (A_TXPOSTCURSOR_REG),
.A_TXPRBSFORCEERR (A_TXPRBSFORCEERR_REG),
.A_TXPRBSSEL (A_TXPRBSSEL_REG),
.A_TXPRECURSOR (A_TXPRECURSOR_REG),
.A_TXPROGDIVRESET (A_TXPROGDIVRESET_REG),
.A_TXRESETSEL (A_TXRESETSEL_REG),
.A_TXSWING (A_TXSWING_REG),
.A_TXSYSCLKSEL (A_TXSYSCLKSEL_REG),
.BSR_ENABLE (BSR_ENABLE_REG),
.CBCC_DATA_SOURCE_SEL (CBCC_DATA_SOURCE_SEL_REG),
.CDR_SWAP_MODE_EN (CDR_SWAP_MODE_EN_REG),
.CFOK_PWRSVE_EN (CFOK_PWRSVE_EN_REG),
.CHAN_BOND_KEEP_ALIGN (CHAN_BOND_KEEP_ALIGN_REG),
.CHAN_BOND_MAX_SKEW (CHAN_BOND_MAX_SKEW_REG),
.CHAN_BOND_SEQ_1_1 (CHAN_BOND_SEQ_1_1_REG),
.CHAN_BOND_SEQ_1_2 (CHAN_BOND_SEQ_1_2_REG),
.CHAN_BOND_SEQ_1_3 (CHAN_BOND_SEQ_1_3_REG),
.CHAN_BOND_SEQ_1_4 (CHAN_BOND_SEQ_1_4_REG),
.CHAN_BOND_SEQ_1_ENABLE (CHAN_BOND_SEQ_1_ENABLE_REG),
.CHAN_BOND_SEQ_2_1 (CHAN_BOND_SEQ_2_1_REG),
.CHAN_BOND_SEQ_2_2 (CHAN_BOND_SEQ_2_2_REG),
.CHAN_BOND_SEQ_2_3 (CHAN_BOND_SEQ_2_3_REG),
.CHAN_BOND_SEQ_2_4 (CHAN_BOND_SEQ_2_4_REG),
.CHAN_BOND_SEQ_2_ENABLE (CHAN_BOND_SEQ_2_ENABLE_REG),
.CHAN_BOND_SEQ_2_USE (CHAN_BOND_SEQ_2_USE_REG),
.CHAN_BOND_SEQ_LEN (CHAN_BOND_SEQ_LEN_REG),
.CH_HSPMUX (CH_HSPMUX_REG),
.CKCAL1_CFG_0 (CKCAL1_CFG_0_REG),
.CKCAL1_CFG_1 (CKCAL1_CFG_1_REG),
.CKCAL1_CFG_2 (CKCAL1_CFG_2_REG),
.CKCAL1_CFG_3 (CKCAL1_CFG_3_REG),
.CKCAL2_CFG_0 (CKCAL2_CFG_0_REG),
.CKCAL2_CFG_1 (CKCAL2_CFG_1_REG),
.CKCAL2_CFG_2 (CKCAL2_CFG_2_REG),
.CKCAL2_CFG_3 (CKCAL2_CFG_3_REG),
.CKCAL2_CFG_4 (CKCAL2_CFG_4_REG),
.CLK_CORRECT_USE (CLK_CORRECT_USE_REG),
.CLK_COR_KEEP_IDLE (CLK_COR_KEEP_IDLE_REG),
.CLK_COR_MAX_LAT (CLK_COR_MAX_LAT_REG),
.CLK_COR_MIN_LAT (CLK_COR_MIN_LAT_REG),
.CLK_COR_PRECEDENCE (CLK_COR_PRECEDENCE_REG),
.CLK_COR_REPEAT_WAIT (CLK_COR_REPEAT_WAIT_REG),
.CLK_COR_SEQ_1_1 (CLK_COR_SEQ_1_1_REG),
.CLK_COR_SEQ_1_2 (CLK_COR_SEQ_1_2_REG),
.CLK_COR_SEQ_1_3 (CLK_COR_SEQ_1_3_REG),
.CLK_COR_SEQ_1_4 (CLK_COR_SEQ_1_4_REG),
.CLK_COR_SEQ_1_ENABLE (CLK_COR_SEQ_1_ENABLE_REG),
.CLK_COR_SEQ_2_1 (CLK_COR_SEQ_2_1_REG),
.CLK_COR_SEQ_2_2 (CLK_COR_SEQ_2_2_REG),
.CLK_COR_SEQ_2_3 (CLK_COR_SEQ_2_3_REG),
.CLK_COR_SEQ_2_4 (CLK_COR_SEQ_2_4_REG),
.CLK_COR_SEQ_2_ENABLE (CLK_COR_SEQ_2_ENABLE_REG),
.CLK_COR_SEQ_2_USE (CLK_COR_SEQ_2_USE_REG),
.CLK_COR_SEQ_LEN (CLK_COR_SEQ_LEN_REG),
.CPLL_CFG0 (CPLL_CFG0_REG),
.CPLL_CFG1 (CPLL_CFG1_REG),
.CPLL_CFG2 (CPLL_CFG2_REG),
.CPLL_CFG3 (CPLL_CFG3_REG),
.CPLL_FBDIV (CPLL_FBDIV_REG),
.CPLL_FBDIV_45 (CPLL_FBDIV_45_REG),
.CPLL_INIT_CFG0 (CPLL_INIT_CFG0_REG),
.CPLL_LOCK_CFG (CPLL_LOCK_CFG_REG),
.CPLL_REFCLK_DIV (CPLL_REFCLK_DIV_REG),
.CSSD_CLK_MASK0 (CSSD_CLK_MASK0_REG),
.CSSD_CLK_MASK1 (CSSD_CLK_MASK1_REG),
.CSSD_REG0 (CSSD_REG0_REG),
.CSSD_REG1 (CSSD_REG1_REG),
.CSSD_REG10 (CSSD_REG10_REG),
.CSSD_REG2 (CSSD_REG2_REG),
.CSSD_REG3 (CSSD_REG3_REG),
.CSSD_REG4 (CSSD_REG4_REG),
.CSSD_REG5 (CSSD_REG5_REG),
.CSSD_REG6 (CSSD_REG6_REG),
.CSSD_REG7 (CSSD_REG7_REG),
.CSSD_REG8 (CSSD_REG8_REG),
.CSSD_REG9 (CSSD_REG9_REG),
.CTLE3_OCAP_EXT_CTRL (CTLE3_OCAP_EXT_CTRL_REG),
.CTLE3_OCAP_EXT_EN (CTLE3_OCAP_EXT_EN_REG),
.DDI_CTRL (DDI_CTRL_REG),
.DDI_REALIGN_WAIT (DDI_REALIGN_WAIT_REG),
.DEC_MCOMMA_DETECT (DEC_MCOMMA_DETECT_REG),
.DEC_PCOMMA_DETECT (DEC_PCOMMA_DETECT_REG),
.DEC_VALID_COMMA_ONLY (DEC_VALID_COMMA_ONLY_REG),
.DELAY_ELEC (DELAY_ELEC_REG),
.DMONITOR_CFG0 (DMONITOR_CFG0_REG),
.DMONITOR_CFG1 (DMONITOR_CFG1_REG),
.ES_CLK_PHASE_SEL (ES_CLK_PHASE_SEL_REG),
.ES_CONTROL (ES_CONTROL_REG),
.ES_ERRDET_EN (ES_ERRDET_EN_REG),
.ES_EYE_SCAN_EN (ES_EYE_SCAN_EN_REG),
.ES_HORZ_OFFSET (ES_HORZ_OFFSET_REG),
.ES_PRESCALE (ES_PRESCALE_REG),
.ES_QUALIFIER0 (ES_QUALIFIER0_REG),
.ES_QUALIFIER1 (ES_QUALIFIER1_REG),
.ES_QUALIFIER2 (ES_QUALIFIER2_REG),
.ES_QUALIFIER3 (ES_QUALIFIER3_REG),
.ES_QUALIFIER4 (ES_QUALIFIER4_REG),
.ES_QUALIFIER5 (ES_QUALIFIER5_REG),
.ES_QUALIFIER6 (ES_QUALIFIER6_REG),
.ES_QUALIFIER7 (ES_QUALIFIER7_REG),
.ES_QUALIFIER8 (ES_QUALIFIER8_REG),
.ES_QUALIFIER9 (ES_QUALIFIER9_REG),
.ES_QUAL_MASK0 (ES_QUAL_MASK0_REG),
.ES_QUAL_MASK1 (ES_QUAL_MASK1_REG),
.ES_QUAL_MASK2 (ES_QUAL_MASK2_REG),
.ES_QUAL_MASK3 (ES_QUAL_MASK3_REG),
.ES_QUAL_MASK4 (ES_QUAL_MASK4_REG),
.ES_QUAL_MASK5 (ES_QUAL_MASK5_REG),
.ES_QUAL_MASK6 (ES_QUAL_MASK6_REG),
.ES_QUAL_MASK7 (ES_QUAL_MASK7_REG),
.ES_QUAL_MASK8 (ES_QUAL_MASK8_REG),
.ES_QUAL_MASK9 (ES_QUAL_MASK9_REG),
.ES_SDATA_MASK0 (ES_SDATA_MASK0_REG),
.ES_SDATA_MASK1 (ES_SDATA_MASK1_REG),
.ES_SDATA_MASK2 (ES_SDATA_MASK2_REG),
.ES_SDATA_MASK3 (ES_SDATA_MASK3_REG),
.ES_SDATA_MASK4 (ES_SDATA_MASK4_REG),
.ES_SDATA_MASK5 (ES_SDATA_MASK5_REG),
.ES_SDATA_MASK6 (ES_SDATA_MASK6_REG),
.ES_SDATA_MASK7 (ES_SDATA_MASK7_REG),
.ES_SDATA_MASK8 (ES_SDATA_MASK8_REG),
.ES_SDATA_MASK9 (ES_SDATA_MASK9_REG),
.EYESCAN_VP_RANGE (EYESCAN_VP_RANGE_REG),
.EYE_SCAN_SWAP_EN (EYE_SCAN_SWAP_EN_REG),
.FTS_DESKEW_SEQ_ENABLE (FTS_DESKEW_SEQ_ENABLE_REG),
.FTS_LANE_DESKEW_CFG (FTS_LANE_DESKEW_CFG_REG),
.FTS_LANE_DESKEW_EN (FTS_LANE_DESKEW_EN_REG),
.GEARBOX_MODE (GEARBOX_MODE_REG),
.GEN_RXUSRCLK (GEN_RXUSRCLK_REG),
.GEN_TXUSRCLK (GEN_TXUSRCLK_REG),
.GT_INSTANTIATED (GT_INSTANTIATED_REG),
.INT_MASK_CFG0 (INT_MASK_CFG0_REG),
.INT_MASK_CFG1 (INT_MASK_CFG1_REG),
.ISCAN_CK_PH_SEL2 (ISCAN_CK_PH_SEL2_REG),
.LOCAL_MASTER (LOCAL_MASTER_REG),
.LPBK_BIAS_CTRL (LPBK_BIAS_CTRL_REG),
.LPBK_EN_RCAL_B (LPBK_EN_RCAL_B_REG),
.LPBK_EXT_RCAL (LPBK_EXT_RCAL_REG),
.LPBK_IND_CTRL0 (LPBK_IND_CTRL0_REG),
.LPBK_IND_CTRL1 (LPBK_IND_CTRL1_REG),
.LPBK_IND_CTRL2 (LPBK_IND_CTRL2_REG),
.LPBK_RG_CTRL (LPBK_RG_CTRL_REG),
.OOBDIVCTL (OOBDIVCTL_REG),
.OOB_PWRUP (OOB_PWRUP_REG),
.PCI3_AUTO_REALIGN (PCI3_AUTO_REALIGN_REG),
.PCI3_PIPE_RX_ELECIDLE (PCI3_PIPE_RX_ELECIDLE_REG),
.PCI3_RX_ASYNC_EBUF_BYPASS (PCI3_RX_ASYNC_EBUF_BYPASS_REG),
.PCI3_RX_ELECIDLE_EI2_ENABLE (PCI3_RX_ELECIDLE_EI2_ENABLE_REG),
.PCI3_RX_ELECIDLE_H2L_COUNT (PCI3_RX_ELECIDLE_H2L_COUNT_REG),
.PCI3_RX_ELECIDLE_H2L_DISABLE (PCI3_RX_ELECIDLE_H2L_DISABLE_REG),
.PCI3_RX_ELECIDLE_HI_COUNT (PCI3_RX_ELECIDLE_HI_COUNT_REG),
.PCI3_RX_ELECIDLE_LP4_DISABLE (PCI3_RX_ELECIDLE_LP4_DISABLE_REG),
.PCI3_RX_FIFO_DISABLE (PCI3_RX_FIFO_DISABLE_REG),
.PCIE3_CLK_COR_EMPTY_THRSH (PCIE3_CLK_COR_EMPTY_THRSH_REG),
.PCIE3_CLK_COR_FULL_THRSH (PCIE3_CLK_COR_FULL_THRSH_REG),
.PCIE3_CLK_COR_MAX_LAT (PCIE3_CLK_COR_MAX_LAT_REG),
.PCIE3_CLK_COR_MIN_LAT (PCIE3_CLK_COR_MIN_LAT_REG),
.PCIE3_CLK_COR_THRSH_TIMER (PCIE3_CLK_COR_THRSH_TIMER_REG),
.PCIE_64B_DYN_CLKSW_DIS (PCIE_64B_DYN_CLKSW_DIS_REG),
.PCIE_BUFG_DIV_CTRL (PCIE_BUFG_DIV_CTRL_REG),
.PCIE_GEN4_64BIT_INT_EN (PCIE_GEN4_64BIT_INT_EN_REG),
.PCIE_PLL_SEL_MODE_GEN12 (PCIE_PLL_SEL_MODE_GEN12_REG),
.PCIE_PLL_SEL_MODE_GEN3 (PCIE_PLL_SEL_MODE_GEN3_REG),
.PCIE_PLL_SEL_MODE_GEN4 (PCIE_PLL_SEL_MODE_GEN4_REG),
.PCIE_RXPCS_CFG_GEN3 (PCIE_RXPCS_CFG_GEN3_REG),
.PCIE_RXPMA_CFG (PCIE_RXPMA_CFG_REG),
.PCIE_TXPCS_CFG_GEN3 (PCIE_TXPCS_CFG_GEN3_REG),
.PCIE_TXPMA_CFG (PCIE_TXPMA_CFG_REG),
.PCS_PCIE_EN (PCS_PCIE_EN_REG),
.PCS_RSVD0 (PCS_RSVD0_REG),
.PD_TRANS_TIME_FROM_P2 (PD_TRANS_TIME_FROM_P2_REG),
.PD_TRANS_TIME_NONE_P2 (PD_TRANS_TIME_NONE_P2_REG),
.PD_TRANS_TIME_TO_P2 (PD_TRANS_TIME_TO_P2_REG),
.PREIQ_FREQ_BST (PREIQ_FREQ_BST_REG),
.RATE_SW_USE_DRP (RATE_SW_USE_DRP_REG),
.RCLK_SIPO_DLY_ENB (RCLK_SIPO_DLY_ENB_REG),
.RCLK_SIPO_INV_EN (RCLK_SIPO_INV_EN_REG),
.RTX_BUF_CML_CTRL (RTX_BUF_CML_CTRL_REG),
.RTX_BUF_TERM_CTRL (RTX_BUF_TERM_CTRL_REG),
.RXBUFRESET_TIME (RXBUFRESET_TIME_REG),
.RXBUF_ADDR_MODE (RXBUF_ADDR_MODE_REG),
.RXBUF_EIDLE_HI_CNT (RXBUF_EIDLE_HI_CNT_REG),
.RXBUF_EIDLE_LO_CNT (RXBUF_EIDLE_LO_CNT_REG),
.RXBUF_EN (RXBUF_EN_REG),
.RXBUF_RESET_ON_CB_CHANGE (RXBUF_RESET_ON_CB_CHANGE_REG),
.RXBUF_RESET_ON_COMMAALIGN (RXBUF_RESET_ON_COMMAALIGN_REG),
.RXBUF_RESET_ON_EIDLE (RXBUF_RESET_ON_EIDLE_REG),
.RXBUF_RESET_ON_RATE_CHANGE (RXBUF_RESET_ON_RATE_CHANGE_REG),
.RXBUF_THRESH_OVFLW (RXBUF_THRESH_OVFLW_REG),
.RXBUF_THRESH_OVRD (RXBUF_THRESH_OVRD_REG),
.RXBUF_THRESH_UNDFLW (RXBUF_THRESH_UNDFLW_REG),
.RXCDRFREQRESET_TIME (RXCDRFREQRESET_TIME_REG),
.RXCDRPHRESET_TIME (RXCDRPHRESET_TIME_REG),
.RXCDR_CFG0 (RXCDR_CFG0_REG),
.RXCDR_CFG0_GEN3 (RXCDR_CFG0_GEN3_REG),
.RXCDR_CFG1 (RXCDR_CFG1_REG),
.RXCDR_CFG1_GEN3 (RXCDR_CFG1_GEN3_REG),
.RXCDR_CFG2 (RXCDR_CFG2_REG),
.RXCDR_CFG2_GEN2 (RXCDR_CFG2_GEN2_REG),
.RXCDR_CFG2_GEN3 (RXCDR_CFG2_GEN3_REG),
.RXCDR_CFG2_GEN4 (RXCDR_CFG2_GEN4_REG),
.RXCDR_CFG3 (RXCDR_CFG3_REG),
.RXCDR_CFG3_GEN2 (RXCDR_CFG3_GEN2_REG),
.RXCDR_CFG3_GEN3 (RXCDR_CFG3_GEN3_REG),
.RXCDR_CFG3_GEN4 (RXCDR_CFG3_GEN4_REG),
.RXCDR_CFG4 (RXCDR_CFG4_REG),
.RXCDR_CFG4_GEN3 (RXCDR_CFG4_GEN3_REG),
.RXCDR_CFG5 (RXCDR_CFG5_REG),
.RXCDR_CFG5_GEN3 (RXCDR_CFG5_GEN3_REG),
.RXCDR_FR_RESET_ON_EIDLE (RXCDR_FR_RESET_ON_EIDLE_REG),
.RXCDR_HOLD_DURING_EIDLE (RXCDR_HOLD_DURING_EIDLE_REG),
.RXCDR_LOCK_CFG0 (RXCDR_LOCK_CFG0_REG),
.RXCDR_LOCK_CFG1 (RXCDR_LOCK_CFG1_REG),
.RXCDR_LOCK_CFG2 (RXCDR_LOCK_CFG2_REG),
.RXCDR_LOCK_CFG3 (RXCDR_LOCK_CFG3_REG),
.RXCDR_LOCK_CFG4 (RXCDR_LOCK_CFG4_REG),
.RXCDR_PH_RESET_ON_EIDLE (RXCDR_PH_RESET_ON_EIDLE_REG),
.RXCFOK_CFG0 (RXCFOK_CFG0_REG),
.RXCFOK_CFG1 (RXCFOK_CFG1_REG),
.RXCFOK_CFG2 (RXCFOK_CFG2_REG),
.RXCKCAL1_IQ_LOOP_RST_CFG (RXCKCAL1_IQ_LOOP_RST_CFG_REG),
.RXCKCAL1_I_LOOP_RST_CFG (RXCKCAL1_I_LOOP_RST_CFG_REG),
.RXCKCAL1_Q_LOOP_RST_CFG (RXCKCAL1_Q_LOOP_RST_CFG_REG),
.RXCKCAL2_DX_LOOP_RST_CFG (RXCKCAL2_DX_LOOP_RST_CFG_REG),
.RXCKCAL2_D_LOOP_RST_CFG (RXCKCAL2_D_LOOP_RST_CFG_REG),
.RXCKCAL2_S_LOOP_RST_CFG (RXCKCAL2_S_LOOP_RST_CFG_REG),
.RXCKCAL2_X_LOOP_RST_CFG (RXCKCAL2_X_LOOP_RST_CFG_REG),
.RXDFELPMRESET_TIME (RXDFELPMRESET_TIME_REG),
.RXDFELPM_KL_CFG0 (RXDFELPM_KL_CFG0_REG),
.RXDFELPM_KL_CFG1 (RXDFELPM_KL_CFG1_REG),
.RXDFELPM_KL_CFG2 (RXDFELPM_KL_CFG2_REG),
.RXDFE_CFG0 (RXDFE_CFG0_REG),
.RXDFE_CFG1 (RXDFE_CFG1_REG),
.RXDFE_GC_CFG0 (RXDFE_GC_CFG0_REG),
.RXDFE_GC_CFG1 (RXDFE_GC_CFG1_REG),
.RXDFE_GC_CFG2 (RXDFE_GC_CFG2_REG),
.RXDFE_H2_CFG0 (RXDFE_H2_CFG0_REG),
.RXDFE_H2_CFG1 (RXDFE_H2_CFG1_REG),
.RXDFE_H3_CFG0 (RXDFE_H3_CFG0_REG),
.RXDFE_H3_CFG1 (RXDFE_H3_CFG1_REG),
.RXDFE_H4_CFG0 (RXDFE_H4_CFG0_REG),
.RXDFE_H4_CFG1 (RXDFE_H4_CFG1_REG),
.RXDFE_H5_CFG0 (RXDFE_H5_CFG0_REG),
.RXDFE_H5_CFG1 (RXDFE_H5_CFG1_REG),
.RXDFE_H6_CFG0 (RXDFE_H6_CFG0_REG),
.RXDFE_H6_CFG1 (RXDFE_H6_CFG1_REG),
.RXDFE_H7_CFG0 (RXDFE_H7_CFG0_REG),
.RXDFE_H7_CFG1 (RXDFE_H7_CFG1_REG),
.RXDFE_H8_CFG0 (RXDFE_H8_CFG0_REG),
.RXDFE_H8_CFG1 (RXDFE_H8_CFG1_REG),
.RXDFE_H9_CFG0 (RXDFE_H9_CFG0_REG),
.RXDFE_H9_CFG1 (RXDFE_H9_CFG1_REG),
.RXDFE_HA_CFG0 (RXDFE_HA_CFG0_REG),
.RXDFE_HA_CFG1 (RXDFE_HA_CFG1_REG),
.RXDFE_HB_CFG0 (RXDFE_HB_CFG0_REG),
.RXDFE_HB_CFG1 (RXDFE_HB_CFG1_REG),
.RXDFE_HC_CFG0 (RXDFE_HC_CFG0_REG),
.RXDFE_HC_CFG1 (RXDFE_HC_CFG1_REG),
.RXDFE_HD_CFG0 (RXDFE_HD_CFG0_REG),
.RXDFE_HD_CFG1 (RXDFE_HD_CFG1_REG),
.RXDFE_HE_CFG0 (RXDFE_HE_CFG0_REG),
.RXDFE_HE_CFG1 (RXDFE_HE_CFG1_REG),
.RXDFE_HF_CFG0 (RXDFE_HF_CFG0_REG),
.RXDFE_HF_CFG1 (RXDFE_HF_CFG1_REG),
.RXDFE_KH_CFG0 (RXDFE_KH_CFG0_REG),
.RXDFE_KH_CFG1 (RXDFE_KH_CFG1_REG),
.RXDFE_KH_CFG2 (RXDFE_KH_CFG2_REG),
.RXDFE_KH_CFG3 (RXDFE_KH_CFG3_REG),
.RXDFE_OS_CFG0 (RXDFE_OS_CFG0_REG),
.RXDFE_OS_CFG1 (RXDFE_OS_CFG1_REG),
.RXDFE_UT_CFG0 (RXDFE_UT_CFG0_REG),
.RXDFE_UT_CFG1 (RXDFE_UT_CFG1_REG),
.RXDFE_UT_CFG2 (RXDFE_UT_CFG2_REG),
.RXDFE_VP_CFG0 (RXDFE_VP_CFG0_REG),
.RXDFE_VP_CFG1 (RXDFE_VP_CFG1_REG),
.RXDLY_CFG (RXDLY_CFG_REG),
.RXDLY_LCFG (RXDLY_LCFG_REG),
.RXELECIDLE_CFG (RXELECIDLE_CFG_REG),
.RXGBOX_FIFO_INIT_RD_ADDR (RXGBOX_FIFO_INIT_RD_ADDR_REG),
.RXGEARBOX_EN (RXGEARBOX_EN_REG),
.RXISCANRESET_TIME (RXISCANRESET_TIME_REG),
.RXLPM_CFG (RXLPM_CFG_REG),
.RXLPM_GC_CFG (RXLPM_GC_CFG_REG),
.RXLPM_KH_CFG0 (RXLPM_KH_CFG0_REG),
.RXLPM_KH_CFG1 (RXLPM_KH_CFG1_REG),
.RXLPM_OS_CFG0 (RXLPM_OS_CFG0_REG),
.RXLPM_OS_CFG1 (RXLPM_OS_CFG1_REG),
.RXOOB_CFG (RXOOB_CFG_REG),
.RXOOB_CLK_CFG (RXOOB_CLK_CFG_REG),
.RXOSCALRESET_TIME (RXOSCALRESET_TIME_REG),
.RXOUT_DIV (RXOUT_DIV_REG),
.RXPCSRESET_TIME (RXPCSRESET_TIME_REG),
.RXPHBEACON_CFG (RXPHBEACON_CFG_REG),
.RXPHDLY_CFG (RXPHDLY_CFG_REG),
.RXPHSAMP_CFG (RXPHSAMP_CFG_REG),
.RXPHSLIP_CFG (RXPHSLIP_CFG_REG),
.RXPH_MONITOR_SEL (RXPH_MONITOR_SEL_REG),
.RXPI_CFG0 (RXPI_CFG0_REG),
.RXPI_CFG1 (RXPI_CFG1_REG),
.RXPMACLK_SEL (RXPMACLK_SEL_REG),
.RXPMARESET_TIME (RXPMARESET_TIME_REG),
.RXPRBS_ERR_LOOPBACK (RXPRBS_ERR_LOOPBACK_REG),
.RXPRBS_LINKACQ_CNT (RXPRBS_LINKACQ_CNT_REG),
.RXREFCLKDIV2_SEL (RXREFCLKDIV2_SEL_REG),
.RXSLIDE_AUTO_WAIT (RXSLIDE_AUTO_WAIT_REG),
.RXSLIDE_MODE (RXSLIDE_MODE_REG),
.RXSYNC_MULTILANE (RXSYNC_MULTILANE_REG),
.RXSYNC_OVRD (RXSYNC_OVRD_REG),
.RXSYNC_SKIP_DA (RXSYNC_SKIP_DA_REG),
.RX_AFE_CM_EN (RX_AFE_CM_EN_REG),
.RX_BIAS_CFG0 (RX_BIAS_CFG0_REG),
.RX_BUFFER_CFG (RX_BUFFER_CFG_REG),
.RX_CAPFF_SARC_ENB (RX_CAPFF_SARC_ENB_REG),
.RX_CLK25_DIV (RX_CLK25_DIV_REG),
.RX_CLKMUX_EN (RX_CLKMUX_EN_REG),
.RX_CLK_SLIP_OVRD (RX_CLK_SLIP_OVRD_REG),
.RX_CM_BUF_CFG (RX_CM_BUF_CFG_REG),
.RX_CM_BUF_PD (RX_CM_BUF_PD_REG),
.RX_CM_SEL (RX_CM_SEL_REG),
.RX_CM_TRIM (RX_CM_TRIM_REG),
.RX_CTLE_PWR_SAVING (RX_CTLE_PWR_SAVING_REG),
.RX_CTLE_RES_CTRL (RX_CTLE_RES_CTRL_REG),
.RX_DATA_WIDTH (RX_DATA_WIDTH_REG),
.RX_DDI_SEL (RX_DDI_SEL_REG),
.RX_DEFER_RESET_BUF_EN (RX_DEFER_RESET_BUF_EN_REG),
.RX_DEGEN_CTRL (RX_DEGEN_CTRL_REG),
.RX_DFECFOKFCDAC (RX_DFECFOKFCDAC_REG),
.RX_DFELPM_CFG0 (RX_DFELPM_CFG0_REG),
.RX_DFELPM_CFG1 (RX_DFELPM_CFG1_REG),
.RX_DFELPM_KLKH_AGC_STUP_EN (RX_DFELPM_KLKH_AGC_STUP_EN_REG),
.RX_DFE_AGC_CFG1 (RX_DFE_AGC_CFG1_REG),
.RX_DFE_KL_LPM_KH_CFG0 (RX_DFE_KL_LPM_KH_CFG0_REG),
.RX_DFE_KL_LPM_KH_CFG1 (RX_DFE_KL_LPM_KH_CFG1_REG),
.RX_DFE_KL_LPM_KL_CFG0 (RX_DFE_KL_LPM_KL_CFG0_REG),
.RX_DFE_KL_LPM_KL_CFG1 (RX_DFE_KL_LPM_KL_CFG1_REG),
.RX_DFE_LPM_HOLD_DURING_EIDLE (RX_DFE_LPM_HOLD_DURING_EIDLE_REG),
.RX_DISPERR_SEQ_MATCH (RX_DISPERR_SEQ_MATCH_REG),
.RX_DIVRESET_TIME (RX_DIVRESET_TIME_REG),
.RX_EN_CTLE_RCAL_B (RX_EN_CTLE_RCAL_B_REG),
.RX_EN_SUM_RCAL_B (RX_EN_SUM_RCAL_B_REG),
.RX_EYESCAN_VS_CODE (RX_EYESCAN_VS_CODE_REG),
.RX_EYESCAN_VS_NEG_DIR (RX_EYESCAN_VS_NEG_DIR_REG),
.RX_EYESCAN_VS_RANGE (RX_EYESCAN_VS_RANGE_REG),
.RX_EYESCAN_VS_UT_SIGN (RX_EYESCAN_VS_UT_SIGN_REG),
.RX_FABINT_USRCLK_FLOP (RX_FABINT_USRCLK_FLOP_REG),
.RX_I2V_FILTER_EN (RX_I2V_FILTER_EN_REG),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH_REG),
.RX_PMA_POWER_SAVE (RX_PMA_POWER_SAVE_REG),
.RX_PMA_RSV0 (RX_PMA_RSV0_REG),
.RX_PROGDIV_CFG (RX_PROGDIV_CFG_BIN),
.RX_PROGDIV_RATE (RX_PROGDIV_RATE_REG),
.RX_RESLOAD_CTRL (RX_RESLOAD_CTRL_REG),
.RX_RESLOAD_OVRD (RX_RESLOAD_OVRD_REG),
.RX_SAMPLE_PERIOD (RX_SAMPLE_PERIOD_REG),
.RX_SIG_VALID_DLY (RX_SIG_VALID_DLY_REG),
.RX_SUM_DEGEN_AVTT_OVERITE (RX_SUM_DEGEN_AVTT_OVERITE_REG),
.RX_SUM_DFETAPREP_EN (RX_SUM_DFETAPREP_EN_REG),
.RX_SUM_IREF_TUNE (RX_SUM_IREF_TUNE_REG),
.RX_SUM_PWR_SAVING (RX_SUM_PWR_SAVING_REG),
.RX_SUM_RES_CTRL (RX_SUM_RES_CTRL_REG),
.RX_SUM_VCMTUNE (RX_SUM_VCMTUNE_REG),
.RX_SUM_VCM_BIAS_TUNE_EN (RX_SUM_VCM_BIAS_TUNE_EN_REG),
.RX_SUM_VCM_OVWR (RX_SUM_VCM_OVWR_REG),
.RX_SUM_VREF_TUNE (RX_SUM_VREF_TUNE_REG),
.RX_TUNE_AFE_OS (RX_TUNE_AFE_OS_REG),
.RX_VREG_CTRL (RX_VREG_CTRL_REG),
.RX_VREG_PDB (RX_VREG_PDB_REG),
.RX_VREG_VREFSEL (RX_VREG_VREFSEL_REG),
.RX_WIDEMODE_CDR (RX_WIDEMODE_CDR_REG),
.RX_WIDEMODE_CDR_GEN3 (RX_WIDEMODE_CDR_GEN3_REG),
.RX_WIDEMODE_CDR_GEN4 (RX_WIDEMODE_CDR_GEN4_REG),
.RX_XCLK_SEL (RX_XCLK_SEL_REG),
.RX_XMODE_SEL (RX_XMODE_SEL_REG),
.SAMPLE_CLK_PHASE (SAMPLE_CLK_PHASE_REG),
.SAS_12G_MODE (SAS_12G_MODE_REG),
.SATA_BURST_SEQ_LEN (SATA_BURST_SEQ_LEN_REG),
.SATA_BURST_VAL (SATA_BURST_VAL_REG),
.SATA_CPLL_CFG (SATA_CPLL_CFG_REG),
.SATA_EIDLE_VAL (SATA_EIDLE_VAL_REG),
.SHOW_REALIGN_COMMA (SHOW_REALIGN_COMMA_REG),
.SIM_DEVICE (SIM_DEVICE_REG),
.SIM_MODE (SIM_MODE_REG),
.SIM_RECEIVER_DETECT_PASS (SIM_RECEIVER_DETECT_PASS_REG),
.SIM_RESET_SPEEDUP (SIM_RESET_SPEEDUP_REG),
.SIM_TX_EIDLE_DRIVE_LEVEL (SIM_TX_EIDLE_DRIVE_LEVEL_REG),
.SRSTMODE (SRSTMODE_REG),
.TAPDLY_SET_TX (TAPDLY_SET_TX_REG),
.TERM_RCAL_CFG (TERM_RCAL_CFG_REG),
.TERM_RCAL_OVRD (TERM_RCAL_OVRD_REG),
.TRANS_TIME_RATE (TRANS_TIME_RATE_REG),
.TST_RSV0 (TST_RSV0_REG),
.TST_RSV1 (TST_RSV1_REG),
.TXBUF_EN (TXBUF_EN_REG),
.TXBUF_RESET_ON_RATE_CHANGE (TXBUF_RESET_ON_RATE_CHANGE_REG),
.TXDLY_CFG (TXDLY_CFG_REG),
.TXDLY_LCFG (TXDLY_LCFG_REG),
.TXDRV_FREQBAND (TXDRV_FREQBAND_REG),
.TXFE_CFG0 (TXFE_CFG0_REG),
.TXFE_CFG1 (TXFE_CFG1_REG),
.TXFE_CFG2 (TXFE_CFG2_REG),
.TXFE_CFG3 (TXFE_CFG3_REG),
.TXFIFO_ADDR_CFG (TXFIFO_ADDR_CFG_REG),
.TXGBOX_FIFO_INIT_RD_ADDR (TXGBOX_FIFO_INIT_RD_ADDR_REG),
.TXGEARBOX_EN (TXGEARBOX_EN_REG),
.TXOUTCLKPCS_SEL (TXOUTCLKPCS_SEL_REG),
.TXOUT_DIV (TXOUT_DIV_REG),
.TXPCSRESET_TIME (TXPCSRESET_TIME_REG),
.TXPHDLY_CFG0 (TXPHDLY_CFG0_REG),
.TXPHDLY_CFG1 (TXPHDLY_CFG1_REG),
.TXPH_CFG (TXPH_CFG_REG),
.TXPH_CFG2 (TXPH_CFG2_REG),
.TXPH_MONITOR_SEL (TXPH_MONITOR_SEL_REG),
.TXPI_CFG0 (TXPI_CFG0_REG),
.TXPI_CFG1 (TXPI_CFG1_REG),
.TXPI_GRAY_SEL (TXPI_GRAY_SEL_REG),
.TXPI_INVSTROBE_SEL (TXPI_INVSTROBE_SEL_REG),
.TXPI_PPM (TXPI_PPM_REG),
.TXPI_PPM_CFG (TXPI_PPM_CFG_REG),
.TXPI_SYNFREQ_PPM (TXPI_SYNFREQ_PPM_REG),
.TXPMARESET_TIME (TXPMARESET_TIME_REG),
.TXREFCLKDIV2_SEL (TXREFCLKDIV2_SEL_REG),
.TXSWBST_BST (TXSWBST_BST_REG),
.TXSWBST_EN (TXSWBST_EN_REG),
.TXSWBST_MAG (TXSWBST_MAG_REG),
.TXSYNC_MULTILANE (TXSYNC_MULTILANE_REG),
.TXSYNC_OVRD (TXSYNC_OVRD_REG),
.TXSYNC_SKIP_DA (TXSYNC_SKIP_DA_REG),
.TX_CLK25_DIV (TX_CLK25_DIV_REG),
.TX_CLKMUX_EN (TX_CLKMUX_EN_REG),
.TX_DATA_WIDTH (TX_DATA_WIDTH_REG),
.TX_DCC_LOOP_RST_CFG (TX_DCC_LOOP_RST_CFG_REG),
.TX_DEEMPH0 (TX_DEEMPH0_REG),
.TX_DEEMPH1 (TX_DEEMPH1_REG),
.TX_DEEMPH2 (TX_DEEMPH2_REG),
.TX_DEEMPH3 (TX_DEEMPH3_REG),
.TX_DIVRESET_TIME (TX_DIVRESET_TIME_REG),
.TX_DRIVE_MODE (TX_DRIVE_MODE_REG),
.TX_EIDLE_ASSERT_DELAY (TX_EIDLE_ASSERT_DELAY_REG),
.TX_EIDLE_DEASSERT_DELAY (TX_EIDLE_DEASSERT_DELAY_REG),
.TX_FABINT_USRCLK_FLOP (TX_FABINT_USRCLK_FLOP_REG),
.TX_FIFO_BYP_EN (TX_FIFO_BYP_EN_REG),
.TX_IDLE_DATA_ZERO (TX_IDLE_DATA_ZERO_REG),
.TX_INT_DATAWIDTH (TX_INT_DATAWIDTH_REG),
.TX_LOOPBACK_DRIVE_HIZ (TX_LOOPBACK_DRIVE_HIZ_REG),
.TX_MAINCURSOR_SEL (TX_MAINCURSOR_SEL_REG),
.TX_MARGIN_FULL_0 (TX_MARGIN_FULL_0_REG),
.TX_MARGIN_FULL_1 (TX_MARGIN_FULL_1_REG),
.TX_MARGIN_FULL_2 (TX_MARGIN_FULL_2_REG),
.TX_MARGIN_FULL_3 (TX_MARGIN_FULL_3_REG),
.TX_MARGIN_FULL_4 (TX_MARGIN_FULL_4_REG),
.TX_MARGIN_LOW_0 (TX_MARGIN_LOW_0_REG),
.TX_MARGIN_LOW_1 (TX_MARGIN_LOW_1_REG),
.TX_MARGIN_LOW_2 (TX_MARGIN_LOW_2_REG),
.TX_MARGIN_LOW_3 (TX_MARGIN_LOW_3_REG),
.TX_MARGIN_LOW_4 (TX_MARGIN_LOW_4_REG),
.TX_PHICAL_CFG0 (TX_PHICAL_CFG0_REG),
.TX_PHICAL_CFG1 (TX_PHICAL_CFG1_REG),
.TX_PI_BIASSET (TX_PI_BIASSET_REG),
.TX_PMADATA_OPT (TX_PMADATA_OPT_REG),
.TX_PMA_POWER_SAVE (TX_PMA_POWER_SAVE_REG),
.TX_PMA_RSV0 (TX_PMA_RSV0_REG),
.TX_PMA_RSV1 (TX_PMA_RSV1_REG),
.TX_PROGCLK_SEL (TX_PROGCLK_SEL_REG),
.TX_PROGDIV_CFG (TX_PROGDIV_CFG_BIN),
.TX_PROGDIV_RATE (TX_PROGDIV_RATE_REG),
.TX_RXDETECT_CFG (TX_RXDETECT_CFG_REG),
.TX_RXDETECT_REF (TX_RXDETECT_REF_REG),
.TX_SAMPLE_PERIOD (TX_SAMPLE_PERIOD_REG),
.TX_SW_MEAS (TX_SW_MEAS_REG),
.TX_USERPATTERN_DATA0 (TX_USERPATTERN_DATA0_REG),
.TX_USERPATTERN_DATA1 (TX_USERPATTERN_DATA1_REG),
.TX_USERPATTERN_DATA2 (TX_USERPATTERN_DATA2_REG),
.TX_USERPATTERN_DATA3 (TX_USERPATTERN_DATA3_REG),
.TX_USERPATTERN_DATA4 (TX_USERPATTERN_DATA4_REG),
.TX_USERPATTERN_DATA5 (TX_USERPATTERN_DATA5_REG),
.TX_USERPATTERN_DATA6 (TX_USERPATTERN_DATA6_REG),
.TX_USERPATTERN_DATA7 (TX_USERPATTERN_DATA7_REG),
.TX_VREG_CTRL (TX_VREG_CTRL_REG),
.TX_VREG_PDB (TX_VREG_PDB_REG),
.TX_VREG_VREFSEL (TX_VREG_VREFSEL_REG),
.TX_XCLK_SEL (TX_XCLK_SEL_REG),
.USB_BOTH_BURST_IDLE (USB_BOTH_BURST_IDLE_REG),
.USB_BURSTMAX_U3WAKE (USB_BURSTMAX_U3WAKE_REG),
.USB_BURSTMIN_U3WAKE (USB_BURSTMIN_U3WAKE_REG),
.USB_CLK_COR_EQ_EN (USB_CLK_COR_EQ_EN_REG),
.USB_EXT_CNTL (USB_EXT_CNTL_REG),
.USB_IDLEMAX_POLLING (USB_IDLEMAX_POLLING_REG),
.USB_IDLEMIN_POLLING (USB_IDLEMIN_POLLING_REG),
.USB_LFPSPING_BURST (USB_LFPSPING_BURST_REG),
.USB_LFPSPOLLING_BURST (USB_LFPSPOLLING_BURST_REG),
.USB_LFPSPOLLING_IDLE_MS (USB_LFPSPOLLING_IDLE_MS_REG),
.USB_LFPSU1EXIT_BURST (USB_LFPSU1EXIT_BURST_REG),
.USB_LFPSU2LPEXIT_BURST_MS (USB_LFPSU2LPEXIT_BURST_MS_REG),
.USB_LFPSU3WAKE_BURST_MS (USB_LFPSU3WAKE_BURST_MS_REG),
.USB_LFPS_TPERIOD (USB_LFPS_TPERIOD_REG),
.USB_LFPS_TPERIOD_ACCURATE (USB_LFPS_TPERIOD_ACCURATE_REG),
.USB_MODE (USB_MODE_REG),
.USB_PCIE_ERR_REP_DIS (USB_PCIE_ERR_REP_DIS_REG),
.USB_PING_SATA_MAX_INIT (USB_PING_SATA_MAX_INIT_REG),
.USB_PING_SATA_MIN_INIT (USB_PING_SATA_MIN_INIT_REG),
.USB_POLL_SATA_MAX_BURST (USB_POLL_SATA_MAX_BURST_REG),
.USB_POLL_SATA_MIN_BURST (USB_POLL_SATA_MIN_BURST_REG),
.USB_RAW_ELEC (USB_RAW_ELEC_REG),
.USB_RXIDLE_P0_CTRL (USB_RXIDLE_P0_CTRL_REG),
.USB_TXIDLE_TUNE_ENABLE (USB_TXIDLE_TUNE_ENABLE_REG),
.USB_U1_SATA_MAX_WAKE (USB_U1_SATA_MAX_WAKE_REG),
.USB_U1_SATA_MIN_WAKE (USB_U1_SATA_MIN_WAKE_REG),
.USB_U2_SAS_MAX_COM (USB_U2_SAS_MAX_COM_REG),
.USB_U2_SAS_MIN_COM (USB_U2_SAS_MIN_COM_REG),
.USE_PCS_CLK_PHASE_SEL (USE_PCS_CLK_PHASE_SEL_REG),
.Y_ALL_MODE (Y_ALL_MODE_REG),
.BUFGTCE (BUFGTCE_out),
.BUFGTCEMASK (BUFGTCEMASK_out),
.BUFGTDIV (BUFGTDIV_out),
.BUFGTRESET (BUFGTRESET_out),
.BUFGTRSTMASK (BUFGTRSTMASK_out),
.CPLLFBCLKLOST (CPLLFBCLKLOST_out),
.CPLLLOCK (CPLLLOCK_out),
.CPLLREFCLKLOST (CPLLREFCLKLOST_out),
.CSSDSTOPCLKDONE (CSSDSTOPCLKDONE_out),
.DMONITOROUT (DMONITOROUT_out),
.DMONITOROUTCLK (DMONITOROUTCLK_out),
.DRPDO (DRPDO_out),
.DRPRDY (DRPRDY_out),
.EYESCANDATAERROR (EYESCANDATAERROR_out),
.GTPOWERGOOD (GTPOWERGOOD_out),
.GTREFCLKMONITOR (GTREFCLKMONITOR_out),
.GTYTXN (GTYTXN_out),
.GTYTXP (GTYTXP_out),
.PCIERATEGEN3 (PCIERATEGEN3_out),
.PCIERATEIDLE (PCIERATEIDLE_out),
.PCIERATEQPLLPD (PCIERATEQPLLPD_out),
.PCIERATEQPLLRESET (PCIERATEQPLLRESET_out),
.PCIESYNCTXSYNCDONE (PCIESYNCTXSYNCDONE_out),
.PCIEUSERGEN3RDY (PCIEUSERGEN3RDY_out),
.PCIEUSERPHYSTATUSRST (PCIEUSERPHYSTATUSRST_out),
.PCIEUSERRATESTART (PCIEUSERRATESTART_out),
.PCSRSVDOUT (PCSRSVDOUT_out),
.PHYSTATUS (PHYSTATUS_out),
.PINRSRVDAS (PINRSRVDAS_out),
.PMASCANOUT (PMASCANOUT_out),
.POWERPRESENT (POWERPRESENT_out),
.RESETEXCEPTION (RESETEXCEPTION_out),
.RXBUFSTATUS (RXBUFSTATUS_out),
.RXBYTEISALIGNED (RXBYTEISALIGNED_out),
.RXBYTEREALIGN (RXBYTEREALIGN_out),
.RXCDRLOCK (RXCDRLOCK_out),
.RXCDRPHDONE (RXCDRPHDONE_out),
.RXCHANBONDSEQ (RXCHANBONDSEQ_out),
.RXCHANISALIGNED (RXCHANISALIGNED_out),
.RXCHANREALIGN (RXCHANREALIGN_out),
.RXCHBONDO (RXCHBONDO_out),
.RXCKCALDONE (RXCKCALDONE_out),
.RXCLKCORCNT (RXCLKCORCNT_out),
.RXCOMINITDET (RXCOMINITDET_out),
.RXCOMMADET (RXCOMMADET_out),
.RXCOMSASDET (RXCOMSASDET_out),
.RXCOMWAKEDET (RXCOMWAKEDET_out),
.RXCTRL0 (RXCTRL0_out),
.RXCTRL1 (RXCTRL1_out),
.RXCTRL2 (RXCTRL2_out),
.RXCTRL3 (RXCTRL3_out),
.RXDATA (RXDATA_out),
.RXDATAEXTENDRSVD (RXDATAEXTENDRSVD_out),
.RXDATAVALID (RXDATAVALID_out),
.RXDLYSRESETDONE (RXDLYSRESETDONE_out),
.RXELECIDLE (RXELECIDLE_out),
.RXHEADER (RXHEADER_out),
.RXHEADERVALID (RXHEADERVALID_out),
.RXLFPSTRESETDET (RXLFPSTRESETDET_out),
.RXLFPSU2LPEXITDET (RXLFPSU2LPEXITDET_out),
.RXLFPSU3WAKEDET (RXLFPSU3WAKEDET_out),
.RXMONITOROUT (RXMONITOROUT_out),
.RXOSINTDONE (RXOSINTDONE_out),
.RXOSINTSTARTED (RXOSINTSTARTED_out),
.RXOSINTSTROBEDONE (RXOSINTSTROBEDONE_out),
.RXOSINTSTROBESTARTED (RXOSINTSTROBESTARTED_out),
.RXOUTCLK (RXOUTCLK_out),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC_out),
.RXOUTCLKPCS (RXOUTCLKPCS_out),
.RXPHALIGNDONE (RXPHALIGNDONE_out),
.RXPHALIGNERR (RXPHALIGNERR_out),
.RXPMARESETDONE (RXPMARESETDONE_out),
.RXPRBSERR (RXPRBSERR_out),
.RXPRBSLOCKED (RXPRBSLOCKED_out),
.RXPRGDIVRESETDONE (RXPRGDIVRESETDONE_out),
.RXRATEDONE (RXRATEDONE_out),
.RXRECCLKOUT (RXRECCLKOUT_out),
.RXRESETDONE (RXRESETDONE_out),
.RXSLIDERDY (RXSLIDERDY_out),
.RXSLIPDONE (RXSLIPDONE_out),
.RXSLIPOUTCLKRDY (RXSLIPOUTCLKRDY_out),
.RXSLIPPMARDY (RXSLIPPMARDY_out),
.RXSTARTOFSEQ (RXSTARTOFSEQ_out),
.RXSTATUS (RXSTATUS_out),
.RXSYNCDONE (RXSYNCDONE_out),
.RXSYNCOUT (RXSYNCOUT_out),
.RXVALID (RXVALID_out),
.SCANOUT (SCANOUT_out),
.TXBUFSTATUS (TXBUFSTATUS_out),
.TXCOMFINISH (TXCOMFINISH_out),
.TXDCCDONE (TXDCCDONE_out),
.TXDLYSRESETDONE (TXDLYSRESETDONE_out),
.TXOUTCLK (TXOUTCLK_out),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC_out),
.TXOUTCLKPCS (TXOUTCLKPCS_out),
.TXPHALIGNDONE (TXPHALIGNDONE_out),
.TXPHINITDONE (TXPHINITDONE_out),
.TXPMARESETDONE (TXPMARESETDONE_out),
.TXPRGDIVRESETDONE (TXPRGDIVRESETDONE_out),
.TXRATEDONE (TXRATEDONE_out),
.TXRESETDONE (TXRESETDONE_out),
.TXSYNCDONE (TXSYNCDONE_out),
.TXSYNCOUT (TXSYNCOUT_out),
.BSR_SERIAL (BSR_SERIAL_in),
.CDRSTEPDIR (CDRSTEPDIR_in),
.CDRSTEPSQ (CDRSTEPSQ_in),
.CDRSTEPSX (CDRSTEPSX_in),
.CFGRESET (CFGRESET_in),
.CLKRSVD0 (CLKRSVD0_in),
.CLKRSVD1 (CLKRSVD1_in),
.CPLLFREQLOCK (CPLLFREQLOCK_in),
.CPLLLOCKDETCLK (CPLLLOCKDETCLK_in),
.CPLLLOCKEN (CPLLLOCKEN_in),
.CPLLPD (CPLLPD_in),
.CPLLREFCLKSEL (CPLLREFCLKSEL_in),
.CPLLRESET (CPLLRESET_in),
.CSSDRSTB (CSSDRSTB_in),
.CSSDSTOPCLK (CSSDSTOPCLK_in),
.DMONFIFORESET (DMONFIFORESET_in),
.DMONITORCLK (DMONITORCLK_in),
.DRPADDR (DRPADDR_in),
.DRPCLK (DRPCLK_in),
.DRPDI (DRPDI_in),
.DRPEN (DRPEN_in),
.DRPRST (DRPRST_in),
.DRPWE (DRPWE_in),
.EYESCANRESET (EYESCANRESET_in),
.EYESCANTRIGGER (EYESCANTRIGGER_in),
.FREQOS (FREQOS_in),
.GTGREFCLK (GTGREFCLK_in),
.GTNORTHREFCLK0 (GTNORTHREFCLK0_in),
.GTNORTHREFCLK1 (GTNORTHREFCLK1_in),
.GTREFCLK0 (GTREFCLK0_in),
.GTREFCLK1 (GTREFCLK1_in),
.GTRSVD (GTRSVD_in),
.GTRXRESET (GTRXRESET_in),
.GTRXRESETSEL (GTRXRESETSEL_in),
.GTSOUTHREFCLK0 (GTSOUTHREFCLK0_in),
.GTSOUTHREFCLK1 (GTSOUTHREFCLK1_in),
.GTTXRESET (GTTXRESET_in),
.GTTXRESETSEL (GTTXRESETSEL_in),
.GTYRXN (GTYRXN_in),
.GTYRXP (GTYRXP_in),
.INCPCTRL (INCPCTRL_in),
.LOOPBACK (LOOPBACK_in),
.PCIEEQRXEQADAPTDONE (PCIEEQRXEQADAPTDONE_in),
.PCIERSTIDLE (PCIERSTIDLE_in),
.PCIERSTTXSYNCSTART (PCIERSTTXSYNCSTART_in),
.PCIEUSERRATEDONE (PCIEUSERRATEDONE_in),
.PCSRSVDIN (PCSRSVDIN_in),
.PMASCANCLK0 (PMASCANCLK0_in),
.PMASCANCLK1 (PMASCANCLK1_in),
.PMASCANCLK2 (PMASCANCLK2_in),
.PMASCANCLK3 (PMASCANCLK3_in),
.PMASCANCLK4 (PMASCANCLK4_in),
.PMASCANCLK5 (PMASCANCLK5_in),
.PMASCANCLK6 (PMASCANCLK6_in),
.PMASCANCLK7 (PMASCANCLK7_in),
.PMASCANCLK8 (PMASCANCLK8_in),
.PMASCANENB (PMASCANENB_in),
.PMASCANIN (PMASCANIN_in),
.PMASCANMODEB (PMASCANMODEB_in),
.PMASCANRSTEN (PMASCANRSTEN_in),
.QPLL0CLK (QPLL0CLK_in),
.QPLL0FREQLOCK (QPLL0FREQLOCK_in),
.QPLL0REFCLK (QPLL0REFCLK_in),
.QPLL1CLK (QPLL1CLK_in),
.QPLL1FREQLOCK (QPLL1FREQLOCK_in),
.QPLL1REFCLK (QPLL1REFCLK_in),
.RESETOVRD (RESETOVRD_in),
.RX8B10BEN (RX8B10BEN_in),
.RXAFECFOKEN (RXAFECFOKEN_in),
.RXBUFRESET (RXBUFRESET_in),
.RXCDRFREQRESET (RXCDRFREQRESET_in),
.RXCDRHOLD (RXCDRHOLD_in),
.RXCDROVRDEN (RXCDROVRDEN_in),
.RXCDRRESET (RXCDRRESET_in),
.RXCHBONDEN (RXCHBONDEN_in),
.RXCHBONDI (RXCHBONDI_in),
.RXCHBONDLEVEL (RXCHBONDLEVEL_in),
.RXCHBONDMASTER (RXCHBONDMASTER_in),
.RXCHBONDSLAVE (RXCHBONDSLAVE_in),
.RXCKCALRESET (RXCKCALRESET_in),
.RXCKCALSTART (RXCKCALSTART_in),
.RXCOMMADETEN (RXCOMMADETEN_in),
.RXDFEAGCHOLD (RXDFEAGCHOLD_in),
.RXDFEAGCOVRDEN (RXDFEAGCOVRDEN_in),
.RXDFECFOKFCNUM (RXDFECFOKFCNUM_in),
.RXDFECFOKFEN (RXDFECFOKFEN_in),
.RXDFECFOKFPULSE (RXDFECFOKFPULSE_in),
.RXDFECFOKHOLD (RXDFECFOKHOLD_in),
.RXDFECFOKOVREN (RXDFECFOKOVREN_in),
.RXDFEKHHOLD (RXDFEKHHOLD_in),
.RXDFEKHOVRDEN (RXDFEKHOVRDEN_in),
.RXDFELFHOLD (RXDFELFHOLD_in),
.RXDFELFOVRDEN (RXDFELFOVRDEN_in),
.RXDFELPMRESET (RXDFELPMRESET_in),
.RXDFETAP10HOLD (RXDFETAP10HOLD_in),
.RXDFETAP10OVRDEN (RXDFETAP10OVRDEN_in),
.RXDFETAP11HOLD (RXDFETAP11HOLD_in),
.RXDFETAP11OVRDEN (RXDFETAP11OVRDEN_in),
.RXDFETAP12HOLD (RXDFETAP12HOLD_in),
.RXDFETAP12OVRDEN (RXDFETAP12OVRDEN_in),
.RXDFETAP13HOLD (RXDFETAP13HOLD_in),
.RXDFETAP13OVRDEN (RXDFETAP13OVRDEN_in),
.RXDFETAP14HOLD (RXDFETAP14HOLD_in),
.RXDFETAP14OVRDEN (RXDFETAP14OVRDEN_in),
.RXDFETAP15HOLD (RXDFETAP15HOLD_in),
.RXDFETAP15OVRDEN (RXDFETAP15OVRDEN_in),
.RXDFETAP2HOLD (RXDFETAP2HOLD_in),
.RXDFETAP2OVRDEN (RXDFETAP2OVRDEN_in),
.RXDFETAP3HOLD (RXDFETAP3HOLD_in),
.RXDFETAP3OVRDEN (RXDFETAP3OVRDEN_in),
.RXDFETAP4HOLD (RXDFETAP4HOLD_in),
.RXDFETAP4OVRDEN (RXDFETAP4OVRDEN_in),
.RXDFETAP5HOLD (RXDFETAP5HOLD_in),
.RXDFETAP5OVRDEN (RXDFETAP5OVRDEN_in),
.RXDFETAP6HOLD (RXDFETAP6HOLD_in),
.RXDFETAP6OVRDEN (RXDFETAP6OVRDEN_in),
.RXDFETAP7HOLD (RXDFETAP7HOLD_in),
.RXDFETAP7OVRDEN (RXDFETAP7OVRDEN_in),
.RXDFETAP8HOLD (RXDFETAP8HOLD_in),
.RXDFETAP8OVRDEN (RXDFETAP8OVRDEN_in),
.RXDFETAP9HOLD (RXDFETAP9HOLD_in),
.RXDFETAP9OVRDEN (RXDFETAP9OVRDEN_in),
.RXDFEUTHOLD (RXDFEUTHOLD_in),
.RXDFEUTOVRDEN (RXDFEUTOVRDEN_in),
.RXDFEVPHOLD (RXDFEVPHOLD_in),
.RXDFEVPOVRDEN (RXDFEVPOVRDEN_in),
.RXDFEXYDEN (RXDFEXYDEN_in),
.RXDLYBYPASS (RXDLYBYPASS_in),
.RXDLYEN (RXDLYEN_in),
.RXDLYOVRDEN (RXDLYOVRDEN_in),
.RXDLYSRESET (RXDLYSRESET_in),
.RXELECIDLEMODE (RXELECIDLEMODE_in),
.RXEQTRAINING (RXEQTRAINING_in),
.RXGEARBOXSLIP (RXGEARBOXSLIP_in),
.RXLATCLK (RXLATCLK_in),
.RXLPMEN (RXLPMEN_in),
.RXLPMGCHOLD (RXLPMGCHOLD_in),
.RXLPMGCOVRDEN (RXLPMGCOVRDEN_in),
.RXLPMHFHOLD (RXLPMHFHOLD_in),
.RXLPMHFOVRDEN (RXLPMHFOVRDEN_in),
.RXLPMLFHOLD (RXLPMLFHOLD_in),
.RXLPMLFKLOVRDEN (RXLPMLFKLOVRDEN_in),
.RXLPMOSHOLD (RXLPMOSHOLD_in),
.RXLPMOSOVRDEN (RXLPMOSOVRDEN_in),
.RXMCOMMAALIGNEN (RXMCOMMAALIGNEN_in),
.RXMONITORSEL (RXMONITORSEL_in),
.RXOOBRESET (RXOOBRESET_in),
.RXOSCALRESET (RXOSCALRESET_in),
.RXOSHOLD (RXOSHOLD_in),
.RXOSOVRDEN (RXOSOVRDEN_in),
.RXOUTCLKSEL (RXOUTCLKSEL_in),
.RXPCOMMAALIGNEN (RXPCOMMAALIGNEN_in),
.RXPCSRESET (RXPCSRESET_in),
.RXPD (RXPD_in),
.RXPHALIGN (RXPHALIGN_in),
.RXPHALIGNEN (RXPHALIGNEN_in),
.RXPHDLYPD (RXPHDLYPD_in),
.RXPHDLYRESET (RXPHDLYRESET_in),
.RXPLLCLKSEL (RXPLLCLKSEL_in),
.RXPMARESET (RXPMARESET_in),
.RXPOLARITY (RXPOLARITY_in),
.RXPRBSCNTRESET (RXPRBSCNTRESET_in),
.RXPRBSSEL (RXPRBSSEL_in),
.RXPROGDIVRESET (RXPROGDIVRESET_in),
.RXRATE (RXRATE_in),
.RXRATEMODE (RXRATEMODE_in),
.RXSLIDE (RXSLIDE_in),
.RXSLIPOUTCLK (RXSLIPOUTCLK_in),
.RXSLIPPMA (RXSLIPPMA_in),
.RXSYNCALLIN (RXSYNCALLIN_in),
.RXSYNCIN (RXSYNCIN_in),
.RXSYNCMODE (RXSYNCMODE_in),
.RXSYSCLKSEL (RXSYSCLKSEL_in),
.RXTERMINATION (RXTERMINATION_in),
.RXUSERRDY (RXUSERRDY_in),
.RXUSRCLK (RXUSRCLK_in),
.RXUSRCLK2 (RXUSRCLK2_in),
.SARCCLK (SARCCLK_in),
.SCANCLK (SCANCLK_in),
.SCANENB (SCANENB_in),
.SCANIN (SCANIN_in),
.SCANMODEB (SCANMODEB_in),
.SCANRSTB (SCANRSTB_in),
.SCANRSTEN (SCANRSTEN_in),
.SIGVALIDCLK (SIGVALIDCLK_in),
.TSTCLK0 (TSTCLK0_in),
.TSTCLK1 (TSTCLK1_in),
.TSTIN (TSTIN_in),
.TSTPD (TSTPD_in),
.TSTPDOVRDB (TSTPDOVRDB_in),
.TX8B10BBYPASS (TX8B10BBYPASS_in),
.TX8B10BEN (TX8B10BEN_in),
.TXCOMINIT (TXCOMINIT_in),
.TXCOMSAS (TXCOMSAS_in),
.TXCOMWAKE (TXCOMWAKE_in),
.TXCTRL0 (TXCTRL0_in),
.TXCTRL1 (TXCTRL1_in),
.TXCTRL2 (TXCTRL2_in),
.TXDATA (TXDATA_in),
.TXDATAEXTENDRSVD (TXDATAEXTENDRSVD_in),
.TXDCCFORCESTART (TXDCCFORCESTART_in),
.TXDCCRESET (TXDCCRESET_in),
.TXDEEMPH (TXDEEMPH_in),
.TXDETECTRX (TXDETECTRX_in),
.TXDIFFCTRL (TXDIFFCTRL_in),
.TXDLYBYPASS (TXDLYBYPASS_in),
.TXDLYEN (TXDLYEN_in),
.TXDLYHOLD (TXDLYHOLD_in),
.TXDLYOVRDEN (TXDLYOVRDEN_in),
.TXDLYSRESET (TXDLYSRESET_in),
.TXDLYUPDOWN (TXDLYUPDOWN_in),
.TXELECIDLE (TXELECIDLE_in),
.TXHEADER (TXHEADER_in),
.TXINHIBIT (TXINHIBIT_in),
.TXLATCLK (TXLATCLK_in),
.TXLFPSTRESET (TXLFPSTRESET_in),
.TXLFPSU2LPEXIT (TXLFPSU2LPEXIT_in),
.TXLFPSU3WAKE (TXLFPSU3WAKE_in),
.TXMAINCURSOR (TXMAINCURSOR_in),
.TXMARGIN (TXMARGIN_in),
.TXMUXDCDEXHOLD (TXMUXDCDEXHOLD_in),
.TXMUXDCDORWREN (TXMUXDCDORWREN_in),
.TXONESZEROS (TXONESZEROS_in),
.TXOUTCLKSEL (TXOUTCLKSEL_in),
.TXPCSRESET (TXPCSRESET_in),
.TXPD (TXPD_in),
.TXPDELECIDLEMODE (TXPDELECIDLEMODE_in),
.TXPHALIGN (TXPHALIGN_in),
.TXPHALIGNEN (TXPHALIGNEN_in),
.TXPHDLYPD (TXPHDLYPD_in),
.TXPHDLYRESET (TXPHDLYRESET_in),
.TXPHDLYTSTCLK (TXPHDLYTSTCLK_in),
.TXPHINIT (TXPHINIT_in),
.TXPHOVRDEN (TXPHOVRDEN_in),
.TXPIPPMEN (TXPIPPMEN_in),
.TXPIPPMOVRDEN (TXPIPPMOVRDEN_in),
.TXPIPPMPD (TXPIPPMPD_in),
.TXPIPPMSEL (TXPIPPMSEL_in),
.TXPIPPMSTEPSIZE (TXPIPPMSTEPSIZE_in),
.TXPISOPD (TXPISOPD_in),
.TXPLLCLKSEL (TXPLLCLKSEL_in),
.TXPMARESET (TXPMARESET_in),
.TXPOLARITY (TXPOLARITY_in),
.TXPOSTCURSOR (TXPOSTCURSOR_in),
.TXPRBSFORCEERR (TXPRBSFORCEERR_in),
.TXPRBSSEL (TXPRBSSEL_in),
.TXPRECURSOR (TXPRECURSOR_in),
.TXPROGDIVRESET (TXPROGDIVRESET_in),
.TXRATE (TXRATE_in),
.TXRATEMODE (TXRATEMODE_in),
.TXSEQUENCE (TXSEQUENCE_in),
.TXSWING (TXSWING_in),
.TXSYNCALLIN (TXSYNCALLIN_in),
.TXSYNCIN (TXSYNCIN_in),
.TXSYNCMODE (TXSYNCMODE_in),
.TXSYSCLKSEL (TXSYSCLKSEL_in),
.TXUSERRDY (TXUSERRDY_in),
.TXUSRCLK (TXUSRCLK_in),
.TXUSRCLK2 (TXUSRCLK2_in),
.GSR (glblGSR)
);
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
reg notifier;
`endif
specify
(DMONITORCLK => DMONITOROUT[0]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[10]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[11]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[12]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[13]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[14]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[15]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[1]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[2]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[3]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[4]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[5]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[6]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[7]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[8]) = (0:0:0, 0:0:0);
(DMONITORCLK => DMONITOROUT[9]) = (0:0:0, 0:0:0);
(DRPCLK => DMONITOROUTCLK) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[0]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[10]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[11]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[12]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[13]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[14]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[15]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[1]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[2]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[3]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[4]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[5]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[6]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[7]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[8]) = (100:100:100, 100:100:100);
(DRPCLK => DRPDO[9]) = (100:100:100, 100:100:100);
(DRPCLK => DRPRDY) = (100:100:100, 100:100:100);
(DRPCLK => RXLFPSTRESETDET) = (100:100:100, 100:100:100);
(GTGREFCLK => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTNORTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK0 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(GTSOUTHREFCLK1 => GTREFCLKMONITOR) = (0:0:0, 0:0:0);
(RXUSRCLK => RXCHBONDO[0]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[1]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[2]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[3]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXCHBONDO[4]) = (100:100:100, 100:100:100);
(RXUSRCLK => RXLFPSTRESETDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => PHYSTATUS) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBUFSTATUS[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBUFSTATUS[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBUFSTATUS[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBYTEISALIGNED) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXBYTEREALIGN) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHANBONDSEQ) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHANISALIGNED) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHANREALIGN) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCHBONDO[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCLKCORCNT[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCLKCORCNT[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMINITDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMMADET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMSASDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCOMWAKEDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[10]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[11]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[12]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[13]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[14]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[15]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[8]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL0[9]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[10]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[11]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[12]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[13]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[14]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[15]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[8]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL1[9]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL2[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXCTRL3[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATAVALID[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATAVALID[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[100]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[101]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[102]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[103]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[104]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[105]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[106]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[107]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[108]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[109]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[10]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[110]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[111]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[112]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[113]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[114]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[115]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[116]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[117]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[118]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[119]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[11]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[120]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[121]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[122]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[123]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[124]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[125]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[126]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[127]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[12]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[13]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[14]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[15]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[16]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[17]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[18]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[19]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[20]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[21]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[22]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[23]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[24]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[25]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[26]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[27]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[28]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[29]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[30]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[31]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[32]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[33]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[34]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[35]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[36]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[37]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[38]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[39]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[40]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[41]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[42]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[43]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[44]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[45]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[46]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[47]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[48]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[49]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[50]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[51]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[52]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[53]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[54]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[55]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[56]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[57]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[58]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[59]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[60]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[61]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[62]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[63]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[64]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[65]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[66]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[67]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[68]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[69]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[6]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[70]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[71]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[72]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[73]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[74]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[75]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[76]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[77]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[78]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[79]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[7]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[80]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[81]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[82]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[83]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[84]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[85]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[86]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[87]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[88]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[89]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[8]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[90]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[91]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[92]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[93]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[94]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[95]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[96]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[97]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[98]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[99]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXDATA[9]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADERVALID[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADERVALID[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[3]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[4]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXHEADER[5]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXLFPSTRESETDET) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXPRBSERR) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXPRBSLOCKED) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXRATEDONE) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXRESETDONE) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIDERDY) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIPDONE) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIPOUTCLKRDY) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSLIPPMARDY) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTARTOFSEQ[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTARTOFSEQ[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTATUS[0]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTATUS[1]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXSTATUS[2]) = (100:100:100, 100:100:100);
(RXUSRCLK2 => RXVALID) = (100:100:100, 100:100:100);
(TXUSRCLK => RXLFPSTRESETDET) = (0:0:0, 0:0:0);
(TXUSRCLK2 => RXLFPSTRESETDET) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXBUFSTATUS[0]) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXBUFSTATUS[1]) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXCOMFINISH) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXRATEDONE) = (100:100:100, 100:100:100);
(TXUSRCLK2 => TXRESETDONE) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge DRPCLK, 0:0:0, notifier);
$period (negedge RXUSRCLK, 0:0:0, notifier);
$period (negedge RXUSRCLK2, 0:0:0, notifier);
$period (negedge TXUSRCLK, 0:0:0, notifier);
$period (negedge TXUSRCLK2, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK, 0:0:0, notifier);
$period (posedge RXUSRCLK2, 0:0:0, notifier);
$period (posedge TXUSRCLK, 0:0:0, notifier);
$period (posedge TXUSRCLK2, 0:0:0, notifier);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPADDR_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPDI_delay[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPEN_delay);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier, , , DRPCLK_delay, DRPWE_delay);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, negedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, negedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, negedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, negedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge RXUSRCLK2, posedge RX8B10BEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RX8B10BEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[3], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[3]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDI[4], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDI_delay[4]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDLEVEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDLEVEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDMASTER, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDMASTER_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCHBONDSLAVE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCHBONDSLAVE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXCOMMADETEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXCOMMADETEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXGEARBOXSLIP, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXGEARBOXSLIP_delay);
$setuphold (posedge RXUSRCLK2, posedge RXMCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXMCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPCOMMAALIGNEN, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPCOMMAALIGNEN_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPOLARITY, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPOLARITY_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSCNTRESET, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSCNTRESET_delay);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXPRBSSEL_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[0], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[0]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[1], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[1]);
$setuphold (posedge RXUSRCLK2, posedge RXRATE[2], 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXRATE_delay[2]);
$setuphold (posedge RXUSRCLK2, posedge RXSLIDE, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIDE_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPOUTCLK, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPOUTCLK_delay);
$setuphold (posedge RXUSRCLK2, posedge RXSLIPPMA, 0:0:0, 0:0:0, notifier, , , RXUSRCLK2_delay, RXSLIPPMA_delay);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL0[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL1[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[112], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[112]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[113], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[113]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[114], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[114]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[115], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[115]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[116], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[116]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[117], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[117]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[118], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[118]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[119], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[119]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[120], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[120]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[121], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[121]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[122], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[122]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[123], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[123]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[124], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[124]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[125], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[125]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[126], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[126]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[127], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[127]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[64], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[64]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[65], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[65]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[66], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[66]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[67], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[67]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[68], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[68]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[69], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[69]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[70], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[70]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[71], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[71]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[72], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[72]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[73], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[73]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[74], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[74]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[75], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[75]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[76], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[76]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[77], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[77]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[78], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[78]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[79], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[79]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[80], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[80]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[81], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[81]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[82], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[82]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[83], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[83]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[84], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[84]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[85], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[85]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[86], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[86]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[87], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[87]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[88], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[88]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[89], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[89]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[90], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[90]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[91], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[91]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[92], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[92]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[93], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[93]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[94], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[94]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[95], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[95]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, negedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, negedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, negedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, negedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BBYPASS[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BBYPASS_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TX8B10BEN, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TX8B10BEN_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMINIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMINIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMSAS, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMSAS_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCOMWAKE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCOMWAKE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL0[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL0_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL1[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL1_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXCTRL2[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXCTRL2_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[100], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[100]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[101], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[101]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[102], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[102]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[103], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[103]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[104], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[104]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[105], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[105]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[106], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[106]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[107], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[107]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[108], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[108]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[109], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[109]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[10], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[10]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[110], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[110]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[111], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[111]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[112], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[112]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[113], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[113]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[114], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[114]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[115], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[115]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[116], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[116]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[117], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[117]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[118], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[118]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[119], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[119]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[11], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[11]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[120], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[120]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[121], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[121]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[122], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[122]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[123], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[123]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[124], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[124]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[125], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[125]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[126], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[126]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[127], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[127]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[12], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[12]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[13], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[13]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[14], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[14]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[15], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[15]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[16], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[16]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[17], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[17]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[18], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[18]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[19], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[19]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[20], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[20]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[21], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[21]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[22], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[22]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[23], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[23]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[24], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[24]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[25], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[25]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[26], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[26]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[27], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[27]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[28], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[28]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[29], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[29]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[30], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[30]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[31], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[31]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[32], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[32]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[33], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[33]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[34], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[34]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[35], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[35]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[36], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[36]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[37], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[37]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[38], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[38]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[39], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[39]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[40], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[40]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[41], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[41]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[42], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[42]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[43], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[43]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[44], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[44]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[45], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[45]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[46], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[46]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[47], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[47]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[48], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[48]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[49], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[49]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[50], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[50]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[51], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[51]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[52], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[52]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[53], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[53]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[54], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[54]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[55], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[55]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[56], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[56]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[57], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[57]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[58], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[58]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[59], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[59]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[60], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[60]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[61], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[61]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[62], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[62]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[63], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[63]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[64], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[64]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[65], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[65]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[66], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[66]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[67], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[67]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[68], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[68]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[69], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[69]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[6]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[70], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[70]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[71], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[71]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[72], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[72]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[73], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[73]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[74], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[74]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[75], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[75]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[76], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[76]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[77], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[77]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[78], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[78]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[79], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[79]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[7], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[7]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[80], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[80]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[81], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[81]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[82], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[82]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[83], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[83]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[84], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[84]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[85], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[85]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[86], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[86]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[87], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[87]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[88], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[88]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[89], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[89]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[8], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[8]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[90], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[90]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[91], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[91]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[92], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[92]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[93], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[93]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[94], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[94]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[95], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[95]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[96], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[96]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[97], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[97]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[98], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[98]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[99], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[99]);
$setuphold (posedge TXUSRCLK2, posedge TXDATA[9], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDATA_delay[9]);
$setuphold (posedge TXUSRCLK2, posedge TXDETECTRX, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXDETECTRX_delay);
$setuphold (posedge TXUSRCLK2, posedge TXELECIDLE, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXELECIDLE_delay);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXHEADER[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXHEADER_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXINHIBIT, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXINHIBIT_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPD[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPD[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPD_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPOLARITY, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPOLARITY_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSFORCEERR, 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSFORCEERR_delay);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXPRBSSEL[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXPRBSSEL_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXRATE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXRATE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[0], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[0]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[1], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[1]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[2], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[2]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[3], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[3]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[4], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[4]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[5], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[5]);
$setuphold (posedge TXUSRCLK2, posedge TXSEQUENCE[6], 0:0:0, 0:0:0, notifier, , , TXUSRCLK2_delay, TXSEQUENCE_delay[6]);
$width (negedge DRPCLK, 0:0:0, 0, notifier);
$width (negedge RXUSRCLK, 0:0:0, 0, notifier);
$width (negedge RXUSRCLK2, 0:0:0, 0, notifier);
$width (negedge TXUSRCLK, 0:0:0, 0, notifier);
$width (negedge TXUSRCLK2, 0:0:0, 0, notifier);
$width (posedge DRPCLK, 0:0:0, 0, notifier);
$width (posedge RXUSRCLK, 0:0:0, 0, notifier);
$width (posedge RXUSRCLK2, 0:0:0, 0, notifier);
$width (posedge TXUSRCLK, 0:0:0, 0, notifier);
$width (posedge TXUSRCLK2, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_PP_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output GCLK;
input GATE;
input CLK ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_PP_V |
`default_nettype none
module mist1032sa_arbiter_matching_queue #(
//Queue Deap
parameter D = 8,
//Queue Deap_N
parameter DN = 3,
//Queue Flag_N
parameter FN = 1
)(
input wire iCLOCK,
input wire inRESET,
//Flash
input wire iFLASH,
//Write
input wire iWR_REQ,
input wire [FN-1:0] iWR_FLAG,
output wire oWR_FULL,
//Read
input wire iRD_REQ,
output wire oRD_VALID,
output wire [FN-1:0] oRD_FLAG,
output wire oRD_EMPTY
);
/***********************************************************
Control
***********************************************************/
wire full_flag;
wire empty_flag;
wire [DN:0] count;
reg [DN:0] wr_counter;
reg [DN:0] rd_counter;
reg queue_valid[0:D-1];
reg [FN-1:0] queue_type[0:D-1];
integer i;
assign full_flag = count[DN];
assign empty_flag = (wr_counter == rd_counter)? 1'b1 : 1'b0;
assign count = wr_counter - rd_counter;
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
wr_counter <= {DN+1{1'b0}};
rd_counter <= {DN+1{1'b0}};
//Flag Clear
for(i = 0; i < D; i = i + 1)begin
queue_valid[i] <= 1'b0;
end
end
else begin
if(iFLASH)begin
//Flag Clear
for(i = 0; i < D; i = i + 1)begin
queue_valid[i] <= 1'b0;
end
end
//Prev -> Next
if(!full_flag && iWR_REQ)begin
wr_counter <= wr_counter + {{DN{1'b0}}, 1'b1};
queue_valid[wr_counter[DN-1:0]] <= 1'b1;
queue_type[wr_counter[DN-1:0]] <= iWR_FLAG;
end
//Next -> Data
if(!empty_flag && iRD_REQ)begin
rd_counter <= rd_counter + {{DN{1'b0}}, 1'b1};
queue_valid[rd_counter[DN-1:0]] <= 1'b0;
end
end
end
/***********************************************************
Output Assign
***********************************************************/
assign oWR_FULL = full_flag;
assign oRD_VALID = queue_valid[rd_counter[DN-1:0]] && !iFLASH;
assign oRD_FLAG = queue_type[rd_counter[DN-1:0]];
assign oRD_EMPTY = empty_flag;
endmodule
`default_nettype wire
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SEDFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__SEDFXBP_FUNCTIONAL_PP_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ms__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__sedfxbp (
Q ,
Q_N ,
CLK ,
D ,
DE ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input DE ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out;
wire de_d ;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD, SCE );
sky130_fd_sc_ms__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D, DE );
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , mux_out, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__SEDFXBP_FUNCTIONAL_PP_V |
`timescale 1ns/10ps
module VGA2Sim;
reg clock;
reg reset;
reg [11:0] inst;
reg inst_en;
wire vga_hsync;
wire vga_vsync;
wire vga_r;
wire vga_g;
wire vga_b;
initial begin
#0 $dumpfile(`VCDFILE);
#0 $dumpvars;
#100000 $finish;
end
initial begin
#0 clock = 1;
forever #2 clock = ~clock;
end
initial begin
#0 reset = 0;
#1 reset = 1;
#4 reset = 0;
end
initial begin
#0.1 inst_en = 0;
// Test each instruction.
#8 inst = {`VGA2_LDR,8'h00};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h20};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1100};
inst_en = 1;
#4 inst = {`VGA2_LDI,4'bxxxx,4'b1010};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test disabled instruction.
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1010};
inst_en = 0;
#4 inst = {`VGA2_LDR,8'h04};
inst_en = 1;
// Test bad instruction.
#4 inst = {8'hF,16'hBEEF};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h3F};
inst_en = 1;
#4 reset = 1;
#8 reset = 0;
#8 inst = {`VGA2_LDR,8'h00};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h20};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1100};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test writing to another row.
#8 inst = {`VGA2_LDR,8'h01};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h04};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b1010};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
// Test writing a less-intense value.
#8 inst = {`VGA2_LDR,8'h00};
inst_en = 1;
#4 inst = {`VGA2_LDC,8'h40};
inst_en = 1;
#4 inst = {`VGA2_LDD,4'bxxxx,4'b0110};
inst_en = 1;
#4 inst = {`VGA2_NOP,8'bxxxxxxxx};
inst_en = 1;
end // initial begin
VGA2
vga (.clock(clock),
.reset(reset),
.inst(inst),
.inst_en(inst_en),
.vga_hsync(vga_hsync),
.vga_vsync(vga_vsync),
.vga_r(vga_r),
.vga_g(vga_g),
.vga_b(vga_b));
endmodule // VGA2Sim
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__DECAP_8_V
`define SKY130_FD_SC_HVL__DECAP_8_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hvl__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hvl__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hvl__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HVL__DECAP_8_V
|
// Copyright (c) 2014 Takashi Toyoshima <[email protected]>.
// All rights reserved. Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.
`timescale 100ps/100ps
module SerialReceiverTest;
reg clk;
reg rst_x;
reg rx;
wire [7:0] w_data;
wire w_valid;
wire w_error;
always #4 clk = ~clk;
always @ (posedge w_valid) begin
$display("receive: $%02x", w_data);
end
always @ (posedge w_error) begin
$display("receive: can not detect stop bit");
end
SerialReceiver dut(
.clk_x4 (clk ),
.rst_x (rst_x ),
.i_rx (rx ),
.o_data (w_data ),
.o_valid(w_valid),
.o_error(w_error));
initial begin
//$dumpfile("SerialReceiver.vcd");
//$dumpvars(0, dut);
clk <= 1'b0;
rst_x <= 1'b1;
rx <= 1'b1;
#8
rst_x <= 1'b0;
#32
rst_x <= 1'b1;
#32
// Receive two bytes without any gap between stop bit and start bit.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#32
rx <= 1'b0; // bit 1
#32
rx <= 1'b1; // bit 2
#32
rx <= 1'b1; // bit 3
#32
rx <= 1'b0; // bit 4
#32
rx <= 1'b0; // bit 5
#32
rx <= 1'b1; // bit 6
#32
rx <= 1'b0; // bit 7
#32
rx <= 1'b1; // stop bit : 0b01001101 = 0x4d
#32
rx <= 1'b0; // start bit
#32
rx <= 1'b0; // bit 0
#32
rx <= 1'b1; // bit 1
#32
rx <= 1'b0; // bit 2
#32
rx <= 1'b1; // bit 3
#32
rx <= 1'b0; // bit 4
#32
rx <= 1'b1; // bit 5
#32
rx <= 1'b0; // bit 6
#32
rx <= 1'b1; // bit 7
#32
rx <= 1'b1; // stop bit : 0b10101010 = 0xaa
#32
// Receive invalid data that does not has stop bit.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#32
rx <= 1'b1; // bit 1
#32
rx <= 1'b1; // bit 2
#32
rx <= 1'b1; // bit 3
#32
rx <= 1'b1; // bit 4
#32
rx <= 1'b1; // bit 5
#32
rx <= 1'b1; // bit 6
#32
rx <= 1'b1; // bit 7
#32
rx <= 1'b0; // invalid stop bit
#32
rx <= 1'b1;
#31
// Receive a data in unstable timing.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#33
rx <= 1'b0; // bit 1
#31
rx <= 1'b1; // bit 2
#32
rx <= 1'b0; // bit 3
#33
rx <= 1'b1; // bit 4
#31
rx <= 1'b0; // bit 5
#32
rx <= 1'b1; // bit 6
#33
rx <= 1'b0; // bit 7
#31
rx <= 1'b1; // stop bit : 0b01010101 = 0x55
#40
// Receive a data in hazardous timing.
rx <= 1'b0; // start bit
#32
rx <= 1'b1; // bit 0
#33
rx <= 1'b0; // bit 1
#31
rx <= 1'b1; // bit 2
#32
rx <= 1'b0; // bit 3
#33
rx <= 1'b1; // bit 4
#31
rx <= 1'b0; // bit 5
#32
rx <= 1'b1; // bit 6
#33
rx <= 1'b0; // bit 7
#32
rx <= 1'b1; // stop bit : 0b01010101 = 0x55
#32
$finish;
end
endmodule // SerialReceiverTest
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RD_FLASH_PRE_FIFO.v when simulating
// the core, RD_FLASH_PRE_FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RD_FLASH_PRE_FIFO(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid
);
input rst;
input wr_clk;
input rd_clk;
input [7 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
output valid;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(7),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(8),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(127),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(126),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(4),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(7),
.C_WR_DEPTH(128),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(7),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.VALID(valid),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 12 18:12:37 2016
/////////////////////////////////////////////////////////////
module Barrel_Shifter_SWR26_EWR5 ( clk, rst, load_i, Shift_Value_i,
Shift_Data_i, Left_Right_i, Bit_Shift_i, N_mant_o );
input [4:0] Shift_Value_i;
input [25:0] Shift_Data_i;
output [25:0] N_mant_o;
input clk, rst, load_i, Left_Right_i, Bit_Shift_i;
wire load_o, n247, n248, n250, n252, n254, n256, n258, n260, n262, n264,
n266, n268, n270, n272, n274, n276, n278, n280, n282, n284, n286,
n288, n290, n292, n294, n296, n298, n300, n302, n304, n306, n308,
n310, n312, n314, n316, n318, n320, n322, n324, n326, n328, n330,
n332, n334, n336, n338, n340, n342, n344, n346, n348, n350, n352,
n353, n354, n355, n356, n357, n358, n359, n360, n361, n362, n363,
n364, n365, n366, n367, n368, n369, n370, n371, n372, n373, n374,
n375, n376, n377, n378, n379, n380, n381, n382, n383, n384, n385,
n386, n387, n388, n389, n390, n391, n392, n393, n394, n395, n396,
n397, n398, n399, n400, n401, n402, n403, n404, n405, n406, n407,
n408, n409, n410, n411, n412, n413, n414, n415, n416, n417, n418,
n419, n420, n421, n422, n423, n424, n425, n426, n427, n428, n429,
n430, n431, n432, n433, n434, n435, n436, n437, n438, n439, n440,
n441, n442, n443, n444, n445, n446, n447, n448, n449, n450, n451,
n452, n453, n454, n455, n456, n457, n458, n459, n460, n461, n462,
n463, n464, n465, n466, n467, n468, n469, n470, n471, n472, n473,
n474, n475, n476, n477, n478, n479, n480, n481, n482, n483, n484,
n485, n486, n487, n488, n489, n490, n491, n492, n493, n494, n495,
n496, n497, n498, n499, n500, n501, n502, n503, n504, n505, n506,
n507, n508, n509, n510, n511, n512, n513, n514, n515, n516, n517,
n518, n519, n520, n521, n522, n523, n524, n525, n526, n527, n528,
n529, n530, n531, n532, n533, n534, n535, n536, n537, n538, n539,
n540, n541, n542, n543, n544, n545, n546, n547, n548, n549, n550,
n551, n552, n553, n554, n555, n556, n557, n558, n559, n560, n561,
n562, n563, n564, n565, n566, n567, n568, n569, n570, n571, n572,
n573, n574, n575, n576, n577, n578, n579, n580, n581, n582, n583,
n584, n585, n586, n587, n588, n589, n590, n591, n592, n593, n594,
n595, n596, n597, n598, n599, n600, n601, n602, n603, n604, n605,
n606, n607, n608, n609, n610, n611, n612, n613, n614;
wire [25:0] Mux_Array_Data_array;
DFFRXLTS Output_Reg_Q_reg_12_ ( .D(n306), .CK(clk), .RN(n611), .Q(
N_mant_o[12]) );
DFFRXLTS Output_Reg_Q_reg_13_ ( .D(n304), .CK(clk), .RN(n611), .Q(
N_mant_o[13]) );
DFFRXLTS Output_Reg_Q_reg_11_ ( .D(n292), .CK(clk), .RN(n612), .Q(
N_mant_o[11]) );
DFFRXLTS Output_Reg_Q_reg_14_ ( .D(n290), .CK(clk), .RN(n612), .Q(
N_mant_o[14]) );
DFFRXLTS Output_Reg_Q_reg_10_ ( .D(n278), .CK(clk), .RN(n612), .Q(
N_mant_o[10]) );
DFFRXLTS Output_Reg_Q_reg_15_ ( .D(n276), .CK(clk), .RN(n612), .Q(
N_mant_o[15]) );
DFFRXLTS Output_Reg_Q_reg_9_ ( .D(n262), .CK(clk), .RN(n247), .Q(N_mant_o[9]) );
DFFRXLTS Output_Reg_Q_reg_16_ ( .D(n260), .CK(clk), .RN(n247), .Q(
N_mant_o[16]) );
DFFRXLTS Output_Reg_Q_reg_8_ ( .D(n258), .CK(clk), .RN(n247), .Q(N_mant_o[8]) );
DFFRXLTS Output_Reg_Q_reg_17_ ( .D(n256), .CK(clk), .RN(n613), .Q(
N_mant_o[17]) );
DFFRXLTS Output_Reg_Q_reg_1_ ( .D(n254), .CK(clk), .RN(n613), .Q(N_mant_o[1]) );
DFFRXLTS Output_Reg_Q_reg_24_ ( .D(n252), .CK(clk), .RN(n613), .Q(
N_mant_o[24]) );
DFFRXLTS Output_Reg_Q_reg_0_ ( .D(n250), .CK(clk), .RN(n613), .Q(N_mant_o[0]) );
DFFRXLTS Output_Reg_Q_reg_25_ ( .D(n248), .CK(clk), .RN(n613), .Q(
N_mant_o[25]) );
DFFRXLTS Output_Reg_Q_reg_5_ ( .D(n302), .CK(clk), .RN(n611), .Q(N_mant_o[5]) );
DFFRXLTS Output_Reg_Q_reg_20_ ( .D(n300), .CK(clk), .RN(n611), .Q(
N_mant_o[20]) );
DFFRXLTS Output_Reg_Q_reg_4_ ( .D(n298), .CK(clk), .RN(n611), .Q(N_mant_o[4]) );
DFFRXLTS Output_Reg_Q_reg_21_ ( .D(n296), .CK(clk), .RN(n611), .Q(
N_mant_o[21]) );
DFFRXLTS Output_Reg_Q_reg_6_ ( .D(n288), .CK(clk), .RN(n612), .Q(N_mant_o[6]) );
DFFRXLTS Output_Reg_Q_reg_19_ ( .D(n286), .CK(clk), .RN(n612), .Q(
N_mant_o[19]) );
DFFRXLTS Output_Reg_Q_reg_3_ ( .D(n284), .CK(clk), .RN(n612), .Q(N_mant_o[3]) );
DFFRXLTS Output_Reg_Q_reg_22_ ( .D(n282), .CK(clk), .RN(n612), .Q(
N_mant_o[22]) );
DFFRXLTS Output_Reg_Q_reg_7_ ( .D(n274), .CK(clk), .RN(n613), .Q(N_mant_o[7]) );
DFFRXLTS Output_Reg_Q_reg_18_ ( .D(n272), .CK(clk), .RN(n613), .Q(
N_mant_o[18]) );
DFFRXLTS Output_Reg_Q_reg_2_ ( .D(n270), .CK(clk), .RN(n613), .Q(N_mant_o[2]) );
DFFRXLTS Output_Reg_Q_reg_23_ ( .D(n268), .CK(clk), .RN(n247), .Q(
N_mant_o[23]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_2_ ( .D(n346), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[2]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_3_ ( .D(n344), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[3]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_4_ ( .D(n342), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[4]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_5_ ( .D(n340), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[5]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_6_ ( .D(n338), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[6]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_7_ ( .D(n336), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[7]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_0_ ( .D(n350), .CK(clk), .RN(n247), .Q(
Mux_Array_Data_array[0]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_1_ ( .D(n348), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[1]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_13_ ( .D(n324), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[13]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_14_ ( .D(n322), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[14]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_15_ ( .D(n320), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[15]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_10_ ( .D(n330), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[10]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_11_ ( .D(n328), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[11]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_12_ ( .D(n326), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[12]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_8_ ( .D(n334), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[8]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_9_ ( .D(n332), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[9]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_16_ ( .D(n318), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[16]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_17_ ( .D(n316), .CK(clk), .RN(n610), .Q(
Mux_Array_Data_array[17]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_24_ ( .D(n266), .CK(clk), .RN(n247), .Q(
Mux_Array_Data_array[24]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_25_ ( .D(n264), .CK(clk), .RN(n614), .Q(
Mux_Array_Data_array[25]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_22_ ( .D(n294), .CK(clk), .RN(n612), .Q(
Mux_Array_Data_array[22]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_23_ ( .D(n280), .CK(clk), .RN(n612), .Q(
Mux_Array_Data_array[23]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_21_ ( .D(n308), .CK(clk), .RN(n611), .Q(
Mux_Array_Data_array[21]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_18_ ( .D(n314), .CK(clk), .RN(n611), .Q(
Mux_Array_Data_array[18]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_19_ ( .D(n312), .CK(clk), .RN(n611), .Q(
Mux_Array_Data_array[19]) );
DFFRXLTS Mux_Array_Mid_Reg_Q_reg_20_ ( .D(n310), .CK(clk), .RN(n611), .Q(
Mux_Array_Data_array[20]) );
DFFRXLTS Mux_Array_Load_reg_Q_reg_0_ ( .D(n352), .CK(clk), .RN(n247), .Q(
load_o), .QN(n609) );
CLKAND2X2TS U301 ( .A(Shift_Value_i[4]), .B(n438), .Y(n385) );
NOR2XLTS U302 ( .A(n430), .B(n438), .Y(n387) );
OAI21XLTS U303 ( .A0(n472), .A1(n498), .B0(n471), .Y(n473) );
MXI2XLTS U304 ( .A(Shift_Data_i[13]), .B(Shift_Data_i[12]), .S0(n518), .Y(
n539) );
NOR2XLTS U305 ( .A(n517), .B(n516), .Y(n518) );
OAI21XLTS U306 ( .A0(n499), .A1(n498), .B0(n497), .Y(n500) );
NAND3XLTS U307 ( .A(Shift_Value_i[2]), .B(Shift_Value_i[1]), .C(load_i), .Y(
n574) );
CLKAND2X2TS U308 ( .A(Shift_Value_i[0]), .B(Left_Right_i), .Y(n577) );
NOR2XLTS U309 ( .A(Left_Right_i), .B(Shift_Value_i[0]), .Y(n586) );
NAND3XLTS U310 ( .A(Shift_Value_i[2]), .B(load_i), .C(Bit_Shift_i), .Y(n462)
);
OAI21XLTS U311 ( .A0(n478), .A1(n498), .B0(n477), .Y(n479) );
NAND3BXLTS U312 ( .AN(Shift_Value_i[1]), .B(Shift_Value_i[2]), .C(load_i),
.Y(n605) );
AO22XLTS U313 ( .A0(Mux_Array_Data_array[16]), .A1(n357), .B0(n385), .B1(
Mux_Array_Data_array[24]), .Y(n386) );
AO22XLTS U314 ( .A0(Mux_Array_Data_array[17]), .A1(n356), .B0(n385), .B1(
Mux_Array_Data_array[25]), .Y(n382) );
INVX2TS U315 ( .A(load_o), .Y(n425) );
OAI211XLTS U316 ( .A0(n606), .A1(n355), .B0(n470), .C0(n469), .Y(n314) );
OAI211XLTS U317 ( .A0(n606), .A1(n464), .B0(n463), .C0(n462), .Y(n294) );
OAI211XLTS U318 ( .A0(n606), .A1(n485), .B0(n484), .C0(n483), .Y(n266) );
OAI211XLTS U319 ( .A0(n561), .A1(n355), .B0(n560), .C0(n559), .Y(n328) );
OAI211XLTS U320 ( .A0(n575), .A1(n355), .B0(n573), .C0(n572), .Y(n320) );
OAI211XLTS U321 ( .A0(n567), .A1(n574), .B0(n566), .C0(n565), .Y(n322) );
OAI211XLTS U322 ( .A0(n550), .A1(n355), .B0(n538), .C0(n537), .Y(n336) );
OAI211XLTS U323 ( .A0(n539), .A1(n574), .B0(n535), .C0(n534), .Y(n338) );
OAI211XLTS U324 ( .A0(n532), .A1(n355), .B0(n531), .C0(n530), .Y(n344) );
OAI211XLTS U325 ( .A0(n549), .A1(n574), .B0(n548), .C0(n547), .Y(n346) );
OR2X1TS U326 ( .A(n438), .B(Shift_Value_i[4]), .Y(n353) );
INVX2TS U327 ( .A(n574), .Y(n354) );
INVX2TS U328 ( .A(n354), .Y(n355) );
INVX2TS U329 ( .A(n353), .Y(n356) );
INVX2TS U330 ( .A(n353), .Y(n357) );
CLKBUFX2TS U331 ( .A(n605), .Y(n358) );
OAI211XLTS U332 ( .A0(n596), .A1(n358), .B0(n595), .C0(n594), .Y(n348) );
OAI211XLTS U333 ( .A0(n584), .A1(n358), .B0(n583), .C0(n582), .Y(n350) );
OAI211XLTS U334 ( .A0(n556), .A1(n358), .B0(n555), .C0(n554), .Y(n326) );
OAI211XLTS U335 ( .A0(n561), .A1(n358), .B0(n552), .C0(n551), .Y(n324) );
OAI211XLTS U336 ( .A0(n539), .A1(n605), .B0(n525), .C0(n524), .Y(n334) );
OAI211XLTS U337 ( .A0(n550), .A1(n605), .B0(n515), .C0(n514), .Y(n332) );
OAI211XLTS U338 ( .A0(n549), .A1(n605), .B0(n508), .C0(n507), .Y(n342) );
OAI211XLTS U339 ( .A0(n532), .A1(n605), .B0(n496), .C0(n495), .Y(n340) );
OAI211XLTS U340 ( .A0(n567), .A1(n605), .B0(n482), .C0(n481), .Y(n318) );
OAI211XLTS U341 ( .A0(n575), .A1(n605), .B0(n476), .C0(n475), .Y(n316) );
CLKBUFX2TS U342 ( .A(n456), .Y(n359) );
OAI21XLTS U343 ( .A0(n457), .A1(n359), .B0(n455), .Y(n258) );
OAI21XLTS U344 ( .A0(n452), .A1(n359), .B0(n451), .Y(n262) );
OAI21XLTS U345 ( .A0(n449), .A1(n359), .B0(n441), .Y(n252) );
OAI21XLTS U346 ( .A0(n435), .A1(n359), .B0(n432), .Y(n304) );
OAI21XLTS U347 ( .A0(n428), .A1(n359), .B0(n424), .Y(n276) );
OAI21XLTS U348 ( .A0(n421), .A1(n456), .B0(n420), .Y(n290) );
OAI21XLTS U349 ( .A0(n444), .A1(n456), .B0(n415), .Y(n248) );
OAI211XLTS U350 ( .A0(n381), .A1(n456), .B0(n372), .C0(n369), .Y(n302) );
OAI211XLTS U351 ( .A0(n379), .A1(n456), .B0(n372), .C0(n368), .Y(n298) );
OAI211XLTS U352 ( .A0(n377), .A1(n456), .B0(n372), .C0(n367), .Y(n288) );
OAI211XLTS U353 ( .A0(n391), .A1(n456), .B0(n372), .C0(n366), .Y(n284) );
OAI211XLTS U354 ( .A0(n375), .A1(n456), .B0(n372), .C0(n365), .Y(n274) );
INVX2TS U355 ( .A(n454), .Y(n360) );
OAI21XLTS U356 ( .A0(n449), .A1(n360), .B0(n447), .Y(n254) );
OAI21XLTS U357 ( .A0(n444), .A1(n360), .B0(n443), .Y(n250) );
OAI21XLTS U358 ( .A0(n435), .A1(n360), .B0(n434), .Y(n306) );
OAI21XLTS U359 ( .A0(n428), .A1(n360), .B0(n427), .Y(n278) );
OAI21XLTS U360 ( .A0(n421), .A1(n360), .B0(n418), .Y(n292) );
OAI21XLTS U361 ( .A0(n452), .A1(n448), .B0(n384), .Y(n260) );
OAI211XLTS U362 ( .A0(n395), .A1(n448), .B0(n394), .C0(n393), .Y(n268) );
OAI211XLTS U363 ( .A0(n391), .A1(n448), .B0(n394), .C0(n390), .Y(n282) );
OAI211XLTS U364 ( .A0(n381), .A1(n448), .B0(n394), .C0(n380), .Y(n300) );
OAI211XLTS U365 ( .A0(n379), .A1(n448), .B0(n394), .C0(n378), .Y(n296) );
OAI211XLTS U366 ( .A0(n377), .A1(n448), .B0(n394), .C0(n376), .Y(n286) );
OAI211XLTS U367 ( .A0(n375), .A1(n448), .B0(n394), .C0(n374), .Y(n272) );
NOR2X1TS U368 ( .A(Shift_Value_i[4]), .B(Shift_Value_i[3]), .Y(n361) );
NOR2X1TS U369 ( .A(Shift_Value_i[4]), .B(Shift_Value_i[3]), .Y(n362) );
NOR2XLTS U370 ( .A(Shift_Value_i[4]), .B(Shift_Value_i[3]), .Y(n437) );
NOR2X1TS U371 ( .A(Shift_Value_i[2]), .B(n397), .Y(n363) );
NOR2X1TS U372 ( .A(Shift_Value_i[2]), .B(n397), .Y(n364) );
NOR2X1TS U373 ( .A(Shift_Value_i[2]), .B(n397), .Y(n602) );
OAI211XLTS U374 ( .A0(n412), .A1(n605), .B0(n411), .C0(n410), .Y(n308) );
OAI211XLTS U375 ( .A0(n412), .A1(n355), .B0(n408), .C0(n407), .Y(n312) );
OAI211XLTS U376 ( .A0(n412), .A1(n464), .B0(n401), .C0(n462), .Y(n280) );
OAI211XLTS U377 ( .A0(n412), .A1(n485), .B0(n484), .C0(n396), .Y(n264) );
INVX2TS U378 ( .A(Left_Right_i), .Y(n398) );
OAI21XLTS U379 ( .A0(n472), .A1(n491), .B0(n465), .Y(n466) );
OAI21XLTS U380 ( .A0(n499), .A1(n491), .B0(n490), .Y(n492) );
AOI211XLTS U381 ( .A0(n361), .A1(Mux_Array_Data_array[8]), .B0(n387), .C0(
n386), .Y(n457) );
AOI211XLTS U382 ( .A0(n362), .A1(Mux_Array_Data_array[9]), .B0(n387), .C0(
n382), .Y(n452) );
OAI211XLTS U383 ( .A0(n606), .A1(n605), .B0(n604), .C0(n603), .Y(n310) );
OAI211XLTS U384 ( .A0(n556), .A1(n355), .B0(n542), .C0(n541), .Y(n330) );
OAI211XLTS U385 ( .A0(n395), .A1(n456), .B0(n372), .C0(n371), .Y(n270) );
OAI21XLTS U386 ( .A0(n457), .A1(n448), .B0(n389), .Y(n256) );
INVX2TS U387 ( .A(Shift_Value_i[3]), .Y(n438) );
AOI222XLTS U388 ( .A0(Mux_Array_Data_array[7]), .A1(n361), .B0(
Mux_Array_Data_array[15]), .B1(n356), .C0(Mux_Array_Data_array[23]),
.C1(n385), .Y(n375) );
CLKBUFX2TS U389 ( .A(n425), .Y(n607) );
NOR2X1TS U390 ( .A(Left_Right_i), .B(n607), .Y(n446) );
INVX2TS U391 ( .A(n446), .Y(n456) );
NAND2X1TS U392 ( .A(Left_Right_i), .B(load_o), .Y(n448) );
INVX2TS U393 ( .A(n448), .Y(n454) );
NOR2BX1TS U394 ( .AN(Bit_Shift_i), .B(n437), .Y(n436) );
NAND2X1TS U395 ( .A(Bit_Shift_i), .B(Shift_Value_i[4]), .Y(n430) );
AOI22X1TS U396 ( .A0(n454), .A1(n436), .B0(n446), .B1(n387), .Y(n372) );
INVX2TS U397 ( .A(n437), .Y(n373) );
NOR2X1TS U398 ( .A(n448), .B(n373), .Y(n370) );
AOI22X1TS U399 ( .A0(Mux_Array_Data_array[18]), .A1(n370), .B0(N_mant_o[7]),
.B1(n425), .Y(n365) );
AOI222XLTS U400 ( .A0(Mux_Array_Data_array[3]), .A1(n361), .B0(
Mux_Array_Data_array[11]), .B1(n357), .C0(Mux_Array_Data_array[19]),
.C1(n385), .Y(n391) );
AOI22X1TS U401 ( .A0(n370), .A1(Mux_Array_Data_array[22]), .B0(N_mant_o[3]),
.B1(n425), .Y(n366) );
AOI222XLTS U402 ( .A0(Mux_Array_Data_array[6]), .A1(n362), .B0(
Mux_Array_Data_array[14]), .B1(n356), .C0(Mux_Array_Data_array[22]),
.C1(n385), .Y(n377) );
AOI22X1TS U403 ( .A0(Mux_Array_Data_array[19]), .A1(n370), .B0(N_mant_o[6]),
.B1(n425), .Y(n367) );
AOI222XLTS U404 ( .A0(Mux_Array_Data_array[4]), .A1(n361), .B0(
Mux_Array_Data_array[12]), .B1(n357), .C0(Mux_Array_Data_array[20]),
.C1(n385), .Y(n379) );
AOI22X1TS U405 ( .A0(Mux_Array_Data_array[21]), .A1(n370), .B0(N_mant_o[4]),
.B1(n607), .Y(n368) );
AOI222XLTS U406 ( .A0(Mux_Array_Data_array[5]), .A1(n362), .B0(
Mux_Array_Data_array[13]), .B1(n356), .C0(Mux_Array_Data_array[21]),
.C1(n385), .Y(n381) );
AOI22X1TS U407 ( .A0(Mux_Array_Data_array[20]), .A1(n370), .B0(N_mant_o[5]),
.B1(n607), .Y(n369) );
AOI222XLTS U408 ( .A0(Mux_Array_Data_array[2]), .A1(n362), .B0(
Mux_Array_Data_array[10]), .B1(n357), .C0(Mux_Array_Data_array[18]),
.C1(n385), .Y(n395) );
AOI22X1TS U409 ( .A0(n370), .A1(Mux_Array_Data_array[23]), .B0(N_mant_o[2]),
.B1(n609), .Y(n371) );
AOI22X1TS U410 ( .A0(n454), .A1(n387), .B0(n446), .B1(n436), .Y(n394) );
NOR2X1TS U411 ( .A(n373), .B(n456), .Y(n392) );
AOI22X1TS U412 ( .A0(Mux_Array_Data_array[18]), .A1(n392), .B0(N_mant_o[18]),
.B1(n609), .Y(n374) );
AOI22X1TS U413 ( .A0(Mux_Array_Data_array[19]), .A1(n392), .B0(N_mant_o[19]),
.B1(n607), .Y(n376) );
AOI22X1TS U414 ( .A0(Mux_Array_Data_array[21]), .A1(n392), .B0(N_mant_o[21]),
.B1(n607), .Y(n378) );
AOI22X1TS U415 ( .A0(Mux_Array_Data_array[20]), .A1(n392), .B0(N_mant_o[20]),
.B1(n607), .Y(n380) );
INVX2TS U416 ( .A(rst), .Y(n247) );
CLKBUFX2TS U417 ( .A(n247), .Y(n614) );
CLKBUFX2TS U418 ( .A(n614), .Y(n610) );
CLKBUFX2TS U419 ( .A(n614), .Y(n611) );
CLKBUFX2TS U420 ( .A(n247), .Y(n613) );
CLKBUFX2TS U421 ( .A(n613), .Y(n612) );
AOI22X1TS U422 ( .A0(Mux_Array_Data_array[16]), .A1(n362), .B0(n356), .B1(
Mux_Array_Data_array[24]), .Y(n383) );
NAND2X1TS U423 ( .A(n383), .B(n430), .Y(n450) );
AOI22X1TS U424 ( .A0(n446), .A1(n450), .B0(N_mant_o[16]), .B1(n609), .Y(n384) );
AOI22X1TS U425 ( .A0(Mux_Array_Data_array[17]), .A1(n361), .B0(n357), .B1(
Mux_Array_Data_array[25]), .Y(n388) );
NAND2X1TS U426 ( .A(n388), .B(n430), .Y(n453) );
AOI22X1TS U427 ( .A0(n446), .A1(n453), .B0(N_mant_o[17]), .B1(n609), .Y(n389) );
AOI22X1TS U428 ( .A0(n392), .A1(Mux_Array_Data_array[22]), .B0(N_mant_o[22]),
.B1(n607), .Y(n390) );
AOI22X1TS U429 ( .A0(n392), .A1(Mux_Array_Data_array[23]), .B0(N_mant_o[23]),
.B1(n609), .Y(n393) );
NOR2X1TS U430 ( .A(Shift_Value_i[0]), .B(n398), .Y(n520) );
INVX2TS U431 ( .A(n520), .Y(n499) );
INVX2TS U432 ( .A(n499), .Y(n516) );
INVX2TS U433 ( .A(n586), .Y(n472) );
INVX2TS U434 ( .A(n472), .Y(n527) );
AOI222XLTS U435 ( .A0(Shift_Value_i[0]), .A1(Bit_Shift_i), .B0(n516), .B1(
Shift_Data_i[0]), .C0(n527), .C1(Shift_Data_i[25]), .Y(n412) );
INVX2TS U436 ( .A(load_i), .Y(n404) );
CLKBUFX2TS U437 ( .A(n404), .Y(n597) );
NOR3X1TS U438 ( .A(Shift_Value_i[2]), .B(Shift_Value_i[1]), .C(n597), .Y(
n480) );
INVX2TS U439 ( .A(n480), .Y(n485) );
OAI211XLTS U440 ( .A0(Shift_Value_i[2]), .A1(Shift_Value_i[1]), .B0(load_i),
.C0(Bit_Shift_i), .Y(n484) );
CLKBUFX2TS U441 ( .A(n404), .Y(n608) );
NAND2X1TS U442 ( .A(Mux_Array_Data_array[25]), .B(n608), .Y(n396) );
NAND2X1TS U443 ( .A(Shift_Value_i[1]), .B(load_i), .Y(n397) );
INVX2TS U444 ( .A(n602), .Y(n464) );
INVX2TS U445 ( .A(n485), .Y(n546) );
AOI22X1TS U446 ( .A0(n516), .A1(Shift_Data_i[2]), .B0(Shift_Data_i[23]),
.B1(n527), .Y(n400) );
CLKBUFX2TS U447 ( .A(n577), .Y(n589) );
NAND2X1TS U448 ( .A(n398), .B(Shift_Value_i[0]), .Y(n478) );
INVX2TS U449 ( .A(n478), .Y(n588) );
CLKBUFX2TS U450 ( .A(n588), .Y(n517) );
AOI22X1TS U451 ( .A0(n589), .A1(Shift_Data_i[1]), .B0(n517), .B1(
Shift_Data_i[24]), .Y(n399) );
NAND2X1TS U452 ( .A(n400), .B(n399), .Y(n474) );
AOI22X1TS U453 ( .A0(n546), .A1(n474), .B0(Mux_Array_Data_array[23]), .B1(
n597), .Y(n401) );
CLKBUFX2TS U454 ( .A(n577), .Y(n510) );
CLKBUFX2TS U455 ( .A(n588), .Y(n521) );
INVX2TS U456 ( .A(n472), .Y(n519) );
AOI22X1TS U457 ( .A0(n516), .A1(Shift_Data_i[4]), .B0(n519), .B1(
Shift_Data_i[21]), .Y(n402) );
OAI2BB1X1TS U458 ( .A0N(Shift_Data_i[22]), .A1N(n521), .B0(n402), .Y(n403)
);
AOI21X1TS U459 ( .A0(n510), .A1(Shift_Data_i[3]), .B0(n403), .Y(n575) );
INVX2TS U460 ( .A(n575), .Y(n409) );
AOI22X1TS U461 ( .A0(n364), .A1(n409), .B0(Mux_Array_Data_array[19]), .B1(
n608), .Y(n408) );
INVX2TS U462 ( .A(n485), .Y(n600) );
AOI22X1TS U463 ( .A0(n520), .A1(Shift_Data_i[6]), .B0(n519), .B1(
Shift_Data_i[19]), .Y(n406) );
AOI22X1TS U464 ( .A0(n589), .A1(Shift_Data_i[5]), .B0(n517), .B1(
Shift_Data_i[20]), .Y(n405) );
NAND2X1TS U465 ( .A(n406), .B(n405), .Y(n569) );
INVX2TS U466 ( .A(n605), .Y(n570) );
AOI22X1TS U467 ( .A0(n600), .A1(n569), .B0(n570), .B1(n474), .Y(n407) );
INVX2TS U468 ( .A(n355), .Y(n598) );
AOI22X1TS U469 ( .A0(Bit_Shift_i), .A1(n598), .B0(Mux_Array_Data_array[21]),
.B1(n597), .Y(n411) );
AOI22X1TS U470 ( .A0(n363), .A1(n474), .B0(n600), .B1(n409), .Y(n410) );
AOI21X1TS U471 ( .A0(Mux_Array_Data_array[25]), .A1(n362), .B0(n436), .Y(
n444) );
AOI22X1TS U472 ( .A0(Mux_Array_Data_array[0]), .A1(n362), .B0(
Mux_Array_Data_array[8]), .B1(n357), .Y(n414) );
OAI221XLTS U473 ( .A0(Shift_Value_i[3]), .A1(Mux_Array_Data_array[16]), .B0(
n438), .B1(Mux_Array_Data_array[24]), .C0(Shift_Value_i[4]), .Y(n413)
);
NAND2X1TS U474 ( .A(n414), .B(n413), .Y(n442) );
AOI22X1TS U475 ( .A0(n454), .A1(n442), .B0(N_mant_o[25]), .B1(n425), .Y(n415) );
OAI2BB1X1TS U476 ( .A0N(n357), .A1N(Mux_Array_Data_array[22]), .B0(n430),
.Y(n416) );
AOI21X1TS U477 ( .A0(Mux_Array_Data_array[14]), .A1(n361), .B0(n416), .Y(
n421) );
AOI22X1TS U478 ( .A0(Mux_Array_Data_array[11]), .A1(n361), .B0(
Mux_Array_Data_array[19]), .B1(n356), .Y(n417) );
NAND2X1TS U479 ( .A(n417), .B(n430), .Y(n419) );
AOI22X1TS U480 ( .A0(n446), .A1(n419), .B0(N_mant_o[11]), .B1(n425), .Y(n418) );
AOI22X1TS U481 ( .A0(n454), .A1(n419), .B0(N_mant_o[14]), .B1(n425), .Y(n420) );
OAI2BB1X1TS U482 ( .A0N(n356), .A1N(Mux_Array_Data_array[23]), .B0(n430),
.Y(n422) );
AOI21X1TS U483 ( .A0(Mux_Array_Data_array[15]), .A1(n362), .B0(n422), .Y(
n428) );
AOI22X1TS U484 ( .A0(Mux_Array_Data_array[10]), .A1(n362), .B0(
Mux_Array_Data_array[18]), .B1(n357), .Y(n423) );
NAND2X1TS U485 ( .A(n423), .B(n430), .Y(n426) );
AOI22X1TS U486 ( .A0(n454), .A1(n426), .B0(N_mant_o[15]), .B1(n425), .Y(n424) );
AOI22X1TS U487 ( .A0(n446), .A1(n426), .B0(N_mant_o[10]), .B1(n425), .Y(n427) );
OAI2BB1X1TS U488 ( .A0N(Mux_Array_Data_array[21]), .A1N(n357), .B0(n430),
.Y(n429) );
AOI21X1TS U489 ( .A0(Mux_Array_Data_array[13]), .A1(n361), .B0(n429), .Y(
n435) );
AOI22X1TS U490 ( .A0(Mux_Array_Data_array[12]), .A1(n361), .B0(
Mux_Array_Data_array[20]), .B1(n356), .Y(n431) );
NAND2X1TS U491 ( .A(n431), .B(n430), .Y(n433) );
AOI22X1TS U492 ( .A0(n454), .A1(n433), .B0(N_mant_o[13]), .B1(n607), .Y(n432) );
AOI22X1TS U493 ( .A0(n446), .A1(n433), .B0(N_mant_o[12]), .B1(n607), .Y(n434) );
AOI21X1TS U494 ( .A0(Mux_Array_Data_array[24]), .A1(n362), .B0(n436), .Y(
n449) );
AOI22X1TS U495 ( .A0(Mux_Array_Data_array[1]), .A1(n361), .B0(
Mux_Array_Data_array[9]), .B1(n356), .Y(n440) );
OAI221XLTS U496 ( .A0(Shift_Value_i[3]), .A1(Mux_Array_Data_array[17]), .B0(
n438), .B1(Mux_Array_Data_array[25]), .C0(Shift_Value_i[4]), .Y(n439)
);
NAND2X1TS U497 ( .A(n440), .B(n439), .Y(n445) );
AOI22X1TS U498 ( .A0(n454), .A1(n445), .B0(N_mant_o[24]), .B1(n609), .Y(n441) );
AOI22X1TS U499 ( .A0(n446), .A1(n442), .B0(N_mant_o[0]), .B1(n609), .Y(n443)
);
AOI22X1TS U500 ( .A0(n446), .A1(n445), .B0(N_mant_o[1]), .B1(n609), .Y(n447)
);
AOI22X1TS U501 ( .A0(n454), .A1(n450), .B0(N_mant_o[9]), .B1(n609), .Y(n451)
);
AOI22X1TS U502 ( .A0(n454), .A1(n453), .B0(N_mant_o[8]), .B1(n609), .Y(n455)
);
AOI22X1TS U503 ( .A0(n517), .A1(Shift_Data_i[25]), .B0(n519), .B1(
Shift_Data_i[24]), .Y(n458) );
OAI2BB1X1TS U504 ( .A0N(n516), .A1N(Shift_Data_i[1]), .B0(n458), .Y(n459) );
AOI21X1TS U505 ( .A0(n577), .A1(Shift_Data_i[0]), .B0(n459), .Y(n606) );
INVX2TS U506 ( .A(n499), .Y(n587) );
AOI22X1TS U507 ( .A0(Shift_Data_i[22]), .A1(n519), .B0(Shift_Data_i[3]),
.B1(n587), .Y(n461) );
AOI22X1TS U508 ( .A0(n589), .A1(Shift_Data_i[2]), .B0(n521), .B1(
Shift_Data_i[23]), .Y(n460) );
NAND2X1TS U509 ( .A(n461), .B(n460), .Y(n601) );
AOI22X1TS U510 ( .A0(n480), .A1(n601), .B0(Mux_Array_Data_array[22]), .B1(
n597), .Y(n463) );
INVX2TS U511 ( .A(Shift_Data_i[20]), .Y(n491) );
AOI22X1TS U512 ( .A0(n517), .A1(Shift_Data_i[21]), .B0(n587), .B1(
Shift_Data_i[5]), .Y(n465) );
AOI21X1TS U513 ( .A0(n510), .A1(Shift_Data_i[4]), .B0(n466), .Y(n567) );
INVX2TS U514 ( .A(n567), .Y(n599) );
AOI22X1TS U515 ( .A0(n364), .A1(n599), .B0(Mux_Array_Data_array[18]), .B1(
n597), .Y(n470) );
AOI22X1TS U516 ( .A0(n520), .A1(Shift_Data_i[7]), .B0(n519), .B1(
Shift_Data_i[18]), .Y(n468) );
AOI22X1TS U517 ( .A0(n589), .A1(Shift_Data_i[6]), .B0(n521), .B1(
Shift_Data_i[19]), .Y(n467) );
NAND2X1TS U518 ( .A(n468), .B(n467), .Y(n563) );
AOI22X1TS U519 ( .A0(n480), .A1(n563), .B0(n570), .B1(n601), .Y(n469) );
AOI22X1TS U520 ( .A0(n602), .A1(n569), .B0(Mux_Array_Data_array[17]), .B1(
n597), .Y(n476) );
INVX2TS U521 ( .A(Shift_Data_i[17]), .Y(n498) );
AOI22X1TS U522 ( .A0(n517), .A1(Shift_Data_i[18]), .B0(n587), .B1(
Shift_Data_i[8]), .Y(n471) );
AOI21X1TS U523 ( .A0(n510), .A1(Shift_Data_i[7]), .B0(n473), .Y(n561) );
INVX2TS U524 ( .A(n561), .Y(n568) );
AOI22X1TS U525 ( .A0(n480), .A1(n568), .B0(n598), .B1(n474), .Y(n475) );
AOI22X1TS U526 ( .A0(n363), .A1(n563), .B0(Mux_Array_Data_array[16]), .B1(
n597), .Y(n482) );
AOI22X1TS U527 ( .A0(n516), .A1(Shift_Data_i[9]), .B0(n519), .B1(
Shift_Data_i[16]), .Y(n477) );
AOI21X1TS U528 ( .A0(n510), .A1(Shift_Data_i[8]), .B0(n479), .Y(n556) );
INVX2TS U529 ( .A(n556), .Y(n562) );
AOI22X1TS U530 ( .A0(n480), .A1(n562), .B0(n598), .B1(n601), .Y(n481) );
NAND2X1TS U531 ( .A(Mux_Array_Data_array[24]), .B(n608), .Y(n483) );
AOI22X1TS U532 ( .A0(n517), .A1(Shift_Data_i[10]), .B0(n527), .B1(
Shift_Data_i[9]), .Y(n486) );
OAI2BB1X1TS U533 ( .A0N(n516), .A1N(Shift_Data_i[16]), .B0(n486), .Y(n487)
);
AOI21X1TS U534 ( .A0(n510), .A1(Shift_Data_i[15]), .B0(n487), .Y(n532) );
AOI22X1TS U535 ( .A0(n587), .A1(Shift_Data_i[18]), .B0(n527), .B1(
Shift_Data_i[7]), .Y(n489) );
AOI22X1TS U536 ( .A0(n510), .A1(Shift_Data_i[17]), .B0(n521), .B1(
Shift_Data_i[8]), .Y(n488) );
NAND2X1TS U537 ( .A(n489), .B(n488), .Y(n585) );
AOI22X1TS U538 ( .A0(n364), .A1(n585), .B0(Mux_Array_Data_array[5]), .B1(
n404), .Y(n496) );
AOI22X1TS U539 ( .A0(n517), .A1(Shift_Data_i[6]), .B0(n527), .B1(
Shift_Data_i[5]), .Y(n490) );
AOI21X1TS U540 ( .A0(n577), .A1(Shift_Data_i[19]), .B0(n492), .Y(n596) );
INVX2TS U541 ( .A(n596), .Y(n526) );
AOI22X1TS U542 ( .A0(n520), .A1(Shift_Data_i[14]), .B0(n519), .B1(
Shift_Data_i[11]), .Y(n494) );
AOI22X1TS U543 ( .A0(n589), .A1(Shift_Data_i[13]), .B0(n521), .B1(
Shift_Data_i[12]), .Y(n493) );
NAND2X1TS U544 ( .A(n494), .B(n493), .Y(n558) );
AOI22X1TS U545 ( .A0(n546), .A1(n526), .B0(n598), .B1(n558), .Y(n495) );
AOI22X1TS U546 ( .A0(n517), .A1(Shift_Data_i[9]), .B0(n527), .B1(
Shift_Data_i[8]), .Y(n497) );
AOI21X1TS U547 ( .A0(n510), .A1(Shift_Data_i[16]), .B0(n500), .Y(n549) );
AOI22X1TS U548 ( .A0(n587), .A1(Shift_Data_i[19]), .B0(n527), .B1(
Shift_Data_i[6]), .Y(n502) );
AOI22X1TS U549 ( .A0(n510), .A1(Shift_Data_i[18]), .B0(n521), .B1(
Shift_Data_i[7]), .Y(n501) );
NAND2X1TS U550 ( .A(n502), .B(n501), .Y(n576) );
AOI22X1TS U551 ( .A0(n363), .A1(n576), .B0(Mux_Array_Data_array[4]), .B1(
n608), .Y(n508) );
AOI22X1TS U552 ( .A0(n516), .A1(Shift_Data_i[21]), .B0(n527), .B1(
Shift_Data_i[4]), .Y(n503) );
OAI2BB1X1TS U553 ( .A0N(n510), .A1N(Shift_Data_i[20]), .B0(n503), .Y(n504)
);
AOI21X1TS U554 ( .A0(n521), .A1(Shift_Data_i[5]), .B0(n504), .Y(n584) );
INVX2TS U555 ( .A(n584), .Y(n543) );
AOI22X1TS U556 ( .A0(n587), .A1(Shift_Data_i[15]), .B0(n527), .B1(
Shift_Data_i[10]), .Y(n506) );
AOI22X1TS U557 ( .A0(n589), .A1(Shift_Data_i[14]), .B0(n521), .B1(
Shift_Data_i[11]), .Y(n505) );
NAND2X1TS U558 ( .A(n506), .B(n505), .Y(n540) );
AOI22X1TS U559 ( .A0(n546), .A1(n543), .B0(n598), .B1(n540), .Y(n507) );
AOI22X1TS U560 ( .A0(n516), .A1(Shift_Data_i[12]), .B0(n519), .B1(
Shift_Data_i[13]), .Y(n509) );
OAI2BB1X1TS U561 ( .A0N(n510), .A1N(Shift_Data_i[11]), .B0(n509), .Y(n511)
);
AOI21X1TS U562 ( .A0(n521), .A1(Shift_Data_i[14]), .B0(n511), .Y(n550) );
AOI22X1TS U563 ( .A0(n364), .A1(n558), .B0(Mux_Array_Data_array[9]), .B1(
n404), .Y(n515) );
INVX2TS U564 ( .A(n532), .Y(n536) );
AOI22X1TS U565 ( .A0(n520), .A1(Shift_Data_i[10]), .B0(n519), .B1(
Shift_Data_i[15]), .Y(n513) );
AOI22X1TS U566 ( .A0(n589), .A1(Shift_Data_i[9]), .B0(n517), .B1(
Shift_Data_i[16]), .Y(n512) );
NAND2X1TS U567 ( .A(n513), .B(n512), .Y(n571) );
AOI22X1TS U568 ( .A0(n546), .A1(n536), .B0(n598), .B1(n571), .Y(n514) );
AOI22X1TS U569 ( .A0(n363), .A1(n540), .B0(Mux_Array_Data_array[8]), .B1(
n404), .Y(n525) );
INVX2TS U570 ( .A(n549), .Y(n533) );
AOI22X1TS U571 ( .A0(n520), .A1(Shift_Data_i[11]), .B0(n519), .B1(
Shift_Data_i[14]), .Y(n523) );
AOI22X1TS U572 ( .A0(n589), .A1(Shift_Data_i[10]), .B0(n521), .B1(
Shift_Data_i[15]), .Y(n522) );
NAND2X1TS U573 ( .A(n523), .B(n522), .Y(n564) );
AOI22X1TS U574 ( .A0(n546), .A1(n533), .B0(n354), .B1(n564), .Y(n524) );
AOI22X1TS U575 ( .A0(n363), .A1(n526), .B0(Mux_Array_Data_array[3]), .B1(
n608), .Y(n531) );
AOI22X1TS U576 ( .A0(Shift_Data_i[22]), .A1(n587), .B0(Shift_Data_i[3]),
.B1(n527), .Y(n529) );
AOI22X1TS U577 ( .A0(n589), .A1(Shift_Data_i[21]), .B0(n588), .B1(
Shift_Data_i[4]), .Y(n528) );
NAND2X1TS U578 ( .A(n529), .B(n528), .Y(n593) );
AOI22X1TS U579 ( .A0(n546), .A1(n593), .B0(n570), .B1(n585), .Y(n530) );
AOI22X1TS U580 ( .A0(n364), .A1(n533), .B0(Mux_Array_Data_array[6]), .B1(
n404), .Y(n535) );
AOI22X1TS U581 ( .A0(n546), .A1(n576), .B0(n570), .B1(n540), .Y(n534) );
AOI22X1TS U582 ( .A0(n363), .A1(n536), .B0(Mux_Array_Data_array[7]), .B1(
n404), .Y(n538) );
AOI22X1TS U583 ( .A0(n546), .A1(n585), .B0(n570), .B1(n558), .Y(n537) );
INVX2TS U584 ( .A(n539), .Y(n553) );
AOI22X1TS U585 ( .A0(n602), .A1(n553), .B0(Mux_Array_Data_array[10]), .B1(
n608), .Y(n542) );
AOI22X1TS U586 ( .A0(n546), .A1(n540), .B0(n570), .B1(n564), .Y(n541) );
AOI22X1TS U587 ( .A0(n364), .A1(n543), .B0(Mux_Array_Data_array[2]), .B1(
n608), .Y(n548) );
AOI22X1TS U588 ( .A0(n587), .A1(Shift_Data_i[23]), .B0(n586), .B1(
Shift_Data_i[2]), .Y(n545) );
AOI22X1TS U589 ( .A0(n577), .A1(Shift_Data_i[22]), .B0(n588), .B1(
Shift_Data_i[3]), .Y(n544) );
NAND2X1TS U590 ( .A(n545), .B(n544), .Y(n581) );
AOI22X1TS U591 ( .A0(n570), .A1(n576), .B0(n546), .B1(n581), .Y(n547) );
AOI22X1TS U592 ( .A0(n364), .A1(n571), .B0(Mux_Array_Data_array[13]), .B1(
n404), .Y(n552) );
INVX2TS U593 ( .A(n550), .Y(n557) );
AOI22X1TS U594 ( .A0(n600), .A1(n557), .B0(n354), .B1(n569), .Y(n551) );
AOI22X1TS U595 ( .A0(n363), .A1(n564), .B0(Mux_Array_Data_array[12]), .B1(
n404), .Y(n555) );
AOI22X1TS U596 ( .A0(n600), .A1(n553), .B0(n598), .B1(n563), .Y(n554) );
AOI22X1TS U597 ( .A0(n363), .A1(n557), .B0(Mux_Array_Data_array[11]), .B1(
n404), .Y(n560) );
AOI22X1TS U598 ( .A0(n600), .A1(n558), .B0(n570), .B1(n571), .Y(n559) );
AOI22X1TS U599 ( .A0(n364), .A1(n562), .B0(Mux_Array_Data_array[14]), .B1(
n597), .Y(n566) );
AOI22X1TS U600 ( .A0(n600), .A1(n564), .B0(n570), .B1(n563), .Y(n565) );
AOI22X1TS U601 ( .A0(n363), .A1(n568), .B0(Mux_Array_Data_array[15]), .B1(
n597), .Y(n573) );
AOI22X1TS U602 ( .A0(n600), .A1(n571), .B0(n570), .B1(n569), .Y(n572) );
AOI22X1TS U603 ( .A0(n598), .A1(n576), .B0(Mux_Array_Data_array[0]), .B1(
n608), .Y(n583) );
AOI22X1TS U604 ( .A0(n587), .A1(Shift_Data_i[25]), .B0(n586), .B1(
Shift_Data_i[0]), .Y(n579) );
AOI22X1TS U605 ( .A0(n577), .A1(Shift_Data_i[24]), .B0(n588), .B1(
Shift_Data_i[1]), .Y(n578) );
NAND2X1TS U606 ( .A(n579), .B(n578), .Y(n580) );
AOI22X1TS U607 ( .A0(n602), .A1(n581), .B0(n600), .B1(n580), .Y(n582) );
AOI22X1TS U608 ( .A0(n598), .A1(n585), .B0(Mux_Array_Data_array[1]), .B1(
n608), .Y(n595) );
AOI22X1TS U609 ( .A0(n587), .A1(Shift_Data_i[24]), .B0(n586), .B1(
Shift_Data_i[1]), .Y(n591) );
AOI22X1TS U610 ( .A0(n589), .A1(Shift_Data_i[23]), .B0(n588), .B1(
Shift_Data_i[2]), .Y(n590) );
NAND2X1TS U611 ( .A(n591), .B(n590), .Y(n592) );
AOI22X1TS U612 ( .A0(n602), .A1(n593), .B0(n600), .B1(n592), .Y(n594) );
AOI22X1TS U613 ( .A0(Bit_Shift_i), .A1(n598), .B0(Mux_Array_Data_array[20]),
.B1(n597), .Y(n604) );
AOI22X1TS U614 ( .A0(n602), .A1(n601), .B0(n600), .B1(n599), .Y(n603) );
NAND2X1TS U615 ( .A(n608), .B(n607), .Y(n352) );
endmodule
|
`timescale 1ns/1ps
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input sata_clk,
input rst,
output master_ready,
input in_ready,
input [31:0] in_command,
input [31:0] in_address,
input [31:0] in_data,
input [27:0] in_data_count,
input out_ready,
output out_en,
output [31:0] out_status,
output [31:0] out_address,
output [31:0] out_data,
output [27:0] out_data_count,
input [31:0] test_id,
input ih_reset,
output device_interrupt
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_in_ready;
reg [31:0] r_in_command;
reg [31:0] r_in_address;
reg [31:0] r_in_data;
reg [27:0] r_in_data_count;
reg r_out_ready;
reg r_ih_reset;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_in_ready = in_ready;
always @ (*) r_in_command = in_command;
always @ (*) r_in_address = in_address;
always @ (*) r_in_data = in_data;
always @ (*) r_in_data_count = in_data_count;
always @ (*) r_out_ready = out_ready;
always @ (*) r_ih_reset = ih_reset;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (r_rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count),
.i_out_ready (r_out_ready ),
.o_en (out_en ),
.o_status (out_status ),
.o_address (out_address ),
.o_data (out_data ),
.o_data_count (out_data_count ),
.o_master_ready (master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
axi_sdb s1 (
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (r_rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (r_rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ),
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
//Disable Slave 0
assign w_wbs0_int = 0;
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign device_interrupt = w_wbp_int;
/*
READ ME IF YOUR MODULE WILL INTERFACE WITH MEMORY
If you want to talk to memory over the wishbone bus directly, your module must control the following signals:
(Your module will be a wishbone master)
mem_o_we
mem_o_stb
mem_o_cyc
mem_o_sel
mem_o_adr
mem_o_dat
mem_i_dat
mem_i_ack
mem_i_int
Currently this bus is disabled so if will not interface with memory these signals can be left
For a reference check out wb_sd_host
*/
assign mem_o_we = 0;
assign mem_o_stb = 0;
assign mem_o_cyc = 0;
assign mem_o_sel = 0;
assign mem_o_adr = 0;
assign mem_o_dat = 0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__nor4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, A, B, C, D );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__NOR4_FUNCTIONAL_V |
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM with byte write signals ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB16 ////
//// - Xilinx Virtex RAMB4 ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_spram_2048x32_bw.v,v $
// Revision 1.1 2008/05/07 22:43:22 daughtry
// Initial Demo RTL check-in
//
// Revision 1.5 2005/10/19 11:37:56 jcastillo
// Added support for RAMB16 Xilinx4/Spartan3 primitives
//
// Revision 1.4 2004/06/08 18:15:32 lampret
// Changed behavior of the simulation generic models
//
// Revision 1.3 2003/10/17 07:59:44 markom
// mbist signals updated according to newest convention
//
// Revision 1.2 2003/09/12 09:03:54 dries
// correct all the syntax errors
//
// Revision 1.1 2003/08/26 09:37:02 simons
// Added support for rams with byte write access.
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_2048x32_bw(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input [3:0] we; // Write enable input
input oe; // Output enable input
input [10:0] addr; // address bus inputs
input [31:0] di; // input data bus
output [31:0] doq; // output data bus
//
// Internal wires and registers
//
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_2048x32_bw artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_2048x32_bw_bist artisan_ssp(
`else
art_hssp_2048x32_bw artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef OR1200_BIST
wire mbist_si_i_ram_0;
wire mbist_si_i_ram_1;
wire mbist_si_i_ram_2;
wire mbist_si_i_ram_3;
wire mbist_so_o_ram_0;
wire mbist_so_o_ram_1;
wire mbist_so_o_ram_2;
wire mbist_so_o_ram_3;
assign mbist_si_i_ram_0 = mbist_si_i;
assign mbist_si_i_ram_1 = mbist_so_o_ram_0;
assign mbist_si_i_ram_2 = mbist_so_o_ram_1;
assign mbist_si_i_ram_3 = mbist_so_o_ram_2;
assign mbist_so_o = mbist_so_o_ram_3;
`endif
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_0(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_0(
`else
vs_hdsp_2048x8 vs_ssp_0(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i_ram_0),
.mbist_so_o(mbist_so_o_ram_0),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di[7:0]),
.WEN(~we[0]),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq[7:0])
);
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_1(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_1(
`else
vs_hdsp_2048x8 vs_ssp_1(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i_ram_1),
.mbist_so_o(mbist_so_o_ram_1),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di[15:8]),
.WEN(~we[1]),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq[15:8])
);
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_2(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_2(
`else
vs_hdsp_2048x8 vs_ssp_2(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i_ram_2),
.mbist_so_o(mbist_so_o_ram_2),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di[23:16]),
.WEN(~we[2]),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq[23:16])
);
`ifdef UNUSED
vs_hdsp_2048x8 vs_ssp_3(
`else
`ifdef OR1200_BIST
vs_hdsp_2048x8_bist vs_ssp_3(
`else
vs_hdsp_2048x8 vs_ssp_3(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i_ram_3),
.mbist_so_o(mbist_so_o_ram_3),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di[31:24]),
.WEN(~we[3]),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq[31:24])
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S2 ramb4_s2_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[1:0]),
.EN(ce),
.WE(we[0]),
.DO(doq[1:0])
);
//
// Block 1
//
RAMB4_S2 ramb4_s2_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[3:2]),
.EN(ce),
.WE(we[0]),
.DO(doq[3:2])
);
//
// Block 2
//
RAMB4_S2 ramb4_s2_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[5:4]),
.EN(ce),
.WE(we[0]),
.DO(doq[5:4])
);
//
// Block 3
//
RAMB4_S2 ramb4_s2_3(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:6]),
.EN(ce),
.WE(we[0]),
.DO(doq[7:6])
);
//
// Block 4
//
RAMB4_S2 ramb4_s2_4(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[9:8]),
.EN(ce),
.WE(we[1]),
.DO(doq[9:8])
);
//
// Block 5
//
RAMB4_S2 ramb4_s2_5(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[11:10]),
.EN(ce),
.WE(we[1]),
.DO(doq[11:10])
);
//
// Block 6
//
RAMB4_S2 ramb4_s2_6(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[13:12]),
.EN(ce),
.WE(we[1]),
.DO(doq[13:12])
);
//
// Block 7
//
RAMB4_S2 ramb4_s2_7(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:14]),
.EN(ce),
.WE(we[1]),
.DO(doq[15:14])
);
//
// Block 8
//
RAMB4_S2 ramb4_s2_8(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[17:16]),
.EN(ce),
.WE(we[2]),
.DO(doq[17:16])
);
//
// Block 9
//
RAMB4_S2 ramb4_s2_9(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[19:18]),
.EN(ce),
.WE(we[2]),
.DO(doq[19:18])
);
//
// Block 10
//
RAMB4_S2 ramb4_s2_10(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[21:20]),
.EN(ce),
.WE(we[2]),
.DO(doq[21:20])
);
//
// Block 11
//
RAMB4_S2 ramb4_s2_11(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[23:22]),
.EN(ce),
.WE(we[2]),
.DO(doq[23:22])
);
//
// Block 12
//
RAMB4_S2 ramb4_s2_12(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[25:24]),
.EN(ce),
.WE(we[3]),
.DO(doq[25:24])
);
//
// Block 13
//
RAMB4_S2 ramb4_s2_13(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[27:26]),
.EN(ce),
.WE(we[3]),
.DO(doq[27:26])
);
//
// Block 14
//
RAMB4_S2 ramb4_s2_14(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[29:28]),
.EN(ce),
.WE(we[3]),
.DO(doq[29:28])
);
//
// Block 15
//
RAMB4_S2 ramb4_s2_15(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[31:30]),
.EN(ce),
.WE(we[3]),
.DO(doq[31:30])
);
`else
`ifdef OR1200_XILINX_RAMB16
//
// Instantiation of FPGA memory:
//
// Virtex4/Spartan3E
//
// Added By Nir Mor
//
//
// Block 0
//
RAMB16_S9 ramb16_s9_0(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[7:0]),
.DIP(1'b0),
.EN(ce),
.WE(we[0]),
.DO(doq[7:0]),
.DOP()
);
//
// Block 1
//
RAMB16_S9 ramb16_s9_1(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[15:8]),
.DIP(1'b0),
.EN(ce),
.WE(we[1]),
.DO(doq[15:8]),
.DOP()
);
//
// Block 2
//
RAMB16_S9 ramb16_s9_2(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[23:16]),
.DIP(1'b0),
.EN(ce),
.WE(we[2]),
.DO(doq[23:16]),
.DOP()
);
//
// Block 3
//
RAMB16_S9 ramb16_s9_3(
.CLK(clk),
.SSR(rst),
.ADDR(addr),
.DI(di[31:24]),
.DIP(1'b0),
.EN(ce),
.WE(we[3]),
.DO(doq[31:24]),
.DOP()
);
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [7:0] mem_0 [2047:0]; // RAM content
reg [7:0] mem_1 [2047:0]; // RAM content
reg [7:0] mem_2 [2047:0]; // RAM content
reg [7:0] mem_3 [2047:0]; // RAM content
reg [10:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? {mem_3[addr_reg], mem_2[addr_reg], mem_1[addr_reg], mem_0[addr_reg]} : {32{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 11'h000;
else if (ce)
addr_reg <= #1 addr;
//
// RAM write byte 0
//
always @(posedge clk)
if (ce && we[0])
mem_0[addr] <= #1 di[7:0];
//
// RAM write byte 1
//
always @(posedge clk)
if (ce && we[1])
mem_1[addr] <= #1 di[15:8];
//
// RAM write byte 2
//
always @(posedge clk)
if (ce && we[2])
mem_2[addr] <= #1 di[23:16];
//
// RAM write byte 3
//
always @(posedge clk)
if (ce && we[3])
mem_3[addr] <= #1 di[31:24];
`endif // !OR1200_XILINX_RAMB16
`endif // !OR1200_XILINX_RAMB4
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2009 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1
// \ \ Description : Xilinx Functional Simulation Library Component
// / / Clock Buffer
// /___/ /\ Filename : AUTOBUF.v
// \ \ / \ Timestamp :
// \___\/\___\
//
// Revision:
// 04/08/08 - Initial version.
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module AUTOBUF (O, I);
parameter BUFFER_TYPE = "AUTO";
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output O;
input I;
initial begin
case (BUFFER_TYPE)
"AUTO" : ;
"BUF" : ;
"BUFG" : ;
"BUFGP" : ;
"BUFH" : ;
"BUFIO" : ;
"BUFIO2" : ;
"BUFIO2FB" : ;
"BUFR" : ;
"IBUF" : ;
"IBUFG" : ;
"NONE" : ;
"OBUF" : ;
default : begin
$display("Attribute Syntax Error : The Attribute BUFFER_TYPE on AUTOBUF instance %m is set to %s. Legal values for this attribute are AUTO, BUF, BUFG, BUFGP, BUFH, BUFIO, BUFIO2, BUFIO2FB, BUFR, IBUF, IBUFG, NONE, and OBUF.", BUFFER_TYPE);
end
endcase
end
buf B1 (O, I);
`ifdef XIL_TIMING
specify
(I => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_x_ddr_if_post_fifo.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Feb 08 2011
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Extends the depth of a PHASER IN_FIFO up to 4 entries
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_0_ddr_if_post_fifo #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter DEPTH = 4, // # of entries
parameter WIDTH = 32 // data bus width
)
(
input clk, // clock
input rst, // synchronous reset
input [3:0] empty_in,
input rd_en_in,
input [WIDTH-1:0] d_in, // write data from controller
output empty_out,
output byte_rd_en,
output [WIDTH-1:0] d_out // write data to OUT_FIFO
);
// # of bits used to represent read/write pointers
localparam PTR_BITS
= (DEPTH == 2) ? 1 :
(((DEPTH == 3) || (DEPTH == 4)) ? 2 : 'bx);
integer i;
reg [WIDTH-1:0] mem[0:DEPTH-1];
(* max_fanout = 40 *) reg [4:0] my_empty /* synthesis syn_maxfan = 3 */;
(* max_fanout = 40 *) reg [1:0] my_full /* synthesis syn_maxfan = 3 */;
reg [PTR_BITS-1:0] rd_ptr /* synthesis syn_maxfan = 10 */;
// Register duplication to reduce the fan out
(* KEEP = "TRUE" *) reg [PTR_BITS-1:0] rd_ptr_timing /* synthesis syn_maxfan = 10 */;
reg [PTR_BITS-1:0] wr_ptr /* synthesis syn_maxfan = 10 */;
wire [WIDTH-1:0] mem_out;
(* max_fanout = 40 *) wire wr_en /* synthesis syn_maxfan = 10 */;
task updt_ptrs;
input rd;
input wr;
reg [1:0] next_rd_ptr;
reg [1:0] next_wr_ptr;
begin
next_rd_ptr = (rd_ptr + 1'b1)%DEPTH;
next_wr_ptr = (wr_ptr + 1'b1)%DEPTH;
casez ({rd, wr, my_empty[1], my_full[1]})
4'b00zz: ; // No access, do nothing
4'b0100: begin
// Write when neither empty, nor full; check for full
wr_ptr <= #TCQ next_wr_ptr;
my_full[0] <= #TCQ (next_wr_ptr == rd_ptr);
my_full[1] <= #TCQ (next_wr_ptr == rd_ptr);
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0110: begin
// Write when empty; no need to check for full
wr_ptr <= #TCQ next_wr_ptr;
my_empty <= #TCQ 5'b00000;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b1000: begin
// Read when neither empty, nor full; check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_empty[0] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[1] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[2] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[3] <= #TCQ (next_rd_ptr == wr_ptr);
my_empty[4] <= #TCQ (next_rd_ptr == wr_ptr);
end
4'b1001: begin
// Read when full; no need to check for empty
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
my_full[0] <= #TCQ 1'b0;
my_full[1] <= #TCQ 1'b0;
end
4'b1100, 4'b1101, 4'b1110: begin
// Read and write when empty, full, or neither empty/full; no need
// to check for empty or full conditions
rd_ptr <= #TCQ next_rd_ptr;
rd_ptr_timing <= #TCQ next_rd_ptr;
wr_ptr <= #TCQ next_wr_ptr;
//mem[wr_ptr] <= #TCQ d_in;
end
4'b0101, 4'b1010: ;
// Read when empty, Write when full; Keep all pointers the same
// and don't change any of the flags (i.e. ignore the read/write).
// This might happen because a faulty DQS_FOUND calibration could
// result in excessive skew between when the various IN_FIFO's
// first become not empty. In this case, the data going to each
// post-FIFO/IN_FIFO should be read out and discarded
// synthesis translate_off
default: begin
// Covers any other cases, in particular for simulation if
// any signals are X's
$display("ERR %m @%t: Bad access: rd:%b,wr:%b,empty:%b,full:%b",
$time, rd, wr, my_empty[1], my_full[1]);
rd_ptr <= #TCQ 2'bxx;
rd_ptr_timing <= #TCQ 2'bxx;
wr_ptr <= #TCQ 2'bxx;
end
// synthesis translate_on
endcase
end
endtask
assign d_out = my_empty[4] ? d_in : mem_out;//mem[rd_ptr];
// The combined IN_FIFO + post FIFO is only "empty" when both are empty
assign empty_out = empty_in[0] & my_empty[0];
assign byte_rd_en = !empty_in[3] || !my_empty[3];
always @(posedge clk)
if (rst) begin
my_empty <= #TCQ 5'b11111;
my_full <= #TCQ 2'b00;
rd_ptr <= #TCQ 'b0;
rd_ptr_timing <= #TCQ 'b0;
wr_ptr <= #TCQ 'b0;
end else begin
// Special mode: If IN_FIFO has data, and controller is reading at
// the same time, then operate post-FIFO in "passthrough" mode (i.e.
// don't update any of the read/write pointers, and route IN_FIFO
// data to post-FIFO data)
if (my_empty[1] && !my_full[1] && rd_en_in && !empty_in[1]) ;
else
// Otherwise, we're writing to FIFO when IN_FIFO is not empty,
// and reading from the FIFO based on the rd_en_in signal (read
// enable from controller). The functino updt_ptrs should catch
// an illegal conditions.
updt_ptrs(rd_en_in, !empty_in[1]);
end
assign wr_en = (!empty_in[2] & ((!rd_en_in & !my_full[0]) |
(rd_en_in & !my_empty[2])));
always @ (posedge clk)
begin
if (wr_en)
mem[wr_ptr] <= #TCQ d_in;
end
assign mem_out = mem[rd_ptr_timing];
endmodule
|
//-----------------------------------------------------------------------------
// File : data_memory.v
// Creation date : 16.05.2017
// Creation time : 10:33:36
// Description :
// Created by : TermosPullo
// Tool : Kactus2 3.4.106 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:cpu.logic.test:data_memory:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/cpu.logic.test/data_memory/1.0/data_memory.1.0.xml
//-----------------------------------------------------------------------------
module data_memory #(
parameter DATA_WIDTH = 32, // Width for data.
parameter ADDR_WIDTH = 9, // Width of the addresses.
parameter MEMORY_SIZE = 128,
parameter AUB = 8
) (
// Interface: slave
input [ADDR_WIDTH-1:0] adr_i,
input write,
input [DATA_WIDTH-1:0] write_data,
output reg [DATA_WIDTH-1:0] read_data,
// These ports are not in any interface
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i // The mandatory reset, as this is synchronous logic.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
reg [AUB-1:0] data_memory [MEMORY_SIZE-1:0];
localparam AU_IN_DATA = DATA_WIDTH/AUB;
// Used to index AUBs to data io.
integer index;
always @(posedge clk_i or posedge rst_i) begin
if(rst_i == 1'b1) begin
read_data <= 0;
end
else begin
if (adr_i < MEMORY_SIZE && adr_i >= 0) begin
if (write == 1) begin
// Writing: Pick every byte from the input and place them to correct addresses.
for (index = 0; index < AU_IN_DATA; index = index + 1) begin
data_memory[adr_i + index] <= write_data[(index*AUB)+:AUB];
end
end
// Reading: Pick every byte from correct addresses and place them to the output.
for (index = 0; index < AU_IN_DATA; index = index + 1) begin
read_data[(index*AUB)+:AUB] <= data_memory[adr_i + index];
end
end
end
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : burst_00.v
// Description : Test burst read/write interfacing
// Author : Philip Tracton
// Created On : Tue Jun 28 11:31:45 2016
// Last Modified By: Philip Tracton
// Last Modified On: Tue Jun 28 11:31:45 2016
// Update Count : 0
// Status : Unknown, Use with caution!
`include "simulation_includes.vh"
module test_case (/*AUTOARG*/ ) ;
//
// Test Configuration
// These parameters need to be set for each test case
//
parameter simulation_name = "burst_00";
parameter number_of_tests = 15;
reg err;
reg [31:0] data_out;
reg [15:0] i;
reg [15:0] index ;
//
// Can't pass memories to tasks, so gigantic arrays!
//
reg [(16*7):0] write_mem = 0;
reg [(16*7):0] read_mem = 0;
initial begin
$display("Test 00 Case");
`TB.master_bfm.reset;
@(posedge `WB_RST);
@(negedge `WB_RST);
@(posedge `WB_CLK);
@(negedge `ADXL362_RESET);
`SIMPLE_SPI_INIT;
`ADXL362_WRITE_DOUBLE_REGISTER(`ADXL362_THRESH_ACT_LOW, 16'h6507);
`ADXL362_CHECK_DOUBLE_REGISTER(`ADXL362_THRESH_ACT_LOW, 16'h507);
repeat(100) @(posedge `WB_CLK);
for (i = 0; i< 14; i= i+1) begin
write_mem[(i*8)+7 -: 8] = i | 8'h80;
end
repeat(100) @(posedge `WB_CLK);
`ADXL362_WRITE_BURST_REGISTERS(`ADXL362_THRESH_ACT_LOW, write_mem, 14);
repeat(50) @(posedge `WB_CLK);
`ADXL362_READ_BURST_REGISTERS(`ADXL362_THRESH_ACT_LOW, read_mem, 14);
//$display("Read Mem 0x%x", read_mem);
`TEST_COMPARE("Reg 0", 8'h80, read_mem[7:0]);
`TEST_COMPARE("Reg 1", 8'h01, read_mem[15:8]);
`TEST_COMPARE("Reg 2", 8'h82, read_mem[23:16]);
`TEST_COMPARE("Reg 3", 8'h83, read_mem[31:24]);
`TEST_COMPARE("Reg 4", 8'h04, read_mem[39:32]);
`TEST_COMPARE("Reg 5", 8'h85, read_mem[47:40]);
`TEST_COMPARE("Reg 6", 8'h86, read_mem[55:48]);
`TEST_COMPARE("Reg 7", 8'h00, read_mem[63:56]);
`TEST_COMPARE("Reg 8", 8'h08, read_mem[71:64]);
`TEST_COMPARE("Reg 9", 8'h89, read_mem[79:72]);
`TEST_COMPARE("Reg 10", 8'h8a, read_mem[87:80]);
`TEST_COMPARE("Reg 11", 8'h8b, read_mem[95:88]);
`TEST_COMPARE("Reg 12", 8'h8c, read_mem[103:96]);
`TEST_COMPARE("Reg 13", 8'h8d, read_mem[111:104]);
/* -----\/----- EXCLUDED -----\/-----
$display("MEM 0: 0x%x", read_mem[07:00]);
$display("MEM 1: 0x%x", read_mem[15:08]);
$display("MEM 2: 0x%x", read_mem[23:16]);
$display("MEM 3: 0x%x", read_mem[31:24]);
$display("MEM 4: 0x%x", read_mem[39:32]);
$display("MEM 5: 0x%x", read_mem[47:40]);
$display("MEM 6: 0x%x", read_mem[55:48]);
$display("MEM 7: 0x%x", read_mem[63:56]);
$display("MEM 8: 0x%x", read_mem[71:64]);
$display("MEM 9: 0x%x", read_mem[79:72]);
$display("MEM 10: 0x%x", read_mem[87:80]);
$display("MEM 11: 0x%x", read_mem[95:88]);
$display("MEM 12: 0x%x", read_mem[103:96]);
$display("MEM 13: 0x%x", read_mem[111:104]);
-----/\----- EXCLUDED -----/\----- */
repeat(10) @(posedge `WB_CLK);
`TEST_COMPLETE;
end
endmodule // test_case
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
//// ////
//// Memory Buffer Arbiter ////
//// Arbitrates between the internal DMA and external bus ////
//// interface for the internal buffer memory ////
//// ////
//// Author: Rudolf Usselmann ////
//// [email protected] ////
//// ////
//// ////
//// Downloaded from: http://www.opencores.org/cores/usb/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000-2003 Rudolf Usselmann ////
//// www.asics.ws ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// CVS Log
//
// $Id: usbf_mem_arb.v,v 1.1 2008/05/07 22:43:23 daughtry Exp $
//
// $Date: 2008/05/07 22:43:23 $
// $Revision: 1.1 $
// $Author: daughtry $
// $Locker: $
// $State: Exp $
//
// Change History:
// $Log: usbf_mem_arb.v,v $
// Revision 1.1 2008/05/07 22:43:23 daughtry
// Initial Demo RTL check-in
//
// Revision 1.3 2003/10/17 02:36:57 rudi
// - Disabling bit stuffing and NRZI encoding during speed negotiation
// - Now the core can send zero size packets
// - Fixed register addresses for some of the higher endpoints
// (conversion between decimal/hex was wrong)
// - The core now does properly evaluate the function address to
// determine if the packet was intended for it.
// - Various other minor bugs and typos
//
// Revision 1.2 2001/11/04 12:22:45 rudi
//
// - Fixed previous fix (brocke something else ...)
// - Majore Synthesis cleanup
//
// Revision 1.1 2001/08/03 05:30:09 rudi
//
//
// 1) Reorganized directory structure
//
// Revision 1.2 2001/03/31 13:00:51 rudi
//
// - Added Core configuration
// - Added handling of OUT packets less than MAX_PL_SZ in DMA mode
// - Modified WISHBONE interface and sync logic
// - Moved SSRAM outside the core (added interface)
// - Many small bug fixes ...
//
// Revision 1.0 2001/03/07 09:17:12 rudi
//
//
// Changed all revisions to revision 1.0. This is because OpenCores CVS
// interface could not handle the original '0.1' revision ....
//
// Revision 0.1.0.1 2001/02/28 08:10:52 rudi
// Initial Release
//
//
`include "usbf_defines.v"
module usbf_mem_arb( phy_clk, wclk, rst,
// SSRAM Interface
sram_adr, sram_din, sram_dout, sram_re, sram_we,
// IDMA Memory Interface
madr, mdout, mdin, mwe, mreq, mack,
// WISHBONE Memory Interface
wadr, wdout, wdin, wwe, wreq, wack
);
parameter SSRAM_HADR = 14;
input phy_clk, wclk, rst;
output [SSRAM_HADR:0] sram_adr;
input [31:0] sram_din;
output [31:0] sram_dout;
output sram_re, sram_we;
input [SSRAM_HADR:0] madr;
output [31:0] mdout;
input [31:0] mdin;
input mwe;
input mreq;
output mack;
input [SSRAM_HADR:0] wadr;
output [31:0] wdout;
input [31:0] wdin;
input wwe;
input wreq;
output wack;
///////////////////////////////////////////////////////////////////
//
// Local Wires and Registers
//
wire wsel;
reg [SSRAM_HADR:0] sram_adr;
reg [31:0] sram_dout;
reg sram_we;
wire mack;
wire mcyc;
reg wack_r;
///////////////////////////////////////////////////////////////////
//
// Memory Arbiter Logic
//
// IDMA has always first priority
// -----------------------------------------
// Ctrl Signals
assign wsel = (wreq | wack) & !mreq;
// -----------------------------------------
// SSRAM Specific
// Data Path
always @(wsel or wdin or mdin)
if(wsel) sram_dout = wdin;
else sram_dout = mdin;
// Address Path
always @(wsel or wadr or madr)
if(wsel) sram_adr = wadr;
else sram_adr = madr;
// Write Enable Path
always @(wsel or wwe or wreq or mwe or mcyc)
if(wsel) sram_we = wreq & wwe;
else sram_we = mwe & mcyc;
assign sram_re = 1'b1;
// -----------------------------------------
// IDMA specific
assign mdout = sram_din;
assign mack = mreq;
assign mcyc = mack; // Qualifier for writes
// -----------------------------------------
// WISHBONE specific
assign wdout = sram_din;
assign wack = wack_r & !mreq;
`ifdef USBF_ASYNC_RESET
always @(posedge phy_clk or negedge rst)
`else
always @(posedge phy_clk)
`endif
//XLNX_MODIFIED this is going to V5 and low resets tie up lut resources
//changing
// if(!rst) wack_r <= 1'b0;
//to the prefered high reset
if(rst) wack_r <= 1'b0;
else wack_r <= wreq & !mreq & !wack;
endmodule
|
//--------------------------------------------------------------------------------
// receiver.vhd
//
// Copyright (C) 2006 Michael Poppitz
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
//
//--------------------------------------------------------------------------------
//
// Details: http://www.sump.org/projects/analyzer/
//
// Receives commands from the serial port. The first byte is the commands
// opcode, the following (optional) four byte are the command data.
// Commands that do not have the highest bit in their opcode set are
// considered short commands without data (1 byte long). All other commands are
// long commands which are 5 bytes long.
//
// After a full command has been received it will be kept available for 10 cycles
// on the op and data outputs. A valid command can be detected by checking if the
// execute output is set. After 10 cycles the registers will be cleared
// automatically and the receiver waits for new data from the serial port.
//
//--------------------------------------------------------------------------------
`timescale 1ns/100ps
module receiver(
clock, trxClock, reset, rx,
// outputs...
op, data, execute);
parameter [31:0] FREQ = 100000000;
parameter [31:0] RATE = 115200;
input clock;
input trxClock;
input reset;
input rx;
output [7:0] op;
output [31:0] data;
output execute;
parameter [2:0]
INIT = 3'h0,
WAITSTOP = 3'h1,
WAITSTART = 3'h2,
WAITBEGIN = 3'h3,
READBYTE = 3'h4,
ANALYZE = 3'h5,
READY = 3'h6;
parameter BITLENGTH = FREQ / RATE; // 100M / 115200 ~= 868
reg [9:0] counter, next_counter; // clock prescaling counter
reg [3:0] bitcount, next_bitcount; // count rxed bits of current byte
reg [2:0] bytecount, next_bytecount; // count rxed bytes of current command
reg [2:0] state, next_state; // receiver state
reg [7:0] opcode, next_opcode; // opcode byte
reg [31:0] databuf, next_databuf; // data dword
reg execute, next_execute;
assign op = opcode;
assign data = databuf;
always @(posedge clock or posedge reset)
begin
if (reset)
state = INIT;
else state = next_state;
counter = next_counter;
bitcount = next_bitcount;
bytecount = next_bytecount;
databuf = next_databuf;
opcode = next_opcode;
execute = next_execute;
end
always #1
begin
next_state = state;
next_counter = counter;
next_bitcount = bitcount;
next_bytecount = bytecount;
next_opcode = opcode;
next_databuf = databuf;
next_execute = 1'b0;
case(state)
INIT :
begin
next_counter = 0;
next_bitcount = 0;
next_bytecount = 0;
next_opcode = 0;
next_databuf = 0;
next_state = WAITSTOP;
end
WAITSTOP : // reset uart
begin
if (rx) next_state = WAITSTART;
end
WAITSTART : // wait for start bit
begin
if (!rx) next_state = WAITBEGIN;
end
WAITBEGIN : // wait for first half of start bit
begin
if (counter == (BITLENGTH / 2))
begin
next_counter = 0;
next_state = READBYTE;
end
else if (trxClock)
next_counter = counter + 1;
end
READBYTE : // receive byte
begin
if (counter == BITLENGTH)
begin
next_counter = 0;
next_bitcount = bitcount + 1;
if (bitcount == 4'h8)
begin
next_bytecount = bytecount + 1;
next_state = ANALYZE;
end
else if (bytecount == 0)
begin
next_opcode = {rx,opcode[7:1]};
next_databuf = databuf;
end
else
begin
next_opcode = opcode;
next_databuf = {rx,databuf[31:1]};
end
end
else if (trxClock)
next_counter = counter + 1;
end
ANALYZE : // check if long or short command has been fully received
begin
next_counter = 0;
next_bitcount = 0;
if (bytecount == 3'h5) // long command when 5 bytes have been received
next_state = READY;
else if (!opcode[7]) // short command when set flag not set
next_state = READY;
else next_state = WAITSTOP; // otherwise continue receiving
end
READY : // done, give 10 cycles for processing
begin
next_counter = counter + 1;
if (counter == 4'd10)
next_state = INIT;
else next_state = state;
end
endcase
next_execute = (next_state == READY);
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_64x512.v
// /___/ /\ Timestamp: Thu Nov 8 18:48:58 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_64x512.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_64x512.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_64x512.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_64x512.v
// # of Modules : 1
// Design Name : fifo_64x512
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_64x512 (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [63 : 0] dout;
input [63 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
LUT3 #(
.INIT ( 8'hF4 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I1(rd_en),
.I2(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT6 #(
.INIT ( 64'hAAFEAAFAFAFEFAFA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
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.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({din[63], din[62], din[61], din[60], din[59], din[58], din[57], din[56], din[55], din[54], din[53], din[52], din[51], din[50], din[49],
din[48], din[47], din[46], din[45], din[44], din[43], din[42], din[41], din[40], din[39], din[38], din[37], din[36], din[35], din[34], din[33],
din[32], din[31], din[30], din[29], din[28], din[27], din[26], din[25], din[24], din[23], din[22], din[21], din[20], din[19], din[18], din[17],
din[16], din[15], din[14], din[13], din[12], din[11], din[10], din[9], din[8], din[7], din[6], din[5], din[4], din[3], din[2], din[1], din[0]}),
.DIP({N0, N0, N0, N0, N0, N0, N0, N0}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({dout[63], dout[62], dout[61], dout[60], dout[59], dout[58], dout[57], dout[56], dout[55], dout[54], dout[53], dout[52], dout[51], dout[50],
dout[49], dout[48], dout[47], dout[46], dout[45], dout[44], dout[43], dout[42], dout[41], dout[40], dout[39], dout[38], dout[37], dout[36], dout[35],
dout[34], dout[33], dout[32], dout[31], dout[30], dout[29], dout[28], dout[27], dout[26], dout[25], dout[24], dout[23], dout[22], dout[21], dout[20],
dout[19], dout[18], dout[17], dout[16], dout[15], dout[14], dout[13], dout[12], dout[11], dout[10], dout[9], dout[8], dout[7], dout[6], dout[5],
dout[4], dout[3], dout[2], dout[1], dout[0]}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<0>_UNCONNECTED
}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
`timescale 1 ns / 1 ps
module system (
input clk,
input resetn,
output trap,
output reg [7:0] out_byte,
output reg out_byte_en
);
// 0x2000 32bit words = 0x8000 Byte = 32kByte memory
parameter MEMW_SIZE = 16'h8000;
integer tb_idx;
wire mem_valid;
wire mem_instr;
reg mem_ready;
reg mem_ready_last;
wire [31:0] mem_addr;
wire [31:0] mem_wdata;
wire [3:0] mem_wstrb;
reg [31:0] mem_rdata;
wire uart_cs;
wire [3:0] uart_wstrb;
wire [31:0] uart_rdata;
wire [31:0] irqs;
wire [31:0] eois;
picorv32 picorv32_core (
.clk (clk ),
.resetn (resetn ),
.trap (trap ),
.mem_valid (mem_valid ),
.mem_instr (mem_instr ),
.mem_ready (mem_ready ),
.mem_addr (mem_addr ),
.mem_wdata (mem_wdata ),
.mem_wstrb (mem_wstrb ),
.mem_rdata (mem_rdata ),
.irq(irqs),
.eoi(eois)
);
`ifndef MEM_FILENAME
simuart uart(
.clk(clk),
.cs(uart_cs),
.bus_addr(mem_addr),
.bus_wr_val(mem_wdata),
.bus_bytesel(uart_wstrb),
.bus_ack(),
.bus_data(uart_rdata),
.inter(irqs[0]),
.intack(eois[0])
);
`else
assign uart_rdata = 32'b0;
assign irqs = 32'b0;
`endif
assign irqs[31:1] = 31'b0;
assign uart_cs = mem_addr[31:4] == 28'h1000000 && mem_valid;
assign uart_wstrb = mem_wstrb & mem_ready;
reg [31:0] memory [0:MEMW_SIZE-1];
initial begin
for (tb_idx=0; tb_idx < MEMW_SIZE; tb_idx=tb_idx+1)
memory[tb_idx] = 32'b0;
`ifdef MEM_FILENAME
$readmemh(`MEM_FILENAME, memory);
`else
$readmemh("../firmware.hex", memory);
`endif
end
reg [31:0] m_read_data;
reg m_read_en;
always @(posedge clk) begin
m_read_en <= 0;
mem_ready <= mem_valid && !mem_ready_last && !mem_ready && m_read_en;
mem_ready_last <= mem_ready;
out_byte_en <= 0;
(* parallel_case *)
case (1)
mem_valid && !mem_ready && !mem_wstrb && (mem_addr >> 2) < MEMW_SIZE: begin
m_read_en <= 1;
m_read_data <= memory[mem_addr >> 2];
mem_rdata <= m_read_data;
end
mem_valid && !mem_ready && |mem_wstrb && (mem_addr >> 2) < MEMW_SIZE: begin
if (mem_wstrb[0]) memory[mem_addr >> 2][ 7: 0] <= mem_wdata[ 7: 0];
if (mem_wstrb[1]) memory[mem_addr >> 2][15: 8] <= mem_wdata[15: 8];
if (mem_wstrb[2]) memory[mem_addr >> 2][23:16] <= mem_wdata[23:16];
if (mem_wstrb[3]) memory[mem_addr >> 2][31:24] <= mem_wdata[31:24];
mem_ready <= 1;
end
mem_valid && !mem_ready && !mem_wstrb && uart_cs: begin
m_read_en <= 1;
mem_rdata <= uart_rdata;
//mem_rdata <= m_read_data;
end
mem_valid && !mem_ready && |mem_wstrb && mem_addr == 32'h2000_0000: begin
out_byte_en <= 1;
out_byte <= mem_wdata;
mem_ready <= 1;
end
mem_valid && !mem_ready && |mem_wstrb : begin
mem_ready <= 1;
end
endcase
if (resetn && out_byte_en) begin
$write("%c", out_byte);
end
end
endmodule
|
//======================================================================
//
// tb_aes_core.v
// -------------
// Testbench for the AES block cipher core.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014, Secworks Sweden AB
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
// conditions are met:
//
// 1. Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
`default_nettype none
module tb_aes_core();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter DEBUG = 0;
parameter DUMP_WAIT = 0;
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
parameter AES_128_BIT_KEY = 0;
parameter AES_256_BIT_KEY = 1;
parameter AES_DECIPHER = 1'b0;
parameter AES_ENCIPHER = 1'b1;
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
reg [31 : 0] cycle_ctr;
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
reg tb_clk;
reg tb_reset_n;
reg tb_encdec;
reg tb_init;
reg tb_next;
wire tb_ready;
reg [255 : 0] tb_key;
reg tb_keylen;
reg [127 : 0] tb_block;
wire [127 : 0] tb_result;
wire tb_result_valid;
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
aes_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
.encdec(tb_encdec),
.init(tb_init),
.next(tb_next),
.ready(tb_ready),
.key(tb_key),
.keylen(tb_keylen),
.block(tb_block),
.result(tb_result)
);
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
//----------------------------------------------------------------
// sys_monitor()
//
// An always running process that creates a cycle counter and
// conditionally displays information about the DUT.
//----------------------------------------------------------------
always
begin : sys_monitor
cycle_ctr = cycle_ctr + 1;
#(CLK_PERIOD);
if (DEBUG)
begin
dump_dut_state();
end
end
//----------------------------------------------------------------
// dump_dut_state()
//
// Dump the state of the dump when needed.
//----------------------------------------------------------------
task dump_dut_state;
begin
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
$display("encdec = 0x%01x, init = 0x%01x, next = 0x%01x",
dut.encdec, dut.init, dut.next);
$display("keylen = 0x%01x, key = 0x%032x ", dut.keylen, dut.key);
$display("block = 0x%032x", dut.block);
$display("");
$display("ready = 0x%01x", dut.ready);
$display("result_valid = 0x%01x, result = 0x%032x",
dut.result_valid, dut.result);
$display("");
$display("Encipher state::");
$display("enc_ctrl = 0x%01x, round_ctr = 0x%01x",
dut.enc_block.enc_ctrl_reg, dut.enc_block.round_ctr_reg);
$display("");
end
endtask // dump_dut_state
//----------------------------------------------------------------
// dump_keys()
//
// Dump the keys in the key memory of the dut.
//----------------------------------------------------------------
task dump_keys;
begin
$display("State of key memory in DUT:");
$display("key[00] = 0x%016x", dut.keymem.key_mem[00]);
$display("key[01] = 0x%016x", dut.keymem.key_mem[01]);
$display("key[02] = 0x%016x", dut.keymem.key_mem[02]);
$display("key[03] = 0x%016x", dut.keymem.key_mem[03]);
$display("key[04] = 0x%016x", dut.keymem.key_mem[04]);
$display("key[05] = 0x%016x", dut.keymem.key_mem[05]);
$display("key[06] = 0x%016x", dut.keymem.key_mem[06]);
$display("key[07] = 0x%016x", dut.keymem.key_mem[07]);
$display("key[08] = 0x%016x", dut.keymem.key_mem[08]);
$display("key[09] = 0x%016x", dut.keymem.key_mem[09]);
$display("key[10] = 0x%016x", dut.keymem.key_mem[10]);
$display("key[11] = 0x%016x", dut.keymem.key_mem[11]);
$display("key[12] = 0x%016x", dut.keymem.key_mem[12]);
$display("key[13] = 0x%016x", dut.keymem.key_mem[13]);
$display("key[14] = 0x%016x", dut.keymem.key_mem[14]);
$display("");
end
endtask // dump_keys
//----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
//----------------------------------------------------------------
task reset_dut;
begin
$display("*** Toggle reset.");
tb_reset_n = 0;
#(2 * CLK_PERIOD);
tb_reset_n = 1;
end
endtask // reset_dut
//----------------------------------------------------------------
// init_sim()
//
// Initialize all counters and testbed functionality as well
// as setting the DUT inputs to defined values.
//----------------------------------------------------------------
task init_sim;
begin
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
tb_clk = 0;
tb_reset_n = 1;
tb_encdec = 0;
tb_init = 0;
tb_next = 0;
tb_key = {8{32'h00000000}};
tb_keylen = 0;
tb_block = {4{32'h00000000}};
end
endtask // init_sim
//----------------------------------------------------------------
// display_test_result()
//
// Display the accumulated test results.
//----------------------------------------------------------------
task display_test_result;
begin
if (error_ctr == 0)
begin
$display("*** All %02d test cases completed successfully", tc_ctr);
end
else
begin
$display("*** %02d tests completed - %02d test cases did not complete successfully.",
tc_ctr, error_ctr);
end
end
endtask // display_test_result
//----------------------------------------------------------------
// wait_ready()
//
// Wait for the ready flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing and will in fact at some
// point set the flag.
//----------------------------------------------------------------
task wait_ready;
begin
while (!tb_ready)
begin
#(CLK_PERIOD);
if (DUMP_WAIT)
begin
dump_dut_state();
end
end
end
endtask // wait_ready
//----------------------------------------------------------------
// wait_valid()
//
// Wait for the result_valid flag in the dut to be set.
//
// Note: It is the callers responsibility to call the function
// when the dut is actively processing a block and will in fact
// at some point set the flag.
//----------------------------------------------------------------
task wait_valid;
begin
while (!tb_result_valid)
begin
#(CLK_PERIOD);
end
end
endtask // wait_valid
//----------------------------------------------------------------
// ecb_mode_single_block_test()
//
// Perform ECB mode encryption or decryption single block test.
//----------------------------------------------------------------
task ecb_mode_single_block_test(input [7 : 0] tc_number,
input encdec,
input [255 : 0] key,
input key_length,
input [127 : 0] block,
input [127 : 0] expected);
begin
$display("*** TC %0d ECB mode test started.", tc_number);
tc_ctr = tc_ctr + 1;
// Init the cipher with the given key and length.
tb_key = key;
tb_keylen = key_length;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
wait_ready();
$display("Key expansion done");
$display("");
dump_keys();
// Perform encipher och decipher operation on the block.
tb_encdec = encdec;
tb_block = block;
tb_next = 1;
#(2 * CLK_PERIOD);
tb_next = 0;
wait_ready();
if (tb_result == expected)
begin
$display("*** TC %0d successful.", tc_number);
$display("");
end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_number);
$display("Expected: 0x%032x", expected);
$display("Got: 0x%032x", tb_result);
$display("");
error_ctr = error_ctr + 1;
end
end
endtask // ecb_mode_single_block_test
//----------------------------------------------------------------
// aes_core_test
// The main test functionality.
// Test vectors copied from the follwing NIST documents.
//
// NIST SP 800-38A:
// http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
//
// NIST FIPS-197, Appendix C:
// https://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.197.pdf
//
// Test cases taken from NIST SP 800-38A:
// http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf
//----------------------------------------------------------------
initial
begin : aes_core_test
reg [255 : 0] nist_aes128_key1;
reg [255 : 0] nist_aes128_key2;
reg [255 : 0] nist_aes256_key1;
reg [255 : 0] nist_aes256_key2;
reg [127 : 0] nist_plaintext0;
reg [127 : 0] nist_plaintext1;
reg [127 : 0] nist_plaintext2;
reg [127 : 0] nist_plaintext3;
reg [127 : 0] nist_plaintext4;
reg [127 : 0] nist_ecb_128_enc_expected0;
reg [127 : 0] nist_ecb_128_enc_expected1;
reg [127 : 0] nist_ecb_128_enc_expected2;
reg [127 : 0] nist_ecb_128_enc_expected3;
reg [127 : 0] nist_ecb_128_enc_expected4;
reg [127 : 0] nist_ecb_256_enc_expected0;
reg [127 : 0] nist_ecb_256_enc_expected1;
reg [127 : 0] nist_ecb_256_enc_expected2;
reg [127 : 0] nist_ecb_256_enc_expected3;
reg [127 : 0] nist_ecb_256_enc_expected4;
nist_aes128_key1 = 256'h2b7e151628aed2a6abf7158809cf4f3c00000000000000000000000000000000;
nist_aes128_key2 = 256'h000102030405060708090a0b0c0d0e0f00000000000000000000000000000000;
nist_aes256_key1 = 256'h603deb1015ca71be2b73aef0857d77811f352c073b6108d72d9810a30914dff4;
nist_aes256_key2 = 256'h000102030405060708090a0b0c0d0e0f101112131415161718191a1b1c1d1e1f;
nist_plaintext0 = 128'h6bc1bee22e409f96e93d7e117393172a;
nist_plaintext1 = 128'hae2d8a571e03ac9c9eb76fac45af8e51;
nist_plaintext2 = 128'h30c81c46a35ce411e5fbc1191a0a52ef;
nist_plaintext3 = 128'hf69f2445df4f9b17ad2b417be66c3710;
nist_plaintext4 = 128'h00112233445566778899aabbccddeeff;
nist_ecb_128_enc_expected0 = 128'h3ad77bb40d7a3660a89ecaf32466ef97;
nist_ecb_128_enc_expected1 = 128'hf5d3d58503b9699de785895a96fdbaaf;
nist_ecb_128_enc_expected2 = 128'h43b1cd7f598ece23881b00e3ed030688;
nist_ecb_128_enc_expected3 = 128'h7b0c785e27e8ad3f8223207104725dd4;
nist_ecb_128_enc_expected4 = 128'h69c4e0d86a7b0430d8cdb78070b4c55a;
nist_ecb_256_enc_expected0 = 128'hf3eed1bdb5d2a03c064b5a7e3db181f8;
nist_ecb_256_enc_expected1 = 128'h591ccb10d410ed26dc5ba74a31362870;
nist_ecb_256_enc_expected2 = 128'hb6ed21b99ca6f4f9f153e7b1beafed1d;
nist_ecb_256_enc_expected3 = 128'h23304b7a39f9f3ff067d8d8f9e24ecc7;
nist_ecb_256_enc_expected4 = 128'h8ea2b7ca516745bfeafc49904b496089;
$display(" -= Testbench for aes core started =-");
$display(" ================================");
$display("");
init_sim();
dump_dut_state();
reset_dut();
dump_dut_state();
$display("ECB 128 bit key tests");
$display("---------------------");
ecb_mode_single_block_test(8'h01, AES_ENCIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_plaintext0, nist_ecb_128_enc_expected0);
ecb_mode_single_block_test(8'h02, AES_ENCIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_plaintext1, nist_ecb_128_enc_expected1);
ecb_mode_single_block_test(8'h03, AES_ENCIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_plaintext2, nist_ecb_128_enc_expected2);
ecb_mode_single_block_test(8'h04, AES_ENCIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_plaintext3, nist_ecb_128_enc_expected3);
ecb_mode_single_block_test(8'h05, AES_DECIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_ecb_128_enc_expected0, nist_plaintext0);
ecb_mode_single_block_test(8'h06, AES_DECIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_ecb_128_enc_expected1, nist_plaintext1);
ecb_mode_single_block_test(8'h07, AES_DECIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_ecb_128_enc_expected2, nist_plaintext2);
ecb_mode_single_block_test(8'h08, AES_DECIPHER, nist_aes128_key1, AES_128_BIT_KEY,
nist_ecb_128_enc_expected3, nist_plaintext3);
ecb_mode_single_block_test(8'h09, AES_ENCIPHER, nist_aes128_key2, AES_128_BIT_KEY,
nist_plaintext4, nist_ecb_128_enc_expected4);
ecb_mode_single_block_test(8'h0a, AES_DECIPHER, nist_aes128_key2, AES_128_BIT_KEY,
nist_ecb_128_enc_expected4, nist_plaintext4);
$display("");
$display("ECB 256 bit key tests");
$display("---------------------");
ecb_mode_single_block_test(8'h10, AES_ENCIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_plaintext0, nist_ecb_256_enc_expected0);
ecb_mode_single_block_test(8'h11, AES_ENCIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_plaintext1, nist_ecb_256_enc_expected1);
ecb_mode_single_block_test(8'h12, AES_ENCIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_plaintext2, nist_ecb_256_enc_expected2);
ecb_mode_single_block_test(8'h13, AES_ENCIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_plaintext3, nist_ecb_256_enc_expected3);
ecb_mode_single_block_test(8'h14, AES_DECIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_ecb_256_enc_expected0, nist_plaintext0);
ecb_mode_single_block_test(8'h15, AES_DECIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_ecb_256_enc_expected1, nist_plaintext1);
ecb_mode_single_block_test(8'h16, AES_DECIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_ecb_256_enc_expected2, nist_plaintext2);
ecb_mode_single_block_test(8'h17, AES_DECIPHER, nist_aes256_key1, AES_256_BIT_KEY,
nist_ecb_256_enc_expected3, nist_plaintext3);
ecb_mode_single_block_test(8'h18, AES_ENCIPHER, nist_aes256_key2, AES_256_BIT_KEY,
nist_plaintext4, nist_ecb_256_enc_expected4);
ecb_mode_single_block_test(8'h19, AES_DECIPHER, nist_aes256_key2, AES_256_BIT_KEY,
nist_ecb_256_enc_expected4, nist_plaintext4);
display_test_result();
$display("");
$display("*** AES core simulation done. ***");
$finish;
end // aes_core_test
endmodule // tb_aes_core
//======================================================================
// EOF tb_aes_core.v
//======================================================================
|
// `define DEBUG
module mixer #(
parameter NUM_CH_IN = 8, // must be multiple of NUM_CH_OUT
parameter NUM_CH_IN_LOG2 = 3,
parameter NUM_CH_OUT = 2,
parameter NUM_CH_OUT_LOG2 = 1,
parameter VOL_WIDTH = 32
)(
input wire clk, // 49.152Mhz
input wire rst,
input wire [(NUM_CH_IN-1):0] rst_ch,
output wire [(NUM_CH_IN-1):0] pop_o, // optional: ack_i accepted any time
input wire [(NUM_CH_IN-1):0] ack_i,
input wire [(NUM_CH_IN*24-1):0] data_i,
input wire [(NUM_CH_IN*VOL_WIDTH-1):0] vol_i,
input wire [(NUM_CH_OUT-1):0] pop_i,
output wire [23:0] data_o,
output wire [(NUM_CH_OUT-1):0] ack_o);
parameter MULT_LATENCY = 6;
// Input ringbuf
wire [23:0] buffered_data [(NUM_CH_IN-1):0];
genvar igi;
generate
for (igi = 0; igi < NUM_CH_IN; igi = igi + 1) begin:gi
ringbuf #(.LEN(4), .LEN_LOG2(2)) rb(
.clk(clk), .rst(rst | rst_ch[igi]),
.data_i(data_i[(igi*24) +: 24]), .we_i(ack_i[igi]),
.pop_i(pop_o[igi]), .offset_i(0), .data_o(buffered_data[igi]));
end
endgenerate
// Sequencer
// OUTPUT:
parameter TIMESLICE = NUM_CH_IN/NUM_CH_OUT + MULT_LATENCY + 1 + 1; // saturate 1clk, sum 1clk
parameter TIMESLICE_LOG2 = NUM_CH_IN_LOG2-NUM_CH_OUT_LOG2 + 4; // assumes MULT_LATENCY + 1 + 1 < 16
reg [(NUM_CH_IN_LOG2-1):0] processing_in_ch_ff;
reg [(NUM_CH_OUT_LOG2-1):0] processing_out_ch_ff;
reg [(TIMESLICE_LOG2-1):0] timeslice_counter;
wire end_of_cycle = (timeslice_counter == TIMESLICE-1) ? 1'b1 : 1'b0;
always @(posedge clk) begin
if (rst) begin
processing_in_ch_ff <= 0;
processing_out_ch_ff <= 0;
timeslice_counter <= 0;
end else if (end_of_cycle) begin
timeslice_counter <= 0;
if (processing_out_ch_ff == NUM_CH_OUT-1) begin
processing_in_ch_ff <= 0;
processing_out_ch_ff <= 0;
end else begin
processing_in_ch_ff <= processing_out_ch_ff + 1;
processing_out_ch_ff <= processing_out_ch_ff + 1;
end
end else begin
processing_in_ch_ff <= processing_in_ch_ff + NUM_CH_OUT;
timeslice_counter <= timeslice_counter + 1;
end
end
// Cycle validity checker
reg cycle_valid_ff;
// - pop_i latch
reg [(NUM_CH_OUT-1):0] ack_pop_ff;
wire [(NUM_CH_OUT-1):0] pop_i_latched;
genvar igo;
generate
for (igo = 0; igo < NUM_CH_OUT; igo = igo + 1) begin:go
pop_latch pop_latch(
.clk(clk), .rst(rst),
.pop_i(pop_i[igo]),
.ack_pop_i(ack_pop_ff[igo]), .pop_latched_o(pop_i_latched[igo]));
end
endgenerate
// - cycle validity check
always @(posedge clk) begin
ack_pop_ff <= 0;
if (rst) begin
cycle_valid_ff <= 1'b0;
end else if (timeslice_counter == 0) begin
ack_pop_ff <= 1 << processing_out_ch_ff;
end else if (timeslice_counter == 1) begin
cycle_valid_ff <= pop_i_latched[processing_out_ch_ff];
end
end
// Supply mpcand
// OUTPUT:
wire [23:0] mpcand = buffered_data[processing_in_ch_ff];
// Supply scale
wire [(VOL_WIDTH-1):0] scale = 32'h01_000000; //vol_i[(processing_in_ch_ff*VOL_WIDTH) +: VOL_WIDTH];
// Multiplier
// OUTPUT:
wire [31:0] mprod;
mpemu_scale mp(
.clk(clk),
.mpcand_i(mpcand), .scale_i(scale),
.mprod_o(mprod));
// Satulated product
reg [23:0] saturated_mprod_ff;
always @(posedge clk) begin
if (mprod[31] == 1'b0) begin
// sum +
if (mprod[30:23] == 8'b0000_0000)
saturated_mprod_ff <= {1'b0, mprod[22:0]};
else
saturated_mprod_ff <= 24'h7f_ffff; // overflow
end else begin
// sum -
if (mprod[30:23] == 8'b1111_1111)
saturated_mprod_ff <= {1'b1, mprod[22:0]};
else
saturated_mprod_ff <= 24'h80_0000; // underflow
end
end
// - drop first MULT_LATENCY + 1 saturated products
reg [(MULT_LATENCY+1-1):0] kill_result_ff;
always @(posedge clk) begin
if (end_of_cycle)
kill_result_ff <= 0;
else
kill_result_ff <= {1'b1, kill_result_ff[(MULT_LATENCY+1-1):1]};
end
wire product_valid = kill_result_ff[0];
// Adder
reg [23:0] sum_ff; // FIXME: this should be >24bit
function [23:0] saturated_add(
input [23:0] a,
input [23:0] b);
reg [24:0] aext;
reg [24:0] bext;
reg [24:0] sumext;
begin
aext = {a[23], a};
bext = {b[23], b};
sumext = $signed(aext) + $signed(bext);
case (sumext[24:23])
2'b00, 2'b11: // sum is in expressible range
saturated_add = sumext[23:0];
2'b01: // overflow
saturated_add = 24'h7f_ffff;
2'b10: // underflow
saturated_add = 24'h80_0000;
endcase
end
endfunction
always @(posedge clk) begin
if (!product_valid) begin
sum_ff <= 0;
end else begin
`ifdef DEBUG
if (cycle_valid_ff)
$display("mixer outch: %d curr_sum: %h. mpcand %h * mplier %h = %h",
processing_out_ch_ff, $signed(sum_ff), $signed(mp.delayed_a2), $signed(mp.delayed_b2), $signed(saturated_mprod_ff));
`endif
sum_ff <= saturated_add(sum_ff, saturated_mprod_ff);
end
end
// Result
assign data_o = sum_ff;
assign ack_o = (end_of_cycle & cycle_valid_ff) << processing_out_ch_ff;
assign pop_o = {(NUM_CH_IN/NUM_CH_OUT){ack_o}};
endmodule
|
//deps: core.v
`timescale 1ns/1ps
module core_tb;
/*AUTOREGINPUT*/
// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)
reg clk; // To core of core.v
reg [31:0] dram_data_in; // To core of core.v
reg dram_data_valid; // To core of core.v
reg dram_write_complete; // To core of core.v
reg rst_n; // To core of core.v
reg rx; // To core of core.v
reg [3:0] switches; // To core of core.v
// End of automatics
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] LED; // From core of core.v
wire [23:0] dram_addr; // From core of core.v
wire [31:0] dram_data_out; // From core of core.v
wire dram_req_read; // From core of core.v
wire dram_req_write; // From core of core.v
wire snd_out; // From core of core.v
wire [3:0] snd_signals; // From core of core.v
wire tx; // From core of core.v
// End of automatics
core core(/*AUTOINST*/
// Outputs
.LED (LED[7:0]),
.tx (tx),
.snd_out (snd_out),
.snd_signals (snd_signals[3:0]),
.dram_data_out (dram_data_out[31:0]),
.dram_addr (dram_addr[23:0]),
.dram_req_read (dram_req_read),
.dram_req_write (dram_req_write),
// Inputs
.clk (clk),
.rst_n (rst_n),
.rx (rx),
.switches (switches[3:0]),
.dram_data_in (dram_data_in[31:0]),
.dram_data_valid (dram_data_valid),
.dram_write_complete (dram_write_complete));
initial begin
clk <= 0;
rst_n <= 0;
rx <= 1;
dram_data_in <= 32'hdeadbeef;
dram_data_valid <= 0;
dram_write_complete <= 0;
switches <= 0;
$dumpfile("dump.vcd");
$dumpvars;
end
always #5 clk <= ~clk;
initial begin
#20 rst_n <= 1;
#10000 $finish;
end
reg busy = 0;
always @(posedge clk) begin
if(dram_req_write && busy == 0) begin
busy <= 1;
#40 dram_write_complete <= 1;
end
if(dram_write_complete) begin
busy <= 0;
dram_write_complete <= 0;
end
if(dram_req_read && busy == 0) begin
busy <= 1;
#80 dram_data_valid <= 1;
end
if(dram_data_valid) begin
busy <= 0;
dram_data_valid <= 0;
end
end
endmodule
|
`timescale 1ns / 1ps
/*
* File : FIFO_NoFull_Count.v
* Creator(s) : Grant Ayers ([email protected])
*
* Modification History:
* Rev Date Initials Description of Change
* 1.0 24-May-2010 GEA Initial design.
*
* Standards/Formatting:
* Verilog 2001, 4 soft tab, wide column.
*
* Description:
* A synchronous FIFO of variable data width and depth. 'enQ' is ignored when
* the FIFO is full and 'deQ' is ignored when the FIFO is empty. If 'enQ' and
* 'deQ' are asserted simultaneously, the FIFO is unchanged and the output data
* is the same as the input data.
*
* This FIFO is "First word fall-through" meaning data can be read without
* asserting 'deQ' by merely supplying an address. This data is only valid
* when not writing and not empty (i.e., valid when ~(empty | enQ)).
* When 'deQ' is asserted, the data is "removed" from the FIFO and one location
* is freed.
*
* Variation:
* - There is no output to indicate the FIFO is full.
* - Output 'count' indicates how many elements are in the FIFO, from 0 to 256
* (for 8-bit ADDR_WIDTH).
*/
module FIFO_NoFull_Count(clock, reset, enQ, deQ, data_in, data_out, empty, count);
parameter DATA_WIDTH = 8;
parameter ADDR_WIDTH = 8;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
input clock;
input reset;
input enQ;
input deQ;
input [(DATA_WIDTH-1):0] data_in;
output [(DATA_WIDTH-1):0] data_out;
output empty;
output reg [(ADDR_WIDTH):0] count; // How many elements are in the FIFO (0->256)
reg [(ADDR_WIDTH-1):0] enQ_ptr, deQ_ptr; // Addresses for reading from and writing to internal memory
wire [(ADDR_WIDTH-1):0] addr = (enQ) ? enQ_ptr : deQ_ptr;
assign empty = (count == 0);
wire full = (count == (1 << ADDR_WIDTH));
wire [(DATA_WIDTH-1):0] w_data_out;
assign data_out = (enQ & deQ) ? data_in : w_data_out;
wire w_enQ = enQ & ~(full | deQ); // Mask 'enQ' when the FIFO is full or reading
wire w_deQ = deQ & ~(empty | enQ); // Mask 'deQ' when the FIFO is empty or writing
always @(posedge clock) begin
if (reset) begin
enQ_ptr <= 0;
deQ_ptr <= 0;
count <= 0;
end
else begin
enQ_ptr <= (w_enQ) ? enQ_ptr + 1'b1 : enQ_ptr;
deQ_ptr <= (w_deQ) ? deQ_ptr + 1'b1 : deQ_ptr;
count <= (w_enQ ~^ w_deQ) ? count : ((w_enQ) ? count + 1'b1 : count - 1'b1);
end
end
RAM_SP_AR #(
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
ram(
.clk (clock),
.addr (addr),
.we (w_enQ),
.din (data_in),
.dout (w_data_out)
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/29/2016 05:57:16 AM
// Design Name:
// Module Name: Testbench_FPU_Add_Subt
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Testbench_FPU_mult();
parameter PERIOD = 10;
`ifdef SINGLE
parameter W = 32;
parameter EW = 8;
parameter SW = 23;
parameter SWR = 26;
parameter EWR = 5;//
`endif
`ifdef DOUBLE
parameter W = 64;
parameter EW = 11;
parameter SW = 52;
parameter SWR = 55;
parameter EWR = 6;
`endif
reg clk;
//INPUT signals
reg rst;
reg beg_FSM;
reg ack_FSM;
//Oper_Start_in signals
reg [W-1:0] Data_X;
reg [W-1:0] Data_Y;
//reg add_subt;
//Round signals signals
reg [1:0] r_mode;
//OUTPUT SIGNALS
wire overflow_flag;
wire underflow_flag;
wire ready;
wire [W-1:0] final_result_ieee;
FPU_Multiplication_Function #(
.W(W),
.EW(EW),
.SW(SW)
) inst_FPU_Multiplication_Function (
.clk (clk),
.rst (rst),
.beg_FSM (beg_FSM),
.ack_FSM (ack_FSM),
.Data_MX (Data_X),
.Data_MY (Data_Y),
.round_mode (r_mode),
.overflow_flag (overflow_flag),
.underflow_flag (underflow_flag),
.ready (ready),
.final_result_ieee (final_result_ieee)
);
reg [W-1:0] Array_IN_1 [0:((2**PERIOD)-1)];
reg [W-1:0] Array_IN_2 [0:((2**PERIOD)-1)];
integer contador;
integer FileSaveData;
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
beg_FSM = 0;
ack_FSM = 0;
Data_X = 0;
Data_Y = 0;
r_mode = 2'b00;
//Abre el archivo testbench
// FileSaveData = $fopen("vector/add_single/ResultadoXilinxFLM.txt","w");
// $readmemh("vector/add_single/Hexadecimal_A.txt", Array_IN_1);
// $readmemh("vector/add_single/Hexadecimal_B.txt", Array_IN_2);
add_subt = 0;
FileSaveData = $fopen("ResultadoXilinxFLM_MULT.txt","w");
$readmemh("Hexadecimal_A.txt", Array_IN_1);
$readmemh("Hexadecimal_B.txt", Array_IN_2);
run_Arch2(FileSaveData,2**PERIOD);
#100 rst = 0;
$finish;
//Add stimulus here
end
//******************************* Se ejecuta el CLK ************************
initial forever #5 clk = ~clk;
task run_Arch2;
input integer FDataO;
input integer Vector_size;
begin
rst = 0;
#15 rst = 1;
#15 rst = 0;
beg_FSM = 0;
ack_FSM = 0;
contador = 0;
repeat(Vector_size) @(negedge clk) begin
//input the new values inside the operator
Data_X = Array_IN_1[contador];
Data_Y = Array_IN_2[contador];
#(PERIOD/4) beg_FSM = 1;
//Wait for the operation ready
@(posedge ready) begin
#(PERIOD+2);
ack_FSM = 1;
#4;
$fwrite(FDataO,"%h\n",final_result_ieee);
end
@(negedge clk) begin
ack_FSM = 0;
end
contador = contador + 1;
end
$fclose(FDataO);
end
endtask
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: fpu_div_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline synthesizable logic
// - special input cases
// - opcode pipeline
// - sign logic
// - exception logic
// - datapath control- select lines and control logic
//
///////////////////////////////////////////////////////////////////////////////
module fpu_div_ctl (
inq_in1_51,
inq_in1_54,
inq_in1_53_0_neq_0,
inq_in1_50_0_neq_0,
inq_in1_53_32_neq_0,
inq_in1_exp_eq_0,
inq_in1_exp_neq_ffs,
inq_in2_51,
inq_in2_54,
inq_in2_53_0_neq_0,
inq_in2_50_0_neq_0,
inq_in2_53_32_neq_0,
inq_in2_exp_eq_0,
inq_in2_exp_neq_ffs,
inq_op,
div_exp1,
div_dest_rdy,
inq_rnd_mode,
inq_id,
inq_in1_63,
inq_in2_63,
inq_div,
div_exp_out,
div_frac_add_52_inva,
div_frac_add_in1_neq_0,
div_frac_out_54,
d6stg_frac_0,
d6stg_frac_1,
d6stg_frac_2,
d6stg_frac_29,
d6stg_frac_30,
d6stg_frac_31,
div_frac_out_53,
div_expadd2_12,
arst_l,
grst_l,
rclk,
div_pipe_active,
d1stg_snan_sng_in1,
d1stg_snan_dbl_in1,
d1stg_snan_sng_in2,
d1stg_snan_dbl_in2,
d1stg_step,
d1stg_dblop,
d234stg_fdiv,
d3stg_fdiv,
d4stg_fdiv,
d5stg_fdiva,
d5stg_fdivb,
d5stg_fdivs,
d5stg_fdivd,
d6stg_fdiv,
d6stg_fdivs,
d6stg_fdivd,
d7stg_fdiv,
d7stg_fdivd,
d8stg_fdiv_in,
d8stg_fdivs,
d8stg_fdivd,
div_id_out_in,
div_sign_out,
div_exc_out,
div_norm_frac_in1_dbl_norm,
div_norm_frac_in1_dbl_dnrm,
div_norm_frac_in1_sng_norm,
div_norm_frac_in1_sng_dnrm,
div_norm_frac_in2_dbl_norm,
div_norm_frac_in2_dbl_dnrm,
div_norm_frac_in2_sng_norm,
div_norm_frac_in2_sng_dnrm,
div_norm_inf,
div_norm_qnan,
div_norm_zero,
div_frac_add_in2_load,
d6stg_frac_out_shl1,
d6stg_frac_out_nosh,
div_frac_add_in1_add,
div_frac_add_in1_load,
d7stg_rndup_inv,
d7stg_to_0,
d7stg_to_0_inv,
div_frac_out_add_in1,
div_frac_out_add,
div_frac_out_shl1_dbl,
div_frac_out_shl1_sng,
div_frac_out_of,
div_frac_out_load,
div_expadd1_in1_dbl,
div_expadd1_in1_sng,
div_expadd1_in2_exp_in2_dbl,
div_expadd1_in2_exp_in2_sng,
div_exp1_expadd1,
div_exp1_0835,
div_exp1_0118,
div_exp1_zero,
div_exp1_load,
div_expadd2_in1_exp_out,
div_expadd2_no_decr_inv,
div_expadd2_cin,
div_exp_out_expadd22_inv,
div_exp_out_expadd2,
div_exp_out_of,
div_exp_out_exp_out,
div_exp_out_load,
se,
si,
so
);
parameter
FDIVS= 8'h4d,
FDIVD= 8'h4e;
input inq_in1_51; // request operand 1[51]
input inq_in1_54; // request operand 1[54]
input inq_in1_53_0_neq_0; // request operand 1[53:0]!=0
input inq_in1_50_0_neq_0; // request operand 1[50:0]!=0
input inq_in1_53_32_neq_0; // request operand 1[53:32]!=0
input inq_in1_exp_eq_0; // request operand 1[62:52]==0
input inq_in1_exp_neq_ffs; // request operand 1[62:52]!=0x7ff
input inq_in2_51; // request operand 2[51]
input inq_in2_54; // request operand 2[54]
input inq_in2_53_0_neq_0; // request operand 2[53:0]!=0
input inq_in2_50_0_neq_0; // request operand 2[50:0]!=0
input inq_in2_53_32_neq_0; // request operand 2[53:32]!=0
input inq_in2_exp_eq_0; // request operand 2[62:52]==0
input inq_in2_exp_neq_ffs; // request operand 2[62:52]!=0x7ff
input [7:0] inq_op; // request opcode to op pipes
input [12:0] div_exp1; // divide exponent- intermediate value
input div_dest_rdy; // divide result req accepted for CPX
input [1:0] inq_rnd_mode; // request rounding mode to op pipes
input [4:0] inq_id; // request ID to the operation pipes
input inq_in1_63; // request operand 1 to op pipes- sign
input inq_in2_63; // request operand 2 to op pipes- sign
input inq_div; // divide pipe request
input [12:0] div_exp_out; // divide exponent output
input div_frac_add_52_inva; // div_frac_add bit[52] inverted
input div_frac_add_in1_neq_0; // div_frac_add_in1 != 0
input div_frac_out_54; // div_frac_out bit[54]
input d6stg_frac_0; // divide fraction[0]- intermediate val
input d6stg_frac_1; // divide fraction[1]- intermediate val
input d6stg_frac_2; // divide fraction[2]- intermediate val
input d6stg_frac_29; // divide fraction[29]- intermediate val
input d6stg_frac_30; // divide fraction[30]- intermediate val
input d6stg_frac_31; // divide fraction[31]- intermediate val
input div_frac_out_53; // div_frac_out bit[53]
input div_expadd2_12; // div_expadd2 bit[12]
input arst_l; // global async. reset- asserted low
input grst_l; // global sync. reset- asserted low
input rclk; // global clock
output div_pipe_active; // div pipe is executing a valid instr
output d1stg_snan_sng_in1; // operand 1 is single signalling NaN
output d1stg_snan_dbl_in1; // operand 1 is double signalling NaN
output d1stg_snan_sng_in2; // operand 2 is single signalling NaN
output d1stg_snan_dbl_in2; // operand 2 is double signalling NaN
output d1stg_step; // divide pipe load
output d1stg_dblop; // double precision operation- d1 stg
output d234stg_fdiv; // select line to div_expadd1
output d3stg_fdiv; // divide operation- divide stage 3
output d4stg_fdiv; // divide operation- divide stage 4
output d5stg_fdiva; // divide operation- divide stage 5
output d5stg_fdivb; // divide operation- divide stage 5
output d5stg_fdivs; // divide single- divide stage 5
output d5stg_fdivd; // divide double- divide stage 5
output d6stg_fdiv; // divide operation- divide stage 6
output d6stg_fdivs; // divide single- divide stage 6
output d6stg_fdivd; // divide double- divide stage 6
output d7stg_fdiv; // divide operation- divide stage 7
output d7stg_fdivd; // divide double- divide stage 7
output d8stg_fdiv_in; // div pipe output request next cycle
output d8stg_fdivs; // divide single- divide stage 8
output d8stg_fdivd; // divide double- divide stage 8
output [9:0] div_id_out_in; // div pipe output ID next cycle
output div_sign_out; // divide sign output
output [4:0] div_exc_out; // divide pipe result- exception flags
output div_norm_frac_in1_dbl_norm; // select line to div_norm
output div_norm_frac_in1_dbl_dnrm; // select line to div_norm
output div_norm_frac_in1_sng_norm; // select line to div_norm
output div_norm_frac_in1_sng_dnrm; // select line to div_norm
output div_norm_frac_in2_dbl_norm; // select line to div_norm
output div_norm_frac_in2_dbl_dnrm; // select line to div_norm
output div_norm_frac_in2_sng_norm; // select line to div_norm
output div_norm_frac_in2_sng_dnrm; // select line to div_norm
output div_norm_inf; // select line to div_norm
output div_norm_qnan; // select line to div_norm
output div_norm_zero; // select line to div_norm
output div_frac_add_in2_load; // load enable to div_frac_add_in2
output d6stg_frac_out_shl1; // select line to d6stg_frac
output d6stg_frac_out_nosh; // select line to d6stg_frac
output div_frac_add_in1_add; // select line to div_frac_add_in1
output div_frac_add_in1_load; // load enable to div_frac_add_in1
output d7stg_rndup_inv; // no rounding increment
output d7stg_to_0; // result to max finite on overflow
output d7stg_to_0_inv; // result to infinity on overflow
output div_frac_out_add_in1; // select line to div_frac_out
output div_frac_out_add; // select line to div_frac_out
output div_frac_out_shl1_dbl; // select line to div_frac_out
output div_frac_out_shl1_sng; // select line to div_frac_out
output div_frac_out_of; // select line to div_frac_out
output div_frac_out_load; // load enable to div_frac_out
output div_expadd1_in1_dbl; // select line to div_expadd1
output div_expadd1_in1_sng; // select line to div_expadd1
output div_expadd1_in2_exp_in2_dbl; // select line to div_expadd1
output div_expadd1_in2_exp_in2_sng; //select line to div_expadd1
output div_exp1_expadd1; // select line to div_exp1
output div_exp1_0835; // select line to div_exp1
output div_exp1_0118; // select line to div_exp1
output div_exp1_zero; // select line to div_exp1
output div_exp1_load; // load enable to div_exp1
output div_expadd2_in1_exp_out; // select line to div_expadd2
output div_expadd2_no_decr_inv; // no exponent decrement
output div_expadd2_cin; // carry in to 2nd exponent adder
output div_exp_out_expadd22_inv; // select line to div_exp_out
output div_exp_out_expadd2; // select line to div_exp_out
output div_exp_out_of; // overflow to exponent output
output div_exp_out_exp_out; // select line to div_exp_out
output div_exp_out_load; // load enable to div_exp_out
input se; // scan_enable
input si; // scan in
output so; // scan out
wire reset;
wire div_frac_in1_51;
wire div_frac_in1_54;
wire div_frac_in1_53_0_neq_0;
wire div_frac_in1_50_0_neq_0;
wire div_frac_in1_53_32_neq_0;
wire div_exp_in1_exp_eq_0;
wire div_exp_in1_exp_neq_ffs;
wire div_frac_in2_51;
wire div_frac_in2_54;
wire div_frac_in2_53_0_neq_0;
wire div_frac_in2_50_0_neq_0;
wire div_frac_in2_53_32_neq_0;
wire div_exp_in2_exp_eq_0;
wire div_exp_in2_exp_neq_ffs;
wire d1stg_denorm_sng_in1;
wire d1stg_denorm_dbl_in1;
wire d1stg_denorm_sng_in2;
wire d1stg_denorm_dbl_in2;
wire d2stg_denorm_sng_in2;
wire d2stg_denorm_dbl_in2;
wire d1stg_norm_sng_in1;
wire d1stg_norm_dbl_in1;
wire d1stg_norm_sng_in2;
wire d1stg_norm_dbl_in2;
wire d2stg_norm_sng_in2;
wire d2stg_norm_dbl_in2;
wire d1stg_snan_sng_in1;
wire d1stg_snan_dbl_in1;
wire d1stg_snan_sng_in2;
wire d1stg_snan_dbl_in2;
wire d1stg_qnan_sng_in1;
wire d1stg_qnan_dbl_in1;
wire d1stg_qnan_sng_in2;
wire d1stg_qnan_dbl_in2;
wire d1stg_snan_in1;
wire d1stg_snan_in2;
wire d1stg_qnan_in1;
wire d1stg_qnan_in2;
wire d1stg_nan_sng_in1;
wire d1stg_nan_dbl_in1;
wire d1stg_nan_sng_in2;
wire d1stg_nan_dbl_in2;
wire d1stg_nan_in1;
wire d1stg_nan_in2;
wire d1stg_nan_in;
wire d2stg_snan_in1;
wire d2stg_snan_in2;
wire d2stg_qnan_in1;
wire d2stg_qnan_in2;
wire d2stg_nan_in2;
wire d2stg_nan_in;
wire d1stg_inf_sng_in1;
wire d1stg_inf_dbl_in1;
wire d1stg_inf_sng_in2;
wire d1stg_inf_dbl_in2;
wire d1stg_inf_in1;
wire d1stg_inf_in2;
wire d1stg_inf_in;
wire d1stg_2inf_in;
wire d2stg_inf_in1;
wire d2stg_inf_in2;
wire d2stg_2inf_in;
wire d1stg_infnan_sng_in1;
wire d1stg_infnan_dbl_in1;
wire d1stg_infnan_sng_in2;
wire d1stg_infnan_dbl_in2;
wire d1stg_infnan_in1;
wire d1stg_infnan_in2;
wire d1stg_infnan_in;
wire d2stg_infnan_in1;
wire d2stg_infnan_in2;
wire d2stg_infnan_in;
wire d1stg_zero_in1;
wire d1stg_zero_in2;
wire d1stg_zero_in;
wire d1stg_2zero_in;
wire d2stg_zero_in1;
wire d2stg_zero_in2;
wire d2stg_zero_in;
wire d2stg_2zero_in;
wire d1stg_hold;
wire d1stg_holda;
wire d1stg_step;
wire d1stg_stepa;
wire [7:0] d1stg_op_in;
wire [7:0] d1stg_op;
wire d1stg_div_in;
wire d1stg_div;
wire [4:0] d1stg_sngopa;
wire d1stg_dblop;
wire [4:0] d1stg_dblopa;
wire d1stg_fdiv;
wire d1stg_fdivs;
wire d1stg_fdivd;
wire [2:0] d1stg_opdec;
wire d234stg_fdiv_in;
wire [2:0] d2stg_opdec;
wire d234stg_fdiv;
wire d2stg_fdiv;
wire d2stg_fdivs;
wire d2stg_fdivd;
wire [2:0] d3stg_opdec;
wire d3stg_fdiv;
wire [2:0] d4stg_opdec;
wire d4stg_fdiv;
wire d4stg_fdivs;
wire d4stg_fdivd;
wire d5stg_step;
wire [2:0] d5stg_opdec;
wire d5stg_fdiva;
wire d5stg_fdivb_in;
wire d5stg_fdivb;
wire d5stg_fdiv;
wire d5stg_fdivs;
wire d5stg_fdivd;
wire d6stg_step;
wire [2:0] d6stg_opdec_in;
wire [2:0] d6stg_opdec;
wire d6stg_fdiv;
wire d6stg_fdivs;
wire d6stg_fdivd;
wire [2:0] d7stg_opdec;
wire d7stg_fdiv;
wire d7stg_fdivs;
wire d7stg_fdivd;
wire d8stg_fdiv_in;
wire [2:0] d8stg_opdec;
wire d8stg_fdiv;
wire d8stg_fdivs;
wire d8stg_fdivd;
wire d8stg_hold;
wire d8stg_step;
wire [1:0] d1stg_rnd_mode;
wire [4:0] d1stg_id;
wire d1stg_sign1;
wire d1stg_sign2;
wire d1stg_sign;
wire div_bkend_step;
wire [1:0] div_rnd_mode;
wire [9:0] div_id_out_in;
wire [9:0] div_id_out;
wire div_sign_out;
wire [5:0] div_cnt_plus1;
wire [5:0] div_cnt_in;
wire div_cnt_step;
wire [5:0] div_cnt;
wire div_cnt_lt_step;
wire divs_cnt_lt_23_in;
wire divs_cnt_lt_23;
wire divs_cnt_lt_23a;
wire divd_cnt_lt_52_in;
wire divd_cnt_lt_52;
wire divd_cnt_lt_52a;
wire div_exc_step;
wire div_of_mask_in;
wire div_of_mask;
wire div_nv_out_in;
wire div_nv_out;
wire div_dz_out_in;
wire div_dz_out;
wire d7stg_in_of;
wire div_of_out_tmp1_in;
wire div_of_out_tmp1;
wire div_of_out_tmp2;
wire div_out_52_inv;
wire div_of_out;
wire div_uf_out_in;
wire div_uf_out;
wire div_nx_out_in;
wire div_nx_out;
wire [4:0] div_exc_out;
wire d1stg_spc_rslt;
wire div_norm_frac_in1_dbl_norm;
wire div_norm_frac_in1_dbl_dnrm;
wire div_norm_frac_in1_sng_norm;
wire div_norm_frac_in1_sng_dnrm;
wire div_norm_frac_in2_dbl_norm;
wire div_norm_frac_in2_dbl_dnrm;
wire div_norm_frac_in2_sng_norm;
wire div_norm_frac_in2_sng_dnrm;
wire div_norm_inf;
wire div_norm_qnan;
wire div_norm_zero;
wire div_frac_add_in2_load;
wire d6stg_frac_out_shl1;
wire d6stg_frac_out_nosh;
wire div_frac_add_in1_add;
wire div_frac_add_in1_load;
wire d7stg_lsb_in;
wire d7stg_grd_in;
wire d7stg_stk_in;
wire d7stg_lsb;
wire d7stg_grd;
wire d7stg_stk;
wire d7stg_rndup;
wire d7stg_rndup_inv;
wire d7stg_to_0;
wire d7stg_to_0_inv;
wire div_frac_out_add_in1;
wire div_frac_out_add;
wire div_frac_out_shl1_dbl;
wire div_frac_out_shl1_sng;
wire div_frac_out_of;
wire div_frac_out_load;
wire div_expadd1_in1_dbl_in;
wire div_expadd1_in1_dbl;
wire div_expadd1_in1_sng_in;
wire div_expadd1_in1_sng;
wire div_expadd1_in2_exp_in2_dbl;
wire div_expadd1_in2_exp_in2_sng;
wire div_exp1_expadd1;
wire div_exp1_0835;
wire div_exp1_0118;
wire div_exp1_zero;
wire d2stg_max_exp;
wire d2stg_zero_exp;
wire div_exp1_load;
wire div_expadd2_in1_exp_out_in;
wire div_expadd2_in1_exp_out;
wire div_expadd2_no_decr_inv_in;
wire div_expadd2_no_decr_load;
wire div_expadd2_no_decr_inv;
wire div_expadd2_cin;
wire div_exp_out_zero;
wire div_exp_out_expadd22_inv;
wire div_exp_out_expadd2;
wire div_exp_out_of;
wire div_exp_out_exp_out;
wire div_exp_out_load;
wire div_pipe_active_in;
wire div_pipe_active;
dffrl_async #(1) dffrl_div_ctl (
.din (grst_l),
.clk (rclk),
.rst_l(arst_l),
.q (div_ctl_rst_l),
.se (se),
.si (),
.so ()
);
assign reset= (!div_ctl_rst_l);
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline special input cases.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(1) i_div_frac_in1_51 (
.din (inq_in1_51),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_54 (
.din (inq_in1_54),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_53_0_neq_0 (
.din (inq_in1_53_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_50_0_neq_0 (
.din (inq_in1_50_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in1_53_32_neq_0 (
.din (inq_in1_53_32_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in1_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in1_exp_eq_0 (
.din (inq_in1_exp_eq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in1_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in1_exp_neq_ffs (
.din (inq_in1_exp_neq_ffs),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in1_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_51 (
.din (inq_in2_51),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_51),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_54 (
.din (inq_in2_54),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_54),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_53_0_neq_0 (
.din (inq_in2_53_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_53_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_50_0_neq_0 (
.din (inq_in2_50_0_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_50_0_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_frac_in2_53_32_neq_0 (
.din (inq_in2_53_32_neq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_frac_in2_53_32_neq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in2_exp_eq_0 (
.din (inq_in2_exp_eq_0),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in2_exp_eq_0),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_exp_in2_exp_neq_ffs (
.din (inq_in2_exp_neq_ffs),
.en (d1stg_step),
.clk (rclk),
.q (div_exp_in2_exp_neq_ffs),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Denorm divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_denorm_sng_in1= div_exp_in1_exp_eq_0 && d1stg_sngopa[0];
assign d1stg_denorm_dbl_in1= div_exp_in1_exp_eq_0 && d1stg_dblopa[0];
assign d1stg_denorm_sng_in2= div_exp_in2_exp_eq_0 && d1stg_sngopa[0];
assign d1stg_denorm_dbl_in2= div_exp_in2_exp_eq_0 && d1stg_dblopa[0];
dff #(1) i_d2stg_denorm_sng_in2 (
.din (d1stg_denorm_sng_in2),
.clk (rclk),
.q (d2stg_denorm_sng_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_denorm_dbl_in2 (
.din (d1stg_denorm_dbl_in2),
.clk (rclk),
.q (d2stg_denorm_dbl_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Non-denorm divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_norm_sng_in1= (!div_exp_in1_exp_eq_0) && d1stg_sngopa[0];
assign d1stg_norm_dbl_in1= (!div_exp_in1_exp_eq_0) && d1stg_dblopa[0];
assign d1stg_norm_sng_in2= (!div_exp_in2_exp_eq_0) && d1stg_sngopa[0];
assign d1stg_norm_dbl_in2= (!div_exp_in2_exp_eq_0) && d1stg_dblopa[0];
dff #(1) i_d2stg_norm_sng_in2 (
.din (d1stg_norm_sng_in2),
.clk (rclk),
.q (d2stg_norm_sng_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_norm_dbl_in2 (
.din (d1stg_norm_dbl_in2),
.clk (rclk),
.q (d2stg_norm_dbl_in2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Nan divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_snan_sng_in1= (!div_exp_in1_exp_neq_ffs) && (!div_frac_in1_54)
&& div_frac_in1_53_32_neq_0 && d1stg_sngopa[1];
assign d1stg_snan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && (!div_frac_in1_51)
&& div_frac_in1_50_0_neq_0 && d1stg_dblopa[1];
assign d1stg_snan_sng_in2= (!div_exp_in2_exp_neq_ffs) && (!div_frac_in2_54)
&& div_frac_in2_53_32_neq_0 && d1stg_sngopa[1];
assign d1stg_snan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && (!div_frac_in2_51)
&& div_frac_in2_50_0_neq_0 && d1stg_dblopa[1];
assign d1stg_qnan_sng_in1= (!div_exp_in1_exp_neq_ffs) && div_frac_in1_54
&& d1stg_sngopa[1];
assign d1stg_qnan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && div_frac_in1_51
&& d1stg_dblopa[1];
assign d1stg_qnan_sng_in2= (!div_exp_in2_exp_neq_ffs) && div_frac_in2_54
&& d1stg_sngopa[1];
assign d1stg_qnan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && div_frac_in2_51
&& d1stg_dblopa[1];
assign d1stg_snan_in1= d1stg_snan_sng_in1 || d1stg_snan_dbl_in1;
assign d1stg_snan_in2= d1stg_snan_sng_in2 || d1stg_snan_dbl_in2;
assign d1stg_qnan_in1= d1stg_qnan_sng_in1 || d1stg_qnan_dbl_in1;
assign d1stg_qnan_in2= d1stg_qnan_sng_in2 || d1stg_qnan_dbl_in2;
assign d1stg_nan_sng_in1= (!div_exp_in1_exp_neq_ffs)
&& (div_frac_in1_54 || div_frac_in1_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_nan_dbl_in1= (!div_exp_in1_exp_neq_ffs)
&& (div_frac_in1_51 || div_frac_in1_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_nan_sng_in2= (!div_exp_in2_exp_neq_ffs)
&& (div_frac_in2_54 || div_frac_in2_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_nan_dbl_in2= (!div_exp_in2_exp_neq_ffs)
&& (div_frac_in2_51 || div_frac_in2_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_nan_in1= d1stg_nan_sng_in1 || d1stg_nan_dbl_in1;
assign d1stg_nan_in2= d1stg_nan_sng_in2 || d1stg_nan_dbl_in2;
assign d1stg_nan_in= d1stg_nan_in1 || d1stg_nan_in2;
dff #(1) i_d2stg_snan_in1 (
.din (d1stg_snan_in1),
.clk (rclk),
.q (d2stg_snan_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_snan_in2 (
.din (d1stg_snan_in2),
.clk (rclk),
.q (d2stg_snan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_qnan_in1 (
.din (d1stg_qnan_in1),
.clk (rclk),
.q (d2stg_qnan_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_qnan_in2 (
.din (d1stg_qnan_in2),
.clk (rclk),
.q (d2stg_qnan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_nan_in2 (
.din (d1stg_nan_in2),
.clk (rclk),
.q (d2stg_nan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_nan_in (
.din (d1stg_nan_in),
.clk (rclk),
.q (d2stg_nan_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_inf_sng_in1= (!div_exp_in1_exp_neq_ffs)
&& (!div_frac_in1_54) && (!div_frac_in1_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_inf_dbl_in1= (!div_exp_in1_exp_neq_ffs)
&& (!div_frac_in1_51) && (!div_frac_in1_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_inf_sng_in2= (!div_exp_in2_exp_neq_ffs)
&& (!div_frac_in2_54) && (!div_frac_in2_53_32_neq_0)
&& d1stg_sngopa[2];
assign d1stg_inf_dbl_in2= (!div_exp_in2_exp_neq_ffs)
&& (!div_frac_in2_51) && (!div_frac_in2_50_0_neq_0)
&& d1stg_dblopa[2];
assign d1stg_inf_in1= d1stg_inf_sng_in1 || d1stg_inf_dbl_in1;
assign d1stg_inf_in2= d1stg_inf_sng_in2 || d1stg_inf_dbl_in2;
assign d1stg_inf_in= d1stg_inf_in1 || d1stg_inf_in2;
assign d1stg_2inf_in= d1stg_inf_in1 && d1stg_inf_in2;
dff #(1) i_d2stg_inf_in1 (
.din (d1stg_inf_in1),
.clk (rclk),
.q (d2stg_inf_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_inf_in2 (
.din (d1stg_inf_in2),
.clk (rclk),
.q (d2stg_inf_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_2inf_in (
.din (d1stg_2inf_in),
.clk (rclk),
.q (d2stg_2inf_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Infinity/Nan divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_infnan_sng_in1= (!div_exp_in1_exp_neq_ffs) && d1stg_sngopa[3];
assign d1stg_infnan_dbl_in1= (!div_exp_in1_exp_neq_ffs) && d1stg_dblopa[3];
assign d1stg_infnan_sng_in2= (!div_exp_in2_exp_neq_ffs) && d1stg_sngopa[3];
assign d1stg_infnan_dbl_in2= (!div_exp_in2_exp_neq_ffs) && d1stg_dblopa[3];
assign d1stg_infnan_in1= d1stg_infnan_sng_in1 || d1stg_infnan_dbl_in1;
assign d1stg_infnan_in2= d1stg_infnan_sng_in2 || d1stg_infnan_dbl_in2;
assign d1stg_infnan_in= d1stg_infnan_in1 || d1stg_infnan_in2;
dff #(1) i_d2stg_infnan_in1 (
.din (d1stg_infnan_in1),
.clk (rclk),
.q (d2stg_infnan_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_infnan_in2 (
.din (d1stg_infnan_in2),
.clk (rclk),
.q (d2stg_infnan_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_infnan_in (
.din (d1stg_infnan_in),
.clk (rclk),
.q (d2stg_infnan_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Zero divide inputs.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_zero_in1= div_exp_in1_exp_eq_0
&& (!div_frac_in1_53_0_neq_0) && (!div_frac_in1_54);
assign d1stg_zero_in2= div_exp_in2_exp_eq_0
&& (!div_frac_in2_53_0_neq_0) && (!div_frac_in2_54);
assign d1stg_zero_in= d1stg_zero_in1 || d1stg_zero_in2;
assign d1stg_2zero_in= d1stg_zero_in1 && d1stg_zero_in2;
dff #(1) i_d2stg_zero_in1 (
.din (d1stg_zero_in1),
.clk (rclk),
.q (d2stg_zero_in1),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_zero_in2 (
.din (d1stg_zero_in2),
.clk (rclk),
.q (d2stg_zero_in2),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_zero_in (
.din (d1stg_zero_in),
.clk (rclk),
.q (d2stg_zero_in),
.se (se),
.si (),
.so ()
);
dff #(1) i_d2stg_2zero_in (
.din (d1stg_2zero_in),
.clk (rclk),
.q (d2stg_2zero_in),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Floating point divide control pipeline.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide pipeline input.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_hold= d1stg_div
|| d234stg_fdiv
|| divs_cnt_lt_23
|| divd_cnt_lt_52;
assign d1stg_holda= d1stg_div
|| d234stg_fdiv
|| divs_cnt_lt_23a
|| divd_cnt_lt_52a;
assign d1stg_step= (!d1stg_hold);
assign d1stg_stepa= (!d1stg_holda);
assign d1stg_op_in[7:0]= ({8{d1stg_stepa}}
& (inq_op[7:0] & {8{inq_div}}));
dffr #(8) i_d1stg_op (
.din (d1stg_op_in[7:0]),
.rst (reset),
.clk (rclk),
.q (d1stg_op[7:0]),
.se (se),
.si (),
.so ()
);
assign d1stg_div_in= inq_div && d1stg_stepa;
dffr #(1) i_d1stg_div (
.din (d1stg_div_in),
.rst (reset),
.clk (rclk),
.q (d1stg_div),
.se (se),
.si (),
.so ()
);
dffe #(5) i_d1stg_sngopa (
.din ({5{inq_op[0]}}),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_sngopa[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d1stg_dblop (
.din (inq_op[1]),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_dblop),
.se (se),
.si (),
.so ()
);
dffe #(5) i_d1stg_dblopa (
.din ({5{inq_op[1]}}),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_dblopa[4:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode decode- divide stage 1.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_fdiv= (d1stg_op[7:0]==FDIVS) || (d1stg_op[7:0]==FDIVD);
assign d1stg_fdivs= (d1stg_op[7:0]==FDIVS);
assign d1stg_fdivd= (d1stg_op[7:0]==FDIVD);
assign d1stg_opdec[2:0]= {d1stg_fdiv,
d1stg_fdivs,
d1stg_fdivd};
assign d234stg_fdiv_in= d1stg_fdiv || d2stg_fdiv || d3stg_fdiv;
dffr #(3) i_d2stg_opdec (
.din (d1stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d2stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
dffr #(1) i_d234stg_fdiv (
.din (d234stg_fdiv_in),
.rst (reset),
.clk (rclk),
.q (d234stg_fdiv),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 2.
//
///////////////////////////////////////////////////////////////////////////////
assign d2stg_fdiv= d2stg_opdec[2];
assign d2stg_fdivs= d2stg_opdec[1];
assign d2stg_fdivd= d2stg_opdec[0];
dffr #(3) i_d3stg_opdec (
.din (d2stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d3stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 3.
//
///////////////////////////////////////////////////////////////////////////////
assign d3stg_fdiv= d3stg_opdec[2];
//assign d3stg_fdivs= d3stg_opdec[1];
//assign d3stg_fdivd= d3stg_opdec[0];
dffr #(3) i_d4stg_opdec (
.din (d3stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d4stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 4.
//
///////////////////////////////////////////////////////////////////////////////
assign d4stg_fdiv= d4stg_opdec[2];
assign d4stg_fdivs= d4stg_opdec[1];
assign d4stg_fdivd= d4stg_opdec[0];
assign d5stg_step= (!d5stg_fdiv) || d6stg_step;
dffre #(3) i_d5stg_opdec (
.din (d4stg_opdec[2:0]),
.en (d5stg_step),
.rst (reset),
.clk (rclk),
.q (d5stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
dffre #(1) i_d5stg_fdiva (
.din (d4stg_fdiv),
.en (d5stg_step),
.rst (reset),
.clk (rclk),
.q (d5stg_fdiva),
.se (se),
.si (),
.so ()
);
assign d5stg_fdivb_in= ((d5stg_step && d4stg_fdiv)
|| ((!d5stg_step) && d5stg_fdiv))
&& (!reset);
dff #(1) i_d5stg_fdivb (
.din (d5stg_fdivb_in),
.clk (rclk),
.q (d5stg_fdivb),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 5.
//
///////////////////////////////////////////////////////////////////////////////
assign d5stg_fdiv= d5stg_opdec[2];
assign d5stg_fdivs= d5stg_opdec[1];
assign d5stg_fdivd= d5stg_opdec[0];
assign d6stg_step= (d5stg_fdivd && (div_cnt[5:0]==6'h36))
|| (d5stg_fdivs && (div_cnt[5:0]==6'h19))
|| (d5stg_fdiv && ((({7'b0, div_cnt[5:0]}==div_exp1[12:0])
&& (div_exp1[12:0]!=13'b0))
|| (({7'b0, div_cnt[5:0]}==div_exp1[12:0])
&& (div_exp1[12:0]==13'b0)
&& d8stg_step)
|| (div_exp1[12] && d8stg_step)));
assign d6stg_opdec_in[2:0]= ({3{d6stg_step}}
& d5stg_opdec[2:0]);
dffr #(3) i_d6stg_opdec (
.din (d6stg_opdec_in[2:0]),
.rst (reset),
.clk (rclk),
.q (d6stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 6.
//
///////////////////////////////////////////////////////////////////////////////
assign d6stg_fdiv= d6stg_opdec[2];
assign d6stg_fdivs= d6stg_opdec[1];
assign d6stg_fdivd= d6stg_opdec[0];
dffr #(3) i_d7stg_opdec (
.din (d6stg_opdec[2:0]),
.rst (reset),
.clk (rclk),
.q (d7stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide stage 7.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_fdiv= d7stg_opdec[2];
assign d7stg_fdivs= d7stg_opdec[1];
assign d7stg_fdivd= d7stg_opdec[0];
assign d8stg_fdiv_in= (d8stg_step && (!reset) && d7stg_fdiv)
|| ((!d8stg_step) && (!reset) && d8stg_fdiv);
dffre #(3) i_d8stg_opdec (
.din (d7stg_opdec[2:0]),
.en (d8stg_step),
.rst (reset),
.clk (rclk),
.q (d8stg_opdec[2:0]),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Opcode pipeline- divide pipeline output.
//
///////////////////////////////////////////////////////////////////////////////
assign d8stg_fdiv= d8stg_opdec[2];
assign d8stg_fdivs= d8stg_opdec[1];
assign d8stg_fdivd= d8stg_opdec[0];
assign d8stg_hold= d8stg_fdiv && (!div_dest_rdy);
assign d8stg_step= (!d8stg_hold);
// Austin update
// Power management update
assign div_pipe_active_in = // div pipe is executing a valid instr
d1stg_fdiv || d2stg_fdiv || d3stg_fdiv || d4stg_fdiv |
d5stg_fdiv || d6stg_fdiv || d7stg_fdiv || d8stg_fdiv ;
dffre #(1) i_div_pipe_active (
.din (div_pipe_active_in),
.en (1'b1),
.rst (reset),
.clk (rclk),
.q (div_pipe_active),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide information pipeline
// - rounding mode
// - ID
// - sign logic
// Front end of the pipeline.
//
///////////////////////////////////////////////////////////////////////////////
dffe #(2) i_d1stg_rnd_mode (
.din (inq_rnd_mode[1:0]),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
dffe #(5) i_d1stg_id (
.din (inq_id[4:0]),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_id[4:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d1stg_sign1 (
.din (inq_in1_63),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_sign1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d1stg_sign2 (
.din (inq_in2_63),
.en (d1stg_stepa),
.clk (rclk),
.q (d1stg_sign2),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide information pipeline
// - rounding mode
// - ID
// - sign logic
// Back end of the pipeline.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_sign= ((d1stg_sign1
&& (!d2stg_snan_in2)
&& (!(d2stg_qnan_in2 && (!d2stg_snan_in1))))
^ (d1stg_sign2
&& (!(d2stg_snan_in1 && (!d2stg_snan_in2)))
&& (!(d2stg_qnan_in1 && (!d2stg_nan_in2)))))
&& (!(d2stg_2inf_in || d2stg_2zero_in));
assign div_bkend_step= (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step);
dffe #(2) i_div_rnd_mode (
.din (d1stg_rnd_mode[1:0]),
.en (div_bkend_step),
.clk (rclk),
.q (div_rnd_mode[1:0]),
.se (se),
.si (),
.so ()
);
assign div_id_out_in[9:0]= ({10{div_bkend_step}}
& {(d1stg_id[4:2]==3'o7),
(d1stg_id[4:2]==3'o6),
(d1stg_id[4:2]==3'o5),
(d1stg_id[4:2]==3'o4),
(d1stg_id[4:2]==3'o3),
(d1stg_id[4:2]==3'o2),
(d1stg_id[4:2]==3'o1),
(d1stg_id[4:2]==3'o0),
d1stg_id[1:0]})
| ({10{(!div_bkend_step)}}
& div_id_out[9:0]);
dff #(10) i_div_id_out (
.din (div_id_out_in[9:0]),
.clk (rclk),
.q (div_id_out[9:0]),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_sign_out (
.din (d1stg_sign),
.en (div_bkend_step),
.clk (rclk),
.q (div_sign_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide counter.
//
// Tracks the number of subtraction iterations.
//
///////////////////////////////////////////////////////////////////////////////
assign div_cnt_plus1[5:0]= (div_cnt[5:0] + 6'h01);
assign div_cnt_in[5:0]= ({6{(d5stg_fdiv && d8stg_step)}}
& div_cnt_plus1[5:0])
| ({6{d4stg_fdiv}}
& 6'b0);
assign div_cnt_step= (d5stg_fdiv && d8stg_step)
|| d4stg_fdiv;
dffre #(6) i_div_cnt (
.din (div_cnt_in[5:0]),
.en (div_cnt_step),
.rst (reset),
.clk (rclk),
.q (div_cnt[5:0]),
.se (se),
.si (),
.so ()
);
assign div_cnt_lt_step= (!d5stg_fdiv) || d6stg_step || d8stg_step;
assign divs_cnt_lt_23_in= d4stg_fdivs
|| (d5stg_fdivs && (!d6stg_step) && (div_cnt_plus1[5:0]<6'h17));
dffre #(1) i_divs_cnt_lt_23 (
.din (divs_cnt_lt_23_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divs_cnt_lt_23),
.se (se),
.si (),
.so ()
);
dffre #(1) i_divs_cnt_lt_23a (
.din (divs_cnt_lt_23_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divs_cnt_lt_23a),
.se (se),
.si (),
.so ()
);
assign divd_cnt_lt_52_in= d4stg_fdivd
|| (d5stg_fdivd && (!d6stg_step) && (div_cnt_plus1[5:0]<6'h34));
dffre #(1) i_divd_cnt_lt_52 (
.din (divd_cnt_lt_52_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divd_cnt_lt_52),
.se (se),
.si (),
.so ()
);
dffre #(1) i_divd_cnt_lt_52a (
.din (divd_cnt_lt_52_in),
.en (div_cnt_lt_step),
.rst (reset),
.clk (rclk),
.q (divd_cnt_lt_52a),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exception logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Divide overflow exception enabled.
//
///////////////////////////////////////////////////////////////////////////////
assign div_exc_step= d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step;
assign div_of_mask_in= (!(d1stg_infnan_in || d1stg_zero_in));
dffe #(1) i_div_of_mask (
.din (div_of_mask_in),
.en (div_exc_step),
.clk (rclk),
.q (div_of_mask),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide invalid exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_nv_out_in= d1stg_snan_in1 || d1stg_snan_in2 || d1stg_2inf_in
|| d1stg_2zero_in;
dffe #(1) i_div_nv_out (
.din (div_nv_out_in),
.en (div_exc_step),
.clk (rclk),
.q (div_nv_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide by zero exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_dz_out_in= d1stg_zero_in2 && (!d1stg_zero_in1)
&& (!d1stg_infnan_in1);
dffe #(1) i_div_dz_out (
.din (div_dz_out_in),
.en (div_exc_step),
.clk (rclk),
.q (div_dz_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide overflow exception.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_in_of= ((!div_exp_out[12])
&& d7stg_fdivd
&& (div_exp_out[11] || (&div_exp_out[10:0]))
&& div_of_mask)
|| ((!div_exp_out[12])
&& d7stg_fdivs
&& ((|div_exp_out[11:8]) || (&div_exp_out[7:0]))
&& div_of_mask);
assign div_of_out_tmp1_in= ((!div_exp_out[12])
&& d7stg_fdivd
&& (&div_exp_out[10:1])
&& d7stg_rndup
&& div_of_mask)
|| ((!div_exp_out[12])
&& d7stg_fdivs
&& (&div_exp_out[7:1])
&& d7stg_rndup
&& div_of_mask);
dffe #(1) i_div_of_out_tmp1 (
.din (div_of_out_tmp1_in),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_of_out_tmp1),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_of_out_tmp2 (
.din (d7stg_in_of),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_of_out_tmp2),
.se (se),
.si (),
.so ()
);
dffe #(1) i_div_out_52_inv (
.din (div_frac_add_52_inva),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_out_52_inv),
// Austin update
// include se pin
.se (se),
.si (),
.so ()
);
assign div_of_out= div_of_out_tmp2
|| (div_of_out_tmp1 && (!div_out_52_inv));
///////////////////////////////////////////////////////////////////////////////
//
// Divide underflow exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_uf_out_in= ((!(|div_exp_out[11:0]))
&& (div_frac_add_in1_neq_0
|| d7stg_grd
|| d7stg_stk)
&& div_of_mask)
|| (div_exp_out[12]
&& div_of_mask);
dffe #(1) i_div_uf_out (
.din (div_uf_out_in),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_uf_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide inexact exception.
//
///////////////////////////////////////////////////////////////////////////////
assign div_nx_out_in= d7stg_grd || d7stg_stk;
dffe #(1) i_div_nx_out (
.din (div_nx_out_in),
.en (d7stg_fdiv),
.clk (rclk),
.q (div_nx_out),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Divide exception output.
//
///////////////////////////////////////////////////////////////////////////////
// Austin update
// Overflow is always accompanied by inexact.
// Previously this was handled within the FFU.
// assign div_exc_out[4:0]= {div_nv_out, div_of_out, div_uf_out, div_dz_out,
// div_nx_out};
assign div_exc_out[4:0] =
{div_nv_out,
div_of_out,
div_uf_out,
div_dz_out,
(div_nx_out || div_of_out)}; // Overflow is always accompanied by inexact
///////////////////////////////////////////////////////////////////////////////
//
// Divide pipeline control logic.
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide normalization and special input injection.
//
///////////////////////////////////////////////////////////////////////////////
assign d1stg_spc_rslt= (d1stg_inf_in || d1stg_zero_in) && (!d1stg_nan_in);
assign div_norm_frac_in1_dbl_norm= d1stg_fdiv && d1stg_norm_dbl_in1
&& (!d1stg_snan_dbl_in2)
&& ((!d1stg_qnan_dbl_in2) || d1stg_snan_dbl_in1)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in1_dbl_dnrm= d1stg_fdiv && d1stg_denorm_dbl_in1
&& (!d1stg_snan_dbl_in2)
&& (!d1stg_qnan_dbl_in2)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in1_sng_norm= d1stg_fdiv && d1stg_norm_sng_in1
&& (!d1stg_snan_sng_in2)
&& ((!d1stg_qnan_sng_in2) || d1stg_snan_sng_in1)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in1_sng_dnrm= d1stg_fdiv && d1stg_denorm_sng_in1
&& (!d1stg_snan_sng_in2)
&& (!d1stg_qnan_sng_in2)
&& (!d1stg_spc_rslt);
assign div_norm_frac_in2_dbl_norm= (d2stg_fdiv && d2stg_norm_dbl_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in))
|| (d1stg_fdiv && d1stg_snan_dbl_in2)
|| (d1stg_fdiv && d1stg_qnan_dbl_in2 && (!d1stg_snan_dbl_in1));
assign div_norm_frac_in2_dbl_dnrm= d2stg_fdiv && d2stg_denorm_dbl_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in);
assign div_norm_frac_in2_sng_norm= (d2stg_fdiv && d2stg_norm_sng_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in))
|| (d1stg_fdiv && d1stg_snan_sng_in2)
|| (d1stg_fdiv && d1stg_qnan_sng_in2 && (!d1stg_snan_sng_in1));
assign div_norm_frac_in2_sng_dnrm= d2stg_fdiv && d2stg_denorm_sng_in2
&& (!d2stg_infnan_in) && (!d2stg_zero_in);
assign div_norm_inf= (d2stg_fdiv && (d2stg_infnan_in || d2stg_zero_in))
|| (d1stg_fdiv && ((d1stg_inf_in1 && (!d1stg_infnan_in2))
|| (d1stg_zero_in2 && (!d1stg_infnan_in1)
&& (!d1stg_zero_in1))));
assign div_norm_qnan= d1stg_fdiv && (d1stg_2inf_in || d1stg_2zero_in);
assign div_norm_zero= d1stg_fdiv
&& ((d1stg_inf_in2 && (!d1stg_infnan_in1))
|| (d1stg_zero_in1 && (!d1stg_infnan_in2)
&& (!d1stg_zero_in2)));
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide left shift.
//
///////////////////////////////////////////////////////////////////////////////
assign div_frac_add_in2_load= d4stg_fdiv || d6stg_fdiv;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide adder/subtractor 2nd input.
//
///////////////////////////////////////////////////////////////////////////////
assign d6stg_frac_out_shl1= (!div_frac_out_54) && (!div_exp_out[12])
&& (div_exp_out[11:1]!=11'b0);
assign d6stg_frac_out_nosh= (!d6stg_frac_out_shl1);
assign div_frac_add_in1_add= d5stg_fdiv && (!div_exp1[12]) && d8stg_step;
assign div_frac_add_in1_load= d4stg_fdiv
|| (d5stg_fdiv && (!div_exp1[12]) && d8stg_step)
|| d6stg_fdiv;
///////////////////////////////////////////////////////////////////////////////
//
// Divide rounding bits.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_lsb_in= (d6stg_fdivd && d6stg_frac_2)
|| ((!d6stg_fdivd) && d6stg_frac_31);
assign d7stg_grd_in= (d6stg_fdivd && d6stg_frac_1)
|| ((!d6stg_fdivd) && d6stg_frac_30);
assign d7stg_stk_in= (d6stg_fdivd && d6stg_frac_0)
|| ((!d6stg_fdivd) && d6stg_frac_29)
|| div_frac_add_in1_neq_0;
dffe #(1) i_d7stg_lsb (
.din (d7stg_lsb_in),
.en (d6stg_fdiv),
.clk (rclk),
.q (d7stg_lsb),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d7stg_grd (
.din (d7stg_grd_in),
.en (d6stg_fdiv),
.clk (rclk),
.q (d7stg_grd),
.se (se),
.si (),
.so ()
);
dffe #(1) i_d7stg_stk (
.din (d7stg_stk_in),
.en (d6stg_fdiv),
.clk (rclk),
.q (d7stg_stk),
.se (se),
.si (),
.so ()
);
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide adder/subtractor and fraction output register.
//
///////////////////////////////////////////////////////////////////////////////
assign d7stg_rndup= ((div_rnd_mode[1:0]==2'b10) && (!div_sign_out)
&& (d7stg_grd || d7stg_stk))
|| ((div_rnd_mode[1:0]==2'b11) && div_sign_out
&& (d7stg_grd || d7stg_stk))
|| ((div_rnd_mode[1:0]==2'b00)
&& ((d7stg_grd && d7stg_stk)
|| (d7stg_grd && (!d7stg_stk) && d7stg_lsb)));
assign d7stg_rndup_inv= (!d7stg_rndup);
assign d7stg_to_0= (div_rnd_mode[1:0]==2'b01)
|| ((div_rnd_mode[1:0]==2'b10) && div_sign_out)
|| ((div_rnd_mode[1:0]==2'b11) && (!div_sign_out));
assign d7stg_to_0_inv= (!d7stg_to_0);
assign div_frac_out_add_in1= d7stg_fdiv && (!d7stg_rndup) && (!d7stg_in_of);
assign div_frac_out_add= d7stg_fdiv && d7stg_rndup && (!d7stg_in_of);
assign div_frac_out_shl1_dbl= d5stg_fdivd && (!div_exp1[12]) && d8stg_step;
assign div_frac_out_shl1_sng= d5stg_fdivs && (!div_exp1[12]) && d8stg_step;
assign div_frac_out_of= d7stg_fdiv && d7stg_in_of;
assign div_frac_out_load= d4stg_fdiv
|| d7stg_fdiv
|| div_frac_out_shl1_dbl
|| div_frac_out_shl1_sng;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide exponent adder in the front end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd1_in1_dbl_in= ((d1stg_stepa && inq_op[1])
|| ((!d1stg_stepa) && d1stg_dblopa[4]))
&& (!((d1stg_fdiv || d2stg_fdiv || d3stg_fdiv) && (!reset)));
dff #(1) i_div_expadd1_in1_dbl (
.din (div_expadd1_in1_dbl_in),
.clk (rclk),
.q (div_expadd1_in1_dbl),
.se (se),
.si (),
.so ()
);
assign div_expadd1_in1_sng_in= ((d1stg_stepa && inq_op[0])
|| ((!d1stg_stepa) && d1stg_sngopa[4]))
&& (!((d1stg_fdiv || d2stg_fdiv || d3stg_fdiv) && (!reset)));
dff #(1) i_div_expadd1_in1_sng (
.din (div_expadd1_in1_sng_in),
.clk (rclk),
.q (div_expadd1_in1_sng),
.se (se),
.si (),
.so ()
);
assign div_expadd1_in2_exp_in2_dbl= d2stg_fdivd;
assign div_expadd1_in2_exp_in2_sng= d2stg_fdivs;
assign div_exp1_expadd1= d1stg_fdiv
|| (d2stg_fdiv && (!d2stg_infnan_in) && (!d2stg_zero_in))
|| d3stg_fdiv
|| d4stg_fdiv;
assign div_exp1_0835= d2stg_fdivd && d2stg_max_exp;
assign div_exp1_0118= d2stg_fdivs && d2stg_max_exp;
assign div_exp1_zero= d2stg_fdiv && d2stg_zero_exp;
assign d2stg_max_exp= d2stg_nan_in || d2stg_inf_in1 || d2stg_zero_in2;
assign d2stg_zero_exp= (d2stg_inf_in2 && (!d2stg_infnan_in1))
|| (d2stg_zero_in1 && (!d2stg_infnan_in2) && (!d2stg_zero_in2));
assign div_exp1_load= d1stg_fdiv || d2stg_fdiv || d3stg_fdiv || d4stg_fdiv;
///////////////////////////////////////////////////////////////////////////////
//
// Select lines- divide exponent adder in the back end of the divide pipe.
//
///////////////////////////////////////////////////////////////////////////////
assign div_expadd2_in1_exp_out_in= d6stg_opdec_in[2] || d6stg_fdiv;
dffr #(1) i_div_expadd2_in1_exp_out (
.din (div_expadd2_in1_exp_out_in),
.rst (reset),
.clk (rclk),
.q (div_expadd2_in1_exp_out),
.se (se),
.si (),
.so ()
);
assign div_expadd2_no_decr_inv_in= (!(div_frac_out_53
|| (div_exp1[11:0]==(({12{(!d5stg_fdivs)}} & 12'h035)
| ({12{d5stg_fdivs}} & 12'h018)))
|| div_expadd2_12));
assign div_expadd2_no_decr_load= d5stg_fdiv && d8stg_step;
dffe #(1) i_div_expadd2_no_decr_inv (
.din (div_expadd2_no_decr_inv_in),
.en (div_expadd2_no_decr_load),
.clk (rclk),
.q (div_expadd2_no_decr_inv),
.se (se),
.si (),
.so ()
);
assign div_expadd2_cin= d5stg_fdiv || d7stg_fdiv;
assign div_exp_out_zero= d7stg_fdiv && div_exp_out[12];
assign div_exp_out_expadd22_inv= (!(d6stg_fdiv
|| (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)));
assign div_exp_out_expadd2= ((d7stg_fdiv && d7stg_rndup && (!d7stg_in_of))
|| (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)
|| d6stg_fdiv)
&& (!div_exp_out_zero);
assign div_exp_out_of= d7stg_fdiv && d7stg_in_of;
assign div_exp_out_exp_out= d7stg_fdiv
&& (!d7stg_in_of)
&& (!div_exp_out_zero);
assign div_exp_out_load= (d5stg_fdiv && (div_cnt[5:0]==6'b0) && d8stg_step)
|| d6stg_fdiv
|| d7stg_fdiv;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__OR3B_1_V
`define SKY130_FD_SC_HD__OR3B_1_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog wrapper for or3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__or3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__or3b_1 (
X ,
A ,
B ,
C_N
);
output X ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__or3b base (
.X(X),
.A(A),
.B(B),
.C_N(C_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__OR3B_1_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EBUFN_TB_V
`define SKY130_FD_SC_HS__EBUFN_TB_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__ebufn.v"
module top();
// Inputs are registered
reg A;
reg TE_B;
reg VPWR;
reg VGND;
// Outputs are wires
wire Z;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
TE_B = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 TE_B = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 A = 1'b1;
#120 TE_B = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 A = 1'b0;
#200 TE_B = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 TE_B = 1'b1;
#320 A = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 TE_B = 1'bx;
#400 A = 1'bx;
end
sky130_fd_sc_hs__ebufn dut (.A(A), .TE_B(TE_B), .VPWR(VPWR), .VGND(VGND), .Z(Z));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__EBUFN_TB_V
|
`timescale 1ns / 1ps
`include "hal/WcaPortDefs.h" //grab register addresses.
// Name: WcaPortController.v
//
// Copyright(c) 2013 Loctronix Corporation
// http://www.loctronix.com
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
module WcaPortController(
input wire reset,
input wire enable,
output wire [(NBITS_ADDR+2):0] portCtrl, // Port State Control bits {addr[NBITS_ADDR:0], read, write, clk }
input wire [1:0] portCmd, // Port Command ID
//Port Interface
output wire [(NBITS_ADDR+1):0] pifCtrl, // {addr[NBITS_ADDR:0], iocmd[1:0] }
input wire [6:0] pifStatus // I/O Status {fifo_full[0], fifo_empty[0], ioBusy, ioState[2:0], clk}
);
parameter COUNT_PORTS = 1;
parameter NBITS_ADDR = 2;
parameter ADDR_MODE = 0;
parameter ADDR_OVERRIDE = 0;
`define PORT_ADDR_MODE_SEQUENTIAL 0
`define PORT_ADDR_MODE_FIXED 1
//State machine states.
`define S_IDLE 3'h0 //Idling state Fixed addressing mode only.
`define S_ADDR 3'h0 //Addressing state. Sequential addressing mode only.
`define S_ADDR_WAIT1 3'h1 //Addressing wait state #1. Sequential addressing mode only.
`define S_ADDR_WAIT2 3'h2 //Addressing wait state #2. Sequential addressing mode only.
`define S_ADDR_WAIT3 3'h3 //Addressing wait state #3. Sequential addressing mode only.
`define S_CMD 3'h4 //Command Initation
`define S_CMD_WAIT1 3'h5 //Wait for IF to settle #1
`define S_CMD_WAIT2 3'h6 //Wait for IF to settle #2
`define S_WAIT_COMPLETE 3'h7 //Wait for Command Completion.
`define ADDR_INCREMENT 2'h1; //Increment address by one.
reg [NBITS_ADDR-1:0] addr;
reg [2:0] cmdState;
reg [1:0] cmd;
wire read;
wire write;
//Map Inputs to Outputs.
assign read = pifStatus[3:1] == `PIFSTAT_READ;
assign write = pifStatus[3:1] == `PIFSTAT_WRITE;
assign pifCtrl = { addr, cmd};
assign portCtrl[NBITS_ADDR+2: 1] = {addr, read, write};
WcaPassthrough pthruClk(.a(pifStatus[0]), .b(portCtrl[0]));
//Control processing of port data based on count.
generate if( ADDR_MODE == `PORT_ADDR_MODE_SEQUENTIAL)
begin
always @(posedge pifStatus[0])
begin :PIFCMD_STATE_MACHINE
if( reset)
begin
addr <= COUNT_PORTS-1;
cmdState <= `S_ADDR;
cmd <= `PIFCMD_IDLE;
end
else
//State machine performs addressing, command, and wait processing.
case (cmdState)
`S_ADDR:
begin
cmd <= `PIFCMD_IDLE;
if( enable)
begin
cmdState <= `S_ADDR_WAIT1;
if( addr == COUNT_PORTS-1) addr <= 0;
else addr <= addr + `ADDR_INCREMENT;
end
end
`S_ADDR_WAIT1: //Wait one for address to settle.
begin
cmdState <= `S_ADDR_WAIT2;
end
`S_ADDR_WAIT2: //Wait another for address to settle.
begin
cmdState <= `S_ADDR_WAIT3;
end
`S_ADDR_WAIT3: //Wait another for address to settle.
begin
cmdState <= `S_CMD;
end
`S_CMD:
begin
cmd <= portCmd;
if( portCmd != `PIFCMD_IDLE)
begin
cmdState <= `S_CMD_WAIT1;
end
else
begin
cmdState <= `S_ADDR;
end
end
`S_CMD_WAIT1: //Wait one clock for the IF to catch up.
begin
cmdState <= `S_CMD_WAIT2;
end
`S_CMD_WAIT2: //Wait another clock for the IF to catch up.
begin
cmdState <= `S_WAIT_COMPLETE;
end
`S_WAIT_COMPLETE:
begin
cmd <= `PIFCMD_IDLE;
if( ~pifStatus[4] ) //if no longer busy, return to idle.
cmdState <= `S_ADDR;
end
endcase
end
end
//*******************************************************************************
// FIXED ADDRESSING MODE.
//*******************************************************************************
else if( ADDR_MODE == `PORT_ADDR_MODE_FIXED)
begin
always @(posedge pifStatus[0])
begin :PIFCMD_STATE_MACHINE
if( reset)
begin
addr <= ADDR_OVERRIDE;
cmdState <= `S_IDLE;
cmd <= `PIFCMD_IDLE;
end
else
//State machine performs addressing, command, and wait processing.
case (cmdState)
`S_IDLE:
begin
cmd <= `PIFCMD_IDLE;
if( enable)
cmdState <= `S_CMD;
end
`S_CMD:
begin
cmd <= portCmd;
if( portCmd != `PIFCMD_IDLE)
begin
cmdState <= `S_CMD_WAIT1;
end
else
begin
cmdState <= `S_IDLE;
end
end
`S_CMD_WAIT1: //Wait one clock for the IF to catch up.
begin
cmdState <= `S_CMD_WAIT2;
end
`S_CMD_WAIT2: //Wait another clock for the IF to catch up.
begin
cmdState <= `S_WAIT_COMPLETE;
end
`S_WAIT_COMPLETE:
begin
cmd <= `PIFCMD_IDLE;
if( ~pifStatus[4] ) //if no longer busy, return to idle.
cmdState <= `S_ADDR;
end
endcase
end
end
endgenerate
endmodule
|
/////////////////////////////////////////////////////////////////////////
// Copyright (c) 2008 Xilinx, Inc. All rights reserved.
//
// XILINX CONFIDENTIAL PROPERTY
// This document contains proprietary information which is
// protected by copyright. All rights are reserved. This notice
// refers to original work by Xilinx, Inc. which may be derivitive
// of other work distributed under license of the authors. In the
// case of derivitive work, nothing in this notice overrides the
// original author's license agreeement. Where applicable, the
// original license agreement is included in it's original
// unmodified form immediately below this header.
//
// Xilinx, Inc.
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
// COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR
// STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION
// IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE
// FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.
// XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO
// THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO
// ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
// AND FITNESS FOR A PARTICULAR PURPOSE.
//
/////////////////////////////////////////////////////////////////////////
module FifoBuffer(
din,
rd_clk,
rd_en,
rst,
wr_clk,
wr_en,
dout,
empty,
full);
input [31 : 0] din;
input rd_clk;
input rd_en;
input rst;
input wr_clk;
input wr_en;
output [31 : 0] dout;
output empty;
output full;
wire full_wire, wr_ack_wire;
async_fifo buffer_fifo (.din(din), .rd_clk(rd_clk), .rd_en(rd_en), .rst(rst), .wr_clk(wr_clk), .wr_en(wr_en), .dout(dout), .full(full_wire), .wr_ack(wr_ack_wire), .empty(empty) );
defparam buffer_fifo.FIFO_WIDTH = 32;
defparam buffer_fifo.FIFO_DEPTH = 10;
defparam buffer_fifo.DEVICE = "7SERIES" ;
defparam buffer_fifo.FIFO_RAM_TYPE = "BLOCKRAM";
// defparam buffer_fifo.OPTIMIZE = "POWER";
assign full = full_wire;
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// This is the LVDS/DDR interface, note that overrange is independent of data path,
// software will not be able to relate overrange to a specific sample!
// Alternative is to concatenate sample value and or status for data.
`timescale 1ns/100ps
module axi_ad9652_if (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// interface outputs
adc_clk,
adc_data_a,
adc_data_b,
adc_or_a,
adc_or_b,
adc_status,
// processor control signals
adc_ddr_edgesel,
// delay control signals
up_clk,
up_dld,
up_dwdata,
up_drdata,
delay_clk,
delay_rst,
delay_locked);
// This parameter controls the buffer type based on the target device.
parameter PCORE_BUFTYPE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [15:0] adc_data_in_p;
input [15:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// interface outputs
output adc_clk;
output [15:0] adc_data_a;
output [15:0] adc_data_b;
output adc_or_a;
output adc_or_b;
output adc_status;
// processor control signals
input adc_ddr_edgesel;
// delay control signals
input up_clk;
input [16:0] up_dld;
input [84:0] up_dwdata;
output [84:0] up_drdata;
input delay_clk;
input delay_rst;
output delay_locked;
// internal registers
reg adc_status = 'd0;
reg [15:0] adc_data_p = 'd0;
reg [15:0] adc_data_n = 'd0;
reg [15:0] adc_data_p_d = 'd0;
reg adc_or_p = 'd0;
reg adc_or_n = 'd0;
reg adc_or_p_d = 'd0;
reg [15:0] adc_data_a = 'd0;
reg [15:0] adc_data_b = 'd0;
reg adc_or_a = 'd0;
reg adc_or_b = 'd0;
// internal signals
wire [15:0] adc_data_p_s;
wire [15:0] adc_data_n_s;
wire adc_or_p_s;
wire adc_or_n_s;
genvar l_inst;
// two data pin modes are supported-
// mux - across clock edges (rising or falling edges),
// mux - within clock edges (lower 7 bits and upper 7 bits)
always @(posedge adc_clk) begin
adc_status <= 1'b1;
adc_data_p <= adc_data_p_s;
adc_data_n <= adc_data_n_s;
adc_data_p_d <= adc_data_p;
adc_or_p <= adc_or_p_s;
adc_or_n <= adc_or_n_s;
adc_or_p_d <= adc_or_p;
end
always @(posedge adc_clk) begin
if (adc_ddr_edgesel == 1'b1) begin
adc_data_a <= adc_data_p_d;
adc_data_b <= adc_data_n;
adc_or_a <= adc_or_p_d;
adc_or_b <= adc_or_n;
end else begin
adc_data_a <= adc_data_n;
adc_data_b <= adc_data_p;
adc_or_a <= adc_or_n;
adc_or_b <= adc_or_p;
end
end
// data interface
generate
for (l_inst = 0; l_inst <= 15; l_inst = l_inst + 1) begin : g_adc_if
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (0),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_data (
.rx_clk (adc_clk),
.rx_data_in_p (adc_data_in_p[l_inst]),
.rx_data_in_n (adc_data_in_n[l_inst]),
.rx_data_p (adc_data_p_s[l_inst]),
.rx_data_n (adc_data_n_s[l_inst]),
.up_clk (up_clk),
.up_dld (up_dld[l_inst]),
.up_dwdata (up_dwdata[((l_inst*5)+4):(l_inst*5)]),
.up_drdata (up_drdata[((l_inst*5)+4):(l_inst*5)]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked ());
end
endgenerate
// over-range interface
ad_lvds_in #(
.BUFTYPE (PCORE_BUFTYPE),
.IODELAY_CTRL (1),
.IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_adc_or (
.rx_clk (adc_clk),
.rx_data_in_p (adc_or_in_p),
.rx_data_in_n (adc_or_in_n),
.rx_data_p (adc_or_p_s),
.rx_data_n (adc_or_n_s),
.up_clk (up_clk),
.up_dld (up_dld[16]),
.up_dwdata (up_dwdata[84:80]),
.up_drdata (up_drdata[84:80]),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked));
// clock
ad_lvds_clk #(
.BUFTYPE (PCORE_BUFTYPE))
i_adc_clk (
.clk_in_p (adc_clk_in_p),
.clk_in_n (adc_clk_in_n),
.clk (adc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*------------------------------------------------------------------------
Purpose
- Data serializing;
- bit staffing;
- nrzi encoding;
- remote wakeup signaling.
------------------------------------------------------------------------*/
module usb_encoder (
input clk,
input rst0_async,
input rst0_sync,
//USB
output reg dtx_plus,
output reg dtx_minus,
output reg dtx_oe,
//DECODER
input usb_interpack,
//ENCFIFO
input encfifo_wr,
input encfifo_wdata,
output encfifo_full,
input remote_wakeup,
input speed
);
wire usb_j;
wire usb_k;
wire encfifo_empty;
reg encfifo_rd;
wire encfifo_rdata;
reg[17:0] counter;
reg[2:0] stuffbit;
reg[3:0] enc_state;
localparam ENC_IDLE=4'd0,
ENC_TIME1=4'd1,
ENC_DRIVE=4'd2,
ENC_STUFF=4'd3,
ENC_SE0=4'd4,
ENC_TIME2=4'd5,
ENC_DRIVEJ=4'd6,
ENC_TIME3=4'd7,
ENC_DRIVEK=4'd8;
usb_fifo_sync #(.ADDR_WIDTH(1'd1),.WDATA_WIDTH(1'd0),.RDATA_WIDTH(1'd0))
i_encfifo
(
.clk(clk),
.rst0_async(rst0_async),
.rst0_sync(rst0_sync),
.wr_en(encfifo_wr),
.wr_data(encfifo_wdata),
.rd_en(encfifo_rd),
.rd_data(encfifo_rdata),
.fifo_full(encfifo_full),
.fifo_empty(encfifo_empty)
);
assign usb_j= speed ? 1'b1 : 1'b0;
assign usb_k= speed ? 1'b0 : 1'b1;
always @(posedge clk, negedge rst0_async)
begin
if(!rst0_async)
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
else if(!rst0_sync)
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
else
begin
case(enc_state)
ENC_IDLE:
begin
stuffbit<=3'd0;
counter<=18'd0;
encfifo_rd<=1'b0;
dtx_plus<= usb_j;
dtx_minus<= ~usb_j;
dtx_oe<= (!encfifo_empty & usb_interpack) |
remote_wakeup ? 1'b1 : 1'b0;
enc_state<= remote_wakeup ? ENC_DRIVEK :
!encfifo_empty & usb_interpack ? ENC_TIME1 :
enc_state;
end
ENC_TIME1:
begin
counter<= counter+1'b1;
encfifo_rd<= counter==18'd2 & stuffbit!=3'd6 &
!encfifo_empty ? 1'b1 :
1'b0;
enc_state<= counter==18'd2 & stuffbit==3'd6 ? ENC_STUFF :
counter==18'd2 & encfifo_empty ? ENC_SE0 :
counter==18'd2 ? ENC_DRIVE :
enc_state;
end
ENC_DRIVE:
begin
counter<=18'd0;
encfifo_rd<=1'b0;
stuffbit<= encfifo_rdata ? stuffbit+1'b1 : 3'd0;
dtx_plus<= encfifo_rdata ? dtx_plus : ~dtx_plus;
dtx_minus<= encfifo_rdata ? ~dtx_plus : dtx_plus;
enc_state<= ENC_TIME1;
end
ENC_STUFF:
begin
counter<=18'd0;
stuffbit<=3'd0;
dtx_plus<= ~dtx_plus;
dtx_minus<= dtx_plus;
enc_state<= ENC_TIME1;
end
ENC_SE0:
begin
counter<=18'd0;
dtx_plus<=1'b0;
dtx_minus<=1'b0;
enc_state<= ENC_TIME2;
end
ENC_TIME2:
begin
counter<= counter+1'b1;
enc_state<= counter==18'd6 ? ENC_DRIVEJ :
enc_state;
end
ENC_DRIVEJ:
begin
counter<=18'd0;
dtx_plus<= usb_j;
dtx_minus<= ~usb_j;
enc_state<= ENC_TIME3;
end
ENC_TIME3:
begin
counter<= counter+1'b1;
enc_state<= counter==18'd2 ? ENC_IDLE :
enc_state;
end
ENC_DRIVEK:
begin
counter<= counter+1'b1;
dtx_plus<= usb_k;
dtx_minus<= ~usb_k;
//REMOTE WAKEUP SIGNALING:
// ~145000 CYCLES ~2,9ms (FULL SPEED)
// ~18000 CYCLES ~3ms (LOW SPEED)
enc_state<= (speed & counter==18'd145000) |
(!speed & counter==18'd18000) ? ENC_IDLE : enc_state;
end
default:
begin
dtx_plus<=1'b1;
dtx_minus<=1'b0;
dtx_oe<=1'b0;
encfifo_rd<=1'b0;
counter<=18'd0;
stuffbit<=3'd0;
enc_state<=ENC_IDLE;
end
endcase
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUSRECEIVER_M_V
`define SKY130_FD_SC_LP__BUSRECEIVER_M_V
/**
* busreceiver: Bus signal receiver.
*
* Verilog wrapper for busreceiver with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__busreceiver.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_m (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__busreceiver_m (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__busreceiver base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUSRECEIVER_M_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
`define SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
/**
* dlygate4sd2: Delay Buffer 4-stage 0.18um length inner stage gates.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__dlygate4sd2.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VPWR = 1'b0;
#80 A = 1'b1;
#100 VGND = 1'b1;
#120 VPWR = 1'b1;
#140 A = 1'b0;
#160 VGND = 1'b0;
#180 VPWR = 1'b0;
#200 VPWR = 1'b1;
#220 VGND = 1'b1;
#240 A = 1'b1;
#260 VPWR = 1'bx;
#280 VGND = 1'bx;
#300 A = 1'bx;
end
sky130_fd_sc_hs__dlygate4sd2 dut (.A(A), .VPWR(VPWR), .VGND(VGND), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLYGATE4SD2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFXTP_1_V
`define SKY130_FD_SC_LS__SDFXTP_1_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog wrapper for sdfxtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__sdfxtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__sdfxtp_1 (
Q ,
CLK,
D ,
SCD,
SCE
);
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__sdfxtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFXTP_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O22A_BEHAVIORAL_V
/**
* o22a: 2-input OR into both inputs of 2-input AND.
*
* X = ((A1 | A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o22a (
X ,
A1,
A2,
B1,
B2
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
or or1 (or1_out , B2, B1 );
and and0 (and0_out_X, or0_out, or1_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22A_BEHAVIORAL_V |
//////////////////////////////////////////////////////////////////////
//// ////
//// CLK_DIV2.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
//// ////
//// Author(s): ////
//// - Jon Gao ([email protected]) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.2 2005/12/16 06:44:20 Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
// no message
//
//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////
module CLK_DIV2 (
input Reset,
input IN,
output reg OUT
);
always @ (posedge IN or posedge Reset)
if (Reset)
OUT <=0;
else
OUT <=!OUT;
endmodule |
// file: timer_tb.v
//
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module timer_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 10.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bits of the sampling counters
wire [2:1] COUNT;
reg COUNTER_RESET = 0;
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
timer_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
// High bits of the counters
.COUNT (COUNT));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EBUFN_LP2_V
`define SKY130_FD_SC_LP__EBUFN_LP2_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog wrapper for ebufn with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__ebufn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_lp2 (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__ebufn_lp2 (
Z ,
A ,
TE_B
);
output Z ;
input A ;
input TE_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__ebufn base (
.Z(Z),
.A(A),
.TE_B(TE_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__EBUFN_LP2_V
|
`define SMV
`include "assertionFabricVerified.v"
/*
* File: assertionFabricVerified_tb.v
* Verification driver for assertionFabricVerified.v
* Includes assertions for verification
*
*/
module main();
// Inputs to DUT
reg clk;
reg rst;
reg enable;
reg [31:0] bakedInAssertions;
reg [`ROUTING_INPUT_BITS-1:0] routingInput;
reg [4:0] routingBlock_0_inputSelect;
reg [4:0] routingBlock_1_inputSelect;
reg [4:0] routingBlock_2_inputSelect;
reg [4:0] routingBlock_3_inputSelect;
reg [4:0] routingBlock_4_inputSelect;
reg [4:0] routingBlock_5_inputSelect;
reg [4:0] routingBlock_6_inputSelect;
reg [4:0] routingBlock_7_inputSelect;
reg [4:0] routingBlock_8_inputSelect;
reg [4:0] routingBlock_9_inputSelect;
reg [4:0] routingBlock_10_inputSelect;
reg [4:0] routingBlock_11_inputSelect;
reg [4:0] routingBlock_12_inputSelect;
reg [4:0] routingBlock_13_inputSelect;
reg [4:0] routingBlock_14_inputSelect;
reg [4:0] routingBlock_15_inputSelect;
reg [4:0] routingBlock_16_inputSelect;
reg [4:0] routingBlock_17_inputSelect;
reg [4:0] routingBlock_18_inputSelect;
reg [4:0] routingBlock_19_inputSelect;
reg [31:0] logicBlock_0_maskA;
reg [31:0] logicBlock_0_maskB;
reg [31:0] logicBlock_0_constant;
reg logicBlock_0_opBMux;
reg [2:0] logicBlock_0_resultMux;
reg [31:0] logicBlock_1_maskA;
reg [31:0] logicBlock_1_maskB;
reg [31:0] logicBlock_1_constant;
reg logicBlock_1_opBMux;
reg [2:0] logicBlock_1_resultMux;
reg [31:0] logicBlock_2_maskA;
reg [31:0] logicBlock_2_maskB;
reg [31:0] logicBlock_2_constant;
reg logicBlock_2_opBMux;
reg [2:0] logicBlock_2_resultMux;
reg [31:0] logicBlock_3_maskA;
reg [31:0] logicBlock_3_maskB;
reg [31:0] logicBlock_3_constant;
reg logicBlock_3_opBMux;
reg [2:0] logicBlock_3_resultMux;
reg [31:0] logicBlock_4_maskA;
reg [31:0] logicBlock_4_maskB;
reg [31:0] logicBlock_4_constant;
reg logicBlock_4_opBMux;
reg [2:0] logicBlock_4_resultMux;
reg [31:0] logicBlock_5_maskA;
reg [31:0] logicBlock_5_maskB;
reg [31:0] logicBlock_5_constant;
reg logicBlock_5_opBMux;
reg [2:0] logicBlock_5_resultMux;
reg [31:0] logicBlock_6_maskA;
reg [31:0] logicBlock_6_maskB;
reg [31:0] logicBlock_6_constant;
reg logicBlock_6_opBMux;
reg [2:0] logicBlock_6_resultMux;
reg [31:0] logicBlock_7_maskA;
reg [31:0] logicBlock_7_maskB;
reg [31:0] logicBlock_7_constant;
reg logicBlock_7_opBMux;
reg [2:0] logicBlock_7_resultMux;
reg [31:0] logicBlock_8_maskA;
reg [31:0] logicBlock_8_maskB;
reg [31:0] logicBlock_8_constant;
reg logicBlock_8_opBMux;
reg [2:0] logicBlock_8_resultMux;
reg [31:0] logicBlock_9_maskA;
reg [31:0] logicBlock_9_maskB;
reg [31:0] logicBlock_9_constant;
reg logicBlock_9_opBMux;
reg [2:0] logicBlock_9_resultMux;
reg [2:0] assertionBlock_0_num_cks;
reg [1:0] assertionBlock_0_select;
reg assertionBlock_0_res_sel;
reg [2:0] assertionBlock_1_num_cks;
reg [1:0] assertionBlock_1_select;
reg assertionBlock_1_res_sel;
reg [2:0] assertionBlock_2_num_cks;
reg [1:0] assertionBlock_2_select;
reg assertionBlock_2_res_sel;
reg [2:0] assertionBlock_3_num_cks;
reg [1:0] assertionBlock_3_select;
reg assertionBlock_3_res_sel;
reg [2:0] assertionBlock_4_num_cks;
reg [1:0] assertionBlock_4_select;
reg assertionBlock_4_res_sel;
// Outputs of DUT
wire assertionViolated;
wire [31:0] assertionsViolated;
assertionFabric af_t(.clk(clk),
.rst(rst),
.enable(rst),
.bakedInAssertions(bakedInAssertions),
.routingInput(routingInput),
.routingBlock_0_inputSelect(routingBlock_0_inputSelect),
.routingBlock_1_inputSelect(routingBlock_1_inputSelect),
.routingBlock_2_inputSelect(routingBlock_2_inputSelect),
.routingBlock_3_inputSelect(routingBlock_3_inputSelect),
.routingBlock_4_inputSelect(routingBlock_4_inputSelect),
.routingBlock_5_inputSelect(routingBlock_5_inputSelect),
.routingBlock_6_inputSelect(routingBlock_6_inputSelect),
.routingBlock_7_inputSelect(routingBlock_7_inputSelect),
.routingBlock_8_inputSelect(routingBlock_8_inputSelect),
.routingBlock_9_inputSelect(routingBlock_9_inputSelect),
.routingBlock_10_inputSelect(routingBlock_10_inputSelect),
.routingBlock_11_inputSelect(routingBlock_11_inputSelect),
.routingBlock_12_inputSelect(routingBlock_12_inputSelect),
.routingBlock_13_inputSelect(routingBlock_13_inputSelect),
.routingBlock_14_inputSelect(routingBlock_14_inputSelect),
.routingBlock_15_inputSelect(routingBlock_15_inputSelect),
.routingBlock_16_inputSelect(routingBlock_16_inputSelect),
.routingBlock_17_inputSelect(routingBlock_17_inputSelect),
.routingBlock_18_inputSelect(routingBlock_18_inputSelect),
.routingBlock_19_inputSelect(routingBlock_19_inputSelect),
.logicBlock_0_maskA(logicBlock_0_maskA),
.logicBlock_0_maskB(logicBlock_0_maskB),
.logicBlock_0_constant(logicBlock_0_constant),
.logicBlock_0_opBMux(logicBlock_0_opBMux),
.logicBlock_0_resultMux(logicBlock_0_resultMux),
.logicBlock_1_maskA(logicBlock_1_maskA),
.logicBlock_1_maskB(logicBlock_1_maskB),
.logicBlock_1_constant(logicBlock_1_constant),
.logicBlock_1_opBMux(logicBlock_1_opBMux),
.logicBlock_1_resultMux(logicBlock_1_resultMux),
.logicBlock_2_maskA(logicBlock_2_maskA),
.logicBlock_2_maskB(logicBlock_2_maskB),
.logicBlock_2_constant(logicBlock_2_constant),
.logicBlock_2_opBMux(logicBlock_2_opBMux),
.logicBlock_2_resultMux(logicBlock_2_resultMux),
.logicBlock_3_maskA(logicBlock_3_maskA),
.logicBlock_3_maskB(logicBlock_3_maskB),
.logicBlock_3_constant(logicBlock_3_constant),
.logicBlock_3_opBMux(logicBlock_3_opBMux),
.logicBlock_3_resultMux(logicBlock_3_resultMux),
.logicBlock_4_maskA(logicBlock_4_maskA),
.logicBlock_4_maskB(logicBlock_4_maskB),
.logicBlock_4_constant(logicBlock_4_constant),
.logicBlock_4_opBMux(logicBlock_4_opBMux),
.logicBlock_4_resultMux(logicBlock_4_resultMux),
.logicBlock_5_maskA(logicBlock_5_maskA),
.logicBlock_5_maskB(logicBlock_5_maskB),
.logicBlock_5_constant(logicBlock_5_constant),
.logicBlock_5_opBMux(logicBlock_5_opBMux),
.logicBlock_5_resultMux(logicBlock_5_resultMux),
.logicBlock_6_maskA(logicBlock_6_maskA),
.logicBlock_6_maskB(logicBlock_6_maskB),
.logicBlock_6_constant(logicBlock_6_constant),
.logicBlock_6_opBMux(logicBlock_6_opBMux),
.logicBlock_6_resultMux(logicBlock_6_resultMux),
.logicBlock_7_maskA(logicBlock_7_maskA),
.logicBlock_7_maskB(logicBlock_7_maskB),
.logicBlock_7_constant(logicBlock_7_constant),
.logicBlock_7_opBMux(logicBlock_7_opBMux),
.logicBlock_7_resultMux(logicBlock_7_resultMux),
.logicBlock_8_maskA(logicBlock_8_maskA),
.logicBlock_8_maskB(logicBlock_8_maskB),
.logicBlock_8_constant(logicBlock_8_constant),
.logicBlock_8_opBMux(logicBlock_8_opBMux),
.logicBlock_8_resultMux(logicBlock_8_resultMux),
.logicBlock_9_maskA(logicBlock_9_maskA),
.logicBlock_9_maskB(logicBlock_9_maskB),
.logicBlock_9_constant(logicBlock_9_constant),
.logicBlock_9_opBMux(logicBlock_9_opBMux),
.logicBlock_9_resultMux(logicBlock_9_resultMux),
.assertionBlock_0_num_cks(assertionBlock_0_num_cks),
.assertionBlock_0_select(assertionBlock_0_select),
.assertionBlock_0_res_sel(assertionBlock_0_res_sel),
.assertionBlock_1_num_cks(assertionBlock_1_num_cks),
.assertionBlock_1_select(assertionBlock_1_select),
.assertionBlock_1_res_sel(assertionBlock_1_res_sel),
.assertionBlock_2_num_cks(assertionBlock_2_num_cks),
.assertionBlock_2_select(assertionBlock_2_select),
.assertionBlock_2_res_sel(assertionBlock_2_res_sel),
.assertionBlock_3_num_cks(assertionBlock_3_num_cks),
.assertionBlock_3_select(assertionBlock_3_select),
.assertionBlock_3_res_sel(assertionBlock_3_res_sel),
.assertionBlock_4_num_cks(assertionBlock_4_num_cks),
.assertionBlock_4_select(assertionBlock_4_select),
.assertionBlock_4_res_sel(assertionBlock_4_res_sel),
.assertionViolated(assertionViolated),
.assertionsViolated(assertionsViolated));
initial begin
clk =0;
rst=1;
enable=0;
bakedInAssertions=0;
routingInput=0;
routingBlock_0_inputSelect=0;
routingBlock_1_inputSelect=0;
routingBlock_2_inputSelect=0;
routingBlock_3_inputSelect=0;
routingBlock_4_inputSelect=0;
routingBlock_5_inputSelect=0;
routingBlock_6_inputSelect=0;
routingBlock_7_inputSelect=0;
routingBlock_8_inputSelect=0;
routingBlock_9_inputSelect=0;
routingBlock_10_inputSelect=0;
routingBlock_11_inputSelect=0;
routingBlock_12_inputSelect=0;
routingBlock_13_inputSelect=0;
routingBlock_14_inputSelect=0;
routingBlock_15_inputSelect=0;
routingBlock_16_inputSelect=0;
routingBlock_17_inputSelect=0;
routingBlock_18_inputSelect=0;
routingBlock_19_inputSelect=0;
logicBlock_0_maskA=0;
logicBlock_0_maskB=0;
logicBlock_0_constant=0;
logicBlock_0_opBMux=0;
logicBlock_0_resultMux=0;
logicBlock_1_maskA=0;
logicBlock_1_maskB=0;
logicBlock_1_constant=0;
logicBlock_1_opBMux=0;
logicBlock_1_resultMux=0;
logicBlock_2_maskA=0;
logicBlock_2_maskB=0;
logicBlock_2_constant=0;
logicBlock_2_opBMux=0;
logicBlock_2_resultMux=0;
logicBlock_3_maskA=0;
logicBlock_3_maskB=0;
logicBlock_3_constant=0;
logicBlock_3_opBMux=0;
logicBlock_3_resultMux=0;
logicBlock_4_maskA=0;
logicBlock_4_maskB=0;
logicBlock_4_constant=0;
logicBlock_4_opBMux=0;
logicBlock_4_resultMux=0;
logicBlock_5_maskA=0;
logicBlock_5_maskB=0;
logicBlock_5_constant=0;
logicBlock_5_opBMux=0;
logicBlock_5_resultMux=0;
logicBlock_6_maskA=0;
logicBlock_6_maskB=0;
logicBlock_6_constant=0;
logicBlock_6_opBMux=0;
logicBlock_6_resultMux=0;
logicBlock_7_maskA=0;
logicBlock_7_maskB=0;
logicBlock_7_constant=0;
logicBlock_7_opBMux=0;
logicBlock_7_resultMux=0;
logicBlock_8_maskA=0;
logicBlock_8_maskB=0;
logicBlock_8_constant=0;
logicBlock_8_opBMux=0;
logicBlock_8_resultMux=0;
logicBlock_9_maskA=0;
logicBlock_9_maskB=0;
logicBlock_9_constant=0;
logicBlock_9_opBMux=0;
logicBlock_9_resultMux=0;
assertionBlock_0_num_cks=0;
assertionBlock_0_select=0;
assertionBlock_0_res_sel=0;
assertionBlock_1_num_cks=0;
assertionBlock_1_select=0;
assertionBlock_1_res_sel=0;
assertionBlock_2_num_cks=0;
assertionBlock_2_select=0;
assertionBlock_2_res_sel=0;
assertionBlock_3_num_cks=0;
assertionBlock_3_select=0;
assertionBlock_3_res_sel=0;
assertionBlock_4_num_cks=0;
assertionBlock_4_select=0;
assertionBlock_4_res_sel=0;
end // initial
always begin
clk = #5 !clk;
end
endmodule // main
/* *************** SMV Assertions *****************
//SMV-Assertions
#If any of the configuration data is invalid, no asserts will fire. Start easy. any internal configInvalid signals -> no assert
no_asserts_for_invalid_assertionBlock_configuration : assert \rst -> X(G(((\af_t .\assertionBlock_0_configInvalid ) || (\af_t .\assertionBlock_1_configInvalid ) || (\af_t .\assertionBlock_2_configInvalid ) || (\af_t .\assertionBlock_3_configInvalid ) || (\af_t .\assertionBlock_4_configInvalid )) -> ~\assertionViolated ));
no_asserts_for_invalid_logicBlock_configuration : assert \rst -> X(G((\af_t .\logicBlock_0_configInvalid || \af_t .\logicBlock_1_configInvalid || \af_t .\logicBlock_2_configInvalid || \af_t .\logicBlock_3_configInvalid || \af_t .\logicBlock_4_configInvalid || \af_t .\logicBlock_5_configInvalid || \af_t .\logicBlock_6_configInvalid || \af_t .\logicBlock_7_configInvalid || \af_t .\logicBlock_8_configInvalid || \af_t .\logicBlock_9_configInvalid ) -> ~\assertionViolated ));
no_asserts_for_invalid_routingBlock_configuration : assert \rst -> X(G((\af_t .\routingBlock_0_configInvalid || \af_t .\routingBlock_1_configInvalid || \af_t .\routingBlock_2_configInvalid || \af_t .\routingBlock_3_configInvalid || \af_t .\routingBlock_4_configInvalid || \af_t .\routingBlock_5_configInvalid || \af_t .\routingBlock_6_configInvalid || \af_t .\routingBlock_7_configInvalid || \af_t .\routingBlock_8_configInvalid || \af_t .\routingBlock_9_configInvalid || \af_t .\routingBlock_10_configInvalid || \af_t .\routingBlock_11_configInvalid || \af_t .\routingBlock_12_configInvalid || \af_t .\routingBlock_13_configInvalid || \af_t .\routingBlock_14_configInvalid || \af_t .\routingBlock_15_configInvalid || \af_t .\routingBlock_16_configInvalid || \af_t .\routingBlock_17_configInvalid || \af_t .\routingBlock_18_configInvalid || \af_t .\routingBlock_19_configInvalid ) -> ~\assertionViolated ));
using \af_t .\routingBlock_0_configInvalid //free ,\af_t .\routingBlock_1_configInvalid //free ,\af_t .\routingBlock_2_configInvalid //free ,\af_t .\routingBlock_3_configInvalid //free ,\af_t .\routingBlock_4_configInvalid //free ,\af_t .\routingBlock_5_configInvalid //free ,\af_t .\routingBlock_6_configInvalid //free ,\af_t .\routingBlock_7_configInvalid //free ,\af_t .\routingBlock_8_configInvalid //free ,\af_t .\routingBlock_9_configInvalid //free ,\af_t .\routingBlock_10_configInvalid //free ,\af_t .\routingBlock_11_configInvalid //free ,\af_t .\routingBlock_12_configInvalid //free ,\af_t .\routingBlock_13_configInvalid //free ,\af_t .\routingBlock_14_configInvalid //free ,\af_t .\routingBlock_15_configInvalid //free ,\af_t .\routingBlock_16_configInvalid //free ,\af_t .\routingBlock_17_configInvalid //free ,\af_t .\routingBlock_18_configInvalid //free ,\af_t .\routingBlock_19_configInvalid //free ,\af_t .\routingBlock_0_result //free ,\af_t .\routingBlock_1_result //free ,\af_t .\routingBlock_2_result //free ,\af_t .\routingBlock_3_result //free ,\af_t .\routingBlock_4_result //free ,\af_t .\routingBlock_5_result //free ,\af_t .\routingBlock_6_result //free ,\af_t .\routingBlock_7_result //free ,\af_t .\routingBlock_8_result //free ,\af_t .\routingBlock_9_result //free ,\af_t .\routingBlock_10_result //free ,\af_t .\routingBlock_11_result //free ,\af_t .\routingBlock_12_result //free ,\af_t .\routingBlock_13_result //free ,\af_t .\routingBlock_14_result //free ,\af_t .\routingBlock_15_result //free ,\af_t .\routingBlock_16_result //free ,\af_t .\routingBlock_17_result //free ,\af_t .\routingBlock_18_result //free ,\af_t .\routingBlock_19_result //free prove \no_asserts_for_invalid_logicBlock_configuration ,\no_asserts_for_invalid_assertionBlock_configuration ,\no_asserts_for_invalid_routingBlock_configuration ;
//SMV-Assertions
*/ |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Wilson Snyder.
`define checkhw(gotv,w,expv) do if (gotv[(w)*32+:$bits(expv)] !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv[(w)*32+:32]), (expv)); $stop; end while(0);
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
bit [4*32-1:0] w4 = {32'h7c709753, 32'hbc8f6059, 32'h3b0db464, 32'h721a8fad};
bit [8*32-2:0] w8m = {31'h7146e1bf, 32'ha8549e42, 32'hca6960bd, 32'h191b7f9b, 32'h93d79866, 32'hf4489e2b, 32'h8e9a3236, 32'h1d2a2d1d};
bit [8*32-1:0] w8 = {32'hc211addc, 32'he5d4a057, 32'h5cbf88fe, 32'h42cf42e2, 32'heb584263, 32'ha585f118, 32'h231531c8, 32'hc73f7b06};
bit [8*32-0:0] w8p = {1'b1, 32'h096aa54b, 32'h48aae18e, 32'hf9502cea, 32'h518c8b61, 32'h9e8641a2, 32'h0dc0249c, 32'hd421a87a, 32'hb8ee9199};
bit [9*32-1:0] w9 = {32'hca800ac1,
32'h0de4823a, 32'ha51663ac, 32'h96351446, 32'h6b0bbcd5, 32'h4a64b530, 32'h4967d59a, 32'hfcc17292, 32'h57926621};
bit [16*32-2:0] w16m = {31'h77ad72c7, 32'h73aa9cbb, 32'h7ecf026d, 32'h985a3ed2, 32'hfe961c1d, 32'h7a01df72, 32'h79e13d71, 32'hb69e2e32,
32'h09fcbc45, 32'hcfd738c1, 32'hc197ac7c, 32'hc316d727, 32'h903034e4, 32'h92a047d1, 32'h6a5357af, 32'ha82ce9c8};
bit [16*32-1:0] w16 = {32'he49548a7, 32'ha02336a2, 32'h2bb48f0d, 32'h9974e098, 32'h34ae644f, 32'hca46dc2c, 32'h9f71a468, 32'h64ae043e,
32'h7bc94d66, 32'h57aba588, 32'h5b9bb4fe, 32'hb87ed644, 32'hd34b5b20, 32'h712928de, 32'h4bdbd28e, 32'ha0576784};
bit [16*32-0:0] w16p = {1'b1, 32'hd278a306, 32'h374ce262, 32'hb608c88e, 32'h43d3e446, 32'h42e26866, 32'h44c31148, 32'hd3db659f, 32'hb3b84b2e,
32'h1aa7a184, 32'h73b28538, 32'h6384e801, 32'h98d58e00, 32'h9c1d1429, 32'hb407730e, 32'he974c1fd, 32'he787c302};
bit [17*32-1:0] w17 = {32'hf1e322ac,
32'hbbdbd761, 32'h760fe07d, 32'h3808cb28, 32'haf313051, 32'h37dc63b9, 32'hdddb418b, 32'he65a9d64, 32'hc1b6ab23,
32'h11131ac1, 32'h0050e0bc, 32'h442e3754, 32'h0eb4556e, 32'hd153064b, 32'h41349f97, 32'hb6f4149f, 32'h34bb1fb1};
function [7:0] bytehash (input [32*32-1:0] data);
integer i;
bytehash = 0;
for (i=0; i<32*32; ++i) begin
bytehash = {bytehash[0], bytehash[7:1]} ^ data[i +: 8];
end
return bytehash;
endfunction
// Aggregate outputs into a single result vector
// verilator lint_off WIDTH
wire [63:0] result = (bytehash(w4)
^ bytehash(w8m)
^ bytehash(w8)
^ bytehash(w8p)
^ bytehash(w9)
^ bytehash(w16m)
^ bytehash(w16)
^ bytehash(w16p)
^ bytehash(w17));
// verilator lint_on WIDTH
`define EXPECTED_SUM 64'hb6fdb64085fc17f5
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
// verilator lint_off SELRANGE
`checkhw(w4,3,32'h7c709753);
`checkhw(w4,2,32'hbc8f6059);
`checkhw(w4,1,32'h3b0db464);
`checkhw(w4,0,32'h721a8fad);
`checkhw(w8m,7,31'h7146e1bf);
`checkhw(w8m,6,32'ha8549e42);
`checkhw(w8m,5,32'hca6960bd);
`checkhw(w8m,4,32'h191b7f9b);
`checkhw(w8m,3,32'h93d79866);
`checkhw(w8m,2,32'hf4489e2b);
`checkhw(w8m,1,32'h8e9a3236);
`checkhw(w8m,0,32'h1d2a2d1d);
`checkhw(w8,7,32'hc211addc);
`checkhw(w8,6,32'he5d4a057);
`checkhw(w8,5,32'h5cbf88fe);
`checkhw(w8,4,32'h42cf42e2);
`checkhw(w8,3,32'heb584263);
`checkhw(w8,2,32'ha585f118);
`checkhw(w8,1,32'h231531c8);
`checkhw(w8,0,32'hc73f7b06);
`checkhw(w8p,8,1'b1);
`checkhw(w8p,7,32'h096aa54b);
`checkhw(w8p,6,32'h48aae18e);
`checkhw(w8p,5,32'hf9502cea);
`checkhw(w8p,4,32'h518c8b61);
`checkhw(w8p,3,32'h9e8641a2);
`checkhw(w8p,2,32'h0dc0249c);
`checkhw(w8p,1,32'hd421a87a);
`checkhw(w8p,0,32'hb8ee9199);
`checkhw(w9,8,32'hca800ac1);
`checkhw(w9,7,32'h0de4823a);
`checkhw(w9,6,32'ha51663ac);
`checkhw(w9,5,32'h96351446);
`checkhw(w9,4,32'h6b0bbcd5);
`checkhw(w9,3,32'h4a64b530);
`checkhw(w9,2,32'h4967d59a);
`checkhw(w9,1,32'hfcc17292);
`checkhw(w9,0,32'h57926621);
`checkhw(w16m,15,31'h77ad72c7);
`checkhw(w16m,14,32'h73aa9cbb);
`checkhw(w16m,13,32'h7ecf026d);
`checkhw(w16m,12,32'h985a3ed2);
`checkhw(w16m,11,32'hfe961c1d);
`checkhw(w16m,10,32'h7a01df72);
`checkhw(w16m,9,32'h79e13d71);
`checkhw(w16m,8,32'hb69e2e32);
`checkhw(w16m,7,32'h09fcbc45);
`checkhw(w16m,6,32'hcfd738c1);
`checkhw(w16m,5,32'hc197ac7c);
`checkhw(w16m,4,32'hc316d727);
`checkhw(w16m,3,32'h903034e4);
`checkhw(w16m,2,32'h92a047d1);
`checkhw(w16m,1,32'h6a5357af);
`checkhw(w16m,0,32'ha82ce9c8);
// verilator lint_on SELRANGE
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w4 = w4 >>> 1;
w8m = w8m >>> 1;
w8 = w8 >>> 1;
w8p = w8p >>> 1;
w9 = w9 >>> 1;
w16m = w16m >>> 1;
w16 = w16 >>> 1;
w16p = w16p >>> 1;
w17 = w17 >>> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:44:23 03/16/2014
// Design Name:
// Module Name: LC3_computer_top
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module LC3_computer_top(
input clk,
input reset,
input LD_char,
input [7:0] I_char,
output [15:0] DDR,
output WR_DDR
);
wire [39:0] CONTROL;
wire [15:0] DATABUS;
/*REGFILE-RELATIVE INPUT*/
wire [1:0] SR1MUX;
wire [1:0] DRMUX;
/*ALU-RELATIVE INPUT*/
wire [1:0] ALUK;
wire SR2MUX;
/*ADDRESS-RELATIVE INPUT*/
wire ADDR1MUX;
wire [1:0] ADDR2MUX;
wire [1:0] PCMUX;
wire MARMUX;
/*PSR-RELATIVE INPUT*/
wire Set_Priv;
wire PSRMUX;
/*INT-RELATIVE INPUT*/
wire [7:0] INTV;
wire [1:0] VectorMUX;
wire [1:0] SPMUX;
wire [2:0] Int_Priority;
/*GATES*/
wire GateALU;
wire GatePSR;
wire GateSP;
wire GateVector;
wire GateMARMUX;
wire GatePC;
wire GatePCsubtract1;
/*LOAD SIGNAL*/
wire LD_REG;
wire LD_IR;
wire LD_PC;
wire LD_CC;
wire LD_Priv;
wire LD_Priority;
wire LD_Vector;
wire LD_SavedUSP;
wire LD_SavedSSP;
/*STATE MACHINE OUTPUT*/
wire INT;
wire [2:0] CC;
wire [15:0] IR;
wire Priv;
wire BEN;
assign Set_Priv=1'b0;
assign R_W=CONTROL[1];
assign MIO_EN=CONTROL[2];
assign ALUK=CONTROL[4:3];
assign PSRMUX=CONTROL[5];
assign VectorMUX=CONTROL[7:6];
assign MARMUX=CONTROL[8];
assign SPMUX=CONTROL[10:9];
assign ADDR2MUX=CONTROL[12:11];
assign ADDR1MUX=CONTROL[13];
assign SR1MUX= CONTROL[15:14];
assign DRMUX= CONTROL[17:16];
assign PCMUX= CONTROL[19:18];
assign GateSP= CONTROL[20];
assign GatePSR= CONTROL[21];
assign GatePCsubtract1=CONTROL[22];
assign GateVector=CONTROL[23];
assign GateMARMUX=CONTROL[24];
assign GateALU= CONTROL[25];
assign GateMDR= CONTROL[26];
assign GatePC= CONTROL[27];
assign LD_Vector=CONTROL[28];
assign LD_SavedUSP=CONTROL[29];
assign LD_SavedSSP=CONTROL[30];
assign LD_Priv =CONTROL[31];
assign LD_Priority=CONTROL[32];
assign LD_PC =CONTROL[33];
assign LD_CC =CONTROL[34];
assign LD_REG =CONTROL[35];
assign LD_BEN =CONTROL[36];
assign LD_IR =CONTROL[37];
assign LD_MDR =CONTROL[38];
assign LD_MAR =CONTROL[39];
/*instance of StateMachine*/
wire R;
LC3_FSM instance_fsm(
.clk (clk),
.reset (reset),
.Priv (Priv),
.BEN (BEN),
.IR (IR[15:11]),
.R (R),
.INT (INT),
.CONTROL (CONTROL)
);
/*instance of datapath*/
LC3_datapath inst_datapath0(
/*GENERAL INPUT*/
.clk(clk),
.reset(reset),
.DATABUS(DATABUS),
/*REGFILE-RELATIVE INPUT*/
.SR1MUX(SR1MUX),
.DRMUX(DRMUX),
/*ALU-RELATIVE INPUT*/
.ALUK(ALUK),
/*ADDRESS-RELATIVE INPUT*/
.ADDR1MUX(ADDR1MUX),
.ADDR2MUX(ADDR2MUX),
.PCMUX(PCMUX),
.MARMUX(MARMUX),
/*PSR-RELATIVE INPUT*/
.Set_Priv(Set_Priv),
.PSRMUX(PSRMUX),
/*INT-RELATIVE INPUT*/
.INTV(INTV),
.VectorMUX(VectorMUX),
.SPMUX(SPMUX),
.Int_Priority(Int_Priority),
/*GATES*/
.GateALU(GateALU),
.GatePSR(GatePSR),
.GateSP(GateSP),
.GateVector(GateVector),
.GateMARMUX(GateMARMUX),
.GatePC(GatePC),
.GatePCsubtract1(GatePCsubtract1),
/*LOAD SIGNAL*/
.LD_BEN(LD_BEN),
.LD_REG(LD_REG),
.LD_IR(LD_IR),
.LD_PC(LD_PC),
.LD_CC(LD_CC),
.LD_Priv(LD_Priv),
.LD_Priority(LD_Priority),
.LD_Vector(LD_Vector),
.LD_SavedUSP(LD_SavedUSP),
.LD_SavedSSP(LD_SavedSSP),
/*DATABUS OUTPUT*/
.ALUbus_out (DATABUS),
.PSRbus_out (DATABUS),
.SPbus_out (DATABUS),
.Vector_bus_out(DATABUS),
.MARbus_out (DATABUS),
.PCbus_out(DATABUS),
.PCsubtract1_bus_out(DATABUS),
/*STATE MACHINE OUTPUT*/
.INT(INT),
.IR_reg(IR),
.Priv_reg(Priv),
.BEN_reg(BEN)
);
/*instance of MIO*/
LC3_MIO inst_memory_io(
.clk (clk),
.reset (reset),
.DATABUS (DATABUS),
.MIO_EN (MIO_EN),
.R_W (R_W),
.LD_MAR (LD_MAR),
.LD_MDR (LD_MDR),
.GateMDR (GateMDR),
.MDRbus_out (DATABUS),
.KB_INT (KB_INT),
.R (R),
.LD_char (LD_char),
.I_char (I_char),
.DDR (DDR),
.WR_DDR (WR_DDR)
);
/*instance of interrupt controler*/
LC3_int_controller inst_int_controller(
.KB_INT (KB_INT),
.INT_Priority (Int_Priority),
.INTV (INTV)
);
endmodule
|
`include "probador_Rx.v"
`include "Rx_Module.v"
module test_bench_Rxt;
//cables de comunicacion entre modulos
wire clock;
wire reset;
wire start;
wire [7:0] RX_BUF_FRAME_TYPE; //B2..0 110b: Received Cable Reset
wire [15:0] ALERT; //B3 Hard Reset
wire [7:0] RECEIVE_DETECT;
wire [7:0] RECEIVE_BYTE_COUNT;
wire tx_State_Machine_ACTIVE;
wire unexpected_GoodCRC;
wire cC_Busy, cC_IDLE;
wire [7:0] data_In;
wire [15:0] ALERTo;
wire [7:0] RECEIVE_BYTE_COUNTo;
wire GoodCRC_to_PHYo;
wire [7:0] DIR_WRITEo;
wire [7:0] DATA_to_Buffero;
//instancia del probador
probador_Rx p_Rx(.CLK(clock),
.reset(reset),
.Start(start),
.iRX_BUF_FRAME_TYPE(RX_BUF_FRAME_TYPE),
.iALERT(ALERT),
.iRECEIVE_DETECT(RECEIVE_DETECT),
.iRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNT),
.Tx_State_Machine_ACTIVE(tx_State_Machine_ACTIVE),
.Unexpected_GoodCRC(unexpected_GoodCRC),
.CC_Busy(cC_Busy),
.CC_IDLE(cC_IDLE),
.Data_In(data_In),
.oALERT(ALERTo),
.oRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNTo),
.oGoodCRC_to_PHY(GoodCRC_to_PHYo),
.oDIR_WRITE(DIR_WRITEo),
.oDATA_to_Buffer(DATA_to_Buffero)
);
//instancia del registro
Rx_Module maquinita_Rx (.CLK(clock),
.reset(reset),
.Start(start),
.iRX_BUF_FRAME_TYPE(RX_BUF_FRAME_TYPE),
.iALERT(ALERT),
.iRECEIVE_DETECT(RECEIVE_DETECT),
.iRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNT),
.Tx_State_Machine_ACTIVE(tx_State_Machine_ACTIVE),
.Unexpected_GoodCRC(unexpected_GoodCRC),
.CC_Busy(cC_Busy),
.CC_IDLE(cC_IDLE),
.Data_In(data_In),
.oALERT(ALERTo),
.oRECEIVE_BYTE_COUNT(RECEIVE_BYTE_COUNTo),
.oGoodCRC_to_PHY(GoodCRC_to_PHYo),
.oDIR_WRITE(DIR_WRITEo),
.oDATA_to_Buffer(DATA_to_Buffero)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB16TO1_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__MUXB16TO1_FUNCTIONAL_PP_V
/**
* muxb16to1: Buffered 16-input multiplexer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__muxb16to1 (
Z ,
D ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input [15:0] D ;
input [15:0] S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_d0 ;
wire pwrgood_pp1_out_s0 ;
wire pwrgood_pp2_out_d1 ;
wire pwrgood_pp3_out_s1 ;
wire pwrgood_pp4_out_d2 ;
wire pwrgood_pp5_out_s2 ;
wire pwrgood_pp6_out_d3 ;
wire pwrgood_pp7_out_s3 ;
wire pwrgood_pp8_out_d4 ;
wire pwrgood_pp9_out_s4 ;
wire pwrgood_pp10_out_d5 ;
wire pwrgood_pp11_out_s5 ;
wire pwrgood_pp12_out_d6 ;
wire pwrgood_pp13_out_s6 ;
wire pwrgood_pp14_out_d7 ;
wire pwrgood_pp15_out_s7 ;
wire pwrgood_pp16_out_d8 ;
wire pwrgood_pp17_out_s8 ;
wire pwrgood_pp18_out_d9 ;
wire pwrgood_pp19_out_s9 ;
wire pwrgood_pp20_out_d10;
wire pwrgood_pp21_out_s10;
wire pwrgood_pp22_out_d11;
wire pwrgood_pp23_out_s11;
wire pwrgood_pp24_out_d12;
wire pwrgood_pp25_out_s12;
wire pwrgood_pp26_out_d13;
wire pwrgood_pp27_out_s13;
wire pwrgood_pp28_out_d14;
wire pwrgood_pp29_out_s14;
wire pwrgood_pp30_out_d15;
wire pwrgood_pp31_out_s15;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_d0 , D[0], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_s0 , S[0], VPWR, VGND );
bufif1 bufif10 (Z , !pwrgood_pp0_out_d0, pwrgood_pp1_out_s0 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp2 (pwrgood_pp2_out_d1 , D[1], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp3 (pwrgood_pp3_out_s1 , S[1], VPWR, VGND );
bufif1 bufif11 (Z , !pwrgood_pp2_out_d1, pwrgood_pp3_out_s1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp4 (pwrgood_pp4_out_d2 , D[2], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp5 (pwrgood_pp5_out_s2 , S[2], VPWR, VGND );
bufif1 bufif12 (Z , !pwrgood_pp4_out_d2, pwrgood_pp5_out_s2 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp6 (pwrgood_pp6_out_d3 , D[3], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp7 (pwrgood_pp7_out_s3 , S[3], VPWR, VGND );
bufif1 bufif13 (Z , !pwrgood_pp6_out_d3, pwrgood_pp7_out_s3 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp8 (pwrgood_pp8_out_d4 , D[4], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp9 (pwrgood_pp9_out_s4 , S[4], VPWR, VGND );
bufif1 bufif14 (Z , !pwrgood_pp8_out_d4, pwrgood_pp9_out_s4 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp10 (pwrgood_pp10_out_d5 , D[5], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp11 (pwrgood_pp11_out_s5 , S[5], VPWR, VGND );
bufif1 bufif15 (Z , !pwrgood_pp10_out_d5, pwrgood_pp11_out_s5 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp12 (pwrgood_pp12_out_d6 , D[6], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp13 (pwrgood_pp13_out_s6 , S[6], VPWR, VGND );
bufif1 bufif16 (Z , !pwrgood_pp12_out_d6, pwrgood_pp13_out_s6 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp14 (pwrgood_pp14_out_d7 , D[7], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp15 (pwrgood_pp15_out_s7 , S[7], VPWR, VGND );
bufif1 bufif17 (Z , !pwrgood_pp14_out_d7, pwrgood_pp15_out_s7 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp16 (pwrgood_pp16_out_d8 , D[8], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp17 (pwrgood_pp17_out_s8 , S[8], VPWR, VGND );
bufif1 bufif18 (Z , !pwrgood_pp16_out_d8, pwrgood_pp17_out_s8 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp18 (pwrgood_pp18_out_d9 , D[9], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp19 (pwrgood_pp19_out_s9 , S[9], VPWR, VGND );
bufif1 bufif19 (Z , !pwrgood_pp18_out_d9, pwrgood_pp19_out_s9 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp20 (pwrgood_pp20_out_d10, D[10], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp21 (pwrgood_pp21_out_s10, S[10], VPWR, VGND );
bufif1 bufif110 (Z , !pwrgood_pp20_out_d10, pwrgood_pp21_out_s10);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp22 (pwrgood_pp22_out_d11, D[11], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp23 (pwrgood_pp23_out_s11, S[11], VPWR, VGND );
bufif1 bufif111 (Z , !pwrgood_pp22_out_d11, pwrgood_pp23_out_s11);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp24 (pwrgood_pp24_out_d12, D[12], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp25 (pwrgood_pp25_out_s12, S[12], VPWR, VGND );
bufif1 bufif112 (Z , !pwrgood_pp24_out_d12, pwrgood_pp25_out_s12);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp26 (pwrgood_pp26_out_d13, D[13], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp27 (pwrgood_pp27_out_s13, S[13], VPWR, VGND );
bufif1 bufif113 (Z , !pwrgood_pp26_out_d13, pwrgood_pp27_out_s13);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp28 (pwrgood_pp28_out_d14, D[14], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp29 (pwrgood_pp29_out_s14, S[14], VPWR, VGND );
bufif1 bufif114 (Z , !pwrgood_pp28_out_d14, pwrgood_pp29_out_s14);
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp30 (pwrgood_pp30_out_d15, D[15], VPWR, VGND );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp31 (pwrgood_pp31_out_s15, S[15], VPWR, VGND );
bufif1 bufif115 (Z , !pwrgood_pp30_out_d15, pwrgood_pp31_out_s15);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB16TO1_FUNCTIONAL_PP_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:58:37 09/29/2014
// Design Name: fifo
// Module Name: C:/ece4743/projects/lab7_solution/tb_fifo.v
// Project Name: lab7_solution
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: fifo
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_fifo;
// Inputs
reg clk;
reg reset;
reg sclr;
reg wren;
reg rden;
reg [7:0] din;
// Outputs
wire full;
wire empty;
wire [7:0] dout;
// Instantiate the Unit Under Test (UUT)
fifo uut (
.clk(clk),
.reset(reset),
.sclr(sclr),
.wren(wren),
.rden(rden),
.full(full),
.empty(empty),
.din(din),
.dout(dout)
);
initial begin
clk = 0;
#100 //reset delay
forever #30 clk = ~clk;
end
integer errors;
integer writeval;
integer fd;
integer count,status;
reg[8*100:1] aline;
integer i_sclr, i_wren, i_wdata, i_rden, i_rdata, i_full, i_empty;
initial begin
// Initialize Inputs
#1
clk = 0;
reset = 1;
sclr = 0;
wren = 0;
rden = 0;
din = 0;
errors = 0;
count = 0;
fd = $fopen("fifo_vectors.txt","r");
// Wait 100 ns for global reset to finish
#100;
reset = 0;
@(posedge clk);
while ($fgets(aline,fd)) begin
if (count != 0) begin
status = $sscanf(aline,"%x %x %x %x %x %x %x",i_sclr,i_wren, i_wdata, i_rden, i_rdata, i_full, i_empty);
sclr = i_sclr;
wren = i_wren;
din = i_wdata;
rden = i_rden;
@(negedge clk);
if (i_rden) begin
if (i_rdata == dout) begin
$display("%d Pass: dout: %x",count,dout);
end else begin
$display("%d FAIL: dout: %x(%x)",count,dout,i_rdata);
errors = errors+1;
end
end //end if (i_rden)
if (i_full == full) $display("%d Pass: full: %x",count,full);
else begin
$display("%d FAIL: full: %x (%x)",count,full,i_full);
errors = errors+1;
end
if (i_empty == empty) $display("%d Pass: empty: %x",count,empty);
else begin
$display("%d FAIL: empty: %x (%x)",count,empty,i_empty);
errors = errors+1;
end
end //end if (aline)
count = count + 1;
end //end while
if (errors == 0) begin
$display("(%t)PASSED: All vectors passed",$time());
end else begin
$display("(%t)FAILED: %d vectors failed",$time(),errors);
end
end
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2018 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2018.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / OBUFDS_GTM_ADV
// /___/ /\ Filename : OBUFDS_GTM_ADV.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module OBUFDS_GTM_ADV #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [0:0] REFCLK_EN_TX_PATH = 1'b0,
parameter integer REFCLK_ICNTL_TX = 0,
parameter [1:0] RXRECCLK_SEL = 2'b00
)(
output O,
output OB,
input CEB,
input [3:0] I
);
// define constants
localparam MODULE_NAME = "OBUFDS_GTM_ADV";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "OBUFDS_GTM_ADV_dr.v"
`else
reg [0:0] REFCLK_EN_TX_PATH_REG = REFCLK_EN_TX_PATH;
reg [31:0] REFCLK_ICNTL_TX_REG = REFCLK_ICNTL_TX;
reg [1:0] RXRECCLK_SEL_REG = RXRECCLK_SEL;
`endif
`ifdef XIL_XECLIB
wire [3:0] REFCLK_ICNTL_TX_BIN;
`else
reg [3:0] REFCLK_ICNTL_TX_BIN;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
reg glblGTS = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
tri0 glblGTS = glbl.GTS;
`endif
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifdef XIL_XECLIB
assign REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
`else
always @ (trig_attr) begin
#1;
REFCLK_ICNTL_TX_BIN = REFCLK_ICNTL_TX_REG[3:0];
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((REFCLK_ICNTL_TX_REG != 0) &&
(REFCLK_ICNTL_TX_REG != 1) &&
(REFCLK_ICNTL_TX_REG != 3) &&
(REFCLK_ICNTL_TX_REG != 7) &&
(REFCLK_ICNTL_TX_REG != 15))) begin
$display("Error: [Unisim %s-102] REFCLK_ICNTL_TX attribute is set to %d. Legal values for this attribute are 0, 1, 3, 7 or 15. Instance: %m", MODULE_NAME, REFCLK_ICNTL_TX_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
// begin behavioral model
reg I_sel = 1'b0;
// =====================
// Generate I_sel
// =====================
always @(*) begin
case (RXRECCLK_SEL_REG)
2'b00: I_sel <= I[0];
2'b01: I_sel <= I[1];
2'b10: I_sel <= I[2];
2'b11: I_sel <= I[3];
default : I_sel <= I[0];
endcase
end
// =====================
// Generate O
// =====================
assign O = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : I_sel;
assign OB = (~REFCLK_EN_TX_PATH_REG || (CEB === 1'b1) || glblGTS) ? 1'bz : ~I_sel;
`ifndef XIL_XECLIB
`ifdef XIL_TIMING
specify
(CEB => O) = (0:0:0, 0:0:0);
(CEB => OB) = (0:0:0, 0:0:0);
(I[0] => O) = (0:0:0, 0:0:0);
(I[0] => OB) = (0:0:0, 0:0:0);
(I[1] => O) = (0:0:0, 0:0:0);
(I[1] => OB) = (0:0:0, 0:0:0);
(I[2] => O) = (0:0:0, 0:0:0);
(I[2] => OB) = (0:0:0, 0:0:0);
(I[3] => O) = (0:0:0, 0:0:0);
(I[3] => OB) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
`endif
// end behavioral model
endmodule
`endcelldefine
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RD_DATA_FIFO.v when simulating
// the core, RD_DATA_FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RD_DATA_FIFO(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [255 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output empty;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(386),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(385),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
/*******************************************************
MIST32 GCI Special Memory : Device Using
Make : 2011/09/27
Update : 2011/0
*******************************************************/
`default_nettype none
module gci_std_display_device_special_memory
#(
parameter USEMEMSIZE = 32'h00000000,
parameter PRIORITY = 32'h00000000,
parameter DEVICECAT = 32'h00000000
)(
//System
input wire iCLOCK,
input wire inRESET,
//Special Addr Access
input wire iSPECIAL_REQ,
input wire iSPECIAL_RW,
input wire [7:0] iSPECIAL_ADDR,
input wire [31:0] iSPECIAL_DATA,
output wire [31:0] oSPECIAL_DATA
);
integer i;
reg [31:0] b_mem[0:255];
always@(posedge iCLOCK or negedge inRESET)begin
if(!inRESET)begin
for(i = 0; i < 256; i = i + 1)begin
if(i == 0)begin
//USEMEMSIZE
b_mem[i] <= USEMEMSIZE;
end
else if(i == 1)begin
//PRIORITY
b_mem[i] <= PRIORITY;
end
else begin
//Other
b_mem[i] <= 32'h00000000;
end
end
end
else begin
if(iSPECIAL_REQ && iSPECIAL_RW)begin
b_mem [iSPECIAL_ADDR] <= iSPECIAL_ADDR;
end
end
end //always
assign oSPECIAL_DATA = b_mem[iSPECIAL_ADDR];
endmodule
`default_nettype wire
|
module add_tb;
parameter N_BITS_A = 3;
parameter BIN_PT_A = 1;
parameter N_BITS_B = 4;
parameter BIN_PT_B = 3;
parameter N_BITS_OUT = 6;
parameter BIN_PT_OUT = 3;
reg [N_BITS_A-1:0] a;
reg [N_BITS_B-1:0] b;
wire [N_BITS_OUT-1:0] sum;
initial begin
a = 3'b0_0_0; // 0
b = 4'b0_001; // + 1/8
// 1/8
#10
a = 3'b1_1_1; // -1/2
b = 4'b0_001; // + 1/8
// -3/8
#5
a = 3'b1_1_0; // -1
b = 4'b1_100; // + -1/2
// -3/2
#5
a = 3'b0_1_1; // 3/2
b = 4'b1_110; // + -1/4
// 5/4
#10 ;
$finish;
end //initial
add #(.N_BITS_A(N_BITS_A),
.BIN_PT_A(BIN_PT_A),
.N_BITS_B(N_BITS_B),
.BIN_PT_B(BIN_PT_B)) a0 (a, b, sum);
initial begin
$monitor("%t, a = \t(%d,%d)b'%b\t a_padded = \t(%d,%d)b'%b\n%t, b = \t(%d,%d)b'%b\t b_padded = \t(%d,%d)b'%b\n%t, sum = \t\t\t\t\t(%d,%d)b'%b", $time, N_BITS_A, BIN_PT_A, a, N_BITS_OUT, BIN_PT_OUT, a0.a_padded, $time, N_BITS_B, BIN_PT_B, b, N_BITS_OUT, BIN_PT_OUT, a0.b_padded, $time, N_BITS_OUT, BIN_PT_OUT, sum);
end
endmodule //add_tb
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: bw_io_impctl_upclk.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module bw_io_impctl_upclk(int_sclk ,l2clk ,synced_upd_imped ,updclk ,
reset_l ,oe_out ,bypass ,avgcntr_rst ,so_l ,hard_reset_n ,si_l ,se
,global_reset_n );
output updclk ;
output oe_out ;
output bypass ;
output avgcntr_rst ;
output so_l ;
output global_reset_n ;
input int_sclk ;
input l2clk ;
input synced_upd_imped ;
input reset_l ;
input hard_reset_n ;
input si_l ;
input se ;
wire [9:0] scan_data ;
wire [7:0] ucarry ;
wire [7:0] next_ucount ;
wire [7:0] ucount ;
wire net183 ;
wire net184 ;
wire net106 ;
wire net187 ;
wire net72 ;
wire net74 ;
wire net190 ;
wire net78 ;
wire net193 ;
wire net112 ;
wire net80 ;
wire net82 ;
wire net88 ;
wire net121 ;
wire int_avgcntr_rst ;
wire net91 ;
wire net94 ;
wire net97 ;
wire osflag_n ;
wire net164 ;
wire net166 ;
wire net168 ;
wire scan_in ;
wire scan_out ;
wire net178 ;
wire osflag ;
wire oneshot_trig ;
wire net181 ;
bw_u1_soffr_4x I226 (
.q (osflag_n ),
.so (scan_data[9] ),
.ck (l2clk ),
.d (net187 ),
.se (se ),
.sd (scan_in ),
.r_l (hard_reset_n ) );
bw_u1_xor2_4x I218_7_ (
.z (next_ucount[7] ),
.a (ucarry[6] ),
.b (ucount[7] ) );
bw_u1_inv_5x I228 (
.z (int_avgcntr_rst ),
.a (net72 ) );
bw_u1_soffr_4x I229 (
.q (avgcntr_rst ),
.so (scan_data[8] ),
.ck (l2clk ),
.d (int_avgcntr_rst ),
.se (se ),
.sd (scan_data[9] ),
.r_l (global_reset_n ) );
bw_u1_inv_5x I234 (
.z (scan_in ),
.a (si_l ) );
bw_u1_soffr_4x I217_4_ (
.q (ucount[4] ),
.so (scan_data[4] ),
.ck (l2clk ),
.d (next_ucount[4] ),
.se (se ),
.sd (scan_data[5] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_6_ (
.z (next_ucount[6] ),
.a (ucarry[5] ),
.b (ucount[6] ) );
bw_u1_nand2_7x I241 (
.z (net106 ),
.a (net121 ),
.b (net164 ) );
bw_u1_nor2_4x I242 (
.z (net121 ),
.a (net168 ),
.b (synced_upd_imped ) );
bw_u1_soffr_4x I217_3_ (
.q (ucount[3] ),
.so (scan_data[3] ),
.ck (l2clk ),
.d (next_ucount[3] ),
.se (se ),
.sd (scan_data[4] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_5_ (
.z (next_ucount[5] ),
.a (ucarry[4] ),
.b (ucount[5] ) );
bw_u1_nand2_2x I245 (
.z (net94 ),
.a (osflag ),
.b (oneshot_trig ) );
bw_u1_inv_4x I246 (
.z (net168 ),
.a (net94 ) );
bw_u1_nand2_2x I248 (
.z (net91 ),
.a (hard_reset_n ),
.b (reset_l ) );
bw_u1_inv_4x I249 (
.z (net164 ),
.a (net91 ) );
bw_u1_inv_20x I252 (
.z (global_reset_n ),
.a (net106 ) );
bw_u1_nand2_4x I253 (
.z (net190 ),
.a (int_sclk ),
.b (ucount[0] ) );
bw_u1_soffr_4x I217_2_ (
.q (ucount[2] ),
.so (scan_data[2] ),
.ck (l2clk ),
.d (next_ucount[2] ),
.se (se ),
.sd (scan_data[3] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_4_ (
.z (next_ucount[4] ),
.a (ucarry[3] ),
.b (ucount[4] ) );
bw_u1_nor2_6x I255 (
.z (oneshot_trig ),
.a (net181 ),
.b (net193 ) );
bw_u1_nand2_4x I256 (
.z (net181 ),
.a (ucount[2] ),
.b (ucount[3] ) );
bw_u1_nor2_2x I257 (
.z (ucarry[7] ),
.a (net97 ),
.b (net112 ) );
bw_u1_nand2_7x I258 (
.z (oe_out ),
.a (net97 ),
.b (net178 ) );
bw_u1_inv_5x I259 (
.z (bypass ),
.a (osflag_n ) );
bw_u1_inv_4x I260 (
.z (net166 ),
.a (ucarry[7] ) );
bw_u1_inv_4x I163 (
.z (ucarry[0] ),
.a (net190 ) );
bw_u1_inv_2x I261 (
.z (net74 ),
.a (oneshot_trig ) );
bw_u1_nand2_4x I164 (
.z (net193 ),
.a (ucarry[0] ),
.b (ucount[1] ) );
bw_u1_inv_2x I262 (
.z (net72 ),
.a (ucarry[5] ) );
bw_u1_inv_4x I165 (
.z (ucarry[1] ),
.a (net193 ) );
bw_u1_soffr_4x I217_1_ (
.q (ucount[1] ),
.so (scan_data[1] ),
.ck (l2clk ),
.d (next_ucount[1] ),
.se (se ),
.sd (scan_data[2] ),
.r_l (global_reset_n ) );
bw_u1_inv_2x I166 (
.z (net82 ),
.a (ucount[2] ) );
bw_u1_xor2_4x I218_3_ (
.z (next_ucount[3] ),
.a (ucarry[2] ),
.b (ucount[3] ) );
bw_u1_nor2_4x I167 (
.z (ucarry[2] ),
.a (net82 ),
.b (net193 ) );
bw_u1_nor2_4x I175 (
.z (ucarry[6] ),
.a (net78 ),
.b (net112 ) );
bw_u1_soffr_4x I217_0_ (
.q (ucount[0] ),
.so (scan_data[0] ),
.ck (l2clk ),
.d (next_ucount[0] ),
.se (se ),
.sd (scan_data[1] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_2_ (
.z (next_ucount[2] ),
.a (ucarry[1] ),
.b (ucount[2] ) );
bw_u1_inv_5x I179 (
.z (ucarry[5] ),
.a (net112 ) );
bw_u1_inv_2x I180 (
.z (net78 ),
.a (ucount[6] ) );
bw_u1_inv_4x I205 (
.z (ucarry[3] ),
.a (net74 ) );
bw_u1_xor2_4x I218_1_ (
.z (next_ucount[1] ),
.a (ucarry[0] ),
.b (ucount[1] ) );
bw_u1_inv_4x I187 (
.z (ucarry[4] ),
.a (net88 ) );
bw_u1_soffr_4x I217_7_ (
.q (ucount[7] ),
.so (scan_data[7] ),
.ck (l2clk ),
.d (next_ucount[7] ),
.se (se ),
.sd (scan_data[8] ),
.r_l (global_reset_n ) );
bw_u1_nand2_5x I207 (
.z (net97 ),
.a (ucount[6] ),
.b (ucount[7] ) );
bw_u1_inv_4x I208 (
.z (net178 ),
.a (bypass ) );
bw_u1_nand3_4x I189 (
.z (net112 ),
.a (oneshot_trig ),
.b (ucount[4] ),
.c (ucount[5] ) );
bw_u1_nand2_4x I211 (
.z (net184 ),
.a (net166 ),
.b (net183 ) );
bw_u1_nand2_2x I212 (
.z (net183 ),
.a (bypass ),
.b (int_sclk ) );
bw_u1_soffr_4x I217_6_ (
.q (ucount[6] ),
.so (scan_data[6] ),
.ck (l2clk ),
.d (next_ucount[6] ),
.se (se ),
.sd (scan_data[7] ),
.r_l (global_reset_n ) );
bw_u1_xor2_4x I218_0_ (
.z (next_ucount[0] ),
.a (int_sclk ),
.b (ucount[0] ) );
bw_u1_nand2_2x I196 (
.z (net88 ),
.a (oneshot_trig ),
.b (ucount[4] ) );
bw_u1_inv_5x I198 (
.z (so_l ),
.a (scan_out ) );
bw_u1_soffr_4x I199 (
.q (updclk ),
.so (scan_out ),
.ck (l2clk ),
.d (net184 ),
.se (se ),
.sd (scan_data[0] ),
.r_l (global_reset_n ) );
bw_u1_nand2_4x I223 (
.z (net187 ),
.a (osflag ),
.b (net80 ) );
bw_u1_inv_2x I224 (
.z (net80 ),
.a (oneshot_trig ) );
bw_u1_soffr_4x I217_5_ (
.q (ucount[5] ),
.so (scan_data[5] ),
.ck (l2clk ),
.d (next_ucount[5] ),
.se (se ),
.sd (scan_data[6] ),
.r_l (global_reset_n ) );
bw_u1_inv_2x I225 (
.z (osflag ),
.a (osflag_n ) );
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ciop_iob.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
`timescale 1ps/1ps
module ciop_iob(
// Outputs
iob_pcx_stall_pq, iob_jbi_mondo_nack, iob_jbi_mondo_ack,
iob_jbi_dbg_lo_vld, iob_jbi_dbg_lo_data, iob_jbi_dbg_hi_vld,
iob_jbi_dbg_hi_data, iob_io_dbg_en, iob_io_dbg_data,
iob_ctu_coreavail, iob_cpx_req_cq, iob_cpx_data_ca, iob_clk_tr,
iob_clk_l2_tr, iob_clk_data, iob_clk_stall, iob_clk_vld,
iob_dram02_data, iob_dram02_stall, iob_dram02_vld,
iob_dram13_data, iob_dram13_stall, iob_dram13_vld,
iob_jbi_pio_data, iob_jbi_pio_stall, iob_jbi_pio_vld,
iob_jbi_spi_data, iob_jbi_spi_stall, iob_jbi_spi_vld,
iob_tap_data, iob_tap_stall, iob_tap_vld, iob_scanout,
iob_io_dbg_ck_p, iob_io_dbg_ck_n,
// Inputs
pcx_iob_data_rdy_px2, pcx_iob_data_px2, l2_dbgbus_23,
l2_dbgbus_01, jbus_grst_l, jbus_gdbginit_l, jbus_gclk,
jbus_arst_l, jbus_adbginit_l, jbi_iob_mondo_vld,
jbi_iob_mondo_data, io_trigin, io_temp_trig, global_shift_enable,
efc_iob_sernum2_dshift, efc_iob_sernum1_dshift,
efc_iob_sernum0_dshift, efc_iob_fusestat_dshift,
efc_iob_fuse_data, efc_iob_fuse_clk2, efc_iob_fuse_clk1,
efc_iob_coreavail_dshift, dbg_en_23, dbg_en_01,
ctu_tst_short_chain, ctu_tst_scanmode, ctu_tst_scan_disable,
ctu_tst_pre_grst_l, ctu_tst_macrotest, ctu_iob_wake_thr,
cpx_iob_grant_cx2, cmp_grst_l, cmp_gdbginit_l, cmp_gclk,
cmp_arst_l, cmp_adbginit_l, clspine_jbus_tx_sync,
clspine_jbus_rx_sync, clspine_iob_resetstat_wr,
clspine_iob_resetstat, clk_iob_cken, clk_iob_data, clk_iob_stall,
clk_iob_vld, dram02_iob_data, dram02_iob_stall, dram02_iob_vld,
dram13_iob_data, dram13_iob_stall, dram13_iob_vld,
jbi_iob_pio_data, jbi_iob_pio_stall, jbi_iob_pio_vld,
jbi_iob_spi_data, jbi_iob_spi_stall, jbi_iob_spi_vld,
tap_iob_data, tap_iob_stall, tap_iob_vld, iob_scanin,
spc0_inst_done, pc_w0, spc1_inst_done, pc_w1, spc2_inst_done,
pc_w2, spc3_inst_done, pc_w3, spc4_inst_done, pc_w4,
spc5_inst_done, pc_w5, spc6_inst_done, pc_w6, spc7_inst_done,
pc_w7
);
input clk_iob_cken; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v, ...
input [`IOB_RESET_STAT_WIDTH-1:0]clspine_iob_resetstat;// To iobdg_ctrl of iobdg_ctrl.v
input clspine_iob_resetstat_wr;// To iobdg_ctrl of iobdg_ctrl.v
input clspine_jbus_rx_sync; // To cluster_header_sync of cluster_header_sync.v
input clspine_jbus_tx_sync; // To cluster_header_sync of cluster_header_sync.v
input cmp_adbginit_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input cmp_arst_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input cmp_gclk; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v, ...
input cmp_gdbginit_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input cmp_grst_l; // To bw_clk_cl_iobdg_cmp of bw_clk_cl_iobdg_cmp.v
input [`IOB_CPU_WIDTH-1:0]cpx_iob_grant_cx2; // To i2c of i2c.v
input ctu_iob_wake_thr; // To iobdg_ctrl of iobdg_ctrl.v
input ctu_tst_macrotest; // To test_stub_scan of test_stub_scan.v
input ctu_tst_pre_grst_l; // To test_stub_scan of test_stub_scan.v
input ctu_tst_scan_disable; // To test_stub_scan of test_stub_scan.v
input ctu_tst_scanmode; // To test_stub_scan of test_stub_scan.v
input ctu_tst_short_chain; // To test_stub_scan of test_stub_scan.v
input dbg_en_01; // To iobdg_dbg of iobdg_dbg.v
input dbg_en_23; // To iobdg_dbg of iobdg_dbg.v
input efc_iob_coreavail_dshift;// To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fuse_clk1; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fuse_clk2; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fuse_data; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_fusestat_dshift;// To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_sernum0_dshift; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_sernum1_dshift; // To iobdg_ctrl of iobdg_ctrl.v
input efc_iob_sernum2_dshift; // To iobdg_ctrl of iobdg_ctrl.v
input global_shift_enable; // To test_stub_scan of test_stub_scan.v
input io_temp_trig; // To iobdg_ctrl of iobdg_ctrl.v
input io_trigin; // To iobdg_dbg of iobdg_dbg.v
input [`JBI_IOB_MONDO_BUS_WIDTH-1:0]jbi_iob_mondo_data;// To i2c of i2c.v
input jbi_iob_mondo_vld; // To i2c of i2c.v
input jbus_adbginit_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input jbus_arst_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v, ...
input jbus_gclk; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input jbus_gdbginit_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input jbus_grst_l; // To bw_clk_cl_iobdg_jbus of bw_clk_cl_iobdg_jbus.v
input [39:0] l2_dbgbus_01; // To iobdg_dbg of iobdg_dbg.v
input [39:0] l2_dbgbus_23; // To iobdg_dbg of iobdg_dbg.v
input [`PCX_WIDTH-1:0]pcx_iob_data_px2; // To c2i of c2i.v
input pcx_iob_data_rdy_px2; // To c2i of c2i.v
input spc0_inst_done;
input [48:0] pc_w0;
input spc1_inst_done;
input [48:0] pc_w1;
input spc2_inst_done;
input [48:0] pc_w2;
input spc3_inst_done;
input [48:0] pc_w3;
input spc4_inst_done;
input [48:0] pc_w4;
input spc5_inst_done;
input [48:0] pc_w5;
input spc6_inst_done;
input [48:0] pc_w6;
input spc7_inst_done;
input [48:0] pc_w7;
output iob_clk_l2_tr; // From iobdg_dbg of iobdg_dbg.v
output iob_clk_tr; // From iobdg_dbg of iobdg_dbg.v
output [`CPX_WIDTH-1:0]iob_cpx_data_ca; // From i2c of i2c.v
output [`IOB_CPU_WIDTH-1:0]iob_cpx_req_cq; // From i2c of i2c.v
output [`IOB_CPU_WIDTH-1:0]iob_ctu_coreavail;// From iobdg_ctrl of iobdg_ctrl.v
output [39:0] iob_io_dbg_data; // From iobdg_dbg of iobdg_dbg.v
output iob_io_dbg_en; // From iobdg_dbg of iobdg_dbg.v
output [47:0] iob_jbi_dbg_hi_data; // From iobdg_dbg of iobdg_dbg.v
output iob_jbi_dbg_hi_vld; // From iobdg_dbg of iobdg_dbg.v
output [47:0] iob_jbi_dbg_lo_data; // From iobdg_dbg of iobdg_dbg.v
output iob_jbi_dbg_lo_vld; // From iobdg_dbg of iobdg_dbg.v
output iob_jbi_mondo_ack; // From i2c of i2c.v
output iob_jbi_mondo_nack; // From i2c of i2c.v
output iob_pcx_stall_pq; // From c2i of c2i.v
input [`CLK_IOB_WIDTH-1:0]clk_iob_data; // To i2c of i2c.v
input clk_iob_stall; // To c2i of c2i.v
input clk_iob_vld; // To i2c of i2c.v
input [`DRAM_IOB_WIDTH-1:0]dram02_iob_data; // To i2c of i2c.v
input dram02_iob_stall; // To c2i of c2i.v
input dram02_iob_vld; // To i2c of i2c.v
input [`DRAM_IOB_WIDTH-1:0]dram13_iob_data; // To i2c of i2c.v
input dram13_iob_stall; // To c2i of c2i.v
input dram13_iob_vld; // To i2c of i2c.v
input [`JBI_IOB_WIDTH-1:0]jbi_iob_pio_data; // To i2c of i2c.v
input jbi_iob_pio_stall; // To c2i of c2i.v
input jbi_iob_pio_vld; // To i2c of i2c.v
input [`SPI_IOB_WIDTH-1:0]jbi_iob_spi_data; // To i2c of i2c.v
input jbi_iob_spi_stall; // To c2i of c2i.v
input jbi_iob_spi_vld; // To i2c of i2c.v
input [`TAP_IOB_WIDTH-1:0]tap_iob_data; // To c2i of c2i.v
input tap_iob_stall; // To i2c of i2c.v
input tap_iob_vld; // To c2i of c2i.v
output [`IOB_CLK_WIDTH-1:0]iob_clk_data; // From c2i of c2i.v
output iob_clk_stall; // From i2c of i2c.v
output iob_clk_vld; // From c2i of c2i.v
output [`IOB_DRAM_WIDTH-1:0]iob_dram02_data; // From c2i of c2i.v
output iob_dram02_stall; // From i2c of i2c.v
output iob_dram02_vld; // From c2i of c2i.v
output [`IOB_DRAM_WIDTH-1:0]iob_dram13_data; // From c2i of c2i.v
output iob_dram13_stall; // From i2c of i2c.v
output iob_dram13_vld; // From c2i of c2i.v
output [`IOB_JBI_WIDTH-1:0]iob_jbi_pio_data; // From c2i of c2i.v
output iob_jbi_pio_stall; // From i2c of i2c.v
output iob_jbi_pio_vld; // From c2i of c2i.v
output [`IOB_SPI_WIDTH-1:0]iob_jbi_spi_data; // From c2i of c2i.v
output iob_jbi_spi_stall; // From i2c of i2c.v
output iob_jbi_spi_vld; // From c2i of c2i.v
output [`IOB_TAP_WIDTH-1:0]iob_tap_data; // From i2c of i2c.v
output iob_tap_stall; // From c2i of c2i.v
output iob_tap_vld; // From i2c of i2c.v
input iob_scanin;
output iob_scanout;
output [2:0] iob_io_dbg_ck_p;
output [2:0] iob_io_dbg_ck_n;
//temp. memory.
reg [`IOB_CPU_WIDTH-1:0] cpx_req;
reg [`CPX_WIDTH-1:0] cpx_data;
reg pio_vld;
reg [`IOB_JBI_WIDTH-1:0] pio_data;
//jbi ucb
reg [3:0] jspi_data;
reg jspi_stall;
reg jspi_vld;
//iob and dram interface
reg [3:0] dram02_data;
reg dram02_vld;
reg [3:0] dram13_data;
reg dram13_vld;
wire iob_pcx_stall_pq;
wire iob_jbi_pio_stall;
wire iob_jbi_dbg_hi_vld;
wire iob_jbi_dbg_lo_vld;
wire iob_jbi_mondo_ack;
wire iob_jbi_mondo_nack;
wire iob_clk_stall;
wire iob_clk_vld;
wire iob_clspine_stall;
wire iob_clspine_vld;
wire iob_dram02_stall;
wire iob_dram02_vld;
wire iob_dram13_stall;
wire iob_dram13_vld;
wire iob_jbi_spi_stall;
wire iob_jbi_spi_vld;
wire iob_tap_stall;
wire iob_tap_vld;
// input signals
wire [`PCX_WIDTH-1:0] pcx_iob_data = pcx_iob_data_px2;
wire [`IOB_CPU_WIDTH-1:0] cpx_iob_grant = cpx_iob_grant_cx2;
wire spc0_inst_done_buf = spc0_inst_done;
wire [48:0] pc_w0_buf = pc_w0;
wire spc1_inst_done_buf = spc1_inst_done;
wire [48:0] pc_w1_buf = pc_w1;
wire spc2_inst_done_buf = spc2_inst_done;
wire [48:0] pc_w2_buf = pc_w2;
wire spc3_inst_done_buf = spc3_inst_done;
wire [48:0] pc_w3_buf = pc_w3;
wire spc4_inst_done_buf = spc4_inst_done;
wire [48:0] pc_w4_buf = pc_w4;
wire spc5_inst_done_buf = spc5_inst_done;
wire [48:0] pc_w5_buf = pc_w5;
wire spc6_inst_done_buf = spc6_inst_done;
wire [48:0] pc_w6_buf = pc_w6;
wire spc7_inst_done_buf = spc7_inst_done;
wire [48:0] pc_w7_buf = pc_w7;
//drive signals.
assign iob_pcx_stall_pq = 0;
assign iob_jbi_pio_stall = 0;
assign iob_cpx_req_cq = cpx_req;
assign iob_cpx_data_ca = cpx_data;
assign iob_jbi_pio_vld = pio_vld;
assign iob_jbi_pio_data = pio_data;
assign iob_jbi_dbg_hi_vld = 0;
assign iob_jbi_dbg_lo_vld = 0;
assign iob_jbi_mondo_ack = 0;
assign iob_jbi_mondo_nack = 0;
assign iob_clk_stall = 0;
assign iob_clk_vld = 0;
assign iob_clspine_stall = 0;
assign iob_clspine_vld = 0;
assign iob_dram02_stall = 0;
assign iob_dram02_vld = dram02_vld;
assign iob_dram02_data = dram02_data;
assign iob_dram13_stall = 0;
assign iob_dram13_vld = dram13_vld;
assign iob_dram13_data = dram13_data;
assign iob_jbi_spi_stall = 0;
assign iob_jbi_spi_vld = 0;
assign iob_tap_stall = 0;
assign iob_tap_vld = 0;
//jbi ucb interface here
assign iob_jbi_spi_stall = 0;
assign iob_jbi_spi_vld = jspi_vld;
assign iob_jbi_spi_data = jspi_data;
//Start here
reg ok_iob;
initial
begin
ok_iob = 0;
cpx_req = 0;
cpx_data = 0;
pio_vld = 0;
//iob and dram interface
dram02_data = 0;
dram02_vld = 0;
dram13_data = 0;
dram13_vld = 0;
//jbi
jspi_vld = 0;
jspi_data = 0;
$init_iob_model();
//repeat(1)@(posedge jbus_grst_l);//wait for the push butten reset.
repeat(1)@(posedge ctu_iob_wake_thr);
//repeat(4)@(posedge jbus_gclk);//Delay issuing wakeup interrupt to let ccx come out of reset.
ok_iob = 1;
end
//cmp clock domain
always @(negedge cmp_gclk)
begin
if(ok_iob)begin
$iob_cdriver(//input to pli
//pcx packet from core
pcx_iob_data,
//cpx request from iob
cpx_req,
cpx_data,
//grand and request
cpx_iob_grant,
//pc event
spc0_inst_done_buf,
pc_w0_buf,
spc1_inst_done_buf,
pc_w1_buf,
spc2_inst_done_buf,
pc_w2_buf,
spc3_inst_done_buf,
pc_w3_buf,
spc4_inst_done_buf,
pc_w4_buf,
spc5_inst_done_buf,
pc_w5_buf,
spc6_inst_done_buf,
pc_w6_buf,
spc7_inst_done_buf,
pc_w7_buf
);
end // if (ok_iob)
end // always @ (posedge cmp_gclk)
//jbus clock domain
always @(posedge jbus_gclk)begin
if(ok_iob)begin
$iob_jdriver(
pio_vld, pio_data,
//dram and iob interface
//output from pli
dram02_iob_stall, dram02_vld, dram02_data,
dram13_iob_stall, dram13_vld, dram13_data,
//input to pli.
dram02_iob_vld, dram02_iob_data,
dram13_iob_vld, dram13_iob_data,
//pio input 13-14
jbi_iob_pio_vld, jbi_iob_pio_data,
//jbi interface
//out from pli 13-15
jbi_iob_spi_stall, jspi_vld, jspi_data,
//in to pli 16-17
jbi_iob_spi_vld, jbi_iob_spi_data
);
end
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_3_axi_basic_rx_pipeline.v
// Version : 1.3
// //
// Description: //
// TRN to AXI RX pipeline. Converts received data from TRN protocol to AXI. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_rx //
// axi_basic_rx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module pcie_7x_v1_3_axi_basic_rx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
// AXI RX
//-----------
output reg [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output reg m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output reg [21:0] m_axis_rx_tuser, // RX user signals
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output reg trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// Null Inputs
//-----------
input null_rx_tvalid, // NULL generated tvalid
input null_rx_tlast, // NULL generated tlast
input [KEEP_WIDTH-1:0] null_rx_tkeep, // NULL generated tkeep
input null_rdst_rdy, // NULL generated rdst_rdy
input [4:0] null_is_eof, // NULL generated is_eof
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Wires and regs for creating AXI signals
wire [4:0] is_sof;
wire [4:0] is_sof_prev;
wire [4:0] is_eof;
wire [4:0] is_eof_prev;
reg [KEEP_WIDTH-1:0] reg_tkeep;
wire [KEEP_WIDTH-1:0] tkeep;
wire [KEEP_WIDTH-1:0] tkeep_prev;
reg reg_tlast;
wire rsrc_rdy_filtered;
// Wires and regs for previous value buffer
wire [C_DATA_WIDTH-1:0] trn_rd_DW_swapped;
reg [C_DATA_WIDTH-1:0] trn_rd_prev;
wire data_hold;
reg data_prev;
reg trn_reof_prev;
reg [REM_WIDTH-1:0] trn_rrem_prev;
reg trn_rsrc_rdy_prev;
reg trn_rsrc_dsc_prev;
reg trn_rsof_prev;
reg [6:0] trn_rbar_hit_prev;
reg trn_rerrfwd_prev;
reg trn_recrc_err_prev;
// Null packet handling signals
reg null_mux_sel;
reg trn_in_packet;
wire dsc_flag;
wire dsc_detect;
reg reg_dsc_detect;
reg trn_rsrc_dsc_d;
// Create "filtered" version of rsrc_rdy, where discontinued SOFs are removed.
assign rsrc_rdy_filtered = trn_rsrc_rdy &&
(trn_in_packet || (trn_rsof && !trn_rsrc_dsc));
//----------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between TRN and AXI, which causes //
// some issues with handshaking signals m_axis_rx_tready/trn_rdst_rdy. The //
// added cycle of latency in the path causes the user design to fall behind //
// the TRN interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all trn_r* //
// signals in case the user throttles. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rd_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
trn_rsof_prev <= #TCQ 1'b0;
trn_rrem_prev <= #TCQ {REM_WIDTH{1'b0}};
trn_rsrc_rdy_prev <= #TCQ 1'b0;
trn_rbar_hit_prev <= #TCQ 7'h00;
trn_rerrfwd_prev <= #TCQ 1'b0;
trn_recrc_err_prev <= #TCQ 1'b0;
trn_reof_prev <= #TCQ 1'b0;
trn_rsrc_dsc_prev <= #TCQ 1'b0;
end
else begin
// prev buffer works by checking trn_rdst_rdy. When trn_rdst_rdy is
// asserted, a new value is present on the interface.
if(trn_rdst_rdy) begin
trn_rd_prev <= #TCQ trn_rd_DW_swapped;
trn_rsof_prev <= #TCQ trn_rsof;
trn_rrem_prev <= #TCQ trn_rrem;
trn_rbar_hit_prev <= #TCQ trn_rbar_hit;
trn_rerrfwd_prev <= #TCQ trn_rerrfwd;
trn_recrc_err_prev <= #TCQ trn_recrc_err;
trn_rsrc_rdy_prev <= #TCQ rsrc_rdy_filtered;
trn_reof_prev <= #TCQ trn_reof;
trn_rsrc_dsc_prev <= #TCQ trn_rsrc_dsc || dsc_flag;
end
end
end
//----------------------------------------------------------------------------//
// Create TDATA //
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN
// 128-bit: 64-bit: 32-bit:
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0
// TRN DW2 maps to AXI DW1
// TRN DW3 maps to AXI DW0
generate
if(C_DATA_WIDTH == 128) begin : rd_DW_swap_128
assign trn_rd_DW_swapped = {trn_rd[31:0],
trn_rd[63:32],
trn_rd[95:64],
trn_rd[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : rd_DW_swap_64
assign trn_rd_DW_swapped = {trn_rd[31:0], trn_rd[63:32]};
end
else begin : rd_DW_swap_32
assign trn_rd_DW_swapped = trn_rd;
end
endgenerate
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the user has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on trn_rd
// - the user has finished throttling, and is a little behind
// the PCIe block
// CURRENT state: the buffer passes the current value on trn_rd
// - the user is caught up and ready to receive the latest
// data from the PCIe block
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
end
else begin
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
m_axis_rx_tdata <= #TCQ trn_rd_prev;
end
// CURRENT state
else begin
m_axis_rx_tdata <= #TCQ trn_rd_DW_swapped;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = (!m_axis_rx_tready && m_axis_rx_tvalid);
// Logic to instruct pipeline to use previous bus values. Always use previous
// value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//----------------------------------------------------------------------------//
// Create TVALID, TLAST, tkeep, TUSER //
// ----------------------------------- //
// Use the same strategy for these signals as for TDATA, except here we need //
// an extra provision for null packets. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
m_axis_rx_tvalid <= #TCQ 1'b0;
reg_tlast <= #TCQ 1'b0;
reg_tkeep <= #TCQ {KEEP_WIDTH{1'b1}};
m_axis_rx_tuser <= #TCQ 22'h0;
end
else begin
if(!data_hold) begin
// If in a null packet, use null generated value
if(null_mux_sel) begin
m_axis_rx_tvalid <= #TCQ null_rx_tvalid;
reg_tlast <= #TCQ null_rx_tlast;
reg_tkeep <= #TCQ null_rx_tkeep;
m_axis_rx_tuser <= #TCQ {null_is_eof, 17'h0000};
end
// PREVIOUS state
else if(data_prev) begin
m_axis_rx_tvalid <= #TCQ (trn_rsrc_rdy_prev || dsc_flag);
reg_tlast <= #TCQ trn_reof_prev;
reg_tkeep <= #TCQ tkeep_prev;
m_axis_rx_tuser <= #TCQ {is_eof_prev, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof_prev, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit_prev, // TUSER bits [8:2]
trn_rerrfwd_prev, // TUSER bit [1]
trn_recrc_err_prev}; // TUSER bit [0]
end
// CURRENT state
else begin
m_axis_rx_tvalid <= #TCQ (rsrc_rdy_filtered || dsc_flag);
reg_tlast <= #TCQ trn_reof;
reg_tkeep <= #TCQ tkeep;
m_axis_rx_tuser <= #TCQ {is_eof, // TUSER bits [21:17]
2'b00, // TUSER bits [16:15]
is_sof, // TUSER bits [14:10]
1'b0, // TUSER bit [9]
trn_rbar_hit, // TUSER bits [8:2]
trn_rerrfwd, // TUSER bit [1]
trn_recrc_err}; // TUSER bit [0]
end
end
// else HOLD state
end
end
// Hook up TLAST and tkeep depending on interface width
generate
// For 128-bit interface, don't pass TLAST and tkeep to user (is_eof and
// is_data passed to user instead). reg_tlast is still used internally.
if(C_DATA_WIDTH == 128) begin : tlast_tkeep_hookup_128
assign m_axis_rx_tlast = 1'b0;
assign m_axis_rx_tkeep = {KEEP_WIDTH{1'b1}};
end
// For 64/32-bit interface, pass TLAST to user.
else begin : tlast_tkeep_hookup_64_32
assign m_axis_rx_tlast = reg_tlast;
assign m_axis_rx_tkeep = reg_tkeep;
end
endgenerate
//----------------------------------------------------------------------------//
// Create tkeep //
// ------------ //
// Convert RREM to STRB. Here, we are converting the encoding method for the //
// location of the EOF from TRN flavor (rrem) to AXI (tkeep). //
// //
// NOTE: for each configuration, we need two values of tkeep, the current and //
// previous values. The need for these two values is described below. //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : rrem_to_tkeep_128
// TLAST and tkeep not used in 128-bit interface. is_sof and is_eof used
// instead.
assign tkeep = 16'h0000;
assign tkeep_prev = 16'h0000;
end
else if(C_DATA_WIDTH == 64) begin : rrem_to_tkeep_64
// 64-bit interface: contains 2 DWORDs per cycle, for a total of 8 bytes
// - tkeep has only two possible values here, 0xFF or 0x0F
assign tkeep = trn_rrem ? 8'hFF : 8'h0F;
assign tkeep_prev = trn_rrem_prev ? 8'hFF : 8'h0F;
end
else begin : rrem_to_tkeep_32
// 32-bit interface: contains 1 DWORD per cycle, for a total of 4 bytes
// - tkeep is always 0xF in this case, due to the nature of the PCIe block
assign tkeep = 4'hF;
assign tkeep_prev = 4'hF;
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_sof //
// ------------- //
// is_sof is a signal to the user indicating the location of SOF in TDATA . //
// Due to inherent 64-bit alignment of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11000 (sof @ byte 8) 128 //
// 5'b10000 (sof @ byte 0) 128, 64, 32 //
// 5'b00000 (sof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_sof_128
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
(trn_rsof && !trn_rrem[1]), // bit 3: sof @ byte 8?
3'b000}; // bit 2-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
(trn_rsof_prev && !trn_rrem_prev[1]), // bit 3
3'b000}; // bit 2-0
end
else begin : is_sof_64_32
assign is_sof = {(trn_rsof && !trn_rsrc_dsc), // bit 4: enable
4'b0000}; // bit 3-0: hardwired 0
assign is_sof_prev = {(trn_rsof_prev && !trn_rsrc_dsc_prev), // bit 4
4'b0000}; // bit 3-0
end
endgenerate
//----------------------------------------------------------------------------//
// Create is_eof //
// ------------- //
// is_eof is a signal to the user indicating the location of EOF in TDATA . //
// Due to DWORD granularity of packets from the block, the only //
// possible values are: //
// Value Valid data widths //
// 5'b11111 (eof @ byte 15) 128 //
// 5'b11011 (eof @ byte 11) 128 //
// 5'b10111 (eof @ byte 7) 128, 64 //
// 5'b10011 (eof @ byte 3)` 128, 64, 32 //
// 5'b00011 (eof not present) 128, 64, 32 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : is_eof_128
assign is_eof = {trn_reof, // bit 4: enable
trn_rrem, // bit 3-2: encoded eof loc rom block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
trn_rrem_prev, // bit 3-2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else if(C_DATA_WIDTH == 64) begin : is_eof_64
assign is_eof = {trn_reof, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
1'b0, // bit 3: hardwired 0
trn_rrem_prev, // bit 2: encoded eof loc from block
2'b11}; // bit 1-0: hardwired 1
end
else begin : is_eof_32
assign is_eof = {trn_reof, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
assign is_eof_prev = {trn_reof_prev, // bit 4: enable
4'b0011}; // bit 3-0: hardwired to byte 3
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_rdst_rdy //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
else begin
// If in a null packet, use null generated value
if(null_mux_sel && m_axis_rx_tready) begin
trn_rdst_rdy <= #TCQ null_rdst_rdy;
end
// If a discontinue needs to be serviced, throttle the block until we are
// ready to pad out the packet.
else if(dsc_flag) begin
trn_rdst_rdy <= #TCQ 1'b0;
end
// If in a packet, pass user back-pressure directly to block
else if(m_axis_rx_tvalid) begin
trn_rdst_rdy <= #TCQ m_axis_rx_tready;
end
// If idle, default to no back-pressure. We need to default to the
// "ready to accept data" state to make sure we catch the first
// clock of data of a new packet.
else begin
trn_rdst_rdy <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create null_mux_sel //
// null_mux_sel is the signal used to detect a discontinue situation and //
// mux in the null packet generated in rx_null_gen. Only mux in null data //
// when not at the beginningof a packet. SOF discontinues do not require //
// padding, as the whole packet is simply squashed instead. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
null_mux_sel <= #TCQ 1'b0;
end
else begin
// NULL packet done
if(null_mux_sel && null_rx_tlast && m_axis_rx_tready)
begin
null_mux_sel <= #TCQ 1'b0;
end
// Discontinue detected and we're in packet, so switch to NULL packet
else if(dsc_flag && !data_hold) begin
null_mux_sel <= #TCQ 1'b1;
end
end
end
//----------------------------------------------------------------------------//
// Create discontinue tracking signals //
//----------------------------------------------------------------------------//
// Create signal trn_in_packet, which is needed to validate trn_rsrc_dsc. We
// should ignore trn_rsrc_dsc when it's asserted out-of-packet.
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_rsof && !trn_reof && rsrc_rdy_filtered && trn_rdst_rdy)
begin
trn_in_packet <= #TCQ 1'b1;
end
else if(trn_rsrc_dsc) begin
trn_in_packet <= #TCQ 1'b0;
end
else if(trn_reof && !trn_rsof && trn_rsrc_rdy && trn_rdst_rdy) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
// Create dsc_flag, which identifies and stores mid-packet discontinues that
// require null packet padding. This signal is edge sensitive to trn_rsrc_dsc,
// to make sure we don't service the same dsc twice in the event that
// trn_rsrc_dsc stays asserted for longer than it takes to pad out the packet.
assign dsc_detect = trn_rsrc_dsc && !trn_rsrc_dsc_d && trn_in_packet &&
(!trn_rsof || trn_reof) && !(trn_rdst_rdy && trn_reof);
always @(posedge user_clk) begin
if(user_rst) begin
reg_dsc_detect <= #TCQ 1'b0;
trn_rsrc_dsc_d <= #TCQ 1'b0;
end
else begin
if(dsc_detect) begin
reg_dsc_detect <= #TCQ 1'b1;
end
else if(null_mux_sel) begin
reg_dsc_detect <= #TCQ 1'b0;
end
trn_rsrc_dsc_d <= #TCQ trn_rsrc_dsc;
end
end
assign dsc_flag = dsc_detect || reg_dsc_detect;
//----------------------------------------------------------------------------//
// Create np_counter (V6 128-bit only). This counter tells the V6 128-bit //
// interface core how many NP packets have left the RX pipeline. The V6 //
// 128-bit interface uses this count to perform rnp_ok modulation. //
//----------------------------------------------------------------------------//
generate
if(C_FAMILY == "V6" && C_DATA_WIDTH == 128) begin : np_cntr_to_128_enabled
reg [2:0] reg_np_counter;
// Look for NP packets beginning on lower (i.e. unaligned) start
wire mrd_lower = (!(|m_axis_rx_tdata[92:88]) && !m_axis_rx_tdata[94]);
wire mrd_lk_lower = (m_axis_rx_tdata[92:88] == 5'b00001);
wire io_rdwr_lower = (m_axis_rx_tdata[92:88] == 5'b00010);
wire cfg_rdwr_lower = (m_axis_rx_tdata[92:89] == 4'b0010);
wire atomic_lower = ((&m_axis_rx_tdata[91:90]) && m_axis_rx_tdata[94]);
wire np_pkt_lower = (mrd_lower ||
mrd_lk_lower ||
io_rdwr_lower ||
cfg_rdwr_lower ||
atomic_lower) && m_axis_rx_tuser[13];
// Look for NP packets beginning on upper (i.e. aligned) start
wire mrd_upper = (!(|m_axis_rx_tdata[28:24]) && !m_axis_rx_tdata[30]);
wire mrd_lk_upper = (m_axis_rx_tdata[28:24] == 5'b00001);
wire io_rdwr_upper = (m_axis_rx_tdata[28:24] == 5'b00010);
wire cfg_rdwr_upper = (m_axis_rx_tdata[28:25] == 4'b0010);
wire atomic_upper = ((&m_axis_rx_tdata[27:26]) && m_axis_rx_tdata[30]);
wire np_pkt_upper = (mrd_upper ||
mrd_lk_upper ||
io_rdwr_upper ||
cfg_rdwr_upper ||
atomic_upper) && !m_axis_rx_tuser[13];
wire pkt_accepted =
m_axis_rx_tuser[14] && m_axis_rx_tready && m_axis_rx_tvalid;
// Increment counter whenever an NP packet leaves the RX pipeline
always @(posedge user_clk) begin
if (user_rst) begin
reg_np_counter <= #TCQ 0;
end
else begin
if((np_pkt_lower || np_pkt_upper) && pkt_accepted)
begin
reg_np_counter <= #TCQ reg_np_counter + 3'h1;
end
end
end
assign np_counter = reg_np_counter;
end
else begin : np_cntr_to_128_disabled
assign np_counter = 3'h0;
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
`define SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21OI_BLACKBOX_V
|
// File: processor.v
// Generated by MyHDL 0.9dev
// Date: Mon Jan 27 10:01:23 2014
`timescale 1ns/10ps
module processor (
clk,
reset,
buttons,
leds,
rx,
tx,
memoryaddr,
memoryin,
memoryout,
romrden,
ramrden,
ramwren,
fifodata,
fifore,
fifowe,
fifoempty,
fifofull,
fifoq
);
// clk (Ibool) -- The clock
// reset (IReset) -- Reset Signal
// buttons (I4) -- 4 input buttons
// leds (O4) -- 4 output LEDS
// rx (Ibool) -- input from rs232
// tx (Obool) -- output from rs232
// memoryaddr (O16) -- memory addr
// memoryin (I32) -- memory read
// memoryout (O32) -- memory write
// romrden (Obool) -- rom-readenable
// ramrden (Obool) -- ram-readenable
// ramwren (Obool) -- ram-writeenable
// fifodata (O8) -- fifo data in
// fifore (Obool) -- enable reading from fifo
// fifowe (Obool) -- enable writing to fifo
// fifoempty (Ibool) -- indicates, that fifo is empty
// fifofull (Ibool) -- indicates, that the fifo is full
// fifoq (I8) -- fifo data out
//
// baudrate -- the baudrate for the rs232
// enCache -- enable cache or not
// interesting -- A list with interesting signals will be returned
input clk;
input reset;
input [3:0] buttons;
output [3:0] leds;
reg [3:0] leds;
input rx;
output tx;
reg tx;
output [15:0] memoryaddr;
reg [15:0] memoryaddr;
input [31:0] memoryin;
wire [31:0] memoryin;
output [31:0] memoryout;
reg [31:0] memoryout;
output romrden;
wire romrden;
output ramrden;
wire ramrden;
output ramwren;
wire ramwren;
output [7:0] fifodata;
reg [7:0] fifodata;
output fifore;
wire fifore;
output fifowe;
reg fifowe;
input fifoempty;
input fifofull;
input [7:0] fifoq;
wire [3:0] irSource;
reg enJump;
reg enCall;
reg [31:0] rgX;
reg [31:0] rgY;
reg bufOp2;
reg cIn;
reg bufClk;
reg bufRy;
wire [31:0] pcOut;
reg rstreadybit;
wire [31:0] bbus;
reg readybit;
reg enReg;
wire [23:0] irImm24;
reg nIn;
wire [3:0] irSource2;
reg bufAddr;
wire irSup;
reg bufRsr;
reg mmuBuf;
reg enPc;
reg addrymux1;
reg addrymux0;
wire [3:0] irAluop;
wire [4:0] irJumpOp;
reg enRst;
reg bufPC;
reg bufBut;
reg bufAddr14;
reg enAlu;
wire [6:0] irPrefix;
wire irOp1;
wire irOp2;
reg zIn;
reg bufAlu;
reg enSup;
wire nOut;
wire cOut;
wire [3:0] irDest;
reg enMmu;
wire vOut;
reg enIr;
wire zOut;
reg enLed;
reg pmux;
reg vIn;
reg jumpResult;
wire [15:0] irImm16;
reg Memory_csO;
reg Memory_csA;
reg [31:0] Memory_mmuOut;
reg Memory_enW;
reg Memory_enO;
wire [31:0] Memory_mmuTristate_o;
reg [7:0] Memory_Mmu_waitingtimer;
reg [1:0] Memory_Mmu_state;
reg [31:0] Memory_Mmu_in_data;
reg Memory_Mmu_with_data;
reg [31:0] IO_ioOut;
wire [31:0] IO_ioTristate_o;
reg [3:0] IO_io_ledBuffer;
reg [3:0] RS232_reader_bitCnt;
reg [0:0] RS232_reader_state;
reg [10:0] RS232_reader_clkCnt;
reg [7:0] RS232_reader_data;
reg [3:0] RS232_writer_bitCnt;
reg [0:0] RS232_writer_state;
reg [31:0] RS232_writer_clkCnt;
reg [7:0] RS232_writer_data;
wire [31:0] RS232_readerTristate_o;
wire [31:0] ClkBuf_clkOut;
reg [31:0] ClkBuf_clock_data;
wire [31:0] ClkBuf_clkTristate_o;
wire [31:0] AddrBuf_addrMuxOut;
wire [31:0] AddrBuf_addOut;
wire [31:0] AddrBuf_addrTristate_o;
wire [31:0] Op2Buf_op2muxOut;
wire [31:0] Op2Buf_op2tristate_o;
wire [31:0] Addr14Buf_addr14;
wire [31:0] Addr14Buf_plusminusMuxOut;
wire [31:0] Addr14Buf_addr14tristate_o;
wire [31:0] PC_pcTristate_o;
reg [31:0] PC_pc_data;
wire [31:0] ALU_BmuxOut;
reg [31:0] ALU_aluRes;
wire [31:0] ALU_aluTristate_o;
reg [3:0] RegisterBank_zMuxOut;
reg [3:0] RegisterBank_yMuxOut;
wire [31:0] RegisterBank_ryTristate_o;
wire StatusFlags_sUp;
reg [0:0] StatusFlags_V_data;
reg [0:0] StatusFlags_C_data;
reg [0:0] StatusFlags_N_data;
reg [0:0] StatusFlags_Z_data;
wire CPU_ffavail;
reg [3:0] CPU_Cpu_substate;
reg [4:0] CPU_Cpu_state;
wire [31:0] IR_ir2idecoder;
reg [31:0] IR_ir_data;
reg [31:0] RegisterBank_rb_reg_data [0:16-1];
assign bbus = RegisterBank_ryTristate_o;
assign bbus = ALU_aluTristate_o;
assign bbus = PC_pcTristate_o;
assign bbus = Addr14Buf_addr14tristate_o;
assign bbus = Op2Buf_op2tristate_o;
assign bbus = AddrBuf_addrTristate_o;
assign bbus = ClkBuf_clkTristate_o;
assign bbus = RS232_readerTristate_o;
assign bbus = IO_ioTristate_o;
assign bbus = Memory_mmuTristate_o;
function integer MYHDL31_calc;
input [4-1:0] opc;
input [32-1:0] first;
input [32-1:0] second;
input [1-1:0] c;
begin: MYHDL51_RETURN
case (opc)
'h0: begin
MYHDL31_calc = (first + second);
disable MYHDL51_RETURN;
end
'h1: begin
MYHDL31_calc = ((first + second) + c);
disable MYHDL51_RETURN;
end
'h4: begin
MYHDL31_calc = ($signed({1'b0, first}) - $signed({1'b0, second}));
disable MYHDL51_RETURN;
end
'h5: begin
MYHDL31_calc = (($signed({1'b0, first}) - $signed({1'b0, second})) - c);
disable MYHDL51_RETURN;
end
'h6: begin
MYHDL31_calc = ($signed({1'b0, second}) - $signed({1'b0, first}));
disable MYHDL51_RETURN;
end
'h7: begin
MYHDL31_calc = ((second + c) - first);
disable MYHDL51_RETURN;
end
'h2: begin
MYHDL31_calc = (first * second);
disable MYHDL51_RETURN;
end
'h3: begin
MYHDL31_calc = (first & (~second));
disable MYHDL51_RETURN;
end
'h8: begin
MYHDL31_calc = (first & second);
disable MYHDL51_RETURN;
end
'h9: begin
MYHDL31_calc = (first | second);
disable MYHDL51_RETURN;
end
'ha: begin
MYHDL31_calc = (first ^ second);
disable MYHDL51_RETURN;
end
'hb: begin
MYHDL31_calc = (first | (~second));
disable MYHDL51_RETURN;
end
'hc: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = (first << second);
disable MYHDL51_RETURN;
end
'hd: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = $signed($signed(first) >>> second);
disable MYHDL51_RETURN;
end
'he: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = (first >>> second);
disable MYHDL51_RETURN;
end
default: begin
if ((second < 32) !== 1) begin
$display("*** AssertionError ***");
end
MYHDL31_calc = (($signed({1'b0, first}) << (32 - $signed({1'b0, second}))) | (first >>> second));
disable MYHDL51_RETURN;
end
endcase
end
endfunction
assign CPU_ffavail = (!fifoempty);
assign fifore = bufRsr;
always @(posedge clk, negedge reset) begin: PROCESSOR_CPU_CPU_LOGIC
if (reset == 0) begin
enJump <= 0;
bufAddr14 <= 0;
CPU_Cpu_substate <= 0;
enCall <= 0;
enPc <= 0;
enReg <= 0;
bufAddr <= 0;
enMmu <= 0;
bufRy <= 0;
bufBut <= 0;
bufClk <= 0;
CPU_Cpu_state <= 5'b00001;
mmuBuf <= 0;
addrymux1 <= 0;
addrymux0 <= 0;
enAlu <= 0;
bufPC <= 0;
bufOp2 <= 0;
pmux <= 0;
bufAlu <= 0;
enIr <= 0;
enRst <= 0;
enLed <= 0;
enSup <= 0;
bufRsr <= 0;
end
else begin
addrymux1 <= 1'b0;
addrymux0 <= 1'b0;
pmux <= 1'b0;
bufAddr <= 1'b0;
bufOp2 <= 1'b0;
bufAddr14 <= 1'b0;
bufRy <= 1'b0;
bufAlu <= 1'b0;
bufPC <= 1'b0;
bufClk <= 1'b0;
bufBut <= 1'b0;
bufRsr <= 1'b0;
enAlu <= 1'b0;
enIr <= 1'b0;
enPc <= 1'b0;
enReg <= 1'b0;
enSup <= 1'b0;
enJump <= 1'b0;
enCall <= 1'b0;
enLed <= 1'b0;
enRst <= 1'b0;
enMmu <= 1'b0;
mmuBuf <= 1'b0;
case (CPU_Cpu_state)
5'b00000: begin
if ((irPrefix[7-1:5] == 0)) begin
CPU_Cpu_state <= 5'b00011;
end
else if ((irPrefix[7-1:5] == 1)) begin
CPU_Cpu_state <= 5'b00100;
end
else if ((irPrefix[7-1:4] == 4)) begin
CPU_Cpu_state <= 5'b00101;
end
else if ((irPrefix[7-1:4] == 5)) begin
CPU_Cpu_state <= 5'b00110;
end
else if ((irPrefix[7-1:4] == 6)) begin
CPU_Cpu_state <= 5'b00111;
end
else if ((irPrefix[7-1:2] == 28)) begin
CPU_Cpu_state <= 5'b01000;
end
else if ((irPrefix[7-1:2] == 29)) begin
CPU_Cpu_state <= 5'b01001;
end
else if ((irPrefix[7-1:1] == 60)) begin
CPU_Cpu_state <= 5'b01010;
end
else if ((irPrefix[7-1:1] == 61)) begin
CPU_Cpu_state <= 5'b01011;
end
else if ((irPrefix[7-1:0] == 124)) begin
CPU_Cpu_state <= 5'b01101;
end
else if ((irPrefix[7-1:0] == 125)) begin
CPU_Cpu_state <= 5'b01100;
end
else if ((irPrefix[7-1:0] == 126)) begin
CPU_Cpu_state <= 5'b01110;
end
else if ((irPrefix[7-1:0] == 127)) begin
CPU_Cpu_state <= 5'b01111;
end
else begin
CPU_Cpu_state <= 5'b10001;
end
end
5'b00001: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
if ((CPU_Cpu_substate == 0)) begin
enMmu <= 1'b1;
bufPC <= 1'b1;
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((CPU_Cpu_substate == 1)) begin
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((!readybit)) begin
// pass
end
else if (readybit) begin
mmuBuf <= 1'b1;
enIr <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00010;
end
end
end
5'b00010: begin
enPc <= 1'b1;
CPU_Cpu_state <= 5'b00000;
end
5'b00011: begin
enAlu <= 1'b1;
bufAlu <= 1'b1;
enReg <= 1'b1;
enSup <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b00100: begin
enJump <= 1'b1;
enPc <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b00101: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
if ((CPU_Cpu_substate == 0)) begin
enMmu <= 1'b1;
bufAddr <= 1'b1;
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((CPU_Cpu_substate == 1)) begin
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if ((!readybit)) begin
// pass
end
else if (readybit) begin
mmuBuf <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
end
end
5'b00110: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
case (CPU_Cpu_substate)
'h0: begin
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
bufRy <= 1'b1;
enMmu <= 1'b1;
end
'h1: begin
CPU_Cpu_substate <= 1;
bufOp2 <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
endcase
end
end
5'b00111: begin
enReg <= 1'b1;
bufAddr <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01000: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
case (CPU_Cpu_substate)
'h0: begin
addrymux1 <= 1'b1;
pmux <= 1'b0;
enReg <= 1'b1;
bufAddr14 <= 1'b1;
CPU_Cpu_substate <= 1;
end
'h1: begin
addrymux1 <= 1'b1;
bufRy <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 2;
end
'h2: begin
bufOp2 <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
endcase
end
end
5'b01001: begin
if (((!readybit) && (CPU_Cpu_substate == 0))) begin
// pass
end
else begin
if ((CPU_Cpu_substate == 0)) begin
addrymux1 <= 1'b1;
bufRy <= 1'b1;
enMmu <= 1'b1;
CPU_Cpu_substate <= 1;
end
else if ((CPU_Cpu_substate == 1)) begin
addrymux1 <= 1'b1;
pmux <= 1'b1;
enReg <= 1'b1;
bufAddr14 <= 1'b1;
CPU_Cpu_substate <= 2;
end
else if ((!readybit)) begin
// pass
end
else if (readybit) begin
mmuBuf <= 1'b1;
addrymux1 <= 1'b1;
addrymux0 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
end
end
5'b01010: begin
case (CPU_Cpu_substate)
'h0: begin
bufPC <= 1'b1;
addrymux0 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_substate <= 1;
end
'h1: begin
enCall <= 1'b1;
enPc <= 1'b1;
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
endcase
end
5'b01011: begin
bufClk <= 1'b1;
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01100: begin
enLed <= 1'b1;
bufOp2 <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01101: begin
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
enReg <= 1'b1;
bufBut <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
5'b01110: begin
if (CPU_ffavail) begin
bufRsr <= 1'b1;
addrymux0 <= 1'b1;
addrymux1 <= 1'b1;
enReg <= 1'b1;
CPU_Cpu_state <= 5'b00001;
end
end
5'b01111: begin
if ((CPU_Cpu_substate <= 2)) begin
enRst <= 1'b1;
bufOp2 <= 1'b1;
CPU_Cpu_substate <= (CPU_Cpu_substate + 1);
end
else if (rstreadybit) begin
CPU_Cpu_substate <= 0;
CPU_Cpu_state <= 5'b00001;
end
end
5'b10000: begin
CPU_Cpu_state <= 5'b10000;
end
default: begin
if (1'b0 !== 1) begin
$display("*** AssertionError ***");
end
end
endcase
end
end
assign Addr14Buf_plusminusMuxOut = pmux ? 4 : (-4);
assign Addr14Buf_addr14 = ($signed(Addr14Buf_plusminusMuxOut) + $signed(rgY));
assign Addr14Buf_addr14tristate_o = bufAddr14 ? Addr14Buf_addr14 : 'bz;
assign ClkBuf_clkTristate_o = bufClk ? ClkBuf_clkOut : 'bz;
always @(posedge clk, negedge reset) begin: PROCESSOR_CLKBUF_CLOCK_WRITE
if (reset == 0) begin
ClkBuf_clock_data <= 0;
end
else begin
ClkBuf_clock_data <= 1 ? (ClkBuf_clock_data + 1) : ClkBuf_clock_data;
end
end
assign ClkBuf_clkOut = ClkBuf_clock_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_PC_PC_WRITE
if (reset == 0) begin
PC_pc_data <= 0;
end
else begin
if (enPc) begin
if ((!(enCall || enJump))) begin
PC_pc_data <= (PC_pc_data + 4);
end
else if ((enCall || (enJump && jumpResult))) begin
PC_pc_data <= irOp1 ? ($signed({1'b0, PC_pc_data}) + $signed(irImm24)) : rgY;
end
end
end
end
assign pcOut = PC_pc_data;
assign PC_pcTristate_o = bufPC ? pcOut : 'bz;
assign AddrBuf_addOut = ($signed(pcOut) + $signed(irImm24));
assign AddrBuf_addrMuxOut = irOp1 ? AddrBuf_addOut : rgY;
assign AddrBuf_addrTristate_o = bufAddr ? AddrBuf_addrMuxOut : 'bz;
assign RS232_readerTristate_o = bufRsr ? fifoq : 'bz;
always @(posedge clk, negedge reset) begin: PROCESSOR_RS232_READER_LOGIC
if (reset == 0) begin
fifowe <= 0;
fifodata <= 0;
RS232_reader_bitCnt <= 0;
RS232_reader_state <= 1'b0;
RS232_reader_clkCnt <= 0;
RS232_reader_data <= 0;
end
else begin
if ((RS232_reader_clkCnt > 0)) begin
RS232_reader_clkCnt <= (RS232_reader_clkCnt - 1);
end
else begin
case (RS232_reader_state)
1'b0: begin
if ((!rx)) begin
RS232_reader_data <= 0;
RS232_reader_bitCnt <= 8;
RS232_reader_clkCnt <= 1301;
fifowe <= 1'b0;
RS232_reader_state <= 1'b1;
end
end
1'b1: begin
RS232_reader_clkCnt <= 867;
if ((RS232_reader_bitCnt > 0)) begin
RS232_reader_data <= ($signed({1'b0, RS232_reader_data}) | ($signed({1'b0, rx}) << (8 - $signed({1'b0, RS232_reader_bitCnt}))));
RS232_reader_bitCnt <= (RS232_reader_bitCnt - 1);
end
else begin
fifodata <= RS232_reader_data;
fifowe <= 1'b1;
RS232_reader_state <= 1'b0;
end
end
endcase
end
end
end
always @(posedge clk, negedge reset) begin: PROCESSOR_RS232_WRITER_LOGIC
if (reset == 0) begin
tx <= 1;
RS232_writer_bitCnt <= 0;
RS232_writer_state <= 1'b0;
RS232_writer_clkCnt <= 0;
RS232_writer_data <= 0;
rstreadybit <= 1;
end
else begin
if ((RS232_writer_clkCnt > 0)) begin
RS232_writer_clkCnt <= (RS232_writer_clkCnt - 1);
end
else begin
tx <= 1'b1;
case (RS232_writer_state)
1'b0: begin
if (enRst) begin
RS232_writer_data <= bbus[8-1:0];
RS232_writer_clkCnt <= 867;
rstreadybit <= 1'b0;
RS232_writer_bitCnt <= 8;
tx <= 1'b0;
RS232_writer_state <= 1'b1;
end
else begin
rstreadybit <= 1'b1;
end
end
1'b1: begin
if ((RS232_writer_bitCnt > 0)) begin
tx <= RS232_writer_data[(8 - $signed({1'b0, RS232_writer_bitCnt}))];
RS232_writer_bitCnt <= (RS232_writer_bitCnt - 1);
RS232_writer_clkCnt <= 867;
end
else begin
tx <= 1'b1;
RS232_writer_clkCnt <= 1301;
RS232_writer_state <= 1'b0;
end
end
endcase
end
end
end
always @(vOut, zOut, irJumpOp, cOut, nOut) begin: PROCESSOR_JUMPUNIT_JU_LOGIC
reg result;
result = 1'b0;
if (irJumpOp[4]) begin
result = (result || (zOut != 0));
end
if (irJumpOp[3]) begin
result = (result || (nOut != 0));
end
if (irJumpOp[2]) begin
result = (result || (cOut != 0));
end
if (irJumpOp[1]) begin
result = (result || (vOut != 0));
end
if (irJumpOp[0]) begin
result = (!result);
end
jumpResult = result;
end
assign StatusFlags_sUp = (irSup & enSup);
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_Z_WRITE
if (reset == 0) begin
StatusFlags_Z_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_Z_data <= zIn;
end
end
end
assign zOut = StatusFlags_Z_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_N_WRITE
if (reset == 0) begin
StatusFlags_N_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_N_data <= nIn;
end
end
end
assign nOut = StatusFlags_N_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_C_WRITE
if (reset == 0) begin
StatusFlags_C_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_C_data <= cIn;
end
end
end
assign cOut = StatusFlags_C_data;
always @(posedge clk, negedge reset) begin: PROCESSOR_STATUSFLAGS_V_WRITE
if (reset == 0) begin
StatusFlags_V_data <= 0;
end
else begin
if (StatusFlags_sUp) begin
StatusFlags_V_data <= vIn;
end
end
end
assign vOut = StatusFlags_V_data;
assign ALU_BmuxOut = irOp2 ? irImm16 : rgY;
always @(rgX, ALU_BmuxOut, enAlu, cOut, irAluop) begin: PROCESSOR_ALU_ALU_LOGIC
reg [32-1:0] alu_res;
integer result;
zIn = 1'b0;
nIn = 1'b0;
cIn = 1'b0;
vIn = 1'b0;
ALU_aluRes = 0;
if (enAlu) begin
result = MYHDL31_calc(irAluop, rgX, ALU_BmuxOut, cOut);
alu_res = result[32-1:0];
zIn = (alu_res == 0);
nIn = alu_res[(32 - 1)];
cIn = ((result & 34'h100000000) != 0);
vIn = ((rgX[(32 - 1)] == ALU_BmuxOut[(32 - 1)]) && (rgX[(32 - 1)] == (!alu_res[(32 - 1)])));
ALU_aluRes = alu_res;
end
end
assign ALU_aluTristate_o = bufAlu ? ALU_aluRes : 'bz;
assign romrden = (Memory_enO & Memory_csO);
assign ramrden = (Memory_enO & Memory_csA);
assign ramwren = (Memory_enW & Memory_csA);
always @(posedge clk, negedge reset) begin: PROCESSOR_MEMORY_MMU_WRITE
if (reset == 0) begin
memoryaddr <= 0;
Memory_enW <= 0;
Memory_enO <= 0;
Memory_Mmu_waitingtimer <= 0;
Memory_Mmu_state <= 2'b00;
memoryout <= 0;
Memory_csA <= 0;
readybit <= 1;
Memory_csO <= 0;
Memory_Mmu_with_data <= 0;
Memory_Mmu_in_data <= 0;
end
else begin
if (enMmu) begin
case (Memory_Mmu_state)
2'b00: begin
readybit <= 1'b0;
memoryaddr <= bbus[16-1:0];
Memory_csA <= bbus[31];
Memory_csO <= (!bbus[31]);
Memory_Mmu_state <= 2'b01;
end
2'b01: begin
if ((Memory_csA != 0) !== 1) begin
$display("*** AssertionError ***");
end
Memory_csA <= 1'b1;
Memory_csO <= 1'b0;
Memory_Mmu_with_data <= 1'b1;
Memory_Mmu_in_data <= bbus;
end
default: begin
$write("Something went wrong! (Did you read the protocoll?)");
$write("\n");
end
endcase
end
else if ((Memory_Mmu_state == 2'b01)) begin
if ((!(Memory_enO && Memory_enW)) !== 1) begin
$display("*** AssertionError ***");
end
if ((!Memory_Mmu_with_data)) begin
Memory_enO <= 1'b1;
if ((Memory_Mmu_waitingtimer == 2)) begin
Memory_Mmu_in_data <= memoryin;
Memory_Mmu_state <= 2'b10;
end
end
else begin
Memory_enW <= 1'b1;
memoryout <= Memory_Mmu_in_data;
if ((Memory_Mmu_waitingtimer == 2)) begin
Memory_Mmu_state <= 2'b10;
end
end
Memory_Mmu_waitingtimer <= (Memory_Mmu_waitingtimer + 1);
end
else if ((Memory_Mmu_state == 2'b10)) begin
Memory_Mmu_waitingtimer <= 0;
Memory_Mmu_with_data <= 1'b0;
Memory_enO <= 1'b0;
Memory_enW <= 1'b0;
readybit <= 1'b1;
Memory_Mmu_state <= 2'b00;
end
end
end
always @(posedge readybit) begin: PROCESSOR_MEMORY_MMU_READ
Memory_mmuOut <= Memory_Mmu_in_data;
end
assign Memory_mmuTristate_o = mmuBuf ? Memory_mmuOut : 'bz;
always @(posedge clk, negedge reset) begin: PROCESSOR_IR_IR_WRITE
if (reset == 0) begin
IR_ir_data <= 0;
end
else begin
if (enIr) begin
IR_ir_data <= bbus;
end
end
end
assign IR_ir2idecoder = IR_ir_data;
assign irAluop = IR_ir2idecoder[25-1:21];
assign irDest = IR_ir2idecoder[29-1:25];
assign irSource = IR_ir2idecoder[21-1:17];
assign irOp1 = IR_ir2idecoder[24];
assign irOp2 = IR_ir2idecoder[16];
assign irSource2 = IR_ir2idecoder[4-1:0];
assign irImm24 = IR_ir2idecoder[24-1:0];
assign irImm16 = IR_ir2idecoder[16-1:0];
assign irSup = IR_ir2idecoder[29];
assign irPrefix = IR_ir2idecoder[32-1:25];
assign irJumpOp = IR_ir2idecoder[30-1:25];
always @(posedge clk, negedge reset) begin: PROCESSOR_IO_IO_LOGIC
if (reset == 0) begin
IO_io_ledBuffer <= 0;
leds <= 15;
IO_ioOut <= 0;
end
else begin
if (enLed) begin
IO_io_ledBuffer <= bbus[4-1:0];
end
IO_ioOut <= (~buttons);
leds <= (~IO_io_ledBuffer);
end
end
assign IO_ioTristate_o = bufBut ? IO_ioOut : 'bz;
always @(addrymux1, addrymux0, irDest, irSource2) begin: PROCESSOR_REGISTERBANK_YMUX_LOGIC
if ((!addrymux1)) begin
if ((!addrymux0)) begin
RegisterBank_yMuxOut = irSource2;
end
else begin
RegisterBank_yMuxOut = 15;
end
end
else begin
if ((!addrymux0)) begin
RegisterBank_yMuxOut = 14;
end
else begin
RegisterBank_yMuxOut = irDest;
end
end
end
always @(addrymux1, addrymux0, irSource2, irDest) begin: PROCESSOR_REGISTERBANK_ZMUX_LOGIC
if ((!addrymux1)) begin
if ((!addrymux0)) begin
RegisterBank_zMuxOut = irDest;
end
else begin
RegisterBank_zMuxOut = 15;
end
end
else begin
if ((!addrymux0)) begin
RegisterBank_zMuxOut = 14;
end
else begin
RegisterBank_zMuxOut = irSource2;
end
end
end
always @(posedge clk, negedge reset) begin: PROCESSOR_REGISTERBANK_RB_WRITE
if (reset == 0) begin
RegisterBank_rb_reg_data[0] <= 0;
RegisterBank_rb_reg_data[1] <= 0;
RegisterBank_rb_reg_data[2] <= 0;
RegisterBank_rb_reg_data[3] <= 0;
RegisterBank_rb_reg_data[4] <= 0;
RegisterBank_rb_reg_data[5] <= 0;
RegisterBank_rb_reg_data[6] <= 0;
RegisterBank_rb_reg_data[7] <= 0;
RegisterBank_rb_reg_data[8] <= 0;
RegisterBank_rb_reg_data[9] <= 0;
RegisterBank_rb_reg_data[10] <= 0;
RegisterBank_rb_reg_data[11] <= 0;
RegisterBank_rb_reg_data[12] <= 0;
RegisterBank_rb_reg_data[13] <= 0;
RegisterBank_rb_reg_data[14] <= 0;
RegisterBank_rb_reg_data[15] <= 0;
end
else begin
if ((irSource < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_yMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_zMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((enReg && (!(1 && (RegisterBank_zMuxOut == 0))))) begin
RegisterBank_rb_reg_data[RegisterBank_zMuxOut] <= bbus[32-1:0];
end
end
end
always @(RegisterBank_rb_reg_data[0], RegisterBank_rb_reg_data[1], RegisterBank_rb_reg_data[2], RegisterBank_rb_reg_data[3], RegisterBank_rb_reg_data[4], RegisterBank_rb_reg_data[5], RegisterBank_rb_reg_data[6], RegisterBank_rb_reg_data[7], RegisterBank_rb_reg_data[8], RegisterBank_rb_reg_data[9], RegisterBank_rb_reg_data[10], RegisterBank_rb_reg_data[11], RegisterBank_rb_reg_data[12], RegisterBank_rb_reg_data[13], RegisterBank_rb_reg_data[14], RegisterBank_rb_reg_data[15], irSource, RegisterBank_yMuxOut) begin: PROCESSOR_REGISTERBANK_RB_READ
if ((irSource < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_yMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
if ((RegisterBank_yMuxOut < 16) !== 1) begin
$display("*** AssertionError ***");
end
rgX = RegisterBank_rb_reg_data[irSource];
rgY = RegisterBank_rb_reg_data[RegisterBank_yMuxOut];
end
assign RegisterBank_ryTristate_o = bufRy ? rgY : 'bz;
assign Op2Buf_op2muxOut = irOp1 ? irImm24 : rgY;
assign Op2Buf_op2tristate_o = bufOp2 ? Op2Buf_op2muxOut : 'bz;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pci_exp_usrapp_rx.v
// Version : 1.8
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
`define EXPECT_FINISH_CHECK board.RP.tx_usrapp.expect_finish_check
module pci_exp_usrapp_rx #(
parameter C_DATA_WIDTH = 64,
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1
)
(
trn_rdst_rdy_n,
trn_rnp_ok_n,
trn_rd,
trn_rrem_n,
trn_rsof_n,
trn_reof_n,
trn_rsrc_rdy_n,
trn_rsrc_dsc_n,
trn_rerrfwd_n,
trn_rbar_hit_n,
trn_clk,
trn_reset_n,
trn_lnk_up_n
);
output trn_rdst_rdy_n;
output trn_rnp_ok_n;
input [C_DATA_WIDTH-1:0] trn_rd;
input [REM_WIDTH-1:0] trn_rrem_n;
input trn_rsof_n;
input trn_reof_n;
input trn_rsrc_rdy_n;
input trn_rsrc_dsc_n;
input trn_rerrfwd_n;
input [6 : 0] trn_rbar_hit_n;
input trn_clk;
input trn_reset_n;
input trn_lnk_up_n;
parameter Tcq = 1;
/* Output variables */
reg trn_rdst_rdy_n, next_trn_rdst_rdy_n;
reg trn_rnp_ok_n, next_trn_rnp_ok_n;
/* Local variables */
reg [4:0] trn_rx_state, next_trn_rx_state;
reg trn_rx_in_frame, next_trn_rx_in_frame;
reg trn_rx_in_channel, next_trn_rx_in_channel;
reg [31:0] next_trn_rx_timeout;
/* State variables */
`define TRN_RX_RESET 5'b00001
`define TRN_RX_DOWN 5'b00010
`define TRN_RX_IDLE 5'b00100
`define TRN_RX_ACTIVE 5'b01000
`define TRN_RX_SRC_DSC 5'b10000
/* Transaction Receive User Interface State Machine */
generate
if (C_DATA_WIDTH == 64) begin : trn_rx_sm_64
always @(posedge trn_clk or negedge trn_reset_n) begin
if (trn_reset_n == 1'b0) begin
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
end else begin
case (trn_rx_state)
`TRN_RX_RESET : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
end
`TRN_RX_DOWN : begin
if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
`TRN_RX_IDLE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
if ( (trn_rsof_n == 1'b0) &&
(trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
end
`TRN_RX_ACTIVE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_reof_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_reof_n == 1'b0) &&
(trn_rsrc_dsc_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA(1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
end
`TRN_RX_SRC_DSC : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
endcase
end
end
end
else if (C_DATA_WIDTH == 128) begin : trn_rx_sm_128
always @(posedge trn_clk or negedge trn_reset_n) begin
if (trn_reset_n == 1'b0) begin
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
end else begin
case (trn_rx_state)
`TRN_RX_RESET : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
end
`TRN_RX_DOWN : begin
if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
`TRN_RX_IDLE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
// single TLP in a Data Beat Case
if ( (trn_rsof_n == 1'b0) &&
(trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA_128(~trn_rsof_n, ~trn_reof_n, `RX_LOG, trn_rd, trn_rrem_n);
if ( (trn_rsof_n == 1'b0) && (trn_reof_n == 1'b0)) begin
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
end
`TRN_RX_ACTIVE : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_rdst_rdy_n == 1'b0) ) begin
case ({trn_rsof_n, trn_reof_n})
// Data Stream - both sof & eof de-asserted
2'b11 : begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
// EOF scenario. Not a straddle case
2'b10 : begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
2'b00 : begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
board.RP.com_usrapp.TSK_READ_DATA_128(1, 0, `RX_LOG, trn_rd, trn_rrem_n);
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
//2'b01 is not a valid option as the TRN_RX_ACTIVE case is only entered when we have seen an SOF but not an EOF, in the TRN_RX_IDLE state
endcase
end else if ( (trn_rsrc_rdy_n == 1'b0) &&
(trn_reof_n == 1'b0) &&
(trn_rsrc_dsc_n == 1'b0) ) begin
board.RP.com_usrapp.TSK_READ_DATA_128(0, 1, `RX_LOG, trn_rd, trn_rrem_n);
board.RP.com_usrapp.TSK_PARSE_FRAME(`RX_LOG);
trn_rx_state <= #(Tcq) `TRN_RX_SRC_DSC;
end else begin
trn_rx_state <= #(Tcq) `TRN_RX_ACTIVE;
end
end
`TRN_RX_SRC_DSC : begin
if (trn_reset_n == 1'b0)
trn_rx_state <= #(Tcq) `TRN_RX_RESET;
else if (trn_lnk_up_n == 1'b1)
trn_rx_state <= #(Tcq) `TRN_RX_DOWN;
else begin
trn_rx_state <= #(Tcq) `TRN_RX_IDLE;
end
end
endcase
end
end
end
endgenerate
reg [1:0] trn_rdst_rdy_toggle_count;
reg [8:0] trn_rnp_ok_toggle_count;
always @(posedge trn_clk or negedge trn_reset_n) begin
if (trn_reset_n == 1'b0) begin
trn_rnp_ok_n <= #(Tcq) 1'b0;
trn_rdst_rdy_n <= #(Tcq) 1'b0;
trn_rdst_rdy_toggle_count <= #(Tcq) $random;
trn_rnp_ok_toggle_count <= #(Tcq) $random;
end else begin
if (trn_rnp_ok_toggle_count == 0) begin
trn_rnp_ok_n <= #(Tcq) !trn_rnp_ok_n;
trn_rnp_ok_toggle_count <= #(Tcq) $random;
end else begin
//trn_rnp_ok_toggle_count <= #(Tcq) trn_rnp_ok_toggle_count - 1;
end
if (trn_rdst_rdy_toggle_count == 0) begin
//trn_rdst_rdy_n <= #(Tcq) !trn_rdst_rdy_n;
trn_rdst_rdy_toggle_count <= #(Tcq) $random;
end else begin
//trn_rdst_rdy_toggle_count <= trn_rdst_rdy_toggle_count - 1;
end
end
end
reg [31:0] sim_timeout;
initial
begin
sim_timeout = `TRN_RX_TIMEOUT;
end
/* Transaction Receive Timeout */
always @(trn_clk or trn_rsof_n or trn_rsrc_rdy_n) begin
if (next_trn_rx_timeout == 0) begin
if(!`EXPECT_FINISH_CHECK)
$display("[%t] : TEST FAILED --- Haven't Received All Expected TLPs", $realtime);
$finish(2);
end
if ((trn_rsof_n == 1'b0) && (trn_rsrc_rdy_n == 1'b0)) begin
next_trn_rx_timeout = sim_timeout;
end else begin
if (trn_lnk_up_n == 1'b0)
next_trn_rx_timeout = next_trn_rx_timeout - 1'b1;
end
end
endmodule // pci_exp_usrapp_rx
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9643 (
// adc interface (clk, data, over-range)
adc_clk_in_p,
adc_clk_in_n,
adc_data_in_p,
adc_data_in_n,
adc_or_in_p,
adc_or_in_n,
// delay interface
delay_clk,
// dma interface
adc_clk,
adc_valid_0,
adc_enable_0,
adc_data_0,
adc_valid_1,
adc_enable_1,
adc_data_1,
adc_dovf,
adc_dunf,
up_adc_gpio_in,
up_adc_gpio_out,
adc_rst,
// axi interface
s_axi_aclk,
s_axi_aresetn,
s_axi_awvalid,
s_axi_awaddr,
s_axi_awready,
s_axi_wvalid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wready,
s_axi_bvalid,
s_axi_bresp,
s_axi_bready,
s_axi_arvalid,
s_axi_araddr,
s_axi_arready,
s_axi_rvalid,
s_axi_rresp,
s_axi_rdata,
s_axi_rready);
// parameters
parameter PCORE_ID = 0;
parameter PCORE_DEVICE_TYPE = 0;
parameter PCORE_ADC_DP_DISABLE = 0;
parameter PCORE_IODELAY_GROUP = "adc_if_delay_group";
// adc interface (clk, data, over-range)
input adc_clk_in_p;
input adc_clk_in_n;
input [13:0] adc_data_in_p;
input [13:0] adc_data_in_n;
input adc_or_in_p;
input adc_or_in_n;
// delay interface
input delay_clk;
// dma interface
output adc_clk;
output adc_valid_0;
output adc_enable_0;
output [15:0] adc_data_0;
output adc_valid_1;
output adc_enable_1;
output [15:0] adc_data_1;
input adc_dovf;
input adc_dunf;
input [31:0] up_adc_gpio_in;
output [31:0] up_adc_gpio_out;
output adc_rst;
// axi interface
input s_axi_aclk;
input s_axi_aresetn;
input s_axi_awvalid;
input [31:0] s_axi_awaddr;
output s_axi_awready;
input s_axi_wvalid;
input [31:0] s_axi_wdata;
input [ 3:0] s_axi_wstrb;
output s_axi_wready;
output s_axi_bvalid;
output [ 1:0] s_axi_bresp;
input s_axi_bready;
input s_axi_arvalid;
input [31:0] s_axi_araddr;
output s_axi_arready;
output s_axi_rvalid;
output [ 1:0] s_axi_rresp;
output [31:0] s_axi_rdata;
input s_axi_rready;
// internal registers
reg up_status_pn_err = 'd0;
reg up_status_pn_oos = 'd0;
reg up_status_or = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
// internal clocks & resets
wire adc_rst;
wire up_rstn;
wire up_clk;
wire delay_rst;
// internal signals
wire [13:0] adc_data_a_s;
wire [13:0] adc_data_b_s;
wire adc_or_a_s;
wire adc_or_b_s;
wire [15:0] adc_dcfilter_data_a_s;
wire [15:0] adc_dcfilter_data_b_s;
wire [15:0] adc_channel_data_a_s;
wire [15:0] adc_channel_data_b_s;
wire [ 1:0] up_status_pn_err_s;
wire [ 1:0] up_status_pn_oos_s;
wire [ 1:0] up_status_or_s;
wire adc_ddr_edgesel_s;
wire adc_pin_mode_s;
wire adc_status_s;
wire [14:0] up_dld_s;
wire [74:0] up_dwdata_s;
wire [74:0] up_drdata_s;
wire delay_locked_s;
wire [31:0] up_rdata_s[0:3];
wire up_rack_s[0:3];
wire up_wack_s[0:3];
wire up_wreq_s;
wire [13:0] up_waddr_s;
wire [31:0] up_wdata_s;
wire up_rreq_s;
wire [13:0] up_raddr_s;
// signal name changes
assign up_clk = s_axi_aclk;
assign up_rstn = s_axi_aresetn;
// dma interface
assign adc_valid_0 = 1'b1;
assign adc_valid_1 = 1'b1;
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_status_pn_err <= 'd0;
up_status_pn_oos <= 'd0;
up_status_or <= 'd0;
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_status_pn_err <= up_status_pn_err_s[0] | up_status_pn_err_s[1];
up_status_pn_oos <= up_status_pn_oos_s[0] | up_status_pn_oos_s[1];
up_status_or <= up_status_or_s[0] | up_status_or_s[1];
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3];
end
end
// channel
axi_ad9643_channel #(
.IQSEL(0),
.CHID(0),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_0 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_a_s),
.adc_or (adc_or_a_s),
.adc_dcfilter_data_out (adc_dcfilter_data_a_s),
.adc_dcfilter_data_in (adc_dcfilter_data_b_s),
.adc_iqcor_data (adc_data_0),
.adc_enable (adc_enable_0),
.up_adc_pn_err (up_status_pn_err_s[0]),
.up_adc_pn_oos (up_status_pn_oos_s[0]),
.up_adc_or (up_status_or_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[0]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[0]),
.up_rack (up_rack_s[0]));
// channel
axi_ad9643_channel #(
.IQSEL(1),
.CHID(1),
.DP_DISABLE (PCORE_ADC_DP_DISABLE))
i_channel_1 (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_data (adc_data_b_s),
.adc_or (adc_or_b_s),
.adc_dcfilter_data_out (adc_dcfilter_data_b_s),
.adc_dcfilter_data_in (adc_dcfilter_data_a_s),
.adc_iqcor_data (adc_data_1),
.adc_enable (adc_enable_1),
.up_adc_pn_err (up_status_pn_err_s[1]),
.up_adc_pn_oos (up_status_pn_oos_s[1]),
.up_adc_or (up_status_or_s[1]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[1]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[1]),
.up_rack (up_rack_s[1]));
// main (device interface)
axi_ad9643_if #(
.PCORE_BUFTYPE (PCORE_DEVICE_TYPE),
.PCORE_IODELAY_GROUP (PCORE_IODELAY_GROUP))
i_if (
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_or_in_p (adc_or_in_p),
.adc_or_in_n (adc_or_in_n),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a_s),
.adc_data_b (adc_data_b_s),
.adc_or_a (adc_or_a_s),
.adc_or_b (adc_or_b_s),
.adc_status (adc_status_s),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.up_clk (up_clk),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s));
// common processor control
up_adc_common #(.PCORE_ID(PCORE_ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (adc_ddr_edgesel_s),
.adc_pin_mode (adc_pin_mode_s),
.adc_status (adc_status_s),
.adc_sync_status (1'd0),
.adc_status_ovf (adc_dovf),
.adc_status_unf (adc_dunf),
.adc_clk_ratio (32'd1),
.adc_start_code (),
.adc_sync (),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (16'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[2]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[2]),
.up_rack (up_rack_s[2]));
// adc delay control
up_delay_cntrl #(.IO_WIDTH(15), .IO_BASEADDR(6'h02)) i_delay_cntrl (
.delay_clk (delay_clk),
.delay_rst (delay_rst),
.delay_locked (delay_locked_s),
.up_dld (up_dld_s),
.up_dwdata (up_dwdata_s),
.up_drdata (up_drdata_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[3]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[3]),
.up_rack (up_rack_s[3]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// MBT 11/9/2014
//
// Synchronous 1-port ram.
// Only one read or one write may be done per cycle.
`define bsg_mem_1rw_sync_macro_bit(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rw_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 ) \
,.TEST ( 2'b0 )); \
end
`define bsg_mem_1rf_sync_macro_bit(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_1rf_lg``lgEls``_w``bits``_m``mux mem \
(.A ( addr_i ) \
,.D ( data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_i ) \
,.CEB ( ~v_i ) \
,.CLK ( clk_i ) \
,.Q ( data_o ) \
,.DELAY ( 2'b0 )); \
end
module bsg_mem_1rw_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p))
(input clk_i
, input reset_i
, input [width_p-1:0] data_i
, input [addr_width_lp-1:0] addr_i
, input v_i
, input [width_p-1:0] w_mask_i
, input w_i
, output [width_p-1:0] data_o
);
wire unused = reset_i;
// we use a 2 port RF because the 1 port RF
// does not support bit-level masking for 80-bit width
// alternatively we could instantiate 2 40-bit 1rw RF's
`bsg_mem_1rf_sync_macro_bit(256,4,8,4) else
`bsg_mem_1rf_sync_macro_bit(256,30,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,32,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,34,8,2) else
`bsg_mem_1rf_sync_macro_bit(256,36,8,2) else
`bsg_mem_1rw_sync_macro_bit(64,80,6,1) else
bsg_mem_1rw_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p(els_p)
) synth
(.*);
// synopsys translate_off
always_ff @(posedge clk_i)
if (v_i)
assert (addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", addr_i, els_p);
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d (%m)",width_p,els_p);
end
// synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1rw_sync_mask_write_bit)
|
// Implements I2C from the Zynq PS
module parallella_i2c
(/*AUTOARG*/
// Outputs
I2C_SDA_I, I2C_SCL_I,
// Inouts
I2C_SDA, I2C_SCL,
// Inputs
I2C_SDA_O, I2C_SDA_T, I2C_SCL_O, I2C_SCL_T
);
input I2C_SDA_O;
input I2C_SDA_T;
output I2C_SDA_I;
input I2C_SCL_O;
input I2C_SCL_T;
output I2C_SCL_I;
inout I2C_SDA;
inout I2C_SCL;
`ifdef PORTABLE
wire I2C_SDA = I2C_SDA_T ? 1'bZ : I2C_SDA_O;
wire I2C_SDA_I = I2C_SDA;
wire I2C_SCL = I2C_SCL_T ? 1'bZ : I2C_SCL_O;
wire I2C_SCL_I = I2C_SCL;
`else
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_sda (
.O(I2C_SDA_I), // Buffer output
.IO(I2C_SDA), // Buffer inout port (connect directly to top-level port)
.I(I2C_SDA_O), // Buffer input
.T(I2C_SDA_T) // 3-state enable input, high=input, low=output
);
IOBUF #(
.DRIVE(8), // Specify the output drive strength
.IBUF_LOW_PWR("TRUE"), // Low Power - "TRUE", High Performance = "FALSE"
.IOSTANDARD("DEFAULT"), // Specify the I/O standard
.SLEW("SLOW") // Specify the output slew rate
) IOBUF_inst (
.O(I2C_SCL_I), // Buffer output
.IO(I2C_SCL), // Buffer inout port (connect directly to top-level port)
.I(I2C_SCL_O), // Buffer input
.T(I2C_SCL_T) // 3-state enable input, high=input, low=output
);
`endif
endmodule // parallella_i2c
/*
File: parallella_i2c
This file is part of the Parallella FPGA Reference Design.
Copyright (C) 2013-2015 Adapteva, Inc.
Contributed by Fred Huettig
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
// Date : Mon May 26 11:16:06 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode synth_stub /home/keith/Documents/VHDL-lib/top/stereo_radio/ip/dds/dds_stub.v
// Design : dds
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "dds_compiler_v6_0,Vivado 2014.1" *)
module dds(aclk, s_axis_phase_tvalid, s_axis_phase_tdata, m_axis_data_tvalid, m_axis_data_tdata, m_axis_phase_tvalid, m_axis_phase_tdata)
/* synthesis syn_black_box black_box_pad_pin="aclk,s_axis_phase_tvalid,s_axis_phase_tdata[39:0],m_axis_data_tvalid,m_axis_data_tdata[31:0],m_axis_phase_tvalid,m_axis_phase_tdata[39:0]" */;
input aclk;
input s_axis_phase_tvalid;
input [39:0]s_axis_phase_tdata;
output m_axis_data_tvalid;
output [31:0]m_axis_data_tdata;
output m_axis_phase_tvalid;
output [39:0]m_axis_phase_tdata;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Yermy Benavides Solano
//
// Create Date: 22:59:01 05/16/2016
// Design Name:
// Module Name: signal_control_rtc_generator
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module signal_control_rtc_generator(
input wire clk,
input wire reset,
input wire in_escribir_leer,
input wire en_funcion,
output reg reg_a_d, //Senales de control RTC
output reg reg_cs,
output reg reg_wr,
output reg reg_rd,
output reg out_direccion_dato,
output wire flag_done
);
/////parametros de estado
localparam
espera = 1'b1,
leer_escribir = 1'b0;
// Bits del contador para generar una señal periódica de (2^N)*10ns
localparam N = 5;
// Declaración de señales
reg [N-1:0] q_reg;
reg [N-1:0] q_next;
reg state_reg, state_next;
reg reset_count;
//Descripción del comportamiento
//=============================================
// Contador para generar un pulso de(2^N)*10ns
//=============================================
always @(posedge clk, posedge reset_count)
begin
if (reset_count) q_reg <= 0;
else q_reg <= q_next;
end
always@*
begin
q_next <= q_reg + 1'b1;
end
// Pulso de salida
assign flag_done = (q_reg == 23) ? 1'b1 : 1'b0;//Tbandera fin de proseso
///logica secuencial
always @(posedge clk, posedge reset)
begin
if (reset)
state_reg <= espera;
else
state_reg <= state_next;
end
// Lógica de estado siguiente y salida
always@*
begin
state_next = state_reg; // default state: the same
case(state_reg)
espera:
begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
reset_count = 1'b1;
if(en_funcion) state_next = leer_escribir;
else state_next = espera;
end
leer_escribir:
begin
reset_count = 1'b0;
//Proseso de lectura_escritura
case(q_reg)
5'd0: begin //inicia
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_rd = 1'b1;
reg_wr = 1'b1;
out_direccion_dato = 1'b0;
end
5'd1: begin // baja salida a_d
reg_a_d = 1'b0;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd2: begin// baja cs con wr o rd incio de manipulacion del bis de datos
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd3: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd4: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd5: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd6: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd7: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd8: begin
reg_a_d = 1'b0;
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd9:begin
reg_a_d = 1'b0;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd10: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd11: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd12: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd13: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd14: begin
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
end
5'd15: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd16:begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd17:begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd18:begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd19: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd20: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end
end
5'd21: begin
reg_a_d = 1'b1;
out_direccion_dato = 1'b1;
if (in_escribir_leer)begin
reg_cs = 1'b0;
reg_wr = 1'b0;
reg_rd = 1'b1;
end
else begin
reg_cs = 1'b0;
reg_wr = 1'b1;
reg_rd = 1'b0;
end end
5'd22: begin reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b1;
end
5'd23:
begin reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_wr = 1'b1;
reg_rd = 1'b1;
out_direccion_dato = 1'b0;
state_next = espera;
end
default: begin
state_next = leer_escribir;
reg_a_d = 1'b1;
reg_cs = 1'b1;
reg_rd = 1'b1;
reg_wr = 1'b1;
out_direccion_dato = 1'b0;
end
endcase
end
default: begin
state_next = espera;
reg_cs = 1'd1;
reg_a_d = 1'd1;
reg_wr = 1'd1;
reg_rd = 1'd1;
out_direccion_dato = 1'd0;
end
endcase
end
endmodule
|
// hub_mem
/*
-------------------------------------------------------------------------------
Copyright 2014 Parallax Inc.
This file is part of the hardware description for the Propeller 1 Design.
The Propeller 1 Design is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by the
Free Software Foundation, either version 3 of the License, or (at your option)
any later version.
The Propeller 1 Design is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details.
You should have received a copy of the GNU General Public License along with
the Propeller 1 Design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
*/
module hub_mem
(
input clk_cog,
input ena_bus,
input w,
input [3:0] wb,
input [13:0] a,
input [31:0] d,
output [31:0] q
);
// 8192 x 32 ram with byte-write enables ($0000..$7FFF)
reg [7:0] ram3 [8191:0];
reg [7:0] ram2 [8191:0];
reg [7:0] ram1 [8191:0];
reg [7:0] ram0 [8191:0];
reg [7:0] ram_q3;
reg [7:0] ram_q2;
reg [7:0] ram_q1;
reg [7:0] ram_q0;
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[3])
ram3[a[12:0]] <= d[31:24];
if (ena_bus && !a[13])
ram_q3 <= ram3[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[2])
ram2[a[12:0]] <= d[23:16];
if (ena_bus && !a[13])
ram_q2 <= ram2[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[1])
ram1[a[12:0]] <= d[15:8];
if (ena_bus && !a[13])
ram_q1 <= ram1[a[12:0]];
end
always @(posedge clk_cog)
begin
if (ena_bus && !a[13] && w && wb[0])
ram0[a[12:0]] <= d[7:0];
if (ena_bus && !a[13])
ram_q0 <= ram0[a[12:0]];
end
// 4096 x 32 rom containing character definitions ($8000..$BFFF)
(* ram_init_file = "hub_rom_low.hex" *) reg [31:0] rom_low [4095:0];
reg [31:0] rom_low_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b10)
rom_low_q <= rom_low[a[11:0]];
// 4096 x 32 rom containing sin table, log table, booter, and interpreter ($C000..$FFFF)
(* ram_init_file = "hub_rom_high.hex" *) reg [31:0] rom_high [4095:0];
reg [31:0] rom_high_q;
always @(posedge clk_cog)
if (ena_bus && a[13:12] == 2'b11)
rom_high_q <= rom_high[a[11:0]];
// memory output mux
reg [1:0] mem;
always @(posedge clk_cog)
if (ena_bus)
mem <= a[13:12];
assign q = !mem[1] ? {ram_q3, ram_q2, ram_q1, ram_q0}
// : !mem[0] ? rom_low_q // comment out this line for DE0-Nano (sacrifices character rom to fit device)
: rom_high_q;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND2_FUNCTIONAL_V
/**
* and2: 2-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND2_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
`define SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
/**
* srsdfstp: Scan flop with sleep mode, inverted set, non-inverted
* clock, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__srsdfstp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input SLEEP_B
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFSTP_SYMBOL_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: iobdg_1r1w_rf32.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: iobdg_1r1w_rf32
// Description: 1r1w regfile emulated using FF's.
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
////////////////////////////////////////////////////////////////////////
// Local header file includes / local defines
////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////
// Interface signal list declarations
////////////////////////////////////////////////////////////////////////
module iobdg_1r1w_rf32 (/*AUTOARG*/
// Outputs
dout,
// Inputs
rd_clk, wr_clk, rd_a, wr_a, din, wen_l
);
parameter REG_WIDTH = 64;
////////////////////////////////////////////////////////////////////////
// Signal declarations
////////////////////////////////////////////////////////////////////////
input rd_clk;
input wr_clk;
input [4:0] rd_a;
input [4:0] wr_a;
input [REG_WIDTH-1:0] din;
input wen_l;
output [REG_WIDTH-1:0] dout;
wire [4:0] wr_a_d1;
wire [REG_WIDTH-1:0] din_d1;
wire wen_l_d1;
wire [31:0] wr_a_dec_d1;
wire [31:0] wen_dec_d1;
wire [REG_WIDTH-1:0] line0;
wire [REG_WIDTH-1:0] line1;
wire [REG_WIDTH-1:0] line2;
wire [REG_WIDTH-1:0] line3;
wire [REG_WIDTH-1:0] line4;
wire [REG_WIDTH-1:0] line5;
wire [REG_WIDTH-1:0] line6;
wire [REG_WIDTH-1:0] line7;
wire [REG_WIDTH-1:0] line8;
wire [REG_WIDTH-1:0] line9;
wire [REG_WIDTH-1:0] line10;
wire [REG_WIDTH-1:0] line11;
wire [REG_WIDTH-1:0] line12;
wire [REG_WIDTH-1:0] line13;
wire [REG_WIDTH-1:0] line14;
wire [REG_WIDTH-1:0] line15;
wire [REG_WIDTH-1:0] line16;
wire [REG_WIDTH-1:0] line17;
wire [REG_WIDTH-1:0] line18;
wire [REG_WIDTH-1:0] line19;
wire [REG_WIDTH-1:0] line20;
wire [REG_WIDTH-1:0] line21;
wire [REG_WIDTH-1:0] line22;
wire [REG_WIDTH-1:0] line23;
wire [REG_WIDTH-1:0] line24;
wire [REG_WIDTH-1:0] line25;
wire [REG_WIDTH-1:0] line26;
wire [REG_WIDTH-1:0] line27;
wire [REG_WIDTH-1:0] line28;
wire [REG_WIDTH-1:0] line29;
wire [REG_WIDTH-1:0] line30;
wire [REG_WIDTH-1:0] line31;
wire [4:0] rd_a_d1;
reg [REG_WIDTH-1:0] dout;
////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
// Flop write address, write data and write enable
dff_ns #(5) wr_a_d1_ff (.din(wr_a),
.clk(wr_clk),
.q(wr_a_d1));
dff_ns #(REG_WIDTH) din_d1_ff (.din(din),
.clk(wr_clk),
.q(din_d1));
dff_ns #(1) wen_l_d1_ff (.din(wen_l),
.clk(wr_clk),
.q(wen_l_d1));
assign wr_a_dec_d1 = 1'b1 << wr_a_d1;
assign wen_dec_d1 = {32{~wen_l_d1}} & wr_a_dec_d1;
// FF's for storage
dffe_ns #(REG_WIDTH) line0_ff (.din(din_d1),.en(wen_dec_d1[0]),.clk(wr_clk),.q(line0));
dffe_ns #(REG_WIDTH) line1_ff (.din(din_d1),.en(wen_dec_d1[1]),.clk(wr_clk),.q(line1));
dffe_ns #(REG_WIDTH) line2_ff (.din(din_d1),.en(wen_dec_d1[2]),.clk(wr_clk),.q(line2));
dffe_ns #(REG_WIDTH) line3_ff (.din(din_d1),.en(wen_dec_d1[3]),.clk(wr_clk),.q(line3));
dffe_ns #(REG_WIDTH) line4_ff (.din(din_d1),.en(wen_dec_d1[4]),.clk(wr_clk),.q(line4));
dffe_ns #(REG_WIDTH) line5_ff (.din(din_d1),.en(wen_dec_d1[5]),.clk(wr_clk),.q(line5));
dffe_ns #(REG_WIDTH) line6_ff (.din(din_d1),.en(wen_dec_d1[6]),.clk(wr_clk),.q(line6));
dffe_ns #(REG_WIDTH) line7_ff (.din(din_d1),.en(wen_dec_d1[7]),.clk(wr_clk),.q(line7));
dffe_ns #(REG_WIDTH) line8_ff (.din(din_d1),.en(wen_dec_d1[8]),.clk(wr_clk),.q(line8));
dffe_ns #(REG_WIDTH) line9_ff (.din(din_d1),.en(wen_dec_d1[9]),.clk(wr_clk),.q(line9));
dffe_ns #(REG_WIDTH) line10_ff (.din(din_d1),.en(wen_dec_d1[10]),.clk(wr_clk),.q(line10));
dffe_ns #(REG_WIDTH) line11_ff (.din(din_d1),.en(wen_dec_d1[11]),.clk(wr_clk),.q(line11));
dffe_ns #(REG_WIDTH) line12_ff (.din(din_d1),.en(wen_dec_d1[12]),.clk(wr_clk),.q(line12));
dffe_ns #(REG_WIDTH) line13_ff (.din(din_d1),.en(wen_dec_d1[13]),.clk(wr_clk),.q(line13));
dffe_ns #(REG_WIDTH) line14_ff (.din(din_d1),.en(wen_dec_d1[14]),.clk(wr_clk),.q(line14));
dffe_ns #(REG_WIDTH) line15_ff (.din(din_d1),.en(wen_dec_d1[15]),.clk(wr_clk),.q(line15));
dffe_ns #(REG_WIDTH) line16_ff (.din(din_d1),.en(wen_dec_d1[16]),.clk(wr_clk),.q(line16));
dffe_ns #(REG_WIDTH) line17_ff (.din(din_d1),.en(wen_dec_d1[17]),.clk(wr_clk),.q(line17));
dffe_ns #(REG_WIDTH) line18_ff (.din(din_d1),.en(wen_dec_d1[18]),.clk(wr_clk),.q(line18));
dffe_ns #(REG_WIDTH) line19_ff (.din(din_d1),.en(wen_dec_d1[19]),.clk(wr_clk),.q(line19));
dffe_ns #(REG_WIDTH) line20_ff (.din(din_d1),.en(wen_dec_d1[20]),.clk(wr_clk),.q(line20));
dffe_ns #(REG_WIDTH) line21_ff (.din(din_d1),.en(wen_dec_d1[21]),.clk(wr_clk),.q(line21));
dffe_ns #(REG_WIDTH) line22_ff (.din(din_d1),.en(wen_dec_d1[22]),.clk(wr_clk),.q(line22));
dffe_ns #(REG_WIDTH) line23_ff (.din(din_d1),.en(wen_dec_d1[23]),.clk(wr_clk),.q(line23));
dffe_ns #(REG_WIDTH) line24_ff (.din(din_d1),.en(wen_dec_d1[24]),.clk(wr_clk),.q(line24));
dffe_ns #(REG_WIDTH) line25_ff (.din(din_d1),.en(wen_dec_d1[25]),.clk(wr_clk),.q(line25));
dffe_ns #(REG_WIDTH) line26_ff (.din(din_d1),.en(wen_dec_d1[26]),.clk(wr_clk),.q(line26));
dffe_ns #(REG_WIDTH) line27_ff (.din(din_d1),.en(wen_dec_d1[27]),.clk(wr_clk),.q(line27));
dffe_ns #(REG_WIDTH) line28_ff (.din(din_d1),.en(wen_dec_d1[28]),.clk(wr_clk),.q(line28));
dffe_ns #(REG_WIDTH) line29_ff (.din(din_d1),.en(wen_dec_d1[29]),.clk(wr_clk),.q(line29));
dffe_ns #(REG_WIDTH) line30_ff (.din(din_d1),.en(wen_dec_d1[30]),.clk(wr_clk),.q(line30));
dffe_ns #(REG_WIDTH) line31_ff (.din(din_d1),.en(wen_dec_d1[31]),.clk(wr_clk),.q(line31));
// Flop read address
dff_ns #(5) rd_a_d1_ff (.din(rd_a),
.clk(rd_clk),
.q(rd_a_d1));
// Mux out read data
always @(/*AUTOSENSE*/line0 or line1 or line10 or line11 or line12
or line13 or line14 or line15 or line16 or line17
or line18 or line19 or line2 or line20 or line21 or line22
or line23 or line24 or line25 or line26 or line27
or line28 or line29 or line3 or line30 or line31 or line4
or line5 or line6 or line7 or line8 or line9 or rd_a_d1) begin
case (rd_a_d1)
5'd0: dout = line0;
5'd1: dout = line1;
5'd2: dout = line2;
5'd3: dout = line3;
5'd4: dout = line4;
5'd5: dout = line5;
5'd6: dout = line6;
5'd7: dout = line7;
5'd8: dout = line8;
5'd9: dout = line9;
5'd10: dout = line10;
5'd11: dout = line11;
5'd12: dout = line12;
5'd13: dout = line13;
5'd14: dout = line14;
5'd15: dout = line15;
5'd16: dout = line16;
5'd17: dout = line17;
5'd18: dout = line18;
5'd19: dout = line19;
5'd20: dout = line20;
5'd21: dout = line21;
5'd22: dout = line22;
5'd23: dout = line23;
5'd24: dout = line24;
5'd25: dout = line25;
5'd26: dout = line26;
5'd27: dout = line27;
5'd28: dout = line28;
5'd29: dout = line29;
5'd30: dout = line30;
5'd31: dout = line31;
default: dout = {REG_WIDTH{1'bx}};
endcase // case(rd_a_d1)
end
endmodule // iobdg_1r1w_rf32
// Local Variables:
// verilog-auto-sense-defines-constant:t
// End:
|
// wasca_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0 (
input wire altpll_1_c0_clk, // altpll_1_c0.clk
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset, // altpll_1_inclk_interface_reset_reset_bridge_in_reset.reset
input wire buffered_spi_0_reset_reset_bridge_in_reset_reset, // buffered_spi_0_reset_reset_bridge_in_reset.reset
input wire nios2_gen2_0_reset_reset_bridge_in_reset_reset, // nios2_gen2_0_reset_reset_bridge_in_reset.reset
input wire [26:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [19:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire [7:0] abus_avalon_sdram_bridge_0_avalon_regs_address, // abus_avalon_sdram_bridge_0_avalon_regs.address
output wire abus_avalon_sdram_bridge_0_avalon_regs_write, // .write
output wire abus_avalon_sdram_bridge_0_avalon_regs_read, // .read
input wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_readdata, // .readdata
output wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_writedata, // .writedata
input wire abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid, // .readdatavalid
input wire abus_avalon_sdram_bridge_0_avalon_regs_waitrequest, // .waitrequest
output wire [25:0] abus_avalon_sdram_bridge_0_avalon_sdram_address, // abus_avalon_sdram_bridge_0_avalon_sdram.address
output wire abus_avalon_sdram_bridge_0_avalon_sdram_write, // .write
output wire abus_avalon_sdram_bridge_0_avalon_sdram_read, // .read
input wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_readdata, // .readdata
output wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_writedata, // .writedata
output wire [1:0] abus_avalon_sdram_bridge_0_avalon_sdram_byteenable, // .byteenable
input wire abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid, // .readdatavalid
input wire abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest, // .waitrequest
output wire [7:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address, // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave.address
output wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write, // .write
output wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read, // .read
input wire [31:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata, // .readdata
output wire [31:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata, // .writedata
output wire [3:0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable, // .byteenable
input wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest, // .waitrequest
output wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect, // .chipselect
output wire [1:0] altpll_1_pll_slave_address, // altpll_1_pll_slave.address
output wire altpll_1_pll_slave_write, // .write
output wire altpll_1_pll_slave_read, // .read
input wire [31:0] altpll_1_pll_slave_readdata, // .readdata
output wire [31:0] altpll_1_pll_slave_writedata, // .writedata
output wire [1:0] audio_0_avalon_audio_slave_address, // audio_0_avalon_audio_slave.address
output wire audio_0_avalon_audio_slave_write, // .write
output wire audio_0_avalon_audio_slave_read, // .read
input wire [31:0] audio_0_avalon_audio_slave_readdata, // .readdata
output wire [31:0] audio_0_avalon_audio_slave_writedata, // .writedata
output wire audio_0_avalon_audio_slave_chipselect, // .chipselect
output wire [13:0] buffered_spi_0_avalon_address, // buffered_spi_0_avalon.address
output wire buffered_spi_0_avalon_write, // .write
output wire buffered_spi_0_avalon_read, // .read
input wire [15:0] buffered_spi_0_avalon_readdata, // .readdata
output wire [15:0] buffered_spi_0_avalon_writedata, // .writedata
input wire buffered_spi_0_avalon_readdatavalid, // .readdatavalid
input wire buffered_spi_0_avalon_waitrequest, // .waitrequest
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [15:0] onchip_flash_0_data_address, // onchip_flash_0_data.address
output wire onchip_flash_0_data_read, // .read
input wire [31:0] onchip_flash_0_data_readdata, // .readdata
output wire [3:0] onchip_flash_0_data_burstcount, // .burstcount
input wire onchip_flash_0_data_readdatavalid, // .readdatavalid
input wire onchip_flash_0_data_waitrequest, // .waitrequest
output wire [11:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [2:0] uart_0_s1_address, // uart_0_s1.address
output wire uart_0_s1_write, // .write
output wire uart_0_s1_read, // .read
input wire [15:0] uart_0_s1_readdata, // .readdata
output wire [15:0] uart_0_s1_writedata, // .writedata
output wire uart_0_s1_begintransfer, // .begintransfer
output wire uart_0_s1_chipselect // .chipselect
);
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [26:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire rsp_mux_src_valid; // rsp_mux:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [107:0] rsp_mux_src_data; // rsp_mux:src_data -> nios2_gen2_0_data_master_agent:rp_data
wire rsp_mux_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux:src_ready
wire [9:0] rsp_mux_src_channel; // rsp_mux:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [26:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [107:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [9:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire [15:0] buffered_spi_0_avalon_agent_m0_readdata; // buffered_spi_0_avalon_translator:uav_readdata -> buffered_spi_0_avalon_agent:m0_readdata
wire buffered_spi_0_avalon_agent_m0_waitrequest; // buffered_spi_0_avalon_translator:uav_waitrequest -> buffered_spi_0_avalon_agent:m0_waitrequest
wire buffered_spi_0_avalon_agent_m0_debugaccess; // buffered_spi_0_avalon_agent:m0_debugaccess -> buffered_spi_0_avalon_translator:uav_debugaccess
wire [26:0] buffered_spi_0_avalon_agent_m0_address; // buffered_spi_0_avalon_agent:m0_address -> buffered_spi_0_avalon_translator:uav_address
wire [1:0] buffered_spi_0_avalon_agent_m0_byteenable; // buffered_spi_0_avalon_agent:m0_byteenable -> buffered_spi_0_avalon_translator:uav_byteenable
wire buffered_spi_0_avalon_agent_m0_read; // buffered_spi_0_avalon_agent:m0_read -> buffered_spi_0_avalon_translator:uav_read
wire buffered_spi_0_avalon_agent_m0_readdatavalid; // buffered_spi_0_avalon_translator:uav_readdatavalid -> buffered_spi_0_avalon_agent:m0_readdatavalid
wire buffered_spi_0_avalon_agent_m0_lock; // buffered_spi_0_avalon_agent:m0_lock -> buffered_spi_0_avalon_translator:uav_lock
wire [15:0] buffered_spi_0_avalon_agent_m0_writedata; // buffered_spi_0_avalon_agent:m0_writedata -> buffered_spi_0_avalon_translator:uav_writedata
wire buffered_spi_0_avalon_agent_m0_write; // buffered_spi_0_avalon_agent:m0_write -> buffered_spi_0_avalon_translator:uav_write
wire [1:0] buffered_spi_0_avalon_agent_m0_burstcount; // buffered_spi_0_avalon_agent:m0_burstcount -> buffered_spi_0_avalon_translator:uav_burstcount
wire buffered_spi_0_avalon_agent_rf_source_valid; // buffered_spi_0_avalon_agent:rf_source_valid -> buffered_spi_0_avalon_agent_rsp_fifo:in_valid
wire [90:0] buffered_spi_0_avalon_agent_rf_source_data; // buffered_spi_0_avalon_agent:rf_source_data -> buffered_spi_0_avalon_agent_rsp_fifo:in_data
wire buffered_spi_0_avalon_agent_rf_source_ready; // buffered_spi_0_avalon_agent_rsp_fifo:in_ready -> buffered_spi_0_avalon_agent:rf_source_ready
wire buffered_spi_0_avalon_agent_rf_source_startofpacket; // buffered_spi_0_avalon_agent:rf_source_startofpacket -> buffered_spi_0_avalon_agent_rsp_fifo:in_startofpacket
wire buffered_spi_0_avalon_agent_rf_source_endofpacket; // buffered_spi_0_avalon_agent:rf_source_endofpacket -> buffered_spi_0_avalon_agent_rsp_fifo:in_endofpacket
wire buffered_spi_0_avalon_agent_rsp_fifo_out_valid; // buffered_spi_0_avalon_agent_rsp_fifo:out_valid -> buffered_spi_0_avalon_agent:rf_sink_valid
wire [90:0] buffered_spi_0_avalon_agent_rsp_fifo_out_data; // buffered_spi_0_avalon_agent_rsp_fifo:out_data -> buffered_spi_0_avalon_agent:rf_sink_data
wire buffered_spi_0_avalon_agent_rsp_fifo_out_ready; // buffered_spi_0_avalon_agent:rf_sink_ready -> buffered_spi_0_avalon_agent_rsp_fifo:out_ready
wire buffered_spi_0_avalon_agent_rsp_fifo_out_startofpacket; // buffered_spi_0_avalon_agent_rsp_fifo:out_startofpacket -> buffered_spi_0_avalon_agent:rf_sink_startofpacket
wire buffered_spi_0_avalon_agent_rsp_fifo_out_endofpacket; // buffered_spi_0_avalon_agent_rsp_fifo:out_endofpacket -> buffered_spi_0_avalon_agent:rf_sink_endofpacket
wire [31:0] audio_0_avalon_audio_slave_agent_m0_readdata; // audio_0_avalon_audio_slave_translator:uav_readdata -> audio_0_avalon_audio_slave_agent:m0_readdata
wire audio_0_avalon_audio_slave_agent_m0_waitrequest; // audio_0_avalon_audio_slave_translator:uav_waitrequest -> audio_0_avalon_audio_slave_agent:m0_waitrequest
wire audio_0_avalon_audio_slave_agent_m0_debugaccess; // audio_0_avalon_audio_slave_agent:m0_debugaccess -> audio_0_avalon_audio_slave_translator:uav_debugaccess
wire [26:0] audio_0_avalon_audio_slave_agent_m0_address; // audio_0_avalon_audio_slave_agent:m0_address -> audio_0_avalon_audio_slave_translator:uav_address
wire [3:0] audio_0_avalon_audio_slave_agent_m0_byteenable; // audio_0_avalon_audio_slave_agent:m0_byteenable -> audio_0_avalon_audio_slave_translator:uav_byteenable
wire audio_0_avalon_audio_slave_agent_m0_read; // audio_0_avalon_audio_slave_agent:m0_read -> audio_0_avalon_audio_slave_translator:uav_read
wire audio_0_avalon_audio_slave_agent_m0_readdatavalid; // audio_0_avalon_audio_slave_translator:uav_readdatavalid -> audio_0_avalon_audio_slave_agent:m0_readdatavalid
wire audio_0_avalon_audio_slave_agent_m0_lock; // audio_0_avalon_audio_slave_agent:m0_lock -> audio_0_avalon_audio_slave_translator:uav_lock
wire [31:0] audio_0_avalon_audio_slave_agent_m0_writedata; // audio_0_avalon_audio_slave_agent:m0_writedata -> audio_0_avalon_audio_slave_translator:uav_writedata
wire audio_0_avalon_audio_slave_agent_m0_write; // audio_0_avalon_audio_slave_agent:m0_write -> audio_0_avalon_audio_slave_translator:uav_write
wire [2:0] audio_0_avalon_audio_slave_agent_m0_burstcount; // audio_0_avalon_audio_slave_agent:m0_burstcount -> audio_0_avalon_audio_slave_translator:uav_burstcount
wire audio_0_avalon_audio_slave_agent_rf_source_valid; // audio_0_avalon_audio_slave_agent:rf_source_valid -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_valid
wire [108:0] audio_0_avalon_audio_slave_agent_rf_source_data; // audio_0_avalon_audio_slave_agent:rf_source_data -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_data
wire audio_0_avalon_audio_slave_agent_rf_source_ready; // audio_0_avalon_audio_slave_agent_rsp_fifo:in_ready -> audio_0_avalon_audio_slave_agent:rf_source_ready
wire audio_0_avalon_audio_slave_agent_rf_source_startofpacket; // audio_0_avalon_audio_slave_agent:rf_source_startofpacket -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_startofpacket
wire audio_0_avalon_audio_slave_agent_rf_source_endofpacket; // audio_0_avalon_audio_slave_agent:rf_source_endofpacket -> audio_0_avalon_audio_slave_agent_rsp_fifo:in_endofpacket
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_valid -> audio_0_avalon_audio_slave_agent:rf_sink_valid
wire [108:0] audio_0_avalon_audio_slave_agent_rsp_fifo_out_data; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_data -> audio_0_avalon_audio_slave_agent:rf_sink_data
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready; // audio_0_avalon_audio_slave_agent:rf_sink_ready -> audio_0_avalon_audio_slave_agent_rsp_fifo:out_ready
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_startofpacket -> audio_0_avalon_audio_slave_agent:rf_sink_startofpacket
wire audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket; // audio_0_avalon_audio_slave_agent_rsp_fifo:out_endofpacket -> audio_0_avalon_audio_slave_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> audio_0_avalon_audio_slave_agent:cp_valid
wire [107:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> audio_0_avalon_audio_slave_agent:cp_data
wire cmd_mux_001_src_ready; // audio_0_avalon_audio_slave_agent:cp_ready -> cmd_mux_001:src_ready
wire [9:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> audio_0_avalon_audio_slave_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> audio_0_avalon_audio_slave_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> audio_0_avalon_audio_slave_agent:cp_endofpacket
wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdata; // abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_readdata -> abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_readdata
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_waitrequest; // abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_waitrequest -> abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_waitrequest
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_debugaccess; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_debugaccess -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_debugaccess
wire [26:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_address; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_address -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_address
wire [1:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_byteenable; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_byteenable -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_byteenable
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_read; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_read -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_read
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdatavalid; // abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_readdatavalid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_readdatavalid
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_lock; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_lock -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_lock
wire [15:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_writedata; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_writedata -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_writedata
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_write; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_write -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_write
wire [1:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_burstcount; // abus_avalon_sdram_bridge_0_avalon_regs_agent:m0_burstcount -> abus_avalon_sdram_bridge_0_avalon_regs_translator:uav_burstcount
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_ready
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_source_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_ready
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rf_sink_endofpacket
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_readdata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_readdata
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_waitrequest; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_waitrequest -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_waitrequest
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_debugaccess; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_debugaccess -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_debugaccess
wire [26:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_address; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_address -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_address
wire [3:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_byteenable; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_byteenable -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_byteenable
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_read; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_read -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_read
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdatavalid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_readdatavalid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_readdatavalid
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_lock; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_lock -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_lock
wire [31:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_writedata; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_writedata -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_writedata
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_write; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_write -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_write
wire [2:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_burstcount; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:m0_burstcount -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_translator:uav_burstcount
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_valid
wire [108:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_startofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_source_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:in_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_valid
wire [108:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_startofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent_rsp_fifo:out_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_valid
wire [107:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_data
wire cmd_mux_003_src_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_ready -> cmd_mux_003:src_ready
wire [9:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:cp_endofpacket
wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdata; // abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_readdata -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_readdata
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_waitrequest; // abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_waitrequest -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_waitrequest
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_debugaccess; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_debugaccess -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_debugaccess
wire [26:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_address; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_address -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_address
wire [1:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_byteenable; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_byteenable -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_byteenable
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_read; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_read -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_read
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdatavalid; // abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_readdatavalid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_readdatavalid
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_lock; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_lock -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_lock
wire [15:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_writedata; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_writedata -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_writedata
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_write; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_write -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_write
wire [1:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_burstcount; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:m0_burstcount -> abus_avalon_sdram_bridge_0_avalon_sdram_translator:uav_burstcount
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_ready
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_source_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_valid
wire [90:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_ready
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rf_sink_endofpacket
wire [31:0] onchip_flash_0_data_agent_m0_readdata; // onchip_flash_0_data_translator:uav_readdata -> onchip_flash_0_data_agent:m0_readdata
wire onchip_flash_0_data_agent_m0_waitrequest; // onchip_flash_0_data_translator:uav_waitrequest -> onchip_flash_0_data_agent:m0_waitrequest
wire onchip_flash_0_data_agent_m0_debugaccess; // onchip_flash_0_data_agent:m0_debugaccess -> onchip_flash_0_data_translator:uav_debugaccess
wire [26:0] onchip_flash_0_data_agent_m0_address; // onchip_flash_0_data_agent:m0_address -> onchip_flash_0_data_translator:uav_address
wire [3:0] onchip_flash_0_data_agent_m0_byteenable; // onchip_flash_0_data_agent:m0_byteenable -> onchip_flash_0_data_translator:uav_byteenable
wire onchip_flash_0_data_agent_m0_read; // onchip_flash_0_data_agent:m0_read -> onchip_flash_0_data_translator:uav_read
wire onchip_flash_0_data_agent_m0_readdatavalid; // onchip_flash_0_data_translator:uav_readdatavalid -> onchip_flash_0_data_agent:m0_readdatavalid
wire onchip_flash_0_data_agent_m0_lock; // onchip_flash_0_data_agent:m0_lock -> onchip_flash_0_data_translator:uav_lock
wire [31:0] onchip_flash_0_data_agent_m0_writedata; // onchip_flash_0_data_agent:m0_writedata -> onchip_flash_0_data_translator:uav_writedata
wire onchip_flash_0_data_agent_m0_write; // onchip_flash_0_data_agent:m0_write -> onchip_flash_0_data_translator:uav_write
wire [5:0] onchip_flash_0_data_agent_m0_burstcount; // onchip_flash_0_data_agent:m0_burstcount -> onchip_flash_0_data_translator:uav_burstcount
wire onchip_flash_0_data_agent_rf_source_valid; // onchip_flash_0_data_agent:rf_source_valid -> onchip_flash_0_data_agent_rsp_fifo:in_valid
wire [108:0] onchip_flash_0_data_agent_rf_source_data; // onchip_flash_0_data_agent:rf_source_data -> onchip_flash_0_data_agent_rsp_fifo:in_data
wire onchip_flash_0_data_agent_rf_source_ready; // onchip_flash_0_data_agent_rsp_fifo:in_ready -> onchip_flash_0_data_agent:rf_source_ready
wire onchip_flash_0_data_agent_rf_source_startofpacket; // onchip_flash_0_data_agent:rf_source_startofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_startofpacket
wire onchip_flash_0_data_agent_rf_source_endofpacket; // onchip_flash_0_data_agent:rf_source_endofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_endofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_valid; // onchip_flash_0_data_agent_rsp_fifo:out_valid -> onchip_flash_0_data_agent:rf_sink_valid
wire [108:0] onchip_flash_0_data_agent_rsp_fifo_out_data; // onchip_flash_0_data_agent_rsp_fifo:out_data -> onchip_flash_0_data_agent:rf_sink_data
wire onchip_flash_0_data_agent_rsp_fifo_out_ready; // onchip_flash_0_data_agent:rf_sink_ready -> onchip_flash_0_data_agent_rsp_fifo:out_ready
wire onchip_flash_0_data_agent_rsp_fifo_out_startofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_data_agent:rf_sink_startofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_endofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_data_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> onchip_flash_0_data_agent:cp_valid
wire [107:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> onchip_flash_0_data_agent:cp_data
wire cmd_mux_005_src_ready; // onchip_flash_0_data_agent:cp_ready -> cmd_mux_005:src_ready
wire [9:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> onchip_flash_0_data_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> onchip_flash_0_data_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> onchip_flash_0_data_agent:cp_endofpacket
wire [31:0] altpll_1_pll_slave_agent_m0_readdata; // altpll_1_pll_slave_translator:uav_readdata -> altpll_1_pll_slave_agent:m0_readdata
wire altpll_1_pll_slave_agent_m0_waitrequest; // altpll_1_pll_slave_translator:uav_waitrequest -> altpll_1_pll_slave_agent:m0_waitrequest
wire altpll_1_pll_slave_agent_m0_debugaccess; // altpll_1_pll_slave_agent:m0_debugaccess -> altpll_1_pll_slave_translator:uav_debugaccess
wire [26:0] altpll_1_pll_slave_agent_m0_address; // altpll_1_pll_slave_agent:m0_address -> altpll_1_pll_slave_translator:uav_address
wire [3:0] altpll_1_pll_slave_agent_m0_byteenable; // altpll_1_pll_slave_agent:m0_byteenable -> altpll_1_pll_slave_translator:uav_byteenable
wire altpll_1_pll_slave_agent_m0_read; // altpll_1_pll_slave_agent:m0_read -> altpll_1_pll_slave_translator:uav_read
wire altpll_1_pll_slave_agent_m0_readdatavalid; // altpll_1_pll_slave_translator:uav_readdatavalid -> altpll_1_pll_slave_agent:m0_readdatavalid
wire altpll_1_pll_slave_agent_m0_lock; // altpll_1_pll_slave_agent:m0_lock -> altpll_1_pll_slave_translator:uav_lock
wire [31:0] altpll_1_pll_slave_agent_m0_writedata; // altpll_1_pll_slave_agent:m0_writedata -> altpll_1_pll_slave_translator:uav_writedata
wire altpll_1_pll_slave_agent_m0_write; // altpll_1_pll_slave_agent:m0_write -> altpll_1_pll_slave_translator:uav_write
wire [2:0] altpll_1_pll_slave_agent_m0_burstcount; // altpll_1_pll_slave_agent:m0_burstcount -> altpll_1_pll_slave_translator:uav_burstcount
wire altpll_1_pll_slave_agent_rf_source_valid; // altpll_1_pll_slave_agent:rf_source_valid -> altpll_1_pll_slave_agent_rsp_fifo:in_valid
wire [108:0] altpll_1_pll_slave_agent_rf_source_data; // altpll_1_pll_slave_agent:rf_source_data -> altpll_1_pll_slave_agent_rsp_fifo:in_data
wire altpll_1_pll_slave_agent_rf_source_ready; // altpll_1_pll_slave_agent_rsp_fifo:in_ready -> altpll_1_pll_slave_agent:rf_source_ready
wire altpll_1_pll_slave_agent_rf_source_startofpacket; // altpll_1_pll_slave_agent:rf_source_startofpacket -> altpll_1_pll_slave_agent_rsp_fifo:in_startofpacket
wire altpll_1_pll_slave_agent_rf_source_endofpacket; // altpll_1_pll_slave_agent:rf_source_endofpacket -> altpll_1_pll_slave_agent_rsp_fifo:in_endofpacket
wire altpll_1_pll_slave_agent_rsp_fifo_out_valid; // altpll_1_pll_slave_agent_rsp_fifo:out_valid -> altpll_1_pll_slave_agent:rf_sink_valid
wire [108:0] altpll_1_pll_slave_agent_rsp_fifo_out_data; // altpll_1_pll_slave_agent_rsp_fifo:out_data -> altpll_1_pll_slave_agent:rf_sink_data
wire altpll_1_pll_slave_agent_rsp_fifo_out_ready; // altpll_1_pll_slave_agent:rf_sink_ready -> altpll_1_pll_slave_agent_rsp_fifo:out_ready
wire altpll_1_pll_slave_agent_rsp_fifo_out_startofpacket; // altpll_1_pll_slave_agent_rsp_fifo:out_startofpacket -> altpll_1_pll_slave_agent:rf_sink_startofpacket
wire altpll_1_pll_slave_agent_rsp_fifo_out_endofpacket; // altpll_1_pll_slave_agent_rsp_fifo:out_endofpacket -> altpll_1_pll_slave_agent:rf_sink_endofpacket
wire altpll_1_pll_slave_agent_rdata_fifo_src_valid; // altpll_1_pll_slave_agent:rdata_fifo_src_valid -> altpll_1_pll_slave_agent_rdata_fifo:in_valid
wire [33:0] altpll_1_pll_slave_agent_rdata_fifo_src_data; // altpll_1_pll_slave_agent:rdata_fifo_src_data -> altpll_1_pll_slave_agent_rdata_fifo:in_data
wire altpll_1_pll_slave_agent_rdata_fifo_src_ready; // altpll_1_pll_slave_agent_rdata_fifo:in_ready -> altpll_1_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> altpll_1_pll_slave_agent:cp_valid
wire [107:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> altpll_1_pll_slave_agent:cp_data
wire cmd_mux_006_src_ready; // altpll_1_pll_slave_agent:cp_ready -> cmd_mux_006:src_ready
wire [9:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> altpll_1_pll_slave_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> altpll_1_pll_slave_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> altpll_1_pll_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [26:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [108:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [108:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [107:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_007_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_007:src_ready
wire [9:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] uart_0_s1_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
wire uart_0_s1_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
wire uart_0_s1_agent_m0_debugaccess; // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
wire [26:0] uart_0_s1_agent_m0_address; // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
wire [3:0] uart_0_s1_agent_m0_byteenable; // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
wire uart_0_s1_agent_m0_read; // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
wire uart_0_s1_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
wire uart_0_s1_agent_m0_lock; // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
wire [31:0] uart_0_s1_agent_m0_writedata; // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
wire uart_0_s1_agent_m0_write; // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
wire [2:0] uart_0_s1_agent_m0_burstcount; // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
wire uart_0_s1_agent_rf_source_valid; // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
wire [108:0] uart_0_s1_agent_rf_source_data; // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
wire uart_0_s1_agent_rf_source_ready; // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
wire uart_0_s1_agent_rf_source_startofpacket; // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
wire uart_0_s1_agent_rf_source_endofpacket; // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
wire uart_0_s1_agent_rsp_fifo_out_valid; // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
wire [108:0] uart_0_s1_agent_rsp_fifo_out_data; // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
wire uart_0_s1_agent_rsp_fifo_out_ready; // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
wire uart_0_s1_agent_rsp_fifo_out_startofpacket; // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
wire uart_0_s1_agent_rsp_fifo_out_endofpacket; // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> uart_0_s1_agent:cp_valid
wire [107:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> uart_0_s1_agent:cp_data
wire cmd_mux_008_src_ready; // uart_0_s1_agent:cp_ready -> cmd_mux_008:src_ready
wire [9:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> uart_0_s1_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [26:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [108:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [107:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_009_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_009:src_ready
wire [9:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router:sink_valid
wire [107:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router:sink_endofpacket
wire router_src_valid; // router:src_valid -> cmd_demux:sink_valid
wire [107:0] router_src_data; // router:src_data -> cmd_demux:sink_data
wire router_src_ready; // cmd_demux:sink_ready -> router:src_ready
wire [9:0] router_src_channel; // router:src_channel -> cmd_demux:sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> cmd_demux:sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> cmd_demux:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_001:sink_valid
wire [107:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [107:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [9:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire buffered_spi_0_avalon_agent_rp_valid; // buffered_spi_0_avalon_agent:rp_valid -> router_002:sink_valid
wire [89:0] buffered_spi_0_avalon_agent_rp_data; // buffered_spi_0_avalon_agent:rp_data -> router_002:sink_data
wire buffered_spi_0_avalon_agent_rp_ready; // router_002:sink_ready -> buffered_spi_0_avalon_agent:rp_ready
wire buffered_spi_0_avalon_agent_rp_startofpacket; // buffered_spi_0_avalon_agent:rp_startofpacket -> router_002:sink_startofpacket
wire buffered_spi_0_avalon_agent_rp_endofpacket; // buffered_spi_0_avalon_agent:rp_endofpacket -> router_002:sink_endofpacket
wire audio_0_avalon_audio_slave_agent_rp_valid; // audio_0_avalon_audio_slave_agent:rp_valid -> router_003:sink_valid
wire [107:0] audio_0_avalon_audio_slave_agent_rp_data; // audio_0_avalon_audio_slave_agent:rp_data -> router_003:sink_data
wire audio_0_avalon_audio_slave_agent_rp_ready; // router_003:sink_ready -> audio_0_avalon_audio_slave_agent:rp_ready
wire audio_0_avalon_audio_slave_agent_rp_startofpacket; // audio_0_avalon_audio_slave_agent:rp_startofpacket -> router_003:sink_startofpacket
wire audio_0_avalon_audio_slave_agent_rp_endofpacket; // audio_0_avalon_audio_slave_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux_001:sink_valid
wire [107:0] router_003_src_data; // router_003:src_data -> rsp_demux_001:sink_data
wire router_003_src_ready; // rsp_demux_001:sink_ready -> router_003:src_ready
wire [9:0] router_003_src_channel; // router_003:src_channel -> rsp_demux_001:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_valid -> router_004:sink_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_data -> router_004:sink_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_ready; // router_004:sink_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_ready
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_startofpacket -> router_004:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rp_endofpacket -> router_004:sink_endofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_valid -> router_005:sink_valid
wire [107:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_data -> router_005:sink_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_ready; // router_005:sink_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_ready
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_startofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_startofpacket -> router_005:sink_startofpacket
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_endofpacket; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_003:sink_valid
wire [107:0] router_005_src_data; // router_005:src_data -> rsp_demux_003:sink_data
wire router_005_src_ready; // rsp_demux_003:sink_ready -> router_005:src_ready
wire [9:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_003:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_valid -> router_006:sink_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_data -> router_006:sink_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_ready; // router_006:sink_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_ready
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_startofpacket -> router_006:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rp_endofpacket -> router_006:sink_endofpacket
wire onchip_flash_0_data_agent_rp_valid; // onchip_flash_0_data_agent:rp_valid -> router_007:sink_valid
wire [107:0] onchip_flash_0_data_agent_rp_data; // onchip_flash_0_data_agent:rp_data -> router_007:sink_data
wire onchip_flash_0_data_agent_rp_ready; // router_007:sink_ready -> onchip_flash_0_data_agent:rp_ready
wire onchip_flash_0_data_agent_rp_startofpacket; // onchip_flash_0_data_agent:rp_startofpacket -> router_007:sink_startofpacket
wire onchip_flash_0_data_agent_rp_endofpacket; // onchip_flash_0_data_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_005:sink_valid
wire [107:0] router_007_src_data; // router_007:src_data -> rsp_demux_005:sink_data
wire router_007_src_ready; // rsp_demux_005:sink_ready -> router_007:src_ready
wire [9:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_005:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire altpll_1_pll_slave_agent_rp_valid; // altpll_1_pll_slave_agent:rp_valid -> router_008:sink_valid
wire [107:0] altpll_1_pll_slave_agent_rp_data; // altpll_1_pll_slave_agent:rp_data -> router_008:sink_data
wire altpll_1_pll_slave_agent_rp_ready; // router_008:sink_ready -> altpll_1_pll_slave_agent:rp_ready
wire altpll_1_pll_slave_agent_rp_startofpacket; // altpll_1_pll_slave_agent:rp_startofpacket -> router_008:sink_startofpacket
wire altpll_1_pll_slave_agent_rp_endofpacket; // altpll_1_pll_slave_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_006:sink_valid
wire [107:0] router_008_src_data; // router_008:src_data -> rsp_demux_006:sink_data
wire router_008_src_ready; // rsp_demux_006:sink_ready -> router_008:src_ready
wire [9:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_006:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_009:sink_valid
wire [107:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_009:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_009:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_009:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_007:sink_valid
wire [107:0] router_009_src_data; // router_009:src_data -> rsp_demux_007:sink_data
wire router_009_src_ready; // rsp_demux_007:sink_ready -> router_009:src_ready
wire [9:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_007:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire uart_0_s1_agent_rp_valid; // uart_0_s1_agent:rp_valid -> router_010:sink_valid
wire [107:0] uart_0_s1_agent_rp_data; // uart_0_s1_agent:rp_data -> router_010:sink_data
wire uart_0_s1_agent_rp_ready; // router_010:sink_ready -> uart_0_s1_agent:rp_ready
wire uart_0_s1_agent_rp_startofpacket; // uart_0_s1_agent:rp_startofpacket -> router_010:sink_startofpacket
wire uart_0_s1_agent_rp_endofpacket; // uart_0_s1_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_008:sink_valid
wire [107:0] router_010_src_data; // router_010:src_data -> rsp_demux_008:sink_data
wire router_010_src_ready; // rsp_demux_008:sink_ready -> router_010:src_ready
wire [9:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_008:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_011:sink_valid
wire [107:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_011:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_011:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_011:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_009:sink_valid
wire [107:0] router_011_src_data; // router_011:src_data -> rsp_demux_009:sink_data
wire router_011_src_ready; // rsp_demux_009:sink_ready -> router_011:src_ready
wire [9:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_009:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire buffered_spi_0_avalon_burst_adapter_source0_valid; // buffered_spi_0_avalon_burst_adapter:source0_valid -> buffered_spi_0_avalon_agent:cp_valid
wire [89:0] buffered_spi_0_avalon_burst_adapter_source0_data; // buffered_spi_0_avalon_burst_adapter:source0_data -> buffered_spi_0_avalon_agent:cp_data
wire buffered_spi_0_avalon_burst_adapter_source0_ready; // buffered_spi_0_avalon_agent:cp_ready -> buffered_spi_0_avalon_burst_adapter:source0_ready
wire [9:0] buffered_spi_0_avalon_burst_adapter_source0_channel; // buffered_spi_0_avalon_burst_adapter:source0_channel -> buffered_spi_0_avalon_agent:cp_channel
wire buffered_spi_0_avalon_burst_adapter_source0_startofpacket; // buffered_spi_0_avalon_burst_adapter:source0_startofpacket -> buffered_spi_0_avalon_agent:cp_startofpacket
wire buffered_spi_0_avalon_burst_adapter_source0_endofpacket; // buffered_spi_0_avalon_burst_adapter:source0_endofpacket -> buffered_spi_0_avalon_agent:cp_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_valid; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_data; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_data
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_ready -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_channel; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_channel -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_channel
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:source0_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_agent:cp_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_data; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_channel; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_channel
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:source0_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [107:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [9:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
wire [107:0] cmd_demux_src1_data; // cmd_demux:src1_data -> cmd_mux_001:sink0_data
wire cmd_demux_src1_ready; // cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
wire [9:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_src2_valid; // cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
wire [107:0] cmd_demux_src2_data; // cmd_demux:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
wire [9:0] cmd_demux_src2_channel; // cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_src2_startofpacket; // cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_src2_endofpacket; // cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_src3_valid; // cmd_demux:src3_valid -> cmd_mux_003:sink0_valid
wire [107:0] cmd_demux_src3_data; // cmd_demux:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux:src3_ready
wire [9:0] cmd_demux_src3_channel; // cmd_demux:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_src3_startofpacket; // cmd_demux:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_src3_endofpacket; // cmd_demux:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_src4_valid; // cmd_demux:src4_valid -> cmd_mux_004:sink0_valid
wire [107:0] cmd_demux_src4_data; // cmd_demux:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux:src4_ready
wire [9:0] cmd_demux_src4_channel; // cmd_demux:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_src4_startofpacket; // cmd_demux:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_src4_endofpacket; // cmd_demux:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_src5_valid; // cmd_demux:src5_valid -> cmd_mux_005:sink0_valid
wire [107:0] cmd_demux_src5_data; // cmd_demux:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux:src5_ready
wire [9:0] cmd_demux_src5_channel; // cmd_demux:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_src5_startofpacket; // cmd_demux:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_src5_endofpacket; // cmd_demux:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_src7_valid; // cmd_demux:src7_valid -> cmd_mux_007:sink0_valid
wire [107:0] cmd_demux_src7_data; // cmd_demux:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux:src7_ready
wire [9:0] cmd_demux_src7_channel; // cmd_demux:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_src7_startofpacket; // cmd_demux:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_src7_endofpacket; // cmd_demux:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_src8_valid; // cmd_demux:src8_valid -> cmd_mux_008:sink0_valid
wire [107:0] cmd_demux_src8_data; // cmd_demux:src8_data -> cmd_mux_008:sink0_data
wire cmd_demux_src8_ready; // cmd_mux_008:sink0_ready -> cmd_demux:src8_ready
wire [9:0] cmd_demux_src8_channel; // cmd_demux:src8_channel -> cmd_mux_008:sink0_channel
wire cmd_demux_src8_startofpacket; // cmd_demux:src8_startofpacket -> cmd_mux_008:sink0_startofpacket
wire cmd_demux_src8_endofpacket; // cmd_demux:src8_endofpacket -> cmd_mux_008:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> cmd_mux_005:sink1_valid
wire [107:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> cmd_mux_005:sink1_data
wire cmd_demux_001_src0_ready; // cmd_mux_005:sink1_ready -> cmd_demux_001:src0_ready
wire [9:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> cmd_mux_005:sink1_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> cmd_mux_005:sink1_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> cmd_mux_005:sink1_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_007:sink1_valid
wire [107:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_007:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_007:sink1_ready -> cmd_demux_001:src1_ready
wire [9:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_007:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_009:sink0_valid
wire [107:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_009:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_009:sink0_ready -> cmd_demux_001:src2_ready
wire [9:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_009:sink0_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [107:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [9:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
wire [107:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> rsp_mux:sink1_data
wire rsp_demux_001_src0_ready; // rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
wire [9:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
wire [107:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
wire [9:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux:sink3_valid
wire [107:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux:sink3_ready -> rsp_demux_003:src0_ready
wire [9:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux:sink4_valid
wire [107:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux:sink4_ready -> rsp_demux_004:src0_ready
wire [9:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux:sink5_valid
wire [107:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux:sink5_ready -> rsp_demux_005:src0_ready
wire [9:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux:sink5_endofpacket
wire rsp_demux_005_src1_valid; // rsp_demux_005:src1_valid -> rsp_mux_001:sink0_valid
wire [107:0] rsp_demux_005_src1_data; // rsp_demux_005:src1_data -> rsp_mux_001:sink0_data
wire rsp_demux_005_src1_ready; // rsp_mux_001:sink0_ready -> rsp_demux_005:src1_ready
wire [9:0] rsp_demux_005_src1_channel; // rsp_demux_005:src1_channel -> rsp_mux_001:sink0_channel
wire rsp_demux_005_src1_startofpacket; // rsp_demux_005:src1_startofpacket -> rsp_mux_001:sink0_startofpacket
wire rsp_demux_005_src1_endofpacket; // rsp_demux_005:src1_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux:sink7_valid
wire [107:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux:sink7_ready -> rsp_demux_007:src0_ready
wire [9:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_001:sink1_valid
wire [107:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_007_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_007:src1_ready
wire [9:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> rsp_mux:sink8_valid
wire [107:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> rsp_mux:sink8_data
wire rsp_demux_008_src0_ready; // rsp_mux:sink8_ready -> rsp_demux_008:src0_ready
wire [9:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> rsp_mux:sink8_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> rsp_mux:sink8_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> rsp_mux:sink8_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux_001:sink2_valid
wire [107:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_009_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_009:src0_ready
wire [9:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire router_002_src_valid; // router_002:src_valid -> buffered_spi_0_avalon_rsp_width_adapter:in_valid
wire [89:0] router_002_src_data; // router_002:src_data -> buffered_spi_0_avalon_rsp_width_adapter:in_data
wire router_002_src_ready; // buffered_spi_0_avalon_rsp_width_adapter:in_ready -> router_002:src_ready
wire [9:0] router_002_src_channel; // router_002:src_channel -> buffered_spi_0_avalon_rsp_width_adapter:in_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> buffered_spi_0_avalon_rsp_width_adapter:in_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> buffered_spi_0_avalon_rsp_width_adapter:in_endofpacket
wire buffered_spi_0_avalon_rsp_width_adapter_src_valid; // buffered_spi_0_avalon_rsp_width_adapter:out_valid -> rsp_demux:sink_valid
wire [107:0] buffered_spi_0_avalon_rsp_width_adapter_src_data; // buffered_spi_0_avalon_rsp_width_adapter:out_data -> rsp_demux:sink_data
wire buffered_spi_0_avalon_rsp_width_adapter_src_ready; // rsp_demux:sink_ready -> buffered_spi_0_avalon_rsp_width_adapter:out_ready
wire [9:0] buffered_spi_0_avalon_rsp_width_adapter_src_channel; // buffered_spi_0_avalon_rsp_width_adapter:out_channel -> rsp_demux:sink_channel
wire buffered_spi_0_avalon_rsp_width_adapter_src_startofpacket; // buffered_spi_0_avalon_rsp_width_adapter:out_startofpacket -> rsp_demux:sink_startofpacket
wire buffered_spi_0_avalon_rsp_width_adapter_src_endofpacket; // buffered_spi_0_avalon_rsp_width_adapter:out_endofpacket -> rsp_demux:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_valid
wire [89:0] router_004_src_data; // router_004:src_data -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_data
wire router_004_src_ready; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_ready -> router_004:src_ready
wire [9:0] router_004_src_channel; // router_004:src_channel -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_valid -> rsp_demux_002:sink_valid
wire [107:0] abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_data -> rsp_demux_002:sink_data
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_ready; // rsp_demux_002:sink_ready -> abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_channel -> rsp_demux_002:sink_channel
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_startofpacket -> rsp_demux_002:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter:out_endofpacket -> rsp_demux_002:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_valid
wire [89:0] router_006_src_data; // router_006:src_data -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_data
wire router_006_src_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_ready -> router_006:src_ready
wire [9:0] router_006_src_channel; // router_006:src_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_valid -> rsp_demux_004:sink_valid
wire [107:0] abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_data -> rsp_demux_004:sink_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_ready; // rsp_demux_004:sink_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_channel -> rsp_demux_004:sink_channel
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_startofpacket -> rsp_demux_004:sink_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter:out_endofpacket -> rsp_demux_004:sink_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> buffered_spi_0_avalon_cmd_width_adapter:in_valid
wire [107:0] cmd_mux_src_data; // cmd_mux:src_data -> buffered_spi_0_avalon_cmd_width_adapter:in_data
wire cmd_mux_src_ready; // buffered_spi_0_avalon_cmd_width_adapter:in_ready -> cmd_mux:src_ready
wire [9:0] cmd_mux_src_channel; // cmd_mux:src_channel -> buffered_spi_0_avalon_cmd_width_adapter:in_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> buffered_spi_0_avalon_cmd_width_adapter:in_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> buffered_spi_0_avalon_cmd_width_adapter:in_endofpacket
wire buffered_spi_0_avalon_cmd_width_adapter_src_valid; // buffered_spi_0_avalon_cmd_width_adapter:out_valid -> buffered_spi_0_avalon_burst_adapter:sink0_valid
wire [89:0] buffered_spi_0_avalon_cmd_width_adapter_src_data; // buffered_spi_0_avalon_cmd_width_adapter:out_data -> buffered_spi_0_avalon_burst_adapter:sink0_data
wire buffered_spi_0_avalon_cmd_width_adapter_src_ready; // buffered_spi_0_avalon_burst_adapter:sink0_ready -> buffered_spi_0_avalon_cmd_width_adapter:out_ready
wire [9:0] buffered_spi_0_avalon_cmd_width_adapter_src_channel; // buffered_spi_0_avalon_cmd_width_adapter:out_channel -> buffered_spi_0_avalon_burst_adapter:sink0_channel
wire buffered_spi_0_avalon_cmd_width_adapter_src_startofpacket; // buffered_spi_0_avalon_cmd_width_adapter:out_startofpacket -> buffered_spi_0_avalon_burst_adapter:sink0_startofpacket
wire buffered_spi_0_avalon_cmd_width_adapter_src_endofpacket; // buffered_spi_0_avalon_cmd_width_adapter:out_endofpacket -> buffered_spi_0_avalon_burst_adapter:sink0_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_valid
wire [107:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_data
wire cmd_mux_002_src_ready; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_ready -> cmd_mux_002:src_ready
wire [9:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_valid -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_data -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_data
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_ready; // abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_ready -> abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_channel -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_channel
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter:sink0_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_valid
wire [107:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_data
wire cmd_mux_004_src_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_ready -> cmd_mux_004:src_ready
wire [9:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:in_endofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_valid
wire [89:0] abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_data; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_data -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_ready
wire [9:0] abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_channel; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_channel -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_channel
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_startofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_startofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_startofpacket
wire abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_endofpacket; // abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter:out_endofpacket -> abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter:sink0_endofpacket
wire cmd_demux_src6_valid; // cmd_demux:src6_valid -> crosser:in_valid
wire [107:0] cmd_demux_src6_data; // cmd_demux:src6_data -> crosser:in_data
wire cmd_demux_src6_ready; // crosser:in_ready -> cmd_demux:src6_ready
wire [9:0] cmd_demux_src6_channel; // cmd_demux:src6_channel -> crosser:in_channel
wire cmd_demux_src6_startofpacket; // cmd_demux:src6_startofpacket -> crosser:in_startofpacket
wire cmd_demux_src6_endofpacket; // cmd_demux:src6_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_006:sink0_valid
wire [107:0] crosser_out_data; // crosser:out_data -> cmd_mux_006:sink0_data
wire crosser_out_ready; // cmd_mux_006:sink0_ready -> crosser:out_ready
wire [9:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_006:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_006:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_006:sink0_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> crosser_001:in_valid
wire [107:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> crosser_001:in_data
wire rsp_demux_006_src0_ready; // crosser_001:in_ready -> rsp_demux_006:src0_ready
wire [9:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> crosser_001:in_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> crosser_001:in_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_mux:sink6_valid
wire [107:0] crosser_001_out_data; // crosser_001:out_data -> rsp_mux:sink6_data
wire crosser_001_out_ready; // rsp_mux:sink6_ready -> crosser_001:out_ready
wire [9:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_mux:sink6_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_mux:sink6_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_mux:sink6_endofpacket
wire buffered_spi_0_avalon_agent_rdata_fifo_src_valid; // buffered_spi_0_avalon_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
wire [17:0] buffered_spi_0_avalon_agent_rdata_fifo_src_data; // buffered_spi_0_avalon_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
wire buffered_spi_0_avalon_agent_rdata_fifo_src_ready; // avalon_st_adapter:in_0_ready -> buffered_spi_0_avalon_agent:rdata_fifo_src_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> buffered_spi_0_avalon_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> buffered_spi_0_avalon_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // buffered_spi_0_avalon_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> buffered_spi_0_avalon_agent:rdata_fifo_sink_error
wire audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid; // audio_0_avalon_audio_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] audio_0_avalon_audio_slave_agent_rdata_fifo_src_data; // audio_0_avalon_audio_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> audio_0_avalon_audio_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // audio_0_avalon_audio_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> audio_0_avalon_audio_slave_agent:rdata_fifo_sink_error
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_valid; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [17:0] abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_data; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> abus_avalon_sdram_bridge_0_avalon_regs_agent:rdata_fifo_sink_error
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_valid; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_data; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_agent:rdata_fifo_sink_error
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_valid; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [17:0] abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_data; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> abus_avalon_sdram_bridge_0_avalon_sdram_agent:rdata_fifo_sink_error
wire onchip_flash_0_data_agent_rdata_fifo_src_valid; // onchip_flash_0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] onchip_flash_0_data_agent_rdata_fifo_src_data; // onchip_flash_0_data_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire onchip_flash_0_data_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> onchip_flash_0_data_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> onchip_flash_0_data_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> onchip_flash_0_data_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // onchip_flash_0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> onchip_flash_0_data_agent:rdata_fifo_sink_error
wire altpll_1_pll_slave_agent_rdata_fifo_out_valid; // altpll_1_pll_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] altpll_1_pll_slave_agent_rdata_fifo_out_data; // altpll_1_pll_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_006:in_0_data
wire altpll_1_pll_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_006:in_0_ready -> altpll_1_pll_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> altpll_1_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> altpll_1_pll_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // altpll_1_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> altpll_1_pll_slave_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire uart_0_s1_agent_rdata_fifo_src_valid; // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] uart_0_s1_agent_rdata_fifo_src_data; // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_008:in_0_data
wire uart_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_008:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_009_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (27),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_gen2_0_data_master_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (20),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (14),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) buffered_spi_0_avalon_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (buffered_spi_0_avalon_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (buffered_spi_0_avalon_agent_m0_burstcount), // .burstcount
.uav_read (buffered_spi_0_avalon_agent_m0_read), // .read
.uav_write (buffered_spi_0_avalon_agent_m0_write), // .write
.uav_waitrequest (buffered_spi_0_avalon_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (buffered_spi_0_avalon_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (buffered_spi_0_avalon_agent_m0_byteenable), // .byteenable
.uav_readdata (buffered_spi_0_avalon_agent_m0_readdata), // .readdata
.uav_writedata (buffered_spi_0_avalon_agent_m0_writedata), // .writedata
.uav_lock (buffered_spi_0_avalon_agent_m0_lock), // .lock
.uav_debugaccess (buffered_spi_0_avalon_agent_m0_debugaccess), // .debugaccess
.av_address (buffered_spi_0_avalon_address), // avalon_anti_slave_0.address
.av_write (buffered_spi_0_avalon_write), // .write
.av_read (buffered_spi_0_avalon_read), // .read
.av_readdata (buffered_spi_0_avalon_readdata), // .readdata
.av_writedata (buffered_spi_0_avalon_writedata), // .writedata
.av_readdatavalid (buffered_spi_0_avalon_readdatavalid), // .readdatavalid
.av_waitrequest (buffered_spi_0_avalon_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) audio_0_avalon_audio_slave_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (audio_0_avalon_audio_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (audio_0_avalon_audio_slave_agent_m0_burstcount), // .burstcount
.uav_read (audio_0_avalon_audio_slave_agent_m0_read), // .read
.uav_write (audio_0_avalon_audio_slave_agent_m0_write), // .write
.uav_waitrequest (audio_0_avalon_audio_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (audio_0_avalon_audio_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (audio_0_avalon_audio_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (audio_0_avalon_audio_slave_agent_m0_readdata), // .readdata
.uav_writedata (audio_0_avalon_audio_slave_agent_m0_writedata), // .writedata
.uav_lock (audio_0_avalon_audio_slave_agent_m0_lock), // .lock
.uav_debugaccess (audio_0_avalon_audio_slave_agent_m0_debugaccess), // .debugaccess
.av_address (audio_0_avalon_audio_slave_address), // avalon_anti_slave_0.address
.av_write (audio_0_avalon_audio_slave_write), // .write
.av_read (audio_0_avalon_audio_slave_read), // .read
.av_readdata (audio_0_avalon_audio_slave_readdata), // .readdata
.av_writedata (audio_0_avalon_audio_slave_writedata), // .writedata
.av_chipselect (audio_0_avalon_audio_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) abus_avalon_sdram_bridge_0_avalon_regs_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_burstcount), // .burstcount
.uav_read (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_read), // .read
.uav_write (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_write), // .write
.uav_waitrequest (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_byteenable), // .byteenable
.uav_readdata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdata), // .readdata
.uav_writedata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_writedata), // .writedata
.uav_lock (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_lock), // .lock
.uav_debugaccess (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_debugaccess), // .debugaccess
.av_address (abus_avalon_sdram_bridge_0_avalon_regs_address), // avalon_anti_slave_0.address
.av_write (abus_avalon_sdram_bridge_0_avalon_regs_write), // .write
.av_read (abus_avalon_sdram_bridge_0_avalon_regs_read), // .read
.av_readdata (abus_avalon_sdram_bridge_0_avalon_regs_readdata), // .readdata
.av_writedata (abus_avalon_sdram_bridge_0_avalon_regs_writedata), // .writedata
.av_readdatavalid (abus_avalon_sdram_bridge_0_avalon_regs_readdatavalid), // .readdatavalid
.av_waitrequest (abus_avalon_sdram_bridge_0_avalon_regs_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_burstcount), // .burstcount
.uav_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_read), // .read
.uav_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_write), // .write
.uav_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdata), // .readdata
.uav_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_writedata), // .writedata
.uav_lock (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_lock), // .lock
.uav_debugaccess (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_debugaccess), // .debugaccess
.av_address (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address), // avalon_anti_slave_0.address
.av_write (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write), // .write
.av_read (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read), // .read
.av_readdata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata), // .readdata
.av_writedata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata), // .writedata
.av_byteenable (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable), // .byteenable
.av_waitrequest (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest), // .waitrequest
.av_chipselect (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (26),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (1),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (25),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_burstcount), // .burstcount
.uav_read (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_read), // .read
.uav_write (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_write), // .write
.uav_waitrequest (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_byteenable), // .byteenable
.uav_readdata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdata), // .readdata
.uav_writedata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_writedata), // .writedata
.uav_lock (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_lock), // .lock
.uav_debugaccess (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_debugaccess), // .debugaccess
.av_address (abus_avalon_sdram_bridge_0_avalon_sdram_address), // avalon_anti_slave_0.address
.av_write (abus_avalon_sdram_bridge_0_avalon_sdram_write), // .write
.av_read (abus_avalon_sdram_bridge_0_avalon_sdram_read), // .read
.av_readdata (abus_avalon_sdram_bridge_0_avalon_sdram_readdata), // .readdata
.av_writedata (abus_avalon_sdram_bridge_0_avalon_sdram_writedata), // .writedata
.av_byteenable (abus_avalon_sdram_bridge_0_avalon_sdram_byteenable), // .byteenable
.av_readdatavalid (abus_avalon_sdram_bridge_0_avalon_sdram_readdatavalid), // .readdatavalid
.av_waitrequest (abus_avalon_sdram_bridge_0_avalon_sdram_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (16),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_flash_0_data_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_flash_0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.uav_read (onchip_flash_0_data_agent_m0_read), // .read
.uav_write (onchip_flash_0_data_agent_m0_write), // .write
.uav_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.uav_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.uav_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.uav_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_flash_0_data_address), // avalon_anti_slave_0.address
.av_read (onchip_flash_0_data_read), // .read
.av_readdata (onchip_flash_0_data_readdata), // .readdata
.av_burstcount (onchip_flash_0_data_burstcount), // .burstcount
.av_readdatavalid (onchip_flash_0_data_readdatavalid), // .readdatavalid
.av_waitrequest (onchip_flash_0_data_waitrequest), // .waitrequest
.av_write (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altpll_1_pll_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altpll_1_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altpll_1_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (altpll_1_pll_slave_agent_m0_read), // .read
.uav_write (altpll_1_pll_slave_agent_m0_write), // .write
.uav_waitrequest (altpll_1_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altpll_1_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altpll_1_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altpll_1_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (altpll_1_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (altpll_1_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (altpll_1_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (altpll_1_pll_slave_address), // avalon_anti_slave_0.address
.av_write (altpll_1_pll_slave_write), // .write
.av_read (altpll_1_pll_slave_read), // .read
.av_readdata (altpll_1_pll_slave_readdata), // .readdata
.av_writedata (altpll_1_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (12),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_0_s1_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_0_s1_agent_m0_read), // .read
.uav_write (uart_0_s1_agent_m0_write), // .write
.uav_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_0_s1_address), // avalon_anti_slave_0.address
.av_write (uart_0_s1_write), // .write
.av_read (uart_0_s1_read), // .read
.av_readdata (uart_0_s1_readdata), // .readdata
.av_writedata (uart_0_s1_writedata), // .writedata
.av_begintransfer (uart_0_s1_begintransfer), // .begintransfer
.av_chipselect (uart_0_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (27),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (86),
.PKT_QOS_L (86),
.PKT_DATA_SIDEBAND_H (84),
.PKT_DATA_SIDEBAND_L (84),
.PKT_ADDR_SIDEBAND_H (83),
.PKT_ADDR_SIDEBAND_L (83),
.PKT_BURST_TYPE_H (82),
.PKT_BURST_TYPE_L (81),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.ST_DATA_W (108),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_src_valid), // rp.valid
.rp_data (rsp_mux_src_data), // .data
.rp_channel (rsp_mux_src_channel), // .channel
.rp_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_QOS_H (86),
.PKT_QOS_L (86),
.PKT_DATA_SIDEBAND_H (84),
.PKT_DATA_SIDEBAND_L (84),
.PKT_ADDR_SIDEBAND_H (83),
.PKT_ADDR_SIDEBAND_L (83),
.PKT_BURST_TYPE_H (82),
.PKT_BURST_TYPE_L (81),
.PKT_CACHE_H (102),
.PKT_CACHE_L (99),
.PKT_THREAD_ID_H (95),
.PKT_THREAD_ID_L (95),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_EXCLUSIVE (68),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.ST_DATA_W (108),
.ST_CHANNEL_W (10),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (67),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (69),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) buffered_spi_0_avalon_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (buffered_spi_0_avalon_agent_m0_address), // m0.address
.m0_burstcount (buffered_spi_0_avalon_agent_m0_burstcount), // .burstcount
.m0_byteenable (buffered_spi_0_avalon_agent_m0_byteenable), // .byteenable
.m0_debugaccess (buffered_spi_0_avalon_agent_m0_debugaccess), // .debugaccess
.m0_lock (buffered_spi_0_avalon_agent_m0_lock), // .lock
.m0_readdata (buffered_spi_0_avalon_agent_m0_readdata), // .readdata
.m0_readdatavalid (buffered_spi_0_avalon_agent_m0_readdatavalid), // .readdatavalid
.m0_read (buffered_spi_0_avalon_agent_m0_read), // .read
.m0_waitrequest (buffered_spi_0_avalon_agent_m0_waitrequest), // .waitrequest
.m0_writedata (buffered_spi_0_avalon_agent_m0_writedata), // .writedata
.m0_write (buffered_spi_0_avalon_agent_m0_write), // .write
.rp_endofpacket (buffered_spi_0_avalon_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (buffered_spi_0_avalon_agent_rp_ready), // .ready
.rp_valid (buffered_spi_0_avalon_agent_rp_valid), // .valid
.rp_data (buffered_spi_0_avalon_agent_rp_data), // .data
.rp_startofpacket (buffered_spi_0_avalon_agent_rp_startofpacket), // .startofpacket
.cp_ready (buffered_spi_0_avalon_burst_adapter_source0_ready), // cp.ready
.cp_valid (buffered_spi_0_avalon_burst_adapter_source0_valid), // .valid
.cp_data (buffered_spi_0_avalon_burst_adapter_source0_data), // .data
.cp_startofpacket (buffered_spi_0_avalon_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (buffered_spi_0_avalon_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (buffered_spi_0_avalon_burst_adapter_source0_channel), // .channel
.rf_sink_ready (buffered_spi_0_avalon_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (buffered_spi_0_avalon_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (buffered_spi_0_avalon_agent_rsp_fifo_out_data), // .data
.rf_source_ready (buffered_spi_0_avalon_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (buffered_spi_0_avalon_agent_rf_source_valid), // .valid
.rf_source_startofpacket (buffered_spi_0_avalon_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (buffered_spi_0_avalon_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (buffered_spi_0_avalon_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (buffered_spi_0_avalon_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (buffered_spi_0_avalon_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (buffered_spi_0_avalon_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) buffered_spi_0_avalon_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (buffered_spi_0_avalon_agent_rf_source_data), // in.data
.in_valid (buffered_spi_0_avalon_agent_rf_source_valid), // .valid
.in_ready (buffered_spi_0_avalon_agent_rf_source_ready), // .ready
.in_startofpacket (buffered_spi_0_avalon_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (buffered_spi_0_avalon_agent_rf_source_endofpacket), // .endofpacket
.out_data (buffered_spi_0_avalon_agent_rsp_fifo_out_data), // out.data
.out_valid (buffered_spi_0_avalon_agent_rsp_fifo_out_valid), // .valid
.out_ready (buffered_spi_0_avalon_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (buffered_spi_0_avalon_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) audio_0_avalon_audio_slave_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (audio_0_avalon_audio_slave_agent_m0_address), // m0.address
.m0_burstcount (audio_0_avalon_audio_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (audio_0_avalon_audio_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (audio_0_avalon_audio_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (audio_0_avalon_audio_slave_agent_m0_lock), // .lock
.m0_readdata (audio_0_avalon_audio_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (audio_0_avalon_audio_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (audio_0_avalon_audio_slave_agent_m0_read), // .read
.m0_waitrequest (audio_0_avalon_audio_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (audio_0_avalon_audio_slave_agent_m0_writedata), // .writedata
.m0_write (audio_0_avalon_audio_slave_agent_m0_write), // .write
.rp_endofpacket (audio_0_avalon_audio_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (audio_0_avalon_audio_slave_agent_rp_ready), // .ready
.rp_valid (audio_0_avalon_audio_slave_agent_rp_valid), // .valid
.rp_data (audio_0_avalon_audio_slave_agent_rp_data), // .data
.rp_startofpacket (audio_0_avalon_audio_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (audio_0_avalon_audio_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (audio_0_avalon_audio_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (audio_0_avalon_audio_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (audio_0_avalon_audio_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (audio_0_avalon_audio_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (audio_0_avalon_audio_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (audio_0_avalon_audio_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) audio_0_avalon_audio_slave_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (audio_0_avalon_audio_slave_agent_rf_source_data), // in.data
.in_valid (audio_0_avalon_audio_slave_agent_rf_source_valid), // .valid
.in_ready (audio_0_avalon_audio_slave_agent_rf_source_ready), // .ready
.in_startofpacket (audio_0_avalon_audio_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (audio_0_avalon_audio_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (audio_0_avalon_audio_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (audio_0_avalon_audio_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (audio_0_avalon_audio_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (audio_0_avalon_audio_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (67),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (69),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) abus_avalon_sdram_bridge_0_avalon_regs_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_address), // m0.address
.m0_burstcount (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_burstcount), // .burstcount
.m0_byteenable (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_byteenable), // .byteenable
.m0_debugaccess (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_debugaccess), // .debugaccess
.m0_lock (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_lock), // .lock
.m0_readdata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdata), // .readdata
.m0_readdatavalid (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_readdatavalid), // .readdatavalid
.m0_read (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_read), // .read
.m0_waitrequest (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_waitrequest), // .waitrequest
.m0_writedata (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_writedata), // .writedata
.m0_write (abus_avalon_sdram_bridge_0_avalon_regs_agent_m0_write), // .write
.rp_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_ready), // .ready
.rp_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_valid), // .valid
.rp_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_data), // .data
.rp_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_startofpacket), // .startofpacket
.cp_ready (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_ready), // cp.ready
.cp_valid (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_valid), // .valid
.cp_data (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_data), // .data
.cp_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_channel), // .channel
.rf_sink_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_data), // .data
.rf_source_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_valid), // .valid
.rf_source_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_data), // in.data
.in_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_valid), // .valid
.in_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_ready), // .ready
.in_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rf_source_endofpacket), // .endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_data), // out.data
.out_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_address), // m0.address
.m0_burstcount (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_lock), // .lock
.m0_readdata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_read), // .read
.m0_waitrequest (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_writedata), // .writedata
.m0_write (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_m0_write), // .write
.rp_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_ready), // .ready
.rp_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_valid), // .valid
.rp_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_data), // .data
.rp_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_data), // in.data
.in_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_valid), // .valid
.in_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (89),
.PKT_ORI_BURST_SIZE_L (87),
.PKT_RESPONSE_STATUS_H (86),
.PKT_RESPONSE_STATUS_L (85),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_TRANS_LOCK (49),
.PKT_BEGIN_BURST (67),
.PKT_PROTECTION_H (80),
.PKT_PROTECTION_L (78),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_POSTED (46),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (72),
.PKT_SRC_ID_L (69),
.PKT_DEST_ID_H (76),
.PKT_DEST_ID_L (73),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (90),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_address), // m0.address
.m0_burstcount (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_burstcount), // .burstcount
.m0_byteenable (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_byteenable), // .byteenable
.m0_debugaccess (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_debugaccess), // .debugaccess
.m0_lock (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_lock), // .lock
.m0_readdata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdata), // .readdata
.m0_readdatavalid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_readdatavalid), // .readdatavalid
.m0_read (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_read), // .read
.m0_waitrequest (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_waitrequest), // .waitrequest
.m0_writedata (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_writedata), // .writedata
.m0_write (abus_avalon_sdram_bridge_0_avalon_sdram_agent_m0_write), // .write
.rp_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_ready), // .ready
.rp_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_valid), // .valid
.rp_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_data), // .data
.rp_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_startofpacket), // .startofpacket
.cp_ready (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_ready), // cp.ready
.cp_valid (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_valid), // .valid
.cp_data (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_data), // .data
.cp_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_channel), // .channel
.rf_sink_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_data), // .data
.rf_source_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_valid), // .valid
.rf_source_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (91),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_data), // in.data
.in_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_valid), // .valid
.in_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_ready), // .ready
.in_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rf_source_endofpacket), // .endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_data), // out.data
.out_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_flash_0_data_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_flash_0_data_agent_m0_address), // m0.address
.m0_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.m0_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_flash_0_data_agent_m0_read), // .read
.m0_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.m0_write (onchip_flash_0_data_agent_m0_write), // .write
.rp_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_flash_0_data_agent_rp_ready), // .ready
.rp_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.rp_data (onchip_flash_0_data_agent_rp_data), // .data
.rp_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_flash_0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_flash_0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_flash_0_data_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_flash_0_data_agent_rf_source_data), // in.data
.in_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.in_ready (onchip_flash_0_data_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altpll_1_pll_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altpll_1_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (altpll_1_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altpll_1_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altpll_1_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altpll_1_pll_slave_agent_m0_lock), // .lock
.m0_readdata (altpll_1_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altpll_1_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altpll_1_pll_slave_agent_m0_read), // .read
.m0_waitrequest (altpll_1_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altpll_1_pll_slave_agent_m0_writedata), // .writedata
.m0_write (altpll_1_pll_slave_agent_m0_write), // .write
.rp_endofpacket (altpll_1_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altpll_1_pll_slave_agent_rp_ready), // .ready
.rp_valid (altpll_1_pll_slave_agent_rp_valid), // .valid
.rp_data (altpll_1_pll_slave_agent_rp_data), // .data
.rp_startofpacket (altpll_1_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (altpll_1_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altpll_1_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altpll_1_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altpll_1_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altpll_1_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altpll_1_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altpll_1_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altpll_1_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (altpll_1_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altpll_1_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altpll_1_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_1_pll_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_1_pll_slave_agent_rf_source_data), // in.data
.in_valid (altpll_1_pll_slave_agent_rf_source_valid), // .valid
.in_ready (altpll_1_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altpll_1_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altpll_1_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altpll_1_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altpll_1_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altpll_1_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altpll_1_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_1_pll_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_1_pll_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (altpll_1_pll_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (altpll_1_pll_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (altpll_1_pll_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (altpll_1_pll_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (altpll_1_pll_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_0_s1_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_0_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_0_s1_agent_m0_lock), // .lock
.m0_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_0_s1_agent_m0_read), // .read
.m0_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.m0_write (uart_0_s1_agent_m0_write), // .write
.rp_endofpacket (uart_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_0_s1_agent_rp_ready), // .ready
.rp_valid (uart_0_s1_agent_rp_valid), // .valid
.rp_data (uart_0_s1_agent_rp_data), // .data
.rp_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (uart_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (uart_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_0_s1_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_0_s1_agent_rf_source_data), // in.data
.in_valid (uart_0_s1_agent_rf_source_valid), // .valid
.in_ready (uart_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (107),
.PKT_ORI_BURST_SIZE_L (105),
.PKT_RESPONSE_STATUS_H (104),
.PKT_RESPONSE_STATUS_L (103),
.PKT_BURST_SIZE_H (80),
.PKT_BURST_SIZE_L (78),
.PKT_TRANS_LOCK (67),
.PKT_BEGIN_BURST (85),
.PKT_PROTECTION_H (98),
.PKT_PROTECTION_L (96),
.PKT_BURSTWRAP_H (77),
.PKT_BURSTWRAP_L (75),
.PKT_BYTE_CNT_H (74),
.PKT_BYTE_CNT_L (69),
.PKT_ADDR_H (62),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (63),
.PKT_TRANS_POSTED (64),
.PKT_TRANS_WRITE (65),
.PKT_TRANS_READ (66),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (90),
.PKT_SRC_ID_L (87),
.PKT_DEST_ID_H (94),
.PKT_DEST_ID_L (91),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (10),
.ST_DATA_W (108),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (109),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
wasca_mm_interconnect_0_router router (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_002 (
.sink_ready (buffered_spi_0_avalon_agent_rp_ready), // sink.ready
.sink_valid (buffered_spi_0_avalon_agent_rp_valid), // .valid
.sink_data (buffered_spi_0_avalon_agent_rp_data), // .data
.sink_startofpacket (buffered_spi_0_avalon_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (buffered_spi_0_avalon_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_003 (
.sink_ready (audio_0_avalon_audio_slave_agent_rp_ready), // sink.ready
.sink_valid (audio_0_avalon_audio_slave_agent_rp_valid), // .valid
.sink_data (audio_0_avalon_audio_slave_agent_rp_data), // .data
.sink_startofpacket (audio_0_avalon_audio_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (audio_0_avalon_audio_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_004 (
.sink_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_ready), // sink.ready
.sink_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_valid), // .valid
.sink_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_005 (
.sink_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_ready), // sink.ready
.sink_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_valid), // .valid
.sink_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_data), // .data
.sink_startofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_006 (
.sink_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_ready), // sink.ready
.sink_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_valid), // .valid
.sink_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_007 (
.sink_ready (onchip_flash_0_data_agent_rp_ready), // sink.ready
.sink_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.sink_data (onchip_flash_0_data_agent_rp_data), // .data
.sink_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_008 (
.sink_ready (altpll_1_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (altpll_1_pll_slave_agent_rp_valid), // .valid
.sink_data (altpll_1_pll_slave_agent_rp_data), // .data
.sink_startofpacket (altpll_1_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altpll_1_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_007 router_009 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_010 (
.sink_ready (uart_0_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_0_s1_agent_rp_valid), // .valid
.sink_data (uart_0_s1_agent_rp_data), // .data
.sink_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_011 router_011 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (67),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_BURST_TYPE_H (64),
.PKT_BURST_TYPE_L (63),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (52),
.OUT_BURSTWRAP_H (59),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) buffered_spi_0_avalon_burst_adapter (
.clk (altpll_1_c0_clk), // cr0.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (buffered_spi_0_avalon_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (buffered_spi_0_avalon_cmd_width_adapter_src_data), // .data
.sink0_channel (buffered_spi_0_avalon_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (buffered_spi_0_avalon_cmd_width_adapter_src_ready), // .ready
.source0_valid (buffered_spi_0_avalon_burst_adapter_source0_valid), // source0.valid
.source0_data (buffered_spi_0_avalon_burst_adapter_source0_data), // .data
.source0_channel (buffered_spi_0_avalon_burst_adapter_source0_channel), // .channel
.source0_startofpacket (buffered_spi_0_avalon_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (buffered_spi_0_avalon_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (buffered_spi_0_avalon_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (67),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_BURST_TYPE_H (64),
.PKT_BURST_TYPE_L (63),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (52),
.OUT_BURSTWRAP_H (59),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter (
.clk (altpll_1_c0_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_data), // .data
.sink0_channel (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_ready), // .ready
.source0_valid (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_valid), // source0.valid
.source0_data (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_data), // .data
.source0_channel (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_channel), // .channel
.source0_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (abus_avalon_sdram_bridge_0_avalon_regs_burst_adapter_source0_ready) // .ready
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (44),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (67),
.PKT_BYTE_CNT_H (56),
.PKT_BYTE_CNT_L (51),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (62),
.PKT_BURST_SIZE_L (60),
.PKT_BURST_TYPE_H (64),
.PKT_BURST_TYPE_L (63),
.PKT_BURSTWRAP_H (59),
.PKT_BURSTWRAP_L (57),
.PKT_TRANS_COMPRESSED_READ (45),
.PKT_TRANS_WRITE (47),
.PKT_TRANS_READ (48),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OUT_BYTE_CNT_H (51),
.OUT_BURSTWRAP_H (59),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter (
.clk (altpll_1_c0_clk), // cr0.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_valid), // sink0.valid
.sink0_data (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_data), // .data
.sink0_channel (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_channel), // .channel
.sink0_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink0_ready (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_ready), // .ready
.source0_valid (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_valid), // source0.valid
.source0_data (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_data), // .data
.source0_channel (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_channel), // .channel
.source0_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (abus_avalon_sdram_bridge_0_avalon_sdram_burst_adapter_source0_ready) // .ready
);
wasca_mm_interconnect_0_cmd_demux cmd_demux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_src_ready), // sink.ready
.sink_channel (router_src_channel), // .channel
.sink_data (router_src_data), // .data
.sink_startofpacket (router_src_startofpacket), // .startofpacket
.sink_endofpacket (router_src_endofpacket), // .endofpacket
.sink_valid (router_src_valid), // .valid
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_src2_ready), // src2.ready
.src2_valid (cmd_demux_src2_valid), // .valid
.src2_data (cmd_demux_src2_data), // .data
.src2_channel (cmd_demux_src2_channel), // .channel
.src2_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_src3_ready), // src3.ready
.src3_valid (cmd_demux_src3_valid), // .valid
.src3_data (cmd_demux_src3_data), // .data
.src3_channel (cmd_demux_src3_channel), // .channel
.src3_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_src4_ready), // src4.ready
.src4_valid (cmd_demux_src4_valid), // .valid
.src4_data (cmd_demux_src4_data), // .data
.src4_channel (cmd_demux_src4_channel), // .channel
.src4_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_src5_ready), // src5.ready
.src5_valid (cmd_demux_src5_valid), // .valid
.src5_data (cmd_demux_src5_data), // .data
.src5_channel (cmd_demux_src5_channel), // .channel
.src5_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_src6_ready), // src6.ready
.src6_valid (cmd_demux_src6_valid), // .valid
.src6_data (cmd_demux_src6_data), // .data
.src6_channel (cmd_demux_src6_channel), // .channel
.src6_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_src7_ready), // src7.ready
.src7_valid (cmd_demux_src7_valid), // .valid
.src7_data (cmd_demux_src7_data), // .data
.src7_channel (cmd_demux_src7_channel), // .channel
.src7_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_src8_ready), // src8.ready
.src8_valid (cmd_demux_src8_valid), // .valid
.src8_data (cmd_demux_src8_data), // .data
.src8_channel (cmd_demux_src8_channel), // .channel
.src8_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src1_ready), // sink0.ready
.sink0_valid (cmd_demux_src1_valid), // .valid
.sink0_channel (cmd_demux_src1_channel), // .channel
.sink0_data (cmd_demux_src1_data), // .data
.sink0_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_002 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_src2_valid), // .valid
.sink0_channel (cmd_demux_src2_channel), // .channel
.sink0_data (cmd_demux_src2_data), // .data
.sink0_startofpacket (cmd_demux_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_003 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_src3_valid), // .valid
.sink0_channel (cmd_demux_src3_channel), // .channel
.sink0_data (cmd_demux_src3_data), // .data
.sink0_startofpacket (cmd_demux_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_004 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_src4_valid), // .valid
.sink0_channel (cmd_demux_src4_channel), // .channel
.sink0_data (cmd_demux_src4_data), // .data
.sink0_startofpacket (cmd_demux_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src4_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_005 cmd_mux_005 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_src5_valid), // .valid
.sink0_channel (cmd_demux_src5_channel), // .channel
.sink0_data (cmd_demux_src5_data), // .data
.sink0_startofpacket (cmd_demux_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src5_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src0_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src0_valid), // .valid
.sink1_channel (cmd_demux_001_src0_channel), // .channel
.sink1_data (cmd_demux_001_src0_data), // .data
.sink1_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_005 cmd_mux_007 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_src7_valid), // .valid
.sink0_channel (cmd_demux_src7_channel), // .channel
.sink0_data (cmd_demux_src7_data), // .data
.sink0_startofpacket (cmd_demux_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_008 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src8_ready), // sink0.ready
.sink0_valid (cmd_demux_src8_valid), // .valid
.sink0_channel (cmd_demux_src8_channel), // .channel
.sink0_data (cmd_demux_src8_data), // .data
.sink0_startofpacket (cmd_demux_src8_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src8_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux_009 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (buffered_spi_0_avalon_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (buffered_spi_0_avalon_rsp_width_adapter_src_channel), // .channel
.sink_data (buffered_spi_0_avalon_rsp_width_adapter_src_data), // .data
.sink_startofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (buffered_spi_0_avalon_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_002 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_channel), // .channel
.sink_data (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_003 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_004 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_ready), // sink.ready
.sink_channel (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_channel), // .channel
.sink_data (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_data), // .data
.sink_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink_valid (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_005 rsp_demux_005 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_005_src1_ready), // src1.ready
.src1_valid (rsp_demux_005_src1_valid), // .valid
.src1_data (rsp_demux_005_src1_data), // .data
.src1_channel (rsp_demux_005_src1_channel), // .channel
.src1_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_005_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_006 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_005 rsp_demux_007 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_008 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux_009 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux rsp_mux (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src0_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src0_valid), // .valid
.sink1_channel (rsp_demux_001_src0_channel), // .channel
.sink1_data (rsp_demux_001_src0_data), // .data
.sink1_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (crosser_001_out_ready), // sink6.ready
.sink6_valid (crosser_001_out_valid), // .valid
.sink6_channel (crosser_001_out_channel), // .channel
.sink6_data (crosser_001_out_data), // .data
.sink6_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink6_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (rsp_demux_008_src0_ready), // sink8.ready
.sink8_valid (rsp_demux_008_src0_valid), // .valid
.sink8_channel (rsp_demux_008_src0_channel), // .channel
.sink8_data (rsp_demux_008_src0_data), // .data
.sink8_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.sink8_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_005_src1_ready), // sink0.ready
.sink0_valid (rsp_demux_005_src1_valid), // .valid
.sink0_channel (rsp_demux_005_src1_channel), // .channel
.sink0_data (rsp_demux_005_src1_data), // .data
.sink0_startofpacket (rsp_demux_005_src1_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_005_src1_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_007_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_007_src1_valid), // .valid
.sink1_channel (rsp_demux_007_src1_channel), // .channel
.sink1_data (rsp_demux_007_src1_data), // .data
.sink1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_009_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_009_src0_valid), // .valid
.sink2_channel (rsp_demux_009_src0_channel), // .channel
.sink2_data (rsp_demux_009_src0_data), // .data
.sink2_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_009_src0_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (59),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (62),
.IN_PKT_BURST_SIZE_L (60),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (64),
.IN_PKT_BURST_TYPE_L (63),
.IN_PKT_ORI_BURST_SIZE_L (87),
.IN_PKT_ORI_BURST_SIZE_H (89),
.IN_ST_DATA_W (90),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (105),
.OUT_PKT_ORI_BURST_SIZE_H (107),
.OUT_ST_DATA_W (108),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) buffered_spi_0_avalon_rsp_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_002_src_valid), // sink.valid
.in_channel (router_002_src_channel), // .channel
.in_startofpacket (router_002_src_startofpacket), // .startofpacket
.in_endofpacket (router_002_src_endofpacket), // .endofpacket
.in_ready (router_002_src_ready), // .ready
.in_data (router_002_src_data), // .data
.out_endofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (buffered_spi_0_avalon_rsp_width_adapter_src_data), // .data
.out_channel (buffered_spi_0_avalon_rsp_width_adapter_src_channel), // .channel
.out_valid (buffered_spi_0_avalon_rsp_width_adapter_src_valid), // .valid
.out_ready (buffered_spi_0_avalon_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (buffered_spi_0_avalon_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (59),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (62),
.IN_PKT_BURST_SIZE_L (60),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (64),
.IN_PKT_BURST_TYPE_L (63),
.IN_PKT_ORI_BURST_SIZE_L (87),
.IN_PKT_ORI_BURST_SIZE_H (89),
.IN_ST_DATA_W (90),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (105),
.OUT_PKT_ORI_BURST_SIZE_H (107),
.OUT_ST_DATA_W (108),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_004_src_valid), // sink.valid
.in_channel (router_004_src_channel), // .channel
.in_startofpacket (router_004_src_startofpacket), // .startofpacket
.in_endofpacket (router_004_src_endofpacket), // .endofpacket
.in_ready (router_004_src_ready), // .ready
.in_data (router_004_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (44),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (56),
.IN_PKT_BYTE_CNT_L (51),
.IN_PKT_TRANS_COMPRESSED_READ (45),
.IN_PKT_TRANS_WRITE (47),
.IN_PKT_BURSTWRAP_H (59),
.IN_PKT_BURSTWRAP_L (57),
.IN_PKT_BURST_SIZE_H (62),
.IN_PKT_BURST_SIZE_L (60),
.IN_PKT_RESPONSE_STATUS_H (86),
.IN_PKT_RESPONSE_STATUS_L (85),
.IN_PKT_TRANS_EXCLUSIVE (50),
.IN_PKT_BURST_TYPE_H (64),
.IN_PKT_BURST_TYPE_L (63),
.IN_PKT_ORI_BURST_SIZE_L (87),
.IN_PKT_ORI_BURST_SIZE_H (89),
.IN_ST_DATA_W (90),
.OUT_PKT_ADDR_H (62),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (74),
.OUT_PKT_BYTE_CNT_L (69),
.OUT_PKT_TRANS_COMPRESSED_READ (63),
.OUT_PKT_BURST_SIZE_H (80),
.OUT_PKT_BURST_SIZE_L (78),
.OUT_PKT_RESPONSE_STATUS_H (104),
.OUT_PKT_RESPONSE_STATUS_L (103),
.OUT_PKT_TRANS_EXCLUSIVE (68),
.OUT_PKT_BURST_TYPE_H (82),
.OUT_PKT_BURST_TYPE_L (81),
.OUT_PKT_ORI_BURST_SIZE_L (105),
.OUT_PKT_ORI_BURST_SIZE_H (107),
.OUT_ST_DATA_W (108),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (router_006_src_valid), // sink.valid
.in_channel (router_006_src_channel), // .channel
.in_startofpacket (router_006_src_startofpacket), // .startofpacket
.in_endofpacket (router_006_src_endofpacket), // .endofpacket
.in_ready (router_006_src_ready), // .ready
.in_data (router_006_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (105),
.IN_PKT_ORI_BURST_SIZE_H (107),
.IN_ST_DATA_W (108),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (62),
.OUT_PKT_BURST_SIZE_L (60),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (64),
.OUT_PKT_BURST_TYPE_L (63),
.OUT_PKT_ORI_BURST_SIZE_L (87),
.OUT_PKT_ORI_BURST_SIZE_H (89),
.OUT_ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) buffered_spi_0_avalon_cmd_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_src_valid), // sink.valid
.in_channel (cmd_mux_src_channel), // .channel
.in_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_src_ready), // .ready
.in_data (cmd_mux_src_data), // .data
.out_endofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (buffered_spi_0_avalon_cmd_width_adapter_src_data), // .data
.out_channel (buffered_spi_0_avalon_cmd_width_adapter_src_channel), // .channel
.out_valid (buffered_spi_0_avalon_cmd_width_adapter_src_valid), // .valid
.out_ready (buffered_spi_0_avalon_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (buffered_spi_0_avalon_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (105),
.IN_PKT_ORI_BURST_SIZE_H (107),
.IN_ST_DATA_W (108),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (62),
.OUT_PKT_BURST_SIZE_L (60),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (64),
.OUT_PKT_BURST_TYPE_L (63),
.OUT_PKT_ORI_BURST_SIZE_L (87),
.OUT_PKT_ORI_BURST_SIZE_H (89),
.OUT_ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_002_src_valid), // sink.valid
.in_channel (cmd_mux_002_src_channel), // .channel
.in_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_002_src_ready), // .ready
.in_data (cmd_mux_002_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_regs_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (62),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (74),
.IN_PKT_BYTE_CNT_L (69),
.IN_PKT_TRANS_COMPRESSED_READ (63),
.IN_PKT_TRANS_WRITE (65),
.IN_PKT_BURSTWRAP_H (77),
.IN_PKT_BURSTWRAP_L (75),
.IN_PKT_BURST_SIZE_H (80),
.IN_PKT_BURST_SIZE_L (78),
.IN_PKT_RESPONSE_STATUS_H (104),
.IN_PKT_RESPONSE_STATUS_L (103),
.IN_PKT_TRANS_EXCLUSIVE (68),
.IN_PKT_BURST_TYPE_H (82),
.IN_PKT_BURST_TYPE_L (81),
.IN_PKT_ORI_BURST_SIZE_L (105),
.IN_PKT_ORI_BURST_SIZE_H (107),
.IN_ST_DATA_W (108),
.OUT_PKT_ADDR_H (44),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (56),
.OUT_PKT_BYTE_CNT_L (51),
.OUT_PKT_TRANS_COMPRESSED_READ (45),
.OUT_PKT_BURST_SIZE_H (62),
.OUT_PKT_BURST_SIZE_L (60),
.OUT_PKT_RESPONSE_STATUS_H (86),
.OUT_PKT_RESPONSE_STATUS_L (85),
.OUT_PKT_TRANS_EXCLUSIVE (50),
.OUT_PKT_BURST_TYPE_H (64),
.OUT_PKT_BURST_TYPE_L (63),
.OUT_PKT_ORI_BURST_SIZE_L (87),
.OUT_PKT_ORI_BURST_SIZE_H (89),
.OUT_ST_DATA_W (90),
.ST_CHANNEL_W (10),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter (
.clk (altpll_1_c0_clk), // clk.clk
.reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_mux_004_src_valid), // sink.valid
.in_channel (cmd_mux_004_src_channel), // .channel
.in_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.in_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.in_ready (cmd_mux_004_src_ready), // .ready
.in_data (cmd_mux_004_src_data), // .data
.out_endofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_data), // .data
.out_channel (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_channel), // .channel
.out_valid (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_valid), // .valid
.out_ready (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (abus_avalon_sdram_bridge_0_avalon_sdram_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (108),
.BITS_PER_SYMBOL (108),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (10),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (altpll_1_c0_clk), // in_clk.clk
.in_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_src6_ready), // in.ready
.in_valid (cmd_demux_src6_valid), // .valid
.in_startofpacket (cmd_demux_src6_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src6_endofpacket), // .endofpacket
.in_channel (cmd_demux_src6_channel), // .channel
.in_data (cmd_demux_src6_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (108),
.BITS_PER_SYMBOL (108),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (10),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_1_c0_clk), // out_clk.clk
.out_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_006_src0_ready), // in.ready
.in_valid (rsp_demux_006_src0_valid), // .valid
.in_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_006_src0_channel), // .channel
.in_data (rsp_demux_006_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (buffered_spi_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (buffered_spi_0_avalon_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (buffered_spi_0_avalon_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (buffered_spi_0_avalon_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (audio_0_avalon_audio_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (audio_0_avalon_audio_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (audio_0_avalon_audio_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (abus_avalon_sdram_bridge_0_avalon_regs_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (altera_up_sd_card_avalon_interface_0_avalon_sdcard_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (abus_avalon_sdram_bridge_0_avalon_sdram_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (altpll_1_inclk_interface_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altpll_1_pll_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (altpll_1_pll_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (altpll_1_pll_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_009 (
.in_clk_0_clk (altpll_1_c0_clk), // in_clk_0.clk
.in_rst_0_reset (nios2_gen2_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
);
endmodule
|
`include "alink_define.v"
module tx_phy(
input clk ,
input rst ,
input reg_flush ,
input reg_scan ,
input tx_phy_start ,
input [31:0] tx_phy_sel ,
output tx_phy_done ,
input [31:0] tx_dout ,//TxFIFO data input
output tx_rd_en ,//TxFIFO pop
output reg task_id_vld ,
output reg [31:0] rx_phy_sel ,
output reg [31:0] task_id_h ,
output reg [31:0] task_id_l ,
output reg [31:0] reg_tout ,
output [`PHY_NUM-1:0] TX_P ,
output [`PHY_NUM-1:0] TX_N
);
/*
__
tx_phy_start _____| |_____________________________________
_____ __ _____________________________________
tx_phy_sel _____|0 |_________________dont care___________
__
tx_phy_done ________________________________________| |__
__
task_id_vld _________________| |_________________________
_________________ __ _________________________
[rx_phy_sel _________________|0_|_________________________
task_id_h
task_id_l]
*/
parameter IDLE = 2'd0 ;
parameter TASK = 2'd1 ;
parameter HASH = 2'd2 ;
parameter NONCE= 2'd3 ;
//----------------------------------------------
// Alink.clock.tick
//----------------------------------------------
reg [2:0] cur_state ;
reg [2:0] nxt_state ;
reg [4:0] word_cnt ;
reg [3:0] timing_cnt ;
reg hash_pop ;
reg [31:0] tx_buf_flg ;
reg [31:0] tx_buf ;
reg [2:0] tx_rd_en_cnt ;
reg [31:0] reg_step ;
always @ ( posedge clk ) begin
if( rst || cur_state == IDLE )
tx_rd_en_cnt <= 3'b0 ;
else if( tx_rd_en && cur_state == TASK )
tx_rd_en_cnt <= tx_rd_en_cnt + 3'b1 ;
end
always @ ( posedge clk ) begin
if( rst )
timing_cnt <= 4'b0 ;
else if( timing_cnt == `TX_PHY_TIMING )
timing_cnt <= 4'b0 ;
else if( cur_state == HASH || cur_state == NONCE )
timing_cnt <= timing_cnt + 4'b1 ;
else
timing_cnt <= 4'b0 ;
end
wire tick = ( timing_cnt == `TX_PHY_TIMING ) ;
reg nonce_over_flow ;
//----------------------------------------------
// FSM
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst )
cur_state <= IDLE ;
else
cur_state <= nxt_state ;
end
always @ ( * ) begin
nxt_state = cur_state ;
case( cur_state )
IDLE : if( tx_phy_start ) nxt_state = TASK ;
TASK : if( tx_rd_en_cnt == `TX_TASKID_LEN-1 ) nxt_state = HASH ;
HASH : if( word_cnt == `TX_DATA_LEN-1 && ~|tx_buf_flg ) nxt_state = NONCE ;
NONCE: if( nonce_over_flow&&tick ) nxt_state = IDLE ;
endcase
end
assign tx_phy_done = (cur_state == NONCE)&&(nxt_state == IDLE) ;
//----------------------------------------------
// TASK.ID
//----------------------------------------------
always @ ( posedge clk ) begin
if( cur_state == IDLE && nxt_state == TASK ) begin
rx_phy_sel <= tx_phy_sel ;
end
if( cur_state == TASK && tx_rd_en_cnt == 2'd0 ) task_id_h <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd1 ) task_id_l <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd2 ) reg_step <= tx_dout ;
if( cur_state == TASK && tx_rd_en_cnt == 2'd3 ) reg_tout <= tx_dout ;
if( rst )
task_id_vld <= 1'b0 ;
else if( cur_state == TASK && nxt_state == HASH )
task_id_vld <= 1'b1 ;
else
task_id_vld <= 1'b0 ;
end
wire [31:0] scan_nonce = task_id_l ;
wire [7:0] scan_no = task_id_h[7:0] ;
reg [7:0] scan_cnt ;
//----------------------------------------------
// Shifter
//----------------------------------------------
always @ ( posedge clk ) begin
if( rst || cur_state == IDLE )
word_cnt <= 5'b0 ;
else if( cur_state == HASH && ~|tx_buf_flg )
word_cnt <= word_cnt + 5'b1 ;
end
assign tx_rd_en = ( cur_state == TASK ) || ( hash_pop ) ;
reg TX_Px ;
reg TX_Nx ;
always @ ( posedge clk or posedge rst ) begin
if( rst || (cur_state == NONCE && nxt_state == IDLE) || reg_flush ) begin
TX_Px <= 1'b1 ;
TX_Nx <= 1'b1 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin //START
TX_Px <= 1'b0 ;
TX_Nx <= 1'b0 ;
end else if( cur_state == HASH || cur_state == NONCE ) begin
if( ~TX_Px && ~TX_Nx && tick ) begin
TX_Px <= tx_buf[0]?1'b1:1'b0 ;
TX_Nx <= (~tx_buf[0])?1'b1:1'b0 ;
end else if( tick ) begin
TX_Px <= 1'b0 ;
TX_Nx <= 1'b0 ;
end
end
end
genvar i;
generate
for(i = 0; i < `PHY_NUM; i = i + 1) begin
assign {TX_P[i],TX_N[i]} = rx_phy_sel[i] ? {TX_Px,TX_Nx} : 2'b11 ;
end
endgenerate
reg [32:0] nonce_buf ;
always @ ( posedge clk or posedge rst ) begin
if( rst ) begin
hash_pop <= 1'b0 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin
hash_pop <= 1'b0 ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
hash_pop <= 1'b0 ;
end else if( cur_state == TASK && nxt_state == HASH ) begin
hash_pop <= 1'b1 ;
end else if( cur_state == HASH && nxt_state != NONCE && ~|tx_buf_flg ) begin
hash_pop <= 1'b1 ;
end else begin
hash_pop <= 1'b0 ;
end
end
always @ ( posedge clk or posedge rst ) begin
if( rst ) begin
tx_buf <= 32'b0 ;
nonce_over_flow <= 1'b0 ;
nonce_buf <= 33'b0 ;
scan_cnt <= 8'b0 ;
end else if( cur_state == IDLE && nxt_state == TASK ) begin
nonce_over_flow <= 1'b0 ;
nonce_buf <= 33'b0 ;
scan_cnt <= 8'b0 ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
tx_buf <= {1'b0,tx_buf[31:1]} ;
end else if( hash_pop ) begin
tx_buf <= tx_dout ;
end else if( cur_state == HASH && nxt_state == NONCE ) begin
tx_buf <= (reg_scan && (scan_no == scan_cnt)) ? scan_nonce : {32{reg_scan}} | 32'b0 ;
nonce_buf <= nonce_buf + {1'b0,reg_step} ;
scan_cnt <= reg_scan + scan_cnt ;
end else if( cur_state == NONCE && ~|tx_buf_flg ) begin
tx_buf <= (reg_scan && (scan_no == scan_cnt)) ? scan_nonce : {32{reg_scan}} | nonce_buf[31:0] ;
nonce_buf <= nonce_buf + {1'b0,reg_step} ;
nonce_over_flow <= ((nonce_buf)>33'hffff_ffff) ? 1'b1:1'b0 ;
scan_cnt <= reg_scan + scan_cnt ;
end
end
always @ ( posedge clk or posedge rst ) begin
if( rst || cur_state == IDLE ) begin
tx_buf_flg <= 32'hffffffff ;
end else if( ~TX_Px && ~TX_Nx && tick ) begin
tx_buf_flg <= {1'b0,tx_buf_flg[31:1]} ;
end else if( (cur_state == HASH || cur_state == NONCE) && ~|tx_buf_flg ) begin
tx_buf_flg <= 32'hffffffff ;
end
end
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus buffered bridge.
*
*/
module rcn_bridge_buf
(
input rst,
input clk,
input [68:0] main_rcn_in,
output [68:0] main_rcn_out,
input [68:0] sub_rcn_in,
output [68:0] sub_rcn_out
);
parameter ID_MASK = 0;
parameter ID_BASE = 1;
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
wire [5:0] my_id_mask = ID_MASK;
wire [5:0] my_id_base = ID_BASE;
wire [23:0] my_addr_mask = ADDR_MASK;
wire [23:0] my_addr_base = ADDR_BASE;
reg [68:0] main_rin;
reg [68:0] main_rout;
reg [68:0] sub_rin;
reg [68:0] sub_rout;
assign main_rcn_out = main_rout;
assign sub_rcn_out = sub_rout;
wire [68:0] sub_fifo_in;
wire sub_fifo_push;
wire sub_fifo_full;
wire [68:0] sub_fifo_out;
wire sub_fifo_pop;
wire sub_fifo_empty;
wire [68:0] main_fifo_in;
wire main_fifo_push;
wire main_fifo_full;
wire [68:0] main_fifo_out;
wire main_fifo_pop;
wire main_fifo_empty;
always @ (posedge clk or posedge rst)
if (rst)
begin
main_rin <= 69'd0;
main_rout <= 69'd0;
sub_rin <= 69'd0;
sub_rout <= 69'd0;
end
else
begin
main_rin <= main_rcn_in;
main_rout <= (sub_fifo_pop) ? sub_fifo_out :
(main_fifo_push) ? 69'd0 : main_rin;
sub_rin <= sub_rcn_in;
sub_rout <= (main_fifo_pop) ? main_fifo_out :
(sub_fifo_push) ? 69'd0 : sub_rin;
end
wire main_id_match = ((main_rin[65:60] & my_id_mask) == my_id_base);
wire main_addr_match = ((main_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
assign main_fifo_push = !main_fifo_full && main_rin[68] &&
((main_rin[67] && main_addr_match) ||
(!main_rin[67] && main_id_match));
assign main_fifo_pop = !main_fifo_empty && (!sub_rin[68] || sub_fifo_push);
rcn_fifo main_fifo
(
.rst(rst),
.clk(clk),
.rcn_in(main_rin),
.push(main_fifo_push),
.full(main_fifo_full),
.rcn_out(main_fifo_out),
.pop(main_fifo_pop),
.empty(main_fifo_empty)
);
wire sub_id_match = ((sub_rin[65:60] & my_id_mask) == my_id_base);
wire sub_addr_match = ((sub_rin[55:34] & my_addr_mask[23:2]) == my_addr_base[23:2]);
assign sub_fifo_push = !sub_fifo_full && sub_rin[68] &&
((sub_rin[67] && !sub_addr_match) ||
(!sub_rin[67] && !sub_id_match));
assign sub_fifo_pop = !sub_fifo_empty && (!main_rin[68] || main_fifo_push);
rcn_fifo sub_fifo
(
.rst(rst),
.clk(clk),
.rcn_in(sub_rin),
.push(sub_fifo_push),
.full(sub_fifo_full),
.rcn_out(sub_fifo_out),
.pop(sub_fifo_pop),
.empty(sub_fifo_empty)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_BEHAVIORAL_PP_V |
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module axi_ad9122_core (
// dac interface
dac_div_clk,
dac_rst,
dac_frame_i0,
dac_data_i0,
dac_frame_i1,
dac_data_i1,
dac_frame_i2,
dac_data_i2,
dac_frame_i3,
dac_data_i3,
dac_frame_q0,
dac_data_q0,
dac_frame_q1,
dac_data_q1,
dac_frame_q2,
dac_data_q2,
dac_frame_q3,
dac_data_q3,
dac_status,
// master/slave
dac_enable_out,
dac_enable_in,
// vdma interface
vdma_clk,
vdma_fs,
vdma_valid,
vdma_data,
vdma_ready,
// mmcm reset
mmcm_rst,
// drp interface
drp_rst,
drp_sel,
drp_wr,
drp_addr,
drp_wdata,
drp_rdata,
drp_ack_t,
// processor interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_ID = 0;
// dac interface
input dac_div_clk;
output dac_rst;
output dac_frame_i0;
output [15:0] dac_data_i0;
output dac_frame_i1;
output [15:0] dac_data_i1;
output dac_frame_i2;
output [15:0] dac_data_i2;
output dac_frame_i3;
output [15:0] dac_data_i3;
output dac_frame_q0;
output [15:0] dac_data_q0;
output dac_frame_q1;
output [15:0] dac_data_q1;
output dac_frame_q2;
output [15:0] dac_data_q2;
output dac_frame_q3;
output [15:0] dac_data_q3;
input dac_status;
// master/slave
output dac_enable_out;
input dac_enable_in;
// vdma interface
input vdma_clk;
output vdma_fs;
input vdma_valid;
input [63:0] vdma_data;
output vdma_ready;
// mmcm reset
output mmcm_rst;
// drp interface
output drp_rst;
output drp_sel;
output drp_wr;
output [11:0] drp_addr;
output [15:0] drp_wdata;
input [15:0] drp_rdata;
input drp_ack_t;
// processor interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg dac_enable = 'd0;
reg [15:0] dac_data_i0 = 'd0;
reg [15:0] dac_data_i1 = 'd0;
reg [15:0] dac_data_i2 = 'd0;
reg [15:0] dac_data_i3 = 'd0;
reg [15:0] dac_data_q0 = 'd0;
reg [15:0] dac_data_q1 = 'd0;
reg [15:0] dac_data_q2 = 'd0;
reg [15:0] dac_data_q3 = 'd0;
reg dac_frame_i0 = 'd0;
reg dac_frame_i1 = 'd0;
reg dac_frame_i2 = 'd0;
reg dac_frame_i3 = 'd0;
reg dac_frame_q0 = 'd0;
reg dac_frame_q1 = 'd0;
reg dac_frame_q2 = 'd0;
reg dac_frame_q3 = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_ack = 'd0;
// internal clock and resets
wire vdma_rst;
// internal signals
wire dac_enable_s;
wire dac_frame_s;
wire dac_datafmt_s;
wire [ 3:0] dac_datasel_s;
wire [15:0] dac_dds_data_0_0_s;
wire [15:0] dac_dds_data_0_1_s;
wire [15:0] dac_dds_data_0_2_s;
wire [15:0] dac_dds_data_0_3_s;
wire [15:0] dac_dds_data_1_0_s;
wire [15:0] dac_dds_data_1_1_s;
wire [15:0] dac_dds_data_1_2_s;
wire [15:0] dac_dds_data_1_3_s;
wire [63:0] dac_vdma_data_s;
wire vdma_ovf_s;
wire vdma_unf_s;
wire [31:0] vdma_frmcnt_s;
wire [31:0] up_rdata_0_s;
wire up_ack_0_s;
wire [31:0] up_rdata_1_s;
wire up_ack_1_s;
wire [31:0] up_rdata_2_s;
wire up_ack_2_s;
wire [31:0] up_rdata_3_s;
wire up_ack_3_s;
wire [31:0] up_rdata_s;
wire up_ack_s;
// master/slave (clocks must be synchronous)
assign dac_enable_s = (PCORE_ID == 0) ? dac_enable_out : dac_enable_in;
always @(posedge dac_div_clk) begin
dac_enable <= dac_enable_s;
end
// dac outputs
always @(posedge dac_div_clk) begin
if (dac_datasel_s[3:1] == 3'd1) begin
dac_data_i0 <= dac_vdma_data_s[15: 0];
dac_data_i1 <= dac_vdma_data_s[15: 0];
dac_data_i2 <= dac_vdma_data_s[47:32];
dac_data_i3 <= dac_vdma_data_s[47:32];
dac_data_q0 <= dac_vdma_data_s[31:16];
dac_data_q1 <= dac_vdma_data_s[31:16];
dac_data_q2 <= dac_vdma_data_s[63:48];
dac_data_q3 <= dac_vdma_data_s[63:48];
end else begin
dac_data_i0 <= dac_dds_data_0_0_s;
dac_data_i1 <= dac_dds_data_0_1_s;
dac_data_i2 <= dac_dds_data_0_2_s;
dac_data_i3 <= dac_dds_data_0_3_s;
dac_data_q0 <= dac_dds_data_1_0_s;
dac_data_q1 <= dac_dds_data_1_1_s;
dac_data_q2 <= dac_dds_data_1_2_s;
dac_data_q3 <= dac_dds_data_1_3_s;
end
if (dac_datasel_s[0] == 3'd1) begin
dac_frame_i0 <= 1'b1;
dac_frame_i1 <= 1'b0;
dac_frame_i2 <= 1'b1;
dac_frame_i3 <= 1'b0;
dac_frame_q0 <= 1'b1;
dac_frame_q1 <= 1'b0;
dac_frame_q2 <= 1'b1;
dac_frame_q3 <= 1'b0;
end else begin
dac_frame_i0 <= dac_frame_s;
dac_frame_i1 <= 1'b0;
dac_frame_i2 <= 1'b0;
dac_frame_i3 <= 1'b0;
dac_frame_q0 <= dac_frame_s;
dac_frame_q1 <= 1'b0;
dac_frame_q2 <= 1'b0;
dac_frame_q3 <= 1'b0;
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_ack <= 'd0;
end else begin
up_rdata <= up_rdata_s | up_rdata_0_s | up_rdata_1_s;
up_ack <= up_ack_s | up_ack_0_s | up_ack_1_s;
end
end
// dac channel
axi_ad9122_channel #(.CHID(0)) i_channel_0 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_0_0_s),
.dac_dds_data_1 (dac_dds_data_0_1_s),
.dac_dds_data_2 (dac_dds_data_0_2_s),
.dac_dds_data_3 (dac_dds_data_0_3_s),
.dac_dds_enable (dac_enable),
.dac_dds_format (dac_datafmt_s),
.dac_dds_pattenb (dac_datasel_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_0_s),
.up_ack (up_ack_0_s));
// dac channel
axi_ad9122_channel #(.CHID(1)) i_channel_1 (
.dac_div_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_dds_data_0 (dac_dds_data_1_0_s),
.dac_dds_data_1 (dac_dds_data_1_1_s),
.dac_dds_data_2 (dac_dds_data_1_2_s),
.dac_dds_data_3 (dac_dds_data_1_3_s),
.dac_dds_enable (dac_enable),
.dac_dds_format (dac_datafmt_s),
.dac_dds_pattenb (dac_datasel_s[0]),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_1_s),
.up_ack (up_ack_1_s));
// dac vdma
vdma_core #(.DATA_WIDTH(64)) i_vdma_core (
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_fs (vdma_fs),
.vdma_valid (vdma_valid),
.vdma_data (vdma_data),
.vdma_ready (vdma_ready),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_rd (dac_enable),
.dac_valid (),
.dac_data (dac_vdma_data_s),
.vdma_frmcnt (vdma_frmcnt_s));
// dac common processor interface
up_dac_common #(.PCORE_ID(PCORE_ID)) i_up_dac_common (
.mmcm_rst (mmcm_rst),
.dac_clk (dac_div_clk),
.dac_rst (dac_rst),
.dac_enable (dac_enable_out),
.dac_frame (dac_frame_s),
.dac_par_type (),
.dac_par_enb (),
.dac_r1_mode (),
.dac_datafmt (dac_datafmt_s),
.dac_datasel (dac_datasel_s),
.dac_datarate (),
.dac_clk_ratio (32'd4),
.dac_status (dac_status),
.drp_clk (up_clk),
.drp_rst (drp_rst),
.drp_sel (drp_sel),
.drp_wr (drp_wr),
.drp_addr (drp_addr),
.drp_wdata (drp_wdata),
.drp_rdata (drp_rdata),
.drp_ack_t (drp_ack_t),
.vdma_clk (vdma_clk),
.vdma_rst (vdma_rst),
.vdma_frmcnt (vdma_frmcnt_s),
.vdma_ovf (vdma_ovf_s),
.vdma_unf (vdma_unf_s),
.up_usr_chanmax (),
.dac_usr_chanmax (8'd3),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_sel (up_sel),
.up_wr (up_wr),
.up_addr (up_addr),
.up_wdata (up_wdata),
.up_rdata (up_rdata_s),
.up_ack (up_ack_s));
endmodule
// ***************************************************************************
// ***************************************************************************
|
//UART Version 3
/*
Distributed under the MIT license.
Copyright (c) 2014 Cospan Design LLC
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
`include "project_defines.v"
`timescale 1 ns/1 ps
`define PRESCALER_COUNT 16
`define BIT_LENGTH 8
`define FULL_PERIOD (`PRESCALER_COUNT )
`define HALF_PERIOD (`PRESCALER_COUNT / 2)
module uart_v3 #(
parameter DEFAULT_BAUDRATE = 115200
)(
input clk,
input rst,
output reg tx,
input transmit,
input [7:0] tx_byte,
output is_transmitting,
input rx,
output reg rx_error,
output reg [7:0] rx_byte,
output reg received,
output is_receiving,
output [31:0] prescaler, //output this so the user can use it to calculate a baudrate
input set_clock_div,
input [31:0] user_clock_div,
output [31:0] default_clock_div
);
//Local Parameters
//Receive State Machine
localparam RX_IDLE = 0;
localparam RX_CHECK_START = 1;
localparam RX_READING = 2;
localparam RX_CHECK_STOP = 3;
localparam RX_DELAY_RESTART = 4;
localparam RX_ERROR = 5;
localparam RX_RECEIVED = 6;
//Transmit State Machine
localparam TX_IDLE = 0;
localparam TX_SENDING = 1;
localparam TX_FINISHED = 2;
//Registers/Wires
//Receive Register
reg [2:0] rx_state;
reg [3:0] rx_bit_count;
reg [7:0] rx_data;
reg [31:0] rx_clock_div;
reg [31:0] rx_clock_div_count;
reg [31:0] rx_prescaler_count;
//Transmit Register
reg [2:0] tx_state;
reg [3:0] tx_bit_count;
reg [7:0] tx_data;
reg [31:0] tx_clock_div;
reg [31:0] tx_prescaler_count;
reg [31:0] tx_clock_div_count;
//Submodules
//Asynchronous Logic
assign prescaler = `CLOCK_RATE / (`PRESCALER_COUNT);
assign default_clock_div = `CLOCK_RATE / (`PRESCALER_COUNT * DEFAULT_BAUDRATE);
assign is_receiving = (rx_state != RX_IDLE);
assign is_transmitting = (tx_state != TX_IDLE);
//Synchronous Logic
always @ (posedge clk) begin
if (rst || set_clock_div) begin
rx_state <= RX_IDLE;
rx_bit_count <= 0;
rx_clock_div_count <= 0;
rx_clock_div <= `FULL_PERIOD;
rx_data <= 0;
rx_byte <= 0;
rx_error <= 0;
if (set_clock_div) begin
rx_clock_div <= user_clock_div;
end
else begin
rx_clock_div <= default_clock_div;
end
end
else begin
//Strobed
received <= 0;
rx_error <= 0;
//have we passed the clock divider count
rx_clock_div_count <= rx_clock_div_count + 1;
if (rx_clock_div_count >= rx_clock_div) begin
rx_prescaler_count <= rx_prescaler_count + 1;
rx_clock_div_count <= 0;
end
//Receive State Machine
case (rx_state)
RX_IDLE: begin
//--*__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
rx_prescaler_count <= 0;
rx_data <= 0;
rx_bit_count <= 0;
if (!rx) begin
rx_state <= RX_CHECK_START;
end
else begin
rx_clock_div_count <= 0;
end
end
RX_CHECK_START: begin
//--|__*__|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|-- --
if (rx_prescaler_count >= (`HALF_PERIOD)) begin
rx_prescaler_count <= 0;
if (!rx) begin
rx_state <= RX_READING;
end
else begin
rx_state <= RX_IDLE;
end
end
end
RX_READING: begin
//--|__ __|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|XX*XX|-- --
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
rx_data <= {rx, rx_data[7:1]};
rx_prescaler_count <= 0;
if (rx_bit_count >= 7) begin
//Finished
rx_state <= RX_CHECK_STOP;
end
else begin
rx_bit_count <= rx_bit_count + 1;
end
end
end
RX_CHECK_STOP: begin
//--|__ __|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|XX XX|--*--
if (rx_prescaler_count >= (`FULL_PERIOD)) begin
if (rx) begin
rx_byte <= rx_data;
//$display ("FOUND DATA!!!: %h", rx_data);
received <= 1;
rx_state <= RX_IDLE;
end
else begin
rx_error <= 1;
rx_state <= RX_IDLE;
end
end
end
default: begin
rx_state <= RX_IDLE;
end
endcase
end
end
always @ (posedge clk) begin
if (rst || set_clock_div) begin
tx <= 1;
tx_state <= TX_IDLE;
tx_data <= 0;
tx_bit_count <= 0;
tx_clock_div_count <= 0;
tx_prescaler_count <= 0;
if (set_clock_div) begin
tx_clock_div <= user_clock_div;
end
else begin
tx_clock_div <= default_clock_div;
end
end
else begin
//have we passed the clock divider count
tx_clock_div_count <= tx_clock_div_count + 1;
if (tx_clock_div_count >= tx_clock_div) begin
tx_prescaler_count <= tx_prescaler_count + 1;
tx_clock_div_count <= 0;
end
case (tx_state)
TX_IDLE: begin
tx <= 1;
tx_clock_div_count <= 1;
tx_prescaler_count <= 0;
if (transmit) begin
tx <= 0;
tx_data <= tx_byte;
tx_bit_count <= 0;
tx_state <= TX_SENDING;
end
end
TX_SENDING: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_prescaler_count <= 0;
if (tx_bit_count < 8) begin
tx <= tx_data[0];
tx_data <= {1'b0, tx_data[7:1]};
tx_bit_count <= tx_bit_count + 1;
end
else begin
tx <= 1;
tx_state <= TX_FINISHED;
end
end
end
TX_FINISHED: begin
if (tx_prescaler_count >= (`FULL_PERIOD)) begin
tx_state <= TX_IDLE;
end
end
default: begin
tx_state <= TX_IDLE;
end
endcase
end
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: gen_task_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module gen_task_fifo #(
parameter DWIDTH = 32,
parameter AWIDTH = 8
)(
aclr,
clock,
data,
rdreq,
wrreq,
empty,
full,
q,
usedw);
input aclr;
input clock;
input [DWIDTH-1:0] data;
input rdreq;
input wrreq;
output empty;
output full;
output [DWIDTH-1:0] q;
output [AWIDTH-1:0] usedw;
wire sub_wire0;
wire sub_wire1;
wire [DWIDTH-1:0] sub_wire2;
wire [AWIDTH-1:0] sub_wire3;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [DWIDTH-1:0] q = sub_wire2[DWIDTH-1:0];
wire [AWIDTH-1:0] usedw = sub_wire3[AWIDTH-1:0];
scfifo scfifo_component (
.aclr (aclr),
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.usedw (sub_wire3),
.almost_empty (),
.almost_full (),
.sclr ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone IV GX",
scfifo_component.lpm_numwords = 2**AWIDTH,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DWIDTH,
scfifo_component.lpm_widthu = AWIDTH,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: usedw 0 0 8 0 OUTPUT NODEFVAL "usedw[7..0]"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: usedw 0 0 8 0 @usedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL gen_task_fifo_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
module erx_io (/*AUTOARG*/
// Outputs
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
rx_lclk_div4, rx_frame_par, rx_data_par, ecfg_rx_datain,
// Inputs
reset, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n,
rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait, ecfg_rx_enable,
ecfg_rx_gpio_enable, ecfg_dataout
);
parameter IOSTD_ELINK = "LVDS_25";
//###########
//# eLink pins
//###########
input reset; // Reset (from ecfg)
//###########
//# eLink pins
//###########
input rxi_lclk_p, rxi_lclk_n; //link rx clock input
input rxi_frame_p, rxi_frame_n; //link rx frame signal
input [7:0] rxi_data_p, rxi_data_n; //link rx data
output rxo_wr_wait_p,rxo_wr_wait_n; //link rx write pushback output
output rxo_rd_wait_p,rxo_rd_wait_n; //link rx read pushback output
//#############
//# Fabric interface, 1/8 bit rate of eLink
//#############
output rx_lclk_div4; // Parallel clock output (slow)
output [7:0] rx_frame_par;
output [63:0] rx_data_par;
input rx_wr_wait;
input rx_rd_wait;
//#############
//# Configuration bits
//#############
input ecfg_rx_enable; //enable signal for rx
input ecfg_rx_gpio_enable; //forces rx wait pins to constants
input [1:0] ecfg_dataout; //rd_wait, wr_wait for GPIO mode
output [8:0] ecfg_rx_datain; //gpio data in (data in and frame)
//############
//# REGS
//############
reg [63:0] rx_data_par; // output registers
reg [7:0] rx_frame_par;
//############
//# WIRES
//############
wire [7:0] rx_data; // High-speed serial data
wire rx_frame; // serial frame
wire serdes_reset;
//################################
//# Input Buffers Instantiation
//################################
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxdata[7:0]
(.I (rxi_data_p[7:0]),
.IB (rxi_data_n[7:0]),
.O (rx_data[7:0]));
IBUFDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rx_frame
(.I (rxi_frame_p),
.IB (rxi_frame_n),
.O (rx_frame));
//#####################
//# Clock Buffers
//#####################
wire rx_lclk; // Single-ended clock
wire rx_lclk_s; // Serial clock after BUFIO
IBUFGDS
#(.DIFF_TERM ("TRUE"), // Differential termination
.IOSTANDARD (IOSTD_ELINK))
ibufds_rxlclk
(.I (rxi_lclk_p),
.IB (rxi_lclk_n),
.O (rx_lclk));
BUFIO bufio_rxlclk
(.I (rx_lclk),
.O (rx_lclk_s));
// BUFR generates the slow clock
BUFR
#(.SIM_DEVICE("7SERIES"),
.BUFR_DIVIDE("4"))
clkout_bufr
(.O (rx_lclk_div4),
.CE(1'b1),
.CLR(reset),
.I (rx_lclk));
//#############################
//# Deserializer instantiations
//#############################
wire [63:0] rx_data_des;
wire [7:0] rx_frame_des;
wire rx_lclk_sn = ~rx_lclk_s;//TODO: Not important, only for MEMORY_QDR mode?
genvar i;
generate for(i=0; i<8; i=i+1)
begin : gen_serdes
ISERDESE2
#(
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
.NUM_CE(2), // Number of clock enables (1,2)
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0)
)
ISERDESE2_rxdata
(
.O(), // 1-bit output: Combinatorial output
// Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q1(rx_data_des[i]), // Last data in?
.Q2(rx_data_des[i+8]),
.Q3(rx_data_des[i+16]),
.Q4(rx_data_des[i+24]),
.Q5(rx_data_des[i+32]),
.Q6(rx_data_des[i+40]),
.Q7(rx_data_des[i+48]),
.Q8(rx_data_des[i+56]), // First data in?
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
// synchronous to CLKDIV when asserted (active High). Subsequently, the data
// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
// operation, one position every time Bitslip is invoked. DDR operation is
// different from SDR.
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0), // 1-bit input: TBD
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
.CLKDIV(rx_lclk_div4), // 1-bit input: Divided clock
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
.D(rx_data[i]), // 1-bit input: Data input
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
end // block: gen_serdes
endgenerate
ISERDESE2
#(
.DATA_RATE("DDR"), // DDR, SDR
.DATA_WIDTH(8), // Parallel data width (2-8,10,14)
.DYN_CLKDIV_INV_EN("FALSE"), // Enable DYNCLKDIVINVSEL inversion (FALSE, TRUE)
.DYN_CLK_INV_EN("FALSE"), // Enable DYNCLKINVSEL inversion (FALSE, TRUE)
// INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
.INIT_Q1(1'b0),
.INIT_Q2(1'b0),
.INIT_Q3(1'b0),
.INIT_Q4(1'b0),
.INTERFACE_TYPE("NETWORKING"),
// MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
.IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
.NUM_CE(2), // Number of clock enables (1,2)
.OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
.SERDES_MODE("MASTER"), // MASTER, SLAVE
// SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
.SRVAL_Q1(1'b0),
.SRVAL_Q2(1'b0),
.SRVAL_Q3(1'b0),
.SRVAL_Q4(1'b0)
)
ISERDESE2_rx_frame
(
.O(), // 1-bit output: Combinatorial output
// Q1 - Q8: 1-bit (each) output: Registered data outputs
.Q1(rx_frame_des[0]),
.Q2(rx_frame_des[1]),
.Q3(rx_frame_des[2]),
.Q4(rx_frame_des[3]),
.Q5(rx_frame_des[4]),
.Q6(rx_frame_des[5]),
.Q7(rx_frame_des[6]),
.Q8(rx_frame_des[7]),
// SHIFTOUT1, SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
.SHIFTOUT1(),
.SHIFTOUT2(),
.BITSLIP(1'b0), // 1-bit input: The BITSLIP pin performs a Bitslip operation
// synchronous to CLKDIV when asserted (active High). Subsequently, the data
// seen on the Q1 to Q8 output ports will shift, as in a barrel-shifter
// operation, one position every time Bitslip is invoked. DDR operation is
// different from SDR.
// CE1, CE2: 1-bit (each) input: Data register clock enable inputs
.CE1(1'b1),
.CE2(1'b1),
.CLKDIVP(1'b0), // 1-bit input: TBD
// Clocks: 1-bit (each) input: ISERDESE2 clock input ports
.CLK(rx_lclk_s), // 1-bit input: High-speed clock
.CLKB(rx_lclk_sn), // 1-bit input: High-speed secondary clock
.CLKDIV(rx_lclk_div4), // 1-bit input: Divided clock
.OCLK(1'b0), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
// Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
.DYNCLKDIVSEL(1'b0), // 1-bit input: Dynamic CLKDIV inversion
.DYNCLKSEL(1'b0), // 1-bit input: Dynamic CLK/CLKB inversion
// Input Data: 1-bit (each) input: ISERDESE2 data input ports
.D(rx_frame), // 1-bit input: Data input
.DDLY(1'b0), // 1-bit input: Serial data from IDELAYE2
.OFB(1'b0), // 1-bit input: Data feedback from OSERDESE2
.OCLKB(1'b0), // 1-bit input: High speed negative edge output clock
.RST(serdes_reset), // 1-bit input: Active high asynchronous reset
// SHIFTIN1, SHIFTIN2: 1-bit (each) input: Data width expansion input ports
.SHIFTIN1(1'b0),
.SHIFTIN2(1'b0)
);
// Sync control signals into our RX clock domain
reg [1:0] rxenb_sync;
wire rxenb = rxenb_sync[0];
assign serdes_reset = ~rxenb;
reg [1:0] rxgpio_sync;
wire rxgpio = rxgpio_sync[0];
// Register outputs once for good measure, then mux in loopback data if enabled
reg [63:0] rx_data_reg;
reg [7:0] rx_frame_reg;
wire rxreset = reset | ~ecfg_rx_enable;
always @ (posedge rx_lclk_div4 or posedge rxreset)
begin
if(rxreset)
rxenb_sync[1:0] <= 'd0;
else
rxenb_sync[1:0] <= {1'b1, rxenb_sync[1]};
end
//TODO: Is this the right place for the enable signal?
always @ (posedge rx_lclk_div4)
begin
rxgpio_sync <= {ecfg_rx_gpio_enable, rxgpio_sync[1]};
rx_data_reg[63:0] <= rx_data_des[63:0];
rx_data_par[63:0] <= rx_data_reg[63:0];
rx_frame_reg[7:0] <= rx_frame_des[7:0] & {8{rxenb}} & {8{~rxgpio}};
rx_frame_par[7:0] <= rx_frame_reg[7:0];
end
//#############
//# GPIO mode inputs
//#############
reg [8:0] datain_reg;
reg [8:0] ecfg_rx_datain;
always @ (posedge rx_lclk_div4)
begin
datain_reg[8] <= rx_frame_par[0];
datain_reg[7:0] <= rx_data[7:0];
ecfg_rx_datain[8:0] <= datain_reg[8:0];
end
//#############
//# Wait signals (asynchronous)
//#############
wire rd_wait = rxgpio ? ecfg_dataout[0] : rx_rd_wait;
wire wr_wait = rxgpio ? ecfg_dataout[1] : rx_wr_wait;
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("SLOW")
) OBUFDS_RXWRWAIT
(
.O(rxo_wr_wait_p),
.OB(rxo_wr_wait_n),
.I(wr_wait)
);
OBUFDS
#(
.IOSTANDARD(IOSTD_ELINK),
.SLEW("SLOW")
) OBUFDS_RXRDWAIT
(
.O(rxo_rd_wait_p),
.OB(rxo_rd_wait_n),
.I(rd_wait)
);
endmodule // erx_io
/*
File: e_rx_io.v
This file is part of the Parallella Project .
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
// File : ../RTL/hostController/directcontrol.v
// Generated : 11/10/06 05:37:19
// From : ../RTL/hostController/directcontrol.asf
// By : FSM2VHDL ver. 5.0.0.9
//////////////////////////////////////////////////////////////////////
//// ////
//// directControl
//// ////
//// This file is part of the usbhostslave opencores effort.
//// http://www.opencores.org/cores/usbhostslave/ ////
//// ////
//// Module Description: ////
////
//// ////
//// To Do: ////
////
//// ////
//// Author(s): ////
//// - Steve Fielding, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2004 Steve Fielding and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
`include "timescale.v"
`include "usbSerialInterfaceEngine_h.v"
module directControl (HCTxPortCntl, HCTxPortData, HCTxPortGnt, HCTxPortRdy, HCTxPortReq, HCTxPortWEn, clk, directControlEn, directControlLineState, rst);
input HCTxPortGnt;
input HCTxPortRdy;
input clk;
input directControlEn;
input [1:0] directControlLineState;
input rst;
output [7:0] HCTxPortCntl;
output [7:0] HCTxPortData;
output HCTxPortReq;
output HCTxPortWEn;
reg [7:0] HCTxPortCntl, next_HCTxPortCntl;
reg [7:0] HCTxPortData, next_HCTxPortData;
wire HCTxPortGnt;
wire HCTxPortRdy;
reg HCTxPortReq, next_HCTxPortReq;
reg HCTxPortWEn, next_HCTxPortWEn;
wire clk;
wire directControlEn;
wire [1:0] directControlLineState;
wire rst;
// BINARY ENCODED state machine: drctCntl
// State codes definitions:
`define START_DC 3'b000
`define CHK_DRCT_CNTL 3'b001
`define DRCT_CNTL_WAIT_GNT 3'b010
`define DRCT_CNTL_CHK_LOOP 3'b011
`define DRCT_CNTL_WAIT_RDY 3'b100
`define IDLE_FIN 3'b101
`define IDLE_WAIT_GNT 3'b110
`define IDLE_WAIT_RDY 3'b111
reg [2:0] CurrState_drctCntl;
reg [2:0] NextState_drctCntl;
// Diagram actions (continuous assignments allowed only: assign ...)
// diagram ACTION
//--------------------------------------------------------------------
// Machine: drctCntl
//--------------------------------------------------------------------
//----------------------------------
// Next State Logic (combinatorial)
//----------------------------------
always @ (directControlLineState or directControlEn or HCTxPortGnt or HCTxPortRdy or HCTxPortReq or HCTxPortWEn or HCTxPortData or HCTxPortCntl or CurrState_drctCntl)
begin : drctCntl_NextState
NextState_drctCntl <= CurrState_drctCntl;
// Set default values for outputs and signals
next_HCTxPortReq <= HCTxPortReq;
next_HCTxPortWEn <= HCTxPortWEn;
next_HCTxPortData <= HCTxPortData;
next_HCTxPortCntl <= HCTxPortCntl;
case (CurrState_drctCntl)
`START_DC:
NextState_drctCntl <= `CHK_DRCT_CNTL;
`CHK_DRCT_CNTL:
if (directControlEn == 1'b1)
begin
NextState_drctCntl <= `DRCT_CNTL_WAIT_GNT;
next_HCTxPortReq <= 1'b1;
end
else
begin
NextState_drctCntl <= `IDLE_WAIT_GNT;
next_HCTxPortReq <= 1'b1;
end
`DRCT_CNTL_WAIT_GNT:
if (HCTxPortGnt == 1'b1)
NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
`DRCT_CNTL_CHK_LOOP:
begin
next_HCTxPortWEn <= 1'b0;
if (directControlEn == 1'b0)
begin
NextState_drctCntl <= `CHK_DRCT_CNTL;
next_HCTxPortReq <= 1'b0;
end
else
NextState_drctCntl <= `DRCT_CNTL_WAIT_RDY;
end
`DRCT_CNTL_WAIT_RDY:
if (HCTxPortRdy == 1'b1)
begin
NextState_drctCntl <= `DRCT_CNTL_CHK_LOOP;
next_HCTxPortWEn <= 1'b1;
next_HCTxPortData <= {6'b000000, directControlLineState};
next_HCTxPortCntl <= `TX_DIRECT_CONTROL;
end
`IDLE_FIN:
begin
next_HCTxPortWEn <= 1'b0;
next_HCTxPortReq <= 1'b0;
NextState_drctCntl <= `CHK_DRCT_CNTL;
end
`IDLE_WAIT_GNT:
if (HCTxPortGnt == 1'b1)
NextState_drctCntl <= `IDLE_WAIT_RDY;
`IDLE_WAIT_RDY:
if (HCTxPortRdy == 1'b1)
begin
NextState_drctCntl <= `IDLE_FIN;
next_HCTxPortWEn <= 1'b1;
next_HCTxPortData <= 8'h00;
next_HCTxPortCntl <= `TX_IDLE;
end
endcase
end
//----------------------------------
// Current State Logic (sequential)
//----------------------------------
always @ (posedge clk)
begin : drctCntl_CurrentState
if (rst)
CurrState_drctCntl <= `START_DC;
else
CurrState_drctCntl <= NextState_drctCntl;
end
//----------------------------------
// Registered outputs logic
//----------------------------------
always @ (posedge clk)
begin : drctCntl_RegOutput
if (rst)
begin
HCTxPortCntl <= 8'h00;
HCTxPortData <= 8'h00;
HCTxPortWEn <= 1'b0;
HCTxPortReq <= 1'b0;
end
else
begin
HCTxPortCntl <= next_HCTxPortCntl;
HCTxPortData <= next_HCTxPortData;
HCTxPortWEn <= next_HCTxPortWEn;
HCTxPortReq <= next_HCTxPortReq;
end
end
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_2_V
`define SKY130_FD_SC_LS__FAH_2_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_2 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__fah_2 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_2_V
|
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