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//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module NIOS_onchip_memory2_0 (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
reset_req,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "NIOS_onchip_memory2_0.hex";
output [ 31: 0] readdata;
input [ 12: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input reset_req;
input write;
input [ 31: 0] writedata;
wire clocken0;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
assign clocken0 = clken & ~reset_req;
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clocken0),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 8192,
the_altsyncram.numwords_a = 8192,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 13;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
endmodule
|
//--------------------------------------------------------------------------//
// Title: golden_top.v //
// Rev: Rev 4 //
// Author: Altera //
//--------------------------------------------------------------------------//
// Description: All Stratix IV GX FPGA Dev Kit I/O signals and settings //
// such as termination, drive strength, etc... //
// Some toggle_rate=0 where needed for fitter rules. (TR=0) //
//--------------------------------------------------------------------------//
// Revision History: //
// Rev 1: First cut from tcl-script output. 3/26/2009 //
// Rev 2: Minor textual edits and clean-up. Board trace models left //
// as separate tcl scripts from golden_top settings file. //
// Transceiver GXB pins including reference clocks are //
// commented out. Add GXB instatiation under to use these. //
// 12/23/2009 //
// Rev 3: Reformat and added comments. Removed logic. Added safe //
// settings. Changed XCVR input termination to OCT 100ohms //
// from Differential. 09/06/2010 //
// Rev 4: Corrected pinout for ddr3bot_ck_p and ddr3bot_ck_n per SPR //
// 320427. //
//----------------------------------------------------------------------------
//------ 1 ------- 2 ------- 3 ------- 4 ------- 5 ------- 6 ------- 7 ------7
//------ 0 ------- 0 ------- 0 ------- 0 ------- 0 ------- 0 ------- 0 ------8
//----------------------------------------------------------------------------
//Copyright © 2010 Altera Corporation. All rights reserved. Altera products
//are protected under numerous U.S. and foreign patents, maskwork rights,
//copyrights and other intellectual property laws.
//
//This reference design file, and your use thereof, is subject to and
//governed by the terms and conditions of the applicable Altera Reference
//Design License Agreement. By using this reference design file, you
//indicate your acceptance of such terms and conditions between you and
//Altera Corporation. In the event that you do not agree with such terms and
//conditions, you may not use the reference design file. Please promptly
//destroy any copies you have made.
//
//This reference design file being provided on an "as-is" basis and as an
//accommodation and therefore all warranties, representations or guarantees
//of any kind (whether express, implied or statutory) including, without
//limitation, warranties of merchantability, non-infringement, or fitness for
//a particular purpose, are specifically disclaimed. By making this
//reference design file available, Altera expressly does not recommend,
//suggest or require that this reference design file be used in combination
//with any other product not provided by Altera.
//
module golden_top (
//GPLL-CLK-----------------------------//8 pins
input clkin_50, //2.5V //50 MHz, also to EPM2210F256
input clkintop_100_p, //LVDS //100 MHz prog osc
input clkinbot_100_p, //LVDS //100 MHz prog osc
input [1:1] clk_125_p, //LVDS //125 MHz GPLL-req's OCT
output clkout_sma, //2.5V //PLL clock output or GPIO
//XCVR-REFCLK--------------------------//12 pins //req's ALTGXB instatiation
//input [0:0] clk_125_p, //LVDS //125 MHz REFCLK-req's OCT
//input clk_148_p, //LVDS //148.5 MHz REFCLK-req's OCT
//input clk_155_p, //LVPECL //155.52 MHz REFCLK-no OCT
//input clk_156_p, //LVDS //156.25 MHz REFCLK-req's OCT
//input clkinlt_100_p, //LVDS //100 MHz prog osc-req's OCT
//input clkinrt_100_p, //LVDS //100 MHz prog osc-req's OCT
//Power-Monitor------------------------//8 pins //--------------------------
//Bussed to FPGA and EPM2210
//EPM2210 is default master
//output sense_adc_f0, //2.5V //LTC2418 Fref (0-ohm-to-GND)
//output sense_cs0n, //2.5V //LTC2418 Device 0 sel (TR=0)
//output sense_cs1n, //2.5V //LTC2418 Device 1 sel (TR=0)
//output sense_sck, //2.5V //LTC2418 Clk (TR=0)
//input sense_sdi, //2.5V //LTC2418 Data out (TR=0)
//output sense_sdo, //2.5V //LTC2418 Data in (TR=0)
//output sense_smb_clk, //2.5V //LTC4151 & MAX1619 Clk(TR=0)
//inout sense_smb_data, //2.5V //LTC4151 & MAX1619 Dat(TR=0)
//DDR3BOT-x64--------------------------//117pins //--------------------------
output [14:0] ddr3bot_a, //SSTL15 //Address
output [2:0] ddr3bot_ba, //SSTL15 //Bank Address
output ddr3bot_casn, //SSTL15 //Column Address Strobe
output ddr3bot_ck_n, //SSTL15 //Diff Clock - Neg
output ddr3bot_ck_p, //SSTL15 //Diff Clock - Pos
output ddr3bot_cke, //SSTL15 //Clock Enable
output ddr3bot_csn, //SSTL15 //Chip Select
output [7:0] ddr3bot_dm, //SSTL15 //Data Write Mask
inout [63:0] ddr3bot_dq, //SSTL15 //Data Bus
inout [7:0] ddr3bot_dqs_n, //SSTL15 //Diff Data Strobe - Neg
inout [7:0] ddr3bot_dqs_p, //SSTL15 //Diff Data Strobe - Pos
output ddr3bot_odt, //SSTL15 //On-Die Termination Enable
output ddr3bot_rasn, //SSTL15 //Row Address Strobe
output ddr3bot_rstn, //SSTL15 //Reset
output ddr3bot_wen, //SSTL15 //Write Enable
//DDR3TOP-x16--------------------------//49 pins //--------------------------
output [14:0] ddr3top_a, //SSTL15 //Address
output [2:0] ddr3top_ba, //SSTL15 //Bank Address
output ddr3top_casn, //SSTL15 //Column Address Strobe
output ddr3top_ck_n, //SSTL15 //Diff Clock - Neg
output ddr3top_ck_p, //SSTL15 //Diff Clock - Pos
output ddr3top_cke, //SSTL15 //Clock Enable
output ddr3top_csn, //SSTL15 //Chip Select
output [1:0] ddr3top_dm, //SSTL15 //Data Write Mask
inout [15:0] ddr3top_dq, //SSTL15 //Data Bus
inout [1:0] ddr3top_dqs_n, //SSTL15 //Diff Data Strobe - Neg
inout [1:0] ddr3top_dqs_p, //SSTL15 //Diff Data Strobe - Pos
output ddr3top_odt, //SSTL15 //On-Die Termination Enable
output ddr3top_rasn, //SSTL15 //Row Address Strobe
output ddr3top_rstn, //SSTL15 //Reset
output ddr3top_wen, //SSTL15 //Write Enable
//QDR2TOP0-x18read/x18write------------//66 pins //--------------------------
output [19:0] qdr2top0_a, //HSTL15 //Address
output [1:0] qdr2top0_bwsn, //HSTL15 //Byte Write Select
input qdr2top0_cq_n, //HSTL15 //Read Data Clock - Neg
input qdr2top0_cq_p, //HSTL15 //Read Data Clock - Pos
output [17:0] qdr2top0_d, //HSTL15 //Write Data
output qdr2top0_doffn, //HSTL15 //PLL disable (TR=0)
output qdr2top0_k_n, //HSTL15 //Write Data Clock - Neg
output qdr2top0_k_p, //HSTL15 //Write Data Clock - Pos
output qdr2top0_odt, //HSTL15 //On-Die Termination Enable
input [17:0] qdr2top0_q, //HSTL15 //Read Data
input qdr2top0_qvld, //HSTL15 //Read Data Valid
output qdr2top0_rpsn, //HSTL15 //Read Port Select
output qdr2top0_wpsn, //HSTL15 //Write Port Select
//QDR2TOP1-x18read/x18write------------//66 pins //--------------------------
output [19:0] qdr2top1_a, //HSTL15 //Address
output [1:0] qdr2top1_bwsn, //HSTL15 //Byte Write Select
input qdr2top1_cq_n, //HSTL15 //Read Data Clock - Neg
input qdr2top1_cq_p, //HSTL15 //Read Data Clock - Pos
output [17:0] qdr2top1_d, //HSTL15 //Write Data
output qdr2top1_doffn, //HSTL15 //PLL disable (TR=0)
output qdr2top1_k_n, //HSTL15 //Write Data Clock - Neg
output qdr2top1_k_p, //HSTL15 //Write Data Clock - Pos
output qdr2top1_odt, //HSTL15 //On-Die Termination Enable
input [17:0] qdr2top1_q, //HSTL15 //Read Data
input qdr2top1_qvld, //HSTL15 //Read Data Valid
output qdr2top1_rpsn, //HSTL15 //Read Port Select
output qdr2top1_wpsn, //HSTL15 //Write Port Select
//Ethernet-10/100/1000-----------------//8 pins //--------------------------
input enet_intn, //2.5V //MDIO Interrupt (TR=0)
output enet_mdc, //2.5V //MDIO Clock (TR=0)
inout enet_mdio, //2.5V //MDIO Data (TR=0)
output enet_resetn, //2.5V //Device Reset (TR=0)
input enet_rx_p, //LVDS //SGMII Receive-req's OCT
output enet_tx_p, //LVDS //SGMII Transmit
//HDMI-Video-Output--------------------//39 pins //--------------------------
output hdmi_clk, //1.8V //Video Data Clock
output [23:0] hdmi_d, //1.8V //Video Data
output hdmi_de, //1.8V //End
output hdmi_hsync, //1.8V //Horizontal Sync
output [3:0] hdmi_i2s, //1.8V //I2S Digital Audio
input hdmi_intn, //1.5V //Interrupt (TR=0)
//(ran out of 1.8V)
output hdmi_lrclk, //1.8V //Digital Audio Clock
output hdmi_mclk, //1.8V //Digital Audio Clock
output hdmi_scl, //1.8V //SM Bus Clock (TR=0)
output hdmi_sclk, //1.8V //I2S Digital Audio Clock
inout hdmi_sda, //1.8V //SM Bus Data (TR=0)
output hdmi_spdif, //1.8V //SPDIF Digital Audio
output hdmi_vsync, //1.8V //Vertical Sync
//SDI-Video-Port-----------------------//7 pins //--------------------------
//input sdi_rx_p, //PCML14 //SDI Video Input-req's OCT
//output sdi_tx_p, //PCML14 //SDI Video Output
output sdi_clk148_dn, //2.5V //VCO Frequency Down
output sdi_clk148_up, //2.5V //VCO Frequency Up
output sdi_tx_sd_hdn, //2.5V //HD Mode Enable
//FSM-Shared-Bus---(Flash/SRAM/Max)----//78 pins //--------------------------
output [25:0] fsm_a, //2.5V //Address
inout [31:0] fsm_d, //2.5V //Data
output flash_advn, //2.5V //Flash Address Valid
output flash_cen, //2.5V //Flash Chip Enable
output flash_clk, //2.5V //Flash Clock
output flash_oen, //2.5V //Flash Output Enable
input flash_rdybsyn, //2.5V //Flash Ready/Busy
output flash_resetn, //2.5V //Flash Reset
output flash_wen, //2.5V //Flash Write Enable
output sram_adscn, //2.5V //SRAM Address Strobe Cntrl
output sram_adspn, //2.5V //SRAM Address Strobe Proc
output sram_advn, //2.5V //SRAM Address Valid
output sram_bwen, //2.5V //SRAM Byte Write Enable
output [3:0] sram_bwn, //2.5V //SRAM Byte Write Per Byte
output sram_cen, //2.5V //SRAM Chip Enable
output sram_clk, //2.5V //SRAM Clock
inout [3:0] sram_dqp, //2.5V //SRAM Parity Bits
output sram_gwn, //2.5V //SRAM Global Write Enable
output sram_oen, //2.5V //SRAM Output Enable
output sram_zz, //2.5V //SRAM Sleep
output [3:0] max2_ben, //2.5V //Max II Byte Enable Per Byte
output max2_clk, //2.5V //Max II Clk
output max2_csn, //2.5V //Max II Chip Select
output max2_oen, //2.5V //Max II Output Enable
output max2_wen, //2.5V //Max II Write Enable
//Character-LCD------------------------//11 pins //--------------------------
output lcd_csn, //2.5V //LCD Chip Select
output lcd_d_cn, //2.5V //LCD Data / Command Select
inout [7:0] lcd_data, //2.5V //LCD Data
output lcd_wen, //2.5V //LCD Write Enable
//User-IO------------------------------//27 pins //--------------------------
input [7:0] user_dipsw, //2.5V //User DIP Switches (TR=0)
output [15:0] user_led, //2.5V //User LEDs
input [2:0] user_pb, //2.5V //User Pushbuttons (TR=0)
input cpu_resetn, //2.5V //CPU Reset Pushbutton (TR=0)
//PCI-Express--------------------------//25 pins //--------------------------
//input [7:0] pcie_rx_p, //PCML14 //PCIe Receive Data-req's OCT
//output [7:0] pcie_tx_p, //PCML14 //PCIe Transmit Data
//input pcie_refclk_p, //HCSL //PCIe Clock- Terminate on MB
output pcie_led_g2, //2.5V //User LED - Labeled Gen2
output pcie_led_x1, //2.5V //User LED - Labeled x1
output pcie_led_x4, //2.5V //User LED - Labeled x4
output pcie_led_x8, //2.5V //User LED - Labeled x8
input pcie_perstn, //2.5V //PCIe Reset
input pcie_smbclk, //2.5V //SMBus Clock (TR=0)
inout pcie_smbdat, //2.5V //SMBus Data (TR=0)
output pcie_waken, //2.5V //PCIe Wake-Up (TR=0)
//must install 0-ohm resistor
//Transceiver-SMA-Output---------------//2 pins //--------------------------
//input sma_tx_p, //PCML14 //SMA Output Pair
//HSMC-Port-A--------------------------//107pins //--------------------------
//input [7:0] hsma_rx_p, //PCML14 //HSMA Receive Data-req's OCT
//output [7:0] hsma_tx_p, //PCML14 //HSMA Transmit Data
//Enable below for CMOS HSMC
//inout [79:0] hsma_d, //2.5V //HSMA CMOS Data Bus
//Enable below for LVDS HSMC
input hsma_clk_in0, //2.5V //Primary single-ended CLKIN
input hsma_clk_in_p1, //LVDS //Secondary diff. CLKIN
input hsma_clk_in_p2, //LVDS //Primary Source-Sync CLKIN
output hsma_clk_out0, //2.5V //Primary single-ended CLKOUT
output hsma_clk_out_p1, //LVDS //Secondary diff. CLKOUT
output hsma_clk_out_p2, //LVDS //Primary Source-Sync CLKOUT
inout [3:0] hsma_d, //2.5V //Dedicated CMOS IO
input hsma_prsntn, //2.5V //HSMC Presence Detect Input
input [16:0] hsma_rx_d_p, //LVDS //LVDS Sounce-Sync Input
output [16:0] hsma_tx_d_p, //LVDS //LVDS Sounce-Sync Output
output hsma_rx_led, //2.5V //User LED - Labeled RX
output hsma_scl, //2.5V //SMBus Clock
inout hsma_sda, //2.5V //SMBus Data
output hsma_tx_led, //2.5V //User LED - Labeled TX
//HSMC-Port-B--------------------------//107pins //--------------------------
//input [7:0] hsmb_rx_p, //PCML14 //HSMB Receive Data-req's OCT
//output [7:0] hsmb_tx_p, //PCML14 //HSMB Transmit Data
//Enable below for CMOS HSMC
//inout [79:0] hsmb_d, //2.5V //HSMB CMOS Data Bus
//Enable below for LVDS HSMC
input hsmb_clk_in0, //2.5V //Primary single-ended CLKIN
input hsmb_clk_in_p1, //LVDS //Secondary diff. CLKIN
input hsmb_clk_in_p2, //LVDS //Primary Source-Sync CLKIN
output hsmb_clk_out0, //2.5V //Primary single-ended CLKOUT
output hsmb_clk_out_p1, //LVDS //Secondary diff. CLKOUT
output hsmb_clk_out_p2, //LVDS //Primary Source-Sync CLKOUT
inout [3:0] hsmb_d, //2.5V //Dedicated CMOS IO
input hsmb_prsntn, //2.5V //HSMC Presence Detect Input
input [16:0] hsmb_rx_d_p, //LVDS //LVDS Sounce-Sync Input
output [16:0] hsmb_tx_d_p, //LVDS //LVDS Sounce-Sync Output
output hsmb_rx_led, //2.5V //User LED - Labeled RX
output hsmb_scl, //2.5V //SMBus Clock
inout hsmb_sda, //2.5V //SMBus Data
output hsmb_tx_led //2.5V //User LED - Labeled TX
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4B_2_V
`define SKY130_FD_SC_LS__OR4B_2_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog wrapper for or4b with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_2 (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4b_2 (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4b base (
.X(X),
.A(A),
.B(B),
.C(C),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4B_2_V
|
// MBT 7/7/2016
//
// 1 read-port, 1 write-port ram
//
// When read and write with the same address, the behavior depends on which
// clock arrives first, and the read/write clock MUST be separated at least
// twrcc, otherwise will incur indeterminate result.
//
// See "TSN45GS2PRF: TSMC 45nm (=N40G) General Purpose Superb Two-Port
// Register File Compiler Databook"
//
`define bsg_mem_1r1w_sync_macro_rf(words,bits,lgEls,mux) \
if (els_p == words && width_p == bits) \
begin: macro \
tsmc40_2rf_lg``lgEls``_w``bits``_m``mux``_bit mem \
( \
.AA ( w_addr_i ) \
,.D ( w_data_i ) \
,.BWEB ( ~w_mask_i ) \
,.WEB ( ~w_v_i ) \
,.CLKW ( clk_i ) \
\
,.AB ( r_addr_i ) \
,.REB ( ~r_v_i ) \
,.CLKR ( clk_i ) \
,.Q ( r_data_o ) \
\
,.RDELAY ( 2'b00 ) \
,.WDELAY ( 2'b00 ) \
); \
end
module bsg_mem_1r1w_sync_mask_write_bit #(parameter `BSG_INV_PARAM(width_p)
, parameter `BSG_INV_PARAM(els_p)
, parameter read_write_same_addr_p=0
, parameter addr_width_lp=`BSG_SAFE_CLOG2(els_p)
, parameter harden_p=1
)
( input clk_i
, input reset_i
, input w_v_i
, input [width_p-1:0] w_mask_i
, input [addr_width_lp-1:0] w_addr_i
, input [width_p-1:0] w_data_i
// currently unused
, input r_v_i
, input [addr_width_lp-1:0] r_addr_i
, output logic [width_p-1:0] r_data_o
);
`bsg_mem_1r1w_sync_macro_rf(256,128,8,1) else
`bsg_mem_1r1w_sync_macro_rf(64,88,6,1) else
bsg_mem_1r1w_sync_mask_write_bit_synth
#(.width_p(width_p)
,.els_p (els_p )
,.read_write_same_addr_p(read_write_same_addr_p)
,.harden_p(harden_p)
) synth
(.*);
//synopsys translate_off
/*
always_ff @(negedge clk_i)
begin
if (reset_i!==1'b1 & (r_v_i | w_v_i))
$display("@@ w=%b w_addr=%x w_data=%x w_mask=%x r=%b r_addr=%x (%m)",w_v_i,w_addr_i,w_data_i,w_mask_i,r_v_i,r_addr_i);
end
*/
always_ff @(posedge clk_i)
if (w_v_i)
begin
assert (w_addr_i < els_p)
else $error("Invalid address %x to %m of size %x\n", w_addr_i, els_p);
assert (~(r_addr_i == w_addr_i && w_v_i && r_v_i && !read_write_same_addr_p))
else
begin
$error("%m: Attempt to read and write same address (reset_i %b, %x <= %x (mask %x)",reset_i, w_addr_i,w_data_i,w_mask_i);
//$finish();
end
end
initial
begin
$display("## %L: instantiating width_p=%d, els_p=%d, read_write_same_addr_p=%d harden_p=%d (%m)",width_p,els_p,read_write_same_addr_p, harden_p);
assert ( read_write_same_addr_p == 0) else begin
$error("## The hard memory do not support read write the same address. (%m)");
$finish;
end
//synopsys translate_on
endmodule
`BSG_ABSTRACT_MODULE(bsg_mem_1r1w_sync_mask_write_bit)
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Wed May 03 18:20:15 2017
// Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/andrewandre/Documents/GitHub/kernel-on-chip/hdl/projects/Nexys4/bd/ip/bd_clk_wiz_0_0/bd_clk_wiz_0_0_stub.v
// Design : bd_clk_wiz_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module bd_clk_wiz_0_0(clk_ref_i, aclk, sys_clk_i, resetn, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_ref_i,aclk,sys_clk_i,resetn,clk_in1" */;
output clk_ref_i;
output aclk;
output sys_clk_i;
input resetn;
input clk_in1;
endmodule
|
`timescale 1ns / 1ps
`define clkperiodby2 10
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05/04/2015 02:52:37 PM
// Design Name:
// Module Name: tb_mult
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_mult;
// Inputs
reg clk;
reg [15 : 0] A, B;
// Outputs
wire [31 : 0] P;
// Instantiate the Unit Under Test (UUT)
MULT multiplier (
.clk(clk), // input clk
.a(A), // input [15 : 0] a
.b(B), // input [15 : 0] b
.p(P) // output [31 : 0] p
);
initial begin
// Initialize Inputs
clk = 0;
A = 0;
B = 0;
#300
A = -2;
B = 15;
#20
A = 3.1;
B = 4;
#20
A = 6;
B = 7;
#20
A = 4;
B = 15;
#20
A = 8;
B = 9;
#20
#100
$stop;
end
always
#`clkperiodby2 clk <= ~clk;
endmodule
|
Require Import List.
Import ListNotations.
Require Import Arith.
Require Import Omega.
Require Import StructTact.StructTactics.
Require Import StructTact.Util.
Require Import Chord.Chord.
Require Import Chord.PairIn.
Require Import mathcomp.ssreflect.ssreflect.
Set Bullet Behavior "Strict Subproofs".
Ltac expand_def :=
repeat (try break_or_hyp; try break_and; try break_exists);
subst_max;
try tuple_inversion;
try (exfalso; tauto).
Ltac smash_handler :=
match goal with
| [H : context[?f ?h] |- _] =>
match type of (f h) with
| res => destruct (f h) as [[[?st ?ms] ?newts] ?clearedts] eqn:?H
| _ => fail
end
end.
(* -------------------------------- *)
(* General handler characterization *)
(* -------------------------------- *)
Lemma handle_query_req_busy_definition :
forall src st msg st' ms newts clearedts,
handle_query_req_busy src st msg = (st', ms, newts, clearedts) ->
st' = delay_query st src msg /\
ms = [(src, Busy)] /\
clearedts = [] /\
((delayed_queries st = [] /\ newts = [KeepaliveTick]) \/
(delayed_queries st <> [] /\ newts = [])).
Proof using.
unfold handle_query_req_busy.
intros.
repeat break_match; tuple_inversion; tauto.
Qed.
Lemma handle_query_res_definition :
forall src dst st q p st' ms newts clearedts,
handle_query_res src dst st q p = (st', ms, newts, clearedts) ->
(request_payload p /\
st' = delay_query st src p /\
clearedts = [] /\
ms = [] /\
((delayed_queries st = [] /\
newts = [KeepaliveTick]) \/
(delayed_queries st <> [] /\
newts = []))) \/
(p = Busy /\
st' = st /\
ms = [] /\
newts = timeouts_in st /\
clearedts = timeouts_in st) \/
(exists n,
q = Rectify n /\
p = Pong /\
((exists pr,
pred st = Some pr /\
end_query (handle_rectify st pr n) = (st', ms, newts, clearedts)) \/
(pred st = None /\
end_query (update_pred st n, [], [], []) = (st', ms, newts, clearedts)))) \/
(q = Stabilize /\
exists new_succ succs,
p = GotPredAndSuccs new_succ succs /\
handle_stabilize dst (make_pointer src) st q new_succ succs = (st', ms, newts, clearedts)) \/
(exists new_succ,
q = Stabilize2 new_succ /\
exists succs,
p = GotSuccList succs /\
end_query (update_succ_list st (make_succs new_succ succs),
[(addr_of new_succ, Notify)], [], []) = (st', ms, newts, clearedts)) \/
(exists k,
q = Join k /\
((exists bestpred,
p = GotBestPredecessor bestpred /\
clearedts = timeouts_in st /\
((st' = update_query st bestpred (Join k) GetSuccList /\
addr_of bestpred = src /\
ms = [(src, GetSuccList)] /\
newts = [Request src GetSuccList]) \/
(st' = update_query st bestpred (Join k) (GetBestPredecessor (ptr st)) /\
addr_of bestpred <> src /\
ms = [(addr_of bestpred, (GetBestPredecessor (ptr st')))] /\
newts = [Request (addr_of bestpred) (GetBestPredecessor (ptr st'))]))) \/
(p = GotSuccList [] /\
end_query (st, [], [], []) = (st', ms, newts, clearedts)) \/
(exists new_succ rest,
p = GotSuccList (new_succ :: rest) /\
(~ between (hash src) (hash dst) (id_of new_succ) /\
end_query (st, [], [], []) = (st', ms, newts, clearedts) \/
between (hash src) (hash dst) (id_of new_succ) /\
add_tick (end_query (update_for_join st (new_succ :: rest), [], [], [])) = (st', ms, newts, clearedts))))) \/
(exists new_succ succs,
q = Join2 new_succ /\
p = GotSuccList succs /\
add_tick (end_query (update_for_join st (make_succs new_succ succs), [], [], [])) = (st', ms, newts, clearedts)) \/
st' = st /\ ms = [] /\ newts = [] /\ clearedts = [] /\
~ query_response q p.
Proof using.
unfold handle_query_res.
intros.
repeat break_match; try tuple_inversion;
try intuition (try inv_prop query_response).
- do 2 right. left. eexists; intuition eauto.
- do 2 right. left. eexists; intuition eauto.
- intuition eauto.
- intuition eauto.
- do 5 right. left.
eexists; split; eauto.
left.
eexists; split; eauto.
repeat split; auto.
unfold next_msg_for_join; break_if; subst_max.
+ intuition eauto.
+ intuition eauto.
- do 5 right. left.
eexists. intuition eauto.
- repeat find_rewrite.
do 5 right. left.
eexists.
find_apply_lem_hyp between_bool_between.
intuition (eexists; eauto).
- repeat find_rewrite.
do 5 right. left.
eexists.
find_apply_lem_hyp between_bool_false_not_between.
intuition (eexists; eauto).
- do 6 right. left.
eexists. intuition eauto.
Qed.
Lemma handle_msg_definition :
forall src dst st p st' ms newts clearedts,
handle_msg src dst st p = (st', ms, newts, clearedts) ->
p = Ping /\
st' = st /\
ms = [(src, Pong)] /\
newts = [] /\
clearedts = [] \/
p = Notify /\
schedule_rectify_with st (make_pointer src) = (st', ms, newts, clearedts) \/
p <> Notify /\
p <> Ping /\
((exists query_dst query query_msg,
cur_request st = Some (query_dst, query, query_msg) /\
(is_request p = true /\
handle_query_req_busy src st p = (st', ms, newts, clearedts) \/
is_request p = false /\
(addr_of query_dst <> src /\ st' = st /\ clearedts = [] /\ newts = [] /\ ms = [] \/
addr_of query_dst = src /\ handle_query_res src dst st query p = (st', ms, newts, clearedts)))) \/
cur_request st = None /\
st' = st /\
clearedts = [] /\
newts = [] /\
ms = handle_query_req st src p).
Proof.
unfold handle_msg.
intros.
destruct (payload_eq_dec p Notify), (payload_eq_dec p Ping);
subst_max; try congruence.
- tauto.
- tuple_inversion; tauto.
- do 2 right.
repeat split; try auto.
destruct (cur_request st) as [[[query_dst query] query_msg]|] eqn:H_cur.
+ left; repeat eexists; eauto.
destruct (is_request p) eqn:?H;
destruct (addr_eq_dec (addr_of query_dst) src) eqn:?H;
repeat find_rewrite; simpl in *;
break_match; simpl in *;
try congruence; try tuple_inversion; intuition.
+ repeat break_match; try tuple_inversion; tauto.
Qed.
Lemma do_rectify_definition :
forall h st st' ms' nts' cts' eff,
do_rectify h st = (st', ms', nts', cts', eff) ->
(cur_request st = None /\
joined st = true /\
(exists new,
rectify_with st = Some new /\
((exists x,
pred st = Some x /\
eff = StartRectify /\
start_query h (clear_rectify_with st) (Rectify new) = (st', ms', nts', cts')) \/
(pred st = None /\
eff = SetPred /\
st' = clear_rectify_with (update_pred st new) /\
ms' = [] /\
nts' = [] /\
cts' = [])))) \/
(exists cr, cur_request st = Some cr) /\
(exists new, rectify_with st = Some new) /\
st' = st /\
ms' = [] /\
nts' = [RectifyTick] /\
cts' = [] /\
eff = Ineffective \/
((joined st = false \/ rectify_with st = None \/ exists r, cur_request st = Some r) /\
st' = st /\ ms' = [] /\ nts' = [] /\ cts' = [] /\ eff = Ineffective).
Proof using.
unfold do_rectify.
intros.
repeat break_match; try tuple_inversion; try tauto.
- firstorder eauto.
- left.
repeat (eexists; firstorder eauto).
- left.
repeat (eexists; firstorder).
- firstorder eauto.
Qed.
Lemma start_query_definition :
forall h st k st' ms nts cts,
start_query h st k = (st', ms, nts, cts) ->
(exists dst msg,
make_request h st k = Some (dst, msg) /\
st' = update_query st dst k msg /\
ms = [(addr_of dst, msg)] /\
nts = [Request (addr_of dst) msg] /\
cts = timeouts_in st) \/
(make_request h st k = None /\
st' = clear_query st /\
ms = [] /\
ms = [] /\
nts = [] /\
cts = timeouts_in st).
Proof using.
unfold start_query.
intros.
repeat break_match; tuple_inversion; try tauto.
left; repeat eexists.
Qed.
Lemma do_delayed_queries_definition :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
(exists r, cur_request st = Some r /\
st' = st /\ ms = [] /\ nts = [] /\ cts = []) \/
(cur_request st = None /\
st' = clear_delayed_queries st /\
ms = concat (map (handle_delayed_query h st) (delayed_queries st)) /\
nts = [] /\
cts = [KeepaliveTick]).
Proof using.
unfold do_delayed_queries.
intros.
repeat break_match; tuple_inversion;
[left; eexists|]; tauto.
Qed.
Lemma succ_list_preserved_by_do_delayed_queries :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
succ_list st = succ_list st'.
Proof.
intros.
find_apply_lem_hyp do_delayed_queries_definition; expand_def; reflexivity.
Qed.
Lemma pred_preserved_by_do_delayed_queries :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
pred st = pred st'.
Proof.
intros.
find_apply_lem_hyp do_delayed_queries_definition; expand_def; reflexivity.
Qed.
Lemma end_query_definition :
forall st ms newts clearedts st' ms' newts' clearedts',
end_query (st, ms, newts, clearedts) = (st', ms', newts', clearedts') ->
st' = clear_query st /\
ms' = ms /\
newts' = newts /\
clearedts' = timeouts_in st ++ clearedts.
Proof using.
unfold end_query; simpl.
intros.
tuple_inversion; tauto.
Qed.
Lemma handle_rectify_definition :
forall st my_pred notifier st' ms nts cts,
handle_rectify st my_pred notifier = (st', ms, nts, cts) ->
ms = [] /\
nts = [] /\
cts = [] /\
(between (id_of my_pred) (id_of notifier) (id_of (ptr st)) /\
st' = update_pred st notifier \/
~ between (id_of my_pred) (id_of notifier) (id_of (ptr st)) /\
st' = st).
Proof using.
unfold handle_rectify.
intros.
rewrite between_between_bool_equiv.
rewrite Bool.not_true_iff_false.
break_match; tuple_inversion; tauto.
Qed.
Lemma recv_handler_definition :
forall src dst st msg st' ms nts cts st1 ms1 nts1 cts1 st2 ms2 nts2 cts2,
recv_handler src dst st msg = (st', ms, nts, cts) ->
handle_msg src dst st msg = (st1, ms1, nts1, cts1) ->
do_delayed_queries dst st1 = (st2, ms2, nts2, cts2) ->
st' = st2 /\
ms = ms2 ++ ms1 /\
nts = nts2 ++ remove_all timeout_eq_dec cts2 nts1 /\
cts = cts1 ++ cts2.
Proof using.
unfold recv_handler.
intros.
repeat find_rewrite.
tuple_inversion; tauto.
Qed.
Lemma recv_handler_definition_existential :
forall src dst st p st' ms nts cts,
recv_handler src dst st p = (st', ms, nts, cts) ->
exists st1 ms1 nts1 cts1 st2 ms2 nts2 cts2,
handle_msg src dst st p = (st1, ms1, nts1, cts1) /\
do_delayed_queries dst st1 = (st2, ms2, nts2, cts2) /\
st' = st2 /\
ms = ms2 ++ ms1 /\
nts = nts2 ++ remove_all timeout_eq_dec cts2 nts1 /\
cts = cts1 ++ cts2.
Proof.
intros.
destruct (handle_msg src dst st p) as [[[st1 ms1] nts1] cts1] eqn:H_hm.
destruct (do_delayed_queries dst st1) as [[[st2 ms2] nts2] cts2] eqn:H_dq.
find_copy_eapply_lem_hyp recv_handler_definition; eauto; expand_def.
repeat eexists; intuition eauto.
Qed.
Lemma recv_handler_l_definition :
forall src dst st p st' ms nts cts l,
recv_handler_l src dst st p = (st', ms, nts, cts, l) ->
l = RecvMsg src dst p /\
recv_handler src dst st p = (st', ms, nts, cts).
Proof.
unfold recv_handler_l.
intuition congruence.
Qed.
Lemma update_for_start_definition :
forall gst gst' h st ms newts,
gst' = update_for_start gst h (st, ms, newts) ->
nodes gst' = h :: nodes gst /\
failed_nodes gst' = failed_nodes gst /\
timeouts gst' = update addr_eq_dec (timeouts gst) h newts /\
sigma gst' = update addr_eq_dec (sigma gst) h (Some st) /\
msgs gst' = (map (send h) ms) ++ (msgs gst) /\
trace gst' = trace gst ++ map e_send (map (send h) ms).
Proof using.
intros.
subst.
repeat split.
Qed.
Lemma add_tick_definition :
forall st ms nts cts st' ms' nts' cts',
add_tick (st, ms, nts, cts) = (st', ms', nts', cts') ->
st' = st /\ ms = ms' /\ cts = cts' /\
nts' = Tick :: nts.
Proof.
unfold add_tick.
intros.
now tuple_inversion.
Qed.
Lemma tick_handler_definition :
forall h st st' ms nts cts eff,
tick_handler h st = (st', ms, nts, cts, eff) ->
cur_request st = None /\ joined st = true /\
add_tick (start_query h st Stabilize) = (st', ms, nts, cts) /\
eff = StartStabilize \/
((exists req, cur_request st = Some req) \/
joined st = false) /\
st' = st /\ ms = [] /\ nts = [Tick] /\ cts = [] /\ eff = Ineffective.
Proof.
unfold tick_handler.
intros.
repeat break_match; try tuple_inversion;
intuition (eexists; eauto).
Qed.
Lemma keepalive_handler_definition :
forall st st' ms nts cts eff,
keepalive_handler st = (st', ms, nts, cts, eff) ->
st' = st /\
ms = send_keepalives st /\
nts = [KeepaliveTick] /\
cts = [] /\
eff = SendKeepalives.
Proof.
unfold keepalive_handler.
intros.
now tuple_inversion.
Qed.
Lemma handle_query_timeout_definition :
forall h st dst query st' ms nts cts,
handle_query_timeout h st dst query = (st', ms, nts, cts) ->
(exists notifier,
query = Rectify notifier /\
end_query (update_pred st notifier, [], [], []) = (st', ms, nts, cts)) \/
(query = Stabilize /\
exists dead rest,
succ_list st = dead :: rest /\
start_query h (update_succ_list st rest) Stabilize = (st', ms, nts, cts)) \/
(exists s, query = Stabilize2 s /\
exists next rest,
succ_list st = next :: rest /\
end_query (st, [(addr_of next, Notify)], [], []) = (st', ms, nts, cts)) \/
end_query (st, [], [], []) = (st', ms, nts, cts) /\
((exists k, query = Join k) \/
(exists k, query = Join2 k) \/
(query = Stabilize /\
succ_list st = []) \/
(exists s, query = Stabilize2 s /\
succ_list st = [])).
Proof.
unfold handle_query_timeout.
intros.
repeat break_match; intuition (eexists; eauto).
Qed.
Lemma request_timeout_handler_definition :
forall h st dst msg st' ms nts cts eff,
request_timeout_handler h st dst msg = (st', ms, nts, cts, eff) ->
(exists dst_ptr query m,
cur_request st = Some (dst_ptr, query, m) /\
((addr_of dst_ptr = dst /\
eff = DetectFailure /\
exists st_h ms_h nts_h cts_h
st_d ms_d nts_d cts_d,
handle_query_timeout h st dst_ptr query = (st_h, ms_h, nts_h, cts_h) /\
do_delayed_queries h st_h = (st_d, ms_d, nts_d, cts_d) /\
(st_d, ms_h ++ ms_d, nts_h ++ nts_d, cts_h ++ cts_d) = (st', ms, nts, cts)) \/
(addr_of dst_ptr <> dst /\
eff = Ineffective /\
st' = st /\ ms = [] /\ nts = [] /\ cts = []))) \/
cur_request st = None /\
eff = Ineffective /\
st' = st /\ ms = [] /\ nts = [] /\ cts = [].
Proof.
unfold request_timeout_handler.
intros; repeat break_match; try tuple_inversion;
tauto || left; repeat eexists; eauto; try tauto.
left.
intuition eauto.
repeat eexists; eauto.
Qed.
Lemma timeout_handler_eff_definition :
forall h st t res,
timeout_handler_eff h st t = res ->
t = Tick /\
tick_handler h st = res \/
t = KeepaliveTick /\
keepalive_handler st = res \/
t = RectifyTick /\
do_rectify h st = res \/
exists dst msg,
t = Request dst msg /\
request_timeout_handler h st dst msg = res.
Proof.
unfold timeout_handler_eff.
intros.
break_match; intuition eauto.
Qed.
Lemma timeout_handler_l_definition :
forall h st t st' ms nts cts l,
timeout_handler_l h st t = (st', ms, nts, cts, l) ->
exists eff,
timeout_handler_eff h st t = (st', ms, nts, cts, eff) /\
l = Chord.ChordSystem.Timeout h t eff.
Proof.
unfold timeout_handler_l.
intros.
break_let.
tuple_inversion.
eauto.
Qed.
(* -------------------------------- *)
(* Specific handler properties *)
(* -------------------------------- *)
Lemma busy_response_exists :
forall msg st' sends nts cts src st,
request_payload msg ->
(st', sends, nts, cts) = handle_query_req_busy src st msg ->
In (src, Busy) sends.
Proof using.
unfold handle_query_req_busy.
intuition.
break_if;
tuple_inversion;
now apply in_eq.
Qed.
Lemma delay_query_adds_query :
forall st src msg st',
delay_query st src msg = st' ->
In (src, msg) (delayed_queries st').
Proof.
intros.
subst.
simpl.
break_if; auto using dedup_In with datatypes.
Qed.
Lemma handle_query_req_busy_delays_query :
forall src st msg st' ms nts cts,
handle_query_req_busy src st msg = (st', ms, nts, cts) ->
In (src, msg) (delayed_queries st').
Proof.
intros.
find_apply_lem_hyp handle_query_req_busy_definition; expand_def;
eauto using delay_query_adds_query.
Qed.
Lemma handle_query_req_busy_sends_busy :
forall src st msg st' ms nts cts,
handle_query_req_busy src st msg = (st', ms, nts, cts) ->
In (src, Busy) ms.
Proof using.
unfold handle_query_req_busy.
intuition.
break_if;
tuple_inversion;
exact: in_eq.
Qed.
Lemma handle_query_req_busy_preserves_cur_request :
forall src st msg st' ms nts cts,
handle_query_req_busy src st msg = (st', ms, nts, cts) ->
cur_request st' = cur_request st.
Proof.
intros.
find_apply_lem_hyp handle_query_req_busy_definition; expand_def;
easy.
Qed.
Lemma unsafe_msgs_not_safe_ones :
forall msg,
is_safe msg = false ->
msg <> Notify /\ msg <> Ping.
Proof using.
unfold is_safe.
intuition;
break_match;
easy.
Qed.
Lemma handle_query_req_gives_response :
forall st src m,
is_safe m = false ->
request_payload m ->
exists p,
handle_query_req st src m = [(src, p)].
Proof using.
unfold handle_query_req.
intuition.
find_copy_apply_lem_hyp unsafe_msgs_not_safe_ones; break_and.
request_payload_inversion;
eauto || congruence.
Qed.
Lemma do_delayed_queries_busy_nop :
forall h st st' ms nts cts,
cur_request st <> None ->
do_delayed_queries h st = (st', ms, nts, cts) ->
st' = st /\ ms = [] /\ nts = [] /\ cts = [].
Proof.
unfold do_delayed_queries.
intros.
break_match; repeat split; congruence.
Qed.
Lemma real_requests_get_queued_and_busy_response :
forall src dst msg st st' sends nts cts,
request_payload msg ->
cur_request st <> None ->
msg <> Ping ->
recv_handler src dst st msg = (st', sends, nts, cts) ->
In (src, Busy) sends /\
In (src, msg) (delayed_queries st').
Proof.
intros.
find_apply_lem_hyp recv_handler_definition_existential; expand_def.
find_apply_lem_hyp handle_msg_definition; expand_def.
- inv_prop request_payload.
- split.
+ eauto using handle_query_req_busy_sends_busy with datatypes.
+ find_copy_apply_lem_hyp handle_query_req_busy_preserves_cur_request.
find_copy_apply_lem_hyp do_delayed_queries_busy_nop; expand_def;
try congruence.
eapply handle_query_req_busy_delays_query; eauto.
- find_apply_lem_hyp is_request_same_as_request_payload; congruence.
- find_apply_lem_hyp is_request_same_as_request_payload; congruence.
Qed.
Lemma real_requests_get_busy_response :
forall src dst msg st st' sends nts cts,
request_payload msg ->
cur_request st <> None ->
msg <> Ping ->
recv_handler src dst st msg = (st', sends, nts, cts) ->
In (src, Busy) sends.
Proof.
intros.
find_apply_lem_hyp real_requests_get_queued_and_busy_response; tauto.
Qed.
Lemma real_requests_get_queued :
forall src dst msg st st' sends nts cts,
request_payload msg ->
cur_request st <> None ->
msg <> Ping ->
recv_handler src dst st msg = (st', sends, nts, cts) ->
In (src, msg) (delayed_queries st').
Proof.
intros.
find_apply_lem_hyp real_requests_get_queued_and_busy_response; tauto.
Qed.
Lemma real_requests_get_response_handle_query_req :
forall st src req sends,
request_payload req ->
req <> Ping ->
handle_query_req st src req = sends ->
exists res,
In (src, res) sends /\
request_response_pair req res.
Proof.
intros.
match goal with
| [H: request_payload _ |- _] =>
inv H; congruence || simpl
end;
eexists; intuition eauto; constructor.
Qed.
Lemma pings_always_get_pongs_handle_msg :
forall src dst st st' sends nts cts,
handle_msg src dst st Ping = (st', sends, nts, cts) ->
In (src, Pong) sends.
Proof.
intros.
find_apply_lem_hyp handle_msg_definition; expand_def;
solve [auto with datatypes | congruence].
Qed.
Lemma pings_always_get_pongs_recv_handler :
forall src dst st st' sends nts cts,
recv_handler src dst st Ping = (st', sends, nts, cts) ->
In (src, Pong) sends.
Proof.
intros.
find_apply_lem_hyp recv_handler_definition_existential; expand_def.
apply in_or_app; right.
eapply pings_always_get_pongs_handle_msg; eauto.
Qed.
Lemma real_requests_get_responses_handle_msg :
forall src dst st req st' sends nts cts,
handle_msg src dst st req = (st', sends, nts, cts) ->
request_payload req ->
req <> Ping ->
cur_request st = None ->
exists res,
In (src, res) sends /\
request_response_pair req res.
Proof.
intros.
find_apply_lem_hyp handle_msg_definition; expand_def.
- solve_by_inversion.
- congruence.
- find_apply_lem_hyp is_request_same_as_request_payload; congruence.
- find_apply_lem_hyp is_request_same_as_request_payload; congruence.
- eapply real_requests_get_response_handle_query_req; eauto.
Qed.
Lemma real_requests_get_responses_recv_handler :
forall src dst st req st' sends nts cts,
recv_handler src dst st req = (st', sends, nts, cts) ->
request_payload req ->
req <> Ping ->
cur_request st = None ->
exists res,
In (src, res) sends /\
request_response_pair req res.
Proof.
intros.
find_apply_lem_hyp recv_handler_definition_existential; expand_def.
find_apply_lem_hyp real_requests_get_responses_handle_msg; eauto.
break_exists_exists; break_and.
eauto with datatypes.
Qed.
Lemma requests_get_responses_recv_handler' :
forall src dst st req st' sends nts cts,
recv_handler src dst st req = (st', sends, nts, cts) ->
request_payload req ->
cur_request st = None \/ req = Ping ->
exists res,
In (src, res) sends /\
request_response_pair req res.
Proof.
intros.
destruct (payload_eq_dec req Ping); subst.
- find_apply_lem_hyp pings_always_get_pongs_recv_handler.
eexists; split; eauto || constructor.
- break_or_hyp; try congruence.
eauto using real_requests_get_responses_recv_handler.
Qed.
Lemma requests_are_always_responded_to :
forall src dst req st st' sends nts cts,
request_payload req ->
recv_handler src dst st req = (st', sends, nts, cts) ->
cur_request st <> None /\
req <> Ping /\
In (src, Busy) sends \/
exists res,
In (src, res) sends /\
request_response_pair req res.
Proof.
intros.
destruct (payload_eq_dec req Ping); subst.
- right.
eexists; eauto using pings_always_get_pongs_recv_handler, pair_Ping.
- destruct (cur_request st) eqn:?H.
+ find_copy_eapply_lem_hyp real_requests_get_busy_response; eauto.
* left; repeat split; assumption || congruence.
* congruence.
+ find_apply_lem_hyp real_requests_get_responses_recv_handler; auto.
Qed.
Lemma requests_get_response_or_queued :
forall src dst req st st' sends nts cts,
request_payload req ->
recv_handler src dst st req = (st', sends, nts, cts) ->
cur_request st <> None /\
req <> Ping /\
In (src, req) (delayed_queries st') \/
exists res,
In (src, res) sends /\
request_response_pair req res.
Proof.
intros.
destruct (payload_eq_dec req Ping); subst.
- right.
eexists; eauto using pings_always_get_pongs_recv_handler, pair_Ping.
- destruct (cur_request st) eqn:?H.
+ find_apply_lem_hyp real_requests_get_queued; eauto.
* left; repeat split; try congruence.
* congruence.
+ find_apply_lem_hyp real_requests_get_responses_recv_handler; auto.
Qed.
Lemma apply_handler_result_preserves_nodes :
forall gst gst' h res e,
gst' = apply_handler_result h res e gst ->
nodes gst = nodes gst'.
Proof using.
unfold apply_handler_result.
intuition.
repeat break_let.
find_rewrite; auto.
Qed.
Lemma apply_handler_result_preserves_failed_nodes :
forall gst gst' h res e,
gst' = apply_handler_result h res e gst ->
failed_nodes gst = failed_nodes gst'.
Proof using.
unfold apply_handler_result.
intuition.
repeat break_let.
find_rewrite; auto.
Qed.
Lemma joined_preserved_by_start_query :
forall h st k st' ms nts cts,
start_query h st k = (st', ms, nts, cts) ->
joined st = joined st'.
Proof using.
unfold start_query.
intuition.
break_match.
- break_let.
tuple_inversion.
unfold update_query; auto.
- tuple_inversion; auto.
Qed.
Lemma joined_preserved_by_do_rectify :
forall h st st' ms' cts' nts' eff,
do_rectify h st = (st', ms', cts', nts', eff) ->
joined st = joined st'.
Proof using.
intros.
find_eapply_lem_hyp do_rectify_definition; expand_def;
try find_eapply_lem_hyp joined_preserved_by_start_query;
simpl in *; eauto.
Qed.
Lemma joined_preserved_by_do_delayed_queries :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
joined st = joined st'.
Proof.
intros.
find_eapply_lem_hyp do_delayed_queries_definition; expand_def;
simpl in *; eauto.
Qed.
Lemma joined_preserved_by_end_query :
forall st st' ms ms' cts cts' nts nts',
end_query (st, ms, cts, nts) = (st', ms', cts', nts') ->
joined st = joined st'.
Proof using.
unfold end_query.
intros.
tuple_inversion.
tauto.
Qed.
Lemma joined_preserved_by_handle_stabilize :
forall h src st q new_succ succ st' ms nts cts,
handle_stabilize h src st q new_succ succ = (st', ms, nts, cts) ->
joined st = joined st'.
Proof using.
unfold handle_stabilize.
unfold update_succ_list.
intuition.
repeat break_match;
solve [find_apply_lem_hyp joined_preserved_by_start_query; auto |
find_apply_lem_hyp joined_preserved_by_end_query; auto].
Qed.
Lemma joined_preserved_by_end_query_handle_rectify :
forall st p n st' ms nts cts,
end_query (handle_rectify st p n) = (st', ms, nts, cts) ->
joined st = joined st'.
Proof using.
unfold handle_rectify.
intuition.
repeat break_match;
find_apply_lem_hyp joined_preserved_by_end_query;
now simpl in *.
Qed.
(* not as strong as the other ones since handle_query for a Join query can change joined st from false to true *)
Lemma joined_preserved_by_handle_query :
forall src h st q m st' ms nts cts,
handle_query_res src h st q m = (st', ms, nts, cts) ->
joined st = true ->
joined st' = true.
Proof.
intros.
find_eapply_lem_hyp handle_query_res_definition; expand_def; auto;
try (find_eapply_lem_hyp joined_preserved_by_end_query; simpl in *; congruence).
- find_eapply_lem_hyp joined_preserved_by_end_query_handle_rectify; congruence.
- find_eapply_lem_hyp joined_preserved_by_handle_stabilize; congruence.
Qed.
Lemma schedule_rectify_with_definition :
forall st rw st' ms nts cts,
schedule_rectify_with st rw = (st', ms, nts, cts) ->
ms = [] /\
cts = [] /\
((exists rw0,
rectify_with st = Some rw0 /\
nts = [] /\
(ptr_between_bool rw0 rw (ptr st) = true /\
st' = set_rectify_with st rw \/
ptr_between_bool rw0 rw (ptr st) = false /\
st' = st)) \/
rectify_with st = None /\
st' = set_rectify_with st rw /\
nts = [RectifyTick]).
Proof.
unfold schedule_rectify_with.
intros.
repeat break_match; tuple_inversion;
intuition (eexists; eauto).
Qed.
Lemma joined_preserved_by_schedule_rectify_with :
forall st rw st' ms nts cts,
schedule_rectify_with st rw = (st', ms, nts, cts) ->
joined st = joined st'.
Proof.
intros.
simpl in *.
find_apply_lem_hyp schedule_rectify_with_definition; expand_def;
simpl; auto.
Qed.
Lemma joined_preserved_by_recv_handler :
forall src h st msg st' ms nts cts,
recv_handler src h st msg = (st', ms, nts, cts) ->
joined st = true ->
joined st' = true.
Proof using.
intros.
find_apply_lem_hyp recv_handler_definition_existential; expand_def.
find_apply_lem_hyp joined_preserved_by_do_delayed_queries.
find_apply_lem_hyp handle_msg_definition; expand_def; try congruence.
- find_apply_lem_hyp joined_preserved_by_schedule_rectify_with; congruence.
- find_apply_lem_hyp handle_query_req_busy_definition; expand_def; simpl in *; congruence.
- find_apply_lem_hyp joined_preserved_by_handle_query; congruence.
Qed.
Lemma joined_preserved_by_tick_handler :
forall h st st' ms nts cts eff,
tick_handler h st = (st', ms, nts, cts, eff) ->
joined st = joined st'.
Proof using.
intros.
find_apply_lem_hyp tick_handler_definition; expand_def; auto.
destruct (start_query _ _ _) as [[[[?st ?ms] ?nts] ?cts] ?eff] eqn:?H.
find_eapply_lem_hyp add_tick_definition; expand_def.
find_eapply_lem_hyp joined_preserved_by_start_query.
congruence.
Qed.
Lemma joined_preserved_by_handle_query_timeout :
forall h st dst q st' ms nts cts,
handle_query_timeout h st dst q = (st', ms, nts, cts) ->
joined st = joined st'.
Proof using.
unfold handle_query_timeout.
intuition.
repeat break_match;
find_apply_lem_hyp joined_preserved_by_end_query ||
find_apply_lem_hyp joined_preserved_by_start_query;
eauto.
Qed.
Lemma joined_preserved_by_timeout_handler_eff :
forall h st t st' ms nts cts eff,
timeout_handler_eff h st t = (st', ms, nts, cts, eff) ->
joined st = joined st'.
Proof using.
unfold timeout_handler_eff.
intuition.
repeat break_match;
try tuple_inversion;
eauto using joined_preserved_by_tick_handler, joined_preserved_by_handle_query_timeout, joined_preserved_by_do_rectify.
- apply keepalive_handler_definition in H; expand_def; auto.
- find_apply_lem_hyp request_timeout_handler_definition; expand_def; try reflexivity.
find_apply_lem_hyp handle_query_timeout_definition;
find_apply_lem_hyp do_delayed_queries_definition;
expand_def;
try find_apply_lem_hyp end_query_definition;
try find_apply_lem_hyp start_query_definition;
expand_def;
reflexivity.
Qed.
Lemma apply_handler_result_updates_sigma :
forall h st ms nts cts e gst gst',
gst' = apply_handler_result h (st, ms, nts, cts) e gst ->
sigma gst' h = Some st.
Proof using.
unfold apply_handler_result, update.
intuition.
repeat find_rewrite.
simpl in *.
break_if; congruence.
Qed.
Lemma sigma_ahr_updates :
forall gst n st ms nts cts e,
sigma (apply_handler_result n (st, ms, nts, cts) e gst) n = Some st.
Proof using.
unfold apply_handler_result.
simpl.
intros.
exact: update_eq.
Qed.
Lemma sigma_ahr_passthrough :
forall gst n st ms nts cts e h d,
n <> h ->
sigma gst h = Some d ->
sigma (apply_handler_result n (st, ms, nts, cts) e gst) h = Some d.
Proof using.
unfold apply_handler_result.
simpl.
intros.
find_reverse_rewrite.
exact: update_diff.
Qed.
Lemma handle_msg_stabilize_response_pred_worse_sets_succs :
forall s h st p succs,
cur_request st = Some (make_pointer s, Stabilize, GetPredAndSuccs) ->
ptr_between_bool (ptr st) p (make_pointer s) = false ->
forall st' ms nts cts,
handle_msg s h st (GotPredAndSuccs (Some p) succs) = (st', ms, nts, cts) ->
succ_list st' = make_succs (make_pointer s) succs.
Proof.
intros until 2.
unfold handle_msg.
find_rewrite; simpl.
repeat (break_if; try congruence).
intros.
find_injection.
reflexivity.
Qed.
Lemma recv_handler_stabilize_response_pred_worse_sets_succs :
forall s h st p succs,
cur_request st = Some (make_pointer s, Stabilize, GetPredAndSuccs) ->
ptr_between_bool (ptr st) p (make_pointer s) = false ->
forall st' ms nts cts,
recv_handler s h st (GotPredAndSuccs (Some p) succs) = (st', ms, nts, cts) ->
succ_list st' = make_succs (make_pointer s) succs.
Proof.
intros until 2.
unfold recv_handler.
repeat break_let.
intros.
find_injection.
erewrite <- succ_list_preserved_by_do_delayed_queries; eauto.
eapply handle_msg_stabilize_response_pred_worse_sets_succs; eauto.
Qed.
Lemma ptr_between_ptr_between_bool :
forall a b c,
ptr_between a b c ->
ptr_between_bool a b c = true.
Proof.
unfold ptr_between, ptr_between_bool.
intros.
now apply between_between_bool_equiv.
Qed.
Hint Resolve ptr_between_ptr_between_bool.
Lemma not_ptr_between :
forall a b c,
~ ptr_between a b c ->
ptr_between_bool a b c = false.
Proof.
intros.
destruct (ptr_between_bool _ _ _) eqn:?H; [|reflexivity].
find_apply_lem_hyp between_between_bool_equiv.
exfalso; eauto.
Qed.
Hint Resolve not_ptr_between.
Lemma ptr_between_bool_false :
forall a b c,
ptr_between_bool a b c = false ->
~ ptr_between a b c.
Proof.
unfold ptr_between, ptr_between_bool.
intros.
now apply between_bool_false_not_between.
Qed.
Hint Resolve ptr_between_bool_false.
Lemma ptr_between_bool_true :
forall a b c,
ptr_between_bool a b c = true ->
ptr_between a b c.
Proof.
unfold ptr_between, ptr_between_bool.
intros.
now apply between_bool_between.
Qed.
Hint Resolve ptr_between_bool_true.
Lemma handle_stabilize_definition :
forall h src st q ns succs result,
handle_stabilize h src st q ns succs = result ->
(exists new_succ,
ns = Some new_succ /\
(ptr_between (ptr st) new_succ src /\
start_query h (update_succ_list st (make_succs src succs)) (Stabilize2 new_succ) = result \/
~ ptr_between (ptr st) new_succ src /\
end_query (update_succ_list st (make_succs src succs), [(addr_of src, Notify)], [], []) = result)) \/
ns = None /\
end_query (update_succ_list st (make_succs src succs), [(addr_of src, Notify)], [], []) = result.
Proof.
unfold handle_stabilize.
intros; repeat break_match;
solve [left; econstructor; eauto | right; eauto].
Qed.
Lemma timeouts_in_None :
forall st,
cur_request st = None ->
timeouts_in st = [].
Proof.
unfold timeouts_in.
intros; find_rewrite; reflexivity.
Qed.
Lemma timeouts_in_Some :
forall st dst q m,
cur_request st = Some (dst, q, m) ->
timeouts_in st = [Request (addr_of dst) m].
Proof.
unfold timeouts_in.
intros; find_rewrite; reflexivity.
Qed.
Lemma timeouts_in_update_pred :
forall st p,
timeouts_in (update_pred st p) = timeouts_in st.
Proof.
easy.
Qed.
Hint Rewrite timeouts_in_update_pred.
Lemma timeouts_in_update_succ_list :
forall st sl,
timeouts_in (update_succ_list st sl) = timeouts_in st.
Proof.
easy.
Qed.
Hint Rewrite timeouts_in_update_succ_list.
Lemma timeouts_in_update_for_join :
forall st sl,
timeouts_in (update_for_join st sl) = timeouts_in st.
Proof.
easy.
Qed.
Hint Rewrite timeouts_in_update_for_join.
Lemma NoDup_two_diff :
forall A (a b : A),
a <> b ->
NoDup [a; b].
Proof.
intros.
constructor.
- intro; find_apply_lem_hyp In_cons_neq; auto.
- repeat constructor; auto.
Qed.
(* Hints for reasoning about handlers *)
Hint Unfold clear_delayed_queries.
Hint Unfold next_msg_for_join.
Hint Constructors request_payload.
Hint Constructors response_payload.
Hint Constructors NoDup.
Hint Resolve NoDup_disjoint_append.
Hint Resolve NoDup_two_diff.
Hint Extern 1 (_ <> _) => congruence.
(* TODO(ryan) move to structtact! *)
Lemma in_singleton_eq :
forall A (x y : A),
In x [y] ->
x = y.
Proof.
intros.
simpl in *.
intuition.
Qed.
Lemma timeout_handler_definition :
forall h st t st' ms nts cts,
timeout_handler h st t = (st', ms, nts, cts) ->
exists eff,
timeout_handler_eff h st t = (st', ms, nts, cts, eff).
Proof.
intros. unfold timeout_handler in *.
match goal with
| _ : context [timeout_handler_eff ?h ?st ?t] |- _ =>
destruct (timeout_handler_eff h st t) eqn:?
end. simpl in *. subst.
eauto.
Qed.
Ltac handler_def :=
match goal with
| H : timeout_handler_l _ _ _ = _ |- _ =>
apply timeout_handler_l_definition in H; expand_def
| H : timeout_handler _ _ _ = _ |- _ =>
apply timeout_handler_definition in H; expand_def
| H : timeout_handler_eff _ _ _ = _ |- _ =>
apply timeout_handler_eff_definition in H; expand_def
| H:request_timeout_handler _ _ _ _ = _ |- _ =>
apply request_timeout_handler_definition in H; expand_def
| H:handle_query_timeout _ _ _ _ = _ |- _ =>
apply handle_query_timeout_definition in H; expand_def
| H: recv_handler_l _ _ _ _ = _ |- _ =>
apply recv_handler_l_definition in H; expand_def
| H: recv_handler _ _ _ _ = _ |- _ =>
apply recv_handler_definition_existential in H; expand_def
| H: handle_msg _ _ _ _ = _ |- _ =>
apply handle_msg_definition in H; expand_def
| H: end_query (_, _, _, _) = _ |- _ =>
apply end_query_definition in H; expand_def
| H: end_query (?arg) = _ |- _ =>
destruct arg as [[[? ?] ?] ?] eqn:?
| H: handle_query_res _ _ _ _ _ = _ |- _ =>
apply handle_query_res_definition in H; expand_def
| H: handle_query_req_busy _ _ _ = _ |- _ =>
apply handle_query_req_busy_definition in H; expand_def
| H: handle_rectify _ _ _ = _ |- _ =>
apply handle_rectify_definition in H; expand_def
| H : do_rectify _ _ = _ |- _ =>
apply do_rectify_definition in H; expand_def
| H: handle_stabilize _ _ _ _ _ _ = _ |- _ =>
apply handle_stabilize_definition in H; expand_def
| H : keepalive_handler _ = _ |- _ =>
apply keepalive_handler_definition in H; expand_def
| H : tick_handler _ _ = _ |- _ =>
apply tick_handler_definition in H; expand_def
| H : add_tick _ = _ |- _ =>
apply add_tick_definition in H; expand_def
| H: start_query _ _ _ = _ |- _ =>
apply start_query_definition in H; expand_def
| H: context [start_query ?h ?st ?q] |- _ =>
destruct (start_query h st q) as [[[? ?] ?] ?] eqn:?
| H: do_delayed_queries _ _ = _ |- _ =>
apply do_delayed_queries_definition in H; expand_def
| H: schedule_rectify_with _ _ = _ |- _ =>
apply schedule_rectify_with_definition in H; expand_def
end.
Ltac handler_simpl :=
match goal with
| |- _ => progress subst
| H: _ = _ |- _ => injc H
| H: In _ [_] |- _ => apply in_singleton_eq in H
| |- _ => progress simpl in *
| |- _ => progress unfold not in *
| |- _ => progress autounfold in *
| |- _ => progress autorewrite with list core in *
| H: cur_request ?st = Some _ |- context[timeouts_in ?st] =>
erewrite timeouts_in_Some; [|eassumption]
| H: cur_request ?st = None |- context[timeouts_in ?st] =>
erewrite timeouts_in_None; [|eassumption]
| |- context[update _ _ _ _ _] => update_destruct_goal; rewrite_update
| H: context[update _ _ _ _ _] |- _ => update_destruct_hyp; rewrite_update
| |- _ => solve [assumption | congruence | eauto ]
end.
Lemma joined_preserved_by_request_timeout_handler :
forall h st dst req st' ms nts cts eff,
request_timeout_handler h st dst req = (st', ms, nts, cts, eff) ->
joined st = joined st'.
Proof.
intros; repeat (handler_def || handler_simpl).
Qed.
Hint Resolve joined_preserved_by_request_timeout_handler.
Lemma handle_query_res_info_from_changed_set_cur_request :
forall src dst st q p st' ms nts cts,
handle_query_res src dst st q p = (st', ms, nts, cts) ->
forall dstp q' req,
cur_request st <> cur_request st' ->
cur_request st' = Some (dstp, q', req) ->
(exists dstp succs,
nts = [Request (addr_of dstp) GetSuccList] /\
cts = timeouts_in st /\
q = Stabilize /\
p = GotPredAndSuccs (Some dstp) succs /\
cur_request st' = Some (dstp, Stabilize2 dstp, GetSuccList) /\
ptr_between (ptr st) dstp (make_pointer src)) \/
(exists j dstp,
nts = [Request (addr_of dstp) GetSuccList] /\
cts = timeouts_in st /\
q = Join j /\
p = GotBestPredecessor dstp /\
addr_of dstp = src /\
cur_request st' = Some (dstp, Join j, GetSuccList)) \/
(exists j dstp,
nts = [Request (addr_of dstp) (GetBestPredecessor (ptr st))] /\
cts = timeouts_in st /\
q = Join j /\
p = GotBestPredecessor dstp /\
addr_of dstp <> src /\
cur_request st' = Some (dstp, Join j, GetBestPredecessor (ptr st))) \/
exists j dstp rest,
nts = [Request (addr_of dstp) GetSuccList] /\
cts = timeouts_in st /\
q = Join j /\
p = GotSuccList (dstp :: rest) /\
cur_request st' = Some (dstp, Join2 dstp, GetSuccList).
Proof.
intros.
repeat (handler_def || handler_simpl);
intuition (repeat eexists; eauto).
Qed.
Lemma cur_request_preserved_by_do_delayed_queries :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
cur_request st = cur_request st'.
Proof.
intros; handler_def; reflexivity.
Qed.
Inductive possible_nts (st : data) : list timeout -> Prop :=
| NilPossible :
possible_nts st []
| TickPossible :
possible_nts st [Tick]
| RectifyTickPossible :
possible_nts st [RectifyTick]
| KeepaliveTickPossible :
possible_nts st [KeepaliveTick]
| Stabilize2RequestPossible :
forall h dstp p,
cur_request st = Some (dstp, Stabilize, p) ->
possible_nts st [Request h GetSuccList]
| JoinGSLRequestPossible :
forall h j dstp p,
cur_request st = Some (dstp, Join j, p) ->
possible_nts st [Request h GetSuccList]
| JoinGBPRequestPossible :
forall h j dstp p,
cur_request st = Some (dstp, Join j, p) ->
possible_nts st [Request h (GetBestPredecessor (ptr st))]
| RefreshRequestPossible :
forall dstp q p,
cur_request st = Some (dstp, q, p) ->
possible_nts st [Request (addr_of dstp) p].
Hint Constructors possible_nts.
Inductive possible_cts (st : data) : list timeout -> Prop :=
| NilClearedPossible :
possible_cts st []
| KeepaliveTickClearedPossible :
possible_cts st [KeepaliveTick]
| CurRequestClearedPossible :
forall dstp q p,
cur_request st = Some (dstp, q, p) ->
possible_cts st [Request (addr_of dstp) p]
| CurRequestAndKeepaliveTickClearedPossible :
forall dstp q p,
cur_request st = Some (dstp, q, p) ->
possible_cts st [Request (addr_of dstp) p; KeepaliveTick]
| GetBestPredClearedPossible :
possible_cts st (timeouts_in st).
Hint Constructors possible_cts.
Lemma recv_handler_possible_nts :
forall src dst st p st' ms nts cts,
recv_handler src dst st p = (st', ms, nts, cts) ->
possible_nts st nts.
Proof.
intros.
repeat (handler_def || handler_simpl).
Qed.
Hint Resolve recv_handler_possible_nts.
Lemma recv_handler_nodup_nts :
forall src dst st p st' ms nts cts,
recv_handler src dst st p = (st', ms, nts, cts) ->
NoDup nts.
Proof.
intros.
assert (possible_nts st nts) by eauto.
invcs_prop possible_nts; eauto.
Qed.
Lemma recv_handler_possible_cts :
forall src dst st p st' ms nts cts,
recv_handler src dst st p = (st', ms, nts, cts) ->
possible_cts st cts.
Proof.
intros.
repeat (handler_def || handler_simpl).
Qed.
Lemma recv_handler_nodup_cts :
forall src dst st p st' ms nts cts,
recv_handler src dst st p = (st', ms, nts, cts) ->
NoDup cts.
Proof.
intros.
repeat (handler_def || handler_simpl).
Qed.
Lemma recv_handler_small_cts :
forall src dst st p st' ms nts cts,
recv_handler src dst st p = (st', ms, nts, cts) ->
length cts <= 2.
Proof.
intros.
repeat (handler_def || handler_simpl).
Qed.
Lemma recv_handler_sets_cur_request_when_adding_new_timeout :
forall src h st p st' ms nts cts,
recv_handler src h st p = (st', ms, nts, cts) ->
forall dst req,
In (Request dst req) nts ->
~ In (Request dst req) cts ->
exists dstp q,
addr_of dstp = dst /\
query_request q req /\
cur_request st' = Some (dstp, q, req).
Proof.
intros.
repeat (handler_def || handler_simpl || expand_def).
Qed.
Lemma split_eq_singleton :
forall A (x y : A) xs ys,
[x] = xs ++ y :: ys ->
x = y /\
xs = [] /\
ys = [].
Proof.
destruct xs; destruct ys;
intros; simpl in *.
- intuition congruence.
- find_inversion.
- find_inversion;
exfalso; eapply app_cons_not_nil; eauto.
- find_inversion;
exfalso; eapply app_cons_not_nil; eauto.
Qed.
Lemma recv_handler_sends_request_when_adding_new_timeout :
forall src h st p st' ms nts cts,
recv_handler src h st p = (st', ms, nts, cts) ->
forall dst req,
In (Request dst req) nts ->
~ In (Request dst req) cts ->
In (dst, req) ms /\
request_payload req /\
forall dst' req' xs ys,
ms = xs ++ (dst, req) :: ys ->
request_payload req' ->
In (dst', req') (xs ++ ys) ->
False.
Proof.
intros.
repeat (handler_def || handler_simpl || expand_def);
intuition;
solve [find_copy_apply_lem_hyp split_eq_singleton; expand_def; tauto].
Qed.
Lemma handle_query_req_only_sends_responses :
forall st src p dst res,
In (dst, res) (handle_query_req st src p) ->
response_payload res.
Proof.
unfold handle_query_req.
intros.
repeat break_match; simpl in *; intuition; find_injection; auto.
Qed.
Hint Resolve handle_query_req_only_sends_responses.
Lemma handle_delayed_query_only_sends_responses :
forall h st l dst p,
In (dst, p) (concat (map (handle_delayed_query h st) l)) ->
response_payload p.
Proof.
intros until 0.
rewrite <- flat_map_concat_map.
intros.
find_apply_lem_hyp in_flat_map; expand_def.
unfold handle_delayed_query in *.
repeat break_match; eauto.
Qed.
Hint Resolve handle_delayed_query_only_sends_responses.
Lemma request_response_mutually_exclusive :
forall p,
request_payload p ->
response_payload p ->
False.
Proof.
intros.
destruct p;
invcs_prop request_payload;
invcs_prop response_payload.
Qed.
Hint Resolve request_response_mutually_exclusive.
Lemma recv_handler_adds_new_timeout_when_sending_request :
forall src h st p st' ms nts cts,
recv_handler src h st p = (st', ms, nts, cts) ->
forall dst req,
request_payload req ->
In (dst, req) ms ->
In (Request dst req) nts.
Proof.
intros.
repeat (handler_def || handler_simpl || expand_def);
repeat (handler_simpl || in_crush);
try solve [inv_prop request_payload].
Qed.
Lemma recv_handler_updating_succ_list :
forall src h st p st' ms nts cts,
recv_handler src h st p = (st', ms, nts, cts) ->
succ_list st' <> succ_list st ->
exists query_dst q m,
cur_request st = Some (query_dst, q, m) /\
addr_of query_dst = src /\
exists succs,
(exists pr, p = GotPredAndSuccs pr succs) \/
p = GotSuccList succs.
Proof.
intros.
repeat handler_def; simpl in * |-; try congruence;
repeat find_injection;
repeat eexists; eauto.
Qed.
Lemma recv_handler_sets_succ_list_when_setting_joined :
forall src dst st m st' ms nts cts,
recv_handler src dst st m = (st', ms, nts, cts) ->
joined st = false ->
joined st' = true ->
exists succs s uccs,
m = GotSuccList succs /\
succ_list st' = s :: uccs.
Proof.
intros.
repeat (handler_def || handler_simpl).
unfold make_succs, chop_succs.
pose proof succ_list_len_lower_bound.
destruct SUCC_LIST_LEN; try omega.
simpl; eexists; eauto.
Qed.
Lemma hd_in_chop_succs :
forall x l,
In x (chop_succs (x :: l)).
Proof.
intros.
unfold chop_succs.
pose proof succ_list_len_lower_bound.
destruct SUCC_LIST_LEN; try omega.
rewrite firstn_cons; in_crush.
Qed.
Hint Resolve hd_in_chop_succs.
Lemma recv_handler_setting_joined_makes_succ_list_nonempty :
forall src dst st m st' ms nts cts,
recv_handler src dst st m = (st', ms, nts, cts) ->
joined st = false ->
joined st' = true ->
succ_list st' <> [].
Proof.
intros.
find_eapply_lem_hyp recv_handler_sets_succ_list_when_setting_joined; eauto.
expand_def.
eauto.
Qed.
Lemma option_map_Some :
forall A B (f : A -> B) a b,
option_map f a = Some b ->
exists a', a = Some a' /\
f a' = b.
Proof.
intros.
destruct a; simpl in *; try congruence.
find_injection.
eexists; eauto.
Qed.
Lemma option_map_None :
forall A B (f : A -> B) a,
option_map f a = None ->
a = None.
Proof.
intros.
destruct a; simpl in *; congruence.
Qed.
Lemma in_concat :
forall A (x : A) (l : list (list A)),
In x (concat l) ->
exists xs,
In xs l /\
In x xs.
Proof.
induction l; intros; simpl in *; auto.
- intuition.
- in_crush; eauto.
break_exists_exists. intuition.
Qed.
Lemma handle_query_req_GotPredAndSuccs_response_accurate :
forall st src m ms,
handle_query_req st src m = ms ->
forall dst pr succs,
In (dst, GotPredAndSuccs pr succs) ms ->
pr = pred st /\
succs = succ_list st.
Proof.
intros.
unfold handle_query_req in *; break_match; subst;
try in_crush; try congruence.
Qed.
Hint Resolve handle_query_req_GotPredAndSuccs_response_accurate.
Lemma handle_delayed_queries_GotPredAndSuccs_response_accurate :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
forall dst pr succs,
In (dst, GotPredAndSuccs pr succs) ms ->
pr = pred st' /\
succs = succ_list st'.
Proof.
unfold do_delayed_queries, handle_delayed_query.
intros.
break_match; find_injection; try solve [in_crush].
find_apply_lem_hyp in_concat; expand_def.
match goal with
| H: _ |- _ => rewrite -> in_map_iff in H; expand_def; break_let; subst
end.
simpl in *; eauto.
Qed.
Hint Resolve handle_delayed_queries_GotPredAndSuccs_response_accurate.
Lemma handle_query_req_GotSuccList_response_accurate :
forall st src m ms,
handle_query_req st src m = ms ->
forall dst succs,
In (dst, GotSuccList succs) ms ->
succs = succ_list st.
Proof.
intros.
unfold handle_query_req in *; break_match; subst;
try in_crush; try congruence.
Qed.
Hint Resolve handle_query_req_GotSuccList_response_accurate.
Lemma handle_delayed_queries_GotSuccList_response_accurate :
forall h st st' ms nts cts,
do_delayed_queries h st = (st', ms, nts, cts) ->
forall dst succs,
In (dst, GotSuccList succs) ms ->
succs = succ_list st'.
Proof.
unfold do_delayed_queries, handle_delayed_query.
intros.
break_match; find_injection; try solve [in_crush].
find_apply_lem_hyp in_concat; expand_def.
match goal with
| H: _ |- _ => rewrite -> in_map_iff in H; expand_def; break_let; subst
end.
simpl in *.
simpl in *; eauto.
Qed.
Hint Resolve handle_delayed_queries_GotSuccList_response_accurate.
Lemma recv_handler_GotPredAndSuccs_response_accurate :
forall src dst st p st' ms nts cts h pr succs,
recv_handler src dst st p = (st', ms, nts, cts) ->
In (h, GotPredAndSuccs pr succs) ms ->
pr = pred st' /\
succs = succ_list st'.
Proof.
intros.
repeat match goal with
| H : context[do_delayed_queries] |- _ => fail 1
| |- _ => handler_def
end.
find_apply_lem_hyp in_app_or; break_or_hyp; eauto.
repeat handler_def; simpl in *; try break_or_hyp; repeat find_injection; try (congruence || tauto).
eauto.
Qed.
Hint Resolve recv_handler_GotPredAndSuccs_response_accurate.
Lemma handle_msg_GotSuccList_response_accurate :
forall src dst st p st' ms nts cts h succs,
handle_msg src dst st p = (st', ms, nts, cts) ->
In (h, GotSuccList succs) ms ->
succs = succ_list st'.
Proof.
intros.
repeat handler_def || handler_simpl.
Qed.
Hint Resolve handle_msg_GotSuccList_response_accurate.
Lemma responses_request_timeout_handler_accurate :
forall h st dst msg st' ms nts cts eff,
request_timeout_handler h st dst msg = (st', ms, nts, cts, eff) ->
forall dst m succs,
In (dst, m) ms ->
succs_msg m succs ->
succs = succ_list st'.
Proof.
intros.
handler_def; auto.
in_crush.
- repeat match goal with
| H: context[do_delayed_queries] |- _ => clear H
| |- _ =>
progress (repeat handler_def; try simpl in *; intuition)
| H: context[option_map] |- _ =>
eapply option_map_Some in H; eauto; expand_def
| H: _ = _ |- _ => injc H
end; invcs_prop succs_msg.
- inv_prop succs_msg.
+ eapply handle_delayed_queries_GotSuccList_response_accurate; eauto.
+ eapply handle_delayed_queries_GotPredAndSuccs_response_accurate; eauto.
Qed.
Lemma joining_start_handler_st_joined:
forall h k st ms nts,
start_handler h [k] = (st, ms, nts) ->
joined st = false.
Proof.
unfold start_handler.
intros.
simpl in *; find_injection.
reflexivity.
Qed.
Lemma start_handler_with_single_known :
forall h k,
start_handler h (k :: nil) = pi (start_query h (init_state_join h k) (Join (make_pointer k))).
Proof.
easy.
Qed.
Hint Rewrite start_handler_with_single_known.
Lemma open_pi :
forall (x : res) a b c,
pi x = (a, b, c) ->
exists d,
x = (a, b, c, d).
Proof.
intros.
destruct x as [[[? ?] ?] ?]; simpl in *; tuple_inversion.
eauto.
Qed.
Lemma sort_one_element :
forall h x,
sort_by_between h [x] = [x].
Proof.
intros. unfold sort_by_between, Sorting.sort, Sorting.iter_merge.
reflexivity.
Qed.
Lemma length_chop_succs :
forall l,
length (chop_succs l) <= SUCC_LIST_LEN.
Proof.
intros. unfold chop_succs. apply firstn_le_length.
Qed.
Lemma chop_succs_short_list :
forall l,
length l <= SUCC_LIST_LEN ->
chop_succs l = l.
Proof.
eauto using firstn_all2.
Qed.
Lemma in_sort_by_between :
forall x h l,
In x (sort_by_between h l) ->
In x l.
Proof.
intros.
eapply Permutation.Permutation_in.
apply Permutation.Permutation_sym.
eapply sort_by_between_permutes.
eauto.
eauto.
Qed.
Lemma query_request_request :
forall q p,
query_request q p ->
request_payload p.
Proof.
intros; inv_prop query_request; eauto.
Qed.
Hint Resolve query_request_request.
Lemma query_response_response :
forall q p,
query_response q p ->
response_payload p.
Proof.
intros; inv_prop query_response; eauto.
Qed.
Hint Resolve query_response_response.
Hint Resolve request_response_mutually_exclusive.
Lemma recv_handler_response_clears_cur_request_q_single :
forall h st dst q req res st' ms nts cts,
recv_handler (addr_of dst) h st res = (st', ms, nts, cts) ->
cur_request st = Some (dst, q, req) ->
query_response q res ->
q <> Stabilize ->
(forall k, q <> Join k) ->
cur_request st' = None.
Proof.
intros.
repeat (handler_def || handler_simpl);
try find_copy_apply_lem_hyp is_request_same_as_request_payload;
solve [exfalso; eauto
|inv_prop query_response].
Qed.
Hint Resolve recv_handler_response_clears_cur_request_q_single.
Lemma recv_handler_response_changes_cur_request_q_Stabilize :
forall h st dst p succs st' ms nts cts,
recv_handler (addr_of dst) h st (GotPredAndSuccs p succs) = (st', ms, nts, cts) ->
cur_request st = Some (dst, Stabilize, GetPredAndSuccs) ->
cur_request st' = None \/
exists ns,
p = Some ns /\
ptr_between (ptr st) ns (make_pointer (addr_of dst)) /\
cur_request st' = Some (ns, Stabilize2 ns, GetSuccList).
Proof.
intros.
repeat (handler_def || handler_simpl);
try solve [exfalso; eauto; inv_prop request_response_pair].
repeat find_rewrite || find_injection.
exfalso; eauto.
Qed.
Hint Resolve recv_handler_response_changes_cur_request_q_Stabilize.
|
// megafunction wizard: %LPM_ADD_SUB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_ADD_SUB
// ============================================================
// File Name: add.v
// Megafunction Name(s):
// LPM_ADD_SUB
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 14.1.0 Build 186 12/03/2014 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module add (
clock,
dataa,
datab,
result);
input clock;
input [8:0] dataa;
input [8:0] datab;
output [8:0] result;
wire [8:0] sub_wire0;
wire [8:0] result = sub_wire0[8:0];
lpm_add_sub LPM_ADD_SUB_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0)
// synopsys translate_off
,
.aclr (),
.add_sub (),
.cin (),
.clken (),
.cout (),
.overflow ()
// synopsys translate_on
);
defparam
LPM_ADD_SUB_component.lpm_direction = "ADD",
LPM_ADD_SUB_component.lpm_hint = "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO",
LPM_ADD_SUB_component.lpm_pipeline = 1,
LPM_ADD_SUB_component.lpm_representation = "SIGNED",
LPM_ADD_SUB_component.lpm_type = "LPM_ADD_SUB",
LPM_ADD_SUB_component.lpm_width = 9;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CarryIn NUMERIC "0"
// Retrieval info: PRIVATE: CarryOut NUMERIC "0"
// Retrieval info: PRIVATE: ConstantA NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: Function NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: Overflow NUMERIC "0"
// Retrieval info: PRIVATE: RadixA NUMERIC "10"
// Retrieval info: PRIVATE: RadixB NUMERIC "10"
// Retrieval info: PRIVATE: Representation NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: ValidCtA NUMERIC "0"
// Retrieval info: PRIVATE: ValidCtB NUMERIC "0"
// Retrieval info: PRIVATE: WhichConstant NUMERIC "0"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "9"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD"
// Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "9"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 9 0 INPUT NODEFVAL "dataa[8..0]"
// Retrieval info: USED_PORT: datab 0 0 9 0 INPUT NODEFVAL "datab[8..0]"
// Retrieval info: USED_PORT: result 0 0 9 0 OUTPUT NODEFVAL "result[8..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 9 0 dataa 0 0 9 0
// Retrieval info: CONNECT: @datab 0 0 9 0 datab 0 0 9 0
// Retrieval info: CONNECT: result 0 0 9 0 @result 0 0 9 0
// Retrieval info: GEN_FILE: TYPE_NORMAL add.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL add.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL add_bb.v FALSE
// Retrieval info: LIB_FILE: lpm
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DECAP_8_V
`define SKY130_FD_SC_LP__DECAP_8_V
/**
* decap: Decoupling capacitance filler.
*
* Verilog wrapper for decap with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__decap.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_8 (
VPWR,
VGND,
VPB ,
VNB
);
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__decap base (
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__decap_8 ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__decap base ();
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DECAP_8_V
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_v1_11_0_pipe_clock.v
// Version : 1.11
//------------------------------------------------------------------------------
// Filename : pipe_clock.v
// Description : PIPE Clock Module for 7 Series Transceiver
// Version : 15.3
//------------------------------------------------------------------------------
`timescale 1ns / 1ps
//---------- PIPE Clock Module -------------------------------------------------
module pcie_7x_v1_11_0_pipe_clock #
(
parameter PCIE_ASYNC_EN = "FALSE", // PCIe async enable
parameter PCIE_TXBUF_EN = "FALSE", // PCIe TX buffer enable for Gen1/Gen2 only
parameter PCIE_LANE = 1, // PCIe number of lanes
parameter PCIE_LINK_SPEED = 3, // PCIe link speed
parameter PCIE_REFCLK_FREQ = 0, // PCIe reference clock frequency
parameter PCIE_USERCLK1_FREQ = 2, // PCIe user clock 1 frequency
parameter PCIE_USERCLK2_FREQ = 2, // PCIe user clock 2 frequency
parameter PCIE_OOBCLK_MODE = 1, // PCIe oob clock mode
parameter PCIE_DEBUG_MODE = 0 // PCIe Debug mode
)
(
//---------- Input -------------------------------------
input CLK_CLK,
input CLK_TXOUTCLK,
input [PCIE_LANE-1:0] CLK_RXOUTCLK_IN,
input CLK_RST_N,
input [PCIE_LANE-1:0] CLK_PCLK_SEL,
input CLK_GEN3,
//---------- Output ------------------------------------
output CLK_PCLK,
output CLK_RXUSRCLK,
output [PCIE_LANE-1:0] CLK_RXOUTCLK_OUT,
output CLK_DCLK,
output CLK_OOBCLK,
output CLK_USERCLK1,
output CLK_USERCLK2,
output CLK_MMCM_LOCK,
output o_clk_in_stopped
);
//---------- Select Clock Divider ----------------------
localparam DIVCLK_DIVIDE = (PCIE_REFCLK_FREQ == 2) ? 1 :
(PCIE_REFCLK_FREQ == 1) ? 1 : 1;
localparam CLKFBOUT_MULT_F = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKIN1_PERIOD = (PCIE_REFCLK_FREQ == 2) ? 4 :
(PCIE_REFCLK_FREQ == 1) ? 8 : 10;
localparam CLKOUT0_DIVIDE_F = 8;
localparam CLKOUT1_DIVIDE = 4;
localparam CLKOUT2_DIVIDE = (PCIE_USERCLK1_FREQ == 5) ? 2 :
(PCIE_USERCLK1_FREQ == 4) ? 4 :
(PCIE_USERCLK1_FREQ == 3) ? 8 :
(PCIE_USERCLK1_FREQ == 1) ? 32 : 16;
localparam CLKOUT3_DIVIDE = (PCIE_USERCLK2_FREQ == 5) ? 2 :
(PCIE_USERCLK2_FREQ == 4) ? 4 :
(PCIE_USERCLK2_FREQ == 3) ? 8 :
(PCIE_USERCLK2_FREQ == 1) ? 32 : 16;
localparam CLKOUT4_DIVIDE = 20;
//---------- Select Reference Clock --------------------
localparam REFCLK_SEL = ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3)) ? 1'd1 : 1'd0;
//---------- Input Registers ---------------------------
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg1 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg1 = 1'd0;
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg [PCIE_LANE-1:0] pclk_sel_reg2 = {PCIE_LANE{1'd0}};
(* ASYNC_REG = "TRUE", SHIFT_EXTRACT = "NO" *) reg gen3_reg2 = 1'd0;
//---------- Internal Signals --------------------------
wire refclk;
wire mmcm_fb;
wire clk_125mhz;
wire clk_125mhz_buf;
wire clk_250mhz;
wire userclk1;
wire userclk2;
wire oobclk;
reg pclk_sel = 1'd0;
//---------- Output Registers --------------------------
wire pclk_1;
wire pclk;
wire userclk1_1;
wire userclk2_1;
wire mmcm_lock;
//---------- Generate Per-Lane Signals -----------------
genvar i; // Index for per-lane signals
//---------- Input FF ----------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= {PCIE_LANE{1'd0}};
gen3_reg1 <= 1'd0;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= {PCIE_LANE{1'd0}};
gen3_reg2 <= 1'd0;
end
else
begin
//---------- 1st Stage FF --------------------------
pclk_sel_reg1 <= CLK_PCLK_SEL;
gen3_reg1 <= CLK_GEN3;
//---------- 2nd Stage FF --------------------------
pclk_sel_reg2 <= pclk_sel_reg1;
gen3_reg2 <= gen3_reg1;
end
end
//---------- Select Reference clock or TXOUTCLK --------------------------------
generate if ((PCIE_TXBUF_EN == "TRUE") && (PCIE_LINK_SPEED != 3))
begin : refclk_i
//---------- Select Reference Clock ----------------------------------------
BUFG refclk_i
(
//---------- Input -------------------------------------
.I (CLK_CLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
else
begin : txoutclk_i
//---------- Select TXOUTCLK -----------------------------------------------
BUFG txoutclk_i
(
//---------- Input -------------------------------------
.I (CLK_TXOUTCLK),
//---------- Output ------------------------------------
.O (refclk)
);
end
endgenerate
//---------- MMCM --------------------------------------------------------------
MMCME2_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("ZHOLD"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_F),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (CLKOUT0_DIVIDE_F),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (CLKOUT1_DIVIDE),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKOUT2_DIVIDE (CLKOUT2_DIVIDE),
.CLKOUT2_PHASE (0.000),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT2_USE_FINE_PS ("FALSE"),
.CLKOUT3_DIVIDE (CLKOUT3_DIVIDE),
.CLKOUT3_PHASE (0.000),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT3_USE_FINE_PS ("FALSE"),
.CLKOUT4_DIVIDE (CLKOUT4_DIVIDE),
.CLKOUT4_PHASE (0.000),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT4_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (CLKIN1_PERIOD),
.REF_JITTER1 (0.010)
)
mmcm_i
(
//---------- Input ------------------------------------
.CLKIN1 (refclk),
.CLKIN2 (1'd0), // not used, comment out CLKIN2 if it cause implementation issues
//.CLKIN2 (refclk), // not used, comment out CLKIN2 if it cause implementation issues
.CLKINSEL (1'd1),
.CLKFBIN (mmcm_fb),
.RST (!CLK_RST_N),
.PWRDWN (1'd0),
//---------- Output ------------------------------------
.CLKFBOUT (mmcm_fb),
.CLKFBOUTB (),
.CLKOUT0 (clk_125mhz),
.CLKOUT0B (),
.CLKOUT1 (clk_250mhz),
.CLKOUT1B (),
.CLKOUT2 (userclk1),
.CLKOUT2B (),
.CLKOUT3 (userclk2),
.CLKOUT3B (),
.CLKOUT4 (oobclk),
.CLKOUT5 (),
.CLKOUT6 (),
.LOCKED (mmcm_lock),
//---------- Dynamic Reconfiguration -------------------
.DCLK ( 1'd0),
.DADDR ( 7'd0),
.DEN ( 1'd0),
.DWE ( 1'd0),
.DI (16'd0),
.DO (),
.DRDY (),
//---------- Dynamic Phase Shift -----------------------
.PSCLK (1'd0),
.PSEN (1'd0),
.PSINCDEC (1'd0),
.PSDONE (),
//---------- Status ------------------------------------
.CLKINSTOPPED (o_clk_in_stopped),
.CLKFBSTOPPED ()
);
//---------- Select PCLK MUX ---------------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : pclk_i1_bufgctrl
//---------- PCLK Mux ----------------------------------
BUFGCTRL pclk_i1
(
//---------- Input ---------------------------------
.CE0 (1'd1),
.CE1 (1'd1),
.I0 (clk_125mhz),
.I1 (clk_250mhz),
.IGNORE0 (1'd0),
.IGNORE1 (1'd0),
.S0 (~pclk_sel),
.S1 ( pclk_sel),
//---------- Output --------------------------------
.O (pclk_1)
);
end
else
//---------- Select PCLK Buffer ------------------------
begin : pclk_i1_bufg
//---------- PCLK Buffer -------------------------------
BUFG pclk_i1
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (clk_125mhz_buf)
);
assign pclk_1 = clk_125mhz_buf;
end
endgenerate
//---------- Generate RXOUTCLK Buffer for Debug --------------------------------
generate if ((PCIE_DEBUG_MODE == 1) || (PCIE_ASYNC_EN == "TRUE"))
begin : rxoutclk_per_lane
//---------- Generate per Lane -------------------------
for (i=0; i<PCIE_LANE; i=i+1)
begin : rxoutclk_i
//---------- RXOUTCLK Buffer -----------------------
BUFG rxoutclk_i
(
//---------- Input -----------------------------
.I (CLK_RXOUTCLK_IN[i]),
//---------- Output ----------------------------
.O (CLK_RXOUTCLK_OUT[i])
);
end
end
else
//---------- Disable RXOUTCLK Buffer for Normal Operation
begin : rxoutclk_i_disable
assign CLK_RXOUTCLK_OUT = {PCIE_LANE{1'd0}};
end
endgenerate
//---------- Generate DCLK Buffer ----------------------------------------------
generate if (PCIE_LINK_SPEED != 1)
begin : dclk_i_bufg
//---------- DCLK Buffer -------------------------------
BUFG dclk_i
(
//---------- Input ---------------------------------
.I (clk_125mhz),
//---------- Output --------------------------------
.O (CLK_DCLK)
);
end
else
//---------- Disable DCLK Buffer -----------------------
begin : dclk_i
assign CLK_DCLK = clk_125mhz_buf; // always 125 MHz in Gen1
end
endgenerate
//---------- Generate USERCLK1 Buffer ------------------------------------------
generate if (PCIE_USERCLK1_FREQ != 0)
begin : userclk1_i1
//---------- USERCLK1 Buffer ---------------------------
BUFG usrclk1_i1
(
//---------- Input ---------------------------------
.I (userclk1),
//---------- Output --------------------------------
.O (userclk1_1)
);
end
else
//---------- Disable USERCLK1 Buffer -------------------
begin : disable_userclk1_i1
assign userclk1_1 = 1'd0;
end
endgenerate
//---------- Generate USERCLK2 Buffer ------------------------------------------
generate if (PCIE_USERCLK2_FREQ != 0)
begin : userclk2_i1
//---------- USERCLK2 Buffer ---------------------------
BUFG usrclk2_i1
(
//---------- Input ---------------------------------
.I (userclk2),
//---------- Output --------------------------------
.O (userclk2_1)
);
end
else
//---------- Disable USERCLK2 Buffer -------------------
begin : userclk2_i1_disable
assign userclk2_1 = 1'd0;
end
endgenerate
//---------- Generate OOBCLK Buffer --------------------------------------------
generate if (PCIE_OOBCLK_MODE == 2)
begin : oobclk_i1
//---------- OOBCLK Buffer -----------------------------
BUFG oobclk_i1
(
//---------- Input ---------------------------------
.I (oobclk),
//---------- Output --------------------------------
.O (CLK_OOBCLK)
);
end
else
//---------- Disable OOBCLK Buffer ---------------------
begin : oobclk_i1_disable
assign CLK_OOBCLK = pclk;
end
endgenerate
//---------- Generate 2nd Stage Buffers ----------------------------------------
generate if ((PCIE_LINK_SPEED == 3) && (PCIE_ASYNC_EN == "TRUE"))
begin : second_stage_buf
//---------- PCLK Buffer ---------------------------------------------------
BUFG pclk_i2
(
//---------- Input -------------------------------------
.I (pclk_1),
//---------- Output ------------------------------------
.O (pclk)
);
//---------- RXUSRCLK Mux --------------------------------------------------
BUFGCTRL rxusrclk_i2
(
//---------- Input ---------------------------------
.CE0 (1'b1),
.CE1 (1'b1),
.I0 (pclk_1),
.I1 (CLK_RXOUTCLK_IN[0]),
.IGNORE0 (1'b0),
.IGNORE1 (1'b0),
.S0 (~gen3_reg2),
.S1 ( gen3_reg2),
//---------- Output --------------------------------
.O (CLK_RXUSRCLK)
);
//---------- Generate USERCLK1 Buffer --------------------------------------
if (PCIE_USERCLK1_FREQ != 0)
begin : userclk1_i2
//---------- USERCLK1 Buffer -----------------------
BUFG usrclk1_i2
(
//---------- Input -----------------------------
.I (userclk1_1),
//---------- Output ----------------------------
.O (CLK_USERCLK1)
);
end
else
//---------- Disable USERCLK1 Buffer ---------------
begin : userclk1_i2_disable
assign CLK_USERCLK1 = userclk1_1;
end
//---------- Generate USERCLK2 Buffer --------------------------------------
if (PCIE_USERCLK2_FREQ != 0)
begin : userclk2_i2
//---------- USERCLK2 Buffer -----------------------
BUFG usrclk2_i2
(
//---------- Input -----------------------------
.I (userclk2_1),
//---------- Output ----------------------------
.O (CLK_USERCLK2)
);
end
else
//---------- Disable USERCLK2 Buffer ---------------
begin : userclk2_i2_disable
assign CLK_USERCLK2 = userclk2_1;
end
end
else
//---------- Disable 2nd Stage Buffer --------------------------------------
begin : second_stage_buf_disable
assign pclk = pclk_1;
assign CLK_RXUSRCLK = pclk_1;
assign CLK_USERCLK1 = userclk1_1;
assign CLK_USERCLK2 = userclk2_1;
end
endgenerate
//---------- Select PCLK -------------------------------------------------------
always @ (posedge pclk)
begin
if (!CLK_RST_N)
pclk_sel <= 1'd0;
else
begin
//---------- Select 250 MHz ------------------------
if (&pclk_sel_reg2)
pclk_sel <= 1'd1;
//---------- Select 125 MHz ------------------------
else if (&(~pclk_sel_reg2))
pclk_sel <= 1'd0;
//---------- Hold PCLK -----------------------------
else
pclk_sel <= pclk_sel;
end
end
//---------- PIPE Clock Output -------------------------------------------------
assign CLK_PCLK = pclk;
assign CLK_MMCM_LOCK = mmcm_lock;
endmodule
|
`timescale 1us/100ns
module testbench ();
initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
end
reg [0:0] clk = 0;
reg [0:0] resetn = 0;
initial begin
// pull reset if available
resetn = 0;
repeat(10) #1 clk = !clk;
// release reset if available
resetn = 1;
forever #1 clk = !clk;
end
reg [0:0] SPI_CS = 1;
reg [0:0] SPI_CLK = 0;
reg [0:0] SPI_MOSI = 0;
wire [0:0] first_byte;
reg [0:0] first_byte_expected;
wire [7:0] read_value;
reg [7:0] read_value_expected;
wire [0:0] done;
localparam FCLK = 100;
localparam BAUDRATE = 15;
localparam HALFBITTIME = FCLK / BAUDRATE / 2;
task send_byte;
input [7:0] byte;
input [3:0] bitcount;
integer i;
// for(i=0; i<8; i=i+1)
begin
for(i=0; i<bitcount; i=i+1) begin
SPI_MOSI <= byte[7-i];
#HALFBITTIME SPI_CLK <= 1;
#HALFBITTIME SPI_CLK <= 0;
end
SPI_MOSI <= 0;
#HALFBITTIME;
end
endtask
// CPOL == 0: clock state while idle is low ("inactive")
// CPOL == 1: clock state while idle is high ("inactive")
parameter CPOL = 0;
// CPHA == 0: write on clock deactivation, sample on clock activation
// CPHA == 1: write on clock activation, sample on clock deactivation
parameter CPHA = 0;
parameter LSBFIRST = 1;
spi_slave #(.CPOL (CPOL),
.CPHA (CPHA),
.LSBFIRST (LSBFIRST),
.TIMEOUT__NOT_CS(0),
.TIMEOUT_CYCLES (1))
DUT (.clk (clk),
.resetn (resetn),
.spi_clk (SPI_CLK),
.spi_mosi (SPI_MOSI),
.spi_cs (SPI_CS),
.read_value (read_value),
.done (done),
.timeout_expired (),
.first_byte (first_byte),
.debug_info ()
);
initial begin
SPI_CS = 1;
#20 SPI_CS <= 0;
read_value_expected <= 8'h81; first_byte_expected <= 1; #1 send_byte(read_value_expected, 8);
read_value_expected <= "@"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
read_value_expected <= "A"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
read_value_expected <= "B"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
read_value_expected <= "C"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
#1 SPI_CS <= 1;
// this is an incomplete transmission
// "done" should not get 1, if it gets 1, the test should fail, since MOSI was inverted
#20 SPI_CS <= 0;
read_value_expected <= "0"; first_byte_expected <= 1; #1 send_byte(~read_value_expected, 7);
#1 SPI_CS <= 1;
// the incomplete transmission shall not have any consequences for following receptions
#20 SPI_CS <= 0;
read_value_expected <= "0"; first_byte_expected <= 1; #1 send_byte(read_value_expected, 8);
read_value_expected <= "-"; first_byte_expected <= 0; #1 send_byte(read_value_expected, 8);
#1 SPI_CS <= 1;
#100 $finish;
end
always @(posedge done) begin
if (read_value == read_value_expected)
$display("pass: value: %c, is_first_byte: %b", read_value, first_byte);
else
$display("fail: value(expected): %c / 0x%X (%c / 0x%X), first_byte: %b(%b)", read_value, read_value, read_value_expected, read_value_expected, first_byte, first_byte_expected);
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* IPv4 and ARP block with UDP support, ethernet frame interface (64 bit datapath)
*/
module udp_complete_64 #(
parameter ARP_CACHE_ADDR_WIDTH = 9,
parameter ARP_REQUEST_RETRY_COUNT = 4,
parameter ARP_REQUEST_RETRY_INTERVAL = 125000000*2,
parameter ARP_REQUEST_TIMEOUT = 125000000*30,
parameter UDP_CHECKSUM_GEN_ENABLE = 1,
parameter UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH = 2048,
parameter UDP_CHECKSUM_HEADER_FIFO_DEPTH = 8
)
(
input wire clk,
input wire rst,
/*
* Ethernet frame input
*/
input wire s_eth_hdr_valid,
output wire s_eth_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [63:0] s_eth_payload_axis_tdata,
input wire [7:0] s_eth_payload_axis_tkeep,
input wire s_eth_payload_axis_tvalid,
output wire s_eth_payload_axis_tready,
input wire s_eth_payload_axis_tlast,
input wire s_eth_payload_axis_tuser,
/*
* Ethernet frame output
*/
output wire m_eth_hdr_valid,
input wire m_eth_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [63:0] m_eth_payload_axis_tdata,
output wire [7:0] m_eth_payload_axis_tkeep,
output wire m_eth_payload_axis_tvalid,
input wire m_eth_payload_axis_tready,
output wire m_eth_payload_axis_tlast,
output wire m_eth_payload_axis_tuser,
/*
* IP input
*/
input wire s_ip_hdr_valid,
output wire s_ip_hdr_ready,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_length,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [63:0] s_ip_payload_axis_tdata,
input wire [7:0] s_ip_payload_axis_tkeep,
input wire s_ip_payload_axis_tvalid,
output wire s_ip_payload_axis_tready,
input wire s_ip_payload_axis_tlast,
input wire s_ip_payload_axis_tuser,
/*
* IP output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_ip_eth_dest_mac,
output wire [47:0] m_ip_eth_src_mac,
output wire [15:0] m_ip_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [63:0] m_ip_payload_axis_tdata,
output wire [7:0] m_ip_payload_axis_tkeep,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* UDP input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [5:0] s_udp_ip_dscp,
input wire [1:0] s_udp_ip_ecn,
input wire [7:0] s_udp_ip_ttl,
input wire [31:0] s_udp_ip_source_ip,
input wire [31:0] s_udp_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [63:0] s_udp_payload_axis_tdata,
input wire [7:0] s_udp_payload_axis_tkeep,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* UDP output
*/
output wire m_udp_hdr_valid,
input wire m_udp_hdr_ready,
output wire [47:0] m_udp_eth_dest_mac,
output wire [47:0] m_udp_eth_src_mac,
output wire [15:0] m_udp_eth_type,
output wire [3:0] m_udp_ip_version,
output wire [3:0] m_udp_ip_ihl,
output wire [5:0] m_udp_ip_dscp,
output wire [1:0] m_udp_ip_ecn,
output wire [15:0] m_udp_ip_length,
output wire [15:0] m_udp_ip_identification,
output wire [2:0] m_udp_ip_flags,
output wire [12:0] m_udp_ip_fragment_offset,
output wire [7:0] m_udp_ip_ttl,
output wire [7:0] m_udp_ip_protocol,
output wire [15:0] m_udp_ip_header_checksum,
output wire [31:0] m_udp_ip_source_ip,
output wire [31:0] m_udp_ip_dest_ip,
output wire [15:0] m_udp_source_port,
output wire [15:0] m_udp_dest_port,
output wire [15:0] m_udp_length,
output wire [15:0] m_udp_checksum,
output wire [63:0] m_udp_payload_axis_tdata,
output wire [7:0] m_udp_payload_axis_tkeep,
output wire m_udp_payload_axis_tvalid,
input wire m_udp_payload_axis_tready,
output wire m_udp_payload_axis_tlast,
output wire m_udp_payload_axis_tuser,
/*
* Status
*/
output wire ip_rx_busy,
output wire ip_tx_busy,
output wire udp_rx_busy,
output wire udp_tx_busy,
output wire ip_rx_error_header_early_termination,
output wire ip_rx_error_payload_early_termination,
output wire ip_rx_error_invalid_header,
output wire ip_rx_error_invalid_checksum,
output wire ip_tx_error_payload_early_termination,
output wire ip_tx_error_arp_failed,
output wire udp_rx_error_header_early_termination,
output wire udp_rx_error_payload_early_termination,
output wire udp_tx_error_payload_early_termination,
/*
* Configuration
*/
input wire [47:0] local_mac,
input wire [31:0] local_ip,
input wire [31:0] gateway_ip,
input wire [31:0] subnet_mask,
input wire clear_arp_cache
);
wire ip_rx_ip_hdr_valid;
wire ip_rx_ip_hdr_ready;
wire [47:0] ip_rx_ip_eth_dest_mac;
wire [47:0] ip_rx_ip_eth_src_mac;
wire [15:0] ip_rx_ip_eth_type;
wire [3:0] ip_rx_ip_version;
wire [3:0] ip_rx_ip_ihl;
wire [5:0] ip_rx_ip_dscp;
wire [1:0] ip_rx_ip_ecn;
wire [15:0] ip_rx_ip_length;
wire [15:0] ip_rx_ip_identification;
wire [2:0] ip_rx_ip_flags;
wire [12:0] ip_rx_ip_fragment_offset;
wire [7:0] ip_rx_ip_ttl;
wire [7:0] ip_rx_ip_protocol;
wire [15:0] ip_rx_ip_header_checksum;
wire [31:0] ip_rx_ip_source_ip;
wire [31:0] ip_rx_ip_dest_ip;
wire [63:0] ip_rx_ip_payload_axis_tdata;
wire [7:0] ip_rx_ip_payload_axis_tkeep;
wire ip_rx_ip_payload_axis_tvalid;
wire ip_rx_ip_payload_axis_tlast;
wire ip_rx_ip_payload_axis_tuser;
wire ip_rx_ip_payload_axis_tready;
wire ip_tx_ip_hdr_valid;
wire ip_tx_ip_hdr_ready;
wire [5:0] ip_tx_ip_dscp;
wire [1:0] ip_tx_ip_ecn;
wire [15:0] ip_tx_ip_length;
wire [7:0] ip_tx_ip_ttl;
wire [7:0] ip_tx_ip_protocol;
wire [31:0] ip_tx_ip_source_ip;
wire [31:0] ip_tx_ip_dest_ip;
wire [63:0] ip_tx_ip_payload_axis_tdata;
wire [7:0] ip_tx_ip_payload_axis_tkeep;
wire ip_tx_ip_payload_axis_tvalid;
wire ip_tx_ip_payload_axis_tlast;
wire ip_tx_ip_payload_axis_tuser;
wire ip_tx_ip_payload_axis_tready;
wire udp_rx_ip_hdr_valid;
wire udp_rx_ip_hdr_ready;
wire [47:0] udp_rx_ip_eth_dest_mac;
wire [47:0] udp_rx_ip_eth_src_mac;
wire [15:0] udp_rx_ip_eth_type;
wire [3:0] udp_rx_ip_version;
wire [3:0] udp_rx_ip_ihl;
wire [5:0] udp_rx_ip_dscp;
wire [1:0] udp_rx_ip_ecn;
wire [15:0] udp_rx_ip_length;
wire [15:0] udp_rx_ip_identification;
wire [2:0] udp_rx_ip_flags;
wire [12:0] udp_rx_ip_fragment_offset;
wire [7:0] udp_rx_ip_ttl;
wire [7:0] udp_rx_ip_protocol;
wire [15:0] udp_rx_ip_header_checksum;
wire [31:0] udp_rx_ip_source_ip;
wire [31:0] udp_rx_ip_dest_ip;
wire [63:0] udp_rx_ip_payload_axis_tdata;
wire [7:0] udp_rx_ip_payload_axis_tkeep;
wire udp_rx_ip_payload_axis_tvalid;
wire udp_rx_ip_payload_axis_tlast;
wire udp_rx_ip_payload_axis_tuser;
wire udp_rx_ip_payload_axis_tready;
wire udp_tx_ip_hdr_valid;
wire udp_tx_ip_hdr_ready;
wire [5:0] udp_tx_ip_dscp;
wire [1:0] udp_tx_ip_ecn;
wire [15:0] udp_tx_ip_length;
wire [7:0] udp_tx_ip_ttl;
wire [7:0] udp_tx_ip_protocol;
wire [31:0] udp_tx_ip_source_ip;
wire [31:0] udp_tx_ip_dest_ip;
wire [63:0] udp_tx_ip_payload_axis_tdata;
wire [7:0] udp_tx_ip_payload_axis_tkeep;
wire udp_tx_ip_payload_axis_tvalid;
wire udp_tx_ip_payload_axis_tlast;
wire udp_tx_ip_payload_axis_tuser;
wire udp_tx_ip_payload_axis_tready;
/*
* Input classifier (ip_protocol)
*/
wire s_select_udp = (ip_rx_ip_protocol == 8'h11);
wire s_select_ip = !s_select_udp;
reg s_select_udp_reg = 1'b0;
reg s_select_ip_reg = 1'b0;
always @(posedge clk) begin
if (rst) begin
s_select_udp_reg <= 1'b0;
s_select_ip_reg <= 1'b0;
end else begin
if (ip_rx_ip_payload_axis_tvalid) begin
if ((!s_select_udp_reg && !s_select_ip_reg) ||
(ip_rx_ip_payload_axis_tvalid && ip_rx_ip_payload_axis_tready && ip_rx_ip_payload_axis_tlast)) begin
s_select_udp_reg <= s_select_udp;
s_select_ip_reg <= s_select_ip;
end
end else begin
s_select_udp_reg <= 1'b0;
s_select_ip_reg <= 1'b0;
end
end
end
// IP frame to UDP module
assign udp_rx_ip_hdr_valid = s_select_udp && ip_rx_ip_hdr_valid;
assign udp_rx_ip_eth_dest_mac = ip_rx_ip_eth_dest_mac;
assign udp_rx_ip_eth_src_mac = ip_rx_ip_eth_src_mac;
assign udp_rx_ip_eth_type = ip_rx_ip_eth_type;
assign udp_rx_ip_version = ip_rx_ip_version;
assign udp_rx_ip_ihl = ip_rx_ip_ihl;
assign udp_rx_ip_dscp = ip_rx_ip_dscp;
assign udp_rx_ip_ecn = ip_rx_ip_ecn;
assign udp_rx_ip_length = ip_rx_ip_length;
assign udp_rx_ip_identification = ip_rx_ip_identification;
assign udp_rx_ip_flags = ip_rx_ip_flags;
assign udp_rx_ip_fragment_offset = ip_rx_ip_fragment_offset;
assign udp_rx_ip_ttl = ip_rx_ip_ttl;
assign udp_rx_ip_protocol = 8'h11;
assign udp_rx_ip_header_checksum = ip_rx_ip_header_checksum;
assign udp_rx_ip_source_ip = ip_rx_ip_source_ip;
assign udp_rx_ip_dest_ip = ip_rx_ip_dest_ip;
assign udp_rx_ip_payload_axis_tdata = ip_rx_ip_payload_axis_tdata;
assign udp_rx_ip_payload_axis_tkeep = ip_rx_ip_payload_axis_tkeep;
assign udp_rx_ip_payload_axis_tvalid = s_select_udp_reg && ip_rx_ip_payload_axis_tvalid;
assign udp_rx_ip_payload_axis_tlast = ip_rx_ip_payload_axis_tlast;
assign udp_rx_ip_payload_axis_tuser = ip_rx_ip_payload_axis_tuser;
// External IP frame output
assign m_ip_hdr_valid = s_select_ip && ip_rx_ip_hdr_valid;
assign m_ip_eth_dest_mac = ip_rx_ip_eth_dest_mac;
assign m_ip_eth_src_mac = ip_rx_ip_eth_src_mac;
assign m_ip_eth_type = ip_rx_ip_eth_type;
assign m_ip_version = ip_rx_ip_version;
assign m_ip_ihl = ip_rx_ip_ihl;
assign m_ip_dscp = ip_rx_ip_dscp;
assign m_ip_ecn = ip_rx_ip_ecn;
assign m_ip_length = ip_rx_ip_length;
assign m_ip_identification = ip_rx_ip_identification;
assign m_ip_flags = ip_rx_ip_flags;
assign m_ip_fragment_offset = ip_rx_ip_fragment_offset;
assign m_ip_ttl = ip_rx_ip_ttl;
assign m_ip_protocol = ip_rx_ip_protocol;
assign m_ip_header_checksum = ip_rx_ip_header_checksum;
assign m_ip_source_ip = ip_rx_ip_source_ip;
assign m_ip_dest_ip = ip_rx_ip_dest_ip;
assign m_ip_payload_axis_tdata = ip_rx_ip_payload_axis_tdata;
assign m_ip_payload_axis_tkeep = ip_rx_ip_payload_axis_tkeep;
assign m_ip_payload_axis_tvalid = s_select_ip_reg && ip_rx_ip_payload_axis_tvalid;
assign m_ip_payload_axis_tlast = ip_rx_ip_payload_axis_tlast;
assign m_ip_payload_axis_tuser = ip_rx_ip_payload_axis_tuser;
assign ip_rx_ip_hdr_ready = (s_select_udp && udp_rx_ip_hdr_ready) ||
(s_select_ip && m_ip_hdr_ready);
assign ip_rx_ip_payload_axis_tready = (s_select_udp_reg && udp_rx_ip_payload_axis_tready) ||
(s_select_ip_reg && m_ip_payload_axis_tready);
/*
* Output arbiter
*/
ip_arb_mux #(
.S_COUNT(2),
.DATA_WIDTH(64),
.KEEP_ENABLE(1),
.ID_ENABLE(0),
.DEST_ENABLE(0),
.USER_ENABLE(1),
.USER_WIDTH(1),
.ARB_TYPE_ROUND_ROBIN(0),
.ARB_LSB_HIGH_PRIORITY(1)
)
ip_arb_mux_inst (
.clk(clk),
.rst(rst),
// IP frame inputs
.s_ip_hdr_valid({s_ip_hdr_valid, udp_tx_ip_hdr_valid}),
.s_ip_hdr_ready({s_ip_hdr_ready, udp_tx_ip_hdr_ready}),
.s_eth_dest_mac(0),
.s_eth_src_mac(0),
.s_eth_type(0),
.s_ip_version(0),
.s_ip_ihl(0),
.s_ip_dscp({s_ip_dscp, udp_tx_ip_dscp}),
.s_ip_ecn({s_ip_ecn, udp_tx_ip_ecn}),
.s_ip_length({s_ip_length, udp_tx_ip_length}),
.s_ip_identification(0),
.s_ip_flags(0),
.s_ip_fragment_offset(0),
.s_ip_ttl({s_ip_ttl, udp_tx_ip_ttl}),
.s_ip_protocol({s_ip_protocol, udp_tx_ip_protocol}),
.s_ip_header_checksum(0),
.s_ip_source_ip({s_ip_source_ip, udp_tx_ip_source_ip}),
.s_ip_dest_ip({s_ip_dest_ip, udp_tx_ip_dest_ip}),
.s_ip_payload_axis_tdata({s_ip_payload_axis_tdata, udp_tx_ip_payload_axis_tdata}),
.s_ip_payload_axis_tkeep({s_ip_payload_axis_tkeep, udp_tx_ip_payload_axis_tkeep}),
.s_ip_payload_axis_tvalid({s_ip_payload_axis_tvalid, udp_tx_ip_payload_axis_tvalid}),
.s_ip_payload_axis_tready({s_ip_payload_axis_tready, udp_tx_ip_payload_axis_tready}),
.s_ip_payload_axis_tlast({s_ip_payload_axis_tlast, udp_tx_ip_payload_axis_tlast}),
.s_ip_payload_axis_tid(0),
.s_ip_payload_axis_tdest(0),
.s_ip_payload_axis_tuser({s_ip_payload_axis_tuser, udp_tx_ip_payload_axis_tuser}),
// IP frame output
.m_ip_hdr_valid(ip_tx_ip_hdr_valid),
.m_ip_hdr_ready(ip_tx_ip_hdr_ready),
.m_eth_dest_mac(),
.m_eth_src_mac(),
.m_eth_type(),
.m_ip_version(),
.m_ip_ihl(),
.m_ip_dscp(ip_tx_ip_dscp),
.m_ip_ecn(ip_tx_ip_ecn),
.m_ip_length(ip_tx_ip_length),
.m_ip_identification(),
.m_ip_flags(),
.m_ip_fragment_offset(),
.m_ip_ttl(ip_tx_ip_ttl),
.m_ip_protocol(ip_tx_ip_protocol),
.m_ip_header_checksum(),
.m_ip_source_ip(ip_tx_ip_source_ip),
.m_ip_dest_ip(ip_tx_ip_dest_ip),
.m_ip_payload_axis_tdata(ip_tx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(ip_tx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(ip_tx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(ip_tx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(ip_tx_ip_payload_axis_tlast),
.m_ip_payload_axis_tid(),
.m_ip_payload_axis_tdest(),
.m_ip_payload_axis_tuser(ip_tx_ip_payload_axis_tuser)
);
/*
* IP stack
*/
ip_complete_64 #(
.ARP_CACHE_ADDR_WIDTH(ARP_CACHE_ADDR_WIDTH),
.ARP_REQUEST_RETRY_COUNT(ARP_REQUEST_RETRY_COUNT),
.ARP_REQUEST_RETRY_INTERVAL(ARP_REQUEST_RETRY_INTERVAL),
.ARP_REQUEST_TIMEOUT(ARP_REQUEST_TIMEOUT)
)
ip_complete_64_inst (
.clk(clk),
.rst(rst),
// Ethernet frame input
.s_eth_hdr_valid(s_eth_hdr_valid),
.s_eth_hdr_ready(s_eth_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_eth_payload_axis_tdata(s_eth_payload_axis_tdata),
.s_eth_payload_axis_tkeep(s_eth_payload_axis_tkeep),
.s_eth_payload_axis_tvalid(s_eth_payload_axis_tvalid),
.s_eth_payload_axis_tready(s_eth_payload_axis_tready),
.s_eth_payload_axis_tlast(s_eth_payload_axis_tlast),
.s_eth_payload_axis_tuser(s_eth_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// IP frame input
.s_ip_hdr_valid(ip_tx_ip_hdr_valid),
.s_ip_hdr_ready(ip_tx_ip_hdr_ready),
.s_ip_dscp(ip_tx_ip_dscp),
.s_ip_ecn(ip_tx_ip_ecn),
.s_ip_length(ip_tx_ip_length),
.s_ip_ttl(ip_tx_ip_ttl),
.s_ip_protocol(ip_tx_ip_protocol),
.s_ip_source_ip(ip_tx_ip_source_ip),
.s_ip_dest_ip(ip_tx_ip_dest_ip),
.s_ip_payload_axis_tdata(ip_tx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(ip_tx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(ip_tx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(ip_tx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(ip_tx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(ip_tx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(ip_rx_ip_hdr_valid),
.m_ip_hdr_ready(ip_rx_ip_hdr_ready),
.m_ip_eth_dest_mac(ip_rx_ip_eth_dest_mac),
.m_ip_eth_src_mac(ip_rx_ip_eth_src_mac),
.m_ip_eth_type(ip_rx_ip_eth_type),
.m_ip_version(ip_rx_ip_version),
.m_ip_ihl(ip_rx_ip_ihl),
.m_ip_dscp(ip_rx_ip_dscp),
.m_ip_ecn(ip_rx_ip_ecn),
.m_ip_length(ip_rx_ip_length),
.m_ip_identification(ip_rx_ip_identification),
.m_ip_flags(ip_rx_ip_flags),
.m_ip_fragment_offset(ip_rx_ip_fragment_offset),
.m_ip_ttl(ip_rx_ip_ttl),
.m_ip_protocol(ip_rx_ip_protocol),
.m_ip_header_checksum(ip_rx_ip_header_checksum),
.m_ip_source_ip(ip_rx_ip_source_ip),
.m_ip_dest_ip(ip_rx_ip_dest_ip),
.m_ip_payload_axis_tdata(ip_rx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(ip_rx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(ip_rx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(ip_rx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(ip_rx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(ip_rx_ip_payload_axis_tuser),
// Status
.rx_busy(ip_rx_busy),
.tx_busy(ip_tx_busy),
.rx_error_header_early_termination(ip_rx_error_header_early_termination),
.rx_error_payload_early_termination(ip_rx_error_payload_early_termination),
.rx_error_invalid_header(ip_rx_error_invalid_header),
.rx_error_invalid_checksum(ip_rx_error_invalid_checksum),
.tx_error_payload_early_termination(ip_tx_error_payload_early_termination),
.tx_error_arp_failed(ip_tx_error_arp_failed),
// Configuration
.local_mac(local_mac),
.local_ip(local_ip),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask),
.clear_arp_cache(clear_arp_cache)
);
/*
* UDP interface
*/
udp_64 #(
.CHECKSUM_GEN_ENABLE(UDP_CHECKSUM_GEN_ENABLE),
.CHECKSUM_PAYLOAD_FIFO_DEPTH(UDP_CHECKSUM_PAYLOAD_FIFO_DEPTH),
.CHECKSUM_HEADER_FIFO_DEPTH(UDP_CHECKSUM_HEADER_FIFO_DEPTH)
)
udp_64_inst (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(udp_rx_ip_hdr_valid),
.s_ip_hdr_ready(udp_rx_ip_hdr_ready),
.s_ip_eth_dest_mac(udp_rx_ip_eth_dest_mac),
.s_ip_eth_src_mac(udp_rx_ip_eth_src_mac),
.s_ip_eth_type(udp_rx_ip_eth_type),
.s_ip_version(udp_rx_ip_version),
.s_ip_ihl(udp_rx_ip_ihl),
.s_ip_dscp(udp_rx_ip_dscp),
.s_ip_ecn(udp_rx_ip_ecn),
.s_ip_length(udp_rx_ip_length),
.s_ip_identification(udp_rx_ip_identification),
.s_ip_flags(udp_rx_ip_flags),
.s_ip_fragment_offset(udp_rx_ip_fragment_offset),
.s_ip_ttl(udp_rx_ip_ttl),
.s_ip_protocol(udp_rx_ip_protocol),
.s_ip_header_checksum(udp_rx_ip_header_checksum),
.s_ip_source_ip(udp_rx_ip_source_ip),
.s_ip_dest_ip(udp_rx_ip_dest_ip),
.s_ip_payload_axis_tdata(udp_rx_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(udp_rx_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(udp_rx_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(udp_rx_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(udp_rx_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(udp_rx_ip_payload_axis_tuser),
// IP frame output
.m_ip_hdr_valid(udp_tx_ip_hdr_valid),
.m_ip_hdr_ready(udp_tx_ip_hdr_ready),
.m_ip_eth_dest_mac(),
.m_ip_eth_src_mac(),
.m_ip_eth_type(),
.m_ip_version(),
.m_ip_ihl(),
.m_ip_dscp(udp_tx_ip_dscp),
.m_ip_ecn(udp_tx_ip_ecn),
.m_ip_length(udp_tx_ip_length),
.m_ip_identification(),
.m_ip_flags(),
.m_ip_fragment_offset(),
.m_ip_ttl(udp_tx_ip_ttl),
.m_ip_protocol(udp_tx_ip_protocol),
.m_ip_header_checksum(),
.m_ip_source_ip(udp_tx_ip_source_ip),
.m_ip_dest_ip(udp_tx_ip_dest_ip),
.m_ip_payload_axis_tdata(udp_tx_ip_payload_axis_tdata),
.m_ip_payload_axis_tkeep(udp_tx_ip_payload_axis_tkeep),
.m_ip_payload_axis_tvalid(udp_tx_ip_payload_axis_tvalid),
.m_ip_payload_axis_tready(udp_tx_ip_payload_axis_tready),
.m_ip_payload_axis_tlast(udp_tx_ip_payload_axis_tlast),
.m_ip_payload_axis_tuser(udp_tx_ip_payload_axis_tuser),
// UDP frame input
.s_udp_hdr_valid(s_udp_hdr_valid),
.s_udp_hdr_ready(s_udp_hdr_ready),
.s_udp_eth_dest_mac(48'd0),
.s_udp_eth_src_mac(48'd0),
.s_udp_eth_type(16'd0),
.s_udp_ip_version(4'd0),
.s_udp_ip_ihl(4'd0),
.s_udp_ip_dscp(s_udp_ip_dscp),
.s_udp_ip_ecn(s_udp_ip_ecn),
.s_udp_ip_identification(16'd0),
.s_udp_ip_flags(3'd0),
.s_udp_ip_fragment_offset(13'd0),
.s_udp_ip_ttl(s_udp_ip_ttl),
.s_udp_ip_header_checksum(16'd0),
.s_udp_ip_source_ip(s_udp_ip_source_ip),
.s_udp_ip_dest_ip(s_udp_ip_dest_ip),
.s_udp_source_port(s_udp_source_port),
.s_udp_dest_port(s_udp_dest_port),
.s_udp_length(s_udp_length),
.s_udp_checksum(s_udp_checksum),
.s_udp_payload_axis_tdata(s_udp_payload_axis_tdata),
.s_udp_payload_axis_tkeep(s_udp_payload_axis_tkeep),
.s_udp_payload_axis_tvalid(s_udp_payload_axis_tvalid),
.s_udp_payload_axis_tready(s_udp_payload_axis_tready),
.s_udp_payload_axis_tlast(s_udp_payload_axis_tlast),
.s_udp_payload_axis_tuser(s_udp_payload_axis_tuser),
// UDP frame output
.m_udp_hdr_valid(m_udp_hdr_valid),
.m_udp_hdr_ready(m_udp_hdr_ready),
.m_udp_eth_dest_mac(m_udp_eth_dest_mac),
.m_udp_eth_src_mac(m_udp_eth_src_mac),
.m_udp_eth_type(m_udp_eth_type),
.m_udp_ip_version(m_udp_ip_version),
.m_udp_ip_ihl(m_udp_ip_ihl),
.m_udp_ip_dscp(m_udp_ip_dscp),
.m_udp_ip_ecn(m_udp_ip_ecn),
.m_udp_ip_length(m_udp_ip_length),
.m_udp_ip_identification(m_udp_ip_identification),
.m_udp_ip_flags(m_udp_ip_flags),
.m_udp_ip_fragment_offset(m_udp_ip_fragment_offset),
.m_udp_ip_ttl(m_udp_ip_ttl),
.m_udp_ip_protocol(m_udp_ip_protocol),
.m_udp_ip_header_checksum(m_udp_ip_header_checksum),
.m_udp_ip_source_ip(m_udp_ip_source_ip),
.m_udp_ip_dest_ip(m_udp_ip_dest_ip),
.m_udp_source_port(m_udp_source_port),
.m_udp_dest_port(m_udp_dest_port),
.m_udp_length(m_udp_length),
.m_udp_checksum(m_udp_checksum),
.m_udp_payload_axis_tdata(m_udp_payload_axis_tdata),
.m_udp_payload_axis_tkeep(m_udp_payload_axis_tkeep),
.m_udp_payload_axis_tvalid(m_udp_payload_axis_tvalid),
.m_udp_payload_axis_tready(m_udp_payload_axis_tready),
.m_udp_payload_axis_tlast(m_udp_payload_axis_tlast),
.m_udp_payload_axis_tuser(m_udp_payload_axis_tuser),
// Status
.rx_busy(udp_rx_busy),
.tx_busy(udp_tx_busy),
.rx_error_header_early_termination(udp_rx_error_header_early_termination),
.rx_error_payload_early_termination(udp_rx_error_payload_early_termination),
.tx_error_payload_early_termination(udp_tx_error_payload_early_termination)
);
endmodule
`resetall
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module DE0_NANO_SOC_QSYS_sw (
// inputs:
address,
chipselect,
clk,
in_port,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input [ 9: 0] in_port;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 9: 0] d1_data_in;
reg [ 9: 0] d2_data_in;
wire [ 9: 0] data_in;
reg [ 9: 0] edge_capture;
wire edge_capture_wr_strobe;
wire [ 9: 0] edge_detect;
wire irq;
reg [ 9: 0] irq_mask;
wire [ 9: 0] read_mux_out;
reg [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = ({10 {(address == 0)}} & data_in) |
({10 {(address == 2)}} & irq_mask) |
({10 {(address == 3)}} & edge_capture);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= {32'b0 | read_mux_out};
end
assign data_in = in_port;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
irq_mask <= 0;
else if (chipselect && ~write_n && (address == 2))
irq_mask <= writedata[9 : 0];
end
assign irq = |(edge_capture & irq_mask);
assign edge_capture_wr_strobe = chipselect && ~write_n && (address == 3);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[0] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[0] <= 0;
else if (edge_detect[0])
edge_capture[0] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[1] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[1] <= 0;
else if (edge_detect[1])
edge_capture[1] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[2] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[2] <= 0;
else if (edge_detect[2])
edge_capture[2] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[3] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[3] <= 0;
else if (edge_detect[3])
edge_capture[3] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[4] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[4] <= 0;
else if (edge_detect[4])
edge_capture[4] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[5] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[5] <= 0;
else if (edge_detect[5])
edge_capture[5] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[6] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[6] <= 0;
else if (edge_detect[6])
edge_capture[6] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[7] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[7] <= 0;
else if (edge_detect[7])
edge_capture[7] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[8] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[8] <= 0;
else if (edge_detect[8])
edge_capture[8] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
edge_capture[9] <= 0;
else if (clk_en)
if (edge_capture_wr_strobe)
edge_capture[9] <= 0;
else if (edge_detect[9])
edge_capture[9] <= -1;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
d1_data_in <= 0;
d2_data_in <= 0;
end
else if (clk_en)
begin
d1_data_in <= data_in;
d2_data_in <= d1_data_in;
end
end
assign edge_detect = d1_data_in ^ d2_data_in;
endmodule
|
//phase 3: testing LSL, LSR, 32bit
`timescale 1ns/10ps
module ARMStb();
reg [31:0] instrbus;
reg [31:0] instrbusin[0:29];
wire [31:0] iaddrbus, dselect;
reg [31:0] iaddrbusout[0:29], dselectout[0:29];
wire [31:0] dbus;
reg [31:0] databusk, dbusout[0:29];
reg clk, reset;
reg clkd;
reg [31:0] dontcare;
reg [24*8:1] iname[0:29];
integer error, k, ntests;
//all opcode parameters to be used
parameter ADD = 11'b10001011000;
parameter ADDI = 10'b1001000100;
parameter ADDIS = 10'b1011000100;
parameter ADDS = 11'b10101011000;
parameter AND = 11'b10001010000;
parameter ANDI = 10'b1001001000;
parameter ANDIS = 10'b1111001000;
parameter ANDS = 11'b11101010000;
parameter CBNZ = 8'b10110101;
parameter CBZ = 8'b10110100;
parameter EOR = 11'b11001010000;
parameter EORI = 10'b1101001000;
parameter LDUR = 11'b11111000010;
parameter LSL = 11'b11010011011;
parameter LSR = 11'b11010011010;
parameter MOVZ = 9'b110100101;
parameter ORR = 11'b10101010000;
parameter ORRI = 10'b1011001000;
parameter STUR = 11'b11111000000;
parameter SUB = 11'b11001011000;
parameter SUBI = 10'b1101000100;
parameter SUBIS = 10'b1111000100;
parameter SUBS = 11'b11101011000;
parameter B = 6'b000101;
parameter B_EQ = 8'b01010101;
parameter B_NE = 8'b01010110;
parameter B_LT = 8'b01010111;
parameter B_GT = 8'b01011000;
//register parameters
parameter R0 = 5'b00000;
parameter R0_dselect = 32'b00000000000000000000000000000001;
parameter R18 = 5'b10010;
parameter R18_dselect = 32'b00000000000001000000000000000000;
parameter R19 = 5'b10011;
parameter R19_dselect = 32'b00000000000010000000000000000000;
parameter R20 = 5'b10100;
parameter R20_dselect = 32'b00000000000100000000000000000000;
parameter R21 = 5'b10101;
parameter R21_dselect = 32'b00000000001000000000000000000000;
parameter R22 = 5'b10110;
parameter R22_dselect = 32'b00000000010000000000000000000000;
parameter R23 = 5'b10111;
parameter R23_dselect = 32'b00000000100000000000000000000000;
parameter R24 = 5'b11000;
parameter R24_dselect = 32'b00000001000000000000000000000000;
parameter R25 = 5'b11001;
parameter R25_dselect = 32'b00000010000000000000000000000000;
parameter R26 = 5'b11010;
parameter R26_dselect = 32'b00000100000000000000000000000000;
parameter R27 = 5'b11011;
parameter R27_dselect = 32'b00001000000000000000000000000000;
parameter R28 = 5'b11100;
parameter R28_dselect = 32'b00010000000000000000000000000000;
parameter R29 = 5'b11101;
parameter R29_dselect = 32'b00100000000000000000000000000000;
parameter R30 = 5'b11110;
parameter R30_dselect = 32'b01000000000000000000000000000000;
parameter R31 = 5'b11111;
parameter R31_dselect = 32'b10000000000000000000000000000000;
//other parameterz to be used
parameter zeroSham = 6'b000000;
parameter RX = 5'b11111;
parameter oneShamt = 6'b000001;
parameter twoShamt = 6'b000010;
parameter threeShamt = 6'b000011;
parameter eightShamt = 6'b001000;
ARMS dut(.reset(reset),.clk(clk),.iaddrbus(iaddrbus),.ibus(instrbus),.dbus(dbus),.dselect(dselect));
initial begin
dontcare = 32'hx;
//phase 1: testing basic op commands and instruction bus
//* ADDI, R20, R31, #AAA
iname[0] = "ADDI, R20, R31, #AAA";//testing addi, result in R20 = 00000AAA
iaddrbusout[0] = 32'h00000000;
// opcode rm/ALUImm rn rd...
instrbusin[0]={ADDI, 12'hAAA, R31, R20};
dselectout[0] = R20_dselect;
dbusout[0] = 32'h00000AAA;
//* ADDI, R31, R23, #002
iname[1] = "ADDI, R31, R23, #002";//testing addi on R31, result in R31 = 00000000
iaddrbusout[1] = 32'h00000004;
// opcode rm/ALUImm rn rd...
instrbusin[1]={ADDI, 12'h002, R23, R31};
dselectout[1] = R31_dselect;
dbusout[1] = dontcare;
//* ADDI, R0, R23, #002
iname[2] = "ADDI, R0, R23, #002";//testing addi on R0, result in R0 = 00000002
iaddrbusout[2] = 32'h00000008;
// opcode rm/ALUImm rn rd...
instrbusin[2]={ADDI, 12'h002, R23, R0};
dselectout[2] = R0_dselect;
dbusout[2] = 32'h00000002;
//* ORRI, R21, R24, #001
iname[3] = "ORRI, R21, R24, #001";//testing ori, result in R21 = 00000001
iaddrbusout[3] = 32'h0000000C;
// opcode rm/ALUImm rn rd...
instrbusin[3]={ORRI, 12'h001, R24, R21};
dselectout[3] = R21_dselect;
dbusout[3] = 32'h00000001;
//* EORI, R22, R20, #000
iname[4] = "EORI, R22, R20, #000";//testing xori, result in R22 = 00000AAA
iaddrbusout[4] = 32'h00000010;
// opcode rm/ALUImm rn rd...
instrbusin[4]={EORI, 12'h000, R20, R22};
dselectout[4] = R22_dselect;
dbusout[4] = 32'h00000AAA;
//* ANDI, R23, R0, #003
iname[5] = "ANDI, R23, R0, #003";//testing andi, result in R23 = 00000002
iaddrbusout[5] = 32'h00000014;
// opcode rm/ALUImm rn rd...
instrbusin[5]={ANDI, 12'h003, R0, R23};
dselectout[5] = R23_dselect;
dbusout[5] = 32'h00000002;
//* SUBI, R24, R20, #00A
iname[6] = "SUBI, R24, R20, #00A";//testing subi, result in R24 = 00000AA0
iaddrbusout[6] = 32'h00000018;
// opcode rm/ALUImm rn rd...
instrbusin[6]={SUBI, 12'h00A, R20, R24};
dselectout[6] = R24_dselect;
dbusout[6] = 32'h00000AA0;
// op, rd, rn, rm
//* ADD, R25, R20, R0
iname[7] = "ADD, R25, R20, R0";//testing add, result in R25 = 00000AAC
iaddrbusout[7] = 32'h0000001C;
// op, rm, shamt, rn, rd
instrbusin[7]={ADD, R0, zeroSham, R20, R25};
dselectout[7] = R25_dselect;
dbusout[7] = 32'h00000AAC;
// op, rd, rn, rm
//* AND, R26, R20, R22
iname[8] = "AND, R26, R20, R22";//testing and, result in R26 = 00000AAA
iaddrbusout[8] = 32'h00000020;
// op, rm, shamt, rn, rd
instrbusin[8]={AND, R22, zeroSham, R20, R26};
dselectout[8] = R26_dselect;
dbusout[8] = 32'h00000AAA;
// op, rd, rn, rm
//* XOR, R27, R23, R21
iname[9] = "EOR, R27, R23, R21";//testing xor, result in R27 = 00000003
iaddrbusout[9] = 32'h00000024;
// op, rm, shamt, rn, rd
instrbusin[9]={EOR, R21, zeroSham, R23, R27};
dselectout[9] = R27_dselect;
dbusout[9] = 32'h00000003;
// op, rd, rn, rm
//* OR, R28, R25, R23
iname[10] = "ORR, R28, R25, R23";//testing or, result in R28 = 00000AAE
iaddrbusout[10] = 32'h00000028;
// op, rm, shamt, rn, rd
instrbusin[10]={ORR, R23, zeroSham, R25, R28};
dselectout[10] = R28_dselect;
dbusout[10] = 32'h00000AAE;
// op, rd, rn, rm
//* SUB, R29, R20, R22
iname[11] = "SUB, R29, R20, R22";//testing sub, result in R29 = 00000000
iaddrbusout[11] = 32'h0000002C;
// op, rm, shamt, rn, rd
instrbusin[11]={SUB, R22, zeroSham, R20, R29};
dselectout[11] = R29_dselect;
dbusout[11] = 32'h00000000;
// op, rd, rn, aluImm
//* ADDI, R30, R31, #000
iname[12] = "ADDI, R30, R31, #000";//testing addi on R31, result in R30 = 00000000
iaddrbusout[12] = 32'h00000030;
// opcode rm/ALUImm rn rd...
instrbusin[12]={ADDI, 12'h000, R31, R30};
dselectout[12] = R30_dselect;
dbusout[12] = 32'h00000000;
//phase 2: testing basic op codes with the n,z,c flags
// op, rd, rn, aluImm
//* SUBIS,R20, R0, #003
iname[13] = "SUBIS,R20, R0, #003";//testing subis, n flag, result in R20 = FFFFFFFF
iaddrbusout[13] = 32'h00000034;
// opcode rm/ALUImm rn rd...
instrbusin[13] = {SUBIS, 12'h003, R0, R20};
dselectout[13] = dontcare;
dbusout[13] = dontcare;
// op, rd, rn, rm
//* SUBS, R21, R25, R28
iname[14] = "SUBS, R21, R25, R28";//testing subs, n flag, result in R21 = FFFFFFFE
iaddrbusout[14] = 32'h00000038;
// op, rm, shamt, rn, rd
instrbusin[14] = {SUBS, R28, zeroSham, R25, R21};
dselectout[14] = dontcare;
dbusout[14] = dontcare;
// op, rd, rn, aluImm
//* ADDIS,R22, R31, #000
iname[15] = "ADDIS,R22, R31, #000";//testing addis, z flag, result in R22 = 00000000
iaddrbusout[15] = 32'h0000003C;
// opcode rm/ALUImm rn rd...
instrbusin[15] = {ADDIS, 12'h000, R31, R22};
dselectout[15] = dontcare;
dbusout[15] = dontcare;
// op, rd, rn, rm
//* ADDS R23, R20, R23
iname[16] = "ADDS R23, R20, R23";//testing adds, c flag, result in R23 = 00000001
iaddrbusout[16] = 32'h00000040;
// op, rm, shamt, rn, rd
instrbusin[16] = {ADDS, R23, zeroSham, R20, R23};
dselectout[16] = dontcare;
dbusout[16] = dontcare;
// op, rd, rn, aluImm
//* ANDIS,R24, R20, #002
iname[17] = "ANDIS,R24, R20, #002";//testing andis, reseting n,z flags to low, result in R24 = 00000002
iaddrbusout[17] = 32'h00000044;
// opcode rm/ALUImm rn rd...
instrbusin[17] = {ANDIS, 12'h002, R20, R24};
dselectout[17] = dontcare;
dbusout[17] = dontcare;
// op, rd, rn, rm
//* ANDS, R25, R21, R20
iname[18] = "ANDS, R25, R21, R20";//testing ands, n flag, result in R25 = FFFFFFFE
iaddrbusout[18] = 32'h00000048;
// op, rm, shamt, rn, rd
instrbusin[18] = {ANDS, R20, zeroSham, R21, R25};
dselectout[18] = dontcare;
dbusout[18] = dontcare;
//phase 3: testing LSL, LSR
//setting up the register R20 for a test of the LSL
// op, rd, rn, rm
iname[19] ="ADDI, R20, R31, #007";//setting up for left shift, result in R20 = 0000000000000007
iaddrbusout[19] = 64'h0000004C;
// opcode rm/ALUImm rn rd
instrbusin[19] ={ADDI, 12'h007, R31, R20};
dselectout[19] = R20_dselect;
dbusout[19] = 64'h00000007;
// op, rd, rn, rm
iname[20] ="ADDI, R21, R31, #700";//setting up for right shift, n flag, result in R21 = 0000000000000700
iaddrbusout[20] = 64'h00000050;
// opcode rm/ALUImm rn rd
instrbusin[20] ={ADDI, 12'h700, R31, R21};
dselectout[20] = R21_dselect;
dbusout[20] = 64'h00000700;
// op, rd, rn, rm
iname[21] ="AND, R19, R31, R31";//delay, result in R19 = 0000000000000000
iaddrbusout[21] = 64'h00000054;
// op, rm, shamt, rn, rd
instrbusin[21] ={AND, R31, zeroSham, R31, R19};
dselectout[21] = R19_dselect;
dbusout[21] = 64'h00000000;
// op, rd, rn, rm
iname[22] ="AND, R18, R31, R31";//delay, result in R18 = 0000000000000000
iaddrbusout[22] = 64'h00000058;
// op, rm, shamt, rn, rd
instrbusin[22] ={AND, R31, zeroSham, R31, R18};
dselectout[22] = R18_dselect;
dbusout[22] = 64'h00000000;
// op, rd, rn, rm
iname[23] ="LSL, R20, R20, 2";//testing left shift, result in R20 = 0000000000000700
iaddrbusout[23] = 64'h0000005C;
// op, rm, shamt, rn, rd
instrbusin[23] ={LSL, RX, eightShamt, R20, R20};
dselectout[23] = R20_dselect;
dbusout[23] = 64'h00000700;
// op, rd, rn, rm
iname[24] ="LSR, R21, R21, 2";//testing right shift, result in R21 = 0000000000000007
iaddrbusout[24] = 64'h00000060;
// op, rm, shamt, rn, rd
instrbusin[24] ={LSR, RX, eightShamt, R21, R21};
dselectout[24] = R21_dselect;
dbusout[24] = 64'h00000007;
//finishing up
iname[25] = "NOP";//nada
iaddrbusout[25] = 64'h00000064;
instrbusin[25] = 64'b0;
dselectout[25] = dontcare;
dbusout[25] = dontcare;
iname[26] = "NOP";//nada
iaddrbusout[26] = 64'h00000068;
instrbusin[26] = 64'b0;
dselectout[26] = dontcare;
dbusout[26] = dontcare;
iname[27] = "NOP";//nada
iaddrbusout[27] = 64'h0000006C;
instrbusin[27] = 64'b0;
dselectout[27] = dontcare;
dbusout[27] = dontcare;
iname[28] = "NOP";//nada
iaddrbusout[28] = 64'h00000070;
instrbusin[28] = 64'b0;
dselectout[28] = dontcare;
dbusout[28] = dontcare;
iname[29] = "NOP";//nada
iaddrbusout[29] = 64'h00000074;
instrbusin[29] = 64'b0;
dselectout[29] = dontcare;
dbusout[29] = dontcare;
//remember to set k down below to ntests - 1
ntests = 30;
$timeformat(-9,1,"ns",12);
end
//assumes positive edge FF.
//testbench reads databus when clk high, writes databus when clk low.
//assign databus = clkd ? 64'bz : databusk;
//Change inputs in middle of period (falling edge).
initial begin
error = 0;
clkd =1;
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
//databusk = 64'bz;
//extended reset to set up PC MUX
reset = 1;
$display ("reset=%b", reset);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=1;
clkd=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
clk=0;
clkd=0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#5
$display ("Time=%t\n clk=%b", $realtime, clk);
for (k=0; k<= 29; k=k+1) begin
clk=1;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd=1;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
reset = 0;
$display ("reset=%b", reset);
//set dbus and dselect data data for 4th previous instruction
if (k >=4)
//databusk = databusin[k-4];
//check PC for this instruction
if (k >= 0) begin
$display (" Testing PC for instruction %d", k);
$display (" Your iaddrbus = %b", iaddrbus);
$display (" Correct iaddrbus = %b", iaddrbusout[k]);
if (iaddrbusout[k] !== iaddrbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//put next instruction on ibus
instrbus=instrbusin[k];
$display (" instrbus=%b%b%b%b%b for instruction %d: %s", instrbus[31:26], instrbus[25:21], instrbus[20:16], instrbus[15:11], instrbus[10:0], k, iname[k]);
//check writeback data address from 4th previous instruction
if ( (k >= 4) && (dselectout[k-4] !== dontcare) ) begin
$display (" Testing writeback data address for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dselect = %b", dselect);
$display (" Correct dselect = %b", dselectout[k-4]);
if (dselectout[k-4] !== dselect) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
//check writeback data from 4th previous instruction
if ( (k >= 4) && (dbusout[k-4] !== dontcare) ) begin
$display (" Testing writeback data for instruction %d:", k-4);
$display (" %s", iname[k-4]);
$display (" Your dbus = %b", dbus);
$display (" Correct dbus = %b", dbusout[k-4]);
if (dbusout[k-4] !== dbus) begin
$display (" -------------ERROR. A Mismatch Has Occured-----------");
error = error + 1;
end
end
clk = 0;
$display ("Time=%t\n clk=%b", $realtime, clk);
#2
clkd = 0;
#3
$display ("Time=%t\n clk=%b", $realtime, clk);
end
if ( error !== 0) begin
$display("--------- SIMULATION UNSUCCESFUL - MISMATCHES HAVE OCCURED ----------");
$display(" No. Of Errors = %d", error);
end
if ( error == 0)
$display("---------YOU DID IT!! SIMULATION SUCCESFULLY FINISHED----------");
end
endmodule
|
/*!
* <b>Module:</b>oob_ctrl
* @file oob_ctrl.v
* @date 2015-07-11
* @author Alexey
*
* @brief module to start oob sequences and to handle errors
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* oob_ctrl.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* oob_ctrl.v file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
//`include "oob.v"
module oob_ctrl #(
parameter DATA_BYTE_WIDTH = 4,
parameter CLK_SPEED_GRADE = 1 // 1 - 75 Mhz, 2 - 150Mhz, 4 - 300Mhz
)
(
input wire clk, // input wire // sata clk = usrclk2
input wire rst, // input wire // reset oob
input wire gtx_ready, // input wire // gtx is ready = all resets are done
output wire [11:0] debug, // output[11:0] wire
input wire rxcominitdet_in,// input wire // oob responses
input wire rxcomwakedet_in,// input wire // oob responses
input wire rxelecidle_in, // input wire // oob responses
output wire txcominit, // output wire // oob issues
output wire txcomwake, // output wire // oob issues
output wire txelecidle, // output wire // oob issues
output wire txpcsreset_req, // output wire // partial tx reset
input wire recal_tx_done, // input wire
output wire rxreset_req, // output wire // rx reset (after rxelecidle -> 0)
input wire rxreset_ack, // input wire
// Andrey: adding new signal and state - after RX is operational try re-align clock
output wire clk_phase_align_req, // Request GTX to align SIPO parallel clock and user- provided RXUSRCLK
input wire clk_phase_align_ack, // GTX aligned clock phase (DEBUG - not always clear when it works or not)
input wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_in, // output[31:0] wire // input data stream (if any data during OOB setting => ignored)
input wire [DATA_BYTE_WIDTH - 1:0] txcharisk_in, // output[3:0] wire // input data stream (if any data during OOB setting => ignored)
output wire [DATA_BYTE_WIDTH*8 - 1:0] txdata_out, // output[31:0] wire // output data stream to gtx
output wire [DATA_BYTE_WIDTH - 1:0] txcharisk_out, // output[3:0] wire // output data stream to gtx
input wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_in, // input[31:0] wire // input data from gtx
input wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_in, // input[3:0] wire // input data from gtx
output wire [DATA_BYTE_WIDTH*8 - 1:0] rxdata_out, // output[31:0] wire // bypassed data from gtx
output wire [DATA_BYTE_WIDTH - 1:0] rxcharisk_out, // output[3:0] wire // bypassed data from gtx
input wire rxbyteisaligned,// input wire // obvious
output wire phy_ready, // output wire // shows if channel is ready
input set_offline, // input wire // electrically idle // From
input comreset_send, // input wire // Not possible yet? // From
output reg re_aligned // re-aligned after alignment loss
,output debug_detected_alignp
);
// oob sequence needs to be issued
wire oob_start;
// connection established, all further data is valid
wire oob_done;
// doc p265, link is established after 3back-to-back non-ALIGNp
wire link_up;
wire link_down;
// the device itself sends cominit
wire cominit_req;
// allow to respond to cominit
wire cominit_allow;
// status information to handle by a control block if any exists
// incompatible host-device speed grades (host cannot lock to alignp)
wire oob_incompatible; // TODO
// timeout in an unexpected place
wire oob_error;
// noone responds to our cominits
wire oob_silence;
// obvious
wire oob_busy;
// 1 - link is up and running, 0 - probably not
reg link_state;
// 1 - connection is being established OR already established, 0 - is not
reg oob_state;
// Andrey: Force offline from AHCI
reg force_offline_r; // AHCI conrol need setting offline/sending comreset
always @ (posedge clk) begin
if (rst || comreset_send) force_offline_r <= 0;
else if (set_offline) force_offline_r <= 1;
end
// Andrey: Make phy ready not go inactive during re-aligning
///assign phy_ready = link_state & gtx_ready & rxbyteisaligned;
reg phy_ready_r;
reg was_aligned_r;
always @ (posedge clk) begin
if (!(link_state & gtx_ready)) phy_ready_r <= 0;
else if (rxbyteisaligned) phy_ready_r <= 1;
was_aligned_r <= rxbyteisaligned;
re_aligned <= phy_ready_r && rxbyteisaligned && !was_aligned_r;
end
assign phy_ready = phy_ready_r;
always @ (posedge clk)
link_state <= (link_state | link_up) & ~link_down & ~rst & ~force_offline_r;
always @ (posedge clk)
oob_state <= (oob_state | oob_start | cominit_req & cominit_allow) & ~oob_error & ~oob_silence & ~(link_down & ~oob_busy & ~oob_start) & ~rst;
// decide when to issue oob: always when gtx is ready
//assign oob_start = gtx_ready & ~oob_state & ~oob_busy;
assign oob_start = gtx_ready & ~oob_state & ~oob_busy & ~force_offline_r;
// set line to idle state before if we're waiting for a device to answer AND while oob sequence
wire txelecidle_inner;
//assign txelecidle = /*~oob_state |*/ txelecidle_inner ;
assign txelecidle = /*~oob_state |*/ txelecidle_inner || force_offline_r;
// let devices always begin oob sequence, if only it's not a glitch
assign cominit_allow = cominit_req & link_state;
oob #(
.DATA_BYTE_WIDTH (DATA_BYTE_WIDTH),
.CLK_SPEED_GRADE (CLK_SPEED_GRADE)
)
oob
(
.debug (debug), // output [11:0] reg
.clk (clk), // input wire // sata clk = usrclk2
.rst (rst), // input wire // reset oob
.rxcominitdet_in (rxcominitdet_in), // input wire // oob responses
.rxcomwakedet_in (rxcomwakedet_in), // input wire // oob responses
.rxelecidle_in (rxelecidle_in), // input wire // oob responses
.txcominit (txcominit), // output wire // oob issues
.txcomwake (txcomwake), // output wire // oob issues
.txelecidle (txelecidle_inner),// output wire // oob issues
.txpcsreset_req (txpcsreset_req), // output wire
.recal_tx_done (recal_tx_done), // input wire
.rxreset_req (rxreset_req), // output wire
.rxreset_ack (rxreset_ack), // input wire
.clk_phase_align_req (clk_phase_align_req), // output wire
.clk_phase_align_ack (clk_phase_align_ack), // input wire
.txdata_in (txdata_in), // input [31:0] wire // input data stream (if any data during OOB setting => ignored)
.txcharisk_in (txcharisk_in), // input [3:0] wire // input data stream (if any data during OOB setting => ignored)
.txdata_out (txdata_out), // output [31:0] wire // output data stream to gtx
.txcharisk_out (txcharisk_out), // output [3:0] wire// output data stream to gtx
.rxdata_in (rxdata_in), // input [31:0] wire // input data from gtx
.rxcharisk_in (rxcharisk_in), // input [3:0] wire // input data from gtx
.rxdata_out (rxdata_out), // output [31:0] wire // bypassed data from gtx
.rxcharisk_out (rxcharisk_out), // output [3:0] wire // bypassed data from gtx
.oob_start (oob_start), // input wire // oob sequence needs to be issued
.oob_done (oob_done), // output wire // connection established, all further data is valid
.oob_busy (oob_busy), // output wire // oob can't handle new start request
.link_up (link_up), // output wire // doc p265, link is established after 3back-to-back non-ALIGNp
.link_down (link_down), // output wire
.cominit_req (cominit_req), // output wire // the device itself sends cominit
.cominit_allow (cominit_allow), // input wire // allow to respond to cominit
// status information to handle by a control block if any exists
.oob_incompatible (oob_incompatible),// output wire // incompatible host-device speed grades (host cannot lock to alignp)
.oob_error (oob_error), // output wire // timeout in an unexpected place
.oob_silence (oob_silence) // output wire // noone responds to our cominits
,.debug_detected_alignp(debug_detected_alignp)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Top level multiplier, divider and MAC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// Multiplier is 32x32 however multiply instructions only ////
//// use lower 32 bits of the result. MAC is 32x32=64+64. ////
//// ////
//// To Do: ////
//// - make signed division better, w/o negating the operands ////
//// - implement non-serial divider that is synthesizable ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// - Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_mult_mac.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// Minor update:
// Bugs fixed.
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_mult_mac(
// Clock and reset
clk, rst,
// Multiplier/MAC interface
ex_freeze, id_macrc_op, macrc_op, a, b, mac_op, alu_op,
result, mult_mac_stall,
// Overflow
ovforw, ov_we,
// SPR interface
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter width = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// Multiplier/MAC interface
//
input ex_freeze;
input id_macrc_op;
input macrc_op;
input [width-1:0] a;
input [width-1:0] b;
input [`OR1200_MACOP_WIDTH-1:0] mac_op;
input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
output [width-1:0] result;
output mult_mac_stall;
output ovforw, ov_we;
//
// SPR interface
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
reg [width-1:0] result;
reg ex_freeze_r;
wire alu_op_mul;
wire alu_op_smul;
`ifdef OR1200_MULT_IMPLEMENTED
reg [2*width-1:0] mul_prod_r;
wire alu_op_umul;
`ifdef OR1200_MULT_SERIAL
reg [5:0] serial_mul_cnt;
reg mul_free;
`endif
`else
wire [2*width-1:0] mul_prod_r;
`endif
wire [2*width-1:0] mul_prod;
wire mul_stall;
reg [1:0] mul_stall_count;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op;
`ifdef OR1200_MAC_IMPLEMENTED
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
reg [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
reg mac_stall_r;
reg [63:0] mac_r;
`else
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r1;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r2;
wire [`OR1200_MACOP_WIDTH-1:0] mac_op_r3;
wire mac_stall_r;
wire [63:0] mac_r;
`endif
wire [width-1:0] x;
wire [width-1:0] y;
wire spr_maclo_we;
wire spr_machi_we;
wire alu_op_div;
wire alu_op_udiv;
wire alu_op_sdiv;
reg div_free;
wire div_stall;
`ifdef OR1200_DIV_IMPLEMENTED
`ifdef OR1200_DIV_SERIAL
reg [2*width-1:0] div_quot_r;
wire [width-1:0] div_tmp;
reg [5:0] div_cntr;
`else
reg [width-1:0] div_quot_r;
reg [width-1:0] div_quot_generic;
`endif
wire div_by_zero;
`endif
reg ovforw, ov_we;
//
// Combinatorial logic
//
`ifdef OR1200_MULT_IMPLEMENTED
assign alu_op_smul = (alu_op == `OR1200_ALUOP_MUL);
assign alu_op_umul = (alu_op == `OR1200_ALUOP_MULU);
assign alu_op_mul = alu_op_smul | alu_op_umul;
`else
assign alu_op_smul = 0;
assign alu_op_mul = 0;
`endif
`ifdef OR1200_MAC_IMPLEMENTED
assign spr_maclo_we = spr_cs & spr_write & spr_addr[`OR1200_MAC_ADDR];
assign spr_machi_we = spr_cs & spr_write & !spr_addr[`OR1200_MAC_ADDR];
assign spr_dat_o = spr_addr[`OR1200_MAC_ADDR] ? mac_r[31:0] : mac_r[63:32];
`else
assign spr_maclo_we = 1'b0;
assign spr_machi_we = 1'b0;
assign spr_dat_o = 32'h0000_0000;
`endif
`ifdef OR1200_DIV_IMPLEMENTED
assign alu_op_sdiv = (alu_op == `OR1200_ALUOP_DIV);
assign alu_op_udiv = (alu_op == `OR1200_ALUOP_DIVU);
assign alu_op_div = alu_op_sdiv | alu_op_udiv;
`else
assign alu_op_udiv = 1'b0;
assign alu_op_sdiv = 1'b0;
assign alu_op_div = 1'b0;
`endif
assign x = (alu_op_sdiv | alu_op_smul) & a[31] ? ~a + 32'b1 :
alu_op_div | alu_op_mul | (|mac_op) ? a : 32'd0;
assign y = (alu_op_sdiv | alu_op_smul) & b[31] ? ~b + 32'b1 :
alu_op_div | alu_op_mul | (|mac_op) ? b : 32'd0;
assign div_by_zero = !(|b) & alu_op_div;
// Used to indicate when we should check for new multiply or MAC ops
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
ex_freeze_r <= 1'b1;
else
ex_freeze_r <= ex_freeze;
//
// Select result of current ALU operation to be forwarded
// to next instruction and to WB stage
//
always @*
casez(alu_op) // synopsys parallel_case
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIV: begin
result = a[31] ^ b[31] ? ~div_quot_r[31:0] + 32'd1 : div_quot_r[31:0];
end
`OR1200_ALUOP_DIVU: begin
result = div_quot_r[31:0];
end
`endif
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_ALUOP_MUL: begin
result = a[31] ^ b[31] ? ~mul_prod_r[31:0] + 32'd1 : mul_prod_r[31:0];
end
`OR1200_ALUOP_MULU: begin
result = mul_prod_r[31:0];
end
`endif
default:
`ifdef OR1200_MAC_IMPLEMENTED
`ifdef OR1200_MAC_SHIFTBY
result = mac_r[`OR1200_MAC_SHIFTBY+31:`OR1200_MAC_SHIFTBY];
`else
result = mac_r[31:0];
`endif
`else
result = {width{1'b0}};
`endif
endcase // casez (alu_op)
//
// Overflow generation
//
always @*
casez(alu_op) // synopsys parallel_case
`ifdef OR1200_IMPL_OV
`ifdef OR1200_MULT_IMPLEMENTED
`OR1200_ALUOP_MUL: begin
// Actually doing unsigned multiply internally, and then negate on
// output as appropriate, so if sign bit is set, then is overflow
// unless incoming signs differ and result is 2^(width-1)
ovforw = (mul_prod_r[width-1] &&
!((a[width-1]^b[width-1]) && ~|mul_prod_r[width-2:0])) ||
|mul_prod_r[2*width-1:32];
ov_we = 1;
end
`OR1200_ALUOP_MULU : begin
// Overflow on unsigned multiply is simpler.
ovforw = |mul_prod_r[2*width-1:32];
ov_we = 1;
end
`endif // `ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
`OR1200_ALUOP_DIVU,
`OR1200_ALUOP_DIV: begin
// Overflow on divide by zero or -2^(width-1)/-1
ovforw = div_by_zero || (a==32'h8000_0000 && b==32'hffff_ffff);
ov_we = 1;
end
`endif
`endif // `ifdef OR1200_IMPL_OV
default: begin
ovforw = 0;
ov_we = 0;
end
endcase // casez (alu_op)
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MULT_SERIAL
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
mul_prod_r <= 64'h0000_0000_0000_0000;
serial_mul_cnt <= 6'd0;
mul_free <= 1'b1;
end
else if (|serial_mul_cnt) begin
serial_mul_cnt <= serial_mul_cnt - 6'd1;
if (mul_prod_r[0])
mul_prod_r[(width*2)-1:width-1] <= mul_prod_r[(width*2)-1:width] + x;
else
mul_prod_r[(width*2)-1:width-1] <= {1'b0,mul_prod_r[(width*2)-1:
width]};
mul_prod_r[width-2:0] <= mul_prod_r[width-1:1];
end
else if (alu_op_mul && mul_free) begin
mul_prod_r <= {32'd0, y};
mul_free <= 0;
serial_mul_cnt <= 6'b10_0000;
end
else if (!ex_freeze | mul_free) begin
mul_free <= 1'b1;
end
assign mul_stall = (|serial_mul_cnt) | (alu_op_mul & !ex_freeze_r);
`else
//
// Instantiation of the multiplier
//
`ifdef OR1200_ASIC_MULTP2_32X32
or1200_amultp2_32x32 or1200_amultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`else // OR1200_ASIC_MULTP2_32X32
or1200_gmultp2_32x32 or1200_gmultp2_32x32(
.X(x),
.Y(y),
.RST(rst),
.CLK(clk),
.P(mul_prod)
);
`endif // OR1200_ASIC_MULTP2_32X32
//
// Registered output from the multiplier
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
mul_prod_r <= 64'h0000_0000_0000_0000;
end
else begin
mul_prod_r <= mul_prod[63:0];
end
//
// Generate stall signal during multiplication
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mul_stall_count <= 0;
else if (!(|mul_stall_count))
mul_stall_count <= {mul_stall_count[0], alu_op_mul & !ex_freeze_r};
else
mul_stall_count <= {mul_stall_count[0],1'b0};
assign mul_stall = (|mul_stall_count) |
(!(|mul_stall_count) & alu_op_mul & !ex_freeze_r);
`endif // !`ifdef OR1200_MULT_SERIAL
`else // OR1200_MULT_IMPLEMENTED
assign mul_prod = {2*width{1'b0}};
assign mul_prod_r = {2*width{1'b0}};
assign mul_stall = 0;
`endif // OR1200_MULT_IMPLEMENTED
`ifdef OR1200_MAC_IMPLEMENTED
//
// Propagation of l.mac opcode, only register it for one cycle
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r1 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r1 <= !ex_freeze_r ? mac_op : `OR1200_MACOP_WIDTH'b0;
//
// Propagation of l.mac opcode
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r2 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r2 <= mac_op_r1;
//
// Propagation of l.mac opcode
//
always @(posedge clk or `OR1200_RST_EVENT rst)
if (rst == `OR1200_RST_VALUE)
mac_op_r3 <= `OR1200_MACOP_WIDTH'b0;
else
mac_op_r3 <= mac_op_r2;
//
// Implementation of MAC
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mac_r <= 64'h0000_0000_0000_0000;
`ifdef OR1200_MAC_SPR_WE
else if (spr_maclo_we)
mac_r[31:0] <= spr_dat_i;
else if (spr_machi_we)
mac_r[63:32] <= spr_dat_i;
`endif
else if (mac_op_r3 == `OR1200_MACOP_MAC)
mac_r <= mac_r + mul_prod_r;
else if (mac_op_r3 == `OR1200_MACOP_MSB)
mac_r <= mac_r - mul_prod_r;
else if (macrc_op && !ex_freeze)
mac_r <= 64'h0000_0000_0000_0000;
//
// Stall CPU if l.macrc is in ID and MAC still has to process l.mac
// instructions in EX stage (e.g. inside multiplier)
// This stall signal is also used by the divider.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE)
mac_stall_r <= 1'b0;
else
mac_stall_r <= (|mac_op | (|mac_op_r1) | (|mac_op_r2)) &
(id_macrc_op | mac_stall_r);
`else // OR1200_MAC_IMPLEMENTED
assign mac_stall_r = 1'b0;
assign mac_r = {2*width{1'b0}};
assign mac_op_r1 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r2 = `OR1200_MACOP_WIDTH'b0;
assign mac_op_r3 = `OR1200_MACOP_WIDTH'b0;
`endif // OR1200_MAC_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
//
// Serial division
//
`ifdef OR1200_DIV_SERIAL
assign div_tmp = div_quot_r[63:32] - y;
always @(`OR1200_RST_EVENT rst or posedge clk)
if (rst == `OR1200_RST_VALUE) begin
div_quot_r <= 64'h0000_0000_0000_0000;
div_free <= 1'b1;
div_cntr <= 6'b00_0000;
end
else if (div_by_zero) begin
div_quot_r <= 64'h0000_0000_0000_0000;
div_free <= 1'b1;
div_cntr <= 6'b00_0000;
end
else if (|div_cntr) begin
if (div_tmp[31])
div_quot_r <= {div_quot_r[62:0], 1'b0};
else
div_quot_r <= {div_tmp[30:0], div_quot_r[31:0], 1'b1};
div_cntr <= div_cntr - 6'd1;
end
else if (alu_op_div && div_free) begin
div_quot_r <= {31'b0, x[31:0], 1'b0};
div_cntr <= 6'b10_0000;
div_free <= 1'b0;
end
else if (div_free | !ex_freeze) begin
div_free <= 1'b1;
end
assign div_stall = (|div_cntr) | (!ex_freeze_r & alu_op_div);
`else // !`ifdef OR1200_DIV_SERIAL
// Full divider
// TODO: Perhaps provide module that can be technology dependent.
always @(`OR1200_RST_EVENT rst or posedge clk) begin
if (rst == `OR1200_RST_VALUE) begin
div_quot_r <= 32'd0;
div_quot_generic <= 32'd0;
end
else begin
if (alu_op_udiv & !(|y)) // unsigned divide by 0 - force to MAX
div_quot_generic[31:0] <= 32'hffff_ffff;
else if (alu_op_div)
div_quot_generic[31:0] <= x / y;
end
// Add any additional statges of pipelining as required here. Ensure
// ends with div_quot_r.
// Then add logic to ensure div_stall stays high for as long as the
// division should take.
div_quot_r[31:0] <= div_quot_generic;
end
assign div_stall = 0;
`endif
`else // !`ifdef OR1200_DIV_IMPLEMENTED
assign div_stall = 0;
`endif // !`ifdef OR1200_DIV_IMPLEMENTED
//
// Stall output
//
assign mult_mac_stall = mac_stall_r | div_stall | mul_stall;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBP_BLACKBOX_V
`define SKY130_FD_SC_MS__SDFBBP_BLACKBOX_V
/**
* sdfbbp: Scan delay flop, inverted set, inverted reset, non-inverted
* clock, complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbp (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK ,
SET_B ,
RESET_B
);
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK ;
input SET_B ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBP_BLACKBOX_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Feb 01 18:22:40 2017
// Host : TheMosass-PC running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_0_stub.v
// Design : design_1_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2016.4" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I,
I2C0_SCL_O, I2C0_SCL_T, SDIO0_WP, UART0_TX, UART0_RX, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n,
DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN,
DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_WP,UART0_TX,UART0_RX,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input SDIO0_WP;
output UART0_TX;
input UART0_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
//altasmi_parallel CBX_AUTO_BLACKBOX="ALL" CBX_SINGLE_OUTPUT_FILE="ON" DATA_WIDTH="STANDARD" DEVICE_FAMILY="Cyclone IV E" ENABLE_SIM="FALSE" EPCS_TYPE="EPCS16" FLASH_RSTPIN="FALSE" PAGE_SIZE=256 PORT_BULK_ERASE="PORT_USED" PORT_DIE_ERASE="PORT_UNUSED" PORT_EN4B_ADDR="PORT_UNUSED" PORT_EX4B_ADDR="PORT_UNUSED" PORT_FAST_READ="PORT_USED" PORT_ILLEGAL_ERASE="PORT_USED" PORT_ILLEGAL_WRITE="PORT_USED" PORT_RDID_OUT="PORT_USED" PORT_READ_ADDRESS="PORT_UNUSED" PORT_READ_DUMMYCLK="PORT_USED" PORT_READ_RDID="PORT_USED" PORT_READ_SID="PORT_USED" PORT_READ_STATUS="PORT_USED" PORT_SECTOR_ERASE="PORT_USED" PORT_SECTOR_PROTECT="PORT_USED" PORT_SHIFT_BYTES="PORT_USED" PORT_WREN="PORT_USED" PORT_WRITE="PORT_USED" USE_ASMIBLOCK="ON" USE_EAB="ON" WRITE_DUMMY_CLK=0 addr bulk_erase busy clkin data_valid datain dataout epcs_id fast_read illegal_erase illegal_write rden rdid_out read_dummyclk read_rdid read_sid read_status reset sector_erase sector_protect shift_bytes status_out wren write INTENDED_DEVICE_FAMILY=""" ALTERA_INTERNAL_OPTIONS=SUPPRESS_DA_RULE_INTERNAL=C106
//VERSION_BEGIN 15.1 cbx_a_gray2bin 2015:10:21:18:09:22:SJ cbx_a_graycounter 2015:10:21:18:09:22:SJ cbx_altasmi_parallel 2015:10:21:18:09:22:SJ cbx_altdpram 2015:10:21:18:09:22:SJ cbx_altera_syncram 2015:10:21:18:09:22:SJ cbx_altera_syncram_nd_impl 2015:10:21:18:09:22:SJ cbx_altsyncram 2015:10:21:18:09:23:SJ cbx_arriav 2015:10:21:18:09:21:SJ cbx_cyclone 2015:10:21:18:09:23:SJ cbx_cycloneii 2015:10:21:18:09:23:SJ cbx_fifo_common 2015:10:21:18:09:22:SJ cbx_lpm_add_sub 2015:10:21:18:09:23:SJ cbx_lpm_compare 2015:10:21:18:09:23:SJ cbx_lpm_counter 2015:10:21:18:09:23:SJ cbx_lpm_decode 2015:10:21:18:09:23:SJ cbx_lpm_mux 2015:10:21:18:09:23:SJ cbx_mgl 2015:10:21:18:12:49:SJ cbx_nadder 2015:10:21:18:09:23:SJ cbx_nightfury 2015:10:21:18:09:22:SJ cbx_scfifo 2015:10:21:18:09:23:SJ cbx_stratix 2015:10:21:18:09:23:SJ cbx_stratixii 2015:10:21:18:09:23:SJ cbx_stratixiii 2015:10:21:18:09:23:SJ cbx_stratixv 2015:10:21:18:09:23:SJ cbx_util_mgl 2015:10:21:18:09:23:SJ cbx_zippleback 2015:10:21:21:00:53:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, the Altera Quartus Prime License Agreement,
// the Altera MegaCore Function License Agreement, or other
// applicable license agreement, including, without limitation,
// that your use is for the sole purpose of programming logic
// devices manufactured by Altera and sold by Altera or its
// authorized distributors. Please refer to the applicable
// agreement for further details.
//synthesis_resources = a_graycounter 5 cycloneive_asmiblock 1 lpm_compare 2 lpm_counter 2 lut 76 mux21 2 reg 153
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C106"} *)
module niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel
(
addr,
bulk_erase,
busy,
clkin,
data_valid,
datain,
dataout,
epcs_id,
fast_read,
illegal_erase,
illegal_write,
rden,
rdid_out,
read_dummyclk,
read_rdid,
read_sid,
read_status,
reset,
sector_erase,
sector_protect,
shift_bytes,
status_out,
wren,
write) /* synthesis synthesis_clearbox=1 */;
input [23:0] addr;
input bulk_erase;
output busy;
input clkin;
output data_valid;
input [7:0] datain;
output [7:0] dataout;
output [7:0] epcs_id;
input fast_read;
output illegal_erase;
output illegal_write;
input rden;
output [7:0] rdid_out;
input read_dummyclk;
input read_rdid;
input read_sid;
input read_status;
input reset;
input sector_erase;
input sector_protect;
input shift_bytes;
output [7:0] status_out;
input wren;
input write;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 bulk_erase;
tri0 [7:0] datain;
tri0 fast_read;
tri0 read_dummyclk;
tri0 read_rdid;
tri0 read_sid;
tri0 read_status;
tri0 reset;
tri0 sector_erase;
tri0 sector_protect;
tri0 shift_bytes;
tri1 wren;
tri0 write;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [2:0] wire_addbyte_cntr_q;
wire [2:0] wire_gen_cntr_q;
wire [1:0] wire_spstage_cntr_q;
wire [1:0] wire_stage_cntr_q;
wire [1:0] wire_wrstage_cntr_q;
wire wire_sd3_data0out;
reg add_msb_reg;
wire wire_add_msb_reg_ena;
wire [23:0] wire_addr_reg_d;
reg [23:0] addr_reg;
wire [23:0] wire_addr_reg_ena;
wire [7:0] wire_asmi_opcode_reg_d;
reg [7:0] asmi_opcode_reg;
wire [7:0] wire_asmi_opcode_reg_ena;
reg buf_empty_reg;
reg bulk_erase_reg;
wire wire_bulk_erase_reg_ena;
reg busy_delay_reg;
reg busy_det_reg;
reg clr_rdid_reg;
reg clr_read_reg;
reg clr_read_reg2;
reg clr_rstat_reg;
reg clr_secprot_reg;
reg clr_secprot_reg1;
reg clr_sid_reg;
reg clr_write_reg;
reg clr_write_reg2;
reg cnt_bfend_reg;
reg do_wrmemadd_reg;
reg dvalid_reg;
wire wire_dvalid_reg_ena;
wire wire_dvalid_reg_sclr;
reg dvalid_reg2;
reg end1_cyc_reg;
reg end1_cyc_reg2;
reg end_op_hdlyreg;
reg end_op_reg;
reg end_pgwrop_reg;
wire wire_end_pgwrop_reg_ena;
reg end_rbyte_reg;
wire wire_end_rbyte_reg_ena;
wire wire_end_rbyte_reg_sclr;
reg end_read_reg;
reg [7:0] epcs_id_reg2;
reg fast_read_reg;
wire wire_fast_read_reg_ena;
reg ill_erase_reg;
reg ill_write_reg;
reg illegal_erase_dly_reg;
reg illegal_write_dly_reg;
reg illegal_write_prot_reg;
reg max_cnt_reg;
reg maxcnt_shift_reg;
reg maxcnt_shift_reg2;
reg ncs_reg;
wire wire_ncs_reg_sclr;
wire [7:0] wire_pgwrbuf_dataout_d;
reg [7:0] pgwrbuf_dataout;
wire [7:0] wire_pgwrbuf_dataout_ena;
reg power_up_reg;
reg [7:0] rdid_out_reg;
reg read_bufdly_reg;
wire [7:0] wire_read_data_reg_d;
reg [7:0] read_data_reg;
wire [7:0] wire_read_data_reg_ena;
wire [7:0] wire_read_dout_reg_d;
reg [7:0] read_dout_reg;
wire [7:0] wire_read_dout_reg_ena;
reg read_rdid_reg;
wire wire_read_rdid_reg_ena;
reg read_sid_reg;
wire wire_read_sid_reg_ena;
reg read_status_reg;
wire wire_read_status_reg_ena;
reg sec_erase_reg;
wire wire_sec_erase_reg_ena;
reg sec_prot_reg;
wire wire_sec_prot_reg_ena;
reg shftpgwr_data_reg;
reg shift_op_reg;
reg sprot_rstat_reg;
reg stage2_reg;
reg stage3_dly_reg;
reg stage3_reg;
reg stage4_reg;
reg start_sppoll_reg;
wire wire_start_sppoll_reg_ena;
reg start_sppoll_reg2;
reg start_wrpoll_reg;
wire wire_start_wrpoll_reg_ena;
reg start_wrpoll_reg2;
wire [7:0] wire_statreg_int_d;
reg [7:0] statreg_int;
wire [7:0] wire_statreg_int_ena;
wire [7:0] wire_statreg_out_d;
reg [7:0] statreg_out;
wire [7:0] wire_statreg_out_ena;
reg streg_datain_reg;
wire wire_streg_datain_reg_ena;
reg write_prot_reg;
wire wire_write_prot_reg_ena;
reg write_reg;
wire wire_write_reg_ena;
reg write_rstat_reg;
wire [7:0] wire_wrstat_dreg_d;
reg [7:0] wrstat_dreg;
wire [7:0] wire_wrstat_dreg_ena;
wire wire_cmpr5_aeb;
wire wire_cmpr6_aeb;
wire [8:0] wire_pgwr_data_cntr_q;
wire [8:0] wire_pgwr_read_cntr_q;
wire wire_mux211_dataout;
wire wire_mux212_dataout;
wire [7:0] wire_scfifo4_q;
wire addr_overdie;
wire addr_overdie_pos;
wire [23:0] addr_reg_overdie;
wire [7:0] b4addr_opcode;
wire be_write_prot;
wire [7:0] berase_opcode;
wire bp0_wire;
wire bp1_wire;
wire bp2_wire;
wire bp3_wire;
wire buf_empty;
wire bulk_erase_wire;
wire busy_wire;
wire clkin_wire;
wire clr_addmsb_wire;
wire clr_endrbyte_wire;
wire clr_rdid_wire;
wire clr_read_wire;
wire clr_read_wire2;
wire clr_rstat_wire;
wire clr_secprot_wire;
wire clr_secprot_wire1;
wire clr_sid_wire;
wire clr_write_wire;
wire clr_write_wire2;
wire cnt_bfend_wire_in;
wire data0out_wire;
wire data_valid_wire;
wire [3:0] datain_wire;
wire [3:0] dataout_wire;
wire [7:0] derase_opcode;
wire do_4baddr;
wire do_bulk_erase;
wire do_die_erase;
wire do_ex4baddr;
wire do_fast_read;
wire do_fread_epcq;
wire do_freadwrv_polling;
wire do_memadd;
wire do_polling;
wire do_read;
wire do_read_nonvolatile;
wire do_read_rdid;
wire do_read_sid;
wire do_read_stat;
wire do_read_volatile;
wire do_sec_erase;
wire do_sec_prot;
wire do_secprot_wren;
wire do_sprot_polling;
wire do_sprot_rstat;
wire do_wait_dummyclk;
wire do_wren;
wire do_write;
wire do_write_polling;
wire do_write_rstat;
wire do_write_volatile;
wire do_write_volatile_rstat;
wire do_write_volatile_wren;
wire do_write_wren;
wire dummy_read_buf;
wire end1_cyc_dlyncs_in_wire;
wire end1_cyc_gen_cntr_wire;
wire end1_cyc_normal_in_wire;
wire end1_cyc_reg_in_wire;
wire end_add_cycle;
wire end_add_cycle_mux_datab_wire;
wire end_fast_read;
wire end_one_cyc_pos;
wire end_one_cycle;
wire end_op_wire;
wire end_operation;
wire end_ophdly;
wire end_pgwr_data;
wire end_read;
wire end_read_byte;
wire end_wrstage;
wire [7:0] exb4addr_opcode;
wire [7:0] fast_read_opcode;
wire fast_read_wire;
wire freadwrv_sdoin;
wire ill_erase_wire;
wire ill_write_wire;
wire illegal_erase_b4out_wire;
wire illegal_write_b4out_wire;
wire in_operation;
wire load_opcode;
wire [4:0] mask_prot;
wire [4:0] mask_prot_add;
wire [4:0] mask_prot_check;
wire [4:0] mask_prot_comp_ntb;
wire [4:0] mask_prot_comp_tb;
wire memadd_sdoin;
wire ncs_reg_ena_wire;
wire not_busy;
wire oe_wire;
wire [8:0] page_size_wire;
wire [8:0] pagewr_buf_not_empty;
wire [7:0] prot_wire;
wire rden_wire;
wire rdid_load;
wire [7:0] rdid_opcode;
wire [7:0] rdummyclk_opcode;
wire reach_max_cnt;
wire read_buf;
wire read_bufdly;
wire [7:0] read_data_reg_in_wire;
wire [7:0] read_opcode;
wire read_rdid_wire;
wire read_sid_wire;
wire read_status_wire;
wire read_wire;
wire [7:0] rflagstat_opcode;
wire [7:0] rnvdummyclk_opcode;
wire [7:0] rsid_opcode;
wire rsid_sdoin;
wire [7:0] rstat_opcode;
wire scein_wire;
wire sdoin_wire;
wire sec_erase_wire;
wire sec_protect_wire;
wire [7:0] secprot_opcode;
wire secprot_sdoin;
wire [7:0] serase_opcode;
wire shift_bytes_wire;
wire shift_opcode;
wire shift_opdata;
wire shift_pgwr_data;
wire sid_load;
wire st_busy_wire;
wire stage2_wire;
wire stage3_wire;
wire stage4_wire;
wire start_frpoll;
wire start_poll;
wire start_sppoll;
wire start_wrpoll;
wire to_sdoin_wire;
wire [7:0] wren_opcode;
wire wren_wire;
wire [7:0] write_opcode;
wire write_prot_true;
wire write_sdoin;
wire write_wire;
wire [7:0] wrvolatile_opcode;
a_graycounter addbyte_cntr
(
.aclr(reset),
.clk_en((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cyc_pos) & (((((((do_read_sid | do_write) | do_sec_erase) | do_die_erase) | do_read_rdid) | do_read) | do_fast_read) | do_read_nonvolatile)) | addr_overdie) | end_operation)),
.clock((~ clkin_wire)),
.q(wire_addbyte_cntr_q),
.qbin(),
.sclr((end_operation | addr_overdie))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
addbyte_cntr.width = 3,
addbyte_cntr.lpm_type = "a_graycounter";
a_graycounter gen_cntr
(
.aclr(reset),
.clk_en((((((in_operation & (~ end_ophdly)) & (~ clr_rstat_wire)) & (~ clr_sid_wire)) | do_wait_dummyclk) | addr_overdie)),
.clock(clkin_wire),
.q(wire_gen_cntr_q),
.qbin(),
.sclr(((end1_cyc_reg_in_wire | addr_overdie) | do_wait_dummyclk))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
gen_cntr.width = 3,
gen_cntr.lpm_type = "a_graycounter";
a_graycounter spstage_cntr
(
.aclr(reset),
.clk_en(((do_sec_prot & end_operation) | clr_secprot_wire1)),
.clock((~ clkin_wire)),
.q(wire_spstage_cntr_q),
.qbin(),
.sclr(clr_secprot_wire1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
spstage_cntr.width = 2,
spstage_cntr.lpm_type = "a_graycounter";
a_graycounter stage_cntr
(
.aclr(reset),
.clk_en(((((((((((((((in_operation & end_one_cycle) & (~ (stage3_wire & (~ end_add_cycle)))) & (~ (stage4_wire & (~ end_read)))) & (~ (stage4_wire & (~ end_fast_read)))) & (~ ((((do_write | do_sec_erase) | do_die_erase) | do_bulk_erase) & write_prot_true))) & (~ (do_write & (~ pagewr_buf_not_empty[8])))) & (~ (stage3_wire & st_busy_wire))) & (~ ((do_write & shift_pgwr_data) & (~ end_pgwr_data)))) & (~ (stage2_wire & do_wren))) & (~ ((((stage3_wire & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & (~ do_read_rdid)))) & (~ (stage3_wire & ((do_write_volatile | do_read_volatile) | do_read_nonvolatile)))) | ((stage3_wire & do_fast_read) & do_wait_dummyclk)) | addr_overdie) | end_ophdly)),
.clock(clkin_wire),
.q(wire_stage_cntr_q),
.qbin(),
.sclr((end_operation | addr_overdie))
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
stage_cntr.width = 2,
stage_cntr.lpm_type = "a_graycounter";
a_graycounter wrstage_cntr
(
.aclr(reset),
.clk_en((((((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & (~ write_prot_true)) | do_4baddr) | do_ex4baddr) & end_wrstage) & (~ st_busy_wire)) | clr_write_wire2)),
.clock((~ clkin_wire)),
.q(wire_wrstage_cntr_q),
.qbin(),
.sclr(clr_write_wire2)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.cnt_en(1'b1),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
wrstage_cntr.width = 2,
wrstage_cntr.lpm_type = "a_graycounter";
cycloneive_asmiblock sd3
(
.data0out(wire_sd3_data0out),
.dclkin(clkin_wire),
.oe(oe_wire),
.scein(scein_wire),
.sdoin((sdoin_wire | datain_wire[0])));
// synopsys translate_off
initial
add_msb_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) add_msb_reg <= 1'b0;
else if (wire_add_msb_reg_ena == 1'b1)
if (clr_addmsb_wire == 1'b1) add_msb_reg <= 1'b0;
else add_msb_reg <= addr_reg[23];
assign
wire_add_msb_reg_ena = ((((((((do_read | do_fast_read) | do_write) | do_sec_erase) | do_die_erase) & (~ (((do_write | do_sec_erase) | do_die_erase) & (~ do_memadd)))) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) | clr_addmsb_wire);
// synopsys translate_off
initial
addr_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[0:0] <= 1'b0;
else if (wire_addr_reg_ena[0:0] == 1'b1) addr_reg[0:0] <= wire_addr_reg_d[0:0];
// synopsys translate_off
initial
addr_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[1:1] <= 1'b0;
else if (wire_addr_reg_ena[1:1] == 1'b1) addr_reg[1:1] <= wire_addr_reg_d[1:1];
// synopsys translate_off
initial
addr_reg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[2:2] <= 1'b0;
else if (wire_addr_reg_ena[2:2] == 1'b1) addr_reg[2:2] <= wire_addr_reg_d[2:2];
// synopsys translate_off
initial
addr_reg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[3:3] <= 1'b0;
else if (wire_addr_reg_ena[3:3] == 1'b1) addr_reg[3:3] <= wire_addr_reg_d[3:3];
// synopsys translate_off
initial
addr_reg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[4:4] <= 1'b0;
else if (wire_addr_reg_ena[4:4] == 1'b1) addr_reg[4:4] <= wire_addr_reg_d[4:4];
// synopsys translate_off
initial
addr_reg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[5:5] <= 1'b0;
else if (wire_addr_reg_ena[5:5] == 1'b1) addr_reg[5:5] <= wire_addr_reg_d[5:5];
// synopsys translate_off
initial
addr_reg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[6:6] <= 1'b0;
else if (wire_addr_reg_ena[6:6] == 1'b1) addr_reg[6:6] <= wire_addr_reg_d[6:6];
// synopsys translate_off
initial
addr_reg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[7:7] <= 1'b0;
else if (wire_addr_reg_ena[7:7] == 1'b1) addr_reg[7:7] <= wire_addr_reg_d[7:7];
// synopsys translate_off
initial
addr_reg[8:8] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[8:8] <= 1'b0;
else if (wire_addr_reg_ena[8:8] == 1'b1) addr_reg[8:8] <= wire_addr_reg_d[8:8];
// synopsys translate_off
initial
addr_reg[9:9] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[9:9] <= 1'b0;
else if (wire_addr_reg_ena[9:9] == 1'b1) addr_reg[9:9] <= wire_addr_reg_d[9:9];
// synopsys translate_off
initial
addr_reg[10:10] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[10:10] <= 1'b0;
else if (wire_addr_reg_ena[10:10] == 1'b1) addr_reg[10:10] <= wire_addr_reg_d[10:10];
// synopsys translate_off
initial
addr_reg[11:11] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[11:11] <= 1'b0;
else if (wire_addr_reg_ena[11:11] == 1'b1) addr_reg[11:11] <= wire_addr_reg_d[11:11];
// synopsys translate_off
initial
addr_reg[12:12] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[12:12] <= 1'b0;
else if (wire_addr_reg_ena[12:12] == 1'b1) addr_reg[12:12] <= wire_addr_reg_d[12:12];
// synopsys translate_off
initial
addr_reg[13:13] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[13:13] <= 1'b0;
else if (wire_addr_reg_ena[13:13] == 1'b1) addr_reg[13:13] <= wire_addr_reg_d[13:13];
// synopsys translate_off
initial
addr_reg[14:14] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[14:14] <= 1'b0;
else if (wire_addr_reg_ena[14:14] == 1'b1) addr_reg[14:14] <= wire_addr_reg_d[14:14];
// synopsys translate_off
initial
addr_reg[15:15] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[15:15] <= 1'b0;
else if (wire_addr_reg_ena[15:15] == 1'b1) addr_reg[15:15] <= wire_addr_reg_d[15:15];
// synopsys translate_off
initial
addr_reg[16:16] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[16:16] <= 1'b0;
else if (wire_addr_reg_ena[16:16] == 1'b1) addr_reg[16:16] <= wire_addr_reg_d[16:16];
// synopsys translate_off
initial
addr_reg[17:17] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[17:17] <= 1'b0;
else if (wire_addr_reg_ena[17:17] == 1'b1) addr_reg[17:17] <= wire_addr_reg_d[17:17];
// synopsys translate_off
initial
addr_reg[18:18] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[18:18] <= 1'b0;
else if (wire_addr_reg_ena[18:18] == 1'b1) addr_reg[18:18] <= wire_addr_reg_d[18:18];
// synopsys translate_off
initial
addr_reg[19:19] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[19:19] <= 1'b0;
else if (wire_addr_reg_ena[19:19] == 1'b1) addr_reg[19:19] <= wire_addr_reg_d[19:19];
// synopsys translate_off
initial
addr_reg[20:20] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[20:20] <= 1'b0;
else if (wire_addr_reg_ena[20:20] == 1'b1) addr_reg[20:20] <= wire_addr_reg_d[20:20];
// synopsys translate_off
initial
addr_reg[21:21] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[21:21] <= 1'b0;
else if (wire_addr_reg_ena[21:21] == 1'b1) addr_reg[21:21] <= wire_addr_reg_d[21:21];
// synopsys translate_off
initial
addr_reg[22:22] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[22:22] <= 1'b0;
else if (wire_addr_reg_ena[22:22] == 1'b1) addr_reg[22:22] <= wire_addr_reg_d[22:22];
// synopsys translate_off
initial
addr_reg[23:23] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) addr_reg[23:23] <= 1'b0;
else if (wire_addr_reg_ena[23:23] == 1'b1) addr_reg[23:23] <= wire_addr_reg_d[23:23];
assign
wire_addr_reg_d = {((({23{not_busy}} & addr[23:1]) | ({23{stage3_wire}} & addr_reg[22:0])) | ({23{addr_overdie}} & addr_reg_overdie[23:1])), ((not_busy & addr[0]) | (addr_overdie & addr_reg_overdie[0]))};
assign
wire_addr_reg_ena = {24{((((rden_wire | wren_wire) & not_busy) | (stage4_wire & addr_overdie)) | (stage3_wire & ((((do_write | do_sec_erase) | do_die_erase) & do_memadd) | (do_read | do_fast_read))))}};
// synopsys translate_off
initial
asmi_opcode_reg[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[0:0] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[0:0] == 1'b1) asmi_opcode_reg[0:0] <= wire_asmi_opcode_reg_d[0:0];
// synopsys translate_off
initial
asmi_opcode_reg[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[1:1] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[1:1] == 1'b1) asmi_opcode_reg[1:1] <= wire_asmi_opcode_reg_d[1:1];
// synopsys translate_off
initial
asmi_opcode_reg[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[2:2] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[2:2] == 1'b1) asmi_opcode_reg[2:2] <= wire_asmi_opcode_reg_d[2:2];
// synopsys translate_off
initial
asmi_opcode_reg[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[3:3] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[3:3] == 1'b1) asmi_opcode_reg[3:3] <= wire_asmi_opcode_reg_d[3:3];
// synopsys translate_off
initial
asmi_opcode_reg[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[4:4] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[4:4] == 1'b1) asmi_opcode_reg[4:4] <= wire_asmi_opcode_reg_d[4:4];
// synopsys translate_off
initial
asmi_opcode_reg[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[5:5] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[5:5] == 1'b1) asmi_opcode_reg[5:5] <= wire_asmi_opcode_reg_d[5:5];
// synopsys translate_off
initial
asmi_opcode_reg[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[6:6] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[6:6] == 1'b1) asmi_opcode_reg[6:6] <= wire_asmi_opcode_reg_d[6:6];
// synopsys translate_off
initial
asmi_opcode_reg[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) asmi_opcode_reg[7:7] <= 1'b0;
else if (wire_asmi_opcode_reg_ena[7:7] == 1'b1) asmi_opcode_reg[7:7] <= wire_asmi_opcode_reg_d[7:7];
assign
wire_asmi_opcode_reg_d = {(((((((((((((((((({7{(load_opcode & do_read_sid)}} & rsid_opcode[7:1]) | ({7{(load_opcode & do_read_rdid)}} & rdid_opcode[7:1])) | ({7{(((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat))}} & secprot_opcode[7:1])) | ({7{(load_opcode & do_read)}} & read_opcode[7:1])) | ({7{(load_opcode & do_fast_read)}} & fast_read_opcode[7:1])) | ({7{((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & rdummyclk_opcode[7:1])) | ({7{((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat))}} & wrvolatile_opcode[7:1])) | ({7{(load_opcode & do_read_nonvolatile)}} & rnvdummyclk_opcode[7:1])) | ({7{(load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren)))}} & write_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & (~ do_polling))}} & rstat_opcode[7:1])) | ({7{((load_opcode & do_read_stat) & do_polling)}} & rflagstat_opcode[7:1])) | ({7{(((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat))}} & serase_opcode[7:1])) | ({7{(((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat))}} & derase_opcode[7:1])) | ({7{(((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat))}} & berase_opcode[7:1])) | ({7{(load_opcode & do_wren)}} & wren_opcode[7:1])) | ({7{(load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren)))}} & b4addr_opcode[7:1])) | ({7{(load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren)))}} & exb4addr_opcode[7:1])) | ({7{shift_opcode}} & asmi_opcode_reg[6:0])), ((((((((((((((((((load_opcode & do_read_sid) & rsid_opcode[0]) | ((load_opcode & do_read_rdid) & rdid_opcode[0])) | ((((load_opcode & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & secprot_opcode[0])) | ((load_opcode & do_read) & read_opcode[0])) | ((load_opcode & do_fast_read) & fast_read_opcode[0])) | (((((load_opcode & do_read_volatile) & (~ do_write_volatile)) & (~ do_wren)) & (~ do_read_stat)) & rdummyclk_opcode[0])) | (((((load_opcode & do_write_volatile) & (~ do_read_volatile)) & (~ do_wren)) & (~ do_read_stat
)) & wrvolatile_opcode[0])) | ((load_opcode & do_read_nonvolatile) & rnvdummyclk_opcode[0])) | ((load_opcode & ((do_write & (~ do_read_stat)) & (~ do_wren))) & write_opcode[0])) | (((load_opcode & do_read_stat) & (~ do_polling)) & rstat_opcode[0])) | (((load_opcode & do_read_stat) & do_polling) & rflagstat_opcode[0])) | ((((load_opcode & do_sec_erase) & (~ do_wren)) & (~ do_read_stat)) & serase_opcode[0])) | ((((load_opcode & do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & derase_opcode[0])) | ((((load_opcode & do_bulk_erase) & (~ do_wren)) & (~ do_read_stat)) & berase_opcode[0])) | ((load_opcode & do_wren) & wren_opcode[0])) | ((load_opcode & ((do_4baddr & (~ do_read_stat)) & (~ do_wren))) & b4addr_opcode[0])) | ((load_opcode & ((do_ex4baddr & (~ do_read_stat)) & (~ do_wren))) & exb4addr_opcode[0]))};
assign
wire_asmi_opcode_reg_ena = {8{(load_opcode | shift_opcode)}};
// synopsys translate_off
initial
buf_empty_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) buf_empty_reg <= 1'b0;
else buf_empty_reg <= wire_cmpr6_aeb;
// synopsys translate_off
initial
bulk_erase_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) bulk_erase_reg <= 1'b0;
else if (wire_bulk_erase_reg_ena == 1'b1)
if (clr_write_wire == 1'b1) bulk_erase_reg <= 1'b0;
else bulk_erase_reg <= bulk_erase;
assign
wire_bulk_erase_reg_ena = (((~ busy_wire) & wren_wire) | clr_write_wire);
// synopsys translate_off
initial
busy_delay_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) busy_delay_reg <= 1'b0;
else if (power_up_reg == 1'b1) busy_delay_reg <= busy_wire;
// synopsys translate_off
initial
busy_det_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) busy_det_reg <= 1'b0;
else busy_det_reg <= (~ busy_wire);
// synopsys translate_off
initial
clr_rdid_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_rdid_reg <= 1'b0;
else clr_rdid_reg <= end_operation;
// synopsys translate_off
initial
clr_read_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_read_reg <= 1'b0;
else clr_read_reg <= ((do_read_sid | do_sec_prot) | (end_operation & (do_read | do_fast_read)));
// synopsys translate_off
initial
clr_read_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_read_reg2 <= 1'b0;
else clr_read_reg2 <= clr_read_reg;
// synopsys translate_off
initial
clr_rstat_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_rstat_reg <= 1'b0;
else clr_rstat_reg <= end_operation;
// synopsys translate_off
initial
clr_secprot_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_secprot_reg <= 1'b0;
else clr_secprot_reg <= (((wire_spstage_cntr_q[1] & wire_spstage_cntr_q[0]) & end_operation) | do_read_sid);
// synopsys translate_off
initial
clr_secprot_reg1 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_secprot_reg1 <= 1'b0;
else clr_secprot_reg1 <= clr_secprot_reg;
// synopsys translate_off
initial
clr_sid_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_sid_reg <= 1'b0;
else clr_sid_reg <= end_ophdly;
// synopsys translate_off
initial
clr_write_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_write_reg <= 1'b0;
else clr_write_reg <= (((((((((((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_ex4baddr) & wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])) & end_operation) | write_prot_true) | (do_write & (~ pagewr_buf_not_empty[8]))) | (((((((~ do_write) & (~ do_sec_erase)) & (~ do_bulk_erase)) & (~ do_die_erase)) & (~ do_4baddr)) & (~ do_ex4baddr)) & end_operation)) | do_read_sid) | do_sec_prot) | do_read) | do_fast_read);
// synopsys translate_off
initial
clr_write_reg2 = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) clr_write_reg2 <= 1'b0;
else clr_write_reg2 <= clr_write_reg;
// synopsys translate_off
initial
cnt_bfend_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) cnt_bfend_reg <= 1'b0;
else cnt_bfend_reg <= cnt_bfend_wire_in;
// synopsys translate_off
initial
do_wrmemadd_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) do_wrmemadd_reg <= 1'b0;
else do_wrmemadd_reg <= (wire_wrstage_cntr_q[1] & wire_wrstage_cntr_q[0]);
// synopsys translate_off
initial
dvalid_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) dvalid_reg <= 1'b0;
else if (wire_dvalid_reg_ena == 1'b1)
if (wire_dvalid_reg_sclr == 1'b1) dvalid_reg <= 1'b0;
else dvalid_reg <= (end_read_byte & end_one_cyc_pos);
assign
wire_dvalid_reg_ena = (do_read | do_fast_read),
wire_dvalid_reg_sclr = (end_op_wire | end_operation);
// synopsys translate_off
initial
dvalid_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) dvalid_reg2 <= 1'b0;
else dvalid_reg2 <= dvalid_reg;
// synopsys translate_off
initial
end1_cyc_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end1_cyc_reg <= 1'b0;
else end1_cyc_reg <= end1_cyc_reg_in_wire;
// synopsys translate_off
initial
end1_cyc_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end1_cyc_reg2 <= 1'b0;
else end1_cyc_reg2 <= end_one_cycle;
// synopsys translate_off
initial
end_op_hdlyreg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end_op_hdlyreg <= 1'b0;
else end_op_hdlyreg <= end_operation;
// synopsys translate_off
initial
end_op_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_op_reg <= 1'b0;
else end_op_reg <= end_op_wire;
// synopsys translate_off
initial
end_pgwrop_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_pgwrop_reg <= 1'b0;
else if (wire_end_pgwrop_reg_ena == 1'b1)
if (clr_write_wire == 1'b1) end_pgwrop_reg <= 1'b0;
else end_pgwrop_reg <= buf_empty;
assign
wire_end_pgwrop_reg_ena = (((cnt_bfend_reg & do_write) & shift_pgwr_data) | clr_write_wire);
// synopsys translate_off
initial
end_rbyte_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) end_rbyte_reg <= 1'b0;
else if (wire_end_rbyte_reg_ena == 1'b1)
if (wire_end_rbyte_reg_sclr == 1'b1) end_rbyte_reg <= 1'b0;
else end_rbyte_reg <= (((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0]));
assign
wire_end_rbyte_reg_ena = (((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]) | clr_endrbyte_wire),
wire_end_rbyte_reg_sclr = (clr_endrbyte_wire | addr_overdie);
// synopsys translate_off
initial
end_read_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) end_read_reg <= 1'b0;
else end_read_reg <= ((((~ rden_wire) & (do_read | do_fast_read)) & data_valid_wire) & end_read_byte);
// synopsys translate_off
initial
epcs_id_reg2 = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) epcs_id_reg2 <= 8'b0;
else if (sid_load == 1'b1) epcs_id_reg2 <= {read_dout_reg[7:0]};
// synopsys translate_off
initial
fast_read_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) fast_read_reg <= 1'b0;
else if (wire_fast_read_reg_ena == 1'b1)
if (clr_read_wire == 1'b1) fast_read_reg <= 1'b0;
else fast_read_reg <= fast_read;
assign
wire_fast_read_reg_ena = (((~ busy_wire) & rden_wire) | clr_read_wire);
// synopsys translate_off
initial
ill_erase_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) ill_erase_reg <= 1'b0;
else ill_erase_reg <= (illegal_erase_dly_reg | illegal_erase_b4out_wire);
// synopsys translate_off
initial
ill_write_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) ill_write_reg <= 1'b0;
else ill_write_reg <= (illegal_write_dly_reg | illegal_write_b4out_wire);
// synopsys translate_off
initial
illegal_erase_dly_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) illegal_erase_dly_reg <= 1'b0;
else if (power_up_reg == 1'b1) illegal_erase_dly_reg <= illegal_erase_b4out_wire;
// synopsys translate_off
initial
illegal_write_dly_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) illegal_write_dly_reg <= 1'b0;
else if (power_up_reg == 1'b1) illegal_write_dly_reg <= illegal_write_b4out_wire;
// synopsys translate_off
initial
illegal_write_prot_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) illegal_write_prot_reg <= 1'b0;
else illegal_write_prot_reg <= do_write;
// synopsys translate_off
initial
max_cnt_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) max_cnt_reg <= 1'b0;
else max_cnt_reg <= wire_cmpr5_aeb;
// synopsys translate_off
initial
maxcnt_shift_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) maxcnt_shift_reg <= 1'b0;
else maxcnt_shift_reg <= (((reach_max_cnt & shift_bytes_wire) & wren_wire) & (~ do_write));
// synopsys translate_off
initial
maxcnt_shift_reg2 = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) maxcnt_shift_reg2 <= 1'b0;
else maxcnt_shift_reg2 <= maxcnt_shift_reg;
// synopsys translate_off
initial
ncs_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) ncs_reg <= 1'b0;
else if (ncs_reg_ena_wire == 1'b1)
if (wire_ncs_reg_sclr == 1'b1) ncs_reg <= 1'b0;
else ncs_reg <= 1'b1;
assign
wire_ncs_reg_sclr = (end_operation | addr_overdie_pos);
// synopsys translate_off
initial
pgwrbuf_dataout[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[0:0] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[0:0] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[0:0] <= 1'b0;
else pgwrbuf_dataout[0:0] <= wire_pgwrbuf_dataout_d[0:0];
// synopsys translate_off
initial
pgwrbuf_dataout[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[1:1] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[1:1] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[1:1] <= 1'b0;
else pgwrbuf_dataout[1:1] <= wire_pgwrbuf_dataout_d[1:1];
// synopsys translate_off
initial
pgwrbuf_dataout[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[2:2] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[2:2] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[2:2] <= 1'b0;
else pgwrbuf_dataout[2:2] <= wire_pgwrbuf_dataout_d[2:2];
// synopsys translate_off
initial
pgwrbuf_dataout[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[3:3] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[3:3] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[3:3] <= 1'b0;
else pgwrbuf_dataout[3:3] <= wire_pgwrbuf_dataout_d[3:3];
// synopsys translate_off
initial
pgwrbuf_dataout[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[4:4] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[4:4] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[4:4] <= 1'b0;
else pgwrbuf_dataout[4:4] <= wire_pgwrbuf_dataout_d[4:4];
// synopsys translate_off
initial
pgwrbuf_dataout[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[5:5] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[5:5] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[5:5] <= 1'b0;
else pgwrbuf_dataout[5:5] <= wire_pgwrbuf_dataout_d[5:5];
// synopsys translate_off
initial
pgwrbuf_dataout[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[6:6] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[6:6] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[6:6] <= 1'b0;
else pgwrbuf_dataout[6:6] <= wire_pgwrbuf_dataout_d[6:6];
// synopsys translate_off
initial
pgwrbuf_dataout[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) pgwrbuf_dataout[7:7] <= 1'b0;
else if (wire_pgwrbuf_dataout_ena[7:7] == 1'b1)
if (clr_write_wire == 1'b1) pgwrbuf_dataout[7:7] <= 1'b0;
else pgwrbuf_dataout[7:7] <= wire_pgwrbuf_dataout_d[7:7];
assign
wire_pgwrbuf_dataout_d = {(({7{read_bufdly}} & wire_scfifo4_q[7:1]) | ({7{(~ read_bufdly)}} & pgwrbuf_dataout[6:0])), (read_bufdly & wire_scfifo4_q[0])};
assign
wire_pgwrbuf_dataout_ena = {8{((read_bufdly | shift_pgwr_data) | clr_write_wire)}};
// synopsys translate_off
initial
power_up_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) power_up_reg <= 1'b0;
else power_up_reg <= (busy_wire | busy_delay_reg);
// synopsys translate_off
initial
rdid_out_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) rdid_out_reg <= 8'b0;
else if (rdid_load == 1'b1) rdid_out_reg <= {read_dout_reg[7:0]};
// synopsys translate_off
initial
read_bufdly_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_bufdly_reg <= 1'b0;
else read_bufdly_reg <= read_buf;
// synopsys translate_off
initial
read_data_reg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[0:0] <= 1'b0;
else if (wire_read_data_reg_ena[0:0] == 1'b1) read_data_reg[0:0] <= wire_read_data_reg_d[0:0];
// synopsys translate_off
initial
read_data_reg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[1:1] <= 1'b0;
else if (wire_read_data_reg_ena[1:1] == 1'b1) read_data_reg[1:1] <= wire_read_data_reg_d[1:1];
// synopsys translate_off
initial
read_data_reg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[2:2] <= 1'b0;
else if (wire_read_data_reg_ena[2:2] == 1'b1) read_data_reg[2:2] <= wire_read_data_reg_d[2:2];
// synopsys translate_off
initial
read_data_reg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[3:3] <= 1'b0;
else if (wire_read_data_reg_ena[3:3] == 1'b1) read_data_reg[3:3] <= wire_read_data_reg_d[3:3];
// synopsys translate_off
initial
read_data_reg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[4:4] <= 1'b0;
else if (wire_read_data_reg_ena[4:4] == 1'b1) read_data_reg[4:4] <= wire_read_data_reg_d[4:4];
// synopsys translate_off
initial
read_data_reg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[5:5] <= 1'b0;
else if (wire_read_data_reg_ena[5:5] == 1'b1) read_data_reg[5:5] <= wire_read_data_reg_d[5:5];
// synopsys translate_off
initial
read_data_reg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[6:6] <= 1'b0;
else if (wire_read_data_reg_ena[6:6] == 1'b1) read_data_reg[6:6] <= wire_read_data_reg_d[6:6];
// synopsys translate_off
initial
read_data_reg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_data_reg[7:7] <= 1'b0;
else if (wire_read_data_reg_ena[7:7] == 1'b1) read_data_reg[7:7] <= wire_read_data_reg_d[7:7];
assign
wire_read_data_reg_d = {read_data_reg_in_wire[7:0]};
assign
wire_read_data_reg_ena = {8{(((((do_read | do_fast_read) & wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & end_one_cyc_pos) & end_read_byte)}};
// synopsys translate_off
initial
read_dout_reg[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[0:0] <= 1'b0;
else if (wire_read_dout_reg_ena[0:0] == 1'b1) read_dout_reg[0:0] <= wire_read_dout_reg_d[0:0];
// synopsys translate_off
initial
read_dout_reg[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[1:1] <= 1'b0;
else if (wire_read_dout_reg_ena[1:1] == 1'b1) read_dout_reg[1:1] <= wire_read_dout_reg_d[1:1];
// synopsys translate_off
initial
read_dout_reg[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[2:2] <= 1'b0;
else if (wire_read_dout_reg_ena[2:2] == 1'b1) read_dout_reg[2:2] <= wire_read_dout_reg_d[2:2];
// synopsys translate_off
initial
read_dout_reg[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[3:3] <= 1'b0;
else if (wire_read_dout_reg_ena[3:3] == 1'b1) read_dout_reg[3:3] <= wire_read_dout_reg_d[3:3];
// synopsys translate_off
initial
read_dout_reg[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[4:4] <= 1'b0;
else if (wire_read_dout_reg_ena[4:4] == 1'b1) read_dout_reg[4:4] <= wire_read_dout_reg_d[4:4];
// synopsys translate_off
initial
read_dout_reg[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[5:5] <= 1'b0;
else if (wire_read_dout_reg_ena[5:5] == 1'b1) read_dout_reg[5:5] <= wire_read_dout_reg_d[5:5];
// synopsys translate_off
initial
read_dout_reg[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[6:6] <= 1'b0;
else if (wire_read_dout_reg_ena[6:6] == 1'b1) read_dout_reg[6:6] <= wire_read_dout_reg_d[6:6];
// synopsys translate_off
initial
read_dout_reg[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) read_dout_reg[7:7] <= 1'b0;
else if (wire_read_dout_reg_ena[7:7] == 1'b1) read_dout_reg[7:7] <= wire_read_dout_reg_d[7:7];
assign
wire_read_dout_reg_d = {read_dout_reg[6:0], (data0out_wire | dataout_wire[1])};
assign
wire_read_dout_reg_ena = {8{((stage4_wire & ((do_read | do_fast_read) | do_read_sid)) | (stage3_wire & (((do_read_stat | do_read_rdid) | do_read_volatile) | do_read_nonvolatile)))}};
// synopsys translate_off
initial
read_rdid_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_rdid_reg <= 1'b0;
else if (wire_read_rdid_reg_ena == 1'b1)
if (clr_rdid_wire == 1'b1) read_rdid_reg <= 1'b0;
else read_rdid_reg <= read_rdid;
assign
wire_read_rdid_reg_ena = ((~ busy_wire) | clr_rdid_wire);
// synopsys translate_off
initial
read_sid_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_sid_reg <= 1'b0;
else if (wire_read_sid_reg_ena == 1'b1)
if (clr_sid_wire == 1'b1) read_sid_reg <= 1'b0;
else read_sid_reg <= read_sid;
assign
wire_read_sid_reg_ena = ((~ busy_wire) | clr_sid_wire);
// synopsys translate_off
initial
read_status_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) read_status_reg <= 1'b0;
else if (wire_read_status_reg_ena == 1'b1)
if (clr_rstat_wire == 1'b1) read_status_reg <= 1'b0;
else read_status_reg <= read_status;
assign
wire_read_status_reg_ena = ((~ busy_wire) | clr_rstat_wire);
// synopsys translate_off
initial
sec_erase_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) sec_erase_reg <= 1'b0;
else if (wire_sec_erase_reg_ena == 1'b1)
if (clr_write_wire == 1'b1) sec_erase_reg <= 1'b0;
else sec_erase_reg <= sector_erase;
assign
wire_sec_erase_reg_ena = (((~ busy_wire) & wren_wire) | clr_write_wire);
// synopsys translate_off
initial
sec_prot_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) sec_prot_reg <= 1'b0;
else if (wire_sec_prot_reg_ena == 1'b1)
if (clr_secprot_wire == 1'b1) sec_prot_reg <= 1'b0;
else sec_prot_reg <= sector_protect;
assign
wire_sec_prot_reg_ena = (((~ busy_wire) & wren_wire) | clr_secprot_wire);
// synopsys translate_off
initial
shftpgwr_data_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) shftpgwr_data_reg <= 1'b0;
else
if (end_operation == 1'b1) shftpgwr_data_reg <= 1'b0;
else shftpgwr_data_reg <= (((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]);
// synopsys translate_off
initial
shift_op_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) shift_op_reg <= 1'b0;
else shift_op_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
sprot_rstat_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) sprot_rstat_reg <= 1'b0;
else
if (clr_secprot_wire == 1'b1) sprot_rstat_reg <= 1'b0;
else sprot_rstat_reg <= ((do_sec_prot & wire_spstage_cntr_q[1]) & wire_spstage_cntr_q[0]);
// synopsys translate_off
initial
stage2_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage2_reg <= 1'b0;
else stage2_reg <= ((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage3_dly_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) stage3_dly_reg <= 1'b0;
else stage3_dly_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage3_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage3_reg <= 1'b0;
else stage3_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
// synopsys translate_off
initial
stage4_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) stage4_reg <= 1'b0;
else stage4_reg <= (wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0]));
// synopsys translate_off
initial
start_sppoll_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) start_sppoll_reg <= 1'b0;
else if (wire_start_sppoll_reg_ena == 1'b1)
if (clr_secprot_wire == 1'b1) start_sppoll_reg <= 1'b0;
else start_sppoll_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
assign
wire_start_sppoll_reg_ena = (((do_sprot_rstat & do_polling) & end_one_cycle) | clr_secprot_wire);
// synopsys translate_off
initial
start_sppoll_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) start_sppoll_reg2 <= 1'b0;
else
if (clr_secprot_wire == 1'b1) start_sppoll_reg2 <= 1'b0;
else start_sppoll_reg2 <= start_sppoll_reg;
// synopsys translate_off
initial
start_wrpoll_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) start_wrpoll_reg <= 1'b0;
else if (wire_start_wrpoll_reg_ena == 1'b1)
if (clr_write_wire == 1'b1) start_wrpoll_reg <= 1'b0;
else start_wrpoll_reg <= (wire_stage_cntr_q[1] & wire_stage_cntr_q[0]);
assign
wire_start_wrpoll_reg_ena = (((do_write_rstat & do_polling) & end_one_cycle) | clr_write_wire);
// synopsys translate_off
initial
start_wrpoll_reg2 = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) start_wrpoll_reg2 <= 1'b0;
else
if (clr_write_wire == 1'b1) start_wrpoll_reg2 <= 1'b0;
else start_wrpoll_reg2 <= start_wrpoll_reg;
// synopsys translate_off
initial
statreg_int[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[0:0] <= 1'b0;
else if (wire_statreg_int_ena[0:0] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[0:0] <= 1'b0;
else statreg_int[0:0] <= wire_statreg_int_d[0:0];
// synopsys translate_off
initial
statreg_int[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[1:1] <= 1'b0;
else if (wire_statreg_int_ena[1:1] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[1:1] <= 1'b0;
else statreg_int[1:1] <= wire_statreg_int_d[1:1];
// synopsys translate_off
initial
statreg_int[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[2:2] <= 1'b0;
else if (wire_statreg_int_ena[2:2] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[2:2] <= 1'b0;
else statreg_int[2:2] <= wire_statreg_int_d[2:2];
// synopsys translate_off
initial
statreg_int[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[3:3] <= 1'b0;
else if (wire_statreg_int_ena[3:3] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[3:3] <= 1'b0;
else statreg_int[3:3] <= wire_statreg_int_d[3:3];
// synopsys translate_off
initial
statreg_int[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[4:4] <= 1'b0;
else if (wire_statreg_int_ena[4:4] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[4:4] <= 1'b0;
else statreg_int[4:4] <= wire_statreg_int_d[4:4];
// synopsys translate_off
initial
statreg_int[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[5:5] <= 1'b0;
else if (wire_statreg_int_ena[5:5] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[5:5] <= 1'b0;
else statreg_int[5:5] <= wire_statreg_int_d[5:5];
// synopsys translate_off
initial
statreg_int[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[6:6] <= 1'b0;
else if (wire_statreg_int_ena[6:6] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[6:6] <= 1'b0;
else statreg_int[6:6] <= wire_statreg_int_d[6:6];
// synopsys translate_off
initial
statreg_int[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_int[7:7] <= 1'b0;
else if (wire_statreg_int_ena[7:7] == 1'b1)
if (clr_rstat_wire == 1'b1) statreg_int[7:7] <= 1'b0;
else statreg_int[7:7] <= wire_statreg_int_d[7:7];
assign
wire_statreg_int_d = {read_dout_reg[7:0]};
assign
wire_statreg_int_ena = {8{(((end_operation | ((do_polling & end_one_cyc_pos) & stage3_dly_reg)) & do_read_stat) | clr_rstat_wire)}};
// synopsys translate_off
initial
statreg_out[0:0] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[0:0] <= 1'b0;
else if (wire_statreg_out_ena[0:0] == 1'b1) statreg_out[0:0] <= wire_statreg_out_d[0:0];
// synopsys translate_off
initial
statreg_out[1:1] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[1:1] <= 1'b0;
else if (wire_statreg_out_ena[1:1] == 1'b1) statreg_out[1:1] <= wire_statreg_out_d[1:1];
// synopsys translate_off
initial
statreg_out[2:2] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[2:2] <= 1'b0;
else if (wire_statreg_out_ena[2:2] == 1'b1) statreg_out[2:2] <= wire_statreg_out_d[2:2];
// synopsys translate_off
initial
statreg_out[3:3] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[3:3] <= 1'b0;
else if (wire_statreg_out_ena[3:3] == 1'b1) statreg_out[3:3] <= wire_statreg_out_d[3:3];
// synopsys translate_off
initial
statreg_out[4:4] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[4:4] <= 1'b0;
else if (wire_statreg_out_ena[4:4] == 1'b1) statreg_out[4:4] <= wire_statreg_out_d[4:4];
// synopsys translate_off
initial
statreg_out[5:5] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[5:5] <= 1'b0;
else if (wire_statreg_out_ena[5:5] == 1'b1) statreg_out[5:5] <= wire_statreg_out_d[5:5];
// synopsys translate_off
initial
statreg_out[6:6] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[6:6] <= 1'b0;
else if (wire_statreg_out_ena[6:6] == 1'b1) statreg_out[6:6] <= wire_statreg_out_d[6:6];
// synopsys translate_off
initial
statreg_out[7:7] = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) statreg_out[7:7] <= 1'b0;
else if (wire_statreg_out_ena[7:7] == 1'b1) statreg_out[7:7] <= wire_statreg_out_d[7:7];
assign
wire_statreg_out_d = {read_dout_reg[7:0]};
assign
wire_statreg_out_ena = {8{((((((((end_ophdly & do_read_stat) & (~ do_write)) & (~ do_sec_erase)) & (~ do_die_erase)) & (~ do_bulk_erase)) & (~ do_sec_prot)) & (~ do_4baddr)) & (~ do_ex4baddr))}};
// synopsys translate_off
initial
streg_datain_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) streg_datain_reg <= 1'b0;
else if (wire_streg_datain_reg_ena == 1'b1)
if (end_operation == 1'b1) streg_datain_reg <= 1'b0;
else streg_datain_reg <= wrstat_dreg[7];
assign
wire_streg_datain_reg_ena = (((do_sec_prot & (~ wire_spstage_cntr_q[1])) & wire_spstage_cntr_q[0]) | end_operation);
// synopsys translate_off
initial
write_prot_reg = 0;
// synopsys translate_on
always @ ( negedge clkin_wire or posedge reset)
if (reset == 1'b1) write_prot_reg <= 1'b0;
else if (wire_write_prot_reg_ena == 1'b1)
if (clr_write_wire == 1'b1) write_prot_reg <= 1'b0;
else write_prot_reg <= ((((do_write | do_sec_erase) & (~ mask_prot_comp_ntb[4])) & (~ prot_wire[0])) | be_write_prot);
assign
wire_write_prot_reg_ena = (((((((do_sec_erase | do_write) | do_bulk_erase) | do_die_erase) & (~ wire_wrstage_cntr_q[1])) & wire_wrstage_cntr_q[0]) & end_ophdly) | clr_write_wire);
// synopsys translate_off
initial
write_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) write_reg <= 1'b0;
else if (wire_write_reg_ena == 1'b1)
if (clr_write_wire == 1'b1) write_reg <= 1'b0;
else write_reg <= write;
assign
wire_write_reg_ena = (((~ busy_wire) & wren_wire) | clr_write_wire);
// synopsys translate_off
initial
write_rstat_reg = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) write_rstat_reg <= 1'b0;
else
if (clr_write_wire == 1'b1) write_rstat_reg <= 1'b0;
else write_rstat_reg <= ((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_ex4baddr) & (((~ wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])) | (wire_wrstage_cntr_q[1] & (~ wire_wrstage_cntr_q[0]))));
// synopsys translate_off
initial
wrstat_dreg[0:0] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[0:0] <= 1'b0;
else if (wire_wrstat_dreg_ena[0:0] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[0:0] <= 1'b0;
else wrstat_dreg[0:0] <= wire_wrstat_dreg_d[0:0];
// synopsys translate_off
initial
wrstat_dreg[1:1] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[1:1] <= 1'b0;
else if (wire_wrstat_dreg_ena[1:1] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[1:1] <= 1'b0;
else wrstat_dreg[1:1] <= wire_wrstat_dreg_d[1:1];
// synopsys translate_off
initial
wrstat_dreg[2:2] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[2:2] <= 1'b0;
else if (wire_wrstat_dreg_ena[2:2] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[2:2] <= 1'b0;
else wrstat_dreg[2:2] <= wire_wrstat_dreg_d[2:2];
// synopsys translate_off
initial
wrstat_dreg[3:3] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[3:3] <= 1'b0;
else if (wire_wrstat_dreg_ena[3:3] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[3:3] <= 1'b0;
else wrstat_dreg[3:3] <= wire_wrstat_dreg_d[3:3];
// synopsys translate_off
initial
wrstat_dreg[4:4] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[4:4] <= 1'b0;
else if (wire_wrstat_dreg_ena[4:4] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[4:4] <= 1'b0;
else wrstat_dreg[4:4] <= wire_wrstat_dreg_d[4:4];
// synopsys translate_off
initial
wrstat_dreg[5:5] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[5:5] <= 1'b0;
else if (wire_wrstat_dreg_ena[5:5] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[5:5] <= 1'b0;
else wrstat_dreg[5:5] <= wire_wrstat_dreg_d[5:5];
// synopsys translate_off
initial
wrstat_dreg[6:6] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[6:6] <= 1'b0;
else if (wire_wrstat_dreg_ena[6:6] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[6:6] <= 1'b0;
else wrstat_dreg[6:6] <= wire_wrstat_dreg_d[6:6];
// synopsys translate_off
initial
wrstat_dreg[7:7] = 0;
// synopsys translate_on
always @ ( posedge clkin_wire or posedge reset)
if (reset == 1'b1) wrstat_dreg[7:7] <= 1'b0;
else if (wire_wrstat_dreg_ena[7:7] == 1'b1)
if (clr_secprot_wire == 1'b1) wrstat_dreg[7:7] <= 1'b0;
else wrstat_dreg[7:7] <= wire_wrstat_dreg_d[7:7];
assign
wire_wrstat_dreg_d = {(({7{not_busy}} & datain[7:1]) | ({7{stage3_wire}} & wrstat_dreg[6:0])), (not_busy & datain[0])};
assign
wire_wrstat_dreg_ena = {8{(((wren_wire & not_busy) | (((do_sec_prot & stage3_wire) & (~ wire_spstage_cntr_q[1])) & wire_spstage_cntr_q[0])) | clr_secprot_wire)}};
lpm_compare cmpr5
(
.aeb(wire_cmpr5_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa({page_size_wire[8:0]}),
.datab({wire_pgwr_data_cntr_q[8:0]})
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr5.lpm_width = 9,
cmpr5.lpm_type = "lpm_compare";
lpm_compare cmpr6
(
.aeb(wire_cmpr6_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa({wire_pgwr_data_cntr_q[8:0]}),
.datab({wire_pgwr_read_cntr_q[8:0]})
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr6.lpm_width = 9,
cmpr6.lpm_type = "lpm_compare";
lpm_counter pgwr_data_cntr
(
.aclr(reset),
.clk_en(((((shift_bytes_wire & wren_wire) & (~ reach_max_cnt)) & (~ do_write)) | clr_write_wire2)),
.clock(clkin_wire),
.cout(),
.eq(),
.q(wire_pgwr_data_cntr_q),
.sclr(clr_write_wire2)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.cnt_en(1'b1),
.data({9{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pgwr_data_cntr.lpm_direction = "UP",
pgwr_data_cntr.lpm_port_updown = "PORT_UNUSED",
pgwr_data_cntr.lpm_width = 9,
pgwr_data_cntr.lpm_type = "lpm_counter";
lpm_counter pgwr_read_cntr
(
.aclr(reset),
.clk_en((read_buf | clr_write_wire2)),
.clock(clkin_wire),
.cout(),
.eq(),
.q(wire_pgwr_read_cntr_q),
.sclr(clr_write_wire2)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.cnt_en(1'b1),
.data({9{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pgwr_read_cntr.lpm_direction = "UP",
pgwr_read_cntr.lpm_port_updown = "PORT_UNUSED",
pgwr_read_cntr.lpm_width = 9,
pgwr_read_cntr.lpm_type = "lpm_counter";
assign wire_mux211_dataout = (((((do_write | do_sec_prot) | do_sec_erase) | do_bulk_erase) | do_die_erase) === 1'b1) ? end1_cyc_dlyncs_in_wire : end1_cyc_normal_in_wire;
assign wire_mux212_dataout = (do_fast_read === 1'b1) ? end_add_cycle_mux_datab_wire : (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0]));
scfifo scfifo4
(
.aclr(reset),
.almost_empty(),
.almost_full(),
.clock(clkin_wire),
.data({datain[7:0]}),
.eccstatus(),
.empty(),
.full(),
.q(wire_scfifo4_q),
.rdreq((read_buf | dummy_read_buf)),
.sclr(clr_write_wire2),
.usedw(),
.wrreq(((shift_bytes_wire & wren_wire) & (~ do_write))));
defparam
scfifo4.lpm_numwords = 258,
scfifo4.lpm_width = 8,
scfifo4.lpm_widthu = 9,
scfifo4.use_eab = "ON",
scfifo4.lpm_type = "scfifo";
assign
addr_overdie = 1'b0,
addr_overdie_pos = 1'b0,
addr_reg_overdie = {24{1'b0}},
b4addr_opcode = {8{1'b0}},
be_write_prot = ((do_bulk_erase | do_die_erase) & (((bp3_wire | bp2_wire) | bp1_wire) | bp0_wire)),
berase_opcode = 8'b11000111,
bp0_wire = statreg_int[2],
bp1_wire = statreg_int[3],
bp2_wire = statreg_int[4],
bp3_wire = statreg_int[6],
buf_empty = buf_empty_reg,
bulk_erase_wire = bulk_erase_reg,
busy = (busy_wire | busy_delay_reg),
busy_wire = ((((((((((((((do_read_rdid | do_read_sid) | do_read) | do_fast_read) | do_write) | do_sec_prot) | do_read_stat) | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_read_volatile) | do_fread_epcq) | do_read_nonvolatile) | do_ex4baddr),
clkin_wire = clkin,
clr_addmsb_wire = (((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & end_add_cycle) & end_one_cyc_pos) | (((~ do_read) & (~ do_fast_read)) & clr_write_wire2)) | ((((do_sec_erase | do_die_erase) & (~ do_wren)) & (~ do_read_stat)) & end_operation)),
clr_endrbyte_wire = (((((do_read | do_fast_read) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | clr_read_wire2),
clr_rdid_wire = clr_rdid_reg,
clr_read_wire = clr_read_reg,
clr_read_wire2 = clr_read_reg2,
clr_rstat_wire = clr_rstat_reg,
clr_secprot_wire = clr_secprot_reg,
clr_secprot_wire1 = clr_secprot_reg1,
clr_sid_wire = clr_sid_reg,
clr_write_wire = clr_write_reg,
clr_write_wire2 = clr_write_reg2,
cnt_bfend_wire_in = ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]),
data0out_wire = wire_sd3_data0out,
data_valid = data_valid_wire,
data_valid_wire = dvalid_reg2,
datain_wire = {{4{1'b0}}},
dataout = {read_data_reg[7:0]},
dataout_wire = {{4{1'b0}}},
derase_opcode = {8{1'b0}},
do_4baddr = 1'b0,
do_bulk_erase = (((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & (~ sec_erase_wire)) & bulk_erase_wire),
do_die_erase = 1'b0,
do_ex4baddr = 1'b0,
do_fast_read = (((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & fast_read_wire),
do_fread_epcq = 1'b0,
do_freadwrv_polling = 1'b0,
do_memadd = do_wrmemadd_reg,
do_polling = ((do_write_polling | do_sprot_polling) | do_freadwrv_polling),
do_read = 1'b0,
do_read_nonvolatile = 1'b0,
do_read_rdid = ((~ do_read_nonvolatile) & read_rdid_wire),
do_read_sid = (((~ do_read_nonvolatile) & (~ read_rdid_wire)) & read_sid_wire),
do_read_stat = ((((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & read_status_wire) | do_write_rstat) | do_sprot_rstat) | do_write_volatile_rstat),
do_read_volatile = 1'b0,
do_sec_erase = ((((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & (~ write_wire)) & (~ read_status_wire)) & sec_erase_wire),
do_sec_prot = ((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & sec_protect_wire),
do_secprot_wren = ((do_sec_prot & (~ wire_spstage_cntr_q[1])) & (~ wire_spstage_cntr_q[0])),
do_sprot_polling = ((do_sec_prot & wire_spstage_cntr_q[1]) & wire_spstage_cntr_q[0]),
do_sprot_rstat = sprot_rstat_reg,
do_wait_dummyclk = 1'b0,
do_wren = ((do_write_wren | do_secprot_wren) | do_write_volatile_wren),
do_write = ((((((~ do_read_nonvolatile) & (~ read_rdid_wire)) & (~ read_sid_wire)) & (~ sec_protect_wire)) & (~ (read_wire | fast_read_wire))) & write_wire),
do_write_polling = (((((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) | do_4baddr) | do_ex4baddr) & wire_wrstage_cntr_q[1]) & (~ wire_wrstage_cntr_q[0])),
do_write_rstat = write_rstat_reg,
do_write_volatile = 1'b0,
do_write_volatile_rstat = 1'b0,
do_write_volatile_wren = 1'b0,
do_write_wren = ((~ wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]),
dummy_read_buf = maxcnt_shift_reg2,
end1_cyc_dlyncs_in_wire = (((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & (~ wire_gen_cntr_q[0])) | ((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & end1_cyc_gen_cntr_wire)) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[8]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))),
end1_cyc_gen_cntr_wire = ((wire_gen_cntr_q[2] & (~ wire_gen_cntr_q[1])) & (~ wire_gen_cntr_q[0])),
end1_cyc_normal_in_wire = ((((((((((((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1])) & (~ wire_gen_cntr_q[2])) & wire_gen_cntr_q[1]) & wire_gen_cntr_q[0]) | ((~ ((~ wire_stage_cntr_q[0]) & (~ wire_stage_cntr_q[1]))) & end1_cyc_gen_cntr_wire)) | (do_read & end_read)) | (do_fast_read & end_fast_read)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | (do_write & (~ pagewr_buf_not_empty[8]))) | ((do_read_stat & start_poll) & (~ st_busy_wire))) | (do_read_rdid & end_op_wire)),
end1_cyc_reg_in_wire = wire_mux211_dataout,
end_add_cycle = wire_mux212_dataout,
end_add_cycle_mux_datab_wire = (wire_addbyte_cntr_q[2] & wire_addbyte_cntr_q[1]),
end_fast_read = end_read_reg,
end_one_cyc_pos = end1_cyc_reg2,
end_one_cycle = end1_cyc_reg,
end_op_wire = ((((((((((((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) & ((((((~ do_read) & (~ do_fast_read)) & (~ (do_write & shift_pgwr_data))) & end_one_cycle) | (do_read & end_read)) | (do_fast_read & end_fast_read))) | ((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_read_stat) & end_one_cycle) & (~ do_polling))) | ((((((do_read_rdid & end_one_cyc_pos) & wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & wire_addbyte_cntr_q[2]) & wire_addbyte_cntr_q[1]) & (~ wire_addbyte_cntr_q[0]))) | (((start_poll & do_read_stat) & do_polling) & (~ st_busy_wire))) | ((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & (do_wren | (do_4baddr | (do_ex4baddr | (do_bulk_erase & (~ do_read_stat)))))) & end_one_cycle)) | ((((do_write | do_sec_erase) | do_bulk_erase) | do_die_erase) & write_prot_true)) | ((do_write & shift_pgwr_data) & end_pgwr_data)) | (do_write & (~ pagewr_buf_not_empty[8]))) | (((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & do_sec_prot) & (~ do_wren)) & (~ do_read_stat)) & end_one_cycle)) | ((((((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & (do_sec_erase | do_die_erase)) & (~ do_wren)) & (~ do_read_stat)) & end_add_cycle) & end_one_cycle)) | (((wire_stage_cntr_q[1] & wire_stage_cntr_q[0]) & end_one_cycle) & ((do_write_volatile | do_read_volatile) | (do_read_nonvolatile & wire_addbyte_cntr_q[1])))),
end_operation = end_op_reg,
end_ophdly = end_op_hdlyreg,
end_pgwr_data = end_pgwrop_reg,
end_read = end_read_reg,
end_read_byte = (end_rbyte_reg & (~ addr_overdie)),
end_wrstage = end_operation,
epcs_id = {epcs_id_reg2[7:0]},
exb4addr_opcode = {8{1'b0}},
fast_read_opcode = 8'b00001011,
fast_read_wire = fast_read_reg,
freadwrv_sdoin = 1'b0,
ill_erase_wire = ill_erase_reg,
ill_write_wire = ill_write_reg,
illegal_erase = ill_erase_wire,
illegal_erase_b4out_wire = (((do_sec_erase | do_bulk_erase) | do_die_erase) & write_prot_true),
illegal_write = ill_write_wire,
illegal_write_b4out_wire = ((do_write & write_prot_true) | (do_write & (~ pagewr_buf_not_empty[8]))),
in_operation = busy_wire,
load_opcode = (((((~ wire_stage_cntr_q[1]) & (~ wire_stage_cntr_q[0])) & (~ wire_gen_cntr_q[2])) & (~ wire_gen_cntr_q[1])) & wire_gen_cntr_q[0]),
mask_prot = {((((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]) | prot_wire[5]), (((prot_wire[1] | prot_wire[2]) | prot_wire[3]) | prot_wire[4]), ((prot_wire[1] | prot_wire[2]) | prot_wire[3]), (prot_wire[1] | prot_wire[2]), prot_wire[1]},
mask_prot_add = {(mask_prot[4] & addr_reg[20]), (mask_prot[3] & addr_reg[19]), (mask_prot[2] & addr_reg[18]), (mask_prot[1] & addr_reg[17]), (mask_prot[0] & addr_reg[16])},
mask_prot_check = {(mask_prot[4] ^ mask_prot_add[4]), (mask_prot[3] ^ mask_prot_add[3]), (mask_prot[2] ^ mask_prot_add[2]), (mask_prot[1] ^ mask_prot_add[1]), (mask_prot[0] ^ mask_prot_add[0])},
mask_prot_comp_ntb = {(mask_prot_check[4] | mask_prot_comp_ntb[3]), (mask_prot_check[3] | mask_prot_comp_ntb[2]), (mask_prot_check[2] | mask_prot_comp_ntb[1]), (mask_prot_check[1] | mask_prot_comp_ntb[0]), mask_prot_check[0]},
mask_prot_comp_tb = {(mask_prot_add[4] | mask_prot_comp_tb[3]), (mask_prot_add[3] | mask_prot_comp_tb[2]), (mask_prot_add[2] | mask_prot_comp_tb[1]), (mask_prot_add[1] | mask_prot_comp_tb[0]), mask_prot_add[0]},
memadd_sdoin = add_msb_reg,
ncs_reg_ena_wire = (((((~ wire_stage_cntr_q[1]) & wire_stage_cntr_q[0]) & end_one_cyc_pos) | addr_overdie_pos) | end_operation),
not_busy = busy_det_reg,
oe_wire = 1'b0,
page_size_wire = 9'b100000000,
pagewr_buf_not_empty = {(pagewr_buf_not_empty[7] | wire_pgwr_data_cntr_q[8]), (pagewr_buf_not_empty[6] | wire_pgwr_data_cntr_q[7]), (pagewr_buf_not_empty[5] | wire_pgwr_data_cntr_q[6]), (pagewr_buf_not_empty[4] | wire_pgwr_data_cntr_q[5]), (pagewr_buf_not_empty[3] | wire_pgwr_data_cntr_q[4]), (pagewr_buf_not_empty[2] | wire_pgwr_data_cntr_q[3]), (pagewr_buf_not_empty[1] | wire_pgwr_data_cntr_q[2]), (pagewr_buf_not_empty[0] | wire_pgwr_data_cntr_q[1]), wire_pgwr_data_cntr_q[0]},
prot_wire = {((bp2_wire & bp1_wire) & bp0_wire), ((bp2_wire & bp1_wire) & (~ bp0_wire)), ((bp2_wire & (~ bp1_wire)) & bp0_wire), ((bp2_wire & (~ bp1_wire)) & (~ bp0_wire)), (((~ bp2_wire) & bp1_wire) & bp0_wire), (((~ bp2_wire) & bp1_wire) & (~ bp0_wire)), (((~ bp2_wire) & (~ bp1_wire)) & bp0_wire), (((~ bp2_wire) & (~ bp1_wire)) & (~ bp0_wire))},
rden_wire = rden,
rdid_load = (end_operation & do_read_rdid),
rdid_opcode = 8'b10011111,
rdid_out = {rdid_out_reg[7:0]},
rdummyclk_opcode = {8{1'b0}},
reach_max_cnt = max_cnt_reg,
read_buf = (((((end_one_cycle & do_write) & (~ do_read_stat)) & (~ do_wren)) & ((wire_stage_cntr_q[1] & (~ wire_stage_cntr_q[0])) | (wire_addbyte_cntr_q[1] & (~ wire_addbyte_cntr_q[0])))) & (~ buf_empty)),
read_bufdly = read_bufdly_reg,
read_data_reg_in_wire = {read_dout_reg[7:0]},
read_opcode = {8{1'b0}},
read_rdid_wire = read_rdid_reg,
read_sid_wire = read_sid_reg,
read_status_wire = read_status_reg,
read_wire = 1'b0,
rflagstat_opcode = 8'b00000101,
rnvdummyclk_opcode = {8{1'b0}},
rsid_opcode = 8'b10101011,
rsid_sdoin = (do_read_sid & stage3_wire),
rstat_opcode = 8'b00000101,
scein_wire = (~ ncs_reg),
sdoin_wire = to_sdoin_wire,
sec_erase_wire = sec_erase_reg,
sec_protect_wire = sec_prot_reg,
secprot_opcode = 8'b00000001,
secprot_sdoin = (stage3_wire & streg_datain_reg),
serase_opcode = 8'b11011000,
shift_bytes_wire = shift_bytes,
shift_opcode = shift_op_reg,
shift_opdata = stage2_wire,
shift_pgwr_data = shftpgwr_data_reg,
sid_load = (end_ophdly & do_read_sid),
st_busy_wire = statreg_int[0],
stage2_wire = stage2_reg,
stage3_wire = stage3_reg,
stage4_wire = stage4_reg,
start_frpoll = 1'b0,
start_poll = ((start_wrpoll | start_sppoll) | start_frpoll),
start_sppoll = start_sppoll_reg2,
start_wrpoll = start_wrpoll_reg2,
status_out = {statreg_out[7:0]},
to_sdoin_wire = ((((((shift_opdata & asmi_opcode_reg[7]) | rsid_sdoin) | memadd_sdoin) | write_sdoin) | secprot_sdoin) | freadwrv_sdoin),
wren_opcode = 8'b00000110,
wren_wire = wren,
write_opcode = 8'b00000010,
write_prot_true = write_prot_reg,
write_sdoin = ((((do_write & stage4_wire) & wire_wrstage_cntr_q[1]) & wire_wrstage_cntr_q[0]) & pgwrbuf_dataout[7]),
write_wire = write_reg,
wrvolatile_opcode = {8{1'b0}};
endmodule //niosii_epcq_controller_0_altera_asmi_parallel_altera_asmi_parallel
//VALID FILE
|
// megafunction wizard: %RAM: 2-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: Cache_DataRAM.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 12.0 Build 232 07/05/2012 SP 1 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2012 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module Cache_DataRAM (
address_a,
address_b,
clock,
data_a,
data_b,
wren_a,
wren_b,
q_a,
q_b);
input [10:0] address_a;
input [10:0] address_b;
input clock;
input [17:0] data_a;
input [17:0] data_b;
input wren_a;
input wren_b;
output [17:0] q_a;
output [17:0] q_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren_a;
tri0 wren_b;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "9"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "36864"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "0"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: REGrren NUMERIC "0"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "18"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "18"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "18"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
// Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]"
// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data_a 0 0 18 0 INPUT NODEFVAL "data_a[17..0]"
// Retrieval info: USED_PORT: data_b 0 0 18 0 INPUT NODEFVAL "data_b[17..0]"
// Retrieval info: USED_PORT: q_a 0 0 18 0 OUTPUT NODEFVAL "q_a[17..0]"
// Retrieval info: USED_PORT: q_b 0 0 18 0 OUTPUT NODEFVAL "q_b[17..0]"
// Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
// Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 18 0 data_a 0 0 18 0
// Retrieval info: CONNECT: @data_b 0 0 18 0 data_b 0 0 18 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
// Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
// Retrieval info: CONNECT: q_a 0 0 18 0 @q_a 0 0 18 0
// Retrieval info: CONNECT: q_b 0 0 18 0 @q_b 0 0 18 0
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Cache_DataRAM_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
//////////////////////////////////////////////////////////////////////////////
//
// Description :
// Brief Description: Contains the capture registers for data back from the
// RAM as well as the FIFO used by the drawing engine data path for
// read-modify-write
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module mc_mff
#(parameter BYTES = 4
)
(
input mclock,
input reset_n,
input [(BYTES*8)-1:0] de_data_in,
input [(BYTES*4)-1:0] de_adata_in,
input [(BYTES*8)-1:0] de_zdata_in,
input [BYTES-1:0] mask_in,
input load_en,
input de_push,
input de_push_a,
input de_push_z,
input unload_mff,
input unload_de,
input unload_z,
input local_ready,
input z_en,
input [(BYTES*8)-1:0] read_data,
input [2:0] kcnt_de,
input [31:0] kcol_de,
input [2:0] kcnt_rd,
input [31:0] kcol_rd,
input [1:0] pix_de,
input [1:0] pix_rd,
output [(BYTES*8)-1:0] mff_data,
output [(BYTES*8)-1:0] de_data_out,
output [(BYTES*4)-1:0] de_adata_out,
output [(BYTES*8)-1:0] de_zdata_out,
output [BYTES-1:0] mask_out,
output [BYTES-1:0] zmask_out,
output reg mff_almost_full,
output reg de_almost_full,
output empty_mff,
output empty_de,
output [6:0] mff_usedw
);
reg [(BYTES*8)-1:0] de_zdata_del;
reg [(BYTES*4)-1:0] de_adata_del;
reg [(BYTES*8)-1:0] de_data_out_last;
reg [(BYTES*4)-1:0] de_adata_out_last;
reg [(BYTES*8)-1:0] de_zdata_out_last;
reg [BYTES-1:0] de_mask_out_last;
reg [BYTES-1:0] de_zmask_out_last;
wire full_mff, full_de;
wire [6:0] usedw;
wire [BYTES-1:0] de_mask_out;
wire [BYTES-1:0] mask_out_rd;
wire [BYTES-1:0] key_mask;
wire [BYTES-1:0] key_mask_rd;
wire [(BYTES*8)-1:0] de_data_out_int;
wire [(BYTES*8)-1:0] de_zdata_out_int;
wire [(BYTES*4)-1:0] de_adata_out_int;
wire [BYTES-1:0] de_mask_out_int;
wire [BYTES-1:0] de_zmask_out_int;
wire empty_z;
wire [BYTES-1:0] rd_mask_in;
assign rd_mask_in = {BYTES{1'b0}};
mc_mff_key
#(.BYTES (BYTES))
u_mc_mff_key
(
.data_in (de_data_in),
// .key_in (kcol_de),
.key_in (kcol_rd),
.pix (pix_de),
// .kcnt ({kcnt_de[2:1], ~kcnt_de[0]}), // New.
.kcnt ({kcnt_rd[2:1], ~kcnt_rd[0]}), // New.
.mask_in (mask_in),
.key_mask (key_mask)
);
mc_mff_key
#(.BYTES (BYTES))
u_mc_mff_key_rd
(
.data_in (read_data),
.key_in (kcol_rd),
.pix (pix_rd),
.kcnt (kcnt_rd),
.mask_in (rd_mask_in),
.key_mask (key_mask_rd)
);
// If we have at least 18 locations free, then we are not almost full.
// Registered result for speed.
always @(posedge mclock) mff_almost_full <= mff_usedw > (128 - 36);
always @(posedge mclock) de_almost_full <= usedw > (128 - 36);
// MFF Fifo
// This is a FIFO with registered addresses and control signals.
`ifdef RAM_FIFO_36x128
ssi_sfifo
#
(
.WIDTH (9*BYTES),
.DEPTH (128),
.DLOG2 (7),
.AFULL (128)
)
U_RD_MASK
(
.data ({key_mask_rd, read_data}),
.wrreq (load_en),
.rdreq (unload_mff),
.clock (mclock),
.aclr (~reset_n),
.q ({mask_out_rd, mff_data}),
.full (full_mff),
.empty (empty_mff),
.usedw (mff_usedw)
);
ssi_sfifo
#
(
.WIDTH (9*BYTES),
.DEPTH (128),
.DLOG2 (7),
.AFULL (128)
)
U_DE_MASK
(
.data ({key_mask, de_data_in}),
.wrreq (de_push),
.rdreq (unload_de),
.clock (mclock),
.aclr (~reset_n),
.q ({de_mask_out_int, de_data_out_int}),
.full (full_de),
.empty (empty_de),
.usedw (usedw)
);
`else
// fifo_36x128 U_RD_MASK[(BYTES/4)-1:0]
fifo_144x128 U_RD_MASK
(
.data ({key_mask_rd, read_data}),
.wrreq (load_en),
.rdreq (unload_mff),
.clock (mclock),
.aclr (~reset_n),
.q ({mask_out_rd, mff_data}),
.full (full_mff),
.empty (empty_mff),
.usedw (mff_usedw)
);
// fifo_36x128 U_DE_MASK[(BYTES/4)-1:0]
fifo_144x128 U_DE_MASK
(
.data ({key_mask, de_data_in}),
.wrreq (de_push),
.rdreq (unload_de),
.clock (mclock),
.aclr (~reset_n),
.q ({de_mask_out_int, de_data_out_int}),
.full (full_de),
.empty (empty_de),
.usedw (usedw)
);
fifo_144x128 U_Z_MASK
(
.data ({key_mask, de_zdata_del}),
.wrreq (de_push_z),
.rdreq (unload_z),
.clock (mclock),
.aclr (~reset_n),
.q ({de_zmask_out_int, de_zdata_out_int}),
.full (),
.empty (empty_z),
.usedw ()
);
fifo_144x128 U_A_MASK
(
.data (de_adata_in),
.wrreq (de_push_a),
.rdreq (unload_de),
.clock (mclock),
.aclr (~reset_n),
.q (de_adata_out_int),
.full (),
.empty (),
.usedw ()
);
`endif // !`ifdef RAM_FIFO_36x128
// assign mask_out = de_mask_out | mask_out_rd & {BYTES{kcnt_rd[2]}};
// Fix stuck mask problem. (J.Macleod 083110).
assign mask_out = de_mask_out | (mask_out_rd & {BYTES{kcnt_rd[0]}}) & {BYTES{kcnt_rd[2]}};
always @(posedge mclock) begin
de_adata_del <= de_adata_in;
de_zdata_del <= de_zdata_in;
de_data_out_last <= de_data_out_int;
de_adata_out_last <= de_adata_out_int;
de_zdata_out_last <= de_zdata_out_int;
de_mask_out_last <= de_mask_out_int;
de_zmask_out_last <= de_zmask_out_int;
end
assign de_data_out = (local_ready) ? de_data_out_int : de_data_out_last;
assign de_adata_out = (local_ready) ? de_adata_out_int : de_adata_out_last;
assign de_zdata_out = (local_ready) ? de_zdata_out_int : de_zdata_out_last;
assign de_mask_out = (local_ready) ? de_mask_out_int : de_mask_out_last;
assign zmask_out = (local_ready) ? de_zmask_out_int : de_zmask_out_last;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NAND2_4_V
`define SKY130_FD_SC_LP__NAND2_4_V
/**
* nand2: 2-input NAND.
*
* Verilog wrapper for nand2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nand2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_4 (
Y ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__nand2_4 (
Y,
A,
B
);
output Y;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__nand2 base (
.Y(Y),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__NAND2_4_V
|
//*****************************************************************************
// (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 4.0
// \ \ Application : MIG
// / / Filename : example_top.v
// /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
// \ \ / \ Date Created : Fri Oct 14 2011
// \___\/\___\
//
// Device : 7 Series
// Design Name : DDR2 SDRAM
// Purpose :
// Top-level module. This module serves as an example,
// and allows the user to synthesize a self-contained design,
// which they can be used to test their hardware.
// In addition to the memory controller, the module instantiates:
// 1. Synthesizable testbench - used to model user's backend logic
// and generate different traffic patterns
// Reference :
// Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module example_top #
(
//***************************************************************************
// Traffic Gen related parameters
//***************************************************************************
parameter BEGIN_ADDRESS = 32'h00000000,
parameter END_ADDRESS = 32'h00ffffff,
parameter PRBS_EADDR_MASK_POS = 32'hff000000,
parameter ENFORCE_RD_WR = 0,
parameter ENFORCE_RD_WR_CMD = 8'h11,
parameter ENFORCE_RD_WR_PATTERN = 3'b000,
parameter C_EN_WRAP_TRANS = 0,
parameter C_AXI_NBURST_TEST = 0,
//***************************************************************************
// The following parameters refer to width of various ports
//***************************************************************************
parameter BANK_WIDTH = 3,
// # of memory Bank Address bits.
parameter COL_WIDTH = 10,
// # of memory Column Address bits.
parameter CS_WIDTH = 1,
// # of unique CS outputs to memory.
parameter DQ_WIDTH = 16,
// # of DQ (data)
parameter DQS_WIDTH = 2,
parameter DQS_CNT_WIDTH = 1,
// = ceil(log2(DQS_WIDTH))
parameter DRAM_WIDTH = 8,
// # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_TEST = "OFF",
//parameter nBANK_MACHS = 4,
parameter nBANK_MACHS = 4,
parameter RANKS = 1,
// # of Ranks.
parameter ROW_WIDTH = 13,
// # of memory Row Address bits.
parameter ADDR_WIDTH = 27,
// # = RANK_WIDTH + BANK_WIDTH
// + ROW_WIDTH + COL_WIDTH;
// Chip Select is always tied to low for
// single rank devices
//***************************************************************************
// The following parameters are mode register settings
//***************************************************************************
parameter BURST_MODE = "8",
// DDR3 SDRAM:
// Burst Length (Mode Register 0).
// # = "8", "4", "OTF".
// DDR2 SDRAM:
// Burst Length (Mode Register).
// # = "8", "4".
//***************************************************************************
// Simulation parameters
//***************************************************************************
parameter SIMULATION = "FALSE",
// Should be TRUE during design simulations and
// FALSE during implementations
//***************************************************************************
// IODELAY and PHY related parameters
//***************************************************************************
parameter TCQ = 100,
//***************************************************************************
// System clock frequency parameters
//***************************************************************************
parameter nCK_PER_CLK = 2,
// # of memory CKs per fabric CLK
//***************************************************************************
// AXI4 Shim parameters
//***************************************************************************
parameter UI_EXTRA_CLOCKS = "FALSE",
// Generates extra clocks as
// 1/2, 1/4 and 1/8 of fabrick clock.
// Valid for DDR2/DDR3 AXI interfaces
// based on GUI selection
parameter C_S_AXI_ID_WIDTH = 4,
// Width of all master and slave ID signals.
// # = >= 1.
parameter C_S_AXI_ADDR_WIDTH = 32,
// Width of S_AXI_AWADDR, S_AXI_ARADDR, M_AXI_AWADDR and
// M_AXI_ARADDR for all SI/MI slots.
// # = 32.
parameter C_S_AXI_DATA_WIDTH = 32,
// Width of WDATA and RDATA on SI slot.
// Must be <= APP_DATA_WIDTH.
// # = 32, 64, 128, 256.
parameter C_S_AXI_SUPPORTS_NARROW_BURST = 0,
// Indicates whether to instatiate upsizer
// Range: 0, 1
parameter C_S_AXI_CTRL_ADDR_WIDTH = 32,
// Width of AXI-4-Lite address bus
parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
// Width of AXI-4-Lite data buses
//***************************************************************************
// Debug parameters
//***************************************************************************
parameter DEBUG_PORT = "OFF"
// # = "ON" Enable debug signals/controls.
// = "OFF" Disable debug signals/controls.
// parameter RST_ACT_LOW = 1
// =1 for active low reset,
// =0 for active high.
)
(
// Inouts
inout [15:0] ddr2_dq,
inout [1:0] ddr2_dqs_n,
inout [1:0] ddr2_dqs_p,
// Outputs
output [12:0] ddr2_addr,
output [2:0] ddr2_ba,
output ddr2_ras_n,
output ddr2_cas_n,
output ddr2_we_n,
output [0:0] ddr2_ck_p,
output [0:0] ddr2_ck_n,
output [0:0] ddr2_cke,
output [0:0] ddr2_cs_n,
output [1:0] ddr2_dm,
output [0:0] ddr2_odt,
// Inputs
// Single-ended system clock
input sys_clk_i,
output tg_compare_error,
output init_calib_complete,
input [11:0] device_temp_i,
// The 12 MSB bits of the temperature sensor transfer
// function need to be connected to this port. This port
// will be synchronized w.r.t. to fabric clock internally.
// System reset - Default polarity of sys_rst pin is Active Low.
// System reset polarity will change based on the option
// selected in GUI.
input sys_rst
);
function integer clogb2 (input integer size);
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
function integer STR_TO_INT;
input [7:0] in;
begin
if(in == "8")
STR_TO_INT = 8;
else if(in == "4")
STR_TO_INT = 4;
else
STR_TO_INT = 0;
end
endfunction
localparam DATA_WIDTH = 16;
localparam RANK_WIDTH = clogb2(RANKS);
localparam PAYLOAD_WIDTH = (ECC_TEST == "OFF") ? DATA_WIDTH : DQ_WIDTH;
localparam BURST_LENGTH = STR_TO_INT(BURST_MODE);
localparam APP_DATA_WIDTH = 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
localparam APP_MASK_WIDTH = APP_DATA_WIDTH / 8;
//***************************************************************************
// Traffic Gen related parameters (derived)
//***************************************************************************
localparam TG_ADDR_WIDTH = ((CS_WIDTH == 1) ? 0 : RANK_WIDTH)
+ BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
localparam MASK_SIZE = DATA_WIDTH/8;
localparam DBG_WR_STS_WIDTH = 40;
localparam DBG_RD_STS_WIDTH = 40;
// Wire declarations
wire clk;
wire rst;
wire mmcm_locked;
reg aresetn;
wire app_sr_active;
wire app_ref_ack;
wire app_zq_ack;
wire app_rd_data_valid;
wire [APP_DATA_WIDTH-1:0] app_rd_data;
wire mem_pattern_init_done;
wire cmd_err;
wire data_msmatch_err;
wire write_err;
wire read_err;
wire test_cmptd;
wire write_cmptd;
wire read_cmptd;
wire cmptd_one_wr_rd;
// Slave Interface Write Address Ports
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid;
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr;
wire [7:0] s_axi_awlen;
wire [2:0] s_axi_awsize;
wire [1:0] s_axi_awburst;
wire [0:0] s_axi_awlock;
wire [3:0] s_axi_awcache;
wire [2:0] s_axi_awprot;
wire s_axi_awvalid;
wire s_axi_awready;
// Slave Interface Write Data Ports
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] s_axi_wstrb;
wire s_axi_wlast;
wire s_axi_wvalid;
wire s_axi_wready;
// Slave Interface Write Response Ports
wire s_axi_bready;
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid;
wire [1:0] s_axi_bresp;
wire s_axi_bvalid;
// Slave Interface Read Address Ports
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid;
wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_araddr;
wire [7:0] s_axi_arlen;
wire [2:0] s_axi_arsize;
wire [1:0] s_axi_arburst;
wire [0:0] s_axi_arlock;
wire [3:0] s_axi_arcache;
wire [2:0] s_axi_arprot;
wire s_axi_arvalid;
wire s_axi_arready;
// Slave Interface Read Data Ports
wire s_axi_rready;
wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid;
wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata;
wire [1:0] s_axi_rresp;
wire s_axi_rlast;
wire s_axi_rvalid;
wire cmp_data_valid;
wire [C_S_AXI_DATA_WIDTH-1:0] cmp_data; // Compare data
wire [C_S_AXI_DATA_WIDTH-1:0] rdata_cmp; // Read data
wire dbg_wr_sts_vld;
wire [DBG_WR_STS_WIDTH-1:0] dbg_wr_sts;
wire dbg_rd_sts_vld;
wire [DBG_RD_STS_WIDTH-1:0] dbg_rd_sts;
//***************************************************************************
assign tg_compare_error = cmd_err | data_msmatch_err | write_err | read_err;
// Start of User Design top instance
//***************************************************************************
// The User design is instantiated below. The memory interface ports are
// connected to the top-level and the application interface ports are
// connected to the traffic generator module. This provides a reference
// for connecting the memory controller to system.
//***************************************************************************
ddr_axi #
(
// #parameters_mapping_user_design_top_instance#
// .RST_ACT_LOW (RST_ACT_LOW)
)
u_ddr_axi
(
// Memory interface ports
.ddr2_addr (ddr2_addr),
.ddr2_ba (ddr2_ba),
.ddr2_cas_n (ddr2_cas_n),
.ddr2_ck_n (ddr2_ck_n),
.ddr2_ck_p (ddr2_ck_p),
.ddr2_cke (ddr2_cke),
.ddr2_ras_n (ddr2_ras_n),
.ddr2_we_n (ddr2_we_n),
.ddr2_dq (ddr2_dq),
.ddr2_dqs_n (ddr2_dqs_n),
.ddr2_dqs_p (ddr2_dqs_p),
.init_calib_complete (init_calib_complete),
.ddr2_cs_n (ddr2_cs_n),
.ddr2_dm (ddr2_dm),
.ddr2_odt (ddr2_odt),
// Application interface ports
.ui_clk (clk),
.ui_clk_sync_rst (rst),
.mmcm_locked (mmcm_locked),
.aresetn (aresetn),
.app_sr_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
// Slave Interface Write Address Ports
.s_axi_awid (s_axi_awid),
.s_axi_awaddr (s_axi_awaddr),
.s_axi_awlen (s_axi_awlen),
.s_axi_awsize (s_axi_awsize),
.s_axi_awburst (s_axi_awburst),
.s_axi_awlock (s_axi_awlock),
.s_axi_awcache (s_axi_awcache),
.s_axi_awprot (s_axi_awprot),
.s_axi_awqos (4'h0),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_awready (s_axi_awready),
// Slave Interface Write Data Ports
.s_axi_wdata (s_axi_wdata),
.s_axi_wstrb (s_axi_wstrb),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_wready (s_axi_wready),
// Slave Interface Write Response Ports
.s_axi_bid (s_axi_bid),
.s_axi_bresp (s_axi_bresp),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_bready (s_axi_bready),
// Slave Interface Read Address Ports
.s_axi_arid (s_axi_arid),
.s_axi_araddr (s_axi_araddr),
.s_axi_arlen (s_axi_arlen),
.s_axi_arsize (s_axi_arsize),
.s_axi_arburst (s_axi_arburst),
.s_axi_arlock (s_axi_arlock),
.s_axi_arcache (s_axi_arcache),
.s_axi_arprot (s_axi_arprot),
.s_axi_arqos (4'h0),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_arready (s_axi_arready),
// Slave Interface Read Data Ports
.s_axi_rid (s_axi_rid),
.s_axi_rdata (s_axi_rdata),
.s_axi_rresp (s_axi_rresp),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.s_axi_rready (s_axi_rready),
// System Clock Ports
.sys_clk_i (sys_clk_i),
.device_temp_i (device_temp_i),
.sys_rst (sys_rst)
);
// End of User Design top instance
//***************************************************************************
// The traffic generation module instantiated below drives traffic (patterns)
// on the application interface of the memory controller
//***************************************************************************
always @(posedge clk) begin
aresetn <= ~rst;
end
mig_7series_v4_0_axi4_tg #(
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_S_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_NBURST_SUPPORT (C_AXI_NBURST_TEST),
.C_EN_WRAP_TRANS (C_EN_WRAP_TRANS),
.C_BEGIN_ADDRESS (BEGIN_ADDRESS),
.C_END_ADDRESS (END_ADDRESS),
.PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS),
.DBG_WR_STS_WIDTH (DBG_WR_STS_WIDTH),
.DBG_RD_STS_WIDTH (DBG_RD_STS_WIDTH),
.ENFORCE_RD_WR (ENFORCE_RD_WR),
.ENFORCE_RD_WR_CMD (ENFORCE_RD_WR_CMD),
.EN_UPSIZER (C_S_AXI_SUPPORTS_NARROW_BURST),
.ENFORCE_RD_WR_PATTERN (ENFORCE_RD_WR_PATTERN)
) u_axi4_tg_inst
(
.aclk (clk),
.aresetn (aresetn),
// Input control signals
.init_cmptd (init_calib_complete),
.init_test (1'b0),
.wdog_mask (~init_calib_complete),
.wrap_en (1'b0),
// AXI write address channel signals
.axi_wready (s_axi_awready),
.axi_wid (s_axi_awid),
.axi_waddr (s_axi_awaddr),
.axi_wlen (s_axi_awlen),
.axi_wsize (s_axi_awsize),
.axi_wburst (s_axi_awburst),
.axi_wlock (s_axi_awlock),
.axi_wcache (s_axi_awcache),
.axi_wprot (s_axi_awprot),
.axi_wvalid (s_axi_awvalid),
// AXI write data channel signals
.axi_wd_wready (s_axi_wready),
.axi_wd_wid (s_axi_wid),
.axi_wd_data (s_axi_wdata),
.axi_wd_strb (s_axi_wstrb),
.axi_wd_last (s_axi_wlast),
.axi_wd_valid (s_axi_wvalid),
// AXI write response channel signals
.axi_wd_bid (s_axi_bid),
.axi_wd_bresp (s_axi_bresp),
.axi_wd_bvalid (s_axi_bvalid),
.axi_wd_bready (s_axi_bready),
// AXI read address channel signals
.axi_rready (s_axi_arready),
.axi_rid (s_axi_arid),
.axi_raddr (s_axi_araddr),
.axi_rlen (s_axi_arlen),
.axi_rsize (s_axi_arsize),
.axi_rburst (s_axi_arburst),
.axi_rlock (s_axi_arlock),
.axi_rcache (s_axi_arcache),
.axi_rprot (s_axi_arprot),
.axi_rvalid (s_axi_arvalid),
// AXI read data channel signals
.axi_rd_bid (s_axi_rid),
.axi_rd_rresp (s_axi_rresp),
.axi_rd_rvalid (s_axi_rvalid),
.axi_rd_data (s_axi_rdata),
.axi_rd_last (s_axi_rlast),
.axi_rd_rready (s_axi_rready),
// Error status signals
.cmd_err (cmd_err),
.data_msmatch_err (data_msmatch_err),
.write_err (write_err),
.read_err (read_err),
.test_cmptd (test_cmptd),
.write_cmptd (write_cmptd),
.read_cmptd (read_cmptd),
.cmptd_one_wr_rd (cmptd_one_wr_rd),
// Debug status signals
.cmp_data_en (cmp_data_valid),
.cmp_data_o (cmp_data),
.rdata_cmp (rdata_cmp),
.dbg_wr_sts_vld (dbg_wr_sts_vld),
.dbg_wr_sts (dbg_wr_sts),
.dbg_rd_sts_vld (dbg_rd_sts_vld),
.dbg_rd_sts (dbg_rd_sts)
);
//*****************************************************************
// Default values are assigned to the debug inputs
//*****************************************************************
assign dbg_sel_pi_incdec = 'b0;
assign dbg_sel_po_incdec = 'b0;
assign dbg_pi_f_inc = 'b0;
assign dbg_pi_f_dec = 'b0;
assign dbg_po_f_inc = 'b0;
assign dbg_po_f_dec = 'b0;
assign dbg_po_f_stg23_sel = 'b0;
assign po_win_tg_rst = 'b0;
assign vio_tg_rst = 'b0;
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// /**
// * This Verilog HDL file is used for simulation in
// * the chained DMA design example.
// */
`timescale 1 ps / 1 ps
//-----------------------------------------------------------------------------
// Title : PCI Express BFM Root Port Driver for the chained DMA
// design example
// Project : PCI Express MegaCore function
//-----------------------------------------------------------------------------
// File : altpcietb_bfm_driver.v
// Author : Altera Corporation
//-----------------------------------------------------------------------------
// Description : This module is driver for the Root Port BFM for the chained DMA
// design example.
// The main process (begin : main) operates in two stages:
// - EP configuration using the task ebfm_cfg_rp_ep
// - Run a chained DMA transfer with the task chained_dma_test
//
// Chained DMA operation:
// The chained DMA consist of a DMA Write and a DMA Read sub-module
// Each DMA use a separate descriptor table mapped in the share memeory
// The descriptor table contains a header with 3 DWORDs (DW0, DW1, DW2)
//
// |31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16|15 .................0
// ----|---------------------------------------------------------------------
// | R| | | | | E|M| D |
// DW0 | E| MSI | | | | P|S| I |
// | S|TRAFFIC | | | | L|I| R |
// | E|CLASS | RESERVED| MSI |1 | A| | E | SIZE:Number
// | R| | | NUMBER | | S| | C | of DMA descriptor
// | V| | | | | T| | T |
// | E| | | | | | | I |
// | D| | | | | | | O |
// | | | | | | | | N |
// ----|---------------------------------------------------------------------
// DW1 | BDT_MSB
// ----|---------------------------------------------------------------------
// DW2 | BDT_LSB
// ----|---------------------------------------------------------------------
//
// RC memory map Overview - Descriptor section
//
// RC memory : 2Mbyte 0h -> 200000h
// BRC+00000h : Descriptor table write
// BRC+00100h : Descriptor table read
// BRC+01000h : Data for write
// BRC+05000h : Data for read
//
//-----------------------------------------------------------------------------
//
// Abreviation:
// EP : End Point
// RC : Root complex
// DT : Descriptor Table
// MWr : Memory write
// MRd : Memory read
// CPLD : Completion with data
// MSI : PCIe Message Signaled Interrupt
// BDT : Base address of the descriptor header table in RC memory
// BDT_LSB : Base address of the descriptor header table in RC memory
// BDT_MSB : Base address of the descriptor header table in RC memory
// BRC : [BDT_MSB:BDT_LSB]
// DW0 : First DWORD of the descriptor table header
// DW1 : Second DWORD of the descriptor table header
// DW2 : Third DWORD of the descriptor table header
// RCLAST : RC MWr RCLAST in EP memeory to reflects the number
// of DMA transfers ready to start
// EPLAST : EP MWr EPLAST in shared memeory to reflects the number
// of completed DMA transfers
//
//-----------------------------------------------------------------------------
// Copyright � 2009 Altera Corporation. All rights reserved. Altera products are
// protected under numerous U.S. and foreign patents, maskwork rights, copyrights and
// other intellectual property laws.
//
// This reference design file, and your use thereof, is subject to and governed by
// the terms and conditions of the applicable Altera Reference Design License Agreement.
// By using this reference design file, you indicate your acceptance of such terms and
// conditions between you and Altera Corporation. In the event that you do not agree with
// such terms and conditions, you may not use the reference design file. Please promptly
// destroy any copies you have made.
//
// This reference design file being provided on an "as-is" basis and as an accommodation
// and therefore all warranties, representations or guarantees of any kind
// (whether express, implied or statutory) including, without limitation, warranties of
// merchantability, non-infringement, or fitness for a particular purpose, are
// specifically disclaimed. By making this reference design file available, Altera
// expressly does not recommend, suggest or require that this reference design file be
// used in combination with any other product not provided by Altera.
//-----------------------------------------------------------------------------
`define STR_SEP "---------"
module altpcietb_bfm_driver_chaining (input clk_in,
input INTA,
input INTB,
input INTC,
input INTD,
input rstn,
output dummy_out);
// TEST_LEVEL is a parameter passed in from the top level test bench that
// could control the amount of testing done. It is not currently used.
// Global parameter
parameter TEST_LEVEL = 1;
parameter TL_BFM_MODE = 1'b0; // 0 means full stack RP BFM mode, 1 means TL-only RP BFM (remove CFG accesses to RP internal cfg space)
parameter TL_BFM_RP_CAP_REG = 32'h42; // In TL BFM mode, pass PCIE Capabilities reg thru parameter (- there is no RP config space).
// {specify: port type, cap version}
parameter TL_BFM_RP_DEV_CAP_REG = 32'h05; // In TL BFM mode, pass Device Capabilities reg thru parameter (- there is no RP config space)..
// {specify: maxpayld size}
parameter USE_CDMA = 1; // When set enable EP upstream MRd/MWr test
parameter USE_TARGET = 1; // When set enable target test
localparam DISPLAY_ALL = 1;
localparam NUMBER_OF_DESCRIPTORS = 3;
localparam SCR_MEM = 2048; // Share memory base address used by DMA
localparam SCR_MEMSLAVE = 64; // Share memory base address used by RC Slave module
localparam SCR_MEM_DOWNSTREAM_WR = SCR_MEMSLAVE;
localparam SCR_MEM_DOWNSTREAM_RD = SCR_MEMSLAVE+2048;
localparam MAX_RCPAYLOAD = 128;
localparam RCSLAVE_MAXLEN = 10; // maximum number of read/write
localparam TIMEOUT_POLLING = 2048; // number of clock' for timout
// using the chaining DMA module
// Descriptor Table Parameters
localparam DT_EPLAST = 4'hc;
localparam MEM_DESCR_LENGTH_INC = 2;
localparam DMA_CONTINOUS_LOOP = 0;
// Write DMA DESCRIPTOR TABLE Content
localparam integer WR_DIRECTION = 1;
localparam integer WR_DESCRIPTOR_DEPTH = 4; // 4 DWORDS
localparam integer WR_BDT_LSB = SCR_MEM;
localparam integer WR_BDT_MSB = 0;
localparam integer WR_FIRST_DESCRIPTOR = WR_BDT_LSB+16;
localparam integer WR_DESC0_CTL_MSI = 0;
localparam integer WR_DESC0_CTL_EPLAST = 1; // send EPLast update when done with this descriptor
localparam integer WR_DESC0_LENGTH = 82;
localparam integer WR_DESC0_EPADDR = 3;
localparam integer WR_DESC0_RCADDR_MSB = 0;
localparam integer WR_DESC0_RCADDR_LSB = WR_BDT_LSB+4096;
localparam integer WR_DESC0_INIT_BFM_MEM = 64'h0000_0000_1515_0001;
localparam integer WR_DESC1_CTL_MSI = 0;
localparam integer WR_DESC1_CTL_EPLAST = 0;
localparam integer WR_DESC1_LENGTH = 1024;
localparam integer WR_DESC1_EPADDR = 0;
localparam integer WR_DESC1_RCADDR_MSB = 0;
localparam integer WR_DESC1_RCADDR_LSB = WR_BDT_LSB+8192;
localparam integer WR_DESC1_INIT_BFM_MEM = 64'h0000_0000_2525_0001;
localparam integer WR_DESC2_CTL_MSI = 1; // send MSI when done with this descriptor
localparam integer WR_DESC2_CTL_EPLAST = 1; // send EPLast update when done with this descriptor
localparam integer WR_DESC2_LENGTH = 644;
localparam integer WR_DESC2_EPADDR = 0;
localparam integer WR_DESC2_RCADDR_MSB = 0;
localparam integer WR_DESC2_RCADDR_LSB = WR_BDT_LSB+20384;
localparam integer WR_DESC2_INIT_BFM_MEM = 64'h0000_0000_3535_0001;
// READ DMA DESCRIPTOR TABLE Content
localparam integer RD_DIRECTION = 0;
localparam integer RD_DESCRIPTOR_DEPTH = 4;
localparam integer RD_BDT_LSB = SCR_MEM+256;
localparam integer RD_BDT_MSB = 0;
localparam integer RD_FIRST_DESCRIPTOR = RD_BDT_LSB+16;
localparam integer RD_DESC0_CTL_MSI = WR_DESC0_CTL_MSI;
localparam integer RD_DESC0_CTL_EPLAST = WR_DESC0_CTL_EPLAST;
localparam integer RD_DESC0_LENGTH = 82;
localparam integer RD_DESC0_EPADDR = 3;
localparam integer RD_DESC0_RCADDR_MSB = 0;
localparam integer RD_DESC0_RCADDR_LSB = RD_BDT_LSB+34032;
localparam integer RD_DESC0_INIT_BFM_MEM = 64'h0000_0000_AAA0_0001;
localparam integer RD_DESC1_CTL_MSI = WR_DESC1_CTL_MSI;
localparam integer RD_DESC1_CTL_EPLAST = WR_DESC1_CTL_EPLAST;
localparam integer RD_DESC1_LENGTH = 1024;
localparam integer RD_DESC1_EPADDR = 0;
localparam integer RD_DESC1_RCADDR_MSB = 10;
localparam integer RD_DESC1_RCADDR_LSB = RD_BDT_LSB+65536;
localparam integer RD_DESC1_INIT_BFM_MEM = 64'h0000_0000_BBBB_0001;
localparam integer RD_DESC2_CTL_MSI = WR_DESC2_CTL_MSI;
localparam integer RD_DESC2_CTL_EPLAST = WR_DESC2_CTL_EPLAST;
localparam integer RD_DESC2_LENGTH = 644;
localparam integer RD_DESC2_EPADDR = 0;
localparam integer RD_DESC2_RCADDR_MSB = 0;
localparam integer RD_DESC2_RCADDR_LSB = RD_BDT_LSB+132592;
localparam integer RD_DESC2_INIT_BFM_MEM = 64'h0000_0000_CCCC_0001;
// Information used by driver for polling Chaining DMA status for completion.
// These must correspond to the _DESCx_CTL_MSI and _DESCx_CTL_EPLAST parameters above.
localparam EPLAST_DONE_VALUE = 2; // The EPLast Number that the driver expects to receive from each DMA after all data transfers have completed
localparam NUM_EPLAST_EXPECTED = WR_DESC0_CTL_EPLAST + WR_DESC1_CTL_EPLAST + WR_DESC2_CTL_EPLAST; // Number of Descriptors programmed to send EPLAST status update to root port
localparam NUM_MSI_EXPECTED = WR_DESC0_CTL_MSI + WR_DESC1_CTL_MSI + WR_DESC2_CTL_MSI; // Number of MSI's that the driver expects to receive from each DMA after all data transfers have completed
localparam DEBUG_PRG = 0;
`include "altpcietb_bfm_constants.v"
`include "altpcietb_bfm_log.v"
`include "altpcietb_bfm_shmem.v"
`include "altpcietb_bfm_rdwr.v"
`include "altpcietb_bfm_configure.v"
// The clk_in and rstn signals are provided for possible use in controlling
// the transactions issued, they are not currently used.
// ebfm_display_verb
// overload ebfm_display by turning on/off verbose when DISPLAY_ALL>0
function ebfm_display_verb(
input integer msg_type,
input [EBFM_MSG_MAX_LEN*8:1] message);
reg unused_result;
begin
if (DISPLAY_ALL==1)
unused_result = ebfm_display(msg_type, message);
ebfm_display_verb = 1'b0 ;
end
endfunction
/////////////////////////////////////////////////////////////////////////
//
// TASK:dma_set_msi:
//
// Setup native PCIe MSI for DMA read and DMA write.
// Retrieve MSI capabilities of EP, program EP MSI cfg register
// with msi_address and msi_data
//
// input argument:
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
// bus_num : default 1
// dev_num : default 0
// fnc_num : default 0
// dt_direction : Read or write
// msi_address : RC Mem MSI address
// msi_data : MSI cgf data
//
// returns:
// msi_number (default : 1 for write , 0 for read)
// msi_traffic_class MSI traffic class (default 0)
// msi_expected Expected data written by MSI to RC Host memory
//
task dma_set_msi (
input integer bar_table ,
input integer setup_bar ,
input integer bus_num ,
input integer dev_num ,
input integer fnc_num ,
input integer dt_direction ,
input integer msi_address ,
input integer msi_data ,
output reg [4:0] msi_number ,
output reg [2:0] msi_traffic_class,
output reg [2:0] multi_message_enable,
output integer msi_expected
);
localparam msi_capabilities = 32'h50;
// The Root Complex BFM has 2MB of address space
localparam msi_upper_address = 32'h0000_0000;
reg [15:0] msi_control_register;
reg msi_64b_capable;
reg [2:0] multi_message_capable;
reg msi_enable;
reg [2:0] compl_status;
reg unused_result ;
begin
// MSI
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
if (dt_direction==RD_DIRECTION)
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_msi READ");
else
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_msi WRITE");
unused_result = ebfm_display_verb(EBFM_MSG_INFO,
" Message Signaled Interrupt Configuration");
// Read the contents of the MSI Control register
msi_traffic_class = 0; //TODO make it an input argument
unused_result = ebfm_display(EBFM_MSG_INFO, {" msi_address (RC memory)= 0x",
himage4(msi_address)});
// RC Reading MSI capabilities of the EP
// to get msi_control_register
ebfm_cfgrd_wait(bus_num, dev_num, fnc_num,
msi_capabilities, 4,
msi_address,
compl_status);
msi_control_register = shmem_read(msi_address+2, 2);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {" msi_control_register = 0x",
himage4(msi_control_register)});
// Program the MSI Message Control register for testing
msi_64b_capable = msi_control_register[7];
// Enable the MSI with Maximum Number of Supported Messages
multi_message_capable = msi_control_register[3:1];
multi_message_enable = multi_message_capable;
msi_enable = 1'b1;
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num,
msi_capabilities, 4,
{8'h00, msi_64b_capable,
multi_message_enable,
multi_message_capable,
msi_enable, 16'h0000},
compl_status);
msi_number[4:0]= (1==dt_direction)?5'h1:5'h0;
// Retrieve msi_expected
if (multi_message_enable==3'b000)
begin
unused_result = ebfm_display(EBFM_MSG_WARNING,
"The chained DMA example design required at least 2 MSI ");
unused_result = ebfm_log_stop_sim(1);
end
else
begin
case (multi_message_enable)
3'b000: msi_expected = msi_data[15:0];
3'b001: msi_expected = {msi_data[15:1], msi_number[0] };
3'b010: msi_expected = {msi_data[15:2], msi_number[1:0]};
3'b011: msi_expected = {msi_data[15:3], msi_number[2:0]};
3'b100: msi_expected = {msi_data[15:4], msi_number[3:0]};
3'b101: msi_expected = {msi_data[15:5], msi_number[4:0]};
default: unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL,
"Illegal multi_message_enable value detected. MSI test fails.");
endcase
end
// Write the rest of the MSI Capabilities Structure:
// Address and Data Fields
if (msi_64b_capable) // 64-bit Addressing
begin
// Specify the RC lower Address where the MSI need to be written
// when EP issues MSI (msi_address= dt_bdt_lsb-16)
// 4 DWORD bellow the descriptor table
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num,
msi_capabilities + 4'h4, 4,
msi_address,
compl_status);
// Specify the RC Upper Address where the MSI need to be written
// when EP issues MSI
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num,
msi_capabilities + 4'h8, 4,
msi_upper_address,
compl_status);
// Specify the data to be written in the RC Memeoryr MSI location
// when EP issues MSI
// (msi_data = 16'hb0fe)
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num,
msi_capabilities + 4'hC, 4,
msi_data,
compl_status);
end
else // 32-bit Addressing
begin
// Specify the RC lower Address where the MSI need to be written
// when EP issues MSI (msi_address= dt_bdt_lsb-16)
// 4 DWORD bellow the descriptor table
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num,
msi_capabilities + 4'h4, 4,
msi_address, compl_status);
// Specify the data to be written in the RC Memeoryr MSI location
// when EP issues MSI
// (msi_data = 16'hb0fe)
ebfm_cfgwr_imm_wait(bus_num, dev_num, fnc_num,
msi_capabilities + 4'h8, 4,
msi_data, compl_status);
end
// Clear RC memory MSI Location
shmem_write(msi_address, 32'h1111_FADE,4);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {" msi_expected = 0x",
himage4(msi_expected)});
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {" msi_capabilities address = 0x",
himage4(msi_capabilities)});
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {" multi_message_enable = 0x",
himage4(multi_message_enable)});
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {" msi_number = ",
dimage4(msi_number)});
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {" msi_traffic_class = ",
dimage4(msi_traffic_class)});
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:dma_set_header :
//
// RC issues MWr to write Descriptor table header DW0, DW1, DW2
// RC initializaed RC shared memory with MSI_DATA, DW0, DW1, DW2
//
// Descriptor header table in EP shared memory :
//
// |----------------------------------------------
// | DMA Write
// |----------------------------------------------
// | 0h | DW0
// |--------|-------------------------------------
// | 04h | DW1
// |--------|-------------------------------------
// | 08h | DW2
// |--------|-------------------------------------
// | 0ch | RCLast
// | | RC MWr RCLast : Available DMA number
// |----------------------------------------------
// | DMA Read
// |----------------------------------------------
// |10h | DW0
// |--------|-------------------------------------
// |14h | DW1
// |--------|-------------------------------------
// |18h | DW2
// |--------|-------------------------------------
// |1ch | RCLast
// | | RC MWr RCLast : Available DMA number
// |----------------------------------------------
//
// Descriptor header table in RC shared memory :
//
// |--------|----------------------------------------------
// | -10h | MSI_DATA
// | | EP MWr MSI at the end of DMA transfer
// |--------|----------------------------------------------
// |BDT LSB | DW0
// |--------|----------------------------------------------
// |+04h | DW1
// |--------|----------------------------------------------
// |+08h | DW2
// |--------|----------------------------------------------
// |+0ch | EPLAST
// | | EP MWr EPLAST to reflects DMA transfer number
// |-------------------------------------------------------
//
task dma_set_header (
input integer bar_table , // Pointer to the BAR sizing and
input integer setup_bar , // BAR to be used for setting up
input integer dt_size , // total number of descriptors in the descriptor table
input integer dt_direction , // Specifies which descriptor table to set up: DMA Read or write
input integer dt_msi , // control bit which specifies to use MSI for all descriptors
input integer dt_eplast , // control bit which specifies to use EPLast for all descriptors
input integer dt_bdt_msb , // upper 32 bits base address of the descriptor table location in Root Port memory space
input integer dt_bdt_lsb , //lower 32 bits base address of the descriptor table location in Root Port memory space
input [4:0] msi_number , // MSI
input [2:0] msi_traffic_class, // MSI
input [2:0] multi_message_enable, // MSI
input stop_dma_loop
);
reg [31:0] dt_dw0;
integer dt_dw1,dt_dw2 ;
integer ep_offset ;
reg unused_result ;
begin
// Constructing header dsecriptor table DWORDS DW0
dt_dw0[15:0] = dt_size;
dt_dw0[16] = 1'b0;
dt_dw0[17] = (dt_msi ==0)?1'b0:1'b1;
dt_dw0[18] = (dt_eplast ==0)?1'b0:1'b1;
dt_dw0[19] = 1'b0;
dt_dw0[24:20] = msi_number[4:0];
dt_dw0[27:25] = 3'b000;
dt_dw0[30:28] = msi_traffic_class;
dt_dw0[31] = ((DMA_CONTINOUS_LOOP>0)&&(stop_dma_loop==1'b0))?1'b1:1'b0;
// Constructing header dsecriptor table DWORDS DW1
dt_dw1 = dt_bdt_msb;
// Constructing header dsecriptor table DWORDS DW2
dt_dw2 = dt_bdt_lsb;
// DMA Write ep_offset /BAR = 0;
// DMA Read ep_offset /BAR = 16 (4 DWORDs);
ep_offset = (WR_DIRECTION==dt_direction)?0:16;
// display section
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
if (dt_direction==RD_DIRECTION)
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_header READ");
else
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_header WRITE");
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "Writing Descriptor header");
// RC writes EP DMA register (for module altpcie_dma_prg_reg)
if (DEBUG_PRG==0) begin
ebfm_barwr_imm(bar_table, setup_bar, 0+ep_offset, dt_dw0, 4, 0);
ebfm_barwr_imm(bar_table, setup_bar, 4+ep_offset, dt_dw1, 4, 0);
ebfm_barwr_imm(bar_table, setup_bar, 8+ep_offset, dt_dw2, 4, 0);
end
else begin
ebfm_barwr_imm(bar_table, setup_bar, 0+ep_offset, 32'hC1FE_FADE, 4, 0);
ebfm_barwr_imm(bar_table, setup_bar, 4+ep_offset, 32'hC2FE_FADE, 4, 0);
ebfm_barwr_imm(bar_table, setup_bar, 8+ep_offset, 32'hC3FE_FADE, 4, 0);
end
// RC writes RC Memory
shmem_write(dt_bdt_lsb , dt_dw0,4);
shmem_write(dt_bdt_lsb+4, dt_dw1,4);
shmem_write(dt_bdt_lsb+8, dt_dw2,4);
shmem_write(dt_bdt_lsb+12, 32'hCAFE_FADE,4);
shmem_fill(dt_bdt_lsb+12,SHMEM_FILL_DWORD_INC,4,32'hCAFE_FADE);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "data content of the DT header");
if (DISPLAY_ALL==1)
unused_result =shmem_display(dt_bdt_lsb,4*4,4,dt_bdt_lsb+(4*4),EBFM_MSG_INFO);
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:dma_set_rclast :
// RC issues MWr RCLast to EP at address C on the EP site
// RCLast is a WORD which represent the number of the DMA descriptor
// ready for transfer.
// Writing RCLast to EP trigger the start of the DMA transfer
//
// input argument
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
// dt_direction : Read (0) or Write (1)
// dt_rclast : status bit to write back ep_counter info
//
task dma_set_rclast (
input integer bar_table ,
input integer setup_bar ,
input integer dt_direction ,
input integer dt_rclast
);
reg [31:0] dt_dw4 ;
integer ep_offset ;
reg unused_result ;
begin
// DMA Write ep_offset /BAR = 0;
// DMA Read ep_offset /BAR = 16 (4 DWORDs);
ep_offset = (WR_DIRECTION==dt_direction)?0:16;
dt_dw4[15:0] = dt_rclast;
dt_dw4[31:16] = 0;
// display section
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_rclast");
if (dt_direction==RD_DIRECTION)
unused_result = ebfm_display_verb(EBFM_MSG_INFO,
{" Start READ DMA : RC issues MWr (RCLast=",
dimage4(dt_rclast), ")"});
else
unused_result = ebfm_display_verb(EBFM_MSG_INFO,
{" Start WRITE DMA : RC issues MWr (RCLast=",
dimage4(dt_rclast), ")"});
// RC writes EP DMA register
ebfm_barwr_imm(bar_table, setup_bar, 12+ep_offset, dt_dw4, 4, 0);
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK: dma_set_wr_desc_data :
//
// write 'write descriptor table in the RC Memory
//
/////////////////////////////////////////////////////
// |-------------------------------------
// | header write
// |-------------------------------------
// BRC+0h | DW0: number of descriptor
// BRC+4h | DW1: BDT MSB
// BRC+8h | DW2: BDT LSB
// BRC+ch | DW3: EP Last
// |-------------------------------------
// | desc0 write
// |-------------------------------------
// BRC+10h | DW0: length : 256 DWORDS
// BRC+14h | DW1: EP ADDR : 0h
// BRC+18h | DW2: RC ADDR MSB : BDT_MSB
// BRC+1ch | DW3: RC ADDR LSB : BRC+01000h
// |-------------------------------------
// | desc1 write
// |-------------------------------------
// BRC+20h | DW0: length : 512 DWORDS
// BRC+24h | DW1: EP ADDR : 0h
// BRC+28h | DW2: RC ADDR MSB : BDT_MSB
// BRC+2ch | DW3: RC ADDR LSB : BRC+02000h
// |-------------------------------------
// | desc2 write
// |-------------------------------------
// BRC+30h | DW0: length : 1024 DWORDS
// BRC+34h | DW1: EP ADDR : 0h
// BRC+38h | DW2: RC ADDR MSB : BDT_MSB
// BRC+3ch | DW3: RC ADDR LSB : BRC+03000h
// |-------------------------------------
//
// input arguments
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
//
task dma_set_wr_desc_data (
input integer bar_table ,
input integer setup_bar
);
reg unused_result ;
integer descriptor_addr,i;
integer loop_DW0;
integer loop_DW1;
integer loop_DW2;
integer loop_DW3;
integer loop_control_field;
begin
//program BFM share memeory
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_wr_desc_data");
// First Descriptor
descriptor_addr = WR_FIRST_DESCRIPTOR;
loop_control_field = ((2**17) * WR_DESC0_CTL_EPLAST) + ((2**16) * WR_DESC0_CTL_MSI); // Assemble Descriptor Control Field
shmem_write(descriptor_addr , (loop_control_field + WR_DESC0_LENGTH) ,4);
shmem_write(descriptor_addr+4, WR_DESC0_EPADDR ,4);
shmem_write(descriptor_addr+8, WR_DESC0_RCADDR_MSB ,4);
shmem_write(descriptor_addr+12, WR_DESC0_RCADDR_LSB ,4);
shmem_fill(WR_DESC0_RCADDR_LSB,SHMEM_FILL_DWORD_INC,
WR_DESC0_LENGTH*4,WR_DESC0_INIT_BFM_MEM);
// Display descriptor table of DMA Write
if (NUMBER_OF_DESCRIPTORS>3)
begin
for (i=1;i<NUMBER_OF_DESCRIPTORS-1;i=i+1)
begin
descriptor_addr = WR_FIRST_DESCRIPTOR + 16*i;
loop_control_field = ((2**17) * WR_DESC1_CTL_EPLAST) + ((2**16) * WR_DESC1_CTL_MSI); // Assemble Descriptor Control Field
loop_DW0 = loop_control_field + WR_DESC1_LENGTH + i*MEM_DESCR_LENGTH_INC;
loop_DW1 = WR_DESC1_EPADDR ;
loop_DW2 = WR_DESC1_RCADDR_MSB;
loop_DW3 = WR_DESC1_RCADDR_LSB;
shmem_write(descriptor_addr , loop_DW0 ,4);
shmem_write(descriptor_addr+4, loop_DW1 ,4);
shmem_write(descriptor_addr+8, loop_DW2 ,4);
shmem_write(descriptor_addr+12, loop_DW3 ,4);
if (i==1)
shmem_fill(WR_DESC1_RCADDR_LSB,SHMEM_FILL_DWORD_INC, loop_DW0*4,
WR_DESC1_INIT_BFM_MEM);
end
i = NUMBER_OF_DESCRIPTORS-2;
end
else
begin
i = 1;
// Descriptor 1
descriptor_addr = WR_FIRST_DESCRIPTOR+16;
loop_control_field = ((2**17) * WR_DESC1_CTL_EPLAST) + ((2**16) * WR_DESC1_CTL_MSI); // Assemble Descriptor Control Field
shmem_write(descriptor_addr , loop_control_field + WR_DESC1_LENGTH ,4);
shmem_write(descriptor_addr+4, WR_DESC1_EPADDR ,4);
shmem_write(descriptor_addr+8, WR_DESC1_RCADDR_MSB ,4);
shmem_write(descriptor_addr+12, WR_DESC1_RCADDR_LSB ,4);
shmem_fill(WR_DESC1_RCADDR_LSB,SHMEM_FILL_DWORD_INC,
WR_DESC1_LENGTH*4,WR_DESC1_INIT_BFM_MEM);
end
// Last Descriptor
descriptor_addr = WR_FIRST_DESCRIPTOR+16*(i+1);
loop_control_field = ((2**17) * WR_DESC2_CTL_EPLAST) + ((2**16) * WR_DESC2_CTL_MSI); // Assemble Descriptor Control Field
shmem_write(descriptor_addr , loop_control_field + WR_DESC2_LENGTH ,4);
shmem_write(descriptor_addr+4, WR_DESC2_EPADDR ,4);
shmem_write(descriptor_addr+8, WR_DESC2_RCADDR_MSB ,4);
shmem_write(descriptor_addr+12, WR_DESC2_RCADDR_LSB ,4);
shmem_fill(WR_DESC2_RCADDR_LSB,SHMEM_FILL_DWORD_INC,
WR_DESC2_LENGTH*4,WR_DESC2_INIT_BFM_MEM);
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:dma_set_rd_desc_data : write 'read descriptor table in the RC Memory
//
// |-------------------------------------
// | header read
// |-------------------------------------
// BRC+100h | DW0: number of descriptor
// BRC+104h | DW1: BDT MSB
// BRC+108h | DW2: BDT LSB
// BRC+10ch | DW3: EP Last
// |-------------------------------------
// | desc0 read
// |-------------------------------------
// BRC+110h | DW0: length
// BRC+114h | DW1: EP ADDR : 0h
// BRC+118h | DW2: RC ADDR MSB : BDT_MSB
// BRC+11ch | DW3: RC ADDR LSB : BRC+05000h
// |-------------------------------------
// | desc1 read
// |-------------------------------------
// BRC+120h | DW0: length
// BRC+124h | DW1: EP ADDR : 0h
// BRC+128h | DW2: RC ADDR MSB : BDT_MSB
// BRC+12ch | DW3: RC ADDR LSB :
// |-------------------------------------
// | desc2 read
// |-------------------------------------
// BRC+130h | DW0: length
// BRC+134h | DW1: EP ADDR : 0h
// BRC+138h | DW2: RC ADDR MSB : BDT_MSB
// BRC+13ch | DW3: RC ADDR LSB :
// |-------------------------------------
//
// input arguments
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
//
task dma_set_rd_desc_data
(
input integer bar_table,
input integer setup_bar
);
// HEADER PARAMETERS
reg unused_result ;
integer descriptor_addr,i;
integer loop_DW0;
integer loop_DW1;
integer loop_DW2;
integer loop_DW3;
integer loop_control_field;
begin
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_set_rd_desc_data");
//program BFM share memory :
// First Descriptor
descriptor_addr = RD_FIRST_DESCRIPTOR;
loop_control_field = ((2**17) * RD_DESC0_CTL_EPLAST) + ((2**16) * RD_DESC0_CTL_MSI); // Assemble Descriptor Control Field
shmem_write(descriptor_addr , loop_control_field + RD_DESC0_LENGTH ,4);
shmem_write(descriptor_addr+4, RD_DESC0_EPADDR ,4);
shmem_write(descriptor_addr+8, RD_DESC0_RCADDR_MSB ,4);
shmem_write(descriptor_addr+12, RD_DESC0_RCADDR_LSB ,4);
shmem_fill(RD_DESC0_RCADDR_LSB,SHMEM_FILL_DWORD_INC,RD_DESC0_LENGTH*4,
RD_DESC0_INIT_BFM_MEM);
if (NUMBER_OF_DESCRIPTORS>3)
begin
for (i=1;i<NUMBER_OF_DESCRIPTORS-1;i=i+1)
begin
descriptor_addr = RD_FIRST_DESCRIPTOR + 16*i;
loop_control_field = ((2**17) * RD_DESC1_CTL_EPLAST) + ((2**16) * RD_DESC1_CTL_MSI); // Assemble Descriptor Control Field
loop_DW0 = loop_control_field + RD_DESC1_LENGTH + i*MEM_DESCR_LENGTH_INC;
loop_DW1 = RD_DESC1_EPADDR ;
loop_DW2 = RD_DESC1_RCADDR_MSB;
loop_DW3 = RD_DESC1_RCADDR_LSB;
shmem_write(descriptor_addr , loop_DW0 ,4);
shmem_write(descriptor_addr+4, loop_DW1 ,4);
shmem_write(descriptor_addr+8, loop_DW2 ,4);
shmem_write(descriptor_addr+12, loop_DW3 ,4);
if (i==1)
shmem_fill(RD_DESC1_RCADDR_LSB,SHMEM_FILL_DWORD_INC, loop_DW0*4,
RD_DESC1_INIT_BFM_MEM);
end
i = NUMBER_OF_DESCRIPTORS-2;
end
else
begin
// Descriptor 1
i = 1;
descriptor_addr = RD_FIRST_DESCRIPTOR+16;
loop_control_field = ((2**17) * RD_DESC1_CTL_EPLAST) + ((2**16) * RD_DESC1_CTL_MSI); // Assemble Descriptor Control Field
shmem_write(descriptor_addr , loop_control_field + RD_DESC1_LENGTH ,4);
shmem_write(descriptor_addr+4, RD_DESC1_EPADDR ,4);
shmem_write(descriptor_addr+8, RD_DESC1_RCADDR_MSB ,4);
shmem_write(descriptor_addr+12, RD_DESC1_RCADDR_LSB ,4);
shmem_fill(RD_DESC1_RCADDR_LSB, SHMEM_FILL_DWORD_INC,
RD_DESC1_LENGTH*4,RD_DESC1_INIT_BFM_MEM);
end
// Last Descriptor
descriptor_addr = RD_FIRST_DESCRIPTOR+16*(i+1);
loop_control_field = ((2**17) * RD_DESC2_CTL_EPLAST) + ((2**16) * RD_DESC2_CTL_MSI); // Assemble Descriptor Control Field
shmem_write(descriptor_addr , loop_control_field + RD_DESC2_LENGTH ,4);
shmem_write(descriptor_addr+4, RD_DESC2_EPADDR ,4);
shmem_write(descriptor_addr+8, RD_DESC2_RCADDR_MSB ,4);
shmem_write(descriptor_addr+12, RD_DESC2_RCADDR_LSB ,4);
shmem_fill(RD_DESC2_RCADDR_LSB,SHMEM_FILL_DWORD_INC,
RD_DESC2_LENGTH*4,RD_DESC2_INIT_BFM_MEM);
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:msi_poll
// Polling process to track in shared memeory received MSI from EP
//
// input argument
// max_number_of_msi : Total Number of MSI to track
// msi_address : MSI Address in shared memeory
// msi_expected_dmawr : Expected MSI when dma_write is set
// msi_expected_dmard : Expected MSI when dma_read is set
// dma_write : Set dma_write
// dma_read : set dma_read
task msi_poll(
input integer max_number_of_msi,
input integer msi_address,
input integer msi_expected_dmawr,
input integer msi_expected_dmard,
input integer dma_write,
input integer dma_read
);
reg unused_result ;
integer msi_received;
integer msi_count;
reg pol_ip;
begin
// unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
// unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:msi_poll Start polling");
for (msi_count=0; msi_count < max_number_of_msi;msi_count=msi_count+1)
begin
pol_ip=0;
fork
// Set timeout failure if expected MSI is not received
begin:timeout_msi
repeat (100000) @(posedge clk_in);
unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL,
"MSI timeout occured, MSI never received, Test Fails");
disable wait_for_msi;
end
// Polling memory for expected MSI data value
// at the assigned MSI address location
begin:wait_for_msi
forever
begin
repeat (4) @(posedge clk_in);
msi_received = shmem_read (msi_address, 2);
if (pol_ip==0)
unused_result = ebfm_display(EBFM_MSG_INFO,{
"TASK:msi_poll Polling MSI Address:",
himage4(msi_address),
"---> Data:",
himage4(msi_received),
"......"});
pol_ip=1;
if ((msi_received == msi_expected_dmawr) && (dma_write==1))
begin
unused_result = ebfm_display(EBFM_MSG_INFO,
{"TASK:msi_poll Received DMA Write MSI(",
dimage4(msi_count),
") : ",
himage4(msi_received)});
shmem_write( msi_address , 32'h1111_FADE, 4);
disable timeout_msi;
disable wait_for_msi;
end
if ((msi_received == msi_expected_dmard) && (dma_read==1))
begin
unused_result = ebfm_display(EBFM_MSG_INFO,
{"TASK:msi_poll Received DMA Read MSI(",
dimage4(msi_count),
") : ",
himage4(msi_received)});
shmem_write( msi_address , 32'h1111_FADE, 4);
disable timeout_msi;
disable wait_for_msi;
end
end
end
join
end
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// rcmem_poll
//
// Polling routine waiting for rc_data at location rc_addr
//
task rcmem_poll(
input integer rc_addr,
input integer rc_data,
input integer rc_data_mask);
reg unused_result ;
integer rc_current;
integer rc_last;
reg [31:0] timout_limit;
reg pol_ip;
begin
// unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
// unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:rcmem_poll Start polling");
pol_ip=0;
timout_limit[31:0]=0;
fork
begin:wait_for_rcmem
forever
begin
repeat (50) @(posedge clk_in);
rc_current = (shmem_read (rc_addr, 4) & (rc_data_mask));
if (pol_ip==0) begin
timout_limit[31:0]=0;
rc_last = rc_current;
unused_result = ebfm_display_verb(EBFM_MSG_INFO,
{"TASK:rcmem_poll Polling RC Address" ,himage8(rc_addr),
" current data (" ,himage8(rc_current),
") expected data (",himage8(rc_data),")"});
end
if (rc_current != rc_last ) begin
unused_result = ebfm_display(EBFM_MSG_INFO,
{"TASK:rcmem_poll Polling RC Address" ,himage8(rc_addr),
" current data (" ,himage8(rc_current),
") expected data (",himage8(rc_data),")"});
timout_limit[31:0]=0;
end
else
timout_limit[31:0]=timout_limit[31:0]+1;
rc_last = rc_current;
pol_ip=1;
if (timout_limit[31:0]>TIMEOUT_POLLING) begin
unused_result = ebfm_display(EBFM_MSG_INFO,
" ---> TASK:rcmem_poll timeout occured");
unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL,
{" ---> Test Fails: RC Address:",
himage8(rc_addr)," contains ", himage8(rc_current)});
disable wait_for_rcmem;
end
if (rc_current == rc_data)
begin
unused_result = ebfm_display(EBFM_MSG_INFO,
{"TASK:rcmem_poll ---> Received Expected Data (",himage8(rc_current),")"});
disable wait_for_rcmem;
end
end
end
join
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:dma_rd_test
//
// Run the chained DMA read
//
// Input argument
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
// 4 Write then Read
// use_global_msi : When set, use global msi
// use_global_eplast: When set, use global eplast
//
task dma_rd_test(
input integer bar_table,
input integer setup_bar,
input integer use_global_msi,
input integer use_global_eplast);
localparam integer MSI_ADDRESS = SCR_MEM-16;
localparam integer MSI_DATA = 16'hb0fe;
reg unused_result ;
integer RCLast;
reg [4:0] msi_number ;
reg [2:0] msi_traffic_class ;
reg [2:0] multi_message_enable;
integer msi_address ;
integer msi_expected_dmawr ;
integer msi_expected_dmard ;
integer msi_received ;
integer msi_count ;
integer max_count ;
integer i;
reg [31:0] track_rclast_loop;
reg use_msi;
reg use_eplast;
reg [4:0] msi_number_int ;
reg [2:0] msi_traffic_class_int ;
reg [2:0] multi_message_enable_int;
begin
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_rd_test");
// Read descriptor table in the RC Memory
dma_set_rd_desc_data(bar_table, setup_bar);
use_msi = use_global_msi | (NUM_MSI_EXPECTED > 0);
use_eplast = use_global_eplast | (NUM_EPLAST_EXPECTED > 0);
// Set MSI for DMA Read
if (use_msi==1)
dma_set_msi( bar_table, // Pointer to the BAR sizing and
setup_bar, // BAR to be used for setting up
1, // bus_num
1, // dev_num
0, // fnc_num
RD_DIRECTION, // Direction
MSI_ADDRESS, // MSI RC memeory address
MSI_DATA, // MSI Cfg data value
msi_number, // msi_number
msi_traffic_class, //msi traffic class
multi_message_enable, // number of msi
msi_expected_dmard // expexted MSI data value
);
msi_number_int = (use_msi == 1'b1) ? msi_number : 5'h0;
msi_traffic_class_int = (use_msi == 1'b1) ? msi_number : 3'h0;
multi_message_enable_int = (use_msi == 1'b1) ? msi_number : 3'h0;
// Read Descriptor header in EP memory PRG
dma_set_header( bar_table, // Pointer to the BAR sizing and
setup_bar, // BAR to be used for setting up
NUMBER_OF_DESCRIPTORS, // number of descriptor
RD_DIRECTION, // Direction read
use_global_msi, // global MSI control
use_global_eplast, // global eplast control
RD_BDT_MSB, // RC upper 32 bits of bdt
RD_BDT_LSB, // RC lower 32 bits of bdt
msi_number_int,
msi_traffic_class_int,
multi_message_enable_int,
0);
//Program RP RCLast
RCLast = NUMBER_OF_DESCRIPTORS-1; // 3 descriptor, written 0,1,2
// Start read DMA
dma_set_rclast(bar_table, setup_bar, RD_DIRECTION, RCLast);
fork // polling
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
// Monitor MSI - Polling MSI
if (use_msi==1)
if (use_global_msi==1)
msi_poll(NUMBER_OF_DESCRIPTORS,MSI_ADDRESS,0, msi_expected_dmard,0,1);
else
msi_poll(NUM_MSI_EXPECTED,MSI_ADDRESS,0, msi_expected_dmard,0,1);
// Polling EP Last
if (use_eplast==1) begin
if (DMA_CONTINOUS_LOOP==0)
rcmem_poll(RD_BDT_LSB+DT_EPLAST, RCLast,32'h0000FFFF);
else begin
for (i=0;i<DMA_CONTINOUS_LOOP;i=i+1) begin
unused_result = ebfm_display(EBFM_MSG_INFO, { " Running DMA loop ", dimage4(i), " : "});
shmem_write(RD_BDT_LSB+DT_EPLAST, 32'hCAFE_FADE,4);
rcmem_poll(RD_BDT_LSB+DT_EPLAST, RCLast,32'h0000FFFF);
end
shmem_write(RD_BDT_LSB+DT_EPLAST, 32'hCAFE_FADE,4);
dma_set_header( bar_table, // Pointer to the BAR sizing and
setup_bar, // BAR to be used for setting up
NUMBER_OF_DESCRIPTORS, // number of descriptor
RD_DIRECTION, // Direction read
use_global_msi, // global MSI control
use_global_eplast, // global eplast control
RD_BDT_MSB, // RC upper 32 bits of bdt
RD_BDT_LSB, // RC lower 32 bits of bdt
msi_number_int,
msi_traffic_class_int,
multi_message_enable_int,
1); // stop_loop
track_rclast_loop[15:0] = (use_global_eplast==1'b1) ? RCLast : EPLAST_DONE_VALUE;
track_rclast_loop[31:16] = 1 ;
unused_result = ebfm_display(EBFM_MSG_INFO, " Flushing DMA loop");
rcmem_poll(RD_BDT_LSB+DT_EPLAST, track_rclast_loop,32'h0001ffff);
end
end
join // polling
ebfm_barwr_imm(bar_table, setup_bar, 16, 32'h0000_FFFF, 4, 0);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "Completed DMA Read");
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:dma_wr_test
//
// Run the chained DMA write
//
// Input argument
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
// 4 Write then Read
// use_global_msi : When set, use msi
// use_global_eplast: When set, poll for ep last
//
task dma_wr_test(
input integer bar_table,
input integer setup_bar,
input integer use_global_msi,
input integer use_global_eplast);
localparam integer MSI_ADDRESS = SCR_MEM-16;
localparam integer MSI_DATA = 16'hb0fe;
reg unused_result ;
integer RCLast;
reg [4:0] msi_number ;
reg [2:0] msi_traffic_class ;
reg [2:0] multi_message_enable;
integer msi_address ;
integer msi_expected_dmawr ;
integer msi_expected_dmard ;
integer msi_received ;
integer msi_count ;
integer max_count ;
integer i ;
reg [31:0] track_rclast_loop;
reg use_msi;
reg use_eplast;
reg [4:0] msi_number_int ;
reg [2:0] msi_traffic_class_int ;
reg [2:0] multi_message_enable_int;
begin
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:dma_wr_test");
unused_result = ebfm_display_verb(EBFM_MSG_INFO," DMA: Write");
// write 'write descriptor table in the RC Memory
dma_set_wr_desc_data(bar_table, setup_bar);
use_msi = use_global_msi | (NUM_MSI_EXPECTED > 0);
use_eplast = use_global_eplast | (NUM_EPLAST_EXPECTED > 0);
// Set MSI for DMA Writew
if (use_msi==1)
dma_set_msi( bar_table, // Pointer to the BAR sizing and
setup_bar, // BAR to be used for setting up
1, // bus_num
1, // dev_num
0, // fnc_num
WR_DIRECTION, // Direction
MSI_ADDRESS,// MSI RC memeory address
MSI_DATA, // MSI Cfg data value
msi_number, // msi_number
msi_traffic_class, //msi traffic class
multi_message_enable,// number of msi
msi_expected_dmawr // expexted MSI data value
);
msi_number_int = (use_msi == 1'b1) ? msi_number : 5'h0;
msi_traffic_class_int = (use_msi == 1'b1) ? msi_number : 3'h0;
multi_message_enable_int = (use_msi == 1'b1) ? msi_number : 3'h0;
// Write Descriptor header in EP memory PRG
dma_set_header( bar_table, // Pointer to the BAR sizing and
setup_bar, // BAR to be used for setting up
NUMBER_OF_DESCRIPTORS, // number of descriptor
WR_DIRECTION, // Direction = Write
use_global_msi, // global MSI control
use_global_eplast, // global eplast control
WR_BDT_MSB, // RC upper 32 bits of bdt
WR_BDT_LSB, // RC lower 32 bits of bdt
msi_number_int,
msi_traffic_class_int,
multi_message_enable_int,
0);
//Program RP RCLast
RCLast = NUMBER_OF_DESCRIPTORS-1;
// Start write DMA
dma_set_rclast(bar_table, setup_bar, WR_DIRECTION, RCLast);
fork // polling
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
// Monitor MSI - Polling MSI
if (use_msi==1)
if (use_global_msi==1)
msi_poll(NUMBER_OF_DESCRIPTORS,MSI_ADDRESS, msi_expected_dmawr,0,1,0);
else
msi_poll(NUM_MSI_EXPECTED,MSI_ADDRESS, msi_expected_dmawr,0,1,0);
if (use_eplast==1) begin
if (DMA_CONTINOUS_LOOP==0)
rcmem_poll(WR_BDT_LSB+DT_EPLAST, EPLAST_DONE_VALUE,32'h0000ffff);
else begin
for (i=0;i<DMA_CONTINOUS_LOOP;i=i+1) begin
unused_result = ebfm_display(EBFM_MSG_INFO, { " Running DMA loop ", dimage4(i), " : "});
shmem_write(WR_BDT_LSB+DT_EPLAST, 32'hCAFE_FADE,4);
rcmem_poll(WR_BDT_LSB+DT_EPLAST, EPLAST_DONE_VALUE,32'h0000ffff);
end
shmem_write(WR_BDT_LSB+DT_EPLAST, 32'hCAFE_FADE,4);
dma_set_header( bar_table, // Pointer to the BAR sizing and
setup_bar, // BAR to be used for setting up
NUMBER_OF_DESCRIPTORS, // number of descriptor
WR_DIRECTION, // Direction = Write
use_global_msi, // global MSI control
use_global_eplast, // global eplast control
WR_BDT_MSB, // RC upper 32 bits of bdt
WR_BDT_LSB, // RC lower 32 bits of bdt
msi_number_int,
msi_traffic_class_int,
multi_message_enable_int,
1);
track_rclast_loop[15:0] = (use_global_eplast==1'b1) ? RCLast : EPLAST_DONE_VALUE;
track_rclast_loop[31:16] = 1 ;
unused_result = ebfm_display(EBFM_MSG_INFO, " Flushing DMA loop");
rcmem_poll(WR_BDT_LSB+DT_EPLAST, track_rclast_loop,32'h0001ffff);
end
end
join // polling
ebfm_barwr_imm(bar_table, setup_bar, 0, 32'h0000_FFFF, 4, 0);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "Completed DMA Write");
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:chained_dma_test
//
// task to run the chained DMA read/Write
//
// Input argument
// bar_table : Pointer to the BAR sizing and
// setup_bar : BAR to be used for setting up
// direction : 0 read,
// 1 write,
// 2 read and write simulataneous
// 3 Read then Write
// 4 Write then Read
//
task chained_dma_test(
input integer bar_table ,
input integer setup_bar ,
input integer direction ,
input integer use_global_msi ,
input integer use_global_eplast
);
reg unused_result ;
begin
unused_result = ebfm_display(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display(EBFM_MSG_INFO, "TASK:chained_dma_test");
case (direction)
0: begin
unused_result = ebfm_display(EBFM_MSG_INFO," DMA: Read");
dma_rd_test(bar_table, setup_bar, use_global_msi, use_global_eplast);
end
1: begin
unused_result = ebfm_display(EBFM_MSG_INFO," DMA: Write");
dma_wr_test(bar_table, setup_bar, use_global_msi, use_global_eplast);
end
default: unused_result = ebfm_display(EBFM_MSG_INFO," Incorrect direction");
endcase
end
endtask
// purpose: Examine the DUT's BAR setup and pick a reasonable BAR to use
task find_mem_bar;
input bar_table;
integer bar_table;
input[5:0] allowed_bars;
input min_log2_size;
integer min_log2_size;
output sel_bar;
integer sel_bar;
integer cur_bar;
reg[31:0] bar32;
integer log2_size;
reg is_mem;
reg is_pref;
reg is_64b;
begin
// find_mem_bar
cur_bar = 0;
begin : sel_bar_loop
while (cur_bar < 6)
begin
ebfm_cfg_decode_bar(bar_table, cur_bar,
log2_size, is_mem, is_pref, is_64b);
if ((is_mem == 1'b1) &
(log2_size >= min_log2_size) &
((allowed_bars[cur_bar]) == 1'b1))
begin
sel_bar = cur_bar;
disable sel_bar_loop ;
end
if (is_64b == 1'b1)
begin
cur_bar = cur_bar + 2;
end
else
begin
cur_bar = cur_bar + 1;
end
end
sel_bar = 7 ; // Invalid BAR if we get this far...
end
end
endtask
// memory content checking - check data transferred for specified descriptor
task check_dma_data;
reg unused_result ;
integer i;
reg [31:0] dmaread_data;
reg [31:0] dmawrite_data;
integer dmaread_addr;
integer dmawrite_addr;
input [31:0] wr_desc_length; // WR_DESC2_LENGTH
input [31:0] rd_desc_length; // RD_DESC2_LENGTH
input [31:0] wr_desc_rcaddr_lsb; // WR_DESC2_RCADDR_LSB
input [31:0] rd_desc_rcaddr_lsb; // RD_DESC2_RCADDR_LSB
begin
if ((wr_desc_length == rd_desc_length ) || (wr_desc_length < rd_desc_length )) begin
unused_result = ebfm_display(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display(EBFM_MSG_INFO, "TASK:check_dma_data ");
for (i=0;i<wr_desc_length;i=i+1) begin
dmaread_addr = rd_desc_rcaddr_lsb+4*i;
dmaread_data = shmem_read(dmaread_addr,4);
dmawrite_addr = wr_desc_rcaddr_lsb+4*i;
dmawrite_data = shmem_read(dmawrite_addr,4);
if (dmaread_data != dmawrite_data) begin
if (DISPLAY_ALL>0) begin
unused_result = ebfm_display_verb(EBFM_MSG_INFO, " DMA read BFM memory");
unused_result = shmem_display (rd_desc_rcaddr_lsb, rd_desc_length*4,4, rd_desc_rcaddr_lsb+(rd_desc_length*4), EBFM_MSG_INFO);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, " DMA write BFM memory");
unused_result = shmem_display (wr_desc_rcaddr_lsb,wr_desc_length*4,4, wr_desc_rcaddr_lsb+(wr_desc_length*4),EBFM_MSG_INFO);
end
unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL,
{" DMA Read : Address (" ,himage8(dmaread_addr),
") Data (" ,himage8(dmaread_data),
") -------> DMA Write : Address (",himage8(dmawrite_addr),
") Data (" ,himage8(dmawrite_data),")"});
end
end
unused_result = ebfm_display(EBFM_MSG_INFO, {" Passed : ",dimage4(wr_desc_length),
" identical dwords."});
end
end
endtask
task scr_memory_compare(
input integer byte_length, // downstream wr/rd length in byte
input integer scr_memorya, //
input integer scr_memoryb); //
integer i;
reg [7:0] bytea;
reg [7:0] byteb;
reg [31:0] addra;
reg [31:0] addrb;
reg unused_result ;
begin
//unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:scr_memory_compare");
addra = scr_memorya;
addrb = scr_memoryb;
for (i=0;i<byte_length;i=i+1) begin
bytea=shmem_read(addra,1);
byteb=shmem_read(addrb,1);
addra=addra+1;
addrb=addrb+1;
if (bytea!=byteb) begin
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "Content of the RC memory A");
unused_result =shmem_display(scr_memorya,byte_length,4,scr_memorya+byte_length,EBFM_MSG_INFO);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "Content of the RC memory B");
unused_result =shmem_display(scr_memoryb,byte_length,4,scr_memoryb+byte_length,EBFM_MSG_INFO);
unused_result = ebfm_display(EBFM_MSG_INFO,
{" A: 0x", himage8(addra), ": ",himage8(bytea)});
unused_result = ebfm_display(EBFM_MSG_INFO,
{" B: 0x", himage8(addrb), ": ",himage8(byteb)});
unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL, {"Different memory content for ",
dimage4(byte_length), " bytes test"});
end
end
unused_result = ebfm_display_verb(EBFM_MSG_INFO, {"Passed: ",dimage4(byte_length),
" same bytes in BFM mem addr 0x", himage8(scr_memorya),
" and 0x", himage8(scr_memoryb)});
end
endtask
task downstream_loop(
input integer bar_table, // Pointer to the BAR sizing and
input integer setup_bar, // Pointer to the BAR sizing and
input integer loop, // Number of Write/read iteration
input integer byte_length, // downstream wr/rd length in byte
input integer epmem_address, // Downstream EP memory address in byte
input [63:0] start_val); // Starting write data value
reg unused_result ;
reg [63:0] Istart_val;
reg [31:0] Iepmem_address;
integer i;
reg [31:0] Ibyte_length;
reg [31:0] cfg_reg ;
reg [31:0] cfg_maxpload_byte ;
reg [7:0] avalon_waddr ;
reg [31:0] avalon_waddr_qw_max;
reg [31:0] avalon_waddr_qw_min;
reg [31:0] cfg_dw1 ;
begin
unused_result = ebfm_display_verb(EBFM_MSG_INFO, `STR_SEP);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "TASK:downstream_loop ");
cfg_maxpload_byte = 0;
// Retrieve Device cfg from RC Slave
// Set EP MWr mode
cfg_reg = 32'h0;
case (cfg_reg[7:5])
3'b000 :cfg_maxpload_byte[12:7 ] = 6'b000001;// 128B
3'b001 :cfg_maxpload_byte[12:7 ] = 6'b000010;// 256B
3'b010 :cfg_maxpload_byte[12:7 ] = 6'b000100;// 512B
3'b011 :cfg_maxpload_byte[12:7 ] = 6'b001000;// 1024B
3'b100 :cfg_maxpload_byte[12:7 ] = 6'b010000;// 2048B
default:cfg_maxpload_byte[12:7 ] = 6'b100000;// 4096B
endcase
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "downstream_write");
downstream_write(bar_table, 0, 32'hC60, 0, 4);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "downstream_write");
downstream_write(bar_table, 0, 32'hC1C, 1, 4);
unused_result = ebfm_display_verb(EBFM_MSG_INFO, "downstream_read");
downstream_read (bar_table, 0, 32'h8, 4);
unused_result = ebfm_log_stop_sim(1);
// Ibyte_length = ((byte_length>cfg_maxpload_byte)||
// (byte_length<4))?4:byte_length;
// Istart_val = start_val;
// for (i=0;i<loop;i=i+1) begin
// downstream_write( bar_table,
// setup_bar,
// epmem_address,
// Istart_val,
// Ibyte_length);
// unused_result=ebfm_display(EBFM_MSG_INFO, {"read bar 0x", himage8(setup_bar), ",0x", himage8(epmem_address)});
// downstream_read ( bar_table,
// setup_bar,
// epmem_address+4,
// Ibyte_length);
// scr_memory_compare(Ibyte_length,
// SCR_MEM_DOWNSTREAM_WR,
// SCR_MEM_DOWNSTREAM_RD);
// Istart_val = Istart_val+cfg_maxpload_byte;
// Ibyte_length = ((Ibyte_length>cfg_maxpload_byte-4)||
// (Ibyte_length<4))?4:Ibyte_length+4;
// end
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:downstream_write
// Prior to run DMA test, this task clears the performance counters
//
task downstream_write(
input integer bar_table, // Pointer to the BAR sizing and
input integer setup_bar, // Pointer to the BAR sizing and
input integer address, // Downstream EP memeory address in byte
input [63:0] data,
input integer byte_length); // BAR to be used for setting up
reg unused_result ;
begin
// Write a data
shmem_fill(SCR_MEM_DOWNSTREAM_WR,SHMEM_FILL_QWORD_INC,byte_length,data);
ebfm_barwr(bar_table,setup_bar,address,SCR_MEM_DOWNSTREAM_WR,byte_length,0);
end
endtask
/////////////////////////////////////////////////////////////////////////
//
// TASK:downstream_read
// Prior to run DMA test, this task clears the performance counters
//
task downstream_read(
input integer bar_table, // Pointer to the BAR sizing and
input integer setup_bar, // Pointer to the BAR sizing and
input integer address, // Downstream EP memeory address in byte
input integer byte_length); // BAR to be used for setting up
reg unused_result ;
begin
// read a data
shmem_fill(SCR_MEM_DOWNSTREAM_RD,SHMEM_FILL_QWORD_INC,byte_length,64'hFADE_FADE_FADE_FADE);
ebfm_barrd_wait(bar_table,setup_bar,address,SCR_MEM_DOWNSTREAM_RD,byte_length,0);
end
endtask
///////////////////////////////////////////////////////////////////////////////
//
//
// Main Program
//
// Start of the test bench driver altpcietb_bfm_driver
//
reg activity_toggle;
reg timer_toggle ;
time time_stamp ;
localparam TIMEOUT = 2000000000;
reg [31:0] err_status;
initial
begin
time_stamp = $time ;
activity_toggle = 1'b0;
timer_toggle = 1'b0;
end
// behavioral
always
begin : main
// If you want to relocate the bar_table, modify the BAR_TABLE_POINTER in altpcietb_bfm_shmem.
// Directly modifying the bar_table at this location may disable overwrite protection for the bar_table
// If the bar_table is overwritten incorrectly, this will break the testbench functionality.
parameter bar_table = BAR_TABLE_POINTER; // Default BAR_TABLE_SIZE is 64 bytes
integer tgt_bar;
integer dma_bar, rc_slave_bar;
reg addr_map_4GB_limit;
reg unused_result ;
reg [15:0] msi_control_register;
// This constant defines where we save the sizes and programmed addresses
// of the Endpoint Device Under Test BARs
// tgt_bar indicates which bar to use for testing the target memory of the
// reference design.
// Setup the Root Port and Endpoint Configuration Spaces
addr_map_4GB_limit = 1'b1;
unused_result = ebfm_display_verb(EBFM_MSG_WARNING,
"----> Starting ebfm_cfg_rp_ep task 0");
ebfm_cfg_rp_ep(
bar_table, // BAR Size/Address info for Endpoint
1, // Bus Number for Endpoint Under Test
1, // Device Number for Endpoint Under Test
512, // Maximum Read Request Size for Root Port
1, // Display EP Config Space after setup
addr_map_4GB_limit // Limit the BAR assignments to 4GB address map
);
activity_toggle <= ~activity_toggle ;
// Find a memory BAR to use to setup the DMA channel
// The reference design implements the DMA channel registers on BAR 2 or 3
// BAR as to be at least 256 B
//find_mem_bar(bar_table, 6'b001100, 8, dma_bar);
///////////////////////////////////////////
// Test the chained DMA example design
// if ((dma_bar < 6) && (USE_CDMA>0)) begin
// chained_dma_test(bar_table, dma_bar,0,0,0); // Read DMA
// time_stamp = $time ;
// chained_dma_test(bar_table, dma_bar,1,0,0); // Write DMA
// // check the data transferred by the last descriptor
// check_dma_data( WR_DESC2_LENGTH,
// RD_DESC2_LENGTH,
// WR_DESC2_RCADDR_LSB,
// RD_DESC2_RCADDR_LSB);
//
//
// end
// else if (USE_CDMA>0)
// unused_result = ebfm_display_verb(EBFM_MSG_WARNING,
// "Unable to find a 256B BAR to setup the chaining DMA DUT; skipping test.");
// // Stop the simulator and indicate successful completion
//////////////////////////////////////////////////////
// Test downstream access to the Chaining DMA Memory
downstream_loop(
bar_table, // Pointer to the BAR sizing and
0, // Pointer to the BAR sizing and
4, // Number of Write/read iteration
4, // downstream wr/rd length in byte
4, // Downstream EP memory address in byte
// (need to be qword aligned)
64'hBABA_0000_BEBE_0000);// Starting write data value
//find_mem_bar(bar_table, 6'b110011, 8, rc_slave_bar);
// if ((rc_slave_bar<6)&&(USE_TARGET>0)) begin
// downstream_loop(
// bar_table, // Pointer to the BAR sizing and
// rc_slave_bar, // Pointer to the BAR sizing and
// RCSLAVE_MAXLEN, // Number of Write/read iteration
// 4, // downstream wr/rd length in byte
// 0, // Downstream EP memory address in byte
// // (need to be qword aligned)
// 64'hBABA_0000_BEBE_0000);// Starting write data value
// end
// else if (USE_TARGET>0)
// unused_result = ebfm_display_verb(EBFM_MSG_WARNING,
// "Unable to find a 256B BAR to setup the RC Slave module ; skipping test.");
// check Chaining DMA Error Status register
ebfm_barrd_wait(bar_table,dma_bar,48,SCR_MEMSLAVE,4,0);
err_status = shmem_read (SCR_MEMSLAVE, 4);
if (err_status != 32'h0) begin
unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL, {"Chaining DMA Error Status Reg - ECRC errors detected: ", himage8(err_status)});
end
else begin
unused_result = ebfm_display(EBFM_MSG_INFO, "Chaining DMA Error Status Reg - PASSED ");
end
unused_result = ebfm_log_stop_sim(1);
forever #100000;
end
always
begin
#(TIMEOUT)
timer_toggle <= ! timer_toggle ;
end
// purpose: this is a watchdog timer, if it sees no activity on the activity
// toggle signal for 200 us it ends the simulation
always @(activity_toggle or timer_toggle)
begin : watchdog
reg unused_result ;
if ( ($time - time_stamp) >= TIMEOUT)
begin
unused_result = ebfm_display(EBFM_MSG_ERROR_FATAL, "Simulation stopped due to inactivity!");
end
time_stamp <= $time ;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A32O_PP_SYMBOL_V
`define SKY130_FD_SC_LP__A32O_PP_SYMBOL_V
/**
* a32o: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input OR.
*
* X = ((A1 & A2 & A3) | (B1 & B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__a32o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input A3 ,
input B1 ,
input B2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A32O_PP_SYMBOL_V
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 6
(* X_CORE_INFO = "axi_crossbar_v2_1_axi_crossbar,Vivado 2015.1" *)
(* CHECK_LICENSE_TYPE = "week1_xbar_0,axi_crossbar_v2_1_axi_crossbar,{}" *)
(* CORE_GENERATION_INFO = "week1_xbar_0,axi_crossbar_v2_1_axi_crossbar,{x_ipProduct=Vivado 2015.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_crossbar,x_ipVersion=2.1,x_ipCoreRevision=6,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_NUM_SLAVE_SLOTS=1,C_NUM_MASTER_SLOTS=7,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_PROTOCOL=2,C_NUM_ADDR_RANGES=1,C_M_AXI_BASE_ADDR=0x0000000043c600000000000043c500000000000043c400000000000043c300000000000043c200000000000043c100000000000043c00000,C_M_AXI_ADDR_WIDTH=0x00000010000000100000001000000010000000100000001000000010,C_S_AXI_BASE_ID=0x00000000,C_S_AXI_THREAD_ID_WIDTH=0x00000000,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_M_AXI_WRITE_CONNECTIVITY=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_CONNECTIVITY=0x00000001000000010000000100000001000000010000000100000001,C_R_REGISTER=1,C_S_AXI_SINGLE_THREAD=0x00000001,C_S_AXI_WRITE_ACCEPTANCE=0x00000001,C_S_AXI_READ_ACCEPTANCE=0x00000001,C_M_AXI_WRITE_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_M_AXI_READ_ISSUING=0x00000001000000010000000100000001000000010000000100000001,C_S_AXI_ARB_PRIORITY=0x00000000,C_M_AXI_SECURE=0x00000000000000000000000000000000000000000000000000000000,C_CONNECTIVITY_MODE=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module week1_xbar_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *)
input wire [0 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *)
output wire [0 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *)
input wire [0 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *)
output wire [0 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *)
output wire [0 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *)
input wire [0 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *)
input wire [0 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *)
output wire [0 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *)
output wire [0 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *)
input wire [0 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI AWADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI AWADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI AWADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI AWADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI AWADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI AWPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI AWPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI AWPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI AWPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI AWPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI AWREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI AWREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI AWREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI AWREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI AWREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI WDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI WDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI WDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI WDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI WDATA [31:0] [223:192]" *)
output wire [223 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4], xilinx.com:interface:aximm:1.0 M02_AXI WSTRB [3:0] [11:8], xilinx.com:interface:aximm:1.0 M03_AXI WSTRB [3:0] [15:12], xilinx.com:interface:aximm:1.0 M04_AXI WSTRB [3:0] [19:16], xilinx.com:interface:aximm:1.0 M05_AXI WSTRB [3:0] [23:20], xilinx.com:interface:aximm:1.0 M06_AXI WSTRB [3:0] [27:24]" *)
output wire [27 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI WREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI WREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI WREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI WREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI WREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI BRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI BRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI BRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI BRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI BRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI BREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI BREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI BREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI BREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI BREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI ARADDR [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI ARADDR [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI ARADDR [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI ARADDR [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI ARADDR [31:0] [223:192]" *)
output wire [223 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3], xilinx.com:interface:aximm:1.0 M02_AXI ARPROT [2:0] [8:6], xilinx.com:interface:aximm:1.0 M03_AXI ARPROT [2:0] [11:9], xilinx.com:interface:aximm:1.0 M04_AXI ARPROT [2:0] [14:12], xilinx.com:interface:aximm:1.0 M05_AXI ARPROT [2:0] [17:15], xilinx.com:interface:aximm:1.0 M06_AXI ARPROT [2:0] [20:18]" *)
output wire [20 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARVALID [0:0] [6:6]" *)
output wire [6 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI ARREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI ARREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI ARREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI ARREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI ARREADY [0:0] [6:6]" *)
input wire [6 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32], xilinx.com:interface:aximm:1.0 M02_AXI RDATA [31:0] [95:64], xilinx.com:interface:aximm:1.0 M03_AXI RDATA [31:0] [127:96], xilinx.com:interface:aximm:1.0 M04_AXI RDATA [31:0] [159:128], xilinx.com:interface:aximm:1.0 M05_AXI RDATA [31:0] [191:160], xilinx.com:interface:aximm:1.0 M06_AXI RDATA [31:0] [223:192]" *)
input wire [223 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2], xilinx.com:interface:aximm:1.0 M02_AXI RRESP [1:0] [5:4], xilinx.com:interface:aximm:1.0 M03_AXI RRESP [1:0] [7:6], xilinx.com:interface:aximm:1.0 M04_AXI RRESP [1:0] [9:8], xilinx.com:interface:aximm:1.0 M05_AXI RRESP [1:0] [11:10], xilinx.com:interface:aximm:1.0 M06_AXI RRESP [1:0] [13:12]" *)
input wire [13 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RVALID [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RVALID [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RVALID [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RVALID [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RVALID [0:0] [6:6]" *)
input wire [6 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1], xilinx.com:interface:aximm:1.0 M02_AXI RREADY [0:0] [2:2], xilinx.com:interface:aximm:1.0 M03_AXI RREADY [0:0] [3:3], xilinx.com:interface:aximm:1.0 M04_AXI RREADY [0:0] [4:4], xilinx.com:interface:aximm:1.0 M05_AXI RREADY [0:0] [5:5], xilinx.com:interface:aximm:1.0 M06_AXI RREADY [0:0] [6:6]" *)
output wire [6 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(1),
.C_NUM_MASTER_SLOTS(7),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_PROTOCOL(2),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(448'H0000000043c600000000000043c500000000000043c400000000000043c300000000000043c200000000000043c100000000000043c00000),
.C_M_AXI_ADDR_WIDTH(224'H00000010000000100000001000000010000000100000001000000010),
.C_S_AXI_BASE_ID(32'H00000000),
.C_S_AXI_THREAD_ID_WIDTH(32'H00000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_CONNECTIVITY(224'H00000001000000010000000100000001000000010000000100000001),
.C_R_REGISTER(1),
.C_S_AXI_SINGLE_THREAD(32'H00000001),
.C_S_AXI_WRITE_ACCEPTANCE(32'H00000001),
.C_S_AXI_READ_ACCEPTANCE(32'H00000001),
.C_M_AXI_WRITE_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_M_AXI_READ_ISSUING(224'H00000001000000010000000100000001000000010000000100000001),
.C_S_AXI_ARB_PRIORITY(32'H00000000),
.C_M_AXI_SECURE(224'H00000000000000000000000000000000000000000000000000000000),
.C_CONNECTIVITY_MODE(0)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(7'H00),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(7'H00),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(7'H00),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(7'H7F),
.m_axi_ruser(7'H00),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) SILAB , Physics Institute of Bonn University
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`include "utils/bus_to_ip.v"
`include "gpio/gpio.v"
`include "spi/spi.v"
`include "spi/spi_core.v"
`include "spi/blk_mem_gen_8_to_1_2k.v"
`include "pulse_gen/pulse_gen.v"
`include "pulse_gen/pulse_gen_core.v"
`include "bram_fifo/bram_fifo_core.v"
`include "bram_fifo/bram_fifo.v"
`include "fast_spi_rx/fast_spi_rx.v"
`include "fast_spi_rx/fast_spi_rx_core.v"
`include "utils/cdc_syncfifo.v"
`include "utils/generic_fifo.v"
`include "utils/cdc_pulse_sync.v"
`include "utils/CG_MOD_pos.v"
`include "utils/clock_divider.v"
`include "utils/RAMB16_S1_S9_sim.v"
module tb (
input wire BUS_CLK,
input wire BUS_RST,
input wire [31:0] BUS_ADD,
inout wire [31:0] BUS_DATA,
input wire BUS_RD,
input wire BUS_WR,
output wire BUS_BYTE_ACCESS
);
// MODULE ADREESSES //
localparam GPIO_BASEADDR = 32'h0000;
localparam GPIO_HIGHADDR = 32'h1000-1;
localparam SPI_BASEADDR = 32'h1000; //0x1000
localparam SPI_HIGHADDR = 32'h2000-1; //0x300f
localparam FAST_SR_AQ_BASEADDR = 32'h2000;
localparam FAST_SR_AQ_HIGHADDR = 32'h3000-1;
localparam PULSE_BASEADDR = 32'h3000;
localparam PULSE_HIGHADDR = PULSE_BASEADDR + 15;
localparam FIFO_BASEADDR = 32'h8000;
localparam FIFO_HIGHADDR = 32'h9000-1;
localparam FIFO_BASEADDR_DATA = 32'h8000_0000;
localparam FIFO_HIGHADDR_DATA = 32'h9000_0000;
localparam ABUSWIDTH = 32;
assign BUS_BYTE_ACCESS = BUS_ADD < 32'h8000_0000 ? 1'b1 : 1'b0;
// MODULES //
gpio
#(
.BASEADDR(GPIO_BASEADDR),
.HIGHADDR(GPIO_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.IO_WIDTH(8),
.IO_DIRECTION(8'hff)
) i_gpio
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.IO()
);
wire SPI_CLK;
wire EX_START_PULSE;
pulse_gen
#(
.BASEADDR(PULSE_BASEADDR),
.HIGHADDR(PULSE_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pulse_gen
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.PULSE_CLK(SPI_CLK),
.EXT_START(1'b0),
.PULSE(EX_START_PULSE)
);
clock_divider #(
.DIVISOR(4)
) i_clock_divisor_spi (
.CLK(BUS_CLK),
.RESET(1'b0),
.CE(),
.CLOCK(SPI_CLK)
);
wire SCLK, SDI, SDO, SEN, SLD;
spi
#(
.BASEADDR(SPI_BASEADDR),
.HIGHADDR(SPI_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH),
.MEM_BYTES(16)
) i_spi
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SPI_CLK(SPI_CLK),
.EXT_START(EX_START_PULSE),
.SCLK(SCLK),
.SDI(SDI),
.SDO(SDO),
.SEN(SEN),
.SLD(SLD)
);
assign SDO = SDI;
wire FIFO_READ_SPI_RX;
wire FIFO_EMPTY_SPI_RX;
wire [31:0] FIFO_DATA_SPI_RX;
fast_spi_rx
#(
.BASEADDR(FAST_SR_AQ_BASEADDR),
.HIGHADDR(FAST_SR_AQ_HIGHADDR),
.ABUSWIDTH(ABUSWIDTH)
) i_pixel_sr_fast_rx
(
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA[7:0]),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.SCLK(~SPI_CLK),
.SDI(SDI),
.SEN(SEN),
.FIFO_READ(FIFO_READ_SPI_RX),
.FIFO_EMPTY(FIFO_EMPTY_SPI_RX),
.FIFO_DATA(FIFO_DATA_SPI_RX)
);
wire FIFO_READ, FIFO_EMPTY;
wire [31:0] FIFO_DATA;
assign FIFO_DATA = FIFO_DATA_SPI_RX;
assign FIFO_EMPTY = FIFO_EMPTY_SPI_RX;
assign FIFO_READ_SPI_RX = FIFO_READ;
bram_fifo
#(
.BASEADDR(FIFO_BASEADDR),
.HIGHADDR(FIFO_HIGHADDR),
.BASEADDR_DATA(FIFO_BASEADDR_DATA),
.HIGHADDR_DATA(FIFO_HIGHADDR_DATA),
.ABUSWIDTH(ABUSWIDTH)
) i_out_fifo (
.BUS_CLK(BUS_CLK),
.BUS_RST(BUS_RST),
.BUS_ADD(BUS_ADD),
.BUS_DATA(BUS_DATA),
.BUS_RD(BUS_RD),
.BUS_WR(BUS_WR),
.FIFO_READ_NEXT_OUT(FIFO_READ),
.FIFO_EMPTY_IN(FIFO_EMPTY),
.FIFO_DATA(FIFO_DATA),
.FIFO_NOT_EMPTY(),
.FIFO_FULL(),
.FIFO_NEAR_FULL(),
.FIFO_READ_ERROR()
);
initial begin
$dumpfile("spi.vcd");
$dumpvars(0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BAI_1_V
`define SKY130_FD_SC_HD__O21BAI_1_V
/**
* o21bai: 2-input OR into first input of 2-input NAND, 2nd iput
* inverted.
*
* Y = !((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21bai with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o21bai.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__o21bai_1 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__o21bai base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BAI_1_V
|
// system.v
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:03
`timescale 1 ps / 1 ps
module system (
input wire clk_50_clk, // clk_50.clk
input wire reset_50_reset_n, // reset_50.reset_n
output wire kernel_clk_clk, // kernel_clk.clk
output wire [14:0] memory_mem_a, // memory.mem_a
output wire [2:0] memory_mem_ba, // .mem_ba
output wire memory_mem_ck, // .mem_ck
output wire memory_mem_ck_n, // .mem_ck_n
output wire memory_mem_cke, // .mem_cke
output wire memory_mem_cs_n, // .mem_cs_n
output wire memory_mem_ras_n, // .mem_ras_n
output wire memory_mem_cas_n, // .mem_cas_n
output wire memory_mem_we_n, // .mem_we_n
output wire memory_mem_reset_n, // .mem_reset_n
inout wire [31:0] memory_mem_dq, // .mem_dq
inout wire [3:0] memory_mem_dqs, // .mem_dqs
inout wire [3:0] memory_mem_dqs_n, // .mem_dqs_n
output wire memory_mem_odt, // .mem_odt
output wire [3:0] memory_mem_dm, // .mem_dm
input wire memory_oct_rzqin, // .oct_rzqin
output wire peripheral_hps_io_emac1_inst_TX_CLK, // peripheral.hps_io_emac1_inst_TX_CLK
output wire peripheral_hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire peripheral_hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire peripheral_hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire peripheral_hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire peripheral_hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire peripheral_hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire peripheral_hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire peripheral_hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire peripheral_hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire peripheral_hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire peripheral_hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire peripheral_hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire peripheral_hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire peripheral_hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire peripheral_hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire peripheral_hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire peripheral_hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire peripheral_hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire peripheral_hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
input wire peripheral_hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire peripheral_hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire peripheral_hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire peripheral_hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire peripheral_hps_io_gpio_inst_GPIO53 // .hps_io_gpio_inst_GPIO53
);
wire acl_iface_kernel_clk_clk; // acl_iface:kernel_clk_clk -> [Gray_Processing_system:clock, avs_graying_cra_cra_ring:clk, cra_root:clk, irq_mapper:clk, mm_interconnect_0:acl_iface_kernel_clk_clk, mm_interconnect_1:acl_iface_kernel_clk_clk]
wire acl_iface_kernel_clk2x_clk; // acl_iface:kernel_clk2x_clk -> Gray_Processing_system:clock2x
wire acl_iface_kernel_reset_reset; // acl_iface:kernel_reset_reset_n -> [Gray_Processing_system:resetn, avs_graying_cra_cra_ring:rst_n, cra_root:rst_n, irq_mapper:reset, mm_interconnect_0:Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset_reset, mm_interconnect_1:cra_root_reset_reset_bridge_in_reset_reset]
wire avs_graying_cra_cra_ring_ring_in_waitrequest; // avs_graying_cra_cra_ring:ri_waitrequest -> cra_root:ro_waitrequest
wire [7:0] cra_root_ring_out_byteena; // cra_root:ro_byteena -> avs_graying_cra_cra_ring:ri_byteena
wire [63:0] cra_root_ring_out_data; // cra_root:ro_data -> avs_graying_cra_cra_ring:ri_data
wire cra_root_ring_out_write; // cra_root:ro_write -> avs_graying_cra_cra_ring:ri_write
wire cra_root_ring_out_read; // cra_root:ro_read -> avs_graying_cra_cra_ring:ri_read
wire [3:0] cra_root_ring_out_addr; // cra_root:ro_addr -> avs_graying_cra_cra_ring:ri_addr
wire cra_root_ring_out_datavalid; // cra_root:ro_datavalid -> avs_graying_cra_cra_ring:ri_datavalid
wire avs_graying_cra_cra_ring_cra_master_waitrequest; // Gray_Processing_system:avs_graying_cra_waitrequest -> avs_graying_cra_cra_ring:avm_waitrequest
wire [63:0] avs_graying_cra_cra_ring_cra_master_writedata; // avs_graying_cra_cra_ring:avm_writedata -> Gray_Processing_system:avs_graying_cra_writedata
wire [3:0] avs_graying_cra_cra_ring_cra_master_address; // avs_graying_cra_cra_ring:avm_addr -> Gray_Processing_system:avs_graying_cra_address
wire avs_graying_cra_cra_ring_cra_master_write; // avs_graying_cra_cra_ring:avm_write -> Gray_Processing_system:avs_graying_cra_write
wire avs_graying_cra_cra_ring_cra_master_read; // avs_graying_cra_cra_ring:avm_read -> Gray_Processing_system:avs_graying_cra_read
wire [63:0] avs_graying_cra_cra_ring_cra_master_readdata; // Gray_Processing_system:avs_graying_cra_readdata -> avs_graying_cra_cra_ring:avm_readdata
wire avs_graying_cra_cra_ring_cra_master_readdatavalid; // Gray_Processing_system:avs_graying_cra_readdatavalid -> avs_graying_cra_cra_ring:avm_readdatavalid
wire [7:0] avs_graying_cra_cra_ring_cra_master_byteenable; // avs_graying_cra_cra_ring:avm_byteena -> Gray_Processing_system:avs_graying_cra_byteenable
wire cra_root_ring_in_waitrequest; // cra_root:ri_waitrequest -> avs_graying_cra_cra_ring:ro_waitrequest
wire [7:0] avs_graying_cra_cra_ring_ring_out_byteena; // avs_graying_cra_cra_ring:ro_byteena -> cra_root:ri_byteena
wire [63:0] avs_graying_cra_cra_ring_ring_out_data; // avs_graying_cra_cra_ring:ro_data -> cra_root:ri_data
wire avs_graying_cra_cra_ring_ring_out_write; // avs_graying_cra_cra_ring:ro_write -> cra_root:ri_write
wire avs_graying_cra_cra_ring_ring_out_read; // avs_graying_cra_cra_ring:ro_read -> cra_root:ri_read
wire [3:0] avs_graying_cra_cra_ring_ring_out_addr; // avs_graying_cra_cra_ring:ro_addr -> cra_root:ri_addr
wire avs_graying_cra_cra_ring_ring_out_datavalid; // avs_graying_cra_cra_ring:ro_datavalid -> cra_root:ri_datavalid
wire gray_processing_system_avm_memgmem0_port_0_0_rw_waitrequest; // mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_waitrequest -> Gray_Processing_system:avm_memgmem0_port_0_0_rw_waitrequest
wire [4:0] gray_processing_system_avm_memgmem0_port_0_0_rw_burstcount; // Gray_Processing_system:avm_memgmem0_port_0_0_rw_burstcount -> mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_burstcount
wire [255:0] gray_processing_system_avm_memgmem0_port_0_0_rw_writedata; // Gray_Processing_system:avm_memgmem0_port_0_0_rw_writedata -> mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_writedata
wire [29:0] gray_processing_system_avm_memgmem0_port_0_0_rw_address; // Gray_Processing_system:avm_memgmem0_port_0_0_rw_address -> mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_address
wire gray_processing_system_avm_memgmem0_port_0_0_rw_write; // Gray_Processing_system:avm_memgmem0_port_0_0_rw_write -> mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_write
wire gray_processing_system_avm_memgmem0_port_0_0_rw_read; // Gray_Processing_system:avm_memgmem0_port_0_0_rw_read -> mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_read
wire [255:0] gray_processing_system_avm_memgmem0_port_0_0_rw_readdata; // mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdata -> Gray_Processing_system:avm_memgmem0_port_0_0_rw_readdata
wire gray_processing_system_avm_memgmem0_port_0_0_rw_readdatavalid; // mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdatavalid -> Gray_Processing_system:avm_memgmem0_port_0_0_rw_readdatavalid
wire [31:0] gray_processing_system_avm_memgmem0_port_0_0_rw_byteenable; // Gray_Processing_system:avm_memgmem0_port_0_0_rw_byteenable -> mm_interconnect_0:Gray_Processing_system_avm_memgmem0_port_0_0_rw_byteenable
wire mm_interconnect_0_acl_iface_kernel_mem0_waitrequest; // acl_iface:kernel_mem0_waitrequest -> mm_interconnect_0:acl_iface_kernel_mem0_waitrequest
wire [4:0] mm_interconnect_0_acl_iface_kernel_mem0_burstcount; // mm_interconnect_0:acl_iface_kernel_mem0_burstcount -> acl_iface:kernel_mem0_burstcount
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_writedata; // mm_interconnect_0:acl_iface_kernel_mem0_writedata -> acl_iface:kernel_mem0_writedata
wire [29:0] mm_interconnect_0_acl_iface_kernel_mem0_address; // mm_interconnect_0:acl_iface_kernel_mem0_address -> acl_iface:kernel_mem0_address
wire mm_interconnect_0_acl_iface_kernel_mem0_write; // mm_interconnect_0:acl_iface_kernel_mem0_write -> acl_iface:kernel_mem0_write
wire mm_interconnect_0_acl_iface_kernel_mem0_read; // mm_interconnect_0:acl_iface_kernel_mem0_read -> acl_iface:kernel_mem0_read
wire [255:0] mm_interconnect_0_acl_iface_kernel_mem0_readdata; // acl_iface:kernel_mem0_readdata -> mm_interconnect_0:acl_iface_kernel_mem0_readdata
wire mm_interconnect_0_acl_iface_kernel_mem0_debugaccess; // mm_interconnect_0:acl_iface_kernel_mem0_debugaccess -> acl_iface:kernel_mem0_debugaccess
wire mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid; // acl_iface:kernel_mem0_readdatavalid -> mm_interconnect_0:acl_iface_kernel_mem0_readdatavalid
wire [31:0] mm_interconnect_0_acl_iface_kernel_mem0_byteenable; // mm_interconnect_0:acl_iface_kernel_mem0_byteenable -> acl_iface:kernel_mem0_byteenable
wire [0:0] acl_iface_kernel_cra_burstcount; // acl_iface:kernel_cra_burstcount -> mm_interconnect_1:acl_iface_kernel_cra_burstcount
wire acl_iface_kernel_cra_waitrequest; // mm_interconnect_1:acl_iface_kernel_cra_waitrequest -> acl_iface:kernel_cra_waitrequest
wire [29:0] acl_iface_kernel_cra_address; // acl_iface:kernel_cra_address -> mm_interconnect_1:acl_iface_kernel_cra_address
wire [63:0] acl_iface_kernel_cra_writedata; // acl_iface:kernel_cra_writedata -> mm_interconnect_1:acl_iface_kernel_cra_writedata
wire acl_iface_kernel_cra_write; // acl_iface:kernel_cra_write -> mm_interconnect_1:acl_iface_kernel_cra_write
wire acl_iface_kernel_cra_read; // acl_iface:kernel_cra_read -> mm_interconnect_1:acl_iface_kernel_cra_read
wire [63:0] acl_iface_kernel_cra_readdata; // mm_interconnect_1:acl_iface_kernel_cra_readdata -> acl_iface:kernel_cra_readdata
wire acl_iface_kernel_cra_debugaccess; // acl_iface:kernel_cra_debugaccess -> mm_interconnect_1:acl_iface_kernel_cra_debugaccess
wire [7:0] acl_iface_kernel_cra_byteenable; // acl_iface:kernel_cra_byteenable -> mm_interconnect_1:acl_iface_kernel_cra_byteenable
wire acl_iface_kernel_cra_readdatavalid; // mm_interconnect_1:acl_iface_kernel_cra_readdatavalid -> acl_iface:kernel_cra_readdatavalid
wire mm_interconnect_1_cra_root_cra_slave_waitrequest; // cra_root:avs_waitrequest -> mm_interconnect_1:cra_root_cra_slave_waitrequest
wire [63:0] mm_interconnect_1_cra_root_cra_slave_writedata; // mm_interconnect_1:cra_root_cra_slave_writedata -> cra_root:avs_writedata
wire [3:0] mm_interconnect_1_cra_root_cra_slave_address; // mm_interconnect_1:cra_root_cra_slave_address -> cra_root:avs_addr
wire mm_interconnect_1_cra_root_cra_slave_write; // mm_interconnect_1:cra_root_cra_slave_write -> cra_root:avs_write
wire mm_interconnect_1_cra_root_cra_slave_read; // mm_interconnect_1:cra_root_cra_slave_read -> cra_root:avs_read
wire [63:0] mm_interconnect_1_cra_root_cra_slave_readdata; // cra_root:avs_readdata -> mm_interconnect_1:cra_root_cra_slave_readdata
wire mm_interconnect_1_cra_root_cra_slave_readdatavalid; // cra_root:avs_readdatavalid -> mm_interconnect_1:cra_root_cra_slave_readdatavalid
wire [7:0] mm_interconnect_1_cra_root_cra_slave_byteenable; // mm_interconnect_1:cra_root_cra_slave_byteenable -> cra_root:avs_byteena
wire irq_mapper_receiver0_irq; // Gray_Processing_system:kernel_irq -> irq_mapper:receiver0_irq
wire [0:0] acl_iface_kernel_irq_irq; // irq_mapper:sender_irq -> acl_iface:kernel_irq_irq
system_acl_iface acl_iface (
.config_clk_clk (clk_50_clk), // config_clk.clk
.reset_n (reset_50_reset_n), // global_reset.reset_n
.kernel_pll_refclk_clk (clk_50_clk), // kernel_pll_refclk.clk
.kernel_clk_clk (acl_iface_kernel_clk_clk), // kernel_clk.clk
.kernel_reset_reset_n (acl_iface_kernel_reset_reset), // kernel_reset.reset_n
.kernel_clk2x_clk (acl_iface_kernel_clk2x_clk), // kernel_clk2x.clk
.kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // kernel_mem0.waitrequest
.kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // .address
.kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess), // .debugaccess
.acl_kernel_clk_kernel_pll_locked_export (), // acl_kernel_clk_kernel_pll_locked.export
.kernel_clk_snoop_clk (kernel_clk_clk), // kernel_clk_snoop.clk
.memory_mem_a (memory_mem_a), // memory.mem_a
.memory_mem_ba (memory_mem_ba), // .mem_ba
.memory_mem_ck (memory_mem_ck), // .mem_ck
.memory_mem_ck_n (memory_mem_ck_n), // .mem_ck_n
.memory_mem_cke (memory_mem_cke), // .mem_cke
.memory_mem_cs_n (memory_mem_cs_n), // .mem_cs_n
.memory_mem_ras_n (memory_mem_ras_n), // .mem_ras_n
.memory_mem_cas_n (memory_mem_cas_n), // .mem_cas_n
.memory_mem_we_n (memory_mem_we_n), // .mem_we_n
.memory_mem_reset_n (memory_mem_reset_n), // .mem_reset_n
.memory_mem_dq (memory_mem_dq), // .mem_dq
.memory_mem_dqs (memory_mem_dqs), // .mem_dqs
.memory_mem_dqs_n (memory_mem_dqs_n), // .mem_dqs_n
.memory_mem_odt (memory_mem_odt), // .mem_odt
.memory_mem_dm (memory_mem_dm), // .mem_dm
.memory_oct_rzqin (memory_oct_rzqin), // .oct_rzqin
.peripheral_hps_io_emac1_inst_TX_CLK (peripheral_hps_io_emac1_inst_TX_CLK), // peripheral.hps_io_emac1_inst_TX_CLK
.peripheral_hps_io_emac1_inst_TXD0 (peripheral_hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.peripheral_hps_io_emac1_inst_TXD1 (peripheral_hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.peripheral_hps_io_emac1_inst_TXD2 (peripheral_hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.peripheral_hps_io_emac1_inst_TXD3 (peripheral_hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.peripheral_hps_io_emac1_inst_RXD0 (peripheral_hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.peripheral_hps_io_emac1_inst_MDIO (peripheral_hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.peripheral_hps_io_emac1_inst_MDC (peripheral_hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.peripheral_hps_io_emac1_inst_RX_CTL (peripheral_hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.peripheral_hps_io_emac1_inst_TX_CTL (peripheral_hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.peripheral_hps_io_emac1_inst_RX_CLK (peripheral_hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.peripheral_hps_io_emac1_inst_RXD1 (peripheral_hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.peripheral_hps_io_emac1_inst_RXD2 (peripheral_hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.peripheral_hps_io_emac1_inst_RXD3 (peripheral_hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.peripheral_hps_io_sdio_inst_CMD (peripheral_hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.peripheral_hps_io_sdio_inst_D0 (peripheral_hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.peripheral_hps_io_sdio_inst_D1 (peripheral_hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.peripheral_hps_io_sdio_inst_CLK (peripheral_hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.peripheral_hps_io_sdio_inst_D2 (peripheral_hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.peripheral_hps_io_sdio_inst_D3 (peripheral_hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.peripheral_hps_io_uart0_inst_RX (peripheral_hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.peripheral_hps_io_uart0_inst_TX (peripheral_hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.peripheral_hps_io_i2c1_inst_SDA (peripheral_hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.peripheral_hps_io_i2c1_inst_SCL (peripheral_hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.peripheral_hps_io_gpio_inst_GPIO53 (peripheral_hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.acl_internal_memorg_kernel_mode (), // acl_internal_memorg_kernel.mode
.kernel_irq_irq (acl_iface_kernel_irq_irq), // kernel_irq.irq
.kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // kernel_cra.waitrequest
.kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.kernel_cra_address (acl_iface_kernel_cra_address), // .address
.kernel_cra_write (acl_iface_kernel_cra_write), // .write
.kernel_cra_read (acl_iface_kernel_cra_read), // .read
.kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.kernel_interface_acl_bsp_memorg_host_mode () // kernel_interface_acl_bsp_memorg_host.mode
);
Gray_Processing_system gray_processing_system (
.clock (acl_iface_kernel_clk_clk), // clock_reset.clk
.resetn (acl_iface_kernel_reset_reset), // clock_reset_reset.reset_n
.clock2x (acl_iface_kernel_clk2x_clk), // clock_reset2x.clk
.avs_graying_cra_read (avs_graying_cra_cra_ring_cra_master_read), // avs_graying_cra.read
.avs_graying_cra_write (avs_graying_cra_cra_ring_cra_master_write), // .write
.avs_graying_cra_address (avs_graying_cra_cra_ring_cra_master_address), // .address
.avs_graying_cra_writedata (avs_graying_cra_cra_ring_cra_master_writedata), // .writedata
.avs_graying_cra_byteenable (avs_graying_cra_cra_ring_cra_master_byteenable), // .byteenable
.avs_graying_cra_waitrequest (avs_graying_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.avs_graying_cra_readdata (avs_graying_cra_cra_ring_cra_master_readdata), // .readdata
.avs_graying_cra_readdatavalid (avs_graying_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.kernel_irq (irq_mapper_receiver0_irq), // kernel_irq.irq
.avm_memgmem0_port_0_0_rw_address (gray_processing_system_avm_memgmem0_port_0_0_rw_address), // avm_memgmem0_port_0_0_rw.address
.avm_memgmem0_port_0_0_rw_read (gray_processing_system_avm_memgmem0_port_0_0_rw_read), // .read
.avm_memgmem0_port_0_0_rw_write (gray_processing_system_avm_memgmem0_port_0_0_rw_write), // .write
.avm_memgmem0_port_0_0_rw_burstcount (gray_processing_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.avm_memgmem0_port_0_0_rw_writedata (gray_processing_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.avm_memgmem0_port_0_0_rw_byteenable (gray_processing_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.avm_memgmem0_port_0_0_rw_readdata (gray_processing_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.avm_memgmem0_port_0_0_rw_waitrequest (gray_processing_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.avm_memgmem0_port_0_0_rw_readdatavalid (gray_processing_system_avm_memgmem0_port_0_0_rw_readdatavalid) // .readdatavalid
);
cra_ring_root #(
.ADDR_W (4),
.DATA_W (64),
.ID_W (0)
) cra_root (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avs_write (mm_interconnect_1_cra_root_cra_slave_write), // cra_slave.write
.avs_addr (mm_interconnect_1_cra_root_cra_slave_address), // .address
.avs_byteena (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.avs_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.avs_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.avs_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.avs_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest), // .waitrequest
.avs_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.ri_write (avs_graying_cra_cra_ring_ring_out_write), // ring_in.write
.ri_addr (avs_graying_cra_cra_ring_ring_out_addr), // .addr
.ri_byteena (avs_graying_cra_cra_ring_ring_out_byteena), // .byteena
.ri_data (avs_graying_cra_cra_ring_ring_out_data), // .data
.ri_read (avs_graying_cra_cra_ring_ring_out_read), // .read
.ri_datavalid (avs_graying_cra_cra_ring_ring_out_datavalid), // .datavalid
.ri_waitrequest (cra_root_ring_in_waitrequest), // .waitrequest
.ro_read (cra_root_ring_out_read), // ring_out.read
.ro_write (cra_root_ring_out_write), // .write
.ro_addr (cra_root_ring_out_addr), // .addr
.ro_data (cra_root_ring_out_data), // .data
.ro_byteena (cra_root_ring_out_byteena), // .byteena
.ro_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ro_waitrequest (avs_graying_cra_cra_ring_ring_in_waitrequest) // .waitrequest
);
cra_ring_node #(
.RING_ADDR_W (4),
.CRA_ADDR_W (4),
.DATA_W (64),
.ID_W (0),
.ID (32'b00000000000000000000000000000000)
) avs_graying_cra_cra_ring (
.clk (acl_iface_kernel_clk_clk), // clock.clk
.rst_n (acl_iface_kernel_reset_reset), // reset.reset_n
.avm_read (avs_graying_cra_cra_ring_cra_master_read), // cra_master.read
.avm_write (avs_graying_cra_cra_ring_cra_master_write), // .write
.avm_addr (avs_graying_cra_cra_ring_cra_master_address), // .address
.avm_byteena (avs_graying_cra_cra_ring_cra_master_byteenable), // .byteenable
.avm_writedata (avs_graying_cra_cra_ring_cra_master_writedata), // .writedata
.avm_readdata (avs_graying_cra_cra_ring_cra_master_readdata), // .readdata
.avm_readdatavalid (avs_graying_cra_cra_ring_cra_master_readdatavalid), // .readdatavalid
.avm_waitrequest (avs_graying_cra_cra_ring_cra_master_waitrequest), // .waitrequest
.ri_read (cra_root_ring_out_read), // ring_in.read
.ri_write (cra_root_ring_out_write), // .write
.ri_addr (cra_root_ring_out_addr), // .addr
.ri_data (cra_root_ring_out_data), // .data
.ri_byteena (cra_root_ring_out_byteena), // .byteena
.ri_datavalid (cra_root_ring_out_datavalid), // .datavalid
.ri_waitrequest (avs_graying_cra_cra_ring_ring_in_waitrequest), // .waitrequest
.ro_read (avs_graying_cra_cra_ring_ring_out_read), // ring_out.read
.ro_write (avs_graying_cra_cra_ring_ring_out_write), // .write
.ro_addr (avs_graying_cra_cra_ring_ring_out_addr), // .addr
.ro_data (avs_graying_cra_cra_ring_ring_out_data), // .data
.ro_byteena (avs_graying_cra_cra_ring_ring_out_byteena), // .byteena
.ro_datavalid (avs_graying_cra_cra_ring_ring_out_datavalid), // .datavalid
.ro_waitrequest (cra_root_ring_in_waitrequest) // .waitrequest
);
system_mm_interconnect_0 mm_interconnect_0 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // Gray_Processing_system_clock_reset_reset_reset_bridge_in_reset.reset
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_address (gray_processing_system_avm_memgmem0_port_0_0_rw_address), // Gray_Processing_system_avm_memgmem0_port_0_0_rw.address
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_waitrequest (gray_processing_system_avm_memgmem0_port_0_0_rw_waitrequest), // .waitrequest
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_burstcount (gray_processing_system_avm_memgmem0_port_0_0_rw_burstcount), // .burstcount
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_byteenable (gray_processing_system_avm_memgmem0_port_0_0_rw_byteenable), // .byteenable
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_read (gray_processing_system_avm_memgmem0_port_0_0_rw_read), // .read
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdata (gray_processing_system_avm_memgmem0_port_0_0_rw_readdata), // .readdata
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_readdatavalid (gray_processing_system_avm_memgmem0_port_0_0_rw_readdatavalid), // .readdatavalid
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_write (gray_processing_system_avm_memgmem0_port_0_0_rw_write), // .write
.Gray_Processing_system_avm_memgmem0_port_0_0_rw_writedata (gray_processing_system_avm_memgmem0_port_0_0_rw_writedata), // .writedata
.acl_iface_kernel_mem0_address (mm_interconnect_0_acl_iface_kernel_mem0_address), // acl_iface_kernel_mem0.address
.acl_iface_kernel_mem0_write (mm_interconnect_0_acl_iface_kernel_mem0_write), // .write
.acl_iface_kernel_mem0_read (mm_interconnect_0_acl_iface_kernel_mem0_read), // .read
.acl_iface_kernel_mem0_readdata (mm_interconnect_0_acl_iface_kernel_mem0_readdata), // .readdata
.acl_iface_kernel_mem0_writedata (mm_interconnect_0_acl_iface_kernel_mem0_writedata), // .writedata
.acl_iface_kernel_mem0_burstcount (mm_interconnect_0_acl_iface_kernel_mem0_burstcount), // .burstcount
.acl_iface_kernel_mem0_byteenable (mm_interconnect_0_acl_iface_kernel_mem0_byteenable), // .byteenable
.acl_iface_kernel_mem0_readdatavalid (mm_interconnect_0_acl_iface_kernel_mem0_readdatavalid), // .readdatavalid
.acl_iface_kernel_mem0_waitrequest (mm_interconnect_0_acl_iface_kernel_mem0_waitrequest), // .waitrequest
.acl_iface_kernel_mem0_debugaccess (mm_interconnect_0_acl_iface_kernel_mem0_debugaccess) // .debugaccess
);
system_mm_interconnect_1 mm_interconnect_1 (
.acl_iface_kernel_clk_clk (acl_iface_kernel_clk_clk), // acl_iface_kernel_clk.clk
.cra_root_reset_reset_bridge_in_reset_reset (~acl_iface_kernel_reset_reset), // cra_root_reset_reset_bridge_in_reset.reset
.acl_iface_kernel_cra_address (acl_iface_kernel_cra_address), // acl_iface_kernel_cra.address
.acl_iface_kernel_cra_waitrequest (acl_iface_kernel_cra_waitrequest), // .waitrequest
.acl_iface_kernel_cra_burstcount (acl_iface_kernel_cra_burstcount), // .burstcount
.acl_iface_kernel_cra_byteenable (acl_iface_kernel_cra_byteenable), // .byteenable
.acl_iface_kernel_cra_read (acl_iface_kernel_cra_read), // .read
.acl_iface_kernel_cra_readdata (acl_iface_kernel_cra_readdata), // .readdata
.acl_iface_kernel_cra_readdatavalid (acl_iface_kernel_cra_readdatavalid), // .readdatavalid
.acl_iface_kernel_cra_write (acl_iface_kernel_cra_write), // .write
.acl_iface_kernel_cra_writedata (acl_iface_kernel_cra_writedata), // .writedata
.acl_iface_kernel_cra_debugaccess (acl_iface_kernel_cra_debugaccess), // .debugaccess
.cra_root_cra_slave_address (mm_interconnect_1_cra_root_cra_slave_address), // cra_root_cra_slave.address
.cra_root_cra_slave_write (mm_interconnect_1_cra_root_cra_slave_write), // .write
.cra_root_cra_slave_read (mm_interconnect_1_cra_root_cra_slave_read), // .read
.cra_root_cra_slave_readdata (mm_interconnect_1_cra_root_cra_slave_readdata), // .readdata
.cra_root_cra_slave_writedata (mm_interconnect_1_cra_root_cra_slave_writedata), // .writedata
.cra_root_cra_slave_byteenable (mm_interconnect_1_cra_root_cra_slave_byteenable), // .byteenable
.cra_root_cra_slave_readdatavalid (mm_interconnect_1_cra_root_cra_slave_readdatavalid), // .readdatavalid
.cra_root_cra_slave_waitrequest (mm_interconnect_1_cra_root_cra_slave_waitrequest) // .waitrequest
);
system_irq_mapper irq_mapper (
.clk (acl_iface_kernel_clk_clk), // clk.clk
.reset (~acl_iface_kernel_reset_reset), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (acl_iface_kernel_irq_irq) // sender.irq
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Instruction TLB ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Instantiation of ITLB. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: or1200_immu_tlb.v,v $
// Revision 1.1 2006-12-21 16:46:58 vak
// Initial revision imported from
// http://www.opencores.org/cvsget.cgi/or1k/orp/orp_soc/rtl/verilog.
//
// Revision 1.9 2004/06/08 18:17:36 lampret
// Non-functional changes. Coding style fixes.
//
// Revision 1.8 2004/04/05 08:29:57 lampret
// Merged branch_qmem into main tree.
//
// Revision 1.6.4.1 2003/12/09 11:46:48 simons
// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
//
// Revision 1.6 2002/10/28 16:34:32 mohor
// RAMs wrong connected to the BIST scan chain.
//
// Revision 1.5 2002/10/17 20:04:40 lampret
// Added BIST scan. Special VS RAMs need to be used to implement BIST.
//
// Revision 1.4 2002/08/14 06:23:50 lampret
// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
//
// Revision 1.3 2002/02/11 04:33:17 lampret
// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
//
// Revision 1.2 2002/01/28 01:16:00 lampret
// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
//
// Revision 1.1 2002/01/03 08:16:15 lampret
// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
//
// Revision 1.8 2001/10/21 17:57:16 lampret
// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
//
// Revision 1.7 2001/10/14 13:12:09 lampret
// MP3 version.
//
// Revision 1.1.1.1 2001/10/06 10:18:36 igorm
// no message
//
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Insn TLB
//
module or1200_immu_tlb(
// Rst and clk
clk, rst,
// I/F for translation
tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// SPR access
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// Clock and reset
//
input clk;
input rst;
//
// I/F for translation
//
input tlb_en;
input [aw-1:0] vaddr;
output hit;
output [31:`OR1200_IMMU_PS] ppn;
output uxe;
output sxe;
output ci;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// SPR access
//
input spr_cs;
input spr_write;
input [31:0] spr_addr;
input [31:0] spr_dat_i;
output [31:0] spr_dat_o;
//
// Internal wires and regs
//
wire [`OR1200_ITLB_TAG] vpn;
wire v;
wire [`OR1200_ITLB_INDXW-1:0] tlb_index;
wire tlb_mr_en;
wire tlb_mr_we;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_in;
wire [`OR1200_ITLBMRW-1:0] tlb_mr_ram_out;
wire tlb_tr_en;
wire tlb_tr_we;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_in;
wire [`OR1200_ITLBTRW-1:0] tlb_tr_ram_out;
// BIST
`ifdef OR1200_BIST
wire itlb_mr_ram_si;
wire itlb_mr_ram_so;
wire itlb_tr_ram_si;
wire itlb_tr_ram_so;
`endif
//
// Implemented bits inside match and translate registers
//
// itlbwYmrX: vpn 31-19 v 0
// itlbwYtrX: ppn 31-13 uxe 7 sxe 6
//
// itlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 2 bits for protection
// 1 bit for cache inhibit
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
//
// Output to SPRS unit
//
assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{vpn, tlb_index & {`OR1200_ITLB_INDXW{v}}, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
(!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
{ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
32'h00000000;
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
//
// Assign outputs from Translate registers
//
assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
`ifdef OR1200_BIST
assign itlb_mr_ram_si = mbist_si_i;
assign itlb_tr_ram_si = itlb_mr_ram_so;
assign mbist_so_o = itlb_tr_ram_so;
`endif
//
// Instantiation of ITLB Match Registers
//
or1200_spram_64x14 itlb_mr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_mr_ram_si),
.mbist_so_o(itlb_mr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_mr_en),
.we(tlb_mr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_mr_ram_in),
.doq(tlb_mr_ram_out)
);
//
// Instantiation of ITLB Translate Registers
//
or1200_spram_64x22 itlb_tr_ram(
.clk(clk),
.rst(rst),
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(itlb_tr_ram_si),
.mbist_so_o(itlb_tr_ram_so),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.ce(tlb_tr_en),
.we(tlb_tr_we),
.oe(1'b1),
.addr(tlb_index),
.di(tlb_tr_ram_in),
.doq(tlb_tr_ram_out)
);
endmodule
|
// megafunction wizard: %Shift register (RAM-based)%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altshift_taps
// ============================================================
// File Name: Line_Buffer.v
// Megafunction Name(s):
// altshift_taps
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2007 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module Line_Buffer (
clken,
clock,
shiftin,
shiftout,
taps0x,
taps1x);
input clken;
input clock;
input [11:0] shiftin;
output [11:0] shiftout;
output [11:0] taps0x;
output [11:0] taps1x;
wire [23:0] sub_wire0;
wire [11:0] sub_wire3;
wire [23:12] sub_wire1 = sub_wire0[23:12];
wire [11:0] sub_wire2 = sub_wire0[11:0];
wire [11:0] taps1x = sub_wire1[23:12];
wire [11:0] taps0x = sub_wire2[11:0];
wire [11:0] shiftout = sub_wire3[11:0];
altshift_taps altshift_taps_component (
.clken (clken),
.clock (clock),
.shiftin (shiftin),
.taps (sub_wire0),
.shiftout (sub_wire3));
defparam
altshift_taps_component.lpm_type = "altshift_taps",
altshift_taps_component.number_of_taps = 2,
altshift_taps_component.tap_distance = 1280,
altshift_taps_component.width = 12;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: CLKEN NUMERIC "1"
// Retrieval info: PRIVATE: GROUP_TAPS NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: NUMBER_OF_TAPS NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: TAP_DISTANCE NUMERIC "1280"
// Retrieval info: PRIVATE: WIDTH NUMERIC "12"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altshift_taps"
// Retrieval info: CONSTANT: NUMBER_OF_TAPS NUMERIC "2"
// Retrieval info: CONSTANT: TAP_DISTANCE NUMERIC "1280"
// Retrieval info: CONSTANT: WIDTH NUMERIC "12"
// Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: shiftin 0 0 12 0 INPUT NODEFVAL shiftin[11..0]
// Retrieval info: USED_PORT: shiftout 0 0 12 0 OUTPUT NODEFVAL shiftout[11..0]
// Retrieval info: USED_PORT: taps0x 0 0 12 0 OUTPUT NODEFVAL taps0x[11..0]
// Retrieval info: USED_PORT: taps1x 0 0 12 0 OUTPUT NODEFVAL taps1x[11..0]
// Retrieval info: CONNECT: @shiftin 0 0 12 0 shiftin 0 0 12 0
// Retrieval info: CONNECT: shiftout 0 0 12 0 @shiftout 0 0 12 0
// Retrieval info: CONNECT: taps0x 0 0 12 0 @taps 0 0 12 0
// Retrieval info: CONNECT: taps1x 0 0 12 0 @taps 0 0 12 12
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer.bsf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL Line_Buffer_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
`timescale 1 ns / 1 ps
module fillbox_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 5
)
(
// Users to add ports here
output wire [27:0] vram,
output wire [9:0] width,
output wire [9:0] height,
output wire [15:0] color,
output wire start,
input wire done,
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 2;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 5
reg [27:0] reg_vram = 0;
reg [9:0] reg_width = 0;
reg [9:0] reg_height = 0;
reg [15:0] reg_color = 0;
reg reg_start = 0;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
reg in_operation = 'b0;
assign vram = reg_vram;
assign width = reg_width;
assign height = reg_height;
assign color = reg_color;
assign start = reg_start;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// user operation
always @(posedge S_AXI_ACLK) begin
if (start)
in_operation <= 'b1;
else if (done)
in_operation <= 'b0;
else
in_operation <= in_operation;
end
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_vram <= 0;
reg_width <= 0;
reg_height <= 0;
reg_color <= 0;
reg_start <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0: // vram
begin
if (S_AXI_WSTRB[0] == 1)
reg_vram[7:0] <= S_AXI_WDATA[7:0];
if (S_AXI_WSTRB[1] == 1)
reg_vram[15:8] <= S_AXI_WDATA[15:8];
if (S_AXI_WSTRB[2] == 1)
reg_vram[23:16] <= S_AXI_WDATA[23:16];
if (S_AXI_WSTRB[3] == 1)
reg_vram[27:24] <= S_AXI_WDATA[27:24];
end
3'h1: // width
begin
if (S_AXI_WSTRB[0] == 1)
reg_width[7:0] <= S_AXI_WDATA[7:0];
if (S_AXI_WSTRB[1] == 1)
reg_width[9:8] <= S_AXI_WDATA[9:8];
end
3'h2: // height
begin
if (S_AXI_WSTRB[0] == 1)
reg_height[7:0] <= S_AXI_WDATA[7:0];
if (S_AXI_WSTRB[1] == 1)
reg_height[9:8] <= S_AXI_WDATA[9:8];
end
3'h3: // color
begin
if (S_AXI_WSTRB[0] == 1)
reg_color[7:0] <= S_AXI_WDATA[7:0];
if (S_AXI_WSTRB[1] == 1)
reg_color[15:8] <= S_AXI_WDATA[15:8];
end
3'h4: // start
reg_start <= 'b1;
default : begin
reg_vram <= reg_vram;
reg_width <= reg_width;
reg_height <= reg_height;
reg_color <= reg_color;
reg_start <= 'b0;
end
endcase
end
else
reg_start <= 'b0;
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
3'h0 : reg_data_out <= {4'b0, vram};
3'h1 : reg_data_out <= {22'b0, width};
3'h2 : reg_data_out <= {22'b0, height};
3'h3 : reg_data_out <= {16'b0, color};
3'h4 : reg_data_out <= {31'b0, ~in_operation};
default : reg_data_out <= 0;
endcase
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
// User logic ends
endmodule
|
/*
-- ============================================================================
-- FILE NAME : chip_top_test.v
-- DESCRIPTION : 测试台
-- ----------------------------------------------------------------------------
-- Revision Date Coding_by Comment
-- 1.0.0 2012/04/02 suito 新規作成
-- ============================================================================
*/
/********** タイムスケール **********/
`timescale 1ns/1ps // タイムスケール
/********** 共通ヘッダファイル **********/
`include "nettype.h"
`include "stddef.h"
`include "global_config.h"
/********** 個別ヘッダファイル **********/
`include "bus.h"
`include "cpu.h"
`include "gpio.h"
/********** モジュール **********/
module chip_top_test;
/********** 入出力信号 **********/
// クロック & リセット
reg clk_ref; // 基底クロック
reg reset_sw; // グローバルリセット
// UART
`ifdef IMPLEMENT_UART // UART実装
wire uart_rx; // UART受信信号
wire uart_tx; // UART送信信号
`endif
// 汎用入出力ポート
`ifdef IMPLEMENT_GPIO // GPIO実装
`ifdef GPIO_IN_CH // 入力ポートの実装
wire [`GPIO_IN_CH-1:0] gpio_in = {`GPIO_IN_CH{1'b0}}; // 入力ポート
`endif
`ifdef GPIO_OUT_CH // 出力ポートの実装
wire [`GPIO_OUT_CH-1:0] gpio_out; // 出力ポート
`endif
`ifdef GPIO_IO_CH // 入出力ポートの実装
wire [`GPIO_IO_CH-1:0] gpio_io = {`GPIO_IO_CH{1'bz}}; // 入出力ポート
`endif
`endif
/********** UARTモデル **********/
`ifdef IMPLEMENT_UART // UART実装
wire rx_busy; // 受信中フラグ
wire rx_end; // 受信完了信号
wire [`ByteDataBus] rx_data; // 受信データ
`endif
/********** シミュレーションサイクル **********/
parameter STEP = 100.0000; // 10 M
/********** クロック生成 **********/
always #( STEP / 2 ) begin
clk_ref <= ~clk_ref;
end
/********** chip_topのインスタンス化 **********/
chip_top chip_top (
/********** クロック & リセット **********/
.clk_ref (clk_ref), // 基底クロック
.reset_sw (reset_sw) // グローバルリセット
/********** UART **********/
`ifdef IMPLEMENT_UART // UART実装
, .uart_rx (uart_rx) // UART受信信号
, .uart_tx (uart_tx) // UART送信信号
`endif
/********** 汎用入出力ポート **********/
`ifdef IMPLEMENT_GPIO // GPIO実装
`ifdef GPIO_IN_CH // 入力ポートの実装
, .gpio_in (gpio_in) // 入力ポート
`endif
`ifdef GPIO_OUT_CH // 出力ポートの実装
, .gpio_out (gpio_out) // 出力ポート
`endif
`ifdef GPIO_IO_CH // 入出力ポートの実装
, .gpio_io (gpio_io) // 入出力ポート
`endif
`endif
);
/********** GPIOのモニタリング **********/
`ifdef IMPLEMENT_GPIO // GPIO実装
`ifdef GPIO_IN_CH // 入力ポートの実装
always @(gpio_in) begin // gpio_inが変化したら値をプリント
$display($time, " gpio_in changed : %b", gpio_in);
end
`endif
`ifdef GPIO_OUT_CH // 出力ポートの実装
always @(gpio_out) begin // gpio_outが変化したら値をプリント
$display($time, " gpio_out changed : %b", gpio_out);
end
`endif
`ifdef GPIO_IO_CH // 入出力ポートの実装
always @(gpio_io) begin // gpio_ioが変化したら値をプリント
$display($time, " gpio_io changed : %b", gpio_io);
end
`endif
`endif
/********** UARTモデルのインスタンス化 **********/
`ifdef IMPLEMENT_UART // UART実装
/********** 受信信号 **********/
assign uart_rx = `HIGH; // アイドル
// assign uart_rx = uart_tx; // ループバック
/********** UARTモデル **********/
uart_rx uart_model (
/********** クロック & リセット **********/
.clk (chip_top.clk), // クロック
.reset (chip_top.chip_reset), // 非同期リセット
/********** 制御信号 **********/
.rx_busy (rx_busy), // 受信中フラグ
.rx_end (rx_end), // 受信完了信号
.rx_data (rx_data), // 受信データ
/********** Receive Signal **********/
.rx (uart_tx) // UART受信信号
);
/********** 送信信号のモニタリング **********/
always @(posedge chip_top.clk) begin
if (rx_end == `ENABLE) begin // 受信したら文字を出力
$write("%c", rx_data);
end
end
`endif
/********** テストシーケンス **********/
initial begin
# 0 begin
clk_ref <= `HIGH;
reset_sw <= `RESET_ENABLE;
end
# ( STEP / 2 )
# ( STEP / 4 ) begin // メモリイメージの読み込み
$readmemh(`ROM_PRG, chip_top.chip.rom.x_s3e_sprom.mem);
$readmemh(`SPM_PRG, chip_top.chip.cpu.spm.x_s3e_dpram.mem);
end
# ( STEP * 20 ) begin // リセットの解除
reset_sw <= `RESET_DISABLE;
end
# ( STEP * `SIM_CYCLE ) begin // シミュレーションの実行
$finish;
end
end
/********** 波形の出力 **********/
initial begin
$dumpfile("chip_top.vcd");
$dumpvars(0, chip_top);
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__NOR4_BEHAVIORAL_PP_V |
module nios (
clk50_clk,
io_ack,
io_rdata,
io_read,
io_wdata,
io_write,
io_address,
io_irq,
mem32_address,
mem32_direction,
mem32_byte_en,
mem32_wdata,
mem32_request,
mem32_tag,
mem32_dack_tag,
mem32_rdata,
mem32_rack,
mem32_rack_tag,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_dm,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
oct_rzqin,
pio_in_port,
pio_out_port,
reset_reset_n,
status_local_init_done,
status_local_cal_success,
status_local_cal_fail,
sys_clock_clk,
sys_reset_reset_n);
input clk50_clk;
input io_ack;
input [7:0] io_rdata;
output io_read;
output [7:0] io_wdata;
output io_write;
output [19:0] io_address;
input io_irq;
input [25:0] mem32_address;
input mem32_direction;
input [3:0] mem32_byte_en;
input [31:0] mem32_wdata;
input mem32_request;
input [7:0] mem32_tag;
output [7:0] mem32_dack_tag;
output [31:0] mem32_rdata;
output mem32_rack;
output [7:0] mem32_rack_tag;
output [13:0] memory_mem_a;
output [1:0] memory_mem_ba;
output [0:0] memory_mem_ck;
output [0:0] memory_mem_ck_n;
output [0:0] memory_mem_cke;
output [0:0] memory_mem_cs_n;
output [0:0] memory_mem_dm;
output [0:0] memory_mem_ras_n;
output [0:0] memory_mem_cas_n;
output [0:0] memory_mem_we_n;
inout [7:0] memory_mem_dq;
inout [0:0] memory_mem_dqs;
inout [0:0] memory_mem_dqs_n;
output [0:0] memory_mem_odt;
input oct_rzqin;
input [31:0] pio_in_port;
output [31:0] pio_out_port;
input reset_reset_n;
output status_local_init_done;
output status_local_cal_success;
output status_local_cal_fail;
output sys_clock_clk;
output sys_reset_reset_n;
endmodule
|
//Legal Notice: (C)2011 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_ram (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../ddr3_s4_uniphy_p0_qsys_sequencer_sequencer_ram.hex";
output [ 31: 0] readdata;
input [ 8: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = "UNUSED",
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 512,
the_altsyncram.numwords_a = 512,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 9;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "UNUSED",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 512,
// the_altsyncram.numwords_a = 512,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 9;
//
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_1_V
`define SKY130_FD_SC_MS__DFXBP_1_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog wrapper for dfxbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfxbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxbp_1 (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__dfxbp_1 (
Q ,
Q_N,
CLK,
D
);
output Q ;
output Q_N;
input CLK;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__dfxbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_1_V
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
// Date : Fri Oct 27 14:51:03 2017
// Host : Juice-Laptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/RATCPU/Experiments/Experiment8-GeterDone/IPI-BD/RAT/ip/RAT_prog_rom_0_0/RAT_prog_rom_0_0_stub.v
// Design : RAT_prog_rom_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7a35tcpg236-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "prog_rom,Vivado 2016.4" *)
module RAT_prog_rom_0_0(ADDRESS, INSTRUCTION, CLK)
/* synthesis syn_black_box black_box_pad_pin="ADDRESS[9:0],INSTRUCTION[17:0],CLK" */;
input [9:0]ADDRESS;
output [17:0]INSTRUCTION;
input CLK;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFRTP_1_V
`define SKY130_FD_SC_HDLL__SDFRTP_1_V
/**
* sdfrtp: Scan delay flop, inverted reset, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfrtp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfrtp_1 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfrtp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.RESET_B(RESET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFRTP_1_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:04:46 03/14/2015
// Design Name: deserializer
// Module Name: C:/Users/omicronns/Workspaces/webpack-ise/sys-rek/lab3/deserializer/tb_deserializer.v
// Project Name: deserializer
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: deserializer
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module tb_deserializer;
wire rxd;
wire rst;
wire clk;
wire [7:0] data;
wire received;
deserializer_gen_test generator (
.rxd(rxd),
.clk(clk)
);
// Instantiate the Unit Under Test (UUT)
deserializer uut (
.rxd(rxd),
.rst(rst),
.clk(clk),
.data(data),
.received(received)
);
deserializer_check_test writer (
.received(received),
.data(data)
);
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Wed Sep 27 18:05:24 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// C:/Projects/srio_test/srio_test/srio_test.srcs/sources_1/ip/dbg_ila/dbg_ila_stub.v
// Design : dbg_ila
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module dbg_ila(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7, probe8, probe9, probe10, probe11, probe12, probe13, probe14, probe15, probe16, probe17,
probe18, probe19, probe20, probe21, probe22, probe23, probe24, probe25)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[63:0],probe8[0:0],probe9[0:0],probe10[0:0],probe11[0:0],probe12[63:0],probe13[0:0],probe14[0:0],probe15[0:0],probe16[0:0],probe17[0:0],probe18[7:0],probe19[8:0],probe20[0:0],probe21[2:0],probe22[2:0],probe23[0:0],probe24[7:0],probe25[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [63:0]probe7;
input [0:0]probe8;
input [0:0]probe9;
input [0:0]probe10;
input [0:0]probe11;
input [63:0]probe12;
input [0:0]probe13;
input [0:0]probe14;
input [0:0]probe15;
input [0:0]probe16;
input [0:0]probe17;
input [7:0]probe18;
input [8:0]probe19;
input [0:0]probe20;
input [2:0]probe21;
input [2:0]probe22;
input [0:0]probe23;
input [7:0]probe24;
input [0:0]probe25;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR3_1_V
`define SKY130_FD_SC_HS__XOR3_1_V
/**
* xor3: 3-input exclusive OR.
*
* X = A ^ B ^ C
*
* Verilog wrapper for xor3 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__xor3.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_1 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__xor3_1 (
X,
A,
B,
C
);
output X;
input A;
input B;
input C;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__xor3 base (
.X(X),
.A(A),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR3_1_V
|
//*******************************************************************************************************************************************************/
// Module Name: reg_array_dual
// Module Type: Synchronous Dual Port Memory Array
// Author: Shreyas Vinod
// Purpose: General Purpose Register Array for Neptune I v3.0
// Description: A synchronous unidirectional dual port general purpose register array with a simple fault mechanism to detect dual write single address
// collisions.
//*******************************************************************************************************************************************************/
module reg_array_dual(clk, rst, we1, we2, add1, add2, wr1, wr2, mem_fault, rd1, rd2);
// Parameter Definitions
parameter width = 'd16; // Register Array Width
parameter depth = 'd8; // Register Array Depth
parameter add_width = 'd3; // Register Addressing Width
// Inputs
input wire clk /* System Clock */, rst /* System Reset. Resets Memory Fault Flag. */; // Management Interfaces
input wire we1 /* Write Enable to Port I */, we2 /* Write Enable to Port II */; // Control Interfaces
input wire [add_width-1:0] add1 /* Address for Port I */, add2 /* Address for Port I */;
input [width-1:0] wr1 /* Write Port I */, wr2 /* Write Port II */;
// Outputs
output reg mem_fault /* Memory Write Collision Fault Flag */;
output reg [width-1:0] rd1 /* Read Port I */, rd2 /* Read Port II */;
// Internal
reg [width-1:0] mem_arr [0:depth-1] /* Memory Array */;
// Fault Logic
always@(posedge clk) begin
if(rst) mem_fault <= 1'b0;
else if((we1 && we2) && (add1 && add2)) mem_fault <= 1'b1;
end
// Memory Read Block
always@(posedge clk) begin
rd1 [width-1:0] <= mem_arr[add1] [width-1:0]; // Read to Port I if re1 is true.
rd2 [width-1:0] <= mem_arr[add2] [width-1:0]; // Read to Port II if re2 is true.
end
// Memory Write Block
always@(posedge clk) begin
if(we1) mem_arr[add1] [width-1:0] <= wr1 [width-1:0]; // Write from Port I if we1 is true.
if(we2) mem_arr[add2] [width-1:0] <= wr2 [width-1:0]; // Write from Port II if we2 is true.
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O221A_BEHAVIORAL_V
`define SKY130_FD_SC_MS__O221A_BEHAVIORAL_V
/**
* o221a: 2-input OR into first two inputs of 3-input AND.
*
* X = ((A1 | A2) & (B1 | B2) & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__o221a (
X ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out ;
wire or1_out ;
wire and0_out_X;
// Name Output Other arguments
or or0 (or0_out , B2, B1 );
or or1 (or1_out , A2, A1 );
and and0 (and0_out_X, or0_out, or1_out, C1);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__O221A_BEHAVIORAL_V |
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
module gpac_adc_iobuf
(
input ADC_CLK,
input ADC_DCO_P, ADC_DCO_N,
(* IOB="TRUE" *)
output reg ADC_DCO,
input ADC_FCO_P, ADC_FCO_N,
(* IOB="TRUE" *)
output reg ADC_FCO,
(* IOB="TRUE" *)
input ADC_ENC,
output ADC_ENC_P, ADC_ENC_N,
input [3:0] ADC_IN_P, ADC_IN_N,
output [13:0] ADC_IN0, ADC_IN1, ADC_IN2, ADC_IN3
);
(* IOB="TRUE" *)
wire ADC_DCO_BUF;
(* IOB="TRUE" *)
wire ADC_FCO_BUF;
(* IOB="TRUE" *)
wire [3:0] ADC_IN_BUF;
(* IOB="TRUE" *)
wire ADC_ENC_BUF;
(* IOB="TRUE" *)
reg [3:0] ADC_IN;
// I/O BUFFERS
always@(negedge ADC_CLK)
ADC_DCO <= ADC_DCO_BUF;
always@(negedge ADC_CLK)
ADC_FCO <= ADC_FCO_BUF;
always@(negedge ADC_CLK)
ADC_IN <= ADC_IN_BUF;
//always@(negedge ADC_CLK)
// ADC_ENC_BUF <= ADC_ENC;
assign ADC_ENC_BUF = ADC_ENC;
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_FCO (
.O(ADC_FCO_BUF), // Clock buffer output
.I(ADC_FCO_P), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_FCO_N) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFGDS // Specify the input I/O standard
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
)
IBUFDS_ADC_DCO (
.O(ADC_DCO_BUF), // Buffer output
.I(ADC_DCO_P), // Diff_p buffer input (connect directly to top-level port)
.IB(ADC_DCO_N) // Diff_n buffer input (connect directly to top-level port)
);
//BUFG ADC_BUFG_INST (.I(ADC_FCO_PB), .O(ADC_FCO));
OBUFDS #(
.IOSTANDARD("LVDS_25") // Specify the output I/O standard
) OBUFDS_ADC_ENC (
.O(ADC_ENC_P), // Diff_p output (connect directly to top-level port)
.OB(ADC_ENC_N), // Diff_n output (connect directly to top-level port)
.I(ADC_ENC_BUF) // Buffer input
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_0 (
.O(ADC_IN_BUF[0]), // Clock buffer output
.I(ADC_IN_P[0]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[0]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_1 (
.O(ADC_IN_BUF[1]), // Clock buffer output
.I(ADC_IN_P[1]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[1]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_2 (
.O(ADC_IN_BUF[2]), // Clock buffer output
.I(ADC_IN_P[2]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[2]) // Diff_n clock buffer input (connect directly to top-level port)
);
IBUFDS
#(
.DIFF_TERM("TRUE"), // Differential Termination
.IOSTANDARD("LVDS_25") // Specify the input I/O standard
) IBUFGDS_ADC_OUT_3 (
.O(ADC_IN_BUF[3]), // Clock buffer output
.I(ADC_IN_P[3]), // Diff_p clock buffer input (connect directly to top-level port)
.IB(ADC_IN_N[3]) // Diff_n clock buffer input (connect directly to top-level port)
);
reg [1:0] fco_sync;
always@(negedge ADC_CLK) begin
fco_sync <= {fco_sync[0],ADC_FCO};
end
wire adc_des_rst;
assign adc_des_rst = fco_sync[0] & !fco_sync[1] ;
reg [15:0] adc_des_cnt;
always@(negedge ADC_CLK) begin
if(adc_des_rst)
adc_des_cnt[0] <= 1;
else
adc_des_cnt <= {adc_des_cnt[14:0],1'b0};
end
wire adc_load;
assign adc_load = adc_des_cnt[12];
reg [13:0] adc_out_sync [3:0];
genvar i;
generate
for (i = 0; i < 4; i = i + 1) begin: gen
reg [13:0] adc_des;
always@(negedge ADC_CLK) begin
adc_des <= {adc_des[12:0],ADC_IN[i]};
end
reg [13:0] adc_des_syn;
always@(negedge ADC_CLK) begin
if(adc_load)
adc_des_syn <= adc_des;
end
always@(posedge ADC_ENC)
adc_out_sync[i] <= adc_des_syn;
end
endgenerate
assign ADC_IN0 = adc_out_sync[0];
assign ADC_IN1 = adc_out_sync[1];
assign ADC_IN2 = adc_out_sync[2];
assign ADC_IN3 = adc_out_sync[3];
`ifdef SYNTHESIS_
wire [35:0] control_bus;
chipscope_icon ichipscope_icon
(
.CONTROL0(control_bus)
);
chipscope_ila ichipscope_ila
(
.CONTROL(control_bus),
.CLK(ADC_CLK),
.TRIG0({ADC_IN0, adc_load, adc_des_rst, fco_sync, ADC_IN[0]})
);
`endif
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKINVLP_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__CLKINVLP_PP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkinvlp (
Y ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKINVLP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A211O_TB_V
`define SKY130_FD_SC_HD__A211O_TB_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a211o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 C1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 B1 = 1'b1;
#240 C1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 B1 = 1'b0;
#400 C1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 C1 = 1'b1;
#600 B1 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 C1 = 1'bx;
#760 B1 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__a211o dut (.A1(A1), .A2(A2), .B1(B1), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__A211O_TB_V
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
/* Uncomment this for LCU????
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
//output [Y_WIDTH-1:0] CO;
output CO;
wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
/* Start implementation */
//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
/*
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1)
(* keep *) cycloneiv_lcell_comb #(.lut_mask(16'b1111_0000_1110_0000), .sum_lutc_input("cin")) carry_end (.combout(CO), .dataa(1'b1), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[Y_WIDTH]));
//assign CO = COx[Y_WIDTH];
else
cycloneiv_lcell_comb #(.lut_mask(16'b1001_0110_1110_1000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(COx[i+1]), .dataa(AA[i]), .datab(BB[i]), .datac(1'b1), .datad(1'b1), .cin(C[i+1]));
end: slice
endgenerate
/* End implementation */
/*assign X = AA ^ BB;
endmodule*/
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] X, Y;
input CI, BI;
output [Y_WIDTH:0] CO;
wire _TECHMAP_FAIL_ = Y_WIDTH < 6;
(* force_downto *)
wire [Y_WIDTH-1:0] A_buf, B_buf;
\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
(* force_downto *)
wire [Y_WIDTH-1:0] AA = A_buf;
(* force_downto *)
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
cycloneiv_lcell_comb #(.lut_mask(16'b0101_1010_0101_0000), .sum_lutc_input("cin")) arith_cell (.combout(Y[i]), .cout(CO[i]), .dataa(BB[i]), .datab(1'b1), .datac(1'b1), .datad(1'b1), .cin(C[i]));
end endgenerate
assign X = AA ^ BB;
endmodule
|
/*
* Copyright 2015, Stephen A. Rodgers. All rights reserved.
*
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301, USA.
*
*/
`default_nettype none
module mux64to8 (inword, sel, outbyte);
input [63:0] inword;
input [2:0] sel;
output reg [7:0] outbyte;
always @(*) begin
case(sel)
3'h0:
outbyte <= inword[7:0];
3'h1:
outbyte <= inword[15:8];
3'h2:
outbyte <= inword[23:16];
3'h3:
outbyte <= inword[31:24];
3'h4:
outbyte <= inword[39:32];
3'h5:
outbyte <= inword[47:40];
3'h6:
outbyte <= inword[55:48];
3'h7:
outbyte <= inword[63:56];
default:
outbyte <= 8'bxxxxxxxx;
endcase
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__HA_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__HA_BEHAVIORAL_PP_V
/**
* ha: Half adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__ha (
VPWR,
VGND,
COUT,
SUM ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output COUT;
output SUM ;
input A ;
input B ;
// Local signals
wire and0_out_COUT ;
wire u_vpwr_vgnd0_out_COUT;
wire xor0_out_SUM ;
wire u_vpwr_vgnd1_out_SUM ;
// Name Output Other arguments
and and0 (and0_out_COUT , A, B );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_COUT, and0_out_COUT, VPWR, VGND);
buf buf0 (COUT , u_vpwr_vgnd0_out_COUT );
xor xor0 (xor0_out_SUM , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_SUM , xor0_out_SUM, VPWR, VGND );
buf buf1 (SUM , u_vpwr_vgnd1_out_SUM );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__HA_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__XOR2_BEHAVIORAL_V
`define SKY130_FD_SC_LS__XOR2_BEHAVIORAL_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__xor2 (
X,
A,
B
);
// Module ports
output X;
input A;
input B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X, B, A );
buf buf0 (X , xor0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__XOR2_BEHAVIORAL_V |
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: fifo32_shallow.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 16.0.0 Build 211 04/27/2016 SJ Lite Edition
// ************************************************************
//Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus Prime License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo32_shallow (
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input [31:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [31:0] q;
output rdempty;
output wrfull;
wire [31:0] sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire [31:0] q = sub_wire0[31:0];
wire rdempty = sub_wire1;
wire wrfull = sub_wire2;
dcfifo dcfifo_component (
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.rdempty (sub_wire1),
.wrfull (sub_wire2),
.aclr (),
.eccstatus (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Cyclone IV E",
dcfifo_component.lpm_numwords = 4,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 32,
dcfifo_component.lpm_widthu = 2,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "4"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "32"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "32"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "2"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo32_shallow_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKINVLP_BLACKBOX_V
`define SKY130_FD_SC_LP__CLKINVLP_BLACKBOX_V
/**
* clkinvlp: Lower power Clock tree inverter.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__clkinvlp (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKINVLP_BLACKBOX_V
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_wdq_ctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Write Decomposition Queue Control
// Top level Module: jbi_min_wdq_ctl
// Where Instantiated: jbi_min_wdq
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_min_wdq_ctl(/*AUTOARG*/
// Outputs
min_csr_perf_dma_wr8, wdq_wr_en, wdq_wdata, wdq_wdata_ecc0,
wdq_wdata_ecc1, wdq_wdata_ecc2, wdq_wdata_ecc3, wdq_waddr, wdq_rd_en,
wdq_raddr, wdq_rdq0_push, wdq_rdq1_push, wdq_rdq2_push,
wdq_rdq3_push, wdq_rdq_wdata, wdq_rhq0_push, wdq_rhq1_push,
wdq_rhq2_push, wdq_rhq3_push, wdq_rhq_wdata, wdq_rq_tag_byps,
wdq_wr_vld, min_aok_on, min_aok_off,
// Inputs
clk, rst_l, csr_jbi_config2_iq_high, csr_jbi_config2_iq_low,
csr_jbi_config2_ord_wr, csr_jbi_config2_ord_rd, io_jbi_j_ad_ff,
io_jbi_j_adtype_ff, parse_wdq_push, parse_sctag_req, parse_hdr,
parse_rw, parse_subline_req, parse_install_mode, parse_data_err,
parse_err_nonex_rd, rdq0_full, rdq1_full, rdq2_full, rdq3_full,
wdq_rdata, rhq0_full, rhq1_full, rhq2_full, rhq3_full
);
input clk;
input rst_l;
// CSR Block Interface
input [3:0] csr_jbi_config2_iq_high;
input [3:0] csr_jbi_config2_iq_low;
input csr_jbi_config2_ord_wr;
input csr_jbi_config2_ord_rd;
output min_csr_perf_dma_wr8;
// Parse Block Interface
input [127:0] io_jbi_j_ad_ff;
input [`JBI_ADTYPE_JID_HI:`JBI_ADTYPE_JID_LO] io_jbi_j_adtype_ff;
input parse_wdq_push;
input [2:0] parse_sctag_req;
input parse_hdr;
input parse_rw;
input parse_subline_req;
input parse_install_mode;
input parse_data_err;
input parse_err_nonex_rd;
// WDQ Interface
input rdq0_full;
input rdq1_full;
input rdq2_full;
input rdq3_full;
input [`JBI_WDQ_WIDTH-1:0] wdq_rdata;
output wdq_wr_en;
output [127:0] wdq_wdata;
output [6:0] wdq_wdata_ecc0;
output [6:0] wdq_wdata_ecc1;
output [6:0] wdq_wdata_ecc2;
output [6:0] wdq_wdata_ecc3;
output [`JBI_WDQ_ADDR_WIDTH-1:0] wdq_waddr;
output wdq_rd_en;
output [`JBI_WDQ_ADDR_WIDTH-1:0] wdq_raddr;
// Request Data Queue Interface
output wdq_rdq0_push;
output wdq_rdq1_push;
output wdq_rdq2_push;
output wdq_rdq3_push;
output [`JBI_RDQ_WIDTH-1:0] wdq_rdq_wdata;
// Request Header Queue Interface
input rhq0_full;
input rhq1_full;
input rhq2_full;
input rhq3_full;
output wdq_rhq0_push;
output wdq_rhq1_push;
output wdq_rhq2_push;
output wdq_rhq3_push;
output [`JBI_RHQ_WIDTH-1:0] wdq_rhq_wdata;
// Request Tag Queue Interface
output wdq_rq_tag_byps;
// Write Tracker Interface
output wdq_wr_vld;
// Memory Out Interface
output min_aok_on;
output min_aok_off;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire min_csr_perf_dma_wr8;
wire wdq_wr_en;
reg [127:0] wdq_wdata;
reg [6:0] wdq_wdata_ecc0;
reg [6:0] wdq_wdata_ecc1;
reg [6:0] wdq_wdata_ecc2;
reg [6:0] wdq_wdata_ecc3;
wire [`JBI_WDQ_ADDR_WIDTH-1:0] wdq_waddr;
wire wdq_rd_en;
wire [`JBI_WDQ_ADDR_WIDTH-1:0] wdq_raddr;
wire wdq_rdq0_push;
wire wdq_rdq1_push;
wire wdq_rdq2_push;
wire wdq_rdq3_push;
wire [`JBI_RDQ_WIDTH-1:0] wdq_rdq_wdata;
wire wdq_rhq0_push;
wire wdq_rhq1_push;
wire wdq_rhq2_push;
wire wdq_rhq3_push;
reg [`JBI_RHQ_WIDTH-1:0] wdq_rhq_wdata;
wire wdq_rq_tag_byps;
wire wdq_wr_vld;
wire min_aok_on;
wire min_aok_off;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter POP_HDR = 3'b001,
POP_WRI = 3'b010,
POP_WRM = 3'b100;
parameter POP_HDR_BIT = 0,
POP_WRI_BIT = 1,
POP_WRM_BIT = 2,
POP_SM_WIDTH = 3;
//
// Code start here
//
wire [POP_SM_WIDTH-1:0] pop_sm;
wire [`JBI_WDQ_ADDR_WIDTH:0] wptr;
wire [`JBI_WDQ_ADDR_WIDTH:0] rptr;
wire [`JBI_WDQ_ADDR_WIDTH:0] wdq_level;
wire [2:0] wr_word_cnt;
wire [5:3] wrm_addr;
wire [`JBI_WDQ_DEPTH-1:0] wdq_data_err;
wire tag_byps;
reg [POP_SM_WIDTH-1:0] next_pop_sm;
reg [`JBI_WDQ_ADDR_WIDTH:0] next_wptr;
reg [`JBI_WDQ_ADDR_WIDTH:0] next_rptr;
reg [`JBI_WDQ_ADDR_WIDTH:0] next_wdq_level;
reg [2:0] next_wr_word_cnt;
reg [5:3] next_wrm_addr;
reg [`JBI_WDQ_DEPTH-1:0] next_wdq_data_err;
reg next_tag_byps;
wire [63:0] pop_hdr;
wire [63:0] wrm_be;
wire [7:0] be;
wire [63:0] next_pop_hdr;
wire [63:0] next_wrm_be;
reg [7:0] next_be;
wire next_min_full;
wire next_min_csr_perf_dma_wr8;
wire pop_hdr_en;
wire wrm_be_en;
wire be_en;
wire wr_word_cnt_rst_l;
wire [`JBI_SCTAG_TAG_WIDTH-1:0] push_hdr_tag;
reg [4:0] push_hdr_addr_lo;
wire [63:0] push_hdr;
wire wdq_drdy;
wire wdq_rdata_rw;
wire [`JBI_SCTAG_TAG_WIDTH-1:0] wdq_rdata_tag;
wire [2:0] wdq_rdata_req;
reg [7:0] be_mask;
reg [2:0] size;
wire addr2;
reg addr1;
reg addr0;
wire addr1_0;
wire addr1_1;
reg addr0_0;
reg addr0_1;
wire addr0_0_0;
wire addr0_0_1;
wire addr0_1_0;
wire addr0_1_1;
wire [2:0] wrm_start_addr;
wire incr_wr_word_cnt;
wire [63:0] wrm_hdr;
wire wdq_rdq_push;
wire wdq_rhq_push;
wire [`JBI_SCTAG_TAG_WIDTH-1:0] pop_tag;
wire wdq_pop;
reg [1:0] sctag_num;
wire [`JBI_WDQ_ADDR_WIDTH:0] wptr_d1;
reg [1:0] stall_sctag_num;
wire wdq_stall;
wire push_wr8;
wire min_full;
wire min_full_d1;
wire [6:0] ecc0;
wire [6:0] ecc1;
wire [6:0] ecc2;
wire [6:0] ecc3;
wire [`JBI_SCTAG_TAG_WIDTH-1:0] wdq_rhq_wdata_tag;
wire wdq_rhq_wdata_rw;
//*******************************************************************************
// Push Inbound Memory Request
//*******************************************************************************
// if read to non-existent memory, treat as subline read to addr zero with
// error bit set in ctag
assign push_hdr_tag[`JBI_SCTAG_TAG_JID_HI:`JBI_SCTAG_TAG_JID_LO] = io_jbi_j_adtype_ff[`JBI_ADTYPE_JID_HI:`JBI_ADTYPE_JID_LO];
assign push_hdr_tag[`JBI_SCTAG_TAG_INSTALL] = parse_install_mode;
assign push_hdr_tag[`JBI_SCTAG_TAG_ERR] = parse_err_nonex_rd;
assign push_hdr_tag[`JBI_SCTAG_TAG_SUBLINE] = parse_subline_req;
assign push_hdr_tag[`JBI_SCTAG_TAG_RW] = parse_rw;
assign push_hdr_tag[`JBI_SCTAG_TAG_WIDTH-1:`JBI_SCTAG_TAG_WIDTH-2] = `JBI_CTAG_PRE;
always @ ( /*AUTOSENSE*/io_jbi_j_ad_ff or parse_subline_req) begin
if (parse_subline_req)
push_hdr_addr_lo[4:0] = {io_jbi_j_ad_ff[4], 4'd0};
else
push_hdr_addr_lo[4:0] = 5'd0;
end
assign push_hdr[`JBI_SCTAG_IN_ADDR_HI:`JBI_SCTAG_IN_ADDR_LO] = {io_jbi_j_ad_ff[39:5], push_hdr_addr_lo[4:0]};
assign push_hdr[`JBI_SCTAG_IN_SZ_HI:`JBI_SCTAG_IN_SZ_LO] = 3'd0;
assign push_hdr[`JBI_SCTAG_IN_RSV0] = 1'b0;
assign push_hdr[`JBI_SCTAG_IN_TAG_HI:`JBI_SCTAG_IN_TAG_LO] = push_hdr_tag[`JBI_SCTAG_TAG_WIDTH-1:0];
assign push_hdr[`JBI_SCTAG_IN_REQ_HI:`JBI_SCTAG_IN_REQ_LO] = parse_sctag_req;
assign push_hdr[`JBI_SCTAG_IN_POISON] = 1'b0;
assign push_hdr[`JBI_SCTAG_IN_RSV1_HI:`JBI_SCTAG_IN_RSV1_LO] = 4'd0;
//-------------------
// Pointer Management
//-------------------
always @ ( /*AUTOSENSE*/parse_wdq_push or wptr) begin
if (parse_wdq_push)
next_wptr = wptr + 1'b1;
else
next_wptr = wptr;
end
// Note: Write CS and Addr are registered before connecting to memory element.
// When parse_wdq_push is asserted, and the data is valid at dout 2 cycles later
//
// | 0 | 1 | 2 | 3 | 4 |
// ____ ____ ____ ____ ____ ____
// ___/ \____/ \____/ \____/ \____/ \____/ \____
// _________
// push ____/ \________________________________________________
// ______ _______________________________________
// csn_wr \_________/
// ______________ _______________________________________
// csn_wr_ff \_________/
// _________________________ _____________________________________
// rdata _________________________X___Valid__Dout_______________________
always @ ( /*AUTOSENSE*/io_jbi_j_ad_ff or parse_hdr or push_hdr) begin
if (parse_hdr)
wdq_wdata = {io_jbi_j_ad_ff[127:64], push_hdr};
else
wdq_wdata = io_jbi_j_ad_ff[127:0];
end
assign wdq_waddr = wptr[`JBI_WDQ_ADDR_WIDTH-1:0];
assign wdq_wr_en = rst_l & parse_wdq_push;
assign wdq_drdy = ~(rptr == wptr_d1);
//-------------------------------------------------------------------------------
// Error Handling
// - for cacheline writes, poison ecc if parity or ue error
// * cacheline writes goes to dram vi L2 and L2 checks ecc (over 32 bits
// before sending it to dram
// - for wr8, ignore ecc and set poison bit in header
// * wr8 goes to cache which generates its own ecc, therefore wants poison
// bit in header and ignores the jbi_scbuf*_ecc
// * separate err array to keep track of data errors
//-------------------------------------------------------------------------------
/* zzecc_sctag_pgen_32b AUTO_TEMPLATE (
.dout (),
.parity (ecc@[]),
.din (io_jbi_j_ad_ff[((@+1)*32-1):(@*32)]),
); */
zzecc_sctag_pgen_32b u_wdq_ecc0 (/*AUTOINST*/
// Outputs
.dout (), // Templated
.parity(ecc0[6:0]), // Templated
// Inputs
.din (io_jbi_j_ad_ff[((0+1)*32-1):(0*32)])); // Templated
zzecc_sctag_pgen_32b u_wdq_ecc1 (/*AUTOINST*/
// Outputs
.dout (), // Templated
.parity(ecc1[6:0]), // Templated
// Inputs
.din (io_jbi_j_ad_ff[((1+1)*32-1):(1*32)])); // Templated
zzecc_sctag_pgen_32b u_wdq_ecc2 (/*AUTOINST*/
// Outputs
.dout (), // Templated
.parity(ecc2[6:0]), // Templated
// Inputs
.din (io_jbi_j_ad_ff[((2+1)*32-1):(2*32)])); // Templated
zzecc_sctag_pgen_32b u_wdq_ecc3 (/*AUTOINST*/
// Outputs
.dout (), // Templated
.parity(ecc3[6:0]), // Templated
// Inputs
.din (io_jbi_j_ad_ff[((3+1)*32-1):(3*32)])); // Templated
always @ ( /*AUTOSENSE*/ecc0 or ecc1 or ecc2 or ecc3 or parse_data_err) begin
if (parse_data_err) begin
//poison ecc
wdq_wdata_ecc0 = { ecc0[6:2], ~ecc0[1:0] };
wdq_wdata_ecc1 = { ecc1[6:2], ~ecc1[1:0] };
wdq_wdata_ecc2 = { ecc2[6:2], ~ecc2[1:0] };
wdq_wdata_ecc3 = { ecc3[6:2], ~ecc3[1:0] };
end
else begin
wdq_wdata_ecc0 = ecc0[6:0];
wdq_wdata_ecc1 = ecc1[6:0];
wdq_wdata_ecc2 = ecc2[6:0];
wdq_wdata_ecc3 = ecc3[6:0];
end
end
always @ ( /*AUTOSENSE*/parse_data_err or parse_wdq_push
or wdq_data_err or wptr) begin
next_wdq_data_err = wdq_data_err;
if (parse_wdq_push)
next_wdq_data_err[wptr[`JBI_WDQ_ADDR_WIDTH-1:0]] = parse_data_err;
end
//*******************************************************************************
// Pop Queue
//*******************************************************************************
assign wdq_rdata_tag = wdq_rdata[`JBI_SCTAG_IN_TAG_HI:`JBI_SCTAG_IN_TAG_LO];
assign wdq_rdata_rw = wdq_rdata_tag[`JBI_SCTAG_TAG_RW];
assign wdq_rdata_req = wdq_rdata[`JBI_SCTAG_IN_REQ_HI:`JBI_SCTAG_IN_REQ_LO];
assign pop_hdr_en = pop_sm[POP_HDR_BIT] & wdq_drdy & ~wdq_stall;
assign next_pop_hdr = wdq_rdata[63:0];
assign pop_tag = pop_hdr[`JBI_SCTAG_IN_TAG_HI:`JBI_SCTAG_IN_TAG_LO];
//-------------------
// Pop State Machine
//-------------------
always @ ( /*AUTOSENSE*/be or be_mask or pop_sm or pop_tag or rst_l
or wdq_drdy or wdq_rdata_req or wdq_rdata_rw or wdq_stall
or wr_word_cnt) begin
if (~rst_l)
next_pop_sm = POP_HDR;
else begin
case (pop_sm)
POP_HDR: begin
// if write, proceed to push data
if (wdq_drdy & ~wdq_stall & ~wdq_rdata_rw) begin
if (wdq_rdata_req[`JBI_SCTAG_REQ_WR8_BIT])
next_pop_sm = POP_WRM;
else
next_pop_sm = POP_WRI;
end
else
next_pop_sm = POP_HDR;
end
POP_WRI: begin // once in this state, rdq guaranteed to have enough space
if (wr_word_cnt == 3'd3)
next_pop_sm = POP_HDR;
else
next_pop_sm = POP_WRI;
end
POP_WRM: begin
if ( ~wdq_stall
& ~|(be & be_mask)
& ( wr_word_cnt == 3'd7
| (wr_word_cnt[0] & pop_tag[`JBI_SCTAG_TAG_SUBLINE])))
next_pop_sm = POP_HDR;
else
next_pop_sm = POP_WRM;
end
// CoverMeter line_off
default: begin
next_pop_sm = {POP_SM_WIDTH{1'bx}};
//synopsys translate_off
$dispmon ("jbi_min_wdq_ctl", 49,"%d %m: pop_sm=%b", $time, pop_sm);
//synopsys translate_on
end
// CoverMeter line_on
endcase
end
end
//-------------------
// Word Count
// - in WRI mode, this counter counts quadword being pushed into rdq
// - in WRM(WR8) mode, this counter counts double word, or more specifically,
// keeps track of which 8-bit chunk of BE that is currently being worked on
//-------------------
assign incr_wr_word_cnt = pop_sm[POP_WRI_BIT]
|(pop_sm[POP_WRM_BIT]
& (~|(be & be_mask))
& ~wdq_stall);
assign wr_word_cnt_rst_l = rst_l & ~pop_sm[POP_HDR_BIT];
always @ ( /*AUTOSENSE*/incr_wr_word_cnt or wr_word_cnt) begin
if (incr_wr_word_cnt)
next_wr_word_cnt = wr_word_cnt + 1'b1;
else
next_wr_word_cnt = wr_word_cnt;
end
//-------------------
// Pointer Management
//-------------------
assign wdq_pop = (pop_sm[POP_HDR_BIT] & wdq_drdy & ~wdq_stall)
| pop_sm[POP_WRI_BIT]
| (pop_sm[POP_WRM_BIT] //done with current wrm quadword
& (~|(be & be_mask))
& wr_word_cnt[0]
& ~wdq_stall);
always @ ( /*AUTOSENSE*/rptr or wdq_pop) begin
if (wdq_pop)
next_rptr = rptr + 1'b1;
else
next_rptr = rptr;
end
assign wdq_raddr = next_rptr[`JBI_WDQ_ADDR_WIDTH-1:0];
assign wdq_rd_en = next_rptr != wptr;
//*******************************************************************************
// Decompose WRM at Top of WDQ
//*******************************************************************************
//------------------------------------------------------
// BE
// - find first string of 1's in an 8-bit chunk of BE,
// mask them out, and repeat until be is all 0's then
// load next 8-bit chunk of BE
//------------------------------------------------------
// at the beginning of wrm txn, load entire 64 bit BE
assign wrm_be_en = pop_sm[POP_HDR_BIT];
assign next_wrm_be = wdq_rdata[127:64];
// as each 8-bit BE dwindle down to all zeros, load next 8-bit be chunk
// - for subline WRM (NCWR) only 2 8-bit chunk where as WRM has 8 8-bit chunks
assign be_en = pop_sm[POP_HDR_BIT]
| (pop_sm[POP_WRM_BIT] & ~wdq_stall);
always @ ( /*AUTOSENSE*/be or be_mask or incr_wr_word_cnt
or next_wr_word_cnt or pop_sm or pop_tag or wdq_rdata
or wdq_rdata_tag or wrm_be) begin
if (pop_sm[POP_HDR_BIT]) begin
if (wdq_rdata_tag[`JBI_SCTAG_TAG_SUBLINE])
next_be = wdq_rdata[119:112];
else
next_be = wdq_rdata[71:64];
end
else if (~incr_wr_word_cnt)
next_be = be & be_mask;
else begin
if (pop_tag[`JBI_SCTAG_TAG_SUBLINE])
next_be = wrm_be[63:56];
else
case (next_wr_word_cnt[2:0])
3'd0: next_be = wrm_be[ 7: 0];
3'd1: next_be = wrm_be[ 15: 8];
3'd2: next_be = wrm_be[ 23: 16];
3'd3: next_be = wrm_be[ 31: 24];
3'd4: next_be = wrm_be[ 39: 32];
3'd5: next_be = wrm_be[ 47: 40];
3'd6: next_be = wrm_be[ 55: 48];
3'd7: next_be = wrm_be[ 63: 56];
// CoverMeter line_off
default: next_be = {8{1'bx}};
// CoverMeter line_on
endcase
end
end
// - after determining the position and size of
// the first string of 1's in BE, mask it out for the
// next iteration
// - also mask out 1 bit to the left since know it's a 0 - reduce logic
always @ ( /*AUTOSENSE*/addr0 or addr1 or addr2 or size) begin
case ({addr2, addr1, addr0}) //starting address
3'b0: begin
case (size[2:0])
3'd1: be_mask = 8'b1111_1100;
3'd2: be_mask = 8'b1111_1000;
3'd3: be_mask = 8'b1111_0000;
3'd4: be_mask = 8'b1110_0000;
3'd5: be_mask = 8'b1100_0000;
3'd6: be_mask = 8'b1000_0000;
default: be_mask = {8{1'b0}};
endcase
end
3'd1: begin
case (size[2:0])
3'd1: be_mask = 8'b1111_1000;
3'd2: be_mask = 8'b1111_0000;
3'd3: be_mask = 8'b1110_0000;
3'd4: be_mask = 8'b1100_0000;
3'd5: be_mask = 8'b1000_0000;
default: be_mask = {8{1'b0}};
endcase
end
3'd2: begin
case (size[2:0])
3'd1: be_mask = 8'b1111_0000;
3'd2: be_mask = 8'b1110_0000;
3'd3: be_mask = 8'b1100_0000;
3'd4: be_mask = 8'b1000_0000;
default: be_mask = {8{1'b0}};
endcase
end
3'd3: begin
case (size[2:0])
3'd1: be_mask = 8'b1110_0000;
3'd2: be_mask = 8'b1100_0000;
3'd3: be_mask = 8'b1000_0000;
default: be_mask = {8{1'b0}};
endcase
end
3'd4: begin
case (size[2:0])
3'd1: be_mask = 8'b1100_0000;
3'd2: be_mask = 8'b1000_0000;
default: be_mask = {8{1'b0}};
endcase
end
3'd5: begin
if (size[2:0] == 3'd1)
be_mask = 8'b1000_0000;
else
be_mask = {8{1'b0}};
end
default: be_mask = {8{1'b0}};
endcase
end
//------------------------------
// Starting Address
//------------------------------
// addr[2:0] is starting byte
// - from right to left, search for first "1"
assign addr2 = ~|be[3:0];
assign addr1_0 = ~|be[1:0];
assign addr1_1 = ~|be[5:4];
assign addr0_0_0 = ~be[0];
assign addr0_0_1 = ~be[2];
assign addr0_1_0 = ~be[4];
assign addr0_1_1 = ~be[6];
always @ ( /*AUTOSENSE*/addr1_0 or addr1_1 or addr2) begin
if (addr2)
addr1 = addr1_1;
else
addr1 = addr1_0;
end
always @ ( /*AUTOSENSE*/addr0_0_0 or addr0_0_1 or addr1_0) begin
if (addr1_0)
addr0_0 = addr0_0_1;
else
addr0_0 = addr0_0_0;
end
always @ ( /*AUTOSENSE*/addr0_1_0 or addr0_1_1 or addr1_1) begin
if (addr1_1)
addr0_1 = addr0_1_1;
else
addr0_1 = addr0_1_0;
end
always @ ( /*AUTOSENSE*/addr0_0 or addr0_1 or addr2) begin
if (addr2)
addr0 = addr0_1;
else
addr0 = addr0_0;
end
assign wrm_start_addr[2:0] = {addr2, addr1, addr0};
//wr8_addr[5:3]
always @ ( /*AUTOSENSE*/incr_wr_word_cnt or next_pop_sm or pop_sm
or wdq_rdata or wrm_addr) begin
if (pop_sm[POP_HDR_BIT] & next_pop_sm[POP_WRM_BIT])
next_wrm_addr[5:3] = wdq_rdata[5:3];
else begin
if (incr_wr_word_cnt)
next_wrm_addr[5:3] = wrm_addr[5:3] + 1'b1;
else
next_wrm_addr[5:3] = wrm_addr[5:3];
end
end
//---------------
// Size 1-8 bytes
//---------------
always @ ( /*AUTOSENSE*/addr0 or addr1 or addr2 or be) begin
case ({addr2, addr1, addr0})
3'd0: begin
if (~be[1])
size = 3'd1;
else if (~be[2])
size = 3'd2;
else if (~be[3])
size = 3'd3;
else if (~be[4])
size = 3'd4;
else if (~be[5])
size = 3'd5;
else if (~be[6])
size = 3'd6;
else if (~be[7])
size = 3'd7;
else
size = 3'd0;
end
3'd1: begin
if (~be[2])
size = 3'd1;
else if (~be[3])
size = 3'd2;
else if (~be[4])
size = 3'd3;
else if (~be[5])
size = 3'd4;
else if (~be[6])
size = 3'd5;
else if (~be[7])
size = 3'd6;
else
size = 3'd7;
end
3'd2: begin
if (~be[3])
size = 3'd1;
else if (~be[4])
size = 3'd2;
else if (~be[5])
size = 3'd3;
else if (~be[6])
size = 3'd4;
else if (~be[7])
size = 3'd5;
else
size = 3'd6;
end
3'd3: begin
if (~be[4])
size = 3'd1;
else if (~be[5])
size = 3'd2;
else if (~be[6])
size = 3'd3;
else if (~be[7])
size = 3'd4;
else
size = 3'd5;
end
3'd4: begin
if (~be[5])
size = 3'd1;
else if (~be[6])
size = 3'd2;
else if (~be[7])
size = 3'd3;
else
size = 3'd4;
end
3'd5: begin
if (~be[6])
size = 3'd1;
else if (~be[7])
size = 3'd2;
else
size = 3'd3;
end
3'd6: begin
if (~be[7])
size = 3'd1;
else
size = 3'd2;
end
3'd7: size = 3'd1;
default: size = 3'bxxx;
endcase
end
//---------------
// WRM Header
//---------------
assign wrm_hdr[`JBI_SCTAG_IN_ADDR_HI:`JBI_SCTAG_IN_ADDR_LO] = {pop_hdr[`JBI_SCTAG_IN_ADDR_HI:6],
wrm_addr[5:3],
wrm_start_addr[2:0]};
assign wrm_hdr[`JBI_SCTAG_IN_SZ_HI:`JBI_SCTAG_IN_SZ_LO] = size[2:0];
assign wrm_hdr[`JBI_SCTAG_IN_REQ_HI:`JBI_SCTAG_IN_RSV0] = pop_hdr[`JBI_SCTAG_IN_REQ_HI:`JBI_SCTAG_IN_RSV0];
assign wrm_hdr[`JBI_SCTAG_IN_POISON] = wdq_data_err[rptr[`JBI_WDQ_ADDR_WIDTH-1:0]];
assign wrm_hdr[`JBI_SCTAG_IN_RSV1_HI:`JBI_SCTAG_IN_RSV1_LO] = pop_hdr[`JBI_SCTAG_IN_RSV1_HI:`JBI_SCTAG_IN_RSV1_LO];
//*******************************************************************************
// Push into SCTAG Header and Data Queues
//*******************************************************************************
always @ ( /*AUTOSENSE*/pop_hdr or pop_sm or wdq_rdata) begin
if (pop_sm[POP_HDR_BIT])
sctag_num = wdq_rdata[`JBI_AD_BTU_NUM_HI:`JBI_AD_BTU_NUM_LO];
else
sctag_num = pop_hdr[`JBI_AD_BTU_NUM_HI:`JBI_AD_BTU_NUM_LO];
end
assign push_wr8 = pop_sm[POP_WRM_BIT] & (|be) & ~wdq_stall;
//------------------------
// To Data Header Queue
//------------------------
assign wdq_rdq_push = push_wr8
| pop_sm[POP_WRI_BIT];
assign wdq_rdq0_push = wdq_rdq_push & sctag_num==2'd0;
assign wdq_rdq1_push = wdq_rdq_push & sctag_num==2'd1;
assign wdq_rdq2_push = wdq_rdq_push & sctag_num==2'd2;
assign wdq_rdq3_push = wdq_rdq_push & sctag_num==2'd3;
assign wdq_rdq_wdata = wdq_rdata;
//------------------------
// To Request Header Queue
//------------------------
// In order to guarantee that corresponding write data is always available
// when the header is available, need to push write header the same time as
// the 3rd cycle of data (takes 4 cpu cycles to push 128bits to sctag)
assign wdq_rhq_push = (pop_sm[POP_HDR_BIT] & wdq_drdy & ~wdq_stall & wdq_rdata_rw)
| (pop_sm[POP_WRI_BIT] & wr_word_cnt==3'd2)
| push_wr8;
assign wdq_rhq0_push = wdq_rhq_push & sctag_num==2'd0;
assign wdq_rhq1_push = wdq_rhq_push & sctag_num==2'd1;
assign wdq_rhq2_push = wdq_rhq_push & sctag_num==2'd2;
assign wdq_rhq3_push = wdq_rhq_push & sctag_num==2'd3;
always @ ( /*AUTOSENSE*/pop_hdr or pop_sm or wdq_rdata or wrm_hdr) begin
case (pop_sm)
POP_HDR: wdq_rhq_wdata = wdq_rdata[63:0];
POP_WRI: wdq_rhq_wdata = pop_hdr;
POP_WRM: wdq_rhq_wdata = wrm_hdr;
// CoverMeter line_off
default: wdq_rhq_wdata = wdq_rdata[63:0];
// CoverMeter line_on
endcase
end
// Writes to the same cache line do not have what for previous write acks
// - only apply to WRM and NCWR txns for simplicity
// - all other writes and read txn must wait for previous write acks unless
// ordering is not turned on
// - wr-wr ordering must be enabled for wr-rd ordering to work
always @ ( /*AUTOSENSE*/next_pop_sm or push_wr8 or tag_byps) begin
if (next_pop_sm[POP_HDR_BIT])
next_tag_byps = 1'b0;
else if (push_wr8)
next_tag_byps = 1'b1;
else
next_tag_byps = tag_byps;
end
assign wdq_rhq_wdata_tag = wdq_rhq_wdata[`JBI_SCTAG_IN_TAG_HI:`JBI_SCTAG_IN_TAG_LO];
assign wdq_rhq_wdata_rw = wdq_rhq_wdata_tag[`JBI_SCTAG_TAG_RW];
assign wdq_rq_tag_byps = tag_byps
| ( wdq_rhq_wdata_rw & ~csr_jbi_config2_ord_rd) // turn off wr-rd ordering
| (~wdq_rhq_wdata_rw & ~csr_jbi_config2_ord_wr); // turn off wr-wr ordering
//------------------------
// Increment Write Count
//------------------------
assign wdq_wr_vld = (pop_sm[POP_WRI_BIT] & wr_word_cnt==3'd3)
| push_wr8;
//*******************************************************************************
// Flow Control
//*******************************************************************************
//--------------------------
// Restrict Pushing into RQ
//--------------------------
always @ ( /*AUTOSENSE*/pop_hdr or pop_sm or wdq_rdata) begin
if (pop_sm[POP_HDR_BIT])
stall_sctag_num = wdq_rdata[`JBI_AD_BTU_NUM_HI:`JBI_AD_BTU_NUM_LO];
else
stall_sctag_num = pop_hdr[`JBI_AD_BTU_NUM_HI:`JBI_AD_BTU_NUM_LO];
end
assign wdq_stall = ((rhq0_full | rdq0_full) & stall_sctag_num==2'd0)
| ((rhq1_full | rdq1_full) & stall_sctag_num==2'd1)
| ((rhq2_full | rdq2_full) & stall_sctag_num==2'd2)
| ((rhq3_full | rdq3_full) & stall_sctag_num==2'd3);
//--------------------------
// Restrict JBUS
//--------------------------
always @ ( /*AUTOSENSE*/parse_wdq_push or wdq_level or wdq_pop) begin
case ({parse_wdq_push, wdq_pop}) // {incr, decr}
2'b00,
2'b11: next_wdq_level = wdq_level;
2'b01: next_wdq_level = wdq_level - 1'b1;
2'b10: next_wdq_level = wdq_level + 1'b1;
default: next_wdq_level = {`JBI_WDQ_ADDR_WIDTH+1{1'bx}};
endcase
end
assign next_min_full = (~min_full & next_wdq_level >= {1'b0, csr_jbi_config2_iq_high[3:0]} )
| ( min_full & ~(next_wdq_level <= {1'b0, csr_jbi_config2_iq_low[3:0]}) );
assign min_aok_off = min_full & ~min_full_d1;
assign min_aok_on = ~min_full & min_full_d1;
//*******************************************************************************
// Performance Counters
//*******************************************************************************
assign next_min_csr_perf_dma_wr8 = wdq_rhq_push & pop_sm[POP_WRM_BIT];
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns #(POP_SM_WIDTH) u_dff_pop_sm
(.din(next_pop_sm),
.clk(clk),
.q(pop_sm)
);
dff_ns #(`JBI_WDQ_ADDR_WIDTH+1) u_dff_wptr_d1
(.din(wptr),
.clk(clk),
.q(wptr_d1)
);
dff_ns #(1) u_dff_min_full_d1
(.din(min_full),
.clk(clk),
.q(min_full_d1)
);
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
dffrl_ns #(`JBI_WDQ_ADDR_WIDTH+1) u_dffrl_wptr
(.din(next_wptr),
.clk(clk),
.rst_l(rst_l),
.q(wptr)
);
dffrl_ns #(`JBI_WDQ_ADDR_WIDTH+1) u_dffrl_rptr
(.din(next_rptr),
.clk(clk),
.rst_l(rst_l),
.q(rptr)
);
dffrl_ns #(3) u_dffrl_wr_word_cnt
(.din(next_wr_word_cnt),
.clk(clk),
.rst_l(wr_word_cnt_rst_l),
.q(wr_word_cnt)
);
dffrl_ns #(3) u_dffrl_wrm_addr
(.din(next_wrm_addr[5:3]),
.clk(clk),
.rst_l(rst_l),
.q(wrm_addr[5:3])
);
dffrl_ns #(`JBI_WDQ_ADDR_WIDTH+1) u_dffrl_wdq_level
(.din(next_wdq_level),
.clk(clk),
.rst_l(rst_l),
.q(wdq_level)
);
dffrl_ns #(1) u_dffrl_min_full
(.din(next_min_full),
.clk(clk),
.rst_l(rst_l),
.q(min_full)
);
dffrl_ns #(1) u_dffrl_tag_byps
(.din(next_tag_byps),
.clk(clk),
.rst_l(rst_l),
.q(tag_byps)
);
dffrl_ns #(`JBI_WDQ_DEPTH) u_dffrl_wdq_data_err
(.din(next_wdq_data_err),
.clk(clk),
.rst_l(rst_l),
.q(wdq_data_err)
);
dffrl_ns #(1) u_dffrl_min_csr_perf_dma_wr8
(.din(next_min_csr_perf_dma_wr8),
.clk(clk),
.rst_l(rst_l),
.q(min_csr_perf_dma_wr8)
);
//*******************************************************************************
// DFFRLE Instantiations
//*******************************************************************************
dffrle_ns #(64) u_dffrle_pop_hdr
(.din(next_pop_hdr),
.clk(clk),
.en(pop_hdr_en),
.rst_l(rst_l),
.q(pop_hdr)
);
dffrle_ns #(64) u_dffrle_wrm_be
(.din(next_wrm_be),
.clk(clk),
.en(wrm_be_en),
.rst_l(rst_l),
.q(wrm_be)
);
dffrle_ns #(8) u_dffrle_be
(.din(next_be),
.clk(clk),
.en(be_en),
.rst_l(rst_l),
.q(be)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
wire wdq_empty = rptr == wptr;
wire wdq_full = wptr[`JBI_WDQ_ADDR_WIDTH] != rptr[`JBI_WDQ_ADDR_WIDTH]
& wptr[`JBI_WDQ_ADDR_WIDTH-1:0] == rptr[`JBI_WDQ_ADDR_WIDTH-1:0];
always @ ( /*AUTOSENSE*/parse_wdq_push or wdq_full) begin
@clk;
if (wdq_full && parse_wdq_push)
$dispmon ("jbi_min_wdq_ctl", 49,"%d %m: ERROR - WDQ overflow!", $time);
end
always @ ( /*AUTOSENSE*/wdq_empty or wdq_pop) begin
@clk;
if (wdq_empty && wdq_pop)
$dispmon ("jbi_min_wdq_ctl", 49,"%d %m: ERROR - WDQ underflow!", $time);
end
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-library-files:("../../../common/rtl/swrvr_macro.v")
// verilog-auto-sense-defines-constant:t
// End:
|
`timescale 1 ps / 1 ps
`include "song_ip_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module song_ip_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
task automatic COMPARE_LITE_DATA;
input expected;
input actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
$stop;
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.49d
// \ \ Application: netgen
// / / Filename: multiplier64fp.v
// /___/ /\ Timestamp: Wed Mar 26 18:32:40 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ecelrc/students/smirkhani/coregenFloatingPoints/virtex-6/multiplier/tmp/_cg/multiplier64fp.ngc /home/ecelrc/students/smirkhani/coregenFloatingPoints/virtex-6/multiplier/tmp/_cg/multiplier64fp.v
// Device : 6vhx250tff1154-2
// Input file : /home/ecelrc/students/smirkhani/coregenFloatingPoints/virtex-6/multiplier/tmp/_cg/multiplier64fp.ngc
// Output file : /home/ecelrc/students/smirkhani/coregenFloatingPoints/virtex-6/multiplier/tmp/_cg/multiplier64fp.v
// # of Modules : 1
// Design Name : multiplier64fp
// Xilinx : /misc/linuxws/packages/Xilinx/14.4/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module multiplier64fp (
clk, ce, rdy, a, b, result
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input ce;
output rdy;
input [63 : 0] a;
input [63 : 0] b;
output [63 : 0] result;
// synthesis translate_off
wire \U0/op_inst/FLT_PT_OP/MULT.OP/OP/sign_op ;
wire \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/HND_SHK/RDY ;
wire sig00000001;
wire sig00000002;
wire sig00000003;
wire sig00000004;
wire sig00000005;
wire sig00000006;
wire sig00000007;
wire sig00000008;
wire sig00000009;
wire sig0000000a;
wire sig0000000b;
wire sig0000000c;
wire sig0000000d;
wire sig0000000e;
wire sig0000000f;
wire sig00000010;
wire sig00000011;
wire sig00000012;
wire sig00000013;
wire sig00000014;
wire sig00000015;
wire sig00000016;
wire sig00000017;
wire sig00000018;
wire sig00000019;
wire sig0000001a;
wire sig0000001b;
wire sig0000001c;
wire sig0000001d;
wire sig0000001e;
wire sig0000001f;
wire sig00000020;
wire sig00000021;
wire sig00000022;
wire sig00000023;
wire sig00000024;
wire sig00000025;
wire sig00000026;
wire sig00000027;
wire sig00000028;
wire sig00000029;
wire sig0000002a;
wire sig0000002b;
wire sig0000002c;
wire sig0000002d;
wire sig0000002e;
wire sig0000002f;
wire sig00000030;
wire sig00000031;
wire sig00000032;
wire sig00000033;
wire sig00000034;
wire sig00000035;
wire sig00000036;
wire sig00000037;
wire sig00000038;
wire sig00000039;
wire sig0000003a;
wire sig0000003b;
wire sig0000003c;
wire sig0000003d;
wire sig0000003e;
wire sig0000003f;
wire sig00000040;
wire sig00000041;
wire sig00000042;
wire sig00000043;
wire sig00000044;
wire sig00000045;
wire sig00000046;
wire sig00000047;
wire sig00000048;
wire sig00000049;
wire sig0000004a;
wire sig0000004b;
wire sig0000004c;
wire sig0000004d;
wire sig0000004e;
wire sig0000004f;
wire sig00000050;
wire sig00000051;
wire sig00000052;
wire sig00000053;
wire sig00000054;
wire sig00000055;
wire sig00000056;
wire sig00000057;
wire sig00000058;
wire sig00000059;
wire sig0000005a;
wire sig0000005b;
wire sig0000005c;
wire sig0000005d;
wire sig0000005e;
wire sig0000005f;
wire sig00000060;
wire sig00000061;
wire sig00000062;
wire sig00000063;
wire sig00000064;
wire sig00000065;
wire sig00000066;
wire sig00000067;
wire sig00000068;
wire sig00000069;
wire sig0000006a;
wire sig0000006b;
wire sig0000006c;
wire sig0000006d;
wire sig0000006e;
wire sig0000006f;
wire sig00000070;
wire sig00000071;
wire sig00000072;
wire sig00000073;
wire sig00000074;
wire sig00000075;
wire sig00000076;
wire sig00000077;
wire sig00000078;
wire sig00000079;
wire sig0000007a;
wire sig0000007b;
wire sig0000007c;
wire sig0000007d;
wire sig0000007e;
wire sig0000007f;
wire sig00000080;
wire sig00000081;
wire sig00000082;
wire sig00000083;
wire sig00000084;
wire sig00000085;
wire sig00000086;
wire sig00000087;
wire sig00000088;
wire sig00000089;
wire sig0000008a;
wire sig0000008b;
wire sig0000008c;
wire sig0000008d;
wire sig0000008e;
wire sig0000008f;
wire sig00000090;
wire sig00000091;
wire sig00000092;
wire sig00000093;
wire sig00000094;
wire sig00000095;
wire sig00000096;
wire sig00000097;
wire sig00000098;
wire sig00000099;
wire sig0000009a;
wire sig0000009b;
wire sig0000009c;
wire sig0000009d;
wire sig0000009e;
wire sig0000009f;
wire sig000000a0;
wire sig000000a1;
wire sig000000a2;
wire sig000000a3;
wire sig000000a4;
wire sig000000a5;
wire sig000000a6;
wire sig000000a7;
wire sig000000a8;
wire sig000000a9;
wire sig000000aa;
wire sig000000ab;
wire sig000000ac;
wire sig000000ad;
wire sig000000ae;
wire sig000000af;
wire sig000000b0;
wire sig000000b1;
wire sig000000b2;
wire sig000000b3;
wire sig000000b4;
wire sig000000b5;
wire sig000000b6;
wire sig000000b7;
wire sig000000b8;
wire sig000000b9;
wire sig000000ba;
wire sig000000bb;
wire sig000000bc;
wire sig000000bd;
wire sig000000be;
wire sig000000bf;
wire sig000000c0;
wire sig000000c1;
wire sig000000c2;
wire sig000000c3;
wire sig000000c4;
wire sig000000c5;
wire sig000000c6;
wire sig000000c7;
wire sig000000c8;
wire sig000000c9;
wire sig000000ca;
wire sig000000cb;
wire sig000000cc;
wire sig000000cd;
wire sig000000ce;
wire sig000000cf;
wire sig000000d0;
wire sig000000d1;
wire sig000000d2;
wire sig000000d3;
wire sig000000d4;
wire sig000000d5;
wire sig000000d6;
wire sig000000d7;
wire sig000000d8;
wire sig000000d9;
wire sig000000da;
wire sig000000db;
wire sig000000dc;
wire sig000000dd;
wire sig000000de;
wire sig000000df;
wire sig000000e0;
wire sig000000e1;
wire sig000000e2;
wire sig000000e3;
wire sig000000e4;
wire sig000000e5;
wire sig000000e6;
wire sig000000e7;
wire sig000000e8;
wire sig000000e9;
wire sig000000ea;
wire sig000000eb;
wire sig000000ec;
wire sig000000ed;
wire sig000000ee;
wire sig000000ef;
wire sig000000f0;
wire sig000000f1;
wire sig000000f2;
wire sig000000f3;
wire sig000000f4;
wire sig000000f5;
wire sig000000f6;
wire sig000000f7;
wire sig000000f8;
wire sig000000f9;
wire sig000000fa;
wire sig000000fb;
wire sig000000fc;
wire sig000000fd;
wire sig000000fe;
wire sig000000ff;
wire sig00000100;
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wire sig00000521;
wire sig00000522;
wire sig00000523;
wire sig00000524;
wire sig00000525;
wire sig00000526;
wire sig00000527;
wire sig00000528;
wire sig00000529;
wire sig0000052a;
wire sig0000052b;
wire sig0000052c;
wire sig0000052d;
wire sig0000052e;
wire sig0000052f;
wire sig00000530;
wire sig00000531;
wire sig00000532;
wire sig00000533;
wire sig00000534;
wire sig00000535;
wire sig00000536;
wire sig00000537;
wire sig00000538;
wire sig00000539;
wire sig0000053a;
wire sig0000053b;
wire sig0000053c;
wire sig0000053d;
wire sig0000053e;
wire sig0000053f;
wire sig00000540;
wire sig00000541;
wire sig00000542;
wire sig00000543;
wire sig00000544;
wire sig00000545;
wire sig00000546;
wire sig00000547;
wire sig00000548;
wire sig00000549;
wire sig0000054a;
wire sig0000054b;
wire sig0000054c;
wire sig0000054d;
wire sig0000054e;
wire sig0000054f;
wire sig00000550;
wire sig00000551;
wire sig00000552;
wire sig00000553;
wire sig00000554;
wire sig00000555;
wire sig00000556;
wire sig00000557;
wire sig00000558;
wire sig00000559;
wire sig0000055a;
wire sig0000055b;
wire sig0000055c;
wire sig0000055d;
wire sig0000055e;
wire sig0000055f;
wire sig00000560;
wire sig00000561;
wire sig00000562;
wire sig00000563;
wire sig00000564;
wire sig00000565;
wire sig00000566;
wire sig00000567;
wire sig00000568;
wire sig00000569;
wire sig0000056a;
wire sig0000056b;
wire sig0000056c;
wire sig0000056d;
wire sig0000056e;
wire sig0000056f;
wire sig00000570;
wire sig00000571;
wire sig00000572;
wire sig00000573;
wire sig00000574;
wire sig00000575;
wire sig00000576;
wire sig00000577;
wire sig00000578;
wire sig00000579;
wire sig0000057a;
wire sig0000057b;
wire sig0000057c;
wire sig0000057d;
wire sig0000057e;
wire sig0000057f;
wire sig00000580;
wire sig00000581;
wire sig00000582;
wire sig00000583;
wire sig00000584;
wire sig00000585;
wire sig00000586;
wire sig00000587;
wire sig00000588;
wire sig00000589;
wire sig0000058a;
wire sig0000058b;
wire sig0000058c;
wire sig0000058d;
wire sig0000058e;
wire sig0000058f;
wire sig00000590;
wire sig00000591;
wire sig00000592;
wire sig00000593;
wire sig00000594;
wire sig00000595;
wire sig00000596;
wire sig00000597;
wire sig00000598;
wire sig00000599;
wire sig0000059a;
wire sig0000059b;
wire sig0000059c;
wire sig0000059d;
wire sig0000059e;
wire sig0000059f;
wire sig000005a0;
wire sig000005a1;
wire sig000005a2;
wire sig000005a3;
wire sig000005a4;
wire sig000005a5;
wire sig000005a6;
wire sig000005a7;
wire sig000005a8;
wire sig000005a9;
wire sig000005aa;
wire sig000005ab;
wire sig000005ac;
wire sig000005ad;
wire sig000005ae;
wire sig000005af;
wire sig000005b0;
wire sig000005b1;
wire sig000005b2;
wire sig000005b3;
wire sig000005b4;
wire sig000005b5;
wire sig000005b6;
wire sig000005b7;
wire sig000005b8;
wire sig000005b9;
wire sig000005ba;
wire sig000005bb;
wire sig000005bc;
wire sig000005bd;
wire sig000005be;
wire sig000005bf;
wire sig000005c0;
wire sig000005c1;
wire sig000005c2;
wire sig000005c3;
wire sig000005c4;
wire sig000005c5;
wire sig000005c6;
wire sig000005c7;
wire sig000005c8;
wire sig000005c9;
wire sig000005ca;
wire sig000005cb;
wire sig000005cc;
wire sig000005cd;
wire sig000005ce;
wire sig000005cf;
wire sig000005d0;
wire sig000005d1;
wire sig000005d2;
wire sig000005d3;
wire sig000005d4;
wire sig000005d5;
wire sig000005d6;
wire sig000005d7;
wire sig000005d8;
wire sig000005d9;
wire sig000005da;
wire sig000005db;
wire sig000005dc;
wire sig000005dd;
wire sig000005de;
wire sig000005df;
wire sig000005e0;
wire sig000005e1;
wire sig000005e2;
wire sig000005e3;
wire sig000005e4;
wire sig000005e5;
wire sig000005e6;
wire sig000005e7;
wire sig000005e8;
wire sig000005e9;
wire sig000005ea;
wire sig000005eb;
wire sig000005ec;
wire sig000005ed;
wire sig000005ee;
wire sig000005ef;
wire sig000005f0;
wire sig000005f1;
wire sig000005f2;
wire sig000005f3;
wire sig000005f4;
wire sig000005f5;
wire sig000005f6;
wire sig000005f7;
wire sig000005f8;
wire sig000005f9;
wire sig000005fa;
wire sig000005fb;
wire sig000005fc;
wire sig000005fd;
wire sig000005fe;
wire sig000005ff;
wire sig00000600;
wire sig00000601;
wire sig00000602;
wire sig00000603;
wire sig00000604;
wire sig00000605;
wire sig00000606;
wire sig00000607;
wire sig00000608;
wire sig00000609;
wire sig0000060a;
wire sig0000060b;
wire sig0000060c;
wire sig0000060d;
wire sig0000060e;
wire sig0000060f;
wire sig00000610;
wire sig00000611;
wire sig00000612;
wire sig00000613;
wire sig00000614;
wire sig00000615;
wire sig00000616;
wire sig00000617;
wire sig00000618;
wire sig00000619;
wire sig0000061a;
wire sig0000061b;
wire sig0000061c;
wire sig0000061d;
wire sig0000061e;
wire sig0000061f;
wire sig00000620;
wire sig00000621;
wire sig00000622;
wire sig00000623;
wire sig00000624;
wire sig00000625;
wire sig00000626;
wire sig00000627;
wire sig00000628;
wire sig00000629;
wire sig0000062a;
wire sig0000062b;
wire sig0000062c;
wire sig0000062d;
wire sig0000062e;
wire sig0000062f;
wire sig00000630;
wire sig00000631;
wire sig00000632;
wire NLW_blk0000010f_O_UNCONNECTED;
wire NLW_blk00000273_Q15_UNCONNECTED;
wire NLW_blk00000275_Q15_UNCONNECTED;
wire NLW_blk00000277_Q15_UNCONNECTED;
wire NLW_blk00000279_Q15_UNCONNECTED;
wire NLW_blk0000027b_Q15_UNCONNECTED;
wire NLW_blk0000027d_Q15_UNCONNECTED;
wire NLW_blk0000027f_Q15_UNCONNECTED;
wire NLW_blk00000281_Q15_UNCONNECTED;
wire NLW_blk00000283_Q15_UNCONNECTED;
wire NLW_blk00000285_Q15_UNCONNECTED;
wire NLW_blk00000287_Q15_UNCONNECTED;
wire NLW_blk00000289_Q15_UNCONNECTED;
wire NLW_blk0000028b_Q15_UNCONNECTED;
wire NLW_blk0000028d_Q15_UNCONNECTED;
wire NLW_blk0000028f_Q15_UNCONNECTED;
wire NLW_blk00000291_Q15_UNCONNECTED;
wire NLW_blk00000293_Q15_UNCONNECTED;
wire NLW_blk00000295_Q15_UNCONNECTED;
wire NLW_blk00000297_Q15_UNCONNECTED;
wire NLW_blk00000299_Q15_UNCONNECTED;
wire NLW_blk0000029b_Q15_UNCONNECTED;
wire NLW_blk0000029d_Q15_UNCONNECTED;
wire NLW_blk0000029f_Q15_UNCONNECTED;
wire NLW_blk000002a1_Q15_UNCONNECTED;
wire NLW_blk000002a3_Q15_UNCONNECTED;
wire NLW_blk000002a5_Q15_UNCONNECTED;
wire NLW_blk000002a7_Q15_UNCONNECTED;
wire NLW_blk000002a9_Q15_UNCONNECTED;
wire NLW_blk000002ab_Q15_UNCONNECTED;
wire NLW_blk000002ad_Q15_UNCONNECTED;
wire NLW_blk000002af_Q15_UNCONNECTED;
wire NLW_blk000002b1_Q15_UNCONNECTED;
wire NLW_blk000002b3_Q15_UNCONNECTED;
wire NLW_blk000002b5_Q15_UNCONNECTED;
wire NLW_blk000002b7_Q15_UNCONNECTED;
wire NLW_blk000002b9_Q15_UNCONNECTED;
wire NLW_blk000002bb_Q15_UNCONNECTED;
wire NLW_blk000002bd_Q15_UNCONNECTED;
wire NLW_blk000002bf_Q15_UNCONNECTED;
wire NLW_blk000002c1_Q15_UNCONNECTED;
wire NLW_blk000002c3_Q15_UNCONNECTED;
wire NLW_blk000002c5_Q15_UNCONNECTED;
wire NLW_blk000002c7_Q15_UNCONNECTED;
wire NLW_blk000002c9_Q15_UNCONNECTED;
wire NLW_blk000002cb_Q15_UNCONNECTED;
wire NLW_blk000002cd_Q15_UNCONNECTED;
wire NLW_blk000002cf_Q15_UNCONNECTED;
wire NLW_blk000002d1_Q15_UNCONNECTED;
wire NLW_blk000002d3_Q15_UNCONNECTED;
wire NLW_blk000002d5_Q15_UNCONNECTED;
wire NLW_blk000002d7_Q15_UNCONNECTED;
wire NLW_blk000002d9_Q15_UNCONNECTED;
wire NLW_blk000002db_Q15_UNCONNECTED;
wire NLW_blk000002dd_Q15_UNCONNECTED;
wire NLW_blk000002df_Q15_UNCONNECTED;
wire NLW_blk000002e1_Q15_UNCONNECTED;
wire NLW_blk000002e3_Q15_UNCONNECTED;
wire NLW_blk000002e5_Q15_UNCONNECTED;
wire NLW_blk000002e7_Q15_UNCONNECTED;
wire NLW_blk000002e9_Q15_UNCONNECTED;
wire NLW_blk000002eb_Q15_UNCONNECTED;
wire NLW_blk000002ed_Q15_UNCONNECTED;
wire NLW_blk000002ef_Q15_UNCONNECTED;
wire NLW_blk000002f1_Q15_UNCONNECTED;
wire NLW_blk000002f3_Q15_UNCONNECTED;
wire NLW_blk000002f5_Q15_UNCONNECTED;
wire NLW_blk000002f7_Q15_UNCONNECTED;
wire NLW_blk000002f9_Q15_UNCONNECTED;
wire NLW_blk000002fb_Q15_UNCONNECTED;
wire NLW_blk000002fd_Q15_UNCONNECTED;
wire NLW_blk000002ff_Q15_UNCONNECTED;
wire NLW_blk00000301_Q15_UNCONNECTED;
wire NLW_blk00000303_Q15_UNCONNECTED;
wire NLW_blk00000305_Q15_UNCONNECTED;
wire NLW_blk00000307_Q15_UNCONNECTED;
wire NLW_blk00000309_Q15_UNCONNECTED;
wire NLW_blk0000030b_Q15_UNCONNECTED;
wire NLW_blk0000030d_Q15_UNCONNECTED;
wire NLW_blk0000030f_Q15_UNCONNECTED;
wire NLW_blk00000311_Q15_UNCONNECTED;
wire NLW_blk00000313_Q15_UNCONNECTED;
wire NLW_blk00000315_Q15_UNCONNECTED;
wire NLW_blk00000317_Q15_UNCONNECTED;
wire NLW_blk00000319_Q15_UNCONNECTED;
wire NLW_blk0000031b_Q15_UNCONNECTED;
wire NLW_blk0000031d_Q15_UNCONNECTED;
wire NLW_blk0000031f_Q15_UNCONNECTED;
wire NLW_blk00000321_Q15_UNCONNECTED;
wire NLW_blk00000323_Q15_UNCONNECTED;
wire NLW_blk00000325_Q15_UNCONNECTED;
wire NLW_blk00000327_Q15_UNCONNECTED;
wire NLW_blk00000329_Q15_UNCONNECTED;
wire NLW_blk0000032b_Q15_UNCONNECTED;
wire NLW_blk0000032d_Q15_UNCONNECTED;
wire NLW_blk0000032f_Q15_UNCONNECTED;
wire NLW_blk00000331_Q15_UNCONNECTED;
wire NLW_blk00000333_Q15_UNCONNECTED;
wire NLW_blk00000335_Q15_UNCONNECTED;
wire NLW_blk00000337_Q15_UNCONNECTED;
wire NLW_blk00000339_Q15_UNCONNECTED;
wire NLW_blk0000033b_Q15_UNCONNECTED;
wire NLW_blk0000033d_Q15_UNCONNECTED;
wire NLW_blk0000033f_Q15_UNCONNECTED;
wire NLW_blk00000341_Q15_UNCONNECTED;
wire NLW_blk00000343_Q15_UNCONNECTED;
wire NLW_blk00000345_Q15_UNCONNECTED;
wire NLW_blk00000347_Q15_UNCONNECTED;
wire NLW_blk00000349_Q15_UNCONNECTED;
wire NLW_blk0000034b_Q15_UNCONNECTED;
wire NLW_blk0000034d_Q15_UNCONNECTED;
wire NLW_blk0000034f_Q15_UNCONNECTED;
wire NLW_blk00000351_Q15_UNCONNECTED;
wire NLW_blk00000353_Q15_UNCONNECTED;
wire NLW_blk00000355_Q15_UNCONNECTED;
wire NLW_blk00000357_Q15_UNCONNECTED;
wire NLW_blk00000359_Q15_UNCONNECTED;
wire NLW_blk0000035b_Q15_UNCONNECTED;
wire NLW_blk0000035d_Q15_UNCONNECTED;
wire NLW_blk0000035f_Q15_UNCONNECTED;
wire NLW_blk00000361_Q15_UNCONNECTED;
wire NLW_blk00000363_Q15_UNCONNECTED;
wire NLW_blk00000365_Q15_UNCONNECTED;
wire NLW_blk00000367_Q15_UNCONNECTED;
wire NLW_blk00000369_Q15_UNCONNECTED;
wire NLW_blk0000036b_Q15_UNCONNECTED;
wire NLW_blk0000036d_Q15_UNCONNECTED;
wire NLW_blk0000036f_Q15_UNCONNECTED;
wire NLW_blk00000371_Q15_UNCONNECTED;
wire NLW_blk00000373_Q15_UNCONNECTED;
wire NLW_blk00000375_Q15_UNCONNECTED;
wire NLW_blk00000377_Q15_UNCONNECTED;
wire NLW_blk00000379_Q15_UNCONNECTED;
wire NLW_blk0000037b_Q15_UNCONNECTED;
wire NLW_blk0000037d_Q15_UNCONNECTED;
wire NLW_blk0000037f_Q15_UNCONNECTED;
wire NLW_blk00000381_Q15_UNCONNECTED;
wire NLW_blk00000383_Q15_UNCONNECTED;
wire NLW_blk00000385_Q15_UNCONNECTED;
wire NLW_blk00000387_Q15_UNCONNECTED;
wire NLW_blk00000389_Q15_UNCONNECTED;
wire NLW_blk0000038b_Q15_UNCONNECTED;
wire NLW_blk0000038d_Q15_UNCONNECTED;
wire NLW_blk0000038f_Q15_UNCONNECTED;
wire NLW_blk00000391_Q15_UNCONNECTED;
wire NLW_blk00000393_Q15_UNCONNECTED;
wire NLW_blk00000395_Q15_UNCONNECTED;
wire NLW_blk00000397_Q15_UNCONNECTED;
wire NLW_blk00000399_Q15_UNCONNECTED;
wire NLW_blk0000039b_Q15_UNCONNECTED;
wire NLW_blk0000039d_Q15_UNCONNECTED;
wire NLW_blk0000039f_Q15_UNCONNECTED;
wire NLW_blk000003a1_Q15_UNCONNECTED;
wire NLW_blk000003a3_Q15_UNCONNECTED;
wire NLW_blk000003a5_Q15_UNCONNECTED;
wire NLW_blk000003a7_Q15_UNCONNECTED;
wire NLW_blk000003a9_Q15_UNCONNECTED;
wire NLW_blk000003ab_Q15_UNCONNECTED;
wire NLW_blk000003ad_Q15_UNCONNECTED;
wire NLW_blk000003af_Q15_UNCONNECTED;
wire NLW_blk000003b1_Q15_UNCONNECTED;
wire NLW_blk000003b3_Q15_UNCONNECTED;
wire NLW_blk000003b5_Q15_UNCONNECTED;
wire NLW_blk000003b7_Q15_UNCONNECTED;
wire NLW_blk000003b9_Q15_UNCONNECTED;
wire NLW_blk000003bb_Q15_UNCONNECTED;
wire NLW_blk000003bd_Q15_UNCONNECTED;
wire NLW_blk000003bf_Q15_UNCONNECTED;
wire NLW_blk000003c1_Q15_UNCONNECTED;
wire NLW_blk000003c3_Q15_UNCONNECTED;
wire NLW_blk000003c5_Q15_UNCONNECTED;
wire NLW_blk000003c7_Q15_UNCONNECTED;
wire NLW_blk000003c9_Q15_UNCONNECTED;
wire NLW_blk000003cb_Q15_UNCONNECTED;
wire NLW_blk000003cd_Q15_UNCONNECTED;
wire NLW_blk000003cf_Q15_UNCONNECTED;
wire NLW_blk000003d1_Q15_UNCONNECTED;
wire NLW_blk000003d3_Q15_UNCONNECTED;
wire NLW_blk000003d5_Q15_UNCONNECTED;
wire NLW_blk000003d7_Q15_UNCONNECTED;
wire NLW_blk000003d9_Q15_UNCONNECTED;
wire NLW_blk000003db_Q15_UNCONNECTED;
wire NLW_blk000003dd_Q15_UNCONNECTED;
wire NLW_blk000003df_Q15_UNCONNECTED;
wire NLW_blk000003e1_Q15_UNCONNECTED;
wire NLW_blk000003e3_Q15_UNCONNECTED;
wire NLW_blk000003e5_Q15_UNCONNECTED;
wire NLW_blk000003e7_Q15_UNCONNECTED;
wire NLW_blk000003e9_Q15_UNCONNECTED;
wire NLW_blk000003eb_Q15_UNCONNECTED;
wire NLW_blk000003ed_Q15_UNCONNECTED;
wire NLW_blk000003ef_Q15_UNCONNECTED;
wire NLW_blk000003f1_Q15_UNCONNECTED;
wire NLW_blk000003f3_Q15_UNCONNECTED;
wire NLW_blk000003f5_Q15_UNCONNECTED;
wire NLW_blk000003f7_Q15_UNCONNECTED;
wire NLW_blk000003f9_Q15_UNCONNECTED;
wire NLW_blk000003fb_Q15_UNCONNECTED;
wire NLW_blk000003fd_Q15_UNCONNECTED;
wire NLW_blk000003ff_Q15_UNCONNECTED;
wire NLW_blk00000401_Q15_UNCONNECTED;
wire NLW_blk00000403_Q15_UNCONNECTED;
wire NLW_blk00000405_Q15_UNCONNECTED;
wire NLW_blk00000407_Q15_UNCONNECTED;
wire NLW_blk00000409_Q15_UNCONNECTED;
wire NLW_blk0000040b_Q15_UNCONNECTED;
wire \NLW_blk0000040d_PCOUT<47>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<46>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<45>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<44>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<43>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<42>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<41>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<40>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<39>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<38>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<37>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<36>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<35>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<34>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<33>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<32>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<31>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<30>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<29>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<28>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<27>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<26>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<25>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<24>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<23>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<22>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<21>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<20>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<19>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<18>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<17>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<16>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<15>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<14>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<13>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<12>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<11>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<10>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<9>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<8>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<7>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<6>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<5>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<4>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040d_PCOUT<0>_UNCONNECTED ;
wire NLW_blk0000040d_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk0000040d_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk0000040d_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk0000040d_UNDERFLOW_UNCONNECTED;
wire NLW_blk0000040d_PATTERNDETECT_UNCONNECTED;
wire NLW_blk0000040d_OVERFLOW_UNCONNECTED;
wire \NLW_blk0000040d_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040d_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040d_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040d_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040d_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040d_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040d_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040d_P<47>_UNCONNECTED ;
wire \NLW_blk0000040d_P<46>_UNCONNECTED ;
wire \NLW_blk0000040d_P<45>_UNCONNECTED ;
wire \NLW_blk0000040d_P<44>_UNCONNECTED ;
wire \NLW_blk0000040d_P<43>_UNCONNECTED ;
wire \NLW_blk0000040d_P<42>_UNCONNECTED ;
wire \NLW_blk0000040d_P<41>_UNCONNECTED ;
wire \NLW_blk0000040d_P<40>_UNCONNECTED ;
wire \NLW_blk0000040d_P<39>_UNCONNECTED ;
wire \NLW_blk0000040d_P<38>_UNCONNECTED ;
wire \NLW_blk0000040d_P<37>_UNCONNECTED ;
wire \NLW_blk0000040d_P<36>_UNCONNECTED ;
wire \NLW_blk0000040d_P<35>_UNCONNECTED ;
wire \NLW_blk0000040d_P<34>_UNCONNECTED ;
wire \NLW_blk0000040d_P<33>_UNCONNECTED ;
wire \NLW_blk0000040d_P<32>_UNCONNECTED ;
wire \NLW_blk0000040d_P<31>_UNCONNECTED ;
wire \NLW_blk0000040d_P<30>_UNCONNECTED ;
wire \NLW_blk0000040d_P<29>_UNCONNECTED ;
wire \NLW_blk0000040d_P<28>_UNCONNECTED ;
wire \NLW_blk0000040d_P<27>_UNCONNECTED ;
wire \NLW_blk0000040d_P<26>_UNCONNECTED ;
wire \NLW_blk0000040d_P<25>_UNCONNECTED ;
wire \NLW_blk0000040d_P<24>_UNCONNECTED ;
wire \NLW_blk0000040d_P<23>_UNCONNECTED ;
wire \NLW_blk0000040d_P<22>_UNCONNECTED ;
wire \NLW_blk0000040d_P<21>_UNCONNECTED ;
wire NLW_blk0000040e_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk0000040e_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk0000040e_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk0000040e_UNDERFLOW_UNCONNECTED;
wire NLW_blk0000040e_PATTERNDETECT_UNCONNECTED;
wire NLW_blk0000040e_OVERFLOW_UNCONNECTED;
wire \NLW_blk0000040e_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040e_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040e_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040e_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040e_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040e_P<47>_UNCONNECTED ;
wire \NLW_blk0000040e_P<46>_UNCONNECTED ;
wire \NLW_blk0000040e_P<45>_UNCONNECTED ;
wire \NLW_blk0000040e_P<44>_UNCONNECTED ;
wire \NLW_blk0000040e_P<43>_UNCONNECTED ;
wire \NLW_blk0000040e_P<42>_UNCONNECTED ;
wire \NLW_blk0000040e_P<41>_UNCONNECTED ;
wire \NLW_blk0000040e_P<40>_UNCONNECTED ;
wire \NLW_blk0000040e_P<39>_UNCONNECTED ;
wire \NLW_blk0000040e_P<38>_UNCONNECTED ;
wire \NLW_blk0000040e_P<37>_UNCONNECTED ;
wire \NLW_blk0000040e_P<36>_UNCONNECTED ;
wire \NLW_blk0000040e_P<35>_UNCONNECTED ;
wire \NLW_blk0000040e_P<34>_UNCONNECTED ;
wire \NLW_blk0000040e_P<33>_UNCONNECTED ;
wire \NLW_blk0000040e_P<32>_UNCONNECTED ;
wire \NLW_blk0000040e_P<31>_UNCONNECTED ;
wire \NLW_blk0000040e_P<30>_UNCONNECTED ;
wire \NLW_blk0000040e_P<29>_UNCONNECTED ;
wire \NLW_blk0000040e_P<28>_UNCONNECTED ;
wire \NLW_blk0000040e_P<27>_UNCONNECTED ;
wire \NLW_blk0000040e_P<26>_UNCONNECTED ;
wire \NLW_blk0000040e_P<25>_UNCONNECTED ;
wire \NLW_blk0000040e_P<24>_UNCONNECTED ;
wire \NLW_blk0000040e_P<23>_UNCONNECTED ;
wire \NLW_blk0000040e_P<22>_UNCONNECTED ;
wire \NLW_blk0000040e_P<21>_UNCONNECTED ;
wire \NLW_blk0000040e_P<20>_UNCONNECTED ;
wire \NLW_blk0000040e_P<19>_UNCONNECTED ;
wire \NLW_blk0000040e_P<18>_UNCONNECTED ;
wire \NLW_blk0000040e_P<17>_UNCONNECTED ;
wire NLW_blk0000040f_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk0000040f_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk0000040f_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk0000040f_UNDERFLOW_UNCONNECTED;
wire NLW_blk0000040f_PATTERNDETECT_UNCONNECTED;
wire NLW_blk0000040f_OVERFLOW_UNCONNECTED;
wire \NLW_blk0000040f_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040f_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040f_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040f_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk0000040f_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk0000040f_P<47>_UNCONNECTED ;
wire \NLW_blk0000040f_P<46>_UNCONNECTED ;
wire \NLW_blk0000040f_P<45>_UNCONNECTED ;
wire \NLW_blk0000040f_P<44>_UNCONNECTED ;
wire \NLW_blk0000040f_P<43>_UNCONNECTED ;
wire \NLW_blk0000040f_P<42>_UNCONNECTED ;
wire \NLW_blk0000040f_P<41>_UNCONNECTED ;
wire \NLW_blk0000040f_P<40>_UNCONNECTED ;
wire \NLW_blk0000040f_P<39>_UNCONNECTED ;
wire \NLW_blk0000040f_P<38>_UNCONNECTED ;
wire \NLW_blk0000040f_P<37>_UNCONNECTED ;
wire \NLW_blk0000040f_P<36>_UNCONNECTED ;
wire \NLW_blk0000040f_P<35>_UNCONNECTED ;
wire \NLW_blk0000040f_P<34>_UNCONNECTED ;
wire \NLW_blk0000040f_P<33>_UNCONNECTED ;
wire \NLW_blk0000040f_P<32>_UNCONNECTED ;
wire \NLW_blk0000040f_P<31>_UNCONNECTED ;
wire \NLW_blk0000040f_P<30>_UNCONNECTED ;
wire \NLW_blk0000040f_P<29>_UNCONNECTED ;
wire \NLW_blk0000040f_P<28>_UNCONNECTED ;
wire \NLW_blk0000040f_P<27>_UNCONNECTED ;
wire \NLW_blk0000040f_P<26>_UNCONNECTED ;
wire \NLW_blk0000040f_P<25>_UNCONNECTED ;
wire \NLW_blk0000040f_P<24>_UNCONNECTED ;
wire \NLW_blk0000040f_P<23>_UNCONNECTED ;
wire \NLW_blk0000040f_P<22>_UNCONNECTED ;
wire \NLW_blk0000040f_P<21>_UNCONNECTED ;
wire \NLW_blk0000040f_P<20>_UNCONNECTED ;
wire \NLW_blk0000040f_P<19>_UNCONNECTED ;
wire \NLW_blk0000040f_P<18>_UNCONNECTED ;
wire \NLW_blk0000040f_P<17>_UNCONNECTED ;
wire NLW_blk00000410_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000410_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000410_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000410_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000410_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000410_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000410_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000410_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000410_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000410_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000410_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000410_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000410_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000410_P<47>_UNCONNECTED ;
wire \NLW_blk00000410_P<46>_UNCONNECTED ;
wire \NLW_blk00000410_P<45>_UNCONNECTED ;
wire \NLW_blk00000410_P<44>_UNCONNECTED ;
wire \NLW_blk00000410_P<43>_UNCONNECTED ;
wire \NLW_blk00000410_P<42>_UNCONNECTED ;
wire \NLW_blk00000410_P<41>_UNCONNECTED ;
wire \NLW_blk00000410_P<40>_UNCONNECTED ;
wire \NLW_blk00000410_P<39>_UNCONNECTED ;
wire \NLW_blk00000410_P<38>_UNCONNECTED ;
wire \NLW_blk00000410_P<37>_UNCONNECTED ;
wire \NLW_blk00000410_P<36>_UNCONNECTED ;
wire \NLW_blk00000410_P<35>_UNCONNECTED ;
wire \NLW_blk00000410_P<34>_UNCONNECTED ;
wire \NLW_blk00000410_P<33>_UNCONNECTED ;
wire \NLW_blk00000410_P<32>_UNCONNECTED ;
wire \NLW_blk00000410_P<31>_UNCONNECTED ;
wire \NLW_blk00000410_P<30>_UNCONNECTED ;
wire \NLW_blk00000410_P<29>_UNCONNECTED ;
wire \NLW_blk00000410_P<28>_UNCONNECTED ;
wire \NLW_blk00000410_P<27>_UNCONNECTED ;
wire \NLW_blk00000410_P<26>_UNCONNECTED ;
wire \NLW_blk00000410_P<25>_UNCONNECTED ;
wire \NLW_blk00000410_P<24>_UNCONNECTED ;
wire \NLW_blk00000410_P<23>_UNCONNECTED ;
wire \NLW_blk00000410_P<22>_UNCONNECTED ;
wire \NLW_blk00000410_P<21>_UNCONNECTED ;
wire \NLW_blk00000410_P<20>_UNCONNECTED ;
wire \NLW_blk00000410_P<19>_UNCONNECTED ;
wire \NLW_blk00000410_P<18>_UNCONNECTED ;
wire \NLW_blk00000410_P<17>_UNCONNECTED ;
wire \NLW_blk00000410_P<16>_UNCONNECTED ;
wire \NLW_blk00000410_P<15>_UNCONNECTED ;
wire \NLW_blk00000410_P<14>_UNCONNECTED ;
wire \NLW_blk00000410_P<13>_UNCONNECTED ;
wire \NLW_blk00000410_P<12>_UNCONNECTED ;
wire \NLW_blk00000410_P<11>_UNCONNECTED ;
wire \NLW_blk00000410_P<10>_UNCONNECTED ;
wire \NLW_blk00000410_P<9>_UNCONNECTED ;
wire \NLW_blk00000410_P<8>_UNCONNECTED ;
wire \NLW_blk00000410_P<7>_UNCONNECTED ;
wire \NLW_blk00000410_P<6>_UNCONNECTED ;
wire \NLW_blk00000410_P<5>_UNCONNECTED ;
wire \NLW_blk00000410_P<4>_UNCONNECTED ;
wire \NLW_blk00000410_P<3>_UNCONNECTED ;
wire \NLW_blk00000410_P<2>_UNCONNECTED ;
wire \NLW_blk00000410_P<1>_UNCONNECTED ;
wire \NLW_blk00000410_P<0>_UNCONNECTED ;
wire NLW_blk00000411_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000411_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000411_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000411_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000411_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000411_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000411_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000411_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000411_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000411_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000411_P<47>_UNCONNECTED ;
wire \NLW_blk00000411_P<46>_UNCONNECTED ;
wire \NLW_blk00000411_P<45>_UNCONNECTED ;
wire \NLW_blk00000411_P<44>_UNCONNECTED ;
wire \NLW_blk00000411_P<43>_UNCONNECTED ;
wire \NLW_blk00000411_P<42>_UNCONNECTED ;
wire \NLW_blk00000411_P<41>_UNCONNECTED ;
wire \NLW_blk00000411_P<40>_UNCONNECTED ;
wire \NLW_blk00000411_P<39>_UNCONNECTED ;
wire \NLW_blk00000411_P<38>_UNCONNECTED ;
wire \NLW_blk00000411_P<37>_UNCONNECTED ;
wire \NLW_blk00000411_P<36>_UNCONNECTED ;
wire \NLW_blk00000411_P<35>_UNCONNECTED ;
wire \NLW_blk00000411_P<34>_UNCONNECTED ;
wire \NLW_blk00000411_P<33>_UNCONNECTED ;
wire \NLW_blk00000411_P<32>_UNCONNECTED ;
wire \NLW_blk00000411_P<31>_UNCONNECTED ;
wire \NLW_blk00000411_P<30>_UNCONNECTED ;
wire \NLW_blk00000411_P<29>_UNCONNECTED ;
wire \NLW_blk00000411_P<28>_UNCONNECTED ;
wire \NLW_blk00000411_P<27>_UNCONNECTED ;
wire \NLW_blk00000411_P<26>_UNCONNECTED ;
wire \NLW_blk00000411_P<25>_UNCONNECTED ;
wire \NLW_blk00000411_P<24>_UNCONNECTED ;
wire \NLW_blk00000411_P<23>_UNCONNECTED ;
wire \NLW_blk00000411_P<22>_UNCONNECTED ;
wire \NLW_blk00000411_P<21>_UNCONNECTED ;
wire \NLW_blk00000411_P<20>_UNCONNECTED ;
wire \NLW_blk00000411_P<19>_UNCONNECTED ;
wire \NLW_blk00000411_P<18>_UNCONNECTED ;
wire \NLW_blk00000411_P<17>_UNCONNECTED ;
wire \NLW_blk00000411_P<16>_UNCONNECTED ;
wire \NLW_blk00000411_P<15>_UNCONNECTED ;
wire \NLW_blk00000411_P<14>_UNCONNECTED ;
wire \NLW_blk00000411_P<13>_UNCONNECTED ;
wire \NLW_blk00000411_P<12>_UNCONNECTED ;
wire \NLW_blk00000411_P<11>_UNCONNECTED ;
wire \NLW_blk00000411_P<10>_UNCONNECTED ;
wire \NLW_blk00000411_P<9>_UNCONNECTED ;
wire \NLW_blk00000411_P<8>_UNCONNECTED ;
wire \NLW_blk00000411_P<7>_UNCONNECTED ;
wire \NLW_blk00000411_P<6>_UNCONNECTED ;
wire \NLW_blk00000411_P<5>_UNCONNECTED ;
wire \NLW_blk00000411_P<4>_UNCONNECTED ;
wire \NLW_blk00000411_P<3>_UNCONNECTED ;
wire \NLW_blk00000411_P<2>_UNCONNECTED ;
wire \NLW_blk00000411_P<1>_UNCONNECTED ;
wire \NLW_blk00000411_P<0>_UNCONNECTED ;
wire NLW_blk00000412_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000412_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000412_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000412_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000412_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000412_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000412_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000412_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000412_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000412_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000412_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000412_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000412_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000412_P<47>_UNCONNECTED ;
wire \NLW_blk00000412_P<46>_UNCONNECTED ;
wire \NLW_blk00000412_P<45>_UNCONNECTED ;
wire \NLW_blk00000412_P<44>_UNCONNECTED ;
wire \NLW_blk00000412_P<43>_UNCONNECTED ;
wire \NLW_blk00000412_P<42>_UNCONNECTED ;
wire \NLW_blk00000412_P<41>_UNCONNECTED ;
wire \NLW_blk00000412_P<40>_UNCONNECTED ;
wire \NLW_blk00000412_P<39>_UNCONNECTED ;
wire \NLW_blk00000412_P<38>_UNCONNECTED ;
wire \NLW_blk00000412_P<37>_UNCONNECTED ;
wire \NLW_blk00000412_P<36>_UNCONNECTED ;
wire \NLW_blk00000412_P<35>_UNCONNECTED ;
wire \NLW_blk00000412_P<34>_UNCONNECTED ;
wire \NLW_blk00000412_P<33>_UNCONNECTED ;
wire \NLW_blk00000412_P<32>_UNCONNECTED ;
wire \NLW_blk00000412_P<31>_UNCONNECTED ;
wire \NLW_blk00000412_P<30>_UNCONNECTED ;
wire \NLW_blk00000412_P<29>_UNCONNECTED ;
wire \NLW_blk00000412_P<28>_UNCONNECTED ;
wire \NLW_blk00000412_P<27>_UNCONNECTED ;
wire \NLW_blk00000412_P<26>_UNCONNECTED ;
wire \NLW_blk00000412_P<25>_UNCONNECTED ;
wire \NLW_blk00000412_P<24>_UNCONNECTED ;
wire \NLW_blk00000412_P<23>_UNCONNECTED ;
wire \NLW_blk00000412_P<22>_UNCONNECTED ;
wire \NLW_blk00000412_P<21>_UNCONNECTED ;
wire \NLW_blk00000412_P<20>_UNCONNECTED ;
wire \NLW_blk00000412_P<19>_UNCONNECTED ;
wire \NLW_blk00000412_P<18>_UNCONNECTED ;
wire \NLW_blk00000412_P<17>_UNCONNECTED ;
wire \NLW_blk00000412_P<16>_UNCONNECTED ;
wire \NLW_blk00000412_P<15>_UNCONNECTED ;
wire \NLW_blk00000412_P<14>_UNCONNECTED ;
wire \NLW_blk00000412_P<13>_UNCONNECTED ;
wire \NLW_blk00000412_P<12>_UNCONNECTED ;
wire \NLW_blk00000412_P<11>_UNCONNECTED ;
wire \NLW_blk00000412_P<10>_UNCONNECTED ;
wire \NLW_blk00000412_P<9>_UNCONNECTED ;
wire \NLW_blk00000412_P<8>_UNCONNECTED ;
wire \NLW_blk00000412_P<7>_UNCONNECTED ;
wire \NLW_blk00000412_P<6>_UNCONNECTED ;
wire \NLW_blk00000412_P<5>_UNCONNECTED ;
wire \NLW_blk00000412_P<4>_UNCONNECTED ;
wire \NLW_blk00000412_P<3>_UNCONNECTED ;
wire \NLW_blk00000412_P<2>_UNCONNECTED ;
wire \NLW_blk00000412_P<1>_UNCONNECTED ;
wire \NLW_blk00000412_P<0>_UNCONNECTED ;
wire NLW_blk00000413_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000413_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000413_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000413_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000413_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000413_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000413_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000413_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000413_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000413_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000413_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000413_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000413_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000413_P<47>_UNCONNECTED ;
wire \NLW_blk00000413_P<46>_UNCONNECTED ;
wire \NLW_blk00000413_P<45>_UNCONNECTED ;
wire \NLW_blk00000413_P<44>_UNCONNECTED ;
wire \NLW_blk00000413_P<43>_UNCONNECTED ;
wire \NLW_blk00000413_P<42>_UNCONNECTED ;
wire \NLW_blk00000413_P<41>_UNCONNECTED ;
wire \NLW_blk00000413_P<40>_UNCONNECTED ;
wire \NLW_blk00000413_P<39>_UNCONNECTED ;
wire \NLW_blk00000413_P<38>_UNCONNECTED ;
wire \NLW_blk00000413_P<37>_UNCONNECTED ;
wire \NLW_blk00000413_P<36>_UNCONNECTED ;
wire \NLW_blk00000413_P<35>_UNCONNECTED ;
wire \NLW_blk00000413_P<34>_UNCONNECTED ;
wire \NLW_blk00000413_P<33>_UNCONNECTED ;
wire \NLW_blk00000413_P<32>_UNCONNECTED ;
wire \NLW_blk00000413_P<31>_UNCONNECTED ;
wire \NLW_blk00000413_P<30>_UNCONNECTED ;
wire \NLW_blk00000413_P<29>_UNCONNECTED ;
wire \NLW_blk00000413_P<28>_UNCONNECTED ;
wire \NLW_blk00000413_P<27>_UNCONNECTED ;
wire \NLW_blk00000413_P<26>_UNCONNECTED ;
wire \NLW_blk00000413_P<25>_UNCONNECTED ;
wire \NLW_blk00000413_P<24>_UNCONNECTED ;
wire \NLW_blk00000413_P<23>_UNCONNECTED ;
wire \NLW_blk00000413_P<22>_UNCONNECTED ;
wire \NLW_blk00000413_P<21>_UNCONNECTED ;
wire \NLW_blk00000413_P<20>_UNCONNECTED ;
wire \NLW_blk00000413_P<19>_UNCONNECTED ;
wire \NLW_blk00000413_P<18>_UNCONNECTED ;
wire \NLW_blk00000413_P<17>_UNCONNECTED ;
wire \NLW_blk00000413_P<16>_UNCONNECTED ;
wire \NLW_blk00000413_P<15>_UNCONNECTED ;
wire \NLW_blk00000413_P<14>_UNCONNECTED ;
wire \NLW_blk00000413_P<13>_UNCONNECTED ;
wire \NLW_blk00000413_P<12>_UNCONNECTED ;
wire \NLW_blk00000413_P<11>_UNCONNECTED ;
wire \NLW_blk00000413_P<10>_UNCONNECTED ;
wire \NLW_blk00000413_P<9>_UNCONNECTED ;
wire \NLW_blk00000413_P<8>_UNCONNECTED ;
wire \NLW_blk00000413_P<7>_UNCONNECTED ;
wire \NLW_blk00000413_P<6>_UNCONNECTED ;
wire \NLW_blk00000413_P<5>_UNCONNECTED ;
wire \NLW_blk00000413_P<4>_UNCONNECTED ;
wire \NLW_blk00000413_P<3>_UNCONNECTED ;
wire \NLW_blk00000413_P<2>_UNCONNECTED ;
wire \NLW_blk00000413_P<1>_UNCONNECTED ;
wire \NLW_blk00000413_P<0>_UNCONNECTED ;
wire NLW_blk00000414_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000414_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000414_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000414_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000414_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000414_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000414_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000414_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000414_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000414_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000414_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000414_P<47>_UNCONNECTED ;
wire \NLW_blk00000414_P<46>_UNCONNECTED ;
wire \NLW_blk00000414_P<45>_UNCONNECTED ;
wire \NLW_blk00000414_P<44>_UNCONNECTED ;
wire \NLW_blk00000414_P<43>_UNCONNECTED ;
wire \NLW_blk00000414_P<42>_UNCONNECTED ;
wire \NLW_blk00000414_P<41>_UNCONNECTED ;
wire \NLW_blk00000414_P<40>_UNCONNECTED ;
wire \NLW_blk00000414_P<39>_UNCONNECTED ;
wire \NLW_blk00000414_P<38>_UNCONNECTED ;
wire \NLW_blk00000414_P<37>_UNCONNECTED ;
wire \NLW_blk00000414_P<36>_UNCONNECTED ;
wire \NLW_blk00000414_P<35>_UNCONNECTED ;
wire \NLW_blk00000414_P<34>_UNCONNECTED ;
wire \NLW_blk00000414_P<33>_UNCONNECTED ;
wire \NLW_blk00000414_P<32>_UNCONNECTED ;
wire \NLW_blk00000414_P<31>_UNCONNECTED ;
wire \NLW_blk00000414_P<30>_UNCONNECTED ;
wire \NLW_blk00000414_P<29>_UNCONNECTED ;
wire \NLW_blk00000414_P<28>_UNCONNECTED ;
wire \NLW_blk00000414_P<27>_UNCONNECTED ;
wire \NLW_blk00000414_P<26>_UNCONNECTED ;
wire \NLW_blk00000414_P<25>_UNCONNECTED ;
wire \NLW_blk00000414_P<24>_UNCONNECTED ;
wire \NLW_blk00000414_P<23>_UNCONNECTED ;
wire \NLW_blk00000414_P<22>_UNCONNECTED ;
wire \NLW_blk00000414_P<21>_UNCONNECTED ;
wire \NLW_blk00000414_P<20>_UNCONNECTED ;
wire \NLW_blk00000414_P<19>_UNCONNECTED ;
wire \NLW_blk00000414_P<18>_UNCONNECTED ;
wire \NLW_blk00000414_P<17>_UNCONNECTED ;
wire \NLW_blk00000414_P<16>_UNCONNECTED ;
wire \NLW_blk00000414_P<15>_UNCONNECTED ;
wire \NLW_blk00000414_P<14>_UNCONNECTED ;
wire \NLW_blk00000414_P<13>_UNCONNECTED ;
wire \NLW_blk00000414_P<12>_UNCONNECTED ;
wire \NLW_blk00000414_P<11>_UNCONNECTED ;
wire \NLW_blk00000414_P<10>_UNCONNECTED ;
wire \NLW_blk00000414_P<9>_UNCONNECTED ;
wire \NLW_blk00000414_P<8>_UNCONNECTED ;
wire \NLW_blk00000414_P<7>_UNCONNECTED ;
wire \NLW_blk00000414_P<6>_UNCONNECTED ;
wire \NLW_blk00000414_P<5>_UNCONNECTED ;
wire \NLW_blk00000414_P<4>_UNCONNECTED ;
wire \NLW_blk00000414_P<3>_UNCONNECTED ;
wire \NLW_blk00000414_P<2>_UNCONNECTED ;
wire \NLW_blk00000414_P<1>_UNCONNECTED ;
wire \NLW_blk00000414_P<0>_UNCONNECTED ;
wire NLW_blk00000415_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000415_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000415_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000415_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000415_PATTERNDETECT_UNCONNECTED;
wire NLW_blk00000415_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000415_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000415_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000415_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000415_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000415_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000415_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000415_BCOUT<0>_UNCONNECTED ;
wire \NLW_blk00000415_P<47>_UNCONNECTED ;
wire \NLW_blk00000415_P<46>_UNCONNECTED ;
wire \NLW_blk00000415_P<45>_UNCONNECTED ;
wire \NLW_blk00000415_P<44>_UNCONNECTED ;
wire \NLW_blk00000415_P<43>_UNCONNECTED ;
wire \NLW_blk00000415_P<42>_UNCONNECTED ;
wire \NLW_blk00000415_P<41>_UNCONNECTED ;
wire \NLW_blk00000415_P<40>_UNCONNECTED ;
wire \NLW_blk00000415_P<39>_UNCONNECTED ;
wire \NLW_blk00000415_P<38>_UNCONNECTED ;
wire \NLW_blk00000415_P<37>_UNCONNECTED ;
wire \NLW_blk00000415_P<36>_UNCONNECTED ;
wire \NLW_blk00000415_P<35>_UNCONNECTED ;
wire \NLW_blk00000415_P<34>_UNCONNECTED ;
wire \NLW_blk00000415_P<33>_UNCONNECTED ;
wire \NLW_blk00000415_P<32>_UNCONNECTED ;
wire \NLW_blk00000415_P<31>_UNCONNECTED ;
wire \NLW_blk00000415_P<30>_UNCONNECTED ;
wire \NLW_blk00000415_P<29>_UNCONNECTED ;
wire \NLW_blk00000415_P<28>_UNCONNECTED ;
wire \NLW_blk00000415_P<27>_UNCONNECTED ;
wire \NLW_blk00000415_P<26>_UNCONNECTED ;
wire \NLW_blk00000415_P<25>_UNCONNECTED ;
wire \NLW_blk00000415_P<24>_UNCONNECTED ;
wire \NLW_blk00000415_P<23>_UNCONNECTED ;
wire \NLW_blk00000415_P<22>_UNCONNECTED ;
wire \NLW_blk00000415_P<21>_UNCONNECTED ;
wire \NLW_blk00000415_P<20>_UNCONNECTED ;
wire \NLW_blk00000415_P<19>_UNCONNECTED ;
wire \NLW_blk00000415_P<18>_UNCONNECTED ;
wire \NLW_blk00000415_P<17>_UNCONNECTED ;
wire \NLW_blk00000415_P<16>_UNCONNECTED ;
wire \NLW_blk00000415_P<15>_UNCONNECTED ;
wire \NLW_blk00000415_P<14>_UNCONNECTED ;
wire \NLW_blk00000415_P<13>_UNCONNECTED ;
wire \NLW_blk00000415_P<12>_UNCONNECTED ;
wire \NLW_blk00000415_P<11>_UNCONNECTED ;
wire \NLW_blk00000415_P<10>_UNCONNECTED ;
wire \NLW_blk00000415_P<9>_UNCONNECTED ;
wire \NLW_blk00000415_P<8>_UNCONNECTED ;
wire \NLW_blk00000415_P<7>_UNCONNECTED ;
wire \NLW_blk00000415_P<6>_UNCONNECTED ;
wire \NLW_blk00000415_P<5>_UNCONNECTED ;
wire \NLW_blk00000415_P<4>_UNCONNECTED ;
wire \NLW_blk00000415_P<3>_UNCONNECTED ;
wire \NLW_blk00000415_P<2>_UNCONNECTED ;
wire \NLW_blk00000415_P<1>_UNCONNECTED ;
wire \NLW_blk00000415_P<0>_UNCONNECTED ;
wire NLW_blk00000416_PATTERNBDETECT_UNCONNECTED;
wire NLW_blk00000416_MULTSIGNOUT_UNCONNECTED;
wire NLW_blk00000416_CARRYCASCOUT_UNCONNECTED;
wire NLW_blk00000416_UNDERFLOW_UNCONNECTED;
wire NLW_blk00000416_OVERFLOW_UNCONNECTED;
wire \NLW_blk00000416_ACOUT<29>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<28>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<27>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<26>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<25>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<24>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<23>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<22>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<21>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<20>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<19>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<18>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<17>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<16>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<15>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<14>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<13>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<12>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<11>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<10>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<9>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<8>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<7>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<6>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<5>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<4>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<3>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<2>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<1>_UNCONNECTED ;
wire \NLW_blk00000416_ACOUT<0>_UNCONNECTED ;
wire \NLW_blk00000416_CARRYOUT<3>_UNCONNECTED ;
wire \NLW_blk00000416_CARRYOUT<2>_UNCONNECTED ;
wire \NLW_blk00000416_CARRYOUT<1>_UNCONNECTED ;
wire \NLW_blk00000416_CARRYOUT<0>_UNCONNECTED ;
wire \NLW_blk00000416_P<47>_UNCONNECTED ;
wire \NLW_blk00000416_P<46>_UNCONNECTED ;
wire \NLW_blk00000416_P<45>_UNCONNECTED ;
wire \NLW_blk00000416_P<44>_UNCONNECTED ;
wire \NLW_blk00000416_P<43>_UNCONNECTED ;
wire \NLW_blk00000416_P<42>_UNCONNECTED ;
wire \NLW_blk00000416_P<41>_UNCONNECTED ;
wire \NLW_blk00000416_P<40>_UNCONNECTED ;
wire \NLW_blk00000416_P<39>_UNCONNECTED ;
wire \NLW_blk00000416_P<38>_UNCONNECTED ;
wire \NLW_blk00000416_P<37>_UNCONNECTED ;
wire \NLW_blk00000416_P<36>_UNCONNECTED ;
wire \NLW_blk00000416_P<35>_UNCONNECTED ;
wire \NLW_blk00000416_P<34>_UNCONNECTED ;
wire \NLW_blk00000416_P<33>_UNCONNECTED ;
wire \NLW_blk00000416_P<32>_UNCONNECTED ;
wire \NLW_blk00000416_P<31>_UNCONNECTED ;
wire \NLW_blk00000416_P<30>_UNCONNECTED ;
wire \NLW_blk00000416_P<29>_UNCONNECTED ;
wire \NLW_blk00000416_P<28>_UNCONNECTED ;
wire \NLW_blk00000416_P<27>_UNCONNECTED ;
wire \NLW_blk00000416_P<26>_UNCONNECTED ;
wire \NLW_blk00000416_P<25>_UNCONNECTED ;
wire \NLW_blk00000416_P<24>_UNCONNECTED ;
wire \NLW_blk00000416_P<23>_UNCONNECTED ;
wire \NLW_blk00000416_P<22>_UNCONNECTED ;
wire \NLW_blk00000416_P<21>_UNCONNECTED ;
wire \NLW_blk00000416_P<20>_UNCONNECTED ;
wire \NLW_blk00000416_P<19>_UNCONNECTED ;
wire \NLW_blk00000416_P<18>_UNCONNECTED ;
wire \NLW_blk00000416_P<17>_UNCONNECTED ;
wire \NLW_blk00000416_P<16>_UNCONNECTED ;
wire \NLW_blk00000416_P<15>_UNCONNECTED ;
wire \NLW_blk00000416_P<14>_UNCONNECTED ;
wire \NLW_blk00000416_P<13>_UNCONNECTED ;
wire \NLW_blk00000416_P<12>_UNCONNECTED ;
wire \NLW_blk00000416_P<11>_UNCONNECTED ;
wire \NLW_blk00000416_P<10>_UNCONNECTED ;
wire \NLW_blk00000416_P<9>_UNCONNECTED ;
wire \NLW_blk00000416_P<8>_UNCONNECTED ;
wire \NLW_blk00000416_P<7>_UNCONNECTED ;
wire \NLW_blk00000416_P<6>_UNCONNECTED ;
wire \NLW_blk00000416_P<5>_UNCONNECTED ;
wire \NLW_blk00000416_P<4>_UNCONNECTED ;
wire \NLW_blk00000416_P<3>_UNCONNECTED ;
wire \NLW_blk00000416_P<2>_UNCONNECTED ;
wire \NLW_blk00000416_P<1>_UNCONNECTED ;
wire \NLW_blk00000416_P<0>_UNCONNECTED ;
wire [10 : 0] \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op ;
wire [51 : 0] \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op ;
assign
result[63] = \U0/op_inst/FLT_PT_OP/MULT.OP/OP/sign_op ,
result[62] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [10],
result[61] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [9],
result[60] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [8],
result[59] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [7],
result[58] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [6],
result[57] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [5],
result[56] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [4],
result[55] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [3],
result[54] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [2],
result[53] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [1],
result[52] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [0],
result[51] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [51],
result[50] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [50],
result[49] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [49],
result[48] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [48],
result[47] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [47],
result[46] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [46],
result[45] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [45],
result[44] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [44],
result[43] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [43],
result[42] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [42],
result[41] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [41],
result[40] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [40],
result[39] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [39],
result[38] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [38],
result[37] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [37],
result[36] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [36],
result[35] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [35],
result[34] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [34],
result[33] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [33],
result[32] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [32],
result[31] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [31],
result[30] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [30],
result[29] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [29],
result[28] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [28],
result[27] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [27],
result[26] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [26],
result[25] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [25],
result[24] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [24],
result[23] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [23],
result[22] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [22],
result[21] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [21],
result[20] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [20],
result[19] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [19],
result[18] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [18],
result[17] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [17],
result[16] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [16],
result[15] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [15],
result[14] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [14],
result[13] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [13],
result[12] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [12],
result[11] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [11],
result[10] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [10],
result[9] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [9],
result[8] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [8],
result[7] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [7],
result[6] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [6],
result[5] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [5],
result[4] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [4],
result[3] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [3],
result[2] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [2],
result[1] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [1],
result[0] = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [0],
rdy = \NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/HND_SHK/RDY ;
VCC blk00000001 (
.P(sig00000001)
);
GND blk00000002 (
.G(sig00000461)
);
FDE #(
.INIT ( 1'b0 ))
blk00000003 (
.C(clk),
.CE(ce),
.D(sig00000091),
.Q(sig0000007e)
);
FDE #(
.INIT ( 1'b0 ))
blk00000004 (
.C(clk),
.CE(ce),
.D(sig00000092),
.Q(sig0000007b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000005 (
.C(clk),
.CE(ce),
.D(sig0000009f),
.Q(sig0000007f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000006 (
.C(clk),
.CE(ce),
.D(sig0000008f),
.Q(sig000000a2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000007 (
.C(clk),
.CE(ce),
.D(sig00000090),
.Q(sig0000009a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000008 (
.C(clk),
.CE(ce),
.D(sig00000083),
.Q(sig000000a3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000009 (
.C(clk),
.CE(ce),
.D(sig00000082),
.Q(sig000000a4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000a (
.C(clk),
.CE(ce),
.D(sig00000081),
.Q(sig000000a6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000000b (
.C(clk),
.CE(ce),
.D(sig00000080),
.Q(sig000000a7)
);
XORCY blk0000000c (
.CI(sig000000b7),
.LI(sig00000461),
.O(sig000000b5)
);
XORCY blk0000000d (
.CI(sig000000b9),
.LI(sig0000008e),
.O(sig000000b6)
);
MUXCY blk0000000e (
.CI(sig000000b9),
.DI(b[62]),
.S(sig0000008e),
.O(sig000000b7)
);
XORCY blk0000000f (
.CI(sig000000bb),
.LI(sig0000008d),
.O(sig000000b8)
);
MUXCY blk00000010 (
.CI(sig000000bb),
.DI(b[61]),
.S(sig0000008d),
.O(sig000000b9)
);
XORCY blk00000011 (
.CI(sig000000bd),
.LI(sig0000008c),
.O(sig000000ba)
);
MUXCY blk00000012 (
.CI(sig000000bd),
.DI(b[60]),
.S(sig0000008c),
.O(sig000000bb)
);
XORCY blk00000013 (
.CI(sig000000bf),
.LI(sig0000008b),
.O(sig000000bc)
);
MUXCY blk00000014 (
.CI(sig000000bf),
.DI(b[59]),
.S(sig0000008b),
.O(sig000000bd)
);
XORCY blk00000015 (
.CI(sig000000c1),
.LI(sig0000008a),
.O(sig000000be)
);
MUXCY blk00000016 (
.CI(sig000000c1),
.DI(b[58]),
.S(sig0000008a),
.O(sig000000bf)
);
XORCY blk00000017 (
.CI(sig000000c3),
.LI(sig00000089),
.O(sig000000c0)
);
MUXCY blk00000018 (
.CI(sig000000c3),
.DI(b[57]),
.S(sig00000089),
.O(sig000000c1)
);
XORCY blk00000019 (
.CI(sig000000c5),
.LI(sig00000088),
.O(sig000000c2)
);
MUXCY blk0000001a (
.CI(sig000000c5),
.DI(b[56]),
.S(sig00000088),
.O(sig000000c3)
);
XORCY blk0000001b (
.CI(sig000000c7),
.LI(sig00000087),
.O(sig000000c4)
);
MUXCY blk0000001c (
.CI(sig000000c7),
.DI(b[55]),
.S(sig00000087),
.O(sig000000c5)
);
XORCY blk0000001d (
.CI(sig000000c9),
.LI(sig00000086),
.O(sig000000c6)
);
MUXCY blk0000001e (
.CI(sig000000c9),
.DI(b[54]),
.S(sig00000086),
.O(sig000000c7)
);
XORCY blk0000001f (
.CI(sig000000cb),
.LI(sig00000085),
.O(sig000000c8)
);
MUXCY blk00000020 (
.CI(sig000000cb),
.DI(b[53]),
.S(sig00000085),
.O(sig000000c9)
);
XORCY blk00000021 (
.CI(sig00000001),
.LI(sig00000084),
.O(sig000000ca)
);
MUXCY blk00000022 (
.CI(sig00000001),
.DI(b[52]),
.S(sig00000084),
.O(sig000000cb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000023 (
.C(clk),
.CE(ce),
.D(sig000000b5),
.Q(sig000000a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000024 (
.C(clk),
.CE(ce),
.D(sig000000b6),
.Q(sig000000b4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000025 (
.C(clk),
.CE(ce),
.D(sig000000b8),
.Q(sig000000b3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000026 (
.C(clk),
.CE(ce),
.D(sig000000ba),
.Q(sig000000b2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000027 (
.C(clk),
.CE(ce),
.D(sig000000bc),
.Q(sig000000b1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000028 (
.C(clk),
.CE(ce),
.D(sig000000be),
.Q(sig000000b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000029 (
.C(clk),
.CE(ce),
.D(sig000000c0),
.Q(sig000000af)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002a (
.C(clk),
.CE(ce),
.D(sig000000c2),
.Q(sig000000ae)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002b (
.C(clk),
.CE(ce),
.D(sig000000c4),
.Q(sig000000ad)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002c (
.C(clk),
.CE(ce),
.D(sig000000c6),
.Q(sig000000ac)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002d (
.C(clk),
.CE(ce),
.D(sig000000c8),
.Q(sig000000ab)
);
FDE #(
.INIT ( 1'b0 ))
blk0000002e (
.C(clk),
.CE(ce),
.D(sig000000ca),
.Q(sig000000aa)
);
MUXCY blk0000002f (
.CI(sig000000df),
.DI(sig00000461),
.S(sig000000dd),
.O(sig000000de)
);
MUXCY blk00000030 (
.CI(sig000000e0),
.DI(sig00000461),
.S(sig000000d5),
.O(sig000000df)
);
MUXCY blk00000031 (
.CI(sig000000e1),
.DI(sig00000461),
.S(sig000000d6),
.O(sig000000e0)
);
MUXCY blk00000032 (
.CI(sig000000e2),
.DI(sig00000461),
.S(sig000000d7),
.O(sig000000e1)
);
MUXCY blk00000033 (
.CI(sig000000e3),
.DI(sig00000461),
.S(sig000000d8),
.O(sig000000e2)
);
MUXCY blk00000034 (
.CI(sig000000e4),
.DI(sig00000461),
.S(sig000000d9),
.O(sig000000e3)
);
MUXCY blk00000035 (
.CI(sig000000e5),
.DI(sig00000461),
.S(sig000000da),
.O(sig000000e4)
);
MUXCY blk00000036 (
.CI(sig000000e6),
.DI(sig00000461),
.S(sig000000db),
.O(sig000000e5)
);
MUXCY blk00000037 (
.CI(sig00000001),
.DI(sig00000461),
.S(sig000000dc),
.O(sig000000e6)
);
FDE #(
.INIT ( 1'b0 ))
blk00000038 (
.C(clk),
.CE(ce),
.D(sig000000de),
.Q(sig000000a5)
);
MUXCY blk00000039 (
.CI(sig000000e8),
.DI(sig00000461),
.S(sig000000d4),
.O(sig000000e7)
);
MUXCY blk0000003a (
.CI(sig000000e9),
.DI(sig00000461),
.S(sig000000cc),
.O(sig000000e8)
);
MUXCY blk0000003b (
.CI(sig000000ea),
.DI(sig00000461),
.S(sig000000cd),
.O(sig000000e9)
);
MUXCY blk0000003c (
.CI(sig000000eb),
.DI(sig00000461),
.S(sig000000ce),
.O(sig000000ea)
);
MUXCY blk0000003d (
.CI(sig000000ec),
.DI(sig00000461),
.S(sig000000cf),
.O(sig000000eb)
);
MUXCY blk0000003e (
.CI(sig000000ed),
.DI(sig00000461),
.S(sig000000d0),
.O(sig000000ec)
);
MUXCY blk0000003f (
.CI(sig000000ee),
.DI(sig00000461),
.S(sig000000d1),
.O(sig000000ed)
);
MUXCY blk00000040 (
.CI(sig000000ef),
.DI(sig00000461),
.S(sig000000d2),
.O(sig000000ee)
);
MUXCY blk00000041 (
.CI(sig00000001),
.DI(sig00000461),
.S(sig000000d3),
.O(sig000000ef)
);
FDE #(
.INIT ( 1'b0 ))
blk00000042 (
.C(clk),
.CE(ce),
.D(sig000000e7),
.Q(sig000000a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000043 (
.C(clk),
.CE(ce),
.D(sig00000097),
.Q(sig000000f1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000044 (
.C(clk),
.CE(ce),
.D(sig00000096),
.Q(sig000000f0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000045 (
.C(clk),
.CE(ce),
.D(sig000000f2),
.Q(sig0000009f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000046 (
.C(clk),
.CE(ce),
.D(sig000000f3),
.Q(sig000000f2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000047 (
.C(clk),
.CE(ce),
.D(sig000000f4),
.Q(sig000000f3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000048 (
.C(clk),
.CE(ce),
.D(sig000000f5),
.Q(sig000000f4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000049 (
.C(clk),
.CE(ce),
.D(sig000000f6),
.Q(sig000000f5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004a (
.C(clk),
.CE(ce),
.D(sig000000f7),
.Q(sig000000f6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004b (
.C(clk),
.CE(ce),
.D(sig000000f8),
.Q(sig000000f7)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004c (
.C(clk),
.CE(ce),
.D(sig000000f9),
.Q(sig000000f8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004d (
.C(clk),
.CE(ce),
.D(sig000000fa),
.Q(sig000000f9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004e (
.C(clk),
.CE(ce),
.D(sig000000fb),
.Q(sig000000fa)
);
FDE #(
.INIT ( 1'b0 ))
blk0000004f (
.C(clk),
.CE(ce),
.D(sig00000098),
.Q(sig000000fb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000050 (
.C(clk),
.CE(ce),
.D(sig00000095),
.Q(sig000000ff)
);
FDE #(
.INIT ( 1'b0 ))
blk00000051 (
.C(clk),
.CE(ce),
.D(sig00000099),
.Q(sig000000fe)
);
FDE #(
.INIT ( 1'b0 ))
blk00000052 (
.C(clk),
.CE(ce),
.D(sig00000093),
.Q(sig000000fd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000053 (
.C(clk),
.CE(ce),
.D(sig00000094),
.Q(sig000000fc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000054 (
.C(clk),
.CE(ce),
.D(sig0000007e),
.Q(sig00000007)
);
FDE #(
.INIT ( 1'b0 ))
blk00000055 (
.C(clk),
.CE(ce),
.D(sig0000007b),
.Q(sig00000005)
);
FDE #(
.INIT ( 1'b0 ))
blk00000056 (
.C(clk),
.CE(ce),
.D(sig00000079),
.Q(sig00000003)
);
FDE #(
.INIT ( 1'b0 ))
blk00000057 (
.C(clk),
.CE(ce),
.D(sig0000007c),
.Q(sig00000004)
);
FDE #(
.INIT ( 1'b0 ))
blk00000058 (
.C(clk),
.CE(ce),
.D(sig0000007d),
.Q(sig00000006)
);
FDE #(
.INIT ( 1'b0 ))
blk00000059 (
.C(clk),
.CE(ce),
.D(sig000001c5),
.Q(sig00000148)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005a (
.C(clk),
.CE(ce),
.D(sig000001c6),
.Q(sig000001a2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005b (
.C(clk),
.CE(ce),
.D(a[16]),
.Q(sig000001a3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005c (
.C(clk),
.CE(ce),
.D(a[15]),
.Q(sig000001a4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005d (
.C(clk),
.CE(ce),
.D(a[14]),
.Q(sig000001a5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005e (
.C(clk),
.CE(ce),
.D(a[13]),
.Q(sig000001a6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000005f (
.C(clk),
.CE(ce),
.D(a[12]),
.Q(sig000001a7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000060 (
.C(clk),
.CE(ce),
.D(a[11]),
.Q(sig000001a8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000061 (
.C(clk),
.CE(ce),
.D(a[10]),
.Q(sig000001a9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000062 (
.C(clk),
.CE(ce),
.D(a[9]),
.Q(sig000001aa)
);
FDE #(
.INIT ( 1'b0 ))
blk00000063 (
.C(clk),
.CE(ce),
.D(a[8]),
.Q(sig000001ab)
);
FDE #(
.INIT ( 1'b0 ))
blk00000064 (
.C(clk),
.CE(ce),
.D(a[7]),
.Q(sig000001ac)
);
FDE #(
.INIT ( 1'b0 ))
blk00000065 (
.C(clk),
.CE(ce),
.D(a[6]),
.Q(sig000001ad)
);
FDE #(
.INIT ( 1'b0 ))
blk00000066 (
.C(clk),
.CE(ce),
.D(a[5]),
.Q(sig000001ae)
);
FDE #(
.INIT ( 1'b0 ))
blk00000067 (
.C(clk),
.CE(ce),
.D(a[4]),
.Q(sig000001af)
);
FDE #(
.INIT ( 1'b0 ))
blk00000068 (
.C(clk),
.CE(ce),
.D(a[3]),
.Q(sig000001b0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000069 (
.C(clk),
.CE(ce),
.D(a[2]),
.Q(sig000001b1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006a (
.C(clk),
.CE(ce),
.D(a[1]),
.Q(sig000001b2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006b (
.C(clk),
.CE(ce),
.D(a[0]),
.Q(sig000001b3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006c (
.C(clk),
.CE(ce),
.D(b[33]),
.Q(sig000001b4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006d (
.C(clk),
.CE(ce),
.D(b[32]),
.Q(sig000001b5)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006e (
.C(clk),
.CE(ce),
.D(b[31]),
.Q(sig000001b6)
);
FDE #(
.INIT ( 1'b0 ))
blk0000006f (
.C(clk),
.CE(ce),
.D(b[30]),
.Q(sig000001b7)
);
FDE #(
.INIT ( 1'b0 ))
blk00000070 (
.C(clk),
.CE(ce),
.D(b[29]),
.Q(sig000001b8)
);
FDE #(
.INIT ( 1'b0 ))
blk00000071 (
.C(clk),
.CE(ce),
.D(b[28]),
.Q(sig000001b9)
);
FDE #(
.INIT ( 1'b0 ))
blk00000072 (
.C(clk),
.CE(ce),
.D(b[27]),
.Q(sig000001ba)
);
FDE #(
.INIT ( 1'b0 ))
blk00000073 (
.C(clk),
.CE(ce),
.D(b[26]),
.Q(sig000001bb)
);
FDE #(
.INIT ( 1'b0 ))
blk00000074 (
.C(clk),
.CE(ce),
.D(b[25]),
.Q(sig000001bc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000075 (
.C(clk),
.CE(ce),
.D(b[24]),
.Q(sig000001bd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000076 (
.C(clk),
.CE(ce),
.D(b[23]),
.Q(sig000001be)
);
FDE #(
.INIT ( 1'b0 ))
blk00000077 (
.C(clk),
.CE(ce),
.D(b[22]),
.Q(sig000001bf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000078 (
.C(clk),
.CE(ce),
.D(b[21]),
.Q(sig000001c0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000079 (
.C(clk),
.CE(ce),
.D(b[20]),
.Q(sig000001c1)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007a (
.C(clk),
.CE(ce),
.D(b[19]),
.Q(sig000001c2)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007b (
.C(clk),
.CE(ce),
.D(b[18]),
.Q(sig000001c3)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007c (
.C(clk),
.CE(ce),
.D(b[17]),
.Q(sig000001c4)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007d (
.C(clk),
.CE(ce),
.D(sig000001d1),
.Q(sig0000001d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007e (
.C(clk),
.CE(ce),
.D(sig000001d0),
.Q(sig0000001e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000007f (
.C(clk),
.CE(ce),
.D(sig000001cf),
.Q(sig0000001f)
);
FDE #(
.INIT ( 1'b0 ))
blk00000080 (
.C(clk),
.CE(ce),
.D(sig000001ce),
.Q(sig00000020)
);
FDE #(
.INIT ( 1'b0 ))
blk00000081 (
.C(clk),
.CE(ce),
.D(sig000001cd),
.Q(sig00000021)
);
FDE #(
.INIT ( 1'b0 ))
blk00000082 (
.C(clk),
.CE(ce),
.D(sig000001cc),
.Q(sig00000022)
);
FDE #(
.INIT ( 1'b0 ))
blk00000083 (
.C(clk),
.CE(ce),
.D(sig000001cb),
.Q(sig00000023)
);
FDE #(
.INIT ( 1'b0 ))
blk00000084 (
.C(clk),
.CE(ce),
.D(sig000001ca),
.Q(sig00000024)
);
FDE #(
.INIT ( 1'b0 ))
blk00000085 (
.C(clk),
.CE(ce),
.D(sig000001c9),
.Q(sig00000025)
);
FDE #(
.INIT ( 1'b0 ))
blk00000086 (
.C(clk),
.CE(ce),
.D(sig000001c8),
.Q(sig00000026)
);
FDE #(
.INIT ( 1'b0 ))
blk00000087 (
.C(clk),
.CE(ce),
.D(sig000001c7),
.Q(sig00000027)
);
FDE #(
.INIT ( 1'b0 ))
blk00000088 (
.C(clk),
.CE(ce),
.D(sig00000550),
.Q(sig0000016d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000089 (
.C(clk),
.CE(ce),
.D(sig0000016d),
.Q(sig00000149)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008a (
.C(clk),
.CE(ce),
.D(sig00000002),
.Q(sig00000460)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008b (
.C(clk),
.CE(ce),
.D(sig00000008),
.Q(sig00000437)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008c (
.C(clk),
.CE(ce),
.D(sig00000009),
.Q(sig0000047c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008d (
.C(clk),
.CE(ce),
.D(sig0000000a),
.Q(sig0000047b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008e (
.C(clk),
.CE(ce),
.D(sig0000000b),
.Q(sig0000047a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000008f (
.C(clk),
.CE(ce),
.D(sig0000000c),
.Q(sig00000479)
);
FDE #(
.INIT ( 1'b0 ))
blk00000090 (
.C(clk),
.CE(ce),
.D(sig0000000d),
.Q(sig00000478)
);
FDE #(
.INIT ( 1'b0 ))
blk00000091 (
.C(clk),
.CE(ce),
.D(sig0000000e),
.Q(sig00000477)
);
FDE #(
.INIT ( 1'b0 ))
blk00000092 (
.C(clk),
.CE(ce),
.D(sig0000000f),
.Q(sig00000476)
);
FDE #(
.INIT ( 1'b0 ))
blk00000093 (
.C(clk),
.CE(ce),
.D(sig00000010),
.Q(sig00000475)
);
FDE #(
.INIT ( 1'b0 ))
blk00000094 (
.C(clk),
.CE(ce),
.D(sig00000011),
.Q(sig00000474)
);
FDE #(
.INIT ( 1'b0 ))
blk00000095 (
.C(clk),
.CE(ce),
.D(sig00000012),
.Q(sig00000473)
);
FDE #(
.INIT ( 1'b0 ))
blk00000096 (
.C(clk),
.CE(ce),
.D(sig00000013),
.Q(sig00000472)
);
FDE #(
.INIT ( 1'b0 ))
blk00000097 (
.C(clk),
.CE(ce),
.D(sig00000014),
.Q(sig00000471)
);
FDE #(
.INIT ( 1'b0 ))
blk00000098 (
.C(clk),
.CE(ce),
.D(sig00000015),
.Q(sig00000470)
);
FDE #(
.INIT ( 1'b0 ))
blk00000099 (
.C(clk),
.CE(ce),
.D(sig00000016),
.Q(sig0000046f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009a (
.C(clk),
.CE(ce),
.D(sig00000017),
.Q(sig0000046e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009b (
.C(clk),
.CE(ce),
.D(sig00000018),
.Q(sig0000046d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009c (
.C(clk),
.CE(ce),
.D(sig00000019),
.Q(sig0000046c)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009d (
.C(clk),
.CE(ce),
.D(sig0000001a),
.Q(sig0000046b)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009e (
.C(clk),
.CE(ce),
.D(sig0000001b),
.Q(sig0000046a)
);
FDE #(
.INIT ( 1'b0 ))
blk0000009f (
.C(clk),
.CE(ce),
.D(sig0000001c),
.Q(sig00000469)
);
FDE #(
.INIT ( 1'b0 ))
blk000000a0 (
.C(clk),
.CE(ce),
.D(sig0000001d),
.Q(sig00000462)
);
MUXCY blk000000a1 (
.CI(sig00000001),
.DI(sig00000461),
.S(sig00000481),
.O(sig0000047e)
);
MUXCY blk000000a2 (
.CI(sig0000047e),
.DI(sig00000461),
.S(sig00000461),
.O(sig0000047f)
);
MUXCY blk000000a3 (
.CI(sig0000047f),
.DI(sig00000001),
.S(sig00000480),
.O(sig0000045f)
);
XORCY blk000000a4 (
.CI(sig00000484),
.LI(sig00000461),
.O(sig00000482)
);
XORCY blk000000a5 (
.CI(sig00000486),
.LI(sig00000451),
.O(sig00000483)
);
MUXCY blk000000a6 (
.CI(sig00000486),
.DI(sig00000461),
.S(sig00000451),
.O(sig00000484)
);
XORCY blk000000a7 (
.CI(sig00000488),
.LI(sig00000450),
.O(sig00000485)
);
MUXCY blk000000a8 (
.CI(sig00000488),
.DI(sig00000461),
.S(sig00000450),
.O(sig00000486)
);
XORCY blk000000a9 (
.CI(sig0000048a),
.LI(sig0000044f),
.O(sig00000487)
);
MUXCY blk000000aa (
.CI(sig0000048a),
.DI(sig00000461),
.S(sig0000044f),
.O(sig00000488)
);
XORCY blk000000ab (
.CI(sig0000048c),
.LI(sig0000044e),
.O(sig00000489)
);
MUXCY blk000000ac (
.CI(sig0000048c),
.DI(sig00000461),
.S(sig0000044e),
.O(sig0000048a)
);
XORCY blk000000ad (
.CI(sig0000048e),
.LI(sig0000044d),
.O(sig0000048b)
);
MUXCY blk000000ae (
.CI(sig0000048e),
.DI(sig00000461),
.S(sig0000044d),
.O(sig0000048c)
);
XORCY blk000000af (
.CI(sig00000490),
.LI(sig0000044c),
.O(sig0000048d)
);
MUXCY blk000000b0 (
.CI(sig00000490),
.DI(sig00000461),
.S(sig0000044c),
.O(sig0000048e)
);
XORCY blk000000b1 (
.CI(sig00000492),
.LI(sig0000044b),
.O(sig0000048f)
);
MUXCY blk000000b2 (
.CI(sig00000492),
.DI(sig00000461),
.S(sig0000044b),
.O(sig00000490)
);
XORCY blk000000b3 (
.CI(sig00000494),
.LI(sig0000044a),
.O(sig00000491)
);
MUXCY blk000000b4 (
.CI(sig00000494),
.DI(sig00000461),
.S(sig0000044a),
.O(sig00000492)
);
XORCY blk000000b5 (
.CI(sig00000496),
.LI(sig00000449),
.O(sig00000493)
);
MUXCY blk000000b6 (
.CI(sig00000496),
.DI(sig00000461),
.S(sig00000449),
.O(sig00000494)
);
XORCY blk000000b7 (
.CI(sig00000498),
.LI(sig00000448),
.O(sig00000495)
);
MUXCY blk000000b8 (
.CI(sig00000498),
.DI(sig00000461),
.S(sig00000448),
.O(sig00000496)
);
XORCY blk000000b9 (
.CI(sig0000049a),
.LI(sig00000447),
.O(sig00000497)
);
MUXCY blk000000ba (
.CI(sig0000049a),
.DI(sig00000461),
.S(sig00000447),
.O(sig00000498)
);
XORCY blk000000bb (
.CI(sig0000049c),
.LI(sig00000446),
.O(sig00000499)
);
MUXCY blk000000bc (
.CI(sig0000049c),
.DI(sig00000461),
.S(sig00000446),
.O(sig0000049a)
);
XORCY blk000000bd (
.CI(sig0000049e),
.LI(sig00000445),
.O(sig0000049b)
);
MUXCY blk000000be (
.CI(sig0000049e),
.DI(sig00000461),
.S(sig00000445),
.O(sig0000049c)
);
XORCY blk000000bf (
.CI(sig000004a0),
.LI(sig00000444),
.O(sig0000049d)
);
MUXCY blk000000c0 (
.CI(sig000004a0),
.DI(sig00000461),
.S(sig00000444),
.O(sig0000049e)
);
XORCY blk000000c1 (
.CI(sig000004a2),
.LI(sig00000443),
.O(sig0000049f)
);
MUXCY blk000000c2 (
.CI(sig000004a2),
.DI(sig00000461),
.S(sig00000443),
.O(sig000004a0)
);
XORCY blk000000c3 (
.CI(sig000004a4),
.LI(sig00000442),
.O(sig000004a1)
);
MUXCY blk000000c4 (
.CI(sig000004a4),
.DI(sig00000461),
.S(sig00000442),
.O(sig000004a2)
);
XORCY blk000000c5 (
.CI(sig000004a6),
.LI(sig00000441),
.O(sig000004a3)
);
MUXCY blk000000c6 (
.CI(sig000004a6),
.DI(sig00000461),
.S(sig00000441),
.O(sig000004a4)
);
XORCY blk000000c7 (
.CI(sig000004a8),
.LI(sig00000440),
.O(sig000004a5)
);
MUXCY blk000000c8 (
.CI(sig000004a8),
.DI(sig00000461),
.S(sig00000440),
.O(sig000004a6)
);
XORCY blk000000c9 (
.CI(sig000004aa),
.LI(sig0000043f),
.O(sig000004a7)
);
MUXCY blk000000ca (
.CI(sig000004aa),
.DI(sig00000461),
.S(sig0000043f),
.O(sig000004a8)
);
XORCY blk000000cb (
.CI(sig000004ac),
.LI(sig0000043e),
.O(sig000004a9)
);
MUXCY blk000000cc (
.CI(sig000004ac),
.DI(sig00000461),
.S(sig0000043e),
.O(sig000004aa)
);
XORCY blk000000cd (
.CI(sig000004ae),
.LI(sig0000043d),
.O(sig000004ab)
);
MUXCY blk000000ce (
.CI(sig000004ae),
.DI(sig00000461),
.S(sig0000043d),
.O(sig000004ac)
);
XORCY blk000000cf (
.CI(sig000004b0),
.LI(sig0000043c),
.O(sig000004ad)
);
MUXCY blk000000d0 (
.CI(sig000004b0),
.DI(sig00000461),
.S(sig0000043c),
.O(sig000004ae)
);
XORCY blk000000d1 (
.CI(sig000004b2),
.LI(sig0000043b),
.O(sig000004af)
);
MUXCY blk000000d2 (
.CI(sig000004b2),
.DI(sig00000461),
.S(sig0000043b),
.O(sig000004b0)
);
XORCY blk000000d3 (
.CI(sig000004b4),
.LI(sig0000043a),
.O(sig000004b1)
);
MUXCY blk000000d4 (
.CI(sig000004b4),
.DI(sig00000461),
.S(sig0000043a),
.O(sig000004b2)
);
XORCY blk000000d5 (
.CI(sig000004b6),
.LI(sig00000439),
.O(sig000004b3)
);
MUXCY blk000000d6 (
.CI(sig000004b6),
.DI(sig00000461),
.S(sig00000439),
.O(sig000004b4)
);
XORCY blk000000d7 (
.CI(sig0000045f),
.LI(sig00000438),
.O(sig000004b5)
);
MUXCY blk000000d8 (
.CI(sig0000045f),
.DI(sig00000461),
.S(sig00000438),
.O(sig000004b6)
);
FDE #(
.INIT ( 1'b0 ))
blk000000d9 (
.C(clk),
.CE(ce),
.D(sig00000482),
.Q(sig0000045e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000da (
.C(clk),
.CE(ce),
.D(sig000004d0),
.Q(sig00000054)
);
FDE #(
.INIT ( 1'b0 ))
blk000000db (
.C(clk),
.CE(ce),
.D(sig000004cf),
.Q(sig00000055)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dc (
.C(clk),
.CE(ce),
.D(sig000004ce),
.Q(sig00000056)
);
FDE #(
.INIT ( 1'b0 ))
blk000000dd (
.C(clk),
.CE(ce),
.D(sig000004cd),
.Q(sig00000057)
);
FDE #(
.INIT ( 1'b0 ))
blk000000de (
.C(clk),
.CE(ce),
.D(sig000004cc),
.Q(sig00000058)
);
FDE #(
.INIT ( 1'b0 ))
blk000000df (
.C(clk),
.CE(ce),
.D(sig000004cb),
.Q(sig00000059)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e0 (
.C(clk),
.CE(ce),
.D(sig000004ca),
.Q(sig0000005a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e1 (
.C(clk),
.CE(ce),
.D(sig000004c9),
.Q(sig0000005b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e2 (
.C(clk),
.CE(ce),
.D(sig000004c8),
.Q(sig0000005c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e3 (
.C(clk),
.CE(ce),
.D(sig000004c7),
.Q(sig0000005d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e4 (
.C(clk),
.CE(ce),
.D(sig000004c6),
.Q(sig0000005e)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e5 (
.C(clk),
.CE(ce),
.D(sig000004c5),
.Q(sig0000005f)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e6 (
.C(clk),
.CE(ce),
.D(sig000004c4),
.Q(sig00000060)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e7 (
.C(clk),
.CE(ce),
.D(sig000004c3),
.Q(sig00000061)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e8 (
.C(clk),
.CE(ce),
.D(sig000004c2),
.Q(sig00000062)
);
FDE #(
.INIT ( 1'b0 ))
blk000000e9 (
.C(clk),
.CE(ce),
.D(sig000004c1),
.Q(sig00000063)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ea (
.C(clk),
.CE(ce),
.D(sig000004c0),
.Q(sig00000064)
);
FDE #(
.INIT ( 1'b0 ))
blk000000eb (
.C(clk),
.CE(ce),
.D(sig000004bf),
.Q(sig00000065)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ec (
.C(clk),
.CE(ce),
.D(sig000004be),
.Q(sig00000066)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ed (
.C(clk),
.CE(ce),
.D(sig000004bd),
.Q(sig00000067)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ee (
.C(clk),
.CE(ce),
.D(sig000004bc),
.Q(sig00000068)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ef (
.C(clk),
.CE(ce),
.D(sig000004bb),
.Q(sig00000069)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f0 (
.C(clk),
.CE(ce),
.D(sig000004ba),
.Q(sig0000006a)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f1 (
.C(clk),
.CE(ce),
.D(sig000004b9),
.Q(sig0000006b)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f2 (
.C(clk),
.CE(ce),
.D(sig000004b8),
.Q(sig0000006c)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f3 (
.C(clk),
.CE(ce),
.D(sig000004b7),
.Q(sig0000006d)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f4 (
.C(clk),
.CE(ce),
.D(sig00000483),
.Q(sig000004d0)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f5 (
.C(clk),
.CE(ce),
.D(sig00000485),
.Q(sig000004cf)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f6 (
.C(clk),
.CE(ce),
.D(sig00000487),
.Q(sig000004ce)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f7 (
.C(clk),
.CE(ce),
.D(sig00000489),
.Q(sig000004cd)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f8 (
.C(clk),
.CE(ce),
.D(sig0000048b),
.Q(sig000004cc)
);
FDE #(
.INIT ( 1'b0 ))
blk000000f9 (
.C(clk),
.CE(ce),
.D(sig0000048d),
.Q(sig000004cb)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fa (
.C(clk),
.CE(ce),
.D(sig0000048f),
.Q(sig000004ca)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fb (
.C(clk),
.CE(ce),
.D(sig00000491),
.Q(sig000004c9)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fc (
.C(clk),
.CE(ce),
.D(sig00000493),
.Q(sig000004c8)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fd (
.C(clk),
.CE(ce),
.D(sig00000495),
.Q(sig000004c7)
);
FDE #(
.INIT ( 1'b0 ))
blk000000fe (
.C(clk),
.CE(ce),
.D(sig00000497),
.Q(sig000004c6)
);
FDE #(
.INIT ( 1'b0 ))
blk000000ff (
.C(clk),
.CE(ce),
.D(sig00000499),
.Q(sig000004c5)
);
FDE #(
.INIT ( 1'b0 ))
blk00000100 (
.C(clk),
.CE(ce),
.D(sig0000049b),
.Q(sig000004c4)
);
FDE #(
.INIT ( 1'b0 ))
blk00000101 (
.C(clk),
.CE(ce),
.D(sig0000049d),
.Q(sig000004c3)
);
FDE #(
.INIT ( 1'b0 ))
blk00000102 (
.C(clk),
.CE(ce),
.D(sig0000049f),
.Q(sig000004c2)
);
FDE #(
.INIT ( 1'b0 ))
blk00000103 (
.C(clk),
.CE(ce),
.D(sig000004a1),
.Q(sig000004c1)
);
FDE #(
.INIT ( 1'b0 ))
blk00000104 (
.C(clk),
.CE(ce),
.D(sig000004a3),
.Q(sig000004c0)
);
FDE #(
.INIT ( 1'b0 ))
blk00000105 (
.C(clk),
.CE(ce),
.D(sig000004a5),
.Q(sig000004bf)
);
FDE #(
.INIT ( 1'b0 ))
blk00000106 (
.C(clk),
.CE(ce),
.D(sig000004a7),
.Q(sig000004be)
);
FDE #(
.INIT ( 1'b0 ))
blk00000107 (
.C(clk),
.CE(ce),
.D(sig000004a9),
.Q(sig000004bd)
);
FDE #(
.INIT ( 1'b0 ))
blk00000108 (
.C(clk),
.CE(ce),
.D(sig000004ab),
.Q(sig000004bc)
);
FDE #(
.INIT ( 1'b0 ))
blk00000109 (
.C(clk),
.CE(ce),
.D(sig000004ad),
.Q(sig000004bb)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010a (
.C(clk),
.CE(ce),
.D(sig000004af),
.Q(sig000004ba)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010b (
.C(clk),
.CE(ce),
.D(sig000004b1),
.Q(sig000004b9)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010c (
.C(clk),
.CE(ce),
.D(sig000004b3),
.Q(sig000004b8)
);
FDE #(
.INIT ( 1'b0 ))
blk0000010d (
.C(clk),
.CE(ce),
.D(sig000004b5),
.Q(sig000004b7)
);
XORCY blk0000010e (
.CI(sig000004d2),
.LI(sig00000461),
.O(sig000004d1)
);
XORCY blk0000010f (
.CI(sig000004d4),
.LI(sig0000041c),
.O(NLW_blk0000010f_O_UNCONNECTED)
);
MUXCY blk00000110 (
.CI(sig000004d4),
.DI(sig00000001),
.S(sig0000041c),
.O(sig000004d2)
);
XORCY blk00000111 (
.CI(sig000004d6),
.LI(sig00000436),
.O(sig000004d3)
);
MUXCY blk00000112 (
.CI(sig000004d6),
.DI(sig00000461),
.S(sig00000436),
.O(sig000004d4)
);
XORCY blk00000113 (
.CI(sig000004d8),
.LI(sig00000435),
.O(sig000004d5)
);
MUXCY blk00000114 (
.CI(sig000004d8),
.DI(sig00000461),
.S(sig00000435),
.O(sig000004d6)
);
XORCY blk00000115 (
.CI(sig000004da),
.LI(sig00000434),
.O(sig000004d7)
);
MUXCY blk00000116 (
.CI(sig000004da),
.DI(sig00000461),
.S(sig00000434),
.O(sig000004d8)
);
XORCY blk00000117 (
.CI(sig000004dc),
.LI(sig00000433),
.O(sig000004d9)
);
MUXCY blk00000118 (
.CI(sig000004dc),
.DI(sig00000461),
.S(sig00000433),
.O(sig000004da)
);
XORCY blk00000119 (
.CI(sig000004de),
.LI(sig00000432),
.O(sig000004db)
);
MUXCY blk0000011a (
.CI(sig000004de),
.DI(sig00000461),
.S(sig00000432),
.O(sig000004dc)
);
XORCY blk0000011b (
.CI(sig000004e0),
.LI(sig00000431),
.O(sig000004dd)
);
MUXCY blk0000011c (
.CI(sig000004e0),
.DI(sig00000461),
.S(sig00000431),
.O(sig000004de)
);
XORCY blk0000011d (
.CI(sig000004e2),
.LI(sig00000430),
.O(sig000004df)
);
MUXCY blk0000011e (
.CI(sig000004e2),
.DI(sig00000461),
.S(sig00000430),
.O(sig000004e0)
);
XORCY blk0000011f (
.CI(sig000004e4),
.LI(sig0000042f),
.O(sig000004e1)
);
MUXCY blk00000120 (
.CI(sig000004e4),
.DI(sig00000461),
.S(sig0000042f),
.O(sig000004e2)
);
XORCY blk00000121 (
.CI(sig000004e6),
.LI(sig0000042e),
.O(sig000004e3)
);
MUXCY blk00000122 (
.CI(sig000004e6),
.DI(sig00000461),
.S(sig0000042e),
.O(sig000004e4)
);
XORCY blk00000123 (
.CI(sig000004e8),
.LI(sig0000042d),
.O(sig000004e5)
);
MUXCY blk00000124 (
.CI(sig000004e8),
.DI(sig00000461),
.S(sig0000042d),
.O(sig000004e6)
);
XORCY blk00000125 (
.CI(sig000004ea),
.LI(sig0000042c),
.O(sig000004e7)
);
MUXCY blk00000126 (
.CI(sig000004ea),
.DI(sig00000461),
.S(sig0000042c),
.O(sig000004e8)
);
XORCY blk00000127 (
.CI(sig000004ec),
.LI(sig0000042b),
.O(sig000004e9)
);
MUXCY blk00000128 (
.CI(sig000004ec),
.DI(sig00000461),
.S(sig0000042b),
.O(sig000004ea)
);
XORCY blk00000129 (
.CI(sig000004ee),
.LI(sig0000042a),
.O(sig000004eb)
);
MUXCY blk0000012a (
.CI(sig000004ee),
.DI(sig00000461),
.S(sig0000042a),
.O(sig000004ec)
);
XORCY blk0000012b (
.CI(sig000004f0),
.LI(sig00000429),
.O(sig000004ed)
);
MUXCY blk0000012c (
.CI(sig000004f0),
.DI(sig00000461),
.S(sig00000429),
.O(sig000004ee)
);
XORCY blk0000012d (
.CI(sig000004f2),
.LI(sig00000428),
.O(sig000004ef)
);
MUXCY blk0000012e (
.CI(sig000004f2),
.DI(sig00000461),
.S(sig00000428),
.O(sig000004f0)
);
XORCY blk0000012f (
.CI(sig000004f4),
.LI(sig00000427),
.O(sig000004f1)
);
MUXCY blk00000130 (
.CI(sig000004f4),
.DI(sig00000461),
.S(sig00000427),
.O(sig000004f2)
);
XORCY blk00000131 (
.CI(sig000004f6),
.LI(sig00000426),
.O(sig000004f3)
);
MUXCY blk00000132 (
.CI(sig000004f6),
.DI(sig00000461),
.S(sig00000426),
.O(sig000004f4)
);
XORCY blk00000133 (
.CI(sig000004f8),
.LI(sig00000425),
.O(sig000004f5)
);
MUXCY blk00000134 (
.CI(sig000004f8),
.DI(sig00000461),
.S(sig00000425),
.O(sig000004f6)
);
XORCY blk00000135 (
.CI(sig000004fa),
.LI(sig00000424),
.O(sig000004f7)
);
MUXCY blk00000136 (
.CI(sig000004fa),
.DI(sig00000461),
.S(sig00000424),
.O(sig000004f8)
);
XORCY blk00000137 (
.CI(sig000004fc),
.LI(sig00000423),
.O(sig000004f9)
);
MUXCY blk00000138 (
.CI(sig000004fc),
.DI(sig00000461),
.S(sig00000423),
.O(sig000004fa)
);
XORCY blk00000139 (
.CI(sig000004fe),
.LI(sig00000422),
.O(sig000004fb)
);
MUXCY blk0000013a (
.CI(sig000004fe),
.DI(sig00000461),
.S(sig00000422),
.O(sig000004fc)
);
XORCY blk0000013b (
.CI(sig00000500),
.LI(sig00000421),
.O(sig000004fd)
);
MUXCY blk0000013c (
.CI(sig00000500),
.DI(sig00000461),
.S(sig00000421),
.O(sig000004fe)
);
XORCY blk0000013d (
.CI(sig00000502),
.LI(sig00000420),
.O(sig000004ff)
);
MUXCY blk0000013e (
.CI(sig00000502),
.DI(sig00000461),
.S(sig00000420),
.O(sig00000500)
);
XORCY blk0000013f (
.CI(sig00000504),
.LI(sig0000041f),
.O(sig00000501)
);
MUXCY blk00000140 (
.CI(sig00000504),
.DI(sig00000461),
.S(sig0000041f),
.O(sig00000502)
);
XORCY blk00000141 (
.CI(sig00000506),
.LI(sig0000041e),
.O(sig00000503)
);
MUXCY blk00000142 (
.CI(sig00000506),
.DI(sig00000461),
.S(sig0000041e),
.O(sig00000504)
);
XORCY blk00000143 (
.CI(sig0000045e),
.LI(sig0000041d),
.O(sig00000505)
);
MUXCY blk00000144 (
.CI(sig0000045e),
.DI(sig00000461),
.S(sig0000041d),
.O(sig00000506)
);
FDE #(
.INIT ( 1'b0 ))
blk00000145 (
.C(clk),
.CE(ce),
.D(sig000004d1),
.Q(sig0000045d)
);
FDE #(
.INIT ( 1'b0 ))
blk00000146 (
.C(clk),
.CE(ce),
.D(sig000004d3),
.Q(sig0000003a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000147 (
.C(clk),
.CE(ce),
.D(sig000004d5),
.Q(sig0000003b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000148 (
.C(clk),
.CE(ce),
.D(sig000004d7),
.Q(sig0000003c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000149 (
.C(clk),
.CE(ce),
.D(sig000004d9),
.Q(sig0000003d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014a (
.C(clk),
.CE(ce),
.D(sig000004db),
.Q(sig0000003e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014b (
.C(clk),
.CE(ce),
.D(sig000004dd),
.Q(sig0000003f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014c (
.C(clk),
.CE(ce),
.D(sig000004df),
.Q(sig00000040)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014d (
.C(clk),
.CE(ce),
.D(sig000004e1),
.Q(sig00000041)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014e (
.C(clk),
.CE(ce),
.D(sig000004e3),
.Q(sig00000042)
);
FDE #(
.INIT ( 1'b0 ))
blk0000014f (
.C(clk),
.CE(ce),
.D(sig000004e5),
.Q(sig00000043)
);
FDE #(
.INIT ( 1'b0 ))
blk00000150 (
.C(clk),
.CE(ce),
.D(sig000004e7),
.Q(sig00000044)
);
FDE #(
.INIT ( 1'b0 ))
blk00000151 (
.C(clk),
.CE(ce),
.D(sig000004e9),
.Q(sig00000045)
);
FDE #(
.INIT ( 1'b0 ))
blk00000152 (
.C(clk),
.CE(ce),
.D(sig000004eb),
.Q(sig00000046)
);
FDE #(
.INIT ( 1'b0 ))
blk00000153 (
.C(clk),
.CE(ce),
.D(sig000004ed),
.Q(sig00000047)
);
FDE #(
.INIT ( 1'b0 ))
blk00000154 (
.C(clk),
.CE(ce),
.D(sig000004ef),
.Q(sig00000048)
);
FDE #(
.INIT ( 1'b0 ))
blk00000155 (
.C(clk),
.CE(ce),
.D(sig000004f1),
.Q(sig00000049)
);
FDE #(
.INIT ( 1'b0 ))
blk00000156 (
.C(clk),
.CE(ce),
.D(sig000004f3),
.Q(sig0000004a)
);
FDE #(
.INIT ( 1'b0 ))
blk00000157 (
.C(clk),
.CE(ce),
.D(sig000004f5),
.Q(sig0000004b)
);
FDE #(
.INIT ( 1'b0 ))
blk00000158 (
.C(clk),
.CE(ce),
.D(sig000004f7),
.Q(sig0000004c)
);
FDE #(
.INIT ( 1'b0 ))
blk00000159 (
.C(clk),
.CE(ce),
.D(sig000004f9),
.Q(sig0000004d)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015a (
.C(clk),
.CE(ce),
.D(sig000004fb),
.Q(sig0000004e)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015b (
.C(clk),
.CE(ce),
.D(sig000004fd),
.Q(sig0000004f)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015c (
.C(clk),
.CE(ce),
.D(sig000004ff),
.Q(sig00000050)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015d (
.C(clk),
.CE(ce),
.D(sig00000501),
.Q(sig00000051)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015e (
.C(clk),
.CE(ce),
.D(sig00000503),
.Q(sig00000052)
);
FDE #(
.INIT ( 1'b0 ))
blk0000015f (
.C(clk),
.CE(ce),
.D(sig00000505),
.Q(sig00000053)
);
XORCY blk00000160 (
.CI(sig00000507),
.LI(sig0000045c),
.O(sig0000006e)
);
XORCY blk00000161 (
.CI(sig00000508),
.LI(sig0000055b),
.O(sig0000006f)
);
MUXCY blk00000162 (
.CI(sig00000508),
.DI(sig00000461),
.S(sig0000055b),
.O(sig00000507)
);
XORCY blk00000163 (
.CI(sig00000509),
.LI(sig0000055c),
.O(sig00000070)
);
MUXCY blk00000164 (
.CI(sig00000509),
.DI(sig00000461),
.S(sig0000055c),
.O(sig00000508)
);
XORCY blk00000165 (
.CI(sig0000050a),
.LI(sig0000055d),
.O(sig00000071)
);
MUXCY blk00000166 (
.CI(sig0000050a),
.DI(sig00000461),
.S(sig0000055d),
.O(sig00000509)
);
XORCY blk00000167 (
.CI(sig0000050b),
.LI(sig0000055e),
.O(sig00000072)
);
MUXCY blk00000168 (
.CI(sig0000050b),
.DI(sig00000461),
.S(sig0000055e),
.O(sig0000050a)
);
XORCY blk00000169 (
.CI(sig0000050c),
.LI(sig0000055f),
.O(sig00000073)
);
MUXCY blk0000016a (
.CI(sig0000050c),
.DI(sig00000461),
.S(sig0000055f),
.O(sig0000050b)
);
XORCY blk0000016b (
.CI(sig0000050d),
.LI(sig00000560),
.O(sig00000074)
);
MUXCY blk0000016c (
.CI(sig0000050d),
.DI(sig00000461),
.S(sig00000560),
.O(sig0000050c)
);
XORCY blk0000016d (
.CI(sig0000050e),
.LI(sig00000561),
.O(sig00000075)
);
MUXCY blk0000016e (
.CI(sig0000050e),
.DI(sig00000461),
.S(sig00000561),
.O(sig0000050d)
);
XORCY blk0000016f (
.CI(sig0000050f),
.LI(sig00000562),
.O(sig00000076)
);
MUXCY blk00000170 (
.CI(sig0000050f),
.DI(sig00000461),
.S(sig00000562),
.O(sig0000050e)
);
XORCY blk00000171 (
.CI(sig00000510),
.LI(sig00000563),
.O(sig00000077)
);
MUXCY blk00000172 (
.CI(sig00000510),
.DI(sig00000461),
.S(sig00000563),
.O(sig0000050f)
);
XORCY blk00000173 (
.CI(sig0000045d),
.LI(sig00000564),
.O(sig00000078)
);
MUXCY blk00000174 (
.CI(sig0000045d),
.DI(sig00000461),
.S(sig00000564),
.O(sig00000510)
);
FD #(
.INIT ( 1'b0 ))
blk00000175 (
.C(clk),
.D(sig00000544),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [51])
);
FD #(
.INIT ( 1'b0 ))
blk00000176 (
.C(clk),
.D(sig00000543),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [50])
);
FD #(
.INIT ( 1'b0 ))
blk00000177 (
.C(clk),
.D(sig00000542),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [49])
);
FD #(
.INIT ( 1'b0 ))
blk00000178 (
.C(clk),
.D(sig00000541),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [48])
);
FD #(
.INIT ( 1'b0 ))
blk00000179 (
.C(clk),
.D(sig00000540),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [47])
);
FD #(
.INIT ( 1'b0 ))
blk0000017a (
.C(clk),
.D(sig0000053f),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [46])
);
FD #(
.INIT ( 1'b0 ))
blk0000017b (
.C(clk),
.D(sig0000053e),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [45])
);
FD #(
.INIT ( 1'b0 ))
blk0000017c (
.C(clk),
.D(sig0000053d),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [44])
);
FD #(
.INIT ( 1'b0 ))
blk0000017d (
.C(clk),
.D(sig0000053c),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [43])
);
FD #(
.INIT ( 1'b0 ))
blk0000017e (
.C(clk),
.D(sig0000053b),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [42])
);
FD #(
.INIT ( 1'b0 ))
blk0000017f (
.C(clk),
.D(sig0000053a),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [41])
);
FD #(
.INIT ( 1'b0 ))
blk00000180 (
.C(clk),
.D(sig00000539),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [40])
);
FD #(
.INIT ( 1'b0 ))
blk00000181 (
.C(clk),
.D(sig00000538),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [39])
);
FD #(
.INIT ( 1'b0 ))
blk00000182 (
.C(clk),
.D(sig00000537),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [38])
);
FD #(
.INIT ( 1'b0 ))
blk00000183 (
.C(clk),
.D(sig00000536),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [37])
);
FD #(
.INIT ( 1'b0 ))
blk00000184 (
.C(clk),
.D(sig00000535),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [36])
);
FD #(
.INIT ( 1'b0 ))
blk00000185 (
.C(clk),
.D(sig00000534),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [35])
);
FD #(
.INIT ( 1'b0 ))
blk00000186 (
.C(clk),
.D(sig00000533),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [34])
);
FD #(
.INIT ( 1'b0 ))
blk00000187 (
.C(clk),
.D(sig00000532),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [33])
);
FD #(
.INIT ( 1'b0 ))
blk00000188 (
.C(clk),
.D(sig00000531),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [32])
);
FD #(
.INIT ( 1'b0 ))
blk00000189 (
.C(clk),
.D(sig00000530),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [31])
);
FD #(
.INIT ( 1'b0 ))
blk0000018a (
.C(clk),
.D(sig0000052f),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [30])
);
FD #(
.INIT ( 1'b0 ))
blk0000018b (
.C(clk),
.D(sig0000052e),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [29])
);
FD #(
.INIT ( 1'b0 ))
blk0000018c (
.C(clk),
.D(sig0000052d),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [28])
);
FD #(
.INIT ( 1'b0 ))
blk0000018d (
.C(clk),
.D(sig0000052c),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [27])
);
FD #(
.INIT ( 1'b0 ))
blk0000018e (
.C(clk),
.D(sig0000052b),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [26])
);
FD #(
.INIT ( 1'b0 ))
blk0000018f (
.C(clk),
.D(sig0000052a),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [25])
);
FD #(
.INIT ( 1'b0 ))
blk00000190 (
.C(clk),
.D(sig00000529),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [24])
);
FD #(
.INIT ( 1'b0 ))
blk00000191 (
.C(clk),
.D(sig00000528),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [23])
);
FD #(
.INIT ( 1'b0 ))
blk00000192 (
.C(clk),
.D(sig00000527),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [22])
);
FD #(
.INIT ( 1'b0 ))
blk00000193 (
.C(clk),
.D(sig00000526),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [21])
);
FD #(
.INIT ( 1'b0 ))
blk00000194 (
.C(clk),
.D(sig00000525),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [20])
);
FD #(
.INIT ( 1'b0 ))
blk00000195 (
.C(clk),
.D(sig00000524),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [19])
);
FD #(
.INIT ( 1'b0 ))
blk00000196 (
.C(clk),
.D(sig00000523),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [18])
);
FD #(
.INIT ( 1'b0 ))
blk00000197 (
.C(clk),
.D(sig00000522),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [17])
);
FD #(
.INIT ( 1'b0 ))
blk00000198 (
.C(clk),
.D(sig00000521),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [16])
);
FD #(
.INIT ( 1'b0 ))
blk00000199 (
.C(clk),
.D(sig00000520),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [15])
);
FD #(
.INIT ( 1'b0 ))
blk0000019a (
.C(clk),
.D(sig0000051f),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [14])
);
FD #(
.INIT ( 1'b0 ))
blk0000019b (
.C(clk),
.D(sig0000051e),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [13])
);
FD #(
.INIT ( 1'b0 ))
blk0000019c (
.C(clk),
.D(sig0000051d),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [12])
);
FD #(
.INIT ( 1'b0 ))
blk0000019d (
.C(clk),
.D(sig0000051c),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [11])
);
FD #(
.INIT ( 1'b0 ))
blk0000019e (
.C(clk),
.D(sig0000051b),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [10])
);
FD #(
.INIT ( 1'b0 ))
blk0000019f (
.C(clk),
.D(sig0000051a),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [9])
);
FD #(
.INIT ( 1'b0 ))
blk000001a0 (
.C(clk),
.D(sig00000519),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [8])
);
FD #(
.INIT ( 1'b0 ))
blk000001a1 (
.C(clk),
.D(sig00000518),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [7])
);
FD #(
.INIT ( 1'b0 ))
blk000001a2 (
.C(clk),
.D(sig00000517),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [6])
);
FD #(
.INIT ( 1'b0 ))
blk000001a3 (
.C(clk),
.D(sig00000516),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [5])
);
FD #(
.INIT ( 1'b0 ))
blk000001a4 (
.C(clk),
.D(sig00000515),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [4])
);
FD #(
.INIT ( 1'b0 ))
blk000001a5 (
.C(clk),
.D(sig00000514),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [3])
);
FD #(
.INIT ( 1'b0 ))
blk000001a6 (
.C(clk),
.D(sig00000513),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [2])
);
FD #(
.INIT ( 1'b0 ))
blk000001a7 (
.C(clk),
.D(sig00000512),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [1])
);
FD #(
.INIT ( 1'b0 ))
blk000001a8 (
.C(clk),
.D(sig00000511),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [0])
);
FD #(
.INIT ( 1'b0 ))
blk000001a9 (
.C(clk),
.D(sig0000054f),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [10])
);
FD #(
.INIT ( 1'b0 ))
blk000001aa (
.C(clk),
.D(sig0000054e),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [9])
);
FD #(
.INIT ( 1'b0 ))
blk000001ab (
.C(clk),
.D(sig0000054d),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [8])
);
FD #(
.INIT ( 1'b0 ))
blk000001ac (
.C(clk),
.D(sig0000054c),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [7])
);
FD #(
.INIT ( 1'b0 ))
blk000001ad (
.C(clk),
.D(sig0000054b),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [6])
);
FD #(
.INIT ( 1'b0 ))
blk000001ae (
.C(clk),
.D(sig0000054a),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [5])
);
FD #(
.INIT ( 1'b0 ))
blk000001af (
.C(clk),
.D(sig00000549),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [4])
);
FD #(
.INIT ( 1'b0 ))
blk000001b0 (
.C(clk),
.D(sig00000548),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [3])
);
FD #(
.INIT ( 1'b0 ))
blk000001b1 (
.C(clk),
.D(sig00000547),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [2])
);
FD #(
.INIT ( 1'b0 ))
blk000001b2 (
.C(clk),
.D(sig00000546),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [1])
);
FD #(
.INIT ( 1'b0 ))
blk000001b3 (
.C(clk),
.D(sig00000545),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [0])
);
LUT6 #(
.INIT ( 64'hFFFFFFFF11101010 ))
blk000001b4 (
.I0(sig0000009b),
.I1(sig000000a1),
.I2(sig0000009c),
.I3(sig0000009e),
.I4(sig00000008),
.I5(sig000000a0),
.O(sig00000091)
);
LUT6 #(
.INIT ( 64'h0202020202000202 ))
blk000001b5 (
.I0(sig0000009d),
.I1(sig000000a0),
.I2(sig000000a1),
.I3(sig0000009b),
.I4(sig00000008),
.I5(sig0000009c),
.O(sig00000090)
);
LUT6 #(
.INIT ( 64'h153E113215141110 ))
blk000001b6 (
.I0(sig000000a4),
.I1(sig000000a7),
.I2(sig000000a3),
.I3(sig000000a6),
.I4(sig000000a8),
.I5(sig000000a5),
.O(sig00000097)
);
LUT3 #(
.INIT ( 8'h04 ))
blk000001b7 (
.I0(sig0000007e),
.I1(sig0000007b),
.I2(sig0000009a),
.O(sig00000079)
);
LUT4 #(
.INIT ( 16'hF888 ))
blk000001b8 (
.I0(sig000000b4),
.I1(sig000000a9),
.I2(sig000000aa),
.I3(sig0000007a),
.O(sig00000094)
);
LUT3 #(
.INIT ( 8'h10 ))
blk000001b9 (
.I0(sig000000aa),
.I1(sig000000b4),
.I2(sig0000007a),
.O(sig00000099)
);
LUT2 #(
.INIT ( 4'hE ))
blk000001ba (
.I0(sig000000a4),
.I1(sig000000a7),
.O(sig00000096)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001bb (
.I0(a[63]),
.I1(b[63]),
.O(sig0000008f)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001bc (
.I0(a[52]),
.I1(b[52]),
.O(sig00000084)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001bd (
.I0(a[53]),
.I1(b[53]),
.O(sig00000085)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001be (
.I0(a[54]),
.I1(b[54]),
.O(sig00000086)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001bf (
.I0(a[55]),
.I1(b[55]),
.O(sig00000087)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c0 (
.I0(a[56]),
.I1(b[56]),
.O(sig00000088)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c1 (
.I0(a[57]),
.I1(b[57]),
.O(sig00000089)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c2 (
.I0(a[58]),
.I1(b[58]),
.O(sig0000008a)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c3 (
.I0(a[59]),
.I1(b[59]),
.O(sig0000008b)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c4 (
.I0(a[60]),
.I1(b[60]),
.O(sig0000008c)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c5 (
.I0(a[61]),
.I1(b[61]),
.O(sig0000008d)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001c6 (
.I0(a[62]),
.I1(b[62]),
.O(sig0000008e)
);
LUT2 #(
.INIT ( 4'hE ))
blk000001c7 (
.I0(sig0000007b),
.I1(sig0000007e),
.O(sig0000007c)
);
LUT2 #(
.INIT ( 4'h2 ))
blk000001c8 (
.I0(sig0000007e),
.I1(sig0000007b),
.O(sig0000007d)
);
LUT2 #(
.INIT ( 4'h1 ))
blk000001c9 (
.I0(sig000000a9),
.I1(sig000000b4),
.O(sig00000093)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001ca (
.I0(a[42]),
.I1(a[43]),
.I2(a[44]),
.I3(a[45]),
.I4(a[46]),
.I5(a[47]),
.O(sig000000cc)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001cb (
.I0(a[36]),
.I1(a[37]),
.I2(a[38]),
.I3(a[39]),
.I4(a[40]),
.I5(a[41]),
.O(sig000000cd)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001cc (
.I0(a[30]),
.I1(a[31]),
.I2(a[32]),
.I3(a[33]),
.I4(a[34]),
.I5(a[35]),
.O(sig000000ce)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001cd (
.I0(a[24]),
.I1(a[25]),
.I2(a[26]),
.I3(a[27]),
.I4(a[28]),
.I5(a[29]),
.O(sig000000cf)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001ce (
.I0(a[18]),
.I1(a[19]),
.I2(a[20]),
.I3(a[21]),
.I4(a[22]),
.I5(a[23]),
.O(sig000000d0)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001cf (
.I0(a[12]),
.I1(a[13]),
.I2(a[14]),
.I3(a[15]),
.I4(a[16]),
.I5(a[17]),
.O(sig000000d1)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d0 (
.I0(a[6]),
.I1(a[7]),
.I2(a[8]),
.I3(a[9]),
.I4(a[10]),
.I5(a[11]),
.O(sig000000d2)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d1 (
.I0(a[0]),
.I1(a[1]),
.I2(a[2]),
.I3(a[3]),
.I4(a[4]),
.I5(a[5]),
.O(sig000000d3)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000001d2 (
.I0(a[48]),
.I1(a[49]),
.I2(a[50]),
.I3(a[51]),
.O(sig000000d4)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d3 (
.I0(b[42]),
.I1(b[43]),
.I2(b[44]),
.I3(b[45]),
.I4(b[46]),
.I5(b[47]),
.O(sig000000d5)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d4 (
.I0(b[36]),
.I1(b[37]),
.I2(b[38]),
.I3(b[39]),
.I4(b[40]),
.I5(b[41]),
.O(sig000000d6)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d5 (
.I0(b[30]),
.I1(b[31]),
.I2(b[32]),
.I3(b[33]),
.I4(b[34]),
.I5(b[35]),
.O(sig000000d7)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d6 (
.I0(b[24]),
.I1(b[25]),
.I2(b[26]),
.I3(b[27]),
.I4(b[28]),
.I5(b[29]),
.O(sig000000d8)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d7 (
.I0(b[18]),
.I1(b[19]),
.I2(b[20]),
.I3(b[21]),
.I4(b[22]),
.I5(b[23]),
.O(sig000000d9)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d8 (
.I0(b[12]),
.I1(b[13]),
.I2(b[14]),
.I3(b[15]),
.I4(b[16]),
.I5(b[17]),
.O(sig000000da)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001d9 (
.I0(b[6]),
.I1(b[7]),
.I2(b[8]),
.I3(b[9]),
.I4(b[10]),
.I5(b[11]),
.O(sig000000db)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk000001da (
.I0(b[0]),
.I1(b[1]),
.I2(b[2]),
.I3(b[3]),
.I4(b[4]),
.I5(b[5]),
.O(sig000000dc)
);
LUT4 #(
.INIT ( 16'h0001 ))
blk000001db (
.I0(b[48]),
.I1(b[49]),
.I2(b[50]),
.I3(b[51]),
.O(sig000000dd)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000001dc (
.I0(sig00000364),
.I1(sig000002b5),
.O(sig000001c5)
);
LUT2 #(
.INIT ( 4'h8 ))
blk000001dd (
.I0(sig00000365),
.I1(sig000003d8),
.O(sig000001c6)
);
LUT3 #(
.INIT ( 8'hAC ))
blk000001de (
.I0(sig00000462),
.I1(sig00000463),
.I2(sig00000460),
.O(sig0000041d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001df (
.I0(sig0000046d),
.I1(sig0000046c),
.I2(sig00000460),
.O(sig00000427)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e0 (
.I0(sig0000046e),
.I1(sig0000046d),
.I2(sig00000460),
.O(sig00000428)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e1 (
.I0(sig0000046f),
.I1(sig0000046e),
.I2(sig00000460),
.O(sig00000429)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e2 (
.I0(sig00000470),
.I1(sig0000046f),
.I2(sig00000460),
.O(sig0000042a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e3 (
.I0(sig00000471),
.I1(sig00000470),
.I2(sig00000460),
.O(sig0000042b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e4 (
.I0(sig00000472),
.I1(sig00000471),
.I2(sig00000460),
.O(sig0000042c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e5 (
.I0(sig00000473),
.I1(sig00000472),
.I2(sig00000460),
.O(sig0000042d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e6 (
.I0(sig00000474),
.I1(sig00000473),
.I2(sig00000460),
.O(sig0000042e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e7 (
.I0(sig00000475),
.I1(sig00000474),
.I2(sig00000460),
.O(sig0000042f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e8 (
.I0(sig00000476),
.I1(sig00000475),
.I2(sig00000460),
.O(sig00000430)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001e9 (
.I0(sig00000464),
.I1(sig00000463),
.I2(sig00000460),
.O(sig0000041e)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ea (
.I0(sig00000460),
.I1(sig00000476),
.I2(sig00000477),
.O(sig00000431)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001eb (
.I0(sig00000460),
.I1(sig00000477),
.I2(sig00000478),
.O(sig00000432)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ec (
.I0(sig00000460),
.I1(sig00000478),
.I2(sig00000479),
.O(sig00000433)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ed (
.I0(sig00000460),
.I1(sig00000479),
.I2(sig0000047a),
.O(sig00000434)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ee (
.I0(sig00000460),
.I1(sig0000047a),
.I2(sig0000047b),
.O(sig00000435)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk000001ef (
.I0(sig00000460),
.I1(sig0000047b),
.I2(sig0000047c),
.O(sig00000436)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f0 (
.I0(sig00000465),
.I1(sig00000464),
.I2(sig00000460),
.O(sig0000041f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f1 (
.I0(sig00000466),
.I1(sig00000465),
.I2(sig00000460),
.O(sig00000420)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f2 (
.I0(sig00000467),
.I1(sig00000466),
.I2(sig00000460),
.O(sig00000421)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f3 (
.I0(sig00000468),
.I1(sig00000467),
.I2(sig00000460),
.O(sig00000422)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f4 (
.I0(sig00000469),
.I1(sig00000468),
.I2(sig00000460),
.O(sig00000423)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f5 (
.I0(sig0000046a),
.I1(sig00000469),
.I2(sig00000460),
.O(sig00000424)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f6 (
.I0(sig0000046b),
.I1(sig0000046a),
.I2(sig00000460),
.O(sig00000425)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f7 (
.I0(sig0000046c),
.I1(sig0000046b),
.I2(sig00000460),
.O(sig00000426)
);
LUT2 #(
.INIT ( 4'h6 ))
blk000001f8 (
.I0(sig00000550),
.I1(sig0000047d),
.O(sig0000045c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001f9 (
.I0(sig00000037),
.I1(sig00000036),
.I2(sig00000008),
.O(sig00000438)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001fa (
.I0(sig0000002d),
.I1(sig0000002c),
.I2(sig00000008),
.O(sig00000442)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001fb (
.I0(sig0000002c),
.I1(sig0000002b),
.I2(sig00000008),
.O(sig00000443)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001fc (
.I0(sig0000002b),
.I1(sig0000002a),
.I2(sig00000008),
.O(sig00000444)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001fd (
.I0(sig0000002a),
.I1(sig00000029),
.I2(sig00000008),
.O(sig00000445)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001fe (
.I0(sig00000029),
.I1(sig00000028),
.I2(sig00000008),
.O(sig00000446)
);
LUT3 #(
.INIT ( 8'hCA ))
blk000001ff (
.I0(sig00000028),
.I1(sig00000027),
.I2(sig00000008),
.O(sig00000447)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000200 (
.I0(sig00000027),
.I1(sig00000026),
.I2(sig00000008),
.O(sig00000448)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000201 (
.I0(sig00000026),
.I1(sig00000025),
.I2(sig00000008),
.O(sig00000449)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000202 (
.I0(sig00000025),
.I1(sig00000024),
.I2(sig00000008),
.O(sig0000044a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000203 (
.I0(sig00000024),
.I1(sig00000023),
.I2(sig00000008),
.O(sig0000044b)
);
LUT3 #(
.INIT ( 8'hAC ))
blk00000204 (
.I0(sig00000035),
.I1(sig00000036),
.I2(sig00000008),
.O(sig00000439)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000205 (
.I0(sig00000023),
.I1(sig00000022),
.I2(sig00000008),
.O(sig0000044c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000206 (
.I0(sig00000022),
.I1(sig00000021),
.I2(sig00000008),
.O(sig0000044d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000207 (
.I0(sig00000021),
.I1(sig00000020),
.I2(sig00000008),
.O(sig0000044e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000208 (
.I0(sig00000020),
.I1(sig0000001f),
.I2(sig00000008),
.O(sig0000044f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000209 (
.I0(sig0000001f),
.I1(sig0000001e),
.I2(sig00000008),
.O(sig00000450)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000020a (
.I0(sig00000008),
.I1(sig0000001d),
.I2(sig0000001e),
.O(sig00000451)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000020b (
.I0(sig00000035),
.I1(sig00000034),
.I2(sig00000008),
.O(sig0000043a)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000020c (
.I0(sig00000034),
.I1(sig00000033),
.I2(sig00000008),
.O(sig0000043b)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000020d (
.I0(sig00000033),
.I1(sig00000032),
.I2(sig00000008),
.O(sig0000043c)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000020e (
.I0(sig00000032),
.I1(sig00000031),
.I2(sig00000008),
.O(sig0000043d)
);
LUT3 #(
.INIT ( 8'hCA ))
blk0000020f (
.I0(sig00000031),
.I1(sig00000030),
.I2(sig00000008),
.O(sig0000043e)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000210 (
.I0(sig00000030),
.I1(sig0000002f),
.I2(sig00000008),
.O(sig0000043f)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000211 (
.I0(sig0000002f),
.I1(sig0000002e),
.I2(sig00000008),
.O(sig00000440)
);
LUT3 #(
.INIT ( 8'hCA ))
blk00000212 (
.I0(sig0000002e),
.I1(sig0000002d),
.I2(sig00000008),
.O(sig00000441)
);
LUT5 #(
.INIT ( 32'h0455FFDD ))
blk00000213 (
.I0(sig00000038),
.I1(sig00000039),
.I2(sig00000036),
.I3(sig00000008),
.I4(sig00000037),
.O(sig00000480)
);
LUT3 #(
.INIT ( 8'hEF ))
blk00000214 (
.I0(sig00000037),
.I1(sig00000038),
.I2(sig00000039),
.O(sig00000481)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk00000215 (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [1]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000077),
.O(sig00000546)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk00000216 (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [3]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000075),
.O(sig00000548)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk00000217 (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [4]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000074),
.O(sig00000549)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk00000218 (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [2]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000076),
.O(sig00000547)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk00000219 (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [6]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000072),
.O(sig0000054b)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk0000021a (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [7]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000071),
.O(sig0000054c)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk0000021b (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [9]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig0000006f),
.O(sig0000054e)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk0000021c (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [10]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig0000006e),
.O(sig0000054f)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk0000021d (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [5]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000073),
.O(sig0000054a)
);
LUT5 #(
.INIT ( 32'h44EE44E4 ))
blk0000021e (
.I0(ce),
.I1(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [8]),
.I2(sig00000007),
.I3(sig00000003),
.I4(sig00000070),
.O(sig0000054d)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000021f (
.I0(ce),
.I1(sig00000004),
.I2(sig0000006c),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [1]),
.O(sig00000512)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000220 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000006b),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [2]),
.O(sig00000513)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000221 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000006d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [0]),
.O(sig00000511)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000222 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000069),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [4]),
.O(sig00000515)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000223 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000068),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [5]),
.O(sig00000516)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000224 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000006a),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [3]),
.O(sig00000514)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000225 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000066),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [7]),
.O(sig00000518)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000226 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000065),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [8]),
.O(sig00000519)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000227 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000067),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [6]),
.O(sig00000517)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000228 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000063),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [10]),
.O(sig0000051b)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000229 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000062),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [11]),
.O(sig0000051c)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000022a (
.I0(ce),
.I1(sig00000004),
.I2(sig00000064),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [9]),
.O(sig0000051a)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000022b (
.I0(ce),
.I1(sig00000004),
.I2(sig0000005f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [14]),
.O(sig0000051f)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000022c (
.I0(ce),
.I1(sig00000004),
.I2(sig00000061),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [12]),
.O(sig0000051d)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000022d (
.I0(ce),
.I1(sig00000004),
.I2(sig00000060),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [13]),
.O(sig0000051e)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000022e (
.I0(ce),
.I1(sig00000004),
.I2(sig0000005d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [16]),
.O(sig00000521)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000022f (
.I0(ce),
.I1(sig00000004),
.I2(sig0000005c),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [17]),
.O(sig00000522)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000230 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000005e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [15]),
.O(sig00000520)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000231 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000005a),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [19]),
.O(sig00000524)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000232 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000059),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [20]),
.O(sig00000525)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000233 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000005b),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [18]),
.O(sig00000523)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000234 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000056),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [23]),
.O(sig00000528)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000235 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000058),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [21]),
.O(sig00000526)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000236 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000057),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [22]),
.O(sig00000527)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000237 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000054),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [25]),
.O(sig0000052a)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000238 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000053),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [26]),
.O(sig0000052b)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000239 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000055),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [24]),
.O(sig00000529)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023a (
.I0(ce),
.I1(sig00000004),
.I2(sig00000051),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [28]),
.O(sig0000052d)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023b (
.I0(ce),
.I1(sig00000004),
.I2(sig00000050),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [29]),
.O(sig0000052e)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023c (
.I0(ce),
.I1(sig00000004),
.I2(sig00000052),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [27]),
.O(sig0000052c)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023d (
.I0(ce),
.I1(sig00000004),
.I2(sig0000004d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [32]),
.O(sig00000531)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023e (
.I0(ce),
.I1(sig00000004),
.I2(sig0000004f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [30]),
.O(sig0000052f)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000023f (
.I0(ce),
.I1(sig00000004),
.I2(sig0000004e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [31]),
.O(sig00000530)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000240 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000004b),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [34]),
.O(sig00000533)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000241 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000004a),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [35]),
.O(sig00000534)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000242 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000004c),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [33]),
.O(sig00000532)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000243 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000048),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [37]),
.O(sig00000536)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000244 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000047),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [38]),
.O(sig00000537)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000245 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000049),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [36]),
.O(sig00000535)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000246 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000044),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [41]),
.O(sig0000053a)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000247 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000046),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [39]),
.O(sig00000538)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000248 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000045),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [40]),
.O(sig00000539)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000249 (
.I0(ce),
.I1(sig00000004),
.I2(sig00000042),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [43]),
.O(sig0000053c)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024a (
.I0(ce),
.I1(sig00000004),
.I2(sig00000041),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [44]),
.O(sig0000053d)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024b (
.I0(ce),
.I1(sig00000004),
.I2(sig00000043),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [42]),
.O(sig0000053b)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024c (
.I0(ce),
.I1(sig00000004),
.I2(sig0000003f),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [46]),
.O(sig0000053f)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024d (
.I0(ce),
.I1(sig00000004),
.I2(sig0000003e),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [47]),
.O(sig00000540)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024e (
.I0(ce),
.I1(sig00000004),
.I2(sig00000040),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [45]),
.O(sig0000053e)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk0000024f (
.I0(ce),
.I1(sig00000004),
.I2(sig0000003b),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [50]),
.O(sig00000543)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000250 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000003d),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [48]),
.O(sig00000541)
);
LUT4 #(
.INIT ( 16'h7520 ))
blk00000251 (
.I0(ce),
.I1(sig00000004),
.I2(sig0000003c),
.I3(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [49]),
.O(sig00000542)
);
LUT5 #(
.INIT ( 32'h77752220 ))
blk00000252 (
.I0(ce),
.I1(sig00000003),
.I2(sig00000007),
.I3(sig00000078),
.I4(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/exp_op [0]),
.O(sig00000545)
);
LUT5 #(
.INIT ( 32'h77752220 ))
blk00000253 (
.I0(ce),
.I1(sig00000005),
.I2(sig00000006),
.I3(sig0000003a),
.I4(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/MULT.OP/OP/mant_op [51]),
.O(sig00000544)
);
LUT2 #(
.INIT ( 4'h1 ))
blk00000254 (
.I0(sig0000009b),
.I1(sig0000009c),
.O(sig00000552)
);
LUT6 #(
.INIT ( 64'hFFFFFFFF51554055 ))
blk00000255 (
.I0(sig000000a0),
.I1(sig00000008),
.I2(sig0000009e),
.I3(sig00000552),
.I4(sig0000009d),
.I5(sig000000a1),
.O(sig00000092)
);
LUT2 #(
.INIT ( 4'hB ))
blk00000256 (
.I0(sig000000a6),
.I1(sig000000a5),
.O(sig00000553)
);
LUT6 #(
.INIT ( 64'h0020202000AAAAAA ))
blk00000257 (
.I0(sig000000a2),
.I1(sig000000a3),
.I2(sig000000a8),
.I3(sig00000553),
.I4(sig000000a4),
.I5(sig000000a7),
.O(sig00000098)
);
LUT5 #(
.INIT ( 32'h80000000 ))
blk00000258 (
.I0(sig000000ab),
.I1(sig000000ae),
.I2(sig000000ad),
.I3(sig000000ac),
.I4(sig000000a9),
.O(sig00000554)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk00000259 (
.I0(sig000000b0),
.I1(sig000000af),
.I2(sig000000b3),
.I3(sig000000b2),
.I4(sig000000b1),
.I5(sig00000554),
.O(sig0000007a)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000025a (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig00000555)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000025b (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig00000555),
.O(sig00000080)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk0000025c (
.I0(a[57]),
.I1(a[56]),
.I2(a[55]),
.I3(a[54]),
.I4(a[53]),
.I5(a[52]),
.O(sig00000556)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk0000025d (
.I0(a[62]),
.I1(a[61]),
.I2(a[60]),
.I3(a[59]),
.I4(a[58]),
.I5(sig00000556),
.O(sig00000081)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000025e (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig00000557)
);
LUT6 #(
.INIT ( 64'h8000000000000000 ))
blk0000025f (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig00000557),
.O(sig00000082)
);
LUT6 #(
.INIT ( 64'hFFFFFFFFFFFFFFFE ))
blk00000260 (
.I0(b[57]),
.I1(b[56]),
.I2(b[55]),
.I3(b[54]),
.I4(b[53]),
.I5(b[52]),
.O(sig00000558)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000261 (
.I0(b[62]),
.I1(b[61]),
.I2(b[60]),
.I3(b[59]),
.I4(b[58]),
.I5(sig00000558),
.O(sig00000083)
);
LUT6 #(
.INIT ( 64'h0000000000010000 ))
blk00000262 (
.I0(sig000000aa),
.I1(sig000000ab),
.I2(sig000000ac),
.I3(sig000000ad),
.I4(sig000000b4),
.I5(sig000000ae),
.O(sig00000559)
);
LUT6 #(
.INIT ( 64'h0000000000000001 ))
blk00000263 (
.I0(sig000000b0),
.I1(sig000000af),
.I2(sig000000b1),
.I3(sig000000b2),
.I4(sig000000b3),
.I5(sig000000a9),
.O(sig0000055a)
);
LUT2 #(
.INIT ( 4'h8 ))
blk00000264 (
.I0(sig00000559),
.I1(sig0000055a),
.O(sig00000095)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000265 (
.I0(sig0000045b),
.O(sig0000055b)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000266 (
.I0(sig0000045a),
.O(sig0000055c)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000267 (
.I0(sig00000459),
.O(sig0000055d)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000268 (
.I0(sig00000458),
.O(sig0000055e)
);
LUT1 #(
.INIT ( 2'h2 ))
blk00000269 (
.I0(sig00000457),
.O(sig0000055f)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000026a (
.I0(sig00000456),
.O(sig00000560)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000026b (
.I0(sig00000455),
.O(sig00000561)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000026c (
.I0(sig00000454),
.O(sig00000562)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000026d (
.I0(sig00000453),
.O(sig00000563)
);
LUT1 #(
.INIT ( 2'h2 ))
blk0000026e (
.I0(sig00000452),
.O(sig00000564)
);
LUT3 #(
.INIT ( 8'hD8 ))
blk0000026f (
.I0(ce),
.I1(sig00000551),
.I2(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/HND_SHK/RDY ),
.O(sig00000565)
);
FD #(
.INIT ( 1'b0 ))
blk00000270 (
.C(clk),
.D(sig00000565),
.Q(\NlwRenamedSig_OI_U0/op_inst/FLT_PT_OP/HND_SHK/RDY )
);
INV blk00000271 (
.I(sig00000008),
.O(sig00000002)
);
INV blk00000272 (
.I(sig00000437),
.O(sig0000041c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000273 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000f1),
.Q(sig00000566),
.Q15(NLW_blk00000273_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000274 (
.C(clk),
.CE(ce),
.D(sig00000566),
.Q(sig000000a1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000275 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000f0),
.Q(sig00000567),
.Q15(NLW_blk00000275_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000276 (
.C(clk),
.CE(ce),
.D(sig00000567),
.Q(sig000000a0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000277 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000ff),
.Q(sig00000568),
.Q15(NLW_blk00000277_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000278 (
.C(clk),
.CE(ce),
.D(sig00000568),
.Q(sig0000009d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000279 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000fe),
.Q(sig00000569),
.Q15(NLW_blk00000279_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000027a (
.C(clk),
.CE(ce),
.D(sig00000569),
.Q(sig0000009e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000027b (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000148),
.Q(sig0000056a),
.Q15(NLW_blk0000027b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000027c (
.C(clk),
.CE(ce),
.D(sig0000056a),
.Q(sig00000039)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000027d (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000fd),
.Q(sig0000056b),
.Q15(NLW_blk0000027d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000027e (
.C(clk),
.CE(ce),
.D(sig0000056b),
.Q(sig0000009b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000027f (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000fc),
.Q(sig0000056c),
.Q15(NLW_blk0000027f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000280 (
.C(clk),
.CE(ce),
.D(sig0000056c),
.Q(sig0000009c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000281 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[33]),
.Q(sig0000056d),
.Q15(NLW_blk00000281_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000282 (
.C(clk),
.CE(ce),
.D(sig0000056d),
.Q(sig00000191)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000283 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a2),
.Q(sig0000056e),
.Q15(NLW_blk00000283_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000284 (
.C(clk),
.CE(ce),
.D(sig0000056e),
.Q(sig00000364)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000285 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000003d9),
.Q(sig0000056f),
.Q15(NLW_blk00000285_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000286 (
.C(clk),
.CE(ce),
.D(sig0000056f),
.Q(sig000003d8)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000287 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[30]),
.Q(sig00000570),
.Q15(NLW_blk00000287_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000288 (
.C(clk),
.CE(ce),
.D(sig00000570),
.Q(sig00000194)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000289 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[32]),
.Q(sig00000571),
.Q15(NLW_blk00000289_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000028a (
.C(clk),
.CE(ce),
.D(sig00000571),
.Q(sig00000192)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000028b (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[31]),
.Q(sig00000572),
.Q15(NLW_blk0000028b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000028c (
.C(clk),
.CE(ce),
.D(sig00000572),
.Q(sig00000193)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000028d (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[29]),
.Q(sig00000573),
.Q15(NLW_blk0000028d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000028e (
.C(clk),
.CE(ce),
.D(sig00000573),
.Q(sig00000195)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000028f (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[28]),
.Q(sig00000574),
.Q15(NLW_blk0000028f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000290 (
.C(clk),
.CE(ce),
.D(sig00000574),
.Q(sig00000196)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000291 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[27]),
.Q(sig00000575),
.Q15(NLW_blk00000291_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000292 (
.C(clk),
.CE(ce),
.D(sig00000575),
.Q(sig00000197)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000293 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[26]),
.Q(sig00000576),
.Q15(NLW_blk00000293_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000294 (
.C(clk),
.CE(ce),
.D(sig00000576),
.Q(sig00000198)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000295 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[23]),
.Q(sig00000577),
.Q15(NLW_blk00000295_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000296 (
.C(clk),
.CE(ce),
.D(sig00000577),
.Q(sig0000019b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000297 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[25]),
.Q(sig00000578),
.Q15(NLW_blk00000297_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000298 (
.C(clk),
.CE(ce),
.D(sig00000578),
.Q(sig00000199)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000299 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[24]),
.Q(sig00000579),
.Q15(NLW_blk00000299_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000029a (
.C(clk),
.CE(ce),
.D(sig00000579),
.Q(sig0000019a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000029b (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[20]),
.Q(sig0000057a),
.Q15(NLW_blk0000029b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000029c (
.C(clk),
.CE(ce),
.D(sig0000057a),
.Q(sig0000019e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000029d (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[22]),
.Q(sig0000057b),
.Q15(NLW_blk0000029d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000029e (
.C(clk),
.CE(ce),
.D(sig0000057b),
.Q(sig0000019c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000029f (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[21]),
.Q(sig0000057c),
.Q15(NLW_blk0000029f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a0 (
.C(clk),
.CE(ce),
.D(sig0000057c),
.Q(sig0000019d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a1 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[17]),
.Q(sig0000057d),
.Q15(NLW_blk000002a1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a2 (
.C(clk),
.CE(ce),
.D(sig0000057d),
.Q(sig000001a1)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a3 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[19]),
.Q(sig0000057e),
.Q15(NLW_blk000002a3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a4 (
.C(clk),
.CE(ce),
.D(sig0000057e),
.Q(sig0000019f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a5 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[18]),
.Q(sig0000057f),
.Q15(NLW_blk000002a5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a6 (
.C(clk),
.CE(ce),
.D(sig0000057f),
.Q(sig000001a0)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a7 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000236),
.Q(sig00000580),
.Q15(NLW_blk000002a7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002a8 (
.C(clk),
.CE(ce),
.D(sig00000580),
.Q(sig00000028)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002a9 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000235),
.Q(sig00000581),
.Q15(NLW_blk000002a9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002aa (
.C(clk),
.CE(ce),
.D(sig00000581),
.Q(sig00000029)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ab (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000234),
.Q(sig00000582),
.Q15(NLW_blk000002ab_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ac (
.C(clk),
.CE(ce),
.D(sig00000582),
.Q(sig0000002a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ad (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000233),
.Q(sig00000583),
.Q15(NLW_blk000002ad_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ae (
.C(clk),
.CE(ce),
.D(sig00000583),
.Q(sig0000002b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002af (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000230),
.Q(sig00000584),
.Q15(NLW_blk000002af_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b0 (
.C(clk),
.CE(ce),
.D(sig00000584),
.Q(sig0000002e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b1 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000232),
.Q(sig00000585),
.Q15(NLW_blk000002b1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b2 (
.C(clk),
.CE(ce),
.D(sig00000585),
.Q(sig0000002c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b3 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000231),
.Q(sig00000586),
.Q15(NLW_blk000002b3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b4 (
.C(clk),
.CE(ce),
.D(sig00000586),
.Q(sig0000002d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b5 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000022d),
.Q(sig00000587),
.Q15(NLW_blk000002b5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b6 (
.C(clk),
.CE(ce),
.D(sig00000587),
.Q(sig00000031)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b7 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000022f),
.Q(sig00000588),
.Q15(NLW_blk000002b7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002b8 (
.C(clk),
.CE(ce),
.D(sig00000588),
.Q(sig0000002f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002b9 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000022e),
.Q(sig00000589),
.Q15(NLW_blk000002b9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ba (
.C(clk),
.CE(ce),
.D(sig00000589),
.Q(sig00000030)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002bb (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000022a),
.Q(sig0000058a),
.Q15(NLW_blk000002bb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002bc (
.C(clk),
.CE(ce),
.D(sig0000058a),
.Q(sig00000034)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002bd (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000022c),
.Q(sig0000058b),
.Q15(NLW_blk000002bd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002be (
.C(clk),
.CE(ce),
.D(sig0000058b),
.Q(sig00000032)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002bf (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000022b),
.Q(sig0000058c),
.Q15(NLW_blk000002bf_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002c0 (
.C(clk),
.CE(ce),
.D(sig0000058c),
.Q(sig00000033)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002c1 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000229),
.Q(sig0000058d),
.Q15(NLW_blk000002c1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002c2 (
.C(clk),
.CE(ce),
.D(sig0000058d),
.Q(sig00000035)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002c3 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000228),
.Q(sig0000058e),
.Q15(NLW_blk000002c3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002c4 (
.C(clk),
.CE(ce),
.D(sig0000058e),
.Q(sig00000036)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002c5 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000227),
.Q(sig0000058f),
.Q15(NLW_blk000002c5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002c6 (
.C(clk),
.CE(ce),
.D(sig0000058f),
.Q(sig00000037)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002c7 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000226),
.Q(sig00000590),
.Q15(NLW_blk000002c7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002c8 (
.C(clk),
.CE(ce),
.D(sig00000590),
.Q(sig00000038)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002c9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[49]),
.Q(sig00000591),
.Q15(NLW_blk000002c9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ca (
.C(clk),
.CE(ce),
.D(sig00000591),
.Q(sig00000170)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002cb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[51]),
.Q(sig00000592),
.Q15(NLW_blk000002cb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002cc (
.C(clk),
.CE(ce),
.D(sig00000592),
.Q(sig0000016e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002cd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[50]),
.Q(sig00000593),
.Q15(NLW_blk000002cd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ce (
.C(clk),
.CE(ce),
.D(sig00000593),
.Q(sig0000016f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002cf (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[46]),
.Q(sig00000594),
.Q15(NLW_blk000002cf_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d0 (
.C(clk),
.CE(ce),
.D(sig00000594),
.Q(sig00000173)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002d1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[48]),
.Q(sig00000595),
.Q15(NLW_blk000002d1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d2 (
.C(clk),
.CE(ce),
.D(sig00000595),
.Q(sig00000171)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002d3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[47]),
.Q(sig00000596),
.Q15(NLW_blk000002d3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d4 (
.C(clk),
.CE(ce),
.D(sig00000596),
.Q(sig00000172)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002d5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[43]),
.Q(sig00000597),
.Q15(NLW_blk000002d5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d6 (
.C(clk),
.CE(ce),
.D(sig00000597),
.Q(sig00000176)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002d7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[45]),
.Q(sig00000598),
.Q15(NLW_blk000002d7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002d8 (
.C(clk),
.CE(ce),
.D(sig00000598),
.Q(sig00000174)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002d9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[44]),
.Q(sig00000599),
.Q15(NLW_blk000002d9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002da (
.C(clk),
.CE(ce),
.D(sig00000599),
.Q(sig00000175)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002db (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[42]),
.Q(sig0000059a),
.Q15(NLW_blk000002db_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002dc (
.C(clk),
.CE(ce),
.D(sig0000059a),
.Q(sig00000177)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002dd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[41]),
.Q(sig0000059b),
.Q15(NLW_blk000002dd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002de (
.C(clk),
.CE(ce),
.D(sig0000059b),
.Q(sig00000178)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002df (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[40]),
.Q(sig0000059c),
.Q15(NLW_blk000002df_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e0 (
.C(clk),
.CE(ce),
.D(sig0000059c),
.Q(sig00000179)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002e1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[39]),
.Q(sig0000059d),
.Q15(NLW_blk000002e1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e2 (
.C(clk),
.CE(ce),
.D(sig0000059d),
.Q(sig0000017a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002e3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[36]),
.Q(sig0000059e),
.Q15(NLW_blk000002e3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e4 (
.C(clk),
.CE(ce),
.D(sig0000059e),
.Q(sig0000017d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002e5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[38]),
.Q(sig0000059f),
.Q15(NLW_blk000002e5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e6 (
.C(clk),
.CE(ce),
.D(sig0000059f),
.Q(sig0000017b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002e7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[37]),
.Q(sig000005a0),
.Q15(NLW_blk000002e7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002e8 (
.C(clk),
.CE(ce),
.D(sig000005a0),
.Q(sig0000017c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002e9 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000001),
.Q(sig000005a1),
.Q15(NLW_blk000002e9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ea (
.C(clk),
.CE(ce),
.D(sig000005a1),
.Q(sig00000550)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002eb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[35]),
.Q(sig000005a2),
.Q15(NLW_blk000002eb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ec (
.C(clk),
.CE(ce),
.D(sig000005a2),
.Q(sig0000017e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ed (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(a[34]),
.Q(sig000005a3),
.Q15(NLW_blk000002ed_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002ee (
.C(clk),
.CE(ce),
.D(sig000005a3),
.Q(sig0000017f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ef (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[14]),
.Q(sig000005a4),
.Q15(NLW_blk000002ef_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f0 (
.C(clk),
.CE(ce),
.D(sig000005a4),
.Q(sig00000182)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002f1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[16]),
.Q(sig000005a5),
.Q15(NLW_blk000002f1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f2 (
.C(clk),
.CE(ce),
.D(sig000005a5),
.Q(sig00000180)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002f3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[15]),
.Q(sig000005a6),
.Q15(NLW_blk000002f3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f4 (
.C(clk),
.CE(ce),
.D(sig000005a6),
.Q(sig00000181)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002f5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[13]),
.Q(sig000005a7),
.Q15(NLW_blk000002f5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f6 (
.C(clk),
.CE(ce),
.D(sig000005a7),
.Q(sig00000183)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002f7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[12]),
.Q(sig000005a8),
.Q15(NLW_blk000002f7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002f8 (
.C(clk),
.CE(ce),
.D(sig000005a8),
.Q(sig00000184)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002f9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[11]),
.Q(sig000005a9),
.Q15(NLW_blk000002f9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fa (
.C(clk),
.CE(ce),
.D(sig000005a9),
.Q(sig00000185)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002fb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[10]),
.Q(sig000005aa),
.Q15(NLW_blk000002fb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fc (
.C(clk),
.CE(ce),
.D(sig000005aa),
.Q(sig00000186)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002fd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[7]),
.Q(sig000005ab),
.Q15(NLW_blk000002fd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000002fe (
.C(clk),
.CE(ce),
.D(sig000005ab),
.Q(sig00000189)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000002ff (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[9]),
.Q(sig000005ac),
.Q15(NLW_blk000002ff_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000300 (
.C(clk),
.CE(ce),
.D(sig000005ac),
.Q(sig00000187)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000301 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[8]),
.Q(sig000005ad),
.Q15(NLW_blk00000301_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000302 (
.C(clk),
.CE(ce),
.D(sig000005ad),
.Q(sig00000188)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000303 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[4]),
.Q(sig000005ae),
.Q15(NLW_blk00000303_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000304 (
.C(clk),
.CE(ce),
.D(sig000005ae),
.Q(sig0000018c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000305 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[6]),
.Q(sig000005af),
.Q15(NLW_blk00000305_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000306 (
.C(clk),
.CE(ce),
.D(sig000005af),
.Q(sig0000018a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000307 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[5]),
.Q(sig000005b0),
.Q15(NLW_blk00000307_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000308 (
.C(clk),
.CE(ce),
.D(sig000005b0),
.Q(sig0000018b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000309 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[1]),
.Q(sig000005b1),
.Q15(NLW_blk00000309_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030a (
.C(clk),
.CE(ce),
.D(sig000005b1),
.Q(sig0000018f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000030b (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[3]),
.Q(sig000005b2),
.Q15(NLW_blk0000030b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030c (
.C(clk),
.CE(ce),
.D(sig000005b2),
.Q(sig0000018d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000030d (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[2]),
.Q(sig000005b3),
.Q15(NLW_blk0000030d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000030e (
.C(clk),
.CE(ce),
.D(sig000005b3),
.Q(sig0000018e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000030f (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[0]),
.Q(sig000005b4),
.Q15(NLW_blk0000030f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000310 (
.C(clk),
.CE(ce),
.D(sig000005b4),
.Q(sig00000190)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000311 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[51]),
.Q(sig000005b5),
.Q15(NLW_blk00000311_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000312 (
.C(clk),
.CE(ce),
.D(sig000005b5),
.Q(sig0000014a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000313 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[50]),
.Q(sig000005b6),
.Q15(NLW_blk00000313_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000314 (
.C(clk),
.CE(ce),
.D(sig000005b6),
.Q(sig0000014b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000315 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[49]),
.Q(sig000005b7),
.Q15(NLW_blk00000315_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000316 (
.C(clk),
.CE(ce),
.D(sig000005b7),
.Q(sig0000014c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000317 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[46]),
.Q(sig000005b8),
.Q15(NLW_blk00000317_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000318 (
.C(clk),
.CE(ce),
.D(sig000005b8),
.Q(sig0000014f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000319 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[48]),
.Q(sig000005b9),
.Q15(NLW_blk00000319_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031a (
.C(clk),
.CE(ce),
.D(sig000005b9),
.Q(sig0000014d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000031b (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[47]),
.Q(sig000005ba),
.Q15(NLW_blk0000031b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031c (
.C(clk),
.CE(ce),
.D(sig000005ba),
.Q(sig0000014e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000031d (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[43]),
.Q(sig000005bb),
.Q15(NLW_blk0000031d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000031e (
.C(clk),
.CE(ce),
.D(sig000005bb),
.Q(sig00000152)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000031f (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[45]),
.Q(sig000005bc),
.Q15(NLW_blk0000031f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000320 (
.C(clk),
.CE(ce),
.D(sig000005bc),
.Q(sig00000150)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000321 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[44]),
.Q(sig000005bd),
.Q15(NLW_blk00000321_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000322 (
.C(clk),
.CE(ce),
.D(sig000005bd),
.Q(sig00000151)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000323 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[40]),
.Q(sig000005be),
.Q15(NLW_blk00000323_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000324 (
.C(clk),
.CE(ce),
.D(sig000005be),
.Q(sig00000155)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000325 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[42]),
.Q(sig000005bf),
.Q15(NLW_blk00000325_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000326 (
.C(clk),
.CE(ce),
.D(sig000005bf),
.Q(sig00000153)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000327 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[41]),
.Q(sig000005c0),
.Q15(NLW_blk00000327_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000328 (
.C(clk),
.CE(ce),
.D(sig000005c0),
.Q(sig00000154)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000329 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[37]),
.Q(sig000005c1),
.Q15(NLW_blk00000329_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032a (
.C(clk),
.CE(ce),
.D(sig000005c1),
.Q(sig00000158)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000032b (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[39]),
.Q(sig000005c2),
.Q15(NLW_blk0000032b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032c (
.C(clk),
.CE(ce),
.D(sig000005c2),
.Q(sig00000156)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000032d (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[38]),
.Q(sig000005c3),
.Q15(NLW_blk0000032d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000032e (
.C(clk),
.CE(ce),
.D(sig000005c3),
.Q(sig00000157)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000032f (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[34]),
.Q(sig000005c4),
.Q15(NLW_blk0000032f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000330 (
.C(clk),
.CE(ce),
.D(sig000005c4),
.Q(sig0000015b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000331 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[36]),
.Q(sig000005c5),
.Q15(NLW_blk00000331_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000332 (
.C(clk),
.CE(ce),
.D(sig000005c5),
.Q(sig00000159)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000333 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(b[35]),
.Q(sig000005c6),
.Q15(NLW_blk00000333_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000334 (
.C(clk),
.CE(ce),
.D(sig000005c6),
.Q(sig0000015a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000335 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a5),
.Q(sig000005c7),
.Q15(NLW_blk00000335_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000336 (
.C(clk),
.CE(ce),
.D(sig000005c7),
.Q(sig0000015e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000337 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a3),
.Q(sig000005c8),
.Q15(NLW_blk00000337_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000338 (
.C(clk),
.CE(ce),
.D(sig000005c8),
.Q(sig0000015c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000339 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a4),
.Q(sig000005c9),
.Q15(NLW_blk00000339_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033a (
.C(clk),
.CE(ce),
.D(sig000005c9),
.Q(sig0000015d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000033b (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a8),
.Q(sig000005ca),
.Q15(NLW_blk0000033b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033c (
.C(clk),
.CE(ce),
.D(sig000005ca),
.Q(sig00000161)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000033d (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a6),
.Q(sig000005cb),
.Q15(NLW_blk0000033d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000033e (
.C(clk),
.CE(ce),
.D(sig000005cb),
.Q(sig0000015f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000033f (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a7),
.Q(sig000005cc),
.Q15(NLW_blk0000033f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000340 (
.C(clk),
.CE(ce),
.D(sig000005cc),
.Q(sig00000160)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000341 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a9),
.Q(sig000005cd),
.Q15(NLW_blk00000341_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000342 (
.C(clk),
.CE(ce),
.D(sig000005cd),
.Q(sig00000162)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000343 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001aa),
.Q(sig000005ce),
.Q15(NLW_blk00000343_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000344 (
.C(clk),
.CE(ce),
.D(sig000005ce),
.Q(sig00000163)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000345 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001ab),
.Q(sig000005cf),
.Q15(NLW_blk00000345_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000346 (
.C(clk),
.CE(ce),
.D(sig000005cf),
.Q(sig00000164)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000347 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001ac),
.Q(sig000005d0),
.Q15(NLW_blk00000347_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000348 (
.C(clk),
.CE(ce),
.D(sig000005d0),
.Q(sig00000165)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000349 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001af),
.Q(sig000005d1),
.Q15(NLW_blk00000349_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034a (
.C(clk),
.CE(ce),
.D(sig000005d1),
.Q(sig00000168)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000034b (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001ad),
.Q(sig000005d2),
.Q15(NLW_blk0000034b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034c (
.C(clk),
.CE(ce),
.D(sig000005d2),
.Q(sig00000166)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000034d (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001ae),
.Q(sig000005d3),
.Q15(NLW_blk0000034d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000034e (
.C(clk),
.CE(ce),
.D(sig000005d3),
.Q(sig00000167)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000034f (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b2),
.Q(sig000005d4),
.Q15(NLW_blk0000034f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000350 (
.C(clk),
.CE(ce),
.D(sig000005d4),
.Q(sig0000016b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000351 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b0),
.Q(sig000005d5),
.Q15(NLW_blk00000351_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000352 (
.C(clk),
.CE(ce),
.D(sig000005d5),
.Q(sig00000169)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000353 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b1),
.Q(sig000005d6),
.Q15(NLW_blk00000353_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000354 (
.C(clk),
.CE(ce),
.D(sig000005d6),
.Q(sig0000016a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000355 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b3),
.Q(sig000005d7),
.Q15(NLW_blk00000355_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000356 (
.C(clk),
.CE(ce),
.D(sig000005d7),
.Q(sig0000016c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000357 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000149),
.Q(sig000005d8),
.Q15(NLW_blk00000357_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000358 (
.C(clk),
.CE(ce),
.D(sig000005d8),
.Q(sig00000113)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000359 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b4),
.Q(sig000005d9),
.Q15(NLW_blk00000359_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035a (
.C(clk),
.CE(ce),
.D(sig000005d9),
.Q(sig00000126)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000035b (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b7),
.Q(sig000005da),
.Q15(NLW_blk0000035b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035c (
.C(clk),
.CE(ce),
.D(sig000005da),
.Q(sig00000129)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000035d (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b5),
.Q(sig000005db),
.Q15(NLW_blk0000035d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000035e (
.C(clk),
.CE(ce),
.D(sig000005db),
.Q(sig00000127)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000035f (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b6),
.Q(sig000005dc),
.Q15(NLW_blk0000035f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000360 (
.C(clk),
.CE(ce),
.D(sig000005dc),
.Q(sig00000128)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000361 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b8),
.Q(sig000005dd),
.Q15(NLW_blk00000361_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000362 (
.C(clk),
.CE(ce),
.D(sig000005dd),
.Q(sig0000012a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000363 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001b9),
.Q(sig000005de),
.Q15(NLW_blk00000363_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000364 (
.C(clk),
.CE(ce),
.D(sig000005de),
.Q(sig0000012b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000365 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001ba),
.Q(sig000005df),
.Q15(NLW_blk00000365_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000366 (
.C(clk),
.CE(ce),
.D(sig000005df),
.Q(sig0000012c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000367 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001bb),
.Q(sig000005e0),
.Q15(NLW_blk00000367_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000368 (
.C(clk),
.CE(ce),
.D(sig000005e0),
.Q(sig0000012d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000369 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001be),
.Q(sig000005e1),
.Q15(NLW_blk00000369_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036a (
.C(clk),
.CE(ce),
.D(sig000005e1),
.Q(sig00000130)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000036b (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001bc),
.Q(sig000005e2),
.Q15(NLW_blk0000036b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036c (
.C(clk),
.CE(ce),
.D(sig000005e2),
.Q(sig0000012e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000036d (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001bd),
.Q(sig000005e3),
.Q15(NLW_blk0000036d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000036e (
.C(clk),
.CE(ce),
.D(sig000005e3),
.Q(sig0000012f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000036f (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001c1),
.Q(sig000005e4),
.Q15(NLW_blk0000036f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000370 (
.C(clk),
.CE(ce),
.D(sig000005e4),
.Q(sig00000133)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000371 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001bf),
.Q(sig000005e5),
.Q15(NLW_blk00000371_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000372 (
.C(clk),
.CE(ce),
.D(sig000005e5),
.Q(sig00000131)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000373 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001c0),
.Q(sig000005e6),
.Q15(NLW_blk00000373_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000374 (
.C(clk),
.CE(ce),
.D(sig000005e6),
.Q(sig00000132)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000375 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001c4),
.Q(sig000005e7),
.Q15(NLW_blk00000375_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000376 (
.C(clk),
.CE(ce),
.D(sig000005e7),
.Q(sig00000136)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000377 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001c2),
.Q(sig000005e8),
.Q15(NLW_blk00000377_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000378 (
.C(clk),
.CE(ce),
.D(sig000005e8),
.Q(sig00000134)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000379 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001c3),
.Q(sig000005e9),
.Q15(NLW_blk00000379_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037a (
.C(clk),
.CE(ce),
.D(sig000005e9),
.Q(sig00000135)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000037b (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000b4),
.Q(sig000005ea),
.Q15(NLW_blk0000037b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037c (
.C(clk),
.CE(ce),
.D(sig000005ea),
.Q(sig0000047d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000037d (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000b1),
.Q(sig000005eb),
.Q15(NLW_blk0000037d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000037e (
.C(clk),
.CE(ce),
.D(sig000005eb),
.Q(sig00000459)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000037f (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000b3),
.Q(sig000005ec),
.Q15(NLW_blk0000037f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000380 (
.C(clk),
.CE(ce),
.D(sig000005ec),
.Q(sig0000045b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000381 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000b2),
.Q(sig000005ed),
.Q15(NLW_blk00000381_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000382 (
.C(clk),
.CE(ce),
.D(sig000005ed),
.Q(sig0000045a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000383 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000ae),
.Q(sig000005ee),
.Q15(NLW_blk00000383_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000384 (
.C(clk),
.CE(ce),
.D(sig000005ee),
.Q(sig00000456)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000385 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000b0),
.Q(sig000005ef),
.Q15(NLW_blk00000385_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000386 (
.C(clk),
.CE(ce),
.D(sig000005ef),
.Q(sig00000458)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000387 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000af),
.Q(sig000005f0),
.Q15(NLW_blk00000387_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000388 (
.C(clk),
.CE(ce),
.D(sig000005f0),
.Q(sig00000457)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000389 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000ab),
.Q(sig000005f1),
.Q15(NLW_blk00000389_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038a (
.C(clk),
.CE(ce),
.D(sig000005f1),
.Q(sig00000453)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000038b (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000ad),
.Q(sig000005f2),
.Q15(NLW_blk0000038b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038c (
.C(clk),
.CE(ce),
.D(sig000005f2),
.Q(sig00000455)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000038d (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000ac),
.Q(sig000005f3),
.Q15(NLW_blk0000038d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000038e (
.C(clk),
.CE(ce),
.D(sig000005f3),
.Q(sig00000454)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000038f (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001d6),
.Q(sig000005f4),
.Q15(NLW_blk0000038f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000390 (
.C(clk),
.CE(ce),
.D(sig000005f4),
.Q(sig00000467)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000391 (
.A0(sig00000001),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000001),
.CE(ce),
.CLK(clk),
.D(sig000000aa),
.Q(sig000005f5),
.Q15(NLW_blk00000391_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000392 (
.C(clk),
.CE(ce),
.D(sig000005f5),
.Q(sig00000452)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000393 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001d7),
.Q(sig000005f6),
.Q15(NLW_blk00000393_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000394 (
.C(clk),
.CE(ce),
.D(sig000005f6),
.Q(sig00000468)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000395 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001d3),
.Q(sig000005f7),
.Q15(NLW_blk00000395_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000396 (
.C(clk),
.CE(ce),
.D(sig000005f7),
.Q(sig00000464)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000397 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001d5),
.Q(sig000005f8),
.Q15(NLW_blk00000397_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000398 (
.C(clk),
.CE(ce),
.D(sig000005f8),
.Q(sig00000466)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000399 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001d4),
.Q(sig000005f9),
.Q15(NLW_blk00000399_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039a (
.C(clk),
.CE(ce),
.D(sig000005f9),
.Q(sig00000465)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000039b (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000007f),
.Q(sig000005fa),
.Q15(NLW_blk0000039b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039c (
.C(clk),
.CE(ce),
.D(sig000005fa),
.Q(\U0/op_inst/FLT_PT_OP/MULT.OP/OP/sign_op )
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000039d (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001d2),
.Q(sig000005fb),
.Q15(NLW_blk0000039d_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000039e (
.C(clk),
.CE(ce),
.D(sig000005fb),
.Q(sig00000463)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000039f (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000192),
.Q(sig000005fc),
.Q15(NLW_blk0000039f_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a0 (
.C(clk),
.CE(ce),
.D(sig000005fc),
.Q(sig00000138)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003a1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000191),
.Q(sig000005fd),
.Q15(NLW_blk000003a1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a2 (
.C(clk),
.CE(ce),
.D(sig000005fd),
.Q(sig00000137)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003a3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000193),
.Q(sig000005fe),
.Q15(NLW_blk000003a3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a4 (
.C(clk),
.CE(ce),
.D(sig000005fe),
.Q(sig00000139)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003a5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000194),
.Q(sig000005ff),
.Q15(NLW_blk000003a5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a6 (
.C(clk),
.CE(ce),
.D(sig000005ff),
.Q(sig0000013a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003a7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000195),
.Q(sig00000600),
.Q15(NLW_blk000003a7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003a8 (
.C(clk),
.CE(ce),
.D(sig00000600),
.Q(sig0000013b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003a9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000196),
.Q(sig00000601),
.Q15(NLW_blk000003a9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003aa (
.C(clk),
.CE(ce),
.D(sig00000601),
.Q(sig0000013c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003ab (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000199),
.Q(sig00000602),
.Q15(NLW_blk000003ab_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ac (
.C(clk),
.CE(ce),
.D(sig00000602),
.Q(sig0000013f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003ad (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000197),
.Q(sig00000603),
.Q15(NLW_blk000003ad_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ae (
.C(clk),
.CE(ce),
.D(sig00000603),
.Q(sig0000013d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003af (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000198),
.Q(sig00000604),
.Q15(NLW_blk000003af_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b0 (
.C(clk),
.CE(ce),
.D(sig00000604),
.Q(sig0000013e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003b1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000019c),
.Q(sig00000605),
.Q15(NLW_blk000003b1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b2 (
.C(clk),
.CE(ce),
.D(sig00000605),
.Q(sig00000142)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003b3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000019a),
.Q(sig00000606),
.Q15(NLW_blk000003b3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b4 (
.C(clk),
.CE(ce),
.D(sig00000606),
.Q(sig00000140)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003b5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000019b),
.Q(sig00000607),
.Q15(NLW_blk000003b5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b6 (
.C(clk),
.CE(ce),
.D(sig00000607),
.Q(sig00000141)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003b7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000019f),
.Q(sig00000608),
.Q15(NLW_blk000003b7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003b8 (
.C(clk),
.CE(ce),
.D(sig00000608),
.Q(sig00000145)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003b9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000019d),
.Q(sig00000609),
.Q15(NLW_blk000003b9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ba (
.C(clk),
.CE(ce),
.D(sig00000609),
.Q(sig00000143)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003bb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000019e),
.Q(sig0000060a),
.Q15(NLW_blk000003bb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003bc (
.C(clk),
.CE(ce),
.D(sig0000060a),
.Q(sig00000144)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003bd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a0),
.Q(sig0000060b),
.Q15(NLW_blk000003bd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003be (
.C(clk),
.CE(ce),
.D(sig0000060b),
.Q(sig00000146)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003bf (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig000001a1),
.Q(sig0000060c),
.Q15(NLW_blk000003bf_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c0 (
.C(clk),
.CE(ce),
.D(sig0000060c),
.Q(sig00000147)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003c1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000016e),
.Q(sig0000060d),
.Q15(NLW_blk000003c1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c2 (
.C(clk),
.CE(ce),
.D(sig0000060d),
.Q(sig00000114)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003c3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000171),
.Q(sig0000060e),
.Q15(NLW_blk000003c3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c4 (
.C(clk),
.CE(ce),
.D(sig0000060e),
.Q(sig00000117)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003c5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000016f),
.Q(sig0000060f),
.Q15(NLW_blk000003c5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c6 (
.C(clk),
.CE(ce),
.D(sig0000060f),
.Q(sig00000115)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003c7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000170),
.Q(sig00000610),
.Q15(NLW_blk000003c7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003c8 (
.C(clk),
.CE(ce),
.D(sig00000610),
.Q(sig00000116)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003c9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000174),
.Q(sig00000611),
.Q15(NLW_blk000003c9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ca (
.C(clk),
.CE(ce),
.D(sig00000611),
.Q(sig0000011a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003cb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000172),
.Q(sig00000612),
.Q15(NLW_blk000003cb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003cc (
.C(clk),
.CE(ce),
.D(sig00000612),
.Q(sig00000118)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003cd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000173),
.Q(sig00000613),
.Q15(NLW_blk000003cd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ce (
.C(clk),
.CE(ce),
.D(sig00000613),
.Q(sig00000119)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003cf (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000177),
.Q(sig00000614),
.Q15(NLW_blk000003cf_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d0 (
.C(clk),
.CE(ce),
.D(sig00000614),
.Q(sig0000011d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003d1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000175),
.Q(sig00000615),
.Q15(NLW_blk000003d1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d2 (
.C(clk),
.CE(ce),
.D(sig00000615),
.Q(sig0000011b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003d3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000176),
.Q(sig00000616),
.Q15(NLW_blk000003d3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d4 (
.C(clk),
.CE(ce),
.D(sig00000616),
.Q(sig0000011c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003d5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000017a),
.Q(sig00000617),
.Q15(NLW_blk000003d5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d6 (
.C(clk),
.CE(ce),
.D(sig00000617),
.Q(sig00000120)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003d7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000178),
.Q(sig00000618),
.Q15(NLW_blk000003d7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003d8 (
.C(clk),
.CE(ce),
.D(sig00000618),
.Q(sig0000011e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003d9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000179),
.Q(sig00000619),
.Q15(NLW_blk000003d9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003da (
.C(clk),
.CE(ce),
.D(sig00000619),
.Q(sig0000011f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003db (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000017d),
.Q(sig0000061a),
.Q15(NLW_blk000003db_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003dc (
.C(clk),
.CE(ce),
.D(sig0000061a),
.Q(sig00000123)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003dd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000017b),
.Q(sig0000061b),
.Q15(NLW_blk000003dd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003de (
.C(clk),
.CE(ce),
.D(sig0000061b),
.Q(sig00000121)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003df (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000017c),
.Q(sig0000061c),
.Q15(NLW_blk000003df_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e0 (
.C(clk),
.CE(ce),
.D(sig0000061c),
.Q(sig00000122)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003e1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000017e),
.Q(sig0000061d),
.Q15(NLW_blk000003e1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e2 (
.C(clk),
.CE(ce),
.D(sig0000061d),
.Q(sig00000124)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003e3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000017f),
.Q(sig0000061e),
.Q15(NLW_blk000003e3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e4 (
.C(clk),
.CE(ce),
.D(sig0000061e),
.Q(sig00000125)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003e5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000014b),
.Q(sig0000061f),
.Q15(NLW_blk000003e5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e6 (
.C(clk),
.CE(ce),
.D(sig0000061f),
.Q(sig00000102)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003e7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000014c),
.Q(sig00000620),
.Q15(NLW_blk000003e7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003e8 (
.C(clk),
.CE(ce),
.D(sig00000620),
.Q(sig00000103)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003e9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000014d),
.Q(sig00000621),
.Q15(NLW_blk000003e9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ea (
.C(clk),
.CE(ce),
.D(sig00000621),
.Q(sig00000104)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003eb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000014e),
.Q(sig00000622),
.Q15(NLW_blk000003eb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ec (
.C(clk),
.CE(ce),
.D(sig00000622),
.Q(sig00000105)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003ed (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000151),
.Q(sig00000623),
.Q15(NLW_blk000003ed_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003ee (
.C(clk),
.CE(ce),
.D(sig00000623),
.Q(sig00000108)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003ef (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000014f),
.Q(sig00000624),
.Q15(NLW_blk000003ef_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f0 (
.C(clk),
.CE(ce),
.D(sig00000624),
.Q(sig00000106)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003f1 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000150),
.Q(sig00000625),
.Q15(NLW_blk000003f1_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f2 (
.C(clk),
.CE(ce),
.D(sig00000625),
.Q(sig00000107)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003f3 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000154),
.Q(sig00000626),
.Q15(NLW_blk000003f3_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f4 (
.C(clk),
.CE(ce),
.D(sig00000626),
.Q(sig0000010b)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003f5 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000152),
.Q(sig00000627),
.Q15(NLW_blk000003f5_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f6 (
.C(clk),
.CE(ce),
.D(sig00000627),
.Q(sig00000109)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003f7 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000153),
.Q(sig00000628),
.Q15(NLW_blk000003f7_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003f8 (
.C(clk),
.CE(ce),
.D(sig00000628),
.Q(sig0000010a)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003f9 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000157),
.Q(sig00000629),
.Q15(NLW_blk000003f9_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fa (
.C(clk),
.CE(ce),
.D(sig00000629),
.Q(sig0000010e)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003fb (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000155),
.Q(sig0000062a),
.Q15(NLW_blk000003fb_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fc (
.C(clk),
.CE(ce),
.D(sig0000062a),
.Q(sig0000010c)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003fd (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000156),
.Q(sig0000062b),
.Q15(NLW_blk000003fd_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk000003fe (
.C(clk),
.CE(ce),
.D(sig0000062b),
.Q(sig0000010d)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk000003ff (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000158),
.Q(sig0000062c),
.Q15(NLW_blk000003ff_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000400 (
.C(clk),
.CE(ce),
.D(sig0000062c),
.Q(sig0000010f)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000401 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000159),
.Q(sig0000062d),
.Q15(NLW_blk00000401_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000402 (
.C(clk),
.CE(ce),
.D(sig0000062d),
.Q(sig00000110)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000403 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000015a),
.Q(sig0000062e),
.Q15(NLW_blk00000403_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000404 (
.C(clk),
.CE(ce),
.D(sig0000062e),
.Q(sig00000111)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000405 (
.A0(sig00000001),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000015b),
.Q(sig0000062f),
.Q15(NLW_blk00000405_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000406 (
.C(clk),
.CE(ce),
.D(sig0000062f),
.Q(sig00000112)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000407 (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000113),
.Q(sig00000630),
.Q15(NLW_blk00000407_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk00000408 (
.C(clk),
.CE(ce),
.D(sig00000630),
.Q(sig00000100)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk00000409 (
.A0(sig00000461),
.A1(sig00000001),
.A2(sig00000461),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig0000014a),
.Q(sig00000631),
.Q15(NLW_blk00000409_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000040a (
.C(clk),
.CE(ce),
.D(sig00000631),
.Q(sig00000101)
);
SRLC16E #(
.INIT ( 16'h0000 ))
blk0000040b (
.A0(sig00000461),
.A1(sig00000461),
.A2(sig00000001),
.A3(sig00000461),
.CE(ce),
.CLK(clk),
.D(sig00000100),
.Q(sig00000632),
.Q15(NLW_blk0000040b_Q15_UNCONNECTED)
);
FDE #(
.INIT ( 1'b0 ))
blk0000040c (
.C(clk),
.CE(ce),
.D(sig00000632),
.Q(sig00000551)
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "CASCADE" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk0000040d (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk0000040d_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk0000040d_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk0000040d_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk0000040d_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk0000040d_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(sig00000461),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk0000040d_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000001, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig00000207, sig00000206, sig00000205, sig00000204, sig00000203, sig00000202, sig00000201, sig00000200, sig000001ff, sig000001fe,
sig000001fd, sig000001fc, sig000001fb, sig000001fa, sig000001f9, sig000001f8, sig000001f7, sig000001f6, sig000001f5, sig000001f4, sig000001f3,
sig000001f2, sig000001f1, sig000001f0, sig000001ef, sig000001ee, sig000001ed, sig000001ec, sig000001eb, sig000001ea, sig000001e9, sig000001e8,
sig000001e7, sig000001e6, sig000001e5, sig000001e4, sig000001e3, sig000001e2, sig000001e1, sig000001e0, sig000001df, sig000001de, sig000001dd,
sig000001dc, sig000001db, sig000001da, sig000001d9, sig000001d8}),
.B({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000100, sig00000101}),
.P({\NLW_blk0000040d_P<47>_UNCONNECTED , \NLW_blk0000040d_P<46>_UNCONNECTED , \NLW_blk0000040d_P<45>_UNCONNECTED ,
\NLW_blk0000040d_P<44>_UNCONNECTED , \NLW_blk0000040d_P<43>_UNCONNECTED , \NLW_blk0000040d_P<42>_UNCONNECTED , \NLW_blk0000040d_P<41>_UNCONNECTED ,
\NLW_blk0000040d_P<40>_UNCONNECTED , \NLW_blk0000040d_P<39>_UNCONNECTED , \NLW_blk0000040d_P<38>_UNCONNECTED , \NLW_blk0000040d_P<37>_UNCONNECTED ,
\NLW_blk0000040d_P<36>_UNCONNECTED , \NLW_blk0000040d_P<35>_UNCONNECTED , \NLW_blk0000040d_P<34>_UNCONNECTED , \NLW_blk0000040d_P<33>_UNCONNECTED ,
\NLW_blk0000040d_P<32>_UNCONNECTED , \NLW_blk0000040d_P<31>_UNCONNECTED , \NLW_blk0000040d_P<30>_UNCONNECTED , \NLW_blk0000040d_P<29>_UNCONNECTED ,
\NLW_blk0000040d_P<28>_UNCONNECTED , \NLW_blk0000040d_P<27>_UNCONNECTED , \NLW_blk0000040d_P<26>_UNCONNECTED , \NLW_blk0000040d_P<25>_UNCONNECTED ,
\NLW_blk0000040d_P<24>_UNCONNECTED , \NLW_blk0000040d_P<23>_UNCONNECTED , \NLW_blk0000040d_P<22>_UNCONNECTED , \NLW_blk0000040d_P<21>_UNCONNECTED ,
sig00000008, sig00000009, sig0000000a, sig0000000b, sig0000000c, sig0000000d, sig0000000e, sig0000000f, sig00000010, sig00000011, sig00000012,
sig00000013, sig00000014, sig00000015, sig00000016, sig00000017, sig00000018, sig00000019, sig0000001a, sig0000001b, sig0000001c}),
.PCOUT({\NLW_blk0000040d_PCOUT<47>_UNCONNECTED , \NLW_blk0000040d_PCOUT<46>_UNCONNECTED , \NLW_blk0000040d_PCOUT<45>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<44>_UNCONNECTED , \NLW_blk0000040d_PCOUT<43>_UNCONNECTED , \NLW_blk0000040d_PCOUT<42>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<41>_UNCONNECTED , \NLW_blk0000040d_PCOUT<40>_UNCONNECTED , \NLW_blk0000040d_PCOUT<39>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<38>_UNCONNECTED , \NLW_blk0000040d_PCOUT<37>_UNCONNECTED , \NLW_blk0000040d_PCOUT<36>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<35>_UNCONNECTED , \NLW_blk0000040d_PCOUT<34>_UNCONNECTED , \NLW_blk0000040d_PCOUT<33>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<32>_UNCONNECTED , \NLW_blk0000040d_PCOUT<31>_UNCONNECTED , \NLW_blk0000040d_PCOUT<30>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<29>_UNCONNECTED , \NLW_blk0000040d_PCOUT<28>_UNCONNECTED , \NLW_blk0000040d_PCOUT<27>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<26>_UNCONNECTED , \NLW_blk0000040d_PCOUT<25>_UNCONNECTED , \NLW_blk0000040d_PCOUT<24>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<23>_UNCONNECTED , \NLW_blk0000040d_PCOUT<22>_UNCONNECTED , \NLW_blk0000040d_PCOUT<21>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<20>_UNCONNECTED , \NLW_blk0000040d_PCOUT<19>_UNCONNECTED , \NLW_blk0000040d_PCOUT<18>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<17>_UNCONNECTED , \NLW_blk0000040d_PCOUT<16>_UNCONNECTED , \NLW_blk0000040d_PCOUT<15>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<14>_UNCONNECTED , \NLW_blk0000040d_PCOUT<13>_UNCONNECTED , \NLW_blk0000040d_PCOUT<12>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<11>_UNCONNECTED , \NLW_blk0000040d_PCOUT<10>_UNCONNECTED , \NLW_blk0000040d_PCOUT<9>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<8>_UNCONNECTED , \NLW_blk0000040d_PCOUT<7>_UNCONNECTED , \NLW_blk0000040d_PCOUT<6>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<5>_UNCONNECTED , \NLW_blk0000040d_PCOUT<4>_UNCONNECTED , \NLW_blk0000040d_PCOUT<3>_UNCONNECTED ,
\NLW_blk0000040d_PCOUT<2>_UNCONNECTED , \NLW_blk0000040d_PCOUT<1>_UNCONNECTED , \NLW_blk0000040d_PCOUT<0>_UNCONNECTED }),
.ACIN({sig00000225, sig00000224, sig00000223, sig00000222, sig00000221, sig00000220, sig0000021f, sig0000021e, sig0000021d, sig0000021c,
sig0000021b, sig0000021a, sig00000219, sig00000218, sig00000217, sig00000216, sig00000215, sig00000214, sig00000213, sig00000212, sig00000211,
sig00000210, sig0000020f, sig0000020e, sig0000020d, sig0000020c, sig0000020b, sig0000020a, sig00000209, sig00000208}),
.ACOUT({\NLW_blk0000040d_ACOUT<29>_UNCONNECTED , \NLW_blk0000040d_ACOUT<28>_UNCONNECTED , \NLW_blk0000040d_ACOUT<27>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<26>_UNCONNECTED , \NLW_blk0000040d_ACOUT<25>_UNCONNECTED , \NLW_blk0000040d_ACOUT<24>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<23>_UNCONNECTED , \NLW_blk0000040d_ACOUT<22>_UNCONNECTED , \NLW_blk0000040d_ACOUT<21>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<20>_UNCONNECTED , \NLW_blk0000040d_ACOUT<19>_UNCONNECTED , \NLW_blk0000040d_ACOUT<18>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<17>_UNCONNECTED , \NLW_blk0000040d_ACOUT<16>_UNCONNECTED , \NLW_blk0000040d_ACOUT<15>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<14>_UNCONNECTED , \NLW_blk0000040d_ACOUT<13>_UNCONNECTED , \NLW_blk0000040d_ACOUT<12>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<11>_UNCONNECTED , \NLW_blk0000040d_ACOUT<10>_UNCONNECTED , \NLW_blk0000040d_ACOUT<9>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<8>_UNCONNECTED , \NLW_blk0000040d_ACOUT<7>_UNCONNECTED , \NLW_blk0000040d_ACOUT<6>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<5>_UNCONNECTED , \NLW_blk0000040d_ACOUT<4>_UNCONNECTED , \NLW_blk0000040d_ACOUT<3>_UNCONNECTED ,
\NLW_blk0000040d_ACOUT<2>_UNCONNECTED , \NLW_blk0000040d_ACOUT<1>_UNCONNECTED , \NLW_blk0000040d_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk0000040d_CARRYOUT<3>_UNCONNECTED , \NLW_blk0000040d_CARRYOUT<2>_UNCONNECTED , \NLW_blk0000040d_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk0000040d_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk0000040d_BCOUT<17>_UNCONNECTED , \NLW_blk0000040d_BCOUT<16>_UNCONNECTED , \NLW_blk0000040d_BCOUT<15>_UNCONNECTED ,
\NLW_blk0000040d_BCOUT<14>_UNCONNECTED , \NLW_blk0000040d_BCOUT<13>_UNCONNECTED , \NLW_blk0000040d_BCOUT<12>_UNCONNECTED ,
\NLW_blk0000040d_BCOUT<11>_UNCONNECTED , \NLW_blk0000040d_BCOUT<10>_UNCONNECTED , \NLW_blk0000040d_BCOUT<9>_UNCONNECTED ,
\NLW_blk0000040d_BCOUT<8>_UNCONNECTED , \NLW_blk0000040d_BCOUT<7>_UNCONNECTED , \NLW_blk0000040d_BCOUT<6>_UNCONNECTED ,
\NLW_blk0000040d_BCOUT<5>_UNCONNECTED , \NLW_blk0000040d_BCOUT<4>_UNCONNECTED , \NLW_blk0000040d_BCOUT<3>_UNCONNECTED ,
\NLW_blk0000040d_BCOUT<2>_UNCONNECTED , \NLW_blk0000040d_BCOUT<1>_UNCONNECTED , \NLW_blk0000040d_BCOUT<0>_UNCONNECTED }),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "CASCADE" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk0000040e (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk0000040e_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk0000040e_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk0000040e_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk0000040e_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk0000040e_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(sig00000461),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk0000040e_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.ACOUT({sig00000225, sig00000224, sig00000223, sig00000222, sig00000221, sig00000220, sig0000021f, sig0000021e, sig0000021d, sig0000021c,
sig0000021b, sig0000021a, sig00000219, sig00000218, sig00000217, sig00000216, sig00000215, sig00000214, sig00000213, sig00000212, sig00000211,
sig00000210, sig0000020f, sig0000020e, sig0000020d, sig0000020c, sig0000020b, sig0000020a, sig00000209, sig00000208}),
.OPMODE({sig00000001, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig00000266, sig00000265, sig00000264, sig00000263, sig00000262, sig00000261, sig00000260, sig0000025f, sig0000025e, sig0000025d,
sig0000025c, sig0000025b, sig0000025a, sig00000259, sig00000258, sig00000257, sig00000256, sig00000255, sig00000254, sig00000253, sig00000252,
sig00000251, sig00000250, sig0000024f, sig0000024e, sig0000024d, sig0000024c, sig0000024b, sig0000024a, sig00000249, sig00000248, sig00000247,
sig00000246, sig00000245, sig00000244, sig00000243, sig00000242, sig00000241, sig00000240, sig0000023f, sig0000023e, sig0000023d, sig0000023c,
sig0000023b, sig0000023a, sig00000239, sig00000238, sig00000237}),
.B({sig00000461, sig00000102, sig00000103, sig00000104, sig00000105, sig00000106, sig00000107, sig00000108, sig00000109, sig0000010a, sig0000010b
, sig0000010c, sig0000010d, sig0000010e, sig0000010f, sig00000110, sig00000111, sig00000112}),
.P({\NLW_blk0000040e_P<47>_UNCONNECTED , \NLW_blk0000040e_P<46>_UNCONNECTED , \NLW_blk0000040e_P<45>_UNCONNECTED ,
\NLW_blk0000040e_P<44>_UNCONNECTED , \NLW_blk0000040e_P<43>_UNCONNECTED , \NLW_blk0000040e_P<42>_UNCONNECTED , \NLW_blk0000040e_P<41>_UNCONNECTED ,
\NLW_blk0000040e_P<40>_UNCONNECTED , \NLW_blk0000040e_P<39>_UNCONNECTED , \NLW_blk0000040e_P<38>_UNCONNECTED , \NLW_blk0000040e_P<37>_UNCONNECTED ,
\NLW_blk0000040e_P<36>_UNCONNECTED , \NLW_blk0000040e_P<35>_UNCONNECTED , \NLW_blk0000040e_P<34>_UNCONNECTED , \NLW_blk0000040e_P<33>_UNCONNECTED ,
\NLW_blk0000040e_P<32>_UNCONNECTED , \NLW_blk0000040e_P<31>_UNCONNECTED , \NLW_blk0000040e_P<30>_UNCONNECTED , \NLW_blk0000040e_P<29>_UNCONNECTED ,
\NLW_blk0000040e_P<28>_UNCONNECTED , \NLW_blk0000040e_P<27>_UNCONNECTED , \NLW_blk0000040e_P<26>_UNCONNECTED , \NLW_blk0000040e_P<25>_UNCONNECTED ,
\NLW_blk0000040e_P<24>_UNCONNECTED , \NLW_blk0000040e_P<23>_UNCONNECTED , \NLW_blk0000040e_P<22>_UNCONNECTED , \NLW_blk0000040e_P<21>_UNCONNECTED ,
\NLW_blk0000040e_P<20>_UNCONNECTED , \NLW_blk0000040e_P<19>_UNCONNECTED , \NLW_blk0000040e_P<18>_UNCONNECTED , \NLW_blk0000040e_P<17>_UNCONNECTED ,
sig000001d7, sig000001d6, sig000001d5, sig000001d4, sig000001d3, sig000001d2, sig000001d1, sig000001d0, sig000001cf, sig000001ce, sig000001cd,
sig000001cc, sig000001cb, sig000001ca, sig000001c9, sig000001c8, sig000001c7}),
.PCOUT({sig00000207, sig00000206, sig00000205, sig00000204, sig00000203, sig00000202, sig00000201, sig00000200, sig000001ff, sig000001fe,
sig000001fd, sig000001fc, sig000001fb, sig000001fa, sig000001f9, sig000001f8, sig000001f7, sig000001f6, sig000001f5, sig000001f4, sig000001f3,
sig000001f2, sig000001f1, sig000001f0, sig000001ef, sig000001ee, sig000001ed, sig000001ec, sig000001eb, sig000001ea, sig000001e9, sig000001e8,
sig000001e7, sig000001e6, sig000001e5, sig000001e4, sig000001e3, sig000001e2, sig000001e1, sig000001e0, sig000001df, sig000001de, sig000001dd,
sig000001dc, sig000001db, sig000001da, sig000001d9, sig000001d8}),
.ACIN({sig00000284, sig00000283, sig00000282, sig00000281, sig00000280, sig0000027f, sig0000027e, sig0000027d, sig0000027c, sig0000027b,
sig0000027a, sig00000279, sig00000278, sig00000277, sig00000276, sig00000275, sig00000274, sig00000273, sig00000272, sig00000271, sig00000270,
sig0000026f, sig0000026e, sig0000026d, sig0000026c, sig0000026b, sig0000026a, sig00000269, sig00000268, sig00000267}),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk0000040e_CARRYOUT<3>_UNCONNECTED , \NLW_blk0000040e_CARRYOUT<2>_UNCONNECTED , \NLW_blk0000040e_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk0000040e_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk0000040e_BCOUT<17>_UNCONNECTED , \NLW_blk0000040e_BCOUT<16>_UNCONNECTED , \NLW_blk0000040e_BCOUT<15>_UNCONNECTED ,
\NLW_blk0000040e_BCOUT<14>_UNCONNECTED , \NLW_blk0000040e_BCOUT<13>_UNCONNECTED , \NLW_blk0000040e_BCOUT<12>_UNCONNECTED ,
\NLW_blk0000040e_BCOUT<11>_UNCONNECTED , \NLW_blk0000040e_BCOUT<10>_UNCONNECTED , \NLW_blk0000040e_BCOUT<9>_UNCONNECTED ,
\NLW_blk0000040e_BCOUT<8>_UNCONNECTED , \NLW_blk0000040e_BCOUT<7>_UNCONNECTED , \NLW_blk0000040e_BCOUT<6>_UNCONNECTED ,
\NLW_blk0000040e_BCOUT<5>_UNCONNECTED , \NLW_blk0000040e_BCOUT<4>_UNCONNECTED , \NLW_blk0000040e_BCOUT<3>_UNCONNECTED ,
\NLW_blk0000040e_BCOUT<2>_UNCONNECTED , \NLW_blk0000040e_BCOUT<1>_UNCONNECTED , \NLW_blk0000040e_BCOUT<0>_UNCONNECTED }),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk0000040f (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk0000040f_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk0000040f_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk0000040f_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk0000040f_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk0000040f_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk0000040f_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.ACOUT({sig00000284, sig00000283, sig00000282, sig00000281, sig00000280, sig0000027f, sig0000027e, sig0000027d, sig0000027c, sig0000027b,
sig0000027a, sig00000279, sig00000278, sig00000277, sig00000276, sig00000275, sig00000274, sig00000273, sig00000272, sig00000271, sig00000270,
sig0000026f, sig0000026e, sig0000026d, sig0000026c, sig0000026b, sig0000026a, sig00000269, sig00000268, sig00000267}),
.OPMODE({sig00000461, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig000002b4, sig000002b3, sig000002b2, sig000002b1, sig000002b0, sig000002af, sig000002ae, sig000002ad, sig000002ac, sig000002ab,
sig000002aa, sig000002a9, sig000002a8, sig000002a7, sig000002a6, sig000002a5, sig000002a4, sig000002a3, sig000002a2, sig000002a1, sig000002a0,
sig0000029f, sig0000029e, sig0000029d, sig0000029c, sig0000029b, sig0000029a, sig00000299, sig00000298, sig00000297, sig00000296, sig00000295,
sig00000294, sig00000293, sig00000292, sig00000291, sig00000290, sig0000028f, sig0000028e, sig0000028d, sig0000028c, sig0000028b, sig0000028a,
sig00000289, sig00000288, sig00000287, sig00000286, sig00000285}),
.B({sig00000461, sig00000126, sig00000127, sig00000128, sig00000129, sig0000012a, sig0000012b, sig0000012c, sig0000012d, sig0000012e, sig0000012f
, sig00000130, sig00000131, sig00000132, sig00000133, sig00000134, sig00000135, sig00000136}),
.P({\NLW_blk0000040f_P<47>_UNCONNECTED , \NLW_blk0000040f_P<46>_UNCONNECTED , \NLW_blk0000040f_P<45>_UNCONNECTED ,
\NLW_blk0000040f_P<44>_UNCONNECTED , \NLW_blk0000040f_P<43>_UNCONNECTED , \NLW_blk0000040f_P<42>_UNCONNECTED , \NLW_blk0000040f_P<41>_UNCONNECTED ,
\NLW_blk0000040f_P<40>_UNCONNECTED , \NLW_blk0000040f_P<39>_UNCONNECTED , \NLW_blk0000040f_P<38>_UNCONNECTED , \NLW_blk0000040f_P<37>_UNCONNECTED ,
\NLW_blk0000040f_P<36>_UNCONNECTED , \NLW_blk0000040f_P<35>_UNCONNECTED , \NLW_blk0000040f_P<34>_UNCONNECTED , \NLW_blk0000040f_P<33>_UNCONNECTED ,
\NLW_blk0000040f_P<32>_UNCONNECTED , \NLW_blk0000040f_P<31>_UNCONNECTED , \NLW_blk0000040f_P<30>_UNCONNECTED , \NLW_blk0000040f_P<29>_UNCONNECTED ,
\NLW_blk0000040f_P<28>_UNCONNECTED , \NLW_blk0000040f_P<27>_UNCONNECTED , \NLW_blk0000040f_P<26>_UNCONNECTED , \NLW_blk0000040f_P<25>_UNCONNECTED ,
\NLW_blk0000040f_P<24>_UNCONNECTED , \NLW_blk0000040f_P<23>_UNCONNECTED , \NLW_blk0000040f_P<22>_UNCONNECTED , \NLW_blk0000040f_P<21>_UNCONNECTED ,
\NLW_blk0000040f_P<20>_UNCONNECTED , \NLW_blk0000040f_P<19>_UNCONNECTED , \NLW_blk0000040f_P<18>_UNCONNECTED , \NLW_blk0000040f_P<17>_UNCONNECTED ,
sig00000236, sig00000235, sig00000234, sig00000233, sig00000232, sig00000231, sig00000230, sig0000022f, sig0000022e, sig0000022d, sig0000022c,
sig0000022b, sig0000022a, sig00000229, sig00000228, sig00000227, sig00000226}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000113, sig00000114, sig00000115, sig00000116, sig00000117, sig00000118, sig00000119, sig0000011a, sig0000011b, sig0000011c, sig0000011d,
sig0000011e, sig0000011f, sig00000120, sig00000121, sig00000122, sig00000123, sig00000124, sig00000125}),
.PCOUT({sig00000266, sig00000265, sig00000264, sig00000263, sig00000262, sig00000261, sig00000260, sig0000025f, sig0000025e, sig0000025d,
sig0000025c, sig0000025b, sig0000025a, sig00000259, sig00000258, sig00000257, sig00000256, sig00000255, sig00000254, sig00000253, sig00000252,
sig00000251, sig00000250, sig0000024f, sig0000024e, sig0000024d, sig0000024c, sig0000024b, sig0000024a, sig00000249, sig00000248, sig00000247,
sig00000246, sig00000245, sig00000244, sig00000243, sig00000242, sig00000241, sig00000240, sig0000023f, sig0000023e, sig0000023d, sig0000023c,
sig0000023b, sig0000023a, sig00000239, sig00000238, sig00000237}),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk0000040f_CARRYOUT<3>_UNCONNECTED , \NLW_blk0000040f_CARRYOUT<2>_UNCONNECTED , \NLW_blk0000040f_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk0000040f_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk0000040f_BCOUT<17>_UNCONNECTED , \NLW_blk0000040f_BCOUT<16>_UNCONNECTED , \NLW_blk0000040f_BCOUT<15>_UNCONNECTED ,
\NLW_blk0000040f_BCOUT<14>_UNCONNECTED , \NLW_blk0000040f_BCOUT<13>_UNCONNECTED , \NLW_blk0000040f_BCOUT<12>_UNCONNECTED ,
\NLW_blk0000040f_BCOUT<11>_UNCONNECTED , \NLW_blk0000040f_BCOUT<10>_UNCONNECTED , \NLW_blk0000040f_BCOUT<9>_UNCONNECTED ,
\NLW_blk0000040f_BCOUT<8>_UNCONNECTED , \NLW_blk0000040f_BCOUT<7>_UNCONNECTED , \NLW_blk0000040f_BCOUT<6>_UNCONNECTED ,
\NLW_blk0000040f_BCOUT<5>_UNCONNECTED , \NLW_blk0000040f_BCOUT<4>_UNCONNECTED , \NLW_blk0000040f_BCOUT<3>_UNCONNECTED ,
\NLW_blk0000040f_BCOUT<2>_UNCONNECTED , \NLW_blk0000040f_BCOUT<1>_UNCONNECTED , \NLW_blk0000040f_BCOUT<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "CASCADE" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000410 (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000410_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk00000410_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000410_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000410_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000410_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(sig00000461),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000410_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000001, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig000002e5, sig000002e4, sig000002e3, sig000002e2, sig000002e1, sig000002e0, sig000002df, sig000002de, sig000002dd, sig000002dc,
sig000002db, sig000002da, sig000002d9, sig000002d8, sig000002d7, sig000002d6, sig000002d5, sig000002d4, sig000002d3, sig000002d2, sig000002d1,
sig000002d0, sig000002cf, sig000002ce, sig000002cd, sig000002cc, sig000002cb, sig000002ca, sig000002c9, sig000002c8, sig000002c7, sig000002c6,
sig000002c5, sig000002c4, sig000002c3, sig000002c2, sig000002c1, sig000002c0, sig000002bf, sig000002be, sig000002bd, sig000002bc, sig000002bb,
sig000002ba, sig000002b9, sig000002b8, sig000002b7, sig000002b6}),
.B({sig00000461, sig00000137, sig00000138, sig00000139, sig0000013a, sig0000013b, sig0000013c, sig0000013d, sig0000013e, sig0000013f, sig00000140
, sig00000141, sig00000142, sig00000143, sig00000144, sig00000145, sig00000146, sig00000147}),
.PCOUT({sig000002b4, sig000002b3, sig000002b2, sig000002b1, sig000002b0, sig000002af, sig000002ae, sig000002ad, sig000002ac, sig000002ab,
sig000002aa, sig000002a9, sig000002a8, sig000002a7, sig000002a6, sig000002a5, sig000002a4, sig000002a3, sig000002a2, sig000002a1, sig000002a0,
sig0000029f, sig0000029e, sig0000029d, sig0000029c, sig0000029b, sig0000029a, sig00000299, sig00000298, sig00000297, sig00000296, sig00000295,
sig00000294, sig00000293, sig00000292, sig00000291, sig00000290, sig0000028f, sig0000028e, sig0000028d, sig0000028c, sig0000028b, sig0000028a,
sig00000289, sig00000288, sig00000287, sig00000286, sig00000285}),
.ACIN({sig00000303, sig00000302, sig00000301, sig00000300, sig000002ff, sig000002fe, sig000002fd, sig000002fc, sig000002fb, sig000002fa,
sig000002f9, sig000002f8, sig000002f7, sig000002f6, sig000002f5, sig000002f4, sig000002f3, sig000002f2, sig000002f1, sig000002f0, sig000002ef,
sig000002ee, sig000002ed, sig000002ec, sig000002eb, sig000002ea, sig000002e9, sig000002e8, sig000002e7, sig000002e6}),
.ACOUT({\NLW_blk00000410_ACOUT<29>_UNCONNECTED , \NLW_blk00000410_ACOUT<28>_UNCONNECTED , \NLW_blk00000410_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<26>_UNCONNECTED , \NLW_blk00000410_ACOUT<25>_UNCONNECTED , \NLW_blk00000410_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<23>_UNCONNECTED , \NLW_blk00000410_ACOUT<22>_UNCONNECTED , \NLW_blk00000410_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<20>_UNCONNECTED , \NLW_blk00000410_ACOUT<19>_UNCONNECTED , \NLW_blk00000410_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<17>_UNCONNECTED , \NLW_blk00000410_ACOUT<16>_UNCONNECTED , \NLW_blk00000410_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<14>_UNCONNECTED , \NLW_blk00000410_ACOUT<13>_UNCONNECTED , \NLW_blk00000410_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<11>_UNCONNECTED , \NLW_blk00000410_ACOUT<10>_UNCONNECTED , \NLW_blk00000410_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<8>_UNCONNECTED , \NLW_blk00000410_ACOUT<7>_UNCONNECTED , \NLW_blk00000410_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<5>_UNCONNECTED , \NLW_blk00000410_ACOUT<4>_UNCONNECTED , \NLW_blk00000410_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000410_ACOUT<2>_UNCONNECTED , \NLW_blk00000410_ACOUT<1>_UNCONNECTED , \NLW_blk00000410_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000410_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000410_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000410_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000410_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk00000410_BCOUT<17>_UNCONNECTED , \NLW_blk00000410_BCOUT<16>_UNCONNECTED , \NLW_blk00000410_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000410_BCOUT<14>_UNCONNECTED , \NLW_blk00000410_BCOUT<13>_UNCONNECTED , \NLW_blk00000410_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000410_BCOUT<11>_UNCONNECTED , \NLW_blk00000410_BCOUT<10>_UNCONNECTED , \NLW_blk00000410_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000410_BCOUT<8>_UNCONNECTED , \NLW_blk00000410_BCOUT<7>_UNCONNECTED , \NLW_blk00000410_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000410_BCOUT<5>_UNCONNECTED , \NLW_blk00000410_BCOUT<4>_UNCONNECTED , \NLW_blk00000410_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000410_BCOUT<2>_UNCONNECTED , \NLW_blk00000410_BCOUT<1>_UNCONNECTED , \NLW_blk00000410_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000410_P<47>_UNCONNECTED , \NLW_blk00000410_P<46>_UNCONNECTED , \NLW_blk00000410_P<45>_UNCONNECTED ,
\NLW_blk00000410_P<44>_UNCONNECTED , \NLW_blk00000410_P<43>_UNCONNECTED , \NLW_blk00000410_P<42>_UNCONNECTED , \NLW_blk00000410_P<41>_UNCONNECTED ,
\NLW_blk00000410_P<40>_UNCONNECTED , \NLW_blk00000410_P<39>_UNCONNECTED , \NLW_blk00000410_P<38>_UNCONNECTED , \NLW_blk00000410_P<37>_UNCONNECTED ,
\NLW_blk00000410_P<36>_UNCONNECTED , \NLW_blk00000410_P<35>_UNCONNECTED , \NLW_blk00000410_P<34>_UNCONNECTED , \NLW_blk00000410_P<33>_UNCONNECTED ,
\NLW_blk00000410_P<32>_UNCONNECTED , \NLW_blk00000410_P<31>_UNCONNECTED , \NLW_blk00000410_P<30>_UNCONNECTED , \NLW_blk00000410_P<29>_UNCONNECTED ,
\NLW_blk00000410_P<28>_UNCONNECTED , \NLW_blk00000410_P<27>_UNCONNECTED , \NLW_blk00000410_P<26>_UNCONNECTED , \NLW_blk00000410_P<25>_UNCONNECTED ,
\NLW_blk00000410_P<24>_UNCONNECTED , \NLW_blk00000410_P<23>_UNCONNECTED , \NLW_blk00000410_P<22>_UNCONNECTED , \NLW_blk00000410_P<21>_UNCONNECTED ,
\NLW_blk00000410_P<20>_UNCONNECTED , \NLW_blk00000410_P<19>_UNCONNECTED , \NLW_blk00000410_P<18>_UNCONNECTED , \NLW_blk00000410_P<17>_UNCONNECTED ,
\NLW_blk00000410_P<16>_UNCONNECTED , \NLW_blk00000410_P<15>_UNCONNECTED , \NLW_blk00000410_P<14>_UNCONNECTED , \NLW_blk00000410_P<13>_UNCONNECTED ,
\NLW_blk00000410_P<12>_UNCONNECTED , \NLW_blk00000410_P<11>_UNCONNECTED , \NLW_blk00000410_P<10>_UNCONNECTED , \NLW_blk00000410_P<9>_UNCONNECTED ,
\NLW_blk00000410_P<8>_UNCONNECTED , \NLW_blk00000410_P<7>_UNCONNECTED , \NLW_blk00000410_P<6>_UNCONNECTED , \NLW_blk00000410_P<5>_UNCONNECTED ,
\NLW_blk00000410_P<4>_UNCONNECTED , \NLW_blk00000410_P<3>_UNCONNECTED , \NLW_blk00000410_P<2>_UNCONNECTED , \NLW_blk00000410_P<1>_UNCONNECTED ,
\NLW_blk00000410_P<0>_UNCONNECTED }),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'hFFFFFFFE0000 ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000411 (
.CEM(ce),
.PATTERNDETECT(sig000002b5),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000411_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk00000411_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000411_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000411_UNDERFLOW_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000411_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.ACOUT({sig00000303, sig00000302, sig00000301, sig00000300, sig000002ff, sig000002fe, sig000002fd, sig000002fc, sig000002fb, sig000002fa,
sig000002f9, sig000002f8, sig000002f7, sig000002f6, sig000002f5, sig000002f4, sig000002f3, sig000002f2, sig000002f1, sig000002f0, sig000002ef,
sig000002ee, sig000002ed, sig000002ec, sig000002eb, sig000002ea, sig000002e9, sig000002e8, sig000002e7, sig000002e6}),
.OPMODE({sig00000461, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig00000333, sig00000332, sig00000331, sig00000330, sig0000032f, sig0000032e, sig0000032d, sig0000032c, sig0000032b, sig0000032a,
sig00000329, sig00000328, sig00000327, sig00000326, sig00000325, sig00000324, sig00000323, sig00000322, sig00000321, sig00000320, sig0000031f,
sig0000031e, sig0000031d, sig0000031c, sig0000031b, sig0000031a, sig00000319, sig00000318, sig00000317, sig00000316, sig00000315, sig00000314,
sig00000313, sig00000312, sig00000311, sig00000310, sig0000030f, sig0000030e, sig0000030d, sig0000030c, sig0000030b, sig0000030a, sig00000309,
sig00000308, sig00000307, sig00000306, sig00000305, sig00000304}),
.B({sig00000461, sig0000015c, sig0000015d, sig0000015e, sig0000015f, sig00000160, sig00000161, sig00000162, sig00000163, sig00000164, sig00000165
, sig00000166, sig00000167, sig00000168, sig00000169, sig0000016a, sig0000016b, sig0000016c}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000149, sig0000014a, sig0000014b, sig0000014c, sig0000014d, sig0000014e, sig0000014f, sig00000150, sig00000151, sig00000152, sig00000153,
sig00000154, sig00000155, sig00000156, sig00000157, sig00000158, sig00000159, sig0000015a, sig0000015b}),
.PCOUT({sig000002e5, sig000002e4, sig000002e3, sig000002e2, sig000002e1, sig000002e0, sig000002df, sig000002de, sig000002dd, sig000002dc,
sig000002db, sig000002da, sig000002d9, sig000002d8, sig000002d7, sig000002d6, sig000002d5, sig000002d4, sig000002d3, sig000002d2, sig000002d1,
sig000002d0, sig000002cf, sig000002ce, sig000002cd, sig000002cc, sig000002cb, sig000002ca, sig000002c9, sig000002c8, sig000002c7, sig000002c6,
sig000002c5, sig000002c4, sig000002c3, sig000002c2, sig000002c1, sig000002c0, sig000002bf, sig000002be, sig000002bd, sig000002bc, sig000002bb,
sig000002ba, sig000002b9, sig000002b8, sig000002b7, sig000002b6}),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000411_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000411_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000411_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000411_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk00000411_BCOUT<17>_UNCONNECTED , \NLW_blk00000411_BCOUT<16>_UNCONNECTED , \NLW_blk00000411_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000411_BCOUT<14>_UNCONNECTED , \NLW_blk00000411_BCOUT<13>_UNCONNECTED , \NLW_blk00000411_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000411_BCOUT<11>_UNCONNECTED , \NLW_blk00000411_BCOUT<10>_UNCONNECTED , \NLW_blk00000411_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000411_BCOUT<8>_UNCONNECTED , \NLW_blk00000411_BCOUT<7>_UNCONNECTED , \NLW_blk00000411_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000411_BCOUT<5>_UNCONNECTED , \NLW_blk00000411_BCOUT<4>_UNCONNECTED , \NLW_blk00000411_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000411_BCOUT<2>_UNCONNECTED , \NLW_blk00000411_BCOUT<1>_UNCONNECTED , \NLW_blk00000411_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000411_P<47>_UNCONNECTED , \NLW_blk00000411_P<46>_UNCONNECTED , \NLW_blk00000411_P<45>_UNCONNECTED ,
\NLW_blk00000411_P<44>_UNCONNECTED , \NLW_blk00000411_P<43>_UNCONNECTED , \NLW_blk00000411_P<42>_UNCONNECTED , \NLW_blk00000411_P<41>_UNCONNECTED ,
\NLW_blk00000411_P<40>_UNCONNECTED , \NLW_blk00000411_P<39>_UNCONNECTED , \NLW_blk00000411_P<38>_UNCONNECTED , \NLW_blk00000411_P<37>_UNCONNECTED ,
\NLW_blk00000411_P<36>_UNCONNECTED , \NLW_blk00000411_P<35>_UNCONNECTED , \NLW_blk00000411_P<34>_UNCONNECTED , \NLW_blk00000411_P<33>_UNCONNECTED ,
\NLW_blk00000411_P<32>_UNCONNECTED , \NLW_blk00000411_P<31>_UNCONNECTED , \NLW_blk00000411_P<30>_UNCONNECTED , \NLW_blk00000411_P<29>_UNCONNECTED ,
\NLW_blk00000411_P<28>_UNCONNECTED , \NLW_blk00000411_P<27>_UNCONNECTED , \NLW_blk00000411_P<26>_UNCONNECTED , \NLW_blk00000411_P<25>_UNCONNECTED ,
\NLW_blk00000411_P<24>_UNCONNECTED , \NLW_blk00000411_P<23>_UNCONNECTED , \NLW_blk00000411_P<22>_UNCONNECTED , \NLW_blk00000411_P<21>_UNCONNECTED ,
\NLW_blk00000411_P<20>_UNCONNECTED , \NLW_blk00000411_P<19>_UNCONNECTED , \NLW_blk00000411_P<18>_UNCONNECTED , \NLW_blk00000411_P<17>_UNCONNECTED ,
\NLW_blk00000411_P<16>_UNCONNECTED , \NLW_blk00000411_P<15>_UNCONNECTED , \NLW_blk00000411_P<14>_UNCONNECTED , \NLW_blk00000411_P<13>_UNCONNECTED ,
\NLW_blk00000411_P<12>_UNCONNECTED , \NLW_blk00000411_P<11>_UNCONNECTED , \NLW_blk00000411_P<10>_UNCONNECTED , \NLW_blk00000411_P<9>_UNCONNECTED ,
\NLW_blk00000411_P<8>_UNCONNECTED , \NLW_blk00000411_P<7>_UNCONNECTED , \NLW_blk00000411_P<6>_UNCONNECTED , \NLW_blk00000411_P<5>_UNCONNECTED ,
\NLW_blk00000411_P<4>_UNCONNECTED , \NLW_blk00000411_P<3>_UNCONNECTED , \NLW_blk00000411_P<2>_UNCONNECTED , \NLW_blk00000411_P<1>_UNCONNECTED ,
\NLW_blk00000411_P<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000412 (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000412_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk00000412_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000412_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000412_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000412_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000412_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000461, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig00000363, sig00000362, sig00000361, sig00000360, sig0000035f, sig0000035e, sig0000035d, sig0000035c, sig0000035b, sig0000035a,
sig00000359, sig00000358, sig00000357, sig00000356, sig00000355, sig00000354, sig00000353, sig00000352, sig00000351, sig00000350, sig0000034f,
sig0000034e, sig0000034d, sig0000034c, sig0000034b, sig0000034a, sig00000349, sig00000348, sig00000347, sig00000346, sig00000345, sig00000344,
sig00000343, sig00000342, sig00000341, sig00000340, sig0000033f, sig0000033e, sig0000033d, sig0000033c, sig0000033b, sig0000033a, sig00000339,
sig00000338, sig00000337, sig00000336, sig00000335, sig00000334}),
.B({sig00000461, sig00000180, sig00000181, sig00000182, sig00000183, sig00000184, sig00000185, sig00000186, sig00000187, sig00000188, sig00000189
, sig0000018a, sig0000018b, sig0000018c, sig0000018d, sig0000018e, sig0000018f, sig00000190}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig0000016d, sig0000016e, sig0000016f, sig00000170, sig00000171, sig00000172, sig00000173, sig00000174, sig00000175, sig00000176, sig00000177,
sig00000178, sig00000179, sig0000017a, sig0000017b, sig0000017c, sig0000017d, sig0000017e, sig0000017f}),
.PCOUT({sig00000333, sig00000332, sig00000331, sig00000330, sig0000032f, sig0000032e, sig0000032d, sig0000032c, sig0000032b, sig0000032a,
sig00000329, sig00000328, sig00000327, sig00000326, sig00000325, sig00000324, sig00000323, sig00000322, sig00000321, sig00000320, sig0000031f,
sig0000031e, sig0000031d, sig0000031c, sig0000031b, sig0000031a, sig00000319, sig00000318, sig00000317, sig00000316, sig00000315, sig00000314,
sig00000313, sig00000312, sig00000311, sig00000310, sig0000030f, sig0000030e, sig0000030d, sig0000030c, sig0000030b, sig0000030a, sig00000309,
sig00000308, sig00000307, sig00000306, sig00000305, sig00000304}),
.ACOUT({\NLW_blk00000412_ACOUT<29>_UNCONNECTED , \NLW_blk00000412_ACOUT<28>_UNCONNECTED , \NLW_blk00000412_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<26>_UNCONNECTED , \NLW_blk00000412_ACOUT<25>_UNCONNECTED , \NLW_blk00000412_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<23>_UNCONNECTED , \NLW_blk00000412_ACOUT<22>_UNCONNECTED , \NLW_blk00000412_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<20>_UNCONNECTED , \NLW_blk00000412_ACOUT<19>_UNCONNECTED , \NLW_blk00000412_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<17>_UNCONNECTED , \NLW_blk00000412_ACOUT<16>_UNCONNECTED , \NLW_blk00000412_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<14>_UNCONNECTED , \NLW_blk00000412_ACOUT<13>_UNCONNECTED , \NLW_blk00000412_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<11>_UNCONNECTED , \NLW_blk00000412_ACOUT<10>_UNCONNECTED , \NLW_blk00000412_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<8>_UNCONNECTED , \NLW_blk00000412_ACOUT<7>_UNCONNECTED , \NLW_blk00000412_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<5>_UNCONNECTED , \NLW_blk00000412_ACOUT<4>_UNCONNECTED , \NLW_blk00000412_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000412_ACOUT<2>_UNCONNECTED , \NLW_blk00000412_ACOUT<1>_UNCONNECTED , \NLW_blk00000412_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000412_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000412_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000412_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000412_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk00000412_BCOUT<17>_UNCONNECTED , \NLW_blk00000412_BCOUT<16>_UNCONNECTED , \NLW_blk00000412_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000412_BCOUT<14>_UNCONNECTED , \NLW_blk00000412_BCOUT<13>_UNCONNECTED , \NLW_blk00000412_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000412_BCOUT<11>_UNCONNECTED , \NLW_blk00000412_BCOUT<10>_UNCONNECTED , \NLW_blk00000412_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000412_BCOUT<8>_UNCONNECTED , \NLW_blk00000412_BCOUT<7>_UNCONNECTED , \NLW_blk00000412_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000412_BCOUT<5>_UNCONNECTED , \NLW_blk00000412_BCOUT<4>_UNCONNECTED , \NLW_blk00000412_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000412_BCOUT<2>_UNCONNECTED , \NLW_blk00000412_BCOUT<1>_UNCONNECTED , \NLW_blk00000412_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000412_P<47>_UNCONNECTED , \NLW_blk00000412_P<46>_UNCONNECTED , \NLW_blk00000412_P<45>_UNCONNECTED ,
\NLW_blk00000412_P<44>_UNCONNECTED , \NLW_blk00000412_P<43>_UNCONNECTED , \NLW_blk00000412_P<42>_UNCONNECTED , \NLW_blk00000412_P<41>_UNCONNECTED ,
\NLW_blk00000412_P<40>_UNCONNECTED , \NLW_blk00000412_P<39>_UNCONNECTED , \NLW_blk00000412_P<38>_UNCONNECTED , \NLW_blk00000412_P<37>_UNCONNECTED ,
\NLW_blk00000412_P<36>_UNCONNECTED , \NLW_blk00000412_P<35>_UNCONNECTED , \NLW_blk00000412_P<34>_UNCONNECTED , \NLW_blk00000412_P<33>_UNCONNECTED ,
\NLW_blk00000412_P<32>_UNCONNECTED , \NLW_blk00000412_P<31>_UNCONNECTED , \NLW_blk00000412_P<30>_UNCONNECTED , \NLW_blk00000412_P<29>_UNCONNECTED ,
\NLW_blk00000412_P<28>_UNCONNECTED , \NLW_blk00000412_P<27>_UNCONNECTED , \NLW_blk00000412_P<26>_UNCONNECTED , \NLW_blk00000412_P<25>_UNCONNECTED ,
\NLW_blk00000412_P<24>_UNCONNECTED , \NLW_blk00000412_P<23>_UNCONNECTED , \NLW_blk00000412_P<22>_UNCONNECTED , \NLW_blk00000412_P<21>_UNCONNECTED ,
\NLW_blk00000412_P<20>_UNCONNECTED , \NLW_blk00000412_P<19>_UNCONNECTED , \NLW_blk00000412_P<18>_UNCONNECTED , \NLW_blk00000412_P<17>_UNCONNECTED ,
\NLW_blk00000412_P<16>_UNCONNECTED , \NLW_blk00000412_P<15>_UNCONNECTED , \NLW_blk00000412_P<14>_UNCONNECTED , \NLW_blk00000412_P<13>_UNCONNECTED ,
\NLW_blk00000412_P<12>_UNCONNECTED , \NLW_blk00000412_P<11>_UNCONNECTED , \NLW_blk00000412_P<10>_UNCONNECTED , \NLW_blk00000412_P<9>_UNCONNECTED ,
\NLW_blk00000412_P<8>_UNCONNECTED , \NLW_blk00000412_P<7>_UNCONNECTED , \NLW_blk00000412_P<6>_UNCONNECTED , \NLW_blk00000412_P<5>_UNCONNECTED ,
\NLW_blk00000412_P<4>_UNCONNECTED , \NLW_blk00000412_P<3>_UNCONNECTED , \NLW_blk00000412_P<2>_UNCONNECTED , \NLW_blk00000412_P<1>_UNCONNECTED ,
\NLW_blk00000412_P<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "CASCADE" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000413 (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000413_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(sig00000461),
.MULTSIGNOUT(NLW_blk00000413_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000413_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000413_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000413_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000413_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000001, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig00000395, sig00000394, sig00000393, sig00000392, sig00000391, sig00000390, sig0000038f, sig0000038e, sig0000038d, sig0000038c,
sig0000038b, sig0000038a, sig00000389, sig00000388, sig00000387, sig00000386, sig00000385, sig00000384, sig00000383, sig00000382, sig00000381,
sig00000380, sig0000037f, sig0000037e, sig0000037d, sig0000037c, sig0000037b, sig0000037a, sig00000379, sig00000378, sig00000377, sig00000376,
sig00000375, sig00000374, sig00000373, sig00000372, sig00000371, sig00000370, sig0000036f, sig0000036e, sig0000036d, sig0000036c, sig0000036b,
sig0000036a, sig00000369, sig00000368, sig00000367, sig00000366}),
.BCIN({sig000003a7, sig000003a6, sig000003a5, sig000003a4, sig000003a3, sig000003a2, sig000003a1, sig000003a0, sig0000039f, sig0000039e,
sig0000039d, sig0000039c, sig0000039b, sig0000039a, sig00000399, sig00000398, sig00000397, sig00000396}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000191, sig00000192, sig00000193, sig00000194, sig00000195, sig00000196, sig00000197, sig00000198, sig00000199,
sig0000019a, sig0000019b, sig0000019c, sig0000019d, sig0000019e, sig0000019f, sig000001a0, sig000001a1}),
.PCOUT({sig00000363, sig00000362, sig00000361, sig00000360, sig0000035f, sig0000035e, sig0000035d, sig0000035c, sig0000035b, sig0000035a,
sig00000359, sig00000358, sig00000357, sig00000356, sig00000355, sig00000354, sig00000353, sig00000352, sig00000351, sig00000350, sig0000034f,
sig0000034e, sig0000034d, sig0000034c, sig0000034b, sig0000034a, sig00000349, sig00000348, sig00000347, sig00000346, sig00000345, sig00000344,
sig00000343, sig00000342, sig00000341, sig00000340, sig0000033f, sig0000033e, sig0000033d, sig0000033c, sig0000033b, sig0000033a, sig00000339,
sig00000338, sig00000337, sig00000336, sig00000335, sig00000334}),
.ACOUT({\NLW_blk00000413_ACOUT<29>_UNCONNECTED , \NLW_blk00000413_ACOUT<28>_UNCONNECTED , \NLW_blk00000413_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<26>_UNCONNECTED , \NLW_blk00000413_ACOUT<25>_UNCONNECTED , \NLW_blk00000413_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<23>_UNCONNECTED , \NLW_blk00000413_ACOUT<22>_UNCONNECTED , \NLW_blk00000413_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<20>_UNCONNECTED , \NLW_blk00000413_ACOUT<19>_UNCONNECTED , \NLW_blk00000413_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<17>_UNCONNECTED , \NLW_blk00000413_ACOUT<16>_UNCONNECTED , \NLW_blk00000413_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<14>_UNCONNECTED , \NLW_blk00000413_ACOUT<13>_UNCONNECTED , \NLW_blk00000413_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<11>_UNCONNECTED , \NLW_blk00000413_ACOUT<10>_UNCONNECTED , \NLW_blk00000413_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<8>_UNCONNECTED , \NLW_blk00000413_ACOUT<7>_UNCONNECTED , \NLW_blk00000413_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<5>_UNCONNECTED , \NLW_blk00000413_ACOUT<4>_UNCONNECTED , \NLW_blk00000413_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000413_ACOUT<2>_UNCONNECTED , \NLW_blk00000413_ACOUT<1>_UNCONNECTED , \NLW_blk00000413_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000413_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000413_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000413_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000413_CARRYOUT<0>_UNCONNECTED }),
.B({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk00000413_BCOUT<17>_UNCONNECTED , \NLW_blk00000413_BCOUT<16>_UNCONNECTED , \NLW_blk00000413_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000413_BCOUT<14>_UNCONNECTED , \NLW_blk00000413_BCOUT<13>_UNCONNECTED , \NLW_blk00000413_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000413_BCOUT<11>_UNCONNECTED , \NLW_blk00000413_BCOUT<10>_UNCONNECTED , \NLW_blk00000413_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000413_BCOUT<8>_UNCONNECTED , \NLW_blk00000413_BCOUT<7>_UNCONNECTED , \NLW_blk00000413_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000413_BCOUT<5>_UNCONNECTED , \NLW_blk00000413_BCOUT<4>_UNCONNECTED , \NLW_blk00000413_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000413_BCOUT<2>_UNCONNECTED , \NLW_blk00000413_BCOUT<1>_UNCONNECTED , \NLW_blk00000413_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000413_P<47>_UNCONNECTED , \NLW_blk00000413_P<46>_UNCONNECTED , \NLW_blk00000413_P<45>_UNCONNECTED ,
\NLW_blk00000413_P<44>_UNCONNECTED , \NLW_blk00000413_P<43>_UNCONNECTED , \NLW_blk00000413_P<42>_UNCONNECTED , \NLW_blk00000413_P<41>_UNCONNECTED ,
\NLW_blk00000413_P<40>_UNCONNECTED , \NLW_blk00000413_P<39>_UNCONNECTED , \NLW_blk00000413_P<38>_UNCONNECTED , \NLW_blk00000413_P<37>_UNCONNECTED ,
\NLW_blk00000413_P<36>_UNCONNECTED , \NLW_blk00000413_P<35>_UNCONNECTED , \NLW_blk00000413_P<34>_UNCONNECTED , \NLW_blk00000413_P<33>_UNCONNECTED ,
\NLW_blk00000413_P<32>_UNCONNECTED , \NLW_blk00000413_P<31>_UNCONNECTED , \NLW_blk00000413_P<30>_UNCONNECTED , \NLW_blk00000413_P<29>_UNCONNECTED ,
\NLW_blk00000413_P<28>_UNCONNECTED , \NLW_blk00000413_P<27>_UNCONNECTED , \NLW_blk00000413_P<26>_UNCONNECTED , \NLW_blk00000413_P<25>_UNCONNECTED ,
\NLW_blk00000413_P<24>_UNCONNECTED , \NLW_blk00000413_P<23>_UNCONNECTED , \NLW_blk00000413_P<22>_UNCONNECTED , \NLW_blk00000413_P<21>_UNCONNECTED ,
\NLW_blk00000413_P<20>_UNCONNECTED , \NLW_blk00000413_P<19>_UNCONNECTED , \NLW_blk00000413_P<18>_UNCONNECTED , \NLW_blk00000413_P<17>_UNCONNECTED ,
\NLW_blk00000413_P<16>_UNCONNECTED , \NLW_blk00000413_P<15>_UNCONNECTED , \NLW_blk00000413_P<14>_UNCONNECTED , \NLW_blk00000413_P<13>_UNCONNECTED ,
\NLW_blk00000413_P<12>_UNCONNECTED , \NLW_blk00000413_P<11>_UNCONNECTED , \NLW_blk00000413_P<10>_UNCONNECTED , \NLW_blk00000413_P<9>_UNCONNECTED ,
\NLW_blk00000413_P<8>_UNCONNECTED , \NLW_blk00000413_P<7>_UNCONNECTED , \NLW_blk00000413_P<6>_UNCONNECTED , \NLW_blk00000413_P<5>_UNCONNECTED ,
\NLW_blk00000413_P<4>_UNCONNECTED , \NLW_blk00000413_P<3>_UNCONNECTED , \NLW_blk00000413_P<2>_UNCONNECTED , \NLW_blk00000413_P<1>_UNCONNECTED ,
\NLW_blk00000413_P<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 2 ),
.BREG ( 2 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'hFFFFFFFE0000 ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000414 (
.CEM(ce),
.PATTERNDETECT(sig00000365),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000414_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(ce),
.MULTSIGNOUT(NLW_blk00000414_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000414_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000414_UNDERFLOW_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000414_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000461, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig000003d7, sig000003d6, sig000003d5, sig000003d4, sig000003d3, sig000003d2, sig000003d1, sig000003d0, sig000003cf, sig000003ce,
sig000003cd, sig000003cc, sig000003cb, sig000003ca, sig000003c9, sig000003c8, sig000003c7, sig000003c6, sig000003c5, sig000003c4, sig000003c3,
sig000003c2, sig000003c1, sig000003c0, sig000003bf, sig000003be, sig000003bd, sig000003bc, sig000003bb, sig000003ba, sig000003b9, sig000003b8,
sig000003b7, sig000003b6, sig000003b5, sig000003b4, sig000003b3, sig000003b2, sig000003b1, sig000003b0, sig000003af, sig000003ae, sig000003ad,
sig000003ac, sig000003ab, sig000003aa, sig000003a9, sig000003a8}),
.B({sig00000461, sig000001b4, sig000001b5, sig000001b6, sig000001b7, sig000001b8, sig000001b9, sig000001ba, sig000001bb, sig000001bc, sig000001bd
, sig000001be, sig000001bf, sig000001c0, sig000001c1, sig000001c2, sig000001c3, sig000001c4}),
.BCOUT({sig000003a7, sig000003a6, sig000003a5, sig000003a4, sig000003a3, sig000003a2, sig000003a1, sig000003a0, sig0000039f, sig0000039e,
sig0000039d, sig0000039c, sig0000039b, sig0000039a, sig00000399, sig00000398, sig00000397, sig00000396}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig000001a3, sig000001a4, sig000001a5, sig000001a6, sig000001a7, sig000001a8, sig000001a9, sig000001aa, sig000001ab,
sig000001ac, sig000001ad, sig000001ae, sig000001af, sig000001b0, sig000001b1, sig000001b2, sig000001b3}),
.PCOUT({sig00000395, sig00000394, sig00000393, sig00000392, sig00000391, sig00000390, sig0000038f, sig0000038e, sig0000038d, sig0000038c,
sig0000038b, sig0000038a, sig00000389, sig00000388, sig00000387, sig00000386, sig00000385, sig00000384, sig00000383, sig00000382, sig00000381,
sig00000380, sig0000037f, sig0000037e, sig0000037d, sig0000037c, sig0000037b, sig0000037a, sig00000379, sig00000378, sig00000377, sig00000376,
sig00000375, sig00000374, sig00000373, sig00000372, sig00000371, sig00000370, sig0000036f, sig0000036e, sig0000036d, sig0000036c, sig0000036b,
sig0000036a, sig00000369, sig00000368, sig00000367, sig00000366}),
.ACOUT({\NLW_blk00000414_ACOUT<29>_UNCONNECTED , \NLW_blk00000414_ACOUT<28>_UNCONNECTED , \NLW_blk00000414_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<26>_UNCONNECTED , \NLW_blk00000414_ACOUT<25>_UNCONNECTED , \NLW_blk00000414_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<23>_UNCONNECTED , \NLW_blk00000414_ACOUT<22>_UNCONNECTED , \NLW_blk00000414_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<20>_UNCONNECTED , \NLW_blk00000414_ACOUT<19>_UNCONNECTED , \NLW_blk00000414_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<17>_UNCONNECTED , \NLW_blk00000414_ACOUT<16>_UNCONNECTED , \NLW_blk00000414_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<14>_UNCONNECTED , \NLW_blk00000414_ACOUT<13>_UNCONNECTED , \NLW_blk00000414_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<11>_UNCONNECTED , \NLW_blk00000414_ACOUT<10>_UNCONNECTED , \NLW_blk00000414_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<8>_UNCONNECTED , \NLW_blk00000414_ACOUT<7>_UNCONNECTED , \NLW_blk00000414_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<5>_UNCONNECTED , \NLW_blk00000414_ACOUT<4>_UNCONNECTED , \NLW_blk00000414_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000414_ACOUT<2>_UNCONNECTED , \NLW_blk00000414_ACOUT<1>_UNCONNECTED , \NLW_blk00000414_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000414_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000414_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000414_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000414_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.P({\NLW_blk00000414_P<47>_UNCONNECTED , \NLW_blk00000414_P<46>_UNCONNECTED , \NLW_blk00000414_P<45>_UNCONNECTED ,
\NLW_blk00000414_P<44>_UNCONNECTED , \NLW_blk00000414_P<43>_UNCONNECTED , \NLW_blk00000414_P<42>_UNCONNECTED , \NLW_blk00000414_P<41>_UNCONNECTED ,
\NLW_blk00000414_P<40>_UNCONNECTED , \NLW_blk00000414_P<39>_UNCONNECTED , \NLW_blk00000414_P<38>_UNCONNECTED , \NLW_blk00000414_P<37>_UNCONNECTED ,
\NLW_blk00000414_P<36>_UNCONNECTED , \NLW_blk00000414_P<35>_UNCONNECTED , \NLW_blk00000414_P<34>_UNCONNECTED , \NLW_blk00000414_P<33>_UNCONNECTED ,
\NLW_blk00000414_P<32>_UNCONNECTED , \NLW_blk00000414_P<31>_UNCONNECTED , \NLW_blk00000414_P<30>_UNCONNECTED , \NLW_blk00000414_P<29>_UNCONNECTED ,
\NLW_blk00000414_P<28>_UNCONNECTED , \NLW_blk00000414_P<27>_UNCONNECTED , \NLW_blk00000414_P<26>_UNCONNECTED , \NLW_blk00000414_P<25>_UNCONNECTED ,
\NLW_blk00000414_P<24>_UNCONNECTED , \NLW_blk00000414_P<23>_UNCONNECTED , \NLW_blk00000414_P<22>_UNCONNECTED , \NLW_blk00000414_P<21>_UNCONNECTED ,
\NLW_blk00000414_P<20>_UNCONNECTED , \NLW_blk00000414_P<19>_UNCONNECTED , \NLW_blk00000414_P<18>_UNCONNECTED , \NLW_blk00000414_P<17>_UNCONNECTED ,
\NLW_blk00000414_P<16>_UNCONNECTED , \NLW_blk00000414_P<15>_UNCONNECTED , \NLW_blk00000414_P<14>_UNCONNECTED , \NLW_blk00000414_P<13>_UNCONNECTED ,
\NLW_blk00000414_P<12>_UNCONNECTED , \NLW_blk00000414_P<11>_UNCONNECTED , \NLW_blk00000414_P<10>_UNCONNECTED , \NLW_blk00000414_P<9>_UNCONNECTED ,
\NLW_blk00000414_P<8>_UNCONNECTED , \NLW_blk00000414_P<7>_UNCONNECTED , \NLW_blk00000414_P<6>_UNCONNECTED , \NLW_blk00000414_P<5>_UNCONNECTED ,
\NLW_blk00000414_P<4>_UNCONNECTED , \NLW_blk00000414_P<3>_UNCONNECTED , \NLW_blk00000414_P<2>_UNCONNECTED , \NLW_blk00000414_P<1>_UNCONNECTED ,
\NLW_blk00000414_P<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 2 ),
.ALUMODEREG ( 0 ),
.AREG ( 2 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "CASCADE" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'h3FFFFFFFFFFF ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "NO_PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000415 (
.CEM(ce),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000415_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(sig00000461),
.MULTSIGNOUT(NLW_blk00000415_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000415_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000415_UNDERFLOW_UNCONNECTED),
.PATTERNDETECT(NLW_blk00000415_PATTERNDETECT_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(ce),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000415_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000001, sig00000461, sig00000001, sig00000461, sig00000001, sig00000461, sig00000001}),
.PCIN({sig00000409, sig00000408, sig00000407, sig00000406, sig00000405, sig00000404, sig00000403, sig00000402, sig00000401, sig00000400,
sig000003ff, sig000003fe, sig000003fd, sig000003fc, sig000003fb, sig000003fa, sig000003f9, sig000003f8, sig000003f7, sig000003f6, sig000003f5,
sig000003f4, sig000003f3, sig000003f2, sig000003f1, sig000003f0, sig000003ef, sig000003ee, sig000003ed, sig000003ec, sig000003eb, sig000003ea,
sig000003e9, sig000003e8, sig000003e7, sig000003e6, sig000003e5, sig000003e4, sig000003e3, sig000003e2, sig000003e1, sig000003e0, sig000003df,
sig000003de, sig000003dd, sig000003dc, sig000003db, sig000003da}),
.BCIN({sig0000041b, sig0000041a, sig00000419, sig00000418, sig00000417, sig00000416, sig00000415, sig00000414, sig00000413, sig00000412,
sig00000411, sig00000410, sig0000040f, sig0000040e, sig0000040d, sig0000040c, sig0000040b, sig0000040a}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, a[33], a[32], a[31], a[30], a[29], a[28], a[27], a[26], a[25], a[24], a[23], a[22], a[21], a[20], a[19], a[18], a[17]}),
.PCOUT({sig000003d7, sig000003d6, sig000003d5, sig000003d4, sig000003d3, sig000003d2, sig000003d1, sig000003d0, sig000003cf, sig000003ce,
sig000003cd, sig000003cc, sig000003cb, sig000003ca, sig000003c9, sig000003c8, sig000003c7, sig000003c6, sig000003c5, sig000003c4, sig000003c3,
sig000003c2, sig000003c1, sig000003c0, sig000003bf, sig000003be, sig000003bd, sig000003bc, sig000003bb, sig000003ba, sig000003b9, sig000003b8,
sig000003b7, sig000003b6, sig000003b5, sig000003b4, sig000003b3, sig000003b2, sig000003b1, sig000003b0, sig000003af, sig000003ae, sig000003ad,
sig000003ac, sig000003ab, sig000003aa, sig000003a9, sig000003a8}),
.ACOUT({\NLW_blk00000415_ACOUT<29>_UNCONNECTED , \NLW_blk00000415_ACOUT<28>_UNCONNECTED , \NLW_blk00000415_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<26>_UNCONNECTED , \NLW_blk00000415_ACOUT<25>_UNCONNECTED , \NLW_blk00000415_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<23>_UNCONNECTED , \NLW_blk00000415_ACOUT<22>_UNCONNECTED , \NLW_blk00000415_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<20>_UNCONNECTED , \NLW_blk00000415_ACOUT<19>_UNCONNECTED , \NLW_blk00000415_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<17>_UNCONNECTED , \NLW_blk00000415_ACOUT<16>_UNCONNECTED , \NLW_blk00000415_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<14>_UNCONNECTED , \NLW_blk00000415_ACOUT<13>_UNCONNECTED , \NLW_blk00000415_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<11>_UNCONNECTED , \NLW_blk00000415_ACOUT<10>_UNCONNECTED , \NLW_blk00000415_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<8>_UNCONNECTED , \NLW_blk00000415_ACOUT<7>_UNCONNECTED , \NLW_blk00000415_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<5>_UNCONNECTED , \NLW_blk00000415_ACOUT<4>_UNCONNECTED , \NLW_blk00000415_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000415_ACOUT<2>_UNCONNECTED , \NLW_blk00000415_ACOUT<1>_UNCONNECTED , \NLW_blk00000415_ACOUT<0>_UNCONNECTED }),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000415_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000415_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000415_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000415_CARRYOUT<0>_UNCONNECTED }),
.B({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.BCOUT({\NLW_blk00000415_BCOUT<17>_UNCONNECTED , \NLW_blk00000415_BCOUT<16>_UNCONNECTED , \NLW_blk00000415_BCOUT<15>_UNCONNECTED ,
\NLW_blk00000415_BCOUT<14>_UNCONNECTED , \NLW_blk00000415_BCOUT<13>_UNCONNECTED , \NLW_blk00000415_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000415_BCOUT<11>_UNCONNECTED , \NLW_blk00000415_BCOUT<10>_UNCONNECTED , \NLW_blk00000415_BCOUT<9>_UNCONNECTED ,
\NLW_blk00000415_BCOUT<8>_UNCONNECTED , \NLW_blk00000415_BCOUT<7>_UNCONNECTED , \NLW_blk00000415_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000415_BCOUT<5>_UNCONNECTED , \NLW_blk00000415_BCOUT<4>_UNCONNECTED , \NLW_blk00000415_BCOUT<3>_UNCONNECTED ,
\NLW_blk00000415_BCOUT<2>_UNCONNECTED , \NLW_blk00000415_BCOUT<1>_UNCONNECTED , \NLW_blk00000415_BCOUT<0>_UNCONNECTED }),
.P({\NLW_blk00000415_P<47>_UNCONNECTED , \NLW_blk00000415_P<46>_UNCONNECTED , \NLW_blk00000415_P<45>_UNCONNECTED ,
\NLW_blk00000415_P<44>_UNCONNECTED , \NLW_blk00000415_P<43>_UNCONNECTED , \NLW_blk00000415_P<42>_UNCONNECTED , \NLW_blk00000415_P<41>_UNCONNECTED ,
\NLW_blk00000415_P<40>_UNCONNECTED , \NLW_blk00000415_P<39>_UNCONNECTED , \NLW_blk00000415_P<38>_UNCONNECTED , \NLW_blk00000415_P<37>_UNCONNECTED ,
\NLW_blk00000415_P<36>_UNCONNECTED , \NLW_blk00000415_P<35>_UNCONNECTED , \NLW_blk00000415_P<34>_UNCONNECTED , \NLW_blk00000415_P<33>_UNCONNECTED ,
\NLW_blk00000415_P<32>_UNCONNECTED , \NLW_blk00000415_P<31>_UNCONNECTED , \NLW_blk00000415_P<30>_UNCONNECTED , \NLW_blk00000415_P<29>_UNCONNECTED ,
\NLW_blk00000415_P<28>_UNCONNECTED , \NLW_blk00000415_P<27>_UNCONNECTED , \NLW_blk00000415_P<26>_UNCONNECTED , \NLW_blk00000415_P<25>_UNCONNECTED ,
\NLW_blk00000415_P<24>_UNCONNECTED , \NLW_blk00000415_P<23>_UNCONNECTED , \NLW_blk00000415_P<22>_UNCONNECTED , \NLW_blk00000415_P<21>_UNCONNECTED ,
\NLW_blk00000415_P<20>_UNCONNECTED , \NLW_blk00000415_P<19>_UNCONNECTED , \NLW_blk00000415_P<18>_UNCONNECTED , \NLW_blk00000415_P<17>_UNCONNECTED ,
\NLW_blk00000415_P<16>_UNCONNECTED , \NLW_blk00000415_P<15>_UNCONNECTED , \NLW_blk00000415_P<14>_UNCONNECTED , \NLW_blk00000415_P<13>_UNCONNECTED ,
\NLW_blk00000415_P<12>_UNCONNECTED , \NLW_blk00000415_P<11>_UNCONNECTED , \NLW_blk00000415_P<10>_UNCONNECTED , \NLW_blk00000415_P<9>_UNCONNECTED ,
\NLW_blk00000415_P<8>_UNCONNECTED , \NLW_blk00000415_P<7>_UNCONNECTED , \NLW_blk00000415_P<6>_UNCONNECTED , \NLW_blk00000415_P<5>_UNCONNECTED ,
\NLW_blk00000415_P<4>_UNCONNECTED , \NLW_blk00000415_P<3>_UNCONNECTED , \NLW_blk00000415_P<2>_UNCONNECTED , \NLW_blk00000415_P<1>_UNCONNECTED ,
\NLW_blk00000415_P<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
DSP48E #(
.ACASCREG ( 1 ),
.ALUMODEREG ( 0 ),
.AREG ( 1 ),
.AUTORESET_PATTERN_DETECT ( "FALSE" ),
.AUTORESET_PATTERN_DETECT_OPTINV ( "MATCH" ),
.A_INPUT ( "DIRECT" ),
.BCASCREG ( 1 ),
.BREG ( 1 ),
.B_INPUT ( "DIRECT" ),
.CARRYINREG ( 0 ),
.CARRYINSELREG ( 0 ),
.CREG ( 0 ),
.MASK ( 48'hFFFFFFFE0000 ),
.MREG ( 1 ),
.MULTCARRYINREG ( 0 ),
.OPMODEREG ( 0 ),
.PATTERN ( 48'h000000000000 ),
.PREG ( 1 ),
.SEL_MASK ( "MASK" ),
.SEL_PATTERN ( "PATTERN" ),
.SEL_ROUNDING_MASK ( "SEL_MASK" ),
.SIM_MODE ( "SAFE" ),
.USE_MULT ( "MULT_S" ),
.USE_PATTERN_DETECT ( "PATDET" ),
.USE_SIMD ( "ONE48" ))
blk00000416 (
.CEM(ce),
.PATTERNDETECT(sig000003d9),
.CLK(clk),
.PATTERNBDETECT(NLW_blk00000416_PATTERNBDETECT_UNCONNECTED),
.RSTC(sig00000461),
.CEB1(sig00000461),
.MULTSIGNOUT(NLW_blk00000416_MULTSIGNOUT_UNCONNECTED),
.CEC(sig00000461),
.RSTM(sig00000461),
.MULTSIGNIN(sig00000461),
.CEB2(ce),
.RSTCTRL(sig00000461),
.CEP(ce),
.CARRYCASCOUT(NLW_blk00000416_CARRYCASCOUT_UNCONNECTED),
.RSTA(sig00000461),
.CECARRYIN(sig00000461),
.UNDERFLOW(NLW_blk00000416_UNDERFLOW_UNCONNECTED),
.RSTALUMODE(sig00000461),
.RSTALLCARRYIN(sig00000461),
.CEALUMODE(sig00000461),
.CEA2(ce),
.CEA1(sig00000461),
.RSTB(sig00000461),
.CEMULTCARRYIN(sig00000461),
.OVERFLOW(NLW_blk00000416_OVERFLOW_UNCONNECTED),
.CECTRL(sig00000461),
.CARRYIN(sig00000461),
.CARRYCASCIN(sig00000461),
.RSTP(sig00000461),
.CARRYINSEL({sig00000461, sig00000461, sig00000461}),
.OPMODE({sig00000461, sig00000461, sig00000461, sig00000461, sig00000001, sig00000461, sig00000001}),
.B({sig00000461, b[16], b[15], b[14], b[13], b[12], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.BCOUT({sig0000041b, sig0000041a, sig00000419, sig00000418, sig00000417, sig00000416, sig00000415, sig00000414, sig00000413, sig00000412,
sig00000411, sig00000410, sig0000040f, sig0000040e, sig0000040d, sig0000040c, sig0000040b, sig0000040a}),
.A({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, a[16], a[15], a[14], a[13], a[12], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.PCOUT({sig00000409, sig00000408, sig00000407, sig00000406, sig00000405, sig00000404, sig00000403, sig00000402, sig00000401, sig00000400,
sig000003ff, sig000003fe, sig000003fd, sig000003fc, sig000003fb, sig000003fa, sig000003f9, sig000003f8, sig000003f7, sig000003f6, sig000003f5,
sig000003f4, sig000003f3, sig000003f2, sig000003f1, sig000003f0, sig000003ef, sig000003ee, sig000003ed, sig000003ec, sig000003eb, sig000003ea,
sig000003e9, sig000003e8, sig000003e7, sig000003e6, sig000003e5, sig000003e4, sig000003e3, sig000003e2, sig000003e1, sig000003e0, sig000003df,
sig000003de, sig000003dd, sig000003dc, sig000003db, sig000003da}),
.ACOUT({\NLW_blk00000416_ACOUT<29>_UNCONNECTED , \NLW_blk00000416_ACOUT<28>_UNCONNECTED , \NLW_blk00000416_ACOUT<27>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<26>_UNCONNECTED , \NLW_blk00000416_ACOUT<25>_UNCONNECTED , \NLW_blk00000416_ACOUT<24>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<23>_UNCONNECTED , \NLW_blk00000416_ACOUT<22>_UNCONNECTED , \NLW_blk00000416_ACOUT<21>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<20>_UNCONNECTED , \NLW_blk00000416_ACOUT<19>_UNCONNECTED , \NLW_blk00000416_ACOUT<18>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<17>_UNCONNECTED , \NLW_blk00000416_ACOUT<16>_UNCONNECTED , \NLW_blk00000416_ACOUT<15>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<14>_UNCONNECTED , \NLW_blk00000416_ACOUT<13>_UNCONNECTED , \NLW_blk00000416_ACOUT<12>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<11>_UNCONNECTED , \NLW_blk00000416_ACOUT<10>_UNCONNECTED , \NLW_blk00000416_ACOUT<9>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<8>_UNCONNECTED , \NLW_blk00000416_ACOUT<7>_UNCONNECTED , \NLW_blk00000416_ACOUT<6>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<5>_UNCONNECTED , \NLW_blk00000416_ACOUT<4>_UNCONNECTED , \NLW_blk00000416_ACOUT<3>_UNCONNECTED ,
\NLW_blk00000416_ACOUT<2>_UNCONNECTED , \NLW_blk00000416_ACOUT<1>_UNCONNECTED , \NLW_blk00000416_ACOUT<0>_UNCONNECTED }),
.PCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.ALUMODE({sig00000461, sig00000461, sig00000461, sig00000461}),
.C({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461
, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461}),
.CARRYOUT({\NLW_blk00000416_CARRYOUT<3>_UNCONNECTED , \NLW_blk00000416_CARRYOUT<2>_UNCONNECTED , \NLW_blk00000416_CARRYOUT<1>_UNCONNECTED ,
\NLW_blk00000416_CARRYOUT<0>_UNCONNECTED }),
.BCIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461}),
.P({\NLW_blk00000416_P<47>_UNCONNECTED , \NLW_blk00000416_P<46>_UNCONNECTED , \NLW_blk00000416_P<45>_UNCONNECTED ,
\NLW_blk00000416_P<44>_UNCONNECTED , \NLW_blk00000416_P<43>_UNCONNECTED , \NLW_blk00000416_P<42>_UNCONNECTED , \NLW_blk00000416_P<41>_UNCONNECTED ,
\NLW_blk00000416_P<40>_UNCONNECTED , \NLW_blk00000416_P<39>_UNCONNECTED , \NLW_blk00000416_P<38>_UNCONNECTED , \NLW_blk00000416_P<37>_UNCONNECTED ,
\NLW_blk00000416_P<36>_UNCONNECTED , \NLW_blk00000416_P<35>_UNCONNECTED , \NLW_blk00000416_P<34>_UNCONNECTED , \NLW_blk00000416_P<33>_UNCONNECTED ,
\NLW_blk00000416_P<32>_UNCONNECTED , \NLW_blk00000416_P<31>_UNCONNECTED , \NLW_blk00000416_P<30>_UNCONNECTED , \NLW_blk00000416_P<29>_UNCONNECTED ,
\NLW_blk00000416_P<28>_UNCONNECTED , \NLW_blk00000416_P<27>_UNCONNECTED , \NLW_blk00000416_P<26>_UNCONNECTED , \NLW_blk00000416_P<25>_UNCONNECTED ,
\NLW_blk00000416_P<24>_UNCONNECTED , \NLW_blk00000416_P<23>_UNCONNECTED , \NLW_blk00000416_P<22>_UNCONNECTED , \NLW_blk00000416_P<21>_UNCONNECTED ,
\NLW_blk00000416_P<20>_UNCONNECTED , \NLW_blk00000416_P<19>_UNCONNECTED , \NLW_blk00000416_P<18>_UNCONNECTED , \NLW_blk00000416_P<17>_UNCONNECTED ,
\NLW_blk00000416_P<16>_UNCONNECTED , \NLW_blk00000416_P<15>_UNCONNECTED , \NLW_blk00000416_P<14>_UNCONNECTED , \NLW_blk00000416_P<13>_UNCONNECTED ,
\NLW_blk00000416_P<12>_UNCONNECTED , \NLW_blk00000416_P<11>_UNCONNECTED , \NLW_blk00000416_P<10>_UNCONNECTED , \NLW_blk00000416_P<9>_UNCONNECTED ,
\NLW_blk00000416_P<8>_UNCONNECTED , \NLW_blk00000416_P<7>_UNCONNECTED , \NLW_blk00000416_P<6>_UNCONNECTED , \NLW_blk00000416_P<5>_UNCONNECTED ,
\NLW_blk00000416_P<4>_UNCONNECTED , \NLW_blk00000416_P<3>_UNCONNECTED , \NLW_blk00000416_P<2>_UNCONNECTED , \NLW_blk00000416_P<1>_UNCONNECTED ,
\NLW_blk00000416_P<0>_UNCONNECTED }),
.ACIN({sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461,
sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461, sig00000461})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: lsu_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////;
// lsu_mon.vpal
//
// Description: LSU Monitor for monitoring some coverage conditions
// as well as some checkers. Run pal to get .v
// like pal -r -o lsu_mon.v lsu_mon.vpal
////////////////////////////////////////////////////////
`include "cross_module.h"
`include "sys.h"
`include "iop.h"
module lsu_mon ( clk, rst_l);
input clk; // the cpu clock
input rst_l; // reset (active low).
reg lsu_mon_msg;
initial
begin
if( $test$plusargs("lsu_mon_msg") )
lsu_mon_msg = 1'b1;
else
lsu_mon_msg= 1'b0;
end // initial begin
//============================================================================================
`ifdef RTL_SPARC0
wire spc0_dva_ren = `TOP_DESIGN.sparc0.lsu.ifu_lsu_ld_inst_e;
wire spc0_dva_wen = `TOP_DESIGN.sparc0.lsu.lsu_dtagv_wr_vld_e;
wire spc0_dva_din = `TOP_DESIGN.sparc0.lsu.dva_din_e;
wire [3:0] spc0_dva_dout = `TOP_DESIGN.sparc0.lsu.dva_vld_m[3:0];
wire [6:0] spc0_dva_raddr = `TOP_DESIGN.sparc0.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc0_dva_waddr = `TOP_DESIGN.sparc0.lsu.dva_wr_adr_e[10:6];
wire spc0_dva_dtag_perror = `TOP_DESIGN.sparc0.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc0_dva_dcache_perror = `TOP_DESIGN.sparc0.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc0_dva_inv_perror = `TOP_DESIGN.sparc0.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc0_ld_miss = `TOP_DESIGN.sparc0.lsu.dctl.lsu_ld_miss_wb;
reg spc0_ld_miss_capture;
wire spc0_atomic_g = `TOP_DESIGN.sparc0.lsu.qctl1.atomic_g;
wire [1:0] spc0_atm_type0 = `TOP_DESIGN.sparc0.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc0_atm_type1 = `TOP_DESIGN.sparc0.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc0_atm_type2 = `TOP_DESIGN.sparc0.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc0_atm_type3 = `TOP_DESIGN.sparc0.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc0_dctl_lsu_way_hit = `TOP_DESIGN.sparc0.lsu.dctl.lsu_way_hit;
wire spc0_dctl_dcache_enable_g = `TOP_DESIGN.sparc0.lsu.dctl.dcache_enable_g;
wire spc0_dctl_ldxa_internal = `TOP_DESIGN.sparc0.lsu.dctl.ldxa_internal;
wire spc0_dctl_ldst_dbl_g = `TOP_DESIGN.sparc0.lsu.dctl.ldst_dbl_g;
wire spc0_dctl_atomic_g = `TOP_DESIGN.sparc0.lsu.dctl.atomic_g;
wire spc0_dctl_stb_cam_hit = `TOP_DESIGN.sparc0.lsu.dctl.stb_cam_hit;
wire spc0_dctl_endian_mispred_g = `TOP_DESIGN.sparc0.lsu.dctl.endian_mispred_g;
wire spc0_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc0.lsu.dctl.dcache_rd_parity_error;
wire spc0_dctl_dtag_perror_g = `TOP_DESIGN.sparc0.lsu.dctl.dtag_perror_g;
wire spc0_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc0.lsu.dctl.tte_data_perror_unc;
wire spc0_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc0.lsu.dctl.ld_inst_vld_g;
wire spc0_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc0.lsu.dctl.lsu_alt_space_g;
wire spc0_dctl_recognized_asi_g = `TOP_DESIGN.sparc0.lsu.dctl.recognized_asi_g;
wire spc0_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc0.lsu.dctl.ncache_asild_rq_g ;
wire spc0_dctl_bld_hit;
wire spc0_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc0_ixinv0 = `TOP_DESIGN.sparc0.lsu.qctl2.imiss0_inv_en;
wire spc0_ixinv1 = `TOP_DESIGN.sparc0.lsu.qctl2.imiss1_inv_en;
wire spc0_ixinv2 = `TOP_DESIGN.sparc0.lsu.qctl2.imiss2_inv_en;
wire spc0_ixinv3 = `TOP_DESIGN.sparc0.lsu.qctl2.imiss3_inv_en;
wire spc0_ifill = `TOP_DESIGN.sparc0.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc0_inv = `TOP_DESIGN.sparc0.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc0_inv_clr = `TOP_DESIGN.sparc0.lsu.qctl2.ifu_lsu_inv_clear;
wire spc0_ibuf_busy = `TOP_DESIGN.sparc0.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc0_l2 = `TOP_DESIGN.sparc0.lsu.dctl.l2fill_vld_g ;
wire spc0_unc = `TOP_DESIGN.sparc0.lsu.dctl.unc_err_trap_g ;
wire spc0_fpld = `TOP_DESIGN.sparc0.lsu.dctl.l2fill_fpld_g ;
wire spc0_fpldst = `TOP_DESIGN.sparc0.lsu.dctl.fp_ldst_g ;
wire spc0_unflush = `TOP_DESIGN.sparc0.lsu.dctl.ld_inst_vld_unflushed ;
wire spc0_ldw = `TOP_DESIGN.sparc0.lsu.dctl.lsu_inst_vld_w ;
wire spc0_byp = `TOP_DESIGN.sparc0.lsu.dctl.intld_byp_data_vld_m ;
wire spc0_flsh = `TOP_DESIGN.sparc0.lsu.lsu_exu_flush_pipe_w ;
wire spc0_chm = `TOP_DESIGN.sparc0.lsu.dctl.common_ldst_miss_w ;
wire spc0_ldxa = `TOP_DESIGN.sparc0.lsu.dctl.ldxa_internal ;
wire spc0_ato = `TOP_DESIGN.sparc0.lsu.dctl.atomic_g ;
wire spc0_pref = `TOP_DESIGN.sparc0.lsu.dctl.pref_inst_g ;
wire spc0_chit = `TOP_DESIGN.sparc0.lsu.dctl.stb_cam_hit ;
wire spc0_dcp = `TOP_DESIGN.sparc0.lsu.dctl.dcache_rd_parity_error ;
wire spc0_dtp = `TOP_DESIGN.sparc0.lsu.dctl.dtag_perror_g ;
//wire spc0_mpc = `TOP_DESIGN.sparc0.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc0_mpc = 1'b0;
wire spc0_mpu = `TOP_DESIGN.sparc0.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc0_exu_und;
reg [4:0] spc0_exu;
// excptn
wire spc0_exp_wtchpt_trp_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc0_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc0_exp_priv_violtn_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc0_exp_daccess_excptn_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc0_exp_daccess_prot_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc0_exp_priv_action_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc0_exp_spec_access_epage_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc0_exp_uncache_atomic_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc0_exp_illegal_asi_action_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc0_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc0_exp_asi_rd_unc = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc0_exp_tlb_data_ce = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc0_exp_asi_rd_unc = 1'b0;
wire spc0_exp_tlb_data_ce = 1'b0;
wire spc0_exp_tlb_data_ue = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc0_exp_tlb_tag_ue = `TOP_DESIGN.sparc0.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc0_exp_unc = `TOP_DESIGN.sparc0.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc0_exp_corr = `TOP_DESIGN.sparc0.lsu.excpctl.tte_data_perror_corr;
wire spc0_exp_corr = 1'b0;
wire [15:0] spc0_exp_und;
reg [4:0] spc0_exp;
// dctl cmplt
wire spc0_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc0.lsu.dctl.stxa_internal_d2;
wire spc0_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc0.lsu.dctl.lsu_l2fill_vld;
wire spc0_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc0.lsu.dctl.atomic_ld_squash_e;
wire spc0_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc0.lsu.qctl2.lsu_ignore_fill;
wire spc0_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc0.lsu.dctl.l2fill_fpld_e;
// wire spc0_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc0.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc0_dctl_fill_err_trap_e = `TOP_DESIGN.sparc0.lsu.dctl.fill_err_trap_e;
wire spc0_dctl_l2_corr_error_e = `TOP_DESIGN.sparc0.lsu.dctl.l2_corr_error_e;
wire [3:0] spc0_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc0.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc0_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc0.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc0_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc0.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc0_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc0.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc0_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc0.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc0_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc0.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc0_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc0_ldstcond_cmplt_d;
wire spc0_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc0.lsu.qctl1.ld_sec_hit_thrd0;
wire spc0_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_inst_vld_g;
wire spc0_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc0_ld0_pkt_vld_unmasked_d;
reg spc0_qctl1_ld_sec_hit_thrd0_w2;
wire spc0_dctl_thread0_w3 = `TOP_DESIGN.sparc0.lsu.dctl.thread0_w3;
wire spc0_dctl_dfill_thread0 = `TOP_DESIGN.sparc0.lsu.dctl.dfill_thread0;
wire spc0_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc0.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc0_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc0.lsu.dctl.diag_wr_cmplt0;
wire spc0_dctl_bsync0_reset = `TOP_DESIGN.sparc0.lsu.dctl.bsync0_reset;
wire spc0_dctl_late_cmplt0 = `TOP_DESIGN.sparc0.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc0_dctl_stxa_cmplt0;
wire spc0_dctl_l2fill_cmplt0;
wire spc0_dctl_atm_cmplt0;
wire spc0_dctl_fillerr0;
wire [4:0] spc0_cmplt0;
wire [5:0] spc0_dctl_ldst_cond_cmplt0;
reg [3:0] spc0_ldstcond_cmplt0;
reg [3:0] spc0_ldstcond_cmplt0_d;
wire spc0_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc0.lsu.qctl1.ld_sec_hit_thrd1;
wire spc0_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_inst_vld_g;
wire spc0_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc0_ld1_pkt_vld_unmasked_d;
reg spc0_qctl1_ld_sec_hit_thrd1_w2;
wire spc0_dctl_thread1_w3 = `TOP_DESIGN.sparc0.lsu.dctl.thread1_w3;
wire spc0_dctl_dfill_thread1 = `TOP_DESIGN.sparc0.lsu.dctl.dfill_thread1;
wire spc0_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc0.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc0_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc0.lsu.dctl.diag_wr_cmplt1;
wire spc0_dctl_bsync1_reset = `TOP_DESIGN.sparc0.lsu.dctl.bsync1_reset;
wire spc0_dctl_late_cmplt1 = `TOP_DESIGN.sparc0.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc0_dctl_stxa_cmplt1;
wire spc0_dctl_l2fill_cmplt1;
wire spc0_dctl_atm_cmplt1;
wire spc0_dctl_fillerr1;
wire [4:0] spc0_cmplt1;
wire [5:0] spc0_dctl_ldst_cond_cmplt1;
reg [3:0] spc0_ldstcond_cmplt1;
reg [3:0] spc0_ldstcond_cmplt1_d;
wire spc0_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc0.lsu.qctl1.ld_sec_hit_thrd2;
wire spc0_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_inst_vld_g;
wire spc0_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc0_ld2_pkt_vld_unmasked_d;
reg spc0_qctl1_ld_sec_hit_thrd2_w2;
wire spc0_dctl_thread2_w3 = `TOP_DESIGN.sparc0.lsu.dctl.thread2_w3;
wire spc0_dctl_dfill_thread2 = `TOP_DESIGN.sparc0.lsu.dctl.dfill_thread2;
wire spc0_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc0.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc0_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc0.lsu.dctl.diag_wr_cmplt2;
wire spc0_dctl_bsync2_reset = `TOP_DESIGN.sparc0.lsu.dctl.bsync2_reset;
wire spc0_dctl_late_cmplt2 = `TOP_DESIGN.sparc0.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc0_dctl_stxa_cmplt2;
wire spc0_dctl_l2fill_cmplt2;
wire spc0_dctl_atm_cmplt2;
wire spc0_dctl_fillerr2;
wire [4:0] spc0_cmplt2;
wire [5:0] spc0_dctl_ldst_cond_cmplt2;
reg [3:0] spc0_ldstcond_cmplt2;
reg [3:0] spc0_ldstcond_cmplt2_d;
wire spc0_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc0.lsu.qctl1.ld_sec_hit_thrd3;
wire spc0_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_inst_vld_g;
wire spc0_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc0_ld3_pkt_vld_unmasked_d;
reg spc0_qctl1_ld_sec_hit_thrd3_w2;
wire spc0_dctl_thread3_w3 = `TOP_DESIGN.sparc0.lsu.dctl.thread3_w3;
wire spc0_dctl_dfill_thread3 = `TOP_DESIGN.sparc0.lsu.dctl.dfill_thread3;
wire spc0_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc0.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc0_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc0.lsu.dctl.diag_wr_cmplt3;
wire spc0_dctl_bsync3_reset = `TOP_DESIGN.sparc0.lsu.dctl.bsync3_reset;
wire spc0_dctl_late_cmplt3 = `TOP_DESIGN.sparc0.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc0_dctl_stxa_cmplt3;
wire spc0_dctl_l2fill_cmplt3;
wire spc0_dctl_atm_cmplt3;
wire spc0_dctl_fillerr3;
wire [4:0] spc0_cmplt3;
wire [5:0] spc0_dctl_ldst_cond_cmplt3;
reg [3:0] spc0_ldstcond_cmplt3;
reg [3:0] spc0_ldstcond_cmplt3_d;
wire spc0_qctl1_bld_g = `TOP_DESIGN.sparc0.lsu.qctl1.bld_g;
wire spc0_qctl1_bld_reset = `TOP_DESIGN.sparc0.lsu.qctl1.bld_reset;
wire [1:0] spc0_qctl1_bld_cnt = `TOP_DESIGN.sparc0.lsu.qctl1.bld_cnt;
reg [9:0] spc0_bld0_full_cntr;
reg [1:0] spc0_bld0_full_d;
reg spc0_bld0_full_capture;
reg [9:0] spc0_bld1_full_cntr;
reg [1:0] spc0_bld1_full_d;
reg spc0_bld1_full_capture;
reg [9:0] spc0_bld2_full_cntr;
reg [1:0] spc0_bld2_full_d;
reg spc0_bld2_full_capture;
reg [9:0] spc0_bld3_full_cntr;
reg [1:0] spc0_bld3_full_d;
reg spc0_bld3_full_capture;
wire spc0_ipick = `TOP_DESIGN.sparc0.lsu.qctl1.imiss_pcx_rq_vld;
wire spc0_lpick = `TOP_DESIGN.sparc0.lsu.qctl1.ld_pcx_rq_all;
wire spc0_spick = `TOP_DESIGN.sparc0.lsu.qctl1.st_pcx_rq_all;
wire spc0_mpick = `TOP_DESIGN.sparc0.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc0_apick = `TOP_DESIGN.sparc0.lsu.qctl1.all_pcx_rq_pick;
wire spc0_msquash = `TOP_DESIGN.sparc0.lsu.qctl1.mcycle_squash_d1;
reg spc0_fpicko;
wire [3:0] spc0_fpick;
wire [39:0] spc0_imiss_pa = `TOP_DESIGN.sparc0.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc0_imiss_vld = `TOP_DESIGN.sparc0.lsu.qctl1.imiss_pcx_rq_vld;
reg spc0_imiss_vld_d;
wire [39:0] spc0_lmiss_pa0 = `TOP_DESIGN.sparc0.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc0_lmiss_vld0 = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_pcx_rq_vld;
wire spc0_ld_pkt_vld0 = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_pkt_vld;
wire spc0_st_pkt_vld0 = `TOP_DESIGN.sparc0.lsu.qctl1.st0_pkt_vld;
reg spc0_lmiss_eq0;
reg spc0_atm_imiss_eq0;
wire [39:0] spc0_lmiss_pa1 = `TOP_DESIGN.sparc0.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc0_lmiss_vld1 = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_pcx_rq_vld;
wire spc0_ld_pkt_vld1 = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_pkt_vld;
wire spc0_st_pkt_vld1 = `TOP_DESIGN.sparc0.lsu.qctl1.st1_pkt_vld;
reg spc0_lmiss_eq1;
reg spc0_atm_imiss_eq1;
wire [39:0] spc0_lmiss_pa2 = `TOP_DESIGN.sparc0.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc0_lmiss_vld2 = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_pcx_rq_vld;
wire spc0_ld_pkt_vld2 = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_pkt_vld;
wire spc0_st_pkt_vld2 = `TOP_DESIGN.sparc0.lsu.qctl1.st2_pkt_vld;
reg spc0_lmiss_eq2;
reg spc0_atm_imiss_eq2;
wire [39:0] spc0_lmiss_pa3 = `TOP_DESIGN.sparc0.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc0_lmiss_vld3 = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_pcx_rq_vld;
wire spc0_ld_pkt_vld3 = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_pkt_vld;
wire spc0_st_pkt_vld3 = `TOP_DESIGN.sparc0.lsu.qctl1.st3_pkt_vld;
reg spc0_lmiss_eq3;
reg spc0_atm_imiss_eq3;
wire [44:0] spc0_wdata_ramc = `TOP_DESIGN.sparc0.lsu.stb_cam.wdata_ramc;
wire spc0_wptr_vld = `TOP_DESIGN.sparc0.lsu.stb_cam.wptr_vld;
wire [75:0] spc0_wdata_ramd = {`TOP_DESIGN.sparc0.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc0.lsu.lsu_stb_st_data_g[63:0]};
wire spc0_stb_cam_hit = `TOP_DESIGN.sparc0.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc0_stb_cam_hit_ptr = `TOP_DESIGN.sparc0.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc0_stb_ld_full_raw = `TOP_DESIGN.sparc0.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc0_stb_ld_partial_raw = `TOP_DESIGN.sparc0.lsu.stb_ld_partial_raw[7:0];
wire spc0_stb_cam_mhit = `TOP_DESIGN.sparc0.lsu.stb_cam_mhit;
wire [3:0] spc0_dfq_vld_entries = `TOP_DESIGN.sparc0.lsu.qctl2.dfq_vld_entries;
wire spc0_dfq_full;
reg [9:0] spc0_dfq_full_cntr;
reg spc0_dfq_full_d;
reg spc0_dfq_full_capture;
reg [9:0] spc0_dfq_full_cntr1;
reg spc0_dfq_full_d1;
wire spc0_dfq_full1;
reg spc0_dfq_full_capture1;
reg [9:0] spc0_dfq_full_cntr2;
reg spc0_dfq_full_d2;
wire spc0_dfq_full2;
reg spc0_dfq_full_capture2;
reg [9:0] spc0_dfq_full_cntr3;
reg spc0_dfq_full_d3;
wire spc0_dfq_full3;
reg spc0_dfq_full_capture3;
reg [9:0] spc0_dfq_full_cntr4;
reg spc0_dfq_full_d4;
wire spc0_dfq_full4;
reg spc0_dfq_full_capture4;
reg [9:0] spc0_dfq_full_cntr5;
reg spc0_dfq_full_d5;
wire spc0_dfq_full5;
reg spc0_dfq_full_capture5;
reg [9:0] spc0_dfq_full_cntr6;
reg spc0_dfq_full_d6;
wire spc0_dfq_full6;
reg spc0_dfq_full_capture6;
reg [9:0] spc0_dfq_full_cntr7;
reg spc0_dfq_full_d7;
wire spc0_dfq_full7;
reg spc0_dfq_full_capture7;
wire spc0_dva_rdwrhit;
reg [9:0] spc0_dva_full_cntr;
reg spc0_dva_full_d;
reg spc0_dva_full_capture;
reg spc0_dva_inv;
reg spc0_dva_inv_d;
reg spc0_dva_vld;
reg spc0_dva_vld_d;
reg [9:0] spc0_dva_vfull_cntr;
reg spc0_dva_vfull_d;
reg spc0_dva_vfull_capture;
reg spc0_dva_collide;
reg spc0_dva_vld2lkup;
reg spc0_dva_invld2lkup;
reg spc0_dva_invld_err;
reg [9:0] spc0_dva_efull_cntr;
reg spc0_dva_efull_d;
reg spc0_dva_vlddtag_err;
reg spc0_dva_vlddcache_err;
reg spc0_dva_err;
reg [6:0] spc0_dva_raddr_d;
reg [4:0] spc0_dva_waddr_d;
reg [4:0] spc0_dva_invwaddr_d;
reg spc0_ld0_lt_1;
reg spc0_ld0_lt_2;
reg spc0_ld0_lt_3;
reg spc0_ld1_lt_0;
reg spc0_ld1_lt_2;
reg spc0_ld1_lt_3;
reg spc0_ld2_lt_0;
reg spc0_ld2_lt_1;
reg spc0_ld2_lt_3;
reg spc0_ld3_lt_0;
reg spc0_ld3_lt_1;
reg spc0_ld3_lt_2;
reg spc0_st0_lt_1;
reg spc0_st0_lt_2;
reg spc0_st0_lt_3;
reg spc0_st1_lt_0;
reg spc0_st1_lt_2;
reg spc0_st1_lt_3;
reg spc0_st2_lt_0;
reg spc0_st2_lt_1;
reg spc0_st2_lt_3;
reg spc0_st3_lt_0;
reg spc0_st3_lt_1;
reg spc0_st3_lt_2;
wire [11:0] spc0_ld_ooo_ret;
wire [11:0] spc0_st_ooo_ret;
wire [7:0] spc0_stb_state_vld0 = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc0_stb_state_ack0 = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc0_stb_state_ced0 = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc0_stb_state_rst0 = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_state_rst;
wire spc0_stb_ack_vld0 = `TOP_DESIGN.sparc0.lsu.stb_ctl0.ack_vld;
wire spc0_ld0_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_inst_vld_g;
wire spc0_intrpt0_cmplt = `TOP_DESIGN.sparc0.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc0_stb0_full = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_full;
wire spc0_stb0_full_w2 = `TOP_DESIGN.sparc0.lsu.stb_ctl0.stb_full_w2;
wire spc0_lmq0_full = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_pcx_rq_vld;
wire spc0_mbar_vld0 = `TOP_DESIGN.sparc0.lsu.dctl.mbar_vld0;
wire spc0_ld0_unfilled = `TOP_DESIGN.sparc0.lsu.qctl1.ld0_unfilled;
wire spc0_flsh_vld0 = `TOP_DESIGN.sparc0.lsu.dctl.flsh_vld0;
reg [9:0] spc0_ld0_unf_cntr;
reg spc0_ld0_unfilled_d;
reg [9:0] spc0_st0_unf_cntr;
reg spc0_st0_unfilled_d;
reg spc0_st0_unfilled;
reg spc0_mbar_vld_d0;
reg spc0_flsh_vld_d0;
reg spc0_lmq0_full_d;
reg [9:0] spc0_lmq_full_cntr0;
reg spc0_lmq_full_capture0;
reg [9:0] spc0_stb_full_cntr0;
reg spc0_stb_full_capture0;
reg [9:0] spc0_mbar_vld_cntr0;
reg spc0_mbar_vld_capture0;
reg [9:0] spc0_flsh_vld_cntr0;
reg spc0_flsh_vld_capture0;
reg spc0_stb_head_hit0;
wire spc0_raw_ack_capture0;
reg [9:0] spc0_stb_ack_cntr0;
reg [9:0] spc0_stb_ced_cntr0;
reg spc0_stb_ced0_d;
reg spc0_stb_ced_capture0;
wire spc0_stb_ced0;
reg spc0_atm0_d;
reg [9:0] spc0_atm_cntr0;
reg spc0_atm_intrpt_capture0;
reg spc0_atm_intrpt_b4capture0;
reg spc0_atm_inv_capture0;
reg [39:0] spc0_stb_wr_addr0;
reg [39:0] spc0_stb_atm_addr0;
reg spc0_atm_lmiss_eq0;
wire [7:0] spc0_stb_state_vld1 = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc0_stb_state_ack1 = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc0_stb_state_ced1 = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc0_stb_state_rst1 = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_state_rst;
wire spc0_stb_ack_vld1 = `TOP_DESIGN.sparc0.lsu.stb_ctl1.ack_vld;
wire spc0_ld1_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_inst_vld_g;
wire spc0_intrpt1_cmplt = `TOP_DESIGN.sparc0.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc0_stb1_full = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_full;
wire spc0_stb1_full_w2 = `TOP_DESIGN.sparc0.lsu.stb_ctl1.stb_full_w2;
wire spc0_lmq1_full = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_pcx_rq_vld;
wire spc0_mbar_vld1 = `TOP_DESIGN.sparc0.lsu.dctl.mbar_vld1;
wire spc0_ld1_unfilled = `TOP_DESIGN.sparc0.lsu.qctl1.ld1_unfilled;
wire spc0_flsh_vld1 = `TOP_DESIGN.sparc0.lsu.dctl.flsh_vld1;
reg [9:0] spc0_ld1_unf_cntr;
reg spc0_ld1_unfilled_d;
reg [9:0] spc0_st1_unf_cntr;
reg spc0_st1_unfilled_d;
reg spc0_st1_unfilled;
reg spc0_mbar_vld_d1;
reg spc0_flsh_vld_d1;
reg spc0_lmq1_full_d;
reg [9:0] spc0_lmq_full_cntr1;
reg spc0_lmq_full_capture1;
reg [9:0] spc0_stb_full_cntr1;
reg spc0_stb_full_capture1;
reg [9:0] spc0_mbar_vld_cntr1;
reg spc0_mbar_vld_capture1;
reg [9:0] spc0_flsh_vld_cntr1;
reg spc0_flsh_vld_capture1;
reg spc0_stb_head_hit1;
wire spc0_raw_ack_capture1;
reg [9:0] spc0_stb_ack_cntr1;
reg [9:0] spc0_stb_ced_cntr1;
reg spc0_stb_ced1_d;
reg spc0_stb_ced_capture1;
wire spc0_stb_ced1;
reg spc0_atm1_d;
reg [9:0] spc0_atm_cntr1;
reg spc0_atm_intrpt_capture1;
reg spc0_atm_intrpt_b4capture1;
reg spc0_atm_inv_capture1;
reg [39:0] spc0_stb_wr_addr1;
reg [39:0] spc0_stb_atm_addr1;
reg spc0_atm_lmiss_eq1;
wire [7:0] spc0_stb_state_vld2 = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc0_stb_state_ack2 = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc0_stb_state_ced2 = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc0_stb_state_rst2 = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_state_rst;
wire spc0_stb_ack_vld2 = `TOP_DESIGN.sparc0.lsu.stb_ctl2.ack_vld;
wire spc0_ld2_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_inst_vld_g;
wire spc0_intrpt2_cmplt = `TOP_DESIGN.sparc0.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc0_stb2_full = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_full;
wire spc0_stb2_full_w2 = `TOP_DESIGN.sparc0.lsu.stb_ctl2.stb_full_w2;
wire spc0_lmq2_full = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_pcx_rq_vld;
wire spc0_mbar_vld2 = `TOP_DESIGN.sparc0.lsu.dctl.mbar_vld2;
wire spc0_ld2_unfilled = `TOP_DESIGN.sparc0.lsu.qctl1.ld2_unfilled;
wire spc0_flsh_vld2 = `TOP_DESIGN.sparc0.lsu.dctl.flsh_vld2;
reg [9:0] spc0_ld2_unf_cntr;
reg spc0_ld2_unfilled_d;
reg [9:0] spc0_st2_unf_cntr;
reg spc0_st2_unfilled_d;
reg spc0_st2_unfilled;
reg spc0_mbar_vld_d2;
reg spc0_flsh_vld_d2;
reg spc0_lmq2_full_d;
reg [9:0] spc0_lmq_full_cntr2;
reg spc0_lmq_full_capture2;
reg [9:0] spc0_stb_full_cntr2;
reg spc0_stb_full_capture2;
reg [9:0] spc0_mbar_vld_cntr2;
reg spc0_mbar_vld_capture2;
reg [9:0] spc0_flsh_vld_cntr2;
reg spc0_flsh_vld_capture2;
reg spc0_stb_head_hit2;
wire spc0_raw_ack_capture2;
reg [9:0] spc0_stb_ack_cntr2;
reg [9:0] spc0_stb_ced_cntr2;
reg spc0_stb_ced2_d;
reg spc0_stb_ced_capture2;
wire spc0_stb_ced2;
reg spc0_atm2_d;
reg [9:0] spc0_atm_cntr2;
reg spc0_atm_intrpt_capture2;
reg spc0_atm_intrpt_b4capture2;
reg spc0_atm_inv_capture2;
reg [39:0] spc0_stb_wr_addr2;
reg [39:0] spc0_stb_atm_addr2;
reg spc0_atm_lmiss_eq2;
wire [7:0] spc0_stb_state_vld3 = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc0_stb_state_ack3 = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc0_stb_state_ced3 = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc0_stb_state_rst3 = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_state_rst;
wire spc0_stb_ack_vld3 = `TOP_DESIGN.sparc0.lsu.stb_ctl3.ack_vld;
wire spc0_ld3_inst_vld_g = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_inst_vld_g;
wire spc0_intrpt3_cmplt = `TOP_DESIGN.sparc0.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc0_stb3_full = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_full;
wire spc0_stb3_full_w2 = `TOP_DESIGN.sparc0.lsu.stb_ctl3.stb_full_w2;
wire spc0_lmq3_full = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_pcx_rq_vld;
wire spc0_mbar_vld3 = `TOP_DESIGN.sparc0.lsu.dctl.mbar_vld3;
wire spc0_ld3_unfilled = `TOP_DESIGN.sparc0.lsu.qctl1.ld3_unfilled;
wire spc0_flsh_vld3 = `TOP_DESIGN.sparc0.lsu.dctl.flsh_vld3;
reg [9:0] spc0_ld3_unf_cntr;
reg spc0_ld3_unfilled_d;
reg [9:0] spc0_st3_unf_cntr;
reg spc0_st3_unfilled_d;
reg spc0_st3_unfilled;
reg spc0_mbar_vld_d3;
reg spc0_flsh_vld_d3;
reg spc0_lmq3_full_d;
reg [9:0] spc0_lmq_full_cntr3;
reg spc0_lmq_full_capture3;
reg [9:0] spc0_stb_full_cntr3;
reg spc0_stb_full_capture3;
reg [9:0] spc0_mbar_vld_cntr3;
reg spc0_mbar_vld_capture3;
reg [9:0] spc0_flsh_vld_cntr3;
reg spc0_flsh_vld_capture3;
reg spc0_stb_head_hit3;
wire spc0_raw_ack_capture3;
reg [9:0] spc0_stb_ack_cntr3;
reg [9:0] spc0_stb_ced_cntr3;
reg spc0_stb_ced3_d;
reg spc0_stb_ced_capture3;
wire spc0_stb_ced3;
reg spc0_atm3_d;
reg [9:0] spc0_atm_cntr3;
reg spc0_atm_intrpt_capture3;
reg spc0_atm_intrpt_b4capture3;
reg spc0_atm_inv_capture3;
reg [39:0] spc0_stb_wr_addr3;
reg [39:0] spc0_stb_atm_addr3;
reg spc0_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc0_fpick = {spc0_mpick,spc0_spick,spc0_lpick,spc0_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc0_msquash,spc0_apick,spc0_fpick})
9'b000000000 : spc0_fpicko = 1'b0;
9'b0xxx1xxx1 : spc0_fpicko = 1'b0;
9'b1xxxxxxxx : spc0_fpicko = 1'b0;
9'b0xxx0xxx0 : spc0_fpicko = 1'b0;
default:
begin
spc0_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon0 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc0_exu_und = {spc0_l2,
spc0_unc,
spc0_fpld,
spc0_fpldst,
spc0_unflush,
spc0_ldw,
spc0_byp,
spc0_flsh,
spc0_chm,
spc0_ldxa,
spc0_ato,
spc0_pref,
spc0_chit,
spc0_dcp,
spc0_dtp,
spc0_mpc,
spc0_mpu};
always @(spc0_exu_und)
begin
case (spc0_exu_und)
17'h00000 : spc0_exu = 5'h00;
17'h00001 : spc0_exu = 5'h01;
17'h00002 : spc0_exu = 5'h02;
17'h00004 : spc0_exu = 5'h03;
17'h00008 : spc0_exu = 5'h04;
17'h00010 : spc0_exu = 5'h05;
17'h00020 : spc0_exu = 5'h06;
17'h00040 : spc0_exu = 5'h07;
17'h00080 : spc0_exu = 5'h08;
17'h00100 : spc0_exu = 5'h09;
17'h00200 : spc0_exu = 5'h0a;
17'h00400 : spc0_exu = 5'h0b;
17'h00800 : spc0_exu = 5'h0c;
17'h01000 : spc0_exu = 5'h0d;
17'h02000 : spc0_exu = 5'h0e;
17'h04000 : spc0_exu = 5'h0f;
17'h08000 : spc0_exu = 5'h10;
17'h10000 : spc0_exu = 5'h11;
default: spc0_exu = 5'h12;
endcase
end
//excp
assign spc0_exp_und = {spc0_exp_wtchpt_trp_g,
spc0_exp_misalign_addr_ldst_atm_m,
spc0_exp_priv_violtn_g,
spc0_exp_daccess_excptn_g,
spc0_exp_daccess_prot_g,
spc0_exp_priv_action_g,
spc0_exp_spec_access_epage_g,
spc0_exp_uncache_atomic_g,
spc0_exp_illegal_asi_action_g,
spc0_exp_flt_ld_nfo_pg_g,
spc0_exp_asi_rd_unc,
spc0_exp_tlb_data_ce,
spc0_exp_tlb_data_ue,
spc0_exp_tlb_tag_ue,
spc0_exp_unc,
spc0_exp_corr};
always @(spc0_exp_und)
begin
case (spc0_exp_und)
16'h0000 : spc0_exp = 5'h00;
16'h0001 : spc0_exp = 5'h01;
16'h0002 : spc0_exp = 5'h02;
16'h0004 : spc0_exp = 5'h03;
16'h0008 : spc0_exp = 5'h04;
16'h0010 : spc0_exp = 5'h05;
16'h0020 : spc0_exp = 5'h06;
16'h0040 : spc0_exp = 5'h07;
16'h0080 : spc0_exp = 5'h08;
16'h0100 : spc0_exp = 5'h09;
16'h0200 : spc0_exp = 5'h0a;
16'h0400 : spc0_exp = 5'h0b;
16'h0800 : spc0_exp = 5'h0c;
16'h1000 : spc0_exp = 5'h0d;
16'h2000 : spc0_exp = 5'h0e;
16'h4000 : spc0_exp = 5'h0f;
16'h8000 : spc0_exp = 5'h10;
default: spc0_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc0_dctl_stxa_cmplt0 = ((spc0_dctl_stxa_internal_d2 & spc0_dctl_thread0_w3) |
spc0_dctl_stxa_stall_wr_cmplt0_d1);
assign spc0_dctl_l2fill_cmplt0 = (((spc0_dctl_lsu_l2fill_vld & ~spc0_dctl_atomic_ld_squash_e &
~spc0_dctl_lsu_ignore_fill)) & ~spc0_dctl_l2fill_fpld_e &
~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread0);
assign spc0_dctl_fillerr0 = spc0_dctl_l2_corr_error_e & spc0_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc0_dctl_atm_cmplt0 = (spc0_dctl_lsu_atm_st_cmplt_e & ~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread0);
assign spc0_dctl_ldst_cond_cmplt0 = { spc0_dctl_stxa_cmplt0, spc0_dctl_l2fill_cmplt0,
spc0_dctl_atomic_ld_squash_e, spc0_dctl_intld_byp_cmplt[0],
spc0_dctl_bsync0_reset, spc0_dctl_lsu_intrpt_cmplt[0]
};
assign spc0_cmplt0 = { spc0_dctl_ldxa_illgl_va_cmplt_d1, spc0_dctl_pref_tlbmiss_cmplt_d2,
spc0_dctl_lsu_pcx_pref_issue, spc0_dctl_diag_wr_cmplt0, spc0_dctl_l2fill_fpld_e};
always @(spc0_cmplt0 or spc0_dctl_ldst_cond_cmplt0)
begin
case ({spc0_dctl_fillerr0,spc0_dctl_ldst_cond_cmplt0,spc0_cmplt0})
12'h000 : spc0_ldstcond_cmplt0 = 4'h0;
12'h001 : spc0_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc0_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc0_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc0_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc0_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc0_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc0_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc0_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc0_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc0_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc0_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc0_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc0_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc0_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc0_dctl_stxa_cmplt1 = ((spc0_dctl_stxa_internal_d2 & spc0_dctl_thread1_w3) |
spc0_dctl_stxa_stall_wr_cmplt1_d1);
assign spc0_dctl_l2fill_cmplt1 = (((spc0_dctl_lsu_l2fill_vld & ~spc0_dctl_atomic_ld_squash_e &
~spc0_dctl_lsu_ignore_fill)) & ~spc0_dctl_l2fill_fpld_e &
~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread1);
assign spc0_dctl_fillerr1 = spc0_dctl_l2_corr_error_e & spc0_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc0_dctl_atm_cmplt1 = (spc0_dctl_lsu_atm_st_cmplt_e & ~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread1);
assign spc0_dctl_ldst_cond_cmplt1 = { spc0_dctl_stxa_cmplt1, spc0_dctl_l2fill_cmplt1,
spc0_dctl_atomic_ld_squash_e, spc0_dctl_intld_byp_cmplt[1],
spc0_dctl_bsync1_reset, spc0_dctl_lsu_intrpt_cmplt[1]
};
assign spc0_cmplt1 = { spc0_dctl_ldxa_illgl_va_cmplt_d1, spc0_dctl_pref_tlbmiss_cmplt_d2,
spc0_dctl_lsu_pcx_pref_issue, spc0_dctl_diag_wr_cmplt1, spc0_dctl_l2fill_fpld_e};
always @(spc0_cmplt1 or spc0_dctl_ldst_cond_cmplt1)
begin
case ({spc0_dctl_fillerr1,spc0_dctl_ldst_cond_cmplt1,spc0_cmplt1})
12'h000 : spc0_ldstcond_cmplt1 = 4'h0;
12'h001 : spc0_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc0_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc0_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc0_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc0_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc0_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc0_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc0_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc0_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc0_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc0_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc0_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc0_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc0_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc0_dctl_stxa_cmplt2 = ((spc0_dctl_stxa_internal_d2 & spc0_dctl_thread2_w3) |
spc0_dctl_stxa_stall_wr_cmplt2_d1);
assign spc0_dctl_l2fill_cmplt2 = (((spc0_dctl_lsu_l2fill_vld & ~spc0_dctl_atomic_ld_squash_e &
~spc0_dctl_lsu_ignore_fill)) & ~spc0_dctl_l2fill_fpld_e &
~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread2);
assign spc0_dctl_fillerr2 = spc0_dctl_l2_corr_error_e & spc0_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc0_dctl_atm_cmplt2 = (spc0_dctl_lsu_atm_st_cmplt_e & ~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread2);
assign spc0_dctl_ldst_cond_cmplt2 = { spc0_dctl_stxa_cmplt2, spc0_dctl_l2fill_cmplt2,
spc0_dctl_atomic_ld_squash_e, spc0_dctl_intld_byp_cmplt[2],
spc0_dctl_bsync2_reset, spc0_dctl_lsu_intrpt_cmplt[2]
};
assign spc0_cmplt2 = { spc0_dctl_ldxa_illgl_va_cmplt_d1, spc0_dctl_pref_tlbmiss_cmplt_d2,
spc0_dctl_lsu_pcx_pref_issue, spc0_dctl_diag_wr_cmplt2, spc0_dctl_l2fill_fpld_e};
always @(spc0_cmplt2 or spc0_dctl_ldst_cond_cmplt2)
begin
case ({spc0_dctl_fillerr2,spc0_dctl_ldst_cond_cmplt2,spc0_cmplt2})
12'h000 : spc0_ldstcond_cmplt2 = 4'h0;
12'h001 : spc0_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc0_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc0_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc0_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc0_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc0_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc0_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc0_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc0_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc0_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc0_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc0_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc0_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc0_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc0_dctl_stxa_cmplt3 = ((spc0_dctl_stxa_internal_d2 & spc0_dctl_thread3_w3) |
spc0_dctl_stxa_stall_wr_cmplt3_d1);
assign spc0_dctl_l2fill_cmplt3 = (((spc0_dctl_lsu_l2fill_vld & ~spc0_dctl_atomic_ld_squash_e &
~spc0_dctl_lsu_ignore_fill)) & ~spc0_dctl_l2fill_fpld_e &
~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread3);
assign spc0_dctl_fillerr3 = spc0_dctl_l2_corr_error_e & spc0_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc0_dctl_atm_cmplt3 = (spc0_dctl_lsu_atm_st_cmplt_e & ~spc0_dctl_fill_err_trap_e & spc0_dctl_dfill_thread3);
assign spc0_dctl_ldst_cond_cmplt3 = { spc0_dctl_stxa_cmplt3, spc0_dctl_l2fill_cmplt3,
spc0_dctl_atomic_ld_squash_e, spc0_dctl_intld_byp_cmplt[3],
spc0_dctl_bsync3_reset, spc0_dctl_lsu_intrpt_cmplt[3]
};
assign spc0_cmplt3 = { spc0_dctl_ldxa_illgl_va_cmplt_d1, spc0_dctl_pref_tlbmiss_cmplt_d2,
spc0_dctl_lsu_pcx_pref_issue, spc0_dctl_diag_wr_cmplt3, spc0_dctl_l2fill_fpld_e};
always @(spc0_cmplt3 or spc0_dctl_ldst_cond_cmplt3)
begin
case ({spc0_dctl_fillerr3,spc0_dctl_ldst_cond_cmplt3,spc0_cmplt3})
12'h000 : spc0_ldstcond_cmplt3 = 4'h0;
12'h001 : spc0_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc0_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc0_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc0_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc0_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc0_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc0_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc0_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc0_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc0_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc0_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc0_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc0_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc0_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc0_ldstcond_cmplt0 or spc0_ldstcond_cmplt1 or spc0_ldstcond_cmplt2
or spc0_ldstcond_cmplt3 or spc0_dctl_lsu_ifu_ldst_cmplt
or spc0_dctl_late_cmplt0 or spc0_dctl_late_cmplt1 or spc0_dctl_late_cmplt2 or spc0_dctl_late_cmplt3)
begin
case (spc0_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc0_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc0_ldstcond_cmplt_d = spc0_dctl_late_cmplt0 ? spc0_ldstcond_cmplt0_d : spc0_ldstcond_cmplt0;
4'b0010 : spc0_ldstcond_cmplt_d = spc0_dctl_late_cmplt1 ? spc0_ldstcond_cmplt1_d : spc0_ldstcond_cmplt1;
4'b0100 : spc0_ldstcond_cmplt_d = spc0_dctl_late_cmplt2 ? spc0_ldstcond_cmplt2_d : spc0_ldstcond_cmplt2;
4'b1000 : spc0_ldstcond_cmplt_d = spc0_dctl_late_cmplt3 ? spc0_ldstcond_cmplt3_d : spc0_ldstcond_cmplt3;
4'b0011 : spc0_ldstcond_cmplt_d = 4'he;
4'b0101 : spc0_ldstcond_cmplt_d = 4'he;
4'b1001 : spc0_ldstcond_cmplt_d = 4'he;
4'b0110 : spc0_ldstcond_cmplt_d = 4'he;
4'b1010 : spc0_ldstcond_cmplt_d = 4'he;
4'b1100 : spc0_ldstcond_cmplt_d = 4'he;
default:
begin
spc0_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc0_st_ooo_ret = { spc0_st0_lt_1, spc0_st0_lt_2, spc0_st0_lt_3,
spc0_st1_lt_0, spc0_st1_lt_2, spc0_st1_lt_3,
spc0_st2_lt_0, spc0_st2_lt_1, spc0_st2_lt_3,
spc0_st3_lt_0, spc0_st3_lt_1, spc0_st3_lt_2};
always @(posedge clk)
begin
if(~spc0_st0_unfilled || ~rst_l)
spc0_st0_unfilled_d <= 1'b0;
else
spc0_st0_unfilled_d <= spc0_st0_unfilled;
if(~rst_l)
spc0_ldstcond_cmplt0_d <= 4'h0;
else
spc0_ldstcond_cmplt0_d <= spc0_ldstcond_cmplt0;
if(~spc0_ld0_pkt_vld_unmasked || ~rst_l)
spc0_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc0_ld0_pkt_vld_unmasked_d <= spc0_ld0_pkt_vld_unmasked;
if(~rst_l)
spc0_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc0_qctl1_ld_sec_hit_thrd0 && spc0_qctl1_ld0_inst_vld_g)
spc0_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc0_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc0_st1_unfilled || ~rst_l)
spc0_st1_unfilled_d <= 1'b0;
else
spc0_st1_unfilled_d <= spc0_st1_unfilled;
if(~rst_l)
spc0_ldstcond_cmplt1_d <= 4'h0;
else
spc0_ldstcond_cmplt1_d <= spc0_ldstcond_cmplt1;
if(~spc0_ld1_pkt_vld_unmasked || ~rst_l)
spc0_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc0_ld1_pkt_vld_unmasked_d <= spc0_ld1_pkt_vld_unmasked;
if(~rst_l)
spc0_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc0_qctl1_ld_sec_hit_thrd1 && spc0_qctl1_ld1_inst_vld_g)
spc0_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc0_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc0_st2_unfilled || ~rst_l)
spc0_st2_unfilled_d <= 1'b0;
else
spc0_st2_unfilled_d <= spc0_st2_unfilled;
if(~rst_l)
spc0_ldstcond_cmplt2_d <= 4'h0;
else
spc0_ldstcond_cmplt2_d <= spc0_ldstcond_cmplt2;
if(~spc0_ld2_pkt_vld_unmasked || ~rst_l)
spc0_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc0_ld2_pkt_vld_unmasked_d <= spc0_ld2_pkt_vld_unmasked;
if(~rst_l)
spc0_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc0_qctl1_ld_sec_hit_thrd2 && spc0_qctl1_ld2_inst_vld_g)
spc0_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc0_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc0_st3_unfilled || ~rst_l)
spc0_st3_unfilled_d <= 1'b0;
else
spc0_st3_unfilled_d <= spc0_st3_unfilled;
if(~rst_l)
spc0_ldstcond_cmplt3_d <= 4'h0;
else
spc0_ldstcond_cmplt3_d <= spc0_ldstcond_cmplt3;
if(~spc0_ld3_pkt_vld_unmasked || ~rst_l)
spc0_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc0_ld3_pkt_vld_unmasked_d <= spc0_ld3_pkt_vld_unmasked;
if(~rst_l)
spc0_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc0_qctl1_ld_sec_hit_thrd3 && spc0_qctl1_ld3_inst_vld_g)
spc0_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc0_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc0_stb_state_ced0) && (|spc0_stb_state_rst0)) || ~rst_l)
spc0_st0_unfilled <= 1'b0;
else if( ((|spc0_stb_state_ced0) && ~(|spc0_stb_state_rst0)))
spc0_st0_unfilled <= 1'b1;
else
spc0_st0_unfilled <= spc0_st0_unfilled;
if( ((|spc0_stb_state_ced1) && (|spc0_stb_state_rst1)) || ~rst_l)
spc0_st1_unfilled <= 1'b0;
else if( ((|spc0_stb_state_ced1) && ~(|spc0_stb_state_rst1)))
spc0_st1_unfilled <= 1'b1;
else
spc0_st1_unfilled <= spc0_st1_unfilled;
if( ((|spc0_stb_state_ced2) && (|spc0_stb_state_rst2)) || ~rst_l)
spc0_st2_unfilled <= 1'b0;
else if( ((|spc0_stb_state_ced2) && ~(|spc0_stb_state_rst2)))
spc0_st2_unfilled <= 1'b1;
else
spc0_st2_unfilled <= spc0_st2_unfilled;
if( ((|spc0_stb_state_ced3) && (|spc0_stb_state_rst3)) || ~rst_l)
spc0_st3_unfilled <= 1'b0;
else if( ((|spc0_stb_state_ced3) && ~(|spc0_stb_state_rst3)))
spc0_st3_unfilled <= 1'b1;
else
spc0_st3_unfilled <= spc0_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc0_st0_unfilled && spc0_st0_unfilled_d)|| ~rst_l)
begin
spc0_st0_unf_cntr <= 9'h000;
end
else if(spc0_st0_unfilled)
begin
spc0_st0_unf_cntr <= spc0_st0_unf_cntr + 1;
end
else
begin
spc0_st0_unf_cntr <= spc0_st0_unf_cntr;
end
if((~spc0_st1_unfilled && spc0_st1_unfilled_d)|| ~rst_l)
begin
spc0_st1_unf_cntr <= 9'h000;
end
else if(spc0_st1_unfilled)
begin
spc0_st1_unf_cntr <= spc0_st1_unf_cntr + 1;
end
else
begin
spc0_st1_unf_cntr <= spc0_st1_unf_cntr;
end
if((~spc0_st2_unfilled && spc0_st2_unfilled_d)|| ~rst_l)
begin
spc0_st2_unf_cntr <= 9'h000;
end
else if(spc0_st2_unfilled)
begin
spc0_st2_unf_cntr <= spc0_st2_unf_cntr + 1;
end
else
begin
spc0_st2_unf_cntr <= spc0_st2_unf_cntr;
end
if((~spc0_st3_unfilled && spc0_st3_unfilled_d)|| ~rst_l)
begin
spc0_st3_unf_cntr <= 9'h000;
end
else if(spc0_st3_unfilled)
begin
spc0_st3_unf_cntr <= spc0_st3_unf_cntr + 1;
end
else
begin
spc0_st3_unf_cntr <= spc0_st3_unf_cntr;
end
end
always @(spc0_st0_unfilled or spc0_st1_unfilled or spc0_st2_unfilled or spc0_st3_unfilled
or spc0_st0_unfilled_d or spc0_st1_unfilled_d or spc0_st2_unfilled_d or spc0_st3_unfilled_d)
begin
if(~spc0_st0_unfilled && spc0_st0_unfilled_d && spc0_st1_unfilled)
spc0_st0_lt_1 <= (spc0_st1_unf_cntr > spc0_st0_unf_cntr);
else
spc0_st0_lt_1 <= 1'b0;
if(~spc0_st0_unfilled && spc0_st0_unfilled_d && spc0_st2_unfilled)
spc0_st0_lt_2 <= (spc0_st2_unf_cntr > spc0_st0_unf_cntr);
else
spc0_st0_lt_2 <= 1'b0;
if(~spc0_st0_unfilled && spc0_st0_unfilled_d && spc0_st3_unfilled)
spc0_st0_lt_3 <= (spc0_st3_unf_cntr > spc0_st0_unf_cntr);
else
spc0_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc0_st1_unfilled && spc0_st1_unfilled_d && spc0_st0_unfilled)
spc0_st1_lt_0 <= (spc0_st0_unf_cntr > spc0_st1_unf_cntr);
else
spc0_st1_lt_0 <= 1'b0;
if(~spc0_st1_unfilled && spc0_st1_unfilled_d && spc0_st2_unfilled)
spc0_st1_lt_2 <= (spc0_st2_unf_cntr > spc0_st1_unf_cntr);
else
spc0_st1_lt_2 <= 1'b0;
if(~spc0_st1_unfilled && spc0_st1_unfilled_d && spc0_st3_unfilled)
spc0_st1_lt_3 <= (spc0_st3_unf_cntr > spc0_st1_unf_cntr);
else
spc0_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc0_st2_unfilled && spc0_st2_unfilled_d && spc0_st0_unfilled)
spc0_st2_lt_0 <= (spc0_st0_unf_cntr > spc0_st2_unf_cntr);
else
spc0_st2_lt_0 <= 1'b0;
if(~spc0_st2_unfilled && spc0_st2_unfilled_d && spc0_st1_unfilled)
spc0_st2_lt_1 <= (spc0_st1_unf_cntr > spc0_st2_unf_cntr);
else
spc0_st2_lt_1 <= 1'b0;
if(~spc0_st2_unfilled && spc0_st2_unfilled_d && spc0_st3_unfilled)
spc0_st2_lt_3 <= (spc0_st3_unf_cntr > spc0_st2_unf_cntr);
else
spc0_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc0_st3_unfilled && spc0_st3_unfilled_d && spc0_st0_unfilled)
spc0_st3_lt_0 <= (spc0_st0_unf_cntr > spc0_st3_unf_cntr);
else
spc0_st3_lt_0 <= 1'b0;
if(~spc0_st3_unfilled && spc0_st3_unfilled_d && spc0_st1_unfilled)
spc0_st3_lt_1 <= (spc0_st1_unf_cntr > spc0_st3_unf_cntr);
else
spc0_st3_lt_1 <= 1'b0;
if(~spc0_st3_unfilled && spc0_st3_unfilled_d && spc0_st2_unfilled)
spc0_st3_lt_2 <= (spc0_st2_unf_cntr > spc0_st3_unf_cntr);
else
spc0_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc0_ld_ooo_ret = { spc0_ld0_lt_1, spc0_ld0_lt_2, spc0_ld0_lt_3,
spc0_ld1_lt_0, spc0_ld1_lt_2, spc0_ld1_lt_3,
spc0_ld2_lt_0, spc0_ld2_lt_1, spc0_ld2_lt_3,
spc0_ld3_lt_0, spc0_ld3_lt_1, spc0_ld3_lt_2};
always @(posedge clk)
begin
if((~spc0_ld0_unfilled && spc0_ld0_unfilled_d)|| ~rst_l)
begin
spc0_ld0_unf_cntr <= 9'h000;
end
else if(spc0_ld0_unfilled)
begin
spc0_ld0_unf_cntr <= spc0_ld0_unf_cntr + 1;
end
else
begin
spc0_ld0_unf_cntr <= spc0_ld0_unf_cntr;
end
if((~spc0_ld1_unfilled && spc0_ld1_unfilled_d)|| ~rst_l)
begin
spc0_ld1_unf_cntr <= 9'h000;
end
else if(spc0_ld1_unfilled)
begin
spc0_ld1_unf_cntr <= spc0_ld1_unf_cntr + 1;
end
else
begin
spc0_ld1_unf_cntr <= spc0_ld1_unf_cntr;
end
if((~spc0_ld2_unfilled && spc0_ld2_unfilled_d)|| ~rst_l)
begin
spc0_ld2_unf_cntr <= 9'h000;
end
else if(spc0_ld2_unfilled)
begin
spc0_ld2_unf_cntr <= spc0_ld2_unf_cntr + 1;
end
else
begin
spc0_ld2_unf_cntr <= spc0_ld2_unf_cntr;
end
if((~spc0_ld3_unfilled && spc0_ld3_unfilled_d)|| ~rst_l)
begin
spc0_ld3_unf_cntr <= 9'h000;
end
else if(spc0_ld3_unfilled)
begin
spc0_ld3_unf_cntr <= spc0_ld3_unf_cntr + 1;
end
else
begin
spc0_ld3_unf_cntr <= spc0_ld3_unf_cntr;
end
end
always @(spc0_ld0_unfilled or spc0_ld1_unfilled or spc0_ld2_unfilled or spc0_ld3_unfilled
or spc0_ld0_unfilled_d or spc0_ld1_unfilled_d or spc0_ld2_unfilled_d or spc0_ld3_unfilled_d)
begin
if(~spc0_ld0_unfilled && spc0_ld0_unfilled_d && spc0_ld1_unfilled)
spc0_ld0_lt_1 <= (spc0_ld1_unf_cntr > spc0_ld0_unf_cntr);
else
spc0_ld0_lt_1 <= 1'b0;
if(~spc0_ld0_unfilled && spc0_ld0_unfilled_d && spc0_ld2_unfilled)
spc0_ld0_lt_2 <= (spc0_ld2_unf_cntr > spc0_ld0_unf_cntr);
else
spc0_ld0_lt_2 <= 1'b0;
if(~spc0_ld0_unfilled && spc0_ld0_unfilled_d && spc0_ld3_unfilled)
spc0_ld0_lt_3 <= (spc0_ld3_unf_cntr > spc0_ld0_unf_cntr);
else
spc0_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc0_ld1_unfilled && spc0_ld1_unfilled_d && spc0_ld0_unfilled)
spc0_ld1_lt_0 <= (spc0_ld0_unf_cntr > spc0_ld1_unf_cntr);
else
spc0_ld1_lt_0 <= 1'b0;
if(~spc0_ld1_unfilled && spc0_ld1_unfilled_d && spc0_ld2_unfilled)
spc0_ld1_lt_2 <= (spc0_ld2_unf_cntr > spc0_ld1_unf_cntr);
else
spc0_ld1_lt_2 <= 1'b0;
if(~spc0_ld1_unfilled && spc0_ld1_unfilled_d && spc0_ld3_unfilled)
spc0_ld1_lt_3 <= (spc0_ld3_unf_cntr > spc0_ld1_unf_cntr);
else
spc0_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc0_ld2_unfilled && spc0_ld2_unfilled_d && spc0_ld0_unfilled)
spc0_ld2_lt_0 <= (spc0_ld0_unf_cntr > spc0_ld2_unf_cntr);
else
spc0_ld2_lt_0 <= 1'b0;
if(~spc0_ld2_unfilled && spc0_ld2_unfilled_d && spc0_ld1_unfilled)
spc0_ld2_lt_1 <= (spc0_ld1_unf_cntr > spc0_ld2_unf_cntr);
else
spc0_ld2_lt_1 <= 1'b0;
if(~spc0_ld2_unfilled && spc0_ld2_unfilled_d && spc0_ld3_unfilled)
spc0_ld2_lt_3 <= (spc0_ld3_unf_cntr > spc0_ld2_unf_cntr);
else
spc0_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc0_ld3_unfilled && spc0_ld3_unfilled_d && spc0_ld0_unfilled)
spc0_ld3_lt_0 <= (spc0_ld0_unf_cntr > spc0_ld3_unf_cntr);
else
spc0_ld3_lt_0 <= 1'b0;
if(~spc0_ld3_unfilled && spc0_ld3_unfilled_d && spc0_ld1_unfilled)
spc0_ld3_lt_1 <= (spc0_ld1_unf_cntr > spc0_ld3_unf_cntr);
else
spc0_ld3_lt_1 <= 1'b0;
if(~spc0_ld3_unfilled && spc0_ld3_unfilled_d && spc0_ld2_unfilled)
spc0_ld3_lt_2 <= (spc0_ld2_unf_cntr > spc0_ld3_unf_cntr);
else
spc0_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc0_dctl_bld_hit =
((|spc0_dctl_lsu_way_hit[3:0]) & spc0_dctl_dcache_enable_g &
~spc0_dctl_ldxa_internal & ~spc0_dctl_dcache_rd_parity_error & ~spc0_dctl_dtag_perror_g &
~spc0_dctl_endian_mispred_g &
~spc0_dctl_atomic_g & ~spc0_dctl_ncache_asild_rq_g) & ~spc0_dctl_tte_data_perror_unc &
spc0_dctl_ld_inst_vld_g & spc0_qctl1_bld_g ;
assign spc0_dctl_bld_stb_hit = spc0_dctl_bld_hit & spc0_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc0_bld0_full_d <= 2'b00;
spc0_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc0_bld0_full_d <= spc0_qctl1_bld_cnt;
spc0_ld0_unfilled_d <= spc0_ld0_unfilled;
end
if(~rst_l)
begin
spc0_bld1_full_d <= 2'b00;
spc0_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc0_bld1_full_d <= spc0_qctl1_bld_cnt;
spc0_ld1_unfilled_d <= spc0_ld1_unfilled;
end
if(~rst_l)
begin
spc0_bld2_full_d <= 2'b00;
spc0_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc0_bld2_full_d <= spc0_qctl1_bld_cnt;
spc0_ld2_unfilled_d <= spc0_ld2_unfilled;
end
if(~rst_l)
begin
spc0_bld3_full_d <= 2'b00;
spc0_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc0_bld3_full_d <= spc0_qctl1_bld_cnt;
spc0_ld3_unfilled_d <= spc0_ld3_unfilled;
end
end
always @(spc0_bld0_full_d or spc0_qctl1_bld_cnt)
begin
if( (spc0_bld0_full_d != spc0_qctl1_bld_cnt) && (spc0_bld0_full_d == 2'd0))
spc0_bld0_full_capture <= 1'b1;
else
spc0_bld0_full_capture <= 1'b0;
end
always @(spc0_bld1_full_d or spc0_qctl1_bld_cnt)
begin
if( (spc0_bld1_full_d != spc0_qctl1_bld_cnt) && (spc0_bld1_full_d == 2'd1))
spc0_bld1_full_capture <= 1'b1;
else
spc0_bld1_full_capture <= 1'b0;
end
always @(spc0_bld2_full_d or spc0_qctl1_bld_cnt)
begin
if( (spc0_bld2_full_d != spc0_qctl1_bld_cnt) && (spc0_bld2_full_d == 2'd2))
spc0_bld2_full_capture <= 1'b1;
else
spc0_bld2_full_capture <= 1'b0;
end
always @(spc0_bld3_full_d or spc0_qctl1_bld_cnt)
begin
if( (spc0_bld3_full_d != spc0_qctl1_bld_cnt) && (spc0_bld3_full_d == 2'd3))
spc0_bld3_full_capture <= 1'b1;
else
spc0_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc0_qctl1_bld_cnt != 2'b00) && (spc0_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc0_bld0_full_cntr <= 9'h000;
end
else if(spc0_qctl1_bld_g && (spc0_qctl1_bld_cnt == 2'b00))
begin
spc0_bld0_full_cntr <= spc0_bld0_full_cntr + 1;
end
else if( (spc0_qctl1_bld_cnt == 2'b00) && (spc0_bld0_full_cntr != 9'h000))
begin
spc0_bld0_full_cntr <= spc0_bld0_full_cntr + 1;
end
else
begin
spc0_bld0_full_cntr <= spc0_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc0_qctl1_bld_cnt != 2'b01) && (spc0_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc0_bld1_full_cntr <= 9'h000;
end
else if(spc0_qctl1_bld_cnt == 2'b01)
begin
spc0_bld1_full_cntr <= spc0_bld1_full_cntr + 1;
end
else if( (spc0_qctl1_bld_cnt == 2'b01) && (spc0_bld1_full_cntr != 9'h000))
begin
spc0_bld1_full_cntr <= spc0_bld1_full_cntr + 1;
end
else
begin
spc0_bld1_full_cntr <= spc0_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc0_qctl1_bld_cnt != 2'b10) && (spc0_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc0_bld2_full_cntr <= 9'h000;
end
else if(spc0_qctl1_bld_cnt == 2'b10)
begin
spc0_bld2_full_cntr <= spc0_bld2_full_cntr + 1;
end
else if( (spc0_qctl1_bld_cnt == 2'b10) && (spc0_bld2_full_cntr != 9'h000))
begin
spc0_bld2_full_cntr <= spc0_bld2_full_cntr + 1;
end
else
begin
spc0_bld2_full_cntr <= spc0_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc0_qctl1_bld_cnt != 2'b11) && (spc0_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc0_bld3_full_cntr <= 9'h000;
end
else if(spc0_qctl1_bld_cnt == 2'b11)
begin
spc0_bld3_full_cntr <= spc0_bld3_full_cntr + 1;
end
else if( (spc0_qctl1_bld_cnt == 2'b11) && (spc0_bld3_full_cntr != 9'h000))
begin
spc0_bld3_full_cntr <= spc0_bld3_full_cntr + 1;
end
else
begin
spc0_bld3_full_cntr <= spc0_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc0_stb_state_vld0) && ~spc0_atomic_g) || ~rst_l)
begin
spc0_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc0_atomic_g && (spc0_atm_type0 != 8'h00) && spc0_wptr_vld)
begin
spc0_stb_atm_addr0 <= {spc0_wdata_ramc[44:9],spc0_wdata_ramd[67:64]};
end
else
begin
spc0_stb_atm_addr0 <= spc0_stb_atm_addr0;
end
if( ( ~(|spc0_stb_state_vld1) && ~spc0_atomic_g) || ~rst_l)
begin
spc0_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc0_atomic_g && (spc0_atm_type1 != 8'h00) && spc0_wptr_vld)
begin
spc0_stb_atm_addr1 <= {spc0_wdata_ramc[44:9],spc0_wdata_ramd[67:64]};
end
else
begin
spc0_stb_atm_addr1 <= spc0_stb_atm_addr1;
end
if( ( ~(|spc0_stb_state_vld2) && ~spc0_atomic_g) || ~rst_l)
begin
spc0_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc0_atomic_g && (spc0_atm_type2 != 8'h00) && spc0_wptr_vld)
begin
spc0_stb_atm_addr2 <= {spc0_wdata_ramc[44:9],spc0_wdata_ramd[67:64]};
end
else
begin
spc0_stb_atm_addr2 <= spc0_stb_atm_addr2;
end
if( ( ~(|spc0_stb_state_vld3) && ~spc0_atomic_g) || ~rst_l)
begin
spc0_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc0_atomic_g && (spc0_atm_type3 != 8'h00) && spc0_wptr_vld)
begin
spc0_stb_atm_addr3 <= {spc0_wdata_ramc[44:9],spc0_wdata_ramd[67:64]};
end
else
begin
spc0_stb_atm_addr3 <= spc0_stb_atm_addr3;
end
end
assign spc0_dfq_full = (spc0_dfq_vld_entries >= 3'd4);
assign spc0_dfq_full1 = (spc0_dfq_vld_entries >= (3'd4 + 1));
always @(spc0_dfq_full_d1 or spc0_dfq_full1)
begin
if (spc0_dfq_full_d1 && ~spc0_dfq_full1)
spc0_dfq_full_capture1 <= 1'b1;
else
spc0_dfq_full_capture1 <= 1'b0;
end
assign spc0_dfq_full2 = (spc0_dfq_vld_entries >= (3'd4 + 2));
always @(spc0_dfq_full_d2 or spc0_dfq_full2)
begin
if (spc0_dfq_full_d2 && ~spc0_dfq_full2)
spc0_dfq_full_capture2 <= 1'b1;
else
spc0_dfq_full_capture2 <= 1'b0;
end
assign spc0_dfq_full3 = (spc0_dfq_vld_entries >= (3'd4 + 3));
always @(spc0_dfq_full_d3 or spc0_dfq_full3)
begin
if (spc0_dfq_full_d3 && ~spc0_dfq_full3)
spc0_dfq_full_capture3 <= 1'b1;
else
spc0_dfq_full_capture3 <= 1'b0;
end
assign spc0_dfq_full4 = (spc0_dfq_vld_entries >= (3'd4 + 4));
always @(spc0_dfq_full_d4 or spc0_dfq_full4)
begin
if (spc0_dfq_full_d4 && ~spc0_dfq_full4)
spc0_dfq_full_capture4 <= 1'b1;
else
spc0_dfq_full_capture4 <= 1'b0;
end
assign spc0_dfq_full5 = (spc0_dfq_vld_entries >= (3'd4 + 5));
always @(spc0_dfq_full_d5 or spc0_dfq_full5)
begin
if (spc0_dfq_full_d5 && ~spc0_dfq_full5)
spc0_dfq_full_capture5 <= 1'b1;
else
spc0_dfq_full_capture5 <= 1'b0;
end
assign spc0_dfq_full6 = (spc0_dfq_vld_entries >= (3'd4 + 6));
always @(spc0_dfq_full_d6 or spc0_dfq_full6)
begin
if (spc0_dfq_full_d6 && ~spc0_dfq_full6)
spc0_dfq_full_capture6 <= 1'b1;
else
spc0_dfq_full_capture6 <= 1'b0;
end
assign spc0_dfq_full7 = (spc0_dfq_vld_entries >= (3'd4 + 7));
always @(spc0_dfq_full_d7 or spc0_dfq_full7)
begin
if (spc0_dfq_full_d7 && ~spc0_dfq_full7)
spc0_dfq_full_capture7 <= 1'b1;
else
spc0_dfq_full_capture7 <= 1'b0;
end
always @(spc0_mbar_vld_d0 or spc0_mbar_vld0)
begin
if (spc0_mbar_vld_d0 && ~spc0_mbar_vld0)
spc0_mbar_vld_capture0 <= 1'b1;
else
spc0_mbar_vld_capture0 <= 1'b0;
end
always @(spc0_mbar_vld_d1 or spc0_mbar_vld1)
begin
if (spc0_mbar_vld_d1 && ~spc0_mbar_vld1)
spc0_mbar_vld_capture1 <= 1'b1;
else
spc0_mbar_vld_capture1 <= 1'b0;
end
always @(spc0_mbar_vld_d2 or spc0_mbar_vld2)
begin
if (spc0_mbar_vld_d2 && ~spc0_mbar_vld2)
spc0_mbar_vld_capture2 <= 1'b1;
else
spc0_mbar_vld_capture2 <= 1'b0;
end
always @(spc0_mbar_vld_d3 or spc0_mbar_vld3)
begin
if (spc0_mbar_vld_d3 && ~spc0_mbar_vld3)
spc0_mbar_vld_capture3 <= 1'b1;
else
spc0_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc0_dfq_full1 && (spc0_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr1 <= 9'h000;
spc0_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr1);
end
else if( spc0_dfq_full1)
begin
spc0_dfq_full_cntr1 <= spc0_dfq_full_cntr1 + 1;
spc0_dfq_full_d1 <= spc0_dfq_full1;
end
else
begin
spc0_dfq_full_cntr1 <= spc0_dfq_full_cntr1;
spc0_dfq_full_d1 <= spc0_dfq_full1;
end
if( ( ~spc0_dfq_full2 && (spc0_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr2 <= 9'h000;
spc0_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr2);
end
else if( spc0_dfq_full2)
begin
spc0_dfq_full_cntr2 <= spc0_dfq_full_cntr2 + 1;
spc0_dfq_full_d2 <= spc0_dfq_full2;
end
else
begin
spc0_dfq_full_cntr2 <= spc0_dfq_full_cntr2;
spc0_dfq_full_d2 <= spc0_dfq_full2;
end
if( ( ~spc0_dfq_full3 && (spc0_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr3 <= 9'h000;
spc0_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr3);
end
else if( spc0_dfq_full3)
begin
spc0_dfq_full_cntr3 <= spc0_dfq_full_cntr3 + 1;
spc0_dfq_full_d3 <= spc0_dfq_full3;
end
else
begin
spc0_dfq_full_cntr3 <= spc0_dfq_full_cntr3;
spc0_dfq_full_d3 <= spc0_dfq_full3;
end
if( ( ~spc0_dfq_full4 && (spc0_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr4 <= 9'h000;
spc0_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr4);
end
else if( spc0_dfq_full4)
begin
spc0_dfq_full_cntr4 <= spc0_dfq_full_cntr4 + 1;
spc0_dfq_full_d4 <= spc0_dfq_full4;
end
else
begin
spc0_dfq_full_cntr4 <= spc0_dfq_full_cntr4;
spc0_dfq_full_d4 <= spc0_dfq_full4;
end
if( ( ~spc0_dfq_full5 && (spc0_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr5 <= 9'h000;
spc0_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr5);
end
else if( spc0_dfq_full5)
begin
spc0_dfq_full_cntr5 <= spc0_dfq_full_cntr5 + 1;
spc0_dfq_full_d5 <= spc0_dfq_full5;
end
else
begin
spc0_dfq_full_cntr5 <= spc0_dfq_full_cntr5;
spc0_dfq_full_d5 <= spc0_dfq_full5;
end
if( ( ~spc0_dfq_full6 && (spc0_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr6 <= 9'h000;
spc0_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr6);
end
else if( spc0_dfq_full6)
begin
spc0_dfq_full_cntr6 <= spc0_dfq_full_cntr6 + 1;
spc0_dfq_full_d6 <= spc0_dfq_full6;
end
else
begin
spc0_dfq_full_cntr6 <= spc0_dfq_full_cntr6;
spc0_dfq_full_d6 <= spc0_dfq_full6;
end
if( ( ~spc0_dfq_full7 && (spc0_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr7 <= 9'h000;
spc0_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr7);
end
else if( spc0_dfq_full7)
begin
spc0_dfq_full_cntr7 <= spc0_dfq_full_cntr7 + 1;
spc0_dfq_full_d7 <= spc0_dfq_full7;
end
else
begin
spc0_dfq_full_cntr7 <= spc0_dfq_full_cntr7;
spc0_dfq_full_d7 <= spc0_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc0_intrpt0_cmplt or spc0_atm_cntr0 or spc0_stb_state_ced0)
begin
if (spc0_intrpt0_cmplt && (spc0_atm_cntr0 != 9'h000) && ~(|spc0_stb_state_ced0))
spc0_atm_intrpt_b4capture0 <= 1'b1;
else
spc0_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc0_intrpt1_cmplt or spc0_atm_cntr1 or spc0_stb_state_ced1)
begin
if (spc0_intrpt1_cmplt && (spc0_atm_cntr1 != 9'h000) && ~(|spc0_stb_state_ced1))
spc0_atm_intrpt_b4capture1 <= 1'b1;
else
spc0_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc0_intrpt2_cmplt or spc0_atm_cntr2 or spc0_stb_state_ced2)
begin
if (spc0_intrpt2_cmplt && (spc0_atm_cntr2 != 9'h000) && ~(|spc0_stb_state_ced2))
spc0_atm_intrpt_b4capture2 <= 1'b1;
else
spc0_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc0_intrpt3_cmplt or spc0_atm_cntr3 or spc0_stb_state_ced3)
begin
if (spc0_intrpt3_cmplt && (spc0_atm_cntr3 != 9'h000) && ~(|spc0_stb_state_ced3))
spc0_atm_intrpt_b4capture3 <= 1'b1;
else
spc0_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc0_intrpt0_cmplt or spc0_atm_cntr0 or spc0_stb_state_ced0)
begin
if (spc0_intrpt0_cmplt && (spc0_atm_cntr0 != 9'h000) && (|spc0_stb_state_ced0))
spc0_atm_intrpt_capture0 <= 1'b1;
else
spc0_atm_intrpt_capture0 <= 1'b0;
end
always @(spc0_intrpt1_cmplt or spc0_atm_cntr1 or spc0_stb_state_ced1)
begin
if (spc0_intrpt1_cmplt && (spc0_atm_cntr1 != 9'h000) && (|spc0_stb_state_ced1))
spc0_atm_intrpt_capture1 <= 1'b1;
else
spc0_atm_intrpt_capture1 <= 1'b0;
end
always @(spc0_intrpt2_cmplt or spc0_atm_cntr2 or spc0_stb_state_ced2)
begin
if (spc0_intrpt2_cmplt && (spc0_atm_cntr2 != 9'h000) && (|spc0_stb_state_ced2))
spc0_atm_intrpt_capture2 <= 1'b1;
else
spc0_atm_intrpt_capture2 <= 1'b0;
end
always @(spc0_intrpt3_cmplt or spc0_atm_cntr3 or spc0_stb_state_ced3)
begin
if (spc0_intrpt3_cmplt && (spc0_atm_cntr3 != 9'h000) && (|spc0_stb_state_ced3))
spc0_atm_intrpt_capture3 <= 1'b1;
else
spc0_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc0_atm_cntr0 or spc0_dva_din or spc0_dva_wen)
begin
if (~spc0_dva_din && spc0_dva_wen && (spc0_atm_cntr0 != 9'h000))
spc0_atm_inv_capture0 <= 1'b1;
else
spc0_atm_inv_capture0 <= 1'b0;
end
always @(spc0_atm_cntr1 or spc0_dva_din or spc0_dva_wen)
begin
if (~spc0_dva_din && spc0_dva_wen && (spc0_atm_cntr1 != 9'h000))
spc0_atm_inv_capture1 <= 1'b1;
else
spc0_atm_inv_capture1 <= 1'b0;
end
always @(spc0_atm_cntr2 or spc0_dva_din or spc0_dva_wen)
begin
if (~spc0_dva_din && spc0_dva_wen && (spc0_atm_cntr2 != 9'h000))
spc0_atm_inv_capture2 <= 1'b1;
else
spc0_atm_inv_capture2 <= 1'b0;
end
always @(spc0_atm_cntr3 or spc0_dva_din or spc0_dva_wen)
begin
if (~spc0_dva_din && spc0_dva_wen && (spc0_atm_cntr3 != 9'h000))
spc0_atm_inv_capture3 <= 1'b1;
else
spc0_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc0_stb_state_vld0) && (spc0_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_atm_cntr0 <= 9'h000;
spc0_atm0_d <= 1'b0;
end
else if( spc0_atomic_g && (spc0_atm_type0 != 8'h00))
begin
spc0_atm_cntr0 <= spc0_atm_cntr0 + 1;
spc0_atm0_d <= 1'b1;
end
else if( spc0_atm0_d && (|spc0_stb_state_vld0))
begin
spc0_atm_cntr0 <= spc0_atm_cntr0 + 1;
spc0_atm0_d <= spc0_atm0_d;
end
else
begin
spc0_atm_cntr0 <= spc0_atm_cntr0;
spc0_atm0_d <= spc0_atm0_d;
end
if( ( ~(|spc0_stb_state_vld1) && (spc0_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_atm_cntr1 <= 9'h000;
spc0_atm1_d <= 1'b0;
end
else if( spc0_atomic_g && (spc0_atm_type1 != 8'h00))
begin
spc0_atm_cntr1 <= spc0_atm_cntr1 + 1;
spc0_atm1_d <= 1'b1;
end
else if( spc0_atm1_d && (|spc0_stb_state_vld1))
begin
spc0_atm_cntr1 <= spc0_atm_cntr1 + 1;
spc0_atm1_d <= spc0_atm1_d;
end
else
begin
spc0_atm_cntr1 <= spc0_atm_cntr1;
spc0_atm1_d <= spc0_atm1_d;
end
if( ( ~(|spc0_stb_state_vld2) && (spc0_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_atm_cntr2 <= 9'h000;
spc0_atm2_d <= 1'b0;
end
else if( spc0_atomic_g && (spc0_atm_type2 != 8'h00))
begin
spc0_atm_cntr2 <= spc0_atm_cntr2 + 1;
spc0_atm2_d <= 1'b1;
end
else if( spc0_atm2_d && (|spc0_stb_state_vld2))
begin
spc0_atm_cntr2 <= spc0_atm_cntr2 + 1;
spc0_atm2_d <= spc0_atm2_d;
end
else
begin
spc0_atm_cntr2 <= spc0_atm_cntr2;
spc0_atm2_d <= spc0_atm2_d;
end
if( ( ~(|spc0_stb_state_vld3) && (spc0_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_atm_cntr3 <= 9'h000;
spc0_atm3_d <= 1'b0;
end
else if( spc0_atomic_g && (spc0_atm_type3 != 8'h00))
begin
spc0_atm_cntr3 <= spc0_atm_cntr3 + 1;
spc0_atm3_d <= 1'b1;
end
else if( spc0_atm3_d && (|spc0_stb_state_vld3))
begin
spc0_atm_cntr3 <= spc0_atm_cntr3 + 1;
spc0_atm3_d <= spc0_atm3_d;
end
else
begin
spc0_atm_cntr3 <= spc0_atm_cntr3;
spc0_atm3_d <= spc0_atm3_d;
end
end
assign spc0_raw_ack_capture0 = spc0_stb_ack_vld0 && (spc0_stb_ack_cntr0 != 9'h000);
assign spc0_stb_ced0 = |spc0_stb_state_ced0;
assign spc0_raw_ack_capture1 = spc0_stb_ack_vld1 && (spc0_stb_ack_cntr1 != 9'h000);
assign spc0_stb_ced1 = |spc0_stb_state_ced1;
assign spc0_raw_ack_capture2 = spc0_stb_ack_vld2 && (spc0_stb_ack_cntr2 != 9'h000);
assign spc0_stb_ced2 = |spc0_stb_state_ced2;
assign spc0_raw_ack_capture3 = spc0_stb_ack_vld3 && (spc0_stb_ack_cntr3 != 9'h000);
assign spc0_stb_ced3 = |spc0_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc0_stb_ced0 && (spc0_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_stb_ced_cntr0 <= 9'h000;
spc0_stb_ced0_d <= 1'b0;
end
else if( spc0_stb_ced0 && (spc0_stb_state_ack0 == 8'h00))
begin
spc0_stb_ced_cntr0 <= spc0_stb_ced_cntr0 + 1;
spc0_stb_ced0_d <= spc0_stb_ced0;
end
else
begin
spc0_stb_ced_cntr0 <= spc0_stb_ced_cntr0;
spc0_stb_ced0_d <= spc0_stb_ced0_d;
end
if( ( ~spc0_mbar_vld0 && (spc0_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_mbar_vld_cntr0 <= 9'h000;
spc0_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_mbar_vld_counter = %d", spc0_mbar_vld_cntr0);
end
else if( spc0_mbar_vld0)
begin
spc0_mbar_vld_cntr0 <= spc0_mbar_vld_cntr0 + 1;
spc0_mbar_vld_d0 <= spc0_mbar_vld0;
end
else
begin
spc0_mbar_vld_cntr0 <= spc0_mbar_vld_cntr0;
spc0_mbar_vld_d0 <= spc0_mbar_vld0;
end
if( ( ~spc0_flsh_vld0 && (spc0_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_flsh_vld_cntr0 <= 9'h000;
spc0_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_flsh_vld_counter = %d", spc0_flsh_vld_cntr0);
end
else if( spc0_flsh_vld0)
begin
spc0_flsh_vld_cntr0 <= spc0_flsh_vld_cntr0 + 1;
spc0_flsh_vld_d0 <= spc0_flsh_vld0;
end
else
begin
spc0_flsh_vld_cntr0 <= spc0_flsh_vld_cntr0;
spc0_flsh_vld_d0 <= spc0_flsh_vld0;
end
if( ( ~spc0_stb_ced1 && (spc0_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_stb_ced_cntr1 <= 9'h000;
spc0_stb_ced1_d <= 1'b0;
end
else if( spc0_stb_ced1 && (spc0_stb_state_ack1 == 8'h00))
begin
spc0_stb_ced_cntr1 <= spc0_stb_ced_cntr1 + 1;
spc0_stb_ced1_d <= spc0_stb_ced1;
end
else
begin
spc0_stb_ced_cntr1 <= spc0_stb_ced_cntr1;
spc0_stb_ced1_d <= spc0_stb_ced1_d;
end
if( ( ~spc0_mbar_vld1 && (spc0_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_mbar_vld_cntr1 <= 9'h000;
spc0_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_mbar_vld_counter = %d", spc0_mbar_vld_cntr1);
end
else if( spc0_mbar_vld1)
begin
spc0_mbar_vld_cntr1 <= spc0_mbar_vld_cntr1 + 1;
spc0_mbar_vld_d1 <= spc0_mbar_vld1;
end
else
begin
spc0_mbar_vld_cntr1 <= spc0_mbar_vld_cntr1;
spc0_mbar_vld_d1 <= spc0_mbar_vld1;
end
if( ( ~spc0_flsh_vld1 && (spc0_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_flsh_vld_cntr1 <= 9'h000;
spc0_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_flsh_vld_counter = %d", spc0_flsh_vld_cntr1);
end
else if( spc0_flsh_vld1)
begin
spc0_flsh_vld_cntr1 <= spc0_flsh_vld_cntr1 + 1;
spc0_flsh_vld_d1 <= spc0_flsh_vld1;
end
else
begin
spc0_flsh_vld_cntr1 <= spc0_flsh_vld_cntr1;
spc0_flsh_vld_d1 <= spc0_flsh_vld1;
end
if( ( ~spc0_stb_ced2 && (spc0_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_stb_ced_cntr2 <= 9'h000;
spc0_stb_ced2_d <= 1'b0;
end
else if( spc0_stb_ced2 && (spc0_stb_state_ack2 == 8'h00))
begin
spc0_stb_ced_cntr2 <= spc0_stb_ced_cntr2 + 1;
spc0_stb_ced2_d <= spc0_stb_ced2;
end
else
begin
spc0_stb_ced_cntr2 <= spc0_stb_ced_cntr2;
spc0_stb_ced2_d <= spc0_stb_ced2_d;
end
if( ( ~spc0_mbar_vld2 && (spc0_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_mbar_vld_cntr2 <= 9'h000;
spc0_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_mbar_vld_counter = %d", spc0_mbar_vld_cntr2);
end
else if( spc0_mbar_vld2)
begin
spc0_mbar_vld_cntr2 <= spc0_mbar_vld_cntr2 + 1;
spc0_mbar_vld_d2 <= spc0_mbar_vld2;
end
else
begin
spc0_mbar_vld_cntr2 <= spc0_mbar_vld_cntr2;
spc0_mbar_vld_d2 <= spc0_mbar_vld2;
end
if( ( ~spc0_flsh_vld2 && (spc0_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_flsh_vld_cntr2 <= 9'h000;
spc0_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_flsh_vld_counter = %d", spc0_flsh_vld_cntr2);
end
else if( spc0_flsh_vld2)
begin
spc0_flsh_vld_cntr2 <= spc0_flsh_vld_cntr2 + 1;
spc0_flsh_vld_d2 <= spc0_flsh_vld2;
end
else
begin
spc0_flsh_vld_cntr2 <= spc0_flsh_vld_cntr2;
spc0_flsh_vld_d2 <= spc0_flsh_vld2;
end
if( ( ~spc0_stb_ced3 && (spc0_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_stb_ced_cntr3 <= 9'h000;
spc0_stb_ced3_d <= 1'b0;
end
else if( spc0_stb_ced3 && (spc0_stb_state_ack3 == 8'h00))
begin
spc0_stb_ced_cntr3 <= spc0_stb_ced_cntr3 + 1;
spc0_stb_ced3_d <= spc0_stb_ced3;
end
else
begin
spc0_stb_ced_cntr3 <= spc0_stb_ced_cntr3;
spc0_stb_ced3_d <= spc0_stb_ced3_d;
end
if( ( ~spc0_mbar_vld3 && (spc0_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_mbar_vld_cntr3 <= 9'h000;
spc0_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_mbar_vld_counter = %d", spc0_mbar_vld_cntr3);
end
else if( spc0_mbar_vld3)
begin
spc0_mbar_vld_cntr3 <= spc0_mbar_vld_cntr3 + 1;
spc0_mbar_vld_d3 <= spc0_mbar_vld3;
end
else
begin
spc0_mbar_vld_cntr3 <= spc0_mbar_vld_cntr3;
spc0_mbar_vld_d3 <= spc0_mbar_vld3;
end
if( ( ~spc0_flsh_vld3 && (spc0_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_flsh_vld_cntr3 <= 9'h000;
spc0_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_flsh_vld_counter = %d", spc0_flsh_vld_cntr3);
end
else if( spc0_flsh_vld3)
begin
spc0_flsh_vld_cntr3 <= spc0_flsh_vld_cntr3 + 1;
spc0_flsh_vld_d3 <= spc0_flsh_vld3;
end
else
begin
spc0_flsh_vld_cntr3 <= spc0_flsh_vld_cntr3;
spc0_flsh_vld_d3 <= spc0_flsh_vld3;
end
end
always @(spc0_flsh_vld_d0 or spc0_flsh_vld0)
begin
if (spc0_flsh_vld_d0 && ~spc0_flsh_vld0)
spc0_flsh_vld_capture0 <= 1'b1;
else
spc0_flsh_vld_capture0 <= 1'b0;
end
always @(spc0_flsh_vld_d1 or spc0_flsh_vld1)
begin
if (spc0_flsh_vld_d1 && ~spc0_flsh_vld1)
spc0_flsh_vld_capture1 <= 1'b1;
else
spc0_flsh_vld_capture1 <= 1'b0;
end
always @(spc0_flsh_vld_d2 or spc0_flsh_vld2)
begin
if (spc0_flsh_vld_d2 && ~spc0_flsh_vld2)
spc0_flsh_vld_capture2 <= 1'b1;
else
spc0_flsh_vld_capture2 <= 1'b0;
end
always @(spc0_flsh_vld_d3 or spc0_flsh_vld3)
begin
if (spc0_flsh_vld_d3 && ~spc0_flsh_vld3)
spc0_flsh_vld_capture3 <= 1'b1;
else
spc0_flsh_vld_capture3 <= 1'b0;
end
always @(spc0_lmiss_pa0 or spc0_imiss_pa or spc0_imiss_vld_d or spc0_lmiss_vld0)
begin
if((spc0_lmiss_pa0 == spc0_imiss_pa) && spc0_imiss_vld_d && spc0_lmiss_vld0)
spc0_lmiss_eq0 = 1'b1;
else
spc0_lmiss_eq0 = 1'b0;
end
always @(spc0_lmiss_pa1 or spc0_imiss_pa or spc0_imiss_vld_d or spc0_lmiss_vld1)
begin
if((spc0_lmiss_pa1 == spc0_imiss_pa) && spc0_imiss_vld_d && spc0_lmiss_vld1)
spc0_lmiss_eq1 = 1'b1;
else
spc0_lmiss_eq1 = 1'b0;
end
always @(spc0_lmiss_pa2 or spc0_imiss_pa or spc0_imiss_vld_d or spc0_lmiss_vld2)
begin
if((spc0_lmiss_pa2 == spc0_imiss_pa) && spc0_imiss_vld_d && spc0_lmiss_vld2)
spc0_lmiss_eq2 = 1'b1;
else
spc0_lmiss_eq2 = 1'b0;
end
always @(spc0_lmiss_pa3 or spc0_imiss_pa or spc0_imiss_vld_d or spc0_lmiss_vld3)
begin
if((spc0_lmiss_pa3 == spc0_imiss_pa) && spc0_imiss_vld_d && spc0_lmiss_vld3)
spc0_lmiss_eq3 = 1'b1;
else
spc0_lmiss_eq3 = 1'b0;
end
always @(spc0_lmiss_pa0 or spc0_stb_atm_addr0 or spc0_atm_cntr0 or spc0_lmiss_vld0)
begin
if ( ((spc0_lmiss_pa0 == spc0_stb_atm_addr0) && (spc0_atm_cntr0 != 9'h000) && spc0_lmiss_vld0) ||
((spc0_lmiss_pa1 == spc0_stb_atm_addr0) && (spc0_atm_cntr0 != 9'h000) && spc0_lmiss_vld1) ||
((spc0_lmiss_pa2 == spc0_stb_atm_addr0) && (spc0_atm_cntr0 != 9'h000) && spc0_lmiss_vld2) ||
((spc0_lmiss_pa3 == spc0_stb_atm_addr0) && (spc0_atm_cntr0 != 9'h000) && spc0_lmiss_vld3) )
spc0_atm_lmiss_eq0 = 1'b1;
else
spc0_atm_lmiss_eq0 = 1'b0;
end
always @(spc0_lmiss_pa1 or spc0_stb_atm_addr1 or spc0_atm_cntr1 or spc0_lmiss_vld1)
begin
if ( ((spc0_lmiss_pa0 == spc0_stb_atm_addr1) && (spc0_atm_cntr1 != 9'h000) && spc0_lmiss_vld0) ||
((spc0_lmiss_pa1 == spc0_stb_atm_addr1) && (spc0_atm_cntr1 != 9'h000) && spc0_lmiss_vld1) ||
((spc0_lmiss_pa2 == spc0_stb_atm_addr1) && (spc0_atm_cntr1 != 9'h000) && spc0_lmiss_vld2) ||
((spc0_lmiss_pa3 == spc0_stb_atm_addr1) && (spc0_atm_cntr1 != 9'h000) && spc0_lmiss_vld3) )
spc0_atm_lmiss_eq1 = 1'b1;
else
spc0_atm_lmiss_eq1 = 1'b0;
end
always @(spc0_lmiss_pa2 or spc0_stb_atm_addr2 or spc0_atm_cntr2 or spc0_lmiss_vld2)
begin
if ( ((spc0_lmiss_pa0 == spc0_stb_atm_addr2) && (spc0_atm_cntr2 != 9'h000) && spc0_lmiss_vld0) ||
((spc0_lmiss_pa1 == spc0_stb_atm_addr2) && (spc0_atm_cntr2 != 9'h000) && spc0_lmiss_vld1) ||
((spc0_lmiss_pa2 == spc0_stb_atm_addr2) && (spc0_atm_cntr2 != 9'h000) && spc0_lmiss_vld2) ||
((spc0_lmiss_pa3 == spc0_stb_atm_addr2) && (spc0_atm_cntr2 != 9'h000) && spc0_lmiss_vld3) )
spc0_atm_lmiss_eq2 = 1'b1;
else
spc0_atm_lmiss_eq2 = 1'b0;
end
always @(spc0_lmiss_pa3 or spc0_stb_atm_addr3 or spc0_atm_cntr3 or spc0_lmiss_vld3)
begin
if ( ((spc0_lmiss_pa0 == spc0_stb_atm_addr3) && (spc0_atm_cntr3 != 9'h000) && spc0_lmiss_vld0) ||
((spc0_lmiss_pa1 == spc0_stb_atm_addr3) && (spc0_atm_cntr3 != 9'h000) && spc0_lmiss_vld1) ||
((spc0_lmiss_pa2 == spc0_stb_atm_addr3) && (spc0_atm_cntr3 != 9'h000) && spc0_lmiss_vld2) ||
((spc0_lmiss_pa3 == spc0_stb_atm_addr3) && (spc0_atm_cntr3 != 9'h000) && spc0_lmiss_vld3) )
spc0_atm_lmiss_eq3 = 1'b1;
else
spc0_atm_lmiss_eq3 = 1'b0;
end
always @(spc0_imiss_pa or spc0_stb_atm_addr0 or spc0_atm_cntr0 or spc0_imiss_vld_d)
begin
if((spc0_imiss_pa == spc0_stb_atm_addr0) && (spc0_atm_cntr0 != 9'h000) && spc0_imiss_vld_d)
spc0_atm_imiss_eq0 = 1'b1;
else
spc0_atm_imiss_eq0 = 1'b0;
end
always @(spc0_imiss_pa or spc0_stb_atm_addr1 or spc0_atm_cntr1 or spc0_imiss_vld_d)
begin
if((spc0_imiss_pa == spc0_stb_atm_addr1) && (spc0_atm_cntr1 != 9'h000) && spc0_imiss_vld_d)
spc0_atm_imiss_eq1 = 1'b1;
else
spc0_atm_imiss_eq1 = 1'b0;
end
always @(spc0_imiss_pa or spc0_stb_atm_addr2 or spc0_atm_cntr2 or spc0_imiss_vld_d)
begin
if((spc0_imiss_pa == spc0_stb_atm_addr2) && (spc0_atm_cntr2 != 9'h000) && spc0_imiss_vld_d)
spc0_atm_imiss_eq2 = 1'b1;
else
spc0_atm_imiss_eq2 = 1'b0;
end
always @(spc0_imiss_pa or spc0_stb_atm_addr3 or spc0_atm_cntr3 or spc0_imiss_vld_d)
begin
if((spc0_imiss_pa == spc0_stb_atm_addr3) && (spc0_atm_cntr3 != 9'h000) && spc0_imiss_vld_d)
spc0_atm_imiss_eq3 = 1'b1;
else
spc0_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc0_imiss_vld || ~rst_l)
spc0_imiss_vld_d <= 1'b0;
else
spc0_imiss_vld_d <= spc0_imiss_vld;
if( ~spc0_ld_miss || ~rst_l)
spc0_ld_miss_capture <= 1'b0;
else
spc0_ld_miss_capture <= spc0_ld_miss;
end
always @(spc0_stb_ced0 or spc0_stb_ced0_d)
begin
if (~spc0_stb_ced0 && spc0_stb_ced0_d)
spc0_stb_ced_capture0 <= 1'b1;
else
spc0_stb_ced_capture0 <= 1'b0;
end
always @(spc0_stb_ced1 or spc0_stb_ced1_d)
begin
if (~spc0_stb_ced1 && spc0_stb_ced1_d)
spc0_stb_ced_capture1 <= 1'b1;
else
spc0_stb_ced_capture1 <= 1'b0;
end
always @(spc0_stb_ced2 or spc0_stb_ced2_d)
begin
if (~spc0_stb_ced2 && spc0_stb_ced2_d)
spc0_stb_ced_capture2 <= 1'b1;
else
spc0_stb_ced_capture2 <= 1'b0;
end
always @(spc0_stb_ced3 or spc0_stb_ced3_d)
begin
if (~spc0_stb_ced3 && spc0_stb_ced3_d)
spc0_stb_ced_capture3 <= 1'b1;
else
spc0_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc0_stb_state_ack0 != 8'h00 && (spc0_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_ack_counter0 = %d", spc0_stb_ack_cntr0);
end
else if(spc0_stb_cam_hit && spc0_ld0_inst_vld_g && (spc0_stb_state_ack0 == 8'h00))
begin
spc0_stb_ack_cntr0 <= spc0_stb_ack_cntr0 + 1;
end
else if( (spc0_stb_state_ack0 == 8'h00 ) && (spc0_stb_ack_cntr0 != 9'h000))
begin
spc0_stb_ack_cntr0 <= spc0_stb_ack_cntr0 + 1;
end // if ( (spc0_stb_state_ack0 == 8'h00 ) && (spc0_stb_ack_cntr0 != 9'h000))
else
begin
spc0_stb_ack_cntr0 <= spc0_stb_ack_cntr0;
end
if( (spc0_stb_state_ack1 != 8'h00 && (spc0_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_ack_counter1 = %d", spc0_stb_ack_cntr1);
end
else if(spc0_stb_cam_hit && spc0_ld1_inst_vld_g && (spc0_stb_state_ack1 == 8'h00))
begin
spc0_stb_ack_cntr1 <= spc0_stb_ack_cntr1 + 1;
end
else if( (spc0_stb_state_ack1 == 8'h00 ) && (spc0_stb_ack_cntr1 != 9'h000))
begin
spc0_stb_ack_cntr1 <= spc0_stb_ack_cntr1 + 1;
end // if ( (spc0_stb_state_ack1 == 8'h00 ) && (spc0_stb_ack_cntr1 != 9'h000))
else
begin
spc0_stb_ack_cntr1 <= spc0_stb_ack_cntr1;
end
if( (spc0_stb_state_ack2 != 8'h00 && (spc0_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_ack_counter2 = %d", spc0_stb_ack_cntr2);
end
else if(spc0_stb_cam_hit && spc0_ld2_inst_vld_g && (spc0_stb_state_ack2 == 8'h00))
begin
spc0_stb_ack_cntr2 <= spc0_stb_ack_cntr2 + 1;
end
else if( (spc0_stb_state_ack2 == 8'h00 ) && (spc0_stb_ack_cntr2 != 9'h000))
begin
spc0_stb_ack_cntr2 <= spc0_stb_ack_cntr2 + 1;
end // if ( (spc0_stb_state_ack2 == 8'h00 ) && (spc0_stb_ack_cntr2 != 9'h000))
else
begin
spc0_stb_ack_cntr2 <= spc0_stb_ack_cntr2;
end
if( (spc0_stb_state_ack3 != 8'h00 && (spc0_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_ack_counter3 = %d", spc0_stb_ack_cntr3);
end
else if(spc0_stb_cam_hit && spc0_ld3_inst_vld_g && (spc0_stb_state_ack3 == 8'h00))
begin
spc0_stb_ack_cntr3 <= spc0_stb_ack_cntr3 + 1;
end
else if( (spc0_stb_state_ack3 == 8'h00 ) && (spc0_stb_ack_cntr3 != 9'h000))
begin
spc0_stb_ack_cntr3 <= spc0_stb_ack_cntr3 + 1;
end // if ( (spc0_stb_state_ack3 == 8'h00 ) && (spc0_stb_ack_cntr3 != 9'h000))
else
begin
spc0_stb_ack_cntr3 <= spc0_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc0_stb0_full_w2 or spc0_stb0_full)
begin
if (~spc0_stb0_full_w2 && spc0_stb0_full)
spc0_stb_full_capture0 <= 1'b1;
else
spc0_stb_full_capture0 <= 1'b0;
end
always @(spc0_stb1_full_w2 or spc0_stb1_full)
begin
if (~spc0_stb1_full_w2 && spc0_stb1_full)
spc0_stb_full_capture1 <= 1'b1;
else
spc0_stb_full_capture1 <= 1'b0;
end
always @(spc0_stb2_full_w2 or spc0_stb2_full)
begin
if (~spc0_stb2_full_w2 && spc0_stb2_full)
spc0_stb_full_capture2 <= 1'b1;
else
spc0_stb_full_capture2 <= 1'b0;
end
always @(spc0_stb3_full_w2 or spc0_stb3_full)
begin
if (~spc0_stb3_full_w2 && spc0_stb3_full)
spc0_stb_full_capture3 <= 1'b1;
else
spc0_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc0_stb0_full && (spc0_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_full_counter0 = %d", spc0_stb_full_cntr0);
end
else if( spc0_stb0_full)
begin
spc0_stb_full_cntr0 <= spc0_stb_full_cntr0 + 1;
end
else
begin
spc0_stb_full_cntr0 <= spc0_stb_full_cntr0;
end
if( ( ~spc0_stb1_full && (spc0_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_full_counter1 = %d", spc0_stb_full_cntr1);
end
else if( spc0_stb1_full)
begin
spc0_stb_full_cntr1 <= spc0_stb_full_cntr1 + 1;
end
else
begin
spc0_stb_full_cntr1 <= spc0_stb_full_cntr1;
end
if( ( ~spc0_stb2_full && (spc0_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_full_counter2 = %d", spc0_stb_full_cntr2);
end
else if( spc0_stb2_full)
begin
spc0_stb_full_cntr2 <= spc0_stb_full_cntr2 + 1;
end
else
begin
spc0_stb_full_cntr2 <= spc0_stb_full_cntr2;
end
if( ( ~spc0_stb3_full && (spc0_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc0_stb_full_counter3 = %d", spc0_stb_full_cntr3);
end
else if( spc0_stb3_full)
begin
spc0_stb_full_cntr3 <= spc0_stb_full_cntr3 + 1;
end
else
begin
spc0_stb_full_cntr3 <= spc0_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc0_lmq0_full_d or spc0_lmq0_full)
begin
if (spc0_lmq0_full_d && ~spc0_lmq0_full)
spc0_lmq_full_capture0 <= 1'b1;
else
spc0_lmq_full_capture0 <= 1'b0;
end
always @(spc0_lmq1_full_d or spc0_lmq1_full)
begin
if (spc0_lmq1_full_d && ~spc0_lmq1_full)
spc0_lmq_full_capture1 <= 1'b1;
else
spc0_lmq_full_capture1 <= 1'b0;
end
always @(spc0_lmq2_full_d or spc0_lmq2_full)
begin
if (spc0_lmq2_full_d && ~spc0_lmq2_full)
spc0_lmq_full_capture2 <= 1'b1;
else
spc0_lmq_full_capture2 <= 1'b0;
end
always @(spc0_lmq3_full_d or spc0_lmq3_full)
begin
if (spc0_lmq3_full_d && ~spc0_lmq3_full)
spc0_lmq_full_capture3 <= 1'b1;
else
spc0_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc0_lmq0_full && (spc0_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc0_lmq_full_cntr0 <= 9'h000;
spc0_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_lmq_full_counter0 = %d", spc0_lmq_full_cntr0);
end
else if( spc0_lmq0_full)
begin
spc0_lmq_full_cntr0 <= spc0_lmq_full_cntr0 + 1;
spc0_lmq0_full_d <= spc0_lmq0_full;
end
else
begin
spc0_lmq_full_cntr0 <= spc0_lmq_full_cntr0;
spc0_lmq0_full_d <= spc0_lmq0_full;
end
if( ( ~spc0_lmq1_full && (spc0_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc0_lmq_full_cntr1 <= 9'h000;
spc0_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_lmq_full_counter1 = %d", spc0_lmq_full_cntr1);
end
else if( spc0_lmq1_full)
begin
spc0_lmq_full_cntr1 <= spc0_lmq_full_cntr1 + 1;
spc0_lmq1_full_d <= spc0_lmq1_full;
end
else
begin
spc0_lmq_full_cntr1 <= spc0_lmq_full_cntr1;
spc0_lmq1_full_d <= spc0_lmq1_full;
end
if( ( ~spc0_lmq2_full && (spc0_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc0_lmq_full_cntr2 <= 9'h000;
spc0_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_lmq_full_counter2 = %d", spc0_lmq_full_cntr2);
end
else if( spc0_lmq2_full)
begin
spc0_lmq_full_cntr2 <= spc0_lmq_full_cntr2 + 1;
spc0_lmq2_full_d <= spc0_lmq2_full;
end
else
begin
spc0_lmq_full_cntr2 <= spc0_lmq_full_cntr2;
spc0_lmq2_full_d <= spc0_lmq2_full;
end
if( ( ~spc0_lmq3_full && (spc0_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc0_lmq_full_cntr3 <= 9'h000;
spc0_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_lmq_full_counter3 = %d", spc0_lmq_full_cntr3);
end
else if( spc0_lmq3_full)
begin
spc0_lmq_full_cntr3 <= spc0_lmq_full_cntr3 + 1;
spc0_lmq3_full_d <= spc0_lmq3_full;
end
else
begin
spc0_lmq_full_cntr3 <= spc0_lmq_full_cntr3;
spc0_lmq3_full_d <= spc0_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc0_dfq_full_d or spc0_dfq_full)
begin
if (spc0_dfq_full_d && ~spc0_dfq_full)
spc0_dfq_full_capture <= 1'b1;
else
spc0_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc0_dfq_full && (spc0_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc0_dfq_full_cntr <= 9'h000;
spc0_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dfq_full_counter = %d", spc0_dfq_full_cntr);
end
else if( spc0_dfq_full)
begin
spc0_dfq_full_cntr <= spc0_dfq_full_cntr + 1;
spc0_dfq_full_d <= spc0_dfq_full;
end
else
begin
spc0_dfq_full_cntr <= spc0_dfq_full_cntr;
spc0_dfq_full_d <= spc0_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc0_dva_full_d or spc0_dva_inv)
begin
if (spc0_dva_full_d && ~spc0_dva_inv)
spc0_dva_full_capture <= 1'b1;
else
spc0_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc0_dva_din && spc0_dva_wen)
begin
spc0_dva_inv <= 1'b1;
spc0_dva_waddr_d <= spc0_dva_waddr;
end
else if(~spc0_dva_din && spc0_dva_wen)
begin
spc0_dva_inv <= 1'b0;
spc0_dva_waddr_d <= 5'b00000;
end
else
begin
spc0_dva_inv <= spc0_dva_inv;
spc0_dva_waddr_d <= spc0_dva_waddr_d;
end
end
always @(spc0_dva_raddr or spc0_dva_ren or spc0_dva_inv)
begin
if (spc0_dva_inv && spc0_dva_ren && (spc0_dva_raddr[6:2] == spc0_dva_waddr_d))
spc0_dva_vld2lkup <= 1'b1;
else
spc0_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc0_dva_inv && (spc0_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc0_dva_full_cntr <= 9'h000;
spc0_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dva_full_counter = %d", spc0_dva_full_cntr);
end
else if( spc0_dva_inv)
begin
spc0_dva_full_cntr <= spc0_dva_full_cntr + 1;
spc0_dva_full_d <= spc0_dva_inv;
end
else
begin
spc0_dva_full_cntr <= spc0_dva_full_cntr;
spc0_dva_full_d <= spc0_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc0_dva_vfull_d or spc0_dva_vld)
begin
if (spc0_dva_vfull_d && ~spc0_dva_vld)
spc0_dva_vfull_capture <= 1'b1;
else
spc0_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc0_dva_din && spc0_dva_wen)
begin
spc0_dva_vld <= 1'b1;
spc0_dva_invwaddr_d <= spc0_dva_waddr;
spc0_dva_invld_err <= spc0_dva_inv_perror;
end
else if(spc0_dva_din && spc0_dva_wen)
begin
spc0_dva_vld <= 1'b0;
spc0_dva_invwaddr_d <= 5'b00000;
spc0_dva_invld_err <= 1'b0;
end
else
begin
spc0_dva_vld <= spc0_dva_vld;
spc0_dva_invwaddr_d <= spc0_dva_invwaddr_d;
spc0_dva_invld_err <= spc0_dva_invld_err;
end
end
always @(spc0_dva_raddr or spc0_dva_ren or spc0_dva_vld)
begin
if (spc0_dva_vld && spc0_dva_ren && (spc0_dva_raddr[6:2] == spc0_dva_waddr_d))
spc0_dva_invld2lkup <= 1'b1;
else
spc0_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc0_dva_vld && (spc0_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc0_dva_vfull_cntr <= 9'h000;
spc0_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc0_dva_vfull_counter = %d", spc0_dva_vfull_cntr);
end
else if( spc0_dva_vld)
begin
spc0_dva_vfull_cntr <= spc0_dva_vfull_cntr + 1;
spc0_dva_vfull_d <= spc0_dva_vld;
end
else
begin
spc0_dva_vfull_cntr <= spc0_dva_vfull_cntr;
spc0_dva_vfull_d <= spc0_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc0_dva_raddr or spc0_dva_waddr or spc0_dva_ren or spc0_dva_wen)
begin
if ( spc0_dva_ren && spc0_dva_wen && (spc0_dva_raddr[6:2] == spc0_dva_waddr))
spc0_dva_collide <= 1'b1;
else
spc0_dva_collide <= 1'b0;
end
// dva error cases
always @(spc0_dva_raddr or spc0_dva_ren or spc0_dva_dtag_perror or spc0_dva_dtag_perror)
begin
if (spc0_dva_ren && (spc0_dva_dtag_perror || spc0_dva_dtag_perror))
spc0_dva_err <= 1'b1;
else
spc0_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc0_dva_err)
spc0_dva_efull_d <= 1'b1;
else
spc0_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc0_dva_ren && ~(spc0_dva_dtag_perror || spc0_dva_dtag_perror ) &&
(spc0_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc0_dva_efull_cntr <= 9'h000;
spc0_dva_raddr_d <= spc0_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc0_dva_efull_counter = %d", spc0_dva_efull_cntr);
end
else if(spc0_dva_efull_d)
begin
spc0_dva_efull_cntr <= spc0_dva_efull_cntr + 1;
spc0_dva_raddr_d <= spc0_dva_raddr_d;
end
else
begin
spc0_dva_efull_cntr <= spc0_dva_efull_cntr;
spc0_dva_raddr_d <= spc0_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC1
wire spc1_dva_ren = `TOP_DESIGN.sparc1.lsu.ifu_lsu_ld_inst_e;
wire spc1_dva_wen = `TOP_DESIGN.sparc1.lsu.lsu_dtagv_wr_vld_e;
wire spc1_dva_din = `TOP_DESIGN.sparc1.lsu.dva_din_e;
wire [3:0] spc1_dva_dout = `TOP_DESIGN.sparc1.lsu.dva_vld_m[3:0];
wire [6:0] spc1_dva_raddr = `TOP_DESIGN.sparc1.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc1_dva_waddr = `TOP_DESIGN.sparc1.lsu.dva_wr_adr_e[10:6];
wire spc1_dva_dtag_perror = `TOP_DESIGN.sparc1.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc1_dva_dcache_perror = `TOP_DESIGN.sparc1.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc1_dva_inv_perror = `TOP_DESIGN.sparc1.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc1_ld_miss = `TOP_DESIGN.sparc1.lsu.dctl.lsu_ld_miss_wb;
reg spc1_ld_miss_capture;
wire spc1_atomic_g = `TOP_DESIGN.sparc1.lsu.qctl1.atomic_g;
wire [1:0] spc1_atm_type0 = `TOP_DESIGN.sparc1.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc1_atm_type1 = `TOP_DESIGN.sparc1.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc1_atm_type2 = `TOP_DESIGN.sparc1.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc1_atm_type3 = `TOP_DESIGN.sparc1.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc1_dctl_lsu_way_hit = `TOP_DESIGN.sparc1.lsu.dctl.lsu_way_hit;
wire spc1_dctl_dcache_enable_g = `TOP_DESIGN.sparc1.lsu.dctl.dcache_enable_g;
wire spc1_dctl_ldxa_internal = `TOP_DESIGN.sparc1.lsu.dctl.ldxa_internal;
wire spc1_dctl_ldst_dbl_g = `TOP_DESIGN.sparc1.lsu.dctl.ldst_dbl_g;
wire spc1_dctl_atomic_g = `TOP_DESIGN.sparc1.lsu.dctl.atomic_g;
wire spc1_dctl_stb_cam_hit = `TOP_DESIGN.sparc1.lsu.dctl.stb_cam_hit;
wire spc1_dctl_endian_mispred_g = `TOP_DESIGN.sparc1.lsu.dctl.endian_mispred_g;
wire spc1_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc1.lsu.dctl.dcache_rd_parity_error;
wire spc1_dctl_dtag_perror_g = `TOP_DESIGN.sparc1.lsu.dctl.dtag_perror_g;
wire spc1_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc1.lsu.dctl.tte_data_perror_unc;
wire spc1_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc1.lsu.dctl.ld_inst_vld_g;
wire spc1_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc1.lsu.dctl.lsu_alt_space_g;
wire spc1_dctl_recognized_asi_g = `TOP_DESIGN.sparc1.lsu.dctl.recognized_asi_g;
wire spc1_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc1.lsu.dctl.ncache_asild_rq_g ;
wire spc1_dctl_bld_hit;
wire spc1_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc1_ixinv0 = `TOP_DESIGN.sparc1.lsu.qctl2.imiss0_inv_en;
wire spc1_ixinv1 = `TOP_DESIGN.sparc1.lsu.qctl2.imiss1_inv_en;
wire spc1_ixinv2 = `TOP_DESIGN.sparc1.lsu.qctl2.imiss2_inv_en;
wire spc1_ixinv3 = `TOP_DESIGN.sparc1.lsu.qctl2.imiss3_inv_en;
wire spc1_ifill = `TOP_DESIGN.sparc1.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc1_inv = `TOP_DESIGN.sparc1.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc1_inv_clr = `TOP_DESIGN.sparc1.lsu.qctl2.ifu_lsu_inv_clear;
wire spc1_ibuf_busy = `TOP_DESIGN.sparc1.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc1_l2 = `TOP_DESIGN.sparc1.lsu.dctl.l2fill_vld_g ;
wire spc1_unc = `TOP_DESIGN.sparc1.lsu.dctl.unc_err_trap_g ;
wire spc1_fpld = `TOP_DESIGN.sparc1.lsu.dctl.l2fill_fpld_g ;
wire spc1_fpldst = `TOP_DESIGN.sparc1.lsu.dctl.fp_ldst_g ;
wire spc1_unflush = `TOP_DESIGN.sparc1.lsu.dctl.ld_inst_vld_unflushed ;
wire spc1_ldw = `TOP_DESIGN.sparc1.lsu.dctl.lsu_inst_vld_w ;
wire spc1_byp = `TOP_DESIGN.sparc1.lsu.dctl.intld_byp_data_vld_m ;
wire spc1_flsh = `TOP_DESIGN.sparc1.lsu.lsu_exu_flush_pipe_w ;
wire spc1_chm = `TOP_DESIGN.sparc1.lsu.dctl.common_ldst_miss_w ;
wire spc1_ldxa = `TOP_DESIGN.sparc1.lsu.dctl.ldxa_internal ;
wire spc1_ato = `TOP_DESIGN.sparc1.lsu.dctl.atomic_g ;
wire spc1_pref = `TOP_DESIGN.sparc1.lsu.dctl.pref_inst_g ;
wire spc1_chit = `TOP_DESIGN.sparc1.lsu.dctl.stb_cam_hit ;
wire spc1_dcp = `TOP_DESIGN.sparc1.lsu.dctl.dcache_rd_parity_error ;
wire spc1_dtp = `TOP_DESIGN.sparc1.lsu.dctl.dtag_perror_g ;
//wire spc1_mpc = `TOP_DESIGN.sparc1.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc1_mpc = 1'b0;
wire spc1_mpu = `TOP_DESIGN.sparc1.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc1_exu_und;
reg [4:0] spc1_exu;
// excptn
wire spc1_exp_wtchpt_trp_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc1_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc1_exp_priv_violtn_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc1_exp_daccess_excptn_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc1_exp_daccess_prot_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc1_exp_priv_action_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc1_exp_spec_access_epage_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc1_exp_uncache_atomic_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc1_exp_illegal_asi_action_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc1_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc1_exp_asi_rd_unc = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc1_exp_tlb_data_ce = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc1_exp_asi_rd_unc = 1'b0;
wire spc1_exp_tlb_data_ce = 1'b0;
wire spc1_exp_tlb_data_ue = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc1_exp_tlb_tag_ue = `TOP_DESIGN.sparc1.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc1_exp_unc = `TOP_DESIGN.sparc1.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc1_exp_corr = `TOP_DESIGN.sparc1.lsu.excpctl.tte_data_perror_corr;
wire spc1_exp_corr = 1'b0;
wire [15:0] spc1_exp_und;
reg [4:0] spc1_exp;
// dctl cmplt
wire spc1_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc1.lsu.dctl.stxa_internal_d2;
wire spc1_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc1.lsu.dctl.lsu_l2fill_vld;
wire spc1_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc1.lsu.dctl.atomic_ld_squash_e;
wire spc1_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc1.lsu.qctl2.lsu_ignore_fill;
wire spc1_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc1.lsu.dctl.l2fill_fpld_e;
// wire spc1_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc1.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc1_dctl_fill_err_trap_e = `TOP_DESIGN.sparc1.lsu.dctl.fill_err_trap_e;
wire spc1_dctl_l2_corr_error_e = `TOP_DESIGN.sparc1.lsu.dctl.l2_corr_error_e;
wire [3:0] spc1_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc1.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc1_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc1.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc1_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc1.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc1_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc1.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc1_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc1.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc1_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc1.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc1_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc1_ldstcond_cmplt_d;
wire spc1_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc1.lsu.qctl1.ld_sec_hit_thrd0;
wire spc1_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_inst_vld_g;
wire spc1_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc1_ld0_pkt_vld_unmasked_d;
reg spc1_qctl1_ld_sec_hit_thrd0_w2;
wire spc1_dctl_thread0_w3 = `TOP_DESIGN.sparc1.lsu.dctl.thread0_w3;
wire spc1_dctl_dfill_thread0 = `TOP_DESIGN.sparc1.lsu.dctl.dfill_thread0;
wire spc1_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc1.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc1_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc1.lsu.dctl.diag_wr_cmplt0;
wire spc1_dctl_bsync0_reset = `TOP_DESIGN.sparc1.lsu.dctl.bsync0_reset;
wire spc1_dctl_late_cmplt0 = `TOP_DESIGN.sparc1.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc1_dctl_stxa_cmplt0;
wire spc1_dctl_l2fill_cmplt0;
wire spc1_dctl_atm_cmplt0;
wire spc1_dctl_fillerr0;
wire [4:0] spc1_cmplt0;
wire [5:0] spc1_dctl_ldst_cond_cmplt0;
reg [3:0] spc1_ldstcond_cmplt0;
reg [3:0] spc1_ldstcond_cmplt0_d;
wire spc1_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc1.lsu.qctl1.ld_sec_hit_thrd1;
wire spc1_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_inst_vld_g;
wire spc1_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc1_ld1_pkt_vld_unmasked_d;
reg spc1_qctl1_ld_sec_hit_thrd1_w2;
wire spc1_dctl_thread1_w3 = `TOP_DESIGN.sparc1.lsu.dctl.thread1_w3;
wire spc1_dctl_dfill_thread1 = `TOP_DESIGN.sparc1.lsu.dctl.dfill_thread1;
wire spc1_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc1.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc1_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc1.lsu.dctl.diag_wr_cmplt1;
wire spc1_dctl_bsync1_reset = `TOP_DESIGN.sparc1.lsu.dctl.bsync1_reset;
wire spc1_dctl_late_cmplt1 = `TOP_DESIGN.sparc1.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc1_dctl_stxa_cmplt1;
wire spc1_dctl_l2fill_cmplt1;
wire spc1_dctl_atm_cmplt1;
wire spc1_dctl_fillerr1;
wire [4:0] spc1_cmplt1;
wire [5:0] spc1_dctl_ldst_cond_cmplt1;
reg [3:0] spc1_ldstcond_cmplt1;
reg [3:0] spc1_ldstcond_cmplt1_d;
wire spc1_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc1.lsu.qctl1.ld_sec_hit_thrd2;
wire spc1_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_inst_vld_g;
wire spc1_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc1_ld2_pkt_vld_unmasked_d;
reg spc1_qctl1_ld_sec_hit_thrd2_w2;
wire spc1_dctl_thread2_w3 = `TOP_DESIGN.sparc1.lsu.dctl.thread2_w3;
wire spc1_dctl_dfill_thread2 = `TOP_DESIGN.sparc1.lsu.dctl.dfill_thread2;
wire spc1_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc1.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc1_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc1.lsu.dctl.diag_wr_cmplt2;
wire spc1_dctl_bsync2_reset = `TOP_DESIGN.sparc1.lsu.dctl.bsync2_reset;
wire spc1_dctl_late_cmplt2 = `TOP_DESIGN.sparc1.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc1_dctl_stxa_cmplt2;
wire spc1_dctl_l2fill_cmplt2;
wire spc1_dctl_atm_cmplt2;
wire spc1_dctl_fillerr2;
wire [4:0] spc1_cmplt2;
wire [5:0] spc1_dctl_ldst_cond_cmplt2;
reg [3:0] spc1_ldstcond_cmplt2;
reg [3:0] spc1_ldstcond_cmplt2_d;
wire spc1_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc1.lsu.qctl1.ld_sec_hit_thrd3;
wire spc1_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_inst_vld_g;
wire spc1_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc1_ld3_pkt_vld_unmasked_d;
reg spc1_qctl1_ld_sec_hit_thrd3_w2;
wire spc1_dctl_thread3_w3 = `TOP_DESIGN.sparc1.lsu.dctl.thread3_w3;
wire spc1_dctl_dfill_thread3 = `TOP_DESIGN.sparc1.lsu.dctl.dfill_thread3;
wire spc1_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc1.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc1_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc1.lsu.dctl.diag_wr_cmplt3;
wire spc1_dctl_bsync3_reset = `TOP_DESIGN.sparc1.lsu.dctl.bsync3_reset;
wire spc1_dctl_late_cmplt3 = `TOP_DESIGN.sparc1.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc1_dctl_stxa_cmplt3;
wire spc1_dctl_l2fill_cmplt3;
wire spc1_dctl_atm_cmplt3;
wire spc1_dctl_fillerr3;
wire [4:0] spc1_cmplt3;
wire [5:0] spc1_dctl_ldst_cond_cmplt3;
reg [3:0] spc1_ldstcond_cmplt3;
reg [3:0] spc1_ldstcond_cmplt3_d;
wire spc1_qctl1_bld_g = `TOP_DESIGN.sparc1.lsu.qctl1.bld_g;
wire spc1_qctl1_bld_reset = `TOP_DESIGN.sparc1.lsu.qctl1.bld_reset;
wire [1:0] spc1_qctl1_bld_cnt = `TOP_DESIGN.sparc1.lsu.qctl1.bld_cnt;
reg [9:0] spc1_bld0_full_cntr;
reg [1:0] spc1_bld0_full_d;
reg spc1_bld0_full_capture;
reg [9:0] spc1_bld1_full_cntr;
reg [1:0] spc1_bld1_full_d;
reg spc1_bld1_full_capture;
reg [9:0] spc1_bld2_full_cntr;
reg [1:0] spc1_bld2_full_d;
reg spc1_bld2_full_capture;
reg [9:0] spc1_bld3_full_cntr;
reg [1:0] spc1_bld3_full_d;
reg spc1_bld3_full_capture;
wire spc1_ipick = `TOP_DESIGN.sparc1.lsu.qctl1.imiss_pcx_rq_vld;
wire spc1_lpick = `TOP_DESIGN.sparc1.lsu.qctl1.ld_pcx_rq_all;
wire spc1_spick = `TOP_DESIGN.sparc1.lsu.qctl1.st_pcx_rq_all;
wire spc1_mpick = `TOP_DESIGN.sparc1.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc1_apick = `TOP_DESIGN.sparc1.lsu.qctl1.all_pcx_rq_pick;
wire spc1_msquash = `TOP_DESIGN.sparc1.lsu.qctl1.mcycle_squash_d1;
reg spc1_fpicko;
wire [3:0] spc1_fpick;
wire [39:0] spc1_imiss_pa = `TOP_DESIGN.sparc1.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc1_imiss_vld = `TOP_DESIGN.sparc1.lsu.qctl1.imiss_pcx_rq_vld;
reg spc1_imiss_vld_d;
wire [39:0] spc1_lmiss_pa0 = `TOP_DESIGN.sparc1.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc1_lmiss_vld0 = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_pcx_rq_vld;
wire spc1_ld_pkt_vld0 = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_pkt_vld;
wire spc1_st_pkt_vld0 = `TOP_DESIGN.sparc1.lsu.qctl1.st0_pkt_vld;
reg spc1_lmiss_eq0;
reg spc1_atm_imiss_eq0;
wire [39:0] spc1_lmiss_pa1 = `TOP_DESIGN.sparc1.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc1_lmiss_vld1 = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_pcx_rq_vld;
wire spc1_ld_pkt_vld1 = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_pkt_vld;
wire spc1_st_pkt_vld1 = `TOP_DESIGN.sparc1.lsu.qctl1.st1_pkt_vld;
reg spc1_lmiss_eq1;
reg spc1_atm_imiss_eq1;
wire [39:0] spc1_lmiss_pa2 = `TOP_DESIGN.sparc1.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc1_lmiss_vld2 = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_pcx_rq_vld;
wire spc1_ld_pkt_vld2 = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_pkt_vld;
wire spc1_st_pkt_vld2 = `TOP_DESIGN.sparc1.lsu.qctl1.st2_pkt_vld;
reg spc1_lmiss_eq2;
reg spc1_atm_imiss_eq2;
wire [39:0] spc1_lmiss_pa3 = `TOP_DESIGN.sparc1.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc1_lmiss_vld3 = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_pcx_rq_vld;
wire spc1_ld_pkt_vld3 = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_pkt_vld;
wire spc1_st_pkt_vld3 = `TOP_DESIGN.sparc1.lsu.qctl1.st3_pkt_vld;
reg spc1_lmiss_eq3;
reg spc1_atm_imiss_eq3;
wire [44:0] spc1_wdata_ramc = `TOP_DESIGN.sparc1.lsu.stb_cam.wdata_ramc;
wire spc1_wptr_vld = `TOP_DESIGN.sparc1.lsu.stb_cam.wptr_vld;
wire [75:0] spc1_wdata_ramd = {`TOP_DESIGN.sparc1.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc1.lsu.lsu_stb_st_data_g[63:0]};
wire spc1_stb_cam_hit = `TOP_DESIGN.sparc1.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc1_stb_cam_hit_ptr = `TOP_DESIGN.sparc1.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc1_stb_ld_full_raw = `TOP_DESIGN.sparc1.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc1_stb_ld_partial_raw = `TOP_DESIGN.sparc1.lsu.stb_ld_partial_raw[7:0];
wire spc1_stb_cam_mhit = `TOP_DESIGN.sparc1.lsu.stb_cam_mhit;
wire [3:0] spc1_dfq_vld_entries = `TOP_DESIGN.sparc1.lsu.qctl2.dfq_vld_entries;
wire spc1_dfq_full;
reg [9:0] spc1_dfq_full_cntr;
reg spc1_dfq_full_d;
reg spc1_dfq_full_capture;
reg [9:0] spc1_dfq_full_cntr1;
reg spc1_dfq_full_d1;
wire spc1_dfq_full1;
reg spc1_dfq_full_capture1;
reg [9:0] spc1_dfq_full_cntr2;
reg spc1_dfq_full_d2;
wire spc1_dfq_full2;
reg spc1_dfq_full_capture2;
reg [9:0] spc1_dfq_full_cntr3;
reg spc1_dfq_full_d3;
wire spc1_dfq_full3;
reg spc1_dfq_full_capture3;
reg [9:0] spc1_dfq_full_cntr4;
reg spc1_dfq_full_d4;
wire spc1_dfq_full4;
reg spc1_dfq_full_capture4;
reg [9:0] spc1_dfq_full_cntr5;
reg spc1_dfq_full_d5;
wire spc1_dfq_full5;
reg spc1_dfq_full_capture5;
reg [9:0] spc1_dfq_full_cntr6;
reg spc1_dfq_full_d6;
wire spc1_dfq_full6;
reg spc1_dfq_full_capture6;
reg [9:0] spc1_dfq_full_cntr7;
reg spc1_dfq_full_d7;
wire spc1_dfq_full7;
reg spc1_dfq_full_capture7;
wire spc1_dva_rdwrhit;
reg [9:0] spc1_dva_full_cntr;
reg spc1_dva_full_d;
reg spc1_dva_full_capture;
reg spc1_dva_inv;
reg spc1_dva_inv_d;
reg spc1_dva_vld;
reg spc1_dva_vld_d;
reg [9:0] spc1_dva_vfull_cntr;
reg spc1_dva_vfull_d;
reg spc1_dva_vfull_capture;
reg spc1_dva_collide;
reg spc1_dva_vld2lkup;
reg spc1_dva_invld2lkup;
reg spc1_dva_invld_err;
reg [9:0] spc1_dva_efull_cntr;
reg spc1_dva_efull_d;
reg spc1_dva_vlddtag_err;
reg spc1_dva_vlddcache_err;
reg spc1_dva_err;
reg [6:0] spc1_dva_raddr_d;
reg [4:0] spc1_dva_waddr_d;
reg [4:0] spc1_dva_invwaddr_d;
reg spc1_ld0_lt_1;
reg spc1_ld0_lt_2;
reg spc1_ld0_lt_3;
reg spc1_ld1_lt_0;
reg spc1_ld1_lt_2;
reg spc1_ld1_lt_3;
reg spc1_ld2_lt_0;
reg spc1_ld2_lt_1;
reg spc1_ld2_lt_3;
reg spc1_ld3_lt_0;
reg spc1_ld3_lt_1;
reg spc1_ld3_lt_2;
reg spc1_st0_lt_1;
reg spc1_st0_lt_2;
reg spc1_st0_lt_3;
reg spc1_st1_lt_0;
reg spc1_st1_lt_2;
reg spc1_st1_lt_3;
reg spc1_st2_lt_0;
reg spc1_st2_lt_1;
reg spc1_st2_lt_3;
reg spc1_st3_lt_0;
reg spc1_st3_lt_1;
reg spc1_st3_lt_2;
wire [11:0] spc1_ld_ooo_ret;
wire [11:0] spc1_st_ooo_ret;
wire [7:0] spc1_stb_state_vld0 = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc1_stb_state_ack0 = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc1_stb_state_ced0 = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc1_stb_state_rst0 = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_state_rst;
wire spc1_stb_ack_vld0 = `TOP_DESIGN.sparc1.lsu.stb_ctl0.ack_vld;
wire spc1_ld0_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_inst_vld_g;
wire spc1_intrpt0_cmplt = `TOP_DESIGN.sparc1.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc1_stb0_full = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_full;
wire spc1_stb0_full_w2 = `TOP_DESIGN.sparc1.lsu.stb_ctl0.stb_full_w2;
wire spc1_lmq0_full = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_pcx_rq_vld;
wire spc1_mbar_vld0 = `TOP_DESIGN.sparc1.lsu.dctl.mbar_vld0;
wire spc1_ld0_unfilled = `TOP_DESIGN.sparc1.lsu.qctl1.ld0_unfilled;
wire spc1_flsh_vld0 = `TOP_DESIGN.sparc1.lsu.dctl.flsh_vld0;
reg [9:0] spc1_ld0_unf_cntr;
reg spc1_ld0_unfilled_d;
reg [9:0] spc1_st0_unf_cntr;
reg spc1_st0_unfilled_d;
reg spc1_st0_unfilled;
reg spc1_mbar_vld_d0;
reg spc1_flsh_vld_d0;
reg spc1_lmq0_full_d;
reg [9:0] spc1_lmq_full_cntr0;
reg spc1_lmq_full_capture0;
reg [9:0] spc1_stb_full_cntr0;
reg spc1_stb_full_capture0;
reg [9:0] spc1_mbar_vld_cntr0;
reg spc1_mbar_vld_capture0;
reg [9:0] spc1_flsh_vld_cntr0;
reg spc1_flsh_vld_capture0;
reg spc1_stb_head_hit0;
wire spc1_raw_ack_capture0;
reg [9:0] spc1_stb_ack_cntr0;
reg [9:0] spc1_stb_ced_cntr0;
reg spc1_stb_ced0_d;
reg spc1_stb_ced_capture0;
wire spc1_stb_ced0;
reg spc1_atm0_d;
reg [9:0] spc1_atm_cntr0;
reg spc1_atm_intrpt_capture0;
reg spc1_atm_intrpt_b4capture0;
reg spc1_atm_inv_capture0;
reg [39:0] spc1_stb_wr_addr0;
reg [39:0] spc1_stb_atm_addr0;
reg spc1_atm_lmiss_eq0;
wire [7:0] spc1_stb_state_vld1 = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc1_stb_state_ack1 = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc1_stb_state_ced1 = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc1_stb_state_rst1 = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_state_rst;
wire spc1_stb_ack_vld1 = `TOP_DESIGN.sparc1.lsu.stb_ctl1.ack_vld;
wire spc1_ld1_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_inst_vld_g;
wire spc1_intrpt1_cmplt = `TOP_DESIGN.sparc1.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc1_stb1_full = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_full;
wire spc1_stb1_full_w2 = `TOP_DESIGN.sparc1.lsu.stb_ctl1.stb_full_w2;
wire spc1_lmq1_full = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_pcx_rq_vld;
wire spc1_mbar_vld1 = `TOP_DESIGN.sparc1.lsu.dctl.mbar_vld1;
wire spc1_ld1_unfilled = `TOP_DESIGN.sparc1.lsu.qctl1.ld1_unfilled;
wire spc1_flsh_vld1 = `TOP_DESIGN.sparc1.lsu.dctl.flsh_vld1;
reg [9:0] spc1_ld1_unf_cntr;
reg spc1_ld1_unfilled_d;
reg [9:0] spc1_st1_unf_cntr;
reg spc1_st1_unfilled_d;
reg spc1_st1_unfilled;
reg spc1_mbar_vld_d1;
reg spc1_flsh_vld_d1;
reg spc1_lmq1_full_d;
reg [9:0] spc1_lmq_full_cntr1;
reg spc1_lmq_full_capture1;
reg [9:0] spc1_stb_full_cntr1;
reg spc1_stb_full_capture1;
reg [9:0] spc1_mbar_vld_cntr1;
reg spc1_mbar_vld_capture1;
reg [9:0] spc1_flsh_vld_cntr1;
reg spc1_flsh_vld_capture1;
reg spc1_stb_head_hit1;
wire spc1_raw_ack_capture1;
reg [9:0] spc1_stb_ack_cntr1;
reg [9:0] spc1_stb_ced_cntr1;
reg spc1_stb_ced1_d;
reg spc1_stb_ced_capture1;
wire spc1_stb_ced1;
reg spc1_atm1_d;
reg [9:0] spc1_atm_cntr1;
reg spc1_atm_intrpt_capture1;
reg spc1_atm_intrpt_b4capture1;
reg spc1_atm_inv_capture1;
reg [39:0] spc1_stb_wr_addr1;
reg [39:0] spc1_stb_atm_addr1;
reg spc1_atm_lmiss_eq1;
wire [7:0] spc1_stb_state_vld2 = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc1_stb_state_ack2 = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc1_stb_state_ced2 = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc1_stb_state_rst2 = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_state_rst;
wire spc1_stb_ack_vld2 = `TOP_DESIGN.sparc1.lsu.stb_ctl2.ack_vld;
wire spc1_ld2_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_inst_vld_g;
wire spc1_intrpt2_cmplt = `TOP_DESIGN.sparc1.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc1_stb2_full = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_full;
wire spc1_stb2_full_w2 = `TOP_DESIGN.sparc1.lsu.stb_ctl2.stb_full_w2;
wire spc1_lmq2_full = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_pcx_rq_vld;
wire spc1_mbar_vld2 = `TOP_DESIGN.sparc1.lsu.dctl.mbar_vld2;
wire spc1_ld2_unfilled = `TOP_DESIGN.sparc1.lsu.qctl1.ld2_unfilled;
wire spc1_flsh_vld2 = `TOP_DESIGN.sparc1.lsu.dctl.flsh_vld2;
reg [9:0] spc1_ld2_unf_cntr;
reg spc1_ld2_unfilled_d;
reg [9:0] spc1_st2_unf_cntr;
reg spc1_st2_unfilled_d;
reg spc1_st2_unfilled;
reg spc1_mbar_vld_d2;
reg spc1_flsh_vld_d2;
reg spc1_lmq2_full_d;
reg [9:0] spc1_lmq_full_cntr2;
reg spc1_lmq_full_capture2;
reg [9:0] spc1_stb_full_cntr2;
reg spc1_stb_full_capture2;
reg [9:0] spc1_mbar_vld_cntr2;
reg spc1_mbar_vld_capture2;
reg [9:0] spc1_flsh_vld_cntr2;
reg spc1_flsh_vld_capture2;
reg spc1_stb_head_hit2;
wire spc1_raw_ack_capture2;
reg [9:0] spc1_stb_ack_cntr2;
reg [9:0] spc1_stb_ced_cntr2;
reg spc1_stb_ced2_d;
reg spc1_stb_ced_capture2;
wire spc1_stb_ced2;
reg spc1_atm2_d;
reg [9:0] spc1_atm_cntr2;
reg spc1_atm_intrpt_capture2;
reg spc1_atm_intrpt_b4capture2;
reg spc1_atm_inv_capture2;
reg [39:0] spc1_stb_wr_addr2;
reg [39:0] spc1_stb_atm_addr2;
reg spc1_atm_lmiss_eq2;
wire [7:0] spc1_stb_state_vld3 = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc1_stb_state_ack3 = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc1_stb_state_ced3 = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc1_stb_state_rst3 = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_state_rst;
wire spc1_stb_ack_vld3 = `TOP_DESIGN.sparc1.lsu.stb_ctl3.ack_vld;
wire spc1_ld3_inst_vld_g = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_inst_vld_g;
wire spc1_intrpt3_cmplt = `TOP_DESIGN.sparc1.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc1_stb3_full = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_full;
wire spc1_stb3_full_w2 = `TOP_DESIGN.sparc1.lsu.stb_ctl3.stb_full_w2;
wire spc1_lmq3_full = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_pcx_rq_vld;
wire spc1_mbar_vld3 = `TOP_DESIGN.sparc1.lsu.dctl.mbar_vld3;
wire spc1_ld3_unfilled = `TOP_DESIGN.sparc1.lsu.qctl1.ld3_unfilled;
wire spc1_flsh_vld3 = `TOP_DESIGN.sparc1.lsu.dctl.flsh_vld3;
reg [9:0] spc1_ld3_unf_cntr;
reg spc1_ld3_unfilled_d;
reg [9:0] spc1_st3_unf_cntr;
reg spc1_st3_unfilled_d;
reg spc1_st3_unfilled;
reg spc1_mbar_vld_d3;
reg spc1_flsh_vld_d3;
reg spc1_lmq3_full_d;
reg [9:0] spc1_lmq_full_cntr3;
reg spc1_lmq_full_capture3;
reg [9:0] spc1_stb_full_cntr3;
reg spc1_stb_full_capture3;
reg [9:0] spc1_mbar_vld_cntr3;
reg spc1_mbar_vld_capture3;
reg [9:0] spc1_flsh_vld_cntr3;
reg spc1_flsh_vld_capture3;
reg spc1_stb_head_hit3;
wire spc1_raw_ack_capture3;
reg [9:0] spc1_stb_ack_cntr3;
reg [9:0] spc1_stb_ced_cntr3;
reg spc1_stb_ced3_d;
reg spc1_stb_ced_capture3;
wire spc1_stb_ced3;
reg spc1_atm3_d;
reg [9:0] spc1_atm_cntr3;
reg spc1_atm_intrpt_capture3;
reg spc1_atm_intrpt_b4capture3;
reg spc1_atm_inv_capture3;
reg [39:0] spc1_stb_wr_addr3;
reg [39:0] spc1_stb_atm_addr3;
reg spc1_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc1_fpick = {spc1_mpick,spc1_spick,spc1_lpick,spc1_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc1_msquash,spc1_apick,spc1_fpick})
9'b000000000 : spc1_fpicko = 1'b0;
9'b0xxx1xxx1 : spc1_fpicko = 1'b0;
9'b1xxxxxxxx : spc1_fpicko = 1'b0;
9'b0xxx0xxx0 : spc1_fpicko = 1'b0;
default:
begin
spc1_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon1 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc1_exu_und = {spc1_l2,
spc1_unc,
spc1_fpld,
spc1_fpldst,
spc1_unflush,
spc1_ldw,
spc1_byp,
spc1_flsh,
spc1_chm,
spc1_ldxa,
spc1_ato,
spc1_pref,
spc1_chit,
spc1_dcp,
spc1_dtp,
spc1_mpc,
spc1_mpu};
always @(spc1_exu_und)
begin
case (spc1_exu_und)
17'h00000 : spc1_exu = 5'h00;
17'h00001 : spc1_exu = 5'h01;
17'h00002 : spc1_exu = 5'h02;
17'h00004 : spc1_exu = 5'h03;
17'h00008 : spc1_exu = 5'h04;
17'h00010 : spc1_exu = 5'h05;
17'h00020 : spc1_exu = 5'h06;
17'h00040 : spc1_exu = 5'h07;
17'h00080 : spc1_exu = 5'h08;
17'h00100 : spc1_exu = 5'h09;
17'h00200 : spc1_exu = 5'h0a;
17'h00400 : spc1_exu = 5'h0b;
17'h00800 : spc1_exu = 5'h0c;
17'h01000 : spc1_exu = 5'h0d;
17'h02000 : spc1_exu = 5'h0e;
17'h04000 : spc1_exu = 5'h0f;
17'h08000 : spc1_exu = 5'h10;
17'h10000 : spc1_exu = 5'h11;
default: spc1_exu = 5'h12;
endcase
end
//excp
assign spc1_exp_und = {spc1_exp_wtchpt_trp_g,
spc1_exp_misalign_addr_ldst_atm_m,
spc1_exp_priv_violtn_g,
spc1_exp_daccess_excptn_g,
spc1_exp_daccess_prot_g,
spc1_exp_priv_action_g,
spc1_exp_spec_access_epage_g,
spc1_exp_uncache_atomic_g,
spc1_exp_illegal_asi_action_g,
spc1_exp_flt_ld_nfo_pg_g,
spc1_exp_asi_rd_unc,
spc1_exp_tlb_data_ce,
spc1_exp_tlb_data_ue,
spc1_exp_tlb_tag_ue,
spc1_exp_unc,
spc1_exp_corr};
always @(spc1_exp_und)
begin
case (spc1_exp_und)
16'h0000 : spc1_exp = 5'h00;
16'h0001 : spc1_exp = 5'h01;
16'h0002 : spc1_exp = 5'h02;
16'h0004 : spc1_exp = 5'h03;
16'h0008 : spc1_exp = 5'h04;
16'h0010 : spc1_exp = 5'h05;
16'h0020 : spc1_exp = 5'h06;
16'h0040 : spc1_exp = 5'h07;
16'h0080 : spc1_exp = 5'h08;
16'h0100 : spc1_exp = 5'h09;
16'h0200 : spc1_exp = 5'h0a;
16'h0400 : spc1_exp = 5'h0b;
16'h0800 : spc1_exp = 5'h0c;
16'h1000 : spc1_exp = 5'h0d;
16'h2000 : spc1_exp = 5'h0e;
16'h4000 : spc1_exp = 5'h0f;
16'h8000 : spc1_exp = 5'h10;
default: spc1_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc1_dctl_stxa_cmplt0 = ((spc1_dctl_stxa_internal_d2 & spc1_dctl_thread0_w3) |
spc1_dctl_stxa_stall_wr_cmplt0_d1);
assign spc1_dctl_l2fill_cmplt0 = (((spc1_dctl_lsu_l2fill_vld & ~spc1_dctl_atomic_ld_squash_e &
~spc1_dctl_lsu_ignore_fill)) & ~spc1_dctl_l2fill_fpld_e &
~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread0);
assign spc1_dctl_fillerr0 = spc1_dctl_l2_corr_error_e & spc1_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc1_dctl_atm_cmplt0 = (spc1_dctl_lsu_atm_st_cmplt_e & ~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread0);
assign spc1_dctl_ldst_cond_cmplt0 = { spc1_dctl_stxa_cmplt0, spc1_dctl_l2fill_cmplt0,
spc1_dctl_atomic_ld_squash_e, spc1_dctl_intld_byp_cmplt[0],
spc1_dctl_bsync0_reset, spc1_dctl_lsu_intrpt_cmplt[0]
};
assign spc1_cmplt0 = { spc1_dctl_ldxa_illgl_va_cmplt_d1, spc1_dctl_pref_tlbmiss_cmplt_d2,
spc1_dctl_lsu_pcx_pref_issue, spc1_dctl_diag_wr_cmplt0, spc1_dctl_l2fill_fpld_e};
always @(spc1_cmplt0 or spc1_dctl_ldst_cond_cmplt0)
begin
case ({spc1_dctl_fillerr0,spc1_dctl_ldst_cond_cmplt0,spc1_cmplt0})
12'h000 : spc1_ldstcond_cmplt0 = 4'h0;
12'h001 : spc1_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc1_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc1_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc1_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc1_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc1_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc1_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc1_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc1_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc1_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc1_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc1_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc1_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc1_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc1_dctl_stxa_cmplt1 = ((spc1_dctl_stxa_internal_d2 & spc1_dctl_thread1_w3) |
spc1_dctl_stxa_stall_wr_cmplt1_d1);
assign spc1_dctl_l2fill_cmplt1 = (((spc1_dctl_lsu_l2fill_vld & ~spc1_dctl_atomic_ld_squash_e &
~spc1_dctl_lsu_ignore_fill)) & ~spc1_dctl_l2fill_fpld_e &
~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread1);
assign spc1_dctl_fillerr1 = spc1_dctl_l2_corr_error_e & spc1_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc1_dctl_atm_cmplt1 = (spc1_dctl_lsu_atm_st_cmplt_e & ~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread1);
assign spc1_dctl_ldst_cond_cmplt1 = { spc1_dctl_stxa_cmplt1, spc1_dctl_l2fill_cmplt1,
spc1_dctl_atomic_ld_squash_e, spc1_dctl_intld_byp_cmplt[1],
spc1_dctl_bsync1_reset, spc1_dctl_lsu_intrpt_cmplt[1]
};
assign spc1_cmplt1 = { spc1_dctl_ldxa_illgl_va_cmplt_d1, spc1_dctl_pref_tlbmiss_cmplt_d2,
spc1_dctl_lsu_pcx_pref_issue, spc1_dctl_diag_wr_cmplt1, spc1_dctl_l2fill_fpld_e};
always @(spc1_cmplt1 or spc1_dctl_ldst_cond_cmplt1)
begin
case ({spc1_dctl_fillerr1,spc1_dctl_ldst_cond_cmplt1,spc1_cmplt1})
12'h000 : spc1_ldstcond_cmplt1 = 4'h0;
12'h001 : spc1_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc1_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc1_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc1_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc1_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc1_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc1_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc1_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc1_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc1_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc1_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc1_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc1_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc1_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc1_dctl_stxa_cmplt2 = ((spc1_dctl_stxa_internal_d2 & spc1_dctl_thread2_w3) |
spc1_dctl_stxa_stall_wr_cmplt2_d1);
assign spc1_dctl_l2fill_cmplt2 = (((spc1_dctl_lsu_l2fill_vld & ~spc1_dctl_atomic_ld_squash_e &
~spc1_dctl_lsu_ignore_fill)) & ~spc1_dctl_l2fill_fpld_e &
~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread2);
assign spc1_dctl_fillerr2 = spc1_dctl_l2_corr_error_e & spc1_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc1_dctl_atm_cmplt2 = (spc1_dctl_lsu_atm_st_cmplt_e & ~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread2);
assign spc1_dctl_ldst_cond_cmplt2 = { spc1_dctl_stxa_cmplt2, spc1_dctl_l2fill_cmplt2,
spc1_dctl_atomic_ld_squash_e, spc1_dctl_intld_byp_cmplt[2],
spc1_dctl_bsync2_reset, spc1_dctl_lsu_intrpt_cmplt[2]
};
assign spc1_cmplt2 = { spc1_dctl_ldxa_illgl_va_cmplt_d1, spc1_dctl_pref_tlbmiss_cmplt_d2,
spc1_dctl_lsu_pcx_pref_issue, spc1_dctl_diag_wr_cmplt2, spc1_dctl_l2fill_fpld_e};
always @(spc1_cmplt2 or spc1_dctl_ldst_cond_cmplt2)
begin
case ({spc1_dctl_fillerr2,spc1_dctl_ldst_cond_cmplt2,spc1_cmplt2})
12'h000 : spc1_ldstcond_cmplt2 = 4'h0;
12'h001 : spc1_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc1_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc1_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc1_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc1_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc1_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc1_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc1_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc1_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc1_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc1_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc1_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc1_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc1_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc1_dctl_stxa_cmplt3 = ((spc1_dctl_stxa_internal_d2 & spc1_dctl_thread3_w3) |
spc1_dctl_stxa_stall_wr_cmplt3_d1);
assign spc1_dctl_l2fill_cmplt3 = (((spc1_dctl_lsu_l2fill_vld & ~spc1_dctl_atomic_ld_squash_e &
~spc1_dctl_lsu_ignore_fill)) & ~spc1_dctl_l2fill_fpld_e &
~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread3);
assign spc1_dctl_fillerr3 = spc1_dctl_l2_corr_error_e & spc1_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc1_dctl_atm_cmplt3 = (spc1_dctl_lsu_atm_st_cmplt_e & ~spc1_dctl_fill_err_trap_e & spc1_dctl_dfill_thread3);
assign spc1_dctl_ldst_cond_cmplt3 = { spc1_dctl_stxa_cmplt3, spc1_dctl_l2fill_cmplt3,
spc1_dctl_atomic_ld_squash_e, spc1_dctl_intld_byp_cmplt[3],
spc1_dctl_bsync3_reset, spc1_dctl_lsu_intrpt_cmplt[3]
};
assign spc1_cmplt3 = { spc1_dctl_ldxa_illgl_va_cmplt_d1, spc1_dctl_pref_tlbmiss_cmplt_d2,
spc1_dctl_lsu_pcx_pref_issue, spc1_dctl_diag_wr_cmplt3, spc1_dctl_l2fill_fpld_e};
always @(spc1_cmplt3 or spc1_dctl_ldst_cond_cmplt3)
begin
case ({spc1_dctl_fillerr3,spc1_dctl_ldst_cond_cmplt3,spc1_cmplt3})
12'h000 : spc1_ldstcond_cmplt3 = 4'h0;
12'h001 : spc1_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc1_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc1_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc1_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc1_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc1_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc1_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc1_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc1_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc1_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc1_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc1_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc1_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc1_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc1_ldstcond_cmplt0 or spc1_ldstcond_cmplt1 or spc1_ldstcond_cmplt2
or spc1_ldstcond_cmplt3 or spc1_dctl_lsu_ifu_ldst_cmplt
or spc1_dctl_late_cmplt0 or spc1_dctl_late_cmplt1 or spc1_dctl_late_cmplt2 or spc1_dctl_late_cmplt3)
begin
case (spc1_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc1_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc1_ldstcond_cmplt_d = spc1_dctl_late_cmplt0 ? spc1_ldstcond_cmplt0_d : spc1_ldstcond_cmplt0;
4'b0010 : spc1_ldstcond_cmplt_d = spc1_dctl_late_cmplt1 ? spc1_ldstcond_cmplt1_d : spc1_ldstcond_cmplt1;
4'b0100 : spc1_ldstcond_cmplt_d = spc1_dctl_late_cmplt2 ? spc1_ldstcond_cmplt2_d : spc1_ldstcond_cmplt2;
4'b1000 : spc1_ldstcond_cmplt_d = spc1_dctl_late_cmplt3 ? spc1_ldstcond_cmplt3_d : spc1_ldstcond_cmplt3;
4'b0011 : spc1_ldstcond_cmplt_d = 4'he;
4'b0101 : spc1_ldstcond_cmplt_d = 4'he;
4'b1001 : spc1_ldstcond_cmplt_d = 4'he;
4'b0110 : spc1_ldstcond_cmplt_d = 4'he;
4'b1010 : spc1_ldstcond_cmplt_d = 4'he;
4'b1100 : spc1_ldstcond_cmplt_d = 4'he;
default:
begin
spc1_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc1_st_ooo_ret = { spc1_st0_lt_1, spc1_st0_lt_2, spc1_st0_lt_3,
spc1_st1_lt_0, spc1_st1_lt_2, spc1_st1_lt_3,
spc1_st2_lt_0, spc1_st2_lt_1, spc1_st2_lt_3,
spc1_st3_lt_0, spc1_st3_lt_1, spc1_st3_lt_2};
always @(posedge clk)
begin
if(~spc1_st0_unfilled || ~rst_l)
spc1_st0_unfilled_d <= 1'b0;
else
spc1_st0_unfilled_d <= spc1_st0_unfilled;
if(~rst_l)
spc1_ldstcond_cmplt0_d <= 4'h0;
else
spc1_ldstcond_cmplt0_d <= spc1_ldstcond_cmplt0;
if(~spc1_ld0_pkt_vld_unmasked || ~rst_l)
spc1_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc1_ld0_pkt_vld_unmasked_d <= spc1_ld0_pkt_vld_unmasked;
if(~rst_l)
spc1_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc1_qctl1_ld_sec_hit_thrd0 && spc1_qctl1_ld0_inst_vld_g)
spc1_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc1_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc1_st1_unfilled || ~rst_l)
spc1_st1_unfilled_d <= 1'b0;
else
spc1_st1_unfilled_d <= spc1_st1_unfilled;
if(~rst_l)
spc1_ldstcond_cmplt1_d <= 4'h0;
else
spc1_ldstcond_cmplt1_d <= spc1_ldstcond_cmplt1;
if(~spc1_ld1_pkt_vld_unmasked || ~rst_l)
spc1_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc1_ld1_pkt_vld_unmasked_d <= spc1_ld1_pkt_vld_unmasked;
if(~rst_l)
spc1_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc1_qctl1_ld_sec_hit_thrd1 && spc1_qctl1_ld1_inst_vld_g)
spc1_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc1_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc1_st2_unfilled || ~rst_l)
spc1_st2_unfilled_d <= 1'b0;
else
spc1_st2_unfilled_d <= spc1_st2_unfilled;
if(~rst_l)
spc1_ldstcond_cmplt2_d <= 4'h0;
else
spc1_ldstcond_cmplt2_d <= spc1_ldstcond_cmplt2;
if(~spc1_ld2_pkt_vld_unmasked || ~rst_l)
spc1_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc1_ld2_pkt_vld_unmasked_d <= spc1_ld2_pkt_vld_unmasked;
if(~rst_l)
spc1_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc1_qctl1_ld_sec_hit_thrd2 && spc1_qctl1_ld2_inst_vld_g)
spc1_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc1_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc1_st3_unfilled || ~rst_l)
spc1_st3_unfilled_d <= 1'b0;
else
spc1_st3_unfilled_d <= spc1_st3_unfilled;
if(~rst_l)
spc1_ldstcond_cmplt3_d <= 4'h0;
else
spc1_ldstcond_cmplt3_d <= spc1_ldstcond_cmplt3;
if(~spc1_ld3_pkt_vld_unmasked || ~rst_l)
spc1_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc1_ld3_pkt_vld_unmasked_d <= spc1_ld3_pkt_vld_unmasked;
if(~rst_l)
spc1_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc1_qctl1_ld_sec_hit_thrd3 && spc1_qctl1_ld3_inst_vld_g)
spc1_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc1_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc1_stb_state_ced0) && (|spc1_stb_state_rst0)) || ~rst_l)
spc1_st0_unfilled <= 1'b0;
else if( ((|spc1_stb_state_ced0) && ~(|spc1_stb_state_rst0)))
spc1_st0_unfilled <= 1'b1;
else
spc1_st0_unfilled <= spc1_st0_unfilled;
if( ((|spc1_stb_state_ced1) && (|spc1_stb_state_rst1)) || ~rst_l)
spc1_st1_unfilled <= 1'b0;
else if( ((|spc1_stb_state_ced1) && ~(|spc1_stb_state_rst1)))
spc1_st1_unfilled <= 1'b1;
else
spc1_st1_unfilled <= spc1_st1_unfilled;
if( ((|spc1_stb_state_ced2) && (|spc1_stb_state_rst2)) || ~rst_l)
spc1_st2_unfilled <= 1'b0;
else if( ((|spc1_stb_state_ced2) && ~(|spc1_stb_state_rst2)))
spc1_st2_unfilled <= 1'b1;
else
spc1_st2_unfilled <= spc1_st2_unfilled;
if( ((|spc1_stb_state_ced3) && (|spc1_stb_state_rst3)) || ~rst_l)
spc1_st3_unfilled <= 1'b0;
else if( ((|spc1_stb_state_ced3) && ~(|spc1_stb_state_rst3)))
spc1_st3_unfilled <= 1'b1;
else
spc1_st3_unfilled <= spc1_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc1_st0_unfilled && spc1_st0_unfilled_d)|| ~rst_l)
begin
spc1_st0_unf_cntr <= 9'h000;
end
else if(spc1_st0_unfilled)
begin
spc1_st0_unf_cntr <= spc1_st0_unf_cntr + 1;
end
else
begin
spc1_st0_unf_cntr <= spc1_st0_unf_cntr;
end
if((~spc1_st1_unfilled && spc1_st1_unfilled_d)|| ~rst_l)
begin
spc1_st1_unf_cntr <= 9'h000;
end
else if(spc1_st1_unfilled)
begin
spc1_st1_unf_cntr <= spc1_st1_unf_cntr + 1;
end
else
begin
spc1_st1_unf_cntr <= spc1_st1_unf_cntr;
end
if((~spc1_st2_unfilled && spc1_st2_unfilled_d)|| ~rst_l)
begin
spc1_st2_unf_cntr <= 9'h000;
end
else if(spc1_st2_unfilled)
begin
spc1_st2_unf_cntr <= spc1_st2_unf_cntr + 1;
end
else
begin
spc1_st2_unf_cntr <= spc1_st2_unf_cntr;
end
if((~spc1_st3_unfilled && spc1_st3_unfilled_d)|| ~rst_l)
begin
spc1_st3_unf_cntr <= 9'h000;
end
else if(spc1_st3_unfilled)
begin
spc1_st3_unf_cntr <= spc1_st3_unf_cntr + 1;
end
else
begin
spc1_st3_unf_cntr <= spc1_st3_unf_cntr;
end
end
always @(spc1_st0_unfilled or spc1_st1_unfilled or spc1_st2_unfilled or spc1_st3_unfilled
or spc1_st0_unfilled_d or spc1_st1_unfilled_d or spc1_st2_unfilled_d or spc1_st3_unfilled_d)
begin
if(~spc1_st0_unfilled && spc1_st0_unfilled_d && spc1_st1_unfilled)
spc1_st0_lt_1 <= (spc1_st1_unf_cntr > spc1_st0_unf_cntr);
else
spc1_st0_lt_1 <= 1'b0;
if(~spc1_st0_unfilled && spc1_st0_unfilled_d && spc1_st2_unfilled)
spc1_st0_lt_2 <= (spc1_st2_unf_cntr > spc1_st0_unf_cntr);
else
spc1_st0_lt_2 <= 1'b0;
if(~spc1_st0_unfilled && spc1_st0_unfilled_d && spc1_st3_unfilled)
spc1_st0_lt_3 <= (spc1_st3_unf_cntr > spc1_st0_unf_cntr);
else
spc1_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc1_st1_unfilled && spc1_st1_unfilled_d && spc1_st0_unfilled)
spc1_st1_lt_0 <= (spc1_st0_unf_cntr > spc1_st1_unf_cntr);
else
spc1_st1_lt_0 <= 1'b0;
if(~spc1_st1_unfilled && spc1_st1_unfilled_d && spc1_st2_unfilled)
spc1_st1_lt_2 <= (spc1_st2_unf_cntr > spc1_st1_unf_cntr);
else
spc1_st1_lt_2 <= 1'b0;
if(~spc1_st1_unfilled && spc1_st1_unfilled_d && spc1_st3_unfilled)
spc1_st1_lt_3 <= (spc1_st3_unf_cntr > spc1_st1_unf_cntr);
else
spc1_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc1_st2_unfilled && spc1_st2_unfilled_d && spc1_st0_unfilled)
spc1_st2_lt_0 <= (spc1_st0_unf_cntr > spc1_st2_unf_cntr);
else
spc1_st2_lt_0 <= 1'b0;
if(~spc1_st2_unfilled && spc1_st2_unfilled_d && spc1_st1_unfilled)
spc1_st2_lt_1 <= (spc1_st1_unf_cntr > spc1_st2_unf_cntr);
else
spc1_st2_lt_1 <= 1'b0;
if(~spc1_st2_unfilled && spc1_st2_unfilled_d && spc1_st3_unfilled)
spc1_st2_lt_3 <= (spc1_st3_unf_cntr > spc1_st2_unf_cntr);
else
spc1_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc1_st3_unfilled && spc1_st3_unfilled_d && spc1_st0_unfilled)
spc1_st3_lt_0 <= (spc1_st0_unf_cntr > spc1_st3_unf_cntr);
else
spc1_st3_lt_0 <= 1'b0;
if(~spc1_st3_unfilled && spc1_st3_unfilled_d && spc1_st1_unfilled)
spc1_st3_lt_1 <= (spc1_st1_unf_cntr > spc1_st3_unf_cntr);
else
spc1_st3_lt_1 <= 1'b0;
if(~spc1_st3_unfilled && spc1_st3_unfilled_d && spc1_st2_unfilled)
spc1_st3_lt_2 <= (spc1_st2_unf_cntr > spc1_st3_unf_cntr);
else
spc1_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc1_ld_ooo_ret = { spc1_ld0_lt_1, spc1_ld0_lt_2, spc1_ld0_lt_3,
spc1_ld1_lt_0, spc1_ld1_lt_2, spc1_ld1_lt_3,
spc1_ld2_lt_0, spc1_ld2_lt_1, spc1_ld2_lt_3,
spc1_ld3_lt_0, spc1_ld3_lt_1, spc1_ld3_lt_2};
always @(posedge clk)
begin
if((~spc1_ld0_unfilled && spc1_ld0_unfilled_d)|| ~rst_l)
begin
spc1_ld0_unf_cntr <= 9'h000;
end
else if(spc1_ld0_unfilled)
begin
spc1_ld0_unf_cntr <= spc1_ld0_unf_cntr + 1;
end
else
begin
spc1_ld0_unf_cntr <= spc1_ld0_unf_cntr;
end
if((~spc1_ld1_unfilled && spc1_ld1_unfilled_d)|| ~rst_l)
begin
spc1_ld1_unf_cntr <= 9'h000;
end
else if(spc1_ld1_unfilled)
begin
spc1_ld1_unf_cntr <= spc1_ld1_unf_cntr + 1;
end
else
begin
spc1_ld1_unf_cntr <= spc1_ld1_unf_cntr;
end
if((~spc1_ld2_unfilled && spc1_ld2_unfilled_d)|| ~rst_l)
begin
spc1_ld2_unf_cntr <= 9'h000;
end
else if(spc1_ld2_unfilled)
begin
spc1_ld2_unf_cntr <= spc1_ld2_unf_cntr + 1;
end
else
begin
spc1_ld2_unf_cntr <= spc1_ld2_unf_cntr;
end
if((~spc1_ld3_unfilled && spc1_ld3_unfilled_d)|| ~rst_l)
begin
spc1_ld3_unf_cntr <= 9'h000;
end
else if(spc1_ld3_unfilled)
begin
spc1_ld3_unf_cntr <= spc1_ld3_unf_cntr + 1;
end
else
begin
spc1_ld3_unf_cntr <= spc1_ld3_unf_cntr;
end
end
always @(spc1_ld0_unfilled or spc1_ld1_unfilled or spc1_ld2_unfilled or spc1_ld3_unfilled
or spc1_ld0_unfilled_d or spc1_ld1_unfilled_d or spc1_ld2_unfilled_d or spc1_ld3_unfilled_d)
begin
if(~spc1_ld0_unfilled && spc1_ld0_unfilled_d && spc1_ld1_unfilled)
spc1_ld0_lt_1 <= (spc1_ld1_unf_cntr > spc1_ld0_unf_cntr);
else
spc1_ld0_lt_1 <= 1'b0;
if(~spc1_ld0_unfilled && spc1_ld0_unfilled_d && spc1_ld2_unfilled)
spc1_ld0_lt_2 <= (spc1_ld2_unf_cntr > spc1_ld0_unf_cntr);
else
spc1_ld0_lt_2 <= 1'b0;
if(~spc1_ld0_unfilled && spc1_ld0_unfilled_d && spc1_ld3_unfilled)
spc1_ld0_lt_3 <= (spc1_ld3_unf_cntr > spc1_ld0_unf_cntr);
else
spc1_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc1_ld1_unfilled && spc1_ld1_unfilled_d && spc1_ld0_unfilled)
spc1_ld1_lt_0 <= (spc1_ld0_unf_cntr > spc1_ld1_unf_cntr);
else
spc1_ld1_lt_0 <= 1'b0;
if(~spc1_ld1_unfilled && spc1_ld1_unfilled_d && spc1_ld2_unfilled)
spc1_ld1_lt_2 <= (spc1_ld2_unf_cntr > spc1_ld1_unf_cntr);
else
spc1_ld1_lt_2 <= 1'b0;
if(~spc1_ld1_unfilled && spc1_ld1_unfilled_d && spc1_ld3_unfilled)
spc1_ld1_lt_3 <= (spc1_ld3_unf_cntr > spc1_ld1_unf_cntr);
else
spc1_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc1_ld2_unfilled && spc1_ld2_unfilled_d && spc1_ld0_unfilled)
spc1_ld2_lt_0 <= (spc1_ld0_unf_cntr > spc1_ld2_unf_cntr);
else
spc1_ld2_lt_0 <= 1'b0;
if(~spc1_ld2_unfilled && spc1_ld2_unfilled_d && spc1_ld1_unfilled)
spc1_ld2_lt_1 <= (spc1_ld1_unf_cntr > spc1_ld2_unf_cntr);
else
spc1_ld2_lt_1 <= 1'b0;
if(~spc1_ld2_unfilled && spc1_ld2_unfilled_d && spc1_ld3_unfilled)
spc1_ld2_lt_3 <= (spc1_ld3_unf_cntr > spc1_ld2_unf_cntr);
else
spc1_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc1_ld3_unfilled && spc1_ld3_unfilled_d && spc1_ld0_unfilled)
spc1_ld3_lt_0 <= (spc1_ld0_unf_cntr > spc1_ld3_unf_cntr);
else
spc1_ld3_lt_0 <= 1'b0;
if(~spc1_ld3_unfilled && spc1_ld3_unfilled_d && spc1_ld1_unfilled)
spc1_ld3_lt_1 <= (spc1_ld1_unf_cntr > spc1_ld3_unf_cntr);
else
spc1_ld3_lt_1 <= 1'b0;
if(~spc1_ld3_unfilled && spc1_ld3_unfilled_d && spc1_ld2_unfilled)
spc1_ld3_lt_2 <= (spc1_ld2_unf_cntr > spc1_ld3_unf_cntr);
else
spc1_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc1_dctl_bld_hit =
((|spc1_dctl_lsu_way_hit[3:0]) & spc1_dctl_dcache_enable_g &
~spc1_dctl_ldxa_internal & ~spc1_dctl_dcache_rd_parity_error & ~spc1_dctl_dtag_perror_g &
~spc1_dctl_endian_mispred_g &
~spc1_dctl_atomic_g & ~spc1_dctl_ncache_asild_rq_g) & ~spc1_dctl_tte_data_perror_unc &
spc1_dctl_ld_inst_vld_g & spc1_qctl1_bld_g ;
assign spc1_dctl_bld_stb_hit = spc1_dctl_bld_hit & spc1_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc1_bld0_full_d <= 2'b00;
spc1_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc1_bld0_full_d <= spc1_qctl1_bld_cnt;
spc1_ld0_unfilled_d <= spc1_ld0_unfilled;
end
if(~rst_l)
begin
spc1_bld1_full_d <= 2'b00;
spc1_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc1_bld1_full_d <= spc1_qctl1_bld_cnt;
spc1_ld1_unfilled_d <= spc1_ld1_unfilled;
end
if(~rst_l)
begin
spc1_bld2_full_d <= 2'b00;
spc1_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc1_bld2_full_d <= spc1_qctl1_bld_cnt;
spc1_ld2_unfilled_d <= spc1_ld2_unfilled;
end
if(~rst_l)
begin
spc1_bld3_full_d <= 2'b00;
spc1_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc1_bld3_full_d <= spc1_qctl1_bld_cnt;
spc1_ld3_unfilled_d <= spc1_ld3_unfilled;
end
end
always @(spc1_bld0_full_d or spc1_qctl1_bld_cnt)
begin
if( (spc1_bld0_full_d != spc1_qctl1_bld_cnt) && (spc1_bld0_full_d == 2'd0))
spc1_bld0_full_capture <= 1'b1;
else
spc1_bld0_full_capture <= 1'b0;
end
always @(spc1_bld1_full_d or spc1_qctl1_bld_cnt)
begin
if( (spc1_bld1_full_d != spc1_qctl1_bld_cnt) && (spc1_bld1_full_d == 2'd1))
spc1_bld1_full_capture <= 1'b1;
else
spc1_bld1_full_capture <= 1'b0;
end
always @(spc1_bld2_full_d or spc1_qctl1_bld_cnt)
begin
if( (spc1_bld2_full_d != spc1_qctl1_bld_cnt) && (spc1_bld2_full_d == 2'd2))
spc1_bld2_full_capture <= 1'b1;
else
spc1_bld2_full_capture <= 1'b0;
end
always @(spc1_bld3_full_d or spc1_qctl1_bld_cnt)
begin
if( (spc1_bld3_full_d != spc1_qctl1_bld_cnt) && (spc1_bld3_full_d == 2'd3))
spc1_bld3_full_capture <= 1'b1;
else
spc1_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc1_qctl1_bld_cnt != 2'b00) && (spc1_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc1_bld0_full_cntr <= 9'h000;
end
else if(spc1_qctl1_bld_g && (spc1_qctl1_bld_cnt == 2'b00))
begin
spc1_bld0_full_cntr <= spc1_bld0_full_cntr + 1;
end
else if( (spc1_qctl1_bld_cnt == 2'b00) && (spc1_bld0_full_cntr != 9'h000))
begin
spc1_bld0_full_cntr <= spc1_bld0_full_cntr + 1;
end
else
begin
spc1_bld0_full_cntr <= spc1_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc1_qctl1_bld_cnt != 2'b01) && (spc1_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc1_bld1_full_cntr <= 9'h000;
end
else if(spc1_qctl1_bld_cnt == 2'b01)
begin
spc1_bld1_full_cntr <= spc1_bld1_full_cntr + 1;
end
else if( (spc1_qctl1_bld_cnt == 2'b01) && (spc1_bld1_full_cntr != 9'h000))
begin
spc1_bld1_full_cntr <= spc1_bld1_full_cntr + 1;
end
else
begin
spc1_bld1_full_cntr <= spc1_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc1_qctl1_bld_cnt != 2'b10) && (spc1_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc1_bld2_full_cntr <= 9'h000;
end
else if(spc1_qctl1_bld_cnt == 2'b10)
begin
spc1_bld2_full_cntr <= spc1_bld2_full_cntr + 1;
end
else if( (spc1_qctl1_bld_cnt == 2'b10) && (spc1_bld2_full_cntr != 9'h000))
begin
spc1_bld2_full_cntr <= spc1_bld2_full_cntr + 1;
end
else
begin
spc1_bld2_full_cntr <= spc1_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc1_qctl1_bld_cnt != 2'b11) && (spc1_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc1_bld3_full_cntr <= 9'h000;
end
else if(spc1_qctl1_bld_cnt == 2'b11)
begin
spc1_bld3_full_cntr <= spc1_bld3_full_cntr + 1;
end
else if( (spc1_qctl1_bld_cnt == 2'b11) && (spc1_bld3_full_cntr != 9'h000))
begin
spc1_bld3_full_cntr <= spc1_bld3_full_cntr + 1;
end
else
begin
spc1_bld3_full_cntr <= spc1_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc1_stb_state_vld0) && ~spc1_atomic_g) || ~rst_l)
begin
spc1_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc1_atomic_g && (spc1_atm_type0 != 8'h00) && spc1_wptr_vld)
begin
spc1_stb_atm_addr0 <= {spc1_wdata_ramc[44:9],spc1_wdata_ramd[67:64]};
end
else
begin
spc1_stb_atm_addr0 <= spc1_stb_atm_addr0;
end
if( ( ~(|spc1_stb_state_vld1) && ~spc1_atomic_g) || ~rst_l)
begin
spc1_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc1_atomic_g && (spc1_atm_type1 != 8'h00) && spc1_wptr_vld)
begin
spc1_stb_atm_addr1 <= {spc1_wdata_ramc[44:9],spc1_wdata_ramd[67:64]};
end
else
begin
spc1_stb_atm_addr1 <= spc1_stb_atm_addr1;
end
if( ( ~(|spc1_stb_state_vld2) && ~spc1_atomic_g) || ~rst_l)
begin
spc1_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc1_atomic_g && (spc1_atm_type2 != 8'h00) && spc1_wptr_vld)
begin
spc1_stb_atm_addr2 <= {spc1_wdata_ramc[44:9],spc1_wdata_ramd[67:64]};
end
else
begin
spc1_stb_atm_addr2 <= spc1_stb_atm_addr2;
end
if( ( ~(|spc1_stb_state_vld3) && ~spc1_atomic_g) || ~rst_l)
begin
spc1_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc1_atomic_g && (spc1_atm_type3 != 8'h00) && spc1_wptr_vld)
begin
spc1_stb_atm_addr3 <= {spc1_wdata_ramc[44:9],spc1_wdata_ramd[67:64]};
end
else
begin
spc1_stb_atm_addr3 <= spc1_stb_atm_addr3;
end
end
assign spc1_dfq_full = (spc1_dfq_vld_entries >= 3'd4);
assign spc1_dfq_full1 = (spc1_dfq_vld_entries >= (3'd4 + 1));
always @(spc1_dfq_full_d1 or spc1_dfq_full1)
begin
if (spc1_dfq_full_d1 && ~spc1_dfq_full1)
spc1_dfq_full_capture1 <= 1'b1;
else
spc1_dfq_full_capture1 <= 1'b0;
end
assign spc1_dfq_full2 = (spc1_dfq_vld_entries >= (3'd4 + 2));
always @(spc1_dfq_full_d2 or spc1_dfq_full2)
begin
if (spc1_dfq_full_d2 && ~spc1_dfq_full2)
spc1_dfq_full_capture2 <= 1'b1;
else
spc1_dfq_full_capture2 <= 1'b0;
end
assign spc1_dfq_full3 = (spc1_dfq_vld_entries >= (3'd4 + 3));
always @(spc1_dfq_full_d3 or spc1_dfq_full3)
begin
if (spc1_dfq_full_d3 && ~spc1_dfq_full3)
spc1_dfq_full_capture3 <= 1'b1;
else
spc1_dfq_full_capture3 <= 1'b0;
end
assign spc1_dfq_full4 = (spc1_dfq_vld_entries >= (3'd4 + 4));
always @(spc1_dfq_full_d4 or spc1_dfq_full4)
begin
if (spc1_dfq_full_d4 && ~spc1_dfq_full4)
spc1_dfq_full_capture4 <= 1'b1;
else
spc1_dfq_full_capture4 <= 1'b0;
end
assign spc1_dfq_full5 = (spc1_dfq_vld_entries >= (3'd4 + 5));
always @(spc1_dfq_full_d5 or spc1_dfq_full5)
begin
if (spc1_dfq_full_d5 && ~spc1_dfq_full5)
spc1_dfq_full_capture5 <= 1'b1;
else
spc1_dfq_full_capture5 <= 1'b0;
end
assign spc1_dfq_full6 = (spc1_dfq_vld_entries >= (3'd4 + 6));
always @(spc1_dfq_full_d6 or spc1_dfq_full6)
begin
if (spc1_dfq_full_d6 && ~spc1_dfq_full6)
spc1_dfq_full_capture6 <= 1'b1;
else
spc1_dfq_full_capture6 <= 1'b0;
end
assign spc1_dfq_full7 = (spc1_dfq_vld_entries >= (3'd4 + 7));
always @(spc1_dfq_full_d7 or spc1_dfq_full7)
begin
if (spc1_dfq_full_d7 && ~spc1_dfq_full7)
spc1_dfq_full_capture7 <= 1'b1;
else
spc1_dfq_full_capture7 <= 1'b0;
end
always @(spc1_mbar_vld_d0 or spc1_mbar_vld0)
begin
if (spc1_mbar_vld_d0 && ~spc1_mbar_vld0)
spc1_mbar_vld_capture0 <= 1'b1;
else
spc1_mbar_vld_capture0 <= 1'b0;
end
always @(spc1_mbar_vld_d1 or spc1_mbar_vld1)
begin
if (spc1_mbar_vld_d1 && ~spc1_mbar_vld1)
spc1_mbar_vld_capture1 <= 1'b1;
else
spc1_mbar_vld_capture1 <= 1'b0;
end
always @(spc1_mbar_vld_d2 or spc1_mbar_vld2)
begin
if (spc1_mbar_vld_d2 && ~spc1_mbar_vld2)
spc1_mbar_vld_capture2 <= 1'b1;
else
spc1_mbar_vld_capture2 <= 1'b0;
end
always @(spc1_mbar_vld_d3 or spc1_mbar_vld3)
begin
if (spc1_mbar_vld_d3 && ~spc1_mbar_vld3)
spc1_mbar_vld_capture3 <= 1'b1;
else
spc1_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc1_dfq_full1 && (spc1_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr1 <= 9'h000;
spc1_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr1);
end
else if( spc1_dfq_full1)
begin
spc1_dfq_full_cntr1 <= spc1_dfq_full_cntr1 + 1;
spc1_dfq_full_d1 <= spc1_dfq_full1;
end
else
begin
spc1_dfq_full_cntr1 <= spc1_dfq_full_cntr1;
spc1_dfq_full_d1 <= spc1_dfq_full1;
end
if( ( ~spc1_dfq_full2 && (spc1_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr2 <= 9'h000;
spc1_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr2);
end
else if( spc1_dfq_full2)
begin
spc1_dfq_full_cntr2 <= spc1_dfq_full_cntr2 + 1;
spc1_dfq_full_d2 <= spc1_dfq_full2;
end
else
begin
spc1_dfq_full_cntr2 <= spc1_dfq_full_cntr2;
spc1_dfq_full_d2 <= spc1_dfq_full2;
end
if( ( ~spc1_dfq_full3 && (spc1_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr3 <= 9'h000;
spc1_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr3);
end
else if( spc1_dfq_full3)
begin
spc1_dfq_full_cntr3 <= spc1_dfq_full_cntr3 + 1;
spc1_dfq_full_d3 <= spc1_dfq_full3;
end
else
begin
spc1_dfq_full_cntr3 <= spc1_dfq_full_cntr3;
spc1_dfq_full_d3 <= spc1_dfq_full3;
end
if( ( ~spc1_dfq_full4 && (spc1_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr4 <= 9'h000;
spc1_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr4);
end
else if( spc1_dfq_full4)
begin
spc1_dfq_full_cntr4 <= spc1_dfq_full_cntr4 + 1;
spc1_dfq_full_d4 <= spc1_dfq_full4;
end
else
begin
spc1_dfq_full_cntr4 <= spc1_dfq_full_cntr4;
spc1_dfq_full_d4 <= spc1_dfq_full4;
end
if( ( ~spc1_dfq_full5 && (spc1_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr5 <= 9'h000;
spc1_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr5);
end
else if( spc1_dfq_full5)
begin
spc1_dfq_full_cntr5 <= spc1_dfq_full_cntr5 + 1;
spc1_dfq_full_d5 <= spc1_dfq_full5;
end
else
begin
spc1_dfq_full_cntr5 <= spc1_dfq_full_cntr5;
spc1_dfq_full_d5 <= spc1_dfq_full5;
end
if( ( ~spc1_dfq_full6 && (spc1_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr6 <= 9'h000;
spc1_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr6);
end
else if( spc1_dfq_full6)
begin
spc1_dfq_full_cntr6 <= spc1_dfq_full_cntr6 + 1;
spc1_dfq_full_d6 <= spc1_dfq_full6;
end
else
begin
spc1_dfq_full_cntr6 <= spc1_dfq_full_cntr6;
spc1_dfq_full_d6 <= spc1_dfq_full6;
end
if( ( ~spc1_dfq_full7 && (spc1_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr7 <= 9'h000;
spc1_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr7);
end
else if( spc1_dfq_full7)
begin
spc1_dfq_full_cntr7 <= spc1_dfq_full_cntr7 + 1;
spc1_dfq_full_d7 <= spc1_dfq_full7;
end
else
begin
spc1_dfq_full_cntr7 <= spc1_dfq_full_cntr7;
spc1_dfq_full_d7 <= spc1_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc1_intrpt0_cmplt or spc1_atm_cntr0 or spc1_stb_state_ced0)
begin
if (spc1_intrpt0_cmplt && (spc1_atm_cntr0 != 9'h000) && ~(|spc1_stb_state_ced0))
spc1_atm_intrpt_b4capture0 <= 1'b1;
else
spc1_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc1_intrpt1_cmplt or spc1_atm_cntr1 or spc1_stb_state_ced1)
begin
if (spc1_intrpt1_cmplt && (spc1_atm_cntr1 != 9'h000) && ~(|spc1_stb_state_ced1))
spc1_atm_intrpt_b4capture1 <= 1'b1;
else
spc1_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc1_intrpt2_cmplt or spc1_atm_cntr2 or spc1_stb_state_ced2)
begin
if (spc1_intrpt2_cmplt && (spc1_atm_cntr2 != 9'h000) && ~(|spc1_stb_state_ced2))
spc1_atm_intrpt_b4capture2 <= 1'b1;
else
spc1_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc1_intrpt3_cmplt or spc1_atm_cntr3 or spc1_stb_state_ced3)
begin
if (spc1_intrpt3_cmplt && (spc1_atm_cntr3 != 9'h000) && ~(|spc1_stb_state_ced3))
spc1_atm_intrpt_b4capture3 <= 1'b1;
else
spc1_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc1_intrpt0_cmplt or spc1_atm_cntr0 or spc1_stb_state_ced0)
begin
if (spc1_intrpt0_cmplt && (spc1_atm_cntr0 != 9'h000) && (|spc1_stb_state_ced0))
spc1_atm_intrpt_capture0 <= 1'b1;
else
spc1_atm_intrpt_capture0 <= 1'b0;
end
always @(spc1_intrpt1_cmplt or spc1_atm_cntr1 or spc1_stb_state_ced1)
begin
if (spc1_intrpt1_cmplt && (spc1_atm_cntr1 != 9'h000) && (|spc1_stb_state_ced1))
spc1_atm_intrpt_capture1 <= 1'b1;
else
spc1_atm_intrpt_capture1 <= 1'b0;
end
always @(spc1_intrpt2_cmplt or spc1_atm_cntr2 or spc1_stb_state_ced2)
begin
if (spc1_intrpt2_cmplt && (spc1_atm_cntr2 != 9'h000) && (|spc1_stb_state_ced2))
spc1_atm_intrpt_capture2 <= 1'b1;
else
spc1_atm_intrpt_capture2 <= 1'b0;
end
always @(spc1_intrpt3_cmplt or spc1_atm_cntr3 or spc1_stb_state_ced3)
begin
if (spc1_intrpt3_cmplt && (spc1_atm_cntr3 != 9'h000) && (|spc1_stb_state_ced3))
spc1_atm_intrpt_capture3 <= 1'b1;
else
spc1_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc1_atm_cntr0 or spc1_dva_din or spc1_dva_wen)
begin
if (~spc1_dva_din && spc1_dva_wen && (spc1_atm_cntr0 != 9'h000))
spc1_atm_inv_capture0 <= 1'b1;
else
spc1_atm_inv_capture0 <= 1'b0;
end
always @(spc1_atm_cntr1 or spc1_dva_din or spc1_dva_wen)
begin
if (~spc1_dva_din && spc1_dva_wen && (spc1_atm_cntr1 != 9'h000))
spc1_atm_inv_capture1 <= 1'b1;
else
spc1_atm_inv_capture1 <= 1'b0;
end
always @(spc1_atm_cntr2 or spc1_dva_din or spc1_dva_wen)
begin
if (~spc1_dva_din && spc1_dva_wen && (spc1_atm_cntr2 != 9'h000))
spc1_atm_inv_capture2 <= 1'b1;
else
spc1_atm_inv_capture2 <= 1'b0;
end
always @(spc1_atm_cntr3 or spc1_dva_din or spc1_dva_wen)
begin
if (~spc1_dva_din && spc1_dva_wen && (spc1_atm_cntr3 != 9'h000))
spc1_atm_inv_capture3 <= 1'b1;
else
spc1_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc1_stb_state_vld0) && (spc1_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_atm_cntr0 <= 9'h000;
spc1_atm0_d <= 1'b0;
end
else if( spc1_atomic_g && (spc1_atm_type0 != 8'h00))
begin
spc1_atm_cntr0 <= spc1_atm_cntr0 + 1;
spc1_atm0_d <= 1'b1;
end
else if( spc1_atm0_d && (|spc1_stb_state_vld0))
begin
spc1_atm_cntr0 <= spc1_atm_cntr0 + 1;
spc1_atm0_d <= spc1_atm0_d;
end
else
begin
spc1_atm_cntr0 <= spc1_atm_cntr0;
spc1_atm0_d <= spc1_atm0_d;
end
if( ( ~(|spc1_stb_state_vld1) && (spc1_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_atm_cntr1 <= 9'h000;
spc1_atm1_d <= 1'b0;
end
else if( spc1_atomic_g && (spc1_atm_type1 != 8'h00))
begin
spc1_atm_cntr1 <= spc1_atm_cntr1 + 1;
spc1_atm1_d <= 1'b1;
end
else if( spc1_atm1_d && (|spc1_stb_state_vld1))
begin
spc1_atm_cntr1 <= spc1_atm_cntr1 + 1;
spc1_atm1_d <= spc1_atm1_d;
end
else
begin
spc1_atm_cntr1 <= spc1_atm_cntr1;
spc1_atm1_d <= spc1_atm1_d;
end
if( ( ~(|spc1_stb_state_vld2) && (spc1_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_atm_cntr2 <= 9'h000;
spc1_atm2_d <= 1'b0;
end
else if( spc1_atomic_g && (spc1_atm_type2 != 8'h00))
begin
spc1_atm_cntr2 <= spc1_atm_cntr2 + 1;
spc1_atm2_d <= 1'b1;
end
else if( spc1_atm2_d && (|spc1_stb_state_vld2))
begin
spc1_atm_cntr2 <= spc1_atm_cntr2 + 1;
spc1_atm2_d <= spc1_atm2_d;
end
else
begin
spc1_atm_cntr2 <= spc1_atm_cntr2;
spc1_atm2_d <= spc1_atm2_d;
end
if( ( ~(|spc1_stb_state_vld3) && (spc1_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_atm_cntr3 <= 9'h000;
spc1_atm3_d <= 1'b0;
end
else if( spc1_atomic_g && (spc1_atm_type3 != 8'h00))
begin
spc1_atm_cntr3 <= spc1_atm_cntr3 + 1;
spc1_atm3_d <= 1'b1;
end
else if( spc1_atm3_d && (|spc1_stb_state_vld3))
begin
spc1_atm_cntr3 <= spc1_atm_cntr3 + 1;
spc1_atm3_d <= spc1_atm3_d;
end
else
begin
spc1_atm_cntr3 <= spc1_atm_cntr3;
spc1_atm3_d <= spc1_atm3_d;
end
end
assign spc1_raw_ack_capture0 = spc1_stb_ack_vld0 && (spc1_stb_ack_cntr0 != 9'h000);
assign spc1_stb_ced0 = |spc1_stb_state_ced0;
assign spc1_raw_ack_capture1 = spc1_stb_ack_vld1 && (spc1_stb_ack_cntr1 != 9'h000);
assign spc1_stb_ced1 = |spc1_stb_state_ced1;
assign spc1_raw_ack_capture2 = spc1_stb_ack_vld2 && (spc1_stb_ack_cntr2 != 9'h000);
assign spc1_stb_ced2 = |spc1_stb_state_ced2;
assign spc1_raw_ack_capture3 = spc1_stb_ack_vld3 && (spc1_stb_ack_cntr3 != 9'h000);
assign spc1_stb_ced3 = |spc1_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc1_stb_ced0 && (spc1_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_stb_ced_cntr0 <= 9'h000;
spc1_stb_ced0_d <= 1'b0;
end
else if( spc1_stb_ced0 && (spc1_stb_state_ack0 == 8'h00))
begin
spc1_stb_ced_cntr0 <= spc1_stb_ced_cntr0 + 1;
spc1_stb_ced0_d <= spc1_stb_ced0;
end
else
begin
spc1_stb_ced_cntr0 <= spc1_stb_ced_cntr0;
spc1_stb_ced0_d <= spc1_stb_ced0_d;
end
if( ( ~spc1_mbar_vld0 && (spc1_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_mbar_vld_cntr0 <= 9'h000;
spc1_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_mbar_vld_counter = %d", spc1_mbar_vld_cntr0);
end
else if( spc1_mbar_vld0)
begin
spc1_mbar_vld_cntr0 <= spc1_mbar_vld_cntr0 + 1;
spc1_mbar_vld_d0 <= spc1_mbar_vld0;
end
else
begin
spc1_mbar_vld_cntr0 <= spc1_mbar_vld_cntr0;
spc1_mbar_vld_d0 <= spc1_mbar_vld0;
end
if( ( ~spc1_flsh_vld0 && (spc1_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_flsh_vld_cntr0 <= 9'h000;
spc1_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_flsh_vld_counter = %d", spc1_flsh_vld_cntr0);
end
else if( spc1_flsh_vld0)
begin
spc1_flsh_vld_cntr0 <= spc1_flsh_vld_cntr0 + 1;
spc1_flsh_vld_d0 <= spc1_flsh_vld0;
end
else
begin
spc1_flsh_vld_cntr0 <= spc1_flsh_vld_cntr0;
spc1_flsh_vld_d0 <= spc1_flsh_vld0;
end
if( ( ~spc1_stb_ced1 && (spc1_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_stb_ced_cntr1 <= 9'h000;
spc1_stb_ced1_d <= 1'b0;
end
else if( spc1_stb_ced1 && (spc1_stb_state_ack1 == 8'h00))
begin
spc1_stb_ced_cntr1 <= spc1_stb_ced_cntr1 + 1;
spc1_stb_ced1_d <= spc1_stb_ced1;
end
else
begin
spc1_stb_ced_cntr1 <= spc1_stb_ced_cntr1;
spc1_stb_ced1_d <= spc1_stb_ced1_d;
end
if( ( ~spc1_mbar_vld1 && (spc1_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_mbar_vld_cntr1 <= 9'h000;
spc1_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_mbar_vld_counter = %d", spc1_mbar_vld_cntr1);
end
else if( spc1_mbar_vld1)
begin
spc1_mbar_vld_cntr1 <= spc1_mbar_vld_cntr1 + 1;
spc1_mbar_vld_d1 <= spc1_mbar_vld1;
end
else
begin
spc1_mbar_vld_cntr1 <= spc1_mbar_vld_cntr1;
spc1_mbar_vld_d1 <= spc1_mbar_vld1;
end
if( ( ~spc1_flsh_vld1 && (spc1_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_flsh_vld_cntr1 <= 9'h000;
spc1_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_flsh_vld_counter = %d", spc1_flsh_vld_cntr1);
end
else if( spc1_flsh_vld1)
begin
spc1_flsh_vld_cntr1 <= spc1_flsh_vld_cntr1 + 1;
spc1_flsh_vld_d1 <= spc1_flsh_vld1;
end
else
begin
spc1_flsh_vld_cntr1 <= spc1_flsh_vld_cntr1;
spc1_flsh_vld_d1 <= spc1_flsh_vld1;
end
if( ( ~spc1_stb_ced2 && (spc1_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_stb_ced_cntr2 <= 9'h000;
spc1_stb_ced2_d <= 1'b0;
end
else if( spc1_stb_ced2 && (spc1_stb_state_ack2 == 8'h00))
begin
spc1_stb_ced_cntr2 <= spc1_stb_ced_cntr2 + 1;
spc1_stb_ced2_d <= spc1_stb_ced2;
end
else
begin
spc1_stb_ced_cntr2 <= spc1_stb_ced_cntr2;
spc1_stb_ced2_d <= spc1_stb_ced2_d;
end
if( ( ~spc1_mbar_vld2 && (spc1_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_mbar_vld_cntr2 <= 9'h000;
spc1_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_mbar_vld_counter = %d", spc1_mbar_vld_cntr2);
end
else if( spc1_mbar_vld2)
begin
spc1_mbar_vld_cntr2 <= spc1_mbar_vld_cntr2 + 1;
spc1_mbar_vld_d2 <= spc1_mbar_vld2;
end
else
begin
spc1_mbar_vld_cntr2 <= spc1_mbar_vld_cntr2;
spc1_mbar_vld_d2 <= spc1_mbar_vld2;
end
if( ( ~spc1_flsh_vld2 && (spc1_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_flsh_vld_cntr2 <= 9'h000;
spc1_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_flsh_vld_counter = %d", spc1_flsh_vld_cntr2);
end
else if( spc1_flsh_vld2)
begin
spc1_flsh_vld_cntr2 <= spc1_flsh_vld_cntr2 + 1;
spc1_flsh_vld_d2 <= spc1_flsh_vld2;
end
else
begin
spc1_flsh_vld_cntr2 <= spc1_flsh_vld_cntr2;
spc1_flsh_vld_d2 <= spc1_flsh_vld2;
end
if( ( ~spc1_stb_ced3 && (spc1_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_stb_ced_cntr3 <= 9'h000;
spc1_stb_ced3_d <= 1'b0;
end
else if( spc1_stb_ced3 && (spc1_stb_state_ack3 == 8'h00))
begin
spc1_stb_ced_cntr3 <= spc1_stb_ced_cntr3 + 1;
spc1_stb_ced3_d <= spc1_stb_ced3;
end
else
begin
spc1_stb_ced_cntr3 <= spc1_stb_ced_cntr3;
spc1_stb_ced3_d <= spc1_stb_ced3_d;
end
if( ( ~spc1_mbar_vld3 && (spc1_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_mbar_vld_cntr3 <= 9'h000;
spc1_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_mbar_vld_counter = %d", spc1_mbar_vld_cntr3);
end
else if( spc1_mbar_vld3)
begin
spc1_mbar_vld_cntr3 <= spc1_mbar_vld_cntr3 + 1;
spc1_mbar_vld_d3 <= spc1_mbar_vld3;
end
else
begin
spc1_mbar_vld_cntr3 <= spc1_mbar_vld_cntr3;
spc1_mbar_vld_d3 <= spc1_mbar_vld3;
end
if( ( ~spc1_flsh_vld3 && (spc1_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_flsh_vld_cntr3 <= 9'h000;
spc1_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_flsh_vld_counter = %d", spc1_flsh_vld_cntr3);
end
else if( spc1_flsh_vld3)
begin
spc1_flsh_vld_cntr3 <= spc1_flsh_vld_cntr3 + 1;
spc1_flsh_vld_d3 <= spc1_flsh_vld3;
end
else
begin
spc1_flsh_vld_cntr3 <= spc1_flsh_vld_cntr3;
spc1_flsh_vld_d3 <= spc1_flsh_vld3;
end
end
always @(spc1_flsh_vld_d0 or spc1_flsh_vld0)
begin
if (spc1_flsh_vld_d0 && ~spc1_flsh_vld0)
spc1_flsh_vld_capture0 <= 1'b1;
else
spc1_flsh_vld_capture0 <= 1'b0;
end
always @(spc1_flsh_vld_d1 or spc1_flsh_vld1)
begin
if (spc1_flsh_vld_d1 && ~spc1_flsh_vld1)
spc1_flsh_vld_capture1 <= 1'b1;
else
spc1_flsh_vld_capture1 <= 1'b0;
end
always @(spc1_flsh_vld_d2 or spc1_flsh_vld2)
begin
if (spc1_flsh_vld_d2 && ~spc1_flsh_vld2)
spc1_flsh_vld_capture2 <= 1'b1;
else
spc1_flsh_vld_capture2 <= 1'b0;
end
always @(spc1_flsh_vld_d3 or spc1_flsh_vld3)
begin
if (spc1_flsh_vld_d3 && ~spc1_flsh_vld3)
spc1_flsh_vld_capture3 <= 1'b1;
else
spc1_flsh_vld_capture3 <= 1'b0;
end
always @(spc1_lmiss_pa0 or spc1_imiss_pa or spc1_imiss_vld_d or spc1_lmiss_vld0)
begin
if((spc1_lmiss_pa0 == spc1_imiss_pa) && spc1_imiss_vld_d && spc1_lmiss_vld0)
spc1_lmiss_eq0 = 1'b1;
else
spc1_lmiss_eq0 = 1'b0;
end
always @(spc1_lmiss_pa1 or spc1_imiss_pa or spc1_imiss_vld_d or spc1_lmiss_vld1)
begin
if((spc1_lmiss_pa1 == spc1_imiss_pa) && spc1_imiss_vld_d && spc1_lmiss_vld1)
spc1_lmiss_eq1 = 1'b1;
else
spc1_lmiss_eq1 = 1'b0;
end
always @(spc1_lmiss_pa2 or spc1_imiss_pa or spc1_imiss_vld_d or spc1_lmiss_vld2)
begin
if((spc1_lmiss_pa2 == spc1_imiss_pa) && spc1_imiss_vld_d && spc1_lmiss_vld2)
spc1_lmiss_eq2 = 1'b1;
else
spc1_lmiss_eq2 = 1'b0;
end
always @(spc1_lmiss_pa3 or spc1_imiss_pa or spc1_imiss_vld_d or spc1_lmiss_vld3)
begin
if((spc1_lmiss_pa3 == spc1_imiss_pa) && spc1_imiss_vld_d && spc1_lmiss_vld3)
spc1_lmiss_eq3 = 1'b1;
else
spc1_lmiss_eq3 = 1'b0;
end
always @(spc1_lmiss_pa0 or spc1_stb_atm_addr0 or spc1_atm_cntr0 or spc1_lmiss_vld0)
begin
if ( ((spc1_lmiss_pa0 == spc1_stb_atm_addr0) && (spc1_atm_cntr0 != 9'h000) && spc1_lmiss_vld0) ||
((spc1_lmiss_pa1 == spc1_stb_atm_addr0) && (spc1_atm_cntr0 != 9'h000) && spc1_lmiss_vld1) ||
((spc1_lmiss_pa2 == spc1_stb_atm_addr0) && (spc1_atm_cntr0 != 9'h000) && spc1_lmiss_vld2) ||
((spc1_lmiss_pa3 == spc1_stb_atm_addr0) && (spc1_atm_cntr0 != 9'h000) && spc1_lmiss_vld3) )
spc1_atm_lmiss_eq0 = 1'b1;
else
spc1_atm_lmiss_eq0 = 1'b0;
end
always @(spc1_lmiss_pa1 or spc1_stb_atm_addr1 or spc1_atm_cntr1 or spc1_lmiss_vld1)
begin
if ( ((spc1_lmiss_pa0 == spc1_stb_atm_addr1) && (spc1_atm_cntr1 != 9'h000) && spc1_lmiss_vld0) ||
((spc1_lmiss_pa1 == spc1_stb_atm_addr1) && (spc1_atm_cntr1 != 9'h000) && spc1_lmiss_vld1) ||
((spc1_lmiss_pa2 == spc1_stb_atm_addr1) && (spc1_atm_cntr1 != 9'h000) && spc1_lmiss_vld2) ||
((spc1_lmiss_pa3 == spc1_stb_atm_addr1) && (spc1_atm_cntr1 != 9'h000) && spc1_lmiss_vld3) )
spc1_atm_lmiss_eq1 = 1'b1;
else
spc1_atm_lmiss_eq1 = 1'b0;
end
always @(spc1_lmiss_pa2 or spc1_stb_atm_addr2 or spc1_atm_cntr2 or spc1_lmiss_vld2)
begin
if ( ((spc1_lmiss_pa0 == spc1_stb_atm_addr2) && (spc1_atm_cntr2 != 9'h000) && spc1_lmiss_vld0) ||
((spc1_lmiss_pa1 == spc1_stb_atm_addr2) && (spc1_atm_cntr2 != 9'h000) && spc1_lmiss_vld1) ||
((spc1_lmiss_pa2 == spc1_stb_atm_addr2) && (spc1_atm_cntr2 != 9'h000) && spc1_lmiss_vld2) ||
((spc1_lmiss_pa3 == spc1_stb_atm_addr2) && (spc1_atm_cntr2 != 9'h000) && spc1_lmiss_vld3) )
spc1_atm_lmiss_eq2 = 1'b1;
else
spc1_atm_lmiss_eq2 = 1'b0;
end
always @(spc1_lmiss_pa3 or spc1_stb_atm_addr3 or spc1_atm_cntr3 or spc1_lmiss_vld3)
begin
if ( ((spc1_lmiss_pa0 == spc1_stb_atm_addr3) && (spc1_atm_cntr3 != 9'h000) && spc1_lmiss_vld0) ||
((spc1_lmiss_pa1 == spc1_stb_atm_addr3) && (spc1_atm_cntr3 != 9'h000) && spc1_lmiss_vld1) ||
((spc1_lmiss_pa2 == spc1_stb_atm_addr3) && (spc1_atm_cntr3 != 9'h000) && spc1_lmiss_vld2) ||
((spc1_lmiss_pa3 == spc1_stb_atm_addr3) && (spc1_atm_cntr3 != 9'h000) && spc1_lmiss_vld3) )
spc1_atm_lmiss_eq3 = 1'b1;
else
spc1_atm_lmiss_eq3 = 1'b0;
end
always @(spc1_imiss_pa or spc1_stb_atm_addr0 or spc1_atm_cntr0 or spc1_imiss_vld_d)
begin
if((spc1_imiss_pa == spc1_stb_atm_addr0) && (spc1_atm_cntr0 != 9'h000) && spc1_imiss_vld_d)
spc1_atm_imiss_eq0 = 1'b1;
else
spc1_atm_imiss_eq0 = 1'b0;
end
always @(spc1_imiss_pa or spc1_stb_atm_addr1 or spc1_atm_cntr1 or spc1_imiss_vld_d)
begin
if((spc1_imiss_pa == spc1_stb_atm_addr1) && (spc1_atm_cntr1 != 9'h000) && spc1_imiss_vld_d)
spc1_atm_imiss_eq1 = 1'b1;
else
spc1_atm_imiss_eq1 = 1'b0;
end
always @(spc1_imiss_pa or spc1_stb_atm_addr2 or spc1_atm_cntr2 or spc1_imiss_vld_d)
begin
if((spc1_imiss_pa == spc1_stb_atm_addr2) && (spc1_atm_cntr2 != 9'h000) && spc1_imiss_vld_d)
spc1_atm_imiss_eq2 = 1'b1;
else
spc1_atm_imiss_eq2 = 1'b0;
end
always @(spc1_imiss_pa or spc1_stb_atm_addr3 or spc1_atm_cntr3 or spc1_imiss_vld_d)
begin
if((spc1_imiss_pa == spc1_stb_atm_addr3) && (spc1_atm_cntr3 != 9'h000) && spc1_imiss_vld_d)
spc1_atm_imiss_eq3 = 1'b1;
else
spc1_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc1_imiss_vld || ~rst_l)
spc1_imiss_vld_d <= 1'b0;
else
spc1_imiss_vld_d <= spc1_imiss_vld;
if( ~spc1_ld_miss || ~rst_l)
spc1_ld_miss_capture <= 1'b0;
else
spc1_ld_miss_capture <= spc1_ld_miss;
end
always @(spc1_stb_ced0 or spc1_stb_ced0_d)
begin
if (~spc1_stb_ced0 && spc1_stb_ced0_d)
spc1_stb_ced_capture0 <= 1'b1;
else
spc1_stb_ced_capture0 <= 1'b0;
end
always @(spc1_stb_ced1 or spc1_stb_ced1_d)
begin
if (~spc1_stb_ced1 && spc1_stb_ced1_d)
spc1_stb_ced_capture1 <= 1'b1;
else
spc1_stb_ced_capture1 <= 1'b0;
end
always @(spc1_stb_ced2 or spc1_stb_ced2_d)
begin
if (~spc1_stb_ced2 && spc1_stb_ced2_d)
spc1_stb_ced_capture2 <= 1'b1;
else
spc1_stb_ced_capture2 <= 1'b0;
end
always @(spc1_stb_ced3 or spc1_stb_ced3_d)
begin
if (~spc1_stb_ced3 && spc1_stb_ced3_d)
spc1_stb_ced_capture3 <= 1'b1;
else
spc1_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc1_stb_state_ack0 != 8'h00 && (spc1_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_ack_counter0 = %d", spc1_stb_ack_cntr0);
end
else if(spc1_stb_cam_hit && spc1_ld0_inst_vld_g && (spc1_stb_state_ack0 == 8'h00))
begin
spc1_stb_ack_cntr0 <= spc1_stb_ack_cntr0 + 1;
end
else if( (spc1_stb_state_ack0 == 8'h00 ) && (spc1_stb_ack_cntr0 != 9'h000))
begin
spc1_stb_ack_cntr0 <= spc1_stb_ack_cntr0 + 1;
end // if ( (spc1_stb_state_ack0 == 8'h00 ) && (spc1_stb_ack_cntr0 != 9'h000))
else
begin
spc1_stb_ack_cntr0 <= spc1_stb_ack_cntr0;
end
if( (spc1_stb_state_ack1 != 8'h00 && (spc1_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_ack_counter1 = %d", spc1_stb_ack_cntr1);
end
else if(spc1_stb_cam_hit && spc1_ld1_inst_vld_g && (spc1_stb_state_ack1 == 8'h00))
begin
spc1_stb_ack_cntr1 <= spc1_stb_ack_cntr1 + 1;
end
else if( (spc1_stb_state_ack1 == 8'h00 ) && (spc1_stb_ack_cntr1 != 9'h000))
begin
spc1_stb_ack_cntr1 <= spc1_stb_ack_cntr1 + 1;
end // if ( (spc1_stb_state_ack1 == 8'h00 ) && (spc1_stb_ack_cntr1 != 9'h000))
else
begin
spc1_stb_ack_cntr1 <= spc1_stb_ack_cntr1;
end
if( (spc1_stb_state_ack2 != 8'h00 && (spc1_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_ack_counter2 = %d", spc1_stb_ack_cntr2);
end
else if(spc1_stb_cam_hit && spc1_ld2_inst_vld_g && (spc1_stb_state_ack2 == 8'h00))
begin
spc1_stb_ack_cntr2 <= spc1_stb_ack_cntr2 + 1;
end
else if( (spc1_stb_state_ack2 == 8'h00 ) && (spc1_stb_ack_cntr2 != 9'h000))
begin
spc1_stb_ack_cntr2 <= spc1_stb_ack_cntr2 + 1;
end // if ( (spc1_stb_state_ack2 == 8'h00 ) && (spc1_stb_ack_cntr2 != 9'h000))
else
begin
spc1_stb_ack_cntr2 <= spc1_stb_ack_cntr2;
end
if( (spc1_stb_state_ack3 != 8'h00 && (spc1_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_ack_counter3 = %d", spc1_stb_ack_cntr3);
end
else if(spc1_stb_cam_hit && spc1_ld3_inst_vld_g && (spc1_stb_state_ack3 == 8'h00))
begin
spc1_stb_ack_cntr3 <= spc1_stb_ack_cntr3 + 1;
end
else if( (spc1_stb_state_ack3 == 8'h00 ) && (spc1_stb_ack_cntr3 != 9'h000))
begin
spc1_stb_ack_cntr3 <= spc1_stb_ack_cntr3 + 1;
end // if ( (spc1_stb_state_ack3 == 8'h00 ) && (spc1_stb_ack_cntr3 != 9'h000))
else
begin
spc1_stb_ack_cntr3 <= spc1_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc1_stb0_full_w2 or spc1_stb0_full)
begin
if (~spc1_stb0_full_w2 && spc1_stb0_full)
spc1_stb_full_capture0 <= 1'b1;
else
spc1_stb_full_capture0 <= 1'b0;
end
always @(spc1_stb1_full_w2 or spc1_stb1_full)
begin
if (~spc1_stb1_full_w2 && spc1_stb1_full)
spc1_stb_full_capture1 <= 1'b1;
else
spc1_stb_full_capture1 <= 1'b0;
end
always @(spc1_stb2_full_w2 or spc1_stb2_full)
begin
if (~spc1_stb2_full_w2 && spc1_stb2_full)
spc1_stb_full_capture2 <= 1'b1;
else
spc1_stb_full_capture2 <= 1'b0;
end
always @(spc1_stb3_full_w2 or spc1_stb3_full)
begin
if (~spc1_stb3_full_w2 && spc1_stb3_full)
spc1_stb_full_capture3 <= 1'b1;
else
spc1_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc1_stb0_full && (spc1_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_full_counter0 = %d", spc1_stb_full_cntr0);
end
else if( spc1_stb0_full)
begin
spc1_stb_full_cntr0 <= spc1_stb_full_cntr0 + 1;
end
else
begin
spc1_stb_full_cntr0 <= spc1_stb_full_cntr0;
end
if( ( ~spc1_stb1_full && (spc1_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_full_counter1 = %d", spc1_stb_full_cntr1);
end
else if( spc1_stb1_full)
begin
spc1_stb_full_cntr1 <= spc1_stb_full_cntr1 + 1;
end
else
begin
spc1_stb_full_cntr1 <= spc1_stb_full_cntr1;
end
if( ( ~spc1_stb2_full && (spc1_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_full_counter2 = %d", spc1_stb_full_cntr2);
end
else if( spc1_stb2_full)
begin
spc1_stb_full_cntr2 <= spc1_stb_full_cntr2 + 1;
end
else
begin
spc1_stb_full_cntr2 <= spc1_stb_full_cntr2;
end
if( ( ~spc1_stb3_full && (spc1_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc1_stb_full_counter3 = %d", spc1_stb_full_cntr3);
end
else if( spc1_stb3_full)
begin
spc1_stb_full_cntr3 <= spc1_stb_full_cntr3 + 1;
end
else
begin
spc1_stb_full_cntr3 <= spc1_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc1_lmq0_full_d or spc1_lmq0_full)
begin
if (spc1_lmq0_full_d && ~spc1_lmq0_full)
spc1_lmq_full_capture0 <= 1'b1;
else
spc1_lmq_full_capture0 <= 1'b0;
end
always @(spc1_lmq1_full_d or spc1_lmq1_full)
begin
if (spc1_lmq1_full_d && ~spc1_lmq1_full)
spc1_lmq_full_capture1 <= 1'b1;
else
spc1_lmq_full_capture1 <= 1'b0;
end
always @(spc1_lmq2_full_d or spc1_lmq2_full)
begin
if (spc1_lmq2_full_d && ~spc1_lmq2_full)
spc1_lmq_full_capture2 <= 1'b1;
else
spc1_lmq_full_capture2 <= 1'b0;
end
always @(spc1_lmq3_full_d or spc1_lmq3_full)
begin
if (spc1_lmq3_full_d && ~spc1_lmq3_full)
spc1_lmq_full_capture3 <= 1'b1;
else
spc1_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc1_lmq0_full && (spc1_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc1_lmq_full_cntr0 <= 9'h000;
spc1_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_lmq_full_counter0 = %d", spc1_lmq_full_cntr0);
end
else if( spc1_lmq0_full)
begin
spc1_lmq_full_cntr0 <= spc1_lmq_full_cntr0 + 1;
spc1_lmq0_full_d <= spc1_lmq0_full;
end
else
begin
spc1_lmq_full_cntr0 <= spc1_lmq_full_cntr0;
spc1_lmq0_full_d <= spc1_lmq0_full;
end
if( ( ~spc1_lmq1_full && (spc1_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc1_lmq_full_cntr1 <= 9'h000;
spc1_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_lmq_full_counter1 = %d", spc1_lmq_full_cntr1);
end
else if( spc1_lmq1_full)
begin
spc1_lmq_full_cntr1 <= spc1_lmq_full_cntr1 + 1;
spc1_lmq1_full_d <= spc1_lmq1_full;
end
else
begin
spc1_lmq_full_cntr1 <= spc1_lmq_full_cntr1;
spc1_lmq1_full_d <= spc1_lmq1_full;
end
if( ( ~spc1_lmq2_full && (spc1_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc1_lmq_full_cntr2 <= 9'h000;
spc1_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_lmq_full_counter2 = %d", spc1_lmq_full_cntr2);
end
else if( spc1_lmq2_full)
begin
spc1_lmq_full_cntr2 <= spc1_lmq_full_cntr2 + 1;
spc1_lmq2_full_d <= spc1_lmq2_full;
end
else
begin
spc1_lmq_full_cntr2 <= spc1_lmq_full_cntr2;
spc1_lmq2_full_d <= spc1_lmq2_full;
end
if( ( ~spc1_lmq3_full && (spc1_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc1_lmq_full_cntr3 <= 9'h000;
spc1_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_lmq_full_counter3 = %d", spc1_lmq_full_cntr3);
end
else if( spc1_lmq3_full)
begin
spc1_lmq_full_cntr3 <= spc1_lmq_full_cntr3 + 1;
spc1_lmq3_full_d <= spc1_lmq3_full;
end
else
begin
spc1_lmq_full_cntr3 <= spc1_lmq_full_cntr3;
spc1_lmq3_full_d <= spc1_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc1_dfq_full_d or spc1_dfq_full)
begin
if (spc1_dfq_full_d && ~spc1_dfq_full)
spc1_dfq_full_capture <= 1'b1;
else
spc1_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc1_dfq_full && (spc1_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc1_dfq_full_cntr <= 9'h000;
spc1_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dfq_full_counter = %d", spc1_dfq_full_cntr);
end
else if( spc1_dfq_full)
begin
spc1_dfq_full_cntr <= spc1_dfq_full_cntr + 1;
spc1_dfq_full_d <= spc1_dfq_full;
end
else
begin
spc1_dfq_full_cntr <= spc1_dfq_full_cntr;
spc1_dfq_full_d <= spc1_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc1_dva_full_d or spc1_dva_inv)
begin
if (spc1_dva_full_d && ~spc1_dva_inv)
spc1_dva_full_capture <= 1'b1;
else
spc1_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc1_dva_din && spc1_dva_wen)
begin
spc1_dva_inv <= 1'b1;
spc1_dva_waddr_d <= spc1_dva_waddr;
end
else if(~spc1_dva_din && spc1_dva_wen)
begin
spc1_dva_inv <= 1'b0;
spc1_dva_waddr_d <= 5'b00000;
end
else
begin
spc1_dva_inv <= spc1_dva_inv;
spc1_dva_waddr_d <= spc1_dva_waddr_d;
end
end
always @(spc1_dva_raddr or spc1_dva_ren or spc1_dva_inv)
begin
if (spc1_dva_inv && spc1_dva_ren && (spc1_dva_raddr[6:2] == spc1_dva_waddr_d))
spc1_dva_vld2lkup <= 1'b1;
else
spc1_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc1_dva_inv && (spc1_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc1_dva_full_cntr <= 9'h000;
spc1_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dva_full_counter = %d", spc1_dva_full_cntr);
end
else if( spc1_dva_inv)
begin
spc1_dva_full_cntr <= spc1_dva_full_cntr + 1;
spc1_dva_full_d <= spc1_dva_inv;
end
else
begin
spc1_dva_full_cntr <= spc1_dva_full_cntr;
spc1_dva_full_d <= spc1_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc1_dva_vfull_d or spc1_dva_vld)
begin
if (spc1_dva_vfull_d && ~spc1_dva_vld)
spc1_dva_vfull_capture <= 1'b1;
else
spc1_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc1_dva_din && spc1_dva_wen)
begin
spc1_dva_vld <= 1'b1;
spc1_dva_invwaddr_d <= spc1_dva_waddr;
spc1_dva_invld_err <= spc1_dva_inv_perror;
end
else if(spc1_dva_din && spc1_dva_wen)
begin
spc1_dva_vld <= 1'b0;
spc1_dva_invwaddr_d <= 5'b00000;
spc1_dva_invld_err <= 1'b0;
end
else
begin
spc1_dva_vld <= spc1_dva_vld;
spc1_dva_invwaddr_d <= spc1_dva_invwaddr_d;
spc1_dva_invld_err <= spc1_dva_invld_err;
end
end
always @(spc1_dva_raddr or spc1_dva_ren or spc1_dva_vld)
begin
if (spc1_dva_vld && spc1_dva_ren && (spc1_dva_raddr[6:2] == spc1_dva_waddr_d))
spc1_dva_invld2lkup <= 1'b1;
else
spc1_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc1_dva_vld && (spc1_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc1_dva_vfull_cntr <= 9'h000;
spc1_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc1_dva_vfull_counter = %d", spc1_dva_vfull_cntr);
end
else if( spc1_dva_vld)
begin
spc1_dva_vfull_cntr <= spc1_dva_vfull_cntr + 1;
spc1_dva_vfull_d <= spc1_dva_vld;
end
else
begin
spc1_dva_vfull_cntr <= spc1_dva_vfull_cntr;
spc1_dva_vfull_d <= spc1_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc1_dva_raddr or spc1_dva_waddr or spc1_dva_ren or spc1_dva_wen)
begin
if ( spc1_dva_ren && spc1_dva_wen && (spc1_dva_raddr[6:2] == spc1_dva_waddr))
spc1_dva_collide <= 1'b1;
else
spc1_dva_collide <= 1'b0;
end
// dva error cases
always @(spc1_dva_raddr or spc1_dva_ren or spc1_dva_dtag_perror or spc1_dva_dtag_perror)
begin
if (spc1_dva_ren && (spc1_dva_dtag_perror || spc1_dva_dtag_perror))
spc1_dva_err <= 1'b1;
else
spc1_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc1_dva_err)
spc1_dva_efull_d <= 1'b1;
else
spc1_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc1_dva_ren && ~(spc1_dva_dtag_perror || spc1_dva_dtag_perror ) &&
(spc1_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc1_dva_efull_cntr <= 9'h000;
spc1_dva_raddr_d <= spc1_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc1_dva_efull_counter = %d", spc1_dva_efull_cntr);
end
else if(spc1_dva_efull_d)
begin
spc1_dva_efull_cntr <= spc1_dva_efull_cntr + 1;
spc1_dva_raddr_d <= spc1_dva_raddr_d;
end
else
begin
spc1_dva_efull_cntr <= spc1_dva_efull_cntr;
spc1_dva_raddr_d <= spc1_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC2
wire spc2_dva_ren = `TOP_DESIGN.sparc2.lsu.ifu_lsu_ld_inst_e;
wire spc2_dva_wen = `TOP_DESIGN.sparc2.lsu.lsu_dtagv_wr_vld_e;
wire spc2_dva_din = `TOP_DESIGN.sparc2.lsu.dva_din_e;
wire [3:0] spc2_dva_dout = `TOP_DESIGN.sparc2.lsu.dva_vld_m[3:0];
wire [6:0] spc2_dva_raddr = `TOP_DESIGN.sparc2.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc2_dva_waddr = `TOP_DESIGN.sparc2.lsu.dva_wr_adr_e[10:6];
wire spc2_dva_dtag_perror = `TOP_DESIGN.sparc2.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc2_dva_dcache_perror = `TOP_DESIGN.sparc2.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc2_dva_inv_perror = `TOP_DESIGN.sparc2.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc2_ld_miss = `TOP_DESIGN.sparc2.lsu.dctl.lsu_ld_miss_wb;
reg spc2_ld_miss_capture;
wire spc2_atomic_g = `TOP_DESIGN.sparc2.lsu.qctl1.atomic_g;
wire [1:0] spc2_atm_type0 = `TOP_DESIGN.sparc2.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc2_atm_type1 = `TOP_DESIGN.sparc2.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc2_atm_type2 = `TOP_DESIGN.sparc2.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc2_atm_type3 = `TOP_DESIGN.sparc2.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc2_dctl_lsu_way_hit = `TOP_DESIGN.sparc2.lsu.dctl.lsu_way_hit;
wire spc2_dctl_dcache_enable_g = `TOP_DESIGN.sparc2.lsu.dctl.dcache_enable_g;
wire spc2_dctl_ldxa_internal = `TOP_DESIGN.sparc2.lsu.dctl.ldxa_internal;
wire spc2_dctl_ldst_dbl_g = `TOP_DESIGN.sparc2.lsu.dctl.ldst_dbl_g;
wire spc2_dctl_atomic_g = `TOP_DESIGN.sparc2.lsu.dctl.atomic_g;
wire spc2_dctl_stb_cam_hit = `TOP_DESIGN.sparc2.lsu.dctl.stb_cam_hit;
wire spc2_dctl_endian_mispred_g = `TOP_DESIGN.sparc2.lsu.dctl.endian_mispred_g;
wire spc2_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc2.lsu.dctl.dcache_rd_parity_error;
wire spc2_dctl_dtag_perror_g = `TOP_DESIGN.sparc2.lsu.dctl.dtag_perror_g;
wire spc2_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc2.lsu.dctl.tte_data_perror_unc;
wire spc2_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc2.lsu.dctl.ld_inst_vld_g;
wire spc2_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc2.lsu.dctl.lsu_alt_space_g;
wire spc2_dctl_recognized_asi_g = `TOP_DESIGN.sparc2.lsu.dctl.recognized_asi_g;
wire spc2_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc2.lsu.dctl.ncache_asild_rq_g ;
wire spc2_dctl_bld_hit;
wire spc2_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc2_ixinv0 = `TOP_DESIGN.sparc2.lsu.qctl2.imiss0_inv_en;
wire spc2_ixinv1 = `TOP_DESIGN.sparc2.lsu.qctl2.imiss1_inv_en;
wire spc2_ixinv2 = `TOP_DESIGN.sparc2.lsu.qctl2.imiss2_inv_en;
wire spc2_ixinv3 = `TOP_DESIGN.sparc2.lsu.qctl2.imiss3_inv_en;
wire spc2_ifill = `TOP_DESIGN.sparc2.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc2_inv = `TOP_DESIGN.sparc2.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc2_inv_clr = `TOP_DESIGN.sparc2.lsu.qctl2.ifu_lsu_inv_clear;
wire spc2_ibuf_busy = `TOP_DESIGN.sparc2.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc2_l2 = `TOP_DESIGN.sparc2.lsu.dctl.l2fill_vld_g ;
wire spc2_unc = `TOP_DESIGN.sparc2.lsu.dctl.unc_err_trap_g ;
wire spc2_fpld = `TOP_DESIGN.sparc2.lsu.dctl.l2fill_fpld_g ;
wire spc2_fpldst = `TOP_DESIGN.sparc2.lsu.dctl.fp_ldst_g ;
wire spc2_unflush = `TOP_DESIGN.sparc2.lsu.dctl.ld_inst_vld_unflushed ;
wire spc2_ldw = `TOP_DESIGN.sparc2.lsu.dctl.lsu_inst_vld_w ;
wire spc2_byp = `TOP_DESIGN.sparc2.lsu.dctl.intld_byp_data_vld_m ;
wire spc2_flsh = `TOP_DESIGN.sparc2.lsu.lsu_exu_flush_pipe_w ;
wire spc2_chm = `TOP_DESIGN.sparc2.lsu.dctl.common_ldst_miss_w ;
wire spc2_ldxa = `TOP_DESIGN.sparc2.lsu.dctl.ldxa_internal ;
wire spc2_ato = `TOP_DESIGN.sparc2.lsu.dctl.atomic_g ;
wire spc2_pref = `TOP_DESIGN.sparc2.lsu.dctl.pref_inst_g ;
wire spc2_chit = `TOP_DESIGN.sparc2.lsu.dctl.stb_cam_hit ;
wire spc2_dcp = `TOP_DESIGN.sparc2.lsu.dctl.dcache_rd_parity_error ;
wire spc2_dtp = `TOP_DESIGN.sparc2.lsu.dctl.dtag_perror_g ;
//wire spc2_mpc = `TOP_DESIGN.sparc2.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc2_mpc = 1'b0;
wire spc2_mpu = `TOP_DESIGN.sparc2.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc2_exu_und;
reg [4:0] spc2_exu;
// excptn
wire spc2_exp_wtchpt_trp_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc2_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc2_exp_priv_violtn_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc2_exp_daccess_excptn_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc2_exp_daccess_prot_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc2_exp_priv_action_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc2_exp_spec_access_epage_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc2_exp_uncache_atomic_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc2_exp_illegal_asi_action_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc2_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc2_exp_asi_rd_unc = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc2_exp_tlb_data_ce = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc2_exp_asi_rd_unc = 1'b0;
wire spc2_exp_tlb_data_ce = 1'b0;
wire spc2_exp_tlb_data_ue = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc2_exp_tlb_tag_ue = `TOP_DESIGN.sparc2.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc2_exp_unc = `TOP_DESIGN.sparc2.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc2_exp_corr = `TOP_DESIGN.sparc2.lsu.excpctl.tte_data_perror_corr;
wire spc2_exp_corr = 1'b0;
wire [15:0] spc2_exp_und;
reg [4:0] spc2_exp;
// dctl cmplt
wire spc2_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc2.lsu.dctl.stxa_internal_d2;
wire spc2_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc2.lsu.dctl.lsu_l2fill_vld;
wire spc2_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc2.lsu.dctl.atomic_ld_squash_e;
wire spc2_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc2.lsu.qctl2.lsu_ignore_fill;
wire spc2_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc2.lsu.dctl.l2fill_fpld_e;
// wire spc2_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc2.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc2_dctl_fill_err_trap_e = `TOP_DESIGN.sparc2.lsu.dctl.fill_err_trap_e;
wire spc2_dctl_l2_corr_error_e = `TOP_DESIGN.sparc2.lsu.dctl.l2_corr_error_e;
wire [3:0] spc2_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc2.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc2_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc2.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc2_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc2.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc2_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc2.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc2_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc2.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc2_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc2.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc2_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc2_ldstcond_cmplt_d;
wire spc2_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc2.lsu.qctl1.ld_sec_hit_thrd0;
wire spc2_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_inst_vld_g;
wire spc2_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc2_ld0_pkt_vld_unmasked_d;
reg spc2_qctl1_ld_sec_hit_thrd0_w2;
wire spc2_dctl_thread0_w3 = `TOP_DESIGN.sparc2.lsu.dctl.thread0_w3;
wire spc2_dctl_dfill_thread0 = `TOP_DESIGN.sparc2.lsu.dctl.dfill_thread0;
wire spc2_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc2.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc2_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc2.lsu.dctl.diag_wr_cmplt0;
wire spc2_dctl_bsync0_reset = `TOP_DESIGN.sparc2.lsu.dctl.bsync0_reset;
wire spc2_dctl_late_cmplt0 = `TOP_DESIGN.sparc2.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc2_dctl_stxa_cmplt0;
wire spc2_dctl_l2fill_cmplt0;
wire spc2_dctl_atm_cmplt0;
wire spc2_dctl_fillerr0;
wire [4:0] spc2_cmplt0;
wire [5:0] spc2_dctl_ldst_cond_cmplt0;
reg [3:0] spc2_ldstcond_cmplt0;
reg [3:0] spc2_ldstcond_cmplt0_d;
wire spc2_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc2.lsu.qctl1.ld_sec_hit_thrd1;
wire spc2_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_inst_vld_g;
wire spc2_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc2_ld1_pkt_vld_unmasked_d;
reg spc2_qctl1_ld_sec_hit_thrd1_w2;
wire spc2_dctl_thread1_w3 = `TOP_DESIGN.sparc2.lsu.dctl.thread1_w3;
wire spc2_dctl_dfill_thread1 = `TOP_DESIGN.sparc2.lsu.dctl.dfill_thread1;
wire spc2_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc2.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc2_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc2.lsu.dctl.diag_wr_cmplt1;
wire spc2_dctl_bsync1_reset = `TOP_DESIGN.sparc2.lsu.dctl.bsync1_reset;
wire spc2_dctl_late_cmplt1 = `TOP_DESIGN.sparc2.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc2_dctl_stxa_cmplt1;
wire spc2_dctl_l2fill_cmplt1;
wire spc2_dctl_atm_cmplt1;
wire spc2_dctl_fillerr1;
wire [4:0] spc2_cmplt1;
wire [5:0] spc2_dctl_ldst_cond_cmplt1;
reg [3:0] spc2_ldstcond_cmplt1;
reg [3:0] spc2_ldstcond_cmplt1_d;
wire spc2_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc2.lsu.qctl1.ld_sec_hit_thrd2;
wire spc2_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_inst_vld_g;
wire spc2_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc2_ld2_pkt_vld_unmasked_d;
reg spc2_qctl1_ld_sec_hit_thrd2_w2;
wire spc2_dctl_thread2_w3 = `TOP_DESIGN.sparc2.lsu.dctl.thread2_w3;
wire spc2_dctl_dfill_thread2 = `TOP_DESIGN.sparc2.lsu.dctl.dfill_thread2;
wire spc2_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc2.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc2_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc2.lsu.dctl.diag_wr_cmplt2;
wire spc2_dctl_bsync2_reset = `TOP_DESIGN.sparc2.lsu.dctl.bsync2_reset;
wire spc2_dctl_late_cmplt2 = `TOP_DESIGN.sparc2.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc2_dctl_stxa_cmplt2;
wire spc2_dctl_l2fill_cmplt2;
wire spc2_dctl_atm_cmplt2;
wire spc2_dctl_fillerr2;
wire [4:0] spc2_cmplt2;
wire [5:0] spc2_dctl_ldst_cond_cmplt2;
reg [3:0] spc2_ldstcond_cmplt2;
reg [3:0] spc2_ldstcond_cmplt2_d;
wire spc2_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc2.lsu.qctl1.ld_sec_hit_thrd3;
wire spc2_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_inst_vld_g;
wire spc2_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc2_ld3_pkt_vld_unmasked_d;
reg spc2_qctl1_ld_sec_hit_thrd3_w2;
wire spc2_dctl_thread3_w3 = `TOP_DESIGN.sparc2.lsu.dctl.thread3_w3;
wire spc2_dctl_dfill_thread3 = `TOP_DESIGN.sparc2.lsu.dctl.dfill_thread3;
wire spc2_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc2.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc2_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc2.lsu.dctl.diag_wr_cmplt3;
wire spc2_dctl_bsync3_reset = `TOP_DESIGN.sparc2.lsu.dctl.bsync3_reset;
wire spc2_dctl_late_cmplt3 = `TOP_DESIGN.sparc2.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc2_dctl_stxa_cmplt3;
wire spc2_dctl_l2fill_cmplt3;
wire spc2_dctl_atm_cmplt3;
wire spc2_dctl_fillerr3;
wire [4:0] spc2_cmplt3;
wire [5:0] spc2_dctl_ldst_cond_cmplt3;
reg [3:0] spc2_ldstcond_cmplt3;
reg [3:0] spc2_ldstcond_cmplt3_d;
wire spc2_qctl1_bld_g = `TOP_DESIGN.sparc2.lsu.qctl1.bld_g;
wire spc2_qctl1_bld_reset = `TOP_DESIGN.sparc2.lsu.qctl1.bld_reset;
wire [1:0] spc2_qctl1_bld_cnt = `TOP_DESIGN.sparc2.lsu.qctl1.bld_cnt;
reg [9:0] spc2_bld0_full_cntr;
reg [1:0] spc2_bld0_full_d;
reg spc2_bld0_full_capture;
reg [9:0] spc2_bld1_full_cntr;
reg [1:0] spc2_bld1_full_d;
reg spc2_bld1_full_capture;
reg [9:0] spc2_bld2_full_cntr;
reg [1:0] spc2_bld2_full_d;
reg spc2_bld2_full_capture;
reg [9:0] spc2_bld3_full_cntr;
reg [1:0] spc2_bld3_full_d;
reg spc2_bld3_full_capture;
wire spc2_ipick = `TOP_DESIGN.sparc2.lsu.qctl1.imiss_pcx_rq_vld;
wire spc2_lpick = `TOP_DESIGN.sparc2.lsu.qctl1.ld_pcx_rq_all;
wire spc2_spick = `TOP_DESIGN.sparc2.lsu.qctl1.st_pcx_rq_all;
wire spc2_mpick = `TOP_DESIGN.sparc2.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc2_apick = `TOP_DESIGN.sparc2.lsu.qctl1.all_pcx_rq_pick;
wire spc2_msquash = `TOP_DESIGN.sparc2.lsu.qctl1.mcycle_squash_d1;
reg spc2_fpicko;
wire [3:0] spc2_fpick;
wire [39:0] spc2_imiss_pa = `TOP_DESIGN.sparc2.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc2_imiss_vld = `TOP_DESIGN.sparc2.lsu.qctl1.imiss_pcx_rq_vld;
reg spc2_imiss_vld_d;
wire [39:0] spc2_lmiss_pa0 = `TOP_DESIGN.sparc2.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc2_lmiss_vld0 = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_pcx_rq_vld;
wire spc2_ld_pkt_vld0 = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_pkt_vld;
wire spc2_st_pkt_vld0 = `TOP_DESIGN.sparc2.lsu.qctl1.st0_pkt_vld;
reg spc2_lmiss_eq0;
reg spc2_atm_imiss_eq0;
wire [39:0] spc2_lmiss_pa1 = `TOP_DESIGN.sparc2.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc2_lmiss_vld1 = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_pcx_rq_vld;
wire spc2_ld_pkt_vld1 = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_pkt_vld;
wire spc2_st_pkt_vld1 = `TOP_DESIGN.sparc2.lsu.qctl1.st1_pkt_vld;
reg spc2_lmiss_eq1;
reg spc2_atm_imiss_eq1;
wire [39:0] spc2_lmiss_pa2 = `TOP_DESIGN.sparc2.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc2_lmiss_vld2 = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_pcx_rq_vld;
wire spc2_ld_pkt_vld2 = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_pkt_vld;
wire spc2_st_pkt_vld2 = `TOP_DESIGN.sparc2.lsu.qctl1.st2_pkt_vld;
reg spc2_lmiss_eq2;
reg spc2_atm_imiss_eq2;
wire [39:0] spc2_lmiss_pa3 = `TOP_DESIGN.sparc2.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc2_lmiss_vld3 = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_pcx_rq_vld;
wire spc2_ld_pkt_vld3 = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_pkt_vld;
wire spc2_st_pkt_vld3 = `TOP_DESIGN.sparc2.lsu.qctl1.st3_pkt_vld;
reg spc2_lmiss_eq3;
reg spc2_atm_imiss_eq3;
wire [44:0] spc2_wdata_ramc = `TOP_DESIGN.sparc2.lsu.stb_cam.wdata_ramc;
wire spc2_wptr_vld = `TOP_DESIGN.sparc2.lsu.stb_cam.wptr_vld;
wire [75:0] spc2_wdata_ramd = {`TOP_DESIGN.sparc2.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc2.lsu.lsu_stb_st_data_g[63:0]};
wire spc2_stb_cam_hit = `TOP_DESIGN.sparc2.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc2_stb_cam_hit_ptr = `TOP_DESIGN.sparc2.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc2_stb_ld_full_raw = `TOP_DESIGN.sparc2.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc2_stb_ld_partial_raw = `TOP_DESIGN.sparc2.lsu.stb_ld_partial_raw[7:0];
wire spc2_stb_cam_mhit = `TOP_DESIGN.sparc2.lsu.stb_cam_mhit;
wire [3:0] spc2_dfq_vld_entries = `TOP_DESIGN.sparc2.lsu.qctl2.dfq_vld_entries;
wire spc2_dfq_full;
reg [9:0] spc2_dfq_full_cntr;
reg spc2_dfq_full_d;
reg spc2_dfq_full_capture;
reg [9:0] spc2_dfq_full_cntr1;
reg spc2_dfq_full_d1;
wire spc2_dfq_full1;
reg spc2_dfq_full_capture1;
reg [9:0] spc2_dfq_full_cntr2;
reg spc2_dfq_full_d2;
wire spc2_dfq_full2;
reg spc2_dfq_full_capture2;
reg [9:0] spc2_dfq_full_cntr3;
reg spc2_dfq_full_d3;
wire spc2_dfq_full3;
reg spc2_dfq_full_capture3;
reg [9:0] spc2_dfq_full_cntr4;
reg spc2_dfq_full_d4;
wire spc2_dfq_full4;
reg spc2_dfq_full_capture4;
reg [9:0] spc2_dfq_full_cntr5;
reg spc2_dfq_full_d5;
wire spc2_dfq_full5;
reg spc2_dfq_full_capture5;
reg [9:0] spc2_dfq_full_cntr6;
reg spc2_dfq_full_d6;
wire spc2_dfq_full6;
reg spc2_dfq_full_capture6;
reg [9:0] spc2_dfq_full_cntr7;
reg spc2_dfq_full_d7;
wire spc2_dfq_full7;
reg spc2_dfq_full_capture7;
wire spc2_dva_rdwrhit;
reg [9:0] spc2_dva_full_cntr;
reg spc2_dva_full_d;
reg spc2_dva_full_capture;
reg spc2_dva_inv;
reg spc2_dva_inv_d;
reg spc2_dva_vld;
reg spc2_dva_vld_d;
reg [9:0] spc2_dva_vfull_cntr;
reg spc2_dva_vfull_d;
reg spc2_dva_vfull_capture;
reg spc2_dva_collide;
reg spc2_dva_vld2lkup;
reg spc2_dva_invld2lkup;
reg spc2_dva_invld_err;
reg [9:0] spc2_dva_efull_cntr;
reg spc2_dva_efull_d;
reg spc2_dva_vlddtag_err;
reg spc2_dva_vlddcache_err;
reg spc2_dva_err;
reg [6:0] spc2_dva_raddr_d;
reg [4:0] spc2_dva_waddr_d;
reg [4:0] spc2_dva_invwaddr_d;
reg spc2_ld0_lt_1;
reg spc2_ld0_lt_2;
reg spc2_ld0_lt_3;
reg spc2_ld1_lt_0;
reg spc2_ld1_lt_2;
reg spc2_ld1_lt_3;
reg spc2_ld2_lt_0;
reg spc2_ld2_lt_1;
reg spc2_ld2_lt_3;
reg spc2_ld3_lt_0;
reg spc2_ld3_lt_1;
reg spc2_ld3_lt_2;
reg spc2_st0_lt_1;
reg spc2_st0_lt_2;
reg spc2_st0_lt_3;
reg spc2_st1_lt_0;
reg spc2_st1_lt_2;
reg spc2_st1_lt_3;
reg spc2_st2_lt_0;
reg spc2_st2_lt_1;
reg spc2_st2_lt_3;
reg spc2_st3_lt_0;
reg spc2_st3_lt_1;
reg spc2_st3_lt_2;
wire [11:0] spc2_ld_ooo_ret;
wire [11:0] spc2_st_ooo_ret;
wire [7:0] spc2_stb_state_vld0 = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc2_stb_state_ack0 = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc2_stb_state_ced0 = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc2_stb_state_rst0 = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_state_rst;
wire spc2_stb_ack_vld0 = `TOP_DESIGN.sparc2.lsu.stb_ctl0.ack_vld;
wire spc2_ld0_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_inst_vld_g;
wire spc2_intrpt0_cmplt = `TOP_DESIGN.sparc2.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc2_stb0_full = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_full;
wire spc2_stb0_full_w2 = `TOP_DESIGN.sparc2.lsu.stb_ctl0.stb_full_w2;
wire spc2_lmq0_full = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_pcx_rq_vld;
wire spc2_mbar_vld0 = `TOP_DESIGN.sparc2.lsu.dctl.mbar_vld0;
wire spc2_ld0_unfilled = `TOP_DESIGN.sparc2.lsu.qctl1.ld0_unfilled;
wire spc2_flsh_vld0 = `TOP_DESIGN.sparc2.lsu.dctl.flsh_vld0;
reg [9:0] spc2_ld0_unf_cntr;
reg spc2_ld0_unfilled_d;
reg [9:0] spc2_st0_unf_cntr;
reg spc2_st0_unfilled_d;
reg spc2_st0_unfilled;
reg spc2_mbar_vld_d0;
reg spc2_flsh_vld_d0;
reg spc2_lmq0_full_d;
reg [9:0] spc2_lmq_full_cntr0;
reg spc2_lmq_full_capture0;
reg [9:0] spc2_stb_full_cntr0;
reg spc2_stb_full_capture0;
reg [9:0] spc2_mbar_vld_cntr0;
reg spc2_mbar_vld_capture0;
reg [9:0] spc2_flsh_vld_cntr0;
reg spc2_flsh_vld_capture0;
reg spc2_stb_head_hit0;
wire spc2_raw_ack_capture0;
reg [9:0] spc2_stb_ack_cntr0;
reg [9:0] spc2_stb_ced_cntr0;
reg spc2_stb_ced0_d;
reg spc2_stb_ced_capture0;
wire spc2_stb_ced0;
reg spc2_atm0_d;
reg [9:0] spc2_atm_cntr0;
reg spc2_atm_intrpt_capture0;
reg spc2_atm_intrpt_b4capture0;
reg spc2_atm_inv_capture0;
reg [39:0] spc2_stb_wr_addr0;
reg [39:0] spc2_stb_atm_addr0;
reg spc2_atm_lmiss_eq0;
wire [7:0] spc2_stb_state_vld1 = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc2_stb_state_ack1 = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc2_stb_state_ced1 = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc2_stb_state_rst1 = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_state_rst;
wire spc2_stb_ack_vld1 = `TOP_DESIGN.sparc2.lsu.stb_ctl1.ack_vld;
wire spc2_ld1_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_inst_vld_g;
wire spc2_intrpt1_cmplt = `TOP_DESIGN.sparc2.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc2_stb1_full = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_full;
wire spc2_stb1_full_w2 = `TOP_DESIGN.sparc2.lsu.stb_ctl1.stb_full_w2;
wire spc2_lmq1_full = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_pcx_rq_vld;
wire spc2_mbar_vld1 = `TOP_DESIGN.sparc2.lsu.dctl.mbar_vld1;
wire spc2_ld1_unfilled = `TOP_DESIGN.sparc2.lsu.qctl1.ld1_unfilled;
wire spc2_flsh_vld1 = `TOP_DESIGN.sparc2.lsu.dctl.flsh_vld1;
reg [9:0] spc2_ld1_unf_cntr;
reg spc2_ld1_unfilled_d;
reg [9:0] spc2_st1_unf_cntr;
reg spc2_st1_unfilled_d;
reg spc2_st1_unfilled;
reg spc2_mbar_vld_d1;
reg spc2_flsh_vld_d1;
reg spc2_lmq1_full_d;
reg [9:0] spc2_lmq_full_cntr1;
reg spc2_lmq_full_capture1;
reg [9:0] spc2_stb_full_cntr1;
reg spc2_stb_full_capture1;
reg [9:0] spc2_mbar_vld_cntr1;
reg spc2_mbar_vld_capture1;
reg [9:0] spc2_flsh_vld_cntr1;
reg spc2_flsh_vld_capture1;
reg spc2_stb_head_hit1;
wire spc2_raw_ack_capture1;
reg [9:0] spc2_stb_ack_cntr1;
reg [9:0] spc2_stb_ced_cntr1;
reg spc2_stb_ced1_d;
reg spc2_stb_ced_capture1;
wire spc2_stb_ced1;
reg spc2_atm1_d;
reg [9:0] spc2_atm_cntr1;
reg spc2_atm_intrpt_capture1;
reg spc2_atm_intrpt_b4capture1;
reg spc2_atm_inv_capture1;
reg [39:0] spc2_stb_wr_addr1;
reg [39:0] spc2_stb_atm_addr1;
reg spc2_atm_lmiss_eq1;
wire [7:0] spc2_stb_state_vld2 = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc2_stb_state_ack2 = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc2_stb_state_ced2 = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc2_stb_state_rst2 = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_state_rst;
wire spc2_stb_ack_vld2 = `TOP_DESIGN.sparc2.lsu.stb_ctl2.ack_vld;
wire spc2_ld2_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_inst_vld_g;
wire spc2_intrpt2_cmplt = `TOP_DESIGN.sparc2.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc2_stb2_full = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_full;
wire spc2_stb2_full_w2 = `TOP_DESIGN.sparc2.lsu.stb_ctl2.stb_full_w2;
wire spc2_lmq2_full = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_pcx_rq_vld;
wire spc2_mbar_vld2 = `TOP_DESIGN.sparc2.lsu.dctl.mbar_vld2;
wire spc2_ld2_unfilled = `TOP_DESIGN.sparc2.lsu.qctl1.ld2_unfilled;
wire spc2_flsh_vld2 = `TOP_DESIGN.sparc2.lsu.dctl.flsh_vld2;
reg [9:0] spc2_ld2_unf_cntr;
reg spc2_ld2_unfilled_d;
reg [9:0] spc2_st2_unf_cntr;
reg spc2_st2_unfilled_d;
reg spc2_st2_unfilled;
reg spc2_mbar_vld_d2;
reg spc2_flsh_vld_d2;
reg spc2_lmq2_full_d;
reg [9:0] spc2_lmq_full_cntr2;
reg spc2_lmq_full_capture2;
reg [9:0] spc2_stb_full_cntr2;
reg spc2_stb_full_capture2;
reg [9:0] spc2_mbar_vld_cntr2;
reg spc2_mbar_vld_capture2;
reg [9:0] spc2_flsh_vld_cntr2;
reg spc2_flsh_vld_capture2;
reg spc2_stb_head_hit2;
wire spc2_raw_ack_capture2;
reg [9:0] spc2_stb_ack_cntr2;
reg [9:0] spc2_stb_ced_cntr2;
reg spc2_stb_ced2_d;
reg spc2_stb_ced_capture2;
wire spc2_stb_ced2;
reg spc2_atm2_d;
reg [9:0] spc2_atm_cntr2;
reg spc2_atm_intrpt_capture2;
reg spc2_atm_intrpt_b4capture2;
reg spc2_atm_inv_capture2;
reg [39:0] spc2_stb_wr_addr2;
reg [39:0] spc2_stb_atm_addr2;
reg spc2_atm_lmiss_eq2;
wire [7:0] spc2_stb_state_vld3 = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc2_stb_state_ack3 = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc2_stb_state_ced3 = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc2_stb_state_rst3 = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_state_rst;
wire spc2_stb_ack_vld3 = `TOP_DESIGN.sparc2.lsu.stb_ctl3.ack_vld;
wire spc2_ld3_inst_vld_g = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_inst_vld_g;
wire spc2_intrpt3_cmplt = `TOP_DESIGN.sparc2.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc2_stb3_full = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_full;
wire spc2_stb3_full_w2 = `TOP_DESIGN.sparc2.lsu.stb_ctl3.stb_full_w2;
wire spc2_lmq3_full = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_pcx_rq_vld;
wire spc2_mbar_vld3 = `TOP_DESIGN.sparc2.lsu.dctl.mbar_vld3;
wire spc2_ld3_unfilled = `TOP_DESIGN.sparc2.lsu.qctl1.ld3_unfilled;
wire spc2_flsh_vld3 = `TOP_DESIGN.sparc2.lsu.dctl.flsh_vld3;
reg [9:0] spc2_ld3_unf_cntr;
reg spc2_ld3_unfilled_d;
reg [9:0] spc2_st3_unf_cntr;
reg spc2_st3_unfilled_d;
reg spc2_st3_unfilled;
reg spc2_mbar_vld_d3;
reg spc2_flsh_vld_d3;
reg spc2_lmq3_full_d;
reg [9:0] spc2_lmq_full_cntr3;
reg spc2_lmq_full_capture3;
reg [9:0] spc2_stb_full_cntr3;
reg spc2_stb_full_capture3;
reg [9:0] spc2_mbar_vld_cntr3;
reg spc2_mbar_vld_capture3;
reg [9:0] spc2_flsh_vld_cntr3;
reg spc2_flsh_vld_capture3;
reg spc2_stb_head_hit3;
wire spc2_raw_ack_capture3;
reg [9:0] spc2_stb_ack_cntr3;
reg [9:0] spc2_stb_ced_cntr3;
reg spc2_stb_ced3_d;
reg spc2_stb_ced_capture3;
wire spc2_stb_ced3;
reg spc2_atm3_d;
reg [9:0] spc2_atm_cntr3;
reg spc2_atm_intrpt_capture3;
reg spc2_atm_intrpt_b4capture3;
reg spc2_atm_inv_capture3;
reg [39:0] spc2_stb_wr_addr3;
reg [39:0] spc2_stb_atm_addr3;
reg spc2_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc2_fpick = {spc2_mpick,spc2_spick,spc2_lpick,spc2_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc2_msquash,spc2_apick,spc2_fpick})
9'b000000000 : spc2_fpicko = 1'b0;
9'b0xxx1xxx1 : spc2_fpicko = 1'b0;
9'b1xxxxxxxx : spc2_fpicko = 1'b0;
9'b0xxx0xxx0 : spc2_fpicko = 1'b0;
default:
begin
spc2_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon2 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc2_exu_und = {spc2_l2,
spc2_unc,
spc2_fpld,
spc2_fpldst,
spc2_unflush,
spc2_ldw,
spc2_byp,
spc2_flsh,
spc2_chm,
spc2_ldxa,
spc2_ato,
spc2_pref,
spc2_chit,
spc2_dcp,
spc2_dtp,
spc2_mpc,
spc2_mpu};
always @(spc2_exu_und)
begin
case (spc2_exu_und)
17'h00000 : spc2_exu = 5'h00;
17'h00001 : spc2_exu = 5'h01;
17'h00002 : spc2_exu = 5'h02;
17'h00004 : spc2_exu = 5'h03;
17'h00008 : spc2_exu = 5'h04;
17'h00010 : spc2_exu = 5'h05;
17'h00020 : spc2_exu = 5'h06;
17'h00040 : spc2_exu = 5'h07;
17'h00080 : spc2_exu = 5'h08;
17'h00100 : spc2_exu = 5'h09;
17'h00200 : spc2_exu = 5'h0a;
17'h00400 : spc2_exu = 5'h0b;
17'h00800 : spc2_exu = 5'h0c;
17'h01000 : spc2_exu = 5'h0d;
17'h02000 : spc2_exu = 5'h0e;
17'h04000 : spc2_exu = 5'h0f;
17'h08000 : spc2_exu = 5'h10;
17'h10000 : spc2_exu = 5'h11;
default: spc2_exu = 5'h12;
endcase
end
//excp
assign spc2_exp_und = {spc2_exp_wtchpt_trp_g,
spc2_exp_misalign_addr_ldst_atm_m,
spc2_exp_priv_violtn_g,
spc2_exp_daccess_excptn_g,
spc2_exp_daccess_prot_g,
spc2_exp_priv_action_g,
spc2_exp_spec_access_epage_g,
spc2_exp_uncache_atomic_g,
spc2_exp_illegal_asi_action_g,
spc2_exp_flt_ld_nfo_pg_g,
spc2_exp_asi_rd_unc,
spc2_exp_tlb_data_ce,
spc2_exp_tlb_data_ue,
spc2_exp_tlb_tag_ue,
spc2_exp_unc,
spc2_exp_corr};
always @(spc2_exp_und)
begin
case (spc2_exp_und)
16'h0000 : spc2_exp = 5'h00;
16'h0001 : spc2_exp = 5'h01;
16'h0002 : spc2_exp = 5'h02;
16'h0004 : spc2_exp = 5'h03;
16'h0008 : spc2_exp = 5'h04;
16'h0010 : spc2_exp = 5'h05;
16'h0020 : spc2_exp = 5'h06;
16'h0040 : spc2_exp = 5'h07;
16'h0080 : spc2_exp = 5'h08;
16'h0100 : spc2_exp = 5'h09;
16'h0200 : spc2_exp = 5'h0a;
16'h0400 : spc2_exp = 5'h0b;
16'h0800 : spc2_exp = 5'h0c;
16'h1000 : spc2_exp = 5'h0d;
16'h2000 : spc2_exp = 5'h0e;
16'h4000 : spc2_exp = 5'h0f;
16'h8000 : spc2_exp = 5'h10;
default: spc2_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc2_dctl_stxa_cmplt0 = ((spc2_dctl_stxa_internal_d2 & spc2_dctl_thread0_w3) |
spc2_dctl_stxa_stall_wr_cmplt0_d1);
assign spc2_dctl_l2fill_cmplt0 = (((spc2_dctl_lsu_l2fill_vld & ~spc2_dctl_atomic_ld_squash_e &
~spc2_dctl_lsu_ignore_fill)) & ~spc2_dctl_l2fill_fpld_e &
~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread0);
assign spc2_dctl_fillerr0 = spc2_dctl_l2_corr_error_e & spc2_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc2_dctl_atm_cmplt0 = (spc2_dctl_lsu_atm_st_cmplt_e & ~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread0);
assign spc2_dctl_ldst_cond_cmplt0 = { spc2_dctl_stxa_cmplt0, spc2_dctl_l2fill_cmplt0,
spc2_dctl_atomic_ld_squash_e, spc2_dctl_intld_byp_cmplt[0],
spc2_dctl_bsync0_reset, spc2_dctl_lsu_intrpt_cmplt[0]
};
assign spc2_cmplt0 = { spc2_dctl_ldxa_illgl_va_cmplt_d1, spc2_dctl_pref_tlbmiss_cmplt_d2,
spc2_dctl_lsu_pcx_pref_issue, spc2_dctl_diag_wr_cmplt0, spc2_dctl_l2fill_fpld_e};
always @(spc2_cmplt0 or spc2_dctl_ldst_cond_cmplt0)
begin
case ({spc2_dctl_fillerr0,spc2_dctl_ldst_cond_cmplt0,spc2_cmplt0})
12'h000 : spc2_ldstcond_cmplt0 = 4'h0;
12'h001 : spc2_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc2_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc2_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc2_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc2_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc2_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc2_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc2_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc2_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc2_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc2_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc2_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc2_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc2_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc2_dctl_stxa_cmplt1 = ((spc2_dctl_stxa_internal_d2 & spc2_dctl_thread1_w3) |
spc2_dctl_stxa_stall_wr_cmplt1_d1);
assign spc2_dctl_l2fill_cmplt1 = (((spc2_dctl_lsu_l2fill_vld & ~spc2_dctl_atomic_ld_squash_e &
~spc2_dctl_lsu_ignore_fill)) & ~spc2_dctl_l2fill_fpld_e &
~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread1);
assign spc2_dctl_fillerr1 = spc2_dctl_l2_corr_error_e & spc2_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc2_dctl_atm_cmplt1 = (spc2_dctl_lsu_atm_st_cmplt_e & ~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread1);
assign spc2_dctl_ldst_cond_cmplt1 = { spc2_dctl_stxa_cmplt1, spc2_dctl_l2fill_cmplt1,
spc2_dctl_atomic_ld_squash_e, spc2_dctl_intld_byp_cmplt[1],
spc2_dctl_bsync1_reset, spc2_dctl_lsu_intrpt_cmplt[1]
};
assign spc2_cmplt1 = { spc2_dctl_ldxa_illgl_va_cmplt_d1, spc2_dctl_pref_tlbmiss_cmplt_d2,
spc2_dctl_lsu_pcx_pref_issue, spc2_dctl_diag_wr_cmplt1, spc2_dctl_l2fill_fpld_e};
always @(spc2_cmplt1 or spc2_dctl_ldst_cond_cmplt1)
begin
case ({spc2_dctl_fillerr1,spc2_dctl_ldst_cond_cmplt1,spc2_cmplt1})
12'h000 : spc2_ldstcond_cmplt1 = 4'h0;
12'h001 : spc2_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc2_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc2_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc2_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc2_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc2_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc2_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc2_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc2_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc2_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc2_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc2_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc2_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc2_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc2_dctl_stxa_cmplt2 = ((spc2_dctl_stxa_internal_d2 & spc2_dctl_thread2_w3) |
spc2_dctl_stxa_stall_wr_cmplt2_d1);
assign spc2_dctl_l2fill_cmplt2 = (((spc2_dctl_lsu_l2fill_vld & ~spc2_dctl_atomic_ld_squash_e &
~spc2_dctl_lsu_ignore_fill)) & ~spc2_dctl_l2fill_fpld_e &
~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread2);
assign spc2_dctl_fillerr2 = spc2_dctl_l2_corr_error_e & spc2_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc2_dctl_atm_cmplt2 = (spc2_dctl_lsu_atm_st_cmplt_e & ~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread2);
assign spc2_dctl_ldst_cond_cmplt2 = { spc2_dctl_stxa_cmplt2, spc2_dctl_l2fill_cmplt2,
spc2_dctl_atomic_ld_squash_e, spc2_dctl_intld_byp_cmplt[2],
spc2_dctl_bsync2_reset, spc2_dctl_lsu_intrpt_cmplt[2]
};
assign spc2_cmplt2 = { spc2_dctl_ldxa_illgl_va_cmplt_d1, spc2_dctl_pref_tlbmiss_cmplt_d2,
spc2_dctl_lsu_pcx_pref_issue, spc2_dctl_diag_wr_cmplt2, spc2_dctl_l2fill_fpld_e};
always @(spc2_cmplt2 or spc2_dctl_ldst_cond_cmplt2)
begin
case ({spc2_dctl_fillerr2,spc2_dctl_ldst_cond_cmplt2,spc2_cmplt2})
12'h000 : spc2_ldstcond_cmplt2 = 4'h0;
12'h001 : spc2_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc2_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc2_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc2_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc2_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc2_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc2_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc2_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc2_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc2_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc2_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc2_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc2_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc2_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc2_dctl_stxa_cmplt3 = ((spc2_dctl_stxa_internal_d2 & spc2_dctl_thread3_w3) |
spc2_dctl_stxa_stall_wr_cmplt3_d1);
assign spc2_dctl_l2fill_cmplt3 = (((spc2_dctl_lsu_l2fill_vld & ~spc2_dctl_atomic_ld_squash_e &
~spc2_dctl_lsu_ignore_fill)) & ~spc2_dctl_l2fill_fpld_e &
~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread3);
assign spc2_dctl_fillerr3 = spc2_dctl_l2_corr_error_e & spc2_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc2_dctl_atm_cmplt3 = (spc2_dctl_lsu_atm_st_cmplt_e & ~spc2_dctl_fill_err_trap_e & spc2_dctl_dfill_thread3);
assign spc2_dctl_ldst_cond_cmplt3 = { spc2_dctl_stxa_cmplt3, spc2_dctl_l2fill_cmplt3,
spc2_dctl_atomic_ld_squash_e, spc2_dctl_intld_byp_cmplt[3],
spc2_dctl_bsync3_reset, spc2_dctl_lsu_intrpt_cmplt[3]
};
assign spc2_cmplt3 = { spc2_dctl_ldxa_illgl_va_cmplt_d1, spc2_dctl_pref_tlbmiss_cmplt_d2,
spc2_dctl_lsu_pcx_pref_issue, spc2_dctl_diag_wr_cmplt3, spc2_dctl_l2fill_fpld_e};
always @(spc2_cmplt3 or spc2_dctl_ldst_cond_cmplt3)
begin
case ({spc2_dctl_fillerr3,spc2_dctl_ldst_cond_cmplt3,spc2_cmplt3})
12'h000 : spc2_ldstcond_cmplt3 = 4'h0;
12'h001 : spc2_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc2_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc2_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc2_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc2_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc2_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc2_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc2_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc2_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc2_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc2_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc2_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc2_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc2_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc2_ldstcond_cmplt0 or spc2_ldstcond_cmplt1 or spc2_ldstcond_cmplt2
or spc2_ldstcond_cmplt3 or spc2_dctl_lsu_ifu_ldst_cmplt
or spc2_dctl_late_cmplt0 or spc2_dctl_late_cmplt1 or spc2_dctl_late_cmplt2 or spc2_dctl_late_cmplt3)
begin
case (spc2_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc2_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc2_ldstcond_cmplt_d = spc2_dctl_late_cmplt0 ? spc2_ldstcond_cmplt0_d : spc2_ldstcond_cmplt0;
4'b0010 : spc2_ldstcond_cmplt_d = spc2_dctl_late_cmplt1 ? spc2_ldstcond_cmplt1_d : spc2_ldstcond_cmplt1;
4'b0100 : spc2_ldstcond_cmplt_d = spc2_dctl_late_cmplt2 ? spc2_ldstcond_cmplt2_d : spc2_ldstcond_cmplt2;
4'b1000 : spc2_ldstcond_cmplt_d = spc2_dctl_late_cmplt3 ? spc2_ldstcond_cmplt3_d : spc2_ldstcond_cmplt3;
4'b0011 : spc2_ldstcond_cmplt_d = 4'he;
4'b0101 : spc2_ldstcond_cmplt_d = 4'he;
4'b1001 : spc2_ldstcond_cmplt_d = 4'he;
4'b0110 : spc2_ldstcond_cmplt_d = 4'he;
4'b1010 : spc2_ldstcond_cmplt_d = 4'he;
4'b1100 : spc2_ldstcond_cmplt_d = 4'he;
default:
begin
spc2_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc2_st_ooo_ret = { spc2_st0_lt_1, spc2_st0_lt_2, spc2_st0_lt_3,
spc2_st1_lt_0, spc2_st1_lt_2, spc2_st1_lt_3,
spc2_st2_lt_0, spc2_st2_lt_1, spc2_st2_lt_3,
spc2_st3_lt_0, spc2_st3_lt_1, spc2_st3_lt_2};
always @(posedge clk)
begin
if(~spc2_st0_unfilled || ~rst_l)
spc2_st0_unfilled_d <= 1'b0;
else
spc2_st0_unfilled_d <= spc2_st0_unfilled;
if(~rst_l)
spc2_ldstcond_cmplt0_d <= 4'h0;
else
spc2_ldstcond_cmplt0_d <= spc2_ldstcond_cmplt0;
if(~spc2_ld0_pkt_vld_unmasked || ~rst_l)
spc2_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc2_ld0_pkt_vld_unmasked_d <= spc2_ld0_pkt_vld_unmasked;
if(~rst_l)
spc2_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc2_qctl1_ld_sec_hit_thrd0 && spc2_qctl1_ld0_inst_vld_g)
spc2_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc2_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc2_st1_unfilled || ~rst_l)
spc2_st1_unfilled_d <= 1'b0;
else
spc2_st1_unfilled_d <= spc2_st1_unfilled;
if(~rst_l)
spc2_ldstcond_cmplt1_d <= 4'h0;
else
spc2_ldstcond_cmplt1_d <= spc2_ldstcond_cmplt1;
if(~spc2_ld1_pkt_vld_unmasked || ~rst_l)
spc2_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc2_ld1_pkt_vld_unmasked_d <= spc2_ld1_pkt_vld_unmasked;
if(~rst_l)
spc2_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc2_qctl1_ld_sec_hit_thrd1 && spc2_qctl1_ld1_inst_vld_g)
spc2_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc2_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc2_st2_unfilled || ~rst_l)
spc2_st2_unfilled_d <= 1'b0;
else
spc2_st2_unfilled_d <= spc2_st2_unfilled;
if(~rst_l)
spc2_ldstcond_cmplt2_d <= 4'h0;
else
spc2_ldstcond_cmplt2_d <= spc2_ldstcond_cmplt2;
if(~spc2_ld2_pkt_vld_unmasked || ~rst_l)
spc2_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc2_ld2_pkt_vld_unmasked_d <= spc2_ld2_pkt_vld_unmasked;
if(~rst_l)
spc2_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc2_qctl1_ld_sec_hit_thrd2 && spc2_qctl1_ld2_inst_vld_g)
spc2_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc2_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc2_st3_unfilled || ~rst_l)
spc2_st3_unfilled_d <= 1'b0;
else
spc2_st3_unfilled_d <= spc2_st3_unfilled;
if(~rst_l)
spc2_ldstcond_cmplt3_d <= 4'h0;
else
spc2_ldstcond_cmplt3_d <= spc2_ldstcond_cmplt3;
if(~spc2_ld3_pkt_vld_unmasked || ~rst_l)
spc2_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc2_ld3_pkt_vld_unmasked_d <= spc2_ld3_pkt_vld_unmasked;
if(~rst_l)
spc2_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc2_qctl1_ld_sec_hit_thrd3 && spc2_qctl1_ld3_inst_vld_g)
spc2_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc2_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc2_stb_state_ced0) && (|spc2_stb_state_rst0)) || ~rst_l)
spc2_st0_unfilled <= 1'b0;
else if( ((|spc2_stb_state_ced0) && ~(|spc2_stb_state_rst0)))
spc2_st0_unfilled <= 1'b1;
else
spc2_st0_unfilled <= spc2_st0_unfilled;
if( ((|spc2_stb_state_ced1) && (|spc2_stb_state_rst1)) || ~rst_l)
spc2_st1_unfilled <= 1'b0;
else if( ((|spc2_stb_state_ced1) && ~(|spc2_stb_state_rst1)))
spc2_st1_unfilled <= 1'b1;
else
spc2_st1_unfilled <= spc2_st1_unfilled;
if( ((|spc2_stb_state_ced2) && (|spc2_stb_state_rst2)) || ~rst_l)
spc2_st2_unfilled <= 1'b0;
else if( ((|spc2_stb_state_ced2) && ~(|spc2_stb_state_rst2)))
spc2_st2_unfilled <= 1'b1;
else
spc2_st2_unfilled <= spc2_st2_unfilled;
if( ((|spc2_stb_state_ced3) && (|spc2_stb_state_rst3)) || ~rst_l)
spc2_st3_unfilled <= 1'b0;
else if( ((|spc2_stb_state_ced3) && ~(|spc2_stb_state_rst3)))
spc2_st3_unfilled <= 1'b1;
else
spc2_st3_unfilled <= spc2_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc2_st0_unfilled && spc2_st0_unfilled_d)|| ~rst_l)
begin
spc2_st0_unf_cntr <= 9'h000;
end
else if(spc2_st0_unfilled)
begin
spc2_st0_unf_cntr <= spc2_st0_unf_cntr + 1;
end
else
begin
spc2_st0_unf_cntr <= spc2_st0_unf_cntr;
end
if((~spc2_st1_unfilled && spc2_st1_unfilled_d)|| ~rst_l)
begin
spc2_st1_unf_cntr <= 9'h000;
end
else if(spc2_st1_unfilled)
begin
spc2_st1_unf_cntr <= spc2_st1_unf_cntr + 1;
end
else
begin
spc2_st1_unf_cntr <= spc2_st1_unf_cntr;
end
if((~spc2_st2_unfilled && spc2_st2_unfilled_d)|| ~rst_l)
begin
spc2_st2_unf_cntr <= 9'h000;
end
else if(spc2_st2_unfilled)
begin
spc2_st2_unf_cntr <= spc2_st2_unf_cntr + 1;
end
else
begin
spc2_st2_unf_cntr <= spc2_st2_unf_cntr;
end
if((~spc2_st3_unfilled && spc2_st3_unfilled_d)|| ~rst_l)
begin
spc2_st3_unf_cntr <= 9'h000;
end
else if(spc2_st3_unfilled)
begin
spc2_st3_unf_cntr <= spc2_st3_unf_cntr + 1;
end
else
begin
spc2_st3_unf_cntr <= spc2_st3_unf_cntr;
end
end
always @(spc2_st0_unfilled or spc2_st1_unfilled or spc2_st2_unfilled or spc2_st3_unfilled
or spc2_st0_unfilled_d or spc2_st1_unfilled_d or spc2_st2_unfilled_d or spc2_st3_unfilled_d)
begin
if(~spc2_st0_unfilled && spc2_st0_unfilled_d && spc2_st1_unfilled)
spc2_st0_lt_1 <= (spc2_st1_unf_cntr > spc2_st0_unf_cntr);
else
spc2_st0_lt_1 <= 1'b0;
if(~spc2_st0_unfilled && spc2_st0_unfilled_d && spc2_st2_unfilled)
spc2_st0_lt_2 <= (spc2_st2_unf_cntr > spc2_st0_unf_cntr);
else
spc2_st0_lt_2 <= 1'b0;
if(~spc2_st0_unfilled && spc2_st0_unfilled_d && spc2_st3_unfilled)
spc2_st0_lt_3 <= (spc2_st3_unf_cntr > spc2_st0_unf_cntr);
else
spc2_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc2_st1_unfilled && spc2_st1_unfilled_d && spc2_st0_unfilled)
spc2_st1_lt_0 <= (spc2_st0_unf_cntr > spc2_st1_unf_cntr);
else
spc2_st1_lt_0 <= 1'b0;
if(~spc2_st1_unfilled && spc2_st1_unfilled_d && spc2_st2_unfilled)
spc2_st1_lt_2 <= (spc2_st2_unf_cntr > spc2_st1_unf_cntr);
else
spc2_st1_lt_2 <= 1'b0;
if(~spc2_st1_unfilled && spc2_st1_unfilled_d && spc2_st3_unfilled)
spc2_st1_lt_3 <= (spc2_st3_unf_cntr > spc2_st1_unf_cntr);
else
spc2_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc2_st2_unfilled && spc2_st2_unfilled_d && spc2_st0_unfilled)
spc2_st2_lt_0 <= (spc2_st0_unf_cntr > spc2_st2_unf_cntr);
else
spc2_st2_lt_0 <= 1'b0;
if(~spc2_st2_unfilled && spc2_st2_unfilled_d && spc2_st1_unfilled)
spc2_st2_lt_1 <= (spc2_st1_unf_cntr > spc2_st2_unf_cntr);
else
spc2_st2_lt_1 <= 1'b0;
if(~spc2_st2_unfilled && spc2_st2_unfilled_d && spc2_st3_unfilled)
spc2_st2_lt_3 <= (spc2_st3_unf_cntr > spc2_st2_unf_cntr);
else
spc2_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc2_st3_unfilled && spc2_st3_unfilled_d && spc2_st0_unfilled)
spc2_st3_lt_0 <= (spc2_st0_unf_cntr > spc2_st3_unf_cntr);
else
spc2_st3_lt_0 <= 1'b0;
if(~spc2_st3_unfilled && spc2_st3_unfilled_d && spc2_st1_unfilled)
spc2_st3_lt_1 <= (spc2_st1_unf_cntr > spc2_st3_unf_cntr);
else
spc2_st3_lt_1 <= 1'b0;
if(~spc2_st3_unfilled && spc2_st3_unfilled_d && spc2_st2_unfilled)
spc2_st3_lt_2 <= (spc2_st2_unf_cntr > spc2_st3_unf_cntr);
else
spc2_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc2_ld_ooo_ret = { spc2_ld0_lt_1, spc2_ld0_lt_2, spc2_ld0_lt_3,
spc2_ld1_lt_0, spc2_ld1_lt_2, spc2_ld1_lt_3,
spc2_ld2_lt_0, spc2_ld2_lt_1, spc2_ld2_lt_3,
spc2_ld3_lt_0, spc2_ld3_lt_1, spc2_ld3_lt_2};
always @(posedge clk)
begin
if((~spc2_ld0_unfilled && spc2_ld0_unfilled_d)|| ~rst_l)
begin
spc2_ld0_unf_cntr <= 9'h000;
end
else if(spc2_ld0_unfilled)
begin
spc2_ld0_unf_cntr <= spc2_ld0_unf_cntr + 1;
end
else
begin
spc2_ld0_unf_cntr <= spc2_ld0_unf_cntr;
end
if((~spc2_ld1_unfilled && spc2_ld1_unfilled_d)|| ~rst_l)
begin
spc2_ld1_unf_cntr <= 9'h000;
end
else if(spc2_ld1_unfilled)
begin
spc2_ld1_unf_cntr <= spc2_ld1_unf_cntr + 1;
end
else
begin
spc2_ld1_unf_cntr <= spc2_ld1_unf_cntr;
end
if((~spc2_ld2_unfilled && spc2_ld2_unfilled_d)|| ~rst_l)
begin
spc2_ld2_unf_cntr <= 9'h000;
end
else if(spc2_ld2_unfilled)
begin
spc2_ld2_unf_cntr <= spc2_ld2_unf_cntr + 1;
end
else
begin
spc2_ld2_unf_cntr <= spc2_ld2_unf_cntr;
end
if((~spc2_ld3_unfilled && spc2_ld3_unfilled_d)|| ~rst_l)
begin
spc2_ld3_unf_cntr <= 9'h000;
end
else if(spc2_ld3_unfilled)
begin
spc2_ld3_unf_cntr <= spc2_ld3_unf_cntr + 1;
end
else
begin
spc2_ld3_unf_cntr <= spc2_ld3_unf_cntr;
end
end
always @(spc2_ld0_unfilled or spc2_ld1_unfilled or spc2_ld2_unfilled or spc2_ld3_unfilled
or spc2_ld0_unfilled_d or spc2_ld1_unfilled_d or spc2_ld2_unfilled_d or spc2_ld3_unfilled_d)
begin
if(~spc2_ld0_unfilled && spc2_ld0_unfilled_d && spc2_ld1_unfilled)
spc2_ld0_lt_1 <= (spc2_ld1_unf_cntr > spc2_ld0_unf_cntr);
else
spc2_ld0_lt_1 <= 1'b0;
if(~spc2_ld0_unfilled && spc2_ld0_unfilled_d && spc2_ld2_unfilled)
spc2_ld0_lt_2 <= (spc2_ld2_unf_cntr > spc2_ld0_unf_cntr);
else
spc2_ld0_lt_2 <= 1'b0;
if(~spc2_ld0_unfilled && spc2_ld0_unfilled_d && spc2_ld3_unfilled)
spc2_ld0_lt_3 <= (spc2_ld3_unf_cntr > spc2_ld0_unf_cntr);
else
spc2_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc2_ld1_unfilled && spc2_ld1_unfilled_d && spc2_ld0_unfilled)
spc2_ld1_lt_0 <= (spc2_ld0_unf_cntr > spc2_ld1_unf_cntr);
else
spc2_ld1_lt_0 <= 1'b0;
if(~spc2_ld1_unfilled && spc2_ld1_unfilled_d && spc2_ld2_unfilled)
spc2_ld1_lt_2 <= (spc2_ld2_unf_cntr > spc2_ld1_unf_cntr);
else
spc2_ld1_lt_2 <= 1'b0;
if(~spc2_ld1_unfilled && spc2_ld1_unfilled_d && spc2_ld3_unfilled)
spc2_ld1_lt_3 <= (spc2_ld3_unf_cntr > spc2_ld1_unf_cntr);
else
spc2_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc2_ld2_unfilled && spc2_ld2_unfilled_d && spc2_ld0_unfilled)
spc2_ld2_lt_0 <= (spc2_ld0_unf_cntr > spc2_ld2_unf_cntr);
else
spc2_ld2_lt_0 <= 1'b0;
if(~spc2_ld2_unfilled && spc2_ld2_unfilled_d && spc2_ld1_unfilled)
spc2_ld2_lt_1 <= (spc2_ld1_unf_cntr > spc2_ld2_unf_cntr);
else
spc2_ld2_lt_1 <= 1'b0;
if(~spc2_ld2_unfilled && spc2_ld2_unfilled_d && spc2_ld3_unfilled)
spc2_ld2_lt_3 <= (spc2_ld3_unf_cntr > spc2_ld2_unf_cntr);
else
spc2_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc2_ld3_unfilled && spc2_ld3_unfilled_d && spc2_ld0_unfilled)
spc2_ld3_lt_0 <= (spc2_ld0_unf_cntr > spc2_ld3_unf_cntr);
else
spc2_ld3_lt_0 <= 1'b0;
if(~spc2_ld3_unfilled && spc2_ld3_unfilled_d && spc2_ld1_unfilled)
spc2_ld3_lt_1 <= (spc2_ld1_unf_cntr > spc2_ld3_unf_cntr);
else
spc2_ld3_lt_1 <= 1'b0;
if(~spc2_ld3_unfilled && spc2_ld3_unfilled_d && spc2_ld2_unfilled)
spc2_ld3_lt_2 <= (spc2_ld2_unf_cntr > spc2_ld3_unf_cntr);
else
spc2_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc2_dctl_bld_hit =
((|spc2_dctl_lsu_way_hit[3:0]) & spc2_dctl_dcache_enable_g &
~spc2_dctl_ldxa_internal & ~spc2_dctl_dcache_rd_parity_error & ~spc2_dctl_dtag_perror_g &
~spc2_dctl_endian_mispred_g &
~spc2_dctl_atomic_g & ~spc2_dctl_ncache_asild_rq_g) & ~spc2_dctl_tte_data_perror_unc &
spc2_dctl_ld_inst_vld_g & spc2_qctl1_bld_g ;
assign spc2_dctl_bld_stb_hit = spc2_dctl_bld_hit & spc2_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc2_bld0_full_d <= 2'b00;
spc2_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc2_bld0_full_d <= spc2_qctl1_bld_cnt;
spc2_ld0_unfilled_d <= spc2_ld0_unfilled;
end
if(~rst_l)
begin
spc2_bld1_full_d <= 2'b00;
spc2_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc2_bld1_full_d <= spc2_qctl1_bld_cnt;
spc2_ld1_unfilled_d <= spc2_ld1_unfilled;
end
if(~rst_l)
begin
spc2_bld2_full_d <= 2'b00;
spc2_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc2_bld2_full_d <= spc2_qctl1_bld_cnt;
spc2_ld2_unfilled_d <= spc2_ld2_unfilled;
end
if(~rst_l)
begin
spc2_bld3_full_d <= 2'b00;
spc2_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc2_bld3_full_d <= spc2_qctl1_bld_cnt;
spc2_ld3_unfilled_d <= spc2_ld3_unfilled;
end
end
always @(spc2_bld0_full_d or spc2_qctl1_bld_cnt)
begin
if( (spc2_bld0_full_d != spc2_qctl1_bld_cnt) && (spc2_bld0_full_d == 2'd0))
spc2_bld0_full_capture <= 1'b1;
else
spc2_bld0_full_capture <= 1'b0;
end
always @(spc2_bld1_full_d or spc2_qctl1_bld_cnt)
begin
if( (spc2_bld1_full_d != spc2_qctl1_bld_cnt) && (spc2_bld1_full_d == 2'd1))
spc2_bld1_full_capture <= 1'b1;
else
spc2_bld1_full_capture <= 1'b0;
end
always @(spc2_bld2_full_d or spc2_qctl1_bld_cnt)
begin
if( (spc2_bld2_full_d != spc2_qctl1_bld_cnt) && (spc2_bld2_full_d == 2'd2))
spc2_bld2_full_capture <= 1'b1;
else
spc2_bld2_full_capture <= 1'b0;
end
always @(spc2_bld3_full_d or spc2_qctl1_bld_cnt)
begin
if( (spc2_bld3_full_d != spc2_qctl1_bld_cnt) && (spc2_bld3_full_d == 2'd3))
spc2_bld3_full_capture <= 1'b1;
else
spc2_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc2_qctl1_bld_cnt != 2'b00) && (spc2_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc2_bld0_full_cntr <= 9'h000;
end
else if(spc2_qctl1_bld_g && (spc2_qctl1_bld_cnt == 2'b00))
begin
spc2_bld0_full_cntr <= spc2_bld0_full_cntr + 1;
end
else if( (spc2_qctl1_bld_cnt == 2'b00) && (spc2_bld0_full_cntr != 9'h000))
begin
spc2_bld0_full_cntr <= spc2_bld0_full_cntr + 1;
end
else
begin
spc2_bld0_full_cntr <= spc2_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc2_qctl1_bld_cnt != 2'b01) && (spc2_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc2_bld1_full_cntr <= 9'h000;
end
else if(spc2_qctl1_bld_cnt == 2'b01)
begin
spc2_bld1_full_cntr <= spc2_bld1_full_cntr + 1;
end
else if( (spc2_qctl1_bld_cnt == 2'b01) && (spc2_bld1_full_cntr != 9'h000))
begin
spc2_bld1_full_cntr <= spc2_bld1_full_cntr + 1;
end
else
begin
spc2_bld1_full_cntr <= spc2_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc2_qctl1_bld_cnt != 2'b10) && (spc2_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc2_bld2_full_cntr <= 9'h000;
end
else if(spc2_qctl1_bld_cnt == 2'b10)
begin
spc2_bld2_full_cntr <= spc2_bld2_full_cntr + 1;
end
else if( (spc2_qctl1_bld_cnt == 2'b10) && (spc2_bld2_full_cntr != 9'h000))
begin
spc2_bld2_full_cntr <= spc2_bld2_full_cntr + 1;
end
else
begin
spc2_bld2_full_cntr <= spc2_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc2_qctl1_bld_cnt != 2'b11) && (spc2_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc2_bld3_full_cntr <= 9'h000;
end
else if(spc2_qctl1_bld_cnt == 2'b11)
begin
spc2_bld3_full_cntr <= spc2_bld3_full_cntr + 1;
end
else if( (spc2_qctl1_bld_cnt == 2'b11) && (spc2_bld3_full_cntr != 9'h000))
begin
spc2_bld3_full_cntr <= spc2_bld3_full_cntr + 1;
end
else
begin
spc2_bld3_full_cntr <= spc2_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc2_stb_state_vld0) && ~spc2_atomic_g) || ~rst_l)
begin
spc2_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc2_atomic_g && (spc2_atm_type0 != 8'h00) && spc2_wptr_vld)
begin
spc2_stb_atm_addr0 <= {spc2_wdata_ramc[44:9],spc2_wdata_ramd[67:64]};
end
else
begin
spc2_stb_atm_addr0 <= spc2_stb_atm_addr0;
end
if( ( ~(|spc2_stb_state_vld1) && ~spc2_atomic_g) || ~rst_l)
begin
spc2_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc2_atomic_g && (spc2_atm_type1 != 8'h00) && spc2_wptr_vld)
begin
spc2_stb_atm_addr1 <= {spc2_wdata_ramc[44:9],spc2_wdata_ramd[67:64]};
end
else
begin
spc2_stb_atm_addr1 <= spc2_stb_atm_addr1;
end
if( ( ~(|spc2_stb_state_vld2) && ~spc2_atomic_g) || ~rst_l)
begin
spc2_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc2_atomic_g && (spc2_atm_type2 != 8'h00) && spc2_wptr_vld)
begin
spc2_stb_atm_addr2 <= {spc2_wdata_ramc[44:9],spc2_wdata_ramd[67:64]};
end
else
begin
spc2_stb_atm_addr2 <= spc2_stb_atm_addr2;
end
if( ( ~(|spc2_stb_state_vld3) && ~spc2_atomic_g) || ~rst_l)
begin
spc2_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc2_atomic_g && (spc2_atm_type3 != 8'h00) && spc2_wptr_vld)
begin
spc2_stb_atm_addr3 <= {spc2_wdata_ramc[44:9],spc2_wdata_ramd[67:64]};
end
else
begin
spc2_stb_atm_addr3 <= spc2_stb_atm_addr3;
end
end
assign spc2_dfq_full = (spc2_dfq_vld_entries >= 3'd4);
assign spc2_dfq_full1 = (spc2_dfq_vld_entries >= (3'd4 + 1));
always @(spc2_dfq_full_d1 or spc2_dfq_full1)
begin
if (spc2_dfq_full_d1 && ~spc2_dfq_full1)
spc2_dfq_full_capture1 <= 1'b1;
else
spc2_dfq_full_capture1 <= 1'b0;
end
assign spc2_dfq_full2 = (spc2_dfq_vld_entries >= (3'd4 + 2));
always @(spc2_dfq_full_d2 or spc2_dfq_full2)
begin
if (spc2_dfq_full_d2 && ~spc2_dfq_full2)
spc2_dfq_full_capture2 <= 1'b1;
else
spc2_dfq_full_capture2 <= 1'b0;
end
assign spc2_dfq_full3 = (spc2_dfq_vld_entries >= (3'd4 + 3));
always @(spc2_dfq_full_d3 or spc2_dfq_full3)
begin
if (spc2_dfq_full_d3 && ~spc2_dfq_full3)
spc2_dfq_full_capture3 <= 1'b1;
else
spc2_dfq_full_capture3 <= 1'b0;
end
assign spc2_dfq_full4 = (spc2_dfq_vld_entries >= (3'd4 + 4));
always @(spc2_dfq_full_d4 or spc2_dfq_full4)
begin
if (spc2_dfq_full_d4 && ~spc2_dfq_full4)
spc2_dfq_full_capture4 <= 1'b1;
else
spc2_dfq_full_capture4 <= 1'b0;
end
assign spc2_dfq_full5 = (spc2_dfq_vld_entries >= (3'd4 + 5));
always @(spc2_dfq_full_d5 or spc2_dfq_full5)
begin
if (spc2_dfq_full_d5 && ~spc2_dfq_full5)
spc2_dfq_full_capture5 <= 1'b1;
else
spc2_dfq_full_capture5 <= 1'b0;
end
assign spc2_dfq_full6 = (spc2_dfq_vld_entries >= (3'd4 + 6));
always @(spc2_dfq_full_d6 or spc2_dfq_full6)
begin
if (spc2_dfq_full_d6 && ~spc2_dfq_full6)
spc2_dfq_full_capture6 <= 1'b1;
else
spc2_dfq_full_capture6 <= 1'b0;
end
assign spc2_dfq_full7 = (spc2_dfq_vld_entries >= (3'd4 + 7));
always @(spc2_dfq_full_d7 or spc2_dfq_full7)
begin
if (spc2_dfq_full_d7 && ~spc2_dfq_full7)
spc2_dfq_full_capture7 <= 1'b1;
else
spc2_dfq_full_capture7 <= 1'b0;
end
always @(spc2_mbar_vld_d0 or spc2_mbar_vld0)
begin
if (spc2_mbar_vld_d0 && ~spc2_mbar_vld0)
spc2_mbar_vld_capture0 <= 1'b1;
else
spc2_mbar_vld_capture0 <= 1'b0;
end
always @(spc2_mbar_vld_d1 or spc2_mbar_vld1)
begin
if (spc2_mbar_vld_d1 && ~spc2_mbar_vld1)
spc2_mbar_vld_capture1 <= 1'b1;
else
spc2_mbar_vld_capture1 <= 1'b0;
end
always @(spc2_mbar_vld_d2 or spc2_mbar_vld2)
begin
if (spc2_mbar_vld_d2 && ~spc2_mbar_vld2)
spc2_mbar_vld_capture2 <= 1'b1;
else
spc2_mbar_vld_capture2 <= 1'b0;
end
always @(spc2_mbar_vld_d3 or spc2_mbar_vld3)
begin
if (spc2_mbar_vld_d3 && ~spc2_mbar_vld3)
spc2_mbar_vld_capture3 <= 1'b1;
else
spc2_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc2_dfq_full1 && (spc2_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr1 <= 9'h000;
spc2_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr1);
end
else if( spc2_dfq_full1)
begin
spc2_dfq_full_cntr1 <= spc2_dfq_full_cntr1 + 1;
spc2_dfq_full_d1 <= spc2_dfq_full1;
end
else
begin
spc2_dfq_full_cntr1 <= spc2_dfq_full_cntr1;
spc2_dfq_full_d1 <= spc2_dfq_full1;
end
if( ( ~spc2_dfq_full2 && (spc2_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr2 <= 9'h000;
spc2_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr2);
end
else if( spc2_dfq_full2)
begin
spc2_dfq_full_cntr2 <= spc2_dfq_full_cntr2 + 1;
spc2_dfq_full_d2 <= spc2_dfq_full2;
end
else
begin
spc2_dfq_full_cntr2 <= spc2_dfq_full_cntr2;
spc2_dfq_full_d2 <= spc2_dfq_full2;
end
if( ( ~spc2_dfq_full3 && (spc2_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr3 <= 9'h000;
spc2_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr3);
end
else if( spc2_dfq_full3)
begin
spc2_dfq_full_cntr3 <= spc2_dfq_full_cntr3 + 1;
spc2_dfq_full_d3 <= spc2_dfq_full3;
end
else
begin
spc2_dfq_full_cntr3 <= spc2_dfq_full_cntr3;
spc2_dfq_full_d3 <= spc2_dfq_full3;
end
if( ( ~spc2_dfq_full4 && (spc2_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr4 <= 9'h000;
spc2_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr4);
end
else if( spc2_dfq_full4)
begin
spc2_dfq_full_cntr4 <= spc2_dfq_full_cntr4 + 1;
spc2_dfq_full_d4 <= spc2_dfq_full4;
end
else
begin
spc2_dfq_full_cntr4 <= spc2_dfq_full_cntr4;
spc2_dfq_full_d4 <= spc2_dfq_full4;
end
if( ( ~spc2_dfq_full5 && (spc2_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr5 <= 9'h000;
spc2_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr5);
end
else if( spc2_dfq_full5)
begin
spc2_dfq_full_cntr5 <= spc2_dfq_full_cntr5 + 1;
spc2_dfq_full_d5 <= spc2_dfq_full5;
end
else
begin
spc2_dfq_full_cntr5 <= spc2_dfq_full_cntr5;
spc2_dfq_full_d5 <= spc2_dfq_full5;
end
if( ( ~spc2_dfq_full6 && (spc2_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr6 <= 9'h000;
spc2_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr6);
end
else if( spc2_dfq_full6)
begin
spc2_dfq_full_cntr6 <= spc2_dfq_full_cntr6 + 1;
spc2_dfq_full_d6 <= spc2_dfq_full6;
end
else
begin
spc2_dfq_full_cntr6 <= spc2_dfq_full_cntr6;
spc2_dfq_full_d6 <= spc2_dfq_full6;
end
if( ( ~spc2_dfq_full7 && (spc2_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr7 <= 9'h000;
spc2_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr7);
end
else if( spc2_dfq_full7)
begin
spc2_dfq_full_cntr7 <= spc2_dfq_full_cntr7 + 1;
spc2_dfq_full_d7 <= spc2_dfq_full7;
end
else
begin
spc2_dfq_full_cntr7 <= spc2_dfq_full_cntr7;
spc2_dfq_full_d7 <= spc2_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc2_intrpt0_cmplt or spc2_atm_cntr0 or spc2_stb_state_ced0)
begin
if (spc2_intrpt0_cmplt && (spc2_atm_cntr0 != 9'h000) && ~(|spc2_stb_state_ced0))
spc2_atm_intrpt_b4capture0 <= 1'b1;
else
spc2_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc2_intrpt1_cmplt or spc2_atm_cntr1 or spc2_stb_state_ced1)
begin
if (spc2_intrpt1_cmplt && (spc2_atm_cntr1 != 9'h000) && ~(|spc2_stb_state_ced1))
spc2_atm_intrpt_b4capture1 <= 1'b1;
else
spc2_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc2_intrpt2_cmplt or spc2_atm_cntr2 or spc2_stb_state_ced2)
begin
if (spc2_intrpt2_cmplt && (spc2_atm_cntr2 != 9'h000) && ~(|spc2_stb_state_ced2))
spc2_atm_intrpt_b4capture2 <= 1'b1;
else
spc2_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc2_intrpt3_cmplt or spc2_atm_cntr3 or spc2_stb_state_ced3)
begin
if (spc2_intrpt3_cmplt && (spc2_atm_cntr3 != 9'h000) && ~(|spc2_stb_state_ced3))
spc2_atm_intrpt_b4capture3 <= 1'b1;
else
spc2_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc2_intrpt0_cmplt or spc2_atm_cntr0 or spc2_stb_state_ced0)
begin
if (spc2_intrpt0_cmplt && (spc2_atm_cntr0 != 9'h000) && (|spc2_stb_state_ced0))
spc2_atm_intrpt_capture0 <= 1'b1;
else
spc2_atm_intrpt_capture0 <= 1'b0;
end
always @(spc2_intrpt1_cmplt or spc2_atm_cntr1 or spc2_stb_state_ced1)
begin
if (spc2_intrpt1_cmplt && (spc2_atm_cntr1 != 9'h000) && (|spc2_stb_state_ced1))
spc2_atm_intrpt_capture1 <= 1'b1;
else
spc2_atm_intrpt_capture1 <= 1'b0;
end
always @(spc2_intrpt2_cmplt or spc2_atm_cntr2 or spc2_stb_state_ced2)
begin
if (spc2_intrpt2_cmplt && (spc2_atm_cntr2 != 9'h000) && (|spc2_stb_state_ced2))
spc2_atm_intrpt_capture2 <= 1'b1;
else
spc2_atm_intrpt_capture2 <= 1'b0;
end
always @(spc2_intrpt3_cmplt or spc2_atm_cntr3 or spc2_stb_state_ced3)
begin
if (spc2_intrpt3_cmplt && (spc2_atm_cntr3 != 9'h000) && (|spc2_stb_state_ced3))
spc2_atm_intrpt_capture3 <= 1'b1;
else
spc2_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc2_atm_cntr0 or spc2_dva_din or spc2_dva_wen)
begin
if (~spc2_dva_din && spc2_dva_wen && (spc2_atm_cntr0 != 9'h000))
spc2_atm_inv_capture0 <= 1'b1;
else
spc2_atm_inv_capture0 <= 1'b0;
end
always @(spc2_atm_cntr1 or spc2_dva_din or spc2_dva_wen)
begin
if (~spc2_dva_din && spc2_dva_wen && (spc2_atm_cntr1 != 9'h000))
spc2_atm_inv_capture1 <= 1'b1;
else
spc2_atm_inv_capture1 <= 1'b0;
end
always @(spc2_atm_cntr2 or spc2_dva_din or spc2_dva_wen)
begin
if (~spc2_dva_din && spc2_dva_wen && (spc2_atm_cntr2 != 9'h000))
spc2_atm_inv_capture2 <= 1'b1;
else
spc2_atm_inv_capture2 <= 1'b0;
end
always @(spc2_atm_cntr3 or spc2_dva_din or spc2_dva_wen)
begin
if (~spc2_dva_din && spc2_dva_wen && (spc2_atm_cntr3 != 9'h000))
spc2_atm_inv_capture3 <= 1'b1;
else
spc2_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc2_stb_state_vld0) && (spc2_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_atm_cntr0 <= 9'h000;
spc2_atm0_d <= 1'b0;
end
else if( spc2_atomic_g && (spc2_atm_type0 != 8'h00))
begin
spc2_atm_cntr0 <= spc2_atm_cntr0 + 1;
spc2_atm0_d <= 1'b1;
end
else if( spc2_atm0_d && (|spc2_stb_state_vld0))
begin
spc2_atm_cntr0 <= spc2_atm_cntr0 + 1;
spc2_atm0_d <= spc2_atm0_d;
end
else
begin
spc2_atm_cntr0 <= spc2_atm_cntr0;
spc2_atm0_d <= spc2_atm0_d;
end
if( ( ~(|spc2_stb_state_vld1) && (spc2_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_atm_cntr1 <= 9'h000;
spc2_atm1_d <= 1'b0;
end
else if( spc2_atomic_g && (spc2_atm_type1 != 8'h00))
begin
spc2_atm_cntr1 <= spc2_atm_cntr1 + 1;
spc2_atm1_d <= 1'b1;
end
else if( spc2_atm1_d && (|spc2_stb_state_vld1))
begin
spc2_atm_cntr1 <= spc2_atm_cntr1 + 1;
spc2_atm1_d <= spc2_atm1_d;
end
else
begin
spc2_atm_cntr1 <= spc2_atm_cntr1;
spc2_atm1_d <= spc2_atm1_d;
end
if( ( ~(|spc2_stb_state_vld2) && (spc2_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_atm_cntr2 <= 9'h000;
spc2_atm2_d <= 1'b0;
end
else if( spc2_atomic_g && (spc2_atm_type2 != 8'h00))
begin
spc2_atm_cntr2 <= spc2_atm_cntr2 + 1;
spc2_atm2_d <= 1'b1;
end
else if( spc2_atm2_d && (|spc2_stb_state_vld2))
begin
spc2_atm_cntr2 <= spc2_atm_cntr2 + 1;
spc2_atm2_d <= spc2_atm2_d;
end
else
begin
spc2_atm_cntr2 <= spc2_atm_cntr2;
spc2_atm2_d <= spc2_atm2_d;
end
if( ( ~(|spc2_stb_state_vld3) && (spc2_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_atm_cntr3 <= 9'h000;
spc2_atm3_d <= 1'b0;
end
else if( spc2_atomic_g && (spc2_atm_type3 != 8'h00))
begin
spc2_atm_cntr3 <= spc2_atm_cntr3 + 1;
spc2_atm3_d <= 1'b1;
end
else if( spc2_atm3_d && (|spc2_stb_state_vld3))
begin
spc2_atm_cntr3 <= spc2_atm_cntr3 + 1;
spc2_atm3_d <= spc2_atm3_d;
end
else
begin
spc2_atm_cntr3 <= spc2_atm_cntr3;
spc2_atm3_d <= spc2_atm3_d;
end
end
assign spc2_raw_ack_capture0 = spc2_stb_ack_vld0 && (spc2_stb_ack_cntr0 != 9'h000);
assign spc2_stb_ced0 = |spc2_stb_state_ced0;
assign spc2_raw_ack_capture1 = spc2_stb_ack_vld1 && (spc2_stb_ack_cntr1 != 9'h000);
assign spc2_stb_ced1 = |spc2_stb_state_ced1;
assign spc2_raw_ack_capture2 = spc2_stb_ack_vld2 && (spc2_stb_ack_cntr2 != 9'h000);
assign spc2_stb_ced2 = |spc2_stb_state_ced2;
assign spc2_raw_ack_capture3 = spc2_stb_ack_vld3 && (spc2_stb_ack_cntr3 != 9'h000);
assign spc2_stb_ced3 = |spc2_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc2_stb_ced0 && (spc2_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_stb_ced_cntr0 <= 9'h000;
spc2_stb_ced0_d <= 1'b0;
end
else if( spc2_stb_ced0 && (spc2_stb_state_ack0 == 8'h00))
begin
spc2_stb_ced_cntr0 <= spc2_stb_ced_cntr0 + 1;
spc2_stb_ced0_d <= spc2_stb_ced0;
end
else
begin
spc2_stb_ced_cntr0 <= spc2_stb_ced_cntr0;
spc2_stb_ced0_d <= spc2_stb_ced0_d;
end
if( ( ~spc2_mbar_vld0 && (spc2_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_mbar_vld_cntr0 <= 9'h000;
spc2_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_mbar_vld_counter = %d", spc2_mbar_vld_cntr0);
end
else if( spc2_mbar_vld0)
begin
spc2_mbar_vld_cntr0 <= spc2_mbar_vld_cntr0 + 1;
spc2_mbar_vld_d0 <= spc2_mbar_vld0;
end
else
begin
spc2_mbar_vld_cntr0 <= spc2_mbar_vld_cntr0;
spc2_mbar_vld_d0 <= spc2_mbar_vld0;
end
if( ( ~spc2_flsh_vld0 && (spc2_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_flsh_vld_cntr0 <= 9'h000;
spc2_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_flsh_vld_counter = %d", spc2_flsh_vld_cntr0);
end
else if( spc2_flsh_vld0)
begin
spc2_flsh_vld_cntr0 <= spc2_flsh_vld_cntr0 + 1;
spc2_flsh_vld_d0 <= spc2_flsh_vld0;
end
else
begin
spc2_flsh_vld_cntr0 <= spc2_flsh_vld_cntr0;
spc2_flsh_vld_d0 <= spc2_flsh_vld0;
end
if( ( ~spc2_stb_ced1 && (spc2_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_stb_ced_cntr1 <= 9'h000;
spc2_stb_ced1_d <= 1'b0;
end
else if( spc2_stb_ced1 && (spc2_stb_state_ack1 == 8'h00))
begin
spc2_stb_ced_cntr1 <= spc2_stb_ced_cntr1 + 1;
spc2_stb_ced1_d <= spc2_stb_ced1;
end
else
begin
spc2_stb_ced_cntr1 <= spc2_stb_ced_cntr1;
spc2_stb_ced1_d <= spc2_stb_ced1_d;
end
if( ( ~spc2_mbar_vld1 && (spc2_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_mbar_vld_cntr1 <= 9'h000;
spc2_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_mbar_vld_counter = %d", spc2_mbar_vld_cntr1);
end
else if( spc2_mbar_vld1)
begin
spc2_mbar_vld_cntr1 <= spc2_mbar_vld_cntr1 + 1;
spc2_mbar_vld_d1 <= spc2_mbar_vld1;
end
else
begin
spc2_mbar_vld_cntr1 <= spc2_mbar_vld_cntr1;
spc2_mbar_vld_d1 <= spc2_mbar_vld1;
end
if( ( ~spc2_flsh_vld1 && (spc2_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_flsh_vld_cntr1 <= 9'h000;
spc2_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_flsh_vld_counter = %d", spc2_flsh_vld_cntr1);
end
else if( spc2_flsh_vld1)
begin
spc2_flsh_vld_cntr1 <= spc2_flsh_vld_cntr1 + 1;
spc2_flsh_vld_d1 <= spc2_flsh_vld1;
end
else
begin
spc2_flsh_vld_cntr1 <= spc2_flsh_vld_cntr1;
spc2_flsh_vld_d1 <= spc2_flsh_vld1;
end
if( ( ~spc2_stb_ced2 && (spc2_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_stb_ced_cntr2 <= 9'h000;
spc2_stb_ced2_d <= 1'b0;
end
else if( spc2_stb_ced2 && (spc2_stb_state_ack2 == 8'h00))
begin
spc2_stb_ced_cntr2 <= spc2_stb_ced_cntr2 + 1;
spc2_stb_ced2_d <= spc2_stb_ced2;
end
else
begin
spc2_stb_ced_cntr2 <= spc2_stb_ced_cntr2;
spc2_stb_ced2_d <= spc2_stb_ced2_d;
end
if( ( ~spc2_mbar_vld2 && (spc2_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_mbar_vld_cntr2 <= 9'h000;
spc2_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_mbar_vld_counter = %d", spc2_mbar_vld_cntr2);
end
else if( spc2_mbar_vld2)
begin
spc2_mbar_vld_cntr2 <= spc2_mbar_vld_cntr2 + 1;
spc2_mbar_vld_d2 <= spc2_mbar_vld2;
end
else
begin
spc2_mbar_vld_cntr2 <= spc2_mbar_vld_cntr2;
spc2_mbar_vld_d2 <= spc2_mbar_vld2;
end
if( ( ~spc2_flsh_vld2 && (spc2_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_flsh_vld_cntr2 <= 9'h000;
spc2_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_flsh_vld_counter = %d", spc2_flsh_vld_cntr2);
end
else if( spc2_flsh_vld2)
begin
spc2_flsh_vld_cntr2 <= spc2_flsh_vld_cntr2 + 1;
spc2_flsh_vld_d2 <= spc2_flsh_vld2;
end
else
begin
spc2_flsh_vld_cntr2 <= spc2_flsh_vld_cntr2;
spc2_flsh_vld_d2 <= spc2_flsh_vld2;
end
if( ( ~spc2_stb_ced3 && (spc2_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_stb_ced_cntr3 <= 9'h000;
spc2_stb_ced3_d <= 1'b0;
end
else if( spc2_stb_ced3 && (spc2_stb_state_ack3 == 8'h00))
begin
spc2_stb_ced_cntr3 <= spc2_stb_ced_cntr3 + 1;
spc2_stb_ced3_d <= spc2_stb_ced3;
end
else
begin
spc2_stb_ced_cntr3 <= spc2_stb_ced_cntr3;
spc2_stb_ced3_d <= spc2_stb_ced3_d;
end
if( ( ~spc2_mbar_vld3 && (spc2_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_mbar_vld_cntr3 <= 9'h000;
spc2_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_mbar_vld_counter = %d", spc2_mbar_vld_cntr3);
end
else if( spc2_mbar_vld3)
begin
spc2_mbar_vld_cntr3 <= spc2_mbar_vld_cntr3 + 1;
spc2_mbar_vld_d3 <= spc2_mbar_vld3;
end
else
begin
spc2_mbar_vld_cntr3 <= spc2_mbar_vld_cntr3;
spc2_mbar_vld_d3 <= spc2_mbar_vld3;
end
if( ( ~spc2_flsh_vld3 && (spc2_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_flsh_vld_cntr3 <= 9'h000;
spc2_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_flsh_vld_counter = %d", spc2_flsh_vld_cntr3);
end
else if( spc2_flsh_vld3)
begin
spc2_flsh_vld_cntr3 <= spc2_flsh_vld_cntr3 + 1;
spc2_flsh_vld_d3 <= spc2_flsh_vld3;
end
else
begin
spc2_flsh_vld_cntr3 <= spc2_flsh_vld_cntr3;
spc2_flsh_vld_d3 <= spc2_flsh_vld3;
end
end
always @(spc2_flsh_vld_d0 or spc2_flsh_vld0)
begin
if (spc2_flsh_vld_d0 && ~spc2_flsh_vld0)
spc2_flsh_vld_capture0 <= 1'b1;
else
spc2_flsh_vld_capture0 <= 1'b0;
end
always @(spc2_flsh_vld_d1 or spc2_flsh_vld1)
begin
if (spc2_flsh_vld_d1 && ~spc2_flsh_vld1)
spc2_flsh_vld_capture1 <= 1'b1;
else
spc2_flsh_vld_capture1 <= 1'b0;
end
always @(spc2_flsh_vld_d2 or spc2_flsh_vld2)
begin
if (spc2_flsh_vld_d2 && ~spc2_flsh_vld2)
spc2_flsh_vld_capture2 <= 1'b1;
else
spc2_flsh_vld_capture2 <= 1'b0;
end
always @(spc2_flsh_vld_d3 or spc2_flsh_vld3)
begin
if (spc2_flsh_vld_d3 && ~spc2_flsh_vld3)
spc2_flsh_vld_capture3 <= 1'b1;
else
spc2_flsh_vld_capture3 <= 1'b0;
end
always @(spc2_lmiss_pa0 or spc2_imiss_pa or spc2_imiss_vld_d or spc2_lmiss_vld0)
begin
if((spc2_lmiss_pa0 == spc2_imiss_pa) && spc2_imiss_vld_d && spc2_lmiss_vld0)
spc2_lmiss_eq0 = 1'b1;
else
spc2_lmiss_eq0 = 1'b0;
end
always @(spc2_lmiss_pa1 or spc2_imiss_pa or spc2_imiss_vld_d or spc2_lmiss_vld1)
begin
if((spc2_lmiss_pa1 == spc2_imiss_pa) && spc2_imiss_vld_d && spc2_lmiss_vld1)
spc2_lmiss_eq1 = 1'b1;
else
spc2_lmiss_eq1 = 1'b0;
end
always @(spc2_lmiss_pa2 or spc2_imiss_pa or spc2_imiss_vld_d or spc2_lmiss_vld2)
begin
if((spc2_lmiss_pa2 == spc2_imiss_pa) && spc2_imiss_vld_d && spc2_lmiss_vld2)
spc2_lmiss_eq2 = 1'b1;
else
spc2_lmiss_eq2 = 1'b0;
end
always @(spc2_lmiss_pa3 or spc2_imiss_pa or spc2_imiss_vld_d or spc2_lmiss_vld3)
begin
if((spc2_lmiss_pa3 == spc2_imiss_pa) && spc2_imiss_vld_d && spc2_lmiss_vld3)
spc2_lmiss_eq3 = 1'b1;
else
spc2_lmiss_eq3 = 1'b0;
end
always @(spc2_lmiss_pa0 or spc2_stb_atm_addr0 or spc2_atm_cntr0 or spc2_lmiss_vld0)
begin
if ( ((spc2_lmiss_pa0 == spc2_stb_atm_addr0) && (spc2_atm_cntr0 != 9'h000) && spc2_lmiss_vld0) ||
((spc2_lmiss_pa1 == spc2_stb_atm_addr0) && (spc2_atm_cntr0 != 9'h000) && spc2_lmiss_vld1) ||
((spc2_lmiss_pa2 == spc2_stb_atm_addr0) && (spc2_atm_cntr0 != 9'h000) && spc2_lmiss_vld2) ||
((spc2_lmiss_pa3 == spc2_stb_atm_addr0) && (spc2_atm_cntr0 != 9'h000) && spc2_lmiss_vld3) )
spc2_atm_lmiss_eq0 = 1'b1;
else
spc2_atm_lmiss_eq0 = 1'b0;
end
always @(spc2_lmiss_pa1 or spc2_stb_atm_addr1 or spc2_atm_cntr1 or spc2_lmiss_vld1)
begin
if ( ((spc2_lmiss_pa0 == spc2_stb_atm_addr1) && (spc2_atm_cntr1 != 9'h000) && spc2_lmiss_vld0) ||
((spc2_lmiss_pa1 == spc2_stb_atm_addr1) && (spc2_atm_cntr1 != 9'h000) && spc2_lmiss_vld1) ||
((spc2_lmiss_pa2 == spc2_stb_atm_addr1) && (spc2_atm_cntr1 != 9'h000) && spc2_lmiss_vld2) ||
((spc2_lmiss_pa3 == spc2_stb_atm_addr1) && (spc2_atm_cntr1 != 9'h000) && spc2_lmiss_vld3) )
spc2_atm_lmiss_eq1 = 1'b1;
else
spc2_atm_lmiss_eq1 = 1'b0;
end
always @(spc2_lmiss_pa2 or spc2_stb_atm_addr2 or spc2_atm_cntr2 or spc2_lmiss_vld2)
begin
if ( ((spc2_lmiss_pa0 == spc2_stb_atm_addr2) && (spc2_atm_cntr2 != 9'h000) && spc2_lmiss_vld0) ||
((spc2_lmiss_pa1 == spc2_stb_atm_addr2) && (spc2_atm_cntr2 != 9'h000) && spc2_lmiss_vld1) ||
((spc2_lmiss_pa2 == spc2_stb_atm_addr2) && (spc2_atm_cntr2 != 9'h000) && spc2_lmiss_vld2) ||
((spc2_lmiss_pa3 == spc2_stb_atm_addr2) && (spc2_atm_cntr2 != 9'h000) && spc2_lmiss_vld3) )
spc2_atm_lmiss_eq2 = 1'b1;
else
spc2_atm_lmiss_eq2 = 1'b0;
end
always @(spc2_lmiss_pa3 or spc2_stb_atm_addr3 or spc2_atm_cntr3 or spc2_lmiss_vld3)
begin
if ( ((spc2_lmiss_pa0 == spc2_stb_atm_addr3) && (spc2_atm_cntr3 != 9'h000) && spc2_lmiss_vld0) ||
((spc2_lmiss_pa1 == spc2_stb_atm_addr3) && (spc2_atm_cntr3 != 9'h000) && spc2_lmiss_vld1) ||
((spc2_lmiss_pa2 == spc2_stb_atm_addr3) && (spc2_atm_cntr3 != 9'h000) && spc2_lmiss_vld2) ||
((spc2_lmiss_pa3 == spc2_stb_atm_addr3) && (spc2_atm_cntr3 != 9'h000) && spc2_lmiss_vld3) )
spc2_atm_lmiss_eq3 = 1'b1;
else
spc2_atm_lmiss_eq3 = 1'b0;
end
always @(spc2_imiss_pa or spc2_stb_atm_addr0 or spc2_atm_cntr0 or spc2_imiss_vld_d)
begin
if((spc2_imiss_pa == spc2_stb_atm_addr0) && (spc2_atm_cntr0 != 9'h000) && spc2_imiss_vld_d)
spc2_atm_imiss_eq0 = 1'b1;
else
spc2_atm_imiss_eq0 = 1'b0;
end
always @(spc2_imiss_pa or spc2_stb_atm_addr1 or spc2_atm_cntr1 or spc2_imiss_vld_d)
begin
if((spc2_imiss_pa == spc2_stb_atm_addr1) && (spc2_atm_cntr1 != 9'h000) && spc2_imiss_vld_d)
spc2_atm_imiss_eq1 = 1'b1;
else
spc2_atm_imiss_eq1 = 1'b0;
end
always @(spc2_imiss_pa or spc2_stb_atm_addr2 or spc2_atm_cntr2 or spc2_imiss_vld_d)
begin
if((spc2_imiss_pa == spc2_stb_atm_addr2) && (spc2_atm_cntr2 != 9'h000) && spc2_imiss_vld_d)
spc2_atm_imiss_eq2 = 1'b1;
else
spc2_atm_imiss_eq2 = 1'b0;
end
always @(spc2_imiss_pa or spc2_stb_atm_addr3 or spc2_atm_cntr3 or spc2_imiss_vld_d)
begin
if((spc2_imiss_pa == spc2_stb_atm_addr3) && (spc2_atm_cntr3 != 9'h000) && spc2_imiss_vld_d)
spc2_atm_imiss_eq3 = 1'b1;
else
spc2_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc2_imiss_vld || ~rst_l)
spc2_imiss_vld_d <= 1'b0;
else
spc2_imiss_vld_d <= spc2_imiss_vld;
if( ~spc2_ld_miss || ~rst_l)
spc2_ld_miss_capture <= 1'b0;
else
spc2_ld_miss_capture <= spc2_ld_miss;
end
always @(spc2_stb_ced0 or spc2_stb_ced0_d)
begin
if (~spc2_stb_ced0 && spc2_stb_ced0_d)
spc2_stb_ced_capture0 <= 1'b1;
else
spc2_stb_ced_capture0 <= 1'b0;
end
always @(spc2_stb_ced1 or spc2_stb_ced1_d)
begin
if (~spc2_stb_ced1 && spc2_stb_ced1_d)
spc2_stb_ced_capture1 <= 1'b1;
else
spc2_stb_ced_capture1 <= 1'b0;
end
always @(spc2_stb_ced2 or spc2_stb_ced2_d)
begin
if (~spc2_stb_ced2 && spc2_stb_ced2_d)
spc2_stb_ced_capture2 <= 1'b1;
else
spc2_stb_ced_capture2 <= 1'b0;
end
always @(spc2_stb_ced3 or spc2_stb_ced3_d)
begin
if (~spc2_stb_ced3 && spc2_stb_ced3_d)
spc2_stb_ced_capture3 <= 1'b1;
else
spc2_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc2_stb_state_ack0 != 8'h00 && (spc2_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_ack_counter0 = %d", spc2_stb_ack_cntr0);
end
else if(spc2_stb_cam_hit && spc2_ld0_inst_vld_g && (spc2_stb_state_ack0 == 8'h00))
begin
spc2_stb_ack_cntr0 <= spc2_stb_ack_cntr0 + 1;
end
else if( (spc2_stb_state_ack0 == 8'h00 ) && (spc2_stb_ack_cntr0 != 9'h000))
begin
spc2_stb_ack_cntr0 <= spc2_stb_ack_cntr0 + 1;
end // if ( (spc2_stb_state_ack0 == 8'h00 ) && (spc2_stb_ack_cntr0 != 9'h000))
else
begin
spc2_stb_ack_cntr0 <= spc2_stb_ack_cntr0;
end
if( (spc2_stb_state_ack1 != 8'h00 && (spc2_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_ack_counter1 = %d", spc2_stb_ack_cntr1);
end
else if(spc2_stb_cam_hit && spc2_ld1_inst_vld_g && (spc2_stb_state_ack1 == 8'h00))
begin
spc2_stb_ack_cntr1 <= spc2_stb_ack_cntr1 + 1;
end
else if( (spc2_stb_state_ack1 == 8'h00 ) && (spc2_stb_ack_cntr1 != 9'h000))
begin
spc2_stb_ack_cntr1 <= spc2_stb_ack_cntr1 + 1;
end // if ( (spc2_stb_state_ack1 == 8'h00 ) && (spc2_stb_ack_cntr1 != 9'h000))
else
begin
spc2_stb_ack_cntr1 <= spc2_stb_ack_cntr1;
end
if( (spc2_stb_state_ack2 != 8'h00 && (spc2_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_ack_counter2 = %d", spc2_stb_ack_cntr2);
end
else if(spc2_stb_cam_hit && spc2_ld2_inst_vld_g && (spc2_stb_state_ack2 == 8'h00))
begin
spc2_stb_ack_cntr2 <= spc2_stb_ack_cntr2 + 1;
end
else if( (spc2_stb_state_ack2 == 8'h00 ) && (spc2_stb_ack_cntr2 != 9'h000))
begin
spc2_stb_ack_cntr2 <= spc2_stb_ack_cntr2 + 1;
end // if ( (spc2_stb_state_ack2 == 8'h00 ) && (spc2_stb_ack_cntr2 != 9'h000))
else
begin
spc2_stb_ack_cntr2 <= spc2_stb_ack_cntr2;
end
if( (spc2_stb_state_ack3 != 8'h00 && (spc2_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_ack_counter3 = %d", spc2_stb_ack_cntr3);
end
else if(spc2_stb_cam_hit && spc2_ld3_inst_vld_g && (spc2_stb_state_ack3 == 8'h00))
begin
spc2_stb_ack_cntr3 <= spc2_stb_ack_cntr3 + 1;
end
else if( (spc2_stb_state_ack3 == 8'h00 ) && (spc2_stb_ack_cntr3 != 9'h000))
begin
spc2_stb_ack_cntr3 <= spc2_stb_ack_cntr3 + 1;
end // if ( (spc2_stb_state_ack3 == 8'h00 ) && (spc2_stb_ack_cntr3 != 9'h000))
else
begin
spc2_stb_ack_cntr3 <= spc2_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc2_stb0_full_w2 or spc2_stb0_full)
begin
if (~spc2_stb0_full_w2 && spc2_stb0_full)
spc2_stb_full_capture0 <= 1'b1;
else
spc2_stb_full_capture0 <= 1'b0;
end
always @(spc2_stb1_full_w2 or spc2_stb1_full)
begin
if (~spc2_stb1_full_w2 && spc2_stb1_full)
spc2_stb_full_capture1 <= 1'b1;
else
spc2_stb_full_capture1 <= 1'b0;
end
always @(spc2_stb2_full_w2 or spc2_stb2_full)
begin
if (~spc2_stb2_full_w2 && spc2_stb2_full)
spc2_stb_full_capture2 <= 1'b1;
else
spc2_stb_full_capture2 <= 1'b0;
end
always @(spc2_stb3_full_w2 or spc2_stb3_full)
begin
if (~spc2_stb3_full_w2 && spc2_stb3_full)
spc2_stb_full_capture3 <= 1'b1;
else
spc2_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc2_stb0_full && (spc2_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_full_counter0 = %d", spc2_stb_full_cntr0);
end
else if( spc2_stb0_full)
begin
spc2_stb_full_cntr0 <= spc2_stb_full_cntr0 + 1;
end
else
begin
spc2_stb_full_cntr0 <= spc2_stb_full_cntr0;
end
if( ( ~spc2_stb1_full && (spc2_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_full_counter1 = %d", spc2_stb_full_cntr1);
end
else if( spc2_stb1_full)
begin
spc2_stb_full_cntr1 <= spc2_stb_full_cntr1 + 1;
end
else
begin
spc2_stb_full_cntr1 <= spc2_stb_full_cntr1;
end
if( ( ~spc2_stb2_full && (spc2_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_full_counter2 = %d", spc2_stb_full_cntr2);
end
else if( spc2_stb2_full)
begin
spc2_stb_full_cntr2 <= spc2_stb_full_cntr2 + 1;
end
else
begin
spc2_stb_full_cntr2 <= spc2_stb_full_cntr2;
end
if( ( ~spc2_stb3_full && (spc2_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc2_stb_full_counter3 = %d", spc2_stb_full_cntr3);
end
else if( spc2_stb3_full)
begin
spc2_stb_full_cntr3 <= spc2_stb_full_cntr3 + 1;
end
else
begin
spc2_stb_full_cntr3 <= spc2_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc2_lmq0_full_d or spc2_lmq0_full)
begin
if (spc2_lmq0_full_d && ~spc2_lmq0_full)
spc2_lmq_full_capture0 <= 1'b1;
else
spc2_lmq_full_capture0 <= 1'b0;
end
always @(spc2_lmq1_full_d or spc2_lmq1_full)
begin
if (spc2_lmq1_full_d && ~spc2_lmq1_full)
spc2_lmq_full_capture1 <= 1'b1;
else
spc2_lmq_full_capture1 <= 1'b0;
end
always @(spc2_lmq2_full_d or spc2_lmq2_full)
begin
if (spc2_lmq2_full_d && ~spc2_lmq2_full)
spc2_lmq_full_capture2 <= 1'b1;
else
spc2_lmq_full_capture2 <= 1'b0;
end
always @(spc2_lmq3_full_d or spc2_lmq3_full)
begin
if (spc2_lmq3_full_d && ~spc2_lmq3_full)
spc2_lmq_full_capture3 <= 1'b1;
else
spc2_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc2_lmq0_full && (spc2_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc2_lmq_full_cntr0 <= 9'h000;
spc2_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_lmq_full_counter0 = %d", spc2_lmq_full_cntr0);
end
else if( spc2_lmq0_full)
begin
spc2_lmq_full_cntr0 <= spc2_lmq_full_cntr0 + 1;
spc2_lmq0_full_d <= spc2_lmq0_full;
end
else
begin
spc2_lmq_full_cntr0 <= spc2_lmq_full_cntr0;
spc2_lmq0_full_d <= spc2_lmq0_full;
end
if( ( ~spc2_lmq1_full && (spc2_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc2_lmq_full_cntr1 <= 9'h000;
spc2_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_lmq_full_counter1 = %d", spc2_lmq_full_cntr1);
end
else if( spc2_lmq1_full)
begin
spc2_lmq_full_cntr1 <= spc2_lmq_full_cntr1 + 1;
spc2_lmq1_full_d <= spc2_lmq1_full;
end
else
begin
spc2_lmq_full_cntr1 <= spc2_lmq_full_cntr1;
spc2_lmq1_full_d <= spc2_lmq1_full;
end
if( ( ~spc2_lmq2_full && (spc2_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc2_lmq_full_cntr2 <= 9'h000;
spc2_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_lmq_full_counter2 = %d", spc2_lmq_full_cntr2);
end
else if( spc2_lmq2_full)
begin
spc2_lmq_full_cntr2 <= spc2_lmq_full_cntr2 + 1;
spc2_lmq2_full_d <= spc2_lmq2_full;
end
else
begin
spc2_lmq_full_cntr2 <= spc2_lmq_full_cntr2;
spc2_lmq2_full_d <= spc2_lmq2_full;
end
if( ( ~spc2_lmq3_full && (spc2_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc2_lmq_full_cntr3 <= 9'h000;
spc2_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_lmq_full_counter3 = %d", spc2_lmq_full_cntr3);
end
else if( spc2_lmq3_full)
begin
spc2_lmq_full_cntr3 <= spc2_lmq_full_cntr3 + 1;
spc2_lmq3_full_d <= spc2_lmq3_full;
end
else
begin
spc2_lmq_full_cntr3 <= spc2_lmq_full_cntr3;
spc2_lmq3_full_d <= spc2_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc2_dfq_full_d or spc2_dfq_full)
begin
if (spc2_dfq_full_d && ~spc2_dfq_full)
spc2_dfq_full_capture <= 1'b1;
else
spc2_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc2_dfq_full && (spc2_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc2_dfq_full_cntr <= 9'h000;
spc2_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dfq_full_counter = %d", spc2_dfq_full_cntr);
end
else if( spc2_dfq_full)
begin
spc2_dfq_full_cntr <= spc2_dfq_full_cntr + 1;
spc2_dfq_full_d <= spc2_dfq_full;
end
else
begin
spc2_dfq_full_cntr <= spc2_dfq_full_cntr;
spc2_dfq_full_d <= spc2_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc2_dva_full_d or spc2_dva_inv)
begin
if (spc2_dva_full_d && ~spc2_dva_inv)
spc2_dva_full_capture <= 1'b1;
else
spc2_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc2_dva_din && spc2_dva_wen)
begin
spc2_dva_inv <= 1'b1;
spc2_dva_waddr_d <= spc2_dva_waddr;
end
else if(~spc2_dva_din && spc2_dva_wen)
begin
spc2_dva_inv <= 1'b0;
spc2_dva_waddr_d <= 5'b00000;
end
else
begin
spc2_dva_inv <= spc2_dva_inv;
spc2_dva_waddr_d <= spc2_dva_waddr_d;
end
end
always @(spc2_dva_raddr or spc2_dva_ren or spc2_dva_inv)
begin
if (spc2_dva_inv && spc2_dva_ren && (spc2_dva_raddr[6:2] == spc2_dva_waddr_d))
spc2_dva_vld2lkup <= 1'b1;
else
spc2_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc2_dva_inv && (spc2_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc2_dva_full_cntr <= 9'h000;
spc2_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dva_full_counter = %d", spc2_dva_full_cntr);
end
else if( spc2_dva_inv)
begin
spc2_dva_full_cntr <= spc2_dva_full_cntr + 1;
spc2_dva_full_d <= spc2_dva_inv;
end
else
begin
spc2_dva_full_cntr <= spc2_dva_full_cntr;
spc2_dva_full_d <= spc2_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc2_dva_vfull_d or spc2_dva_vld)
begin
if (spc2_dva_vfull_d && ~spc2_dva_vld)
spc2_dva_vfull_capture <= 1'b1;
else
spc2_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc2_dva_din && spc2_dva_wen)
begin
spc2_dva_vld <= 1'b1;
spc2_dva_invwaddr_d <= spc2_dva_waddr;
spc2_dva_invld_err <= spc2_dva_inv_perror;
end
else if(spc2_dva_din && spc2_dva_wen)
begin
spc2_dva_vld <= 1'b0;
spc2_dva_invwaddr_d <= 5'b00000;
spc2_dva_invld_err <= 1'b0;
end
else
begin
spc2_dva_vld <= spc2_dva_vld;
spc2_dva_invwaddr_d <= spc2_dva_invwaddr_d;
spc2_dva_invld_err <= spc2_dva_invld_err;
end
end
always @(spc2_dva_raddr or spc2_dva_ren or spc2_dva_vld)
begin
if (spc2_dva_vld && spc2_dva_ren && (spc2_dva_raddr[6:2] == spc2_dva_waddr_d))
spc2_dva_invld2lkup <= 1'b1;
else
spc2_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc2_dva_vld && (spc2_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc2_dva_vfull_cntr <= 9'h000;
spc2_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc2_dva_vfull_counter = %d", spc2_dva_vfull_cntr);
end
else if( spc2_dva_vld)
begin
spc2_dva_vfull_cntr <= spc2_dva_vfull_cntr + 1;
spc2_dva_vfull_d <= spc2_dva_vld;
end
else
begin
spc2_dva_vfull_cntr <= spc2_dva_vfull_cntr;
spc2_dva_vfull_d <= spc2_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc2_dva_raddr or spc2_dva_waddr or spc2_dva_ren or spc2_dva_wen)
begin
if ( spc2_dva_ren && spc2_dva_wen && (spc2_dva_raddr[6:2] == spc2_dva_waddr))
spc2_dva_collide <= 1'b1;
else
spc2_dva_collide <= 1'b0;
end
// dva error cases
always @(spc2_dva_raddr or spc2_dva_ren or spc2_dva_dtag_perror or spc2_dva_dtag_perror)
begin
if (spc2_dva_ren && (spc2_dva_dtag_perror || spc2_dva_dtag_perror))
spc2_dva_err <= 1'b1;
else
spc2_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc2_dva_err)
spc2_dva_efull_d <= 1'b1;
else
spc2_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc2_dva_ren && ~(spc2_dva_dtag_perror || spc2_dva_dtag_perror ) &&
(spc2_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc2_dva_efull_cntr <= 9'h000;
spc2_dva_raddr_d <= spc2_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc2_dva_efull_counter = %d", spc2_dva_efull_cntr);
end
else if(spc2_dva_efull_d)
begin
spc2_dva_efull_cntr <= spc2_dva_efull_cntr + 1;
spc2_dva_raddr_d <= spc2_dva_raddr_d;
end
else
begin
spc2_dva_efull_cntr <= spc2_dva_efull_cntr;
spc2_dva_raddr_d <= spc2_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC3
wire spc3_dva_ren = `TOP_DESIGN.sparc3.lsu.ifu_lsu_ld_inst_e;
wire spc3_dva_wen = `TOP_DESIGN.sparc3.lsu.lsu_dtagv_wr_vld_e;
wire spc3_dva_din = `TOP_DESIGN.sparc3.lsu.dva_din_e;
wire [3:0] spc3_dva_dout = `TOP_DESIGN.sparc3.lsu.dva_vld_m[3:0];
wire [6:0] spc3_dva_raddr = `TOP_DESIGN.sparc3.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc3_dva_waddr = `TOP_DESIGN.sparc3.lsu.dva_wr_adr_e[10:6];
wire spc3_dva_dtag_perror = `TOP_DESIGN.sparc3.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc3_dva_dcache_perror = `TOP_DESIGN.sparc3.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc3_dva_inv_perror = `TOP_DESIGN.sparc3.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc3_ld_miss = `TOP_DESIGN.sparc3.lsu.dctl.lsu_ld_miss_wb;
reg spc3_ld_miss_capture;
wire spc3_atomic_g = `TOP_DESIGN.sparc3.lsu.qctl1.atomic_g;
wire [1:0] spc3_atm_type0 = `TOP_DESIGN.sparc3.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc3_atm_type1 = `TOP_DESIGN.sparc3.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc3_atm_type2 = `TOP_DESIGN.sparc3.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc3_atm_type3 = `TOP_DESIGN.sparc3.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc3_dctl_lsu_way_hit = `TOP_DESIGN.sparc3.lsu.dctl.lsu_way_hit;
wire spc3_dctl_dcache_enable_g = `TOP_DESIGN.sparc3.lsu.dctl.dcache_enable_g;
wire spc3_dctl_ldxa_internal = `TOP_DESIGN.sparc3.lsu.dctl.ldxa_internal;
wire spc3_dctl_ldst_dbl_g = `TOP_DESIGN.sparc3.lsu.dctl.ldst_dbl_g;
wire spc3_dctl_atomic_g = `TOP_DESIGN.sparc3.lsu.dctl.atomic_g;
wire spc3_dctl_stb_cam_hit = `TOP_DESIGN.sparc3.lsu.dctl.stb_cam_hit;
wire spc3_dctl_endian_mispred_g = `TOP_DESIGN.sparc3.lsu.dctl.endian_mispred_g;
wire spc3_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc3.lsu.dctl.dcache_rd_parity_error;
wire spc3_dctl_dtag_perror_g = `TOP_DESIGN.sparc3.lsu.dctl.dtag_perror_g;
wire spc3_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc3.lsu.dctl.tte_data_perror_unc;
wire spc3_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc3.lsu.dctl.ld_inst_vld_g;
wire spc3_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc3.lsu.dctl.lsu_alt_space_g;
wire spc3_dctl_recognized_asi_g = `TOP_DESIGN.sparc3.lsu.dctl.recognized_asi_g;
wire spc3_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc3.lsu.dctl.ncache_asild_rq_g ;
wire spc3_dctl_bld_hit;
wire spc3_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc3_ixinv0 = `TOP_DESIGN.sparc3.lsu.qctl2.imiss0_inv_en;
wire spc3_ixinv1 = `TOP_DESIGN.sparc3.lsu.qctl2.imiss1_inv_en;
wire spc3_ixinv2 = `TOP_DESIGN.sparc3.lsu.qctl2.imiss2_inv_en;
wire spc3_ixinv3 = `TOP_DESIGN.sparc3.lsu.qctl2.imiss3_inv_en;
wire spc3_ifill = `TOP_DESIGN.sparc3.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc3_inv = `TOP_DESIGN.sparc3.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc3_inv_clr = `TOP_DESIGN.sparc3.lsu.qctl2.ifu_lsu_inv_clear;
wire spc3_ibuf_busy = `TOP_DESIGN.sparc3.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc3_l2 = `TOP_DESIGN.sparc3.lsu.dctl.l2fill_vld_g ;
wire spc3_unc = `TOP_DESIGN.sparc3.lsu.dctl.unc_err_trap_g ;
wire spc3_fpld = `TOP_DESIGN.sparc3.lsu.dctl.l2fill_fpld_g ;
wire spc3_fpldst = `TOP_DESIGN.sparc3.lsu.dctl.fp_ldst_g ;
wire spc3_unflush = `TOP_DESIGN.sparc3.lsu.dctl.ld_inst_vld_unflushed ;
wire spc3_ldw = `TOP_DESIGN.sparc3.lsu.dctl.lsu_inst_vld_w ;
wire spc3_byp = `TOP_DESIGN.sparc3.lsu.dctl.intld_byp_data_vld_m ;
wire spc3_flsh = `TOP_DESIGN.sparc3.lsu.lsu_exu_flush_pipe_w ;
wire spc3_chm = `TOP_DESIGN.sparc3.lsu.dctl.common_ldst_miss_w ;
wire spc3_ldxa = `TOP_DESIGN.sparc3.lsu.dctl.ldxa_internal ;
wire spc3_ato = `TOP_DESIGN.sparc3.lsu.dctl.atomic_g ;
wire spc3_pref = `TOP_DESIGN.sparc3.lsu.dctl.pref_inst_g ;
wire spc3_chit = `TOP_DESIGN.sparc3.lsu.dctl.stb_cam_hit ;
wire spc3_dcp = `TOP_DESIGN.sparc3.lsu.dctl.dcache_rd_parity_error ;
wire spc3_dtp = `TOP_DESIGN.sparc3.lsu.dctl.dtag_perror_g ;
//wire spc3_mpc = `TOP_DESIGN.sparc3.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc3_mpc = 1'b0;
wire spc3_mpu = `TOP_DESIGN.sparc3.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc3_exu_und;
reg [4:0] spc3_exu;
// excptn
wire spc3_exp_wtchpt_trp_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc3_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc3_exp_priv_violtn_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc3_exp_daccess_excptn_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc3_exp_daccess_prot_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc3_exp_priv_action_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc3_exp_spec_access_epage_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc3_exp_uncache_atomic_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc3_exp_illegal_asi_action_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc3_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc3_exp_asi_rd_unc = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc3_exp_tlb_data_ce = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc3_exp_asi_rd_unc = 1'b0;
wire spc3_exp_tlb_data_ce = 1'b0;
wire spc3_exp_tlb_data_ue = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc3_exp_tlb_tag_ue = `TOP_DESIGN.sparc3.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc3_exp_unc = `TOP_DESIGN.sparc3.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc3_exp_corr = `TOP_DESIGN.sparc3.lsu.excpctl.tte_data_perror_corr;
wire spc3_exp_corr = 1'b0;
wire [15:0] spc3_exp_und;
reg [4:0] spc3_exp;
// dctl cmplt
wire spc3_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc3.lsu.dctl.stxa_internal_d2;
wire spc3_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc3.lsu.dctl.lsu_l2fill_vld;
wire spc3_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc3.lsu.dctl.atomic_ld_squash_e;
wire spc3_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc3.lsu.qctl2.lsu_ignore_fill;
wire spc3_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc3.lsu.dctl.l2fill_fpld_e;
// wire spc3_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc3.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc3_dctl_fill_err_trap_e = `TOP_DESIGN.sparc3.lsu.dctl.fill_err_trap_e;
wire spc3_dctl_l2_corr_error_e = `TOP_DESIGN.sparc3.lsu.dctl.l2_corr_error_e;
wire [3:0] spc3_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc3.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc3_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc3.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc3_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc3.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc3_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc3.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc3_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc3.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc3_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc3.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc3_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc3_ldstcond_cmplt_d;
wire spc3_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc3.lsu.qctl1.ld_sec_hit_thrd0;
wire spc3_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_inst_vld_g;
wire spc3_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc3_ld0_pkt_vld_unmasked_d;
reg spc3_qctl1_ld_sec_hit_thrd0_w2;
wire spc3_dctl_thread0_w3 = `TOP_DESIGN.sparc3.lsu.dctl.thread0_w3;
wire spc3_dctl_dfill_thread0 = `TOP_DESIGN.sparc3.lsu.dctl.dfill_thread0;
wire spc3_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc3.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc3_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc3.lsu.dctl.diag_wr_cmplt0;
wire spc3_dctl_bsync0_reset = `TOP_DESIGN.sparc3.lsu.dctl.bsync0_reset;
wire spc3_dctl_late_cmplt0 = `TOP_DESIGN.sparc3.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc3_dctl_stxa_cmplt0;
wire spc3_dctl_l2fill_cmplt0;
wire spc3_dctl_atm_cmplt0;
wire spc3_dctl_fillerr0;
wire [4:0] spc3_cmplt0;
wire [5:0] spc3_dctl_ldst_cond_cmplt0;
reg [3:0] spc3_ldstcond_cmplt0;
reg [3:0] spc3_ldstcond_cmplt0_d;
wire spc3_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc3.lsu.qctl1.ld_sec_hit_thrd1;
wire spc3_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_inst_vld_g;
wire spc3_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc3_ld1_pkt_vld_unmasked_d;
reg spc3_qctl1_ld_sec_hit_thrd1_w2;
wire spc3_dctl_thread1_w3 = `TOP_DESIGN.sparc3.lsu.dctl.thread1_w3;
wire spc3_dctl_dfill_thread1 = `TOP_DESIGN.sparc3.lsu.dctl.dfill_thread1;
wire spc3_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc3.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc3_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc3.lsu.dctl.diag_wr_cmplt1;
wire spc3_dctl_bsync1_reset = `TOP_DESIGN.sparc3.lsu.dctl.bsync1_reset;
wire spc3_dctl_late_cmplt1 = `TOP_DESIGN.sparc3.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc3_dctl_stxa_cmplt1;
wire spc3_dctl_l2fill_cmplt1;
wire spc3_dctl_atm_cmplt1;
wire spc3_dctl_fillerr1;
wire [4:0] spc3_cmplt1;
wire [5:0] spc3_dctl_ldst_cond_cmplt1;
reg [3:0] spc3_ldstcond_cmplt1;
reg [3:0] spc3_ldstcond_cmplt1_d;
wire spc3_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc3.lsu.qctl1.ld_sec_hit_thrd2;
wire spc3_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_inst_vld_g;
wire spc3_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc3_ld2_pkt_vld_unmasked_d;
reg spc3_qctl1_ld_sec_hit_thrd2_w2;
wire spc3_dctl_thread2_w3 = `TOP_DESIGN.sparc3.lsu.dctl.thread2_w3;
wire spc3_dctl_dfill_thread2 = `TOP_DESIGN.sparc3.lsu.dctl.dfill_thread2;
wire spc3_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc3.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc3_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc3.lsu.dctl.diag_wr_cmplt2;
wire spc3_dctl_bsync2_reset = `TOP_DESIGN.sparc3.lsu.dctl.bsync2_reset;
wire spc3_dctl_late_cmplt2 = `TOP_DESIGN.sparc3.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc3_dctl_stxa_cmplt2;
wire spc3_dctl_l2fill_cmplt2;
wire spc3_dctl_atm_cmplt2;
wire spc3_dctl_fillerr2;
wire [4:0] spc3_cmplt2;
wire [5:0] spc3_dctl_ldst_cond_cmplt2;
reg [3:0] spc3_ldstcond_cmplt2;
reg [3:0] spc3_ldstcond_cmplt2_d;
wire spc3_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc3.lsu.qctl1.ld_sec_hit_thrd3;
wire spc3_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_inst_vld_g;
wire spc3_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc3_ld3_pkt_vld_unmasked_d;
reg spc3_qctl1_ld_sec_hit_thrd3_w2;
wire spc3_dctl_thread3_w3 = `TOP_DESIGN.sparc3.lsu.dctl.thread3_w3;
wire spc3_dctl_dfill_thread3 = `TOP_DESIGN.sparc3.lsu.dctl.dfill_thread3;
wire spc3_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc3.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc3_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc3.lsu.dctl.diag_wr_cmplt3;
wire spc3_dctl_bsync3_reset = `TOP_DESIGN.sparc3.lsu.dctl.bsync3_reset;
wire spc3_dctl_late_cmplt3 = `TOP_DESIGN.sparc3.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc3_dctl_stxa_cmplt3;
wire spc3_dctl_l2fill_cmplt3;
wire spc3_dctl_atm_cmplt3;
wire spc3_dctl_fillerr3;
wire [4:0] spc3_cmplt3;
wire [5:0] spc3_dctl_ldst_cond_cmplt3;
reg [3:0] spc3_ldstcond_cmplt3;
reg [3:0] spc3_ldstcond_cmplt3_d;
wire spc3_qctl1_bld_g = `TOP_DESIGN.sparc3.lsu.qctl1.bld_g;
wire spc3_qctl1_bld_reset = `TOP_DESIGN.sparc3.lsu.qctl1.bld_reset;
wire [1:0] spc3_qctl1_bld_cnt = `TOP_DESIGN.sparc3.lsu.qctl1.bld_cnt;
reg [9:0] spc3_bld0_full_cntr;
reg [1:0] spc3_bld0_full_d;
reg spc3_bld0_full_capture;
reg [9:0] spc3_bld1_full_cntr;
reg [1:0] spc3_bld1_full_d;
reg spc3_bld1_full_capture;
reg [9:0] spc3_bld2_full_cntr;
reg [1:0] spc3_bld2_full_d;
reg spc3_bld2_full_capture;
reg [9:0] spc3_bld3_full_cntr;
reg [1:0] spc3_bld3_full_d;
reg spc3_bld3_full_capture;
wire spc3_ipick = `TOP_DESIGN.sparc3.lsu.qctl1.imiss_pcx_rq_vld;
wire spc3_lpick = `TOP_DESIGN.sparc3.lsu.qctl1.ld_pcx_rq_all;
wire spc3_spick = `TOP_DESIGN.sparc3.lsu.qctl1.st_pcx_rq_all;
wire spc3_mpick = `TOP_DESIGN.sparc3.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc3_apick = `TOP_DESIGN.sparc3.lsu.qctl1.all_pcx_rq_pick;
wire spc3_msquash = `TOP_DESIGN.sparc3.lsu.qctl1.mcycle_squash_d1;
reg spc3_fpicko;
wire [3:0] spc3_fpick;
wire [39:0] spc3_imiss_pa = `TOP_DESIGN.sparc3.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc3_imiss_vld = `TOP_DESIGN.sparc3.lsu.qctl1.imiss_pcx_rq_vld;
reg spc3_imiss_vld_d;
wire [39:0] spc3_lmiss_pa0 = `TOP_DESIGN.sparc3.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc3_lmiss_vld0 = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_pcx_rq_vld;
wire spc3_ld_pkt_vld0 = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_pkt_vld;
wire spc3_st_pkt_vld0 = `TOP_DESIGN.sparc3.lsu.qctl1.st0_pkt_vld;
reg spc3_lmiss_eq0;
reg spc3_atm_imiss_eq0;
wire [39:0] spc3_lmiss_pa1 = `TOP_DESIGN.sparc3.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc3_lmiss_vld1 = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_pcx_rq_vld;
wire spc3_ld_pkt_vld1 = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_pkt_vld;
wire spc3_st_pkt_vld1 = `TOP_DESIGN.sparc3.lsu.qctl1.st1_pkt_vld;
reg spc3_lmiss_eq1;
reg spc3_atm_imiss_eq1;
wire [39:0] spc3_lmiss_pa2 = `TOP_DESIGN.sparc3.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc3_lmiss_vld2 = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_pcx_rq_vld;
wire spc3_ld_pkt_vld2 = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_pkt_vld;
wire spc3_st_pkt_vld2 = `TOP_DESIGN.sparc3.lsu.qctl1.st2_pkt_vld;
reg spc3_lmiss_eq2;
reg spc3_atm_imiss_eq2;
wire [39:0] spc3_lmiss_pa3 = `TOP_DESIGN.sparc3.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc3_lmiss_vld3 = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_pcx_rq_vld;
wire spc3_ld_pkt_vld3 = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_pkt_vld;
wire spc3_st_pkt_vld3 = `TOP_DESIGN.sparc3.lsu.qctl1.st3_pkt_vld;
reg spc3_lmiss_eq3;
reg spc3_atm_imiss_eq3;
wire [44:0] spc3_wdata_ramc = `TOP_DESIGN.sparc3.lsu.stb_cam.wdata_ramc;
wire spc3_wptr_vld = `TOP_DESIGN.sparc3.lsu.stb_cam.wptr_vld;
wire [75:0] spc3_wdata_ramd = {`TOP_DESIGN.sparc3.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc3.lsu.lsu_stb_st_data_g[63:0]};
wire spc3_stb_cam_hit = `TOP_DESIGN.sparc3.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc3_stb_cam_hit_ptr = `TOP_DESIGN.sparc3.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc3_stb_ld_full_raw = `TOP_DESIGN.sparc3.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc3_stb_ld_partial_raw = `TOP_DESIGN.sparc3.lsu.stb_ld_partial_raw[7:0];
wire spc3_stb_cam_mhit = `TOP_DESIGN.sparc3.lsu.stb_cam_mhit;
wire [3:0] spc3_dfq_vld_entries = `TOP_DESIGN.sparc3.lsu.qctl2.dfq_vld_entries;
wire spc3_dfq_full;
reg [9:0] spc3_dfq_full_cntr;
reg spc3_dfq_full_d;
reg spc3_dfq_full_capture;
reg [9:0] spc3_dfq_full_cntr1;
reg spc3_dfq_full_d1;
wire spc3_dfq_full1;
reg spc3_dfq_full_capture1;
reg [9:0] spc3_dfq_full_cntr2;
reg spc3_dfq_full_d2;
wire spc3_dfq_full2;
reg spc3_dfq_full_capture2;
reg [9:0] spc3_dfq_full_cntr3;
reg spc3_dfq_full_d3;
wire spc3_dfq_full3;
reg spc3_dfq_full_capture3;
reg [9:0] spc3_dfq_full_cntr4;
reg spc3_dfq_full_d4;
wire spc3_dfq_full4;
reg spc3_dfq_full_capture4;
reg [9:0] spc3_dfq_full_cntr5;
reg spc3_dfq_full_d5;
wire spc3_dfq_full5;
reg spc3_dfq_full_capture5;
reg [9:0] spc3_dfq_full_cntr6;
reg spc3_dfq_full_d6;
wire spc3_dfq_full6;
reg spc3_dfq_full_capture6;
reg [9:0] spc3_dfq_full_cntr7;
reg spc3_dfq_full_d7;
wire spc3_dfq_full7;
reg spc3_dfq_full_capture7;
wire spc3_dva_rdwrhit;
reg [9:0] spc3_dva_full_cntr;
reg spc3_dva_full_d;
reg spc3_dva_full_capture;
reg spc3_dva_inv;
reg spc3_dva_inv_d;
reg spc3_dva_vld;
reg spc3_dva_vld_d;
reg [9:0] spc3_dva_vfull_cntr;
reg spc3_dva_vfull_d;
reg spc3_dva_vfull_capture;
reg spc3_dva_collide;
reg spc3_dva_vld2lkup;
reg spc3_dva_invld2lkup;
reg spc3_dva_invld_err;
reg [9:0] spc3_dva_efull_cntr;
reg spc3_dva_efull_d;
reg spc3_dva_vlddtag_err;
reg spc3_dva_vlddcache_err;
reg spc3_dva_err;
reg [6:0] spc3_dva_raddr_d;
reg [4:0] spc3_dva_waddr_d;
reg [4:0] spc3_dva_invwaddr_d;
reg spc3_ld0_lt_1;
reg spc3_ld0_lt_2;
reg spc3_ld0_lt_3;
reg spc3_ld1_lt_0;
reg spc3_ld1_lt_2;
reg spc3_ld1_lt_3;
reg spc3_ld2_lt_0;
reg spc3_ld2_lt_1;
reg spc3_ld2_lt_3;
reg spc3_ld3_lt_0;
reg spc3_ld3_lt_1;
reg spc3_ld3_lt_2;
reg spc3_st0_lt_1;
reg spc3_st0_lt_2;
reg spc3_st0_lt_3;
reg spc3_st1_lt_0;
reg spc3_st1_lt_2;
reg spc3_st1_lt_3;
reg spc3_st2_lt_0;
reg spc3_st2_lt_1;
reg spc3_st2_lt_3;
reg spc3_st3_lt_0;
reg spc3_st3_lt_1;
reg spc3_st3_lt_2;
wire [11:0] spc3_ld_ooo_ret;
wire [11:0] spc3_st_ooo_ret;
wire [7:0] spc3_stb_state_vld0 = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc3_stb_state_ack0 = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc3_stb_state_ced0 = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc3_stb_state_rst0 = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_state_rst;
wire spc3_stb_ack_vld0 = `TOP_DESIGN.sparc3.lsu.stb_ctl0.ack_vld;
wire spc3_ld0_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_inst_vld_g;
wire spc3_intrpt0_cmplt = `TOP_DESIGN.sparc3.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc3_stb0_full = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_full;
wire spc3_stb0_full_w2 = `TOP_DESIGN.sparc3.lsu.stb_ctl0.stb_full_w2;
wire spc3_lmq0_full = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_pcx_rq_vld;
wire spc3_mbar_vld0 = `TOP_DESIGN.sparc3.lsu.dctl.mbar_vld0;
wire spc3_ld0_unfilled = `TOP_DESIGN.sparc3.lsu.qctl1.ld0_unfilled;
wire spc3_flsh_vld0 = `TOP_DESIGN.sparc3.lsu.dctl.flsh_vld0;
reg [9:0] spc3_ld0_unf_cntr;
reg spc3_ld0_unfilled_d;
reg [9:0] spc3_st0_unf_cntr;
reg spc3_st0_unfilled_d;
reg spc3_st0_unfilled;
reg spc3_mbar_vld_d0;
reg spc3_flsh_vld_d0;
reg spc3_lmq0_full_d;
reg [9:0] spc3_lmq_full_cntr0;
reg spc3_lmq_full_capture0;
reg [9:0] spc3_stb_full_cntr0;
reg spc3_stb_full_capture0;
reg [9:0] spc3_mbar_vld_cntr0;
reg spc3_mbar_vld_capture0;
reg [9:0] spc3_flsh_vld_cntr0;
reg spc3_flsh_vld_capture0;
reg spc3_stb_head_hit0;
wire spc3_raw_ack_capture0;
reg [9:0] spc3_stb_ack_cntr0;
reg [9:0] spc3_stb_ced_cntr0;
reg spc3_stb_ced0_d;
reg spc3_stb_ced_capture0;
wire spc3_stb_ced0;
reg spc3_atm0_d;
reg [9:0] spc3_atm_cntr0;
reg spc3_atm_intrpt_capture0;
reg spc3_atm_intrpt_b4capture0;
reg spc3_atm_inv_capture0;
reg [39:0] spc3_stb_wr_addr0;
reg [39:0] spc3_stb_atm_addr0;
reg spc3_atm_lmiss_eq0;
wire [7:0] spc3_stb_state_vld1 = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc3_stb_state_ack1 = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc3_stb_state_ced1 = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc3_stb_state_rst1 = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_state_rst;
wire spc3_stb_ack_vld1 = `TOP_DESIGN.sparc3.lsu.stb_ctl1.ack_vld;
wire spc3_ld1_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_inst_vld_g;
wire spc3_intrpt1_cmplt = `TOP_DESIGN.sparc3.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc3_stb1_full = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_full;
wire spc3_stb1_full_w2 = `TOP_DESIGN.sparc3.lsu.stb_ctl1.stb_full_w2;
wire spc3_lmq1_full = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_pcx_rq_vld;
wire spc3_mbar_vld1 = `TOP_DESIGN.sparc3.lsu.dctl.mbar_vld1;
wire spc3_ld1_unfilled = `TOP_DESIGN.sparc3.lsu.qctl1.ld1_unfilled;
wire spc3_flsh_vld1 = `TOP_DESIGN.sparc3.lsu.dctl.flsh_vld1;
reg [9:0] spc3_ld1_unf_cntr;
reg spc3_ld1_unfilled_d;
reg [9:0] spc3_st1_unf_cntr;
reg spc3_st1_unfilled_d;
reg spc3_st1_unfilled;
reg spc3_mbar_vld_d1;
reg spc3_flsh_vld_d1;
reg spc3_lmq1_full_d;
reg [9:0] spc3_lmq_full_cntr1;
reg spc3_lmq_full_capture1;
reg [9:0] spc3_stb_full_cntr1;
reg spc3_stb_full_capture1;
reg [9:0] spc3_mbar_vld_cntr1;
reg spc3_mbar_vld_capture1;
reg [9:0] spc3_flsh_vld_cntr1;
reg spc3_flsh_vld_capture1;
reg spc3_stb_head_hit1;
wire spc3_raw_ack_capture1;
reg [9:0] spc3_stb_ack_cntr1;
reg [9:0] spc3_stb_ced_cntr1;
reg spc3_stb_ced1_d;
reg spc3_stb_ced_capture1;
wire spc3_stb_ced1;
reg spc3_atm1_d;
reg [9:0] spc3_atm_cntr1;
reg spc3_atm_intrpt_capture1;
reg spc3_atm_intrpt_b4capture1;
reg spc3_atm_inv_capture1;
reg [39:0] spc3_stb_wr_addr1;
reg [39:0] spc3_stb_atm_addr1;
reg spc3_atm_lmiss_eq1;
wire [7:0] spc3_stb_state_vld2 = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc3_stb_state_ack2 = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc3_stb_state_ced2 = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc3_stb_state_rst2 = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_state_rst;
wire spc3_stb_ack_vld2 = `TOP_DESIGN.sparc3.lsu.stb_ctl2.ack_vld;
wire spc3_ld2_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_inst_vld_g;
wire spc3_intrpt2_cmplt = `TOP_DESIGN.sparc3.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc3_stb2_full = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_full;
wire spc3_stb2_full_w2 = `TOP_DESIGN.sparc3.lsu.stb_ctl2.stb_full_w2;
wire spc3_lmq2_full = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_pcx_rq_vld;
wire spc3_mbar_vld2 = `TOP_DESIGN.sparc3.lsu.dctl.mbar_vld2;
wire spc3_ld2_unfilled = `TOP_DESIGN.sparc3.lsu.qctl1.ld2_unfilled;
wire spc3_flsh_vld2 = `TOP_DESIGN.sparc3.lsu.dctl.flsh_vld2;
reg [9:0] spc3_ld2_unf_cntr;
reg spc3_ld2_unfilled_d;
reg [9:0] spc3_st2_unf_cntr;
reg spc3_st2_unfilled_d;
reg spc3_st2_unfilled;
reg spc3_mbar_vld_d2;
reg spc3_flsh_vld_d2;
reg spc3_lmq2_full_d;
reg [9:0] spc3_lmq_full_cntr2;
reg spc3_lmq_full_capture2;
reg [9:0] spc3_stb_full_cntr2;
reg spc3_stb_full_capture2;
reg [9:0] spc3_mbar_vld_cntr2;
reg spc3_mbar_vld_capture2;
reg [9:0] spc3_flsh_vld_cntr2;
reg spc3_flsh_vld_capture2;
reg spc3_stb_head_hit2;
wire spc3_raw_ack_capture2;
reg [9:0] spc3_stb_ack_cntr2;
reg [9:0] spc3_stb_ced_cntr2;
reg spc3_stb_ced2_d;
reg spc3_stb_ced_capture2;
wire spc3_stb_ced2;
reg spc3_atm2_d;
reg [9:0] spc3_atm_cntr2;
reg spc3_atm_intrpt_capture2;
reg spc3_atm_intrpt_b4capture2;
reg spc3_atm_inv_capture2;
reg [39:0] spc3_stb_wr_addr2;
reg [39:0] spc3_stb_atm_addr2;
reg spc3_atm_lmiss_eq2;
wire [7:0] spc3_stb_state_vld3 = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc3_stb_state_ack3 = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc3_stb_state_ced3 = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc3_stb_state_rst3 = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_state_rst;
wire spc3_stb_ack_vld3 = `TOP_DESIGN.sparc3.lsu.stb_ctl3.ack_vld;
wire spc3_ld3_inst_vld_g = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_inst_vld_g;
wire spc3_intrpt3_cmplt = `TOP_DESIGN.sparc3.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc3_stb3_full = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_full;
wire spc3_stb3_full_w2 = `TOP_DESIGN.sparc3.lsu.stb_ctl3.stb_full_w2;
wire spc3_lmq3_full = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_pcx_rq_vld;
wire spc3_mbar_vld3 = `TOP_DESIGN.sparc3.lsu.dctl.mbar_vld3;
wire spc3_ld3_unfilled = `TOP_DESIGN.sparc3.lsu.qctl1.ld3_unfilled;
wire spc3_flsh_vld3 = `TOP_DESIGN.sparc3.lsu.dctl.flsh_vld3;
reg [9:0] spc3_ld3_unf_cntr;
reg spc3_ld3_unfilled_d;
reg [9:0] spc3_st3_unf_cntr;
reg spc3_st3_unfilled_d;
reg spc3_st3_unfilled;
reg spc3_mbar_vld_d3;
reg spc3_flsh_vld_d3;
reg spc3_lmq3_full_d;
reg [9:0] spc3_lmq_full_cntr3;
reg spc3_lmq_full_capture3;
reg [9:0] spc3_stb_full_cntr3;
reg spc3_stb_full_capture3;
reg [9:0] spc3_mbar_vld_cntr3;
reg spc3_mbar_vld_capture3;
reg [9:0] spc3_flsh_vld_cntr3;
reg spc3_flsh_vld_capture3;
reg spc3_stb_head_hit3;
wire spc3_raw_ack_capture3;
reg [9:0] spc3_stb_ack_cntr3;
reg [9:0] spc3_stb_ced_cntr3;
reg spc3_stb_ced3_d;
reg spc3_stb_ced_capture3;
wire spc3_stb_ced3;
reg spc3_atm3_d;
reg [9:0] spc3_atm_cntr3;
reg spc3_atm_intrpt_capture3;
reg spc3_atm_intrpt_b4capture3;
reg spc3_atm_inv_capture3;
reg [39:0] spc3_stb_wr_addr3;
reg [39:0] spc3_stb_atm_addr3;
reg spc3_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc3_fpick = {spc3_mpick,spc3_spick,spc3_lpick,spc3_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc3_msquash,spc3_apick,spc3_fpick})
9'b000000000 : spc3_fpicko = 1'b0;
9'b0xxx1xxx1 : spc3_fpicko = 1'b0;
9'b1xxxxxxxx : spc3_fpicko = 1'b0;
9'b0xxx0xxx0 : spc3_fpicko = 1'b0;
default:
begin
spc3_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon3 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc3_exu_und = {spc3_l2,
spc3_unc,
spc3_fpld,
spc3_fpldst,
spc3_unflush,
spc3_ldw,
spc3_byp,
spc3_flsh,
spc3_chm,
spc3_ldxa,
spc3_ato,
spc3_pref,
spc3_chit,
spc3_dcp,
spc3_dtp,
spc3_mpc,
spc3_mpu};
always @(spc3_exu_und)
begin
case (spc3_exu_und)
17'h00000 : spc3_exu = 5'h00;
17'h00001 : spc3_exu = 5'h01;
17'h00002 : spc3_exu = 5'h02;
17'h00004 : spc3_exu = 5'h03;
17'h00008 : spc3_exu = 5'h04;
17'h00010 : spc3_exu = 5'h05;
17'h00020 : spc3_exu = 5'h06;
17'h00040 : spc3_exu = 5'h07;
17'h00080 : spc3_exu = 5'h08;
17'h00100 : spc3_exu = 5'h09;
17'h00200 : spc3_exu = 5'h0a;
17'h00400 : spc3_exu = 5'h0b;
17'h00800 : spc3_exu = 5'h0c;
17'h01000 : spc3_exu = 5'h0d;
17'h02000 : spc3_exu = 5'h0e;
17'h04000 : spc3_exu = 5'h0f;
17'h08000 : spc3_exu = 5'h10;
17'h10000 : spc3_exu = 5'h11;
default: spc3_exu = 5'h12;
endcase
end
//excp
assign spc3_exp_und = {spc3_exp_wtchpt_trp_g,
spc3_exp_misalign_addr_ldst_atm_m,
spc3_exp_priv_violtn_g,
spc3_exp_daccess_excptn_g,
spc3_exp_daccess_prot_g,
spc3_exp_priv_action_g,
spc3_exp_spec_access_epage_g,
spc3_exp_uncache_atomic_g,
spc3_exp_illegal_asi_action_g,
spc3_exp_flt_ld_nfo_pg_g,
spc3_exp_asi_rd_unc,
spc3_exp_tlb_data_ce,
spc3_exp_tlb_data_ue,
spc3_exp_tlb_tag_ue,
spc3_exp_unc,
spc3_exp_corr};
always @(spc3_exp_und)
begin
case (spc3_exp_und)
16'h0000 : spc3_exp = 5'h00;
16'h0001 : spc3_exp = 5'h01;
16'h0002 : spc3_exp = 5'h02;
16'h0004 : spc3_exp = 5'h03;
16'h0008 : spc3_exp = 5'h04;
16'h0010 : spc3_exp = 5'h05;
16'h0020 : spc3_exp = 5'h06;
16'h0040 : spc3_exp = 5'h07;
16'h0080 : spc3_exp = 5'h08;
16'h0100 : spc3_exp = 5'h09;
16'h0200 : spc3_exp = 5'h0a;
16'h0400 : spc3_exp = 5'h0b;
16'h0800 : spc3_exp = 5'h0c;
16'h1000 : spc3_exp = 5'h0d;
16'h2000 : spc3_exp = 5'h0e;
16'h4000 : spc3_exp = 5'h0f;
16'h8000 : spc3_exp = 5'h10;
default: spc3_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc3_dctl_stxa_cmplt0 = ((spc3_dctl_stxa_internal_d2 & spc3_dctl_thread0_w3) |
spc3_dctl_stxa_stall_wr_cmplt0_d1);
assign spc3_dctl_l2fill_cmplt0 = (((spc3_dctl_lsu_l2fill_vld & ~spc3_dctl_atomic_ld_squash_e &
~spc3_dctl_lsu_ignore_fill)) & ~spc3_dctl_l2fill_fpld_e &
~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread0);
assign spc3_dctl_fillerr0 = spc3_dctl_l2_corr_error_e & spc3_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc3_dctl_atm_cmplt0 = (spc3_dctl_lsu_atm_st_cmplt_e & ~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread0);
assign spc3_dctl_ldst_cond_cmplt0 = { spc3_dctl_stxa_cmplt0, spc3_dctl_l2fill_cmplt0,
spc3_dctl_atomic_ld_squash_e, spc3_dctl_intld_byp_cmplt[0],
spc3_dctl_bsync0_reset, spc3_dctl_lsu_intrpt_cmplt[0]
};
assign spc3_cmplt0 = { spc3_dctl_ldxa_illgl_va_cmplt_d1, spc3_dctl_pref_tlbmiss_cmplt_d2,
spc3_dctl_lsu_pcx_pref_issue, spc3_dctl_diag_wr_cmplt0, spc3_dctl_l2fill_fpld_e};
always @(spc3_cmplt0 or spc3_dctl_ldst_cond_cmplt0)
begin
case ({spc3_dctl_fillerr0,spc3_dctl_ldst_cond_cmplt0,spc3_cmplt0})
12'h000 : spc3_ldstcond_cmplt0 = 4'h0;
12'h001 : spc3_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc3_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc3_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc3_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc3_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc3_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc3_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc3_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc3_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc3_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc3_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc3_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc3_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc3_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc3_dctl_stxa_cmplt1 = ((spc3_dctl_stxa_internal_d2 & spc3_dctl_thread1_w3) |
spc3_dctl_stxa_stall_wr_cmplt1_d1);
assign spc3_dctl_l2fill_cmplt1 = (((spc3_dctl_lsu_l2fill_vld & ~spc3_dctl_atomic_ld_squash_e &
~spc3_dctl_lsu_ignore_fill)) & ~spc3_dctl_l2fill_fpld_e &
~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread1);
assign spc3_dctl_fillerr1 = spc3_dctl_l2_corr_error_e & spc3_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc3_dctl_atm_cmplt1 = (spc3_dctl_lsu_atm_st_cmplt_e & ~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread1);
assign spc3_dctl_ldst_cond_cmplt1 = { spc3_dctl_stxa_cmplt1, spc3_dctl_l2fill_cmplt1,
spc3_dctl_atomic_ld_squash_e, spc3_dctl_intld_byp_cmplt[1],
spc3_dctl_bsync1_reset, spc3_dctl_lsu_intrpt_cmplt[1]
};
assign spc3_cmplt1 = { spc3_dctl_ldxa_illgl_va_cmplt_d1, spc3_dctl_pref_tlbmiss_cmplt_d2,
spc3_dctl_lsu_pcx_pref_issue, spc3_dctl_diag_wr_cmplt1, spc3_dctl_l2fill_fpld_e};
always @(spc3_cmplt1 or spc3_dctl_ldst_cond_cmplt1)
begin
case ({spc3_dctl_fillerr1,spc3_dctl_ldst_cond_cmplt1,spc3_cmplt1})
12'h000 : spc3_ldstcond_cmplt1 = 4'h0;
12'h001 : spc3_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc3_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc3_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc3_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc3_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc3_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc3_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc3_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc3_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc3_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc3_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc3_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc3_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc3_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc3_dctl_stxa_cmplt2 = ((spc3_dctl_stxa_internal_d2 & spc3_dctl_thread2_w3) |
spc3_dctl_stxa_stall_wr_cmplt2_d1);
assign spc3_dctl_l2fill_cmplt2 = (((spc3_dctl_lsu_l2fill_vld & ~spc3_dctl_atomic_ld_squash_e &
~spc3_dctl_lsu_ignore_fill)) & ~spc3_dctl_l2fill_fpld_e &
~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread2);
assign spc3_dctl_fillerr2 = spc3_dctl_l2_corr_error_e & spc3_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc3_dctl_atm_cmplt2 = (spc3_dctl_lsu_atm_st_cmplt_e & ~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread2);
assign spc3_dctl_ldst_cond_cmplt2 = { spc3_dctl_stxa_cmplt2, spc3_dctl_l2fill_cmplt2,
spc3_dctl_atomic_ld_squash_e, spc3_dctl_intld_byp_cmplt[2],
spc3_dctl_bsync2_reset, spc3_dctl_lsu_intrpt_cmplt[2]
};
assign spc3_cmplt2 = { spc3_dctl_ldxa_illgl_va_cmplt_d1, spc3_dctl_pref_tlbmiss_cmplt_d2,
spc3_dctl_lsu_pcx_pref_issue, spc3_dctl_diag_wr_cmplt2, spc3_dctl_l2fill_fpld_e};
always @(spc3_cmplt2 or spc3_dctl_ldst_cond_cmplt2)
begin
case ({spc3_dctl_fillerr2,spc3_dctl_ldst_cond_cmplt2,spc3_cmplt2})
12'h000 : spc3_ldstcond_cmplt2 = 4'h0;
12'h001 : spc3_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc3_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc3_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc3_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc3_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc3_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc3_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc3_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc3_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc3_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc3_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc3_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc3_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc3_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc3_dctl_stxa_cmplt3 = ((spc3_dctl_stxa_internal_d2 & spc3_dctl_thread3_w3) |
spc3_dctl_stxa_stall_wr_cmplt3_d1);
assign spc3_dctl_l2fill_cmplt3 = (((spc3_dctl_lsu_l2fill_vld & ~spc3_dctl_atomic_ld_squash_e &
~spc3_dctl_lsu_ignore_fill)) & ~spc3_dctl_l2fill_fpld_e &
~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread3);
assign spc3_dctl_fillerr3 = spc3_dctl_l2_corr_error_e & spc3_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc3_dctl_atm_cmplt3 = (spc3_dctl_lsu_atm_st_cmplt_e & ~spc3_dctl_fill_err_trap_e & spc3_dctl_dfill_thread3);
assign spc3_dctl_ldst_cond_cmplt3 = { spc3_dctl_stxa_cmplt3, spc3_dctl_l2fill_cmplt3,
spc3_dctl_atomic_ld_squash_e, spc3_dctl_intld_byp_cmplt[3],
spc3_dctl_bsync3_reset, spc3_dctl_lsu_intrpt_cmplt[3]
};
assign spc3_cmplt3 = { spc3_dctl_ldxa_illgl_va_cmplt_d1, spc3_dctl_pref_tlbmiss_cmplt_d2,
spc3_dctl_lsu_pcx_pref_issue, spc3_dctl_diag_wr_cmplt3, spc3_dctl_l2fill_fpld_e};
always @(spc3_cmplt3 or spc3_dctl_ldst_cond_cmplt3)
begin
case ({spc3_dctl_fillerr3,spc3_dctl_ldst_cond_cmplt3,spc3_cmplt3})
12'h000 : spc3_ldstcond_cmplt3 = 4'h0;
12'h001 : spc3_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc3_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc3_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc3_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc3_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc3_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc3_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc3_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc3_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc3_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc3_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc3_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc3_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc3_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc3_ldstcond_cmplt0 or spc3_ldstcond_cmplt1 or spc3_ldstcond_cmplt2
or spc3_ldstcond_cmplt3 or spc3_dctl_lsu_ifu_ldst_cmplt
or spc3_dctl_late_cmplt0 or spc3_dctl_late_cmplt1 or spc3_dctl_late_cmplt2 or spc3_dctl_late_cmplt3)
begin
case (spc3_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc3_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc3_ldstcond_cmplt_d = spc3_dctl_late_cmplt0 ? spc3_ldstcond_cmplt0_d : spc3_ldstcond_cmplt0;
4'b0010 : spc3_ldstcond_cmplt_d = spc3_dctl_late_cmplt1 ? spc3_ldstcond_cmplt1_d : spc3_ldstcond_cmplt1;
4'b0100 : spc3_ldstcond_cmplt_d = spc3_dctl_late_cmplt2 ? spc3_ldstcond_cmplt2_d : spc3_ldstcond_cmplt2;
4'b1000 : spc3_ldstcond_cmplt_d = spc3_dctl_late_cmplt3 ? spc3_ldstcond_cmplt3_d : spc3_ldstcond_cmplt3;
4'b0011 : spc3_ldstcond_cmplt_d = 4'he;
4'b0101 : spc3_ldstcond_cmplt_d = 4'he;
4'b1001 : spc3_ldstcond_cmplt_d = 4'he;
4'b0110 : spc3_ldstcond_cmplt_d = 4'he;
4'b1010 : spc3_ldstcond_cmplt_d = 4'he;
4'b1100 : spc3_ldstcond_cmplt_d = 4'he;
default:
begin
spc3_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc3_st_ooo_ret = { spc3_st0_lt_1, spc3_st0_lt_2, spc3_st0_lt_3,
spc3_st1_lt_0, spc3_st1_lt_2, spc3_st1_lt_3,
spc3_st2_lt_0, spc3_st2_lt_1, spc3_st2_lt_3,
spc3_st3_lt_0, spc3_st3_lt_1, spc3_st3_lt_2};
always @(posedge clk)
begin
if(~spc3_st0_unfilled || ~rst_l)
spc3_st0_unfilled_d <= 1'b0;
else
spc3_st0_unfilled_d <= spc3_st0_unfilled;
if(~rst_l)
spc3_ldstcond_cmplt0_d <= 4'h0;
else
spc3_ldstcond_cmplt0_d <= spc3_ldstcond_cmplt0;
if(~spc3_ld0_pkt_vld_unmasked || ~rst_l)
spc3_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc3_ld0_pkt_vld_unmasked_d <= spc3_ld0_pkt_vld_unmasked;
if(~rst_l)
spc3_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc3_qctl1_ld_sec_hit_thrd0 && spc3_qctl1_ld0_inst_vld_g)
spc3_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc3_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc3_st1_unfilled || ~rst_l)
spc3_st1_unfilled_d <= 1'b0;
else
spc3_st1_unfilled_d <= spc3_st1_unfilled;
if(~rst_l)
spc3_ldstcond_cmplt1_d <= 4'h0;
else
spc3_ldstcond_cmplt1_d <= spc3_ldstcond_cmplt1;
if(~spc3_ld1_pkt_vld_unmasked || ~rst_l)
spc3_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc3_ld1_pkt_vld_unmasked_d <= spc3_ld1_pkt_vld_unmasked;
if(~rst_l)
spc3_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc3_qctl1_ld_sec_hit_thrd1 && spc3_qctl1_ld1_inst_vld_g)
spc3_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc3_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc3_st2_unfilled || ~rst_l)
spc3_st2_unfilled_d <= 1'b0;
else
spc3_st2_unfilled_d <= spc3_st2_unfilled;
if(~rst_l)
spc3_ldstcond_cmplt2_d <= 4'h0;
else
spc3_ldstcond_cmplt2_d <= spc3_ldstcond_cmplt2;
if(~spc3_ld2_pkt_vld_unmasked || ~rst_l)
spc3_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc3_ld2_pkt_vld_unmasked_d <= spc3_ld2_pkt_vld_unmasked;
if(~rst_l)
spc3_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc3_qctl1_ld_sec_hit_thrd2 && spc3_qctl1_ld2_inst_vld_g)
spc3_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc3_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc3_st3_unfilled || ~rst_l)
spc3_st3_unfilled_d <= 1'b0;
else
spc3_st3_unfilled_d <= spc3_st3_unfilled;
if(~rst_l)
spc3_ldstcond_cmplt3_d <= 4'h0;
else
spc3_ldstcond_cmplt3_d <= spc3_ldstcond_cmplt3;
if(~spc3_ld3_pkt_vld_unmasked || ~rst_l)
spc3_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc3_ld3_pkt_vld_unmasked_d <= spc3_ld3_pkt_vld_unmasked;
if(~rst_l)
spc3_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc3_qctl1_ld_sec_hit_thrd3 && spc3_qctl1_ld3_inst_vld_g)
spc3_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc3_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc3_stb_state_ced0) && (|spc3_stb_state_rst0)) || ~rst_l)
spc3_st0_unfilled <= 1'b0;
else if( ((|spc3_stb_state_ced0) && ~(|spc3_stb_state_rst0)))
spc3_st0_unfilled <= 1'b1;
else
spc3_st0_unfilled <= spc3_st0_unfilled;
if( ((|spc3_stb_state_ced1) && (|spc3_stb_state_rst1)) || ~rst_l)
spc3_st1_unfilled <= 1'b0;
else if( ((|spc3_stb_state_ced1) && ~(|spc3_stb_state_rst1)))
spc3_st1_unfilled <= 1'b1;
else
spc3_st1_unfilled <= spc3_st1_unfilled;
if( ((|spc3_stb_state_ced2) && (|spc3_stb_state_rst2)) || ~rst_l)
spc3_st2_unfilled <= 1'b0;
else if( ((|spc3_stb_state_ced2) && ~(|spc3_stb_state_rst2)))
spc3_st2_unfilled <= 1'b1;
else
spc3_st2_unfilled <= spc3_st2_unfilled;
if( ((|spc3_stb_state_ced3) && (|spc3_stb_state_rst3)) || ~rst_l)
spc3_st3_unfilled <= 1'b0;
else if( ((|spc3_stb_state_ced3) && ~(|spc3_stb_state_rst3)))
spc3_st3_unfilled <= 1'b1;
else
spc3_st3_unfilled <= spc3_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc3_st0_unfilled && spc3_st0_unfilled_d)|| ~rst_l)
begin
spc3_st0_unf_cntr <= 9'h000;
end
else if(spc3_st0_unfilled)
begin
spc3_st0_unf_cntr <= spc3_st0_unf_cntr + 1;
end
else
begin
spc3_st0_unf_cntr <= spc3_st0_unf_cntr;
end
if((~spc3_st1_unfilled && spc3_st1_unfilled_d)|| ~rst_l)
begin
spc3_st1_unf_cntr <= 9'h000;
end
else if(spc3_st1_unfilled)
begin
spc3_st1_unf_cntr <= spc3_st1_unf_cntr + 1;
end
else
begin
spc3_st1_unf_cntr <= spc3_st1_unf_cntr;
end
if((~spc3_st2_unfilled && spc3_st2_unfilled_d)|| ~rst_l)
begin
spc3_st2_unf_cntr <= 9'h000;
end
else if(spc3_st2_unfilled)
begin
spc3_st2_unf_cntr <= spc3_st2_unf_cntr + 1;
end
else
begin
spc3_st2_unf_cntr <= spc3_st2_unf_cntr;
end
if((~spc3_st3_unfilled && spc3_st3_unfilled_d)|| ~rst_l)
begin
spc3_st3_unf_cntr <= 9'h000;
end
else if(spc3_st3_unfilled)
begin
spc3_st3_unf_cntr <= spc3_st3_unf_cntr + 1;
end
else
begin
spc3_st3_unf_cntr <= spc3_st3_unf_cntr;
end
end
always @(spc3_st0_unfilled or spc3_st1_unfilled or spc3_st2_unfilled or spc3_st3_unfilled
or spc3_st0_unfilled_d or spc3_st1_unfilled_d or spc3_st2_unfilled_d or spc3_st3_unfilled_d)
begin
if(~spc3_st0_unfilled && spc3_st0_unfilled_d && spc3_st1_unfilled)
spc3_st0_lt_1 <= (spc3_st1_unf_cntr > spc3_st0_unf_cntr);
else
spc3_st0_lt_1 <= 1'b0;
if(~spc3_st0_unfilled && spc3_st0_unfilled_d && spc3_st2_unfilled)
spc3_st0_lt_2 <= (spc3_st2_unf_cntr > spc3_st0_unf_cntr);
else
spc3_st0_lt_2 <= 1'b0;
if(~spc3_st0_unfilled && spc3_st0_unfilled_d && spc3_st3_unfilled)
spc3_st0_lt_3 <= (spc3_st3_unf_cntr > spc3_st0_unf_cntr);
else
spc3_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc3_st1_unfilled && spc3_st1_unfilled_d && spc3_st0_unfilled)
spc3_st1_lt_0 <= (spc3_st0_unf_cntr > spc3_st1_unf_cntr);
else
spc3_st1_lt_0 <= 1'b0;
if(~spc3_st1_unfilled && spc3_st1_unfilled_d && spc3_st2_unfilled)
spc3_st1_lt_2 <= (spc3_st2_unf_cntr > spc3_st1_unf_cntr);
else
spc3_st1_lt_2 <= 1'b0;
if(~spc3_st1_unfilled && spc3_st1_unfilled_d && spc3_st3_unfilled)
spc3_st1_lt_3 <= (spc3_st3_unf_cntr > spc3_st1_unf_cntr);
else
spc3_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc3_st2_unfilled && spc3_st2_unfilled_d && spc3_st0_unfilled)
spc3_st2_lt_0 <= (spc3_st0_unf_cntr > spc3_st2_unf_cntr);
else
spc3_st2_lt_0 <= 1'b0;
if(~spc3_st2_unfilled && spc3_st2_unfilled_d && spc3_st1_unfilled)
spc3_st2_lt_1 <= (spc3_st1_unf_cntr > spc3_st2_unf_cntr);
else
spc3_st2_lt_1 <= 1'b0;
if(~spc3_st2_unfilled && spc3_st2_unfilled_d && spc3_st3_unfilled)
spc3_st2_lt_3 <= (spc3_st3_unf_cntr > spc3_st2_unf_cntr);
else
spc3_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc3_st3_unfilled && spc3_st3_unfilled_d && spc3_st0_unfilled)
spc3_st3_lt_0 <= (spc3_st0_unf_cntr > spc3_st3_unf_cntr);
else
spc3_st3_lt_0 <= 1'b0;
if(~spc3_st3_unfilled && spc3_st3_unfilled_d && spc3_st1_unfilled)
spc3_st3_lt_1 <= (spc3_st1_unf_cntr > spc3_st3_unf_cntr);
else
spc3_st3_lt_1 <= 1'b0;
if(~spc3_st3_unfilled && spc3_st3_unfilled_d && spc3_st2_unfilled)
spc3_st3_lt_2 <= (spc3_st2_unf_cntr > spc3_st3_unf_cntr);
else
spc3_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc3_ld_ooo_ret = { spc3_ld0_lt_1, spc3_ld0_lt_2, spc3_ld0_lt_3,
spc3_ld1_lt_0, spc3_ld1_lt_2, spc3_ld1_lt_3,
spc3_ld2_lt_0, spc3_ld2_lt_1, spc3_ld2_lt_3,
spc3_ld3_lt_0, spc3_ld3_lt_1, spc3_ld3_lt_2};
always @(posedge clk)
begin
if((~spc3_ld0_unfilled && spc3_ld0_unfilled_d)|| ~rst_l)
begin
spc3_ld0_unf_cntr <= 9'h000;
end
else if(spc3_ld0_unfilled)
begin
spc3_ld0_unf_cntr <= spc3_ld0_unf_cntr + 1;
end
else
begin
spc3_ld0_unf_cntr <= spc3_ld0_unf_cntr;
end
if((~spc3_ld1_unfilled && spc3_ld1_unfilled_d)|| ~rst_l)
begin
spc3_ld1_unf_cntr <= 9'h000;
end
else if(spc3_ld1_unfilled)
begin
spc3_ld1_unf_cntr <= spc3_ld1_unf_cntr + 1;
end
else
begin
spc3_ld1_unf_cntr <= spc3_ld1_unf_cntr;
end
if((~spc3_ld2_unfilled && spc3_ld2_unfilled_d)|| ~rst_l)
begin
spc3_ld2_unf_cntr <= 9'h000;
end
else if(spc3_ld2_unfilled)
begin
spc3_ld2_unf_cntr <= spc3_ld2_unf_cntr + 1;
end
else
begin
spc3_ld2_unf_cntr <= spc3_ld2_unf_cntr;
end
if((~spc3_ld3_unfilled && spc3_ld3_unfilled_d)|| ~rst_l)
begin
spc3_ld3_unf_cntr <= 9'h000;
end
else if(spc3_ld3_unfilled)
begin
spc3_ld3_unf_cntr <= spc3_ld3_unf_cntr + 1;
end
else
begin
spc3_ld3_unf_cntr <= spc3_ld3_unf_cntr;
end
end
always @(spc3_ld0_unfilled or spc3_ld1_unfilled or spc3_ld2_unfilled or spc3_ld3_unfilled
or spc3_ld0_unfilled_d or spc3_ld1_unfilled_d or spc3_ld2_unfilled_d or spc3_ld3_unfilled_d)
begin
if(~spc3_ld0_unfilled && spc3_ld0_unfilled_d && spc3_ld1_unfilled)
spc3_ld0_lt_1 <= (spc3_ld1_unf_cntr > spc3_ld0_unf_cntr);
else
spc3_ld0_lt_1 <= 1'b0;
if(~spc3_ld0_unfilled && spc3_ld0_unfilled_d && spc3_ld2_unfilled)
spc3_ld0_lt_2 <= (spc3_ld2_unf_cntr > spc3_ld0_unf_cntr);
else
spc3_ld0_lt_2 <= 1'b0;
if(~spc3_ld0_unfilled && spc3_ld0_unfilled_d && spc3_ld3_unfilled)
spc3_ld0_lt_3 <= (spc3_ld3_unf_cntr > spc3_ld0_unf_cntr);
else
spc3_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc3_ld1_unfilled && spc3_ld1_unfilled_d && spc3_ld0_unfilled)
spc3_ld1_lt_0 <= (spc3_ld0_unf_cntr > spc3_ld1_unf_cntr);
else
spc3_ld1_lt_0 <= 1'b0;
if(~spc3_ld1_unfilled && spc3_ld1_unfilled_d && spc3_ld2_unfilled)
spc3_ld1_lt_2 <= (spc3_ld2_unf_cntr > spc3_ld1_unf_cntr);
else
spc3_ld1_lt_2 <= 1'b0;
if(~spc3_ld1_unfilled && spc3_ld1_unfilled_d && spc3_ld3_unfilled)
spc3_ld1_lt_3 <= (spc3_ld3_unf_cntr > spc3_ld1_unf_cntr);
else
spc3_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc3_ld2_unfilled && spc3_ld2_unfilled_d && spc3_ld0_unfilled)
spc3_ld2_lt_0 <= (spc3_ld0_unf_cntr > spc3_ld2_unf_cntr);
else
spc3_ld2_lt_0 <= 1'b0;
if(~spc3_ld2_unfilled && spc3_ld2_unfilled_d && spc3_ld1_unfilled)
spc3_ld2_lt_1 <= (spc3_ld1_unf_cntr > spc3_ld2_unf_cntr);
else
spc3_ld2_lt_1 <= 1'b0;
if(~spc3_ld2_unfilled && spc3_ld2_unfilled_d && spc3_ld3_unfilled)
spc3_ld2_lt_3 <= (spc3_ld3_unf_cntr > spc3_ld2_unf_cntr);
else
spc3_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc3_ld3_unfilled && spc3_ld3_unfilled_d && spc3_ld0_unfilled)
spc3_ld3_lt_0 <= (spc3_ld0_unf_cntr > spc3_ld3_unf_cntr);
else
spc3_ld3_lt_0 <= 1'b0;
if(~spc3_ld3_unfilled && spc3_ld3_unfilled_d && spc3_ld1_unfilled)
spc3_ld3_lt_1 <= (spc3_ld1_unf_cntr > spc3_ld3_unf_cntr);
else
spc3_ld3_lt_1 <= 1'b0;
if(~spc3_ld3_unfilled && spc3_ld3_unfilled_d && spc3_ld2_unfilled)
spc3_ld3_lt_2 <= (spc3_ld2_unf_cntr > spc3_ld3_unf_cntr);
else
spc3_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc3_dctl_bld_hit =
((|spc3_dctl_lsu_way_hit[3:0]) & spc3_dctl_dcache_enable_g &
~spc3_dctl_ldxa_internal & ~spc3_dctl_dcache_rd_parity_error & ~spc3_dctl_dtag_perror_g &
~spc3_dctl_endian_mispred_g &
~spc3_dctl_atomic_g & ~spc3_dctl_ncache_asild_rq_g) & ~spc3_dctl_tte_data_perror_unc &
spc3_dctl_ld_inst_vld_g & spc3_qctl1_bld_g ;
assign spc3_dctl_bld_stb_hit = spc3_dctl_bld_hit & spc3_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc3_bld0_full_d <= 2'b00;
spc3_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc3_bld0_full_d <= spc3_qctl1_bld_cnt;
spc3_ld0_unfilled_d <= spc3_ld0_unfilled;
end
if(~rst_l)
begin
spc3_bld1_full_d <= 2'b00;
spc3_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc3_bld1_full_d <= spc3_qctl1_bld_cnt;
spc3_ld1_unfilled_d <= spc3_ld1_unfilled;
end
if(~rst_l)
begin
spc3_bld2_full_d <= 2'b00;
spc3_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc3_bld2_full_d <= spc3_qctl1_bld_cnt;
spc3_ld2_unfilled_d <= spc3_ld2_unfilled;
end
if(~rst_l)
begin
spc3_bld3_full_d <= 2'b00;
spc3_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc3_bld3_full_d <= spc3_qctl1_bld_cnt;
spc3_ld3_unfilled_d <= spc3_ld3_unfilled;
end
end
always @(spc3_bld0_full_d or spc3_qctl1_bld_cnt)
begin
if( (spc3_bld0_full_d != spc3_qctl1_bld_cnt) && (spc3_bld0_full_d == 2'd0))
spc3_bld0_full_capture <= 1'b1;
else
spc3_bld0_full_capture <= 1'b0;
end
always @(spc3_bld1_full_d or spc3_qctl1_bld_cnt)
begin
if( (spc3_bld1_full_d != spc3_qctl1_bld_cnt) && (spc3_bld1_full_d == 2'd1))
spc3_bld1_full_capture <= 1'b1;
else
spc3_bld1_full_capture <= 1'b0;
end
always @(spc3_bld2_full_d or spc3_qctl1_bld_cnt)
begin
if( (spc3_bld2_full_d != spc3_qctl1_bld_cnt) && (spc3_bld2_full_d == 2'd2))
spc3_bld2_full_capture <= 1'b1;
else
spc3_bld2_full_capture <= 1'b0;
end
always @(spc3_bld3_full_d or spc3_qctl1_bld_cnt)
begin
if( (spc3_bld3_full_d != spc3_qctl1_bld_cnt) && (spc3_bld3_full_d == 2'd3))
spc3_bld3_full_capture <= 1'b1;
else
spc3_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc3_qctl1_bld_cnt != 2'b00) && (spc3_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc3_bld0_full_cntr <= 9'h000;
end
else if(spc3_qctl1_bld_g && (spc3_qctl1_bld_cnt == 2'b00))
begin
spc3_bld0_full_cntr <= spc3_bld0_full_cntr + 1;
end
else if( (spc3_qctl1_bld_cnt == 2'b00) && (spc3_bld0_full_cntr != 9'h000))
begin
spc3_bld0_full_cntr <= spc3_bld0_full_cntr + 1;
end
else
begin
spc3_bld0_full_cntr <= spc3_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc3_qctl1_bld_cnt != 2'b01) && (spc3_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc3_bld1_full_cntr <= 9'h000;
end
else if(spc3_qctl1_bld_cnt == 2'b01)
begin
spc3_bld1_full_cntr <= spc3_bld1_full_cntr + 1;
end
else if( (spc3_qctl1_bld_cnt == 2'b01) && (spc3_bld1_full_cntr != 9'h000))
begin
spc3_bld1_full_cntr <= spc3_bld1_full_cntr + 1;
end
else
begin
spc3_bld1_full_cntr <= spc3_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc3_qctl1_bld_cnt != 2'b10) && (spc3_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc3_bld2_full_cntr <= 9'h000;
end
else if(spc3_qctl1_bld_cnt == 2'b10)
begin
spc3_bld2_full_cntr <= spc3_bld2_full_cntr + 1;
end
else if( (spc3_qctl1_bld_cnt == 2'b10) && (spc3_bld2_full_cntr != 9'h000))
begin
spc3_bld2_full_cntr <= spc3_bld2_full_cntr + 1;
end
else
begin
spc3_bld2_full_cntr <= spc3_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc3_qctl1_bld_cnt != 2'b11) && (spc3_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc3_bld3_full_cntr <= 9'h000;
end
else if(spc3_qctl1_bld_cnt == 2'b11)
begin
spc3_bld3_full_cntr <= spc3_bld3_full_cntr + 1;
end
else if( (spc3_qctl1_bld_cnt == 2'b11) && (spc3_bld3_full_cntr != 9'h000))
begin
spc3_bld3_full_cntr <= spc3_bld3_full_cntr + 1;
end
else
begin
spc3_bld3_full_cntr <= spc3_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc3_stb_state_vld0) && ~spc3_atomic_g) || ~rst_l)
begin
spc3_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc3_atomic_g && (spc3_atm_type0 != 8'h00) && spc3_wptr_vld)
begin
spc3_stb_atm_addr0 <= {spc3_wdata_ramc[44:9],spc3_wdata_ramd[67:64]};
end
else
begin
spc3_stb_atm_addr0 <= spc3_stb_atm_addr0;
end
if( ( ~(|spc3_stb_state_vld1) && ~spc3_atomic_g) || ~rst_l)
begin
spc3_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc3_atomic_g && (spc3_atm_type1 != 8'h00) && spc3_wptr_vld)
begin
spc3_stb_atm_addr1 <= {spc3_wdata_ramc[44:9],spc3_wdata_ramd[67:64]};
end
else
begin
spc3_stb_atm_addr1 <= spc3_stb_atm_addr1;
end
if( ( ~(|spc3_stb_state_vld2) && ~spc3_atomic_g) || ~rst_l)
begin
spc3_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc3_atomic_g && (spc3_atm_type2 != 8'h00) && spc3_wptr_vld)
begin
spc3_stb_atm_addr2 <= {spc3_wdata_ramc[44:9],spc3_wdata_ramd[67:64]};
end
else
begin
spc3_stb_atm_addr2 <= spc3_stb_atm_addr2;
end
if( ( ~(|spc3_stb_state_vld3) && ~spc3_atomic_g) || ~rst_l)
begin
spc3_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc3_atomic_g && (spc3_atm_type3 != 8'h00) && spc3_wptr_vld)
begin
spc3_stb_atm_addr3 <= {spc3_wdata_ramc[44:9],spc3_wdata_ramd[67:64]};
end
else
begin
spc3_stb_atm_addr3 <= spc3_stb_atm_addr3;
end
end
assign spc3_dfq_full = (spc3_dfq_vld_entries >= 3'd4);
assign spc3_dfq_full1 = (spc3_dfq_vld_entries >= (3'd4 + 1));
always @(spc3_dfq_full_d1 or spc3_dfq_full1)
begin
if (spc3_dfq_full_d1 && ~spc3_dfq_full1)
spc3_dfq_full_capture1 <= 1'b1;
else
spc3_dfq_full_capture1 <= 1'b0;
end
assign spc3_dfq_full2 = (spc3_dfq_vld_entries >= (3'd4 + 2));
always @(spc3_dfq_full_d2 or spc3_dfq_full2)
begin
if (spc3_dfq_full_d2 && ~spc3_dfq_full2)
spc3_dfq_full_capture2 <= 1'b1;
else
spc3_dfq_full_capture2 <= 1'b0;
end
assign spc3_dfq_full3 = (spc3_dfq_vld_entries >= (3'd4 + 3));
always @(spc3_dfq_full_d3 or spc3_dfq_full3)
begin
if (spc3_dfq_full_d3 && ~spc3_dfq_full3)
spc3_dfq_full_capture3 <= 1'b1;
else
spc3_dfq_full_capture3 <= 1'b0;
end
assign spc3_dfq_full4 = (spc3_dfq_vld_entries >= (3'd4 + 4));
always @(spc3_dfq_full_d4 or spc3_dfq_full4)
begin
if (spc3_dfq_full_d4 && ~spc3_dfq_full4)
spc3_dfq_full_capture4 <= 1'b1;
else
spc3_dfq_full_capture4 <= 1'b0;
end
assign spc3_dfq_full5 = (spc3_dfq_vld_entries >= (3'd4 + 5));
always @(spc3_dfq_full_d5 or spc3_dfq_full5)
begin
if (spc3_dfq_full_d5 && ~spc3_dfq_full5)
spc3_dfq_full_capture5 <= 1'b1;
else
spc3_dfq_full_capture5 <= 1'b0;
end
assign spc3_dfq_full6 = (spc3_dfq_vld_entries >= (3'd4 + 6));
always @(spc3_dfq_full_d6 or spc3_dfq_full6)
begin
if (spc3_dfq_full_d6 && ~spc3_dfq_full6)
spc3_dfq_full_capture6 <= 1'b1;
else
spc3_dfq_full_capture6 <= 1'b0;
end
assign spc3_dfq_full7 = (spc3_dfq_vld_entries >= (3'd4 + 7));
always @(spc3_dfq_full_d7 or spc3_dfq_full7)
begin
if (spc3_dfq_full_d7 && ~spc3_dfq_full7)
spc3_dfq_full_capture7 <= 1'b1;
else
spc3_dfq_full_capture7 <= 1'b0;
end
always @(spc3_mbar_vld_d0 or spc3_mbar_vld0)
begin
if (spc3_mbar_vld_d0 && ~spc3_mbar_vld0)
spc3_mbar_vld_capture0 <= 1'b1;
else
spc3_mbar_vld_capture0 <= 1'b0;
end
always @(spc3_mbar_vld_d1 or spc3_mbar_vld1)
begin
if (spc3_mbar_vld_d1 && ~spc3_mbar_vld1)
spc3_mbar_vld_capture1 <= 1'b1;
else
spc3_mbar_vld_capture1 <= 1'b0;
end
always @(spc3_mbar_vld_d2 or spc3_mbar_vld2)
begin
if (spc3_mbar_vld_d2 && ~spc3_mbar_vld2)
spc3_mbar_vld_capture2 <= 1'b1;
else
spc3_mbar_vld_capture2 <= 1'b0;
end
always @(spc3_mbar_vld_d3 or spc3_mbar_vld3)
begin
if (spc3_mbar_vld_d3 && ~spc3_mbar_vld3)
spc3_mbar_vld_capture3 <= 1'b1;
else
spc3_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc3_dfq_full1 && (spc3_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr1 <= 9'h000;
spc3_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr1);
end
else if( spc3_dfq_full1)
begin
spc3_dfq_full_cntr1 <= spc3_dfq_full_cntr1 + 1;
spc3_dfq_full_d1 <= spc3_dfq_full1;
end
else
begin
spc3_dfq_full_cntr1 <= spc3_dfq_full_cntr1;
spc3_dfq_full_d1 <= spc3_dfq_full1;
end
if( ( ~spc3_dfq_full2 && (spc3_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr2 <= 9'h000;
spc3_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr2);
end
else if( spc3_dfq_full2)
begin
spc3_dfq_full_cntr2 <= spc3_dfq_full_cntr2 + 1;
spc3_dfq_full_d2 <= spc3_dfq_full2;
end
else
begin
spc3_dfq_full_cntr2 <= spc3_dfq_full_cntr2;
spc3_dfq_full_d2 <= spc3_dfq_full2;
end
if( ( ~spc3_dfq_full3 && (spc3_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr3 <= 9'h000;
spc3_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr3);
end
else if( spc3_dfq_full3)
begin
spc3_dfq_full_cntr3 <= spc3_dfq_full_cntr3 + 1;
spc3_dfq_full_d3 <= spc3_dfq_full3;
end
else
begin
spc3_dfq_full_cntr3 <= spc3_dfq_full_cntr3;
spc3_dfq_full_d3 <= spc3_dfq_full3;
end
if( ( ~spc3_dfq_full4 && (spc3_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr4 <= 9'h000;
spc3_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr4);
end
else if( spc3_dfq_full4)
begin
spc3_dfq_full_cntr4 <= spc3_dfq_full_cntr4 + 1;
spc3_dfq_full_d4 <= spc3_dfq_full4;
end
else
begin
spc3_dfq_full_cntr4 <= spc3_dfq_full_cntr4;
spc3_dfq_full_d4 <= spc3_dfq_full4;
end
if( ( ~spc3_dfq_full5 && (spc3_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr5 <= 9'h000;
spc3_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr5);
end
else if( spc3_dfq_full5)
begin
spc3_dfq_full_cntr5 <= spc3_dfq_full_cntr5 + 1;
spc3_dfq_full_d5 <= spc3_dfq_full5;
end
else
begin
spc3_dfq_full_cntr5 <= spc3_dfq_full_cntr5;
spc3_dfq_full_d5 <= spc3_dfq_full5;
end
if( ( ~spc3_dfq_full6 && (spc3_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr6 <= 9'h000;
spc3_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr6);
end
else if( spc3_dfq_full6)
begin
spc3_dfq_full_cntr6 <= spc3_dfq_full_cntr6 + 1;
spc3_dfq_full_d6 <= spc3_dfq_full6;
end
else
begin
spc3_dfq_full_cntr6 <= spc3_dfq_full_cntr6;
spc3_dfq_full_d6 <= spc3_dfq_full6;
end
if( ( ~spc3_dfq_full7 && (spc3_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr7 <= 9'h000;
spc3_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr7);
end
else if( spc3_dfq_full7)
begin
spc3_dfq_full_cntr7 <= spc3_dfq_full_cntr7 + 1;
spc3_dfq_full_d7 <= spc3_dfq_full7;
end
else
begin
spc3_dfq_full_cntr7 <= spc3_dfq_full_cntr7;
spc3_dfq_full_d7 <= spc3_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc3_intrpt0_cmplt or spc3_atm_cntr0 or spc3_stb_state_ced0)
begin
if (spc3_intrpt0_cmplt && (spc3_atm_cntr0 != 9'h000) && ~(|spc3_stb_state_ced0))
spc3_atm_intrpt_b4capture0 <= 1'b1;
else
spc3_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc3_intrpt1_cmplt or spc3_atm_cntr1 or spc3_stb_state_ced1)
begin
if (spc3_intrpt1_cmplt && (spc3_atm_cntr1 != 9'h000) && ~(|spc3_stb_state_ced1))
spc3_atm_intrpt_b4capture1 <= 1'b1;
else
spc3_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc3_intrpt2_cmplt or spc3_atm_cntr2 or spc3_stb_state_ced2)
begin
if (spc3_intrpt2_cmplt && (spc3_atm_cntr2 != 9'h000) && ~(|spc3_stb_state_ced2))
spc3_atm_intrpt_b4capture2 <= 1'b1;
else
spc3_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc3_intrpt3_cmplt or spc3_atm_cntr3 or spc3_stb_state_ced3)
begin
if (spc3_intrpt3_cmplt && (spc3_atm_cntr3 != 9'h000) && ~(|spc3_stb_state_ced3))
spc3_atm_intrpt_b4capture3 <= 1'b1;
else
spc3_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc3_intrpt0_cmplt or spc3_atm_cntr0 or spc3_stb_state_ced0)
begin
if (spc3_intrpt0_cmplt && (spc3_atm_cntr0 != 9'h000) && (|spc3_stb_state_ced0))
spc3_atm_intrpt_capture0 <= 1'b1;
else
spc3_atm_intrpt_capture0 <= 1'b0;
end
always @(spc3_intrpt1_cmplt or spc3_atm_cntr1 or spc3_stb_state_ced1)
begin
if (spc3_intrpt1_cmplt && (spc3_atm_cntr1 != 9'h000) && (|spc3_stb_state_ced1))
spc3_atm_intrpt_capture1 <= 1'b1;
else
spc3_atm_intrpt_capture1 <= 1'b0;
end
always @(spc3_intrpt2_cmplt or spc3_atm_cntr2 or spc3_stb_state_ced2)
begin
if (spc3_intrpt2_cmplt && (spc3_atm_cntr2 != 9'h000) && (|spc3_stb_state_ced2))
spc3_atm_intrpt_capture2 <= 1'b1;
else
spc3_atm_intrpt_capture2 <= 1'b0;
end
always @(spc3_intrpt3_cmplt or spc3_atm_cntr3 or spc3_stb_state_ced3)
begin
if (spc3_intrpt3_cmplt && (spc3_atm_cntr3 != 9'h000) && (|spc3_stb_state_ced3))
spc3_atm_intrpt_capture3 <= 1'b1;
else
spc3_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc3_atm_cntr0 or spc3_dva_din or spc3_dva_wen)
begin
if (~spc3_dva_din && spc3_dva_wen && (spc3_atm_cntr0 != 9'h000))
spc3_atm_inv_capture0 <= 1'b1;
else
spc3_atm_inv_capture0 <= 1'b0;
end
always @(spc3_atm_cntr1 or spc3_dva_din or spc3_dva_wen)
begin
if (~spc3_dva_din && spc3_dva_wen && (spc3_atm_cntr1 != 9'h000))
spc3_atm_inv_capture1 <= 1'b1;
else
spc3_atm_inv_capture1 <= 1'b0;
end
always @(spc3_atm_cntr2 or spc3_dva_din or spc3_dva_wen)
begin
if (~spc3_dva_din && spc3_dva_wen && (spc3_atm_cntr2 != 9'h000))
spc3_atm_inv_capture2 <= 1'b1;
else
spc3_atm_inv_capture2 <= 1'b0;
end
always @(spc3_atm_cntr3 or spc3_dva_din or spc3_dva_wen)
begin
if (~spc3_dva_din && spc3_dva_wen && (spc3_atm_cntr3 != 9'h000))
spc3_atm_inv_capture3 <= 1'b1;
else
spc3_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc3_stb_state_vld0) && (spc3_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_atm_cntr0 <= 9'h000;
spc3_atm0_d <= 1'b0;
end
else if( spc3_atomic_g && (spc3_atm_type0 != 8'h00))
begin
spc3_atm_cntr0 <= spc3_atm_cntr0 + 1;
spc3_atm0_d <= 1'b1;
end
else if( spc3_atm0_d && (|spc3_stb_state_vld0))
begin
spc3_atm_cntr0 <= spc3_atm_cntr0 + 1;
spc3_atm0_d <= spc3_atm0_d;
end
else
begin
spc3_atm_cntr0 <= spc3_atm_cntr0;
spc3_atm0_d <= spc3_atm0_d;
end
if( ( ~(|spc3_stb_state_vld1) && (spc3_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_atm_cntr1 <= 9'h000;
spc3_atm1_d <= 1'b0;
end
else if( spc3_atomic_g && (spc3_atm_type1 != 8'h00))
begin
spc3_atm_cntr1 <= spc3_atm_cntr1 + 1;
spc3_atm1_d <= 1'b1;
end
else if( spc3_atm1_d && (|spc3_stb_state_vld1))
begin
spc3_atm_cntr1 <= spc3_atm_cntr1 + 1;
spc3_atm1_d <= spc3_atm1_d;
end
else
begin
spc3_atm_cntr1 <= spc3_atm_cntr1;
spc3_atm1_d <= spc3_atm1_d;
end
if( ( ~(|spc3_stb_state_vld2) && (spc3_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_atm_cntr2 <= 9'h000;
spc3_atm2_d <= 1'b0;
end
else if( spc3_atomic_g && (spc3_atm_type2 != 8'h00))
begin
spc3_atm_cntr2 <= spc3_atm_cntr2 + 1;
spc3_atm2_d <= 1'b1;
end
else if( spc3_atm2_d && (|spc3_stb_state_vld2))
begin
spc3_atm_cntr2 <= spc3_atm_cntr2 + 1;
spc3_atm2_d <= spc3_atm2_d;
end
else
begin
spc3_atm_cntr2 <= spc3_atm_cntr2;
spc3_atm2_d <= spc3_atm2_d;
end
if( ( ~(|spc3_stb_state_vld3) && (spc3_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_atm_cntr3 <= 9'h000;
spc3_atm3_d <= 1'b0;
end
else if( spc3_atomic_g && (spc3_atm_type3 != 8'h00))
begin
spc3_atm_cntr3 <= spc3_atm_cntr3 + 1;
spc3_atm3_d <= 1'b1;
end
else if( spc3_atm3_d && (|spc3_stb_state_vld3))
begin
spc3_atm_cntr3 <= spc3_atm_cntr3 + 1;
spc3_atm3_d <= spc3_atm3_d;
end
else
begin
spc3_atm_cntr3 <= spc3_atm_cntr3;
spc3_atm3_d <= spc3_atm3_d;
end
end
assign spc3_raw_ack_capture0 = spc3_stb_ack_vld0 && (spc3_stb_ack_cntr0 != 9'h000);
assign spc3_stb_ced0 = |spc3_stb_state_ced0;
assign spc3_raw_ack_capture1 = spc3_stb_ack_vld1 && (spc3_stb_ack_cntr1 != 9'h000);
assign spc3_stb_ced1 = |spc3_stb_state_ced1;
assign spc3_raw_ack_capture2 = spc3_stb_ack_vld2 && (spc3_stb_ack_cntr2 != 9'h000);
assign spc3_stb_ced2 = |spc3_stb_state_ced2;
assign spc3_raw_ack_capture3 = spc3_stb_ack_vld3 && (spc3_stb_ack_cntr3 != 9'h000);
assign spc3_stb_ced3 = |spc3_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc3_stb_ced0 && (spc3_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_stb_ced_cntr0 <= 9'h000;
spc3_stb_ced0_d <= 1'b0;
end
else if( spc3_stb_ced0 && (spc3_stb_state_ack0 == 8'h00))
begin
spc3_stb_ced_cntr0 <= spc3_stb_ced_cntr0 + 1;
spc3_stb_ced0_d <= spc3_stb_ced0;
end
else
begin
spc3_stb_ced_cntr0 <= spc3_stb_ced_cntr0;
spc3_stb_ced0_d <= spc3_stb_ced0_d;
end
if( ( ~spc3_mbar_vld0 && (spc3_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_mbar_vld_cntr0 <= 9'h000;
spc3_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_mbar_vld_counter = %d", spc3_mbar_vld_cntr0);
end
else if( spc3_mbar_vld0)
begin
spc3_mbar_vld_cntr0 <= spc3_mbar_vld_cntr0 + 1;
spc3_mbar_vld_d0 <= spc3_mbar_vld0;
end
else
begin
spc3_mbar_vld_cntr0 <= spc3_mbar_vld_cntr0;
spc3_mbar_vld_d0 <= spc3_mbar_vld0;
end
if( ( ~spc3_flsh_vld0 && (spc3_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_flsh_vld_cntr0 <= 9'h000;
spc3_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_flsh_vld_counter = %d", spc3_flsh_vld_cntr0);
end
else if( spc3_flsh_vld0)
begin
spc3_flsh_vld_cntr0 <= spc3_flsh_vld_cntr0 + 1;
spc3_flsh_vld_d0 <= spc3_flsh_vld0;
end
else
begin
spc3_flsh_vld_cntr0 <= spc3_flsh_vld_cntr0;
spc3_flsh_vld_d0 <= spc3_flsh_vld0;
end
if( ( ~spc3_stb_ced1 && (spc3_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_stb_ced_cntr1 <= 9'h000;
spc3_stb_ced1_d <= 1'b0;
end
else if( spc3_stb_ced1 && (spc3_stb_state_ack1 == 8'h00))
begin
spc3_stb_ced_cntr1 <= spc3_stb_ced_cntr1 + 1;
spc3_stb_ced1_d <= spc3_stb_ced1;
end
else
begin
spc3_stb_ced_cntr1 <= spc3_stb_ced_cntr1;
spc3_stb_ced1_d <= spc3_stb_ced1_d;
end
if( ( ~spc3_mbar_vld1 && (spc3_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_mbar_vld_cntr1 <= 9'h000;
spc3_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_mbar_vld_counter = %d", spc3_mbar_vld_cntr1);
end
else if( spc3_mbar_vld1)
begin
spc3_mbar_vld_cntr1 <= spc3_mbar_vld_cntr1 + 1;
spc3_mbar_vld_d1 <= spc3_mbar_vld1;
end
else
begin
spc3_mbar_vld_cntr1 <= spc3_mbar_vld_cntr1;
spc3_mbar_vld_d1 <= spc3_mbar_vld1;
end
if( ( ~spc3_flsh_vld1 && (spc3_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_flsh_vld_cntr1 <= 9'h000;
spc3_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_flsh_vld_counter = %d", spc3_flsh_vld_cntr1);
end
else if( spc3_flsh_vld1)
begin
spc3_flsh_vld_cntr1 <= spc3_flsh_vld_cntr1 + 1;
spc3_flsh_vld_d1 <= spc3_flsh_vld1;
end
else
begin
spc3_flsh_vld_cntr1 <= spc3_flsh_vld_cntr1;
spc3_flsh_vld_d1 <= spc3_flsh_vld1;
end
if( ( ~spc3_stb_ced2 && (spc3_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_stb_ced_cntr2 <= 9'h000;
spc3_stb_ced2_d <= 1'b0;
end
else if( spc3_stb_ced2 && (spc3_stb_state_ack2 == 8'h00))
begin
spc3_stb_ced_cntr2 <= spc3_stb_ced_cntr2 + 1;
spc3_stb_ced2_d <= spc3_stb_ced2;
end
else
begin
spc3_stb_ced_cntr2 <= spc3_stb_ced_cntr2;
spc3_stb_ced2_d <= spc3_stb_ced2_d;
end
if( ( ~spc3_mbar_vld2 && (spc3_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_mbar_vld_cntr2 <= 9'h000;
spc3_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_mbar_vld_counter = %d", spc3_mbar_vld_cntr2);
end
else if( spc3_mbar_vld2)
begin
spc3_mbar_vld_cntr2 <= spc3_mbar_vld_cntr2 + 1;
spc3_mbar_vld_d2 <= spc3_mbar_vld2;
end
else
begin
spc3_mbar_vld_cntr2 <= spc3_mbar_vld_cntr2;
spc3_mbar_vld_d2 <= spc3_mbar_vld2;
end
if( ( ~spc3_flsh_vld2 && (spc3_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_flsh_vld_cntr2 <= 9'h000;
spc3_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_flsh_vld_counter = %d", spc3_flsh_vld_cntr2);
end
else if( spc3_flsh_vld2)
begin
spc3_flsh_vld_cntr2 <= spc3_flsh_vld_cntr2 + 1;
spc3_flsh_vld_d2 <= spc3_flsh_vld2;
end
else
begin
spc3_flsh_vld_cntr2 <= spc3_flsh_vld_cntr2;
spc3_flsh_vld_d2 <= spc3_flsh_vld2;
end
if( ( ~spc3_stb_ced3 && (spc3_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_stb_ced_cntr3 <= 9'h000;
spc3_stb_ced3_d <= 1'b0;
end
else if( spc3_stb_ced3 && (spc3_stb_state_ack3 == 8'h00))
begin
spc3_stb_ced_cntr3 <= spc3_stb_ced_cntr3 + 1;
spc3_stb_ced3_d <= spc3_stb_ced3;
end
else
begin
spc3_stb_ced_cntr3 <= spc3_stb_ced_cntr3;
spc3_stb_ced3_d <= spc3_stb_ced3_d;
end
if( ( ~spc3_mbar_vld3 && (spc3_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_mbar_vld_cntr3 <= 9'h000;
spc3_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_mbar_vld_counter = %d", spc3_mbar_vld_cntr3);
end
else if( spc3_mbar_vld3)
begin
spc3_mbar_vld_cntr3 <= spc3_mbar_vld_cntr3 + 1;
spc3_mbar_vld_d3 <= spc3_mbar_vld3;
end
else
begin
spc3_mbar_vld_cntr3 <= spc3_mbar_vld_cntr3;
spc3_mbar_vld_d3 <= spc3_mbar_vld3;
end
if( ( ~spc3_flsh_vld3 && (spc3_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_flsh_vld_cntr3 <= 9'h000;
spc3_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_flsh_vld_counter = %d", spc3_flsh_vld_cntr3);
end
else if( spc3_flsh_vld3)
begin
spc3_flsh_vld_cntr3 <= spc3_flsh_vld_cntr3 + 1;
spc3_flsh_vld_d3 <= spc3_flsh_vld3;
end
else
begin
spc3_flsh_vld_cntr3 <= spc3_flsh_vld_cntr3;
spc3_flsh_vld_d3 <= spc3_flsh_vld3;
end
end
always @(spc3_flsh_vld_d0 or spc3_flsh_vld0)
begin
if (spc3_flsh_vld_d0 && ~spc3_flsh_vld0)
spc3_flsh_vld_capture0 <= 1'b1;
else
spc3_flsh_vld_capture0 <= 1'b0;
end
always @(spc3_flsh_vld_d1 or spc3_flsh_vld1)
begin
if (spc3_flsh_vld_d1 && ~spc3_flsh_vld1)
spc3_flsh_vld_capture1 <= 1'b1;
else
spc3_flsh_vld_capture1 <= 1'b0;
end
always @(spc3_flsh_vld_d2 or spc3_flsh_vld2)
begin
if (spc3_flsh_vld_d2 && ~spc3_flsh_vld2)
spc3_flsh_vld_capture2 <= 1'b1;
else
spc3_flsh_vld_capture2 <= 1'b0;
end
always @(spc3_flsh_vld_d3 or spc3_flsh_vld3)
begin
if (spc3_flsh_vld_d3 && ~spc3_flsh_vld3)
spc3_flsh_vld_capture3 <= 1'b1;
else
spc3_flsh_vld_capture3 <= 1'b0;
end
always @(spc3_lmiss_pa0 or spc3_imiss_pa or spc3_imiss_vld_d or spc3_lmiss_vld0)
begin
if((spc3_lmiss_pa0 == spc3_imiss_pa) && spc3_imiss_vld_d && spc3_lmiss_vld0)
spc3_lmiss_eq0 = 1'b1;
else
spc3_lmiss_eq0 = 1'b0;
end
always @(spc3_lmiss_pa1 or spc3_imiss_pa or spc3_imiss_vld_d or spc3_lmiss_vld1)
begin
if((spc3_lmiss_pa1 == spc3_imiss_pa) && spc3_imiss_vld_d && spc3_lmiss_vld1)
spc3_lmiss_eq1 = 1'b1;
else
spc3_lmiss_eq1 = 1'b0;
end
always @(spc3_lmiss_pa2 or spc3_imiss_pa or spc3_imiss_vld_d or spc3_lmiss_vld2)
begin
if((spc3_lmiss_pa2 == spc3_imiss_pa) && spc3_imiss_vld_d && spc3_lmiss_vld2)
spc3_lmiss_eq2 = 1'b1;
else
spc3_lmiss_eq2 = 1'b0;
end
always @(spc3_lmiss_pa3 or spc3_imiss_pa or spc3_imiss_vld_d or spc3_lmiss_vld3)
begin
if((spc3_lmiss_pa3 == spc3_imiss_pa) && spc3_imiss_vld_d && spc3_lmiss_vld3)
spc3_lmiss_eq3 = 1'b1;
else
spc3_lmiss_eq3 = 1'b0;
end
always @(spc3_lmiss_pa0 or spc3_stb_atm_addr0 or spc3_atm_cntr0 or spc3_lmiss_vld0)
begin
if ( ((spc3_lmiss_pa0 == spc3_stb_atm_addr0) && (spc3_atm_cntr0 != 9'h000) && spc3_lmiss_vld0) ||
((spc3_lmiss_pa1 == spc3_stb_atm_addr0) && (spc3_atm_cntr0 != 9'h000) && spc3_lmiss_vld1) ||
((spc3_lmiss_pa2 == spc3_stb_atm_addr0) && (spc3_atm_cntr0 != 9'h000) && spc3_lmiss_vld2) ||
((spc3_lmiss_pa3 == spc3_stb_atm_addr0) && (spc3_atm_cntr0 != 9'h000) && spc3_lmiss_vld3) )
spc3_atm_lmiss_eq0 = 1'b1;
else
spc3_atm_lmiss_eq0 = 1'b0;
end
always @(spc3_lmiss_pa1 or spc3_stb_atm_addr1 or spc3_atm_cntr1 or spc3_lmiss_vld1)
begin
if ( ((spc3_lmiss_pa0 == spc3_stb_atm_addr1) && (spc3_atm_cntr1 != 9'h000) && spc3_lmiss_vld0) ||
((spc3_lmiss_pa1 == spc3_stb_atm_addr1) && (spc3_atm_cntr1 != 9'h000) && spc3_lmiss_vld1) ||
((spc3_lmiss_pa2 == spc3_stb_atm_addr1) && (spc3_atm_cntr1 != 9'h000) && spc3_lmiss_vld2) ||
((spc3_lmiss_pa3 == spc3_stb_atm_addr1) && (spc3_atm_cntr1 != 9'h000) && spc3_lmiss_vld3) )
spc3_atm_lmiss_eq1 = 1'b1;
else
spc3_atm_lmiss_eq1 = 1'b0;
end
always @(spc3_lmiss_pa2 or spc3_stb_atm_addr2 or spc3_atm_cntr2 or spc3_lmiss_vld2)
begin
if ( ((spc3_lmiss_pa0 == spc3_stb_atm_addr2) && (spc3_atm_cntr2 != 9'h000) && spc3_lmiss_vld0) ||
((spc3_lmiss_pa1 == spc3_stb_atm_addr2) && (spc3_atm_cntr2 != 9'h000) && spc3_lmiss_vld1) ||
((spc3_lmiss_pa2 == spc3_stb_atm_addr2) && (spc3_atm_cntr2 != 9'h000) && spc3_lmiss_vld2) ||
((spc3_lmiss_pa3 == spc3_stb_atm_addr2) && (spc3_atm_cntr2 != 9'h000) && spc3_lmiss_vld3) )
spc3_atm_lmiss_eq2 = 1'b1;
else
spc3_atm_lmiss_eq2 = 1'b0;
end
always @(spc3_lmiss_pa3 or spc3_stb_atm_addr3 or spc3_atm_cntr3 or spc3_lmiss_vld3)
begin
if ( ((spc3_lmiss_pa0 == spc3_stb_atm_addr3) && (spc3_atm_cntr3 != 9'h000) && spc3_lmiss_vld0) ||
((spc3_lmiss_pa1 == spc3_stb_atm_addr3) && (spc3_atm_cntr3 != 9'h000) && spc3_lmiss_vld1) ||
((spc3_lmiss_pa2 == spc3_stb_atm_addr3) && (spc3_atm_cntr3 != 9'h000) && spc3_lmiss_vld2) ||
((spc3_lmiss_pa3 == spc3_stb_atm_addr3) && (spc3_atm_cntr3 != 9'h000) && spc3_lmiss_vld3) )
spc3_atm_lmiss_eq3 = 1'b1;
else
spc3_atm_lmiss_eq3 = 1'b0;
end
always @(spc3_imiss_pa or spc3_stb_atm_addr0 or spc3_atm_cntr0 or spc3_imiss_vld_d)
begin
if((spc3_imiss_pa == spc3_stb_atm_addr0) && (spc3_atm_cntr0 != 9'h000) && spc3_imiss_vld_d)
spc3_atm_imiss_eq0 = 1'b1;
else
spc3_atm_imiss_eq0 = 1'b0;
end
always @(spc3_imiss_pa or spc3_stb_atm_addr1 or spc3_atm_cntr1 or spc3_imiss_vld_d)
begin
if((spc3_imiss_pa == spc3_stb_atm_addr1) && (spc3_atm_cntr1 != 9'h000) && spc3_imiss_vld_d)
spc3_atm_imiss_eq1 = 1'b1;
else
spc3_atm_imiss_eq1 = 1'b0;
end
always @(spc3_imiss_pa or spc3_stb_atm_addr2 or spc3_atm_cntr2 or spc3_imiss_vld_d)
begin
if((spc3_imiss_pa == spc3_stb_atm_addr2) && (spc3_atm_cntr2 != 9'h000) && spc3_imiss_vld_d)
spc3_atm_imiss_eq2 = 1'b1;
else
spc3_atm_imiss_eq2 = 1'b0;
end
always @(spc3_imiss_pa or spc3_stb_atm_addr3 or spc3_atm_cntr3 or spc3_imiss_vld_d)
begin
if((spc3_imiss_pa == spc3_stb_atm_addr3) && (spc3_atm_cntr3 != 9'h000) && spc3_imiss_vld_d)
spc3_atm_imiss_eq3 = 1'b1;
else
spc3_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc3_imiss_vld || ~rst_l)
spc3_imiss_vld_d <= 1'b0;
else
spc3_imiss_vld_d <= spc3_imiss_vld;
if( ~spc3_ld_miss || ~rst_l)
spc3_ld_miss_capture <= 1'b0;
else
spc3_ld_miss_capture <= spc3_ld_miss;
end
always @(spc3_stb_ced0 or spc3_stb_ced0_d)
begin
if (~spc3_stb_ced0 && spc3_stb_ced0_d)
spc3_stb_ced_capture0 <= 1'b1;
else
spc3_stb_ced_capture0 <= 1'b0;
end
always @(spc3_stb_ced1 or spc3_stb_ced1_d)
begin
if (~spc3_stb_ced1 && spc3_stb_ced1_d)
spc3_stb_ced_capture1 <= 1'b1;
else
spc3_stb_ced_capture1 <= 1'b0;
end
always @(spc3_stb_ced2 or spc3_stb_ced2_d)
begin
if (~spc3_stb_ced2 && spc3_stb_ced2_d)
spc3_stb_ced_capture2 <= 1'b1;
else
spc3_stb_ced_capture2 <= 1'b0;
end
always @(spc3_stb_ced3 or spc3_stb_ced3_d)
begin
if (~spc3_stb_ced3 && spc3_stb_ced3_d)
spc3_stb_ced_capture3 <= 1'b1;
else
spc3_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc3_stb_state_ack0 != 8'h00 && (spc3_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_ack_counter0 = %d", spc3_stb_ack_cntr0);
end
else if(spc3_stb_cam_hit && spc3_ld0_inst_vld_g && (spc3_stb_state_ack0 == 8'h00))
begin
spc3_stb_ack_cntr0 <= spc3_stb_ack_cntr0 + 1;
end
else if( (spc3_stb_state_ack0 == 8'h00 ) && (spc3_stb_ack_cntr0 != 9'h000))
begin
spc3_stb_ack_cntr0 <= spc3_stb_ack_cntr0 + 1;
end // if ( (spc3_stb_state_ack0 == 8'h00 ) && (spc3_stb_ack_cntr0 != 9'h000))
else
begin
spc3_stb_ack_cntr0 <= spc3_stb_ack_cntr0;
end
if( (spc3_stb_state_ack1 != 8'h00 && (spc3_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_ack_counter1 = %d", spc3_stb_ack_cntr1);
end
else if(spc3_stb_cam_hit && spc3_ld1_inst_vld_g && (spc3_stb_state_ack1 == 8'h00))
begin
spc3_stb_ack_cntr1 <= spc3_stb_ack_cntr1 + 1;
end
else if( (spc3_stb_state_ack1 == 8'h00 ) && (spc3_stb_ack_cntr1 != 9'h000))
begin
spc3_stb_ack_cntr1 <= spc3_stb_ack_cntr1 + 1;
end // if ( (spc3_stb_state_ack1 == 8'h00 ) && (spc3_stb_ack_cntr1 != 9'h000))
else
begin
spc3_stb_ack_cntr1 <= spc3_stb_ack_cntr1;
end
if( (spc3_stb_state_ack2 != 8'h00 && (spc3_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_ack_counter2 = %d", spc3_stb_ack_cntr2);
end
else if(spc3_stb_cam_hit && spc3_ld2_inst_vld_g && (spc3_stb_state_ack2 == 8'h00))
begin
spc3_stb_ack_cntr2 <= spc3_stb_ack_cntr2 + 1;
end
else if( (spc3_stb_state_ack2 == 8'h00 ) && (spc3_stb_ack_cntr2 != 9'h000))
begin
spc3_stb_ack_cntr2 <= spc3_stb_ack_cntr2 + 1;
end // if ( (spc3_stb_state_ack2 == 8'h00 ) && (spc3_stb_ack_cntr2 != 9'h000))
else
begin
spc3_stb_ack_cntr2 <= spc3_stb_ack_cntr2;
end
if( (spc3_stb_state_ack3 != 8'h00 && (spc3_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_ack_counter3 = %d", spc3_stb_ack_cntr3);
end
else if(spc3_stb_cam_hit && spc3_ld3_inst_vld_g && (spc3_stb_state_ack3 == 8'h00))
begin
spc3_stb_ack_cntr3 <= spc3_stb_ack_cntr3 + 1;
end
else if( (spc3_stb_state_ack3 == 8'h00 ) && (spc3_stb_ack_cntr3 != 9'h000))
begin
spc3_stb_ack_cntr3 <= spc3_stb_ack_cntr3 + 1;
end // if ( (spc3_stb_state_ack3 == 8'h00 ) && (spc3_stb_ack_cntr3 != 9'h000))
else
begin
spc3_stb_ack_cntr3 <= spc3_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc3_stb0_full_w2 or spc3_stb0_full)
begin
if (~spc3_stb0_full_w2 && spc3_stb0_full)
spc3_stb_full_capture0 <= 1'b1;
else
spc3_stb_full_capture0 <= 1'b0;
end
always @(spc3_stb1_full_w2 or spc3_stb1_full)
begin
if (~spc3_stb1_full_w2 && spc3_stb1_full)
spc3_stb_full_capture1 <= 1'b1;
else
spc3_stb_full_capture1 <= 1'b0;
end
always @(spc3_stb2_full_w2 or spc3_stb2_full)
begin
if (~spc3_stb2_full_w2 && spc3_stb2_full)
spc3_stb_full_capture2 <= 1'b1;
else
spc3_stb_full_capture2 <= 1'b0;
end
always @(spc3_stb3_full_w2 or spc3_stb3_full)
begin
if (~spc3_stb3_full_w2 && spc3_stb3_full)
spc3_stb_full_capture3 <= 1'b1;
else
spc3_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc3_stb0_full && (spc3_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_full_counter0 = %d", spc3_stb_full_cntr0);
end
else if( spc3_stb0_full)
begin
spc3_stb_full_cntr0 <= spc3_stb_full_cntr0 + 1;
end
else
begin
spc3_stb_full_cntr0 <= spc3_stb_full_cntr0;
end
if( ( ~spc3_stb1_full && (spc3_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_full_counter1 = %d", spc3_stb_full_cntr1);
end
else if( spc3_stb1_full)
begin
spc3_stb_full_cntr1 <= spc3_stb_full_cntr1 + 1;
end
else
begin
spc3_stb_full_cntr1 <= spc3_stb_full_cntr1;
end
if( ( ~spc3_stb2_full && (spc3_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_full_counter2 = %d", spc3_stb_full_cntr2);
end
else if( spc3_stb2_full)
begin
spc3_stb_full_cntr2 <= spc3_stb_full_cntr2 + 1;
end
else
begin
spc3_stb_full_cntr2 <= spc3_stb_full_cntr2;
end
if( ( ~spc3_stb3_full && (spc3_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc3_stb_full_counter3 = %d", spc3_stb_full_cntr3);
end
else if( spc3_stb3_full)
begin
spc3_stb_full_cntr3 <= spc3_stb_full_cntr3 + 1;
end
else
begin
spc3_stb_full_cntr3 <= spc3_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc3_lmq0_full_d or spc3_lmq0_full)
begin
if (spc3_lmq0_full_d && ~spc3_lmq0_full)
spc3_lmq_full_capture0 <= 1'b1;
else
spc3_lmq_full_capture0 <= 1'b0;
end
always @(spc3_lmq1_full_d or spc3_lmq1_full)
begin
if (spc3_lmq1_full_d && ~spc3_lmq1_full)
spc3_lmq_full_capture1 <= 1'b1;
else
spc3_lmq_full_capture1 <= 1'b0;
end
always @(spc3_lmq2_full_d or spc3_lmq2_full)
begin
if (spc3_lmq2_full_d && ~spc3_lmq2_full)
spc3_lmq_full_capture2 <= 1'b1;
else
spc3_lmq_full_capture2 <= 1'b0;
end
always @(spc3_lmq3_full_d or spc3_lmq3_full)
begin
if (spc3_lmq3_full_d && ~spc3_lmq3_full)
spc3_lmq_full_capture3 <= 1'b1;
else
spc3_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc3_lmq0_full && (spc3_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc3_lmq_full_cntr0 <= 9'h000;
spc3_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_lmq_full_counter0 = %d", spc3_lmq_full_cntr0);
end
else if( spc3_lmq0_full)
begin
spc3_lmq_full_cntr0 <= spc3_lmq_full_cntr0 + 1;
spc3_lmq0_full_d <= spc3_lmq0_full;
end
else
begin
spc3_lmq_full_cntr0 <= spc3_lmq_full_cntr0;
spc3_lmq0_full_d <= spc3_lmq0_full;
end
if( ( ~spc3_lmq1_full && (spc3_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc3_lmq_full_cntr1 <= 9'h000;
spc3_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_lmq_full_counter1 = %d", spc3_lmq_full_cntr1);
end
else if( spc3_lmq1_full)
begin
spc3_lmq_full_cntr1 <= spc3_lmq_full_cntr1 + 1;
spc3_lmq1_full_d <= spc3_lmq1_full;
end
else
begin
spc3_lmq_full_cntr1 <= spc3_lmq_full_cntr1;
spc3_lmq1_full_d <= spc3_lmq1_full;
end
if( ( ~spc3_lmq2_full && (spc3_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc3_lmq_full_cntr2 <= 9'h000;
spc3_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_lmq_full_counter2 = %d", spc3_lmq_full_cntr2);
end
else if( spc3_lmq2_full)
begin
spc3_lmq_full_cntr2 <= spc3_lmq_full_cntr2 + 1;
spc3_lmq2_full_d <= spc3_lmq2_full;
end
else
begin
spc3_lmq_full_cntr2 <= spc3_lmq_full_cntr2;
spc3_lmq2_full_d <= spc3_lmq2_full;
end
if( ( ~spc3_lmq3_full && (spc3_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc3_lmq_full_cntr3 <= 9'h000;
spc3_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_lmq_full_counter3 = %d", spc3_lmq_full_cntr3);
end
else if( spc3_lmq3_full)
begin
spc3_lmq_full_cntr3 <= spc3_lmq_full_cntr3 + 1;
spc3_lmq3_full_d <= spc3_lmq3_full;
end
else
begin
spc3_lmq_full_cntr3 <= spc3_lmq_full_cntr3;
spc3_lmq3_full_d <= spc3_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc3_dfq_full_d or spc3_dfq_full)
begin
if (spc3_dfq_full_d && ~spc3_dfq_full)
spc3_dfq_full_capture <= 1'b1;
else
spc3_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc3_dfq_full && (spc3_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc3_dfq_full_cntr <= 9'h000;
spc3_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dfq_full_counter = %d", spc3_dfq_full_cntr);
end
else if( spc3_dfq_full)
begin
spc3_dfq_full_cntr <= spc3_dfq_full_cntr + 1;
spc3_dfq_full_d <= spc3_dfq_full;
end
else
begin
spc3_dfq_full_cntr <= spc3_dfq_full_cntr;
spc3_dfq_full_d <= spc3_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc3_dva_full_d or spc3_dva_inv)
begin
if (spc3_dva_full_d && ~spc3_dva_inv)
spc3_dva_full_capture <= 1'b1;
else
spc3_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc3_dva_din && spc3_dva_wen)
begin
spc3_dva_inv <= 1'b1;
spc3_dva_waddr_d <= spc3_dva_waddr;
end
else if(~spc3_dva_din && spc3_dva_wen)
begin
spc3_dva_inv <= 1'b0;
spc3_dva_waddr_d <= 5'b00000;
end
else
begin
spc3_dva_inv <= spc3_dva_inv;
spc3_dva_waddr_d <= spc3_dva_waddr_d;
end
end
always @(spc3_dva_raddr or spc3_dva_ren or spc3_dva_inv)
begin
if (spc3_dva_inv && spc3_dva_ren && (spc3_dva_raddr[6:2] == spc3_dva_waddr_d))
spc3_dva_vld2lkup <= 1'b1;
else
spc3_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc3_dva_inv && (spc3_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc3_dva_full_cntr <= 9'h000;
spc3_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dva_full_counter = %d", spc3_dva_full_cntr);
end
else if( spc3_dva_inv)
begin
spc3_dva_full_cntr <= spc3_dva_full_cntr + 1;
spc3_dva_full_d <= spc3_dva_inv;
end
else
begin
spc3_dva_full_cntr <= spc3_dva_full_cntr;
spc3_dva_full_d <= spc3_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc3_dva_vfull_d or spc3_dva_vld)
begin
if (spc3_dva_vfull_d && ~spc3_dva_vld)
spc3_dva_vfull_capture <= 1'b1;
else
spc3_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc3_dva_din && spc3_dva_wen)
begin
spc3_dva_vld <= 1'b1;
spc3_dva_invwaddr_d <= spc3_dva_waddr;
spc3_dva_invld_err <= spc3_dva_inv_perror;
end
else if(spc3_dva_din && spc3_dva_wen)
begin
spc3_dva_vld <= 1'b0;
spc3_dva_invwaddr_d <= 5'b00000;
spc3_dva_invld_err <= 1'b0;
end
else
begin
spc3_dva_vld <= spc3_dva_vld;
spc3_dva_invwaddr_d <= spc3_dva_invwaddr_d;
spc3_dva_invld_err <= spc3_dva_invld_err;
end
end
always @(spc3_dva_raddr or spc3_dva_ren or spc3_dva_vld)
begin
if (spc3_dva_vld && spc3_dva_ren && (spc3_dva_raddr[6:2] == spc3_dva_waddr_d))
spc3_dva_invld2lkup <= 1'b1;
else
spc3_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc3_dva_vld && (spc3_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc3_dva_vfull_cntr <= 9'h000;
spc3_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc3_dva_vfull_counter = %d", spc3_dva_vfull_cntr);
end
else if( spc3_dva_vld)
begin
spc3_dva_vfull_cntr <= spc3_dva_vfull_cntr + 1;
spc3_dva_vfull_d <= spc3_dva_vld;
end
else
begin
spc3_dva_vfull_cntr <= spc3_dva_vfull_cntr;
spc3_dva_vfull_d <= spc3_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc3_dva_raddr or spc3_dva_waddr or spc3_dva_ren or spc3_dva_wen)
begin
if ( spc3_dva_ren && spc3_dva_wen && (spc3_dva_raddr[6:2] == spc3_dva_waddr))
spc3_dva_collide <= 1'b1;
else
spc3_dva_collide <= 1'b0;
end
// dva error cases
always @(spc3_dva_raddr or spc3_dva_ren or spc3_dva_dtag_perror or spc3_dva_dtag_perror)
begin
if (spc3_dva_ren && (spc3_dva_dtag_perror || spc3_dva_dtag_perror))
spc3_dva_err <= 1'b1;
else
spc3_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc3_dva_err)
spc3_dva_efull_d <= 1'b1;
else
spc3_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc3_dva_ren && ~(spc3_dva_dtag_perror || spc3_dva_dtag_perror ) &&
(spc3_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc3_dva_efull_cntr <= 9'h000;
spc3_dva_raddr_d <= spc3_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc3_dva_efull_counter = %d", spc3_dva_efull_cntr);
end
else if(spc3_dva_efull_d)
begin
spc3_dva_efull_cntr <= spc3_dva_efull_cntr + 1;
spc3_dva_raddr_d <= spc3_dva_raddr_d;
end
else
begin
spc3_dva_efull_cntr <= spc3_dva_efull_cntr;
spc3_dva_raddr_d <= spc3_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC4
wire spc4_dva_ren = `TOP_DESIGN.sparc4.lsu.ifu_lsu_ld_inst_e;
wire spc4_dva_wen = `TOP_DESIGN.sparc4.lsu.lsu_dtagv_wr_vld_e;
wire spc4_dva_din = `TOP_DESIGN.sparc4.lsu.dva_din_e;
wire [3:0] spc4_dva_dout = `TOP_DESIGN.sparc4.lsu.dva_vld_m[3:0];
wire [6:0] spc4_dva_raddr = `TOP_DESIGN.sparc4.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc4_dva_waddr = `TOP_DESIGN.sparc4.lsu.dva_wr_adr_e[10:6];
wire spc4_dva_dtag_perror = `TOP_DESIGN.sparc4.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc4_dva_dcache_perror = `TOP_DESIGN.sparc4.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc4_dva_inv_perror = `TOP_DESIGN.sparc4.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc4_ld_miss = `TOP_DESIGN.sparc4.lsu.dctl.lsu_ld_miss_wb;
reg spc4_ld_miss_capture;
wire spc4_atomic_g = `TOP_DESIGN.sparc4.lsu.qctl1.atomic_g;
wire [1:0] spc4_atm_type0 = `TOP_DESIGN.sparc4.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc4_atm_type1 = `TOP_DESIGN.sparc4.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc4_atm_type2 = `TOP_DESIGN.sparc4.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc4_atm_type3 = `TOP_DESIGN.sparc4.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc4_dctl_lsu_way_hit = `TOP_DESIGN.sparc4.lsu.dctl.lsu_way_hit;
wire spc4_dctl_dcache_enable_g = `TOP_DESIGN.sparc4.lsu.dctl.dcache_enable_g;
wire spc4_dctl_ldxa_internal = `TOP_DESIGN.sparc4.lsu.dctl.ldxa_internal;
wire spc4_dctl_ldst_dbl_g = `TOP_DESIGN.sparc4.lsu.dctl.ldst_dbl_g;
wire spc4_dctl_atomic_g = `TOP_DESIGN.sparc4.lsu.dctl.atomic_g;
wire spc4_dctl_stb_cam_hit = `TOP_DESIGN.sparc4.lsu.dctl.stb_cam_hit;
wire spc4_dctl_endian_mispred_g = `TOP_DESIGN.sparc4.lsu.dctl.endian_mispred_g;
wire spc4_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc4.lsu.dctl.dcache_rd_parity_error;
wire spc4_dctl_dtag_perror_g = `TOP_DESIGN.sparc4.lsu.dctl.dtag_perror_g;
wire spc4_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc4.lsu.dctl.tte_data_perror_unc;
wire spc4_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc4.lsu.dctl.ld_inst_vld_g;
wire spc4_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc4.lsu.dctl.lsu_alt_space_g;
wire spc4_dctl_recognized_asi_g = `TOP_DESIGN.sparc4.lsu.dctl.recognized_asi_g;
wire spc4_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc4.lsu.dctl.ncache_asild_rq_g ;
wire spc4_dctl_bld_hit;
wire spc4_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc4_ixinv0 = `TOP_DESIGN.sparc4.lsu.qctl2.imiss0_inv_en;
wire spc4_ixinv1 = `TOP_DESIGN.sparc4.lsu.qctl2.imiss1_inv_en;
wire spc4_ixinv2 = `TOP_DESIGN.sparc4.lsu.qctl2.imiss2_inv_en;
wire spc4_ixinv3 = `TOP_DESIGN.sparc4.lsu.qctl2.imiss3_inv_en;
wire spc4_ifill = `TOP_DESIGN.sparc4.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc4_inv = `TOP_DESIGN.sparc4.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc4_inv_clr = `TOP_DESIGN.sparc4.lsu.qctl2.ifu_lsu_inv_clear;
wire spc4_ibuf_busy = `TOP_DESIGN.sparc4.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc4_l2 = `TOP_DESIGN.sparc4.lsu.dctl.l2fill_vld_g ;
wire spc4_unc = `TOP_DESIGN.sparc4.lsu.dctl.unc_err_trap_g ;
wire spc4_fpld = `TOP_DESIGN.sparc4.lsu.dctl.l2fill_fpld_g ;
wire spc4_fpldst = `TOP_DESIGN.sparc4.lsu.dctl.fp_ldst_g ;
wire spc4_unflush = `TOP_DESIGN.sparc4.lsu.dctl.ld_inst_vld_unflushed ;
wire spc4_ldw = `TOP_DESIGN.sparc4.lsu.dctl.lsu_inst_vld_w ;
wire spc4_byp = `TOP_DESIGN.sparc4.lsu.dctl.intld_byp_data_vld_m ;
wire spc4_flsh = `TOP_DESIGN.sparc4.lsu.lsu_exu_flush_pipe_w ;
wire spc4_chm = `TOP_DESIGN.sparc4.lsu.dctl.common_ldst_miss_w ;
wire spc4_ldxa = `TOP_DESIGN.sparc4.lsu.dctl.ldxa_internal ;
wire spc4_ato = `TOP_DESIGN.sparc4.lsu.dctl.atomic_g ;
wire spc4_pref = `TOP_DESIGN.sparc4.lsu.dctl.pref_inst_g ;
wire spc4_chit = `TOP_DESIGN.sparc4.lsu.dctl.stb_cam_hit ;
wire spc4_dcp = `TOP_DESIGN.sparc4.lsu.dctl.dcache_rd_parity_error ;
wire spc4_dtp = `TOP_DESIGN.sparc4.lsu.dctl.dtag_perror_g ;
//wire spc4_mpc = `TOP_DESIGN.sparc4.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc4_mpc = 1'b0;
wire spc4_mpu = `TOP_DESIGN.sparc4.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc4_exu_und;
reg [4:0] spc4_exu;
// excptn
wire spc4_exp_wtchpt_trp_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc4_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc4_exp_priv_violtn_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc4_exp_daccess_excptn_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc4_exp_daccess_prot_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc4_exp_priv_action_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc4_exp_spec_access_epage_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc4_exp_uncache_atomic_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc4_exp_illegal_asi_action_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc4_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc4_exp_asi_rd_unc = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc4_exp_tlb_data_ce = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc4_exp_asi_rd_unc = 1'b0;
wire spc4_exp_tlb_data_ce = 1'b0;
wire spc4_exp_tlb_data_ue = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc4_exp_tlb_tag_ue = `TOP_DESIGN.sparc4.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc4_exp_unc = `TOP_DESIGN.sparc4.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc4_exp_corr = `TOP_DESIGN.sparc4.lsu.excpctl.tte_data_perror_corr;
wire spc4_exp_corr = 1'b0;
wire [15:0] spc4_exp_und;
reg [4:0] spc4_exp;
// dctl cmplt
wire spc4_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc4.lsu.dctl.stxa_internal_d2;
wire spc4_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc4.lsu.dctl.lsu_l2fill_vld;
wire spc4_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc4.lsu.dctl.atomic_ld_squash_e;
wire spc4_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc4.lsu.qctl2.lsu_ignore_fill;
wire spc4_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc4.lsu.dctl.l2fill_fpld_e;
// wire spc4_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc4.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc4_dctl_fill_err_trap_e = `TOP_DESIGN.sparc4.lsu.dctl.fill_err_trap_e;
wire spc4_dctl_l2_corr_error_e = `TOP_DESIGN.sparc4.lsu.dctl.l2_corr_error_e;
wire [3:0] spc4_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc4.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc4_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc4.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc4_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc4.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc4_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc4.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc4_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc4.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc4_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc4.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc4_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc4_ldstcond_cmplt_d;
wire spc4_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc4.lsu.qctl1.ld_sec_hit_thrd0;
wire spc4_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_inst_vld_g;
wire spc4_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc4_ld0_pkt_vld_unmasked_d;
reg spc4_qctl1_ld_sec_hit_thrd0_w2;
wire spc4_dctl_thread0_w3 = `TOP_DESIGN.sparc4.lsu.dctl.thread0_w3;
wire spc4_dctl_dfill_thread0 = `TOP_DESIGN.sparc4.lsu.dctl.dfill_thread0;
wire spc4_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc4.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc4_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc4.lsu.dctl.diag_wr_cmplt0;
wire spc4_dctl_bsync0_reset = `TOP_DESIGN.sparc4.lsu.dctl.bsync0_reset;
wire spc4_dctl_late_cmplt0 = `TOP_DESIGN.sparc4.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc4_dctl_stxa_cmplt0;
wire spc4_dctl_l2fill_cmplt0;
wire spc4_dctl_atm_cmplt0;
wire spc4_dctl_fillerr0;
wire [4:0] spc4_cmplt0;
wire [5:0] spc4_dctl_ldst_cond_cmplt0;
reg [3:0] spc4_ldstcond_cmplt0;
reg [3:0] spc4_ldstcond_cmplt0_d;
wire spc4_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc4.lsu.qctl1.ld_sec_hit_thrd1;
wire spc4_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_inst_vld_g;
wire spc4_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc4_ld1_pkt_vld_unmasked_d;
reg spc4_qctl1_ld_sec_hit_thrd1_w2;
wire spc4_dctl_thread1_w3 = `TOP_DESIGN.sparc4.lsu.dctl.thread1_w3;
wire spc4_dctl_dfill_thread1 = `TOP_DESIGN.sparc4.lsu.dctl.dfill_thread1;
wire spc4_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc4.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc4_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc4.lsu.dctl.diag_wr_cmplt1;
wire spc4_dctl_bsync1_reset = `TOP_DESIGN.sparc4.lsu.dctl.bsync1_reset;
wire spc4_dctl_late_cmplt1 = `TOP_DESIGN.sparc4.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc4_dctl_stxa_cmplt1;
wire spc4_dctl_l2fill_cmplt1;
wire spc4_dctl_atm_cmplt1;
wire spc4_dctl_fillerr1;
wire [4:0] spc4_cmplt1;
wire [5:0] spc4_dctl_ldst_cond_cmplt1;
reg [3:0] spc4_ldstcond_cmplt1;
reg [3:0] spc4_ldstcond_cmplt1_d;
wire spc4_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc4.lsu.qctl1.ld_sec_hit_thrd2;
wire spc4_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_inst_vld_g;
wire spc4_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc4_ld2_pkt_vld_unmasked_d;
reg spc4_qctl1_ld_sec_hit_thrd2_w2;
wire spc4_dctl_thread2_w3 = `TOP_DESIGN.sparc4.lsu.dctl.thread2_w3;
wire spc4_dctl_dfill_thread2 = `TOP_DESIGN.sparc4.lsu.dctl.dfill_thread2;
wire spc4_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc4.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc4_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc4.lsu.dctl.diag_wr_cmplt2;
wire spc4_dctl_bsync2_reset = `TOP_DESIGN.sparc4.lsu.dctl.bsync2_reset;
wire spc4_dctl_late_cmplt2 = `TOP_DESIGN.sparc4.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc4_dctl_stxa_cmplt2;
wire spc4_dctl_l2fill_cmplt2;
wire spc4_dctl_atm_cmplt2;
wire spc4_dctl_fillerr2;
wire [4:0] spc4_cmplt2;
wire [5:0] spc4_dctl_ldst_cond_cmplt2;
reg [3:0] spc4_ldstcond_cmplt2;
reg [3:0] spc4_ldstcond_cmplt2_d;
wire spc4_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc4.lsu.qctl1.ld_sec_hit_thrd3;
wire spc4_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_inst_vld_g;
wire spc4_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc4_ld3_pkt_vld_unmasked_d;
reg spc4_qctl1_ld_sec_hit_thrd3_w2;
wire spc4_dctl_thread3_w3 = `TOP_DESIGN.sparc4.lsu.dctl.thread3_w3;
wire spc4_dctl_dfill_thread3 = `TOP_DESIGN.sparc4.lsu.dctl.dfill_thread3;
wire spc4_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc4.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc4_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc4.lsu.dctl.diag_wr_cmplt3;
wire spc4_dctl_bsync3_reset = `TOP_DESIGN.sparc4.lsu.dctl.bsync3_reset;
wire spc4_dctl_late_cmplt3 = `TOP_DESIGN.sparc4.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc4_dctl_stxa_cmplt3;
wire spc4_dctl_l2fill_cmplt3;
wire spc4_dctl_atm_cmplt3;
wire spc4_dctl_fillerr3;
wire [4:0] spc4_cmplt3;
wire [5:0] spc4_dctl_ldst_cond_cmplt3;
reg [3:0] spc4_ldstcond_cmplt3;
reg [3:0] spc4_ldstcond_cmplt3_d;
wire spc4_qctl1_bld_g = `TOP_DESIGN.sparc4.lsu.qctl1.bld_g;
wire spc4_qctl1_bld_reset = `TOP_DESIGN.sparc4.lsu.qctl1.bld_reset;
wire [1:0] spc4_qctl1_bld_cnt = `TOP_DESIGN.sparc4.lsu.qctl1.bld_cnt;
reg [9:0] spc4_bld0_full_cntr;
reg [1:0] spc4_bld0_full_d;
reg spc4_bld0_full_capture;
reg [9:0] spc4_bld1_full_cntr;
reg [1:0] spc4_bld1_full_d;
reg spc4_bld1_full_capture;
reg [9:0] spc4_bld2_full_cntr;
reg [1:0] spc4_bld2_full_d;
reg spc4_bld2_full_capture;
reg [9:0] spc4_bld3_full_cntr;
reg [1:0] spc4_bld3_full_d;
reg spc4_bld3_full_capture;
wire spc4_ipick = `TOP_DESIGN.sparc4.lsu.qctl1.imiss_pcx_rq_vld;
wire spc4_lpick = `TOP_DESIGN.sparc4.lsu.qctl1.ld_pcx_rq_all;
wire spc4_spick = `TOP_DESIGN.sparc4.lsu.qctl1.st_pcx_rq_all;
wire spc4_mpick = `TOP_DESIGN.sparc4.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc4_apick = `TOP_DESIGN.sparc4.lsu.qctl1.all_pcx_rq_pick;
wire spc4_msquash = `TOP_DESIGN.sparc4.lsu.qctl1.mcycle_squash_d1;
reg spc4_fpicko;
wire [3:0] spc4_fpick;
wire [39:0] spc4_imiss_pa = `TOP_DESIGN.sparc4.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc4_imiss_vld = `TOP_DESIGN.sparc4.lsu.qctl1.imiss_pcx_rq_vld;
reg spc4_imiss_vld_d;
wire [39:0] spc4_lmiss_pa0 = `TOP_DESIGN.sparc4.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc4_lmiss_vld0 = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_pcx_rq_vld;
wire spc4_ld_pkt_vld0 = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_pkt_vld;
wire spc4_st_pkt_vld0 = `TOP_DESIGN.sparc4.lsu.qctl1.st0_pkt_vld;
reg spc4_lmiss_eq0;
reg spc4_atm_imiss_eq0;
wire [39:0] spc4_lmiss_pa1 = `TOP_DESIGN.sparc4.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc4_lmiss_vld1 = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_pcx_rq_vld;
wire spc4_ld_pkt_vld1 = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_pkt_vld;
wire spc4_st_pkt_vld1 = `TOP_DESIGN.sparc4.lsu.qctl1.st1_pkt_vld;
reg spc4_lmiss_eq1;
reg spc4_atm_imiss_eq1;
wire [39:0] spc4_lmiss_pa2 = `TOP_DESIGN.sparc4.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc4_lmiss_vld2 = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_pcx_rq_vld;
wire spc4_ld_pkt_vld2 = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_pkt_vld;
wire spc4_st_pkt_vld2 = `TOP_DESIGN.sparc4.lsu.qctl1.st2_pkt_vld;
reg spc4_lmiss_eq2;
reg spc4_atm_imiss_eq2;
wire [39:0] spc4_lmiss_pa3 = `TOP_DESIGN.sparc4.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc4_lmiss_vld3 = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_pcx_rq_vld;
wire spc4_ld_pkt_vld3 = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_pkt_vld;
wire spc4_st_pkt_vld3 = `TOP_DESIGN.sparc4.lsu.qctl1.st3_pkt_vld;
reg spc4_lmiss_eq3;
reg spc4_atm_imiss_eq3;
wire [44:0] spc4_wdata_ramc = `TOP_DESIGN.sparc4.lsu.stb_cam.wdata_ramc;
wire spc4_wptr_vld = `TOP_DESIGN.sparc4.lsu.stb_cam.wptr_vld;
wire [75:0] spc4_wdata_ramd = {`TOP_DESIGN.sparc4.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc4.lsu.lsu_stb_st_data_g[63:0]};
wire spc4_stb_cam_hit = `TOP_DESIGN.sparc4.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc4_stb_cam_hit_ptr = `TOP_DESIGN.sparc4.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc4_stb_ld_full_raw = `TOP_DESIGN.sparc4.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc4_stb_ld_partial_raw = `TOP_DESIGN.sparc4.lsu.stb_ld_partial_raw[7:0];
wire spc4_stb_cam_mhit = `TOP_DESIGN.sparc4.lsu.stb_cam_mhit;
wire [3:0] spc4_dfq_vld_entries = `TOP_DESIGN.sparc4.lsu.qctl2.dfq_vld_entries;
wire spc4_dfq_full;
reg [9:0] spc4_dfq_full_cntr;
reg spc4_dfq_full_d;
reg spc4_dfq_full_capture;
reg [9:0] spc4_dfq_full_cntr1;
reg spc4_dfq_full_d1;
wire spc4_dfq_full1;
reg spc4_dfq_full_capture1;
reg [9:0] spc4_dfq_full_cntr2;
reg spc4_dfq_full_d2;
wire spc4_dfq_full2;
reg spc4_dfq_full_capture2;
reg [9:0] spc4_dfq_full_cntr3;
reg spc4_dfq_full_d3;
wire spc4_dfq_full3;
reg spc4_dfq_full_capture3;
reg [9:0] spc4_dfq_full_cntr4;
reg spc4_dfq_full_d4;
wire spc4_dfq_full4;
reg spc4_dfq_full_capture4;
reg [9:0] spc4_dfq_full_cntr5;
reg spc4_dfq_full_d5;
wire spc4_dfq_full5;
reg spc4_dfq_full_capture5;
reg [9:0] spc4_dfq_full_cntr6;
reg spc4_dfq_full_d6;
wire spc4_dfq_full6;
reg spc4_dfq_full_capture6;
reg [9:0] spc4_dfq_full_cntr7;
reg spc4_dfq_full_d7;
wire spc4_dfq_full7;
reg spc4_dfq_full_capture7;
wire spc4_dva_rdwrhit;
reg [9:0] spc4_dva_full_cntr;
reg spc4_dva_full_d;
reg spc4_dva_full_capture;
reg spc4_dva_inv;
reg spc4_dva_inv_d;
reg spc4_dva_vld;
reg spc4_dva_vld_d;
reg [9:0] spc4_dva_vfull_cntr;
reg spc4_dva_vfull_d;
reg spc4_dva_vfull_capture;
reg spc4_dva_collide;
reg spc4_dva_vld2lkup;
reg spc4_dva_invld2lkup;
reg spc4_dva_invld_err;
reg [9:0] spc4_dva_efull_cntr;
reg spc4_dva_efull_d;
reg spc4_dva_vlddtag_err;
reg spc4_dva_vlddcache_err;
reg spc4_dva_err;
reg [6:0] spc4_dva_raddr_d;
reg [4:0] spc4_dva_waddr_d;
reg [4:0] spc4_dva_invwaddr_d;
reg spc4_ld0_lt_1;
reg spc4_ld0_lt_2;
reg spc4_ld0_lt_3;
reg spc4_ld1_lt_0;
reg spc4_ld1_lt_2;
reg spc4_ld1_lt_3;
reg spc4_ld2_lt_0;
reg spc4_ld2_lt_1;
reg spc4_ld2_lt_3;
reg spc4_ld3_lt_0;
reg spc4_ld3_lt_1;
reg spc4_ld3_lt_2;
reg spc4_st0_lt_1;
reg spc4_st0_lt_2;
reg spc4_st0_lt_3;
reg spc4_st1_lt_0;
reg spc4_st1_lt_2;
reg spc4_st1_lt_3;
reg spc4_st2_lt_0;
reg spc4_st2_lt_1;
reg spc4_st2_lt_3;
reg spc4_st3_lt_0;
reg spc4_st3_lt_1;
reg spc4_st3_lt_2;
wire [11:0] spc4_ld_ooo_ret;
wire [11:0] spc4_st_ooo_ret;
wire [7:0] spc4_stb_state_vld0 = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc4_stb_state_ack0 = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc4_stb_state_ced0 = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc4_stb_state_rst0 = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_state_rst;
wire spc4_stb_ack_vld0 = `TOP_DESIGN.sparc4.lsu.stb_ctl0.ack_vld;
wire spc4_ld0_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_inst_vld_g;
wire spc4_intrpt0_cmplt = `TOP_DESIGN.sparc4.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc4_stb0_full = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_full;
wire spc4_stb0_full_w2 = `TOP_DESIGN.sparc4.lsu.stb_ctl0.stb_full_w2;
wire spc4_lmq0_full = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_pcx_rq_vld;
wire spc4_mbar_vld0 = `TOP_DESIGN.sparc4.lsu.dctl.mbar_vld0;
wire spc4_ld0_unfilled = `TOP_DESIGN.sparc4.lsu.qctl1.ld0_unfilled;
wire spc4_flsh_vld0 = `TOP_DESIGN.sparc4.lsu.dctl.flsh_vld0;
reg [9:0] spc4_ld0_unf_cntr;
reg spc4_ld0_unfilled_d;
reg [9:0] spc4_st0_unf_cntr;
reg spc4_st0_unfilled_d;
reg spc4_st0_unfilled;
reg spc4_mbar_vld_d0;
reg spc4_flsh_vld_d0;
reg spc4_lmq0_full_d;
reg [9:0] spc4_lmq_full_cntr0;
reg spc4_lmq_full_capture0;
reg [9:0] spc4_stb_full_cntr0;
reg spc4_stb_full_capture0;
reg [9:0] spc4_mbar_vld_cntr0;
reg spc4_mbar_vld_capture0;
reg [9:0] spc4_flsh_vld_cntr0;
reg spc4_flsh_vld_capture0;
reg spc4_stb_head_hit0;
wire spc4_raw_ack_capture0;
reg [9:0] spc4_stb_ack_cntr0;
reg [9:0] spc4_stb_ced_cntr0;
reg spc4_stb_ced0_d;
reg spc4_stb_ced_capture0;
wire spc4_stb_ced0;
reg spc4_atm0_d;
reg [9:0] spc4_atm_cntr0;
reg spc4_atm_intrpt_capture0;
reg spc4_atm_intrpt_b4capture0;
reg spc4_atm_inv_capture0;
reg [39:0] spc4_stb_wr_addr0;
reg [39:0] spc4_stb_atm_addr0;
reg spc4_atm_lmiss_eq0;
wire [7:0] spc4_stb_state_vld1 = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc4_stb_state_ack1 = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc4_stb_state_ced1 = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc4_stb_state_rst1 = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_state_rst;
wire spc4_stb_ack_vld1 = `TOP_DESIGN.sparc4.lsu.stb_ctl1.ack_vld;
wire spc4_ld1_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_inst_vld_g;
wire spc4_intrpt1_cmplt = `TOP_DESIGN.sparc4.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc4_stb1_full = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_full;
wire spc4_stb1_full_w2 = `TOP_DESIGN.sparc4.lsu.stb_ctl1.stb_full_w2;
wire spc4_lmq1_full = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_pcx_rq_vld;
wire spc4_mbar_vld1 = `TOP_DESIGN.sparc4.lsu.dctl.mbar_vld1;
wire spc4_ld1_unfilled = `TOP_DESIGN.sparc4.lsu.qctl1.ld1_unfilled;
wire spc4_flsh_vld1 = `TOP_DESIGN.sparc4.lsu.dctl.flsh_vld1;
reg [9:0] spc4_ld1_unf_cntr;
reg spc4_ld1_unfilled_d;
reg [9:0] spc4_st1_unf_cntr;
reg spc4_st1_unfilled_d;
reg spc4_st1_unfilled;
reg spc4_mbar_vld_d1;
reg spc4_flsh_vld_d1;
reg spc4_lmq1_full_d;
reg [9:0] spc4_lmq_full_cntr1;
reg spc4_lmq_full_capture1;
reg [9:0] spc4_stb_full_cntr1;
reg spc4_stb_full_capture1;
reg [9:0] spc4_mbar_vld_cntr1;
reg spc4_mbar_vld_capture1;
reg [9:0] spc4_flsh_vld_cntr1;
reg spc4_flsh_vld_capture1;
reg spc4_stb_head_hit1;
wire spc4_raw_ack_capture1;
reg [9:0] spc4_stb_ack_cntr1;
reg [9:0] spc4_stb_ced_cntr1;
reg spc4_stb_ced1_d;
reg spc4_stb_ced_capture1;
wire spc4_stb_ced1;
reg spc4_atm1_d;
reg [9:0] spc4_atm_cntr1;
reg spc4_atm_intrpt_capture1;
reg spc4_atm_intrpt_b4capture1;
reg spc4_atm_inv_capture1;
reg [39:0] spc4_stb_wr_addr1;
reg [39:0] spc4_stb_atm_addr1;
reg spc4_atm_lmiss_eq1;
wire [7:0] spc4_stb_state_vld2 = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc4_stb_state_ack2 = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc4_stb_state_ced2 = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc4_stb_state_rst2 = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_state_rst;
wire spc4_stb_ack_vld2 = `TOP_DESIGN.sparc4.lsu.stb_ctl2.ack_vld;
wire spc4_ld2_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_inst_vld_g;
wire spc4_intrpt2_cmplt = `TOP_DESIGN.sparc4.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc4_stb2_full = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_full;
wire spc4_stb2_full_w2 = `TOP_DESIGN.sparc4.lsu.stb_ctl2.stb_full_w2;
wire spc4_lmq2_full = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_pcx_rq_vld;
wire spc4_mbar_vld2 = `TOP_DESIGN.sparc4.lsu.dctl.mbar_vld2;
wire spc4_ld2_unfilled = `TOP_DESIGN.sparc4.lsu.qctl1.ld2_unfilled;
wire spc4_flsh_vld2 = `TOP_DESIGN.sparc4.lsu.dctl.flsh_vld2;
reg [9:0] spc4_ld2_unf_cntr;
reg spc4_ld2_unfilled_d;
reg [9:0] spc4_st2_unf_cntr;
reg spc4_st2_unfilled_d;
reg spc4_st2_unfilled;
reg spc4_mbar_vld_d2;
reg spc4_flsh_vld_d2;
reg spc4_lmq2_full_d;
reg [9:0] spc4_lmq_full_cntr2;
reg spc4_lmq_full_capture2;
reg [9:0] spc4_stb_full_cntr2;
reg spc4_stb_full_capture2;
reg [9:0] spc4_mbar_vld_cntr2;
reg spc4_mbar_vld_capture2;
reg [9:0] spc4_flsh_vld_cntr2;
reg spc4_flsh_vld_capture2;
reg spc4_stb_head_hit2;
wire spc4_raw_ack_capture2;
reg [9:0] spc4_stb_ack_cntr2;
reg [9:0] spc4_stb_ced_cntr2;
reg spc4_stb_ced2_d;
reg spc4_stb_ced_capture2;
wire spc4_stb_ced2;
reg spc4_atm2_d;
reg [9:0] spc4_atm_cntr2;
reg spc4_atm_intrpt_capture2;
reg spc4_atm_intrpt_b4capture2;
reg spc4_atm_inv_capture2;
reg [39:0] spc4_stb_wr_addr2;
reg [39:0] spc4_stb_atm_addr2;
reg spc4_atm_lmiss_eq2;
wire [7:0] spc4_stb_state_vld3 = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc4_stb_state_ack3 = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc4_stb_state_ced3 = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc4_stb_state_rst3 = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_state_rst;
wire spc4_stb_ack_vld3 = `TOP_DESIGN.sparc4.lsu.stb_ctl3.ack_vld;
wire spc4_ld3_inst_vld_g = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_inst_vld_g;
wire spc4_intrpt3_cmplt = `TOP_DESIGN.sparc4.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc4_stb3_full = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_full;
wire spc4_stb3_full_w2 = `TOP_DESIGN.sparc4.lsu.stb_ctl3.stb_full_w2;
wire spc4_lmq3_full = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_pcx_rq_vld;
wire spc4_mbar_vld3 = `TOP_DESIGN.sparc4.lsu.dctl.mbar_vld3;
wire spc4_ld3_unfilled = `TOP_DESIGN.sparc4.lsu.qctl1.ld3_unfilled;
wire spc4_flsh_vld3 = `TOP_DESIGN.sparc4.lsu.dctl.flsh_vld3;
reg [9:0] spc4_ld3_unf_cntr;
reg spc4_ld3_unfilled_d;
reg [9:0] spc4_st3_unf_cntr;
reg spc4_st3_unfilled_d;
reg spc4_st3_unfilled;
reg spc4_mbar_vld_d3;
reg spc4_flsh_vld_d3;
reg spc4_lmq3_full_d;
reg [9:0] spc4_lmq_full_cntr3;
reg spc4_lmq_full_capture3;
reg [9:0] spc4_stb_full_cntr3;
reg spc4_stb_full_capture3;
reg [9:0] spc4_mbar_vld_cntr3;
reg spc4_mbar_vld_capture3;
reg [9:0] spc4_flsh_vld_cntr3;
reg spc4_flsh_vld_capture3;
reg spc4_stb_head_hit3;
wire spc4_raw_ack_capture3;
reg [9:0] spc4_stb_ack_cntr3;
reg [9:0] spc4_stb_ced_cntr3;
reg spc4_stb_ced3_d;
reg spc4_stb_ced_capture3;
wire spc4_stb_ced3;
reg spc4_atm3_d;
reg [9:0] spc4_atm_cntr3;
reg spc4_atm_intrpt_capture3;
reg spc4_atm_intrpt_b4capture3;
reg spc4_atm_inv_capture3;
reg [39:0] spc4_stb_wr_addr3;
reg [39:0] spc4_stb_atm_addr3;
reg spc4_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc4_fpick = {spc4_mpick,spc4_spick,spc4_lpick,spc4_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc4_msquash,spc4_apick,spc4_fpick})
9'b000000000 : spc4_fpicko = 1'b0;
9'b0xxx1xxx1 : spc4_fpicko = 1'b0;
9'b1xxxxxxxx : spc4_fpicko = 1'b0;
9'b0xxx0xxx0 : spc4_fpicko = 1'b0;
default:
begin
spc4_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon4 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc4_exu_und = {spc4_l2,
spc4_unc,
spc4_fpld,
spc4_fpldst,
spc4_unflush,
spc4_ldw,
spc4_byp,
spc4_flsh,
spc4_chm,
spc4_ldxa,
spc4_ato,
spc4_pref,
spc4_chit,
spc4_dcp,
spc4_dtp,
spc4_mpc,
spc4_mpu};
always @(spc4_exu_und)
begin
case (spc4_exu_und)
17'h00000 : spc4_exu = 5'h00;
17'h00001 : spc4_exu = 5'h01;
17'h00002 : spc4_exu = 5'h02;
17'h00004 : spc4_exu = 5'h03;
17'h00008 : spc4_exu = 5'h04;
17'h00010 : spc4_exu = 5'h05;
17'h00020 : spc4_exu = 5'h06;
17'h00040 : spc4_exu = 5'h07;
17'h00080 : spc4_exu = 5'h08;
17'h00100 : spc4_exu = 5'h09;
17'h00200 : spc4_exu = 5'h0a;
17'h00400 : spc4_exu = 5'h0b;
17'h00800 : spc4_exu = 5'h0c;
17'h01000 : spc4_exu = 5'h0d;
17'h02000 : spc4_exu = 5'h0e;
17'h04000 : spc4_exu = 5'h0f;
17'h08000 : spc4_exu = 5'h10;
17'h10000 : spc4_exu = 5'h11;
default: spc4_exu = 5'h12;
endcase
end
//excp
assign spc4_exp_und = {spc4_exp_wtchpt_trp_g,
spc4_exp_misalign_addr_ldst_atm_m,
spc4_exp_priv_violtn_g,
spc4_exp_daccess_excptn_g,
spc4_exp_daccess_prot_g,
spc4_exp_priv_action_g,
spc4_exp_spec_access_epage_g,
spc4_exp_uncache_atomic_g,
spc4_exp_illegal_asi_action_g,
spc4_exp_flt_ld_nfo_pg_g,
spc4_exp_asi_rd_unc,
spc4_exp_tlb_data_ce,
spc4_exp_tlb_data_ue,
spc4_exp_tlb_tag_ue,
spc4_exp_unc,
spc4_exp_corr};
always @(spc4_exp_und)
begin
case (spc4_exp_und)
16'h0000 : spc4_exp = 5'h00;
16'h0001 : spc4_exp = 5'h01;
16'h0002 : spc4_exp = 5'h02;
16'h0004 : spc4_exp = 5'h03;
16'h0008 : spc4_exp = 5'h04;
16'h0010 : spc4_exp = 5'h05;
16'h0020 : spc4_exp = 5'h06;
16'h0040 : spc4_exp = 5'h07;
16'h0080 : spc4_exp = 5'h08;
16'h0100 : spc4_exp = 5'h09;
16'h0200 : spc4_exp = 5'h0a;
16'h0400 : spc4_exp = 5'h0b;
16'h0800 : spc4_exp = 5'h0c;
16'h1000 : spc4_exp = 5'h0d;
16'h2000 : spc4_exp = 5'h0e;
16'h4000 : spc4_exp = 5'h0f;
16'h8000 : spc4_exp = 5'h10;
default: spc4_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc4_dctl_stxa_cmplt0 = ((spc4_dctl_stxa_internal_d2 & spc4_dctl_thread0_w3) |
spc4_dctl_stxa_stall_wr_cmplt0_d1);
assign spc4_dctl_l2fill_cmplt0 = (((spc4_dctl_lsu_l2fill_vld & ~spc4_dctl_atomic_ld_squash_e &
~spc4_dctl_lsu_ignore_fill)) & ~spc4_dctl_l2fill_fpld_e &
~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread0);
assign spc4_dctl_fillerr0 = spc4_dctl_l2_corr_error_e & spc4_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc4_dctl_atm_cmplt0 = (spc4_dctl_lsu_atm_st_cmplt_e & ~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread0);
assign spc4_dctl_ldst_cond_cmplt0 = { spc4_dctl_stxa_cmplt0, spc4_dctl_l2fill_cmplt0,
spc4_dctl_atomic_ld_squash_e, spc4_dctl_intld_byp_cmplt[0],
spc4_dctl_bsync0_reset, spc4_dctl_lsu_intrpt_cmplt[0]
};
assign spc4_cmplt0 = { spc4_dctl_ldxa_illgl_va_cmplt_d1, spc4_dctl_pref_tlbmiss_cmplt_d2,
spc4_dctl_lsu_pcx_pref_issue, spc4_dctl_diag_wr_cmplt0, spc4_dctl_l2fill_fpld_e};
always @(spc4_cmplt0 or spc4_dctl_ldst_cond_cmplt0)
begin
case ({spc4_dctl_fillerr0,spc4_dctl_ldst_cond_cmplt0,spc4_cmplt0})
12'h000 : spc4_ldstcond_cmplt0 = 4'h0;
12'h001 : spc4_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc4_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc4_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc4_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc4_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc4_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc4_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc4_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc4_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc4_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc4_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc4_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc4_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc4_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc4_dctl_stxa_cmplt1 = ((spc4_dctl_stxa_internal_d2 & spc4_dctl_thread1_w3) |
spc4_dctl_stxa_stall_wr_cmplt1_d1);
assign spc4_dctl_l2fill_cmplt1 = (((spc4_dctl_lsu_l2fill_vld & ~spc4_dctl_atomic_ld_squash_e &
~spc4_dctl_lsu_ignore_fill)) & ~spc4_dctl_l2fill_fpld_e &
~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread1);
assign spc4_dctl_fillerr1 = spc4_dctl_l2_corr_error_e & spc4_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc4_dctl_atm_cmplt1 = (spc4_dctl_lsu_atm_st_cmplt_e & ~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread1);
assign spc4_dctl_ldst_cond_cmplt1 = { spc4_dctl_stxa_cmplt1, spc4_dctl_l2fill_cmplt1,
spc4_dctl_atomic_ld_squash_e, spc4_dctl_intld_byp_cmplt[1],
spc4_dctl_bsync1_reset, spc4_dctl_lsu_intrpt_cmplt[1]
};
assign spc4_cmplt1 = { spc4_dctl_ldxa_illgl_va_cmplt_d1, spc4_dctl_pref_tlbmiss_cmplt_d2,
spc4_dctl_lsu_pcx_pref_issue, spc4_dctl_diag_wr_cmplt1, spc4_dctl_l2fill_fpld_e};
always @(spc4_cmplt1 or spc4_dctl_ldst_cond_cmplt1)
begin
case ({spc4_dctl_fillerr1,spc4_dctl_ldst_cond_cmplt1,spc4_cmplt1})
12'h000 : spc4_ldstcond_cmplt1 = 4'h0;
12'h001 : spc4_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc4_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc4_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc4_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc4_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc4_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc4_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc4_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc4_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc4_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc4_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc4_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc4_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc4_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc4_dctl_stxa_cmplt2 = ((spc4_dctl_stxa_internal_d2 & spc4_dctl_thread2_w3) |
spc4_dctl_stxa_stall_wr_cmplt2_d1);
assign spc4_dctl_l2fill_cmplt2 = (((spc4_dctl_lsu_l2fill_vld & ~spc4_dctl_atomic_ld_squash_e &
~spc4_dctl_lsu_ignore_fill)) & ~spc4_dctl_l2fill_fpld_e &
~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread2);
assign spc4_dctl_fillerr2 = spc4_dctl_l2_corr_error_e & spc4_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc4_dctl_atm_cmplt2 = (spc4_dctl_lsu_atm_st_cmplt_e & ~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread2);
assign spc4_dctl_ldst_cond_cmplt2 = { spc4_dctl_stxa_cmplt2, spc4_dctl_l2fill_cmplt2,
spc4_dctl_atomic_ld_squash_e, spc4_dctl_intld_byp_cmplt[2],
spc4_dctl_bsync2_reset, spc4_dctl_lsu_intrpt_cmplt[2]
};
assign spc4_cmplt2 = { spc4_dctl_ldxa_illgl_va_cmplt_d1, spc4_dctl_pref_tlbmiss_cmplt_d2,
spc4_dctl_lsu_pcx_pref_issue, spc4_dctl_diag_wr_cmplt2, spc4_dctl_l2fill_fpld_e};
always @(spc4_cmplt2 or spc4_dctl_ldst_cond_cmplt2)
begin
case ({spc4_dctl_fillerr2,spc4_dctl_ldst_cond_cmplt2,spc4_cmplt2})
12'h000 : spc4_ldstcond_cmplt2 = 4'h0;
12'h001 : spc4_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc4_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc4_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc4_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc4_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc4_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc4_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc4_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc4_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc4_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc4_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc4_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc4_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc4_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc4_dctl_stxa_cmplt3 = ((spc4_dctl_stxa_internal_d2 & spc4_dctl_thread3_w3) |
spc4_dctl_stxa_stall_wr_cmplt3_d1);
assign spc4_dctl_l2fill_cmplt3 = (((spc4_dctl_lsu_l2fill_vld & ~spc4_dctl_atomic_ld_squash_e &
~spc4_dctl_lsu_ignore_fill)) & ~spc4_dctl_l2fill_fpld_e &
~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread3);
assign spc4_dctl_fillerr3 = spc4_dctl_l2_corr_error_e & spc4_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc4_dctl_atm_cmplt3 = (spc4_dctl_lsu_atm_st_cmplt_e & ~spc4_dctl_fill_err_trap_e & spc4_dctl_dfill_thread3);
assign spc4_dctl_ldst_cond_cmplt3 = { spc4_dctl_stxa_cmplt3, spc4_dctl_l2fill_cmplt3,
spc4_dctl_atomic_ld_squash_e, spc4_dctl_intld_byp_cmplt[3],
spc4_dctl_bsync3_reset, spc4_dctl_lsu_intrpt_cmplt[3]
};
assign spc4_cmplt3 = { spc4_dctl_ldxa_illgl_va_cmplt_d1, spc4_dctl_pref_tlbmiss_cmplt_d2,
spc4_dctl_lsu_pcx_pref_issue, spc4_dctl_diag_wr_cmplt3, spc4_dctl_l2fill_fpld_e};
always @(spc4_cmplt3 or spc4_dctl_ldst_cond_cmplt3)
begin
case ({spc4_dctl_fillerr3,spc4_dctl_ldst_cond_cmplt3,spc4_cmplt3})
12'h000 : spc4_ldstcond_cmplt3 = 4'h0;
12'h001 : spc4_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc4_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc4_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc4_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc4_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc4_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc4_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc4_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc4_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc4_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc4_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc4_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc4_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc4_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc4_ldstcond_cmplt0 or spc4_ldstcond_cmplt1 or spc4_ldstcond_cmplt2
or spc4_ldstcond_cmplt3 or spc4_dctl_lsu_ifu_ldst_cmplt
or spc4_dctl_late_cmplt0 or spc4_dctl_late_cmplt1 or spc4_dctl_late_cmplt2 or spc4_dctl_late_cmplt3)
begin
case (spc4_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc4_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc4_ldstcond_cmplt_d = spc4_dctl_late_cmplt0 ? spc4_ldstcond_cmplt0_d : spc4_ldstcond_cmplt0;
4'b0010 : spc4_ldstcond_cmplt_d = spc4_dctl_late_cmplt1 ? spc4_ldstcond_cmplt1_d : spc4_ldstcond_cmplt1;
4'b0100 : spc4_ldstcond_cmplt_d = spc4_dctl_late_cmplt2 ? spc4_ldstcond_cmplt2_d : spc4_ldstcond_cmplt2;
4'b1000 : spc4_ldstcond_cmplt_d = spc4_dctl_late_cmplt3 ? spc4_ldstcond_cmplt3_d : spc4_ldstcond_cmplt3;
4'b0011 : spc4_ldstcond_cmplt_d = 4'he;
4'b0101 : spc4_ldstcond_cmplt_d = 4'he;
4'b1001 : spc4_ldstcond_cmplt_d = 4'he;
4'b0110 : spc4_ldstcond_cmplt_d = 4'he;
4'b1010 : spc4_ldstcond_cmplt_d = 4'he;
4'b1100 : spc4_ldstcond_cmplt_d = 4'he;
default:
begin
spc4_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc4_st_ooo_ret = { spc4_st0_lt_1, spc4_st0_lt_2, spc4_st0_lt_3,
spc4_st1_lt_0, spc4_st1_lt_2, spc4_st1_lt_3,
spc4_st2_lt_0, spc4_st2_lt_1, spc4_st2_lt_3,
spc4_st3_lt_0, spc4_st3_lt_1, spc4_st3_lt_2};
always @(posedge clk)
begin
if(~spc4_st0_unfilled || ~rst_l)
spc4_st0_unfilled_d <= 1'b0;
else
spc4_st0_unfilled_d <= spc4_st0_unfilled;
if(~rst_l)
spc4_ldstcond_cmplt0_d <= 4'h0;
else
spc4_ldstcond_cmplt0_d <= spc4_ldstcond_cmplt0;
if(~spc4_ld0_pkt_vld_unmasked || ~rst_l)
spc4_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc4_ld0_pkt_vld_unmasked_d <= spc4_ld0_pkt_vld_unmasked;
if(~rst_l)
spc4_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc4_qctl1_ld_sec_hit_thrd0 && spc4_qctl1_ld0_inst_vld_g)
spc4_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc4_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc4_st1_unfilled || ~rst_l)
spc4_st1_unfilled_d <= 1'b0;
else
spc4_st1_unfilled_d <= spc4_st1_unfilled;
if(~rst_l)
spc4_ldstcond_cmplt1_d <= 4'h0;
else
spc4_ldstcond_cmplt1_d <= spc4_ldstcond_cmplt1;
if(~spc4_ld1_pkt_vld_unmasked || ~rst_l)
spc4_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc4_ld1_pkt_vld_unmasked_d <= spc4_ld1_pkt_vld_unmasked;
if(~rst_l)
spc4_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc4_qctl1_ld_sec_hit_thrd1 && spc4_qctl1_ld1_inst_vld_g)
spc4_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc4_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc4_st2_unfilled || ~rst_l)
spc4_st2_unfilled_d <= 1'b0;
else
spc4_st2_unfilled_d <= spc4_st2_unfilled;
if(~rst_l)
spc4_ldstcond_cmplt2_d <= 4'h0;
else
spc4_ldstcond_cmplt2_d <= spc4_ldstcond_cmplt2;
if(~spc4_ld2_pkt_vld_unmasked || ~rst_l)
spc4_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc4_ld2_pkt_vld_unmasked_d <= spc4_ld2_pkt_vld_unmasked;
if(~rst_l)
spc4_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc4_qctl1_ld_sec_hit_thrd2 && spc4_qctl1_ld2_inst_vld_g)
spc4_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc4_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc4_st3_unfilled || ~rst_l)
spc4_st3_unfilled_d <= 1'b0;
else
spc4_st3_unfilled_d <= spc4_st3_unfilled;
if(~rst_l)
spc4_ldstcond_cmplt3_d <= 4'h0;
else
spc4_ldstcond_cmplt3_d <= spc4_ldstcond_cmplt3;
if(~spc4_ld3_pkt_vld_unmasked || ~rst_l)
spc4_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc4_ld3_pkt_vld_unmasked_d <= spc4_ld3_pkt_vld_unmasked;
if(~rst_l)
spc4_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc4_qctl1_ld_sec_hit_thrd3 && spc4_qctl1_ld3_inst_vld_g)
spc4_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc4_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc4_stb_state_ced0) && (|spc4_stb_state_rst0)) || ~rst_l)
spc4_st0_unfilled <= 1'b0;
else if( ((|spc4_stb_state_ced0) && ~(|spc4_stb_state_rst0)))
spc4_st0_unfilled <= 1'b1;
else
spc4_st0_unfilled <= spc4_st0_unfilled;
if( ((|spc4_stb_state_ced1) && (|spc4_stb_state_rst1)) || ~rst_l)
spc4_st1_unfilled <= 1'b0;
else if( ((|spc4_stb_state_ced1) && ~(|spc4_stb_state_rst1)))
spc4_st1_unfilled <= 1'b1;
else
spc4_st1_unfilled <= spc4_st1_unfilled;
if( ((|spc4_stb_state_ced2) && (|spc4_stb_state_rst2)) || ~rst_l)
spc4_st2_unfilled <= 1'b0;
else if( ((|spc4_stb_state_ced2) && ~(|spc4_stb_state_rst2)))
spc4_st2_unfilled <= 1'b1;
else
spc4_st2_unfilled <= spc4_st2_unfilled;
if( ((|spc4_stb_state_ced3) && (|spc4_stb_state_rst3)) || ~rst_l)
spc4_st3_unfilled <= 1'b0;
else if( ((|spc4_stb_state_ced3) && ~(|spc4_stb_state_rst3)))
spc4_st3_unfilled <= 1'b1;
else
spc4_st3_unfilled <= spc4_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc4_st0_unfilled && spc4_st0_unfilled_d)|| ~rst_l)
begin
spc4_st0_unf_cntr <= 9'h000;
end
else if(spc4_st0_unfilled)
begin
spc4_st0_unf_cntr <= spc4_st0_unf_cntr + 1;
end
else
begin
spc4_st0_unf_cntr <= spc4_st0_unf_cntr;
end
if((~spc4_st1_unfilled && spc4_st1_unfilled_d)|| ~rst_l)
begin
spc4_st1_unf_cntr <= 9'h000;
end
else if(spc4_st1_unfilled)
begin
spc4_st1_unf_cntr <= spc4_st1_unf_cntr + 1;
end
else
begin
spc4_st1_unf_cntr <= spc4_st1_unf_cntr;
end
if((~spc4_st2_unfilled && spc4_st2_unfilled_d)|| ~rst_l)
begin
spc4_st2_unf_cntr <= 9'h000;
end
else if(spc4_st2_unfilled)
begin
spc4_st2_unf_cntr <= spc4_st2_unf_cntr + 1;
end
else
begin
spc4_st2_unf_cntr <= spc4_st2_unf_cntr;
end
if((~spc4_st3_unfilled && spc4_st3_unfilled_d)|| ~rst_l)
begin
spc4_st3_unf_cntr <= 9'h000;
end
else if(spc4_st3_unfilled)
begin
spc4_st3_unf_cntr <= spc4_st3_unf_cntr + 1;
end
else
begin
spc4_st3_unf_cntr <= spc4_st3_unf_cntr;
end
end
always @(spc4_st0_unfilled or spc4_st1_unfilled or spc4_st2_unfilled or spc4_st3_unfilled
or spc4_st0_unfilled_d or spc4_st1_unfilled_d or spc4_st2_unfilled_d or spc4_st3_unfilled_d)
begin
if(~spc4_st0_unfilled && spc4_st0_unfilled_d && spc4_st1_unfilled)
spc4_st0_lt_1 <= (spc4_st1_unf_cntr > spc4_st0_unf_cntr);
else
spc4_st0_lt_1 <= 1'b0;
if(~spc4_st0_unfilled && spc4_st0_unfilled_d && spc4_st2_unfilled)
spc4_st0_lt_2 <= (spc4_st2_unf_cntr > spc4_st0_unf_cntr);
else
spc4_st0_lt_2 <= 1'b0;
if(~spc4_st0_unfilled && spc4_st0_unfilled_d && spc4_st3_unfilled)
spc4_st0_lt_3 <= (spc4_st3_unf_cntr > spc4_st0_unf_cntr);
else
spc4_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc4_st1_unfilled && spc4_st1_unfilled_d && spc4_st0_unfilled)
spc4_st1_lt_0 <= (spc4_st0_unf_cntr > spc4_st1_unf_cntr);
else
spc4_st1_lt_0 <= 1'b0;
if(~spc4_st1_unfilled && spc4_st1_unfilled_d && spc4_st2_unfilled)
spc4_st1_lt_2 <= (spc4_st2_unf_cntr > spc4_st1_unf_cntr);
else
spc4_st1_lt_2 <= 1'b0;
if(~spc4_st1_unfilled && spc4_st1_unfilled_d && spc4_st3_unfilled)
spc4_st1_lt_3 <= (spc4_st3_unf_cntr > spc4_st1_unf_cntr);
else
spc4_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc4_st2_unfilled && spc4_st2_unfilled_d && spc4_st0_unfilled)
spc4_st2_lt_0 <= (spc4_st0_unf_cntr > spc4_st2_unf_cntr);
else
spc4_st2_lt_0 <= 1'b0;
if(~spc4_st2_unfilled && spc4_st2_unfilled_d && spc4_st1_unfilled)
spc4_st2_lt_1 <= (spc4_st1_unf_cntr > spc4_st2_unf_cntr);
else
spc4_st2_lt_1 <= 1'b0;
if(~spc4_st2_unfilled && spc4_st2_unfilled_d && spc4_st3_unfilled)
spc4_st2_lt_3 <= (spc4_st3_unf_cntr > spc4_st2_unf_cntr);
else
spc4_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc4_st3_unfilled && spc4_st3_unfilled_d && spc4_st0_unfilled)
spc4_st3_lt_0 <= (spc4_st0_unf_cntr > spc4_st3_unf_cntr);
else
spc4_st3_lt_0 <= 1'b0;
if(~spc4_st3_unfilled && spc4_st3_unfilled_d && spc4_st1_unfilled)
spc4_st3_lt_1 <= (spc4_st1_unf_cntr > spc4_st3_unf_cntr);
else
spc4_st3_lt_1 <= 1'b0;
if(~spc4_st3_unfilled && spc4_st3_unfilled_d && spc4_st2_unfilled)
spc4_st3_lt_2 <= (spc4_st2_unf_cntr > spc4_st3_unf_cntr);
else
spc4_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc4_ld_ooo_ret = { spc4_ld0_lt_1, spc4_ld0_lt_2, spc4_ld0_lt_3,
spc4_ld1_lt_0, spc4_ld1_lt_2, spc4_ld1_lt_3,
spc4_ld2_lt_0, spc4_ld2_lt_1, spc4_ld2_lt_3,
spc4_ld3_lt_0, spc4_ld3_lt_1, spc4_ld3_lt_2};
always @(posedge clk)
begin
if((~spc4_ld0_unfilled && spc4_ld0_unfilled_d)|| ~rst_l)
begin
spc4_ld0_unf_cntr <= 9'h000;
end
else if(spc4_ld0_unfilled)
begin
spc4_ld0_unf_cntr <= spc4_ld0_unf_cntr + 1;
end
else
begin
spc4_ld0_unf_cntr <= spc4_ld0_unf_cntr;
end
if((~spc4_ld1_unfilled && spc4_ld1_unfilled_d)|| ~rst_l)
begin
spc4_ld1_unf_cntr <= 9'h000;
end
else if(spc4_ld1_unfilled)
begin
spc4_ld1_unf_cntr <= spc4_ld1_unf_cntr + 1;
end
else
begin
spc4_ld1_unf_cntr <= spc4_ld1_unf_cntr;
end
if((~spc4_ld2_unfilled && spc4_ld2_unfilled_d)|| ~rst_l)
begin
spc4_ld2_unf_cntr <= 9'h000;
end
else if(spc4_ld2_unfilled)
begin
spc4_ld2_unf_cntr <= spc4_ld2_unf_cntr + 1;
end
else
begin
spc4_ld2_unf_cntr <= spc4_ld2_unf_cntr;
end
if((~spc4_ld3_unfilled && spc4_ld3_unfilled_d)|| ~rst_l)
begin
spc4_ld3_unf_cntr <= 9'h000;
end
else if(spc4_ld3_unfilled)
begin
spc4_ld3_unf_cntr <= spc4_ld3_unf_cntr + 1;
end
else
begin
spc4_ld3_unf_cntr <= spc4_ld3_unf_cntr;
end
end
always @(spc4_ld0_unfilled or spc4_ld1_unfilled or spc4_ld2_unfilled or spc4_ld3_unfilled
or spc4_ld0_unfilled_d or spc4_ld1_unfilled_d or spc4_ld2_unfilled_d or spc4_ld3_unfilled_d)
begin
if(~spc4_ld0_unfilled && spc4_ld0_unfilled_d && spc4_ld1_unfilled)
spc4_ld0_lt_1 <= (spc4_ld1_unf_cntr > spc4_ld0_unf_cntr);
else
spc4_ld0_lt_1 <= 1'b0;
if(~spc4_ld0_unfilled && spc4_ld0_unfilled_d && spc4_ld2_unfilled)
spc4_ld0_lt_2 <= (spc4_ld2_unf_cntr > spc4_ld0_unf_cntr);
else
spc4_ld0_lt_2 <= 1'b0;
if(~spc4_ld0_unfilled && spc4_ld0_unfilled_d && spc4_ld3_unfilled)
spc4_ld0_lt_3 <= (spc4_ld3_unf_cntr > spc4_ld0_unf_cntr);
else
spc4_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc4_ld1_unfilled && spc4_ld1_unfilled_d && spc4_ld0_unfilled)
spc4_ld1_lt_0 <= (spc4_ld0_unf_cntr > spc4_ld1_unf_cntr);
else
spc4_ld1_lt_0 <= 1'b0;
if(~spc4_ld1_unfilled && spc4_ld1_unfilled_d && spc4_ld2_unfilled)
spc4_ld1_lt_2 <= (spc4_ld2_unf_cntr > spc4_ld1_unf_cntr);
else
spc4_ld1_lt_2 <= 1'b0;
if(~spc4_ld1_unfilled && spc4_ld1_unfilled_d && spc4_ld3_unfilled)
spc4_ld1_lt_3 <= (spc4_ld3_unf_cntr > spc4_ld1_unf_cntr);
else
spc4_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc4_ld2_unfilled && spc4_ld2_unfilled_d && spc4_ld0_unfilled)
spc4_ld2_lt_0 <= (spc4_ld0_unf_cntr > spc4_ld2_unf_cntr);
else
spc4_ld2_lt_0 <= 1'b0;
if(~spc4_ld2_unfilled && spc4_ld2_unfilled_d && spc4_ld1_unfilled)
spc4_ld2_lt_1 <= (spc4_ld1_unf_cntr > spc4_ld2_unf_cntr);
else
spc4_ld2_lt_1 <= 1'b0;
if(~spc4_ld2_unfilled && spc4_ld2_unfilled_d && spc4_ld3_unfilled)
spc4_ld2_lt_3 <= (spc4_ld3_unf_cntr > spc4_ld2_unf_cntr);
else
spc4_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc4_ld3_unfilled && spc4_ld3_unfilled_d && spc4_ld0_unfilled)
spc4_ld3_lt_0 <= (spc4_ld0_unf_cntr > spc4_ld3_unf_cntr);
else
spc4_ld3_lt_0 <= 1'b0;
if(~spc4_ld3_unfilled && spc4_ld3_unfilled_d && spc4_ld1_unfilled)
spc4_ld3_lt_1 <= (spc4_ld1_unf_cntr > spc4_ld3_unf_cntr);
else
spc4_ld3_lt_1 <= 1'b0;
if(~spc4_ld3_unfilled && spc4_ld3_unfilled_d && spc4_ld2_unfilled)
spc4_ld3_lt_2 <= (spc4_ld2_unf_cntr > spc4_ld3_unf_cntr);
else
spc4_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc4_dctl_bld_hit =
((|spc4_dctl_lsu_way_hit[3:0]) & spc4_dctl_dcache_enable_g &
~spc4_dctl_ldxa_internal & ~spc4_dctl_dcache_rd_parity_error & ~spc4_dctl_dtag_perror_g &
~spc4_dctl_endian_mispred_g &
~spc4_dctl_atomic_g & ~spc4_dctl_ncache_asild_rq_g) & ~spc4_dctl_tte_data_perror_unc &
spc4_dctl_ld_inst_vld_g & spc4_qctl1_bld_g ;
assign spc4_dctl_bld_stb_hit = spc4_dctl_bld_hit & spc4_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc4_bld0_full_d <= 2'b00;
spc4_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc4_bld0_full_d <= spc4_qctl1_bld_cnt;
spc4_ld0_unfilled_d <= spc4_ld0_unfilled;
end
if(~rst_l)
begin
spc4_bld1_full_d <= 2'b00;
spc4_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc4_bld1_full_d <= spc4_qctl1_bld_cnt;
spc4_ld1_unfilled_d <= spc4_ld1_unfilled;
end
if(~rst_l)
begin
spc4_bld2_full_d <= 2'b00;
spc4_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc4_bld2_full_d <= spc4_qctl1_bld_cnt;
spc4_ld2_unfilled_d <= spc4_ld2_unfilled;
end
if(~rst_l)
begin
spc4_bld3_full_d <= 2'b00;
spc4_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc4_bld3_full_d <= spc4_qctl1_bld_cnt;
spc4_ld3_unfilled_d <= spc4_ld3_unfilled;
end
end
always @(spc4_bld0_full_d or spc4_qctl1_bld_cnt)
begin
if( (spc4_bld0_full_d != spc4_qctl1_bld_cnt) && (spc4_bld0_full_d == 2'd0))
spc4_bld0_full_capture <= 1'b1;
else
spc4_bld0_full_capture <= 1'b0;
end
always @(spc4_bld1_full_d or spc4_qctl1_bld_cnt)
begin
if( (spc4_bld1_full_d != spc4_qctl1_bld_cnt) && (spc4_bld1_full_d == 2'd1))
spc4_bld1_full_capture <= 1'b1;
else
spc4_bld1_full_capture <= 1'b0;
end
always @(spc4_bld2_full_d or spc4_qctl1_bld_cnt)
begin
if( (spc4_bld2_full_d != spc4_qctl1_bld_cnt) && (spc4_bld2_full_d == 2'd2))
spc4_bld2_full_capture <= 1'b1;
else
spc4_bld2_full_capture <= 1'b0;
end
always @(spc4_bld3_full_d or spc4_qctl1_bld_cnt)
begin
if( (spc4_bld3_full_d != spc4_qctl1_bld_cnt) && (spc4_bld3_full_d == 2'd3))
spc4_bld3_full_capture <= 1'b1;
else
spc4_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc4_qctl1_bld_cnt != 2'b00) && (spc4_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc4_bld0_full_cntr <= 9'h000;
end
else if(spc4_qctl1_bld_g && (spc4_qctl1_bld_cnt == 2'b00))
begin
spc4_bld0_full_cntr <= spc4_bld0_full_cntr + 1;
end
else if( (spc4_qctl1_bld_cnt == 2'b00) && (spc4_bld0_full_cntr != 9'h000))
begin
spc4_bld0_full_cntr <= spc4_bld0_full_cntr + 1;
end
else
begin
spc4_bld0_full_cntr <= spc4_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc4_qctl1_bld_cnt != 2'b01) && (spc4_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc4_bld1_full_cntr <= 9'h000;
end
else if(spc4_qctl1_bld_cnt == 2'b01)
begin
spc4_bld1_full_cntr <= spc4_bld1_full_cntr + 1;
end
else if( (spc4_qctl1_bld_cnt == 2'b01) && (spc4_bld1_full_cntr != 9'h000))
begin
spc4_bld1_full_cntr <= spc4_bld1_full_cntr + 1;
end
else
begin
spc4_bld1_full_cntr <= spc4_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc4_qctl1_bld_cnt != 2'b10) && (spc4_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc4_bld2_full_cntr <= 9'h000;
end
else if(spc4_qctl1_bld_cnt == 2'b10)
begin
spc4_bld2_full_cntr <= spc4_bld2_full_cntr + 1;
end
else if( (spc4_qctl1_bld_cnt == 2'b10) && (spc4_bld2_full_cntr != 9'h000))
begin
spc4_bld2_full_cntr <= spc4_bld2_full_cntr + 1;
end
else
begin
spc4_bld2_full_cntr <= spc4_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc4_qctl1_bld_cnt != 2'b11) && (spc4_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc4_bld3_full_cntr <= 9'h000;
end
else if(spc4_qctl1_bld_cnt == 2'b11)
begin
spc4_bld3_full_cntr <= spc4_bld3_full_cntr + 1;
end
else if( (spc4_qctl1_bld_cnt == 2'b11) && (spc4_bld3_full_cntr != 9'h000))
begin
spc4_bld3_full_cntr <= spc4_bld3_full_cntr + 1;
end
else
begin
spc4_bld3_full_cntr <= spc4_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc4_stb_state_vld0) && ~spc4_atomic_g) || ~rst_l)
begin
spc4_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc4_atomic_g && (spc4_atm_type0 != 8'h00) && spc4_wptr_vld)
begin
spc4_stb_atm_addr0 <= {spc4_wdata_ramc[44:9],spc4_wdata_ramd[67:64]};
end
else
begin
spc4_stb_atm_addr0 <= spc4_stb_atm_addr0;
end
if( ( ~(|spc4_stb_state_vld1) && ~spc4_atomic_g) || ~rst_l)
begin
spc4_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc4_atomic_g && (spc4_atm_type1 != 8'h00) && spc4_wptr_vld)
begin
spc4_stb_atm_addr1 <= {spc4_wdata_ramc[44:9],spc4_wdata_ramd[67:64]};
end
else
begin
spc4_stb_atm_addr1 <= spc4_stb_atm_addr1;
end
if( ( ~(|spc4_stb_state_vld2) && ~spc4_atomic_g) || ~rst_l)
begin
spc4_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc4_atomic_g && (spc4_atm_type2 != 8'h00) && spc4_wptr_vld)
begin
spc4_stb_atm_addr2 <= {spc4_wdata_ramc[44:9],spc4_wdata_ramd[67:64]};
end
else
begin
spc4_stb_atm_addr2 <= spc4_stb_atm_addr2;
end
if( ( ~(|spc4_stb_state_vld3) && ~spc4_atomic_g) || ~rst_l)
begin
spc4_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc4_atomic_g && (spc4_atm_type3 != 8'h00) && spc4_wptr_vld)
begin
spc4_stb_atm_addr3 <= {spc4_wdata_ramc[44:9],spc4_wdata_ramd[67:64]};
end
else
begin
spc4_stb_atm_addr3 <= spc4_stb_atm_addr3;
end
end
assign spc4_dfq_full = (spc4_dfq_vld_entries >= 3'd4);
assign spc4_dfq_full1 = (spc4_dfq_vld_entries >= (3'd4 + 1));
always @(spc4_dfq_full_d1 or spc4_dfq_full1)
begin
if (spc4_dfq_full_d1 && ~spc4_dfq_full1)
spc4_dfq_full_capture1 <= 1'b1;
else
spc4_dfq_full_capture1 <= 1'b0;
end
assign spc4_dfq_full2 = (spc4_dfq_vld_entries >= (3'd4 + 2));
always @(spc4_dfq_full_d2 or spc4_dfq_full2)
begin
if (spc4_dfq_full_d2 && ~spc4_dfq_full2)
spc4_dfq_full_capture2 <= 1'b1;
else
spc4_dfq_full_capture2 <= 1'b0;
end
assign spc4_dfq_full3 = (spc4_dfq_vld_entries >= (3'd4 + 3));
always @(spc4_dfq_full_d3 or spc4_dfq_full3)
begin
if (spc4_dfq_full_d3 && ~spc4_dfq_full3)
spc4_dfq_full_capture3 <= 1'b1;
else
spc4_dfq_full_capture3 <= 1'b0;
end
assign spc4_dfq_full4 = (spc4_dfq_vld_entries >= (3'd4 + 4));
always @(spc4_dfq_full_d4 or spc4_dfq_full4)
begin
if (spc4_dfq_full_d4 && ~spc4_dfq_full4)
spc4_dfq_full_capture4 <= 1'b1;
else
spc4_dfq_full_capture4 <= 1'b0;
end
assign spc4_dfq_full5 = (spc4_dfq_vld_entries >= (3'd4 + 5));
always @(spc4_dfq_full_d5 or spc4_dfq_full5)
begin
if (spc4_dfq_full_d5 && ~spc4_dfq_full5)
spc4_dfq_full_capture5 <= 1'b1;
else
spc4_dfq_full_capture5 <= 1'b0;
end
assign spc4_dfq_full6 = (spc4_dfq_vld_entries >= (3'd4 + 6));
always @(spc4_dfq_full_d6 or spc4_dfq_full6)
begin
if (spc4_dfq_full_d6 && ~spc4_dfq_full6)
spc4_dfq_full_capture6 <= 1'b1;
else
spc4_dfq_full_capture6 <= 1'b0;
end
assign spc4_dfq_full7 = (spc4_dfq_vld_entries >= (3'd4 + 7));
always @(spc4_dfq_full_d7 or spc4_dfq_full7)
begin
if (spc4_dfq_full_d7 && ~spc4_dfq_full7)
spc4_dfq_full_capture7 <= 1'b1;
else
spc4_dfq_full_capture7 <= 1'b0;
end
always @(spc4_mbar_vld_d0 or spc4_mbar_vld0)
begin
if (spc4_mbar_vld_d0 && ~spc4_mbar_vld0)
spc4_mbar_vld_capture0 <= 1'b1;
else
spc4_mbar_vld_capture0 <= 1'b0;
end
always @(spc4_mbar_vld_d1 or spc4_mbar_vld1)
begin
if (spc4_mbar_vld_d1 && ~spc4_mbar_vld1)
spc4_mbar_vld_capture1 <= 1'b1;
else
spc4_mbar_vld_capture1 <= 1'b0;
end
always @(spc4_mbar_vld_d2 or spc4_mbar_vld2)
begin
if (spc4_mbar_vld_d2 && ~spc4_mbar_vld2)
spc4_mbar_vld_capture2 <= 1'b1;
else
spc4_mbar_vld_capture2 <= 1'b0;
end
always @(spc4_mbar_vld_d3 or spc4_mbar_vld3)
begin
if (spc4_mbar_vld_d3 && ~spc4_mbar_vld3)
spc4_mbar_vld_capture3 <= 1'b1;
else
spc4_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc4_dfq_full1 && (spc4_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr1 <= 9'h000;
spc4_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr1);
end
else if( spc4_dfq_full1)
begin
spc4_dfq_full_cntr1 <= spc4_dfq_full_cntr1 + 1;
spc4_dfq_full_d1 <= spc4_dfq_full1;
end
else
begin
spc4_dfq_full_cntr1 <= spc4_dfq_full_cntr1;
spc4_dfq_full_d1 <= spc4_dfq_full1;
end
if( ( ~spc4_dfq_full2 && (spc4_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr2 <= 9'h000;
spc4_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr2);
end
else if( spc4_dfq_full2)
begin
spc4_dfq_full_cntr2 <= spc4_dfq_full_cntr2 + 1;
spc4_dfq_full_d2 <= spc4_dfq_full2;
end
else
begin
spc4_dfq_full_cntr2 <= spc4_dfq_full_cntr2;
spc4_dfq_full_d2 <= spc4_dfq_full2;
end
if( ( ~spc4_dfq_full3 && (spc4_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr3 <= 9'h000;
spc4_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr3);
end
else if( spc4_dfq_full3)
begin
spc4_dfq_full_cntr3 <= spc4_dfq_full_cntr3 + 1;
spc4_dfq_full_d3 <= spc4_dfq_full3;
end
else
begin
spc4_dfq_full_cntr3 <= spc4_dfq_full_cntr3;
spc4_dfq_full_d3 <= spc4_dfq_full3;
end
if( ( ~spc4_dfq_full4 && (spc4_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr4 <= 9'h000;
spc4_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr4);
end
else if( spc4_dfq_full4)
begin
spc4_dfq_full_cntr4 <= spc4_dfq_full_cntr4 + 1;
spc4_dfq_full_d4 <= spc4_dfq_full4;
end
else
begin
spc4_dfq_full_cntr4 <= spc4_dfq_full_cntr4;
spc4_dfq_full_d4 <= spc4_dfq_full4;
end
if( ( ~spc4_dfq_full5 && (spc4_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr5 <= 9'h000;
spc4_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr5);
end
else if( spc4_dfq_full5)
begin
spc4_dfq_full_cntr5 <= spc4_dfq_full_cntr5 + 1;
spc4_dfq_full_d5 <= spc4_dfq_full5;
end
else
begin
spc4_dfq_full_cntr5 <= spc4_dfq_full_cntr5;
spc4_dfq_full_d5 <= spc4_dfq_full5;
end
if( ( ~spc4_dfq_full6 && (spc4_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr6 <= 9'h000;
spc4_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr6);
end
else if( spc4_dfq_full6)
begin
spc4_dfq_full_cntr6 <= spc4_dfq_full_cntr6 + 1;
spc4_dfq_full_d6 <= spc4_dfq_full6;
end
else
begin
spc4_dfq_full_cntr6 <= spc4_dfq_full_cntr6;
spc4_dfq_full_d6 <= spc4_dfq_full6;
end
if( ( ~spc4_dfq_full7 && (spc4_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr7 <= 9'h000;
spc4_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr7);
end
else if( spc4_dfq_full7)
begin
spc4_dfq_full_cntr7 <= spc4_dfq_full_cntr7 + 1;
spc4_dfq_full_d7 <= spc4_dfq_full7;
end
else
begin
spc4_dfq_full_cntr7 <= spc4_dfq_full_cntr7;
spc4_dfq_full_d7 <= spc4_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc4_intrpt0_cmplt or spc4_atm_cntr0 or spc4_stb_state_ced0)
begin
if (spc4_intrpt0_cmplt && (spc4_atm_cntr0 != 9'h000) && ~(|spc4_stb_state_ced0))
spc4_atm_intrpt_b4capture0 <= 1'b1;
else
spc4_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc4_intrpt1_cmplt or spc4_atm_cntr1 or spc4_stb_state_ced1)
begin
if (spc4_intrpt1_cmplt && (spc4_atm_cntr1 != 9'h000) && ~(|spc4_stb_state_ced1))
spc4_atm_intrpt_b4capture1 <= 1'b1;
else
spc4_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc4_intrpt2_cmplt or spc4_atm_cntr2 or spc4_stb_state_ced2)
begin
if (spc4_intrpt2_cmplt && (spc4_atm_cntr2 != 9'h000) && ~(|spc4_stb_state_ced2))
spc4_atm_intrpt_b4capture2 <= 1'b1;
else
spc4_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc4_intrpt3_cmplt or spc4_atm_cntr3 or spc4_stb_state_ced3)
begin
if (spc4_intrpt3_cmplt && (spc4_atm_cntr3 != 9'h000) && ~(|spc4_stb_state_ced3))
spc4_atm_intrpt_b4capture3 <= 1'b1;
else
spc4_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc4_intrpt0_cmplt or spc4_atm_cntr0 or spc4_stb_state_ced0)
begin
if (spc4_intrpt0_cmplt && (spc4_atm_cntr0 != 9'h000) && (|spc4_stb_state_ced0))
spc4_atm_intrpt_capture0 <= 1'b1;
else
spc4_atm_intrpt_capture0 <= 1'b0;
end
always @(spc4_intrpt1_cmplt or spc4_atm_cntr1 or spc4_stb_state_ced1)
begin
if (spc4_intrpt1_cmplt && (spc4_atm_cntr1 != 9'h000) && (|spc4_stb_state_ced1))
spc4_atm_intrpt_capture1 <= 1'b1;
else
spc4_atm_intrpt_capture1 <= 1'b0;
end
always @(spc4_intrpt2_cmplt or spc4_atm_cntr2 or spc4_stb_state_ced2)
begin
if (spc4_intrpt2_cmplt && (spc4_atm_cntr2 != 9'h000) && (|spc4_stb_state_ced2))
spc4_atm_intrpt_capture2 <= 1'b1;
else
spc4_atm_intrpt_capture2 <= 1'b0;
end
always @(spc4_intrpt3_cmplt or spc4_atm_cntr3 or spc4_stb_state_ced3)
begin
if (spc4_intrpt3_cmplt && (spc4_atm_cntr3 != 9'h000) && (|spc4_stb_state_ced3))
spc4_atm_intrpt_capture3 <= 1'b1;
else
spc4_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc4_atm_cntr0 or spc4_dva_din or spc4_dva_wen)
begin
if (~spc4_dva_din && spc4_dva_wen && (spc4_atm_cntr0 != 9'h000))
spc4_atm_inv_capture0 <= 1'b1;
else
spc4_atm_inv_capture0 <= 1'b0;
end
always @(spc4_atm_cntr1 or spc4_dva_din or spc4_dva_wen)
begin
if (~spc4_dva_din && spc4_dva_wen && (spc4_atm_cntr1 != 9'h000))
spc4_atm_inv_capture1 <= 1'b1;
else
spc4_atm_inv_capture1 <= 1'b0;
end
always @(spc4_atm_cntr2 or spc4_dva_din or spc4_dva_wen)
begin
if (~spc4_dva_din && spc4_dva_wen && (spc4_atm_cntr2 != 9'h000))
spc4_atm_inv_capture2 <= 1'b1;
else
spc4_atm_inv_capture2 <= 1'b0;
end
always @(spc4_atm_cntr3 or spc4_dva_din or spc4_dva_wen)
begin
if (~spc4_dva_din && spc4_dva_wen && (spc4_atm_cntr3 != 9'h000))
spc4_atm_inv_capture3 <= 1'b1;
else
spc4_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc4_stb_state_vld0) && (spc4_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_atm_cntr0 <= 9'h000;
spc4_atm0_d <= 1'b0;
end
else if( spc4_atomic_g && (spc4_atm_type0 != 8'h00))
begin
spc4_atm_cntr0 <= spc4_atm_cntr0 + 1;
spc4_atm0_d <= 1'b1;
end
else if( spc4_atm0_d && (|spc4_stb_state_vld0))
begin
spc4_atm_cntr0 <= spc4_atm_cntr0 + 1;
spc4_atm0_d <= spc4_atm0_d;
end
else
begin
spc4_atm_cntr0 <= spc4_atm_cntr0;
spc4_atm0_d <= spc4_atm0_d;
end
if( ( ~(|spc4_stb_state_vld1) && (spc4_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_atm_cntr1 <= 9'h000;
spc4_atm1_d <= 1'b0;
end
else if( spc4_atomic_g && (spc4_atm_type1 != 8'h00))
begin
spc4_atm_cntr1 <= spc4_atm_cntr1 + 1;
spc4_atm1_d <= 1'b1;
end
else if( spc4_atm1_d && (|spc4_stb_state_vld1))
begin
spc4_atm_cntr1 <= spc4_atm_cntr1 + 1;
spc4_atm1_d <= spc4_atm1_d;
end
else
begin
spc4_atm_cntr1 <= spc4_atm_cntr1;
spc4_atm1_d <= spc4_atm1_d;
end
if( ( ~(|spc4_stb_state_vld2) && (spc4_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_atm_cntr2 <= 9'h000;
spc4_atm2_d <= 1'b0;
end
else if( spc4_atomic_g && (spc4_atm_type2 != 8'h00))
begin
spc4_atm_cntr2 <= spc4_atm_cntr2 + 1;
spc4_atm2_d <= 1'b1;
end
else if( spc4_atm2_d && (|spc4_stb_state_vld2))
begin
spc4_atm_cntr2 <= spc4_atm_cntr2 + 1;
spc4_atm2_d <= spc4_atm2_d;
end
else
begin
spc4_atm_cntr2 <= spc4_atm_cntr2;
spc4_atm2_d <= spc4_atm2_d;
end
if( ( ~(|spc4_stb_state_vld3) && (spc4_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_atm_cntr3 <= 9'h000;
spc4_atm3_d <= 1'b0;
end
else if( spc4_atomic_g && (spc4_atm_type3 != 8'h00))
begin
spc4_atm_cntr3 <= spc4_atm_cntr3 + 1;
spc4_atm3_d <= 1'b1;
end
else if( spc4_atm3_d && (|spc4_stb_state_vld3))
begin
spc4_atm_cntr3 <= spc4_atm_cntr3 + 1;
spc4_atm3_d <= spc4_atm3_d;
end
else
begin
spc4_atm_cntr3 <= spc4_atm_cntr3;
spc4_atm3_d <= spc4_atm3_d;
end
end
assign spc4_raw_ack_capture0 = spc4_stb_ack_vld0 && (spc4_stb_ack_cntr0 != 9'h000);
assign spc4_stb_ced0 = |spc4_stb_state_ced0;
assign spc4_raw_ack_capture1 = spc4_stb_ack_vld1 && (spc4_stb_ack_cntr1 != 9'h000);
assign spc4_stb_ced1 = |spc4_stb_state_ced1;
assign spc4_raw_ack_capture2 = spc4_stb_ack_vld2 && (spc4_stb_ack_cntr2 != 9'h000);
assign spc4_stb_ced2 = |spc4_stb_state_ced2;
assign spc4_raw_ack_capture3 = spc4_stb_ack_vld3 && (spc4_stb_ack_cntr3 != 9'h000);
assign spc4_stb_ced3 = |spc4_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc4_stb_ced0 && (spc4_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_stb_ced_cntr0 <= 9'h000;
spc4_stb_ced0_d <= 1'b0;
end
else if( spc4_stb_ced0 && (spc4_stb_state_ack0 == 8'h00))
begin
spc4_stb_ced_cntr0 <= spc4_stb_ced_cntr0 + 1;
spc4_stb_ced0_d <= spc4_stb_ced0;
end
else
begin
spc4_stb_ced_cntr0 <= spc4_stb_ced_cntr0;
spc4_stb_ced0_d <= spc4_stb_ced0_d;
end
if( ( ~spc4_mbar_vld0 && (spc4_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_mbar_vld_cntr0 <= 9'h000;
spc4_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_mbar_vld_counter = %d", spc4_mbar_vld_cntr0);
end
else if( spc4_mbar_vld0)
begin
spc4_mbar_vld_cntr0 <= spc4_mbar_vld_cntr0 + 1;
spc4_mbar_vld_d0 <= spc4_mbar_vld0;
end
else
begin
spc4_mbar_vld_cntr0 <= spc4_mbar_vld_cntr0;
spc4_mbar_vld_d0 <= spc4_mbar_vld0;
end
if( ( ~spc4_flsh_vld0 && (spc4_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_flsh_vld_cntr0 <= 9'h000;
spc4_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_flsh_vld_counter = %d", spc4_flsh_vld_cntr0);
end
else if( spc4_flsh_vld0)
begin
spc4_flsh_vld_cntr0 <= spc4_flsh_vld_cntr0 + 1;
spc4_flsh_vld_d0 <= spc4_flsh_vld0;
end
else
begin
spc4_flsh_vld_cntr0 <= spc4_flsh_vld_cntr0;
spc4_flsh_vld_d0 <= spc4_flsh_vld0;
end
if( ( ~spc4_stb_ced1 && (spc4_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_stb_ced_cntr1 <= 9'h000;
spc4_stb_ced1_d <= 1'b0;
end
else if( spc4_stb_ced1 && (spc4_stb_state_ack1 == 8'h00))
begin
spc4_stb_ced_cntr1 <= spc4_stb_ced_cntr1 + 1;
spc4_stb_ced1_d <= spc4_stb_ced1;
end
else
begin
spc4_stb_ced_cntr1 <= spc4_stb_ced_cntr1;
spc4_stb_ced1_d <= spc4_stb_ced1_d;
end
if( ( ~spc4_mbar_vld1 && (spc4_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_mbar_vld_cntr1 <= 9'h000;
spc4_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_mbar_vld_counter = %d", spc4_mbar_vld_cntr1);
end
else if( spc4_mbar_vld1)
begin
spc4_mbar_vld_cntr1 <= spc4_mbar_vld_cntr1 + 1;
spc4_mbar_vld_d1 <= spc4_mbar_vld1;
end
else
begin
spc4_mbar_vld_cntr1 <= spc4_mbar_vld_cntr1;
spc4_mbar_vld_d1 <= spc4_mbar_vld1;
end
if( ( ~spc4_flsh_vld1 && (spc4_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_flsh_vld_cntr1 <= 9'h000;
spc4_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_flsh_vld_counter = %d", spc4_flsh_vld_cntr1);
end
else if( spc4_flsh_vld1)
begin
spc4_flsh_vld_cntr1 <= spc4_flsh_vld_cntr1 + 1;
spc4_flsh_vld_d1 <= spc4_flsh_vld1;
end
else
begin
spc4_flsh_vld_cntr1 <= spc4_flsh_vld_cntr1;
spc4_flsh_vld_d1 <= spc4_flsh_vld1;
end
if( ( ~spc4_stb_ced2 && (spc4_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_stb_ced_cntr2 <= 9'h000;
spc4_stb_ced2_d <= 1'b0;
end
else if( spc4_stb_ced2 && (spc4_stb_state_ack2 == 8'h00))
begin
spc4_stb_ced_cntr2 <= spc4_stb_ced_cntr2 + 1;
spc4_stb_ced2_d <= spc4_stb_ced2;
end
else
begin
spc4_stb_ced_cntr2 <= spc4_stb_ced_cntr2;
spc4_stb_ced2_d <= spc4_stb_ced2_d;
end
if( ( ~spc4_mbar_vld2 && (spc4_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_mbar_vld_cntr2 <= 9'h000;
spc4_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_mbar_vld_counter = %d", spc4_mbar_vld_cntr2);
end
else if( spc4_mbar_vld2)
begin
spc4_mbar_vld_cntr2 <= spc4_mbar_vld_cntr2 + 1;
spc4_mbar_vld_d2 <= spc4_mbar_vld2;
end
else
begin
spc4_mbar_vld_cntr2 <= spc4_mbar_vld_cntr2;
spc4_mbar_vld_d2 <= spc4_mbar_vld2;
end
if( ( ~spc4_flsh_vld2 && (spc4_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_flsh_vld_cntr2 <= 9'h000;
spc4_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_flsh_vld_counter = %d", spc4_flsh_vld_cntr2);
end
else if( spc4_flsh_vld2)
begin
spc4_flsh_vld_cntr2 <= spc4_flsh_vld_cntr2 + 1;
spc4_flsh_vld_d2 <= spc4_flsh_vld2;
end
else
begin
spc4_flsh_vld_cntr2 <= spc4_flsh_vld_cntr2;
spc4_flsh_vld_d2 <= spc4_flsh_vld2;
end
if( ( ~spc4_stb_ced3 && (spc4_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_stb_ced_cntr3 <= 9'h000;
spc4_stb_ced3_d <= 1'b0;
end
else if( spc4_stb_ced3 && (spc4_stb_state_ack3 == 8'h00))
begin
spc4_stb_ced_cntr3 <= spc4_stb_ced_cntr3 + 1;
spc4_stb_ced3_d <= spc4_stb_ced3;
end
else
begin
spc4_stb_ced_cntr3 <= spc4_stb_ced_cntr3;
spc4_stb_ced3_d <= spc4_stb_ced3_d;
end
if( ( ~spc4_mbar_vld3 && (spc4_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_mbar_vld_cntr3 <= 9'h000;
spc4_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_mbar_vld_counter = %d", spc4_mbar_vld_cntr3);
end
else if( spc4_mbar_vld3)
begin
spc4_mbar_vld_cntr3 <= spc4_mbar_vld_cntr3 + 1;
spc4_mbar_vld_d3 <= spc4_mbar_vld3;
end
else
begin
spc4_mbar_vld_cntr3 <= spc4_mbar_vld_cntr3;
spc4_mbar_vld_d3 <= spc4_mbar_vld3;
end
if( ( ~spc4_flsh_vld3 && (spc4_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_flsh_vld_cntr3 <= 9'h000;
spc4_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_flsh_vld_counter = %d", spc4_flsh_vld_cntr3);
end
else if( spc4_flsh_vld3)
begin
spc4_flsh_vld_cntr3 <= spc4_flsh_vld_cntr3 + 1;
spc4_flsh_vld_d3 <= spc4_flsh_vld3;
end
else
begin
spc4_flsh_vld_cntr3 <= spc4_flsh_vld_cntr3;
spc4_flsh_vld_d3 <= spc4_flsh_vld3;
end
end
always @(spc4_flsh_vld_d0 or spc4_flsh_vld0)
begin
if (spc4_flsh_vld_d0 && ~spc4_flsh_vld0)
spc4_flsh_vld_capture0 <= 1'b1;
else
spc4_flsh_vld_capture0 <= 1'b0;
end
always @(spc4_flsh_vld_d1 or spc4_flsh_vld1)
begin
if (spc4_flsh_vld_d1 && ~spc4_flsh_vld1)
spc4_flsh_vld_capture1 <= 1'b1;
else
spc4_flsh_vld_capture1 <= 1'b0;
end
always @(spc4_flsh_vld_d2 or spc4_flsh_vld2)
begin
if (spc4_flsh_vld_d2 && ~spc4_flsh_vld2)
spc4_flsh_vld_capture2 <= 1'b1;
else
spc4_flsh_vld_capture2 <= 1'b0;
end
always @(spc4_flsh_vld_d3 or spc4_flsh_vld3)
begin
if (spc4_flsh_vld_d3 && ~spc4_flsh_vld3)
spc4_flsh_vld_capture3 <= 1'b1;
else
spc4_flsh_vld_capture3 <= 1'b0;
end
always @(spc4_lmiss_pa0 or spc4_imiss_pa or spc4_imiss_vld_d or spc4_lmiss_vld0)
begin
if((spc4_lmiss_pa0 == spc4_imiss_pa) && spc4_imiss_vld_d && spc4_lmiss_vld0)
spc4_lmiss_eq0 = 1'b1;
else
spc4_lmiss_eq0 = 1'b0;
end
always @(spc4_lmiss_pa1 or spc4_imiss_pa or spc4_imiss_vld_d or spc4_lmiss_vld1)
begin
if((spc4_lmiss_pa1 == spc4_imiss_pa) && spc4_imiss_vld_d && spc4_lmiss_vld1)
spc4_lmiss_eq1 = 1'b1;
else
spc4_lmiss_eq1 = 1'b0;
end
always @(spc4_lmiss_pa2 or spc4_imiss_pa or spc4_imiss_vld_d or spc4_lmiss_vld2)
begin
if((spc4_lmiss_pa2 == spc4_imiss_pa) && spc4_imiss_vld_d && spc4_lmiss_vld2)
spc4_lmiss_eq2 = 1'b1;
else
spc4_lmiss_eq2 = 1'b0;
end
always @(spc4_lmiss_pa3 or spc4_imiss_pa or spc4_imiss_vld_d or spc4_lmiss_vld3)
begin
if((spc4_lmiss_pa3 == spc4_imiss_pa) && spc4_imiss_vld_d && spc4_lmiss_vld3)
spc4_lmiss_eq3 = 1'b1;
else
spc4_lmiss_eq3 = 1'b0;
end
always @(spc4_lmiss_pa0 or spc4_stb_atm_addr0 or spc4_atm_cntr0 or spc4_lmiss_vld0)
begin
if ( ((spc4_lmiss_pa0 == spc4_stb_atm_addr0) && (spc4_atm_cntr0 != 9'h000) && spc4_lmiss_vld0) ||
((spc4_lmiss_pa1 == spc4_stb_atm_addr0) && (spc4_atm_cntr0 != 9'h000) && spc4_lmiss_vld1) ||
((spc4_lmiss_pa2 == spc4_stb_atm_addr0) && (spc4_atm_cntr0 != 9'h000) && spc4_lmiss_vld2) ||
((spc4_lmiss_pa3 == spc4_stb_atm_addr0) && (spc4_atm_cntr0 != 9'h000) && spc4_lmiss_vld3) )
spc4_atm_lmiss_eq0 = 1'b1;
else
spc4_atm_lmiss_eq0 = 1'b0;
end
always @(spc4_lmiss_pa1 or spc4_stb_atm_addr1 or spc4_atm_cntr1 or spc4_lmiss_vld1)
begin
if ( ((spc4_lmiss_pa0 == spc4_stb_atm_addr1) && (spc4_atm_cntr1 != 9'h000) && spc4_lmiss_vld0) ||
((spc4_lmiss_pa1 == spc4_stb_atm_addr1) && (spc4_atm_cntr1 != 9'h000) && spc4_lmiss_vld1) ||
((spc4_lmiss_pa2 == spc4_stb_atm_addr1) && (spc4_atm_cntr1 != 9'h000) && spc4_lmiss_vld2) ||
((spc4_lmiss_pa3 == spc4_stb_atm_addr1) && (spc4_atm_cntr1 != 9'h000) && spc4_lmiss_vld3) )
spc4_atm_lmiss_eq1 = 1'b1;
else
spc4_atm_lmiss_eq1 = 1'b0;
end
always @(spc4_lmiss_pa2 or spc4_stb_atm_addr2 or spc4_atm_cntr2 or spc4_lmiss_vld2)
begin
if ( ((spc4_lmiss_pa0 == spc4_stb_atm_addr2) && (spc4_atm_cntr2 != 9'h000) && spc4_lmiss_vld0) ||
((spc4_lmiss_pa1 == spc4_stb_atm_addr2) && (spc4_atm_cntr2 != 9'h000) && spc4_lmiss_vld1) ||
((spc4_lmiss_pa2 == spc4_stb_atm_addr2) && (spc4_atm_cntr2 != 9'h000) && spc4_lmiss_vld2) ||
((spc4_lmiss_pa3 == spc4_stb_atm_addr2) && (spc4_atm_cntr2 != 9'h000) && spc4_lmiss_vld3) )
spc4_atm_lmiss_eq2 = 1'b1;
else
spc4_atm_lmiss_eq2 = 1'b0;
end
always @(spc4_lmiss_pa3 or spc4_stb_atm_addr3 or spc4_atm_cntr3 or spc4_lmiss_vld3)
begin
if ( ((spc4_lmiss_pa0 == spc4_stb_atm_addr3) && (spc4_atm_cntr3 != 9'h000) && spc4_lmiss_vld0) ||
((spc4_lmiss_pa1 == spc4_stb_atm_addr3) && (spc4_atm_cntr3 != 9'h000) && spc4_lmiss_vld1) ||
((spc4_lmiss_pa2 == spc4_stb_atm_addr3) && (spc4_atm_cntr3 != 9'h000) && spc4_lmiss_vld2) ||
((spc4_lmiss_pa3 == spc4_stb_atm_addr3) && (spc4_atm_cntr3 != 9'h000) && spc4_lmiss_vld3) )
spc4_atm_lmiss_eq3 = 1'b1;
else
spc4_atm_lmiss_eq3 = 1'b0;
end
always @(spc4_imiss_pa or spc4_stb_atm_addr0 or spc4_atm_cntr0 or spc4_imiss_vld_d)
begin
if((spc4_imiss_pa == spc4_stb_atm_addr0) && (spc4_atm_cntr0 != 9'h000) && spc4_imiss_vld_d)
spc4_atm_imiss_eq0 = 1'b1;
else
spc4_atm_imiss_eq0 = 1'b0;
end
always @(spc4_imiss_pa or spc4_stb_atm_addr1 or spc4_atm_cntr1 or spc4_imiss_vld_d)
begin
if((spc4_imiss_pa == spc4_stb_atm_addr1) && (spc4_atm_cntr1 != 9'h000) && spc4_imiss_vld_d)
spc4_atm_imiss_eq1 = 1'b1;
else
spc4_atm_imiss_eq1 = 1'b0;
end
always @(spc4_imiss_pa or spc4_stb_atm_addr2 or spc4_atm_cntr2 or spc4_imiss_vld_d)
begin
if((spc4_imiss_pa == spc4_stb_atm_addr2) && (spc4_atm_cntr2 != 9'h000) && spc4_imiss_vld_d)
spc4_atm_imiss_eq2 = 1'b1;
else
spc4_atm_imiss_eq2 = 1'b0;
end
always @(spc4_imiss_pa or spc4_stb_atm_addr3 or spc4_atm_cntr3 or spc4_imiss_vld_d)
begin
if((spc4_imiss_pa == spc4_stb_atm_addr3) && (spc4_atm_cntr3 != 9'h000) && spc4_imiss_vld_d)
spc4_atm_imiss_eq3 = 1'b1;
else
spc4_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc4_imiss_vld || ~rst_l)
spc4_imiss_vld_d <= 1'b0;
else
spc4_imiss_vld_d <= spc4_imiss_vld;
if( ~spc4_ld_miss || ~rst_l)
spc4_ld_miss_capture <= 1'b0;
else
spc4_ld_miss_capture <= spc4_ld_miss;
end
always @(spc4_stb_ced0 or spc4_stb_ced0_d)
begin
if (~spc4_stb_ced0 && spc4_stb_ced0_d)
spc4_stb_ced_capture0 <= 1'b1;
else
spc4_stb_ced_capture0 <= 1'b0;
end
always @(spc4_stb_ced1 or spc4_stb_ced1_d)
begin
if (~spc4_stb_ced1 && spc4_stb_ced1_d)
spc4_stb_ced_capture1 <= 1'b1;
else
spc4_stb_ced_capture1 <= 1'b0;
end
always @(spc4_stb_ced2 or spc4_stb_ced2_d)
begin
if (~spc4_stb_ced2 && spc4_stb_ced2_d)
spc4_stb_ced_capture2 <= 1'b1;
else
spc4_stb_ced_capture2 <= 1'b0;
end
always @(spc4_stb_ced3 or spc4_stb_ced3_d)
begin
if (~spc4_stb_ced3 && spc4_stb_ced3_d)
spc4_stb_ced_capture3 <= 1'b1;
else
spc4_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc4_stb_state_ack0 != 8'h00 && (spc4_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_ack_counter0 = %d", spc4_stb_ack_cntr0);
end
else if(spc4_stb_cam_hit && spc4_ld0_inst_vld_g && (spc4_stb_state_ack0 == 8'h00))
begin
spc4_stb_ack_cntr0 <= spc4_stb_ack_cntr0 + 1;
end
else if( (spc4_stb_state_ack0 == 8'h00 ) && (spc4_stb_ack_cntr0 != 9'h000))
begin
spc4_stb_ack_cntr0 <= spc4_stb_ack_cntr0 + 1;
end // if ( (spc4_stb_state_ack0 == 8'h00 ) && (spc4_stb_ack_cntr0 != 9'h000))
else
begin
spc4_stb_ack_cntr0 <= spc4_stb_ack_cntr0;
end
if( (spc4_stb_state_ack1 != 8'h00 && (spc4_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_ack_counter1 = %d", spc4_stb_ack_cntr1);
end
else if(spc4_stb_cam_hit && spc4_ld1_inst_vld_g && (spc4_stb_state_ack1 == 8'h00))
begin
spc4_stb_ack_cntr1 <= spc4_stb_ack_cntr1 + 1;
end
else if( (spc4_stb_state_ack1 == 8'h00 ) && (spc4_stb_ack_cntr1 != 9'h000))
begin
spc4_stb_ack_cntr1 <= spc4_stb_ack_cntr1 + 1;
end // if ( (spc4_stb_state_ack1 == 8'h00 ) && (spc4_stb_ack_cntr1 != 9'h000))
else
begin
spc4_stb_ack_cntr1 <= spc4_stb_ack_cntr1;
end
if( (spc4_stb_state_ack2 != 8'h00 && (spc4_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_ack_counter2 = %d", spc4_stb_ack_cntr2);
end
else if(spc4_stb_cam_hit && spc4_ld2_inst_vld_g && (spc4_stb_state_ack2 == 8'h00))
begin
spc4_stb_ack_cntr2 <= spc4_stb_ack_cntr2 + 1;
end
else if( (spc4_stb_state_ack2 == 8'h00 ) && (spc4_stb_ack_cntr2 != 9'h000))
begin
spc4_stb_ack_cntr2 <= spc4_stb_ack_cntr2 + 1;
end // if ( (spc4_stb_state_ack2 == 8'h00 ) && (spc4_stb_ack_cntr2 != 9'h000))
else
begin
spc4_stb_ack_cntr2 <= spc4_stb_ack_cntr2;
end
if( (spc4_stb_state_ack3 != 8'h00 && (spc4_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_ack_counter3 = %d", spc4_stb_ack_cntr3);
end
else if(spc4_stb_cam_hit && spc4_ld3_inst_vld_g && (spc4_stb_state_ack3 == 8'h00))
begin
spc4_stb_ack_cntr3 <= spc4_stb_ack_cntr3 + 1;
end
else if( (spc4_stb_state_ack3 == 8'h00 ) && (spc4_stb_ack_cntr3 != 9'h000))
begin
spc4_stb_ack_cntr3 <= spc4_stb_ack_cntr3 + 1;
end // if ( (spc4_stb_state_ack3 == 8'h00 ) && (spc4_stb_ack_cntr3 != 9'h000))
else
begin
spc4_stb_ack_cntr3 <= spc4_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc4_stb0_full_w2 or spc4_stb0_full)
begin
if (~spc4_stb0_full_w2 && spc4_stb0_full)
spc4_stb_full_capture0 <= 1'b1;
else
spc4_stb_full_capture0 <= 1'b0;
end
always @(spc4_stb1_full_w2 or spc4_stb1_full)
begin
if (~spc4_stb1_full_w2 && spc4_stb1_full)
spc4_stb_full_capture1 <= 1'b1;
else
spc4_stb_full_capture1 <= 1'b0;
end
always @(spc4_stb2_full_w2 or spc4_stb2_full)
begin
if (~spc4_stb2_full_w2 && spc4_stb2_full)
spc4_stb_full_capture2 <= 1'b1;
else
spc4_stb_full_capture2 <= 1'b0;
end
always @(spc4_stb3_full_w2 or spc4_stb3_full)
begin
if (~spc4_stb3_full_w2 && spc4_stb3_full)
spc4_stb_full_capture3 <= 1'b1;
else
spc4_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc4_stb0_full && (spc4_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_full_counter0 = %d", spc4_stb_full_cntr0);
end
else if( spc4_stb0_full)
begin
spc4_stb_full_cntr0 <= spc4_stb_full_cntr0 + 1;
end
else
begin
spc4_stb_full_cntr0 <= spc4_stb_full_cntr0;
end
if( ( ~spc4_stb1_full && (spc4_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_full_counter1 = %d", spc4_stb_full_cntr1);
end
else if( spc4_stb1_full)
begin
spc4_stb_full_cntr1 <= spc4_stb_full_cntr1 + 1;
end
else
begin
spc4_stb_full_cntr1 <= spc4_stb_full_cntr1;
end
if( ( ~spc4_stb2_full && (spc4_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_full_counter2 = %d", spc4_stb_full_cntr2);
end
else if( spc4_stb2_full)
begin
spc4_stb_full_cntr2 <= spc4_stb_full_cntr2 + 1;
end
else
begin
spc4_stb_full_cntr2 <= spc4_stb_full_cntr2;
end
if( ( ~spc4_stb3_full && (spc4_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc4_stb_full_counter3 = %d", spc4_stb_full_cntr3);
end
else if( spc4_stb3_full)
begin
spc4_stb_full_cntr3 <= spc4_stb_full_cntr3 + 1;
end
else
begin
spc4_stb_full_cntr3 <= spc4_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc4_lmq0_full_d or spc4_lmq0_full)
begin
if (spc4_lmq0_full_d && ~spc4_lmq0_full)
spc4_lmq_full_capture0 <= 1'b1;
else
spc4_lmq_full_capture0 <= 1'b0;
end
always @(spc4_lmq1_full_d or spc4_lmq1_full)
begin
if (spc4_lmq1_full_d && ~spc4_lmq1_full)
spc4_lmq_full_capture1 <= 1'b1;
else
spc4_lmq_full_capture1 <= 1'b0;
end
always @(spc4_lmq2_full_d or spc4_lmq2_full)
begin
if (spc4_lmq2_full_d && ~spc4_lmq2_full)
spc4_lmq_full_capture2 <= 1'b1;
else
spc4_lmq_full_capture2 <= 1'b0;
end
always @(spc4_lmq3_full_d or spc4_lmq3_full)
begin
if (spc4_lmq3_full_d && ~spc4_lmq3_full)
spc4_lmq_full_capture3 <= 1'b1;
else
spc4_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc4_lmq0_full && (spc4_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc4_lmq_full_cntr0 <= 9'h000;
spc4_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_lmq_full_counter0 = %d", spc4_lmq_full_cntr0);
end
else if( spc4_lmq0_full)
begin
spc4_lmq_full_cntr0 <= spc4_lmq_full_cntr0 + 1;
spc4_lmq0_full_d <= spc4_lmq0_full;
end
else
begin
spc4_lmq_full_cntr0 <= spc4_lmq_full_cntr0;
spc4_lmq0_full_d <= spc4_lmq0_full;
end
if( ( ~spc4_lmq1_full && (spc4_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc4_lmq_full_cntr1 <= 9'h000;
spc4_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_lmq_full_counter1 = %d", spc4_lmq_full_cntr1);
end
else if( spc4_lmq1_full)
begin
spc4_lmq_full_cntr1 <= spc4_lmq_full_cntr1 + 1;
spc4_lmq1_full_d <= spc4_lmq1_full;
end
else
begin
spc4_lmq_full_cntr1 <= spc4_lmq_full_cntr1;
spc4_lmq1_full_d <= spc4_lmq1_full;
end
if( ( ~spc4_lmq2_full && (spc4_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc4_lmq_full_cntr2 <= 9'h000;
spc4_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_lmq_full_counter2 = %d", spc4_lmq_full_cntr2);
end
else if( spc4_lmq2_full)
begin
spc4_lmq_full_cntr2 <= spc4_lmq_full_cntr2 + 1;
spc4_lmq2_full_d <= spc4_lmq2_full;
end
else
begin
spc4_lmq_full_cntr2 <= spc4_lmq_full_cntr2;
spc4_lmq2_full_d <= spc4_lmq2_full;
end
if( ( ~spc4_lmq3_full && (spc4_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc4_lmq_full_cntr3 <= 9'h000;
spc4_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_lmq_full_counter3 = %d", spc4_lmq_full_cntr3);
end
else if( spc4_lmq3_full)
begin
spc4_lmq_full_cntr3 <= spc4_lmq_full_cntr3 + 1;
spc4_lmq3_full_d <= spc4_lmq3_full;
end
else
begin
spc4_lmq_full_cntr3 <= spc4_lmq_full_cntr3;
spc4_lmq3_full_d <= spc4_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc4_dfq_full_d or spc4_dfq_full)
begin
if (spc4_dfq_full_d && ~spc4_dfq_full)
spc4_dfq_full_capture <= 1'b1;
else
spc4_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc4_dfq_full && (spc4_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc4_dfq_full_cntr <= 9'h000;
spc4_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dfq_full_counter = %d", spc4_dfq_full_cntr);
end
else if( spc4_dfq_full)
begin
spc4_dfq_full_cntr <= spc4_dfq_full_cntr + 1;
spc4_dfq_full_d <= spc4_dfq_full;
end
else
begin
spc4_dfq_full_cntr <= spc4_dfq_full_cntr;
spc4_dfq_full_d <= spc4_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc4_dva_full_d or spc4_dva_inv)
begin
if (spc4_dva_full_d && ~spc4_dva_inv)
spc4_dva_full_capture <= 1'b1;
else
spc4_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc4_dva_din && spc4_dva_wen)
begin
spc4_dva_inv <= 1'b1;
spc4_dva_waddr_d <= spc4_dva_waddr;
end
else if(~spc4_dva_din && spc4_dva_wen)
begin
spc4_dva_inv <= 1'b0;
spc4_dva_waddr_d <= 5'b00000;
end
else
begin
spc4_dva_inv <= spc4_dva_inv;
spc4_dva_waddr_d <= spc4_dva_waddr_d;
end
end
always @(spc4_dva_raddr or spc4_dva_ren or spc4_dva_inv)
begin
if (spc4_dva_inv && spc4_dva_ren && (spc4_dva_raddr[6:2] == spc4_dva_waddr_d))
spc4_dva_vld2lkup <= 1'b1;
else
spc4_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc4_dva_inv && (spc4_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc4_dva_full_cntr <= 9'h000;
spc4_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dva_full_counter = %d", spc4_dva_full_cntr);
end
else if( spc4_dva_inv)
begin
spc4_dva_full_cntr <= spc4_dva_full_cntr + 1;
spc4_dva_full_d <= spc4_dva_inv;
end
else
begin
spc4_dva_full_cntr <= spc4_dva_full_cntr;
spc4_dva_full_d <= spc4_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc4_dva_vfull_d or spc4_dva_vld)
begin
if (spc4_dva_vfull_d && ~spc4_dva_vld)
spc4_dva_vfull_capture <= 1'b1;
else
spc4_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc4_dva_din && spc4_dva_wen)
begin
spc4_dva_vld <= 1'b1;
spc4_dva_invwaddr_d <= spc4_dva_waddr;
spc4_dva_invld_err <= spc4_dva_inv_perror;
end
else if(spc4_dva_din && spc4_dva_wen)
begin
spc4_dva_vld <= 1'b0;
spc4_dva_invwaddr_d <= 5'b00000;
spc4_dva_invld_err <= 1'b0;
end
else
begin
spc4_dva_vld <= spc4_dva_vld;
spc4_dva_invwaddr_d <= spc4_dva_invwaddr_d;
spc4_dva_invld_err <= spc4_dva_invld_err;
end
end
always @(spc4_dva_raddr or spc4_dva_ren or spc4_dva_vld)
begin
if (spc4_dva_vld && spc4_dva_ren && (spc4_dva_raddr[6:2] == spc4_dva_waddr_d))
spc4_dva_invld2lkup <= 1'b1;
else
spc4_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc4_dva_vld && (spc4_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc4_dva_vfull_cntr <= 9'h000;
spc4_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc4_dva_vfull_counter = %d", spc4_dva_vfull_cntr);
end
else if( spc4_dva_vld)
begin
spc4_dva_vfull_cntr <= spc4_dva_vfull_cntr + 1;
spc4_dva_vfull_d <= spc4_dva_vld;
end
else
begin
spc4_dva_vfull_cntr <= spc4_dva_vfull_cntr;
spc4_dva_vfull_d <= spc4_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc4_dva_raddr or spc4_dva_waddr or spc4_dva_ren or spc4_dva_wen)
begin
if ( spc4_dva_ren && spc4_dva_wen && (spc4_dva_raddr[6:2] == spc4_dva_waddr))
spc4_dva_collide <= 1'b1;
else
spc4_dva_collide <= 1'b0;
end
// dva error cases
always @(spc4_dva_raddr or spc4_dva_ren or spc4_dva_dtag_perror or spc4_dva_dtag_perror)
begin
if (spc4_dva_ren && (spc4_dva_dtag_perror || spc4_dva_dtag_perror))
spc4_dva_err <= 1'b1;
else
spc4_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc4_dva_err)
spc4_dva_efull_d <= 1'b1;
else
spc4_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc4_dva_ren && ~(spc4_dva_dtag_perror || spc4_dva_dtag_perror ) &&
(spc4_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc4_dva_efull_cntr <= 9'h000;
spc4_dva_raddr_d <= spc4_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc4_dva_efull_counter = %d", spc4_dva_efull_cntr);
end
else if(spc4_dva_efull_d)
begin
spc4_dva_efull_cntr <= spc4_dva_efull_cntr + 1;
spc4_dva_raddr_d <= spc4_dva_raddr_d;
end
else
begin
spc4_dva_efull_cntr <= spc4_dva_efull_cntr;
spc4_dva_raddr_d <= spc4_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC5
wire spc5_dva_ren = `TOP_DESIGN.sparc5.lsu.ifu_lsu_ld_inst_e;
wire spc5_dva_wen = `TOP_DESIGN.sparc5.lsu.lsu_dtagv_wr_vld_e;
wire spc5_dva_din = `TOP_DESIGN.sparc5.lsu.dva_din_e;
wire [3:0] spc5_dva_dout = `TOP_DESIGN.sparc5.lsu.dva_vld_m[3:0];
wire [6:0] spc5_dva_raddr = `TOP_DESIGN.sparc5.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc5_dva_waddr = `TOP_DESIGN.sparc5.lsu.dva_wr_adr_e[10:6];
wire spc5_dva_dtag_perror = `TOP_DESIGN.sparc5.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc5_dva_dcache_perror = `TOP_DESIGN.sparc5.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc5_dva_inv_perror = `TOP_DESIGN.sparc5.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc5_ld_miss = `TOP_DESIGN.sparc5.lsu.dctl.lsu_ld_miss_wb;
reg spc5_ld_miss_capture;
wire spc5_atomic_g = `TOP_DESIGN.sparc5.lsu.qctl1.atomic_g;
wire [1:0] spc5_atm_type0 = `TOP_DESIGN.sparc5.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc5_atm_type1 = `TOP_DESIGN.sparc5.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc5_atm_type2 = `TOP_DESIGN.sparc5.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc5_atm_type3 = `TOP_DESIGN.sparc5.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc5_dctl_lsu_way_hit = `TOP_DESIGN.sparc5.lsu.dctl.lsu_way_hit;
wire spc5_dctl_dcache_enable_g = `TOP_DESIGN.sparc5.lsu.dctl.dcache_enable_g;
wire spc5_dctl_ldxa_internal = `TOP_DESIGN.sparc5.lsu.dctl.ldxa_internal;
wire spc5_dctl_ldst_dbl_g = `TOP_DESIGN.sparc5.lsu.dctl.ldst_dbl_g;
wire spc5_dctl_atomic_g = `TOP_DESIGN.sparc5.lsu.dctl.atomic_g;
wire spc5_dctl_stb_cam_hit = `TOP_DESIGN.sparc5.lsu.dctl.stb_cam_hit;
wire spc5_dctl_endian_mispred_g = `TOP_DESIGN.sparc5.lsu.dctl.endian_mispred_g;
wire spc5_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc5.lsu.dctl.dcache_rd_parity_error;
wire spc5_dctl_dtag_perror_g = `TOP_DESIGN.sparc5.lsu.dctl.dtag_perror_g;
wire spc5_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc5.lsu.dctl.tte_data_perror_unc;
wire spc5_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc5.lsu.dctl.ld_inst_vld_g;
wire spc5_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc5.lsu.dctl.lsu_alt_space_g;
wire spc5_dctl_recognized_asi_g = `TOP_DESIGN.sparc5.lsu.dctl.recognized_asi_g;
wire spc5_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc5.lsu.dctl.ncache_asild_rq_g ;
wire spc5_dctl_bld_hit;
wire spc5_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc5_ixinv0 = `TOP_DESIGN.sparc5.lsu.qctl2.imiss0_inv_en;
wire spc5_ixinv1 = `TOP_DESIGN.sparc5.lsu.qctl2.imiss1_inv_en;
wire spc5_ixinv2 = `TOP_DESIGN.sparc5.lsu.qctl2.imiss2_inv_en;
wire spc5_ixinv3 = `TOP_DESIGN.sparc5.lsu.qctl2.imiss3_inv_en;
wire spc5_ifill = `TOP_DESIGN.sparc5.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc5_inv = `TOP_DESIGN.sparc5.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc5_inv_clr = `TOP_DESIGN.sparc5.lsu.qctl2.ifu_lsu_inv_clear;
wire spc5_ibuf_busy = `TOP_DESIGN.sparc5.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc5_l2 = `TOP_DESIGN.sparc5.lsu.dctl.l2fill_vld_g ;
wire spc5_unc = `TOP_DESIGN.sparc5.lsu.dctl.unc_err_trap_g ;
wire spc5_fpld = `TOP_DESIGN.sparc5.lsu.dctl.l2fill_fpld_g ;
wire spc5_fpldst = `TOP_DESIGN.sparc5.lsu.dctl.fp_ldst_g ;
wire spc5_unflush = `TOP_DESIGN.sparc5.lsu.dctl.ld_inst_vld_unflushed ;
wire spc5_ldw = `TOP_DESIGN.sparc5.lsu.dctl.lsu_inst_vld_w ;
wire spc5_byp = `TOP_DESIGN.sparc5.lsu.dctl.intld_byp_data_vld_m ;
wire spc5_flsh = `TOP_DESIGN.sparc5.lsu.lsu_exu_flush_pipe_w ;
wire spc5_chm = `TOP_DESIGN.sparc5.lsu.dctl.common_ldst_miss_w ;
wire spc5_ldxa = `TOP_DESIGN.sparc5.lsu.dctl.ldxa_internal ;
wire spc5_ato = `TOP_DESIGN.sparc5.lsu.dctl.atomic_g ;
wire spc5_pref = `TOP_DESIGN.sparc5.lsu.dctl.pref_inst_g ;
wire spc5_chit = `TOP_DESIGN.sparc5.lsu.dctl.stb_cam_hit ;
wire spc5_dcp = `TOP_DESIGN.sparc5.lsu.dctl.dcache_rd_parity_error ;
wire spc5_dtp = `TOP_DESIGN.sparc5.lsu.dctl.dtag_perror_g ;
//wire spc5_mpc = `TOP_DESIGN.sparc5.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc5_mpc = 1'b0;
wire spc5_mpu = `TOP_DESIGN.sparc5.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc5_exu_und;
reg [4:0] spc5_exu;
// excptn
wire spc5_exp_wtchpt_trp_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc5_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc5_exp_priv_violtn_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc5_exp_daccess_excptn_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc5_exp_daccess_prot_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc5_exp_priv_action_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc5_exp_spec_access_epage_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc5_exp_uncache_atomic_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc5_exp_illegal_asi_action_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc5_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc5_exp_asi_rd_unc = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc5_exp_tlb_data_ce = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc5_exp_asi_rd_unc = 1'b0;
wire spc5_exp_tlb_data_ce = 1'b0;
wire spc5_exp_tlb_data_ue = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc5_exp_tlb_tag_ue = `TOP_DESIGN.sparc5.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc5_exp_unc = `TOP_DESIGN.sparc5.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc5_exp_corr = `TOP_DESIGN.sparc5.lsu.excpctl.tte_data_perror_corr;
wire spc5_exp_corr = 1'b0;
wire [15:0] spc5_exp_und;
reg [4:0] spc5_exp;
// dctl cmplt
wire spc5_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc5.lsu.dctl.stxa_internal_d2;
wire spc5_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc5.lsu.dctl.lsu_l2fill_vld;
wire spc5_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc5.lsu.dctl.atomic_ld_squash_e;
wire spc5_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc5.lsu.qctl2.lsu_ignore_fill;
wire spc5_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc5.lsu.dctl.l2fill_fpld_e;
// wire spc5_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc5.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc5_dctl_fill_err_trap_e = `TOP_DESIGN.sparc5.lsu.dctl.fill_err_trap_e;
wire spc5_dctl_l2_corr_error_e = `TOP_DESIGN.sparc5.lsu.dctl.l2_corr_error_e;
wire [3:0] spc5_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc5.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc5_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc5.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc5_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc5.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc5_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc5.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc5_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc5.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc5_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc5.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc5_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc5_ldstcond_cmplt_d;
wire spc5_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc5.lsu.qctl1.ld_sec_hit_thrd0;
wire spc5_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_inst_vld_g;
wire spc5_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc5_ld0_pkt_vld_unmasked_d;
reg spc5_qctl1_ld_sec_hit_thrd0_w2;
wire spc5_dctl_thread0_w3 = `TOP_DESIGN.sparc5.lsu.dctl.thread0_w3;
wire spc5_dctl_dfill_thread0 = `TOP_DESIGN.sparc5.lsu.dctl.dfill_thread0;
wire spc5_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc5.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc5_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc5.lsu.dctl.diag_wr_cmplt0;
wire spc5_dctl_bsync0_reset = `TOP_DESIGN.sparc5.lsu.dctl.bsync0_reset;
wire spc5_dctl_late_cmplt0 = `TOP_DESIGN.sparc5.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc5_dctl_stxa_cmplt0;
wire spc5_dctl_l2fill_cmplt0;
wire spc5_dctl_atm_cmplt0;
wire spc5_dctl_fillerr0;
wire [4:0] spc5_cmplt0;
wire [5:0] spc5_dctl_ldst_cond_cmplt0;
reg [3:0] spc5_ldstcond_cmplt0;
reg [3:0] spc5_ldstcond_cmplt0_d;
wire spc5_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc5.lsu.qctl1.ld_sec_hit_thrd1;
wire spc5_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_inst_vld_g;
wire spc5_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc5_ld1_pkt_vld_unmasked_d;
reg spc5_qctl1_ld_sec_hit_thrd1_w2;
wire spc5_dctl_thread1_w3 = `TOP_DESIGN.sparc5.lsu.dctl.thread1_w3;
wire spc5_dctl_dfill_thread1 = `TOP_DESIGN.sparc5.lsu.dctl.dfill_thread1;
wire spc5_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc5.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc5_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc5.lsu.dctl.diag_wr_cmplt1;
wire spc5_dctl_bsync1_reset = `TOP_DESIGN.sparc5.lsu.dctl.bsync1_reset;
wire spc5_dctl_late_cmplt1 = `TOP_DESIGN.sparc5.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc5_dctl_stxa_cmplt1;
wire spc5_dctl_l2fill_cmplt1;
wire spc5_dctl_atm_cmplt1;
wire spc5_dctl_fillerr1;
wire [4:0] spc5_cmplt1;
wire [5:0] spc5_dctl_ldst_cond_cmplt1;
reg [3:0] spc5_ldstcond_cmplt1;
reg [3:0] spc5_ldstcond_cmplt1_d;
wire spc5_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc5.lsu.qctl1.ld_sec_hit_thrd2;
wire spc5_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_inst_vld_g;
wire spc5_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc5_ld2_pkt_vld_unmasked_d;
reg spc5_qctl1_ld_sec_hit_thrd2_w2;
wire spc5_dctl_thread2_w3 = `TOP_DESIGN.sparc5.lsu.dctl.thread2_w3;
wire spc5_dctl_dfill_thread2 = `TOP_DESIGN.sparc5.lsu.dctl.dfill_thread2;
wire spc5_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc5.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc5_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc5.lsu.dctl.diag_wr_cmplt2;
wire spc5_dctl_bsync2_reset = `TOP_DESIGN.sparc5.lsu.dctl.bsync2_reset;
wire spc5_dctl_late_cmplt2 = `TOP_DESIGN.sparc5.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc5_dctl_stxa_cmplt2;
wire spc5_dctl_l2fill_cmplt2;
wire spc5_dctl_atm_cmplt2;
wire spc5_dctl_fillerr2;
wire [4:0] spc5_cmplt2;
wire [5:0] spc5_dctl_ldst_cond_cmplt2;
reg [3:0] spc5_ldstcond_cmplt2;
reg [3:0] spc5_ldstcond_cmplt2_d;
wire spc5_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc5.lsu.qctl1.ld_sec_hit_thrd3;
wire spc5_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_inst_vld_g;
wire spc5_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc5_ld3_pkt_vld_unmasked_d;
reg spc5_qctl1_ld_sec_hit_thrd3_w2;
wire spc5_dctl_thread3_w3 = `TOP_DESIGN.sparc5.lsu.dctl.thread3_w3;
wire spc5_dctl_dfill_thread3 = `TOP_DESIGN.sparc5.lsu.dctl.dfill_thread3;
wire spc5_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc5.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc5_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc5.lsu.dctl.diag_wr_cmplt3;
wire spc5_dctl_bsync3_reset = `TOP_DESIGN.sparc5.lsu.dctl.bsync3_reset;
wire spc5_dctl_late_cmplt3 = `TOP_DESIGN.sparc5.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc5_dctl_stxa_cmplt3;
wire spc5_dctl_l2fill_cmplt3;
wire spc5_dctl_atm_cmplt3;
wire spc5_dctl_fillerr3;
wire [4:0] spc5_cmplt3;
wire [5:0] spc5_dctl_ldst_cond_cmplt3;
reg [3:0] spc5_ldstcond_cmplt3;
reg [3:0] spc5_ldstcond_cmplt3_d;
wire spc5_qctl1_bld_g = `TOP_DESIGN.sparc5.lsu.qctl1.bld_g;
wire spc5_qctl1_bld_reset = `TOP_DESIGN.sparc5.lsu.qctl1.bld_reset;
wire [1:0] spc5_qctl1_bld_cnt = `TOP_DESIGN.sparc5.lsu.qctl1.bld_cnt;
reg [9:0] spc5_bld0_full_cntr;
reg [1:0] spc5_bld0_full_d;
reg spc5_bld0_full_capture;
reg [9:0] spc5_bld1_full_cntr;
reg [1:0] spc5_bld1_full_d;
reg spc5_bld1_full_capture;
reg [9:0] spc5_bld2_full_cntr;
reg [1:0] spc5_bld2_full_d;
reg spc5_bld2_full_capture;
reg [9:0] spc5_bld3_full_cntr;
reg [1:0] spc5_bld3_full_d;
reg spc5_bld3_full_capture;
wire spc5_ipick = `TOP_DESIGN.sparc5.lsu.qctl1.imiss_pcx_rq_vld;
wire spc5_lpick = `TOP_DESIGN.sparc5.lsu.qctl1.ld_pcx_rq_all;
wire spc5_spick = `TOP_DESIGN.sparc5.lsu.qctl1.st_pcx_rq_all;
wire spc5_mpick = `TOP_DESIGN.sparc5.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc5_apick = `TOP_DESIGN.sparc5.lsu.qctl1.all_pcx_rq_pick;
wire spc5_msquash = `TOP_DESIGN.sparc5.lsu.qctl1.mcycle_squash_d1;
reg spc5_fpicko;
wire [3:0] spc5_fpick;
wire [39:0] spc5_imiss_pa = `TOP_DESIGN.sparc5.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc5_imiss_vld = `TOP_DESIGN.sparc5.lsu.qctl1.imiss_pcx_rq_vld;
reg spc5_imiss_vld_d;
wire [39:0] spc5_lmiss_pa0 = `TOP_DESIGN.sparc5.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc5_lmiss_vld0 = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_pcx_rq_vld;
wire spc5_ld_pkt_vld0 = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_pkt_vld;
wire spc5_st_pkt_vld0 = `TOP_DESIGN.sparc5.lsu.qctl1.st0_pkt_vld;
reg spc5_lmiss_eq0;
reg spc5_atm_imiss_eq0;
wire [39:0] spc5_lmiss_pa1 = `TOP_DESIGN.sparc5.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc5_lmiss_vld1 = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_pcx_rq_vld;
wire spc5_ld_pkt_vld1 = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_pkt_vld;
wire spc5_st_pkt_vld1 = `TOP_DESIGN.sparc5.lsu.qctl1.st1_pkt_vld;
reg spc5_lmiss_eq1;
reg spc5_atm_imiss_eq1;
wire [39:0] spc5_lmiss_pa2 = `TOP_DESIGN.sparc5.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc5_lmiss_vld2 = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_pcx_rq_vld;
wire spc5_ld_pkt_vld2 = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_pkt_vld;
wire spc5_st_pkt_vld2 = `TOP_DESIGN.sparc5.lsu.qctl1.st2_pkt_vld;
reg spc5_lmiss_eq2;
reg spc5_atm_imiss_eq2;
wire [39:0] spc5_lmiss_pa3 = `TOP_DESIGN.sparc5.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc5_lmiss_vld3 = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_pcx_rq_vld;
wire spc5_ld_pkt_vld3 = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_pkt_vld;
wire spc5_st_pkt_vld3 = `TOP_DESIGN.sparc5.lsu.qctl1.st3_pkt_vld;
reg spc5_lmiss_eq3;
reg spc5_atm_imiss_eq3;
wire [44:0] spc5_wdata_ramc = `TOP_DESIGN.sparc5.lsu.stb_cam.wdata_ramc;
wire spc5_wptr_vld = `TOP_DESIGN.sparc5.lsu.stb_cam.wptr_vld;
wire [75:0] spc5_wdata_ramd = {`TOP_DESIGN.sparc5.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc5.lsu.lsu_stb_st_data_g[63:0]};
wire spc5_stb_cam_hit = `TOP_DESIGN.sparc5.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc5_stb_cam_hit_ptr = `TOP_DESIGN.sparc5.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc5_stb_ld_full_raw = `TOP_DESIGN.sparc5.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc5_stb_ld_partial_raw = `TOP_DESIGN.sparc5.lsu.stb_ld_partial_raw[7:0];
wire spc5_stb_cam_mhit = `TOP_DESIGN.sparc5.lsu.stb_cam_mhit;
wire [3:0] spc5_dfq_vld_entries = `TOP_DESIGN.sparc5.lsu.qctl2.dfq_vld_entries;
wire spc5_dfq_full;
reg [9:0] spc5_dfq_full_cntr;
reg spc5_dfq_full_d;
reg spc5_dfq_full_capture;
reg [9:0] spc5_dfq_full_cntr1;
reg spc5_dfq_full_d1;
wire spc5_dfq_full1;
reg spc5_dfq_full_capture1;
reg [9:0] spc5_dfq_full_cntr2;
reg spc5_dfq_full_d2;
wire spc5_dfq_full2;
reg spc5_dfq_full_capture2;
reg [9:0] spc5_dfq_full_cntr3;
reg spc5_dfq_full_d3;
wire spc5_dfq_full3;
reg spc5_dfq_full_capture3;
reg [9:0] spc5_dfq_full_cntr4;
reg spc5_dfq_full_d4;
wire spc5_dfq_full4;
reg spc5_dfq_full_capture4;
reg [9:0] spc5_dfq_full_cntr5;
reg spc5_dfq_full_d5;
wire spc5_dfq_full5;
reg spc5_dfq_full_capture5;
reg [9:0] spc5_dfq_full_cntr6;
reg spc5_dfq_full_d6;
wire spc5_dfq_full6;
reg spc5_dfq_full_capture6;
reg [9:0] spc5_dfq_full_cntr7;
reg spc5_dfq_full_d7;
wire spc5_dfq_full7;
reg spc5_dfq_full_capture7;
wire spc5_dva_rdwrhit;
reg [9:0] spc5_dva_full_cntr;
reg spc5_dva_full_d;
reg spc5_dva_full_capture;
reg spc5_dva_inv;
reg spc5_dva_inv_d;
reg spc5_dva_vld;
reg spc5_dva_vld_d;
reg [9:0] spc5_dva_vfull_cntr;
reg spc5_dva_vfull_d;
reg spc5_dva_vfull_capture;
reg spc5_dva_collide;
reg spc5_dva_vld2lkup;
reg spc5_dva_invld2lkup;
reg spc5_dva_invld_err;
reg [9:0] spc5_dva_efull_cntr;
reg spc5_dva_efull_d;
reg spc5_dva_vlddtag_err;
reg spc5_dva_vlddcache_err;
reg spc5_dva_err;
reg [6:0] spc5_dva_raddr_d;
reg [4:0] spc5_dva_waddr_d;
reg [4:0] spc5_dva_invwaddr_d;
reg spc5_ld0_lt_1;
reg spc5_ld0_lt_2;
reg spc5_ld0_lt_3;
reg spc5_ld1_lt_0;
reg spc5_ld1_lt_2;
reg spc5_ld1_lt_3;
reg spc5_ld2_lt_0;
reg spc5_ld2_lt_1;
reg spc5_ld2_lt_3;
reg spc5_ld3_lt_0;
reg spc5_ld3_lt_1;
reg spc5_ld3_lt_2;
reg spc5_st0_lt_1;
reg spc5_st0_lt_2;
reg spc5_st0_lt_3;
reg spc5_st1_lt_0;
reg spc5_st1_lt_2;
reg spc5_st1_lt_3;
reg spc5_st2_lt_0;
reg spc5_st2_lt_1;
reg spc5_st2_lt_3;
reg spc5_st3_lt_0;
reg spc5_st3_lt_1;
reg spc5_st3_lt_2;
wire [11:0] spc5_ld_ooo_ret;
wire [11:0] spc5_st_ooo_ret;
wire [7:0] spc5_stb_state_vld0 = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc5_stb_state_ack0 = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc5_stb_state_ced0 = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc5_stb_state_rst0 = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_state_rst;
wire spc5_stb_ack_vld0 = `TOP_DESIGN.sparc5.lsu.stb_ctl0.ack_vld;
wire spc5_ld0_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_inst_vld_g;
wire spc5_intrpt0_cmplt = `TOP_DESIGN.sparc5.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc5_stb0_full = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_full;
wire spc5_stb0_full_w2 = `TOP_DESIGN.sparc5.lsu.stb_ctl0.stb_full_w2;
wire spc5_lmq0_full = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_pcx_rq_vld;
wire spc5_mbar_vld0 = `TOP_DESIGN.sparc5.lsu.dctl.mbar_vld0;
wire spc5_ld0_unfilled = `TOP_DESIGN.sparc5.lsu.qctl1.ld0_unfilled;
wire spc5_flsh_vld0 = `TOP_DESIGN.sparc5.lsu.dctl.flsh_vld0;
reg [9:0] spc5_ld0_unf_cntr;
reg spc5_ld0_unfilled_d;
reg [9:0] spc5_st0_unf_cntr;
reg spc5_st0_unfilled_d;
reg spc5_st0_unfilled;
reg spc5_mbar_vld_d0;
reg spc5_flsh_vld_d0;
reg spc5_lmq0_full_d;
reg [9:0] spc5_lmq_full_cntr0;
reg spc5_lmq_full_capture0;
reg [9:0] spc5_stb_full_cntr0;
reg spc5_stb_full_capture0;
reg [9:0] spc5_mbar_vld_cntr0;
reg spc5_mbar_vld_capture0;
reg [9:0] spc5_flsh_vld_cntr0;
reg spc5_flsh_vld_capture0;
reg spc5_stb_head_hit0;
wire spc5_raw_ack_capture0;
reg [9:0] spc5_stb_ack_cntr0;
reg [9:0] spc5_stb_ced_cntr0;
reg spc5_stb_ced0_d;
reg spc5_stb_ced_capture0;
wire spc5_stb_ced0;
reg spc5_atm0_d;
reg [9:0] spc5_atm_cntr0;
reg spc5_atm_intrpt_capture0;
reg spc5_atm_intrpt_b4capture0;
reg spc5_atm_inv_capture0;
reg [39:0] spc5_stb_wr_addr0;
reg [39:0] spc5_stb_atm_addr0;
reg spc5_atm_lmiss_eq0;
wire [7:0] spc5_stb_state_vld1 = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc5_stb_state_ack1 = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc5_stb_state_ced1 = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc5_stb_state_rst1 = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_state_rst;
wire spc5_stb_ack_vld1 = `TOP_DESIGN.sparc5.lsu.stb_ctl1.ack_vld;
wire spc5_ld1_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_inst_vld_g;
wire spc5_intrpt1_cmplt = `TOP_DESIGN.sparc5.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc5_stb1_full = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_full;
wire spc5_stb1_full_w2 = `TOP_DESIGN.sparc5.lsu.stb_ctl1.stb_full_w2;
wire spc5_lmq1_full = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_pcx_rq_vld;
wire spc5_mbar_vld1 = `TOP_DESIGN.sparc5.lsu.dctl.mbar_vld1;
wire spc5_ld1_unfilled = `TOP_DESIGN.sparc5.lsu.qctl1.ld1_unfilled;
wire spc5_flsh_vld1 = `TOP_DESIGN.sparc5.lsu.dctl.flsh_vld1;
reg [9:0] spc5_ld1_unf_cntr;
reg spc5_ld1_unfilled_d;
reg [9:0] spc5_st1_unf_cntr;
reg spc5_st1_unfilled_d;
reg spc5_st1_unfilled;
reg spc5_mbar_vld_d1;
reg spc5_flsh_vld_d1;
reg spc5_lmq1_full_d;
reg [9:0] spc5_lmq_full_cntr1;
reg spc5_lmq_full_capture1;
reg [9:0] spc5_stb_full_cntr1;
reg spc5_stb_full_capture1;
reg [9:0] spc5_mbar_vld_cntr1;
reg spc5_mbar_vld_capture1;
reg [9:0] spc5_flsh_vld_cntr1;
reg spc5_flsh_vld_capture1;
reg spc5_stb_head_hit1;
wire spc5_raw_ack_capture1;
reg [9:0] spc5_stb_ack_cntr1;
reg [9:0] spc5_stb_ced_cntr1;
reg spc5_stb_ced1_d;
reg spc5_stb_ced_capture1;
wire spc5_stb_ced1;
reg spc5_atm1_d;
reg [9:0] spc5_atm_cntr1;
reg spc5_atm_intrpt_capture1;
reg spc5_atm_intrpt_b4capture1;
reg spc5_atm_inv_capture1;
reg [39:0] spc5_stb_wr_addr1;
reg [39:0] spc5_stb_atm_addr1;
reg spc5_atm_lmiss_eq1;
wire [7:0] spc5_stb_state_vld2 = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc5_stb_state_ack2 = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc5_stb_state_ced2 = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc5_stb_state_rst2 = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_state_rst;
wire spc5_stb_ack_vld2 = `TOP_DESIGN.sparc5.lsu.stb_ctl2.ack_vld;
wire spc5_ld2_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_inst_vld_g;
wire spc5_intrpt2_cmplt = `TOP_DESIGN.sparc5.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc5_stb2_full = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_full;
wire spc5_stb2_full_w2 = `TOP_DESIGN.sparc5.lsu.stb_ctl2.stb_full_w2;
wire spc5_lmq2_full = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_pcx_rq_vld;
wire spc5_mbar_vld2 = `TOP_DESIGN.sparc5.lsu.dctl.mbar_vld2;
wire spc5_ld2_unfilled = `TOP_DESIGN.sparc5.lsu.qctl1.ld2_unfilled;
wire spc5_flsh_vld2 = `TOP_DESIGN.sparc5.lsu.dctl.flsh_vld2;
reg [9:0] spc5_ld2_unf_cntr;
reg spc5_ld2_unfilled_d;
reg [9:0] spc5_st2_unf_cntr;
reg spc5_st2_unfilled_d;
reg spc5_st2_unfilled;
reg spc5_mbar_vld_d2;
reg spc5_flsh_vld_d2;
reg spc5_lmq2_full_d;
reg [9:0] spc5_lmq_full_cntr2;
reg spc5_lmq_full_capture2;
reg [9:0] spc5_stb_full_cntr2;
reg spc5_stb_full_capture2;
reg [9:0] spc5_mbar_vld_cntr2;
reg spc5_mbar_vld_capture2;
reg [9:0] spc5_flsh_vld_cntr2;
reg spc5_flsh_vld_capture2;
reg spc5_stb_head_hit2;
wire spc5_raw_ack_capture2;
reg [9:0] spc5_stb_ack_cntr2;
reg [9:0] spc5_stb_ced_cntr2;
reg spc5_stb_ced2_d;
reg spc5_stb_ced_capture2;
wire spc5_stb_ced2;
reg spc5_atm2_d;
reg [9:0] spc5_atm_cntr2;
reg spc5_atm_intrpt_capture2;
reg spc5_atm_intrpt_b4capture2;
reg spc5_atm_inv_capture2;
reg [39:0] spc5_stb_wr_addr2;
reg [39:0] spc5_stb_atm_addr2;
reg spc5_atm_lmiss_eq2;
wire [7:0] spc5_stb_state_vld3 = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc5_stb_state_ack3 = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc5_stb_state_ced3 = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc5_stb_state_rst3 = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_state_rst;
wire spc5_stb_ack_vld3 = `TOP_DESIGN.sparc5.lsu.stb_ctl3.ack_vld;
wire spc5_ld3_inst_vld_g = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_inst_vld_g;
wire spc5_intrpt3_cmplt = `TOP_DESIGN.sparc5.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc5_stb3_full = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_full;
wire spc5_stb3_full_w2 = `TOP_DESIGN.sparc5.lsu.stb_ctl3.stb_full_w2;
wire spc5_lmq3_full = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_pcx_rq_vld;
wire spc5_mbar_vld3 = `TOP_DESIGN.sparc5.lsu.dctl.mbar_vld3;
wire spc5_ld3_unfilled = `TOP_DESIGN.sparc5.lsu.qctl1.ld3_unfilled;
wire spc5_flsh_vld3 = `TOP_DESIGN.sparc5.lsu.dctl.flsh_vld3;
reg [9:0] spc5_ld3_unf_cntr;
reg spc5_ld3_unfilled_d;
reg [9:0] spc5_st3_unf_cntr;
reg spc5_st3_unfilled_d;
reg spc5_st3_unfilled;
reg spc5_mbar_vld_d3;
reg spc5_flsh_vld_d3;
reg spc5_lmq3_full_d;
reg [9:0] spc5_lmq_full_cntr3;
reg spc5_lmq_full_capture3;
reg [9:0] spc5_stb_full_cntr3;
reg spc5_stb_full_capture3;
reg [9:0] spc5_mbar_vld_cntr3;
reg spc5_mbar_vld_capture3;
reg [9:0] spc5_flsh_vld_cntr3;
reg spc5_flsh_vld_capture3;
reg spc5_stb_head_hit3;
wire spc5_raw_ack_capture3;
reg [9:0] spc5_stb_ack_cntr3;
reg [9:0] spc5_stb_ced_cntr3;
reg spc5_stb_ced3_d;
reg spc5_stb_ced_capture3;
wire spc5_stb_ced3;
reg spc5_atm3_d;
reg [9:0] spc5_atm_cntr3;
reg spc5_atm_intrpt_capture3;
reg spc5_atm_intrpt_b4capture3;
reg spc5_atm_inv_capture3;
reg [39:0] spc5_stb_wr_addr3;
reg [39:0] spc5_stb_atm_addr3;
reg spc5_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc5_fpick = {spc5_mpick,spc5_spick,spc5_lpick,spc5_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc5_msquash,spc5_apick,spc5_fpick})
9'b000000000 : spc5_fpicko = 1'b0;
9'b0xxx1xxx1 : spc5_fpicko = 1'b0;
9'b1xxxxxxxx : spc5_fpicko = 1'b0;
9'b0xxx0xxx0 : spc5_fpicko = 1'b0;
default:
begin
spc5_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon5 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc5_exu_und = {spc5_l2,
spc5_unc,
spc5_fpld,
spc5_fpldst,
spc5_unflush,
spc5_ldw,
spc5_byp,
spc5_flsh,
spc5_chm,
spc5_ldxa,
spc5_ato,
spc5_pref,
spc5_chit,
spc5_dcp,
spc5_dtp,
spc5_mpc,
spc5_mpu};
always @(spc5_exu_und)
begin
case (spc5_exu_und)
17'h00000 : spc5_exu = 5'h00;
17'h00001 : spc5_exu = 5'h01;
17'h00002 : spc5_exu = 5'h02;
17'h00004 : spc5_exu = 5'h03;
17'h00008 : spc5_exu = 5'h04;
17'h00010 : spc5_exu = 5'h05;
17'h00020 : spc5_exu = 5'h06;
17'h00040 : spc5_exu = 5'h07;
17'h00080 : spc5_exu = 5'h08;
17'h00100 : spc5_exu = 5'h09;
17'h00200 : spc5_exu = 5'h0a;
17'h00400 : spc5_exu = 5'h0b;
17'h00800 : spc5_exu = 5'h0c;
17'h01000 : spc5_exu = 5'h0d;
17'h02000 : spc5_exu = 5'h0e;
17'h04000 : spc5_exu = 5'h0f;
17'h08000 : spc5_exu = 5'h10;
17'h10000 : spc5_exu = 5'h11;
default: spc5_exu = 5'h12;
endcase
end
//excp
assign spc5_exp_und = {spc5_exp_wtchpt_trp_g,
spc5_exp_misalign_addr_ldst_atm_m,
spc5_exp_priv_violtn_g,
spc5_exp_daccess_excptn_g,
spc5_exp_daccess_prot_g,
spc5_exp_priv_action_g,
spc5_exp_spec_access_epage_g,
spc5_exp_uncache_atomic_g,
spc5_exp_illegal_asi_action_g,
spc5_exp_flt_ld_nfo_pg_g,
spc5_exp_asi_rd_unc,
spc5_exp_tlb_data_ce,
spc5_exp_tlb_data_ue,
spc5_exp_tlb_tag_ue,
spc5_exp_unc,
spc5_exp_corr};
always @(spc5_exp_und)
begin
case (spc5_exp_und)
16'h0000 : spc5_exp = 5'h00;
16'h0001 : spc5_exp = 5'h01;
16'h0002 : spc5_exp = 5'h02;
16'h0004 : spc5_exp = 5'h03;
16'h0008 : spc5_exp = 5'h04;
16'h0010 : spc5_exp = 5'h05;
16'h0020 : spc5_exp = 5'h06;
16'h0040 : spc5_exp = 5'h07;
16'h0080 : spc5_exp = 5'h08;
16'h0100 : spc5_exp = 5'h09;
16'h0200 : spc5_exp = 5'h0a;
16'h0400 : spc5_exp = 5'h0b;
16'h0800 : spc5_exp = 5'h0c;
16'h1000 : spc5_exp = 5'h0d;
16'h2000 : spc5_exp = 5'h0e;
16'h4000 : spc5_exp = 5'h0f;
16'h8000 : spc5_exp = 5'h10;
default: spc5_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc5_dctl_stxa_cmplt0 = ((spc5_dctl_stxa_internal_d2 & spc5_dctl_thread0_w3) |
spc5_dctl_stxa_stall_wr_cmplt0_d1);
assign spc5_dctl_l2fill_cmplt0 = (((spc5_dctl_lsu_l2fill_vld & ~spc5_dctl_atomic_ld_squash_e &
~spc5_dctl_lsu_ignore_fill)) & ~spc5_dctl_l2fill_fpld_e &
~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread0);
assign spc5_dctl_fillerr0 = spc5_dctl_l2_corr_error_e & spc5_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc5_dctl_atm_cmplt0 = (spc5_dctl_lsu_atm_st_cmplt_e & ~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread0);
assign spc5_dctl_ldst_cond_cmplt0 = { spc5_dctl_stxa_cmplt0, spc5_dctl_l2fill_cmplt0,
spc5_dctl_atomic_ld_squash_e, spc5_dctl_intld_byp_cmplt[0],
spc5_dctl_bsync0_reset, spc5_dctl_lsu_intrpt_cmplt[0]
};
assign spc5_cmplt0 = { spc5_dctl_ldxa_illgl_va_cmplt_d1, spc5_dctl_pref_tlbmiss_cmplt_d2,
spc5_dctl_lsu_pcx_pref_issue, spc5_dctl_diag_wr_cmplt0, spc5_dctl_l2fill_fpld_e};
always @(spc5_cmplt0 or spc5_dctl_ldst_cond_cmplt0)
begin
case ({spc5_dctl_fillerr0,spc5_dctl_ldst_cond_cmplt0,spc5_cmplt0})
12'h000 : spc5_ldstcond_cmplt0 = 4'h0;
12'h001 : spc5_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc5_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc5_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc5_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc5_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc5_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc5_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc5_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc5_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc5_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc5_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc5_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc5_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc5_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc5_dctl_stxa_cmplt1 = ((spc5_dctl_stxa_internal_d2 & spc5_dctl_thread1_w3) |
spc5_dctl_stxa_stall_wr_cmplt1_d1);
assign spc5_dctl_l2fill_cmplt1 = (((spc5_dctl_lsu_l2fill_vld & ~spc5_dctl_atomic_ld_squash_e &
~spc5_dctl_lsu_ignore_fill)) & ~spc5_dctl_l2fill_fpld_e &
~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread1);
assign spc5_dctl_fillerr1 = spc5_dctl_l2_corr_error_e & spc5_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc5_dctl_atm_cmplt1 = (spc5_dctl_lsu_atm_st_cmplt_e & ~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread1);
assign spc5_dctl_ldst_cond_cmplt1 = { spc5_dctl_stxa_cmplt1, spc5_dctl_l2fill_cmplt1,
spc5_dctl_atomic_ld_squash_e, spc5_dctl_intld_byp_cmplt[1],
spc5_dctl_bsync1_reset, spc5_dctl_lsu_intrpt_cmplt[1]
};
assign spc5_cmplt1 = { spc5_dctl_ldxa_illgl_va_cmplt_d1, spc5_dctl_pref_tlbmiss_cmplt_d2,
spc5_dctl_lsu_pcx_pref_issue, spc5_dctl_diag_wr_cmplt1, spc5_dctl_l2fill_fpld_e};
always @(spc5_cmplt1 or spc5_dctl_ldst_cond_cmplt1)
begin
case ({spc5_dctl_fillerr1,spc5_dctl_ldst_cond_cmplt1,spc5_cmplt1})
12'h000 : spc5_ldstcond_cmplt1 = 4'h0;
12'h001 : spc5_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc5_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc5_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc5_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc5_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc5_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc5_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc5_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc5_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc5_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc5_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc5_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc5_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc5_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc5_dctl_stxa_cmplt2 = ((spc5_dctl_stxa_internal_d2 & spc5_dctl_thread2_w3) |
spc5_dctl_stxa_stall_wr_cmplt2_d1);
assign spc5_dctl_l2fill_cmplt2 = (((spc5_dctl_lsu_l2fill_vld & ~spc5_dctl_atomic_ld_squash_e &
~spc5_dctl_lsu_ignore_fill)) & ~spc5_dctl_l2fill_fpld_e &
~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread2);
assign spc5_dctl_fillerr2 = spc5_dctl_l2_corr_error_e & spc5_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc5_dctl_atm_cmplt2 = (spc5_dctl_lsu_atm_st_cmplt_e & ~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread2);
assign spc5_dctl_ldst_cond_cmplt2 = { spc5_dctl_stxa_cmplt2, spc5_dctl_l2fill_cmplt2,
spc5_dctl_atomic_ld_squash_e, spc5_dctl_intld_byp_cmplt[2],
spc5_dctl_bsync2_reset, spc5_dctl_lsu_intrpt_cmplt[2]
};
assign spc5_cmplt2 = { spc5_dctl_ldxa_illgl_va_cmplt_d1, spc5_dctl_pref_tlbmiss_cmplt_d2,
spc5_dctl_lsu_pcx_pref_issue, spc5_dctl_diag_wr_cmplt2, spc5_dctl_l2fill_fpld_e};
always @(spc5_cmplt2 or spc5_dctl_ldst_cond_cmplt2)
begin
case ({spc5_dctl_fillerr2,spc5_dctl_ldst_cond_cmplt2,spc5_cmplt2})
12'h000 : spc5_ldstcond_cmplt2 = 4'h0;
12'h001 : spc5_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc5_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc5_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc5_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc5_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc5_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc5_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc5_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc5_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc5_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc5_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc5_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc5_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc5_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc5_dctl_stxa_cmplt3 = ((spc5_dctl_stxa_internal_d2 & spc5_dctl_thread3_w3) |
spc5_dctl_stxa_stall_wr_cmplt3_d1);
assign spc5_dctl_l2fill_cmplt3 = (((spc5_dctl_lsu_l2fill_vld & ~spc5_dctl_atomic_ld_squash_e &
~spc5_dctl_lsu_ignore_fill)) & ~spc5_dctl_l2fill_fpld_e &
~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread3);
assign spc5_dctl_fillerr3 = spc5_dctl_l2_corr_error_e & spc5_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc5_dctl_atm_cmplt3 = (spc5_dctl_lsu_atm_st_cmplt_e & ~spc5_dctl_fill_err_trap_e & spc5_dctl_dfill_thread3);
assign spc5_dctl_ldst_cond_cmplt3 = { spc5_dctl_stxa_cmplt3, spc5_dctl_l2fill_cmplt3,
spc5_dctl_atomic_ld_squash_e, spc5_dctl_intld_byp_cmplt[3],
spc5_dctl_bsync3_reset, spc5_dctl_lsu_intrpt_cmplt[3]
};
assign spc5_cmplt3 = { spc5_dctl_ldxa_illgl_va_cmplt_d1, spc5_dctl_pref_tlbmiss_cmplt_d2,
spc5_dctl_lsu_pcx_pref_issue, spc5_dctl_diag_wr_cmplt3, spc5_dctl_l2fill_fpld_e};
always @(spc5_cmplt3 or spc5_dctl_ldst_cond_cmplt3)
begin
case ({spc5_dctl_fillerr3,spc5_dctl_ldst_cond_cmplt3,spc5_cmplt3})
12'h000 : spc5_ldstcond_cmplt3 = 4'h0;
12'h001 : spc5_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc5_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc5_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc5_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc5_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc5_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc5_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc5_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc5_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc5_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc5_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc5_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc5_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc5_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc5_ldstcond_cmplt0 or spc5_ldstcond_cmplt1 or spc5_ldstcond_cmplt2
or spc5_ldstcond_cmplt3 or spc5_dctl_lsu_ifu_ldst_cmplt
or spc5_dctl_late_cmplt0 or spc5_dctl_late_cmplt1 or spc5_dctl_late_cmplt2 or spc5_dctl_late_cmplt3)
begin
case (spc5_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc5_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc5_ldstcond_cmplt_d = spc5_dctl_late_cmplt0 ? spc5_ldstcond_cmplt0_d : spc5_ldstcond_cmplt0;
4'b0010 : spc5_ldstcond_cmplt_d = spc5_dctl_late_cmplt1 ? spc5_ldstcond_cmplt1_d : spc5_ldstcond_cmplt1;
4'b0100 : spc5_ldstcond_cmplt_d = spc5_dctl_late_cmplt2 ? spc5_ldstcond_cmplt2_d : spc5_ldstcond_cmplt2;
4'b1000 : spc5_ldstcond_cmplt_d = spc5_dctl_late_cmplt3 ? spc5_ldstcond_cmplt3_d : spc5_ldstcond_cmplt3;
4'b0011 : spc5_ldstcond_cmplt_d = 4'he;
4'b0101 : spc5_ldstcond_cmplt_d = 4'he;
4'b1001 : spc5_ldstcond_cmplt_d = 4'he;
4'b0110 : spc5_ldstcond_cmplt_d = 4'he;
4'b1010 : spc5_ldstcond_cmplt_d = 4'he;
4'b1100 : spc5_ldstcond_cmplt_d = 4'he;
default:
begin
spc5_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc5_st_ooo_ret = { spc5_st0_lt_1, spc5_st0_lt_2, spc5_st0_lt_3,
spc5_st1_lt_0, spc5_st1_lt_2, spc5_st1_lt_3,
spc5_st2_lt_0, spc5_st2_lt_1, spc5_st2_lt_3,
spc5_st3_lt_0, spc5_st3_lt_1, spc5_st3_lt_2};
always @(posedge clk)
begin
if(~spc5_st0_unfilled || ~rst_l)
spc5_st0_unfilled_d <= 1'b0;
else
spc5_st0_unfilled_d <= spc5_st0_unfilled;
if(~rst_l)
spc5_ldstcond_cmplt0_d <= 4'h0;
else
spc5_ldstcond_cmplt0_d <= spc5_ldstcond_cmplt0;
if(~spc5_ld0_pkt_vld_unmasked || ~rst_l)
spc5_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc5_ld0_pkt_vld_unmasked_d <= spc5_ld0_pkt_vld_unmasked;
if(~rst_l)
spc5_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc5_qctl1_ld_sec_hit_thrd0 && spc5_qctl1_ld0_inst_vld_g)
spc5_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc5_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc5_st1_unfilled || ~rst_l)
spc5_st1_unfilled_d <= 1'b0;
else
spc5_st1_unfilled_d <= spc5_st1_unfilled;
if(~rst_l)
spc5_ldstcond_cmplt1_d <= 4'h0;
else
spc5_ldstcond_cmplt1_d <= spc5_ldstcond_cmplt1;
if(~spc5_ld1_pkt_vld_unmasked || ~rst_l)
spc5_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc5_ld1_pkt_vld_unmasked_d <= spc5_ld1_pkt_vld_unmasked;
if(~rst_l)
spc5_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc5_qctl1_ld_sec_hit_thrd1 && spc5_qctl1_ld1_inst_vld_g)
spc5_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc5_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc5_st2_unfilled || ~rst_l)
spc5_st2_unfilled_d <= 1'b0;
else
spc5_st2_unfilled_d <= spc5_st2_unfilled;
if(~rst_l)
spc5_ldstcond_cmplt2_d <= 4'h0;
else
spc5_ldstcond_cmplt2_d <= spc5_ldstcond_cmplt2;
if(~spc5_ld2_pkt_vld_unmasked || ~rst_l)
spc5_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc5_ld2_pkt_vld_unmasked_d <= spc5_ld2_pkt_vld_unmasked;
if(~rst_l)
spc5_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc5_qctl1_ld_sec_hit_thrd2 && spc5_qctl1_ld2_inst_vld_g)
spc5_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc5_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc5_st3_unfilled || ~rst_l)
spc5_st3_unfilled_d <= 1'b0;
else
spc5_st3_unfilled_d <= spc5_st3_unfilled;
if(~rst_l)
spc5_ldstcond_cmplt3_d <= 4'h0;
else
spc5_ldstcond_cmplt3_d <= spc5_ldstcond_cmplt3;
if(~spc5_ld3_pkt_vld_unmasked || ~rst_l)
spc5_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc5_ld3_pkt_vld_unmasked_d <= spc5_ld3_pkt_vld_unmasked;
if(~rst_l)
spc5_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc5_qctl1_ld_sec_hit_thrd3 && spc5_qctl1_ld3_inst_vld_g)
spc5_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc5_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc5_stb_state_ced0) && (|spc5_stb_state_rst0)) || ~rst_l)
spc5_st0_unfilled <= 1'b0;
else if( ((|spc5_stb_state_ced0) && ~(|spc5_stb_state_rst0)))
spc5_st0_unfilled <= 1'b1;
else
spc5_st0_unfilled <= spc5_st0_unfilled;
if( ((|spc5_stb_state_ced1) && (|spc5_stb_state_rst1)) || ~rst_l)
spc5_st1_unfilled <= 1'b0;
else if( ((|spc5_stb_state_ced1) && ~(|spc5_stb_state_rst1)))
spc5_st1_unfilled <= 1'b1;
else
spc5_st1_unfilled <= spc5_st1_unfilled;
if( ((|spc5_stb_state_ced2) && (|spc5_stb_state_rst2)) || ~rst_l)
spc5_st2_unfilled <= 1'b0;
else if( ((|spc5_stb_state_ced2) && ~(|spc5_stb_state_rst2)))
spc5_st2_unfilled <= 1'b1;
else
spc5_st2_unfilled <= spc5_st2_unfilled;
if( ((|spc5_stb_state_ced3) && (|spc5_stb_state_rst3)) || ~rst_l)
spc5_st3_unfilled <= 1'b0;
else if( ((|spc5_stb_state_ced3) && ~(|spc5_stb_state_rst3)))
spc5_st3_unfilled <= 1'b1;
else
spc5_st3_unfilled <= spc5_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc5_st0_unfilled && spc5_st0_unfilled_d)|| ~rst_l)
begin
spc5_st0_unf_cntr <= 9'h000;
end
else if(spc5_st0_unfilled)
begin
spc5_st0_unf_cntr <= spc5_st0_unf_cntr + 1;
end
else
begin
spc5_st0_unf_cntr <= spc5_st0_unf_cntr;
end
if((~spc5_st1_unfilled && spc5_st1_unfilled_d)|| ~rst_l)
begin
spc5_st1_unf_cntr <= 9'h000;
end
else if(spc5_st1_unfilled)
begin
spc5_st1_unf_cntr <= spc5_st1_unf_cntr + 1;
end
else
begin
spc5_st1_unf_cntr <= spc5_st1_unf_cntr;
end
if((~spc5_st2_unfilled && spc5_st2_unfilled_d)|| ~rst_l)
begin
spc5_st2_unf_cntr <= 9'h000;
end
else if(spc5_st2_unfilled)
begin
spc5_st2_unf_cntr <= spc5_st2_unf_cntr + 1;
end
else
begin
spc5_st2_unf_cntr <= spc5_st2_unf_cntr;
end
if((~spc5_st3_unfilled && spc5_st3_unfilled_d)|| ~rst_l)
begin
spc5_st3_unf_cntr <= 9'h000;
end
else if(spc5_st3_unfilled)
begin
spc5_st3_unf_cntr <= spc5_st3_unf_cntr + 1;
end
else
begin
spc5_st3_unf_cntr <= spc5_st3_unf_cntr;
end
end
always @(spc5_st0_unfilled or spc5_st1_unfilled or spc5_st2_unfilled or spc5_st3_unfilled
or spc5_st0_unfilled_d or spc5_st1_unfilled_d or spc5_st2_unfilled_d or spc5_st3_unfilled_d)
begin
if(~spc5_st0_unfilled && spc5_st0_unfilled_d && spc5_st1_unfilled)
spc5_st0_lt_1 <= (spc5_st1_unf_cntr > spc5_st0_unf_cntr);
else
spc5_st0_lt_1 <= 1'b0;
if(~spc5_st0_unfilled && spc5_st0_unfilled_d && spc5_st2_unfilled)
spc5_st0_lt_2 <= (spc5_st2_unf_cntr > spc5_st0_unf_cntr);
else
spc5_st0_lt_2 <= 1'b0;
if(~spc5_st0_unfilled && spc5_st0_unfilled_d && spc5_st3_unfilled)
spc5_st0_lt_3 <= (spc5_st3_unf_cntr > spc5_st0_unf_cntr);
else
spc5_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc5_st1_unfilled && spc5_st1_unfilled_d && spc5_st0_unfilled)
spc5_st1_lt_0 <= (spc5_st0_unf_cntr > spc5_st1_unf_cntr);
else
spc5_st1_lt_0 <= 1'b0;
if(~spc5_st1_unfilled && spc5_st1_unfilled_d && spc5_st2_unfilled)
spc5_st1_lt_2 <= (spc5_st2_unf_cntr > spc5_st1_unf_cntr);
else
spc5_st1_lt_2 <= 1'b0;
if(~spc5_st1_unfilled && spc5_st1_unfilled_d && spc5_st3_unfilled)
spc5_st1_lt_3 <= (spc5_st3_unf_cntr > spc5_st1_unf_cntr);
else
spc5_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc5_st2_unfilled && spc5_st2_unfilled_d && spc5_st0_unfilled)
spc5_st2_lt_0 <= (spc5_st0_unf_cntr > spc5_st2_unf_cntr);
else
spc5_st2_lt_0 <= 1'b0;
if(~spc5_st2_unfilled && spc5_st2_unfilled_d && spc5_st1_unfilled)
spc5_st2_lt_1 <= (spc5_st1_unf_cntr > spc5_st2_unf_cntr);
else
spc5_st2_lt_1 <= 1'b0;
if(~spc5_st2_unfilled && spc5_st2_unfilled_d && spc5_st3_unfilled)
spc5_st2_lt_3 <= (spc5_st3_unf_cntr > spc5_st2_unf_cntr);
else
spc5_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc5_st3_unfilled && spc5_st3_unfilled_d && spc5_st0_unfilled)
spc5_st3_lt_0 <= (spc5_st0_unf_cntr > spc5_st3_unf_cntr);
else
spc5_st3_lt_0 <= 1'b0;
if(~spc5_st3_unfilled && spc5_st3_unfilled_d && spc5_st1_unfilled)
spc5_st3_lt_1 <= (spc5_st1_unf_cntr > spc5_st3_unf_cntr);
else
spc5_st3_lt_1 <= 1'b0;
if(~spc5_st3_unfilled && spc5_st3_unfilled_d && spc5_st2_unfilled)
spc5_st3_lt_2 <= (spc5_st2_unf_cntr > spc5_st3_unf_cntr);
else
spc5_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc5_ld_ooo_ret = { spc5_ld0_lt_1, spc5_ld0_lt_2, spc5_ld0_lt_3,
spc5_ld1_lt_0, spc5_ld1_lt_2, spc5_ld1_lt_3,
spc5_ld2_lt_0, spc5_ld2_lt_1, spc5_ld2_lt_3,
spc5_ld3_lt_0, spc5_ld3_lt_1, spc5_ld3_lt_2};
always @(posedge clk)
begin
if((~spc5_ld0_unfilled && spc5_ld0_unfilled_d)|| ~rst_l)
begin
spc5_ld0_unf_cntr <= 9'h000;
end
else if(spc5_ld0_unfilled)
begin
spc5_ld0_unf_cntr <= spc5_ld0_unf_cntr + 1;
end
else
begin
spc5_ld0_unf_cntr <= spc5_ld0_unf_cntr;
end
if((~spc5_ld1_unfilled && spc5_ld1_unfilled_d)|| ~rst_l)
begin
spc5_ld1_unf_cntr <= 9'h000;
end
else if(spc5_ld1_unfilled)
begin
spc5_ld1_unf_cntr <= spc5_ld1_unf_cntr + 1;
end
else
begin
spc5_ld1_unf_cntr <= spc5_ld1_unf_cntr;
end
if((~spc5_ld2_unfilled && spc5_ld2_unfilled_d)|| ~rst_l)
begin
spc5_ld2_unf_cntr <= 9'h000;
end
else if(spc5_ld2_unfilled)
begin
spc5_ld2_unf_cntr <= spc5_ld2_unf_cntr + 1;
end
else
begin
spc5_ld2_unf_cntr <= spc5_ld2_unf_cntr;
end
if((~spc5_ld3_unfilled && spc5_ld3_unfilled_d)|| ~rst_l)
begin
spc5_ld3_unf_cntr <= 9'h000;
end
else if(spc5_ld3_unfilled)
begin
spc5_ld3_unf_cntr <= spc5_ld3_unf_cntr + 1;
end
else
begin
spc5_ld3_unf_cntr <= spc5_ld3_unf_cntr;
end
end
always @(spc5_ld0_unfilled or spc5_ld1_unfilled or spc5_ld2_unfilled or spc5_ld3_unfilled
or spc5_ld0_unfilled_d or spc5_ld1_unfilled_d or spc5_ld2_unfilled_d or spc5_ld3_unfilled_d)
begin
if(~spc5_ld0_unfilled && spc5_ld0_unfilled_d && spc5_ld1_unfilled)
spc5_ld0_lt_1 <= (spc5_ld1_unf_cntr > spc5_ld0_unf_cntr);
else
spc5_ld0_lt_1 <= 1'b0;
if(~spc5_ld0_unfilled && spc5_ld0_unfilled_d && spc5_ld2_unfilled)
spc5_ld0_lt_2 <= (spc5_ld2_unf_cntr > spc5_ld0_unf_cntr);
else
spc5_ld0_lt_2 <= 1'b0;
if(~spc5_ld0_unfilled && spc5_ld0_unfilled_d && spc5_ld3_unfilled)
spc5_ld0_lt_3 <= (spc5_ld3_unf_cntr > spc5_ld0_unf_cntr);
else
spc5_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc5_ld1_unfilled && spc5_ld1_unfilled_d && spc5_ld0_unfilled)
spc5_ld1_lt_0 <= (spc5_ld0_unf_cntr > spc5_ld1_unf_cntr);
else
spc5_ld1_lt_0 <= 1'b0;
if(~spc5_ld1_unfilled && spc5_ld1_unfilled_d && spc5_ld2_unfilled)
spc5_ld1_lt_2 <= (spc5_ld2_unf_cntr > spc5_ld1_unf_cntr);
else
spc5_ld1_lt_2 <= 1'b0;
if(~spc5_ld1_unfilled && spc5_ld1_unfilled_d && spc5_ld3_unfilled)
spc5_ld1_lt_3 <= (spc5_ld3_unf_cntr > spc5_ld1_unf_cntr);
else
spc5_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc5_ld2_unfilled && spc5_ld2_unfilled_d && spc5_ld0_unfilled)
spc5_ld2_lt_0 <= (spc5_ld0_unf_cntr > spc5_ld2_unf_cntr);
else
spc5_ld2_lt_0 <= 1'b0;
if(~spc5_ld2_unfilled && spc5_ld2_unfilled_d && spc5_ld1_unfilled)
spc5_ld2_lt_1 <= (spc5_ld1_unf_cntr > spc5_ld2_unf_cntr);
else
spc5_ld2_lt_1 <= 1'b0;
if(~spc5_ld2_unfilled && spc5_ld2_unfilled_d && spc5_ld3_unfilled)
spc5_ld2_lt_3 <= (spc5_ld3_unf_cntr > spc5_ld2_unf_cntr);
else
spc5_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc5_ld3_unfilled && spc5_ld3_unfilled_d && spc5_ld0_unfilled)
spc5_ld3_lt_0 <= (spc5_ld0_unf_cntr > spc5_ld3_unf_cntr);
else
spc5_ld3_lt_0 <= 1'b0;
if(~spc5_ld3_unfilled && spc5_ld3_unfilled_d && spc5_ld1_unfilled)
spc5_ld3_lt_1 <= (spc5_ld1_unf_cntr > spc5_ld3_unf_cntr);
else
spc5_ld3_lt_1 <= 1'b0;
if(~spc5_ld3_unfilled && spc5_ld3_unfilled_d && spc5_ld2_unfilled)
spc5_ld3_lt_2 <= (spc5_ld2_unf_cntr > spc5_ld3_unf_cntr);
else
spc5_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc5_dctl_bld_hit =
((|spc5_dctl_lsu_way_hit[3:0]) & spc5_dctl_dcache_enable_g &
~spc5_dctl_ldxa_internal & ~spc5_dctl_dcache_rd_parity_error & ~spc5_dctl_dtag_perror_g &
~spc5_dctl_endian_mispred_g &
~spc5_dctl_atomic_g & ~spc5_dctl_ncache_asild_rq_g) & ~spc5_dctl_tte_data_perror_unc &
spc5_dctl_ld_inst_vld_g & spc5_qctl1_bld_g ;
assign spc5_dctl_bld_stb_hit = spc5_dctl_bld_hit & spc5_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc5_bld0_full_d <= 2'b00;
spc5_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc5_bld0_full_d <= spc5_qctl1_bld_cnt;
spc5_ld0_unfilled_d <= spc5_ld0_unfilled;
end
if(~rst_l)
begin
spc5_bld1_full_d <= 2'b00;
spc5_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc5_bld1_full_d <= spc5_qctl1_bld_cnt;
spc5_ld1_unfilled_d <= spc5_ld1_unfilled;
end
if(~rst_l)
begin
spc5_bld2_full_d <= 2'b00;
spc5_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc5_bld2_full_d <= spc5_qctl1_bld_cnt;
spc5_ld2_unfilled_d <= spc5_ld2_unfilled;
end
if(~rst_l)
begin
spc5_bld3_full_d <= 2'b00;
spc5_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc5_bld3_full_d <= spc5_qctl1_bld_cnt;
spc5_ld3_unfilled_d <= spc5_ld3_unfilled;
end
end
always @(spc5_bld0_full_d or spc5_qctl1_bld_cnt)
begin
if( (spc5_bld0_full_d != spc5_qctl1_bld_cnt) && (spc5_bld0_full_d == 2'd0))
spc5_bld0_full_capture <= 1'b1;
else
spc5_bld0_full_capture <= 1'b0;
end
always @(spc5_bld1_full_d or spc5_qctl1_bld_cnt)
begin
if( (spc5_bld1_full_d != spc5_qctl1_bld_cnt) && (spc5_bld1_full_d == 2'd1))
spc5_bld1_full_capture <= 1'b1;
else
spc5_bld1_full_capture <= 1'b0;
end
always @(spc5_bld2_full_d or spc5_qctl1_bld_cnt)
begin
if( (spc5_bld2_full_d != spc5_qctl1_bld_cnt) && (spc5_bld2_full_d == 2'd2))
spc5_bld2_full_capture <= 1'b1;
else
spc5_bld2_full_capture <= 1'b0;
end
always @(spc5_bld3_full_d or spc5_qctl1_bld_cnt)
begin
if( (spc5_bld3_full_d != spc5_qctl1_bld_cnt) && (spc5_bld3_full_d == 2'd3))
spc5_bld3_full_capture <= 1'b1;
else
spc5_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc5_qctl1_bld_cnt != 2'b00) && (spc5_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc5_bld0_full_cntr <= 9'h000;
end
else if(spc5_qctl1_bld_g && (spc5_qctl1_bld_cnt == 2'b00))
begin
spc5_bld0_full_cntr <= spc5_bld0_full_cntr + 1;
end
else if( (spc5_qctl1_bld_cnt == 2'b00) && (spc5_bld0_full_cntr != 9'h000))
begin
spc5_bld0_full_cntr <= spc5_bld0_full_cntr + 1;
end
else
begin
spc5_bld0_full_cntr <= spc5_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc5_qctl1_bld_cnt != 2'b01) && (spc5_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc5_bld1_full_cntr <= 9'h000;
end
else if(spc5_qctl1_bld_cnt == 2'b01)
begin
spc5_bld1_full_cntr <= spc5_bld1_full_cntr + 1;
end
else if( (spc5_qctl1_bld_cnt == 2'b01) && (spc5_bld1_full_cntr != 9'h000))
begin
spc5_bld1_full_cntr <= spc5_bld1_full_cntr + 1;
end
else
begin
spc5_bld1_full_cntr <= spc5_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc5_qctl1_bld_cnt != 2'b10) && (spc5_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc5_bld2_full_cntr <= 9'h000;
end
else if(spc5_qctl1_bld_cnt == 2'b10)
begin
spc5_bld2_full_cntr <= spc5_bld2_full_cntr + 1;
end
else if( (spc5_qctl1_bld_cnt == 2'b10) && (spc5_bld2_full_cntr != 9'h000))
begin
spc5_bld2_full_cntr <= spc5_bld2_full_cntr + 1;
end
else
begin
spc5_bld2_full_cntr <= spc5_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc5_qctl1_bld_cnt != 2'b11) && (spc5_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc5_bld3_full_cntr <= 9'h000;
end
else if(spc5_qctl1_bld_cnt == 2'b11)
begin
spc5_bld3_full_cntr <= spc5_bld3_full_cntr + 1;
end
else if( (spc5_qctl1_bld_cnt == 2'b11) && (spc5_bld3_full_cntr != 9'h000))
begin
spc5_bld3_full_cntr <= spc5_bld3_full_cntr + 1;
end
else
begin
spc5_bld3_full_cntr <= spc5_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc5_stb_state_vld0) && ~spc5_atomic_g) || ~rst_l)
begin
spc5_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc5_atomic_g && (spc5_atm_type0 != 8'h00) && spc5_wptr_vld)
begin
spc5_stb_atm_addr0 <= {spc5_wdata_ramc[44:9],spc5_wdata_ramd[67:64]};
end
else
begin
spc5_stb_atm_addr0 <= spc5_stb_atm_addr0;
end
if( ( ~(|spc5_stb_state_vld1) && ~spc5_atomic_g) || ~rst_l)
begin
spc5_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc5_atomic_g && (spc5_atm_type1 != 8'h00) && spc5_wptr_vld)
begin
spc5_stb_atm_addr1 <= {spc5_wdata_ramc[44:9],spc5_wdata_ramd[67:64]};
end
else
begin
spc5_stb_atm_addr1 <= spc5_stb_atm_addr1;
end
if( ( ~(|spc5_stb_state_vld2) && ~spc5_atomic_g) || ~rst_l)
begin
spc5_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc5_atomic_g && (spc5_atm_type2 != 8'h00) && spc5_wptr_vld)
begin
spc5_stb_atm_addr2 <= {spc5_wdata_ramc[44:9],spc5_wdata_ramd[67:64]};
end
else
begin
spc5_stb_atm_addr2 <= spc5_stb_atm_addr2;
end
if( ( ~(|spc5_stb_state_vld3) && ~spc5_atomic_g) || ~rst_l)
begin
spc5_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc5_atomic_g && (spc5_atm_type3 != 8'h00) && spc5_wptr_vld)
begin
spc5_stb_atm_addr3 <= {spc5_wdata_ramc[44:9],spc5_wdata_ramd[67:64]};
end
else
begin
spc5_stb_atm_addr3 <= spc5_stb_atm_addr3;
end
end
assign spc5_dfq_full = (spc5_dfq_vld_entries >= 3'd4);
assign spc5_dfq_full1 = (spc5_dfq_vld_entries >= (3'd4 + 1));
always @(spc5_dfq_full_d1 or spc5_dfq_full1)
begin
if (spc5_dfq_full_d1 && ~spc5_dfq_full1)
spc5_dfq_full_capture1 <= 1'b1;
else
spc5_dfq_full_capture1 <= 1'b0;
end
assign spc5_dfq_full2 = (spc5_dfq_vld_entries >= (3'd4 + 2));
always @(spc5_dfq_full_d2 or spc5_dfq_full2)
begin
if (spc5_dfq_full_d2 && ~spc5_dfq_full2)
spc5_dfq_full_capture2 <= 1'b1;
else
spc5_dfq_full_capture2 <= 1'b0;
end
assign spc5_dfq_full3 = (spc5_dfq_vld_entries >= (3'd4 + 3));
always @(spc5_dfq_full_d3 or spc5_dfq_full3)
begin
if (spc5_dfq_full_d3 && ~spc5_dfq_full3)
spc5_dfq_full_capture3 <= 1'b1;
else
spc5_dfq_full_capture3 <= 1'b0;
end
assign spc5_dfq_full4 = (spc5_dfq_vld_entries >= (3'd4 + 4));
always @(spc5_dfq_full_d4 or spc5_dfq_full4)
begin
if (spc5_dfq_full_d4 && ~spc5_dfq_full4)
spc5_dfq_full_capture4 <= 1'b1;
else
spc5_dfq_full_capture4 <= 1'b0;
end
assign spc5_dfq_full5 = (spc5_dfq_vld_entries >= (3'd4 + 5));
always @(spc5_dfq_full_d5 or spc5_dfq_full5)
begin
if (spc5_dfq_full_d5 && ~spc5_dfq_full5)
spc5_dfq_full_capture5 <= 1'b1;
else
spc5_dfq_full_capture5 <= 1'b0;
end
assign spc5_dfq_full6 = (spc5_dfq_vld_entries >= (3'd4 + 6));
always @(spc5_dfq_full_d6 or spc5_dfq_full6)
begin
if (spc5_dfq_full_d6 && ~spc5_dfq_full6)
spc5_dfq_full_capture6 <= 1'b1;
else
spc5_dfq_full_capture6 <= 1'b0;
end
assign spc5_dfq_full7 = (spc5_dfq_vld_entries >= (3'd4 + 7));
always @(spc5_dfq_full_d7 or spc5_dfq_full7)
begin
if (spc5_dfq_full_d7 && ~spc5_dfq_full7)
spc5_dfq_full_capture7 <= 1'b1;
else
spc5_dfq_full_capture7 <= 1'b0;
end
always @(spc5_mbar_vld_d0 or spc5_mbar_vld0)
begin
if (spc5_mbar_vld_d0 && ~spc5_mbar_vld0)
spc5_mbar_vld_capture0 <= 1'b1;
else
spc5_mbar_vld_capture0 <= 1'b0;
end
always @(spc5_mbar_vld_d1 or spc5_mbar_vld1)
begin
if (spc5_mbar_vld_d1 && ~spc5_mbar_vld1)
spc5_mbar_vld_capture1 <= 1'b1;
else
spc5_mbar_vld_capture1 <= 1'b0;
end
always @(spc5_mbar_vld_d2 or spc5_mbar_vld2)
begin
if (spc5_mbar_vld_d2 && ~spc5_mbar_vld2)
spc5_mbar_vld_capture2 <= 1'b1;
else
spc5_mbar_vld_capture2 <= 1'b0;
end
always @(spc5_mbar_vld_d3 or spc5_mbar_vld3)
begin
if (spc5_mbar_vld_d3 && ~spc5_mbar_vld3)
spc5_mbar_vld_capture3 <= 1'b1;
else
spc5_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc5_dfq_full1 && (spc5_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr1 <= 9'h000;
spc5_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr1);
end
else if( spc5_dfq_full1)
begin
spc5_dfq_full_cntr1 <= spc5_dfq_full_cntr1 + 1;
spc5_dfq_full_d1 <= spc5_dfq_full1;
end
else
begin
spc5_dfq_full_cntr1 <= spc5_dfq_full_cntr1;
spc5_dfq_full_d1 <= spc5_dfq_full1;
end
if( ( ~spc5_dfq_full2 && (spc5_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr2 <= 9'h000;
spc5_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr2);
end
else if( spc5_dfq_full2)
begin
spc5_dfq_full_cntr2 <= spc5_dfq_full_cntr2 + 1;
spc5_dfq_full_d2 <= spc5_dfq_full2;
end
else
begin
spc5_dfq_full_cntr2 <= spc5_dfq_full_cntr2;
spc5_dfq_full_d2 <= spc5_dfq_full2;
end
if( ( ~spc5_dfq_full3 && (spc5_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr3 <= 9'h000;
spc5_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr3);
end
else if( spc5_dfq_full3)
begin
spc5_dfq_full_cntr3 <= spc5_dfq_full_cntr3 + 1;
spc5_dfq_full_d3 <= spc5_dfq_full3;
end
else
begin
spc5_dfq_full_cntr3 <= spc5_dfq_full_cntr3;
spc5_dfq_full_d3 <= spc5_dfq_full3;
end
if( ( ~spc5_dfq_full4 && (spc5_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr4 <= 9'h000;
spc5_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr4);
end
else if( spc5_dfq_full4)
begin
spc5_dfq_full_cntr4 <= spc5_dfq_full_cntr4 + 1;
spc5_dfq_full_d4 <= spc5_dfq_full4;
end
else
begin
spc5_dfq_full_cntr4 <= spc5_dfq_full_cntr4;
spc5_dfq_full_d4 <= spc5_dfq_full4;
end
if( ( ~spc5_dfq_full5 && (spc5_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr5 <= 9'h000;
spc5_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr5);
end
else if( spc5_dfq_full5)
begin
spc5_dfq_full_cntr5 <= spc5_dfq_full_cntr5 + 1;
spc5_dfq_full_d5 <= spc5_dfq_full5;
end
else
begin
spc5_dfq_full_cntr5 <= spc5_dfq_full_cntr5;
spc5_dfq_full_d5 <= spc5_dfq_full5;
end
if( ( ~spc5_dfq_full6 && (spc5_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr6 <= 9'h000;
spc5_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr6);
end
else if( spc5_dfq_full6)
begin
spc5_dfq_full_cntr6 <= spc5_dfq_full_cntr6 + 1;
spc5_dfq_full_d6 <= spc5_dfq_full6;
end
else
begin
spc5_dfq_full_cntr6 <= spc5_dfq_full_cntr6;
spc5_dfq_full_d6 <= spc5_dfq_full6;
end
if( ( ~spc5_dfq_full7 && (spc5_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr7 <= 9'h000;
spc5_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr7);
end
else if( spc5_dfq_full7)
begin
spc5_dfq_full_cntr7 <= spc5_dfq_full_cntr7 + 1;
spc5_dfq_full_d7 <= spc5_dfq_full7;
end
else
begin
spc5_dfq_full_cntr7 <= spc5_dfq_full_cntr7;
spc5_dfq_full_d7 <= spc5_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc5_intrpt0_cmplt or spc5_atm_cntr0 or spc5_stb_state_ced0)
begin
if (spc5_intrpt0_cmplt && (spc5_atm_cntr0 != 9'h000) && ~(|spc5_stb_state_ced0))
spc5_atm_intrpt_b4capture0 <= 1'b1;
else
spc5_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc5_intrpt1_cmplt or spc5_atm_cntr1 or spc5_stb_state_ced1)
begin
if (spc5_intrpt1_cmplt && (spc5_atm_cntr1 != 9'h000) && ~(|spc5_stb_state_ced1))
spc5_atm_intrpt_b4capture1 <= 1'b1;
else
spc5_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc5_intrpt2_cmplt or spc5_atm_cntr2 or spc5_stb_state_ced2)
begin
if (spc5_intrpt2_cmplt && (spc5_atm_cntr2 != 9'h000) && ~(|spc5_stb_state_ced2))
spc5_atm_intrpt_b4capture2 <= 1'b1;
else
spc5_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc5_intrpt3_cmplt or spc5_atm_cntr3 or spc5_stb_state_ced3)
begin
if (spc5_intrpt3_cmplt && (spc5_atm_cntr3 != 9'h000) && ~(|spc5_stb_state_ced3))
spc5_atm_intrpt_b4capture3 <= 1'b1;
else
spc5_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc5_intrpt0_cmplt or spc5_atm_cntr0 or spc5_stb_state_ced0)
begin
if (spc5_intrpt0_cmplt && (spc5_atm_cntr0 != 9'h000) && (|spc5_stb_state_ced0))
spc5_atm_intrpt_capture0 <= 1'b1;
else
spc5_atm_intrpt_capture0 <= 1'b0;
end
always @(spc5_intrpt1_cmplt or spc5_atm_cntr1 or spc5_stb_state_ced1)
begin
if (spc5_intrpt1_cmplt && (spc5_atm_cntr1 != 9'h000) && (|spc5_stb_state_ced1))
spc5_atm_intrpt_capture1 <= 1'b1;
else
spc5_atm_intrpt_capture1 <= 1'b0;
end
always @(spc5_intrpt2_cmplt or spc5_atm_cntr2 or spc5_stb_state_ced2)
begin
if (spc5_intrpt2_cmplt && (spc5_atm_cntr2 != 9'h000) && (|spc5_stb_state_ced2))
spc5_atm_intrpt_capture2 <= 1'b1;
else
spc5_atm_intrpt_capture2 <= 1'b0;
end
always @(spc5_intrpt3_cmplt or spc5_atm_cntr3 or spc5_stb_state_ced3)
begin
if (spc5_intrpt3_cmplt && (spc5_atm_cntr3 != 9'h000) && (|spc5_stb_state_ced3))
spc5_atm_intrpt_capture3 <= 1'b1;
else
spc5_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc5_atm_cntr0 or spc5_dva_din or spc5_dva_wen)
begin
if (~spc5_dva_din && spc5_dva_wen && (spc5_atm_cntr0 != 9'h000))
spc5_atm_inv_capture0 <= 1'b1;
else
spc5_atm_inv_capture0 <= 1'b0;
end
always @(spc5_atm_cntr1 or spc5_dva_din or spc5_dva_wen)
begin
if (~spc5_dva_din && spc5_dva_wen && (spc5_atm_cntr1 != 9'h000))
spc5_atm_inv_capture1 <= 1'b1;
else
spc5_atm_inv_capture1 <= 1'b0;
end
always @(spc5_atm_cntr2 or spc5_dva_din or spc5_dva_wen)
begin
if (~spc5_dva_din && spc5_dva_wen && (spc5_atm_cntr2 != 9'h000))
spc5_atm_inv_capture2 <= 1'b1;
else
spc5_atm_inv_capture2 <= 1'b0;
end
always @(spc5_atm_cntr3 or spc5_dva_din or spc5_dva_wen)
begin
if (~spc5_dva_din && spc5_dva_wen && (spc5_atm_cntr3 != 9'h000))
spc5_atm_inv_capture3 <= 1'b1;
else
spc5_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc5_stb_state_vld0) && (spc5_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_atm_cntr0 <= 9'h000;
spc5_atm0_d <= 1'b0;
end
else if( spc5_atomic_g && (spc5_atm_type0 != 8'h00))
begin
spc5_atm_cntr0 <= spc5_atm_cntr0 + 1;
spc5_atm0_d <= 1'b1;
end
else if( spc5_atm0_d && (|spc5_stb_state_vld0))
begin
spc5_atm_cntr0 <= spc5_atm_cntr0 + 1;
spc5_atm0_d <= spc5_atm0_d;
end
else
begin
spc5_atm_cntr0 <= spc5_atm_cntr0;
spc5_atm0_d <= spc5_atm0_d;
end
if( ( ~(|spc5_stb_state_vld1) && (spc5_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_atm_cntr1 <= 9'h000;
spc5_atm1_d <= 1'b0;
end
else if( spc5_atomic_g && (spc5_atm_type1 != 8'h00))
begin
spc5_atm_cntr1 <= spc5_atm_cntr1 + 1;
spc5_atm1_d <= 1'b1;
end
else if( spc5_atm1_d && (|spc5_stb_state_vld1))
begin
spc5_atm_cntr1 <= spc5_atm_cntr1 + 1;
spc5_atm1_d <= spc5_atm1_d;
end
else
begin
spc5_atm_cntr1 <= spc5_atm_cntr1;
spc5_atm1_d <= spc5_atm1_d;
end
if( ( ~(|spc5_stb_state_vld2) && (spc5_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_atm_cntr2 <= 9'h000;
spc5_atm2_d <= 1'b0;
end
else if( spc5_atomic_g && (spc5_atm_type2 != 8'h00))
begin
spc5_atm_cntr2 <= spc5_atm_cntr2 + 1;
spc5_atm2_d <= 1'b1;
end
else if( spc5_atm2_d && (|spc5_stb_state_vld2))
begin
spc5_atm_cntr2 <= spc5_atm_cntr2 + 1;
spc5_atm2_d <= spc5_atm2_d;
end
else
begin
spc5_atm_cntr2 <= spc5_atm_cntr2;
spc5_atm2_d <= spc5_atm2_d;
end
if( ( ~(|spc5_stb_state_vld3) && (spc5_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_atm_cntr3 <= 9'h000;
spc5_atm3_d <= 1'b0;
end
else if( spc5_atomic_g && (spc5_atm_type3 != 8'h00))
begin
spc5_atm_cntr3 <= spc5_atm_cntr3 + 1;
spc5_atm3_d <= 1'b1;
end
else if( spc5_atm3_d && (|spc5_stb_state_vld3))
begin
spc5_atm_cntr3 <= spc5_atm_cntr3 + 1;
spc5_atm3_d <= spc5_atm3_d;
end
else
begin
spc5_atm_cntr3 <= spc5_atm_cntr3;
spc5_atm3_d <= spc5_atm3_d;
end
end
assign spc5_raw_ack_capture0 = spc5_stb_ack_vld0 && (spc5_stb_ack_cntr0 != 9'h000);
assign spc5_stb_ced0 = |spc5_stb_state_ced0;
assign spc5_raw_ack_capture1 = spc5_stb_ack_vld1 && (spc5_stb_ack_cntr1 != 9'h000);
assign spc5_stb_ced1 = |spc5_stb_state_ced1;
assign spc5_raw_ack_capture2 = spc5_stb_ack_vld2 && (spc5_stb_ack_cntr2 != 9'h000);
assign spc5_stb_ced2 = |spc5_stb_state_ced2;
assign spc5_raw_ack_capture3 = spc5_stb_ack_vld3 && (spc5_stb_ack_cntr3 != 9'h000);
assign spc5_stb_ced3 = |spc5_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc5_stb_ced0 && (spc5_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_stb_ced_cntr0 <= 9'h000;
spc5_stb_ced0_d <= 1'b0;
end
else if( spc5_stb_ced0 && (spc5_stb_state_ack0 == 8'h00))
begin
spc5_stb_ced_cntr0 <= spc5_stb_ced_cntr0 + 1;
spc5_stb_ced0_d <= spc5_stb_ced0;
end
else
begin
spc5_stb_ced_cntr0 <= spc5_stb_ced_cntr0;
spc5_stb_ced0_d <= spc5_stb_ced0_d;
end
if( ( ~spc5_mbar_vld0 && (spc5_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_mbar_vld_cntr0 <= 9'h000;
spc5_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_mbar_vld_counter = %d", spc5_mbar_vld_cntr0);
end
else if( spc5_mbar_vld0)
begin
spc5_mbar_vld_cntr0 <= spc5_mbar_vld_cntr0 + 1;
spc5_mbar_vld_d0 <= spc5_mbar_vld0;
end
else
begin
spc5_mbar_vld_cntr0 <= spc5_mbar_vld_cntr0;
spc5_mbar_vld_d0 <= spc5_mbar_vld0;
end
if( ( ~spc5_flsh_vld0 && (spc5_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_flsh_vld_cntr0 <= 9'h000;
spc5_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_flsh_vld_counter = %d", spc5_flsh_vld_cntr0);
end
else if( spc5_flsh_vld0)
begin
spc5_flsh_vld_cntr0 <= spc5_flsh_vld_cntr0 + 1;
spc5_flsh_vld_d0 <= spc5_flsh_vld0;
end
else
begin
spc5_flsh_vld_cntr0 <= spc5_flsh_vld_cntr0;
spc5_flsh_vld_d0 <= spc5_flsh_vld0;
end
if( ( ~spc5_stb_ced1 && (spc5_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_stb_ced_cntr1 <= 9'h000;
spc5_stb_ced1_d <= 1'b0;
end
else if( spc5_stb_ced1 && (spc5_stb_state_ack1 == 8'h00))
begin
spc5_stb_ced_cntr1 <= spc5_stb_ced_cntr1 + 1;
spc5_stb_ced1_d <= spc5_stb_ced1;
end
else
begin
spc5_stb_ced_cntr1 <= spc5_stb_ced_cntr1;
spc5_stb_ced1_d <= spc5_stb_ced1_d;
end
if( ( ~spc5_mbar_vld1 && (spc5_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_mbar_vld_cntr1 <= 9'h000;
spc5_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_mbar_vld_counter = %d", spc5_mbar_vld_cntr1);
end
else if( spc5_mbar_vld1)
begin
spc5_mbar_vld_cntr1 <= spc5_mbar_vld_cntr1 + 1;
spc5_mbar_vld_d1 <= spc5_mbar_vld1;
end
else
begin
spc5_mbar_vld_cntr1 <= spc5_mbar_vld_cntr1;
spc5_mbar_vld_d1 <= spc5_mbar_vld1;
end
if( ( ~spc5_flsh_vld1 && (spc5_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_flsh_vld_cntr1 <= 9'h000;
spc5_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_flsh_vld_counter = %d", spc5_flsh_vld_cntr1);
end
else if( spc5_flsh_vld1)
begin
spc5_flsh_vld_cntr1 <= spc5_flsh_vld_cntr1 + 1;
spc5_flsh_vld_d1 <= spc5_flsh_vld1;
end
else
begin
spc5_flsh_vld_cntr1 <= spc5_flsh_vld_cntr1;
spc5_flsh_vld_d1 <= spc5_flsh_vld1;
end
if( ( ~spc5_stb_ced2 && (spc5_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_stb_ced_cntr2 <= 9'h000;
spc5_stb_ced2_d <= 1'b0;
end
else if( spc5_stb_ced2 && (spc5_stb_state_ack2 == 8'h00))
begin
spc5_stb_ced_cntr2 <= spc5_stb_ced_cntr2 + 1;
spc5_stb_ced2_d <= spc5_stb_ced2;
end
else
begin
spc5_stb_ced_cntr2 <= spc5_stb_ced_cntr2;
spc5_stb_ced2_d <= spc5_stb_ced2_d;
end
if( ( ~spc5_mbar_vld2 && (spc5_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_mbar_vld_cntr2 <= 9'h000;
spc5_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_mbar_vld_counter = %d", spc5_mbar_vld_cntr2);
end
else if( spc5_mbar_vld2)
begin
spc5_mbar_vld_cntr2 <= spc5_mbar_vld_cntr2 + 1;
spc5_mbar_vld_d2 <= spc5_mbar_vld2;
end
else
begin
spc5_mbar_vld_cntr2 <= spc5_mbar_vld_cntr2;
spc5_mbar_vld_d2 <= spc5_mbar_vld2;
end
if( ( ~spc5_flsh_vld2 && (spc5_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_flsh_vld_cntr2 <= 9'h000;
spc5_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_flsh_vld_counter = %d", spc5_flsh_vld_cntr2);
end
else if( spc5_flsh_vld2)
begin
spc5_flsh_vld_cntr2 <= spc5_flsh_vld_cntr2 + 1;
spc5_flsh_vld_d2 <= spc5_flsh_vld2;
end
else
begin
spc5_flsh_vld_cntr2 <= spc5_flsh_vld_cntr2;
spc5_flsh_vld_d2 <= spc5_flsh_vld2;
end
if( ( ~spc5_stb_ced3 && (spc5_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_stb_ced_cntr3 <= 9'h000;
spc5_stb_ced3_d <= 1'b0;
end
else if( spc5_stb_ced3 && (spc5_stb_state_ack3 == 8'h00))
begin
spc5_stb_ced_cntr3 <= spc5_stb_ced_cntr3 + 1;
spc5_stb_ced3_d <= spc5_stb_ced3;
end
else
begin
spc5_stb_ced_cntr3 <= spc5_stb_ced_cntr3;
spc5_stb_ced3_d <= spc5_stb_ced3_d;
end
if( ( ~spc5_mbar_vld3 && (spc5_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_mbar_vld_cntr3 <= 9'h000;
spc5_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_mbar_vld_counter = %d", spc5_mbar_vld_cntr3);
end
else if( spc5_mbar_vld3)
begin
spc5_mbar_vld_cntr3 <= spc5_mbar_vld_cntr3 + 1;
spc5_mbar_vld_d3 <= spc5_mbar_vld3;
end
else
begin
spc5_mbar_vld_cntr3 <= spc5_mbar_vld_cntr3;
spc5_mbar_vld_d3 <= spc5_mbar_vld3;
end
if( ( ~spc5_flsh_vld3 && (spc5_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_flsh_vld_cntr3 <= 9'h000;
spc5_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_flsh_vld_counter = %d", spc5_flsh_vld_cntr3);
end
else if( spc5_flsh_vld3)
begin
spc5_flsh_vld_cntr3 <= spc5_flsh_vld_cntr3 + 1;
spc5_flsh_vld_d3 <= spc5_flsh_vld3;
end
else
begin
spc5_flsh_vld_cntr3 <= spc5_flsh_vld_cntr3;
spc5_flsh_vld_d3 <= spc5_flsh_vld3;
end
end
always @(spc5_flsh_vld_d0 or spc5_flsh_vld0)
begin
if (spc5_flsh_vld_d0 && ~spc5_flsh_vld0)
spc5_flsh_vld_capture0 <= 1'b1;
else
spc5_flsh_vld_capture0 <= 1'b0;
end
always @(spc5_flsh_vld_d1 or spc5_flsh_vld1)
begin
if (spc5_flsh_vld_d1 && ~spc5_flsh_vld1)
spc5_flsh_vld_capture1 <= 1'b1;
else
spc5_flsh_vld_capture1 <= 1'b0;
end
always @(spc5_flsh_vld_d2 or spc5_flsh_vld2)
begin
if (spc5_flsh_vld_d2 && ~spc5_flsh_vld2)
spc5_flsh_vld_capture2 <= 1'b1;
else
spc5_flsh_vld_capture2 <= 1'b0;
end
always @(spc5_flsh_vld_d3 or spc5_flsh_vld3)
begin
if (spc5_flsh_vld_d3 && ~spc5_flsh_vld3)
spc5_flsh_vld_capture3 <= 1'b1;
else
spc5_flsh_vld_capture3 <= 1'b0;
end
always @(spc5_lmiss_pa0 or spc5_imiss_pa or spc5_imiss_vld_d or spc5_lmiss_vld0)
begin
if((spc5_lmiss_pa0 == spc5_imiss_pa) && spc5_imiss_vld_d && spc5_lmiss_vld0)
spc5_lmiss_eq0 = 1'b1;
else
spc5_lmiss_eq0 = 1'b0;
end
always @(spc5_lmiss_pa1 or spc5_imiss_pa or spc5_imiss_vld_d or spc5_lmiss_vld1)
begin
if((spc5_lmiss_pa1 == spc5_imiss_pa) && spc5_imiss_vld_d && spc5_lmiss_vld1)
spc5_lmiss_eq1 = 1'b1;
else
spc5_lmiss_eq1 = 1'b0;
end
always @(spc5_lmiss_pa2 or spc5_imiss_pa or spc5_imiss_vld_d or spc5_lmiss_vld2)
begin
if((spc5_lmiss_pa2 == spc5_imiss_pa) && spc5_imiss_vld_d && spc5_lmiss_vld2)
spc5_lmiss_eq2 = 1'b1;
else
spc5_lmiss_eq2 = 1'b0;
end
always @(spc5_lmiss_pa3 or spc5_imiss_pa or spc5_imiss_vld_d or spc5_lmiss_vld3)
begin
if((spc5_lmiss_pa3 == spc5_imiss_pa) && spc5_imiss_vld_d && spc5_lmiss_vld3)
spc5_lmiss_eq3 = 1'b1;
else
spc5_lmiss_eq3 = 1'b0;
end
always @(spc5_lmiss_pa0 or spc5_stb_atm_addr0 or spc5_atm_cntr0 or spc5_lmiss_vld0)
begin
if ( ((spc5_lmiss_pa0 == spc5_stb_atm_addr0) && (spc5_atm_cntr0 != 9'h000) && spc5_lmiss_vld0) ||
((spc5_lmiss_pa1 == spc5_stb_atm_addr0) && (spc5_atm_cntr0 != 9'h000) && spc5_lmiss_vld1) ||
((spc5_lmiss_pa2 == spc5_stb_atm_addr0) && (spc5_atm_cntr0 != 9'h000) && spc5_lmiss_vld2) ||
((spc5_lmiss_pa3 == spc5_stb_atm_addr0) && (spc5_atm_cntr0 != 9'h000) && spc5_lmiss_vld3) )
spc5_atm_lmiss_eq0 = 1'b1;
else
spc5_atm_lmiss_eq0 = 1'b0;
end
always @(spc5_lmiss_pa1 or spc5_stb_atm_addr1 or spc5_atm_cntr1 or spc5_lmiss_vld1)
begin
if ( ((spc5_lmiss_pa0 == spc5_stb_atm_addr1) && (spc5_atm_cntr1 != 9'h000) && spc5_lmiss_vld0) ||
((spc5_lmiss_pa1 == spc5_stb_atm_addr1) && (spc5_atm_cntr1 != 9'h000) && spc5_lmiss_vld1) ||
((spc5_lmiss_pa2 == spc5_stb_atm_addr1) && (spc5_atm_cntr1 != 9'h000) && spc5_lmiss_vld2) ||
((spc5_lmiss_pa3 == spc5_stb_atm_addr1) && (spc5_atm_cntr1 != 9'h000) && spc5_lmiss_vld3) )
spc5_atm_lmiss_eq1 = 1'b1;
else
spc5_atm_lmiss_eq1 = 1'b0;
end
always @(spc5_lmiss_pa2 or spc5_stb_atm_addr2 or spc5_atm_cntr2 or spc5_lmiss_vld2)
begin
if ( ((spc5_lmiss_pa0 == spc5_stb_atm_addr2) && (spc5_atm_cntr2 != 9'h000) && spc5_lmiss_vld0) ||
((spc5_lmiss_pa1 == spc5_stb_atm_addr2) && (spc5_atm_cntr2 != 9'h000) && spc5_lmiss_vld1) ||
((spc5_lmiss_pa2 == spc5_stb_atm_addr2) && (spc5_atm_cntr2 != 9'h000) && spc5_lmiss_vld2) ||
((spc5_lmiss_pa3 == spc5_stb_atm_addr2) && (spc5_atm_cntr2 != 9'h000) && spc5_lmiss_vld3) )
spc5_atm_lmiss_eq2 = 1'b1;
else
spc5_atm_lmiss_eq2 = 1'b0;
end
always @(spc5_lmiss_pa3 or spc5_stb_atm_addr3 or spc5_atm_cntr3 or spc5_lmiss_vld3)
begin
if ( ((spc5_lmiss_pa0 == spc5_stb_atm_addr3) && (spc5_atm_cntr3 != 9'h000) && spc5_lmiss_vld0) ||
((spc5_lmiss_pa1 == spc5_stb_atm_addr3) && (spc5_atm_cntr3 != 9'h000) && spc5_lmiss_vld1) ||
((spc5_lmiss_pa2 == spc5_stb_atm_addr3) && (spc5_atm_cntr3 != 9'h000) && spc5_lmiss_vld2) ||
((spc5_lmiss_pa3 == spc5_stb_atm_addr3) && (spc5_atm_cntr3 != 9'h000) && spc5_lmiss_vld3) )
spc5_atm_lmiss_eq3 = 1'b1;
else
spc5_atm_lmiss_eq3 = 1'b0;
end
always @(spc5_imiss_pa or spc5_stb_atm_addr0 or spc5_atm_cntr0 or spc5_imiss_vld_d)
begin
if((spc5_imiss_pa == spc5_stb_atm_addr0) && (spc5_atm_cntr0 != 9'h000) && spc5_imiss_vld_d)
spc5_atm_imiss_eq0 = 1'b1;
else
spc5_atm_imiss_eq0 = 1'b0;
end
always @(spc5_imiss_pa or spc5_stb_atm_addr1 or spc5_atm_cntr1 or spc5_imiss_vld_d)
begin
if((spc5_imiss_pa == spc5_stb_atm_addr1) && (spc5_atm_cntr1 != 9'h000) && spc5_imiss_vld_d)
spc5_atm_imiss_eq1 = 1'b1;
else
spc5_atm_imiss_eq1 = 1'b0;
end
always @(spc5_imiss_pa or spc5_stb_atm_addr2 or spc5_atm_cntr2 or spc5_imiss_vld_d)
begin
if((spc5_imiss_pa == spc5_stb_atm_addr2) && (spc5_atm_cntr2 != 9'h000) && spc5_imiss_vld_d)
spc5_atm_imiss_eq2 = 1'b1;
else
spc5_atm_imiss_eq2 = 1'b0;
end
always @(spc5_imiss_pa or spc5_stb_atm_addr3 or spc5_atm_cntr3 or spc5_imiss_vld_d)
begin
if((spc5_imiss_pa == spc5_stb_atm_addr3) && (spc5_atm_cntr3 != 9'h000) && spc5_imiss_vld_d)
spc5_atm_imiss_eq3 = 1'b1;
else
spc5_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc5_imiss_vld || ~rst_l)
spc5_imiss_vld_d <= 1'b0;
else
spc5_imiss_vld_d <= spc5_imiss_vld;
if( ~spc5_ld_miss || ~rst_l)
spc5_ld_miss_capture <= 1'b0;
else
spc5_ld_miss_capture <= spc5_ld_miss;
end
always @(spc5_stb_ced0 or spc5_stb_ced0_d)
begin
if (~spc5_stb_ced0 && spc5_stb_ced0_d)
spc5_stb_ced_capture0 <= 1'b1;
else
spc5_stb_ced_capture0 <= 1'b0;
end
always @(spc5_stb_ced1 or spc5_stb_ced1_d)
begin
if (~spc5_stb_ced1 && spc5_stb_ced1_d)
spc5_stb_ced_capture1 <= 1'b1;
else
spc5_stb_ced_capture1 <= 1'b0;
end
always @(spc5_stb_ced2 or spc5_stb_ced2_d)
begin
if (~spc5_stb_ced2 && spc5_stb_ced2_d)
spc5_stb_ced_capture2 <= 1'b1;
else
spc5_stb_ced_capture2 <= 1'b0;
end
always @(spc5_stb_ced3 or spc5_stb_ced3_d)
begin
if (~spc5_stb_ced3 && spc5_stb_ced3_d)
spc5_stb_ced_capture3 <= 1'b1;
else
spc5_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc5_stb_state_ack0 != 8'h00 && (spc5_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_ack_counter0 = %d", spc5_stb_ack_cntr0);
end
else if(spc5_stb_cam_hit && spc5_ld0_inst_vld_g && (spc5_stb_state_ack0 == 8'h00))
begin
spc5_stb_ack_cntr0 <= spc5_stb_ack_cntr0 + 1;
end
else if( (spc5_stb_state_ack0 == 8'h00 ) && (spc5_stb_ack_cntr0 != 9'h000))
begin
spc5_stb_ack_cntr0 <= spc5_stb_ack_cntr0 + 1;
end // if ( (spc5_stb_state_ack0 == 8'h00 ) && (spc5_stb_ack_cntr0 != 9'h000))
else
begin
spc5_stb_ack_cntr0 <= spc5_stb_ack_cntr0;
end
if( (spc5_stb_state_ack1 != 8'h00 && (spc5_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_ack_counter1 = %d", spc5_stb_ack_cntr1);
end
else if(spc5_stb_cam_hit && spc5_ld1_inst_vld_g && (spc5_stb_state_ack1 == 8'h00))
begin
spc5_stb_ack_cntr1 <= spc5_stb_ack_cntr1 + 1;
end
else if( (spc5_stb_state_ack1 == 8'h00 ) && (spc5_stb_ack_cntr1 != 9'h000))
begin
spc5_stb_ack_cntr1 <= spc5_stb_ack_cntr1 + 1;
end // if ( (spc5_stb_state_ack1 == 8'h00 ) && (spc5_stb_ack_cntr1 != 9'h000))
else
begin
spc5_stb_ack_cntr1 <= spc5_stb_ack_cntr1;
end
if( (spc5_stb_state_ack2 != 8'h00 && (spc5_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_ack_counter2 = %d", spc5_stb_ack_cntr2);
end
else if(spc5_stb_cam_hit && spc5_ld2_inst_vld_g && (spc5_stb_state_ack2 == 8'h00))
begin
spc5_stb_ack_cntr2 <= spc5_stb_ack_cntr2 + 1;
end
else if( (spc5_stb_state_ack2 == 8'h00 ) && (spc5_stb_ack_cntr2 != 9'h000))
begin
spc5_stb_ack_cntr2 <= spc5_stb_ack_cntr2 + 1;
end // if ( (spc5_stb_state_ack2 == 8'h00 ) && (spc5_stb_ack_cntr2 != 9'h000))
else
begin
spc5_stb_ack_cntr2 <= spc5_stb_ack_cntr2;
end
if( (spc5_stb_state_ack3 != 8'h00 && (spc5_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_ack_counter3 = %d", spc5_stb_ack_cntr3);
end
else if(spc5_stb_cam_hit && spc5_ld3_inst_vld_g && (spc5_stb_state_ack3 == 8'h00))
begin
spc5_stb_ack_cntr3 <= spc5_stb_ack_cntr3 + 1;
end
else if( (spc5_stb_state_ack3 == 8'h00 ) && (spc5_stb_ack_cntr3 != 9'h000))
begin
spc5_stb_ack_cntr3 <= spc5_stb_ack_cntr3 + 1;
end // if ( (spc5_stb_state_ack3 == 8'h00 ) && (spc5_stb_ack_cntr3 != 9'h000))
else
begin
spc5_stb_ack_cntr3 <= spc5_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc5_stb0_full_w2 or spc5_stb0_full)
begin
if (~spc5_stb0_full_w2 && spc5_stb0_full)
spc5_stb_full_capture0 <= 1'b1;
else
spc5_stb_full_capture0 <= 1'b0;
end
always @(spc5_stb1_full_w2 or spc5_stb1_full)
begin
if (~spc5_stb1_full_w2 && spc5_stb1_full)
spc5_stb_full_capture1 <= 1'b1;
else
spc5_stb_full_capture1 <= 1'b0;
end
always @(spc5_stb2_full_w2 or spc5_stb2_full)
begin
if (~spc5_stb2_full_w2 && spc5_stb2_full)
spc5_stb_full_capture2 <= 1'b1;
else
spc5_stb_full_capture2 <= 1'b0;
end
always @(spc5_stb3_full_w2 or spc5_stb3_full)
begin
if (~spc5_stb3_full_w2 && spc5_stb3_full)
spc5_stb_full_capture3 <= 1'b1;
else
spc5_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc5_stb0_full && (spc5_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_full_counter0 = %d", spc5_stb_full_cntr0);
end
else if( spc5_stb0_full)
begin
spc5_stb_full_cntr0 <= spc5_stb_full_cntr0 + 1;
end
else
begin
spc5_stb_full_cntr0 <= spc5_stb_full_cntr0;
end
if( ( ~spc5_stb1_full && (spc5_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_full_counter1 = %d", spc5_stb_full_cntr1);
end
else if( spc5_stb1_full)
begin
spc5_stb_full_cntr1 <= spc5_stb_full_cntr1 + 1;
end
else
begin
spc5_stb_full_cntr1 <= spc5_stb_full_cntr1;
end
if( ( ~spc5_stb2_full && (spc5_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_full_counter2 = %d", spc5_stb_full_cntr2);
end
else if( spc5_stb2_full)
begin
spc5_stb_full_cntr2 <= spc5_stb_full_cntr2 + 1;
end
else
begin
spc5_stb_full_cntr2 <= spc5_stb_full_cntr2;
end
if( ( ~spc5_stb3_full && (spc5_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc5_stb_full_counter3 = %d", spc5_stb_full_cntr3);
end
else if( spc5_stb3_full)
begin
spc5_stb_full_cntr3 <= spc5_stb_full_cntr3 + 1;
end
else
begin
spc5_stb_full_cntr3 <= spc5_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc5_lmq0_full_d or spc5_lmq0_full)
begin
if (spc5_lmq0_full_d && ~spc5_lmq0_full)
spc5_lmq_full_capture0 <= 1'b1;
else
spc5_lmq_full_capture0 <= 1'b0;
end
always @(spc5_lmq1_full_d or spc5_lmq1_full)
begin
if (spc5_lmq1_full_d && ~spc5_lmq1_full)
spc5_lmq_full_capture1 <= 1'b1;
else
spc5_lmq_full_capture1 <= 1'b0;
end
always @(spc5_lmq2_full_d or spc5_lmq2_full)
begin
if (spc5_lmq2_full_d && ~spc5_lmq2_full)
spc5_lmq_full_capture2 <= 1'b1;
else
spc5_lmq_full_capture2 <= 1'b0;
end
always @(spc5_lmq3_full_d or spc5_lmq3_full)
begin
if (spc5_lmq3_full_d && ~spc5_lmq3_full)
spc5_lmq_full_capture3 <= 1'b1;
else
spc5_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc5_lmq0_full && (spc5_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc5_lmq_full_cntr0 <= 9'h000;
spc5_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_lmq_full_counter0 = %d", spc5_lmq_full_cntr0);
end
else if( spc5_lmq0_full)
begin
spc5_lmq_full_cntr0 <= spc5_lmq_full_cntr0 + 1;
spc5_lmq0_full_d <= spc5_lmq0_full;
end
else
begin
spc5_lmq_full_cntr0 <= spc5_lmq_full_cntr0;
spc5_lmq0_full_d <= spc5_lmq0_full;
end
if( ( ~spc5_lmq1_full && (spc5_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc5_lmq_full_cntr1 <= 9'h000;
spc5_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_lmq_full_counter1 = %d", spc5_lmq_full_cntr1);
end
else if( spc5_lmq1_full)
begin
spc5_lmq_full_cntr1 <= spc5_lmq_full_cntr1 + 1;
spc5_lmq1_full_d <= spc5_lmq1_full;
end
else
begin
spc5_lmq_full_cntr1 <= spc5_lmq_full_cntr1;
spc5_lmq1_full_d <= spc5_lmq1_full;
end
if( ( ~spc5_lmq2_full && (spc5_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc5_lmq_full_cntr2 <= 9'h000;
spc5_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_lmq_full_counter2 = %d", spc5_lmq_full_cntr2);
end
else if( spc5_lmq2_full)
begin
spc5_lmq_full_cntr2 <= spc5_lmq_full_cntr2 + 1;
spc5_lmq2_full_d <= spc5_lmq2_full;
end
else
begin
spc5_lmq_full_cntr2 <= spc5_lmq_full_cntr2;
spc5_lmq2_full_d <= spc5_lmq2_full;
end
if( ( ~spc5_lmq3_full && (spc5_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc5_lmq_full_cntr3 <= 9'h000;
spc5_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_lmq_full_counter3 = %d", spc5_lmq_full_cntr3);
end
else if( spc5_lmq3_full)
begin
spc5_lmq_full_cntr3 <= spc5_lmq_full_cntr3 + 1;
spc5_lmq3_full_d <= spc5_lmq3_full;
end
else
begin
spc5_lmq_full_cntr3 <= spc5_lmq_full_cntr3;
spc5_lmq3_full_d <= spc5_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc5_dfq_full_d or spc5_dfq_full)
begin
if (spc5_dfq_full_d && ~spc5_dfq_full)
spc5_dfq_full_capture <= 1'b1;
else
spc5_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc5_dfq_full && (spc5_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc5_dfq_full_cntr <= 9'h000;
spc5_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dfq_full_counter = %d", spc5_dfq_full_cntr);
end
else if( spc5_dfq_full)
begin
spc5_dfq_full_cntr <= spc5_dfq_full_cntr + 1;
spc5_dfq_full_d <= spc5_dfq_full;
end
else
begin
spc5_dfq_full_cntr <= spc5_dfq_full_cntr;
spc5_dfq_full_d <= spc5_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc5_dva_full_d or spc5_dva_inv)
begin
if (spc5_dva_full_d && ~spc5_dva_inv)
spc5_dva_full_capture <= 1'b1;
else
spc5_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc5_dva_din && spc5_dva_wen)
begin
spc5_dva_inv <= 1'b1;
spc5_dva_waddr_d <= spc5_dva_waddr;
end
else if(~spc5_dva_din && spc5_dva_wen)
begin
spc5_dva_inv <= 1'b0;
spc5_dva_waddr_d <= 5'b00000;
end
else
begin
spc5_dva_inv <= spc5_dva_inv;
spc5_dva_waddr_d <= spc5_dva_waddr_d;
end
end
always @(spc5_dva_raddr or spc5_dva_ren or spc5_dva_inv)
begin
if (spc5_dva_inv && spc5_dva_ren && (spc5_dva_raddr[6:2] == spc5_dva_waddr_d))
spc5_dva_vld2lkup <= 1'b1;
else
spc5_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc5_dva_inv && (spc5_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc5_dva_full_cntr <= 9'h000;
spc5_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dva_full_counter = %d", spc5_dva_full_cntr);
end
else if( spc5_dva_inv)
begin
spc5_dva_full_cntr <= spc5_dva_full_cntr + 1;
spc5_dva_full_d <= spc5_dva_inv;
end
else
begin
spc5_dva_full_cntr <= spc5_dva_full_cntr;
spc5_dva_full_d <= spc5_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc5_dva_vfull_d or spc5_dva_vld)
begin
if (spc5_dva_vfull_d && ~spc5_dva_vld)
spc5_dva_vfull_capture <= 1'b1;
else
spc5_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc5_dva_din && spc5_dva_wen)
begin
spc5_dva_vld <= 1'b1;
spc5_dva_invwaddr_d <= spc5_dva_waddr;
spc5_dva_invld_err <= spc5_dva_inv_perror;
end
else if(spc5_dva_din && spc5_dva_wen)
begin
spc5_dva_vld <= 1'b0;
spc5_dva_invwaddr_d <= 5'b00000;
spc5_dva_invld_err <= 1'b0;
end
else
begin
spc5_dva_vld <= spc5_dva_vld;
spc5_dva_invwaddr_d <= spc5_dva_invwaddr_d;
spc5_dva_invld_err <= spc5_dva_invld_err;
end
end
always @(spc5_dva_raddr or spc5_dva_ren or spc5_dva_vld)
begin
if (spc5_dva_vld && spc5_dva_ren && (spc5_dva_raddr[6:2] == spc5_dva_waddr_d))
spc5_dva_invld2lkup <= 1'b1;
else
spc5_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc5_dva_vld && (spc5_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc5_dva_vfull_cntr <= 9'h000;
spc5_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc5_dva_vfull_counter = %d", spc5_dva_vfull_cntr);
end
else if( spc5_dva_vld)
begin
spc5_dva_vfull_cntr <= spc5_dva_vfull_cntr + 1;
spc5_dva_vfull_d <= spc5_dva_vld;
end
else
begin
spc5_dva_vfull_cntr <= spc5_dva_vfull_cntr;
spc5_dva_vfull_d <= spc5_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc5_dva_raddr or spc5_dva_waddr or spc5_dva_ren or spc5_dva_wen)
begin
if ( spc5_dva_ren && spc5_dva_wen && (spc5_dva_raddr[6:2] == spc5_dva_waddr))
spc5_dva_collide <= 1'b1;
else
spc5_dva_collide <= 1'b0;
end
// dva error cases
always @(spc5_dva_raddr or spc5_dva_ren or spc5_dva_dtag_perror or spc5_dva_dtag_perror)
begin
if (spc5_dva_ren && (spc5_dva_dtag_perror || spc5_dva_dtag_perror))
spc5_dva_err <= 1'b1;
else
spc5_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc5_dva_err)
spc5_dva_efull_d <= 1'b1;
else
spc5_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc5_dva_ren && ~(spc5_dva_dtag_perror || spc5_dva_dtag_perror ) &&
(spc5_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc5_dva_efull_cntr <= 9'h000;
spc5_dva_raddr_d <= spc5_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc5_dva_efull_counter = %d", spc5_dva_efull_cntr);
end
else if(spc5_dva_efull_d)
begin
spc5_dva_efull_cntr <= spc5_dva_efull_cntr + 1;
spc5_dva_raddr_d <= spc5_dva_raddr_d;
end
else
begin
spc5_dva_efull_cntr <= spc5_dva_efull_cntr;
spc5_dva_raddr_d <= spc5_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC6
wire spc6_dva_ren = `TOP_DESIGN.sparc6.lsu.ifu_lsu_ld_inst_e;
wire spc6_dva_wen = `TOP_DESIGN.sparc6.lsu.lsu_dtagv_wr_vld_e;
wire spc6_dva_din = `TOP_DESIGN.sparc6.lsu.dva_din_e;
wire [3:0] spc6_dva_dout = `TOP_DESIGN.sparc6.lsu.dva_vld_m[3:0];
wire [6:0] spc6_dva_raddr = `TOP_DESIGN.sparc6.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc6_dva_waddr = `TOP_DESIGN.sparc6.lsu.dva_wr_adr_e[10:6];
wire spc6_dva_dtag_perror = `TOP_DESIGN.sparc6.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc6_dva_dcache_perror = `TOP_DESIGN.sparc6.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc6_dva_inv_perror = `TOP_DESIGN.sparc6.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc6_ld_miss = `TOP_DESIGN.sparc6.lsu.dctl.lsu_ld_miss_wb;
reg spc6_ld_miss_capture;
wire spc6_atomic_g = `TOP_DESIGN.sparc6.lsu.qctl1.atomic_g;
wire [1:0] spc6_atm_type0 = `TOP_DESIGN.sparc6.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc6_atm_type1 = `TOP_DESIGN.sparc6.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc6_atm_type2 = `TOP_DESIGN.sparc6.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc6_atm_type3 = `TOP_DESIGN.sparc6.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc6_dctl_lsu_way_hit = `TOP_DESIGN.sparc6.lsu.dctl.lsu_way_hit;
wire spc6_dctl_dcache_enable_g = `TOP_DESIGN.sparc6.lsu.dctl.dcache_enable_g;
wire spc6_dctl_ldxa_internal = `TOP_DESIGN.sparc6.lsu.dctl.ldxa_internal;
wire spc6_dctl_ldst_dbl_g = `TOP_DESIGN.sparc6.lsu.dctl.ldst_dbl_g;
wire spc6_dctl_atomic_g = `TOP_DESIGN.sparc6.lsu.dctl.atomic_g;
wire spc6_dctl_stb_cam_hit = `TOP_DESIGN.sparc6.lsu.dctl.stb_cam_hit;
wire spc6_dctl_endian_mispred_g = `TOP_DESIGN.sparc6.lsu.dctl.endian_mispred_g;
wire spc6_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc6.lsu.dctl.dcache_rd_parity_error;
wire spc6_dctl_dtag_perror_g = `TOP_DESIGN.sparc6.lsu.dctl.dtag_perror_g;
wire spc6_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc6.lsu.dctl.tte_data_perror_unc;
wire spc6_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc6.lsu.dctl.ld_inst_vld_g;
wire spc6_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc6.lsu.dctl.lsu_alt_space_g;
wire spc6_dctl_recognized_asi_g = `TOP_DESIGN.sparc6.lsu.dctl.recognized_asi_g;
wire spc6_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc6.lsu.dctl.ncache_asild_rq_g ;
wire spc6_dctl_bld_hit;
wire spc6_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc6_ixinv0 = `TOP_DESIGN.sparc6.lsu.qctl2.imiss0_inv_en;
wire spc6_ixinv1 = `TOP_DESIGN.sparc6.lsu.qctl2.imiss1_inv_en;
wire spc6_ixinv2 = `TOP_DESIGN.sparc6.lsu.qctl2.imiss2_inv_en;
wire spc6_ixinv3 = `TOP_DESIGN.sparc6.lsu.qctl2.imiss3_inv_en;
wire spc6_ifill = `TOP_DESIGN.sparc6.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc6_inv = `TOP_DESIGN.sparc6.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc6_inv_clr = `TOP_DESIGN.sparc6.lsu.qctl2.ifu_lsu_inv_clear;
wire spc6_ibuf_busy = `TOP_DESIGN.sparc6.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc6_l2 = `TOP_DESIGN.sparc6.lsu.dctl.l2fill_vld_g ;
wire spc6_unc = `TOP_DESIGN.sparc6.lsu.dctl.unc_err_trap_g ;
wire spc6_fpld = `TOP_DESIGN.sparc6.lsu.dctl.l2fill_fpld_g ;
wire spc6_fpldst = `TOP_DESIGN.sparc6.lsu.dctl.fp_ldst_g ;
wire spc6_unflush = `TOP_DESIGN.sparc6.lsu.dctl.ld_inst_vld_unflushed ;
wire spc6_ldw = `TOP_DESIGN.sparc6.lsu.dctl.lsu_inst_vld_w ;
wire spc6_byp = `TOP_DESIGN.sparc6.lsu.dctl.intld_byp_data_vld_m ;
wire spc6_flsh = `TOP_DESIGN.sparc6.lsu.lsu_exu_flush_pipe_w ;
wire spc6_chm = `TOP_DESIGN.sparc6.lsu.dctl.common_ldst_miss_w ;
wire spc6_ldxa = `TOP_DESIGN.sparc6.lsu.dctl.ldxa_internal ;
wire spc6_ato = `TOP_DESIGN.sparc6.lsu.dctl.atomic_g ;
wire spc6_pref = `TOP_DESIGN.sparc6.lsu.dctl.pref_inst_g ;
wire spc6_chit = `TOP_DESIGN.sparc6.lsu.dctl.stb_cam_hit ;
wire spc6_dcp = `TOP_DESIGN.sparc6.lsu.dctl.dcache_rd_parity_error ;
wire spc6_dtp = `TOP_DESIGN.sparc6.lsu.dctl.dtag_perror_g ;
//wire spc6_mpc = `TOP_DESIGN.sparc6.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc6_mpc = 1'b0;
wire spc6_mpu = `TOP_DESIGN.sparc6.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc6_exu_und;
reg [4:0] spc6_exu;
// excptn
wire spc6_exp_wtchpt_trp_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc6_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc6_exp_priv_violtn_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc6_exp_daccess_excptn_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc6_exp_daccess_prot_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc6_exp_priv_action_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc6_exp_spec_access_epage_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc6_exp_uncache_atomic_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc6_exp_illegal_asi_action_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc6_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc6_exp_asi_rd_unc = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc6_exp_tlb_data_ce = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc6_exp_asi_rd_unc = 1'b0;
wire spc6_exp_tlb_data_ce = 1'b0;
wire spc6_exp_tlb_data_ue = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc6_exp_tlb_tag_ue = `TOP_DESIGN.sparc6.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc6_exp_unc = `TOP_DESIGN.sparc6.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc6_exp_corr = `TOP_DESIGN.sparc6.lsu.excpctl.tte_data_perror_corr;
wire spc6_exp_corr = 1'b0;
wire [15:0] spc6_exp_und;
reg [4:0] spc6_exp;
// dctl cmplt
wire spc6_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc6.lsu.dctl.stxa_internal_d2;
wire spc6_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc6.lsu.dctl.lsu_l2fill_vld;
wire spc6_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc6.lsu.dctl.atomic_ld_squash_e;
wire spc6_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc6.lsu.qctl2.lsu_ignore_fill;
wire spc6_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc6.lsu.dctl.l2fill_fpld_e;
// wire spc6_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc6.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc6_dctl_fill_err_trap_e = `TOP_DESIGN.sparc6.lsu.dctl.fill_err_trap_e;
wire spc6_dctl_l2_corr_error_e = `TOP_DESIGN.sparc6.lsu.dctl.l2_corr_error_e;
wire [3:0] spc6_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc6.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc6_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc6.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc6_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc6.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc6_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc6.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc6_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc6.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc6_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc6.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc6_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc6_ldstcond_cmplt_d;
wire spc6_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc6.lsu.qctl1.ld_sec_hit_thrd0;
wire spc6_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_inst_vld_g;
wire spc6_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc6_ld0_pkt_vld_unmasked_d;
reg spc6_qctl1_ld_sec_hit_thrd0_w2;
wire spc6_dctl_thread0_w3 = `TOP_DESIGN.sparc6.lsu.dctl.thread0_w3;
wire spc6_dctl_dfill_thread0 = `TOP_DESIGN.sparc6.lsu.dctl.dfill_thread0;
wire spc6_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc6.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc6_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc6.lsu.dctl.diag_wr_cmplt0;
wire spc6_dctl_bsync0_reset = `TOP_DESIGN.sparc6.lsu.dctl.bsync0_reset;
wire spc6_dctl_late_cmplt0 = `TOP_DESIGN.sparc6.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc6_dctl_stxa_cmplt0;
wire spc6_dctl_l2fill_cmplt0;
wire spc6_dctl_atm_cmplt0;
wire spc6_dctl_fillerr0;
wire [4:0] spc6_cmplt0;
wire [5:0] spc6_dctl_ldst_cond_cmplt0;
reg [3:0] spc6_ldstcond_cmplt0;
reg [3:0] spc6_ldstcond_cmplt0_d;
wire spc6_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc6.lsu.qctl1.ld_sec_hit_thrd1;
wire spc6_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_inst_vld_g;
wire spc6_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc6_ld1_pkt_vld_unmasked_d;
reg spc6_qctl1_ld_sec_hit_thrd1_w2;
wire spc6_dctl_thread1_w3 = `TOP_DESIGN.sparc6.lsu.dctl.thread1_w3;
wire spc6_dctl_dfill_thread1 = `TOP_DESIGN.sparc6.lsu.dctl.dfill_thread1;
wire spc6_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc6.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc6_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc6.lsu.dctl.diag_wr_cmplt1;
wire spc6_dctl_bsync1_reset = `TOP_DESIGN.sparc6.lsu.dctl.bsync1_reset;
wire spc6_dctl_late_cmplt1 = `TOP_DESIGN.sparc6.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc6_dctl_stxa_cmplt1;
wire spc6_dctl_l2fill_cmplt1;
wire spc6_dctl_atm_cmplt1;
wire spc6_dctl_fillerr1;
wire [4:0] spc6_cmplt1;
wire [5:0] spc6_dctl_ldst_cond_cmplt1;
reg [3:0] spc6_ldstcond_cmplt1;
reg [3:0] spc6_ldstcond_cmplt1_d;
wire spc6_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc6.lsu.qctl1.ld_sec_hit_thrd2;
wire spc6_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_inst_vld_g;
wire spc6_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc6_ld2_pkt_vld_unmasked_d;
reg spc6_qctl1_ld_sec_hit_thrd2_w2;
wire spc6_dctl_thread2_w3 = `TOP_DESIGN.sparc6.lsu.dctl.thread2_w3;
wire spc6_dctl_dfill_thread2 = `TOP_DESIGN.sparc6.lsu.dctl.dfill_thread2;
wire spc6_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc6.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc6_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc6.lsu.dctl.diag_wr_cmplt2;
wire spc6_dctl_bsync2_reset = `TOP_DESIGN.sparc6.lsu.dctl.bsync2_reset;
wire spc6_dctl_late_cmplt2 = `TOP_DESIGN.sparc6.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc6_dctl_stxa_cmplt2;
wire spc6_dctl_l2fill_cmplt2;
wire spc6_dctl_atm_cmplt2;
wire spc6_dctl_fillerr2;
wire [4:0] spc6_cmplt2;
wire [5:0] spc6_dctl_ldst_cond_cmplt2;
reg [3:0] spc6_ldstcond_cmplt2;
reg [3:0] spc6_ldstcond_cmplt2_d;
wire spc6_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc6.lsu.qctl1.ld_sec_hit_thrd3;
wire spc6_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_inst_vld_g;
wire spc6_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc6_ld3_pkt_vld_unmasked_d;
reg spc6_qctl1_ld_sec_hit_thrd3_w2;
wire spc6_dctl_thread3_w3 = `TOP_DESIGN.sparc6.lsu.dctl.thread3_w3;
wire spc6_dctl_dfill_thread3 = `TOP_DESIGN.sparc6.lsu.dctl.dfill_thread3;
wire spc6_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc6.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc6_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc6.lsu.dctl.diag_wr_cmplt3;
wire spc6_dctl_bsync3_reset = `TOP_DESIGN.sparc6.lsu.dctl.bsync3_reset;
wire spc6_dctl_late_cmplt3 = `TOP_DESIGN.sparc6.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc6_dctl_stxa_cmplt3;
wire spc6_dctl_l2fill_cmplt3;
wire spc6_dctl_atm_cmplt3;
wire spc6_dctl_fillerr3;
wire [4:0] spc6_cmplt3;
wire [5:0] spc6_dctl_ldst_cond_cmplt3;
reg [3:0] spc6_ldstcond_cmplt3;
reg [3:0] spc6_ldstcond_cmplt3_d;
wire spc6_qctl1_bld_g = `TOP_DESIGN.sparc6.lsu.qctl1.bld_g;
wire spc6_qctl1_bld_reset = `TOP_DESIGN.sparc6.lsu.qctl1.bld_reset;
wire [1:0] spc6_qctl1_bld_cnt = `TOP_DESIGN.sparc6.lsu.qctl1.bld_cnt;
reg [9:0] spc6_bld0_full_cntr;
reg [1:0] spc6_bld0_full_d;
reg spc6_bld0_full_capture;
reg [9:0] spc6_bld1_full_cntr;
reg [1:0] spc6_bld1_full_d;
reg spc6_bld1_full_capture;
reg [9:0] spc6_bld2_full_cntr;
reg [1:0] spc6_bld2_full_d;
reg spc6_bld2_full_capture;
reg [9:0] spc6_bld3_full_cntr;
reg [1:0] spc6_bld3_full_d;
reg spc6_bld3_full_capture;
wire spc6_ipick = `TOP_DESIGN.sparc6.lsu.qctl1.imiss_pcx_rq_vld;
wire spc6_lpick = `TOP_DESIGN.sparc6.lsu.qctl1.ld_pcx_rq_all;
wire spc6_spick = `TOP_DESIGN.sparc6.lsu.qctl1.st_pcx_rq_all;
wire spc6_mpick = `TOP_DESIGN.sparc6.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc6_apick = `TOP_DESIGN.sparc6.lsu.qctl1.all_pcx_rq_pick;
wire spc6_msquash = `TOP_DESIGN.sparc6.lsu.qctl1.mcycle_squash_d1;
reg spc6_fpicko;
wire [3:0] spc6_fpick;
wire [39:0] spc6_imiss_pa = `TOP_DESIGN.sparc6.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc6_imiss_vld = `TOP_DESIGN.sparc6.lsu.qctl1.imiss_pcx_rq_vld;
reg spc6_imiss_vld_d;
wire [39:0] spc6_lmiss_pa0 = `TOP_DESIGN.sparc6.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc6_lmiss_vld0 = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_pcx_rq_vld;
wire spc6_ld_pkt_vld0 = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_pkt_vld;
wire spc6_st_pkt_vld0 = `TOP_DESIGN.sparc6.lsu.qctl1.st0_pkt_vld;
reg spc6_lmiss_eq0;
reg spc6_atm_imiss_eq0;
wire [39:0] spc6_lmiss_pa1 = `TOP_DESIGN.sparc6.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc6_lmiss_vld1 = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_pcx_rq_vld;
wire spc6_ld_pkt_vld1 = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_pkt_vld;
wire spc6_st_pkt_vld1 = `TOP_DESIGN.sparc6.lsu.qctl1.st1_pkt_vld;
reg spc6_lmiss_eq1;
reg spc6_atm_imiss_eq1;
wire [39:0] spc6_lmiss_pa2 = `TOP_DESIGN.sparc6.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc6_lmiss_vld2 = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_pcx_rq_vld;
wire spc6_ld_pkt_vld2 = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_pkt_vld;
wire spc6_st_pkt_vld2 = `TOP_DESIGN.sparc6.lsu.qctl1.st2_pkt_vld;
reg spc6_lmiss_eq2;
reg spc6_atm_imiss_eq2;
wire [39:0] spc6_lmiss_pa3 = `TOP_DESIGN.sparc6.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc6_lmiss_vld3 = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_pcx_rq_vld;
wire spc6_ld_pkt_vld3 = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_pkt_vld;
wire spc6_st_pkt_vld3 = `TOP_DESIGN.sparc6.lsu.qctl1.st3_pkt_vld;
reg spc6_lmiss_eq3;
reg spc6_atm_imiss_eq3;
wire [44:0] spc6_wdata_ramc = `TOP_DESIGN.sparc6.lsu.stb_cam.wdata_ramc;
wire spc6_wptr_vld = `TOP_DESIGN.sparc6.lsu.stb_cam.wptr_vld;
wire [75:0] spc6_wdata_ramd = {`TOP_DESIGN.sparc6.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc6.lsu.lsu_stb_st_data_g[63:0]};
wire spc6_stb_cam_hit = `TOP_DESIGN.sparc6.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc6_stb_cam_hit_ptr = `TOP_DESIGN.sparc6.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc6_stb_ld_full_raw = `TOP_DESIGN.sparc6.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc6_stb_ld_partial_raw = `TOP_DESIGN.sparc6.lsu.stb_ld_partial_raw[7:0];
wire spc6_stb_cam_mhit = `TOP_DESIGN.sparc6.lsu.stb_cam_mhit;
wire [3:0] spc6_dfq_vld_entries = `TOP_DESIGN.sparc6.lsu.qctl2.dfq_vld_entries;
wire spc6_dfq_full;
reg [9:0] spc6_dfq_full_cntr;
reg spc6_dfq_full_d;
reg spc6_dfq_full_capture;
reg [9:0] spc6_dfq_full_cntr1;
reg spc6_dfq_full_d1;
wire spc6_dfq_full1;
reg spc6_dfq_full_capture1;
reg [9:0] spc6_dfq_full_cntr2;
reg spc6_dfq_full_d2;
wire spc6_dfq_full2;
reg spc6_dfq_full_capture2;
reg [9:0] spc6_dfq_full_cntr3;
reg spc6_dfq_full_d3;
wire spc6_dfq_full3;
reg spc6_dfq_full_capture3;
reg [9:0] spc6_dfq_full_cntr4;
reg spc6_dfq_full_d4;
wire spc6_dfq_full4;
reg spc6_dfq_full_capture4;
reg [9:0] spc6_dfq_full_cntr5;
reg spc6_dfq_full_d5;
wire spc6_dfq_full5;
reg spc6_dfq_full_capture5;
reg [9:0] spc6_dfq_full_cntr6;
reg spc6_dfq_full_d6;
wire spc6_dfq_full6;
reg spc6_dfq_full_capture6;
reg [9:0] spc6_dfq_full_cntr7;
reg spc6_dfq_full_d7;
wire spc6_dfq_full7;
reg spc6_dfq_full_capture7;
wire spc6_dva_rdwrhit;
reg [9:0] spc6_dva_full_cntr;
reg spc6_dva_full_d;
reg spc6_dva_full_capture;
reg spc6_dva_inv;
reg spc6_dva_inv_d;
reg spc6_dva_vld;
reg spc6_dva_vld_d;
reg [9:0] spc6_dva_vfull_cntr;
reg spc6_dva_vfull_d;
reg spc6_dva_vfull_capture;
reg spc6_dva_collide;
reg spc6_dva_vld2lkup;
reg spc6_dva_invld2lkup;
reg spc6_dva_invld_err;
reg [9:0] spc6_dva_efull_cntr;
reg spc6_dva_efull_d;
reg spc6_dva_vlddtag_err;
reg spc6_dva_vlddcache_err;
reg spc6_dva_err;
reg [6:0] spc6_dva_raddr_d;
reg [4:0] spc6_dva_waddr_d;
reg [4:0] spc6_dva_invwaddr_d;
reg spc6_ld0_lt_1;
reg spc6_ld0_lt_2;
reg spc6_ld0_lt_3;
reg spc6_ld1_lt_0;
reg spc6_ld1_lt_2;
reg spc6_ld1_lt_3;
reg spc6_ld2_lt_0;
reg spc6_ld2_lt_1;
reg spc6_ld2_lt_3;
reg spc6_ld3_lt_0;
reg spc6_ld3_lt_1;
reg spc6_ld3_lt_2;
reg spc6_st0_lt_1;
reg spc6_st0_lt_2;
reg spc6_st0_lt_3;
reg spc6_st1_lt_0;
reg spc6_st1_lt_2;
reg spc6_st1_lt_3;
reg spc6_st2_lt_0;
reg spc6_st2_lt_1;
reg spc6_st2_lt_3;
reg spc6_st3_lt_0;
reg spc6_st3_lt_1;
reg spc6_st3_lt_2;
wire [11:0] spc6_ld_ooo_ret;
wire [11:0] spc6_st_ooo_ret;
wire [7:0] spc6_stb_state_vld0 = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc6_stb_state_ack0 = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc6_stb_state_ced0 = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc6_stb_state_rst0 = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_state_rst;
wire spc6_stb_ack_vld0 = `TOP_DESIGN.sparc6.lsu.stb_ctl0.ack_vld;
wire spc6_ld0_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_inst_vld_g;
wire spc6_intrpt0_cmplt = `TOP_DESIGN.sparc6.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc6_stb0_full = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_full;
wire spc6_stb0_full_w2 = `TOP_DESIGN.sparc6.lsu.stb_ctl0.stb_full_w2;
wire spc6_lmq0_full = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_pcx_rq_vld;
wire spc6_mbar_vld0 = `TOP_DESIGN.sparc6.lsu.dctl.mbar_vld0;
wire spc6_ld0_unfilled = `TOP_DESIGN.sparc6.lsu.qctl1.ld0_unfilled;
wire spc6_flsh_vld0 = `TOP_DESIGN.sparc6.lsu.dctl.flsh_vld0;
reg [9:0] spc6_ld0_unf_cntr;
reg spc6_ld0_unfilled_d;
reg [9:0] spc6_st0_unf_cntr;
reg spc6_st0_unfilled_d;
reg spc6_st0_unfilled;
reg spc6_mbar_vld_d0;
reg spc6_flsh_vld_d0;
reg spc6_lmq0_full_d;
reg [9:0] spc6_lmq_full_cntr0;
reg spc6_lmq_full_capture0;
reg [9:0] spc6_stb_full_cntr0;
reg spc6_stb_full_capture0;
reg [9:0] spc6_mbar_vld_cntr0;
reg spc6_mbar_vld_capture0;
reg [9:0] spc6_flsh_vld_cntr0;
reg spc6_flsh_vld_capture0;
reg spc6_stb_head_hit0;
wire spc6_raw_ack_capture0;
reg [9:0] spc6_stb_ack_cntr0;
reg [9:0] spc6_stb_ced_cntr0;
reg spc6_stb_ced0_d;
reg spc6_stb_ced_capture0;
wire spc6_stb_ced0;
reg spc6_atm0_d;
reg [9:0] spc6_atm_cntr0;
reg spc6_atm_intrpt_capture0;
reg spc6_atm_intrpt_b4capture0;
reg spc6_atm_inv_capture0;
reg [39:0] spc6_stb_wr_addr0;
reg [39:0] spc6_stb_atm_addr0;
reg spc6_atm_lmiss_eq0;
wire [7:0] spc6_stb_state_vld1 = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc6_stb_state_ack1 = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc6_stb_state_ced1 = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc6_stb_state_rst1 = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_state_rst;
wire spc6_stb_ack_vld1 = `TOP_DESIGN.sparc6.lsu.stb_ctl1.ack_vld;
wire spc6_ld1_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_inst_vld_g;
wire spc6_intrpt1_cmplt = `TOP_DESIGN.sparc6.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc6_stb1_full = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_full;
wire spc6_stb1_full_w2 = `TOP_DESIGN.sparc6.lsu.stb_ctl1.stb_full_w2;
wire spc6_lmq1_full = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_pcx_rq_vld;
wire spc6_mbar_vld1 = `TOP_DESIGN.sparc6.lsu.dctl.mbar_vld1;
wire spc6_ld1_unfilled = `TOP_DESIGN.sparc6.lsu.qctl1.ld1_unfilled;
wire spc6_flsh_vld1 = `TOP_DESIGN.sparc6.lsu.dctl.flsh_vld1;
reg [9:0] spc6_ld1_unf_cntr;
reg spc6_ld1_unfilled_d;
reg [9:0] spc6_st1_unf_cntr;
reg spc6_st1_unfilled_d;
reg spc6_st1_unfilled;
reg spc6_mbar_vld_d1;
reg spc6_flsh_vld_d1;
reg spc6_lmq1_full_d;
reg [9:0] spc6_lmq_full_cntr1;
reg spc6_lmq_full_capture1;
reg [9:0] spc6_stb_full_cntr1;
reg spc6_stb_full_capture1;
reg [9:0] spc6_mbar_vld_cntr1;
reg spc6_mbar_vld_capture1;
reg [9:0] spc6_flsh_vld_cntr1;
reg spc6_flsh_vld_capture1;
reg spc6_stb_head_hit1;
wire spc6_raw_ack_capture1;
reg [9:0] spc6_stb_ack_cntr1;
reg [9:0] spc6_stb_ced_cntr1;
reg spc6_stb_ced1_d;
reg spc6_stb_ced_capture1;
wire spc6_stb_ced1;
reg spc6_atm1_d;
reg [9:0] spc6_atm_cntr1;
reg spc6_atm_intrpt_capture1;
reg spc6_atm_intrpt_b4capture1;
reg spc6_atm_inv_capture1;
reg [39:0] spc6_stb_wr_addr1;
reg [39:0] spc6_stb_atm_addr1;
reg spc6_atm_lmiss_eq1;
wire [7:0] spc6_stb_state_vld2 = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc6_stb_state_ack2 = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc6_stb_state_ced2 = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc6_stb_state_rst2 = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_state_rst;
wire spc6_stb_ack_vld2 = `TOP_DESIGN.sparc6.lsu.stb_ctl2.ack_vld;
wire spc6_ld2_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_inst_vld_g;
wire spc6_intrpt2_cmplt = `TOP_DESIGN.sparc6.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc6_stb2_full = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_full;
wire spc6_stb2_full_w2 = `TOP_DESIGN.sparc6.lsu.stb_ctl2.stb_full_w2;
wire spc6_lmq2_full = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_pcx_rq_vld;
wire spc6_mbar_vld2 = `TOP_DESIGN.sparc6.lsu.dctl.mbar_vld2;
wire spc6_ld2_unfilled = `TOP_DESIGN.sparc6.lsu.qctl1.ld2_unfilled;
wire spc6_flsh_vld2 = `TOP_DESIGN.sparc6.lsu.dctl.flsh_vld2;
reg [9:0] spc6_ld2_unf_cntr;
reg spc6_ld2_unfilled_d;
reg [9:0] spc6_st2_unf_cntr;
reg spc6_st2_unfilled_d;
reg spc6_st2_unfilled;
reg spc6_mbar_vld_d2;
reg spc6_flsh_vld_d2;
reg spc6_lmq2_full_d;
reg [9:0] spc6_lmq_full_cntr2;
reg spc6_lmq_full_capture2;
reg [9:0] spc6_stb_full_cntr2;
reg spc6_stb_full_capture2;
reg [9:0] spc6_mbar_vld_cntr2;
reg spc6_mbar_vld_capture2;
reg [9:0] spc6_flsh_vld_cntr2;
reg spc6_flsh_vld_capture2;
reg spc6_stb_head_hit2;
wire spc6_raw_ack_capture2;
reg [9:0] spc6_stb_ack_cntr2;
reg [9:0] spc6_stb_ced_cntr2;
reg spc6_stb_ced2_d;
reg spc6_stb_ced_capture2;
wire spc6_stb_ced2;
reg spc6_atm2_d;
reg [9:0] spc6_atm_cntr2;
reg spc6_atm_intrpt_capture2;
reg spc6_atm_intrpt_b4capture2;
reg spc6_atm_inv_capture2;
reg [39:0] spc6_stb_wr_addr2;
reg [39:0] spc6_stb_atm_addr2;
reg spc6_atm_lmiss_eq2;
wire [7:0] spc6_stb_state_vld3 = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc6_stb_state_ack3 = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc6_stb_state_ced3 = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc6_stb_state_rst3 = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_state_rst;
wire spc6_stb_ack_vld3 = `TOP_DESIGN.sparc6.lsu.stb_ctl3.ack_vld;
wire spc6_ld3_inst_vld_g = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_inst_vld_g;
wire spc6_intrpt3_cmplt = `TOP_DESIGN.sparc6.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc6_stb3_full = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_full;
wire spc6_stb3_full_w2 = `TOP_DESIGN.sparc6.lsu.stb_ctl3.stb_full_w2;
wire spc6_lmq3_full = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_pcx_rq_vld;
wire spc6_mbar_vld3 = `TOP_DESIGN.sparc6.lsu.dctl.mbar_vld3;
wire spc6_ld3_unfilled = `TOP_DESIGN.sparc6.lsu.qctl1.ld3_unfilled;
wire spc6_flsh_vld3 = `TOP_DESIGN.sparc6.lsu.dctl.flsh_vld3;
reg [9:0] spc6_ld3_unf_cntr;
reg spc6_ld3_unfilled_d;
reg [9:0] spc6_st3_unf_cntr;
reg spc6_st3_unfilled_d;
reg spc6_st3_unfilled;
reg spc6_mbar_vld_d3;
reg spc6_flsh_vld_d3;
reg spc6_lmq3_full_d;
reg [9:0] spc6_lmq_full_cntr3;
reg spc6_lmq_full_capture3;
reg [9:0] spc6_stb_full_cntr3;
reg spc6_stb_full_capture3;
reg [9:0] spc6_mbar_vld_cntr3;
reg spc6_mbar_vld_capture3;
reg [9:0] spc6_flsh_vld_cntr3;
reg spc6_flsh_vld_capture3;
reg spc6_stb_head_hit3;
wire spc6_raw_ack_capture3;
reg [9:0] spc6_stb_ack_cntr3;
reg [9:0] spc6_stb_ced_cntr3;
reg spc6_stb_ced3_d;
reg spc6_stb_ced_capture3;
wire spc6_stb_ced3;
reg spc6_atm3_d;
reg [9:0] spc6_atm_cntr3;
reg spc6_atm_intrpt_capture3;
reg spc6_atm_intrpt_b4capture3;
reg spc6_atm_inv_capture3;
reg [39:0] spc6_stb_wr_addr3;
reg [39:0] spc6_stb_atm_addr3;
reg spc6_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc6_fpick = {spc6_mpick,spc6_spick,spc6_lpick,spc6_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc6_msquash,spc6_apick,spc6_fpick})
9'b000000000 : spc6_fpicko = 1'b0;
9'b0xxx1xxx1 : spc6_fpicko = 1'b0;
9'b1xxxxxxxx : spc6_fpicko = 1'b0;
9'b0xxx0xxx0 : spc6_fpicko = 1'b0;
default:
begin
spc6_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon6 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc6_exu_und = {spc6_l2,
spc6_unc,
spc6_fpld,
spc6_fpldst,
spc6_unflush,
spc6_ldw,
spc6_byp,
spc6_flsh,
spc6_chm,
spc6_ldxa,
spc6_ato,
spc6_pref,
spc6_chit,
spc6_dcp,
spc6_dtp,
spc6_mpc,
spc6_mpu};
always @(spc6_exu_und)
begin
case (spc6_exu_und)
17'h00000 : spc6_exu = 5'h00;
17'h00001 : spc6_exu = 5'h01;
17'h00002 : spc6_exu = 5'h02;
17'h00004 : spc6_exu = 5'h03;
17'h00008 : spc6_exu = 5'h04;
17'h00010 : spc6_exu = 5'h05;
17'h00020 : spc6_exu = 5'h06;
17'h00040 : spc6_exu = 5'h07;
17'h00080 : spc6_exu = 5'h08;
17'h00100 : spc6_exu = 5'h09;
17'h00200 : spc6_exu = 5'h0a;
17'h00400 : spc6_exu = 5'h0b;
17'h00800 : spc6_exu = 5'h0c;
17'h01000 : spc6_exu = 5'h0d;
17'h02000 : spc6_exu = 5'h0e;
17'h04000 : spc6_exu = 5'h0f;
17'h08000 : spc6_exu = 5'h10;
17'h10000 : spc6_exu = 5'h11;
default: spc6_exu = 5'h12;
endcase
end
//excp
assign spc6_exp_und = {spc6_exp_wtchpt_trp_g,
spc6_exp_misalign_addr_ldst_atm_m,
spc6_exp_priv_violtn_g,
spc6_exp_daccess_excptn_g,
spc6_exp_daccess_prot_g,
spc6_exp_priv_action_g,
spc6_exp_spec_access_epage_g,
spc6_exp_uncache_atomic_g,
spc6_exp_illegal_asi_action_g,
spc6_exp_flt_ld_nfo_pg_g,
spc6_exp_asi_rd_unc,
spc6_exp_tlb_data_ce,
spc6_exp_tlb_data_ue,
spc6_exp_tlb_tag_ue,
spc6_exp_unc,
spc6_exp_corr};
always @(spc6_exp_und)
begin
case (spc6_exp_und)
16'h0000 : spc6_exp = 5'h00;
16'h0001 : spc6_exp = 5'h01;
16'h0002 : spc6_exp = 5'h02;
16'h0004 : spc6_exp = 5'h03;
16'h0008 : spc6_exp = 5'h04;
16'h0010 : spc6_exp = 5'h05;
16'h0020 : spc6_exp = 5'h06;
16'h0040 : spc6_exp = 5'h07;
16'h0080 : spc6_exp = 5'h08;
16'h0100 : spc6_exp = 5'h09;
16'h0200 : spc6_exp = 5'h0a;
16'h0400 : spc6_exp = 5'h0b;
16'h0800 : spc6_exp = 5'h0c;
16'h1000 : spc6_exp = 5'h0d;
16'h2000 : spc6_exp = 5'h0e;
16'h4000 : spc6_exp = 5'h0f;
16'h8000 : spc6_exp = 5'h10;
default: spc6_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc6_dctl_stxa_cmplt0 = ((spc6_dctl_stxa_internal_d2 & spc6_dctl_thread0_w3) |
spc6_dctl_stxa_stall_wr_cmplt0_d1);
assign spc6_dctl_l2fill_cmplt0 = (((spc6_dctl_lsu_l2fill_vld & ~spc6_dctl_atomic_ld_squash_e &
~spc6_dctl_lsu_ignore_fill)) & ~spc6_dctl_l2fill_fpld_e &
~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread0);
assign spc6_dctl_fillerr0 = spc6_dctl_l2_corr_error_e & spc6_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc6_dctl_atm_cmplt0 = (spc6_dctl_lsu_atm_st_cmplt_e & ~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread0);
assign spc6_dctl_ldst_cond_cmplt0 = { spc6_dctl_stxa_cmplt0, spc6_dctl_l2fill_cmplt0,
spc6_dctl_atomic_ld_squash_e, spc6_dctl_intld_byp_cmplt[0],
spc6_dctl_bsync0_reset, spc6_dctl_lsu_intrpt_cmplt[0]
};
assign spc6_cmplt0 = { spc6_dctl_ldxa_illgl_va_cmplt_d1, spc6_dctl_pref_tlbmiss_cmplt_d2,
spc6_dctl_lsu_pcx_pref_issue, spc6_dctl_diag_wr_cmplt0, spc6_dctl_l2fill_fpld_e};
always @(spc6_cmplt0 or spc6_dctl_ldst_cond_cmplt0)
begin
case ({spc6_dctl_fillerr0,spc6_dctl_ldst_cond_cmplt0,spc6_cmplt0})
12'h000 : spc6_ldstcond_cmplt0 = 4'h0;
12'h001 : spc6_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc6_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc6_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc6_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc6_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc6_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc6_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc6_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc6_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc6_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc6_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc6_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc6_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc6_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc6_dctl_stxa_cmplt1 = ((spc6_dctl_stxa_internal_d2 & spc6_dctl_thread1_w3) |
spc6_dctl_stxa_stall_wr_cmplt1_d1);
assign spc6_dctl_l2fill_cmplt1 = (((spc6_dctl_lsu_l2fill_vld & ~spc6_dctl_atomic_ld_squash_e &
~spc6_dctl_lsu_ignore_fill)) & ~spc6_dctl_l2fill_fpld_e &
~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread1);
assign spc6_dctl_fillerr1 = spc6_dctl_l2_corr_error_e & spc6_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc6_dctl_atm_cmplt1 = (spc6_dctl_lsu_atm_st_cmplt_e & ~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread1);
assign spc6_dctl_ldst_cond_cmplt1 = { spc6_dctl_stxa_cmplt1, spc6_dctl_l2fill_cmplt1,
spc6_dctl_atomic_ld_squash_e, spc6_dctl_intld_byp_cmplt[1],
spc6_dctl_bsync1_reset, spc6_dctl_lsu_intrpt_cmplt[1]
};
assign spc6_cmplt1 = { spc6_dctl_ldxa_illgl_va_cmplt_d1, spc6_dctl_pref_tlbmiss_cmplt_d2,
spc6_dctl_lsu_pcx_pref_issue, spc6_dctl_diag_wr_cmplt1, spc6_dctl_l2fill_fpld_e};
always @(spc6_cmplt1 or spc6_dctl_ldst_cond_cmplt1)
begin
case ({spc6_dctl_fillerr1,spc6_dctl_ldst_cond_cmplt1,spc6_cmplt1})
12'h000 : spc6_ldstcond_cmplt1 = 4'h0;
12'h001 : spc6_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc6_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc6_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc6_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc6_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc6_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc6_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc6_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc6_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc6_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc6_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc6_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc6_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc6_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc6_dctl_stxa_cmplt2 = ((spc6_dctl_stxa_internal_d2 & spc6_dctl_thread2_w3) |
spc6_dctl_stxa_stall_wr_cmplt2_d1);
assign spc6_dctl_l2fill_cmplt2 = (((spc6_dctl_lsu_l2fill_vld & ~spc6_dctl_atomic_ld_squash_e &
~spc6_dctl_lsu_ignore_fill)) & ~spc6_dctl_l2fill_fpld_e &
~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread2);
assign spc6_dctl_fillerr2 = spc6_dctl_l2_corr_error_e & spc6_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc6_dctl_atm_cmplt2 = (spc6_dctl_lsu_atm_st_cmplt_e & ~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread2);
assign spc6_dctl_ldst_cond_cmplt2 = { spc6_dctl_stxa_cmplt2, spc6_dctl_l2fill_cmplt2,
spc6_dctl_atomic_ld_squash_e, spc6_dctl_intld_byp_cmplt[2],
spc6_dctl_bsync2_reset, spc6_dctl_lsu_intrpt_cmplt[2]
};
assign spc6_cmplt2 = { spc6_dctl_ldxa_illgl_va_cmplt_d1, spc6_dctl_pref_tlbmiss_cmplt_d2,
spc6_dctl_lsu_pcx_pref_issue, spc6_dctl_diag_wr_cmplt2, spc6_dctl_l2fill_fpld_e};
always @(spc6_cmplt2 or spc6_dctl_ldst_cond_cmplt2)
begin
case ({spc6_dctl_fillerr2,spc6_dctl_ldst_cond_cmplt2,spc6_cmplt2})
12'h000 : spc6_ldstcond_cmplt2 = 4'h0;
12'h001 : spc6_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc6_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc6_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc6_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc6_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc6_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc6_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc6_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc6_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc6_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc6_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc6_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc6_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc6_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc6_dctl_stxa_cmplt3 = ((spc6_dctl_stxa_internal_d2 & spc6_dctl_thread3_w3) |
spc6_dctl_stxa_stall_wr_cmplt3_d1);
assign spc6_dctl_l2fill_cmplt3 = (((spc6_dctl_lsu_l2fill_vld & ~spc6_dctl_atomic_ld_squash_e &
~spc6_dctl_lsu_ignore_fill)) & ~spc6_dctl_l2fill_fpld_e &
~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread3);
assign spc6_dctl_fillerr3 = spc6_dctl_l2_corr_error_e & spc6_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc6_dctl_atm_cmplt3 = (spc6_dctl_lsu_atm_st_cmplt_e & ~spc6_dctl_fill_err_trap_e & spc6_dctl_dfill_thread3);
assign spc6_dctl_ldst_cond_cmplt3 = { spc6_dctl_stxa_cmplt3, spc6_dctl_l2fill_cmplt3,
spc6_dctl_atomic_ld_squash_e, spc6_dctl_intld_byp_cmplt[3],
spc6_dctl_bsync3_reset, spc6_dctl_lsu_intrpt_cmplt[3]
};
assign spc6_cmplt3 = { spc6_dctl_ldxa_illgl_va_cmplt_d1, spc6_dctl_pref_tlbmiss_cmplt_d2,
spc6_dctl_lsu_pcx_pref_issue, spc6_dctl_diag_wr_cmplt3, spc6_dctl_l2fill_fpld_e};
always @(spc6_cmplt3 or spc6_dctl_ldst_cond_cmplt3)
begin
case ({spc6_dctl_fillerr3,spc6_dctl_ldst_cond_cmplt3,spc6_cmplt3})
12'h000 : spc6_ldstcond_cmplt3 = 4'h0;
12'h001 : spc6_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc6_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc6_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc6_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc6_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc6_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc6_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc6_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc6_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc6_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc6_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc6_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc6_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc6_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc6_ldstcond_cmplt0 or spc6_ldstcond_cmplt1 or spc6_ldstcond_cmplt2
or spc6_ldstcond_cmplt3 or spc6_dctl_lsu_ifu_ldst_cmplt
or spc6_dctl_late_cmplt0 or spc6_dctl_late_cmplt1 or spc6_dctl_late_cmplt2 or spc6_dctl_late_cmplt3)
begin
case (spc6_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc6_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc6_ldstcond_cmplt_d = spc6_dctl_late_cmplt0 ? spc6_ldstcond_cmplt0_d : spc6_ldstcond_cmplt0;
4'b0010 : spc6_ldstcond_cmplt_d = spc6_dctl_late_cmplt1 ? spc6_ldstcond_cmplt1_d : spc6_ldstcond_cmplt1;
4'b0100 : spc6_ldstcond_cmplt_d = spc6_dctl_late_cmplt2 ? spc6_ldstcond_cmplt2_d : spc6_ldstcond_cmplt2;
4'b1000 : spc6_ldstcond_cmplt_d = spc6_dctl_late_cmplt3 ? spc6_ldstcond_cmplt3_d : spc6_ldstcond_cmplt3;
4'b0011 : spc6_ldstcond_cmplt_d = 4'he;
4'b0101 : spc6_ldstcond_cmplt_d = 4'he;
4'b1001 : spc6_ldstcond_cmplt_d = 4'he;
4'b0110 : spc6_ldstcond_cmplt_d = 4'he;
4'b1010 : spc6_ldstcond_cmplt_d = 4'he;
4'b1100 : spc6_ldstcond_cmplt_d = 4'he;
default:
begin
spc6_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc6_st_ooo_ret = { spc6_st0_lt_1, spc6_st0_lt_2, spc6_st0_lt_3,
spc6_st1_lt_0, spc6_st1_lt_2, spc6_st1_lt_3,
spc6_st2_lt_0, spc6_st2_lt_1, spc6_st2_lt_3,
spc6_st3_lt_0, spc6_st3_lt_1, spc6_st3_lt_2};
always @(posedge clk)
begin
if(~spc6_st0_unfilled || ~rst_l)
spc6_st0_unfilled_d <= 1'b0;
else
spc6_st0_unfilled_d <= spc6_st0_unfilled;
if(~rst_l)
spc6_ldstcond_cmplt0_d <= 4'h0;
else
spc6_ldstcond_cmplt0_d <= spc6_ldstcond_cmplt0;
if(~spc6_ld0_pkt_vld_unmasked || ~rst_l)
spc6_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc6_ld0_pkt_vld_unmasked_d <= spc6_ld0_pkt_vld_unmasked;
if(~rst_l)
spc6_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc6_qctl1_ld_sec_hit_thrd0 && spc6_qctl1_ld0_inst_vld_g)
spc6_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc6_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc6_st1_unfilled || ~rst_l)
spc6_st1_unfilled_d <= 1'b0;
else
spc6_st1_unfilled_d <= spc6_st1_unfilled;
if(~rst_l)
spc6_ldstcond_cmplt1_d <= 4'h0;
else
spc6_ldstcond_cmplt1_d <= spc6_ldstcond_cmplt1;
if(~spc6_ld1_pkt_vld_unmasked || ~rst_l)
spc6_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc6_ld1_pkt_vld_unmasked_d <= spc6_ld1_pkt_vld_unmasked;
if(~rst_l)
spc6_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc6_qctl1_ld_sec_hit_thrd1 && spc6_qctl1_ld1_inst_vld_g)
spc6_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc6_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc6_st2_unfilled || ~rst_l)
spc6_st2_unfilled_d <= 1'b0;
else
spc6_st2_unfilled_d <= spc6_st2_unfilled;
if(~rst_l)
spc6_ldstcond_cmplt2_d <= 4'h0;
else
spc6_ldstcond_cmplt2_d <= spc6_ldstcond_cmplt2;
if(~spc6_ld2_pkt_vld_unmasked || ~rst_l)
spc6_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc6_ld2_pkt_vld_unmasked_d <= spc6_ld2_pkt_vld_unmasked;
if(~rst_l)
spc6_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc6_qctl1_ld_sec_hit_thrd2 && spc6_qctl1_ld2_inst_vld_g)
spc6_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc6_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc6_st3_unfilled || ~rst_l)
spc6_st3_unfilled_d <= 1'b0;
else
spc6_st3_unfilled_d <= spc6_st3_unfilled;
if(~rst_l)
spc6_ldstcond_cmplt3_d <= 4'h0;
else
spc6_ldstcond_cmplt3_d <= spc6_ldstcond_cmplt3;
if(~spc6_ld3_pkt_vld_unmasked || ~rst_l)
spc6_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc6_ld3_pkt_vld_unmasked_d <= spc6_ld3_pkt_vld_unmasked;
if(~rst_l)
spc6_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc6_qctl1_ld_sec_hit_thrd3 && spc6_qctl1_ld3_inst_vld_g)
spc6_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc6_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc6_stb_state_ced0) && (|spc6_stb_state_rst0)) || ~rst_l)
spc6_st0_unfilled <= 1'b0;
else if( ((|spc6_stb_state_ced0) && ~(|spc6_stb_state_rst0)))
spc6_st0_unfilled <= 1'b1;
else
spc6_st0_unfilled <= spc6_st0_unfilled;
if( ((|spc6_stb_state_ced1) && (|spc6_stb_state_rst1)) || ~rst_l)
spc6_st1_unfilled <= 1'b0;
else if( ((|spc6_stb_state_ced1) && ~(|spc6_stb_state_rst1)))
spc6_st1_unfilled <= 1'b1;
else
spc6_st1_unfilled <= spc6_st1_unfilled;
if( ((|spc6_stb_state_ced2) && (|spc6_stb_state_rst2)) || ~rst_l)
spc6_st2_unfilled <= 1'b0;
else if( ((|spc6_stb_state_ced2) && ~(|spc6_stb_state_rst2)))
spc6_st2_unfilled <= 1'b1;
else
spc6_st2_unfilled <= spc6_st2_unfilled;
if( ((|spc6_stb_state_ced3) && (|spc6_stb_state_rst3)) || ~rst_l)
spc6_st3_unfilled <= 1'b0;
else if( ((|spc6_stb_state_ced3) && ~(|spc6_stb_state_rst3)))
spc6_st3_unfilled <= 1'b1;
else
spc6_st3_unfilled <= spc6_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc6_st0_unfilled && spc6_st0_unfilled_d)|| ~rst_l)
begin
spc6_st0_unf_cntr <= 9'h000;
end
else if(spc6_st0_unfilled)
begin
spc6_st0_unf_cntr <= spc6_st0_unf_cntr + 1;
end
else
begin
spc6_st0_unf_cntr <= spc6_st0_unf_cntr;
end
if((~spc6_st1_unfilled && spc6_st1_unfilled_d)|| ~rst_l)
begin
spc6_st1_unf_cntr <= 9'h000;
end
else if(spc6_st1_unfilled)
begin
spc6_st1_unf_cntr <= spc6_st1_unf_cntr + 1;
end
else
begin
spc6_st1_unf_cntr <= spc6_st1_unf_cntr;
end
if((~spc6_st2_unfilled && spc6_st2_unfilled_d)|| ~rst_l)
begin
spc6_st2_unf_cntr <= 9'h000;
end
else if(spc6_st2_unfilled)
begin
spc6_st2_unf_cntr <= spc6_st2_unf_cntr + 1;
end
else
begin
spc6_st2_unf_cntr <= spc6_st2_unf_cntr;
end
if((~spc6_st3_unfilled && spc6_st3_unfilled_d)|| ~rst_l)
begin
spc6_st3_unf_cntr <= 9'h000;
end
else if(spc6_st3_unfilled)
begin
spc6_st3_unf_cntr <= spc6_st3_unf_cntr + 1;
end
else
begin
spc6_st3_unf_cntr <= spc6_st3_unf_cntr;
end
end
always @(spc6_st0_unfilled or spc6_st1_unfilled or spc6_st2_unfilled or spc6_st3_unfilled
or spc6_st0_unfilled_d or spc6_st1_unfilled_d or spc6_st2_unfilled_d or spc6_st3_unfilled_d)
begin
if(~spc6_st0_unfilled && spc6_st0_unfilled_d && spc6_st1_unfilled)
spc6_st0_lt_1 <= (spc6_st1_unf_cntr > spc6_st0_unf_cntr);
else
spc6_st0_lt_1 <= 1'b0;
if(~spc6_st0_unfilled && spc6_st0_unfilled_d && spc6_st2_unfilled)
spc6_st0_lt_2 <= (spc6_st2_unf_cntr > spc6_st0_unf_cntr);
else
spc6_st0_lt_2 <= 1'b0;
if(~spc6_st0_unfilled && spc6_st0_unfilled_d && spc6_st3_unfilled)
spc6_st0_lt_3 <= (spc6_st3_unf_cntr > spc6_st0_unf_cntr);
else
spc6_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc6_st1_unfilled && spc6_st1_unfilled_d && spc6_st0_unfilled)
spc6_st1_lt_0 <= (spc6_st0_unf_cntr > spc6_st1_unf_cntr);
else
spc6_st1_lt_0 <= 1'b0;
if(~spc6_st1_unfilled && spc6_st1_unfilled_d && spc6_st2_unfilled)
spc6_st1_lt_2 <= (spc6_st2_unf_cntr > spc6_st1_unf_cntr);
else
spc6_st1_lt_2 <= 1'b0;
if(~spc6_st1_unfilled && spc6_st1_unfilled_d && spc6_st3_unfilled)
spc6_st1_lt_3 <= (spc6_st3_unf_cntr > spc6_st1_unf_cntr);
else
spc6_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc6_st2_unfilled && spc6_st2_unfilled_d && spc6_st0_unfilled)
spc6_st2_lt_0 <= (spc6_st0_unf_cntr > spc6_st2_unf_cntr);
else
spc6_st2_lt_0 <= 1'b0;
if(~spc6_st2_unfilled && spc6_st2_unfilled_d && spc6_st1_unfilled)
spc6_st2_lt_1 <= (spc6_st1_unf_cntr > spc6_st2_unf_cntr);
else
spc6_st2_lt_1 <= 1'b0;
if(~spc6_st2_unfilled && spc6_st2_unfilled_d && spc6_st3_unfilled)
spc6_st2_lt_3 <= (spc6_st3_unf_cntr > spc6_st2_unf_cntr);
else
spc6_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc6_st3_unfilled && spc6_st3_unfilled_d && spc6_st0_unfilled)
spc6_st3_lt_0 <= (spc6_st0_unf_cntr > spc6_st3_unf_cntr);
else
spc6_st3_lt_0 <= 1'b0;
if(~spc6_st3_unfilled && spc6_st3_unfilled_d && spc6_st1_unfilled)
spc6_st3_lt_1 <= (spc6_st1_unf_cntr > spc6_st3_unf_cntr);
else
spc6_st3_lt_1 <= 1'b0;
if(~spc6_st3_unfilled && spc6_st3_unfilled_d && spc6_st2_unfilled)
spc6_st3_lt_2 <= (spc6_st2_unf_cntr > spc6_st3_unf_cntr);
else
spc6_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc6_ld_ooo_ret = { spc6_ld0_lt_1, spc6_ld0_lt_2, spc6_ld0_lt_3,
spc6_ld1_lt_0, spc6_ld1_lt_2, spc6_ld1_lt_3,
spc6_ld2_lt_0, spc6_ld2_lt_1, spc6_ld2_lt_3,
spc6_ld3_lt_0, spc6_ld3_lt_1, spc6_ld3_lt_2};
always @(posedge clk)
begin
if((~spc6_ld0_unfilled && spc6_ld0_unfilled_d)|| ~rst_l)
begin
spc6_ld0_unf_cntr <= 9'h000;
end
else if(spc6_ld0_unfilled)
begin
spc6_ld0_unf_cntr <= spc6_ld0_unf_cntr + 1;
end
else
begin
spc6_ld0_unf_cntr <= spc6_ld0_unf_cntr;
end
if((~spc6_ld1_unfilled && spc6_ld1_unfilled_d)|| ~rst_l)
begin
spc6_ld1_unf_cntr <= 9'h000;
end
else if(spc6_ld1_unfilled)
begin
spc6_ld1_unf_cntr <= spc6_ld1_unf_cntr + 1;
end
else
begin
spc6_ld1_unf_cntr <= spc6_ld1_unf_cntr;
end
if((~spc6_ld2_unfilled && spc6_ld2_unfilled_d)|| ~rst_l)
begin
spc6_ld2_unf_cntr <= 9'h000;
end
else if(spc6_ld2_unfilled)
begin
spc6_ld2_unf_cntr <= spc6_ld2_unf_cntr + 1;
end
else
begin
spc6_ld2_unf_cntr <= spc6_ld2_unf_cntr;
end
if((~spc6_ld3_unfilled && spc6_ld3_unfilled_d)|| ~rst_l)
begin
spc6_ld3_unf_cntr <= 9'h000;
end
else if(spc6_ld3_unfilled)
begin
spc6_ld3_unf_cntr <= spc6_ld3_unf_cntr + 1;
end
else
begin
spc6_ld3_unf_cntr <= spc6_ld3_unf_cntr;
end
end
always @(spc6_ld0_unfilled or spc6_ld1_unfilled or spc6_ld2_unfilled or spc6_ld3_unfilled
or spc6_ld0_unfilled_d or spc6_ld1_unfilled_d or spc6_ld2_unfilled_d or spc6_ld3_unfilled_d)
begin
if(~spc6_ld0_unfilled && spc6_ld0_unfilled_d && spc6_ld1_unfilled)
spc6_ld0_lt_1 <= (spc6_ld1_unf_cntr > spc6_ld0_unf_cntr);
else
spc6_ld0_lt_1 <= 1'b0;
if(~spc6_ld0_unfilled && spc6_ld0_unfilled_d && spc6_ld2_unfilled)
spc6_ld0_lt_2 <= (spc6_ld2_unf_cntr > spc6_ld0_unf_cntr);
else
spc6_ld0_lt_2 <= 1'b0;
if(~spc6_ld0_unfilled && spc6_ld0_unfilled_d && spc6_ld3_unfilled)
spc6_ld0_lt_3 <= (spc6_ld3_unf_cntr > spc6_ld0_unf_cntr);
else
spc6_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc6_ld1_unfilled && spc6_ld1_unfilled_d && spc6_ld0_unfilled)
spc6_ld1_lt_0 <= (spc6_ld0_unf_cntr > spc6_ld1_unf_cntr);
else
spc6_ld1_lt_0 <= 1'b0;
if(~spc6_ld1_unfilled && spc6_ld1_unfilled_d && spc6_ld2_unfilled)
spc6_ld1_lt_2 <= (spc6_ld2_unf_cntr > spc6_ld1_unf_cntr);
else
spc6_ld1_lt_2 <= 1'b0;
if(~spc6_ld1_unfilled && spc6_ld1_unfilled_d && spc6_ld3_unfilled)
spc6_ld1_lt_3 <= (spc6_ld3_unf_cntr > spc6_ld1_unf_cntr);
else
spc6_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc6_ld2_unfilled && spc6_ld2_unfilled_d && spc6_ld0_unfilled)
spc6_ld2_lt_0 <= (spc6_ld0_unf_cntr > spc6_ld2_unf_cntr);
else
spc6_ld2_lt_0 <= 1'b0;
if(~spc6_ld2_unfilled && spc6_ld2_unfilled_d && spc6_ld1_unfilled)
spc6_ld2_lt_1 <= (spc6_ld1_unf_cntr > spc6_ld2_unf_cntr);
else
spc6_ld2_lt_1 <= 1'b0;
if(~spc6_ld2_unfilled && spc6_ld2_unfilled_d && spc6_ld3_unfilled)
spc6_ld2_lt_3 <= (spc6_ld3_unf_cntr > spc6_ld2_unf_cntr);
else
spc6_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc6_ld3_unfilled && spc6_ld3_unfilled_d && spc6_ld0_unfilled)
spc6_ld3_lt_0 <= (spc6_ld0_unf_cntr > spc6_ld3_unf_cntr);
else
spc6_ld3_lt_0 <= 1'b0;
if(~spc6_ld3_unfilled && spc6_ld3_unfilled_d && spc6_ld1_unfilled)
spc6_ld3_lt_1 <= (spc6_ld1_unf_cntr > spc6_ld3_unf_cntr);
else
spc6_ld3_lt_1 <= 1'b0;
if(~spc6_ld3_unfilled && spc6_ld3_unfilled_d && spc6_ld2_unfilled)
spc6_ld3_lt_2 <= (spc6_ld2_unf_cntr > spc6_ld3_unf_cntr);
else
spc6_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc6_dctl_bld_hit =
((|spc6_dctl_lsu_way_hit[3:0]) & spc6_dctl_dcache_enable_g &
~spc6_dctl_ldxa_internal & ~spc6_dctl_dcache_rd_parity_error & ~spc6_dctl_dtag_perror_g &
~spc6_dctl_endian_mispred_g &
~spc6_dctl_atomic_g & ~spc6_dctl_ncache_asild_rq_g) & ~spc6_dctl_tte_data_perror_unc &
spc6_dctl_ld_inst_vld_g & spc6_qctl1_bld_g ;
assign spc6_dctl_bld_stb_hit = spc6_dctl_bld_hit & spc6_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc6_bld0_full_d <= 2'b00;
spc6_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc6_bld0_full_d <= spc6_qctl1_bld_cnt;
spc6_ld0_unfilled_d <= spc6_ld0_unfilled;
end
if(~rst_l)
begin
spc6_bld1_full_d <= 2'b00;
spc6_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc6_bld1_full_d <= spc6_qctl1_bld_cnt;
spc6_ld1_unfilled_d <= spc6_ld1_unfilled;
end
if(~rst_l)
begin
spc6_bld2_full_d <= 2'b00;
spc6_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc6_bld2_full_d <= spc6_qctl1_bld_cnt;
spc6_ld2_unfilled_d <= spc6_ld2_unfilled;
end
if(~rst_l)
begin
spc6_bld3_full_d <= 2'b00;
spc6_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc6_bld3_full_d <= spc6_qctl1_bld_cnt;
spc6_ld3_unfilled_d <= spc6_ld3_unfilled;
end
end
always @(spc6_bld0_full_d or spc6_qctl1_bld_cnt)
begin
if( (spc6_bld0_full_d != spc6_qctl1_bld_cnt) && (spc6_bld0_full_d == 2'd0))
spc6_bld0_full_capture <= 1'b1;
else
spc6_bld0_full_capture <= 1'b0;
end
always @(spc6_bld1_full_d or spc6_qctl1_bld_cnt)
begin
if( (spc6_bld1_full_d != spc6_qctl1_bld_cnt) && (spc6_bld1_full_d == 2'd1))
spc6_bld1_full_capture <= 1'b1;
else
spc6_bld1_full_capture <= 1'b0;
end
always @(spc6_bld2_full_d or spc6_qctl1_bld_cnt)
begin
if( (spc6_bld2_full_d != spc6_qctl1_bld_cnt) && (spc6_bld2_full_d == 2'd2))
spc6_bld2_full_capture <= 1'b1;
else
spc6_bld2_full_capture <= 1'b0;
end
always @(spc6_bld3_full_d or spc6_qctl1_bld_cnt)
begin
if( (spc6_bld3_full_d != spc6_qctl1_bld_cnt) && (spc6_bld3_full_d == 2'd3))
spc6_bld3_full_capture <= 1'b1;
else
spc6_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc6_qctl1_bld_cnt != 2'b00) && (spc6_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc6_bld0_full_cntr <= 9'h000;
end
else if(spc6_qctl1_bld_g && (spc6_qctl1_bld_cnt == 2'b00))
begin
spc6_bld0_full_cntr <= spc6_bld0_full_cntr + 1;
end
else if( (spc6_qctl1_bld_cnt == 2'b00) && (spc6_bld0_full_cntr != 9'h000))
begin
spc6_bld0_full_cntr <= spc6_bld0_full_cntr + 1;
end
else
begin
spc6_bld0_full_cntr <= spc6_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc6_qctl1_bld_cnt != 2'b01) && (spc6_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc6_bld1_full_cntr <= 9'h000;
end
else if(spc6_qctl1_bld_cnt == 2'b01)
begin
spc6_bld1_full_cntr <= spc6_bld1_full_cntr + 1;
end
else if( (spc6_qctl1_bld_cnt == 2'b01) && (spc6_bld1_full_cntr != 9'h000))
begin
spc6_bld1_full_cntr <= spc6_bld1_full_cntr + 1;
end
else
begin
spc6_bld1_full_cntr <= spc6_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc6_qctl1_bld_cnt != 2'b10) && (spc6_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc6_bld2_full_cntr <= 9'h000;
end
else if(spc6_qctl1_bld_cnt == 2'b10)
begin
spc6_bld2_full_cntr <= spc6_bld2_full_cntr + 1;
end
else if( (spc6_qctl1_bld_cnt == 2'b10) && (spc6_bld2_full_cntr != 9'h000))
begin
spc6_bld2_full_cntr <= spc6_bld2_full_cntr + 1;
end
else
begin
spc6_bld2_full_cntr <= spc6_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc6_qctl1_bld_cnt != 2'b11) && (spc6_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc6_bld3_full_cntr <= 9'h000;
end
else if(spc6_qctl1_bld_cnt == 2'b11)
begin
spc6_bld3_full_cntr <= spc6_bld3_full_cntr + 1;
end
else if( (spc6_qctl1_bld_cnt == 2'b11) && (spc6_bld3_full_cntr != 9'h000))
begin
spc6_bld3_full_cntr <= spc6_bld3_full_cntr + 1;
end
else
begin
spc6_bld3_full_cntr <= spc6_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc6_stb_state_vld0) && ~spc6_atomic_g) || ~rst_l)
begin
spc6_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc6_atomic_g && (spc6_atm_type0 != 8'h00) && spc6_wptr_vld)
begin
spc6_stb_atm_addr0 <= {spc6_wdata_ramc[44:9],spc6_wdata_ramd[67:64]};
end
else
begin
spc6_stb_atm_addr0 <= spc6_stb_atm_addr0;
end
if( ( ~(|spc6_stb_state_vld1) && ~spc6_atomic_g) || ~rst_l)
begin
spc6_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc6_atomic_g && (spc6_atm_type1 != 8'h00) && spc6_wptr_vld)
begin
spc6_stb_atm_addr1 <= {spc6_wdata_ramc[44:9],spc6_wdata_ramd[67:64]};
end
else
begin
spc6_stb_atm_addr1 <= spc6_stb_atm_addr1;
end
if( ( ~(|spc6_stb_state_vld2) && ~spc6_atomic_g) || ~rst_l)
begin
spc6_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc6_atomic_g && (spc6_atm_type2 != 8'h00) && spc6_wptr_vld)
begin
spc6_stb_atm_addr2 <= {spc6_wdata_ramc[44:9],spc6_wdata_ramd[67:64]};
end
else
begin
spc6_stb_atm_addr2 <= spc6_stb_atm_addr2;
end
if( ( ~(|spc6_stb_state_vld3) && ~spc6_atomic_g) || ~rst_l)
begin
spc6_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc6_atomic_g && (spc6_atm_type3 != 8'h00) && spc6_wptr_vld)
begin
spc6_stb_atm_addr3 <= {spc6_wdata_ramc[44:9],spc6_wdata_ramd[67:64]};
end
else
begin
spc6_stb_atm_addr3 <= spc6_stb_atm_addr3;
end
end
assign spc6_dfq_full = (spc6_dfq_vld_entries >= 3'd4);
assign spc6_dfq_full1 = (spc6_dfq_vld_entries >= (3'd4 + 1));
always @(spc6_dfq_full_d1 or spc6_dfq_full1)
begin
if (spc6_dfq_full_d1 && ~spc6_dfq_full1)
spc6_dfq_full_capture1 <= 1'b1;
else
spc6_dfq_full_capture1 <= 1'b0;
end
assign spc6_dfq_full2 = (spc6_dfq_vld_entries >= (3'd4 + 2));
always @(spc6_dfq_full_d2 or spc6_dfq_full2)
begin
if (spc6_dfq_full_d2 && ~spc6_dfq_full2)
spc6_dfq_full_capture2 <= 1'b1;
else
spc6_dfq_full_capture2 <= 1'b0;
end
assign spc6_dfq_full3 = (spc6_dfq_vld_entries >= (3'd4 + 3));
always @(spc6_dfq_full_d3 or spc6_dfq_full3)
begin
if (spc6_dfq_full_d3 && ~spc6_dfq_full3)
spc6_dfq_full_capture3 <= 1'b1;
else
spc6_dfq_full_capture3 <= 1'b0;
end
assign spc6_dfq_full4 = (spc6_dfq_vld_entries >= (3'd4 + 4));
always @(spc6_dfq_full_d4 or spc6_dfq_full4)
begin
if (spc6_dfq_full_d4 && ~spc6_dfq_full4)
spc6_dfq_full_capture4 <= 1'b1;
else
spc6_dfq_full_capture4 <= 1'b0;
end
assign spc6_dfq_full5 = (spc6_dfq_vld_entries >= (3'd4 + 5));
always @(spc6_dfq_full_d5 or spc6_dfq_full5)
begin
if (spc6_dfq_full_d5 && ~spc6_dfq_full5)
spc6_dfq_full_capture5 <= 1'b1;
else
spc6_dfq_full_capture5 <= 1'b0;
end
assign spc6_dfq_full6 = (spc6_dfq_vld_entries >= (3'd4 + 6));
always @(spc6_dfq_full_d6 or spc6_dfq_full6)
begin
if (spc6_dfq_full_d6 && ~spc6_dfq_full6)
spc6_dfq_full_capture6 <= 1'b1;
else
spc6_dfq_full_capture6 <= 1'b0;
end
assign spc6_dfq_full7 = (spc6_dfq_vld_entries >= (3'd4 + 7));
always @(spc6_dfq_full_d7 or spc6_dfq_full7)
begin
if (spc6_dfq_full_d7 && ~spc6_dfq_full7)
spc6_dfq_full_capture7 <= 1'b1;
else
spc6_dfq_full_capture7 <= 1'b0;
end
always @(spc6_mbar_vld_d0 or spc6_mbar_vld0)
begin
if (spc6_mbar_vld_d0 && ~spc6_mbar_vld0)
spc6_mbar_vld_capture0 <= 1'b1;
else
spc6_mbar_vld_capture0 <= 1'b0;
end
always @(spc6_mbar_vld_d1 or spc6_mbar_vld1)
begin
if (spc6_mbar_vld_d1 && ~spc6_mbar_vld1)
spc6_mbar_vld_capture1 <= 1'b1;
else
spc6_mbar_vld_capture1 <= 1'b0;
end
always @(spc6_mbar_vld_d2 or spc6_mbar_vld2)
begin
if (spc6_mbar_vld_d2 && ~spc6_mbar_vld2)
spc6_mbar_vld_capture2 <= 1'b1;
else
spc6_mbar_vld_capture2 <= 1'b0;
end
always @(spc6_mbar_vld_d3 or spc6_mbar_vld3)
begin
if (spc6_mbar_vld_d3 && ~spc6_mbar_vld3)
spc6_mbar_vld_capture3 <= 1'b1;
else
spc6_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc6_dfq_full1 && (spc6_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr1 <= 9'h000;
spc6_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr1);
end
else if( spc6_dfq_full1)
begin
spc6_dfq_full_cntr1 <= spc6_dfq_full_cntr1 + 1;
spc6_dfq_full_d1 <= spc6_dfq_full1;
end
else
begin
spc6_dfq_full_cntr1 <= spc6_dfq_full_cntr1;
spc6_dfq_full_d1 <= spc6_dfq_full1;
end
if( ( ~spc6_dfq_full2 && (spc6_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr2 <= 9'h000;
spc6_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr2);
end
else if( spc6_dfq_full2)
begin
spc6_dfq_full_cntr2 <= spc6_dfq_full_cntr2 + 1;
spc6_dfq_full_d2 <= spc6_dfq_full2;
end
else
begin
spc6_dfq_full_cntr2 <= spc6_dfq_full_cntr2;
spc6_dfq_full_d2 <= spc6_dfq_full2;
end
if( ( ~spc6_dfq_full3 && (spc6_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr3 <= 9'h000;
spc6_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr3);
end
else if( spc6_dfq_full3)
begin
spc6_dfq_full_cntr3 <= spc6_dfq_full_cntr3 + 1;
spc6_dfq_full_d3 <= spc6_dfq_full3;
end
else
begin
spc6_dfq_full_cntr3 <= spc6_dfq_full_cntr3;
spc6_dfq_full_d3 <= spc6_dfq_full3;
end
if( ( ~spc6_dfq_full4 && (spc6_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr4 <= 9'h000;
spc6_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr4);
end
else if( spc6_dfq_full4)
begin
spc6_dfq_full_cntr4 <= spc6_dfq_full_cntr4 + 1;
spc6_dfq_full_d4 <= spc6_dfq_full4;
end
else
begin
spc6_dfq_full_cntr4 <= spc6_dfq_full_cntr4;
spc6_dfq_full_d4 <= spc6_dfq_full4;
end
if( ( ~spc6_dfq_full5 && (spc6_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr5 <= 9'h000;
spc6_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr5);
end
else if( spc6_dfq_full5)
begin
spc6_dfq_full_cntr5 <= spc6_dfq_full_cntr5 + 1;
spc6_dfq_full_d5 <= spc6_dfq_full5;
end
else
begin
spc6_dfq_full_cntr5 <= spc6_dfq_full_cntr5;
spc6_dfq_full_d5 <= spc6_dfq_full5;
end
if( ( ~spc6_dfq_full6 && (spc6_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr6 <= 9'h000;
spc6_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr6);
end
else if( spc6_dfq_full6)
begin
spc6_dfq_full_cntr6 <= spc6_dfq_full_cntr6 + 1;
spc6_dfq_full_d6 <= spc6_dfq_full6;
end
else
begin
spc6_dfq_full_cntr6 <= spc6_dfq_full_cntr6;
spc6_dfq_full_d6 <= spc6_dfq_full6;
end
if( ( ~spc6_dfq_full7 && (spc6_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr7 <= 9'h000;
spc6_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr7);
end
else if( spc6_dfq_full7)
begin
spc6_dfq_full_cntr7 <= spc6_dfq_full_cntr7 + 1;
spc6_dfq_full_d7 <= spc6_dfq_full7;
end
else
begin
spc6_dfq_full_cntr7 <= spc6_dfq_full_cntr7;
spc6_dfq_full_d7 <= spc6_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc6_intrpt0_cmplt or spc6_atm_cntr0 or spc6_stb_state_ced0)
begin
if (spc6_intrpt0_cmplt && (spc6_atm_cntr0 != 9'h000) && ~(|spc6_stb_state_ced0))
spc6_atm_intrpt_b4capture0 <= 1'b1;
else
spc6_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc6_intrpt1_cmplt or spc6_atm_cntr1 or spc6_stb_state_ced1)
begin
if (spc6_intrpt1_cmplt && (spc6_atm_cntr1 != 9'h000) && ~(|spc6_stb_state_ced1))
spc6_atm_intrpt_b4capture1 <= 1'b1;
else
spc6_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc6_intrpt2_cmplt or spc6_atm_cntr2 or spc6_stb_state_ced2)
begin
if (spc6_intrpt2_cmplt && (spc6_atm_cntr2 != 9'h000) && ~(|spc6_stb_state_ced2))
spc6_atm_intrpt_b4capture2 <= 1'b1;
else
spc6_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc6_intrpt3_cmplt or spc6_atm_cntr3 or spc6_stb_state_ced3)
begin
if (spc6_intrpt3_cmplt && (spc6_atm_cntr3 != 9'h000) && ~(|spc6_stb_state_ced3))
spc6_atm_intrpt_b4capture3 <= 1'b1;
else
spc6_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc6_intrpt0_cmplt or spc6_atm_cntr0 or spc6_stb_state_ced0)
begin
if (spc6_intrpt0_cmplt && (spc6_atm_cntr0 != 9'h000) && (|spc6_stb_state_ced0))
spc6_atm_intrpt_capture0 <= 1'b1;
else
spc6_atm_intrpt_capture0 <= 1'b0;
end
always @(spc6_intrpt1_cmplt or spc6_atm_cntr1 or spc6_stb_state_ced1)
begin
if (spc6_intrpt1_cmplt && (spc6_atm_cntr1 != 9'h000) && (|spc6_stb_state_ced1))
spc6_atm_intrpt_capture1 <= 1'b1;
else
spc6_atm_intrpt_capture1 <= 1'b0;
end
always @(spc6_intrpt2_cmplt or spc6_atm_cntr2 or spc6_stb_state_ced2)
begin
if (spc6_intrpt2_cmplt && (spc6_atm_cntr2 != 9'h000) && (|spc6_stb_state_ced2))
spc6_atm_intrpt_capture2 <= 1'b1;
else
spc6_atm_intrpt_capture2 <= 1'b0;
end
always @(spc6_intrpt3_cmplt or spc6_atm_cntr3 or spc6_stb_state_ced3)
begin
if (spc6_intrpt3_cmplt && (spc6_atm_cntr3 != 9'h000) && (|spc6_stb_state_ced3))
spc6_atm_intrpt_capture3 <= 1'b1;
else
spc6_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc6_atm_cntr0 or spc6_dva_din or spc6_dva_wen)
begin
if (~spc6_dva_din && spc6_dva_wen && (spc6_atm_cntr0 != 9'h000))
spc6_atm_inv_capture0 <= 1'b1;
else
spc6_atm_inv_capture0 <= 1'b0;
end
always @(spc6_atm_cntr1 or spc6_dva_din or spc6_dva_wen)
begin
if (~spc6_dva_din && spc6_dva_wen && (spc6_atm_cntr1 != 9'h000))
spc6_atm_inv_capture1 <= 1'b1;
else
spc6_atm_inv_capture1 <= 1'b0;
end
always @(spc6_atm_cntr2 or spc6_dva_din or spc6_dva_wen)
begin
if (~spc6_dva_din && spc6_dva_wen && (spc6_atm_cntr2 != 9'h000))
spc6_atm_inv_capture2 <= 1'b1;
else
spc6_atm_inv_capture2 <= 1'b0;
end
always @(spc6_atm_cntr3 or spc6_dva_din or spc6_dva_wen)
begin
if (~spc6_dva_din && spc6_dva_wen && (spc6_atm_cntr3 != 9'h000))
spc6_atm_inv_capture3 <= 1'b1;
else
spc6_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc6_stb_state_vld0) && (spc6_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_atm_cntr0 <= 9'h000;
spc6_atm0_d <= 1'b0;
end
else if( spc6_atomic_g && (spc6_atm_type0 != 8'h00))
begin
spc6_atm_cntr0 <= spc6_atm_cntr0 + 1;
spc6_atm0_d <= 1'b1;
end
else if( spc6_atm0_d && (|spc6_stb_state_vld0))
begin
spc6_atm_cntr0 <= spc6_atm_cntr0 + 1;
spc6_atm0_d <= spc6_atm0_d;
end
else
begin
spc6_atm_cntr0 <= spc6_atm_cntr0;
spc6_atm0_d <= spc6_atm0_d;
end
if( ( ~(|spc6_stb_state_vld1) && (spc6_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_atm_cntr1 <= 9'h000;
spc6_atm1_d <= 1'b0;
end
else if( spc6_atomic_g && (spc6_atm_type1 != 8'h00))
begin
spc6_atm_cntr1 <= spc6_atm_cntr1 + 1;
spc6_atm1_d <= 1'b1;
end
else if( spc6_atm1_d && (|spc6_stb_state_vld1))
begin
spc6_atm_cntr1 <= spc6_atm_cntr1 + 1;
spc6_atm1_d <= spc6_atm1_d;
end
else
begin
spc6_atm_cntr1 <= spc6_atm_cntr1;
spc6_atm1_d <= spc6_atm1_d;
end
if( ( ~(|spc6_stb_state_vld2) && (spc6_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_atm_cntr2 <= 9'h000;
spc6_atm2_d <= 1'b0;
end
else if( spc6_atomic_g && (spc6_atm_type2 != 8'h00))
begin
spc6_atm_cntr2 <= spc6_atm_cntr2 + 1;
spc6_atm2_d <= 1'b1;
end
else if( spc6_atm2_d && (|spc6_stb_state_vld2))
begin
spc6_atm_cntr2 <= spc6_atm_cntr2 + 1;
spc6_atm2_d <= spc6_atm2_d;
end
else
begin
spc6_atm_cntr2 <= spc6_atm_cntr2;
spc6_atm2_d <= spc6_atm2_d;
end
if( ( ~(|spc6_stb_state_vld3) && (spc6_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_atm_cntr3 <= 9'h000;
spc6_atm3_d <= 1'b0;
end
else if( spc6_atomic_g && (spc6_atm_type3 != 8'h00))
begin
spc6_atm_cntr3 <= spc6_atm_cntr3 + 1;
spc6_atm3_d <= 1'b1;
end
else if( spc6_atm3_d && (|spc6_stb_state_vld3))
begin
spc6_atm_cntr3 <= spc6_atm_cntr3 + 1;
spc6_atm3_d <= spc6_atm3_d;
end
else
begin
spc6_atm_cntr3 <= spc6_atm_cntr3;
spc6_atm3_d <= spc6_atm3_d;
end
end
assign spc6_raw_ack_capture0 = spc6_stb_ack_vld0 && (spc6_stb_ack_cntr0 != 9'h000);
assign spc6_stb_ced0 = |spc6_stb_state_ced0;
assign spc6_raw_ack_capture1 = spc6_stb_ack_vld1 && (spc6_stb_ack_cntr1 != 9'h000);
assign spc6_stb_ced1 = |spc6_stb_state_ced1;
assign spc6_raw_ack_capture2 = spc6_stb_ack_vld2 && (spc6_stb_ack_cntr2 != 9'h000);
assign spc6_stb_ced2 = |spc6_stb_state_ced2;
assign spc6_raw_ack_capture3 = spc6_stb_ack_vld3 && (spc6_stb_ack_cntr3 != 9'h000);
assign spc6_stb_ced3 = |spc6_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc6_stb_ced0 && (spc6_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_stb_ced_cntr0 <= 9'h000;
spc6_stb_ced0_d <= 1'b0;
end
else if( spc6_stb_ced0 && (spc6_stb_state_ack0 == 8'h00))
begin
spc6_stb_ced_cntr0 <= spc6_stb_ced_cntr0 + 1;
spc6_stb_ced0_d <= spc6_stb_ced0;
end
else
begin
spc6_stb_ced_cntr0 <= spc6_stb_ced_cntr0;
spc6_stb_ced0_d <= spc6_stb_ced0_d;
end
if( ( ~spc6_mbar_vld0 && (spc6_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_mbar_vld_cntr0 <= 9'h000;
spc6_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_mbar_vld_counter = %d", spc6_mbar_vld_cntr0);
end
else if( spc6_mbar_vld0)
begin
spc6_mbar_vld_cntr0 <= spc6_mbar_vld_cntr0 + 1;
spc6_mbar_vld_d0 <= spc6_mbar_vld0;
end
else
begin
spc6_mbar_vld_cntr0 <= spc6_mbar_vld_cntr0;
spc6_mbar_vld_d0 <= spc6_mbar_vld0;
end
if( ( ~spc6_flsh_vld0 && (spc6_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_flsh_vld_cntr0 <= 9'h000;
spc6_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_flsh_vld_counter = %d", spc6_flsh_vld_cntr0);
end
else if( spc6_flsh_vld0)
begin
spc6_flsh_vld_cntr0 <= spc6_flsh_vld_cntr0 + 1;
spc6_flsh_vld_d0 <= spc6_flsh_vld0;
end
else
begin
spc6_flsh_vld_cntr0 <= spc6_flsh_vld_cntr0;
spc6_flsh_vld_d0 <= spc6_flsh_vld0;
end
if( ( ~spc6_stb_ced1 && (spc6_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_stb_ced_cntr1 <= 9'h000;
spc6_stb_ced1_d <= 1'b0;
end
else if( spc6_stb_ced1 && (spc6_stb_state_ack1 == 8'h00))
begin
spc6_stb_ced_cntr1 <= spc6_stb_ced_cntr1 + 1;
spc6_stb_ced1_d <= spc6_stb_ced1;
end
else
begin
spc6_stb_ced_cntr1 <= spc6_stb_ced_cntr1;
spc6_stb_ced1_d <= spc6_stb_ced1_d;
end
if( ( ~spc6_mbar_vld1 && (spc6_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_mbar_vld_cntr1 <= 9'h000;
spc6_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_mbar_vld_counter = %d", spc6_mbar_vld_cntr1);
end
else if( spc6_mbar_vld1)
begin
spc6_mbar_vld_cntr1 <= spc6_mbar_vld_cntr1 + 1;
spc6_mbar_vld_d1 <= spc6_mbar_vld1;
end
else
begin
spc6_mbar_vld_cntr1 <= spc6_mbar_vld_cntr1;
spc6_mbar_vld_d1 <= spc6_mbar_vld1;
end
if( ( ~spc6_flsh_vld1 && (spc6_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_flsh_vld_cntr1 <= 9'h000;
spc6_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_flsh_vld_counter = %d", spc6_flsh_vld_cntr1);
end
else if( spc6_flsh_vld1)
begin
spc6_flsh_vld_cntr1 <= spc6_flsh_vld_cntr1 + 1;
spc6_flsh_vld_d1 <= spc6_flsh_vld1;
end
else
begin
spc6_flsh_vld_cntr1 <= spc6_flsh_vld_cntr1;
spc6_flsh_vld_d1 <= spc6_flsh_vld1;
end
if( ( ~spc6_stb_ced2 && (spc6_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_stb_ced_cntr2 <= 9'h000;
spc6_stb_ced2_d <= 1'b0;
end
else if( spc6_stb_ced2 && (spc6_stb_state_ack2 == 8'h00))
begin
spc6_stb_ced_cntr2 <= spc6_stb_ced_cntr2 + 1;
spc6_stb_ced2_d <= spc6_stb_ced2;
end
else
begin
spc6_stb_ced_cntr2 <= spc6_stb_ced_cntr2;
spc6_stb_ced2_d <= spc6_stb_ced2_d;
end
if( ( ~spc6_mbar_vld2 && (spc6_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_mbar_vld_cntr2 <= 9'h000;
spc6_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_mbar_vld_counter = %d", spc6_mbar_vld_cntr2);
end
else if( spc6_mbar_vld2)
begin
spc6_mbar_vld_cntr2 <= spc6_mbar_vld_cntr2 + 1;
spc6_mbar_vld_d2 <= spc6_mbar_vld2;
end
else
begin
spc6_mbar_vld_cntr2 <= spc6_mbar_vld_cntr2;
spc6_mbar_vld_d2 <= spc6_mbar_vld2;
end
if( ( ~spc6_flsh_vld2 && (spc6_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_flsh_vld_cntr2 <= 9'h000;
spc6_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_flsh_vld_counter = %d", spc6_flsh_vld_cntr2);
end
else if( spc6_flsh_vld2)
begin
spc6_flsh_vld_cntr2 <= spc6_flsh_vld_cntr2 + 1;
spc6_flsh_vld_d2 <= spc6_flsh_vld2;
end
else
begin
spc6_flsh_vld_cntr2 <= spc6_flsh_vld_cntr2;
spc6_flsh_vld_d2 <= spc6_flsh_vld2;
end
if( ( ~spc6_stb_ced3 && (spc6_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_stb_ced_cntr3 <= 9'h000;
spc6_stb_ced3_d <= 1'b0;
end
else if( spc6_stb_ced3 && (spc6_stb_state_ack3 == 8'h00))
begin
spc6_stb_ced_cntr3 <= spc6_stb_ced_cntr3 + 1;
spc6_stb_ced3_d <= spc6_stb_ced3;
end
else
begin
spc6_stb_ced_cntr3 <= spc6_stb_ced_cntr3;
spc6_stb_ced3_d <= spc6_stb_ced3_d;
end
if( ( ~spc6_mbar_vld3 && (spc6_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_mbar_vld_cntr3 <= 9'h000;
spc6_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_mbar_vld_counter = %d", spc6_mbar_vld_cntr3);
end
else if( spc6_mbar_vld3)
begin
spc6_mbar_vld_cntr3 <= spc6_mbar_vld_cntr3 + 1;
spc6_mbar_vld_d3 <= spc6_mbar_vld3;
end
else
begin
spc6_mbar_vld_cntr3 <= spc6_mbar_vld_cntr3;
spc6_mbar_vld_d3 <= spc6_mbar_vld3;
end
if( ( ~spc6_flsh_vld3 && (spc6_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_flsh_vld_cntr3 <= 9'h000;
spc6_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_flsh_vld_counter = %d", spc6_flsh_vld_cntr3);
end
else if( spc6_flsh_vld3)
begin
spc6_flsh_vld_cntr3 <= spc6_flsh_vld_cntr3 + 1;
spc6_flsh_vld_d3 <= spc6_flsh_vld3;
end
else
begin
spc6_flsh_vld_cntr3 <= spc6_flsh_vld_cntr3;
spc6_flsh_vld_d3 <= spc6_flsh_vld3;
end
end
always @(spc6_flsh_vld_d0 or spc6_flsh_vld0)
begin
if (spc6_flsh_vld_d0 && ~spc6_flsh_vld0)
spc6_flsh_vld_capture0 <= 1'b1;
else
spc6_flsh_vld_capture0 <= 1'b0;
end
always @(spc6_flsh_vld_d1 or spc6_flsh_vld1)
begin
if (spc6_flsh_vld_d1 && ~spc6_flsh_vld1)
spc6_flsh_vld_capture1 <= 1'b1;
else
spc6_flsh_vld_capture1 <= 1'b0;
end
always @(spc6_flsh_vld_d2 or spc6_flsh_vld2)
begin
if (spc6_flsh_vld_d2 && ~spc6_flsh_vld2)
spc6_flsh_vld_capture2 <= 1'b1;
else
spc6_flsh_vld_capture2 <= 1'b0;
end
always @(spc6_flsh_vld_d3 or spc6_flsh_vld3)
begin
if (spc6_flsh_vld_d3 && ~spc6_flsh_vld3)
spc6_flsh_vld_capture3 <= 1'b1;
else
spc6_flsh_vld_capture3 <= 1'b0;
end
always @(spc6_lmiss_pa0 or spc6_imiss_pa or spc6_imiss_vld_d or spc6_lmiss_vld0)
begin
if((spc6_lmiss_pa0 == spc6_imiss_pa) && spc6_imiss_vld_d && spc6_lmiss_vld0)
spc6_lmiss_eq0 = 1'b1;
else
spc6_lmiss_eq0 = 1'b0;
end
always @(spc6_lmiss_pa1 or spc6_imiss_pa or spc6_imiss_vld_d or spc6_lmiss_vld1)
begin
if((spc6_lmiss_pa1 == spc6_imiss_pa) && spc6_imiss_vld_d && spc6_lmiss_vld1)
spc6_lmiss_eq1 = 1'b1;
else
spc6_lmiss_eq1 = 1'b0;
end
always @(spc6_lmiss_pa2 or spc6_imiss_pa or spc6_imiss_vld_d or spc6_lmiss_vld2)
begin
if((spc6_lmiss_pa2 == spc6_imiss_pa) && spc6_imiss_vld_d && spc6_lmiss_vld2)
spc6_lmiss_eq2 = 1'b1;
else
spc6_lmiss_eq2 = 1'b0;
end
always @(spc6_lmiss_pa3 or spc6_imiss_pa or spc6_imiss_vld_d or spc6_lmiss_vld3)
begin
if((spc6_lmiss_pa3 == spc6_imiss_pa) && spc6_imiss_vld_d && spc6_lmiss_vld3)
spc6_lmiss_eq3 = 1'b1;
else
spc6_lmiss_eq3 = 1'b0;
end
always @(spc6_lmiss_pa0 or spc6_stb_atm_addr0 or spc6_atm_cntr0 or spc6_lmiss_vld0)
begin
if ( ((spc6_lmiss_pa0 == spc6_stb_atm_addr0) && (spc6_atm_cntr0 != 9'h000) && spc6_lmiss_vld0) ||
((spc6_lmiss_pa1 == spc6_stb_atm_addr0) && (spc6_atm_cntr0 != 9'h000) && spc6_lmiss_vld1) ||
((spc6_lmiss_pa2 == spc6_stb_atm_addr0) && (spc6_atm_cntr0 != 9'h000) && spc6_lmiss_vld2) ||
((spc6_lmiss_pa3 == spc6_stb_atm_addr0) && (spc6_atm_cntr0 != 9'h000) && spc6_lmiss_vld3) )
spc6_atm_lmiss_eq0 = 1'b1;
else
spc6_atm_lmiss_eq0 = 1'b0;
end
always @(spc6_lmiss_pa1 or spc6_stb_atm_addr1 or spc6_atm_cntr1 or spc6_lmiss_vld1)
begin
if ( ((spc6_lmiss_pa0 == spc6_stb_atm_addr1) && (spc6_atm_cntr1 != 9'h000) && spc6_lmiss_vld0) ||
((spc6_lmiss_pa1 == spc6_stb_atm_addr1) && (spc6_atm_cntr1 != 9'h000) && spc6_lmiss_vld1) ||
((spc6_lmiss_pa2 == spc6_stb_atm_addr1) && (spc6_atm_cntr1 != 9'h000) && spc6_lmiss_vld2) ||
((spc6_lmiss_pa3 == spc6_stb_atm_addr1) && (spc6_atm_cntr1 != 9'h000) && spc6_lmiss_vld3) )
spc6_atm_lmiss_eq1 = 1'b1;
else
spc6_atm_lmiss_eq1 = 1'b0;
end
always @(spc6_lmiss_pa2 or spc6_stb_atm_addr2 or spc6_atm_cntr2 or spc6_lmiss_vld2)
begin
if ( ((spc6_lmiss_pa0 == spc6_stb_atm_addr2) && (spc6_atm_cntr2 != 9'h000) && spc6_lmiss_vld0) ||
((spc6_lmiss_pa1 == spc6_stb_atm_addr2) && (spc6_atm_cntr2 != 9'h000) && spc6_lmiss_vld1) ||
((spc6_lmiss_pa2 == spc6_stb_atm_addr2) && (spc6_atm_cntr2 != 9'h000) && spc6_lmiss_vld2) ||
((spc6_lmiss_pa3 == spc6_stb_atm_addr2) && (spc6_atm_cntr2 != 9'h000) && spc6_lmiss_vld3) )
spc6_atm_lmiss_eq2 = 1'b1;
else
spc6_atm_lmiss_eq2 = 1'b0;
end
always @(spc6_lmiss_pa3 or spc6_stb_atm_addr3 or spc6_atm_cntr3 or spc6_lmiss_vld3)
begin
if ( ((spc6_lmiss_pa0 == spc6_stb_atm_addr3) && (spc6_atm_cntr3 != 9'h000) && spc6_lmiss_vld0) ||
((spc6_lmiss_pa1 == spc6_stb_atm_addr3) && (spc6_atm_cntr3 != 9'h000) && spc6_lmiss_vld1) ||
((spc6_lmiss_pa2 == spc6_stb_atm_addr3) && (spc6_atm_cntr3 != 9'h000) && spc6_lmiss_vld2) ||
((spc6_lmiss_pa3 == spc6_stb_atm_addr3) && (spc6_atm_cntr3 != 9'h000) && spc6_lmiss_vld3) )
spc6_atm_lmiss_eq3 = 1'b1;
else
spc6_atm_lmiss_eq3 = 1'b0;
end
always @(spc6_imiss_pa or spc6_stb_atm_addr0 or spc6_atm_cntr0 or spc6_imiss_vld_d)
begin
if((spc6_imiss_pa == spc6_stb_atm_addr0) && (spc6_atm_cntr0 != 9'h000) && spc6_imiss_vld_d)
spc6_atm_imiss_eq0 = 1'b1;
else
spc6_atm_imiss_eq0 = 1'b0;
end
always @(spc6_imiss_pa or spc6_stb_atm_addr1 or spc6_atm_cntr1 or spc6_imiss_vld_d)
begin
if((spc6_imiss_pa == spc6_stb_atm_addr1) && (spc6_atm_cntr1 != 9'h000) && spc6_imiss_vld_d)
spc6_atm_imiss_eq1 = 1'b1;
else
spc6_atm_imiss_eq1 = 1'b0;
end
always @(spc6_imiss_pa or spc6_stb_atm_addr2 or spc6_atm_cntr2 or spc6_imiss_vld_d)
begin
if((spc6_imiss_pa == spc6_stb_atm_addr2) && (spc6_atm_cntr2 != 9'h000) && spc6_imiss_vld_d)
spc6_atm_imiss_eq2 = 1'b1;
else
spc6_atm_imiss_eq2 = 1'b0;
end
always @(spc6_imiss_pa or spc6_stb_atm_addr3 or spc6_atm_cntr3 or spc6_imiss_vld_d)
begin
if((spc6_imiss_pa == spc6_stb_atm_addr3) && (spc6_atm_cntr3 != 9'h000) && spc6_imiss_vld_d)
spc6_atm_imiss_eq3 = 1'b1;
else
spc6_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc6_imiss_vld || ~rst_l)
spc6_imiss_vld_d <= 1'b0;
else
spc6_imiss_vld_d <= spc6_imiss_vld;
if( ~spc6_ld_miss || ~rst_l)
spc6_ld_miss_capture <= 1'b0;
else
spc6_ld_miss_capture <= spc6_ld_miss;
end
always @(spc6_stb_ced0 or spc6_stb_ced0_d)
begin
if (~spc6_stb_ced0 && spc6_stb_ced0_d)
spc6_stb_ced_capture0 <= 1'b1;
else
spc6_stb_ced_capture0 <= 1'b0;
end
always @(spc6_stb_ced1 or spc6_stb_ced1_d)
begin
if (~spc6_stb_ced1 && spc6_stb_ced1_d)
spc6_stb_ced_capture1 <= 1'b1;
else
spc6_stb_ced_capture1 <= 1'b0;
end
always @(spc6_stb_ced2 or spc6_stb_ced2_d)
begin
if (~spc6_stb_ced2 && spc6_stb_ced2_d)
spc6_stb_ced_capture2 <= 1'b1;
else
spc6_stb_ced_capture2 <= 1'b0;
end
always @(spc6_stb_ced3 or spc6_stb_ced3_d)
begin
if (~spc6_stb_ced3 && spc6_stb_ced3_d)
spc6_stb_ced_capture3 <= 1'b1;
else
spc6_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc6_stb_state_ack0 != 8'h00 && (spc6_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_ack_counter0 = %d", spc6_stb_ack_cntr0);
end
else if(spc6_stb_cam_hit && spc6_ld0_inst_vld_g && (spc6_stb_state_ack0 == 8'h00))
begin
spc6_stb_ack_cntr0 <= spc6_stb_ack_cntr0 + 1;
end
else if( (spc6_stb_state_ack0 == 8'h00 ) && (spc6_stb_ack_cntr0 != 9'h000))
begin
spc6_stb_ack_cntr0 <= spc6_stb_ack_cntr0 + 1;
end // if ( (spc6_stb_state_ack0 == 8'h00 ) && (spc6_stb_ack_cntr0 != 9'h000))
else
begin
spc6_stb_ack_cntr0 <= spc6_stb_ack_cntr0;
end
if( (spc6_stb_state_ack1 != 8'h00 && (spc6_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_ack_counter1 = %d", spc6_stb_ack_cntr1);
end
else if(spc6_stb_cam_hit && spc6_ld1_inst_vld_g && (spc6_stb_state_ack1 == 8'h00))
begin
spc6_stb_ack_cntr1 <= spc6_stb_ack_cntr1 + 1;
end
else if( (spc6_stb_state_ack1 == 8'h00 ) && (spc6_stb_ack_cntr1 != 9'h000))
begin
spc6_stb_ack_cntr1 <= spc6_stb_ack_cntr1 + 1;
end // if ( (spc6_stb_state_ack1 == 8'h00 ) && (spc6_stb_ack_cntr1 != 9'h000))
else
begin
spc6_stb_ack_cntr1 <= spc6_stb_ack_cntr1;
end
if( (spc6_stb_state_ack2 != 8'h00 && (spc6_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_ack_counter2 = %d", spc6_stb_ack_cntr2);
end
else if(spc6_stb_cam_hit && spc6_ld2_inst_vld_g && (spc6_stb_state_ack2 == 8'h00))
begin
spc6_stb_ack_cntr2 <= spc6_stb_ack_cntr2 + 1;
end
else if( (spc6_stb_state_ack2 == 8'h00 ) && (spc6_stb_ack_cntr2 != 9'h000))
begin
spc6_stb_ack_cntr2 <= spc6_stb_ack_cntr2 + 1;
end // if ( (spc6_stb_state_ack2 == 8'h00 ) && (spc6_stb_ack_cntr2 != 9'h000))
else
begin
spc6_stb_ack_cntr2 <= spc6_stb_ack_cntr2;
end
if( (spc6_stb_state_ack3 != 8'h00 && (spc6_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_ack_counter3 = %d", spc6_stb_ack_cntr3);
end
else if(spc6_stb_cam_hit && spc6_ld3_inst_vld_g && (spc6_stb_state_ack3 == 8'h00))
begin
spc6_stb_ack_cntr3 <= spc6_stb_ack_cntr3 + 1;
end
else if( (spc6_stb_state_ack3 == 8'h00 ) && (spc6_stb_ack_cntr3 != 9'h000))
begin
spc6_stb_ack_cntr3 <= spc6_stb_ack_cntr3 + 1;
end // if ( (spc6_stb_state_ack3 == 8'h00 ) && (spc6_stb_ack_cntr3 != 9'h000))
else
begin
spc6_stb_ack_cntr3 <= spc6_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc6_stb0_full_w2 or spc6_stb0_full)
begin
if (~spc6_stb0_full_w2 && spc6_stb0_full)
spc6_stb_full_capture0 <= 1'b1;
else
spc6_stb_full_capture0 <= 1'b0;
end
always @(spc6_stb1_full_w2 or spc6_stb1_full)
begin
if (~spc6_stb1_full_w2 && spc6_stb1_full)
spc6_stb_full_capture1 <= 1'b1;
else
spc6_stb_full_capture1 <= 1'b0;
end
always @(spc6_stb2_full_w2 or spc6_stb2_full)
begin
if (~spc6_stb2_full_w2 && spc6_stb2_full)
spc6_stb_full_capture2 <= 1'b1;
else
spc6_stb_full_capture2 <= 1'b0;
end
always @(spc6_stb3_full_w2 or spc6_stb3_full)
begin
if (~spc6_stb3_full_w2 && spc6_stb3_full)
spc6_stb_full_capture3 <= 1'b1;
else
spc6_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc6_stb0_full && (spc6_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_full_counter0 = %d", spc6_stb_full_cntr0);
end
else if( spc6_stb0_full)
begin
spc6_stb_full_cntr0 <= spc6_stb_full_cntr0 + 1;
end
else
begin
spc6_stb_full_cntr0 <= spc6_stb_full_cntr0;
end
if( ( ~spc6_stb1_full && (spc6_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_full_counter1 = %d", spc6_stb_full_cntr1);
end
else if( spc6_stb1_full)
begin
spc6_stb_full_cntr1 <= spc6_stb_full_cntr1 + 1;
end
else
begin
spc6_stb_full_cntr1 <= spc6_stb_full_cntr1;
end
if( ( ~spc6_stb2_full && (spc6_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_full_counter2 = %d", spc6_stb_full_cntr2);
end
else if( spc6_stb2_full)
begin
spc6_stb_full_cntr2 <= spc6_stb_full_cntr2 + 1;
end
else
begin
spc6_stb_full_cntr2 <= spc6_stb_full_cntr2;
end
if( ( ~spc6_stb3_full && (spc6_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc6_stb_full_counter3 = %d", spc6_stb_full_cntr3);
end
else if( spc6_stb3_full)
begin
spc6_stb_full_cntr3 <= spc6_stb_full_cntr3 + 1;
end
else
begin
spc6_stb_full_cntr3 <= spc6_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc6_lmq0_full_d or spc6_lmq0_full)
begin
if (spc6_lmq0_full_d && ~spc6_lmq0_full)
spc6_lmq_full_capture0 <= 1'b1;
else
spc6_lmq_full_capture0 <= 1'b0;
end
always @(spc6_lmq1_full_d or spc6_lmq1_full)
begin
if (spc6_lmq1_full_d && ~spc6_lmq1_full)
spc6_lmq_full_capture1 <= 1'b1;
else
spc6_lmq_full_capture1 <= 1'b0;
end
always @(spc6_lmq2_full_d or spc6_lmq2_full)
begin
if (spc6_lmq2_full_d && ~spc6_lmq2_full)
spc6_lmq_full_capture2 <= 1'b1;
else
spc6_lmq_full_capture2 <= 1'b0;
end
always @(spc6_lmq3_full_d or spc6_lmq3_full)
begin
if (spc6_lmq3_full_d && ~spc6_lmq3_full)
spc6_lmq_full_capture3 <= 1'b1;
else
spc6_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc6_lmq0_full && (spc6_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc6_lmq_full_cntr0 <= 9'h000;
spc6_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_lmq_full_counter0 = %d", spc6_lmq_full_cntr0);
end
else if( spc6_lmq0_full)
begin
spc6_lmq_full_cntr0 <= spc6_lmq_full_cntr0 + 1;
spc6_lmq0_full_d <= spc6_lmq0_full;
end
else
begin
spc6_lmq_full_cntr0 <= spc6_lmq_full_cntr0;
spc6_lmq0_full_d <= spc6_lmq0_full;
end
if( ( ~spc6_lmq1_full && (spc6_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc6_lmq_full_cntr1 <= 9'h000;
spc6_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_lmq_full_counter1 = %d", spc6_lmq_full_cntr1);
end
else if( spc6_lmq1_full)
begin
spc6_lmq_full_cntr1 <= spc6_lmq_full_cntr1 + 1;
spc6_lmq1_full_d <= spc6_lmq1_full;
end
else
begin
spc6_lmq_full_cntr1 <= spc6_lmq_full_cntr1;
spc6_lmq1_full_d <= spc6_lmq1_full;
end
if( ( ~spc6_lmq2_full && (spc6_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc6_lmq_full_cntr2 <= 9'h000;
spc6_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_lmq_full_counter2 = %d", spc6_lmq_full_cntr2);
end
else if( spc6_lmq2_full)
begin
spc6_lmq_full_cntr2 <= spc6_lmq_full_cntr2 + 1;
spc6_lmq2_full_d <= spc6_lmq2_full;
end
else
begin
spc6_lmq_full_cntr2 <= spc6_lmq_full_cntr2;
spc6_lmq2_full_d <= spc6_lmq2_full;
end
if( ( ~spc6_lmq3_full && (spc6_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc6_lmq_full_cntr3 <= 9'h000;
spc6_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_lmq_full_counter3 = %d", spc6_lmq_full_cntr3);
end
else if( spc6_lmq3_full)
begin
spc6_lmq_full_cntr3 <= spc6_lmq_full_cntr3 + 1;
spc6_lmq3_full_d <= spc6_lmq3_full;
end
else
begin
spc6_lmq_full_cntr3 <= spc6_lmq_full_cntr3;
spc6_lmq3_full_d <= spc6_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc6_dfq_full_d or spc6_dfq_full)
begin
if (spc6_dfq_full_d && ~spc6_dfq_full)
spc6_dfq_full_capture <= 1'b1;
else
spc6_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc6_dfq_full && (spc6_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc6_dfq_full_cntr <= 9'h000;
spc6_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dfq_full_counter = %d", spc6_dfq_full_cntr);
end
else if( spc6_dfq_full)
begin
spc6_dfq_full_cntr <= spc6_dfq_full_cntr + 1;
spc6_dfq_full_d <= spc6_dfq_full;
end
else
begin
spc6_dfq_full_cntr <= spc6_dfq_full_cntr;
spc6_dfq_full_d <= spc6_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc6_dva_full_d or spc6_dva_inv)
begin
if (spc6_dva_full_d && ~spc6_dva_inv)
spc6_dva_full_capture <= 1'b1;
else
spc6_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc6_dva_din && spc6_dva_wen)
begin
spc6_dva_inv <= 1'b1;
spc6_dva_waddr_d <= spc6_dva_waddr;
end
else if(~spc6_dva_din && spc6_dva_wen)
begin
spc6_dva_inv <= 1'b0;
spc6_dva_waddr_d <= 5'b00000;
end
else
begin
spc6_dva_inv <= spc6_dva_inv;
spc6_dva_waddr_d <= spc6_dva_waddr_d;
end
end
always @(spc6_dva_raddr or spc6_dva_ren or spc6_dva_inv)
begin
if (spc6_dva_inv && spc6_dva_ren && (spc6_dva_raddr[6:2] == spc6_dva_waddr_d))
spc6_dva_vld2lkup <= 1'b1;
else
spc6_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc6_dva_inv && (spc6_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc6_dva_full_cntr <= 9'h000;
spc6_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dva_full_counter = %d", spc6_dva_full_cntr);
end
else if( spc6_dva_inv)
begin
spc6_dva_full_cntr <= spc6_dva_full_cntr + 1;
spc6_dva_full_d <= spc6_dva_inv;
end
else
begin
spc6_dva_full_cntr <= spc6_dva_full_cntr;
spc6_dva_full_d <= spc6_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc6_dva_vfull_d or spc6_dva_vld)
begin
if (spc6_dva_vfull_d && ~spc6_dva_vld)
spc6_dva_vfull_capture <= 1'b1;
else
spc6_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc6_dva_din && spc6_dva_wen)
begin
spc6_dva_vld <= 1'b1;
spc6_dva_invwaddr_d <= spc6_dva_waddr;
spc6_dva_invld_err <= spc6_dva_inv_perror;
end
else if(spc6_dva_din && spc6_dva_wen)
begin
spc6_dva_vld <= 1'b0;
spc6_dva_invwaddr_d <= 5'b00000;
spc6_dva_invld_err <= 1'b0;
end
else
begin
spc6_dva_vld <= spc6_dva_vld;
spc6_dva_invwaddr_d <= spc6_dva_invwaddr_d;
spc6_dva_invld_err <= spc6_dva_invld_err;
end
end
always @(spc6_dva_raddr or spc6_dva_ren or spc6_dva_vld)
begin
if (spc6_dva_vld && spc6_dva_ren && (spc6_dva_raddr[6:2] == spc6_dva_waddr_d))
spc6_dva_invld2lkup <= 1'b1;
else
spc6_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc6_dva_vld && (spc6_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc6_dva_vfull_cntr <= 9'h000;
spc6_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc6_dva_vfull_counter = %d", spc6_dva_vfull_cntr);
end
else if( spc6_dva_vld)
begin
spc6_dva_vfull_cntr <= spc6_dva_vfull_cntr + 1;
spc6_dva_vfull_d <= spc6_dva_vld;
end
else
begin
spc6_dva_vfull_cntr <= spc6_dva_vfull_cntr;
spc6_dva_vfull_d <= spc6_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc6_dva_raddr or spc6_dva_waddr or spc6_dva_ren or spc6_dva_wen)
begin
if ( spc6_dva_ren && spc6_dva_wen && (spc6_dva_raddr[6:2] == spc6_dva_waddr))
spc6_dva_collide <= 1'b1;
else
spc6_dva_collide <= 1'b0;
end
// dva error cases
always @(spc6_dva_raddr or spc6_dva_ren or spc6_dva_dtag_perror or spc6_dva_dtag_perror)
begin
if (spc6_dva_ren && (spc6_dva_dtag_perror || spc6_dva_dtag_perror))
spc6_dva_err <= 1'b1;
else
spc6_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc6_dva_err)
spc6_dva_efull_d <= 1'b1;
else
spc6_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc6_dva_ren && ~(spc6_dva_dtag_perror || spc6_dva_dtag_perror ) &&
(spc6_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc6_dva_efull_cntr <= 9'h000;
spc6_dva_raddr_d <= spc6_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc6_dva_efull_counter = %d", spc6_dva_efull_cntr);
end
else if(spc6_dva_efull_d)
begin
spc6_dva_efull_cntr <= spc6_dva_efull_cntr + 1;
spc6_dva_raddr_d <= spc6_dva_raddr_d;
end
else
begin
spc6_dva_efull_cntr <= spc6_dva_efull_cntr;
spc6_dva_raddr_d <= spc6_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
//============================================================================================
`ifdef RTL_SPARC7
wire spc7_dva_ren = `TOP_DESIGN.sparc7.lsu.ifu_lsu_ld_inst_e;
wire spc7_dva_wen = `TOP_DESIGN.sparc7.lsu.lsu_dtagv_wr_vld_e;
wire spc7_dva_din = `TOP_DESIGN.sparc7.lsu.dva_din_e;
wire [3:0] spc7_dva_dout = `TOP_DESIGN.sparc7.lsu.dva_vld_m[3:0];
wire [6:0] spc7_dva_raddr = `TOP_DESIGN.sparc7.lsu.exu_lsu_early_va_e[10:4];
wire [4:0] spc7_dva_waddr = `TOP_DESIGN.sparc7.lsu.dva_wr_adr_e[10:6];
wire spc7_dva_dtag_perror = `TOP_DESIGN.sparc7.lsu.lsu_cpx_ld_dtag_perror_e;
wire spc7_dva_dcache_perror = `TOP_DESIGN.sparc7.lsu.lsu_cpx_ld_dcache_perror_e;
wire spc7_dva_inv_perror = `TOP_DESIGN.sparc7.lsu.qctl2.lsu_cpx_pkt_perror_dinv;
wire spc7_ld_miss = `TOP_DESIGN.sparc7.lsu.dctl.lsu_ld_miss_wb;
reg spc7_ld_miss_capture;
wire spc7_atomic_g = `TOP_DESIGN.sparc7.lsu.qctl1.atomic_g;
wire [1:0] spc7_atm_type0 = `TOP_DESIGN.sparc7.lsu.qctl1.stb0_atm_rq_type[2:1];
wire [1:0] spc7_atm_type1 = `TOP_DESIGN.sparc7.lsu.qctl1.stb1_atm_rq_type[2:1];
wire [1:0] spc7_atm_type2 = `TOP_DESIGN.sparc7.lsu.qctl1.stb2_atm_rq_type[2:1];
wire [1:0] spc7_atm_type3 = `TOP_DESIGN.sparc7.lsu.qctl1.stb3_atm_rq_type[2:1];
wire [3:0] spc7_dctl_lsu_way_hit = `TOP_DESIGN.sparc7.lsu.dctl.lsu_way_hit;
wire spc7_dctl_dcache_enable_g = `TOP_DESIGN.sparc7.lsu.dctl.dcache_enable_g;
wire spc7_dctl_ldxa_internal = `TOP_DESIGN.sparc7.lsu.dctl.ldxa_internal;
wire spc7_dctl_ldst_dbl_g = `TOP_DESIGN.sparc7.lsu.dctl.ldst_dbl_g;
wire spc7_dctl_atomic_g = `TOP_DESIGN.sparc7.lsu.dctl.atomic_g;
wire spc7_dctl_stb_cam_hit = `TOP_DESIGN.sparc7.lsu.dctl.stb_cam_hit;
wire spc7_dctl_endian_mispred_g = `TOP_DESIGN.sparc7.lsu.dctl.endian_mispred_g;
wire spc7_dctl_dcache_rd_parity_error = `TOP_DESIGN.sparc7.lsu.dctl.dcache_rd_parity_error;
wire spc7_dctl_dtag_perror_g = `TOP_DESIGN.sparc7.lsu.dctl.dtag_perror_g;
wire spc7_dctl_tte_data_perror_unc = `TOP_DESIGN.sparc7.lsu.dctl.tte_data_perror_unc;
wire spc7_dctl_ld_inst_vld_g = `TOP_DESIGN.sparc7.lsu.dctl.ld_inst_vld_g;
wire spc7_dctl_lsu_alt_space_g = `TOP_DESIGN.sparc7.lsu.dctl.lsu_alt_space_g;
wire spc7_dctl_recognized_asi_g = `TOP_DESIGN.sparc7.lsu.dctl.recognized_asi_g;
wire spc7_dctl_ncache_asild_rq_g = `TOP_DESIGN.sparc7.lsu.dctl.ncache_asild_rq_g ;
wire spc7_dctl_bld_hit;
wire spc7_dctl_bld_stb_hit;
// interfaces
// ifu
wire spc7_ixinv0 = `TOP_DESIGN.sparc7.lsu.qctl2.imiss0_inv_en;
wire spc7_ixinv1 = `TOP_DESIGN.sparc7.lsu.qctl2.imiss1_inv_en;
wire spc7_ixinv2 = `TOP_DESIGN.sparc7.lsu.qctl2.imiss2_inv_en;
wire spc7_ixinv3 = `TOP_DESIGN.sparc7.lsu.qctl2.imiss3_inv_en;
wire spc7_ifill = `TOP_DESIGN.sparc7.lsu.qctl2.lsu_ifill_pkt_vld ;
wire spc7_inv = `TOP_DESIGN.sparc7.lsu.qctl2.lsu_cpx_spc_inv_vld ;
wire spc7_inv_clr = `TOP_DESIGN.sparc7.lsu.qctl2.ifu_lsu_inv_clear;
wire spc7_ibuf_busy = `TOP_DESIGN.sparc7.lsu.qctl2.ifu_lsu_ibuf_busy;
//exu
wire spc7_l2 = `TOP_DESIGN.sparc7.lsu.dctl.l2fill_vld_g ;
wire spc7_unc = `TOP_DESIGN.sparc7.lsu.dctl.unc_err_trap_g ;
wire spc7_fpld = `TOP_DESIGN.sparc7.lsu.dctl.l2fill_fpld_g ;
wire spc7_fpldst = `TOP_DESIGN.sparc7.lsu.dctl.fp_ldst_g ;
wire spc7_unflush = `TOP_DESIGN.sparc7.lsu.dctl.ld_inst_vld_unflushed ;
wire spc7_ldw = `TOP_DESIGN.sparc7.lsu.dctl.lsu_inst_vld_w ;
wire spc7_byp = `TOP_DESIGN.sparc7.lsu.dctl.intld_byp_data_vld_m ;
wire spc7_flsh = `TOP_DESIGN.sparc7.lsu.lsu_exu_flush_pipe_w ;
wire spc7_chm = `TOP_DESIGN.sparc7.lsu.dctl.common_ldst_miss_w ;
wire spc7_ldxa = `TOP_DESIGN.sparc7.lsu.dctl.ldxa_internal ;
wire spc7_ato = `TOP_DESIGN.sparc7.lsu.dctl.atomic_g ;
wire spc7_pref = `TOP_DESIGN.sparc7.lsu.dctl.pref_inst_g ;
wire spc7_chit = `TOP_DESIGN.sparc7.lsu.dctl.stb_cam_hit ;
wire spc7_dcp = `TOP_DESIGN.sparc7.lsu.dctl.dcache_rd_parity_error ;
wire spc7_dtp = `TOP_DESIGN.sparc7.lsu.dctl.dtag_perror_g ;
//wire spc7_mpc = `TOP_DESIGN.sparc7.lsu.dctl.tte_data_perror_corr_en ;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
wire spc7_mpc = 1'b0;
wire spc7_mpu = `TOP_DESIGN.sparc7.lsu.dctl.tte_data_perror_unc_en ;
wire [17:0] spc7_exu_und;
reg [4:0] spc7_exu;
// excptn
wire spc7_exp_wtchpt_trp_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_wtchpt_trp_g ;
wire spc7_exp_misalign_addr_ldst_atm_m = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_misalign_addr_ldst_atm_m ;
wire spc7_exp_priv_violtn_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_priv_violtn_g;
wire spc7_exp_daccess_excptn_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_daccess_excptn_g;
wire spc7_exp_daccess_prot_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_daccess_prot_g;
wire spc7_exp_priv_action_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_priv_action_g;
wire spc7_exp_spec_access_epage_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_spec_access_epage_g;
wire spc7_exp_uncache_atomic_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_uncache_atomic_g;
wire spc7_exp_illegal_asi_action_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_illegal_asi_action_g;
wire spc7_exp_flt_ld_nfo_pg_g = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_flt_ld_nfo_pg_g;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc7_exp_asi_rd_unc = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_tlu_asi_rd_unc;
// wire spc7_exp_tlb_data_ce = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_ifu_tlb_data_ce ;
wire spc7_exp_asi_rd_unc = 1'b0;
wire spc7_exp_tlb_data_ce = 1'b0;
wire spc7_exp_tlb_data_ue = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_ifu_tlb_data_ue ;
wire spc7_exp_tlb_tag_ue = `TOP_DESIGN.sparc7.lsu.excpctl.lsu_ifu_tlb_tag_ue ;
wire spc7_exp_unc = `TOP_DESIGN.sparc7.lsu.excpctl.tte_data_perror_unc;
// Combine sanjay's change in lsu_mon.v hack 1.21 to 1.24
// wire spc7_exp_corr = `TOP_DESIGN.sparc7.lsu.excpctl.tte_data_perror_corr;
wire spc7_exp_corr = 1'b0;
wire [15:0] spc7_exp_und;
reg [4:0] spc7_exp;
// dctl cmplt
wire spc7_dctl_stxa_internal_d2 = `TOP_DESIGN.sparc7.lsu.dctl.stxa_internal_d2;
wire spc7_dctl_lsu_l2fill_vld = `TOP_DESIGN.sparc7.lsu.dctl.lsu_l2fill_vld;
wire spc7_dctl_atomic_ld_squash_e = `TOP_DESIGN.sparc7.lsu.dctl.atomic_ld_squash_e;
wire spc7_dctl_lsu_ignore_fill = `TOP_DESIGN.sparc7.lsu.qctl2.lsu_ignore_fill;
wire spc7_dctl_l2fill_fpld_e = `TOP_DESIGN.sparc7.lsu.dctl.l2fill_fpld_e;
// wire spc7_dctl_lsu_atm_st_cmplt_e = `TOP_DESIGN.sparc7.lsu.dctl.lsu_atm_st_cmplt_e;
wire spc7_dctl_fill_err_trap_e = `TOP_DESIGN.sparc7.lsu.dctl.fill_err_trap_e;
wire spc7_dctl_l2_corr_error_e = `TOP_DESIGN.sparc7.lsu.dctl.l2_corr_error_e;
wire [3:0] spc7_dctl_intld_byp_cmplt = `TOP_DESIGN.sparc7.lsu.dctl.intld_byp_cmplt;
wire [3:0] spc7_dctl_lsu_intrpt_cmplt = `TOP_DESIGN.sparc7.lsu.dctl.lsu_intrpt_cmplt;
wire [3:0] spc7_dctl_ldxa_illgl_va_cmplt_d1 = `TOP_DESIGN.sparc7.lsu.dctl.ldxa_illgl_va_cmplt_d1;
wire [3:0] spc7_dctl_pref_tlbmiss_cmplt_d2 = `TOP_DESIGN.sparc7.lsu.dctl.pref_tlbmiss_cmplt_d2;
wire [3:0] spc7_dctl_lsu_pcx_pref_issue = `TOP_DESIGN.sparc7.lsu.dctl.lsu_pcx_pref_issue;
wire [3:0] spc7_dctl_lsu_ifu_ldst_cmplt = `TOP_DESIGN.sparc7.lsu.dctl.lsu_ifu_ldst_cmplt;
reg [3:0] spc7_dctl_lsu_ifu_ldst_cmplt_d;
reg [3:0] spc7_ldstcond_cmplt_d;
wire spc7_qctl1_ld_sec_hit_thrd0 = `TOP_DESIGN.sparc7.lsu.qctl1.ld_sec_hit_thrd0;
wire spc7_qctl1_ld0_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_inst_vld_g;
wire spc7_ld0_pkt_vld_unmasked = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_pkt_vld_unmasked;
reg spc7_ld0_pkt_vld_unmasked_d;
reg spc7_qctl1_ld_sec_hit_thrd0_w2;
wire spc7_dctl_thread0_w3 = `TOP_DESIGN.sparc7.lsu.dctl.thread0_w3;
wire spc7_dctl_dfill_thread0 = `TOP_DESIGN.sparc7.lsu.dctl.dfill_thread0;
wire spc7_dctl_stxa_stall_wr_cmplt0_d1 = `TOP_DESIGN.sparc7.lsu.dctl.stxa_stall_wr_cmplt0_d1;
wire spc7_dctl_diag_wr_cmplt0 = `TOP_DESIGN.sparc7.lsu.dctl.diag_wr_cmplt0;
wire spc7_dctl_bsync0_reset = `TOP_DESIGN.sparc7.lsu.dctl.bsync0_reset;
wire spc7_dctl_late_cmplt0 = `TOP_DESIGN.sparc7.lsu.dctl.ldst_cmplt_late_0_d1;
wire spc7_dctl_stxa_cmplt0;
wire spc7_dctl_l2fill_cmplt0;
wire spc7_dctl_atm_cmplt0;
wire spc7_dctl_fillerr0;
wire [4:0] spc7_cmplt0;
wire [5:0] spc7_dctl_ldst_cond_cmplt0;
reg [3:0] spc7_ldstcond_cmplt0;
reg [3:0] spc7_ldstcond_cmplt0_d;
wire spc7_qctl1_ld_sec_hit_thrd1 = `TOP_DESIGN.sparc7.lsu.qctl1.ld_sec_hit_thrd1;
wire spc7_qctl1_ld1_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_inst_vld_g;
wire spc7_ld1_pkt_vld_unmasked = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_pkt_vld_unmasked;
reg spc7_ld1_pkt_vld_unmasked_d;
reg spc7_qctl1_ld_sec_hit_thrd1_w2;
wire spc7_dctl_thread1_w3 = `TOP_DESIGN.sparc7.lsu.dctl.thread1_w3;
wire spc7_dctl_dfill_thread1 = `TOP_DESIGN.sparc7.lsu.dctl.dfill_thread1;
wire spc7_dctl_stxa_stall_wr_cmplt1_d1 = `TOP_DESIGN.sparc7.lsu.dctl.stxa_stall_wr_cmplt1_d1;
wire spc7_dctl_diag_wr_cmplt1 = `TOP_DESIGN.sparc7.lsu.dctl.diag_wr_cmplt1;
wire spc7_dctl_bsync1_reset = `TOP_DESIGN.sparc7.lsu.dctl.bsync1_reset;
wire spc7_dctl_late_cmplt1 = `TOP_DESIGN.sparc7.lsu.dctl.ldst_cmplt_late_1_d1;
wire spc7_dctl_stxa_cmplt1;
wire spc7_dctl_l2fill_cmplt1;
wire spc7_dctl_atm_cmplt1;
wire spc7_dctl_fillerr1;
wire [4:0] spc7_cmplt1;
wire [5:0] spc7_dctl_ldst_cond_cmplt1;
reg [3:0] spc7_ldstcond_cmplt1;
reg [3:0] spc7_ldstcond_cmplt1_d;
wire spc7_qctl1_ld_sec_hit_thrd2 = `TOP_DESIGN.sparc7.lsu.qctl1.ld_sec_hit_thrd2;
wire spc7_qctl1_ld2_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_inst_vld_g;
wire spc7_ld2_pkt_vld_unmasked = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_pkt_vld_unmasked;
reg spc7_ld2_pkt_vld_unmasked_d;
reg spc7_qctl1_ld_sec_hit_thrd2_w2;
wire spc7_dctl_thread2_w3 = `TOP_DESIGN.sparc7.lsu.dctl.thread2_w3;
wire spc7_dctl_dfill_thread2 = `TOP_DESIGN.sparc7.lsu.dctl.dfill_thread2;
wire spc7_dctl_stxa_stall_wr_cmplt2_d1 = `TOP_DESIGN.sparc7.lsu.dctl.stxa_stall_wr_cmplt2_d1;
wire spc7_dctl_diag_wr_cmplt2 = `TOP_DESIGN.sparc7.lsu.dctl.diag_wr_cmplt2;
wire spc7_dctl_bsync2_reset = `TOP_DESIGN.sparc7.lsu.dctl.bsync2_reset;
wire spc7_dctl_late_cmplt2 = `TOP_DESIGN.sparc7.lsu.dctl.ldst_cmplt_late_2_d1;
wire spc7_dctl_stxa_cmplt2;
wire spc7_dctl_l2fill_cmplt2;
wire spc7_dctl_atm_cmplt2;
wire spc7_dctl_fillerr2;
wire [4:0] spc7_cmplt2;
wire [5:0] spc7_dctl_ldst_cond_cmplt2;
reg [3:0] spc7_ldstcond_cmplt2;
reg [3:0] spc7_ldstcond_cmplt2_d;
wire spc7_qctl1_ld_sec_hit_thrd3 = `TOP_DESIGN.sparc7.lsu.qctl1.ld_sec_hit_thrd3;
wire spc7_qctl1_ld3_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_inst_vld_g;
wire spc7_ld3_pkt_vld_unmasked = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_pkt_vld_unmasked;
reg spc7_ld3_pkt_vld_unmasked_d;
reg spc7_qctl1_ld_sec_hit_thrd3_w2;
wire spc7_dctl_thread3_w3 = `TOP_DESIGN.sparc7.lsu.dctl.thread3_w3;
wire spc7_dctl_dfill_thread3 = `TOP_DESIGN.sparc7.lsu.dctl.dfill_thread3;
wire spc7_dctl_stxa_stall_wr_cmplt3_d1 = `TOP_DESIGN.sparc7.lsu.dctl.stxa_stall_wr_cmplt3_d1;
wire spc7_dctl_diag_wr_cmplt3 = `TOP_DESIGN.sparc7.lsu.dctl.diag_wr_cmplt3;
wire spc7_dctl_bsync3_reset = `TOP_DESIGN.sparc7.lsu.dctl.bsync3_reset;
wire spc7_dctl_late_cmplt3 = `TOP_DESIGN.sparc7.lsu.dctl.ldst_cmplt_late_3_d1;
wire spc7_dctl_stxa_cmplt3;
wire spc7_dctl_l2fill_cmplt3;
wire spc7_dctl_atm_cmplt3;
wire spc7_dctl_fillerr3;
wire [4:0] spc7_cmplt3;
wire [5:0] spc7_dctl_ldst_cond_cmplt3;
reg [3:0] spc7_ldstcond_cmplt3;
reg [3:0] spc7_ldstcond_cmplt3_d;
wire spc7_qctl1_bld_g = `TOP_DESIGN.sparc7.lsu.qctl1.bld_g;
wire spc7_qctl1_bld_reset = `TOP_DESIGN.sparc7.lsu.qctl1.bld_reset;
wire [1:0] spc7_qctl1_bld_cnt = `TOP_DESIGN.sparc7.lsu.qctl1.bld_cnt;
reg [9:0] spc7_bld0_full_cntr;
reg [1:0] spc7_bld0_full_d;
reg spc7_bld0_full_capture;
reg [9:0] spc7_bld1_full_cntr;
reg [1:0] spc7_bld1_full_d;
reg spc7_bld1_full_capture;
reg [9:0] spc7_bld2_full_cntr;
reg [1:0] spc7_bld2_full_d;
reg spc7_bld2_full_capture;
reg [9:0] spc7_bld3_full_cntr;
reg [1:0] spc7_bld3_full_d;
reg spc7_bld3_full_capture;
wire spc7_ipick = `TOP_DESIGN.sparc7.lsu.qctl1.imiss_pcx_rq_vld;
wire spc7_lpick = `TOP_DESIGN.sparc7.lsu.qctl1.ld_pcx_rq_all;
wire spc7_spick = `TOP_DESIGN.sparc7.lsu.qctl1.st_pcx_rq_all;
wire spc7_mpick = `TOP_DESIGN.sparc7.lsu.qctl1.misc_pcx_rq_all;
wire [3:0] spc7_apick = `TOP_DESIGN.sparc7.lsu.qctl1.all_pcx_rq_pick;
wire spc7_msquash = `TOP_DESIGN.sparc7.lsu.qctl1.mcycle_squash_d1;
reg spc7_fpicko;
wire [3:0] spc7_fpick;
wire [39:0] spc7_imiss_pa = `TOP_DESIGN.sparc7.lsu.ifu_lsu_pcxpkt_e[39:0];
wire spc7_imiss_vld = `TOP_DESIGN.sparc7.lsu.qctl1.imiss_pcx_rq_vld;
reg spc7_imiss_vld_d;
wire [39:0] spc7_lmiss_pa0 = `TOP_DESIGN.sparc7.lsu.qdp1.lmq0_pcx_pkt[39:0];
wire spc7_lmiss_vld0 = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_pcx_rq_vld;
wire spc7_ld_pkt_vld0 = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_pkt_vld;
wire spc7_st_pkt_vld0 = `TOP_DESIGN.sparc7.lsu.qctl1.st0_pkt_vld;
reg spc7_lmiss_eq0;
reg spc7_atm_imiss_eq0;
wire [39:0] spc7_lmiss_pa1 = `TOP_DESIGN.sparc7.lsu.qdp1.lmq1_pcx_pkt[39:0];
wire spc7_lmiss_vld1 = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_pcx_rq_vld;
wire spc7_ld_pkt_vld1 = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_pkt_vld;
wire spc7_st_pkt_vld1 = `TOP_DESIGN.sparc7.lsu.qctl1.st1_pkt_vld;
reg spc7_lmiss_eq1;
reg spc7_atm_imiss_eq1;
wire [39:0] spc7_lmiss_pa2 = `TOP_DESIGN.sparc7.lsu.qdp1.lmq2_pcx_pkt[39:0];
wire spc7_lmiss_vld2 = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_pcx_rq_vld;
wire spc7_ld_pkt_vld2 = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_pkt_vld;
wire spc7_st_pkt_vld2 = `TOP_DESIGN.sparc7.lsu.qctl1.st2_pkt_vld;
reg spc7_lmiss_eq2;
reg spc7_atm_imiss_eq2;
wire [39:0] spc7_lmiss_pa3 = `TOP_DESIGN.sparc7.lsu.qdp1.lmq3_pcx_pkt[39:0];
wire spc7_lmiss_vld3 = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_pcx_rq_vld;
wire spc7_ld_pkt_vld3 = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_pkt_vld;
wire spc7_st_pkt_vld3 = `TOP_DESIGN.sparc7.lsu.qctl1.st3_pkt_vld;
reg spc7_lmiss_eq3;
reg spc7_atm_imiss_eq3;
wire [44:0] spc7_wdata_ramc = `TOP_DESIGN.sparc7.lsu.stb_cam.wdata_ramc;
wire spc7_wptr_vld = `TOP_DESIGN.sparc7.lsu.stb_cam.wptr_vld;
wire [75:0] spc7_wdata_ramd = {`TOP_DESIGN.sparc7.lsu.stb_wdata_ramd_b75_b64[75:64],`TOP_DESIGN.sparc7.lsu.lsu_stb_st_data_g[63:0]};
wire spc7_stb_cam_hit = `TOP_DESIGN.sparc7.lsu.stb_rwctl.stb_cam_hit;
wire [2:0] spc7_stb_cam_hit_ptr = `TOP_DESIGN.sparc7.lsu.stb_rwctl.stb_cam_hit_ptr;
wire [7:0] spc7_stb_ld_full_raw = `TOP_DESIGN.sparc7.lsu.stb_ld_full_raw[7:0];
wire [7:0] spc7_stb_ld_partial_raw = `TOP_DESIGN.sparc7.lsu.stb_ld_partial_raw[7:0];
wire spc7_stb_cam_mhit = `TOP_DESIGN.sparc7.lsu.stb_cam_mhit;
wire [3:0] spc7_dfq_vld_entries = `TOP_DESIGN.sparc7.lsu.qctl2.dfq_vld_entries;
wire spc7_dfq_full;
reg [9:0] spc7_dfq_full_cntr;
reg spc7_dfq_full_d;
reg spc7_dfq_full_capture;
reg [9:0] spc7_dfq_full_cntr1;
reg spc7_dfq_full_d1;
wire spc7_dfq_full1;
reg spc7_dfq_full_capture1;
reg [9:0] spc7_dfq_full_cntr2;
reg spc7_dfq_full_d2;
wire spc7_dfq_full2;
reg spc7_dfq_full_capture2;
reg [9:0] spc7_dfq_full_cntr3;
reg spc7_dfq_full_d3;
wire spc7_dfq_full3;
reg spc7_dfq_full_capture3;
reg [9:0] spc7_dfq_full_cntr4;
reg spc7_dfq_full_d4;
wire spc7_dfq_full4;
reg spc7_dfq_full_capture4;
reg [9:0] spc7_dfq_full_cntr5;
reg spc7_dfq_full_d5;
wire spc7_dfq_full5;
reg spc7_dfq_full_capture5;
reg [9:0] spc7_dfq_full_cntr6;
reg spc7_dfq_full_d6;
wire spc7_dfq_full6;
reg spc7_dfq_full_capture6;
reg [9:0] spc7_dfq_full_cntr7;
reg spc7_dfq_full_d7;
wire spc7_dfq_full7;
reg spc7_dfq_full_capture7;
wire spc7_dva_rdwrhit;
reg [9:0] spc7_dva_full_cntr;
reg spc7_dva_full_d;
reg spc7_dva_full_capture;
reg spc7_dva_inv;
reg spc7_dva_inv_d;
reg spc7_dva_vld;
reg spc7_dva_vld_d;
reg [9:0] spc7_dva_vfull_cntr;
reg spc7_dva_vfull_d;
reg spc7_dva_vfull_capture;
reg spc7_dva_collide;
reg spc7_dva_vld2lkup;
reg spc7_dva_invld2lkup;
reg spc7_dva_invld_err;
reg [9:0] spc7_dva_efull_cntr;
reg spc7_dva_efull_d;
reg spc7_dva_vlddtag_err;
reg spc7_dva_vlddcache_err;
reg spc7_dva_err;
reg [6:0] spc7_dva_raddr_d;
reg [4:0] spc7_dva_waddr_d;
reg [4:0] spc7_dva_invwaddr_d;
reg spc7_ld0_lt_1;
reg spc7_ld0_lt_2;
reg spc7_ld0_lt_3;
reg spc7_ld1_lt_0;
reg spc7_ld1_lt_2;
reg spc7_ld1_lt_3;
reg spc7_ld2_lt_0;
reg spc7_ld2_lt_1;
reg spc7_ld2_lt_3;
reg spc7_ld3_lt_0;
reg spc7_ld3_lt_1;
reg spc7_ld3_lt_2;
reg spc7_st0_lt_1;
reg spc7_st0_lt_2;
reg spc7_st0_lt_3;
reg spc7_st1_lt_0;
reg spc7_st1_lt_2;
reg spc7_st1_lt_3;
reg spc7_st2_lt_0;
reg spc7_st2_lt_1;
reg spc7_st2_lt_3;
reg spc7_st3_lt_0;
reg spc7_st3_lt_1;
reg spc7_st3_lt_2;
wire [11:0] spc7_ld_ooo_ret;
wire [11:0] spc7_st_ooo_ret;
wire [7:0] spc7_stb_state_vld0 = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_vld;
wire [7:0] spc7_stb_state_ack0 = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_ack;
wire [7:0] spc7_stb_state_ced0 = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_ced;
wire [7:0] spc7_stb_state_rst0 = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_state_rst;
wire spc7_stb_ack_vld0 = `TOP_DESIGN.sparc7.lsu.stb_ctl0.ack_vld;
wire spc7_ld0_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_inst_vld_g;
wire spc7_intrpt0_cmplt = `TOP_DESIGN.sparc7.lsu.qctl1.lsu_intrpt_cmplt[0];
wire spc7_stb0_full = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_full;
wire spc7_stb0_full_w2 = `TOP_DESIGN.sparc7.lsu.stb_ctl0.stb_full_w2;
wire spc7_lmq0_full = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_pcx_rq_vld;
wire spc7_mbar_vld0 = `TOP_DESIGN.sparc7.lsu.dctl.mbar_vld0;
wire spc7_ld0_unfilled = `TOP_DESIGN.sparc7.lsu.qctl1.ld0_unfilled;
wire spc7_flsh_vld0 = `TOP_DESIGN.sparc7.lsu.dctl.flsh_vld0;
reg [9:0] spc7_ld0_unf_cntr;
reg spc7_ld0_unfilled_d;
reg [9:0] spc7_st0_unf_cntr;
reg spc7_st0_unfilled_d;
reg spc7_st0_unfilled;
reg spc7_mbar_vld_d0;
reg spc7_flsh_vld_d0;
reg spc7_lmq0_full_d;
reg [9:0] spc7_lmq_full_cntr0;
reg spc7_lmq_full_capture0;
reg [9:0] spc7_stb_full_cntr0;
reg spc7_stb_full_capture0;
reg [9:0] spc7_mbar_vld_cntr0;
reg spc7_mbar_vld_capture0;
reg [9:0] spc7_flsh_vld_cntr0;
reg spc7_flsh_vld_capture0;
reg spc7_stb_head_hit0;
wire spc7_raw_ack_capture0;
reg [9:0] spc7_stb_ack_cntr0;
reg [9:0] spc7_stb_ced_cntr0;
reg spc7_stb_ced0_d;
reg spc7_stb_ced_capture0;
wire spc7_stb_ced0;
reg spc7_atm0_d;
reg [9:0] spc7_atm_cntr0;
reg spc7_atm_intrpt_capture0;
reg spc7_atm_intrpt_b4capture0;
reg spc7_atm_inv_capture0;
reg [39:0] spc7_stb_wr_addr0;
reg [39:0] spc7_stb_atm_addr0;
reg spc7_atm_lmiss_eq0;
wire [7:0] spc7_stb_state_vld1 = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_vld;
wire [7:0] spc7_stb_state_ack1 = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_ack;
wire [7:0] spc7_stb_state_ced1 = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_ced;
wire [7:0] spc7_stb_state_rst1 = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_state_rst;
wire spc7_stb_ack_vld1 = `TOP_DESIGN.sparc7.lsu.stb_ctl1.ack_vld;
wire spc7_ld1_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_inst_vld_g;
wire spc7_intrpt1_cmplt = `TOP_DESIGN.sparc7.lsu.qctl1.lsu_intrpt_cmplt[1];
wire spc7_stb1_full = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_full;
wire spc7_stb1_full_w2 = `TOP_DESIGN.sparc7.lsu.stb_ctl1.stb_full_w2;
wire spc7_lmq1_full = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_pcx_rq_vld;
wire spc7_mbar_vld1 = `TOP_DESIGN.sparc7.lsu.dctl.mbar_vld1;
wire spc7_ld1_unfilled = `TOP_DESIGN.sparc7.lsu.qctl1.ld1_unfilled;
wire spc7_flsh_vld1 = `TOP_DESIGN.sparc7.lsu.dctl.flsh_vld1;
reg [9:0] spc7_ld1_unf_cntr;
reg spc7_ld1_unfilled_d;
reg [9:0] spc7_st1_unf_cntr;
reg spc7_st1_unfilled_d;
reg spc7_st1_unfilled;
reg spc7_mbar_vld_d1;
reg spc7_flsh_vld_d1;
reg spc7_lmq1_full_d;
reg [9:0] spc7_lmq_full_cntr1;
reg spc7_lmq_full_capture1;
reg [9:0] spc7_stb_full_cntr1;
reg spc7_stb_full_capture1;
reg [9:0] spc7_mbar_vld_cntr1;
reg spc7_mbar_vld_capture1;
reg [9:0] spc7_flsh_vld_cntr1;
reg spc7_flsh_vld_capture1;
reg spc7_stb_head_hit1;
wire spc7_raw_ack_capture1;
reg [9:0] spc7_stb_ack_cntr1;
reg [9:0] spc7_stb_ced_cntr1;
reg spc7_stb_ced1_d;
reg spc7_stb_ced_capture1;
wire spc7_stb_ced1;
reg spc7_atm1_d;
reg [9:0] spc7_atm_cntr1;
reg spc7_atm_intrpt_capture1;
reg spc7_atm_intrpt_b4capture1;
reg spc7_atm_inv_capture1;
reg [39:0] spc7_stb_wr_addr1;
reg [39:0] spc7_stb_atm_addr1;
reg spc7_atm_lmiss_eq1;
wire [7:0] spc7_stb_state_vld2 = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_vld;
wire [7:0] spc7_stb_state_ack2 = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_ack;
wire [7:0] spc7_stb_state_ced2 = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_ced;
wire [7:0] spc7_stb_state_rst2 = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_state_rst;
wire spc7_stb_ack_vld2 = `TOP_DESIGN.sparc7.lsu.stb_ctl2.ack_vld;
wire spc7_ld2_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_inst_vld_g;
wire spc7_intrpt2_cmplt = `TOP_DESIGN.sparc7.lsu.qctl1.lsu_intrpt_cmplt[2];
wire spc7_stb2_full = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_full;
wire spc7_stb2_full_w2 = `TOP_DESIGN.sparc7.lsu.stb_ctl2.stb_full_w2;
wire spc7_lmq2_full = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_pcx_rq_vld;
wire spc7_mbar_vld2 = `TOP_DESIGN.sparc7.lsu.dctl.mbar_vld2;
wire spc7_ld2_unfilled = `TOP_DESIGN.sparc7.lsu.qctl1.ld2_unfilled;
wire spc7_flsh_vld2 = `TOP_DESIGN.sparc7.lsu.dctl.flsh_vld2;
reg [9:0] spc7_ld2_unf_cntr;
reg spc7_ld2_unfilled_d;
reg [9:0] spc7_st2_unf_cntr;
reg spc7_st2_unfilled_d;
reg spc7_st2_unfilled;
reg spc7_mbar_vld_d2;
reg spc7_flsh_vld_d2;
reg spc7_lmq2_full_d;
reg [9:0] spc7_lmq_full_cntr2;
reg spc7_lmq_full_capture2;
reg [9:0] spc7_stb_full_cntr2;
reg spc7_stb_full_capture2;
reg [9:0] spc7_mbar_vld_cntr2;
reg spc7_mbar_vld_capture2;
reg [9:0] spc7_flsh_vld_cntr2;
reg spc7_flsh_vld_capture2;
reg spc7_stb_head_hit2;
wire spc7_raw_ack_capture2;
reg [9:0] spc7_stb_ack_cntr2;
reg [9:0] spc7_stb_ced_cntr2;
reg spc7_stb_ced2_d;
reg spc7_stb_ced_capture2;
wire spc7_stb_ced2;
reg spc7_atm2_d;
reg [9:0] spc7_atm_cntr2;
reg spc7_atm_intrpt_capture2;
reg spc7_atm_intrpt_b4capture2;
reg spc7_atm_inv_capture2;
reg [39:0] spc7_stb_wr_addr2;
reg [39:0] spc7_stb_atm_addr2;
reg spc7_atm_lmiss_eq2;
wire [7:0] spc7_stb_state_vld3 = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_vld;
wire [7:0] spc7_stb_state_ack3 = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_ack;
wire [7:0] spc7_stb_state_ced3 = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_ced;
wire [7:0] spc7_stb_state_rst3 = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_state_rst;
wire spc7_stb_ack_vld3 = `TOP_DESIGN.sparc7.lsu.stb_ctl3.ack_vld;
wire spc7_ld3_inst_vld_g = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_inst_vld_g;
wire spc7_intrpt3_cmplt = `TOP_DESIGN.sparc7.lsu.qctl1.lsu_intrpt_cmplt[3];
wire spc7_stb3_full = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_full;
wire spc7_stb3_full_w2 = `TOP_DESIGN.sparc7.lsu.stb_ctl3.stb_full_w2;
wire spc7_lmq3_full = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_pcx_rq_vld;
wire spc7_mbar_vld3 = `TOP_DESIGN.sparc7.lsu.dctl.mbar_vld3;
wire spc7_ld3_unfilled = `TOP_DESIGN.sparc7.lsu.qctl1.ld3_unfilled;
wire spc7_flsh_vld3 = `TOP_DESIGN.sparc7.lsu.dctl.flsh_vld3;
reg [9:0] spc7_ld3_unf_cntr;
reg spc7_ld3_unfilled_d;
reg [9:0] spc7_st3_unf_cntr;
reg spc7_st3_unfilled_d;
reg spc7_st3_unfilled;
reg spc7_mbar_vld_d3;
reg spc7_flsh_vld_d3;
reg spc7_lmq3_full_d;
reg [9:0] spc7_lmq_full_cntr3;
reg spc7_lmq_full_capture3;
reg [9:0] spc7_stb_full_cntr3;
reg spc7_stb_full_capture3;
reg [9:0] spc7_mbar_vld_cntr3;
reg spc7_mbar_vld_capture3;
reg [9:0] spc7_flsh_vld_cntr3;
reg spc7_flsh_vld_capture3;
reg spc7_stb_head_hit3;
wire spc7_raw_ack_capture3;
reg [9:0] spc7_stb_ack_cntr3;
reg [9:0] spc7_stb_ced_cntr3;
reg spc7_stb_ced3_d;
reg spc7_stb_ced_capture3;
wire spc7_stb_ced3;
reg spc7_atm3_d;
reg [9:0] spc7_atm_cntr3;
reg spc7_atm_intrpt_capture3;
reg spc7_atm_intrpt_b4capture3;
reg spc7_atm_inv_capture3;
reg [39:0] spc7_stb_wr_addr3;
reg [39:0] spc7_stb_atm_addr3;
reg spc7_atm_lmiss_eq3;
// bug 3967
// The following bad_states needs to be added in lsu_mon.
// < bad_state s_not_ipick (8'bxxx1xxx0);
// < bad_state s_not_lpick (8'bxx10xx0x);
// < bad_state s_not_spick (8'bx100x0xx);
// < bad_state s_not_mpick (8'b10000xxx);
assign spc7_fpick = {spc7_mpick,spc7_spick,spc7_lpick,spc7_ipick};
// Sanjay mentioned, that the final picker is just
// priority encoded for i miss but ld/st/misc are round robin.
// At some point he as to communicate this thru either in a spec.
// or a mail.
always @(negedge clk)
begin
if(rst_l)
begin
casex ({spc7_msquash,spc7_apick,spc7_fpick})
9'b000000000 : spc7_fpicko = 1'b0;
9'b0xxx1xxx1 : spc7_fpicko = 1'b0;
9'b1xxxxxxxx : spc7_fpicko = 1'b0;
9'b0xxx0xxx0 : spc7_fpicko = 1'b0;
default:
begin
spc7_fpicko = 1'b1;
$display("%0d ERROR: lsu_mon7 final picker imiss not picked", $time);
repeat(100) @(posedge clk);
$finish;
end
endcase
end
end
// interface
//exu
assign spc7_exu_und = {spc7_l2,
spc7_unc,
spc7_fpld,
spc7_fpldst,
spc7_unflush,
spc7_ldw,
spc7_byp,
spc7_flsh,
spc7_chm,
spc7_ldxa,
spc7_ato,
spc7_pref,
spc7_chit,
spc7_dcp,
spc7_dtp,
spc7_mpc,
spc7_mpu};
always @(spc7_exu_und)
begin
case (spc7_exu_und)
17'h00000 : spc7_exu = 5'h00;
17'h00001 : spc7_exu = 5'h01;
17'h00002 : spc7_exu = 5'h02;
17'h00004 : spc7_exu = 5'h03;
17'h00008 : spc7_exu = 5'h04;
17'h00010 : spc7_exu = 5'h05;
17'h00020 : spc7_exu = 5'h06;
17'h00040 : spc7_exu = 5'h07;
17'h00080 : spc7_exu = 5'h08;
17'h00100 : spc7_exu = 5'h09;
17'h00200 : spc7_exu = 5'h0a;
17'h00400 : spc7_exu = 5'h0b;
17'h00800 : spc7_exu = 5'h0c;
17'h01000 : spc7_exu = 5'h0d;
17'h02000 : spc7_exu = 5'h0e;
17'h04000 : spc7_exu = 5'h0f;
17'h08000 : spc7_exu = 5'h10;
17'h10000 : spc7_exu = 5'h11;
default: spc7_exu = 5'h12;
endcase
end
//excp
assign spc7_exp_und = {spc7_exp_wtchpt_trp_g,
spc7_exp_misalign_addr_ldst_atm_m,
spc7_exp_priv_violtn_g,
spc7_exp_daccess_excptn_g,
spc7_exp_daccess_prot_g,
spc7_exp_priv_action_g,
spc7_exp_spec_access_epage_g,
spc7_exp_uncache_atomic_g,
spc7_exp_illegal_asi_action_g,
spc7_exp_flt_ld_nfo_pg_g,
spc7_exp_asi_rd_unc,
spc7_exp_tlb_data_ce,
spc7_exp_tlb_data_ue,
spc7_exp_tlb_tag_ue,
spc7_exp_unc,
spc7_exp_corr};
always @(spc7_exp_und)
begin
case (spc7_exp_und)
16'h0000 : spc7_exp = 5'h00;
16'h0001 : spc7_exp = 5'h01;
16'h0002 : spc7_exp = 5'h02;
16'h0004 : spc7_exp = 5'h03;
16'h0008 : spc7_exp = 5'h04;
16'h0010 : spc7_exp = 5'h05;
16'h0020 : spc7_exp = 5'h06;
16'h0040 : spc7_exp = 5'h07;
16'h0080 : spc7_exp = 5'h08;
16'h0100 : spc7_exp = 5'h09;
16'h0200 : spc7_exp = 5'h0a;
16'h0400 : spc7_exp = 5'h0b;
16'h0800 : spc7_exp = 5'h0c;
16'h1000 : spc7_exp = 5'h0d;
16'h2000 : spc7_exp = 5'h0e;
16'h4000 : spc7_exp = 5'h0f;
16'h8000 : spc7_exp = 5'h10;
default: spc7_exp = 5'h11;
endcase
end
//dctl cmplt compact
// Change for rtl timing fix :
// assign lsu_ifu_ldst_cmplt[0] =
// // * can be early or
// ((stxa_internal_d2 & thread0_w3) | stxa_stall_wr_cmplt0_d1) |
// // * late signal and critical.
// // Can this be snapped earlier ?
// (((l2fill_vld_e & ~atomic_ld_squash_e & ~ignore_fill))
// & ~l2fill_fpld_e & ~lsu_cpx_pkt_ld_err[1] & dfill_thread0) |// 1st fill for ldd.
// //& ~l2fill_fpld_e & ~fill_err_trap_e & dfill_thread0) |// 1st fill for ldd.
// intld_byp_cmplt[0] |
// // * early-or signals
// ldst_cmplt_late_0_d1 ;
// assign ldst_cmplt_late_0 =
// (lsu_atm_st_cmplt_e & ~fill_err_trap_e & dfill_thread0) |
// bsync0_reset |
// lsu_intrpt_cmplt[0] |
// diag_wr_cmplt0 |
// dc0_diagnstc_rd_w2 |
// ldxa_illgl_va_cmplt_d1[0] |
// pref_tlbmiss_cmplt_d2[0] |
// lsu_pcx_pref_issue[0];
assign spc7_dctl_stxa_cmplt0 = ((spc7_dctl_stxa_internal_d2 & spc7_dctl_thread0_w3) |
spc7_dctl_stxa_stall_wr_cmplt0_d1);
assign spc7_dctl_l2fill_cmplt0 = (((spc7_dctl_lsu_l2fill_vld & ~spc7_dctl_atomic_ld_squash_e &
~spc7_dctl_lsu_ignore_fill)) & ~spc7_dctl_l2fill_fpld_e &
~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread0);
assign spc7_dctl_fillerr0 = spc7_dctl_l2_corr_error_e & spc7_dctl_dfill_thread0;
// Rolling in changes due to bug 3624
// assign spc7_dctl_atm_cmplt0 = (spc7_dctl_lsu_atm_st_cmplt_e & ~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread0);
assign spc7_dctl_ldst_cond_cmplt0 = { spc7_dctl_stxa_cmplt0, spc7_dctl_l2fill_cmplt0,
spc7_dctl_atomic_ld_squash_e, spc7_dctl_intld_byp_cmplt[0],
spc7_dctl_bsync0_reset, spc7_dctl_lsu_intrpt_cmplt[0]
};
assign spc7_cmplt0 = { spc7_dctl_ldxa_illgl_va_cmplt_d1, spc7_dctl_pref_tlbmiss_cmplt_d2,
spc7_dctl_lsu_pcx_pref_issue, spc7_dctl_diag_wr_cmplt0, spc7_dctl_l2fill_fpld_e};
always @(spc7_cmplt0 or spc7_dctl_ldst_cond_cmplt0)
begin
case ({spc7_dctl_fillerr0,spc7_dctl_ldst_cond_cmplt0,spc7_cmplt0})
12'h000 : spc7_ldstcond_cmplt0 = 4'h0;
12'h001 : spc7_ldstcond_cmplt0 = 4'h1; // fp
12'h002 : spc7_ldstcond_cmplt0 = 4'h2; // dwr
12'h004 : spc7_ldstcond_cmplt0 = 4'h3; // pref
12'h008 : spc7_ldstcond_cmplt0 = 4'h4; // ptlb
12'h010 : spc7_ldstcond_cmplt0 = 4'h5; // va
12'h020 : spc7_ldstcond_cmplt0 = 4'h6; // intr
12'h040 : spc7_ldstcond_cmplt0 = 4'h7; // bsyn
12'h080 : spc7_ldstcond_cmplt0 = 4'h8; // intld
12'h100 : spc7_ldstcond_cmplt0 = 4'h9; // atm
12'h200 : spc7_ldstcond_cmplt0 = 4'ha; // l2
12'h400 : spc7_ldstcond_cmplt0 = 4'hb; // stxa
12'h800 : spc7_ldstcond_cmplt0 = 4'hc; // err
12'ha00 : spc7_ldstcond_cmplt0 = 4'hd; // err & l2
default:
begin
spc7_ldstcond_cmplt0 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc7_dctl_stxa_cmplt1 = ((spc7_dctl_stxa_internal_d2 & spc7_dctl_thread1_w3) |
spc7_dctl_stxa_stall_wr_cmplt1_d1);
assign spc7_dctl_l2fill_cmplt1 = (((spc7_dctl_lsu_l2fill_vld & ~spc7_dctl_atomic_ld_squash_e &
~spc7_dctl_lsu_ignore_fill)) & ~spc7_dctl_l2fill_fpld_e &
~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread1);
assign spc7_dctl_fillerr1 = spc7_dctl_l2_corr_error_e & spc7_dctl_dfill_thread1;
// Rolling in changes due to bug 3624
// assign spc7_dctl_atm_cmplt1 = (spc7_dctl_lsu_atm_st_cmplt_e & ~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread1);
assign spc7_dctl_ldst_cond_cmplt1 = { spc7_dctl_stxa_cmplt1, spc7_dctl_l2fill_cmplt1,
spc7_dctl_atomic_ld_squash_e, spc7_dctl_intld_byp_cmplt[1],
spc7_dctl_bsync1_reset, spc7_dctl_lsu_intrpt_cmplt[1]
};
assign spc7_cmplt1 = { spc7_dctl_ldxa_illgl_va_cmplt_d1, spc7_dctl_pref_tlbmiss_cmplt_d2,
spc7_dctl_lsu_pcx_pref_issue, spc7_dctl_diag_wr_cmplt1, spc7_dctl_l2fill_fpld_e};
always @(spc7_cmplt1 or spc7_dctl_ldst_cond_cmplt1)
begin
case ({spc7_dctl_fillerr1,spc7_dctl_ldst_cond_cmplt1,spc7_cmplt1})
12'h000 : spc7_ldstcond_cmplt1 = 4'h0;
12'h001 : spc7_ldstcond_cmplt1 = 4'h1; // fp
12'h002 : spc7_ldstcond_cmplt1 = 4'h2; // dwr
12'h004 : spc7_ldstcond_cmplt1 = 4'h3; // pref
12'h008 : spc7_ldstcond_cmplt1 = 4'h4; // ptlb
12'h010 : spc7_ldstcond_cmplt1 = 4'h5; // va
12'h020 : spc7_ldstcond_cmplt1 = 4'h6; // intr
12'h040 : spc7_ldstcond_cmplt1 = 4'h7; // bsyn
12'h080 : spc7_ldstcond_cmplt1 = 4'h8; // intld
12'h100 : spc7_ldstcond_cmplt1 = 4'h9; // atm
12'h200 : spc7_ldstcond_cmplt1 = 4'ha; // l2
12'h400 : spc7_ldstcond_cmplt1 = 4'hb; // stxa
12'h800 : spc7_ldstcond_cmplt1 = 4'hc; // err
12'ha00 : spc7_ldstcond_cmplt1 = 4'hd; // err & l2
default:
begin
spc7_ldstcond_cmplt1 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc7_dctl_stxa_cmplt2 = ((spc7_dctl_stxa_internal_d2 & spc7_dctl_thread2_w3) |
spc7_dctl_stxa_stall_wr_cmplt2_d1);
assign spc7_dctl_l2fill_cmplt2 = (((spc7_dctl_lsu_l2fill_vld & ~spc7_dctl_atomic_ld_squash_e &
~spc7_dctl_lsu_ignore_fill)) & ~spc7_dctl_l2fill_fpld_e &
~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread2);
assign spc7_dctl_fillerr2 = spc7_dctl_l2_corr_error_e & spc7_dctl_dfill_thread2;
// Rolling in changes due to bug 3624
// assign spc7_dctl_atm_cmplt2 = (spc7_dctl_lsu_atm_st_cmplt_e & ~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread2);
assign spc7_dctl_ldst_cond_cmplt2 = { spc7_dctl_stxa_cmplt2, spc7_dctl_l2fill_cmplt2,
spc7_dctl_atomic_ld_squash_e, spc7_dctl_intld_byp_cmplt[2],
spc7_dctl_bsync2_reset, spc7_dctl_lsu_intrpt_cmplt[2]
};
assign spc7_cmplt2 = { spc7_dctl_ldxa_illgl_va_cmplt_d1, spc7_dctl_pref_tlbmiss_cmplt_d2,
spc7_dctl_lsu_pcx_pref_issue, spc7_dctl_diag_wr_cmplt2, spc7_dctl_l2fill_fpld_e};
always @(spc7_cmplt2 or spc7_dctl_ldst_cond_cmplt2)
begin
case ({spc7_dctl_fillerr2,spc7_dctl_ldst_cond_cmplt2,spc7_cmplt2})
12'h000 : spc7_ldstcond_cmplt2 = 4'h0;
12'h001 : spc7_ldstcond_cmplt2 = 4'h1; // fp
12'h002 : spc7_ldstcond_cmplt2 = 4'h2; // dwr
12'h004 : spc7_ldstcond_cmplt2 = 4'h3; // pref
12'h008 : spc7_ldstcond_cmplt2 = 4'h4; // ptlb
12'h010 : spc7_ldstcond_cmplt2 = 4'h5; // va
12'h020 : spc7_ldstcond_cmplt2 = 4'h6; // intr
12'h040 : spc7_ldstcond_cmplt2 = 4'h7; // bsyn
12'h080 : spc7_ldstcond_cmplt2 = 4'h8; // intld
12'h100 : spc7_ldstcond_cmplt2 = 4'h9; // atm
12'h200 : spc7_ldstcond_cmplt2 = 4'ha; // l2
12'h400 : spc7_ldstcond_cmplt2 = 4'hb; // stxa
12'h800 : spc7_ldstcond_cmplt2 = 4'hc; // err
12'ha00 : spc7_ldstcond_cmplt2 = 4'hd; // err & l2
default:
begin
spc7_ldstcond_cmplt2 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
assign spc7_dctl_stxa_cmplt3 = ((spc7_dctl_stxa_internal_d2 & spc7_dctl_thread3_w3) |
spc7_dctl_stxa_stall_wr_cmplt3_d1);
assign spc7_dctl_l2fill_cmplt3 = (((spc7_dctl_lsu_l2fill_vld & ~spc7_dctl_atomic_ld_squash_e &
~spc7_dctl_lsu_ignore_fill)) & ~spc7_dctl_l2fill_fpld_e &
~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread3);
assign spc7_dctl_fillerr3 = spc7_dctl_l2_corr_error_e & spc7_dctl_dfill_thread3;
// Rolling in changes due to bug 3624
// assign spc7_dctl_atm_cmplt3 = (spc7_dctl_lsu_atm_st_cmplt_e & ~spc7_dctl_fill_err_trap_e & spc7_dctl_dfill_thread3);
assign spc7_dctl_ldst_cond_cmplt3 = { spc7_dctl_stxa_cmplt3, spc7_dctl_l2fill_cmplt3,
spc7_dctl_atomic_ld_squash_e, spc7_dctl_intld_byp_cmplt[3],
spc7_dctl_bsync3_reset, spc7_dctl_lsu_intrpt_cmplt[3]
};
assign spc7_cmplt3 = { spc7_dctl_ldxa_illgl_va_cmplt_d1, spc7_dctl_pref_tlbmiss_cmplt_d2,
spc7_dctl_lsu_pcx_pref_issue, spc7_dctl_diag_wr_cmplt3, spc7_dctl_l2fill_fpld_e};
always @(spc7_cmplt3 or spc7_dctl_ldst_cond_cmplt3)
begin
case ({spc7_dctl_fillerr3,spc7_dctl_ldst_cond_cmplt3,spc7_cmplt3})
12'h000 : spc7_ldstcond_cmplt3 = 4'h0;
12'h001 : spc7_ldstcond_cmplt3 = 4'h1; // fp
12'h002 : spc7_ldstcond_cmplt3 = 4'h2; // dwr
12'h004 : spc7_ldstcond_cmplt3 = 4'h3; // pref
12'h008 : spc7_ldstcond_cmplt3 = 4'h4; // ptlb
12'h010 : spc7_ldstcond_cmplt3 = 4'h5; // va
12'h020 : spc7_ldstcond_cmplt3 = 4'h6; // intr
12'h040 : spc7_ldstcond_cmplt3 = 4'h7; // bsyn
12'h080 : spc7_ldstcond_cmplt3 = 4'h8; // intld
12'h100 : spc7_ldstcond_cmplt3 = 4'h9; // atm
12'h200 : spc7_ldstcond_cmplt3 = 4'ha; // l2
12'h400 : spc7_ldstcond_cmplt3 = 4'hb; // stxa
12'h800 : spc7_ldstcond_cmplt3 = 4'hc; // err
12'ha00 : spc7_ldstcond_cmplt3 = 4'hd; // err & l2
default:
begin
spc7_ldstcond_cmplt3 = 4'hd;
// Got filter out fp ld and err and check one hot
end
endcase
end
always @(spc7_ldstcond_cmplt0 or spc7_ldstcond_cmplt1 or spc7_ldstcond_cmplt2
or spc7_ldstcond_cmplt3 or spc7_dctl_lsu_ifu_ldst_cmplt
or spc7_dctl_late_cmplt0 or spc7_dctl_late_cmplt1 or spc7_dctl_late_cmplt2 or spc7_dctl_late_cmplt3)
begin
case (spc7_dctl_lsu_ifu_ldst_cmplt)
4'b0000 : spc7_ldstcond_cmplt_d = 4'h0;
4'b0001 : spc7_ldstcond_cmplt_d = spc7_dctl_late_cmplt0 ? spc7_ldstcond_cmplt0_d : spc7_ldstcond_cmplt0;
4'b0010 : spc7_ldstcond_cmplt_d = spc7_dctl_late_cmplt1 ? spc7_ldstcond_cmplt1_d : spc7_ldstcond_cmplt1;
4'b0100 : spc7_ldstcond_cmplt_d = spc7_dctl_late_cmplt2 ? spc7_ldstcond_cmplt2_d : spc7_ldstcond_cmplt2;
4'b1000 : spc7_ldstcond_cmplt_d = spc7_dctl_late_cmplt3 ? spc7_ldstcond_cmplt3_d : spc7_ldstcond_cmplt3;
4'b0011 : spc7_ldstcond_cmplt_d = 4'he;
4'b0101 : spc7_ldstcond_cmplt_d = 4'he;
4'b1001 : spc7_ldstcond_cmplt_d = 4'he;
4'b0110 : spc7_ldstcond_cmplt_d = 4'he;
4'b1010 : spc7_ldstcond_cmplt_d = 4'he;
4'b1100 : spc7_ldstcond_cmplt_d = 4'he;
default:
begin
spc7_ldstcond_cmplt_d = 4'hf;
end
endcase
end
// st returns ooo
assign spc7_st_ooo_ret = { spc7_st0_lt_1, spc7_st0_lt_2, spc7_st0_lt_3,
spc7_st1_lt_0, spc7_st1_lt_2, spc7_st1_lt_3,
spc7_st2_lt_0, spc7_st2_lt_1, spc7_st2_lt_3,
spc7_st3_lt_0, spc7_st3_lt_1, spc7_st3_lt_2};
always @(posedge clk)
begin
if(~spc7_st0_unfilled || ~rst_l)
spc7_st0_unfilled_d <= 1'b0;
else
spc7_st0_unfilled_d <= spc7_st0_unfilled;
if(~rst_l)
spc7_ldstcond_cmplt0_d <= 4'h0;
else
spc7_ldstcond_cmplt0_d <= spc7_ldstcond_cmplt0;
if(~spc7_ld0_pkt_vld_unmasked || ~rst_l)
spc7_ld0_pkt_vld_unmasked_d <= 1'b0;
else
spc7_ld0_pkt_vld_unmasked_d <= spc7_ld0_pkt_vld_unmasked;
if(~rst_l)
spc7_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
else if(spc7_qctl1_ld_sec_hit_thrd0 && spc7_qctl1_ld0_inst_vld_g)
spc7_qctl1_ld_sec_hit_thrd0_w2 <= 1'b1;
else
spc7_qctl1_ld_sec_hit_thrd0_w2 <= 1'b0;
if(~spc7_st1_unfilled || ~rst_l)
spc7_st1_unfilled_d <= 1'b0;
else
spc7_st1_unfilled_d <= spc7_st1_unfilled;
if(~rst_l)
spc7_ldstcond_cmplt1_d <= 4'h0;
else
spc7_ldstcond_cmplt1_d <= spc7_ldstcond_cmplt1;
if(~spc7_ld1_pkt_vld_unmasked || ~rst_l)
spc7_ld1_pkt_vld_unmasked_d <= 1'b0;
else
spc7_ld1_pkt_vld_unmasked_d <= spc7_ld1_pkt_vld_unmasked;
if(~rst_l)
spc7_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
else if(spc7_qctl1_ld_sec_hit_thrd1 && spc7_qctl1_ld1_inst_vld_g)
spc7_qctl1_ld_sec_hit_thrd1_w2 <= 1'b1;
else
spc7_qctl1_ld_sec_hit_thrd1_w2 <= 1'b0;
if(~spc7_st2_unfilled || ~rst_l)
spc7_st2_unfilled_d <= 1'b0;
else
spc7_st2_unfilled_d <= spc7_st2_unfilled;
if(~rst_l)
spc7_ldstcond_cmplt2_d <= 4'h0;
else
spc7_ldstcond_cmplt2_d <= spc7_ldstcond_cmplt2;
if(~spc7_ld2_pkt_vld_unmasked || ~rst_l)
spc7_ld2_pkt_vld_unmasked_d <= 1'b0;
else
spc7_ld2_pkt_vld_unmasked_d <= spc7_ld2_pkt_vld_unmasked;
if(~rst_l)
spc7_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
else if(spc7_qctl1_ld_sec_hit_thrd2 && spc7_qctl1_ld2_inst_vld_g)
spc7_qctl1_ld_sec_hit_thrd2_w2 <= 1'b1;
else
spc7_qctl1_ld_sec_hit_thrd2_w2 <= 1'b0;
if(~spc7_st3_unfilled || ~rst_l)
spc7_st3_unfilled_d <= 1'b0;
else
spc7_st3_unfilled_d <= spc7_st3_unfilled;
if(~rst_l)
spc7_ldstcond_cmplt3_d <= 4'h0;
else
spc7_ldstcond_cmplt3_d <= spc7_ldstcond_cmplt3;
if(~spc7_ld3_pkt_vld_unmasked || ~rst_l)
spc7_ld3_pkt_vld_unmasked_d <= 1'b0;
else
spc7_ld3_pkt_vld_unmasked_d <= spc7_ld3_pkt_vld_unmasked;
if(~rst_l)
spc7_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
else if(spc7_qctl1_ld_sec_hit_thrd3 && spc7_qctl1_ld3_inst_vld_g)
spc7_qctl1_ld_sec_hit_thrd3_w2 <= 1'b1;
else
spc7_qctl1_ld_sec_hit_thrd3_w2 <= 1'b0;
end
always @(posedge clk)
begin
if( ((|spc7_stb_state_ced0) && (|spc7_stb_state_rst0)) || ~rst_l)
spc7_st0_unfilled <= 1'b0;
else if( ((|spc7_stb_state_ced0) && ~(|spc7_stb_state_rst0)))
spc7_st0_unfilled <= 1'b1;
else
spc7_st0_unfilled <= spc7_st0_unfilled;
if( ((|spc7_stb_state_ced1) && (|spc7_stb_state_rst1)) || ~rst_l)
spc7_st1_unfilled <= 1'b0;
else if( ((|spc7_stb_state_ced1) && ~(|spc7_stb_state_rst1)))
spc7_st1_unfilled <= 1'b1;
else
spc7_st1_unfilled <= spc7_st1_unfilled;
if( ((|spc7_stb_state_ced2) && (|spc7_stb_state_rst2)) || ~rst_l)
spc7_st2_unfilled <= 1'b0;
else if( ((|spc7_stb_state_ced2) && ~(|spc7_stb_state_rst2)))
spc7_st2_unfilled <= 1'b1;
else
spc7_st2_unfilled <= spc7_st2_unfilled;
if( ((|spc7_stb_state_ced3) && (|spc7_stb_state_rst3)) || ~rst_l)
spc7_st3_unfilled <= 1'b0;
else if( ((|spc7_stb_state_ced3) && ~(|spc7_stb_state_rst3)))
spc7_st3_unfilled <= 1'b1;
else
spc7_st3_unfilled <= spc7_st3_unfilled;
end
always @(posedge clk)
begin
if((~spc7_st0_unfilled && spc7_st0_unfilled_d)|| ~rst_l)
begin
spc7_st0_unf_cntr <= 9'h000;
end
else if(spc7_st0_unfilled)
begin
spc7_st0_unf_cntr <= spc7_st0_unf_cntr + 1;
end
else
begin
spc7_st0_unf_cntr <= spc7_st0_unf_cntr;
end
if((~spc7_st1_unfilled && spc7_st1_unfilled_d)|| ~rst_l)
begin
spc7_st1_unf_cntr <= 9'h000;
end
else if(spc7_st1_unfilled)
begin
spc7_st1_unf_cntr <= spc7_st1_unf_cntr + 1;
end
else
begin
spc7_st1_unf_cntr <= spc7_st1_unf_cntr;
end
if((~spc7_st2_unfilled && spc7_st2_unfilled_d)|| ~rst_l)
begin
spc7_st2_unf_cntr <= 9'h000;
end
else if(spc7_st2_unfilled)
begin
spc7_st2_unf_cntr <= spc7_st2_unf_cntr + 1;
end
else
begin
spc7_st2_unf_cntr <= spc7_st2_unf_cntr;
end
if((~spc7_st3_unfilled && spc7_st3_unfilled_d)|| ~rst_l)
begin
spc7_st3_unf_cntr <= 9'h000;
end
else if(spc7_st3_unfilled)
begin
spc7_st3_unf_cntr <= spc7_st3_unf_cntr + 1;
end
else
begin
spc7_st3_unf_cntr <= spc7_st3_unf_cntr;
end
end
always @(spc7_st0_unfilled or spc7_st1_unfilled or spc7_st2_unfilled or spc7_st3_unfilled
or spc7_st0_unfilled_d or spc7_st1_unfilled_d or spc7_st2_unfilled_d or spc7_st3_unfilled_d)
begin
if(~spc7_st0_unfilled && spc7_st0_unfilled_d && spc7_st1_unfilled)
spc7_st0_lt_1 <= (spc7_st1_unf_cntr > spc7_st0_unf_cntr);
else
spc7_st0_lt_1 <= 1'b0;
if(~spc7_st0_unfilled && spc7_st0_unfilled_d && spc7_st2_unfilled)
spc7_st0_lt_2 <= (spc7_st2_unf_cntr > spc7_st0_unf_cntr);
else
spc7_st0_lt_2 <= 1'b0;
if(~spc7_st0_unfilled && spc7_st0_unfilled_d && spc7_st3_unfilled)
spc7_st0_lt_3 <= (spc7_st3_unf_cntr > spc7_st0_unf_cntr);
else
spc7_st0_lt_3 <= 1'b0;
// get thr 1
if(~spc7_st1_unfilled && spc7_st1_unfilled_d && spc7_st0_unfilled)
spc7_st1_lt_0 <= (spc7_st0_unf_cntr > spc7_st1_unf_cntr);
else
spc7_st1_lt_0 <= 1'b0;
if(~spc7_st1_unfilled && spc7_st1_unfilled_d && spc7_st2_unfilled)
spc7_st1_lt_2 <= (spc7_st2_unf_cntr > spc7_st1_unf_cntr);
else
spc7_st1_lt_2 <= 1'b0;
if(~spc7_st1_unfilled && spc7_st1_unfilled_d && spc7_st3_unfilled)
spc7_st1_lt_3 <= (spc7_st3_unf_cntr > spc7_st1_unf_cntr);
else
spc7_st1_lt_3 <= 1'b0;
// get thr 2
if(~spc7_st2_unfilled && spc7_st2_unfilled_d && spc7_st0_unfilled)
spc7_st2_lt_0 <= (spc7_st0_unf_cntr > spc7_st2_unf_cntr);
else
spc7_st2_lt_0 <= 1'b0;
if(~spc7_st2_unfilled && spc7_st2_unfilled_d && spc7_st1_unfilled)
spc7_st2_lt_1 <= (spc7_st1_unf_cntr > spc7_st2_unf_cntr);
else
spc7_st2_lt_1 <= 1'b0;
if(~spc7_st2_unfilled && spc7_st2_unfilled_d && spc7_st3_unfilled)
spc7_st2_lt_3 <= (spc7_st3_unf_cntr > spc7_st2_unf_cntr);
else
spc7_st2_lt_3 <= 1'b0;
// get thr 3
if(~spc7_st3_unfilled && spc7_st3_unfilled_d && spc7_st0_unfilled)
spc7_st3_lt_0 <= (spc7_st0_unf_cntr > spc7_st3_unf_cntr);
else
spc7_st3_lt_0 <= 1'b0;
if(~spc7_st3_unfilled && spc7_st3_unfilled_d && spc7_st1_unfilled)
spc7_st3_lt_1 <= (spc7_st1_unf_cntr > spc7_st3_unf_cntr);
else
spc7_st3_lt_1 <= 1'b0;
if(~spc7_st3_unfilled && spc7_st3_unfilled_d && spc7_st2_unfilled)
spc7_st3_lt_2 <= (spc7_st2_unf_cntr > spc7_st3_unf_cntr);
else
spc7_st3_lt_2 <= 1'b0; //
end
// load returns ooo
assign spc7_ld_ooo_ret = { spc7_ld0_lt_1, spc7_ld0_lt_2, spc7_ld0_lt_3,
spc7_ld1_lt_0, spc7_ld1_lt_2, spc7_ld1_lt_3,
spc7_ld2_lt_0, spc7_ld2_lt_1, spc7_ld2_lt_3,
spc7_ld3_lt_0, spc7_ld3_lt_1, spc7_ld3_lt_2};
always @(posedge clk)
begin
if((~spc7_ld0_unfilled && spc7_ld0_unfilled_d)|| ~rst_l)
begin
spc7_ld0_unf_cntr <= 9'h000;
end
else if(spc7_ld0_unfilled)
begin
spc7_ld0_unf_cntr <= spc7_ld0_unf_cntr + 1;
end
else
begin
spc7_ld0_unf_cntr <= spc7_ld0_unf_cntr;
end
if((~spc7_ld1_unfilled && spc7_ld1_unfilled_d)|| ~rst_l)
begin
spc7_ld1_unf_cntr <= 9'h000;
end
else if(spc7_ld1_unfilled)
begin
spc7_ld1_unf_cntr <= spc7_ld1_unf_cntr + 1;
end
else
begin
spc7_ld1_unf_cntr <= spc7_ld1_unf_cntr;
end
if((~spc7_ld2_unfilled && spc7_ld2_unfilled_d)|| ~rst_l)
begin
spc7_ld2_unf_cntr <= 9'h000;
end
else if(spc7_ld2_unfilled)
begin
spc7_ld2_unf_cntr <= spc7_ld2_unf_cntr + 1;
end
else
begin
spc7_ld2_unf_cntr <= spc7_ld2_unf_cntr;
end
if((~spc7_ld3_unfilled && spc7_ld3_unfilled_d)|| ~rst_l)
begin
spc7_ld3_unf_cntr <= 9'h000;
end
else if(spc7_ld3_unfilled)
begin
spc7_ld3_unf_cntr <= spc7_ld3_unf_cntr + 1;
end
else
begin
spc7_ld3_unf_cntr <= spc7_ld3_unf_cntr;
end
end
always @(spc7_ld0_unfilled or spc7_ld1_unfilled or spc7_ld2_unfilled or spc7_ld3_unfilled
or spc7_ld0_unfilled_d or spc7_ld1_unfilled_d or spc7_ld2_unfilled_d or spc7_ld3_unfilled_d)
begin
if(~spc7_ld0_unfilled && spc7_ld0_unfilled_d && spc7_ld1_unfilled)
spc7_ld0_lt_1 <= (spc7_ld1_unf_cntr > spc7_ld0_unf_cntr);
else
spc7_ld0_lt_1 <= 1'b0;
if(~spc7_ld0_unfilled && spc7_ld0_unfilled_d && spc7_ld2_unfilled)
spc7_ld0_lt_2 <= (spc7_ld2_unf_cntr > spc7_ld0_unf_cntr);
else
spc7_ld0_lt_2 <= 1'b0;
if(~spc7_ld0_unfilled && spc7_ld0_unfilled_d && spc7_ld3_unfilled)
spc7_ld0_lt_3 <= (spc7_ld3_unf_cntr > spc7_ld0_unf_cntr);
else
spc7_ld0_lt_3 <= 1'b0;
// get thr 1
if(~spc7_ld1_unfilled && spc7_ld1_unfilled_d && spc7_ld0_unfilled)
spc7_ld1_lt_0 <= (spc7_ld0_unf_cntr > spc7_ld1_unf_cntr);
else
spc7_ld1_lt_0 <= 1'b0;
if(~spc7_ld1_unfilled && spc7_ld1_unfilled_d && spc7_ld2_unfilled)
spc7_ld1_lt_2 <= (spc7_ld2_unf_cntr > spc7_ld1_unf_cntr);
else
spc7_ld1_lt_2 <= 1'b0;
if(~spc7_ld1_unfilled && spc7_ld1_unfilled_d && spc7_ld3_unfilled)
spc7_ld1_lt_3 <= (spc7_ld3_unf_cntr > spc7_ld1_unf_cntr);
else
spc7_ld1_lt_3 <= 1'b0;
// get thr 2
if(~spc7_ld2_unfilled && spc7_ld2_unfilled_d && spc7_ld0_unfilled)
spc7_ld2_lt_0 <= (spc7_ld0_unf_cntr > spc7_ld2_unf_cntr);
else
spc7_ld2_lt_0 <= 1'b0;
if(~spc7_ld2_unfilled && spc7_ld2_unfilled_d && spc7_ld1_unfilled)
spc7_ld2_lt_1 <= (spc7_ld1_unf_cntr > spc7_ld2_unf_cntr);
else
spc7_ld2_lt_1 <= 1'b0;
if(~spc7_ld2_unfilled && spc7_ld2_unfilled_d && spc7_ld3_unfilled)
spc7_ld2_lt_3 <= (spc7_ld3_unf_cntr > spc7_ld2_unf_cntr);
else
spc7_ld2_lt_3 <= 1'b0;
// get thr 3
if(~spc7_ld3_unfilled && spc7_ld3_unfilled_d && spc7_ld0_unfilled)
spc7_ld3_lt_0 <= (spc7_ld0_unf_cntr > spc7_ld3_unf_cntr);
else
spc7_ld3_lt_0 <= 1'b0;
if(~spc7_ld3_unfilled && spc7_ld3_unfilled_d && spc7_ld1_unfilled)
spc7_ld3_lt_1 <= (spc7_ld1_unf_cntr > spc7_ld3_unf_cntr);
else
spc7_ld3_lt_1 <= 1'b0;
if(~spc7_ld3_unfilled && spc7_ld3_unfilled_d && spc7_ld2_unfilled)
spc7_ld3_lt_2 <= (spc7_ld2_unf_cntr > spc7_ld3_unf_cntr);
else
spc7_ld3_lt_2 <= 1'b0; //
end
// bld checks note it has stb_cam hit, ldst_dbl and asi terms removed from the dctl hit equation
assign spc7_dctl_bld_hit =
((|spc7_dctl_lsu_way_hit[3:0]) & spc7_dctl_dcache_enable_g &
~spc7_dctl_ldxa_internal & ~spc7_dctl_dcache_rd_parity_error & ~spc7_dctl_dtag_perror_g &
~spc7_dctl_endian_mispred_g &
~spc7_dctl_atomic_g & ~spc7_dctl_ncache_asild_rq_g) & ~spc7_dctl_tte_data_perror_unc &
spc7_dctl_ld_inst_vld_g & spc7_qctl1_bld_g ;
assign spc7_dctl_bld_stb_hit = spc7_dctl_bld_hit & spc7_dctl_stb_cam_hit;
always @(posedge clk)
begin
if(~rst_l)
begin
spc7_bld0_full_d <= 2'b00;
spc7_ld0_unfilled_d <= 4'b0000;
end
else
begin
spc7_bld0_full_d <= spc7_qctl1_bld_cnt;
spc7_ld0_unfilled_d <= spc7_ld0_unfilled;
end
if(~rst_l)
begin
spc7_bld1_full_d <= 2'b00;
spc7_ld1_unfilled_d <= 4'b0000;
end
else
begin
spc7_bld1_full_d <= spc7_qctl1_bld_cnt;
spc7_ld1_unfilled_d <= spc7_ld1_unfilled;
end
if(~rst_l)
begin
spc7_bld2_full_d <= 2'b00;
spc7_ld2_unfilled_d <= 4'b0000;
end
else
begin
spc7_bld2_full_d <= spc7_qctl1_bld_cnt;
spc7_ld2_unfilled_d <= spc7_ld2_unfilled;
end
if(~rst_l)
begin
spc7_bld3_full_d <= 2'b00;
spc7_ld3_unfilled_d <= 4'b0000;
end
else
begin
spc7_bld3_full_d <= spc7_qctl1_bld_cnt;
spc7_ld3_unfilled_d <= spc7_ld3_unfilled;
end
end
always @(spc7_bld0_full_d or spc7_qctl1_bld_cnt)
begin
if( (spc7_bld0_full_d != spc7_qctl1_bld_cnt) && (spc7_bld0_full_d == 2'd0))
spc7_bld0_full_capture <= 1'b1;
else
spc7_bld0_full_capture <= 1'b0;
end
always @(spc7_bld1_full_d or spc7_qctl1_bld_cnt)
begin
if( (spc7_bld1_full_d != spc7_qctl1_bld_cnt) && (spc7_bld1_full_d == 2'd1))
spc7_bld1_full_capture <= 1'b1;
else
spc7_bld1_full_capture <= 1'b0;
end
always @(spc7_bld2_full_d or spc7_qctl1_bld_cnt)
begin
if( (spc7_bld2_full_d != spc7_qctl1_bld_cnt) && (spc7_bld2_full_d == 2'd2))
spc7_bld2_full_capture <= 1'b1;
else
spc7_bld2_full_capture <= 1'b0;
end
always @(spc7_bld3_full_d or spc7_qctl1_bld_cnt)
begin
if( (spc7_bld3_full_d != spc7_qctl1_bld_cnt) && (spc7_bld3_full_d == 2'd3))
spc7_bld3_full_capture <= 1'b1;
else
spc7_bld3_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( (spc7_qctl1_bld_cnt != 2'b00) && (spc7_bld0_full_cntr != 9'h000)) || ~rst_l)
begin
spc7_bld0_full_cntr <= 9'h000;
end
else if(spc7_qctl1_bld_g && (spc7_qctl1_bld_cnt == 2'b00))
begin
spc7_bld0_full_cntr <= spc7_bld0_full_cntr + 1;
end
else if( (spc7_qctl1_bld_cnt == 2'b00) && (spc7_bld0_full_cntr != 9'h000))
begin
spc7_bld0_full_cntr <= spc7_bld0_full_cntr + 1;
end
else
begin
spc7_bld0_full_cntr <= spc7_bld0_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc7_qctl1_bld_cnt != 2'b01) && (spc7_bld1_full_cntr != 9'h000)) || ~rst_l)
begin
spc7_bld1_full_cntr <= 9'h000;
end
else if(spc7_qctl1_bld_cnt == 2'b01)
begin
spc7_bld1_full_cntr <= spc7_bld1_full_cntr + 1;
end
else if( (spc7_qctl1_bld_cnt == 2'b01) && (spc7_bld1_full_cntr != 9'h000))
begin
spc7_bld1_full_cntr <= spc7_bld1_full_cntr + 1;
end
else
begin
spc7_bld1_full_cntr <= spc7_bld1_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc7_qctl1_bld_cnt != 2'b10) && (spc7_bld2_full_cntr != 9'h000)) || ~rst_l)
begin
spc7_bld2_full_cntr <= 9'h000;
end
else if(spc7_qctl1_bld_cnt == 2'b10)
begin
spc7_bld2_full_cntr <= spc7_bld2_full_cntr + 1;
end
else if( (spc7_qctl1_bld_cnt == 2'b10) && (spc7_bld2_full_cntr != 9'h000))
begin
spc7_bld2_full_cntr <= spc7_bld2_full_cntr + 1;
end
else
begin
spc7_bld2_full_cntr <= spc7_bld2_full_cntr;
end
end
always @(posedge clk)
begin
if( ( (spc7_qctl1_bld_cnt != 2'b11) && (spc7_bld3_full_cntr != 9'h000)) || ~rst_l)
begin
spc7_bld3_full_cntr <= 9'h000;
end
else if(spc7_qctl1_bld_cnt == 2'b11)
begin
spc7_bld3_full_cntr <= spc7_bld3_full_cntr + 1;
end
else if( (spc7_qctl1_bld_cnt == 2'b11) && (spc7_bld3_full_cntr != 9'h000))
begin
spc7_bld3_full_cntr <= spc7_bld3_full_cntr + 1;
end
else
begin
spc7_bld3_full_cntr <= spc7_bld3_full_cntr;
end
end
// Capture atomic address until it's retired
// Used for comparing colliding address
always @(posedge clk)
begin
if( ( ~(|spc7_stb_state_vld0) && ~spc7_atomic_g) || ~rst_l)
begin
spc7_stb_atm_addr0 <= 40'h0000000000;
end
else if(spc7_atomic_g && (spc7_atm_type0 != 8'h00) && spc7_wptr_vld)
begin
spc7_stb_atm_addr0 <= {spc7_wdata_ramc[44:9],spc7_wdata_ramd[67:64]};
end
else
begin
spc7_stb_atm_addr0 <= spc7_stb_atm_addr0;
end
if( ( ~(|spc7_stb_state_vld1) && ~spc7_atomic_g) || ~rst_l)
begin
spc7_stb_atm_addr1 <= 40'h0000000000;
end
else if(spc7_atomic_g && (spc7_atm_type1 != 8'h00) && spc7_wptr_vld)
begin
spc7_stb_atm_addr1 <= {spc7_wdata_ramc[44:9],spc7_wdata_ramd[67:64]};
end
else
begin
spc7_stb_atm_addr1 <= spc7_stb_atm_addr1;
end
if( ( ~(|spc7_stb_state_vld2) && ~spc7_atomic_g) || ~rst_l)
begin
spc7_stb_atm_addr2 <= 40'h0000000000;
end
else if(spc7_atomic_g && (spc7_atm_type2 != 8'h00) && spc7_wptr_vld)
begin
spc7_stb_atm_addr2 <= {spc7_wdata_ramc[44:9],spc7_wdata_ramd[67:64]};
end
else
begin
spc7_stb_atm_addr2 <= spc7_stb_atm_addr2;
end
if( ( ~(|spc7_stb_state_vld3) && ~spc7_atomic_g) || ~rst_l)
begin
spc7_stb_atm_addr3 <= 40'h0000000000;
end
else if(spc7_atomic_g && (spc7_atm_type3 != 8'h00) && spc7_wptr_vld)
begin
spc7_stb_atm_addr3 <= {spc7_wdata_ramc[44:9],spc7_wdata_ramd[67:64]};
end
else
begin
spc7_stb_atm_addr3 <= spc7_stb_atm_addr3;
end
end
assign spc7_dfq_full = (spc7_dfq_vld_entries >= 3'd4);
assign spc7_dfq_full1 = (spc7_dfq_vld_entries >= (3'd4 + 1));
always @(spc7_dfq_full_d1 or spc7_dfq_full1)
begin
if (spc7_dfq_full_d1 && ~spc7_dfq_full1)
spc7_dfq_full_capture1 <= 1'b1;
else
spc7_dfq_full_capture1 <= 1'b0;
end
assign spc7_dfq_full2 = (spc7_dfq_vld_entries >= (3'd4 + 2));
always @(spc7_dfq_full_d2 or spc7_dfq_full2)
begin
if (spc7_dfq_full_d2 && ~spc7_dfq_full2)
spc7_dfq_full_capture2 <= 1'b1;
else
spc7_dfq_full_capture2 <= 1'b0;
end
assign spc7_dfq_full3 = (spc7_dfq_vld_entries >= (3'd4 + 3));
always @(spc7_dfq_full_d3 or spc7_dfq_full3)
begin
if (spc7_dfq_full_d3 && ~spc7_dfq_full3)
spc7_dfq_full_capture3 <= 1'b1;
else
spc7_dfq_full_capture3 <= 1'b0;
end
assign spc7_dfq_full4 = (spc7_dfq_vld_entries >= (3'd4 + 4));
always @(spc7_dfq_full_d4 or spc7_dfq_full4)
begin
if (spc7_dfq_full_d4 && ~spc7_dfq_full4)
spc7_dfq_full_capture4 <= 1'b1;
else
spc7_dfq_full_capture4 <= 1'b0;
end
assign spc7_dfq_full5 = (spc7_dfq_vld_entries >= (3'd4 + 5));
always @(spc7_dfq_full_d5 or spc7_dfq_full5)
begin
if (spc7_dfq_full_d5 && ~spc7_dfq_full5)
spc7_dfq_full_capture5 <= 1'b1;
else
spc7_dfq_full_capture5 <= 1'b0;
end
assign spc7_dfq_full6 = (spc7_dfq_vld_entries >= (3'd4 + 6));
always @(spc7_dfq_full_d6 or spc7_dfq_full6)
begin
if (spc7_dfq_full_d6 && ~spc7_dfq_full6)
spc7_dfq_full_capture6 <= 1'b1;
else
spc7_dfq_full_capture6 <= 1'b0;
end
assign spc7_dfq_full7 = (spc7_dfq_vld_entries >= (3'd4 + 7));
always @(spc7_dfq_full_d7 or spc7_dfq_full7)
begin
if (spc7_dfq_full_d7 && ~spc7_dfq_full7)
spc7_dfq_full_capture7 <= 1'b1;
else
spc7_dfq_full_capture7 <= 1'b0;
end
always @(spc7_mbar_vld_d0 or spc7_mbar_vld0)
begin
if (spc7_mbar_vld_d0 && ~spc7_mbar_vld0)
spc7_mbar_vld_capture0 <= 1'b1;
else
spc7_mbar_vld_capture0 <= 1'b0;
end
always @(spc7_mbar_vld_d1 or spc7_mbar_vld1)
begin
if (spc7_mbar_vld_d1 && ~spc7_mbar_vld1)
spc7_mbar_vld_capture1 <= 1'b1;
else
spc7_mbar_vld_capture1 <= 1'b0;
end
always @(spc7_mbar_vld_d2 or spc7_mbar_vld2)
begin
if (spc7_mbar_vld_d2 && ~spc7_mbar_vld2)
spc7_mbar_vld_capture2 <= 1'b1;
else
spc7_mbar_vld_capture2 <= 1'b0;
end
always @(spc7_mbar_vld_d3 or spc7_mbar_vld3)
begin
if (spc7_mbar_vld_d3 && ~spc7_mbar_vld3)
spc7_mbar_vld_capture3 <= 1'b1;
else
spc7_mbar_vld_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc7_dfq_full1 && (spc7_dfq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr1 <= 9'h000;
spc7_dfq_full_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr1);
end
else if( spc7_dfq_full1)
begin
spc7_dfq_full_cntr1 <= spc7_dfq_full_cntr1 + 1;
spc7_dfq_full_d1 <= spc7_dfq_full1;
end
else
begin
spc7_dfq_full_cntr1 <= spc7_dfq_full_cntr1;
spc7_dfq_full_d1 <= spc7_dfq_full1;
end
if( ( ~spc7_dfq_full2 && (spc7_dfq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr2 <= 9'h000;
spc7_dfq_full_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr2);
end
else if( spc7_dfq_full2)
begin
spc7_dfq_full_cntr2 <= spc7_dfq_full_cntr2 + 1;
spc7_dfq_full_d2 <= spc7_dfq_full2;
end
else
begin
spc7_dfq_full_cntr2 <= spc7_dfq_full_cntr2;
spc7_dfq_full_d2 <= spc7_dfq_full2;
end
if( ( ~spc7_dfq_full3 && (spc7_dfq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr3 <= 9'h000;
spc7_dfq_full_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr3);
end
else if( spc7_dfq_full3)
begin
spc7_dfq_full_cntr3 <= spc7_dfq_full_cntr3 + 1;
spc7_dfq_full_d3 <= spc7_dfq_full3;
end
else
begin
spc7_dfq_full_cntr3 <= spc7_dfq_full_cntr3;
spc7_dfq_full_d3 <= spc7_dfq_full3;
end
if( ( ~spc7_dfq_full4 && (spc7_dfq_full_cntr4 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr4 <= 9'h000;
spc7_dfq_full_d4 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr4);
end
else if( spc7_dfq_full4)
begin
spc7_dfq_full_cntr4 <= spc7_dfq_full_cntr4 + 1;
spc7_dfq_full_d4 <= spc7_dfq_full4;
end
else
begin
spc7_dfq_full_cntr4 <= spc7_dfq_full_cntr4;
spc7_dfq_full_d4 <= spc7_dfq_full4;
end
if( ( ~spc7_dfq_full5 && (spc7_dfq_full_cntr5 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr5 <= 9'h000;
spc7_dfq_full_d5 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr5);
end
else if( spc7_dfq_full5)
begin
spc7_dfq_full_cntr5 <= spc7_dfq_full_cntr5 + 1;
spc7_dfq_full_d5 <= spc7_dfq_full5;
end
else
begin
spc7_dfq_full_cntr5 <= spc7_dfq_full_cntr5;
spc7_dfq_full_d5 <= spc7_dfq_full5;
end
if( ( ~spc7_dfq_full6 && (spc7_dfq_full_cntr6 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr6 <= 9'h000;
spc7_dfq_full_d6 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr6);
end
else if( spc7_dfq_full6)
begin
spc7_dfq_full_cntr6 <= spc7_dfq_full_cntr6 + 1;
spc7_dfq_full_d6 <= spc7_dfq_full6;
end
else
begin
spc7_dfq_full_cntr6 <= spc7_dfq_full_cntr6;
spc7_dfq_full_d6 <= spc7_dfq_full6;
end
if( ( ~spc7_dfq_full7 && (spc7_dfq_full_cntr7 != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr7 <= 9'h000;
spc7_dfq_full_d7 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr7);
end
else if( spc7_dfq_full7)
begin
spc7_dfq_full_cntr7 <= spc7_dfq_full_cntr7 + 1;
spc7_dfq_full_d7 <= spc7_dfq_full7;
end
else
begin
spc7_dfq_full_cntr7 <= spc7_dfq_full_cntr7;
spc7_dfq_full_d7 <= spc7_dfq_full7;
end
end // always @ (posedge clk)
//Capture b4 atomic is sent to pcx
always @(spc7_intrpt0_cmplt or spc7_atm_cntr0 or spc7_stb_state_ced0)
begin
if (spc7_intrpt0_cmplt && (spc7_atm_cntr0 != 9'h000) && ~(|spc7_stb_state_ced0))
spc7_atm_intrpt_b4capture0 <= 1'b1;
else
spc7_atm_intrpt_b4capture0 <= 1'b0;
end
always @(spc7_intrpt1_cmplt or spc7_atm_cntr1 or spc7_stb_state_ced1)
begin
if (spc7_intrpt1_cmplt && (spc7_atm_cntr1 != 9'h000) && ~(|spc7_stb_state_ced1))
spc7_atm_intrpt_b4capture1 <= 1'b1;
else
spc7_atm_intrpt_b4capture1 <= 1'b0;
end
always @(spc7_intrpt2_cmplt or spc7_atm_cntr2 or spc7_stb_state_ced2)
begin
if (spc7_intrpt2_cmplt && (spc7_atm_cntr2 != 9'h000) && ~(|spc7_stb_state_ced2))
spc7_atm_intrpt_b4capture2 <= 1'b1;
else
spc7_atm_intrpt_b4capture2 <= 1'b0;
end
always @(spc7_intrpt3_cmplt or spc7_atm_cntr3 or spc7_stb_state_ced3)
begin
if (spc7_intrpt3_cmplt && (spc7_atm_cntr3 != 9'h000) && ~(|spc7_stb_state_ced3))
spc7_atm_intrpt_b4capture3 <= 1'b1;
else
spc7_atm_intrpt_b4capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc7_intrpt0_cmplt or spc7_atm_cntr0 or spc7_stb_state_ced0)
begin
if (spc7_intrpt0_cmplt && (spc7_atm_cntr0 != 9'h000) && (|spc7_stb_state_ced0))
spc7_atm_intrpt_capture0 <= 1'b1;
else
spc7_atm_intrpt_capture0 <= 1'b0;
end
always @(spc7_intrpt1_cmplt or spc7_atm_cntr1 or spc7_stb_state_ced1)
begin
if (spc7_intrpt1_cmplt && (spc7_atm_cntr1 != 9'h000) && (|spc7_stb_state_ced1))
spc7_atm_intrpt_capture1 <= 1'b1;
else
spc7_atm_intrpt_capture1 <= 1'b0;
end
always @(spc7_intrpt2_cmplt or spc7_atm_cntr2 or spc7_stb_state_ced2)
begin
if (spc7_intrpt2_cmplt && (spc7_atm_cntr2 != 9'h000) && (|spc7_stb_state_ced2))
spc7_atm_intrpt_capture2 <= 1'b1;
else
spc7_atm_intrpt_capture2 <= 1'b0;
end
always @(spc7_intrpt3_cmplt or spc7_atm_cntr3 or spc7_stb_state_ced3)
begin
if (spc7_intrpt3_cmplt && (spc7_atm_cntr3 != 9'h000) && (|spc7_stb_state_ced3))
spc7_atm_intrpt_capture3 <= 1'b1;
else
spc7_atm_intrpt_capture3 <= 1'b0;
end
//Capture after atomic is sent to pcx
always @(spc7_atm_cntr0 or spc7_dva_din or spc7_dva_wen)
begin
if (~spc7_dva_din && spc7_dva_wen && (spc7_atm_cntr0 != 9'h000))
spc7_atm_inv_capture0 <= 1'b1;
else
spc7_atm_inv_capture0 <= 1'b0;
end
always @(spc7_atm_cntr1 or spc7_dva_din or spc7_dva_wen)
begin
if (~spc7_dva_din && spc7_dva_wen && (spc7_atm_cntr1 != 9'h000))
spc7_atm_inv_capture1 <= 1'b1;
else
spc7_atm_inv_capture1 <= 1'b0;
end
always @(spc7_atm_cntr2 or spc7_dva_din or spc7_dva_wen)
begin
if (~spc7_dva_din && spc7_dva_wen && (spc7_atm_cntr2 != 9'h000))
spc7_atm_inv_capture2 <= 1'b1;
else
spc7_atm_inv_capture2 <= 1'b0;
end
always @(spc7_atm_cntr3 or spc7_dva_din or spc7_dva_wen)
begin
if (~spc7_dva_din && spc7_dva_wen && (spc7_atm_cntr3 != 9'h000))
spc7_atm_inv_capture3 <= 1'b1;
else
spc7_atm_inv_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~(|spc7_stb_state_vld0) && (spc7_atm_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_atm_cntr0 <= 9'h000;
spc7_atm0_d <= 1'b0;
end
else if( spc7_atomic_g && (spc7_atm_type0 != 8'h00))
begin
spc7_atm_cntr0 <= spc7_atm_cntr0 + 1;
spc7_atm0_d <= 1'b1;
end
else if( spc7_atm0_d && (|spc7_stb_state_vld0))
begin
spc7_atm_cntr0 <= spc7_atm_cntr0 + 1;
spc7_atm0_d <= spc7_atm0_d;
end
else
begin
spc7_atm_cntr0 <= spc7_atm_cntr0;
spc7_atm0_d <= spc7_atm0_d;
end
if( ( ~(|spc7_stb_state_vld1) && (spc7_atm_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_atm_cntr1 <= 9'h000;
spc7_atm1_d <= 1'b0;
end
else if( spc7_atomic_g && (spc7_atm_type1 != 8'h00))
begin
spc7_atm_cntr1 <= spc7_atm_cntr1 + 1;
spc7_atm1_d <= 1'b1;
end
else if( spc7_atm1_d && (|spc7_stb_state_vld1))
begin
spc7_atm_cntr1 <= spc7_atm_cntr1 + 1;
spc7_atm1_d <= spc7_atm1_d;
end
else
begin
spc7_atm_cntr1 <= spc7_atm_cntr1;
spc7_atm1_d <= spc7_atm1_d;
end
if( ( ~(|spc7_stb_state_vld2) && (spc7_atm_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_atm_cntr2 <= 9'h000;
spc7_atm2_d <= 1'b0;
end
else if( spc7_atomic_g && (spc7_atm_type2 != 8'h00))
begin
spc7_atm_cntr2 <= spc7_atm_cntr2 + 1;
spc7_atm2_d <= 1'b1;
end
else if( spc7_atm2_d && (|spc7_stb_state_vld2))
begin
spc7_atm_cntr2 <= spc7_atm_cntr2 + 1;
spc7_atm2_d <= spc7_atm2_d;
end
else
begin
spc7_atm_cntr2 <= spc7_atm_cntr2;
spc7_atm2_d <= spc7_atm2_d;
end
if( ( ~(|spc7_stb_state_vld3) && (spc7_atm_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_atm_cntr3 <= 9'h000;
spc7_atm3_d <= 1'b0;
end
else if( spc7_atomic_g && (spc7_atm_type3 != 8'h00))
begin
spc7_atm_cntr3 <= spc7_atm_cntr3 + 1;
spc7_atm3_d <= 1'b1;
end
else if( spc7_atm3_d && (|spc7_stb_state_vld3))
begin
spc7_atm_cntr3 <= spc7_atm_cntr3 + 1;
spc7_atm3_d <= spc7_atm3_d;
end
else
begin
spc7_atm_cntr3 <= spc7_atm_cntr3;
spc7_atm3_d <= spc7_atm3_d;
end
end
assign spc7_raw_ack_capture0 = spc7_stb_ack_vld0 && (spc7_stb_ack_cntr0 != 9'h000);
assign spc7_stb_ced0 = |spc7_stb_state_ced0;
assign spc7_raw_ack_capture1 = spc7_stb_ack_vld1 && (spc7_stb_ack_cntr1 != 9'h000);
assign spc7_stb_ced1 = |spc7_stb_state_ced1;
assign spc7_raw_ack_capture2 = spc7_stb_ack_vld2 && (spc7_stb_ack_cntr2 != 9'h000);
assign spc7_stb_ced2 = |spc7_stb_state_ced2;
assign spc7_raw_ack_capture3 = spc7_stb_ack_vld3 && (spc7_stb_ack_cntr3 != 9'h000);
assign spc7_stb_ced3 = |spc7_stb_state_ced3;
always @(posedge clk)
begin
if( ( ~spc7_stb_ced0 && (spc7_stb_ced_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_stb_ced_cntr0 <= 9'h000;
spc7_stb_ced0_d <= 1'b0;
end
else if( spc7_stb_ced0 && (spc7_stb_state_ack0 == 8'h00))
begin
spc7_stb_ced_cntr0 <= spc7_stb_ced_cntr0 + 1;
spc7_stb_ced0_d <= spc7_stb_ced0;
end
else
begin
spc7_stb_ced_cntr0 <= spc7_stb_ced_cntr0;
spc7_stb_ced0_d <= spc7_stb_ced0_d;
end
if( ( ~spc7_mbar_vld0 && (spc7_mbar_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_mbar_vld_cntr0 <= 9'h000;
spc7_mbar_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_mbar_vld_counter = %d", spc7_mbar_vld_cntr0);
end
else if( spc7_mbar_vld0)
begin
spc7_mbar_vld_cntr0 <= spc7_mbar_vld_cntr0 + 1;
spc7_mbar_vld_d0 <= spc7_mbar_vld0;
end
else
begin
spc7_mbar_vld_cntr0 <= spc7_mbar_vld_cntr0;
spc7_mbar_vld_d0 <= spc7_mbar_vld0;
end
if( ( ~spc7_flsh_vld0 && (spc7_flsh_vld_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_flsh_vld_cntr0 <= 9'h000;
spc7_flsh_vld_d0 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_flsh_vld_counter = %d", spc7_flsh_vld_cntr0);
end
else if( spc7_flsh_vld0)
begin
spc7_flsh_vld_cntr0 <= spc7_flsh_vld_cntr0 + 1;
spc7_flsh_vld_d0 <= spc7_flsh_vld0;
end
else
begin
spc7_flsh_vld_cntr0 <= spc7_flsh_vld_cntr0;
spc7_flsh_vld_d0 <= spc7_flsh_vld0;
end
if( ( ~spc7_stb_ced1 && (spc7_stb_ced_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_stb_ced_cntr1 <= 9'h000;
spc7_stb_ced1_d <= 1'b0;
end
else if( spc7_stb_ced1 && (spc7_stb_state_ack1 == 8'h00))
begin
spc7_stb_ced_cntr1 <= spc7_stb_ced_cntr1 + 1;
spc7_stb_ced1_d <= spc7_stb_ced1;
end
else
begin
spc7_stb_ced_cntr1 <= spc7_stb_ced_cntr1;
spc7_stb_ced1_d <= spc7_stb_ced1_d;
end
if( ( ~spc7_mbar_vld1 && (spc7_mbar_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_mbar_vld_cntr1 <= 9'h000;
spc7_mbar_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_mbar_vld_counter = %d", spc7_mbar_vld_cntr1);
end
else if( spc7_mbar_vld1)
begin
spc7_mbar_vld_cntr1 <= spc7_mbar_vld_cntr1 + 1;
spc7_mbar_vld_d1 <= spc7_mbar_vld1;
end
else
begin
spc7_mbar_vld_cntr1 <= spc7_mbar_vld_cntr1;
spc7_mbar_vld_d1 <= spc7_mbar_vld1;
end
if( ( ~spc7_flsh_vld1 && (spc7_flsh_vld_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_flsh_vld_cntr1 <= 9'h000;
spc7_flsh_vld_d1 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_flsh_vld_counter = %d", spc7_flsh_vld_cntr1);
end
else if( spc7_flsh_vld1)
begin
spc7_flsh_vld_cntr1 <= spc7_flsh_vld_cntr1 + 1;
spc7_flsh_vld_d1 <= spc7_flsh_vld1;
end
else
begin
spc7_flsh_vld_cntr1 <= spc7_flsh_vld_cntr1;
spc7_flsh_vld_d1 <= spc7_flsh_vld1;
end
if( ( ~spc7_stb_ced2 && (spc7_stb_ced_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_stb_ced_cntr2 <= 9'h000;
spc7_stb_ced2_d <= 1'b0;
end
else if( spc7_stb_ced2 && (spc7_stb_state_ack2 == 8'h00))
begin
spc7_stb_ced_cntr2 <= spc7_stb_ced_cntr2 + 1;
spc7_stb_ced2_d <= spc7_stb_ced2;
end
else
begin
spc7_stb_ced_cntr2 <= spc7_stb_ced_cntr2;
spc7_stb_ced2_d <= spc7_stb_ced2_d;
end
if( ( ~spc7_mbar_vld2 && (spc7_mbar_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_mbar_vld_cntr2 <= 9'h000;
spc7_mbar_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_mbar_vld_counter = %d", spc7_mbar_vld_cntr2);
end
else if( spc7_mbar_vld2)
begin
spc7_mbar_vld_cntr2 <= spc7_mbar_vld_cntr2 + 1;
spc7_mbar_vld_d2 <= spc7_mbar_vld2;
end
else
begin
spc7_mbar_vld_cntr2 <= spc7_mbar_vld_cntr2;
spc7_mbar_vld_d2 <= spc7_mbar_vld2;
end
if( ( ~spc7_flsh_vld2 && (spc7_flsh_vld_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_flsh_vld_cntr2 <= 9'h000;
spc7_flsh_vld_d2 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_flsh_vld_counter = %d", spc7_flsh_vld_cntr2);
end
else if( spc7_flsh_vld2)
begin
spc7_flsh_vld_cntr2 <= spc7_flsh_vld_cntr2 + 1;
spc7_flsh_vld_d2 <= spc7_flsh_vld2;
end
else
begin
spc7_flsh_vld_cntr2 <= spc7_flsh_vld_cntr2;
spc7_flsh_vld_d2 <= spc7_flsh_vld2;
end
if( ( ~spc7_stb_ced3 && (spc7_stb_ced_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_stb_ced_cntr3 <= 9'h000;
spc7_stb_ced3_d <= 1'b0;
end
else if( spc7_stb_ced3 && (spc7_stb_state_ack3 == 8'h00))
begin
spc7_stb_ced_cntr3 <= spc7_stb_ced_cntr3 + 1;
spc7_stb_ced3_d <= spc7_stb_ced3;
end
else
begin
spc7_stb_ced_cntr3 <= spc7_stb_ced_cntr3;
spc7_stb_ced3_d <= spc7_stb_ced3_d;
end
if( ( ~spc7_mbar_vld3 && (spc7_mbar_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_mbar_vld_cntr3 <= 9'h000;
spc7_mbar_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_mbar_vld_counter = %d", spc7_mbar_vld_cntr3);
end
else if( spc7_mbar_vld3)
begin
spc7_mbar_vld_cntr3 <= spc7_mbar_vld_cntr3 + 1;
spc7_mbar_vld_d3 <= spc7_mbar_vld3;
end
else
begin
spc7_mbar_vld_cntr3 <= spc7_mbar_vld_cntr3;
spc7_mbar_vld_d3 <= spc7_mbar_vld3;
end
if( ( ~spc7_flsh_vld3 && (spc7_flsh_vld_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_flsh_vld_cntr3 <= 9'h000;
spc7_flsh_vld_d3 <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_flsh_vld_counter = %d", spc7_flsh_vld_cntr3);
end
else if( spc7_flsh_vld3)
begin
spc7_flsh_vld_cntr3 <= spc7_flsh_vld_cntr3 + 1;
spc7_flsh_vld_d3 <= spc7_flsh_vld3;
end
else
begin
spc7_flsh_vld_cntr3 <= spc7_flsh_vld_cntr3;
spc7_flsh_vld_d3 <= spc7_flsh_vld3;
end
end
always @(spc7_flsh_vld_d0 or spc7_flsh_vld0)
begin
if (spc7_flsh_vld_d0 && ~spc7_flsh_vld0)
spc7_flsh_vld_capture0 <= 1'b1;
else
spc7_flsh_vld_capture0 <= 1'b0;
end
always @(spc7_flsh_vld_d1 or spc7_flsh_vld1)
begin
if (spc7_flsh_vld_d1 && ~spc7_flsh_vld1)
spc7_flsh_vld_capture1 <= 1'b1;
else
spc7_flsh_vld_capture1 <= 1'b0;
end
always @(spc7_flsh_vld_d2 or spc7_flsh_vld2)
begin
if (spc7_flsh_vld_d2 && ~spc7_flsh_vld2)
spc7_flsh_vld_capture2 <= 1'b1;
else
spc7_flsh_vld_capture2 <= 1'b0;
end
always @(spc7_flsh_vld_d3 or spc7_flsh_vld3)
begin
if (spc7_flsh_vld_d3 && ~spc7_flsh_vld3)
spc7_flsh_vld_capture3 <= 1'b1;
else
spc7_flsh_vld_capture3 <= 1'b0;
end
always @(spc7_lmiss_pa0 or spc7_imiss_pa or spc7_imiss_vld_d or spc7_lmiss_vld0)
begin
if((spc7_lmiss_pa0 == spc7_imiss_pa) && spc7_imiss_vld_d && spc7_lmiss_vld0)
spc7_lmiss_eq0 = 1'b1;
else
spc7_lmiss_eq0 = 1'b0;
end
always @(spc7_lmiss_pa1 or spc7_imiss_pa or spc7_imiss_vld_d or spc7_lmiss_vld1)
begin
if((spc7_lmiss_pa1 == spc7_imiss_pa) && spc7_imiss_vld_d && spc7_lmiss_vld1)
spc7_lmiss_eq1 = 1'b1;
else
spc7_lmiss_eq1 = 1'b0;
end
always @(spc7_lmiss_pa2 or spc7_imiss_pa or spc7_imiss_vld_d or spc7_lmiss_vld2)
begin
if((spc7_lmiss_pa2 == spc7_imiss_pa) && spc7_imiss_vld_d && spc7_lmiss_vld2)
spc7_lmiss_eq2 = 1'b1;
else
spc7_lmiss_eq2 = 1'b0;
end
always @(spc7_lmiss_pa3 or spc7_imiss_pa or spc7_imiss_vld_d or spc7_lmiss_vld3)
begin
if((spc7_lmiss_pa3 == spc7_imiss_pa) && spc7_imiss_vld_d && spc7_lmiss_vld3)
spc7_lmiss_eq3 = 1'b1;
else
spc7_lmiss_eq3 = 1'b0;
end
always @(spc7_lmiss_pa0 or spc7_stb_atm_addr0 or spc7_atm_cntr0 or spc7_lmiss_vld0)
begin
if ( ((spc7_lmiss_pa0 == spc7_stb_atm_addr0) && (spc7_atm_cntr0 != 9'h000) && spc7_lmiss_vld0) ||
((spc7_lmiss_pa1 == spc7_stb_atm_addr0) && (spc7_atm_cntr0 != 9'h000) && spc7_lmiss_vld1) ||
((spc7_lmiss_pa2 == spc7_stb_atm_addr0) && (spc7_atm_cntr0 != 9'h000) && spc7_lmiss_vld2) ||
((spc7_lmiss_pa3 == spc7_stb_atm_addr0) && (spc7_atm_cntr0 != 9'h000) && spc7_lmiss_vld3) )
spc7_atm_lmiss_eq0 = 1'b1;
else
spc7_atm_lmiss_eq0 = 1'b0;
end
always @(spc7_lmiss_pa1 or spc7_stb_atm_addr1 or spc7_atm_cntr1 or spc7_lmiss_vld1)
begin
if ( ((spc7_lmiss_pa0 == spc7_stb_atm_addr1) && (spc7_atm_cntr1 != 9'h000) && spc7_lmiss_vld0) ||
((spc7_lmiss_pa1 == spc7_stb_atm_addr1) && (spc7_atm_cntr1 != 9'h000) && spc7_lmiss_vld1) ||
((spc7_lmiss_pa2 == spc7_stb_atm_addr1) && (spc7_atm_cntr1 != 9'h000) && spc7_lmiss_vld2) ||
((spc7_lmiss_pa3 == spc7_stb_atm_addr1) && (spc7_atm_cntr1 != 9'h000) && spc7_lmiss_vld3) )
spc7_atm_lmiss_eq1 = 1'b1;
else
spc7_atm_lmiss_eq1 = 1'b0;
end
always @(spc7_lmiss_pa2 or spc7_stb_atm_addr2 or spc7_atm_cntr2 or spc7_lmiss_vld2)
begin
if ( ((spc7_lmiss_pa0 == spc7_stb_atm_addr2) && (spc7_atm_cntr2 != 9'h000) && spc7_lmiss_vld0) ||
((spc7_lmiss_pa1 == spc7_stb_atm_addr2) && (spc7_atm_cntr2 != 9'h000) && spc7_lmiss_vld1) ||
((spc7_lmiss_pa2 == spc7_stb_atm_addr2) && (spc7_atm_cntr2 != 9'h000) && spc7_lmiss_vld2) ||
((spc7_lmiss_pa3 == spc7_stb_atm_addr2) && (spc7_atm_cntr2 != 9'h000) && spc7_lmiss_vld3) )
spc7_atm_lmiss_eq2 = 1'b1;
else
spc7_atm_lmiss_eq2 = 1'b0;
end
always @(spc7_lmiss_pa3 or spc7_stb_atm_addr3 or spc7_atm_cntr3 or spc7_lmiss_vld3)
begin
if ( ((spc7_lmiss_pa0 == spc7_stb_atm_addr3) && (spc7_atm_cntr3 != 9'h000) && spc7_lmiss_vld0) ||
((spc7_lmiss_pa1 == spc7_stb_atm_addr3) && (spc7_atm_cntr3 != 9'h000) && spc7_lmiss_vld1) ||
((spc7_lmiss_pa2 == spc7_stb_atm_addr3) && (spc7_atm_cntr3 != 9'h000) && spc7_lmiss_vld2) ||
((spc7_lmiss_pa3 == spc7_stb_atm_addr3) && (spc7_atm_cntr3 != 9'h000) && spc7_lmiss_vld3) )
spc7_atm_lmiss_eq3 = 1'b1;
else
spc7_atm_lmiss_eq3 = 1'b0;
end
always @(spc7_imiss_pa or spc7_stb_atm_addr0 or spc7_atm_cntr0 or spc7_imiss_vld_d)
begin
if((spc7_imiss_pa == spc7_stb_atm_addr0) && (spc7_atm_cntr0 != 9'h000) && spc7_imiss_vld_d)
spc7_atm_imiss_eq0 = 1'b1;
else
spc7_atm_imiss_eq0 = 1'b0;
end
always @(spc7_imiss_pa or spc7_stb_atm_addr1 or spc7_atm_cntr1 or spc7_imiss_vld_d)
begin
if((spc7_imiss_pa == spc7_stb_atm_addr1) && (spc7_atm_cntr1 != 9'h000) && spc7_imiss_vld_d)
spc7_atm_imiss_eq1 = 1'b1;
else
spc7_atm_imiss_eq1 = 1'b0;
end
always @(spc7_imiss_pa or spc7_stb_atm_addr2 or spc7_atm_cntr2 or spc7_imiss_vld_d)
begin
if((spc7_imiss_pa == spc7_stb_atm_addr2) && (spc7_atm_cntr2 != 9'h000) && spc7_imiss_vld_d)
spc7_atm_imiss_eq2 = 1'b1;
else
spc7_atm_imiss_eq2 = 1'b0;
end
always @(spc7_imiss_pa or spc7_stb_atm_addr3 or spc7_atm_cntr3 or spc7_imiss_vld_d)
begin
if((spc7_imiss_pa == spc7_stb_atm_addr3) && (spc7_atm_cntr3 != 9'h000) && spc7_imiss_vld_d)
spc7_atm_imiss_eq3 = 1'b1;
else
spc7_atm_imiss_eq3 = 1'b0;
end
always @(posedge clk)
begin
if( ~spc7_imiss_vld || ~rst_l)
spc7_imiss_vld_d <= 1'b0;
else
spc7_imiss_vld_d <= spc7_imiss_vld;
if( ~spc7_ld_miss || ~rst_l)
spc7_ld_miss_capture <= 1'b0;
else
spc7_ld_miss_capture <= spc7_ld_miss;
end
always @(spc7_stb_ced0 or spc7_stb_ced0_d)
begin
if (~spc7_stb_ced0 && spc7_stb_ced0_d)
spc7_stb_ced_capture0 <= 1'b1;
else
spc7_stb_ced_capture0 <= 1'b0;
end
always @(spc7_stb_ced1 or spc7_stb_ced1_d)
begin
if (~spc7_stb_ced1 && spc7_stb_ced1_d)
spc7_stb_ced_capture1 <= 1'b1;
else
spc7_stb_ced_capture1 <= 1'b0;
end
always @(spc7_stb_ced2 or spc7_stb_ced2_d)
begin
if (~spc7_stb_ced2 && spc7_stb_ced2_d)
spc7_stb_ced_capture2 <= 1'b1;
else
spc7_stb_ced_capture2 <= 1'b0;
end
always @(spc7_stb_ced3 or spc7_stb_ced3_d)
begin
if (~spc7_stb_ced3 && spc7_stb_ced3_d)
spc7_stb_ced_capture3 <= 1'b1;
else
spc7_stb_ced_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( (spc7_stb_state_ack0 != 8'h00 && (spc7_stb_ack_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_stb_ack_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_ack_counter0 = %d", spc7_stb_ack_cntr0);
end
else if(spc7_stb_cam_hit && spc7_ld0_inst_vld_g && (spc7_stb_state_ack0 == 8'h00))
begin
spc7_stb_ack_cntr0 <= spc7_stb_ack_cntr0 + 1;
end
else if( (spc7_stb_state_ack0 == 8'h00 ) && (spc7_stb_ack_cntr0 != 9'h000))
begin
spc7_stb_ack_cntr0 <= spc7_stb_ack_cntr0 + 1;
end // if ( (spc7_stb_state_ack0 == 8'h00 ) && (spc7_stb_ack_cntr0 != 9'h000))
else
begin
spc7_stb_ack_cntr0 <= spc7_stb_ack_cntr0;
end
if( (spc7_stb_state_ack1 != 8'h00 && (spc7_stb_ack_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_stb_ack_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_ack_counter1 = %d", spc7_stb_ack_cntr1);
end
else if(spc7_stb_cam_hit && spc7_ld1_inst_vld_g && (spc7_stb_state_ack1 == 8'h00))
begin
spc7_stb_ack_cntr1 <= spc7_stb_ack_cntr1 + 1;
end
else if( (spc7_stb_state_ack1 == 8'h00 ) && (spc7_stb_ack_cntr1 != 9'h000))
begin
spc7_stb_ack_cntr1 <= spc7_stb_ack_cntr1 + 1;
end // if ( (spc7_stb_state_ack1 == 8'h00 ) && (spc7_stb_ack_cntr1 != 9'h000))
else
begin
spc7_stb_ack_cntr1 <= spc7_stb_ack_cntr1;
end
if( (spc7_stb_state_ack2 != 8'h00 && (spc7_stb_ack_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_stb_ack_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_ack_counter2 = %d", spc7_stb_ack_cntr2);
end
else if(spc7_stb_cam_hit && spc7_ld2_inst_vld_g && (spc7_stb_state_ack2 == 8'h00))
begin
spc7_stb_ack_cntr2 <= spc7_stb_ack_cntr2 + 1;
end
else if( (spc7_stb_state_ack2 == 8'h00 ) && (spc7_stb_ack_cntr2 != 9'h000))
begin
spc7_stb_ack_cntr2 <= spc7_stb_ack_cntr2 + 1;
end // if ( (spc7_stb_state_ack2 == 8'h00 ) && (spc7_stb_ack_cntr2 != 9'h000))
else
begin
spc7_stb_ack_cntr2 <= spc7_stb_ack_cntr2;
end
if( (spc7_stb_state_ack3 != 8'h00 && (spc7_stb_ack_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_stb_ack_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_ack_counter3 = %d", spc7_stb_ack_cntr3);
end
else if(spc7_stb_cam_hit && spc7_ld3_inst_vld_g && (spc7_stb_state_ack3 == 8'h00))
begin
spc7_stb_ack_cntr3 <= spc7_stb_ack_cntr3 + 1;
end
else if( (spc7_stb_state_ack3 == 8'h00 ) && (spc7_stb_ack_cntr3 != 9'h000))
begin
spc7_stb_ack_cntr3 <= spc7_stb_ack_cntr3 + 1;
end // if ( (spc7_stb_state_ack3 == 8'h00 ) && (spc7_stb_ack_cntr3 != 9'h000))
else
begin
spc7_stb_ack_cntr3 <= spc7_stb_ack_cntr3;
end
end // always @ (posedge clk)
// stb full coverage window
always @(spc7_stb0_full_w2 or spc7_stb0_full)
begin
if (~spc7_stb0_full_w2 && spc7_stb0_full)
spc7_stb_full_capture0 <= 1'b1;
else
spc7_stb_full_capture0 <= 1'b0;
end
always @(spc7_stb1_full_w2 or spc7_stb1_full)
begin
if (~spc7_stb1_full_w2 && spc7_stb1_full)
spc7_stb_full_capture1 <= 1'b1;
else
spc7_stb_full_capture1 <= 1'b0;
end
always @(spc7_stb2_full_w2 or spc7_stb2_full)
begin
if (~spc7_stb2_full_w2 && spc7_stb2_full)
spc7_stb_full_capture2 <= 1'b1;
else
spc7_stb_full_capture2 <= 1'b0;
end
always @(spc7_stb3_full_w2 or spc7_stb3_full)
begin
if (~spc7_stb3_full_w2 && spc7_stb3_full)
spc7_stb_full_capture3 <= 1'b1;
else
spc7_stb_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc7_stb0_full && (spc7_stb_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_stb_full_cntr0 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_full_counter0 = %d", spc7_stb_full_cntr0);
end
else if( spc7_stb0_full)
begin
spc7_stb_full_cntr0 <= spc7_stb_full_cntr0 + 1;
end
else
begin
spc7_stb_full_cntr0 <= spc7_stb_full_cntr0;
end
if( ( ~spc7_stb1_full && (spc7_stb_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_stb_full_cntr1 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_full_counter1 = %d", spc7_stb_full_cntr1);
end
else if( spc7_stb1_full)
begin
spc7_stb_full_cntr1 <= spc7_stb_full_cntr1 + 1;
end
else
begin
spc7_stb_full_cntr1 <= spc7_stb_full_cntr1;
end
if( ( ~spc7_stb2_full && (spc7_stb_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_stb_full_cntr2 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_full_counter2 = %d", spc7_stb_full_cntr2);
end
else if( spc7_stb2_full)
begin
spc7_stb_full_cntr2 <= spc7_stb_full_cntr2 + 1;
end
else
begin
spc7_stb_full_cntr2 <= spc7_stb_full_cntr2;
end
if( ( ~spc7_stb3_full && (spc7_stb_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_stb_full_cntr3 <= 9'h000;
if(lsu_mon_msg) $display("lsu_mon: spc7_stb_full_counter3 = %d", spc7_stb_full_cntr3);
end
else if( spc7_stb3_full)
begin
spc7_stb_full_cntr3 <= spc7_stb_full_cntr3 + 1;
end
else
begin
spc7_stb_full_cntr3 <= spc7_stb_full_cntr3;
end
end // always @ (posedge clk)
// lmq full coverage window
always @(spc7_lmq0_full_d or spc7_lmq0_full)
begin
if (spc7_lmq0_full_d && ~spc7_lmq0_full)
spc7_lmq_full_capture0 <= 1'b1;
else
spc7_lmq_full_capture0 <= 1'b0;
end
always @(spc7_lmq1_full_d or spc7_lmq1_full)
begin
if (spc7_lmq1_full_d && ~spc7_lmq1_full)
spc7_lmq_full_capture1 <= 1'b1;
else
spc7_lmq_full_capture1 <= 1'b0;
end
always @(spc7_lmq2_full_d or spc7_lmq2_full)
begin
if (spc7_lmq2_full_d && ~spc7_lmq2_full)
spc7_lmq_full_capture2 <= 1'b1;
else
spc7_lmq_full_capture2 <= 1'b0;
end
always @(spc7_lmq3_full_d or spc7_lmq3_full)
begin
if (spc7_lmq3_full_d && ~spc7_lmq3_full)
spc7_lmq_full_capture3 <= 1'b1;
else
spc7_lmq_full_capture3 <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc7_lmq0_full && (spc7_lmq_full_cntr0 != 9'h000)) || ~rst_l)
begin
spc7_lmq_full_cntr0 <= 9'h000;
spc7_lmq0_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_lmq_full_counter0 = %d", spc7_lmq_full_cntr0);
end
else if( spc7_lmq0_full)
begin
spc7_lmq_full_cntr0 <= spc7_lmq_full_cntr0 + 1;
spc7_lmq0_full_d <= spc7_lmq0_full;
end
else
begin
spc7_lmq_full_cntr0 <= spc7_lmq_full_cntr0;
spc7_lmq0_full_d <= spc7_lmq0_full;
end
if( ( ~spc7_lmq1_full && (spc7_lmq_full_cntr1 != 9'h000)) || ~rst_l)
begin
spc7_lmq_full_cntr1 <= 9'h000;
spc7_lmq1_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_lmq_full_counter1 = %d", spc7_lmq_full_cntr1);
end
else if( spc7_lmq1_full)
begin
spc7_lmq_full_cntr1 <= spc7_lmq_full_cntr1 + 1;
spc7_lmq1_full_d <= spc7_lmq1_full;
end
else
begin
spc7_lmq_full_cntr1 <= spc7_lmq_full_cntr1;
spc7_lmq1_full_d <= spc7_lmq1_full;
end
if( ( ~spc7_lmq2_full && (spc7_lmq_full_cntr2 != 9'h000)) || ~rst_l)
begin
spc7_lmq_full_cntr2 <= 9'h000;
spc7_lmq2_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_lmq_full_counter2 = %d", spc7_lmq_full_cntr2);
end
else if( spc7_lmq2_full)
begin
spc7_lmq_full_cntr2 <= spc7_lmq_full_cntr2 + 1;
spc7_lmq2_full_d <= spc7_lmq2_full;
end
else
begin
spc7_lmq_full_cntr2 <= spc7_lmq_full_cntr2;
spc7_lmq2_full_d <= spc7_lmq2_full;
end
if( ( ~spc7_lmq3_full && (spc7_lmq_full_cntr3 != 9'h000)) || ~rst_l)
begin
spc7_lmq_full_cntr3 <= 9'h000;
spc7_lmq3_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_lmq_full_counter3 = %d", spc7_lmq_full_cntr3);
end
else if( spc7_lmq3_full)
begin
spc7_lmq_full_cntr3 <= spc7_lmq_full_cntr3 + 1;
spc7_lmq3_full_d <= spc7_lmq3_full;
end
else
begin
spc7_lmq_full_cntr3 <= spc7_lmq_full_cntr3;
spc7_lmq3_full_d <= spc7_lmq3_full;
end
end // always @ (posedge clk)
// dfq full coverage window
always @(spc7_dfq_full_d or spc7_dfq_full)
begin
if (spc7_dfq_full_d && ~spc7_dfq_full)
spc7_dfq_full_capture <= 1'b1;
else
spc7_dfq_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc7_dfq_full && (spc7_dfq_full_cntr != 9'h000)) || ~rst_l)
begin
spc7_dfq_full_cntr <= 9'h000;
spc7_dfq_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dfq_full_counter = %d", spc7_dfq_full_cntr);
end
else if( spc7_dfq_full)
begin
spc7_dfq_full_cntr <= spc7_dfq_full_cntr + 1;
spc7_dfq_full_d <= spc7_dfq_full;
end
else
begin
spc7_dfq_full_cntr <= spc7_dfq_full_cntr;
spc7_dfq_full_d <= spc7_dfq_full;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc7_dva_full_d or spc7_dva_inv)
begin
if (spc7_dva_full_d && ~spc7_dva_inv)
spc7_dva_full_capture <= 1'b1;
else
spc7_dva_full_capture <= 1'b0;
end
always @(posedge clk)
begin
if (spc7_dva_din && spc7_dva_wen)
begin
spc7_dva_inv <= 1'b1;
spc7_dva_waddr_d <= spc7_dva_waddr;
end
else if(~spc7_dva_din && spc7_dva_wen)
begin
spc7_dva_inv <= 1'b0;
spc7_dva_waddr_d <= 5'b00000;
end
else
begin
spc7_dva_inv <= spc7_dva_inv;
spc7_dva_waddr_d <= spc7_dva_waddr_d;
end
end
always @(spc7_dva_raddr or spc7_dva_ren or spc7_dva_inv)
begin
if (spc7_dva_inv && spc7_dva_ren && (spc7_dva_raddr[6:2] == spc7_dva_waddr_d))
spc7_dva_vld2lkup <= 1'b1;
else
spc7_dva_vld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc7_dva_inv && (spc7_dva_full_cntr != 9'h000)) || ~rst_l)
begin
spc7_dva_full_cntr <= 9'h000;
spc7_dva_full_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dva_full_counter = %d", spc7_dva_full_cntr);
end
else if( spc7_dva_inv)
begin
spc7_dva_full_cntr <= spc7_dva_full_cntr + 1;
spc7_dva_full_d <= spc7_dva_inv;
end
else
begin
spc7_dva_full_cntr <= spc7_dva_full_cntr;
spc7_dva_full_d <= spc7_dva_full_d;
end
end // always @ (posedge clk)
// dva valid/invalidate coverage window
always @(spc7_dva_vfull_d or spc7_dva_vld)
begin
if (spc7_dva_vfull_d && ~spc7_dva_vld)
spc7_dva_vfull_capture <= 1'b1;
else
spc7_dva_vfull_capture <= 1'b0;
end
always @(posedge clk)
begin
if (~spc7_dva_din && spc7_dva_wen)
begin
spc7_dva_vld <= 1'b1;
spc7_dva_invwaddr_d <= spc7_dva_waddr;
spc7_dva_invld_err <= spc7_dva_inv_perror;
end
else if(spc7_dva_din && spc7_dva_wen)
begin
spc7_dva_vld <= 1'b0;
spc7_dva_invwaddr_d <= 5'b00000;
spc7_dva_invld_err <= 1'b0;
end
else
begin
spc7_dva_vld <= spc7_dva_vld;
spc7_dva_invwaddr_d <= spc7_dva_invwaddr_d;
spc7_dva_invld_err <= spc7_dva_invld_err;
end
end
always @(spc7_dva_raddr or spc7_dva_ren or spc7_dva_vld)
begin
if (spc7_dva_vld && spc7_dva_ren && (spc7_dva_raddr[6:2] == spc7_dva_waddr_d))
spc7_dva_invld2lkup <= 1'b1;
else
spc7_dva_invld2lkup <= 1'b0;
end
always @(posedge clk)
begin
if( ( ~spc7_dva_vld && (spc7_dva_vfull_cntr != 9'h000)) || ~rst_l)
begin
spc7_dva_vfull_cntr <= 9'h000;
spc7_dva_vfull_d <= 1'b0;
if(lsu_mon_msg) $display("lsu_mon: spc7_dva_vfull_counter = %d", spc7_dva_vfull_cntr);
end
else if( spc7_dva_vld)
begin
spc7_dva_vfull_cntr <= spc7_dva_vfull_cntr + 1;
spc7_dva_vfull_d <= spc7_dva_vld;
end
else
begin
spc7_dva_vfull_cntr <= spc7_dva_vfull_cntr;
spc7_dva_vfull_d <= spc7_dva_vfull_d;
end
end // always @ (posedge clk)
// Can this ever happen/Might have to flag this as an error..
always @(spc7_dva_raddr or spc7_dva_waddr or spc7_dva_ren or spc7_dva_wen)
begin
if ( spc7_dva_ren && spc7_dva_wen && (spc7_dva_raddr[6:2] == spc7_dva_waddr))
spc7_dva_collide <= 1'b1;
else
spc7_dva_collide <= 1'b0;
end
// dva error cases
always @(spc7_dva_raddr or spc7_dva_ren or spc7_dva_dtag_perror or spc7_dva_dtag_perror)
begin
if (spc7_dva_ren && (spc7_dva_dtag_perror || spc7_dva_dtag_perror))
spc7_dva_err <= 1'b1;
else
spc7_dva_err <= 1'b0;
end
always @(posedge clk)
begin
if(spc7_dva_err)
spc7_dva_efull_d <= 1'b1;
else
spc7_dva_efull_d <= 1'b0;
end
always @(posedge clk)
begin
if( (spc7_dva_ren && ~(spc7_dva_dtag_perror || spc7_dva_dtag_perror ) &&
(spc7_dva_efull_cntr != 9'h000)) || ~rst_l)
begin
spc7_dva_efull_cntr <= 9'h000;
spc7_dva_raddr_d <= spc7_dva_raddr;
if(lsu_mon_msg) $display("lsu_mon: spc7_dva_efull_counter = %d", spc7_dva_efull_cntr);
end
else if(spc7_dva_efull_d)
begin
spc7_dva_efull_cntr <= spc7_dva_efull_cntr + 1;
spc7_dva_raddr_d <= spc7_dva_raddr_d;
end
else
begin
spc7_dva_efull_cntr <= spc7_dva_efull_cntr;
spc7_dva_raddr_d <= spc7_dva_raddr_d;
end
end // always @ (posedge clk)
`endif
endmodule
|
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Quick and dirty test harness for zl_top (including FT2232 interfacing).
//
//------------------------------------------------------------------------------
`ifndef _ZL_TOP_TB_V_
`define _ZL_TOP_TB_V_
`timescale 1ns/1ps
module zl_top_tb ();
reg clk;
reg rst_n;
initial begin
clk = 0;
forever clk = #10 ~clk;
end
integer infile;
integer outfile;
reg usb_fifo_rxf_n;
reg [7:0] usb_fifo_data;
wire usb_fifo_rd_n;
reg [7:0] next_data;
wire dac_clk;
wire dac_i_pre;
wire dac_q_pre;
initial begin
rst_n = 0;
usb_fifo_rxf_n = 1;
usb_fifo_data = 8'bx;
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
rst_n = 1;
outfile = $fopen("out.bin", "w");
infile = $fopen("test.m2v","r");
next_data = $fgetc(infile);
while (!$feof(infile)) begin
usb_fifo_rxf_n = 1'b0;
wait(!usb_fifo_rd_n);
#1;
usb_fifo_data = next_data;
wait(usb_fifo_rd_n);
#1;
usb_fifo_data = 8'bx;
usb_fifo_rxf_n = 1'b1;
#49;
next_data = $fgetc(infile);
end
wait(!uut.sample_out_valid);
wait(clk);
wait(!clk);
wait(clk);
$fclose(infile);
$fclose(outfile);
$finish;
end
always @(posedge dac_clk) begin
if(uut.sample_out_valid) begin
$fwrite(outfile, "%c", dac_i_pre);
$fwrite(outfile, "%c", dac_q_pre);
end
end
zl_top uut
(
.ext_clk_50(clk),
.ext_rst_button_n(rst_n),
//
.usb_fifo_rxf_n(usb_fifo_rxf_n),
.usb_fifo_rd_n(usb_fifo_rd_n),
.usb_fifo_data(usb_fifo_data),
//
.dac_clk(dac_clk),
.dac_i(),
.dac_q(),
.dac_i_pre(dac_i_pre),
.dac_q_pre(dac_q_pre),
//
.debug_led()
);
endmodule // zl_top_tb
`endif // _ZL_TOP_TB_V_
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_4_V
`define SKY130_FD_SC_HDLL__A32OI_4_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32oi_4 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32oi_4 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_4_V
|
/**
* bsg_serial_in_parallel_out_dynamic.v
*
* Paul Gao 06/2019
*
*/
`include "bsg_defines.v"
module bsg_serial_in_parallel_out_dynamic
#(parameter `BSG_INV_PARAM(width_p )
,parameter `BSG_INV_PARAM(max_els_p )
,parameter lg_max_els_lp = `BSG_SAFE_CLOG2(max_els_p)
)
(input clk_i
,input reset_i
// Input side
,input v_i
,input [lg_max_els_lp-1:0] len_i
,input [width_p-1:0] data_i
,output ready_o
,output len_ready_o
// Output side
,output v_o
,output [max_els_p-1:0][width_p-1:0] data_o
,input yumi_i
);
genvar i;
logic yumi_lo;
assign yumi_lo = v_i & ready_o;
logic [lg_max_els_lp-1:0] count_r, count_lo, len_r, len_lo;
logic clear_li, up_li, dff_en_li, go_fifo_v_li;
logic count_r_is_zero, count_r_is_last;
// fix evaluate to Z problem in simulation
assign count_lo = count_r;
// When new packet coming, use new length, otherwise use registered length
assign len_lo = (count_r_is_zero)? len_i : len_r;
assign count_r_is_zero = (count_lo == lg_max_els_lp'(0));
assign count_r_is_last = (count_lo == len_lo );
// We accept new length when first word comes in
// At this time, counter is at initial value 0
assign len_ready_o = count_r_is_zero;
// Count up if data word is not last word of current packet.
assign up_li = yumi_lo & ~count_r_is_last;
// Clear counter when it reaches target length
assign clear_li = yumi_lo & count_r_is_last;
assign go_fifo_v_li = clear_li;
// Update length register when new packet comes in
assign dff_en_li = yumi_lo & count_r_is_zero;
// Length counter
bsg_counter_clear_up
#(.max_val_p (max_els_p-1)
,.init_val_p(0)
) ctr
(.clk_i (clk_i )
,.reset_i (reset_i )
,.clear_i (clear_li)
,.up_i (up_li )
,.count_o (count_r )
);
// Length register
bsg_dff_reset_en
#(.width_p (lg_max_els_lp)
,.reset_val_p(0)
) dff_len
(.clk_i (clk_i )
,.reset_i (reset_i )
,.en_i (dff_en_li)
,.data_i (len_i )
,.data_o (len_r )
);
// Go fifo
// Notify output side that packet is ready to send
// Must use two element fifo to match lowest word data fifo!
logic one_word_lo;
bsg_two_fifo
#(.width_p(1)
) go_fifo
(.clk_i (clk_i )
,.reset_i(reset_i )
,.ready_o(/* This fifo has same size of lowest word data fifo
No need to check ready_o here */)
,.data_i (count_r_is_zero) // Indicate whether it is single word packet
,.v_i (go_fifo_v_li )
,.v_o (v_o )
,.data_o (one_word_lo )
,.yumi_i (yumi_i )
);
logic [max_els_p-1:0] fifo_valid_li, fifo_ready_lo;
logic [max_els_p-1:0] fifo_valid_lo, fifo_yumi_li;
// Ready signal from selected fifo
assign ready_o = fifo_ready_lo[count_lo];
for (i = 0; i < max_els_p; i++)
begin: rof0
if (i == 0)
// Lowest word fifo always dequeue (packet should have at least one word)
assign fifo_yumi_li[i] = yumi_i;
else
// Rest are bsg_one_fifo, only dequeue when they have valid data
//
// Corner case: a single-word packet comes in firstly, then a
// multi-word packet comes. Use one_word_lo to determine whether
// first packet is one-word or not.
//
// Case above can be prevented if we use bsg_one_fifo everywhere, but
// there will be one-cycle bubble between packets.
assign fifo_yumi_li[i] = fifo_valid_lo[i] & yumi_i & ~one_word_lo;
end
// Trigger selected valid signal
bsg_decode_with_v
#(.num_out_p(max_els_p)
) bdwv
(.i (count_lo )
,.v_i(v_i )
,.o (fifo_valid_li)
);
// Data fifos
for (i = 0; i < max_els_p; i++)
begin: fifos
if (i == 0)
begin: twofifo
// Use two element fifo to avoid bubble
bsg_two_fifo
#(.width_p(width_p)
) fifo
(.clk_i (clk_i )
,.reset_i(reset_i)
,.ready_o(fifo_ready_lo[i])
,.data_i (data_i )
,.v_i (fifo_valid_li[i])
,.v_o (fifo_valid_lo[i])
,.data_o (data_o [i])
,.yumi_i (fifo_yumi_li [i])
);
end
else
begin: onefifo
// Must use one element fifo to work correctly!
bsg_one_fifo
#(.width_p(width_p)
) fifo
(.clk_i (clk_i )
,.reset_i(reset_i)
,.ready_o(fifo_ready_lo[i])
,.data_i (data_i )
,.v_i (fifo_valid_li[i])
,.v_o (fifo_valid_lo[i])
,.data_o (data_o [i])
,.yumi_i (fifo_yumi_li [i])
);
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_serial_in_parallel_out_dynamic)
|
module servo_driver #(parameter freq = 50_000_000) (
input wire clk,
input wire rst_n,
input wire[7:0] angle,
output reg servo_pwm = 0,
output reg cycle_done = 0
);
parameter CYCLES_1_MS = freq / 1_000;
parameter CYCLES_PER_ANGLE = (CYCLES_1_MS * 2) / 8'hFF;
parameter CYCLES_21u33_MS = CYCLES_1_MS * 21 + CYCLES_1_MS / 3;
parameter CYCLES_22_MS = CYCLES_1_MS * 22;
// INTERNAL REGISTERS
reg[7:0] angle_reg = 0; // Used for storing angle
reg[31:0] counter = 0; // Used for store one period
reg[31:0] pulse_width = 0; // Used for vary pulse width (reversed)
reg[1:0] state = 0; // FSM current state
reg[1:0] next_state = 0; // FSM next state
parameter GET_ANGLE = 2'b00;
parameter GET_WIDTH = 2'b01;
parameter HIGH_PULSE = 2'b10;
parameter LOW_PULSE = 2'b11;
// Assign new state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
state = GET_ANGLE;
end else begin
state = next_state;
end
end
// Next state logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
next_state = GET_ANGLE;
end else begin
case (state)
GET_ANGLE: begin
next_state = GET_WIDTH;
end
GET_WIDTH: begin
next_state = HIGH_PULSE;
end
HIGH_PULSE: begin
if (counter == pulse_width) begin
next_state = LOW_PULSE;
end
end
LOW_PULSE: begin
if (counter == 0) begin
next_state = GET_ANGLE;
end
end
endcase
end
end
// Outputs logic
always @(posedge clk or negedge rst_n) begin
if (~rst_n) begin
servo_pwm = 0;
cycle_done = 0;
counter = 0;
angle_reg = 0;
pulse_width = 0;
end else begin
case (state)
GET_ANGLE: begin
angle_reg = angle;
cycle_done = 1;
counter = CYCLES_22_MS;
end
GET_WIDTH: begin
pulse_width = CYCLES_21u33_MS - angle_reg * CYCLES_PER_ANGLE;
servo_pwm = 1;
cycle_done = 0;
end
HIGH_PULSE: begin
counter = counter - 1;
servo_pwm = 1;
end
LOW_PULSE: begin
counter = counter - 1;
servo_pwm = 0;
end
endcase
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 18:28:34 03/22/2016
// Design Name:
// Module Name: Generador_Caracteres
// Project Name:
// Target Devices:
// Tool versions:
// Description: Este módulo se encarga de generar el texto que se requiere en la imagen del monitor.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module generador_caracteres
(
input wire clk,
input wire [3:0] digit0_HH, digit1_HH, digit0_MM, digit1_MM, digit0_SS, digit1_SS,//
digit0_DAY, digit1_DAY, digit0_MES, digit1_MES, digit0_YEAR, digit1_YEAR,//
digit0_HH_T, digit1_HH_T, digit0_MM_T, digit1_MM_T, digit0_SS_T, digit1_SS_T,//Decenas y unidades para los números en pantalla (18 inputs de 3 bits)
input wire AM_PM,//Entrada para conocer si en la información de hora se despliega AM o PM
input wire parpadeo,//parpadeo del cursor
input wire [1:0] config_mode,//Cuatro estados del modo configuración
input wire [1:0] cursor_location,//Marca la posición del cursor en modo configuración
input wire [9:0] pixel_x, pixel_y,//Coordenada de cada pixel
output wire AMPM_on, //Localización de esos respectivos textos
output wire text_on, //10 "textos" en total en pantalla (bandera de indica que se debe escribir texto)
output reg [7:0] text_RGB //8 bpp (Nexys 3)
);
//Declaración de señales
//Font ROM (caracteres 16x32)
wire [11:0] rom_addr; //ASCII 7-bits + Fila 5-bits
reg [6:0] char_addr; //ASCII 7-bits
reg [4:0] row_addr; //Direccion de fila del patrón de caracter en particular(5 bits)
reg [3:0] bit_addr; //Columna del pixel particular de un patrón de caracter (4 bits)
wire [15:0] font_word;//Fila de pixeles del patrón de caracter en particular (16 bits)
wire font_bit;//1 pixel del font_word específicado por bit_addr
//Direcciones "auxiliares" para cada uno de los dígitos de los números a mostrar
reg [6:0] char_addr_digHORA, char_addr_digFECHA, char_addr_digTIMER, char_addr_AMPM;
wire [4:0] row_addr_digHORA, row_addr_digFECHA, row_addr_digTIMER, row_addr_AMPM;
wire [3:0] bit_addr_digHORA, bit_addr_digFECHA, bit_addr_digTIMER, bit_addr_AMPM;
wire digHORA_on, digFECHA_on, digTIMER_on;
//Instanciación de la font ROM
ROM_16x32 Instancia_ROM_16x32
(.clk(clk), .addr(rom_addr), .data(font_word));
//Descripción de comportamiento
//1.Dígitos para representar la HORA(tamaño de fuente 16x32)
assign digHORA_on = (pixel_y[9:5]==4)&&(pixel_x[9:4]>=16)&&(pixel_x[9:4]<=23);
assign row_addr_digHORA = pixel_y[4:0];
assign bit_addr_digHORA = pixel_x[3:0];
always@*
begin
case(pixel_x[6:4])
3'b000: char_addr_digHORA = {3'b011, digit1_HH};//(decenas hrs)
3'b001: char_addr_digHORA = {3'b011, digit0_HH};//(unidades hrs)
3'b010: char_addr_digHORA = 7'h3a;//:
3'b011: char_addr_digHORA = {3'b011, digit1_MM};//(decenas min)
3'b100: char_addr_digHORA = {3'b011, digit0_MM};//(unidades min)
3'b101: char_addr_digHORA = 7'h3a;//:
3'b110: char_addr_digHORA = {3'b011, digit1_SS};//(decenas s)
3'b111: char_addr_digHORA = {3'b011, digit0_SS};//(unidades s)
endcase
end
//2.Dígitos para representar la FECHA(tamaño de fuente 16x32)
assign digFECHA_on = (pixel_y[9:5]==12)&&(pixel_x[9:4]>=7)&&(pixel_x[9:4]<=14);
assign row_addr_digFECHA = pixel_y[4:0];
assign bit_addr_digFECHA = pixel_x[3:0];
always@*
begin
case(pixel_x[6:4])
3'b111: char_addr_digFECHA = {3'b011, digit1_DAY};//(decenas DIA)
3'b000: char_addr_digFECHA = {3'b011, digit0_DAY};//(unidades DIA)
3'b001: char_addr_digFECHA = 7'h2f;//"/"
3'b010: char_addr_digFECHA = {3'b011, digit1_MES};//(decenas MES)
3'b011: char_addr_digFECHA = {3'b011, digit0_MES};//(unidades MES)
3'b100: char_addr_digFECHA = 7'h2f;//"/"
3'b101: char_addr_digFECHA = {3'b011, digit1_YEAR};//(decenas AÑO)
3'b110: char_addr_digFECHA = {3'b011, digit0_YEAR};//(unidades AÑO)
endcase
end
//3.Dígitos para la cuenta del TIMER(tamaño de fuente 16x32)
assign digTIMER_on = (pixel_y[9:5]==12)&&(pixel_x[9:4]>=25)&&(pixel_x[9:4]<=32);
assign row_addr_digTIMER = pixel_y[4:0];
assign bit_addr_digTIMER = pixel_x[3:0];
always@*
begin
case(pixel_x[6:4])
3'b001: char_addr_digTIMER = {3'b011, digit1_HH_T};//(decenas hrs)
3'b010: char_addr_digTIMER = {3'b011, digit0_HH_T};//(unidades hrs)
3'b011: char_addr_digTIMER = 7'h3a;//:
3'b100: char_addr_digTIMER = {3'b011, digit1_MM_T};//(decenas min)
3'b101: char_addr_digTIMER = {3'b011, digit0_MM_T};//(unidades min)
3'b110: char_addr_digTIMER = 7'h3a;//:
3'b111: char_addr_digTIMER = {3'b011, digit1_SS_T};//(decenas s)
3'b000: char_addr_digTIMER = {3'b011, digit0_SS_T};//(decenas s)
endcase
end
//4.Palabra AM o PM(tamaño de fuente 16x32)
assign AMPM_on = (pixel_y[9:5]==1)&&(pixel_x[9:4]>=26)&&(pixel_x[9:4]<=27);
assign row_addr_AMPM = pixel_y[4:0];
assign bit_addr_AMPM = pixel_x[3:0];
always@*
begin
case(pixel_x[4])
1'b0:
begin
case(AM_PM)//AM_PM = 0: se escribe AM
1'b0: char_addr_AMPM = 7'h61;//A
1'b1: char_addr_AMPM = 7'h64;//P
endcase
end
1'b1: char_addr_AMPM = 7'h63;//M
endcase
end
//Multiplexar las direcciones para font ROM y salida RBG
always @*
begin
text_RGB = 8'b0;//Fondo negro
if(digHORA_on)
begin
char_addr = char_addr_digHORA;
row_addr = row_addr_digHORA;
bit_addr = bit_addr_digHORA;
//(0: Los dos dígitos a la derecha, 1: Los dos dígitos intermedios, 2: Los dos dígitos a la izquierda, 3: Ubicación de AM/PM)
//Evalúa que se está configurando (0: modo normal, 1: config.hora, 2: config.fecha, 3: config.timer)
if(font_bit) text_RGB = 8'h00; //Negro
else if ((parpadeo)&&(~font_bit)&&(config_mode == 1)&&(pixel_y[9:5]==4)&&(pixel_x[9:4]>=16)&&(pixel_x[9:4]<=17)&&(cursor_location==2))
text_RGB =8'hFF;//Hace un cursor si se está en modo configuración
else if ((parpadeo)&&(~font_bit)&&(config_mode == 1)&&(pixel_y[9:5]==4)&&(pixel_x[9:4]>=19)&&(pixel_x[9:4]<=20)&&(cursor_location==1))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if ((parpadeo)&&(~font_bit)&&(config_mode == 1)&&(pixel_y[9:5]==4)&&(pixel_x[9:4]>=22)&&(pixel_x[9:4]<=23)&&(cursor_location==0))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if(~font_bit) text_RGB = 8'h1E;//Fondo del texto igual al de los recuadros
end
else if(digFECHA_on)
begin
char_addr = char_addr_digFECHA;
row_addr = row_addr_digFECHA;
bit_addr = bit_addr_digFECHA;
//(0: Los dos dígitos a la derecha, 1: Los dos dígitos intermedios, 2: Los dos dígitos a la izquierda, 3: Ubicación de día semana)
if(font_bit) text_RGB =8'h00; //Negro
else if ((parpadeo)&&(~font_bit)&&(config_mode == 2)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=7)&&(pixel_x[9:4]<=8)&&(cursor_location==2))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if ((parpadeo)&&(~font_bit)&&(config_mode == 2)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=10)&&(pixel_x[9:4]<=11)&&(cursor_location==1))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if ((parpadeo)&&(~font_bit)&&(config_mode == 2)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=13)&&(pixel_x[9:4]<=14)&&(cursor_location==0))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if(~font_bit) text_RGB = 8'h1E;//Fondo del texto igual al de los recuadros
end
else if ((digTIMER_on))
begin
char_addr = char_addr_digTIMER;
row_addr = row_addr_digTIMER;
bit_addr = bit_addr_digTIMER;
//(0: Los dos dígitos a la derecha, 1: Los dos dígitos intermedios, 2: Los dos dígitos a la izquierda)
if(font_bit) text_RGB = 8'h00; //Negro
else if ((parpadeo)&&(~font_bit)&&(config_mode == 3)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=25)&&(pixel_x[9:4]<=26)&&(cursor_location==2))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if ((parpadeo)&&(~font_bit)&&(config_mode == 3)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=28)&&(pixel_x[9:4]<=29)&&(cursor_location==1))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if ((parpadeo)&&(~font_bit)&&(config_mode == 3)&&(pixel_y[9:5]==12)&&(pixel_x[9:4]>=31)&&(pixel_x[9:4]<=32)&&(cursor_location==0))
text_RGB = 8'hFF;//Hace un cursor si se está en modo configuración
else if(~font_bit) text_RGB = 8'h1E;//Fondo del texto igual al de los recuadros
end
else
begin
char_addr = char_addr_AMPM;
row_addr = row_addr_AMPM;
bit_addr = bit_addr_AMPM;
if(font_bit) text_RGB = 8'hFF; //Blanco
end
end
assign text_on = digHORA_on|digFECHA_on|digTIMER_on;//3 bloques de texto en total
//Interfaz con la font ROM
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
/*
Nota: Los 10 textos a mostrar son
1.La palabra HORA
2.Los dígitos para la hora
3.Los números de la fecha
4.El día de la semana
5.La palabra TIMER
6.Los dígitos para la cuenta del timer
7.La palabra RING
8.AM o PM
9.RTC DISPLAY v1.0
*/ |
{{define "compositeFB"}}// This file has been automatically generated by goFB and should not be edited by hand
// Compiler written by Hammond Pearce and available at github.com/kiwih/goFB
// Verilog support is EXPERIMENTAL ONLY
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$compositeFB := $block.CompositeFB}}{{$uniqueConnsWithTypes := $block.GetUniqueDataConnSourcesWithTypes $blocks}}
// This file represents the Composite Function Block for {{$block.Name}}
module FB_{{$block.Name}} {{template "_moduleDeclr" .}}
//Wires needed for event connections
{{range $curConnIndex, $connName := $compositeFB.GetUniqueEventConnSources}}wire {{renameConnSignal $connName}};
{{end}}
//Wires needed for data connections
{{range $curConnIndex, $conn := $uniqueConnsWithTypes}}wire {{getVerilogSize $conn.Type}} {{renameConnSignal $conn.Source}};
{{end}}
//top level I/O to signals
{{if $block.EventInputs}}//input events
{{range $index, $event := $block.EventInputs}}{{range $curConnIndex, $conn := $compositeFB.EventConnections}}{{if eq $conn.Source $event.Name}}assign {{renameConnSignal $conn.Source}} = {{$event.Name}}_eI;
{{end}}{{end}}{{end}}
{{end}}{{if $block.EventOutputs}}//output events
{{range $index, $event := $block.EventOutputs}}{{range $curConnIndex, $conn := $compositeFB.EventConnections}}{{if eq $conn.Destination $event.Name}}assign {{$event.Name}}_eO = {{renameConnSignal $conn.Source}};
{{end}}{{end}}{{end}}
{{end}}{{if $block.InputVars}}//input variables
{{range $index, $var := $block.InputVars}}{{range $curConnIndex, $conn := $compositeFB.DataConnections}}{{if eq $conn.Source $var.Name}}assign {{renameConnSignal $conn.Source}} = {{$var.Name}}_I;
{{end}}{{end}}{{end}}
{{end}}{{if $block.OutputVars}}//output events
{{range $index, $var := $block.OutputVars}}{{range $curConnIndex, $conn := $compositeFB.DataConnections}}{{if eq $conn.Destination $var.Name}}assign {{$var.Name}}_O = {{renameConnSignal $conn.Source}};
{{end}}{{end}}{{end}}
{{end}}
// child I/O to signals
{{range $currChildIndex, $child := $compositeFB.FBs}}
FB_{{$child.Type}} {{$child.Name}} (
.clk(clk),
//event outputs {{/* For both events and data connection outputs, we need to only output the *unique* signals (vhdl can't drive many signals from a single output). Hence this rigmarole. */}}
{{range $curConnIndex, $connName := $compositeFB.GetUniqueEventConnSources}}{{if connChildNameMatches $connName $child.Name}}.{{connChildSourceOnly $connName}}_eO({{renameConnSignal $connName}}),
{{end}}{{end}}
//event inputs
{{range $curConnIndex, $conn := $compositeFB.EventConnections}}{{if connChildNameMatches $conn.Destination $child.Name}}.{{connChildSourceOnly $conn.Destination}}_eI({{renameConnSignal $conn.Source}}),
{{end}}{{end}}
//data outputs
{{range $curConnIndex, $connName := $compositeFB.GetUniqueDataConnSources}}{{if connChildNameMatches $connName $child.Name}}.{{connChildSourceOnly $connName}}_O({{renameConnSignal $connName}}),
{{end}}{{end}}
//data inputs
{{range $curConnIndex, $conn := $compositeFB.DataConnections}}{{if connChildNameMatches $conn.Destination $child.Name}}.{{connChildSourceOnly $conn.Destination}}_I({{renameConnSignal $conn.Source}}),
{{end}}{{end}}
.reset(reset)
);
{{end}}
endmodule{{end}} |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a222oi (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
C1 ,
C2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input C1 ;
input C2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y , nand0_out, nand1_out, nand2_out);
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND );
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222OI_FUNCTIONAL_PP_V |
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module mi_nios_LED (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
out_port,
readdata
)
;
output [ 7: 0] out_port;
output [ 31: 0] readdata;
input [ 1: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 31: 0] writedata;
wire clk_en;
reg [ 7: 0] data_out;
wire [ 7: 0] out_port;
wire [ 7: 0] read_mux_out;
wire [ 31: 0] readdata;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign read_mux_out = {8 {(address == 0)}} & data_out;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else if (chipselect && ~write_n && (address == 0))
data_out <= writedata[7 : 0];
end
assign readdata = {32'b0 | read_mux_out};
assign out_port = data_out;
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps / 1ps
`default_nettype none
module tcp_to_bus (
input wire BUS_RST,
input wire BUS_CLK,
// SiTCP TCP RX
output reg [15:0] TCP_RX_WC, // Rx FIFO write count[15:0] (Unused bits should be set 1)
input wire TCP_RX_WR, // Write enable
input wire [7:0] TCP_RX_DATA, // Write data[7:0]
//input wire TCP_TX_FULL, // Almost full flag
//output wire TCP_TX_WR, // Write enable
//output reg TCP_TX_DATA, // Write data[7:0]
// SiTCP RBCP (UDP)
input wire RBCP_ACT,
input wire [31:0] RBCP_ADDR,
input wire [7:0] RBCP_WD,
input wire RBCP_WE,
input wire RBCP_RE,
output reg RBCP_ACK,
output wire [7:0] RBCP_RD,
// BUS
output wire BUS_WR,
output wire BUS_RD,
output wire [31:0] BUS_ADD,
inout wire [7:0] BUS_DATA,
output reg INVALID
);
// TCP
wire TCP_RESET;
reg [15:0] LENGTH;
reg [15:0] BYTE_CNT;
reg [31:0] TCP_TO_BUS_ADD;
reg [15:0] RX_DATA_255_CNT;
wire TCP_TO_BUS_WR;
always @(posedge BUS_CLK)
if(BUS_RST) begin
TCP_RX_WC <= 0;
end else if(TCP_RX_WR) begin
TCP_RX_WC <= TCP_RX_WC + 1;
end else begin
TCP_RX_WC <= 0;
end
always @(posedge BUS_CLK)
if(BUS_RST) begin
BYTE_CNT <= 0;
end else if(INVALID || TCP_RESET) begin
BYTE_CNT <= 0;
end else if((BYTE_CNT >= 5) && ((BYTE_CNT - 5) == LENGTH)) begin
BYTE_CNT <= 0;
end else if(TCP_RX_WR) begin
BYTE_CNT <= BYTE_CNT + 1;
end else begin
BYTE_CNT <= BYTE_CNT;
end
// invalid signal will prevent from writing to BUS
// invalid signal will be reset when TCP write request is de-asserted
always @(posedge BUS_CLK)
if (BUS_RST)
INVALID <= 1'b0;
else if (TCP_RESET)
INVALID <= 1'b0;
// check for correct length, substract header size 6
// check for correct max. address
else if (({TCP_RX_DATA, LENGTH[7:0]} > 65529 && BYTE_CNT == 1) || ((LENGTH + {TCP_RX_DATA, TCP_TO_BUS_ADD[23:0]} > 33'h1_0000_0000) && BYTE_CNT == 5))
INVALID <= 1'b1;
else
INVALID <= INVALID;
always @(posedge BUS_CLK)
if(BUS_RST) begin
RX_DATA_255_CNT <= 0;
end else if(TCP_RX_WR && ~&TCP_RX_DATA) begin // TCP data is not 255
RX_DATA_255_CNT <= 0;
end else if(TCP_RX_WR && &TCP_RX_DATA && ~&RX_DATA_255_CNT) begin // TCP data is 255
RX_DATA_255_CNT <= RX_DATA_255_CNT + 1;
end else begin
RX_DATA_255_CNT <= RX_DATA_255_CNT;
end
assign TCP_RESET = (&TCP_RX_DATA && RX_DATA_255_CNT == 16'hff_fe && TCP_RX_WR) || ((&TCP_RX_DATA && &RX_DATA_255_CNT && TCP_RX_WR));
always @(posedge BUS_CLK)
if(BUS_RST) begin
LENGTH <= 0;
end else if(TCP_RX_WR && BYTE_CNT == 0) begin
LENGTH[7:0] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 1) begin
LENGTH[15:8] <= TCP_RX_DATA;
end else begin
LENGTH <= LENGTH;
end
assign TCP_TO_BUS_WR = (TCP_RX_WR && BYTE_CNT > 5 && !INVALID) ? 1'b1 : 1'b0;
always @(posedge BUS_CLK)
if(BUS_RST) begin
TCP_TO_BUS_ADD <= 0;
end else if(TCP_RX_WR && BYTE_CNT == 2) begin
TCP_TO_BUS_ADD[7:0] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 3) begin
TCP_TO_BUS_ADD[15:8] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 4) begin
TCP_TO_BUS_ADD[23:16] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT == 5) begin
TCP_TO_BUS_ADD[31:24] <= TCP_RX_DATA;
end else if(TCP_RX_WR && BYTE_CNT > 5) begin
TCP_TO_BUS_ADD <= TCP_TO_BUS_ADD + 1;
end else begin
TCP_TO_BUS_ADD <= TCP_TO_BUS_ADD;
end
// RBCP
wire RBCP_TO_BUS_WR;
always @(posedge BUS_CLK) begin
if(BUS_RST)
RBCP_ACK <= 0;
else begin
if (RBCP_ACK == 1)
RBCP_ACK <= 0;
else
RBCP_ACK <= (RBCP_WE | RBCP_RE) & ~TCP_TO_BUS_WR;
end
end
assign RBCP_TO_BUS_WR = RBCP_WE & RBCP_ACT;
assign RBCP_RD[7:0] = BUS_WR ? 8'bz : BUS_DATA;
// BUS
assign BUS_WR = TCP_TO_BUS_WR | RBCP_TO_BUS_WR;
assign BUS_RD = RBCP_RE & RBCP_ACT & ~BUS_WR;
assign BUS_ADD = (TCP_TO_BUS_WR) ? TCP_TO_BUS_ADD : RBCP_ADDR;
assign BUS_DATA = (BUS_WR) ? ((TCP_TO_BUS_WR) ? TCP_RX_DATA : RBCP_WD) : 8'bz;
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import Nnat ZArith_base Lia ZArithRing Zdiv Morphisms.
Local Open Scope Z_scope.
(** This file provides results about the Round-Toward-Zero Euclidean
division [Z.quotrem], whose projections are [Z.quot] (noted ÷)
and [Z.rem].
This division and [Z.div] agree only on positive numbers.
Otherwise, [Z.div] performs Round-Toward-Bottom (a.k.a Floor).
This [Z.quot] is compatible with the division of usual
programming languages such as Ocaml. In addition, it has nicer
properties with respect to opposite and other usual operations.
The definition of this division is now in file [BinIntDef],
while most of the results about here are now in the main module
[BinInt.Z], thanks to the generic "Numbers" layer. Remain here:
- some compatibility notation for old names.
- some extra results with less preconditions (in particular
exploiting the arbitrary value of division by 0).
*)
Notation Ndiv_Zquot := N2Z.inj_quot (only parsing).
Notation Nmod_Zrem := N2Z.inj_rem (only parsing).
Notation Z_quot_rem_eq := Z.quot_rem' (only parsing).
Notation Zrem_lt := Z.rem_bound_abs (only parsing).
Notation Zquot_unique := Z.quot_unique (compat "8.7").
Notation Zrem_unique := Z.rem_unique (compat "8.7").
Notation Zrem_1_r := Z.rem_1_r (compat "8.7").
Notation Zquot_1_r := Z.quot_1_r (compat "8.7").
Notation Zrem_1_l := Z.rem_1_l (compat "8.7").
Notation Zquot_1_l := Z.quot_1_l (compat "8.7").
Notation Z_quot_same := Z.quot_same (compat "8.7").
Notation Z_quot_mult := Z.quot_mul (only parsing).
Notation Zquot_small := Z.quot_small (compat "8.7").
Notation Zrem_small := Z.rem_small (compat "8.7").
Notation Zquot2_quot := Zquot2_quot (compat "8.7").
(** Particular values taken for [a÷0] and [(Z.rem a 0)].
We avise to not rely on these arbitrary values. *)
Lemma Zquot_0_r a : a ÷ 0 = 0.
Proof. now destruct a. Qed.
Lemma Zrem_0_r a : Z.rem a 0 = a.
Proof. now destruct a. Qed.
(** The following results are expressed without the [b<>0] condition
whenever possible. *)
Lemma Zrem_0_l a : Z.rem 0 a = 0.
Proof. now destruct a. Qed.
Lemma Zquot_0_l a : 0÷a = 0.
Proof. now destruct a. Qed.
Hint Resolve Zrem_0_l Zrem_0_r Zquot_0_l Zquot_0_r Z.quot_1_r Z.rem_1_r
: zarith.
Ltac zero_or_not a :=
destruct (Z.eq_decidable a 0) as [->|?];
[rewrite ?Zquot_0_l, ?Zrem_0_l, ?Zquot_0_r, ?Zrem_0_r;
auto with zarith|].
Lemma Z_rem_same a : Z.rem a a = 0.
Proof. zero_or_not a. now apply Z.rem_same. Qed.
Lemma Z_rem_mult a b : Z.rem (a*b) b = 0.
Proof. zero_or_not b. now apply Z.rem_mul. Qed.
(** * Division and Opposite *)
(* The precise equalities that are invalid with "historic" Zdiv. *)
Theorem Zquot_opp_l a b : (-a)÷b = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_l. Qed.
Theorem Zquot_opp_r a b : a÷(-b) = -(a÷b).
Proof. zero_or_not b. now apply Z.quot_opp_r. Qed.
Theorem Zrem_opp_l a b : Z.rem (-a) b = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_l. Qed.
Theorem Zrem_opp_r a b : Z.rem a (-b) = Z.rem a b.
Proof. zero_or_not b. now apply Z.rem_opp_r. Qed.
Theorem Zquot_opp_opp a b : (-a)÷(-b) = a÷b.
Proof. zero_or_not b. now apply Z.quot_opp_opp. Qed.
Theorem Zrem_opp_opp a b : Z.rem (-a) (-b) = -(Z.rem a b).
Proof. zero_or_not b. now apply Z.rem_opp_opp. Qed.
(** The sign of the remainder is the one of [a]. Due to the possible
nullity of [a], a general result is to be stated in the following form:
*)
Theorem Zrem_sgn a b : 0 <= Z.sgn (Z.rem a b) * Z.sgn a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- zero_or_not (Z.rem a b).
rewrite Z.rem_sign_nz; trivial. apply Z.square_nonneg.
Qed.
(** This can also be said in a simplier way: *)
Theorem Zrem_sgn2 a b : 0 <= (Z.rem a b) * a.
Proof.
zero_or_not b.
- apply Z.square_nonneg.
- now apply Z.rem_sign_mul.
Qed.
(** Reformulation of [Z.rem_bound_abs] in 2 then 4 particular cases. *)
Theorem Zrem_lt_pos a b : 0<=a -> b<>0 -> 0 <= Z.rem a b < Z.abs b.
Proof.
intros; generalize (Z.rem_nonneg a b) (Z.rem_bound_abs a b);
lia.
Qed.
Theorem Zrem_lt_neg a b : a<=0 -> b<>0 -> -Z.abs b < Z.rem a b <= 0.
Proof.
intros; generalize (Z.rem_nonpos a b) (Z.rem_bound_abs a b);
lia.
Qed.
Theorem Zrem_lt_pos_pos a b : 0<=a -> 0<b -> 0 <= Z.rem a b < b.
Proof.
intros; generalize (Zrem_lt_pos a b); lia.
Qed.
Theorem Zrem_lt_pos_neg a b : 0<=a -> b<0 -> 0 <= Z.rem a b < -b.
Proof.
intros; generalize (Zrem_lt_pos a b); lia.
Qed.
Theorem Zrem_lt_neg_pos a b : a<=0 -> 0<b -> -b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); lia.
Qed.
Theorem Zrem_lt_neg_neg a b : a<=0 -> b<0 -> b < Z.rem a b <= 0.
Proof.
intros; generalize (Zrem_lt_neg a b); lia.
Qed.
(** * Unicity results *)
Definition Remainder a b r :=
(0 <= a /\ 0 <= r < Z.abs b) \/ (a <= 0 /\ -Z.abs b < r <= 0).
Definition Remainder_alt a b r :=
Z.abs r < Z.abs b /\ 0 <= r * a.
Lemma Remainder_equiv : forall a b r,
Remainder a b r <-> Remainder_alt a b r.
Proof.
unfold Remainder, Remainder_alt; intuition.
- lia.
- lia.
- rewrite <-(Z.mul_opp_opp). apply Z.mul_nonneg_nonneg; lia.
- assert (0 <= Z.sgn r * Z.sgn a).
{ rewrite <-Z.sgn_mul, Z.sgn_nonneg; auto. }
destruct r; simpl Z.sgn in *; lia.
Qed.
Theorem Zquot_mod_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b /\ r = Z.rem a b.
Proof.
destruct 1 as [(H,H0)|(H,H0)]; intros.
apply Zdiv_mod_unique with b; auto.
apply Zrem_lt_pos; auto.
lia.
rewrite <- H1; apply Z.quot_rem'.
rewrite <- (Z.opp_involutive a).
rewrite Zquot_opp_l, Zrem_opp_l.
generalize (Zdiv_mod_unique b (-q) (-a÷b) (-r) (Z.rem (-a) b)).
generalize (Zrem_lt_pos (-a) b).
rewrite <-Z.quot_rem', Z.mul_opp_r, <-Z.opp_add_distr, <-H1.
lia.
Qed.
Theorem Zquot_unique_full a b q r :
Remainder a b r -> a = b*q + r -> q = a÷b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
Theorem Zrem_unique_full a b q r :
Remainder a b r -> a = b*q + r -> r = Z.rem a b.
Proof.
intros; destruct (Zquot_mod_unique_full a b q r); auto.
Qed.
(** * Order results about Zrem and Zquot *)
(* Division of positive numbers is positive. *)
Lemma Z_quot_pos a b : 0 <= a -> 0 <= b -> 0 <= a÷b.
Proof. intros. zero_or_not b. apply Z.quot_pos; auto with zarith. Qed.
(** As soon as the divisor is greater or equal than 2,
the division is strictly decreasing. *)
Lemma Z_quot_lt a b : 0 < a -> 2 <= b -> a÷b < a.
Proof. intros. apply Z.quot_lt; auto with zarith. Qed.
(** [<=] is compatible with a positive division. *)
Lemma Z_quot_monotone a b c : 0<=c -> a<=b -> a÷c <= b÷c.
Proof. intros. zero_or_not c. apply Z.quot_le_mono; auto with zarith. Qed.
(** With our choice of division, rounding of (a÷b) is always done toward 0: *)
Lemma Z_mult_quot_le a b : 0 <= a -> 0 <= b*(a÷b) <= a.
Proof. intros. zero_or_not b. apply Z.mul_quot_le; auto with zarith. Qed.
Lemma Z_mult_quot_ge a b : a <= 0 -> a <= b*(a÷b) <= 0.
Proof. intros. zero_or_not b. apply Z.mul_quot_ge; auto with zarith. Qed.
(** The previous inequalities between [b*(a÷b)] and [a] are exact
iff the modulo is zero. *)
Lemma Z_quot_exact_full a b : a = b*(a÷b) <-> Z.rem a b = 0.
Proof. intros. zero_or_not b. intuition. apply Z.quot_exact; auto. Qed.
(** A modulo cannot grow beyond its starting point. *)
Theorem Zrem_le a b : 0 <= a -> 0 <= b -> Z.rem a b <= a.
Proof. intros. zero_or_not b. apply Z.rem_le; auto with zarith. Qed.
(** Some additional inequalities about Zdiv. *)
Theorem Zquot_le_upper_bound:
forall a b q, 0 < b -> a <= q*b -> a÷b <= q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_upper_bound. Qed.
Theorem Zquot_lt_upper_bound:
forall a b q, 0 <= a -> 0 < b -> a < q*b -> a÷b < q.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_lt_upper_bound. Qed.
Theorem Zquot_le_lower_bound:
forall a b q, 0 < b -> q*b <= a -> q <= a÷b.
Proof. intros a b q; rewrite Z.mul_comm; apply Z.quot_le_lower_bound. Qed.
Theorem Zquot_sgn: forall a b,
0 <= Z.sgn (a÷b) * Z.sgn a * Z.sgn b.
Proof.
destruct a as [ |a|a]; destruct b as [ |b|b]; simpl; auto with zarith;
unfold Z.quot; simpl; destruct N.pos_div_eucl; simpl; destruct n; simpl; auto with zarith.
Qed.
(** * Relations between usual operations and Zmod and Zdiv *)
(** First, a result that used to be always valid with Zdiv,
but must be restricted here.
For instance, now (9+(-5)*2) rem 2 = -1 <> 1 = 9 rem 2 *)
Lemma Z_rem_plus : forall a b c:Z,
0 <= (a+b*c) * a ->
Z.rem (a + b * c) c = Z.rem a c.
Proof. intros. zero_or_not c. apply Z.rem_add; auto with zarith. Qed.
Lemma Z_quot_plus : forall a b c:Z,
0 <= (a+b*c) * a -> c<>0 ->
(a + b * c) ÷ c = a ÷ c + b.
Proof. intros. apply Z.quot_add; auto with zarith. Qed.
Theorem Z_quot_plus_l: forall a b c : Z,
0 <= (a*b+c)*c -> b<>0 ->
b<>0 -> (a * b + c) ÷ b = a + c ÷ b.
Proof. intros. apply Z.quot_add_l; auto with zarith. Qed.
(** Cancellations. *)
Lemma Zquot_mult_cancel_r : forall a b c:Z,
c<>0 -> (a*c)÷(b*c) = a÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_cancel_r; auto. Qed.
Lemma Zquot_mult_cancel_l : forall a b c:Z,
c<>0 -> (c*a)÷(c*b) = a÷b.
Proof.
intros. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.quot_mul_cancel_l; auto.
Qed.
Lemma Zmult_rem_distr_l: forall a b c,
Z.rem (c*a) (c*b) = c * (Z.rem a b).
Proof.
intros. zero_or_not c. rewrite (Z.mul_comm c b). zero_or_not b.
rewrite (Z.mul_comm b c). apply Z.mul_rem_distr_l; auto.
Qed.
Lemma Zmult_rem_distr_r: forall a b c,
Z.rem (a*c) (b*c) = (Z.rem a b) * c.
Proof.
intros. zero_or_not b. rewrite (Z.mul_comm b c). zero_or_not c.
rewrite (Z.mul_comm c b). apply Z.mul_rem_distr_r; auto.
Qed.
(** Operations modulo. *)
Theorem Zrem_rem: forall a n, Z.rem (Z.rem a n) n = Z.rem a n.
Proof. intros. zero_or_not n. apply Z.rem_rem; auto. Qed.
Theorem Zmult_rem: forall a b n,
Z.rem (a * b) n = Z.rem (Z.rem a n * Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.mul_rem; auto. Qed.
(** addition and modulo
Generally speaking, unlike with Zdiv, we don't have
(a+b) rem n = (a rem n + b rem n) rem n
for any a and b.
For instance, take (8 + (-10)) rem 3 = -2 whereas
(8 rem 3 + (-10 rem 3)) rem 3 = 1. *)
Theorem Zplus_rem: forall a b n,
0 <= a * b ->
Z.rem (a + b) n = Z.rem (Z.rem a n + Z.rem b n) n.
Proof. intros. zero_or_not n. apply Z.add_rem; auto. Qed.
Lemma Zplus_rem_idemp_l: forall a b n,
0 <= a * b ->
Z.rem (Z.rem a n + b) n = Z.rem (a + b) n.
Proof. intros. zero_or_not n. apply Z.add_rem_idemp_l; auto. Qed.
Lemma Zplus_rem_idemp_r: forall a b n,
0 <= a*b ->
Z.rem (b + Z.rem a n) n = Z.rem (b + a) n.
Proof.
intros. zero_or_not n. apply Z.add_rem_idemp_r; auto.
rewrite Z.mul_comm; auto.
Qed.
Lemma Zmult_rem_idemp_l: forall a b n, Z.rem (Z.rem a n * b) n = Z.rem (a * b) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_l; auto. Qed.
Lemma Zmult_rem_idemp_r: forall a b n, Z.rem (b * Z.rem a n) n = Z.rem (b * a) n.
Proof. intros. zero_or_not n. apply Z.mul_rem_idemp_r; auto. Qed.
(** Unlike with Zdiv, the following result is true without restrictions. *)
Lemma Zquot_Zquot : forall a b c, (a÷b)÷c = a÷(b*c).
Proof.
intros. zero_or_not b. rewrite Z.mul_comm. zero_or_not c.
rewrite Z.mul_comm. apply Z.quot_quot; auto.
Qed.
(** A last inequality: *)
Theorem Zquot_mult_le:
forall a b c, 0<=a -> 0<=b -> 0<=c -> c*(a÷b) <= (c*a)÷b.
Proof. intros. zero_or_not b. apply Z.quot_mul_le; auto with zarith. Qed.
(** Z.rem is related to divisibility (see more in Znumtheory) *)
Lemma Zrem_divides : forall a b,
Z.rem a b = 0 <-> exists c, a = b*c.
Proof.
intros. zero_or_not b. firstorder.
rewrite Z.rem_divide; trivial.
split; intros (c,Hc); exists c; subst; auto with zarith.
Qed.
(** Particular case : dividing by 2 is related with parity *)
Lemma Zquot2_odd_remainder : forall a,
Remainder a 2 (if Z.odd a then Z.sgn a else 0).
Proof.
intros [ |p|p]. simpl.
left. simpl. auto with zarith.
left. destruct p; simpl; auto with zarith.
right. destruct p; simpl; split; now auto with zarith.
Qed.
Lemma Zrem_odd : forall a, Z.rem a 2 = if Z.odd a then Z.sgn a else 0.
Proof.
intros. symmetry.
apply Zrem_unique_full with (Z.quot2 a).
apply Zquot2_odd_remainder.
apply Zquot2_odd_eqn.
Qed.
Lemma Zrem_even : forall a, Z.rem a 2 = if Z.even a then 0 else Z.sgn a.
Proof.
intros a. rewrite Zrem_odd, Zodd_even_bool. now destruct Z.even.
Qed.
Lemma Zeven_rem : forall a, Z.even a = Z.eqb (Z.rem a 2) 0.
Proof.
intros a. rewrite Zrem_even.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
Lemma Zodd_rem : forall a, Z.odd a = negb (Z.eqb (Z.rem a 2) 0).
Proof.
intros a. rewrite Zrem_odd.
destruct a as [ |p|p]; trivial; now destruct p.
Qed.
(** * Interaction with "historic" Zdiv *)
(** They agree at least on positive numbers: *)
Theorem Zquotrem_Zdiv_eucl_pos : forall a b:Z, 0 <= a -> 0 < b ->
a÷b = a/b /\ Z.rem a b = a mod b.
Proof.
intros.
apply Zdiv_mod_unique with b.
apply Zrem_lt_pos; auto with zarith.
rewrite Z.abs_eq; auto with *; apply Z_mod_lt; auto with *.
rewrite <- Z_div_mod_eq; auto with *.
symmetry; apply Z.quot_rem; auto with *.
Qed.
Theorem Zquot_Zdiv_pos : forall a b, 0 <= a -> 0 <= b ->
a÷b = a/b.
Proof.
intros a b Ha Hb. Z.le_elim Hb.
- generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb); intuition.
- subst; now rewrite Zquot_0_r, Zdiv_0_r.
Qed.
Theorem Zrem_Zmod_pos : forall a b, 0 <= a -> 0 < b ->
Z.rem a b = a mod b.
Proof.
intros a b Ha Hb; generalize (Zquotrem_Zdiv_eucl_pos a b Ha Hb);
intuition.
Qed.
(** Modulos are null at the same places *)
Theorem Zrem_Zmod_zero : forall a b, b<>0 ->
(Z.rem a b = 0 <-> a mod b = 0).
Proof.
intros.
rewrite Zrem_divides, Zmod_divides; intuition.
Qed.
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* UDP ethernet frame transmitter (UDP frame in, IP frame out)
*/
module udp_ip_tx
(
input wire clk,
input wire rst,
/*
* UDP frame input
*/
input wire s_udp_hdr_valid,
output wire s_udp_hdr_ready,
input wire [47:0] s_eth_dest_mac,
input wire [47:0] s_eth_src_mac,
input wire [15:0] s_eth_type,
input wire [3:0] s_ip_version,
input wire [3:0] s_ip_ihl,
input wire [5:0] s_ip_dscp,
input wire [1:0] s_ip_ecn,
input wire [15:0] s_ip_identification,
input wire [2:0] s_ip_flags,
input wire [12:0] s_ip_fragment_offset,
input wire [7:0] s_ip_ttl,
input wire [7:0] s_ip_protocol,
input wire [15:0] s_ip_header_checksum,
input wire [31:0] s_ip_source_ip,
input wire [31:0] s_ip_dest_ip,
input wire [15:0] s_udp_source_port,
input wire [15:0] s_udp_dest_port,
input wire [15:0] s_udp_length,
input wire [15:0] s_udp_checksum,
input wire [7:0] s_udp_payload_axis_tdata,
input wire s_udp_payload_axis_tvalid,
output wire s_udp_payload_axis_tready,
input wire s_udp_payload_axis_tlast,
input wire s_udp_payload_axis_tuser,
/*
* IP frame output
*/
output wire m_ip_hdr_valid,
input wire m_ip_hdr_ready,
output wire [47:0] m_eth_dest_mac,
output wire [47:0] m_eth_src_mac,
output wire [15:0] m_eth_type,
output wire [3:0] m_ip_version,
output wire [3:0] m_ip_ihl,
output wire [5:0] m_ip_dscp,
output wire [1:0] m_ip_ecn,
output wire [15:0] m_ip_length,
output wire [15:0] m_ip_identification,
output wire [2:0] m_ip_flags,
output wire [12:0] m_ip_fragment_offset,
output wire [7:0] m_ip_ttl,
output wire [7:0] m_ip_protocol,
output wire [15:0] m_ip_header_checksum,
output wire [31:0] m_ip_source_ip,
output wire [31:0] m_ip_dest_ip,
output wire [7:0] m_ip_payload_axis_tdata,
output wire m_ip_payload_axis_tvalid,
input wire m_ip_payload_axis_tready,
output wire m_ip_payload_axis_tlast,
output wire m_ip_payload_axis_tuser,
/*
* Status signals
*/
output wire busy,
output wire error_payload_early_termination
);
/*
UDP Frame
Field Length
Destination MAC address 6 octets
Source MAC address 6 octets
Ethertype (0x0800) 2 octets
Version (4) 4 bits
IHL (5-15) 4 bits
DSCP (0) 6 bits
ECN (0) 2 bits
length 2 octets
identification (0?) 2 octets
flags (010) 3 bits
fragment offset (0) 13 bits
time to live (64?) 1 octet
protocol 1 octet
header checksum 2 octets
source IP 4 octets
destination IP 4 octets
options (IHL-5)*4 octets
source port 2 octets
desination port 2 octets
length 2 octets
checksum 2 octets
payload length octets
This module receives a UDP frame with header fields in parallel along with the
payload in an AXI stream, combines the header with the payload, passes through
the IP headers, and transmits the complete IP payload on an AXI interface.
*/
localparam [2:0]
STATE_IDLE = 3'd0,
STATE_WRITE_HEADER = 3'd1,
STATE_WRITE_PAYLOAD = 3'd2,
STATE_WRITE_PAYLOAD_LAST = 3'd3,
STATE_WAIT_LAST = 3'd4;
reg [2:0] state_reg = STATE_IDLE, state_next;
// datapath control signals
reg store_udp_hdr;
reg store_last_word;
reg [2:0] hdr_ptr_reg = 3'd0, hdr_ptr_next;
reg [15:0] word_count_reg = 16'd0, word_count_next;
reg [7:0] last_word_data_reg = 8'd0;
reg [15:0] udp_source_port_reg = 16'd0;
reg [15:0] udp_dest_port_reg = 16'd0;
reg [15:0] udp_length_reg = 16'd0;
reg [15:0] udp_checksum_reg = 16'd0;
reg s_udp_hdr_ready_reg = 1'b0, s_udp_hdr_ready_next;
reg s_udp_payload_axis_tready_reg = 1'b0, s_udp_payload_axis_tready_next;
reg m_ip_hdr_valid_reg = 1'b0, m_ip_hdr_valid_next;
reg [47:0] m_eth_dest_mac_reg = 48'd0;
reg [47:0] m_eth_src_mac_reg = 48'd0;
reg [15:0] m_eth_type_reg = 16'd0;
reg [3:0] m_ip_version_reg = 4'd0;
reg [3:0] m_ip_ihl_reg = 4'd0;
reg [5:0] m_ip_dscp_reg = 6'd0;
reg [1:0] m_ip_ecn_reg = 2'd0;
reg [15:0] m_ip_length_reg = 16'd0;
reg [15:0] m_ip_identification_reg = 16'd0;
reg [2:0] m_ip_flags_reg = 3'd0;
reg [12:0] m_ip_fragment_offset_reg = 13'd0;
reg [7:0] m_ip_ttl_reg = 8'd0;
reg [7:0] m_ip_protocol_reg = 8'd0;
reg [15:0] m_ip_header_checksum_reg = 16'd0;
reg [31:0] m_ip_source_ip_reg = 32'd0;
reg [31:0] m_ip_dest_ip_reg = 32'd0;
reg busy_reg = 1'b0;
reg error_payload_early_termination_reg = 1'b0, error_payload_early_termination_next;
// internal datapath
reg [7:0] m_ip_payload_axis_tdata_int;
reg m_ip_payload_axis_tvalid_int;
reg m_ip_payload_axis_tready_int_reg = 1'b0;
reg m_ip_payload_axis_tlast_int;
reg m_ip_payload_axis_tuser_int;
wire m_ip_payload_axis_tready_int_early;
assign s_udp_hdr_ready = s_udp_hdr_ready_reg;
assign s_udp_payload_axis_tready = s_udp_payload_axis_tready_reg;
assign m_ip_hdr_valid = m_ip_hdr_valid_reg;
assign m_eth_dest_mac = m_eth_dest_mac_reg;
assign m_eth_src_mac = m_eth_src_mac_reg;
assign m_eth_type = m_eth_type_reg;
assign m_ip_version = m_ip_version_reg;
assign m_ip_ihl = m_ip_ihl_reg;
assign m_ip_dscp = m_ip_dscp_reg;
assign m_ip_ecn = m_ip_ecn_reg;
assign m_ip_length = m_ip_length_reg;
assign m_ip_identification = m_ip_identification_reg;
assign m_ip_flags = m_ip_flags_reg;
assign m_ip_fragment_offset = m_ip_fragment_offset_reg;
assign m_ip_ttl = m_ip_ttl_reg;
assign m_ip_protocol = m_ip_protocol_reg;
assign m_ip_header_checksum = m_ip_header_checksum_reg;
assign m_ip_source_ip = m_ip_source_ip_reg;
assign m_ip_dest_ip = m_ip_dest_ip_reg;
assign busy = busy_reg;
assign error_payload_early_termination = error_payload_early_termination_reg;
always @* begin
state_next = STATE_IDLE;
s_udp_hdr_ready_next = 1'b0;
s_udp_payload_axis_tready_next = 1'b0;
store_udp_hdr = 1'b0;
store_last_word = 1'b0;
hdr_ptr_next = hdr_ptr_reg;
word_count_next = word_count_reg;
m_ip_hdr_valid_next = m_ip_hdr_valid_reg && !m_ip_hdr_ready;
error_payload_early_termination_next = 1'b0;
m_ip_payload_axis_tdata_int = 8'd0;
m_ip_payload_axis_tvalid_int = 1'b0;
m_ip_payload_axis_tlast_int = 1'b0;
m_ip_payload_axis_tuser_int = 1'b0;
case (state_reg)
STATE_IDLE: begin
// idle state - wait for data
hdr_ptr_next = 3'd0;
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
if (s_udp_hdr_ready && s_udp_hdr_valid) begin
store_udp_hdr = 1'b1;
s_udp_hdr_ready_next = 1'b0;
m_ip_hdr_valid_next = 1'b1;
if (m_ip_payload_axis_tready_int_reg) begin
m_ip_payload_axis_tvalid_int = 1'b1;
m_ip_payload_axis_tdata_int = s_udp_source_port[15: 8];
hdr_ptr_next = 3'd1;
end
state_next = STATE_WRITE_HEADER;
end else begin
state_next = STATE_IDLE;
end
end
STATE_WRITE_HEADER: begin
// write header state
word_count_next = udp_length_reg - 16'd8;
if (m_ip_payload_axis_tready_int_reg) begin
// word transfer out
hdr_ptr_next = hdr_ptr_reg + 3'd1;
m_ip_payload_axis_tvalid_int = 1'b1;
state_next = STATE_WRITE_HEADER;
case (hdr_ptr_reg)
3'h0: m_ip_payload_axis_tdata_int = udp_source_port_reg[15: 8];
3'h1: m_ip_payload_axis_tdata_int = udp_source_port_reg[ 7: 0];
3'h2: m_ip_payload_axis_tdata_int = udp_dest_port_reg[15: 8];
3'h3: m_ip_payload_axis_tdata_int = udp_dest_port_reg[ 7: 0];
3'h4: m_ip_payload_axis_tdata_int = udp_length_reg[15: 8];
3'h5: m_ip_payload_axis_tdata_int = udp_length_reg[ 7: 0];
3'h6: m_ip_payload_axis_tdata_int = udp_checksum_reg[15: 8];
3'h7: begin
m_ip_payload_axis_tdata_int = udp_checksum_reg[ 7: 0];
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
state_next = STATE_WRITE_PAYLOAD;
end
endcase
end else begin
state_next = STATE_WRITE_HEADER;
end
end
STATE_WRITE_PAYLOAD: begin
// write payload
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
m_ip_payload_axis_tdata_int = s_udp_payload_axis_tdata;
m_ip_payload_axis_tvalid_int = s_udp_payload_axis_tvalid;
m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast;
m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
// word transfer through
word_count_next = word_count_reg - 16'd1;
if (s_udp_payload_axis_tlast) begin
if (word_count_reg != 16'd1) begin
// end of frame, but length does not match
m_ip_payload_axis_tuser_int = 1'b1;
error_payload_early_termination_next = 1'b1;
end
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
if (word_count_reg == 16'd1) begin
store_last_word = 1'b1;
m_ip_payload_axis_tvalid_int = 1'b0;
state_next = STATE_WRITE_PAYLOAD_LAST;
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
end else begin
state_next = STATE_WRITE_PAYLOAD;
end
end
STATE_WRITE_PAYLOAD_LAST: begin
// read and discard until end of frame
s_udp_payload_axis_tready_next = m_ip_payload_axis_tready_int_early;
m_ip_payload_axis_tdata_int = last_word_data_reg;
m_ip_payload_axis_tvalid_int = s_udp_payload_axis_tvalid && s_udp_payload_axis_tlast;
m_ip_payload_axis_tlast_int = s_udp_payload_axis_tlast;
m_ip_payload_axis_tuser_int = s_udp_payload_axis_tuser;
if (s_udp_payload_axis_tready && s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end else begin
state_next = STATE_WRITE_PAYLOAD_LAST;
end
end
STATE_WAIT_LAST: begin
// wait for end of frame; read and discard
s_udp_payload_axis_tready_next = 1'b1;
if (s_udp_payload_axis_tvalid) begin
if (s_udp_payload_axis_tlast) begin
s_udp_hdr_ready_next = !m_ip_hdr_valid_next;
s_udp_payload_axis_tready_next = 1'b0;
state_next = STATE_IDLE;
end else begin
state_next = STATE_WAIT_LAST;
end
end else begin
state_next = STATE_WAIT_LAST;
end
end
endcase
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
s_udp_hdr_ready_reg <= 1'b0;
s_udp_payload_axis_tready_reg <= 1'b0;
m_ip_hdr_valid_reg <= 1'b0;
busy_reg <= 1'b0;
error_payload_early_termination_reg <= 1'b0;
end else begin
state_reg <= state_next;
s_udp_hdr_ready_reg <= s_udp_hdr_ready_next;
s_udp_payload_axis_tready_reg <= s_udp_payload_axis_tready_next;
m_ip_hdr_valid_reg <= m_ip_hdr_valid_next;
busy_reg <= state_next != STATE_IDLE;
error_payload_early_termination_reg <= error_payload_early_termination_next;
end
hdr_ptr_reg <= hdr_ptr_next;
word_count_reg <= word_count_next;
// datapath
if (store_udp_hdr) begin
m_eth_dest_mac_reg <= s_eth_dest_mac;
m_eth_src_mac_reg <= s_eth_src_mac;
m_eth_type_reg <= s_eth_type;
m_ip_version_reg <= s_ip_version;
m_ip_ihl_reg <= s_ip_ihl;
m_ip_dscp_reg <= s_ip_dscp;
m_ip_ecn_reg <= s_ip_ecn;
m_ip_length_reg <= s_udp_length + 20;
m_ip_identification_reg <= s_ip_identification;
m_ip_flags_reg <= s_ip_flags;
m_ip_fragment_offset_reg <= s_ip_fragment_offset;
m_ip_ttl_reg <= s_ip_ttl;
m_ip_protocol_reg <= s_ip_protocol;
m_ip_header_checksum_reg <= s_ip_header_checksum;
m_ip_source_ip_reg <= s_ip_source_ip;
m_ip_dest_ip_reg <= s_ip_dest_ip;
udp_source_port_reg <= s_udp_source_port;
udp_dest_port_reg <= s_udp_dest_port;
udp_length_reg <= s_udp_length;
udp_checksum_reg <= s_udp_checksum;
end
if (store_last_word) begin
last_word_data_reg <= m_ip_payload_axis_tdata_int;
end
end
// output datapath logic
reg [7:0] m_ip_payload_axis_tdata_reg = 8'd0;
reg m_ip_payload_axis_tvalid_reg = 1'b0, m_ip_payload_axis_tvalid_next;
reg m_ip_payload_axis_tlast_reg = 1'b0;
reg m_ip_payload_axis_tuser_reg = 1'b0;
reg [7:0] temp_m_ip_payload_axis_tdata_reg = 8'd0;
reg temp_m_ip_payload_axis_tvalid_reg = 1'b0, temp_m_ip_payload_axis_tvalid_next;
reg temp_m_ip_payload_axis_tlast_reg = 1'b0;
reg temp_m_ip_payload_axis_tuser_reg = 1'b0;
// datapath control
reg store_ip_payload_int_to_output;
reg store_ip_payload_int_to_temp;
reg store_ip_payload_axis_temp_to_output;
assign m_ip_payload_axis_tdata = m_ip_payload_axis_tdata_reg;
assign m_ip_payload_axis_tvalid = m_ip_payload_axis_tvalid_reg;
assign m_ip_payload_axis_tlast = m_ip_payload_axis_tlast_reg;
assign m_ip_payload_axis_tuser = m_ip_payload_axis_tuser_reg;
// enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
assign m_ip_payload_axis_tready_int_early = m_ip_payload_axis_tready || (!temp_m_ip_payload_axis_tvalid_reg && (!m_ip_payload_axis_tvalid_reg || !m_ip_payload_axis_tvalid_int));
always @* begin
// transfer sink ready state to source
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
store_ip_payload_int_to_output = 1'b0;
store_ip_payload_int_to_temp = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b0;
if (m_ip_payload_axis_tready_int_reg) begin
// input is ready
if (m_ip_payload_axis_tready || !m_ip_payload_axis_tvalid_reg) begin
// output is ready or currently not valid, transfer data to output
m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_output = 1'b1;
end else begin
// output is not ready, store input in temp
temp_m_ip_payload_axis_tvalid_next = m_ip_payload_axis_tvalid_int;
store_ip_payload_int_to_temp = 1'b1;
end
end else if (m_ip_payload_axis_tready) begin
// input is not ready, but output is ready
m_ip_payload_axis_tvalid_next = temp_m_ip_payload_axis_tvalid_reg;
temp_m_ip_payload_axis_tvalid_next = 1'b0;
store_ip_payload_axis_temp_to_output = 1'b1;
end
end
always @(posedge clk) begin
if (rst) begin
m_ip_payload_axis_tvalid_reg <= 1'b0;
m_ip_payload_axis_tready_int_reg <= 1'b0;
temp_m_ip_payload_axis_tvalid_reg <= 1'b0;
end else begin
m_ip_payload_axis_tvalid_reg <= m_ip_payload_axis_tvalid_next;
m_ip_payload_axis_tready_int_reg <= m_ip_payload_axis_tready_int_early;
temp_m_ip_payload_axis_tvalid_reg <= temp_m_ip_payload_axis_tvalid_next;
end
// datapath
if (store_ip_payload_int_to_output) begin
m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end else if (store_ip_payload_axis_temp_to_output) begin
m_ip_payload_axis_tdata_reg <= temp_m_ip_payload_axis_tdata_reg;
m_ip_payload_axis_tlast_reg <= temp_m_ip_payload_axis_tlast_reg;
m_ip_payload_axis_tuser_reg <= temp_m_ip_payload_axis_tuser_reg;
end
if (store_ip_payload_int_to_temp) begin
temp_m_ip_payload_axis_tdata_reg <= m_ip_payload_axis_tdata_int;
temp_m_ip_payload_axis_tlast_reg <= m_ip_payload_axis_tlast_int;
temp_m_ip_payload_axis_tuser_reg <= m_ip_payload_axis_tuser_int;
end
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Fri Sep 22 20:11:26 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ tx_axis_gen_sim_netlist.v
// Design : tx_axis_gen
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "tx_axis_gen,fifo_generator_v13_1_2,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "fifo_generator_v13_1_2,Vivado 2016.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
almost_full,
empty);
(* x_interface_info = "xilinx.com:signal:clock:1.0 core_clk CLK" *) input clk;
input rst;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *) input [64:0]din;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *) input wr_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *) input rd_en;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *) output [64:0]dout;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *) output full;
(* x_interface_info = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE ALMOST_FULL" *) output almost_full;
(* x_interface_info = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *) output empty;
wire almost_full;
wire clk;
wire [64:0]din;
wire [64:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire NLW_U0_almost_empty_UNCONNECTED;
wire NLW_U0_axi_ar_dbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_overflow_UNCONNECTED;
wire NLW_U0_axi_ar_prog_empty_UNCONNECTED;
wire NLW_U0_axi_ar_prog_full_UNCONNECTED;
wire NLW_U0_axi_ar_sbiterr_UNCONNECTED;
wire NLW_U0_axi_ar_underflow_UNCONNECTED;
wire NLW_U0_axi_aw_dbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_overflow_UNCONNECTED;
wire NLW_U0_axi_aw_prog_empty_UNCONNECTED;
wire NLW_U0_axi_aw_prog_full_UNCONNECTED;
wire NLW_U0_axi_aw_sbiterr_UNCONNECTED;
wire NLW_U0_axi_aw_underflow_UNCONNECTED;
wire NLW_U0_axi_b_dbiterr_UNCONNECTED;
wire NLW_U0_axi_b_overflow_UNCONNECTED;
wire NLW_U0_axi_b_prog_empty_UNCONNECTED;
wire NLW_U0_axi_b_prog_full_UNCONNECTED;
wire NLW_U0_axi_b_sbiterr_UNCONNECTED;
wire NLW_U0_axi_b_underflow_UNCONNECTED;
wire NLW_U0_axi_r_dbiterr_UNCONNECTED;
wire NLW_U0_axi_r_overflow_UNCONNECTED;
wire NLW_U0_axi_r_prog_empty_UNCONNECTED;
wire NLW_U0_axi_r_prog_full_UNCONNECTED;
wire NLW_U0_axi_r_sbiterr_UNCONNECTED;
wire NLW_U0_axi_r_underflow_UNCONNECTED;
wire NLW_U0_axi_w_dbiterr_UNCONNECTED;
wire NLW_U0_axi_w_overflow_UNCONNECTED;
wire NLW_U0_axi_w_prog_empty_UNCONNECTED;
wire NLW_U0_axi_w_prog_full_UNCONNECTED;
wire NLW_U0_axi_w_sbiterr_UNCONNECTED;
wire NLW_U0_axi_w_underflow_UNCONNECTED;
wire NLW_U0_axis_dbiterr_UNCONNECTED;
wire NLW_U0_axis_overflow_UNCONNECTED;
wire NLW_U0_axis_prog_empty_UNCONNECTED;
wire NLW_U0_axis_prog_full_UNCONNECTED;
wire NLW_U0_axis_sbiterr_UNCONNECTED;
wire NLW_U0_axis_underflow_UNCONNECTED;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_m_axi_arvalid_UNCONNECTED;
wire NLW_U0_m_axi_awvalid_UNCONNECTED;
wire NLW_U0_m_axi_bready_UNCONNECTED;
wire NLW_U0_m_axi_rready_UNCONNECTED;
wire NLW_U0_m_axi_wlast_UNCONNECTED;
wire NLW_U0_m_axi_wvalid_UNCONNECTED;
wire NLW_U0_m_axis_tlast_UNCONNECTED;
wire NLW_U0_m_axis_tvalid_UNCONNECTED;
wire NLW_U0_overflow_UNCONNECTED;
wire NLW_U0_prog_empty_UNCONNECTED;
wire NLW_U0_prog_full_UNCONNECTED;
wire NLW_U0_rd_rst_busy_UNCONNECTED;
wire NLW_U0_s_axi_arready_UNCONNECTED;
wire NLW_U0_s_axi_awready_UNCONNECTED;
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
wire NLW_U0_s_axi_rlast_UNCONNECTED;
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
wire NLW_U0_s_axi_wready_UNCONNECTED;
wire NLW_U0_s_axis_tready_UNCONNECTED;
wire NLW_U0_sbiterr_UNCONNECTED;
wire NLW_U0_underflow_UNCONNECTED;
wire NLW_U0_valid_UNCONNECTED;
wire NLW_U0_wr_ack_UNCONNECTED;
wire NLW_U0_wr_rst_busy_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_ar_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_aw_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_rd_data_count_UNCONNECTED;
wire [4:0]NLW_U0_axi_b_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_r_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axi_w_wr_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_rd_data_count_UNCONNECTED;
wire [10:0]NLW_U0_axis_wr_data_count_UNCONNECTED;
wire [4:0]NLW_U0_data_count_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_araddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_arlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_aruser_UNCONNECTED;
wire [31:0]NLW_U0_m_axi_awaddr_UNCONNECTED;
wire [1:0]NLW_U0_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awlock_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awprot_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_U0_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_U0_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_awuser_UNCONNECTED;
wire [63:0]NLW_U0_m_axi_wdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wid_UNCONNECTED;
wire [7:0]NLW_U0_m_axi_wstrb_UNCONNECTED;
wire [0:0]NLW_U0_m_axi_wuser_UNCONNECTED;
wire [7:0]NLW_U0_m_axis_tdata_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tdest_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tid_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tkeep_UNCONNECTED;
wire [0:0]NLW_U0_m_axis_tstrb_UNCONNECTED;
wire [3:0]NLW_U0_m_axis_tuser_UNCONNECTED;
wire [4:0]NLW_U0_rd_data_count_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_bid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_buser_UNCONNECTED;
wire [63:0]NLW_U0_s_axi_rdata_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_rid_UNCONNECTED;
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
wire [0:0]NLW_U0_s_axi_ruser_UNCONNECTED;
wire [4:0]NLW_U0_wr_data_count_UNCONNECTED;
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "1" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "5" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "65" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "32" *)
(* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *)
(* C_DIN_WIDTH_WDCH = "64" *)
(* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "65" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "1" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "1" *)
(* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WACH = "1" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "2" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *)
(* C_PRELOAD_REGS = "1" *)
(* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "14" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "5" *)
(* C_RD_DEPTH = "16" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "4" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "2" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "1" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "5" *)
(* C_WR_DEPTH = "16" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "4" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "10" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2 U0
(.almost_empty(NLW_U0_almost_empty_UNCONNECTED),
.almost_full(almost_full),
.axi_ar_data_count(NLW_U0_axi_ar_data_count_UNCONNECTED[4:0]),
.axi_ar_dbiterr(NLW_U0_axi_ar_dbiterr_UNCONNECTED),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(NLW_U0_axi_ar_overflow_UNCONNECTED),
.axi_ar_prog_empty(NLW_U0_axi_ar_prog_empty_UNCONNECTED),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(NLW_U0_axi_ar_prog_full_UNCONNECTED),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(NLW_U0_axi_ar_rd_data_count_UNCONNECTED[4:0]),
.axi_ar_sbiterr(NLW_U0_axi_ar_sbiterr_UNCONNECTED),
.axi_ar_underflow(NLW_U0_axi_ar_underflow_UNCONNECTED),
.axi_ar_wr_data_count(NLW_U0_axi_ar_wr_data_count_UNCONNECTED[4:0]),
.axi_aw_data_count(NLW_U0_axi_aw_data_count_UNCONNECTED[4:0]),
.axi_aw_dbiterr(NLW_U0_axi_aw_dbiterr_UNCONNECTED),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(NLW_U0_axi_aw_overflow_UNCONNECTED),
.axi_aw_prog_empty(NLW_U0_axi_aw_prog_empty_UNCONNECTED),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(NLW_U0_axi_aw_prog_full_UNCONNECTED),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(NLW_U0_axi_aw_rd_data_count_UNCONNECTED[4:0]),
.axi_aw_sbiterr(NLW_U0_axi_aw_sbiterr_UNCONNECTED),
.axi_aw_underflow(NLW_U0_axi_aw_underflow_UNCONNECTED),
.axi_aw_wr_data_count(NLW_U0_axi_aw_wr_data_count_UNCONNECTED[4:0]),
.axi_b_data_count(NLW_U0_axi_b_data_count_UNCONNECTED[4:0]),
.axi_b_dbiterr(NLW_U0_axi_b_dbiterr_UNCONNECTED),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(NLW_U0_axi_b_overflow_UNCONNECTED),
.axi_b_prog_empty(NLW_U0_axi_b_prog_empty_UNCONNECTED),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(NLW_U0_axi_b_prog_full_UNCONNECTED),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(NLW_U0_axi_b_rd_data_count_UNCONNECTED[4:0]),
.axi_b_sbiterr(NLW_U0_axi_b_sbiterr_UNCONNECTED),
.axi_b_underflow(NLW_U0_axi_b_underflow_UNCONNECTED),
.axi_b_wr_data_count(NLW_U0_axi_b_wr_data_count_UNCONNECTED[4:0]),
.axi_r_data_count(NLW_U0_axi_r_data_count_UNCONNECTED[10:0]),
.axi_r_dbiterr(NLW_U0_axi_r_dbiterr_UNCONNECTED),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(NLW_U0_axi_r_overflow_UNCONNECTED),
.axi_r_prog_empty(NLW_U0_axi_r_prog_empty_UNCONNECTED),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(NLW_U0_axi_r_prog_full_UNCONNECTED),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(NLW_U0_axi_r_rd_data_count_UNCONNECTED[10:0]),
.axi_r_sbiterr(NLW_U0_axi_r_sbiterr_UNCONNECTED),
.axi_r_underflow(NLW_U0_axi_r_underflow_UNCONNECTED),
.axi_r_wr_data_count(NLW_U0_axi_r_wr_data_count_UNCONNECTED[10:0]),
.axi_w_data_count(NLW_U0_axi_w_data_count_UNCONNECTED[10:0]),
.axi_w_dbiterr(NLW_U0_axi_w_dbiterr_UNCONNECTED),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(NLW_U0_axi_w_overflow_UNCONNECTED),
.axi_w_prog_empty(NLW_U0_axi_w_prog_empty_UNCONNECTED),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(NLW_U0_axi_w_prog_full_UNCONNECTED),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(NLW_U0_axi_w_rd_data_count_UNCONNECTED[10:0]),
.axi_w_sbiterr(NLW_U0_axi_w_sbiterr_UNCONNECTED),
.axi_w_underflow(NLW_U0_axi_w_underflow_UNCONNECTED),
.axi_w_wr_data_count(NLW_U0_axi_w_wr_data_count_UNCONNECTED[10:0]),
.axis_data_count(NLW_U0_axis_data_count_UNCONNECTED[10:0]),
.axis_dbiterr(NLW_U0_axis_dbiterr_UNCONNECTED),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(NLW_U0_axis_overflow_UNCONNECTED),
.axis_prog_empty(NLW_U0_axis_prog_empty_UNCONNECTED),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(NLW_U0_axis_prog_full_UNCONNECTED),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(NLW_U0_axis_rd_data_count_UNCONNECTED[10:0]),
.axis_sbiterr(NLW_U0_axis_sbiterr_UNCONNECTED),
.axis_underflow(NLW_U0_axis_underflow_UNCONNECTED),
.axis_wr_data_count(NLW_U0_axis_wr_data_count_UNCONNECTED[10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(clk),
.data_count(NLW_U0_data_count_UNCONNECTED[4:0]),
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(1'b0),
.m_aclk_en(1'b0),
.m_axi_araddr(NLW_U0_m_axi_araddr_UNCONNECTED[31:0]),
.m_axi_arburst(NLW_U0_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_U0_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_U0_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_U0_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_U0_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(NLW_U0_m_axi_arprot_UNCONNECTED[2:0]),
.m_axi_arqos(NLW_U0_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(1'b0),
.m_axi_arregion(NLW_U0_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_U0_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_U0_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(NLW_U0_m_axi_arvalid_UNCONNECTED),
.m_axi_awaddr(NLW_U0_m_axi_awaddr_UNCONNECTED[31:0]),
.m_axi_awburst(NLW_U0_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_U0_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_U0_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_U0_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_U0_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(NLW_U0_m_axi_awprot_UNCONNECTED[2:0]),
.m_axi_awqos(NLW_U0_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(1'b0),
.m_axi_awregion(NLW_U0_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_U0_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_U0_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(NLW_U0_m_axi_awvalid_UNCONNECTED),
.m_axi_bid(1'b0),
.m_axi_bready(NLW_U0_m_axi_bready_UNCONNECTED),
.m_axi_bresp({1'b0,1'b0}),
.m_axi_buser(1'b0),
.m_axi_bvalid(1'b0),
.m_axi_rdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b0),
.m_axi_rready(NLW_U0_m_axi_rready_UNCONNECTED),
.m_axi_rresp({1'b0,1'b0}),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_wdata(NLW_U0_m_axi_wdata_UNCONNECTED[63:0]),
.m_axi_wid(NLW_U0_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_U0_m_axi_wlast_UNCONNECTED),
.m_axi_wready(1'b0),
.m_axi_wstrb(NLW_U0_m_axi_wstrb_UNCONNECTED[7:0]),
.m_axi_wuser(NLW_U0_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(NLW_U0_m_axi_wvalid_UNCONNECTED),
.m_axis_tdata(NLW_U0_m_axis_tdata_UNCONNECTED[7:0]),
.m_axis_tdest(NLW_U0_m_axis_tdest_UNCONNECTED[0]),
.m_axis_tid(NLW_U0_m_axis_tid_UNCONNECTED[0]),
.m_axis_tkeep(NLW_U0_m_axis_tkeep_UNCONNECTED[0]),
.m_axis_tlast(NLW_U0_m_axis_tlast_UNCONNECTED),
.m_axis_tready(1'b0),
.m_axis_tstrb(NLW_U0_m_axis_tstrb_UNCONNECTED[0]),
.m_axis_tuser(NLW_U0_m_axis_tuser_UNCONNECTED[3:0]),
.m_axis_tvalid(NLW_U0_m_axis_tvalid_UNCONNECTED),
.overflow(NLW_U0_overflow_UNCONNECTED),
.prog_empty(NLW_U0_prog_empty_UNCONNECTED),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0}),
.prog_full(NLW_U0_prog_full_UNCONNECTED),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(NLW_U0_rd_data_count_UNCONNECTED[4:0]),
.rd_en(rd_en),
.rd_rst(1'b0),
.rd_rst_busy(NLW_U0_rd_rst_busy_UNCONNECTED),
.rst(rst),
.s_aclk(1'b0),
.s_aclk_en(1'b0),
.s_aresetn(1'b0),
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arburst({1'b0,1'b0}),
.s_axi_arcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arid(1'b0),
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_arlock(1'b0),
.s_axi_arprot({1'b0,1'b0,1'b0}),
.s_axi_arqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
.s_axi_arregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_arsize({1'b0,1'b0,1'b0}),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awburst({1'b0,1'b0}),
.s_axi_awcache({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awid(1'b0),
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_awlock(1'b0),
.s_axi_awprot({1'b0,1'b0,1'b0}),
.s_axi_awqos({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
.s_axi_awregion({1'b0,1'b0,1'b0,1'b0}),
.s_axi_awsize({1'b0,1'b0,1'b0}),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[0]),
.s_axi_bready(1'b0),
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
.s_axi_buser(NLW_U0_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[63:0]),
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[0]),
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
.s_axi_rready(1'b0),
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
.s_axi_ruser(NLW_U0_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wid(1'b0),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(NLW_U0_s_axis_tready_UNCONNECTED),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.sleep(1'b0),
.srst(1'b0),
.underflow(NLW_U0_underflow_UNCONNECTED),
.valid(NLW_U0_valid_UNCONNECTED),
.wr_ack(NLW_U0_wr_ack_UNCONNECTED),
.wr_clk(1'b0),
.wr_data_count(NLW_U0_wr_data_count_UNCONNECTED[4:0]),
.wr_en(wr_en),
.wr_rst(1'b0),
.wr_rst_busy(NLW_U0_wr_rst_busy_UNCONNECTED));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem
(\goreg_dm.dout_i_reg[64] ,
clk,
EN,
din,
\gc0.count_d1_reg[3] ,
Q,
E,
AR);
output [64:0]\goreg_dm.dout_i_reg[64] ;
input clk;
input EN;
input [64:0]din;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]Q;
input [0:0]E;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire EN;
wire [3:0]Q;
wire clk;
wire [64:0]din;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [64:0]\goreg_dm.dout_i_reg[64] ;
wire [64:0]p_0_out;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[1:0]),
.DIB(din[3:2]),
.DIC(din[5:4]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[1:0]),
.DOB(p_0_out[3:2]),
.DOC(p_0_out[5:4]),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[13:12]),
.DIB(din[15:14]),
.DIC(din[17:16]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[13:12]),
.DOB(p_0_out[15:14]),
.DOC(p_0_out[17:16]),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[19:18]),
.DIB(din[21:20]),
.DIC(din[23:22]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[19:18]),
.DOB(p_0_out[21:20]),
.DOC(p_0_out[23:22]),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[25:24]),
.DIB(din[27:26]),
.DIC(din[29:28]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[25:24]),
.DOB(p_0_out[27:26]),
.DOC(p_0_out[29:28]),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[31:30]),
.DIB(din[33:32]),
.DIC(din[35:34]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[31:30]),
.DOB(p_0_out[33:32]),
.DOC(p_0_out[35:34]),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[37:36]),
.DIB(din[39:38]),
.DIC(din[41:40]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[37:36]),
.DOB(p_0_out[39:38]),
.DOC(p_0_out[41:40]),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[43:42]),
.DIB(din[45:44]),
.DIC(din[47:46]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[43:42]),
.DOB(p_0_out[45:44]),
.DOC(p_0_out[47:46]),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[49:48]),
.DIB(din[51:50]),
.DIC(din[53:52]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[49:48]),
.DOB(p_0_out[51:50]),
.DOC(p_0_out[53:52]),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[55:54]),
.DIB(din[57:56]),
.DIC(din[59:58]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[55:54]),
.DOB(p_0_out[57:56]),
.DOC(p_0_out[59:58]),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_64
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[61:60]),
.DIB(din[63:62]),
.DIC({1'b0,din[64]}),
.DID({1'b0,1'b0}),
.DOA(p_0_out[61:60]),
.DOB(p_0_out[63:62]),
.DOC({NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED[1],p_0_out[64]}),
.DOD(NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,Q}),
.DIA(din[7:6]),
.DIB(din[9:8]),
.DIC(din[11:10]),
.DID({1'b0,1'b0}),
.DOA(p_0_out[7:6]),
.DOB(p_0_out[9:8]),
.DOC(p_0_out[11:10]),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(clk),
.WE(EN));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[0]),
.Q(\goreg_dm.dout_i_reg[64] [0]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[10]),
.Q(\goreg_dm.dout_i_reg[64] [10]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[11]),
.Q(\goreg_dm.dout_i_reg[64] [11]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[12]),
.Q(\goreg_dm.dout_i_reg[64] [12]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[13]),
.Q(\goreg_dm.dout_i_reg[64] [13]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[14]),
.Q(\goreg_dm.dout_i_reg[64] [14]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[15]),
.Q(\goreg_dm.dout_i_reg[64] [15]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[16]),
.Q(\goreg_dm.dout_i_reg[64] [16]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[17]),
.Q(\goreg_dm.dout_i_reg[64] [17]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[18]),
.Q(\goreg_dm.dout_i_reg[64] [18]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[19]),
.Q(\goreg_dm.dout_i_reg[64] [19]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[1]),
.Q(\goreg_dm.dout_i_reg[64] [1]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[20]),
.Q(\goreg_dm.dout_i_reg[64] [20]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[21]),
.Q(\goreg_dm.dout_i_reg[64] [21]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[22]),
.Q(\goreg_dm.dout_i_reg[64] [22]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[23]),
.Q(\goreg_dm.dout_i_reg[64] [23]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[24]),
.Q(\goreg_dm.dout_i_reg[64] [24]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[25]),
.Q(\goreg_dm.dout_i_reg[64] [25]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[26]),
.Q(\goreg_dm.dout_i_reg[64] [26]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[27]),
.Q(\goreg_dm.dout_i_reg[64] [27]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[28]),
.Q(\goreg_dm.dout_i_reg[64] [28]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[29]),
.Q(\goreg_dm.dout_i_reg[64] [29]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[2]),
.Q(\goreg_dm.dout_i_reg[64] [2]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[30]),
.Q(\goreg_dm.dout_i_reg[64] [30]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[31]),
.Q(\goreg_dm.dout_i_reg[64] [31]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[32]),
.Q(\goreg_dm.dout_i_reg[64] [32]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[33]),
.Q(\goreg_dm.dout_i_reg[64] [33]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[34]),
.Q(\goreg_dm.dout_i_reg[64] [34]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[35]),
.Q(\goreg_dm.dout_i_reg[64] [35]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[36]),
.Q(\goreg_dm.dout_i_reg[64] [36]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[37]),
.Q(\goreg_dm.dout_i_reg[64] [37]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[38]),
.Q(\goreg_dm.dout_i_reg[64] [38]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[39]),
.Q(\goreg_dm.dout_i_reg[64] [39]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[3]),
.Q(\goreg_dm.dout_i_reg[64] [3]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[40]),
.Q(\goreg_dm.dout_i_reg[64] [40]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[41]),
.Q(\goreg_dm.dout_i_reg[64] [41]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[42]),
.Q(\goreg_dm.dout_i_reg[64] [42]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[43]),
.Q(\goreg_dm.dout_i_reg[64] [43]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[44]),
.Q(\goreg_dm.dout_i_reg[64] [44]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[45]),
.Q(\goreg_dm.dout_i_reg[64] [45]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[46]),
.Q(\goreg_dm.dout_i_reg[64] [46]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[47]),
.Q(\goreg_dm.dout_i_reg[64] [47]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[48]),
.Q(\goreg_dm.dout_i_reg[64] [48]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[49]),
.Q(\goreg_dm.dout_i_reg[64] [49]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[4]),
.Q(\goreg_dm.dout_i_reg[64] [4]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[50]),
.Q(\goreg_dm.dout_i_reg[64] [50]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[51]),
.Q(\goreg_dm.dout_i_reg[64] [51]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[52]),
.Q(\goreg_dm.dout_i_reg[64] [52]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[53]),
.Q(\goreg_dm.dout_i_reg[64] [53]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[54]),
.Q(\goreg_dm.dout_i_reg[64] [54]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[55]),
.Q(\goreg_dm.dout_i_reg[64] [55]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[56]),
.Q(\goreg_dm.dout_i_reg[64] [56]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[57]),
.Q(\goreg_dm.dout_i_reg[64] [57]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[58]),
.Q(\goreg_dm.dout_i_reg[64] [58]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[59]),
.Q(\goreg_dm.dout_i_reg[64] [59]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[5]),
.Q(\goreg_dm.dout_i_reg[64] [5]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[60]),
.Q(\goreg_dm.dout_i_reg[64] [60]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[61]),
.Q(\goreg_dm.dout_i_reg[64] [61]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[62]),
.Q(\goreg_dm.dout_i_reg[64] [62]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[63]),
.Q(\goreg_dm.dout_i_reg[64] [63]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[64]),
.Q(\goreg_dm.dout_i_reg[64] [64]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[6]),
.Q(\goreg_dm.dout_i_reg[64] [6]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[7]),
.Q(\goreg_dm.dout_i_reg[64] [7]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[8]),
.Q(\goreg_dm.dout_i_reg[64] [8]));
FDCE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_0_out[9]),
.Q(\goreg_dm.dout_i_reg[64] [9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo
(wr_rst_busy,
empty,
full,
almost_full,
dout,
rd_en,
wr_en,
clk,
rst,
din);
output wr_rst_busy;
output empty;
output full;
output almost_full;
output [64:0]dout;
input rd_en;
input wr_en;
input clk;
input rst;
input [64:0]din;
wire almost_full;
wire clk;
wire [64:0]din;
wire [64:0]dout;
wire empty;
wire full;
wire \gntv_or_sync_fifo.gl0.rd_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_2 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [3:0]p_0_out_0;
wire [3:0]p_11_out;
wire p_2_out;
wire p_5_out;
wire p_7_out;
wire rd_en;
wire [3:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst;
wire rst_full_ff_i;
wire wr_en;
wire wr_rst_busy;
wire [1:1]wr_rst_i;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.Q(rd_pntr_plus1),
.clk(clk),
.empty(empty),
.\goreg_dm.dout_i_reg[64] (p_5_out),
.\gpr1.dout_i_reg[1] (p_0_out_0),
.out(p_2_out),
.p_7_out(p_7_out),
.ram_empty_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.rd_en(rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i),
.E(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.Q(p_11_out),
.almost_full(almost_full),
.clk(clk),
.full(full),
.\gc0.count_d1_reg[3] (p_0_out_0),
.\gc0.count_reg[3] (rd_pntr_plus1),
.out(rst_full_ff_i),
.p_7_out(p_7_out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory \gntv_or_sync_fifo.mem
(.AR(rd_rst_i[0]),
.E(\gntv_or_sync_fifo.gl0.rd_n_2 ),
.EN(\gntv_or_sync_fifo.gl0.wr_n_2 ),
.Q(p_11_out),
.clk(clk),
.din(din),
.dout(dout),
.\gc0.count_d1_reg[3] (p_0_out_0),
.\gpregsm1.curr_fwft_state_reg[1] (p_5_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo rstblk
(.clk(clk),
.\gc0.count_reg[1] ({rd_rst_i[2],rd_rst_i[0]}),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.out(wr_rst_i),
.rst(rst),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top
(wr_rst_busy,
empty,
full,
almost_full,
dout,
rd_en,
wr_en,
clk,
rst,
din);
output wr_rst_busy;
output empty;
output full;
output almost_full;
output [64:0]dout;
input rd_en;
input wr_en;
input clk;
input rst;
input [64:0]din;
wire almost_full;
wire clk;
wire [64:0]din;
wire [64:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_ramfifo \grf.rf
(.almost_full(almost_full),
.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "64" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "1" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "5" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "65" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "32" *) (* C_DIN_WIDTH_RDCH = "64" *)
(* C_DIN_WIDTH_WACH = "1" *) (* C_DIN_WIDTH_WDCH = "64" *) (* C_DIN_WIDTH_WRCH = "2" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "65" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "kintex7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "1" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "0" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "1" *) (* C_IMPLEMENTATION_TYPE_RACH = "1" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "1" *) (* C_IMPLEMENTATION_TYPE_WACH = "1" *) (* C_IMPLEMENTATION_TYPE_WDCH = "1" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "1" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "0" *)
(* C_MEMORY_TYPE = "2" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "0" *) (* C_PRELOAD_REGS = "1" *) (* C_PRIM_FIFO_TYPE = "512x72" *)
(* C_PRIM_FIFO_TYPE_AXIS = "1kx18" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "1kx36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "1kx36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "4" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "1022" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "1022" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "1022" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "5" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "1023" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "14" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "5" *)
(* C_RD_DEPTH = "16" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "4" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "2" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "1" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "5" *)
(* C_WR_DEPTH = "16" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "1024" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "1024" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "4" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "10" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "10" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [64:0]din;
input wr_en;
input rd_en;
input [3:0]prog_empty_thresh;
input [3:0]prog_empty_thresh_assert;
input [3:0]prog_empty_thresh_negate;
input [3:0]prog_full_thresh;
input [3:0]prog_full_thresh_assert;
input [3:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [64:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [4:0]data_count;
output [4:0]rd_data_count;
output [4:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [63:0]s_axi_wdata;
input [7:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [63:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [9:0]axi_w_prog_full_thresh;
input [9:0]axi_w_prog_empty_thresh;
output [10:0]axi_w_data_count;
output [10:0]axi_w_wr_data_count;
output [10:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [9:0]axi_r_prog_full_thresh;
input [9:0]axi_r_prog_empty_thresh;
output [10:0]axi_r_data_count;
output [10:0]axi_r_wr_data_count;
output [10:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire \<const1> ;
wire almost_full;
wire clk;
wire [64:0]din;
wire [64:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
assign almost_empty = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const1> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const1> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const1> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[10] = \<const0> ;
assign axi_r_data_count[9] = \<const0> ;
assign axi_r_data_count[8] = \<const0> ;
assign axi_r_data_count[7] = \<const0> ;
assign axi_r_data_count[6] = \<const0> ;
assign axi_r_data_count[5] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const1> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[10] = \<const0> ;
assign axi_r_rd_data_count[9] = \<const0> ;
assign axi_r_rd_data_count[8] = \<const0> ;
assign axi_r_rd_data_count[7] = \<const0> ;
assign axi_r_rd_data_count[6] = \<const0> ;
assign axi_r_rd_data_count[5] = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[10] = \<const0> ;
assign axi_r_wr_data_count[9] = \<const0> ;
assign axi_r_wr_data_count[8] = \<const0> ;
assign axi_r_wr_data_count[7] = \<const0> ;
assign axi_r_wr_data_count[6] = \<const0> ;
assign axi_r_wr_data_count[5] = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[10] = \<const0> ;
assign axi_w_data_count[9] = \<const0> ;
assign axi_w_data_count[8] = \<const0> ;
assign axi_w_data_count[7] = \<const0> ;
assign axi_w_data_count[6] = \<const0> ;
assign axi_w_data_count[5] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const1> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[10] = \<const0> ;
assign axi_w_rd_data_count[9] = \<const0> ;
assign axi_w_rd_data_count[8] = \<const0> ;
assign axi_w_rd_data_count[7] = \<const0> ;
assign axi_w_rd_data_count[6] = \<const0> ;
assign axi_w_rd_data_count[5] = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[10] = \<const0> ;
assign axi_w_wr_data_count[9] = \<const0> ;
assign axi_w_wr_data_count[8] = \<const0> ;
assign axi_w_wr_data_count[7] = \<const0> ;
assign axi_w_wr_data_count[6] = \<const0> ;
assign axi_w_wr_data_count[5] = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const1> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign m_axi_araddr[31] = \<const0> ;
assign m_axi_araddr[30] = \<const0> ;
assign m_axi_araddr[29] = \<const0> ;
assign m_axi_araddr[28] = \<const0> ;
assign m_axi_araddr[27] = \<const0> ;
assign m_axi_araddr[26] = \<const0> ;
assign m_axi_araddr[25] = \<const0> ;
assign m_axi_araddr[24] = \<const0> ;
assign m_axi_araddr[23] = \<const0> ;
assign m_axi_araddr[22] = \<const0> ;
assign m_axi_araddr[21] = \<const0> ;
assign m_axi_araddr[20] = \<const0> ;
assign m_axi_araddr[19] = \<const0> ;
assign m_axi_araddr[18] = \<const0> ;
assign m_axi_araddr[17] = \<const0> ;
assign m_axi_araddr[16] = \<const0> ;
assign m_axi_araddr[15] = \<const0> ;
assign m_axi_araddr[14] = \<const0> ;
assign m_axi_araddr[13] = \<const0> ;
assign m_axi_araddr[12] = \<const0> ;
assign m_axi_araddr[11] = \<const0> ;
assign m_axi_araddr[10] = \<const0> ;
assign m_axi_araddr[9] = \<const0> ;
assign m_axi_araddr[8] = \<const0> ;
assign m_axi_araddr[7] = \<const0> ;
assign m_axi_araddr[6] = \<const0> ;
assign m_axi_araddr[5] = \<const0> ;
assign m_axi_araddr[4] = \<const0> ;
assign m_axi_araddr[3] = \<const0> ;
assign m_axi_araddr[2] = \<const0> ;
assign m_axi_araddr[1] = \<const0> ;
assign m_axi_araddr[0] = \<const0> ;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const0> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arprot[2] = \<const0> ;
assign m_axi_arprot[1] = \<const0> ;
assign m_axi_arprot[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const0> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_arvalid = \<const0> ;
assign m_axi_awaddr[31] = \<const0> ;
assign m_axi_awaddr[30] = \<const0> ;
assign m_axi_awaddr[29] = \<const0> ;
assign m_axi_awaddr[28] = \<const0> ;
assign m_axi_awaddr[27] = \<const0> ;
assign m_axi_awaddr[26] = \<const0> ;
assign m_axi_awaddr[25] = \<const0> ;
assign m_axi_awaddr[24] = \<const0> ;
assign m_axi_awaddr[23] = \<const0> ;
assign m_axi_awaddr[22] = \<const0> ;
assign m_axi_awaddr[21] = \<const0> ;
assign m_axi_awaddr[20] = \<const0> ;
assign m_axi_awaddr[19] = \<const0> ;
assign m_axi_awaddr[18] = \<const0> ;
assign m_axi_awaddr[17] = \<const0> ;
assign m_axi_awaddr[16] = \<const0> ;
assign m_axi_awaddr[15] = \<const0> ;
assign m_axi_awaddr[14] = \<const0> ;
assign m_axi_awaddr[13] = \<const0> ;
assign m_axi_awaddr[12] = \<const0> ;
assign m_axi_awaddr[11] = \<const0> ;
assign m_axi_awaddr[10] = \<const0> ;
assign m_axi_awaddr[9] = \<const0> ;
assign m_axi_awaddr[8] = \<const0> ;
assign m_axi_awaddr[7] = \<const0> ;
assign m_axi_awaddr[6] = \<const0> ;
assign m_axi_awaddr[5] = \<const0> ;
assign m_axi_awaddr[4] = \<const0> ;
assign m_axi_awaddr[3] = \<const0> ;
assign m_axi_awaddr[2] = \<const0> ;
assign m_axi_awaddr[1] = \<const0> ;
assign m_axi_awaddr[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const0> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awprot[2] = \<const0> ;
assign m_axi_awprot[1] = \<const0> ;
assign m_axi_awprot[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const0> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_awvalid = \<const0> ;
assign m_axi_bready = \<const0> ;
assign m_axi_rready = \<const0> ;
assign m_axi_wdata[63] = \<const0> ;
assign m_axi_wdata[62] = \<const0> ;
assign m_axi_wdata[61] = \<const0> ;
assign m_axi_wdata[60] = \<const0> ;
assign m_axi_wdata[59] = \<const0> ;
assign m_axi_wdata[58] = \<const0> ;
assign m_axi_wdata[57] = \<const0> ;
assign m_axi_wdata[56] = \<const0> ;
assign m_axi_wdata[55] = \<const0> ;
assign m_axi_wdata[54] = \<const0> ;
assign m_axi_wdata[53] = \<const0> ;
assign m_axi_wdata[52] = \<const0> ;
assign m_axi_wdata[51] = \<const0> ;
assign m_axi_wdata[50] = \<const0> ;
assign m_axi_wdata[49] = \<const0> ;
assign m_axi_wdata[48] = \<const0> ;
assign m_axi_wdata[47] = \<const0> ;
assign m_axi_wdata[46] = \<const0> ;
assign m_axi_wdata[45] = \<const0> ;
assign m_axi_wdata[44] = \<const0> ;
assign m_axi_wdata[43] = \<const0> ;
assign m_axi_wdata[42] = \<const0> ;
assign m_axi_wdata[41] = \<const0> ;
assign m_axi_wdata[40] = \<const0> ;
assign m_axi_wdata[39] = \<const0> ;
assign m_axi_wdata[38] = \<const0> ;
assign m_axi_wdata[37] = \<const0> ;
assign m_axi_wdata[36] = \<const0> ;
assign m_axi_wdata[35] = \<const0> ;
assign m_axi_wdata[34] = \<const0> ;
assign m_axi_wdata[33] = \<const0> ;
assign m_axi_wdata[32] = \<const0> ;
assign m_axi_wdata[31] = \<const0> ;
assign m_axi_wdata[30] = \<const0> ;
assign m_axi_wdata[29] = \<const0> ;
assign m_axi_wdata[28] = \<const0> ;
assign m_axi_wdata[27] = \<const0> ;
assign m_axi_wdata[26] = \<const0> ;
assign m_axi_wdata[25] = \<const0> ;
assign m_axi_wdata[24] = \<const0> ;
assign m_axi_wdata[23] = \<const0> ;
assign m_axi_wdata[22] = \<const0> ;
assign m_axi_wdata[21] = \<const0> ;
assign m_axi_wdata[20] = \<const0> ;
assign m_axi_wdata[19] = \<const0> ;
assign m_axi_wdata[18] = \<const0> ;
assign m_axi_wdata[17] = \<const0> ;
assign m_axi_wdata[16] = \<const0> ;
assign m_axi_wdata[15] = \<const0> ;
assign m_axi_wdata[14] = \<const0> ;
assign m_axi_wdata[13] = \<const0> ;
assign m_axi_wdata[12] = \<const0> ;
assign m_axi_wdata[11] = \<const0> ;
assign m_axi_wdata[10] = \<const0> ;
assign m_axi_wdata[9] = \<const0> ;
assign m_axi_wdata[8] = \<const0> ;
assign m_axi_wdata[7] = \<const0> ;
assign m_axi_wdata[6] = \<const0> ;
assign m_axi_wdata[5] = \<const0> ;
assign m_axi_wdata[4] = \<const0> ;
assign m_axi_wdata[3] = \<const0> ;
assign m_axi_wdata[2] = \<const0> ;
assign m_axi_wdata[1] = \<const0> ;
assign m_axi_wdata[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const0> ;
assign m_axi_wstrb[7] = \<const0> ;
assign m_axi_wstrb[6] = \<const0> ;
assign m_axi_wstrb[5] = \<const0> ;
assign m_axi_wstrb[4] = \<const0> ;
assign m_axi_wstrb[3] = \<const0> ;
assign m_axi_wstrb[2] = \<const0> ;
assign m_axi_wstrb[1] = \<const0> ;
assign m_axi_wstrb[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_arready = \<const0> ;
assign s_axi_awready = \<const0> ;
assign s_axi_bid[0] = \<const0> ;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_bvalid = \<const0> ;
assign s_axi_rdata[63] = \<const0> ;
assign s_axi_rdata[62] = \<const0> ;
assign s_axi_rdata[61] = \<const0> ;
assign s_axi_rdata[60] = \<const0> ;
assign s_axi_rdata[59] = \<const0> ;
assign s_axi_rdata[58] = \<const0> ;
assign s_axi_rdata[57] = \<const0> ;
assign s_axi_rdata[56] = \<const0> ;
assign s_axi_rdata[55] = \<const0> ;
assign s_axi_rdata[54] = \<const0> ;
assign s_axi_rdata[53] = \<const0> ;
assign s_axi_rdata[52] = \<const0> ;
assign s_axi_rdata[51] = \<const0> ;
assign s_axi_rdata[50] = \<const0> ;
assign s_axi_rdata[49] = \<const0> ;
assign s_axi_rdata[48] = \<const0> ;
assign s_axi_rdata[47] = \<const0> ;
assign s_axi_rdata[46] = \<const0> ;
assign s_axi_rdata[45] = \<const0> ;
assign s_axi_rdata[44] = \<const0> ;
assign s_axi_rdata[43] = \<const0> ;
assign s_axi_rdata[42] = \<const0> ;
assign s_axi_rdata[41] = \<const0> ;
assign s_axi_rdata[40] = \<const0> ;
assign s_axi_rdata[39] = \<const0> ;
assign s_axi_rdata[38] = \<const0> ;
assign s_axi_rdata[37] = \<const0> ;
assign s_axi_rdata[36] = \<const0> ;
assign s_axi_rdata[35] = \<const0> ;
assign s_axi_rdata[34] = \<const0> ;
assign s_axi_rdata[33] = \<const0> ;
assign s_axi_rdata[32] = \<const0> ;
assign s_axi_rdata[31] = \<const0> ;
assign s_axi_rdata[30] = \<const0> ;
assign s_axi_rdata[29] = \<const0> ;
assign s_axi_rdata[28] = \<const0> ;
assign s_axi_rdata[27] = \<const0> ;
assign s_axi_rdata[26] = \<const0> ;
assign s_axi_rdata[25] = \<const0> ;
assign s_axi_rdata[24] = \<const0> ;
assign s_axi_rdata[23] = \<const0> ;
assign s_axi_rdata[22] = \<const0> ;
assign s_axi_rdata[21] = \<const0> ;
assign s_axi_rdata[20] = \<const0> ;
assign s_axi_rdata[19] = \<const0> ;
assign s_axi_rdata[18] = \<const0> ;
assign s_axi_rdata[17] = \<const0> ;
assign s_axi_rdata[16] = \<const0> ;
assign s_axi_rdata[15] = \<const0> ;
assign s_axi_rdata[14] = \<const0> ;
assign s_axi_rdata[13] = \<const0> ;
assign s_axi_rdata[12] = \<const0> ;
assign s_axi_rdata[11] = \<const0> ;
assign s_axi_rdata[10] = \<const0> ;
assign s_axi_rdata[9] = \<const0> ;
assign s_axi_rdata[8] = \<const0> ;
assign s_axi_rdata[7] = \<const0> ;
assign s_axi_rdata[6] = \<const0> ;
assign s_axi_rdata[5] = \<const0> ;
assign s_axi_rdata[4] = \<const0> ;
assign s_axi_rdata[3] = \<const0> ;
assign s_axi_rdata[2] = \<const0> ;
assign s_axi_rdata[1] = \<const0> ;
assign s_axi_rdata[0] = \<const0> ;
assign s_axi_rid[0] = \<const0> ;
assign s_axi_rlast = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_rvalid = \<const0> ;
assign s_axi_wready = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth inst_fifo_gen
(.almost_full(almost_full),
.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_v13_1_2_synth
(wr_rst_busy,
empty,
full,
almost_full,
dout,
rd_en,
wr_en,
clk,
rst,
din);
output wr_rst_busy;
output empty;
output full;
output almost_full;
output [64:0]dout;
input rd_en;
input wr_en;
input clk;
input rst;
input [64:0]din;
wire almost_full;
wire clk;
wire [64:0]din;
wire [64:0]dout;
wire empty;
wire full;
wire rd_en;
wire rst;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_fifo_generator_top \gconvfifo.rf
(.almost_full(almost_full),
.clk(clk),
.din(din),
.dout(dout),
.empty(empty),
.full(full),
.rd_en(rd_en),
.rst(rst),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_memory
(dout,
clk,
EN,
din,
\gc0.count_d1_reg[3] ,
Q,
E,
AR,
\gpregsm1.curr_fwft_state_reg[1] );
output [64:0]dout;
input clk;
input EN;
input [64:0]din;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]Q;
input [0:0]E;
input [0:0]AR;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]AR;
wire [0:0]E;
wire EN;
wire [3:0]Q;
wire clk;
wire [64:0]din;
wire [64:0]dout;
wire [64:0]dout_i;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_dmem \gdm.dm_gen.dm
(.AR(AR),
.E(E),
.EN(EN),
.Q(Q),
.clk(clk),
.din(din),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\goreg_dm.dout_i_reg[64] (dout_i));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[0]),
.Q(dout[0]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[10]),
.Q(dout[10]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[11]),
.Q(dout[11]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[12]),
.Q(dout[12]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[13]),
.Q(dout[13]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[14]),
.Q(dout[14]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[15]),
.Q(dout[15]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[16]),
.Q(dout[16]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[17]),
.Q(dout[17]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[18]),
.Q(dout[18]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[19]),
.Q(dout[19]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[1]),
.Q(dout[1]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[20]),
.Q(dout[20]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[21]),
.Q(dout[21]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[22]),
.Q(dout[22]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[23]),
.Q(dout[23]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[24]),
.Q(dout[24]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[25]),
.Q(dout[25]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[26]),
.Q(dout[26]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[27]),
.Q(dout[27]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[28]),
.Q(dout[28]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[29]),
.Q(dout[29]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[2]),
.Q(dout[2]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[30]),
.Q(dout[30]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[31]),
.Q(dout[31]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[32]),
.Q(dout[32]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[33]),
.Q(dout[33]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[34]),
.Q(dout[34]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[35]),
.Q(dout[35]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[36]),
.Q(dout[36]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[37]),
.Q(dout[37]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[38]),
.Q(dout[38]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[39]),
.Q(dout[39]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[3]),
.Q(dout[3]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[40]),
.Q(dout[40]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[41]),
.Q(dout[41]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[42]),
.Q(dout[42]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[43]),
.Q(dout[43]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[44]),
.Q(dout[44]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[45]),
.Q(dout[45]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[46]),
.Q(dout[46]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[47]),
.Q(dout[47]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[48]),
.Q(dout[48]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[49]),
.Q(dout[49]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[4]),
.Q(dout[4]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[50]),
.Q(dout[50]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[51]),
.Q(dout[51]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[52]),
.Q(dout[52]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[53]),
.Q(dout[53]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[54]),
.Q(dout[54]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[55]),
.Q(dout[55]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[56]),
.Q(dout[56]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[57]),
.Q(dout[57]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[58]),
.Q(dout[58]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[59]),
.Q(dout[59]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[5]),
.Q(dout[5]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[60]),
.Q(dout[60]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[61]),
.Q(dout[61]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[62]),
.Q(dout[62]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[63]),
.Q(dout[63]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[64]),
.Q(dout[64]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[6]),
.Q(dout[6]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[7]),
.Q(dout[7]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[8]),
.Q(dout[8]));
FDCE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(clk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.CLR(AR),
.D(dout_i[9]),
.Q(dout[9]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr
(Q,
\gpr1.dout_i_reg[1] ,
E,
clk,
AR);
output [3:0]Q;
output [3:0]\gpr1.dout_i_reg[1] ;
input [0:0]E;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire clk;
wire [3:0]\gpr1.dout_i_reg[1] ;
wire [3:0]plusOp;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(plusOp[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\gpr1.dout_i_reg[1] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gpr1.dout_i_reg[1] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gpr1.dout_i_reg[1] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gpr1.dout_i_reg[1] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(clk),
.CE(E),
.D(plusOp[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp[3]),
.Q(Q[3]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft
(empty,
E,
\gc0.count_reg[0] ,
\goreg_dm.dout_i_reg[64] ,
clk,
AR,
rd_en,
out);
output empty;
output [0:0]E;
output [0:0]\gc0.count_reg[0] ;
output [0:0]\goreg_dm.dout_i_reg[64] ;
input clk;
input [0:0]AR;
input rd_en;
input out;
wire [0:0]AR;
wire [0:0]E;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
wire clk;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gc0.count_reg[0] ;
wire [0:0]\goreg_dm.dout_i_reg[64] ;
wire [1:0]next_fwft_state;
wire out;
wire rd_en;
(* DONT_TOUCH *) wire user_valid;
assign empty = empty_fwft_i;
LUT5 #(
.INIT(32'hEEFD8000))
aempty_fwft_fb_i_i_1
(.I0(curr_fwft_state[0]),
.I1(out),
.I2(rd_en),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(AR),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(clk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(AR),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hF320))
empty_fwft_fb_i_i_1
(.I0(rd_en),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(empty_fwft_fb_i),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(AR),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hF320))
empty_fwft_fb_o_i_i_1
(.I0(rd_en),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(empty_fwft_fb_o_i),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(AR),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(clk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(AR),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00BF))
\gc0.count_d1[3]_i_1
(.I0(rd_en),
.I1(curr_fwft_state[0]),
.I2(curr_fwft_state[1]),
.I3(out),
.O(\gc0.count_reg[0] ));
LUT3 #(
.INIT(8'hA2))
\goreg_dm.dout_i[64]_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(rd_en),
.O(\goreg_dm.dout_i_reg[64] ));
LUT4 #(
.INIT(16'h00F7))
\gpr1.dout_i[64]_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(rd_en),
.I3(out),
.O(E));
LUT3 #(
.INIT(8'hBA))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state[1]),
.I1(rd_en),
.I2(curr_fwft_state[0]),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state[1]),
.I1(rd_en),
.I2(curr_fwft_state[0]),
.I3(out),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(clk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(clk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(clk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[0]),
.Q(user_valid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_logic
(out,
empty,
E,
Q,
p_7_out,
\goreg_dm.dout_i_reg[64] ,
\gpr1.dout_i_reg[1] ,
ram_empty_fb_i_reg,
clk,
AR,
rd_en);
output out;
output empty;
output [0:0]E;
output [3:0]Q;
output p_7_out;
output [0:0]\goreg_dm.dout_i_reg[64] ;
output [3:0]\gpr1.dout_i_reg[1] ;
input ram_empty_fb_i_reg;
input clk;
input [0:0]AR;
input rd_en;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire clk;
wire empty;
wire [0:0]\goreg_dm.dout_i_reg[64] ;
wire [3:0]\gpr1.dout_i_reg[1] ;
wire out;
wire p_7_out;
wire ram_empty_fb_i_reg;
wire rd_en;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_fwft \gr1.gr1_int.rfwft
(.AR(AR),
.E(E),
.clk(clk),
.empty(empty),
.\gc0.count_reg[0] (p_7_out),
.\goreg_dm.dout_i_reg[64] (\goreg_dm.dout_i_reg[64] ),
.out(out),
.rd_en(rd_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss \grss.rsts
(.AR(AR),
.clk(clk),
.out(out),
.ram_empty_fb_i_reg_0(ram_empty_fb_i_reg));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_bin_cntr rpntr
(.AR(AR),
.E(p_7_out),
.Q(Q),
.clk(clk),
.\gpr1.dout_i_reg[1] (\gpr1.dout_i_reg[1] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_rd_status_flags_ss
(out,
ram_empty_fb_i_reg_0,
clk,
AR);
output out;
input ram_empty_fb_i_reg_0;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire clk;
(* DONT_TOUCH *) wire ram_empty_fb_i;
wire ram_empty_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_empty_fb_i_reg_0),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_empty_fb_i_reg_0),
.PRE(AR),
.Q(ram_empty_i));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
wr_rst_busy,
clk,
rst);
output [0:0]out;
output [1:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output wr_rst_busy;
input clk;
input rst;
wire clk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
wire rst;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [1] = rd_rst_reg[2];
assign \gc0.count_reg[1] [0] = rd_rst_reg[0];
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[0] = wr_rst_reg[1];
assign wr_rst_busy = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(clk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(clk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.clk(clk),
.in0(rd_rst_asreg),
.\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.clk(clk),
.in0(wr_rst_asreg),
.\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg (\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.out(p_8_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.clk(clk),
.in0(rd_rst_asreg),
.out(p_7_out));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.clk(clk),
.in0(wr_rst_asreg),
.out(p_8_out));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_0 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(rst),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(rst),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(clk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(rst),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(clk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(clk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_0 ),
.Q(wr_rst_reg[2]));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff
(out,
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_0
(out,
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ,
in0,
clk);
output out;
output \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
input [0:0]in0;
input clk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire \ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_i_1
(.I0(in0),
.I1(Q_reg),
.O(\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg ));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_1
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_synchronizer_ff_2
(AS,
out,
clk,
in0);
output [0:0]AS;
input out;
input clk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire clk;
wire [0:0]in0;
wire out;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(clk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr
(p_2_out,
ram_full_comb,
ram_empty_i_reg,
Q,
almost_full,
p_7_out,
E,
wr_rst_busy,
wr_en,
out,
ram_empty_fb_i_reg,
\gc0.count_reg[3] ,
\gc0.count_d1_reg[3] ,
clk,
AR);
output p_2_out;
output ram_full_comb;
output ram_empty_i_reg;
output [3:0]Q;
input almost_full;
input p_7_out;
input [0:0]E;
input wr_rst_busy;
input wr_en;
input out;
input ram_empty_fb_i_reg;
input [3:0]\gc0.count_reg[3] ;
input [3:0]\gc0.count_d1_reg[3] ;
input clk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire almost_full;
wire clk;
wire \gaf.gaf0.ram_afull_i_i_3_n_0 ;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gc0.count_reg[3] ;
wire \gwss.wsts/comp0 ;
wire \gwss.wsts/comp1 ;
wire \gwss.wsts/p_0_in ;
wire out;
wire [3:0]p_12_out;
wire p_2_out;
wire p_7_out;
wire [3:0]plusOp__0;
wire ram_empty_fb_i_i_3_n_0;
wire ram_empty_fb_i_i_4_n_0;
wire ram_empty_fb_i_i_5_n_0;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire ram_full_comb;
wire ram_full_fb_i_i_3_n_0;
wire wr_en;
wire [3:0]wr_pntr_plus2;
wire wr_rst_busy;
LUT6 #(
.INIT(64'h00AA0000CCEE0CCC))
\gaf.gaf0.ram_afull_i_i_1
(.I0(\gwss.wsts/p_0_in ),
.I1(almost_full),
.I2(\gwss.wsts/comp1 ),
.I3(p_7_out),
.I4(E),
.I5(wr_rst_busy),
.O(p_2_out));
LUT5 #(
.INIT(32'h00009009))
\gaf.gaf0.ram_afull_i_i_2
(.I0(\gc0.count_d1_reg[3] [3]),
.I1(wr_pntr_plus2[3]),
.I2(\gc0.count_d1_reg[3] [2]),
.I3(wr_pntr_plus2[2]),
.I4(\gaf.gaf0.ram_afull_i_i_3_n_0 ),
.O(\gwss.wsts/p_0_in ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h6FF6))
\gaf.gaf0.ram_afull_i_i_3
(.I0(wr_pntr_plus2[1]),
.I1(\gc0.count_d1_reg[3] [1]),
.I2(wr_pntr_plus2[0]),
.I3(\gc0.count_d1_reg[3] [0]),
.O(\gaf.gaf0.ram_afull_i_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gcc0.gc1.gsym.count[0]_i_1
(.I0(wr_pntr_plus2[0]),
.O(plusOp__0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gcc0.gc1.gsym.count[1]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'h78))
\gcc0.gc1.gsym.count[2]_i_1
(.I0(wr_pntr_plus2[0]),
.I1(wr_pntr_plus2[1]),
.I2(wr_pntr_plus2[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h7F80))
\gcc0.gc1.gsym.count[3]_i_1
(.I0(wr_pntr_plus2[1]),
.I1(wr_pntr_plus2[0]),
.I2(wr_pntr_plus2[2]),
.I3(wr_pntr_plus2[3]),
.O(plusOp__0[3]));
FDPE #(
.INIT(1'b1))
\gcc0.gc1.gsym.count_d1_reg[0]
(.C(clk),
.CE(E),
.D(wr_pntr_plus2[0]),
.PRE(AR),
.Q(p_12_out[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d1_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[1]),
.Q(p_12_out[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d1_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[2]),
.Q(p_12_out[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d1_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(wr_pntr_plus2[3]),
.Q(p_12_out[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d2_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d2_reg[1]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d2_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_d2_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(p_12_out[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_reg[0]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[0]),
.Q(wr_pntr_plus2[0]));
FDPE #(
.INIT(1'b1))
\gcc0.gc1.gsym.count_reg[1]
(.C(clk),
.CE(E),
.D(plusOp__0[1]),
.PRE(AR),
.Q(wr_pntr_plus2[1]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_reg[2]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[2]),
.Q(wr_pntr_plus2[2]));
FDCE #(
.INIT(1'b0))
\gcc0.gc1.gsym.count_reg[3]
(.C(clk),
.CE(E),
.CLR(AR),
.D(plusOp__0[3]),
.Q(wr_pntr_plus2[3]));
LUT5 #(
.INIT(32'hFCFC44FC))
ram_empty_fb_i_i_1
(.I0(\gwss.wsts/comp0 ),
.I1(ram_empty_fb_i_reg),
.I2(ram_empty_fb_i_i_3_n_0),
.I3(wr_en),
.I4(out),
.O(ram_empty_i_reg));
LUT5 #(
.INIT(32'h00009009))
ram_empty_fb_i_i_2
(.I0(\gc0.count_d1_reg[3] [3]),
.I1(Q[3]),
.I2(\gc0.count_d1_reg[3] [2]),
.I3(Q[2]),
.I4(ram_empty_fb_i_i_4_n_0),
.O(\gwss.wsts/comp0 ));
LUT6 #(
.INIT(64'h4100004100000000))
ram_empty_fb_i_i_3
(.I0(ram_empty_fb_i_i_5_n_0),
.I1(Q[2]),
.I2(\gc0.count_reg[3] [2]),
.I3(Q[3]),
.I4(\gc0.count_reg[3] [3]),
.I5(p_7_out),
.O(ram_empty_fb_i_i_3_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_empty_fb_i_i_4
(.I0(Q[1]),
.I1(\gc0.count_d1_reg[3] [1]),
.I2(Q[0]),
.I3(\gc0.count_d1_reg[3] [0]),
.O(ram_empty_fb_i_i_4_n_0));
LUT4 #(
.INIT(16'h6FF6))
ram_empty_fb_i_i_5
(.I0(Q[1]),
.I1(\gc0.count_reg[3] [1]),
.I2(Q[0]),
.I3(\gc0.count_reg[3] [0]),
.O(ram_empty_fb_i_i_5_n_0));
LUT6 #(
.INIT(64'h0008000800F8F0F8))
ram_full_fb_i_i_1
(.I0(\gwss.wsts/comp1 ),
.I1(wr_en),
.I2(out),
.I3(p_7_out),
.I4(\gwss.wsts/comp0 ),
.I5(wr_rst_busy),
.O(ram_full_comb));
LUT5 #(
.INIT(32'h00009009))
ram_full_fb_i_i_2
(.I0(\gc0.count_d1_reg[3] [3]),
.I1(p_12_out[3]),
.I2(\gc0.count_d1_reg[3] [2]),
.I3(p_12_out[2]),
.I4(ram_full_fb_i_i_3_n_0),
.O(\gwss.wsts/comp1 ));
LUT4 #(
.INIT(16'h6FF6))
ram_full_fb_i_i_3
(.I0(p_12_out[1]),
.I1(\gc0.count_d1_reg[3] [1]),
.I2(p_12_out[0]),
.I3(\gc0.count_d1_reg[3] [0]),
.O(ram_full_fb_i_i_3_n_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_logic
(full,
almost_full,
E,
ram_empty_i_reg,
Q,
clk,
out,
wr_en,
p_7_out,
wr_rst_busy,
ram_empty_fb_i_reg,
\gc0.count_reg[3] ,
\gc0.count_d1_reg[3] ,
AR);
output full;
output almost_full;
output [0:0]E;
output ram_empty_i_reg;
output [3:0]Q;
input clk;
input out;
input wr_en;
input p_7_out;
input wr_rst_busy;
input ram_empty_fb_i_reg;
input [3:0]\gc0.count_reg[3] ;
input [3:0]\gc0.count_d1_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire almost_full;
wire clk;
wire full;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gc0.count_reg[3] ;
wire \gwss.wsts_n_0 ;
wire out;
wire p_2_out;
wire p_7_out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire ram_full_comb;
wire wr_en;
wire wr_rst_busy;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss \gwss.wsts
(.E(E),
.almost_full(almost_full),
.clk(clk),
.full(full),
.\grstd1.grst_full.grst_f.rst_d2_reg (out),
.out(\gwss.wsts_n_0 ),
.p_2_out(p_2_out),
.ram_full_comb(ram_full_comb),
.wr_en(wr_en));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_bin_cntr wpntr
(.AR(AR),
.E(E),
.Q(Q),
.almost_full(almost_full),
.clk(clk),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gc0.count_reg[3] (\gc0.count_reg[3] ),
.out(\gwss.wsts_n_0 ),
.p_2_out(p_2_out),
.p_7_out(p_7_out),
.ram_empty_fb_i_reg(ram_empty_fb_i_reg),
.ram_empty_i_reg(ram_empty_i_reg),
.ram_full_comb(ram_full_comb),
.wr_en(wr_en),
.wr_rst_busy(wr_rst_busy));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_wr_status_flags_ss
(out,
full,
almost_full,
E,
ram_full_comb,
clk,
\grstd1.grst_full.grst_f.rst_d2_reg ,
p_2_out,
wr_en);
output out;
output full;
output almost_full;
output [0:0]E;
input ram_full_comb;
input clk;
input \grstd1.grst_full.grst_f.rst_d2_reg ;
input p_2_out;
input wr_en;
wire [0:0]E;
wire clk;
wire \grstd1.grst_full.grst_f.rst_d2_reg ;
(* DONT_TOUCH *) wire p_15_out;
wire p_2_out;
(* DONT_TOUCH *) wire ram_afull_i;
wire ram_full_comb;
(* DONT_TOUCH *) wire ram_full_fb_i;
(* DONT_TOUCH *) wire ram_full_i;
wire wr_en;
assign almost_full = ram_afull_i;
assign full = ram_full_i;
assign out = ram_full_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\gaf.gaf0.ram_afull_i_reg
(.C(clk),
.CE(1'b1),
.D(p_2_out),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_afull_i));
LUT2 #(
.INIT(4'h2))
\gcc0.gc1.gsym.count_d1[3]_i_1
(.I0(wr_en),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(p_15_out));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(clk),
.CE(1'b1),
.D(ram_full_comb),
.PRE(\grstd1.grst_full.grst_f.rst_d2_reg ),
.Q(ram_full_i));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: dram_l2if.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module dram_l2if (/*AUTOARG*/
// Outputs
dram_ucb_ack_vld, dram_ucb_nack_vld, dram_ucb_data,
l2if_que_rd_req_vld, l2if_que_wr_req_vld, l2if_que_addr,
l2if_que_data, dram_sctag_chunk_id, dram_sctag_data_vld,
dram_sctag_rd_req_id, dram_sctag_data, dram_sctag_mecc_err,
dram_sctag_pa_err, dram_sctag_secc_err, dram_sctag_ecc,
dram_sctag_rd_ack, dram_sctag_wr_ack, l2if_data_mecc0,
l2if_data_mecc1, l2if_data_mecc2, l2if_data_mecc3,
l2if_data_mecc4, l2if_data_mecc5, l2if_data_mecc6,
l2if_data_mecc7, l2if_data_wr_addr, dram_cpu_wr_addr,
dram_cpu_wr_en, dram_cpu_wr_data, l2if_wr_req, l2if_rd_req,
l2if_rd_addr, l2if_wr_addr, l2if_rd_id, l2if_scrb_data_en,
l2if_scrb_data, l2if_scrb_ecc, l2if_err_loc, l2if_err_cnt,
l2if_dbg_trig_en, l2if_err_intr, dram_sctag_scb_mecc_err,
dram_sctag_scb_secc_err, l2if_err_addr_reg, l2if_err_sts_reg,
dram_data_val_other_ch, dp_data_valid_d1, l2if_channel_disabled,
err_loc, err_syn, l2if_ucb_trig, l2if_que_selfrsh,
// Inputs
clk, rst_l, arst_l, ucb_l2if_selfrsh, que_wr_req,
sctag_dram_rd_req, sctag_dram_rd_dummy_req, sctag_dram_rd_req_id,
sctag_dram_addr, sctag_dram_wr_req, sctag_dram_data_vld,
sctag_dram_wr_data, sctag_dram_data_mecc, readqbank0vld0,
readqbank0vld1, readqbank0vld2, readqbank0vld3, writeqbank0vld0,
writeqbank0vld1, writeqbank0vld2, writeqbank0vld3, readqbank0vld4,
readqbank0vld5, readqbank0vld6, readqbank0vld7, writeqbank0vld4,
writeqbank0vld5, writeqbank0vld6, writeqbank0vld7, que_scrb_addr,
dram_fail_over_mode, que_wr_entry_free, config_reg,
que_rank1_present, ucb_dram_rd_req_vld, ucb_dram_wr_req_vld,
ucb_dram_addr, ucb_dram_data, que_eight_bank_mode,
que_l2if_ack_vld, que_l2if_nack_vld, que_l2if_data,
que_dram_clk_toggle, dp_data_valid, que_l2if_send_info,
dp_data_in, dp_ecc_in, dram_dram_rx_sync, dram_dram_tx_sync,
dram_jbus_rx_sync, dram_jbus_tx_sync, que_addr_bank_low_sel,
que_channel_disabled, other_channel_disabled, ch0_err_loc,
ch0_err_syn, ch0_dp_data_valid_d1, ch0_dram_data_val_other_ch,
ch0_dram_sctag_chunk_id, ch0_dram_sctag_rd_req_id,
ch0_dram_sctag_data, ch0_dram_sctag_ecc, ch0_dram_sctag_mecc_err,
ch0_dram_sctag_pa_err, ch0_dram_sctag_secc_err
);
// DRAM controller interface
input clk;
input rst_l;
input arst_l;
input ucb_l2if_selfrsh;
// rd interface
input sctag_dram_rd_req;
input sctag_dram_rd_dummy_req;
input [2:0] sctag_dram_rd_req_id;
input [39:5] sctag_dram_addr;
// wr interface
input sctag_dram_wr_req;
input sctag_dram_data_vld;
input [63:0] sctag_dram_wr_data;
input sctag_dram_data_mecc;
input readqbank0vld0;
input readqbank0vld1;
input readqbank0vld2;
input readqbank0vld3;
input writeqbank0vld0;
input writeqbank0vld1;
input writeqbank0vld2;
input writeqbank0vld3;
input readqbank0vld4;
input readqbank0vld5;
input readqbank0vld6;
input readqbank0vld7;
input writeqbank0vld4;
input writeqbank0vld5;
input writeqbank0vld6;
input writeqbank0vld7;
input que_wr_req;
input [32:0] que_scrb_addr;
input dram_fail_over_mode;
input [3:0] que_wr_entry_free;
input [8:0] config_reg;
input que_rank1_present;
// FROM UCB
input ucb_dram_rd_req_vld;
input ucb_dram_wr_req_vld;
input [31:0] ucb_dram_addr;
input [63:0] ucb_dram_data;
// TO UCB
output dram_ucb_ack_vld;
output dram_ucb_nack_vld;
output [63:0] dram_ucb_data;
// TO QUE
output l2if_que_rd_req_vld;
output l2if_que_wr_req_vld;
output [31:0] l2if_que_addr;
output [63:0] l2if_que_data;
// FROM QUE
input que_eight_bank_mode;
input que_l2if_ack_vld;
input que_l2if_nack_vld;
input [63:0] que_l2if_data;
// cas related info
input que_dram_clk_toggle;
input dp_data_valid;
input [9:0] que_l2if_send_info;
// read data
input [255:0] dp_data_in;
input [31:0] dp_ecc_in;
// rd interface
output [1:0] dram_sctag_chunk_id;
output dram_sctag_data_vld;
output [2:0] dram_sctag_rd_req_id;
output [127:0] dram_sctag_data;
output dram_sctag_mecc_err;
output dram_sctag_pa_err;
output dram_sctag_secc_err;
output [27:0] dram_sctag_ecc;
output dram_sctag_rd_ack;
// wr interface
output dram_sctag_wr_ack;
// To DP for poisoning data
output [3:0] l2if_data_mecc0;
output [3:0] l2if_data_mecc1;
output [3:0] l2if_data_mecc2;
output [3:0] l2if_data_mecc3;
output [3:0] l2if_data_mecc4;
output [3:0] l2if_data_mecc5;
output [3:0] l2if_data_mecc6;
output [3:0] l2if_data_mecc7;
// write address
output [2:0] l2if_data_wr_addr;
output [3:0] dram_cpu_wr_addr;
output [3:0] dram_cpu_wr_en;
output [63:0] dram_cpu_wr_data;
// Going to dram clk domain
output l2if_wr_req;
output l2if_rd_req;
output [35:0] l2if_rd_addr;
output [35:0] l2if_wr_addr;
output [2:0] l2if_rd_id;
output l2if_scrb_data_en;
output [255:0] l2if_scrb_data;
output [33:0] l2if_scrb_ecc;
output [35:0] l2if_err_loc;
output [17:0] l2if_err_cnt;
output l2if_dbg_trig_en;
// Going to jbus clk domain
output l2if_err_intr;
// Async scrub error signals
output dram_sctag_scb_mecc_err;
output dram_sctag_scb_secc_err;
// FROM QUE
output [35:0] l2if_err_addr_reg;
output [22:0] l2if_err_sts_reg;
// SYNC Pulse
input dram_dram_rx_sync;
input dram_dram_tx_sync;
input dram_jbus_rx_sync;
input dram_jbus_tx_sync;
input que_addr_bank_low_sel;
// NEW DUE TO TWO CHANNEL MODE
input que_channel_disabled;
input other_channel_disabled;
output dram_data_val_other_ch;
output dp_data_valid_d1;
input [35:0] ch0_err_loc;
input [15:0] ch0_err_syn;
input ch0_dp_data_valid_d1;
input ch0_dram_data_val_other_ch;
input [1:0] ch0_dram_sctag_chunk_id;
input [2:0] ch0_dram_sctag_rd_req_id;
input [127:0] ch0_dram_sctag_data;
input [27:0] ch0_dram_sctag_ecc;
input ch0_dram_sctag_mecc_err;
input ch0_dram_sctag_pa_err;
input ch0_dram_sctag_secc_err;
output l2if_channel_disabled;
output [35:0] err_loc;
output [15:0] err_syn;
output l2if_ucb_trig;
output l2if_que_selfrsh;
//////////////////////////////////////////////////////////////////
// Wires
//////////////////////////////////////////////////////////////////
wire [35:0] ch0_err_loc_d1;
wire [15:0] ch0_err_syn_d1;
wire l2if_scrb_data_val;
wire l2if_trig;
wire l2if_dummy_data_cnt_val;
wire l2if_ucb_ack_vld_cpu;
wire l2if_ucb_nack_vld_cpu;
wire [31:0] l2if_ucb_addr_cpu;
wire [63:0] l2if_ucb_que_data_cpu;
wire [63:0] l2if_ucb_data_cpu;
wire [63:0] l2if_ucb_que_data;
wire l2if_addr_bank_low_sel;
wire [1:0] l2if_data_cnt_d1;
wire [1:0] l2if_data_cnt_d2;
wire [1:0] l2if_data_cnt_d3;
wire l2if_secc_err;
wire ecc_multi_lo_err;
wire ecc_multi_hi_err;
wire l2if_mecc_err_partial;
wire ecc_single_lo_err;
wire ecc_single_hi_err;
wire [127:0] ecc_cor_lo_data;
wire [127:0] ecc_cor_hi_data;
wire [27:0] l2if_rd_ecc_lo_d1;
wire [27:0] l2if_l2_ecc_lo;
wire [27:0] l2if_l2_ecc_hi;
wire l2if_wr_ack;
wire l2if_rd_ack;
wire [3:0] l2if_b0_wr_val;
wire [3:0] l2if_b1_wr_val;
wire [3:0] l2if_b0_rd_val;
wire [3:0] l2if_b1_rd_val;
wire [255:0] l2if_rd_data_p1;
wire [127:0] l2if_rd_data_d1;
wire [1:0] l2if_data_offset;
wire l2if_data_first_chunk_in;
wire l2if_data_mux_sel_en;
wire l2if_data_first_chunk;
wire l2if_l2_val;
wire [5:0] l2if_wr_b0_data_addr_in;
wire [5:0] l2if_wr_b0_data_addr;
wire [31:0] l2if_rd_ecc_p1;
wire [1:0] l2if_data_cnt_in;
wire [1:0] l2if_data_cnt;
wire l2if_data_cnt_en;
wire l2if_add_fifo_valid;
wire [9:0] l2if_fifo_ent0;
wire [9:0] l2if_fifo_ent1;
wire [9:0] l2if_fifo_ent2;
wire [9:0] l2if_fifo_ent3;
wire [9:0] l2if_fifo_ent4;
wire [9:0] l2if_fifo_ent5;
wire [9:0] l2if_fifo_ent6;
wire [9:0] l2if_fifo_ent7;
wire l2if_data_valid_reset;
wire l2if_data_valid_d1;
wire [9:0] l2if_send_info;
wire l2if_data_cnt_val;
wire l2if_add_scrb_valid;
wire [127:0] ecc_cor_hi_data_d1;
wire [127:0] ecc_cor_lo_data_d1;
wire [127:0] ecc_cor_mux_hi_data;
wire [127:0] ecc_cor_mux_lo_data;
wire l2if_fifo_reset;
wire [127:0] l2if_ecc_cor_data;
wire [27:0] l2if_gen_ecc;
wire [3:0] l2if_mecc0_en;
wire [3:0] l2if_mecc1_en;
wire [3:0] l2if_mecc2_en;
wire [3:0] l2if_mecc3_en;
wire [3:0] l2if_mecc4_en;
wire [3:0] l2if_mecc5_en;
wire [3:0] l2if_mecc6_en;
wire [3:0] l2if_mecc7_en;
wire [3:0] l2if_data_mecc0_in;
wire [3:0] l2if_data_mecc1_in;
wire [3:0] l2if_data_mecc2_in;
wire [3:0] l2if_data_mecc3_in;
wire [3:0] l2if_data_mecc4_in;
wire [3:0] l2if_data_mecc5_in;
wire [3:0] l2if_data_mecc6_in;
wire [3:0] l2if_data_mecc7_in;
wire [3:0] data_mecc0;
wire [3:0] data_mecc1;
wire [3:0] data_mecc2;
wire [3:0] data_mecc3;
wire [3:0] data_mecc4;
wire [3:0] data_mecc5;
wire [3:0] data_mecc6;
wire [3:0] data_mecc7;
wire [32:0] l2if_scrb_addr;
wire [31:0] l2if_rd_ecc_d1;
wire [31:0] l2if_rd_ecc_d2;
wire [31:0] l2if_rd_ecc_d3;
wire [31:0] l2if_ucb_addr;
wire [63:0] l2if_ucb_data;
wire l2if_dram_clk_toggle_d1;
wire [35:0] err_addr_reg;
wire [22:0] err_sts_reg;
wire [39:4] l2if_rd_addr_p1;
wire [2:0] l2if_rd_id_p1;
wire [39:6] l2if_wr_addr_p1;
wire l2if_scrb_val_d1;
wire l2if_scrb_val_d2;
wire l2if_scrb_val_d3;
wire l2if_wr_entry0;
wire l2if_wr_entry1;
wire l2if_wr_entry2;
wire l2if_wr_entry3;
wire l2if_wr_entry4;
wire l2if_wr_entry5;
wire l2if_wr_entry6;
wire l2if_wr_entry7;
wire [3:0] l2if_wr_entry_free;
wire [35:0] ecc_loc_lo_d1;
wire [35:0] ecc_loc_hi_d1;
wire [35:0] l2if_secc_loc;
wire [15:0] l2if_secc_cnt;
wire [35:0] ecc_loc_lo;
wire [35:0] ecc_loc_hi;
wire [35:0] l2if_split_rd_addr;
wire [35:0] l2if_split_rd_addr_lo;
wire [35:0] l2if_split_rd_addr_hi;
wire [35:0] l2if_split_wr_addr;
wire [35:0] l2if_split_wr_addr_lo;
wire [35:0] l2if_split_wr_addr_hi;
wire [8:0] l2if_config_reg;
wire l2if_offset_inc;
wire [3:0] l2if_wr_val_cnt;
wire l2if_rd_dummy_req_p1;
//////////////////////////////////////////////////////////////////
// Flop L2 input requests
//////////////////////////////////////////////////////////////////
//dram_dram_rx_sync (enable for signals comming from dram clk to fast clk)
//dram_dram_tx_sync (enable for signals going from fast clk to dram clk)
//dram_jbus_rx_sync (enable for signals comming from jbus clk to fast clk)
//dram_jbus_tx_sync (enable for signals going from fast clk to jbus clk)
dff_ns #(2) ff_dram_sync_pulses (
.din ({dram_dram_rx_sync, dram_dram_tx_sync}),
.q ({l2if_dram_rx_sync, l2if_dram_tx_sync}),
.clk (clk));
dff_ns #(2) ff_jbus_sync_pulses (
.din ({dram_jbus_rx_sync, dram_jbus_tx_sync}),
.q ({l2if_jbus_rx_sync, l2if_jbus_tx_sync}),
.clk (clk));
dff_ns #(2) ff_dram_sync_pulses_d1 (
.din ({l2if_dram_rx_sync, l2if_jbus_rx_sync}),
.q ({l2if_dram_rx_sync_d1, l2if_jbus_rx_sync_d1}),
.clk (clk));
// Delay the err_syn and err_loc by 1 cycle to match with data val for 2 channel mode
dffrl_ns #(52) ff_ch0_syn_loc(
.din({ch0_err_loc[35:0], ch0_err_syn[15:0]}),
.q({ch0_err_loc_d1[35:0], ch0_err_syn_d1[15:0]}),
.rst_l(rst_l),
.clk(clk));
// This staged signal is needed in 2 channel mode for muxing the data
dff_ns #(2) ff_ch0_dp_data_valid (
.din ({ch0_dp_data_valid_d1, other_ch_dp_data_valid_d1}),
.q ({other_ch_dp_data_valid_d1, other_ch_dp_data_valid_d2}),
.clk (clk));
wire l2if_wr_req_flop_reset = rst_l & ~l2if_wr_ack;
dffrle_ns #(1) l2wrreqflop_cpu (
.din (sctag_dram_wr_req),
.q (l2if_wr_req_cpu),
.en (sctag_dram_wr_req),
.rst_l (l2if_wr_req_flop_reset),
.clk (clk));
wire l2if_rd_req_flop_reset = rst_l & ~l2if_rd_ack;
dffrle_ns #(1) l2rdreqflop_cpu (
.din (sctag_dram_rd_req),
.q (l2if_dram_rd_req),
.en (sctag_dram_rd_req),
.rst_l (l2if_rd_req_flop_reset),
.clk (clk));
wire l2if_rd_dummy_req_flop_reset = rst_l & ~((l2if_data_cnt == 2'h3) &
l2if_rd_dummy_req_p1 & ~l2if_data_valid_d1 & ~sctag_dram_rd_dummy_req);
dffrle_ns #(1) l2id_rd_dummy_req (
.din (sctag_dram_rd_dummy_req),
.q (l2if_rd_dummy_req_p1),
.en (sctag_dram_rd_req),
.rst_l (l2if_rd_dummy_req_flop_reset),
.clk (clk));
wire l2if_rd_req_cpu = l2if_dram_rd_req & ~l2if_rd_dummy_req_p1;
// Flop rd address input
dffe_ns #(36) l2addr_rdflop0 (
.din ({sctag_dram_addr[39:5], 1'b0}),
.q (l2if_rd_addr_p1[39:4]),
.en (sctag_dram_rd_req),
.clk (clk));
// generating two channel mode bit
dff_ns #(1) flop_other_channel_disabled (
.din (other_channel_disabled),
.q (l2if_other_channel_disabled),
.clk (clk));
wire l2if_two_channel_mode = l2if_channel_disabled | l2if_other_channel_disabled;
dff_ns #(1) flop_two_channel_mode (
.din (l2if_two_channel_mode),
.q (two_channel_mode),
.clk (clk));
// Generate bank, ras, cas and addr error signals for read addr.
/*dram_addr_gen AUTO_TEMPLATE( .addr_err(l2if_split_rd_addr_hi[32]),
.addr_parity(l2if_split_rd_addr_hi[34]),
.stack_adr(l2if_split_rd_addr_hi[33]),
.rank_adr (l2if_split_rd_addr_hi[35]),
.ras_adr (l2if_split_rd_addr_hi[31:17]),
.cas_adr (l2if_split_rd_addr_hi[16:3]),
.bank_adr (l2if_split_rd_addr_hi[2:0]),
// Inputs
.addr_in (l2if_rd_addr_p1[39:4]),
.eight_bank_mode(l2if_eight_bank_mode),
.rank1_present(rank1_present),
.two_channel_mode(two_channel_mode),
.config_reg(l2if_config_reg[8:0])); */
/*dram_addr_gen_lo AUTO_TEMPLATE( .addr_err(l2if_split_rd_addr_lo[32]),
.addr_parity(l2if_split_rd_addr_lo[34]),
.stack_adr(l2if_split_rd_addr_lo[33]),
.rank_adr (l2if_split_rd_addr_lo[35]),
.ras_adr (l2if_split_rd_addr_lo[31:17]),
.cas_adr (l2if_split_rd_addr_lo[16:3]),
.bank_adr (l2if_split_rd_addr_lo[2:0]),
// Inputs
.addr_in (l2if_rd_addr_p1[39:4]),
.eight_bank_mode(l2if_eight_bank_mode),
.rank1_present(rank1_present),
.two_channel_mode(two_channel_mode),
.config_reg(l2if_config_reg[8:0])); */
dram_addr_gen dram_rd_addr_gen_hi(/*AUTOINST*/
// Outputs
.addr_parity(l2if_split_rd_addr_hi[34]), // Templated
.addr_err(l2if_split_rd_addr_hi[32]), // Templated
.rank_adr(l2if_split_rd_addr_hi[35]), // Templated
.stack_adr(l2if_split_rd_addr_hi[33]), // Templated
.bank_adr(l2if_split_rd_addr_hi[2:0]), // Templated
.ras_adr(l2if_split_rd_addr_hi[31:17]), // Templated
.cas_adr(l2if_split_rd_addr_hi[16:3]), // Templated
// Inputs
.addr_in(l2if_rd_addr_p1[39:4]), // Templated
.config_reg(l2if_config_reg[8:0]), // Templated
.rank1_present(rank1_present), // Templated
.eight_bank_mode(l2if_eight_bank_mode), // Templated
.two_channel_mode(two_channel_mode)); // Templated
dram_addr_gen_lo dram_rd_addr_gen_lo(/*AUTOINST*/
// Outputs
.addr_parity(l2if_split_rd_addr_lo[34]), // Templated
.addr_err(l2if_split_rd_addr_lo[32]), // Templated
.rank_adr(l2if_split_rd_addr_lo[35]), // Templated
.stack_adr(l2if_split_rd_addr_lo[33]), // Templated
.bank_adr(l2if_split_rd_addr_lo[2:0]), // Templated
.ras_adr(l2if_split_rd_addr_lo[31:17]), // Templated
.cas_adr(l2if_split_rd_addr_lo[16:3]), // Templated
// Inputs
.addr_in(l2if_rd_addr_p1[39:4]), // Templated
.config_reg(l2if_config_reg[8:0]), // Templated
.rank1_present(rank1_present), // Templated
.eight_bank_mode(l2if_eight_bank_mode), // Templated
.two_channel_mode(two_channel_mode)); // Templated
assign l2if_split_rd_addr[35:0] = l2if_addr_bank_low_sel ? l2if_split_rd_addr_lo[35:0] :
l2if_split_rd_addr_hi[35:0];
dffe_ns #(3) l2id_rdflop0 (
.din (sctag_dram_rd_req_id[2:0]),
.q (l2if_rd_id_p1[2:0]),
.en (sctag_dram_rd_req),
.clk (clk));
// Flop wr address input
dffe_ns #(34) l2addr_wrflop0 (
.din (sctag_dram_addr[39:6]),
.q (l2if_wr_addr_p1[39:6]),
.en (sctag_dram_wr_req),
.clk (clk));
// Generate bank, ras, cas and addr error signals for wr addr.
/*dram_addr_gen AUTO_TEMPLATE( .addr_err(l2if_split_wr_addr_hi[32]),
.addr_parity(l2if_split_wr_addr_hi[34]),
.stack_adr(l2if_split_wr_addr_hi[33]),
.rank_adr (l2if_split_wr_addr_hi[35]),
.ras_adr (l2if_split_wr_addr_hi[31:17]),
.cas_adr (l2if_split_wr_addr_hi[16:3]),
.bank_adr (l2if_split_wr_addr_hi[2:0]),
// Inputs
.addr_in ({l2if_wr_addr_p1[39:6], 2'h0}),
.rank1_present(rank1_present),
.eight_bank_mode(l2if_eight_bank_mode),
.config_reg(l2if_config_reg[8:0])); */
/*dram_addr_gen_lo AUTO_TEMPLATE( .addr_err(l2if_split_wr_addr_lo[32]),
.addr_parity(l2if_split_wr_addr_lo[34]),
.stack_adr(l2if_split_wr_addr_lo[33]),
.rank_adr (l2if_split_wr_addr_lo[35]),
.ras_adr (l2if_split_wr_addr_lo[31:17]),
.cas_adr (l2if_split_wr_addr_lo[16:3]),
.bank_adr (l2if_split_wr_addr_lo[2:0]),
// Inputs
.addr_in ({l2if_wr_addr_p1[39:6], 2'h0}),
.eight_bank_mode(l2if_eight_bank_mode),
.rank1_present(rank1_present),
.config_reg(l2if_config_reg[8:0])); */
dram_addr_gen dram_wr_addr_gen_hi(/*AUTOINST*/
// Outputs
.addr_parity(l2if_split_wr_addr_hi[34]), // Templated
.addr_err(l2if_split_wr_addr_hi[32]), // Templated
.rank_adr(l2if_split_wr_addr_hi[35]), // Templated
.stack_adr(l2if_split_wr_addr_hi[33]), // Templated
.bank_adr(l2if_split_wr_addr_hi[2:0]), // Templated
.ras_adr(l2if_split_wr_addr_hi[31:17]), // Templated
.cas_adr(l2if_split_wr_addr_hi[16:3]), // Templated
// Inputs
.addr_in({l2if_wr_addr_p1[39:6], 2'h0}), // Templated
.config_reg(l2if_config_reg[8:0]), // Templated
.rank1_present(rank1_present), // Templated
.eight_bank_mode(l2if_eight_bank_mode), // Templated
.two_channel_mode(two_channel_mode));
dram_addr_gen_lo dram_wr_addr_gen_lo(/*AUTOINST*/
// Outputs
.addr_parity(l2if_split_wr_addr_lo[34]), // Templated
.addr_err(l2if_split_wr_addr_lo[32]), // Templated
.rank_adr(l2if_split_wr_addr_lo[35]), // Templated
.stack_adr(l2if_split_wr_addr_lo[33]), // Templated
.bank_adr(l2if_split_wr_addr_lo[2:0]), // Templated
.ras_adr(l2if_split_wr_addr_lo[31:17]), // Templated
.cas_adr(l2if_split_wr_addr_lo[16:3]), // Templated
// Inputs
.addr_in({l2if_wr_addr_p1[39:6], 2'h0}), // Templated
.config_reg(l2if_config_reg[8:0]), // Templated
.rank1_present(rank1_present), // Templated
.eight_bank_mode(l2if_eight_bank_mode), // Templated
.two_channel_mode(two_channel_mode));
assign l2if_split_wr_addr[35:0] = l2if_addr_bank_low_sel ? l2if_split_wr_addr_lo[35:0] :
l2if_split_wr_addr_hi[35:0];
// Flop wr address out of range bit
dffrl_ns #(1) l2addr_wr_en_d1 (
.din (sctag_dram_wr_req),
.q (l2if_wr_en0_d1),
.rst_l (rst_l),
.clk (clk));
wire l2if_wr_addr_err_in = l2if_split_wr_addr[32];
dffrle_ns #(1) l2addr_wr_pa_err (
.din (l2if_wr_addr_err_in),
.q (l2if_wr_addr_err),
.en (l2if_wr_en0_d1),
.rst_l (rst_l),
.clk (clk));
/////////////////////////////////////////////////
// SIGNALS FROM CPU CLK TO DRAM CLK
/////////////////////////////////////////////////
// write and read req valids
dffe_ns #(2) l2wrreqflop_dram (
.din ({l2if_wr_ack, l2if_rd_req_cpu}),
.q ({l2if_wr_req,l2if_rd_req}),
.en (l2if_dram_tx_sync),
.clk (clk));
// Error status register
dffe_ns #(23) ff_err_sts_reg(
.din (err_sts_reg[22:0]),
.q (l2if_err_sts_reg[22:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// Error address register
dffe_ns #(36) err_addr(
.din (err_addr_reg[35:0]),
.q (l2if_err_addr_reg[35:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// scrb data for dram clk domain
dffe_ns #(256) scrb_data(
.din ({ecc_cor_hi_data_d1[127:0], ecc_cor_lo_data_d1[127:0]}),
.q (l2if_scrb_data[255:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
dffe_ns #(34) scrb_ecc(
.din ({ecc_multi_hi_err_d1, ecc_multi_lo_err_d1, l2if_rd_ecc_d3[31:16],
l2if_rd_ecc_d3[15:0]}),
.q (l2if_scrb_ecc[33:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// scrub valid signal for dram side
dffe_ns #(2) scrb_val(
.din ({l2if_dbg_trig, l2if_scrb_val_d3}),
.q ({l2if_dbg_trig_en, l2if_scrb_data_en}),
.en (l2if_dram_tx_sync),
.clk (clk));
// rd address input
dffe_ns #(36) rd_addr (
.din (l2if_split_rd_addr[35:0]),
.q (l2if_rd_addr[35:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// rd req id
dffe_ns #(3) rd_id (
.din (l2if_rd_id_p1[2:0]),
.q (l2if_rd_id[2:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// wr address input
dffe_ns #(36) wr_addr (
.din (l2if_split_wr_addr[35:0]),
.q (l2if_wr_addr[35:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// data write address into mem
dffe_ns #(3) ff_wr_addr(
.din (l2if_wr_b0_data_addr[5:3]),
.q (l2if_data_wr_addr[2:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// l2 poison on mecc err bits
dffe_ns #(16) ff_l2_poison0_3(
.din ({data_mecc0[3:0], data_mecc1[3:0], data_mecc2[3:0], data_mecc3[3:0]}),
.q ({l2if_data_mecc0[3:0], l2if_data_mecc1[3:0], l2if_data_mecc2[3:0],
l2if_data_mecc3[3:0]}),
.en (l2if_dram_tx_sync),
.clk (clk));
dffe_ns #(16) ff_l2_poison4_7(
.din ({data_mecc4[3:0], data_mecc5[3:0], data_mecc6[3:0], data_mecc7[3:0]}),
.q ({l2if_data_mecc4[3:0], l2if_data_mecc5[3:0], l2if_data_mecc6[3:0],
l2if_data_mecc7[3:0]}),
.en (l2if_dram_tx_sync),
.clk (clk));
// ecc loc reg
dffe_ns #(36) ff_ecc_loc_reg(
.din (l2if_secc_loc[35:0]),
.q (l2if_err_loc[35:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// err counter reg
dffe_ns #(18) ff_err_cnt_reg(
.din ({l2if_secc_int_enabled, l2if_secc_vld, l2if_secc_cnt[15:0]}),
.q (l2if_err_cnt[17:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// flop write and read valid
dffe_ns #(2) l2if_ucb_rd_wr_vld(
.din ({l2if_ucb_rd_req_vld_cpu, l2if_ucb_wr_req_vld_cpu}),
.q ({l2if_que_rd_req_vld, l2if_que_wr_req_vld}),
.en (l2if_dram_tx_sync),
.clk (clk));
// flop addr in
dffe_ns #(32) l2if_ucb_addr_in(
.din (l2if_ucb_addr_cpu[31:0]),
.q (l2if_que_addr[31:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// flop data in
dffe_ns #(64) l2if_ucb_data_in(
.din (l2if_ucb_data_cpu[63:0]),
.q (l2if_que_data[63:0]),
.en (l2if_dram_tx_sync),
.clk (clk));
// Freq 200 sel
dffe_ns #(1) ff_test_signals(
.din ({l2if_selfrsh}),
.q ({l2if_que_selfrsh}),
.en (l2if_dram_tx_sync),
.clk (clk));
//////////////////////////////////////////////////////////////////
// SIGNALS FROM JBUS TO CPU CLK
//////////////////////////////////////////////////////////////////
// Test signals
dffe_ns #(1) ff_ucb_test_signals(
.din ({ucb_l2if_selfrsh}),
.q ({l2if_selfrsh}),
.en (l2if_jbus_rx_sync),
.clk (clk));
// flop write and read valid
dffe_ns #(2) ucb_rd_wr_vld(
.din ({ucb_dram_rd_req_vld, ucb_dram_wr_req_vld}),
.q ({l2if_ucb_rd_req_vld, l2if_ucb_wr_req_vld}),
.en (l2if_jbus_rx_sync),
.clk (clk));
// flop addr in
dffe_ns #(32) ucb_addr_in(
.din (ucb_dram_addr[31:0]),
.q (l2if_ucb_addr[31:0]),
.en (l2if_jbus_rx_sync),
.clk (clk));
// flop data in
dffe_ns #(64) ucb_data_in(
.din (ucb_dram_data[63:0]),
.q (l2if_ucb_data[63:0]),
.en (l2if_jbus_rx_sync),
.clk (clk));
////////////////////////
// Flop enable so that its reset on dram sync pulse
////////////////////////
wire l2if_ucb_wr_req_vld_en = l2if_jbus_rx_sync_d1 & l2if_ucb_wr_req_vld;
wire l2if_ucb_rd_req_vld_en = l2if_jbus_rx_sync_d1 & l2if_ucb_rd_req_vld;
wire l2if_ucb_wr_req_rst_l = rst_l & ~(l2if_dram_tx_sync & l2if_ucb_wr_req_vld_cpu);
wire l2if_ucb_rd_req_rst_l = rst_l & ~(l2if_dram_tx_sync & l2if_ucb_rd_req_vld_cpu);
// flop write valid
dffrle_ns #(1) l2if_wr_vld(
.din (l2if_ucb_wr_req_vld),
.q (l2if_ucb_wr_req_vld_cpu),
.en (l2if_ucb_wr_req_vld_en),
.rst_l (l2if_ucb_wr_req_rst_l),
.clk (clk));
// flop read valid
dffrle_ns #(1) l2if_rd_vld(
.din (l2if_ucb_rd_req_vld),
.q (l2if_ucb_rd_req_vld_cpu),
.en (l2if_ucb_rd_req_vld_en),
.rst_l (l2if_ucb_rd_req_rst_l),
.clk (clk));
wire l2if_ucb_addr_en = l2if_ucb_wr_req_vld_en | l2if_ucb_rd_req_vld_en;
// flop addr in
dffe_ns #(32) ff_l2if_ucb_addr_cpu(
.din (l2if_ucb_addr[31:0]),
.q (l2if_ucb_addr_cpu[31:0]),
.en (l2if_ucb_addr_en),
.clk (clk));
// flop data in
dffe_ns #(64) ff_l2if_ucb_data_cpu(
.din (l2if_ucb_data[63:0]),
.q (l2if_ucb_data_cpu[63:0]),
.en (l2if_ucb_wr_req_vld),
.clk (clk));
/////////////////////////////////////////////////
// SIGNALS FROM DRAM CLK TO CPU CLK
/////////////////////////////////////////////////
// Select bank bits
dffe_ns #(1) bank_bits_sel (
.din(que_addr_bank_low_sel),
.q(l2if_addr_bank_low_sel),
.en(l2if_dram_rx_sync),
.clk(clk));
// channel disable bit
dffe_ns #(1) ch_disabled (
.din(que_channel_disabled),
.q(l2if_channel_disabled),
.en(l2if_dram_rx_sync),
.clk(clk));
// 8 bank mode bit
dffe_ns #(1) eight_bank_mode (
.din(que_eight_bank_mode),
.q(l2if_eight_bank_mode),
.en(l2if_dram_rx_sync),
.clk(clk));
// fail over bit
dffe_ns #(1) fail_over_mode (
.din(dram_fail_over_mode),
.q(l2if_dram_fail_over_mode),
.en(l2if_dram_rx_sync),
.clk(clk));
// Flop scrb address input
dffe_ns #(33) scrb_addr (
.din(que_scrb_addr[32:0]),
.q(l2if_scrb_addr[32:0]),
.en(l2if_dram_rx_sync),
.clk(clk));
// dram to cpu clk domain of the buffer valids
dffe_ns #(17) ff_que_val(
.din ({que_wr_req, readqbank0vld0, readqbank0vld1, readqbank0vld2, readqbank0vld3,
writeqbank0vld0, writeqbank0vld1, writeqbank0vld2, writeqbank0vld3,
readqbank0vld4, readqbank0vld5, readqbank0vld6, readqbank0vld7,
writeqbank0vld4, writeqbank0vld5, writeqbank0vld6, writeqbank0vld7 }),
.q ({l2if_new_wr_req_ret, l2if_b0_rd_val[3:0],l2if_b0_wr_val[3:0],
l2if_b1_rd_val[3:0],l2if_b1_wr_val[3:0]}),
.en(l2if_dram_rx_sync),
.clk (clk));
dffrle_ns #(12) l2_read_info(
.din ({que_dram_clk_toggle, dp_data_valid, que_l2if_send_info[9:0]}),
.q ({l2if_dram_clk_toggle, dp_data_valid_d1, l2if_send_info[9:0]}),
.rst_l (rst_l),
.en (l2if_dram_rx_sync),
.clk (clk));
// flop dp data to send to l2
dffe_ns #(288) l2_read_data(
.din ({dp_ecc_in[31:0], dp_data_in[255:0]}),
.q ({l2if_rd_ecc_p1[31:0], l2if_rd_data_p1[255:0]}),
.en (l2if_dram_rx_sync),
.clk (clk));
// flop write data entry free
dffe_ns #(4) wr_entry_free(
.din (que_wr_entry_free[3:0]),
.q (l2if_wr_entry_free[3:0]),
.en (l2if_dram_rx_sync),
.clk (clk));
// flop chip config for ras cas width and stack dimm
dffe_ns #(10) ff_config(
.din ({que_rank1_present, config_reg[8:0]}),
.q ({rank1_present, l2if_config_reg[8:0]}),
.en (l2if_dram_rx_sync),
.clk (clk));
// flop ack and nack
dffe_ns #(2) l2if_ucb_ack_nack(
.din ({que_l2if_ack_vld, que_l2if_nack_vld}),
.q ({l2if_ucb_ack_vld, l2if_ucb_nack_vld}),
.en (l2if_dram_rx_sync),
.clk (clk));
// flop data
dffe_ns #(64) l2if_ucb_data_out(
.din (que_l2if_data[63:0]),
.q (l2if_ucb_que_data[63:0]),
.en (l2if_dram_rx_sync),
.clk (clk));
////////////////////////////////////////
// Flop enable so that its reset on jbus sync pulse
////////////////////////////////////////
wire l2if_ucb_ack_en = l2if_dram_rx_sync_d1 & l2if_ucb_ack_vld;
wire l2if_ucb_nack_en = l2if_dram_rx_sync_d1 & l2if_ucb_nack_vld;
wire l2if_ucb_ack_rst_l = rst_l & ~(l2if_jbus_tx_sync & l2if_ucb_ack_vld_cpu);
wire l2if_ucb_nack_rst_l = rst_l & ~(l2if_jbus_tx_sync & l2if_ucb_nack_vld_cpu);
wire l2if_secc_trig_rst_l = rst_l & ~(l2if_jbus_tx_sync & l2if_trig);
// flop ack
dffrle_ns #(1) ucb_ack(
.din (l2if_ucb_ack_vld),
.q (l2if_ucb_ack_vld_cpu),
.en (l2if_ucb_ack_en),
.rst_l (l2if_ucb_ack_rst_l),
.clk (clk));
// flop nack
dffrle_ns #(1) ucb_nack(
.din (l2if_ucb_nack_vld),
.q (l2if_ucb_nack_vld_cpu),
.en (l2if_ucb_nack_en),
.rst_l (l2if_ucb_nack_rst_l),
.clk (clk));
// flop data
dffe_ns #(64) ucb_data_cpu(
.din (l2if_ucb_que_data[63:0]),
.q (l2if_ucb_que_data_cpu[63:0]),
.en (l2if_ucb_ack_en),
.clk (clk));
// flop dbg_trig
dffrle_ns #(1) ff_dgb_trig(
.din (l2if_secc_trig),
.q (l2if_trig),
.en (l2if_secc_trig),
.rst_l (l2if_secc_trig_rst_l),
.clk (clk));
//////////////////////////////////////////////////////////////////
// SIGNALS FROM CPU TO JBUS CLK
//////////////////////////////////////////////////////////////////
// flop ack and nack
dffe_ns #(2) ucb_ack_nack(
.din ({l2if_ucb_ack_vld_cpu, l2if_ucb_nack_vld_cpu}),
.q ({dram_ucb_ack_vld, dram_ucb_nack_vld}),
.en (l2if_jbus_tx_sync),
.clk (clk));
// flop data
dffe_ns #(64) ucb_data_out(
.din (l2if_ucb_que_data_cpu[63:0]),
.q (dram_ucb_data[63:0]),
.en (l2if_jbus_tx_sync),
.clk (clk));
// err interrupt
dffe_ns #(1) ff_err_intr(
.din (l2if_secc_cnt_intr),
.q (l2if_err_intr),
.en (l2if_jbus_tx_sync),
.clk (clk));
// flop debug trigger
dffe_ns #(1) dbg_trig(
.din (l2if_trig),
.q (l2if_ucb_trig),
.en (l2if_jbus_tx_sync),
.clk (clk));
//////////////////////////////////////////////////////////////////
// Generate the ack for L2
//////////////////////////////////////////////////////////////////
// There could be corner case in writes due to more than 8 requests
// being asserted unlike in reads due to no id numbers.
// Need to count only for write not for read because L2 does have id for read
// and does not have more than 8 id's but no id for writes.
assign l2if_wr_val_cnt[3:0] = {3'h0, l2if_b0_wr_val[3]} + {3'h0, l2if_b0_wr_val[2]} +
{3'h0, l2if_b0_wr_val[1]} + {3'h0, l2if_b0_wr_val[0]} +
{3'h0, l2if_b1_wr_val[3]} + {3'h0, l2if_b1_wr_val[2]} +
{3'h0, l2if_b1_wr_val[1]}+ {3'h0, l2if_b1_wr_val[0]};
// Send ack only if cnt is - (below 7 | if 7 then no ack in prev cycle) & new req in tx cycle
// Because the turn around is 2 dram cycles min. we have to look at the req signal after a cycle
assign l2if_wr_ack = ( (~l2if_wr_val_cnt[3] & ~(&l2if_wr_val_cnt[2:0])) |
(&l2if_wr_val_cnt[2:0] & ~(l2if_wr_req | l2if_new_wr_req_ret)) ) &
l2if_wr_req_cpu & l2if_dram_tx_sync;
assign l2if_rd_ack = ~(&{l2if_b0_rd_val[3:0],l2if_b1_rd_val[3:0]}) &
l2if_rd_req_cpu & l2if_dram_tx_sync |
~l2if_channel_disabled & ~dp_data_valid_d1 & l2if_dram_rx_sync_d1 &
l2if_dram_rd_req & l2if_rd_dummy_req_p1 |
l2if_channel_disabled & ~ch0_dp_data_valid_d1 & l2if_dram_rx_sync_d1 &
l2if_dram_rd_req & l2if_rd_dummy_req_p1;
// Read Ack
dffrl_ns ff_rd_ack0(
.din (l2if_rd_ack),
.q (dram_sctag_rd_ack),
.rst_l (rst_l),
.clk (clk));
// Write Ack logic
dffrl_ns ff_wr_ack(
.din (l2if_wr_ack),
.q (dram_sctag_wr_ack),
.rst_l (rst_l),
.clk (clk));
//////////////////////////////////////////////////////////////////
//// L2 Interface DP Portion (Possibly to Synthesize)
//////////////////////////////////////////////////////////////////
// Flop all data input
dff_ns #(64) l2dataflop0 (
.din (sctag_dram_wr_data[63:0]),
.q (dram_cpu_wr_data[63:0]),
.clk (clk));
dffrl_ns #(2) l2datavldflop (
.din ({sctag_dram_data_vld, sctag_dram_data_mecc}),
.q ({l2if_b0_data_vld, l2if_dram_data_mecc}),
.rst_l (rst_l),
.clk (clk));
// stage data valid
dffrl_ns #(1) ff_data_vld (
.din (l2if_b0_data_vld),
.q (l2if_b0_data_vld_d1),
.rst_l (rst_l),
.clk (clk));
//////////////////////////////////////////////////////////////////
// Generate address and enable for writing data into arrays.
//////////////////////////////////////////////////////////////////
// generate enable for write
assign dram_cpu_wr_en[3:0] = ~({4{l2if_b0_data_vld}} &
({ l2if_wr_b0_data_addr[1] & l2if_wr_b0_data_addr[0],
l2if_wr_b0_data_addr[1] & ~l2if_wr_b0_data_addr[0],
~l2if_wr_b0_data_addr[1] & l2if_wr_b0_data_addr[0],
~l2if_wr_b0_data_addr[1] & ~l2if_wr_b0_data_addr[0] }));
// generate the index into the array
// When data valid is high just increment the address to write into that location.
// When its low, eval only when the data valid is just gone low and there is no pending req at that time
// and also tha there is some entry empty. If all entries are occupied, then check for entry that's
// getting free and make that as free entry. By default it will keep its old value.
assign l2if_wr_b0_data_addr_in[5:0] = (~l2if_b0_data_vld) ? (
~l2if_wr_entry0 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h0 :
~l2if_wr_entry1 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h8 :
~l2if_wr_entry2 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h10 :
~l2if_wr_entry3 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h18 :
~l2if_wr_entry4 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h20 :
~l2if_wr_entry5 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h28 :
~l2if_wr_entry6 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h30 :
~l2if_wr_entry7 & ~l2if_wr_req_cpu & l2if_b0_data_vld_d1 ? 6'h38 :
l2if_wr_entry0 & l2if_wr_entry1 & l2if_wr_entry2 & l2if_wr_entry3 &
l2if_wr_entry4 & l2if_wr_entry5 & l2if_wr_entry6 & l2if_wr_entry7 &
l2if_wr_entry_free[3] ? {l2if_wr_entry_free[2:0],3'h0} :
l2if_wr_b0_data_addr[5:0]) : l2if_wr_b0_data_addr[5:0] + 6'h1;
dffrl_ns #(6) ff_b0_data_addr (
.din(l2if_wr_b0_data_addr_in[5:0]),
.q(l2if_wr_b0_data_addr[5:0]),
.rst_l(rst_l),
.clk(clk));
assign dram_cpu_wr_addr = l2if_wr_b0_data_addr[5:2];
// Keep track of in use entries. A 1 means its in use or else free.
// Keep it free if there was address error in write address. The write is silently dropped.
wire l2if_wr_entry0_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h0) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h0);
wire l2if_wr_entry0_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h0) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent0(
.din(l2if_wr_entry0_in),
.q(l2if_wr_entry0),
.rst_l(rst_l),
.en(l2if_wr_entry0_en),
.clk(clk));
wire l2if_wr_entry1_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h1) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h1);
wire l2if_wr_entry1_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h1) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent1(
.din(l2if_wr_entry1_in),
.q(l2if_wr_entry1),
.rst_l(rst_l),
.en(l2if_wr_entry1_en),
.clk(clk));
wire l2if_wr_entry2_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h2) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h2);
wire l2if_wr_entry2_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h2) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent2(
.din(l2if_wr_entry2_in),
.q(l2if_wr_entry2),
.rst_l(rst_l),
.en(l2if_wr_entry2_en),
.clk(clk));
wire l2if_wr_entry3_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h3) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h3);
wire l2if_wr_entry3_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h3) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent3(
.din(l2if_wr_entry3_in),
.q(l2if_wr_entry3),
.rst_l(rst_l),
.en(l2if_wr_entry3_en),
.clk(clk));
wire l2if_wr_entry4_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h4) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h4);
wire l2if_wr_entry4_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h4) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent4(
.din(l2if_wr_entry4_in),
.q(l2if_wr_entry4),
.rst_l(rst_l),
.en(l2if_wr_entry4_en),
.clk(clk));
wire l2if_wr_entry5_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h5) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h5);
wire l2if_wr_entry5_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h5) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent5(
.din(l2if_wr_entry5_in),
.q(l2if_wr_entry5),
.rst_l(rst_l),
.en(l2if_wr_entry5_en),
.clk(clk));
wire l2if_wr_entry6_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h6) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h6);
wire l2if_wr_entry6_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h6) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent6(
.din(l2if_wr_entry6_in),
.q(l2if_wr_entry6),
.rst_l(rst_l),
.en(l2if_wr_entry6_en),
.clk(clk));
wire l2if_wr_entry7_en = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h7) |
~l2if_wr_addr_err & l2if_b0_data_vld & ~l2if_b0_data_vld_d1 &
(l2if_wr_b0_data_addr[5:3] == 3'h7);
wire l2if_wr_entry7_in = l2if_wr_entry_free[3] & (l2if_wr_entry_free[2:0] == 3'h7) ? 1'b0 : 1'b1;
dffrle_ns #(1) ff_wr_ent7(
.din(l2if_wr_entry7_in),
.q(l2if_wr_entry7),
.rst_l(rst_l),
.en(l2if_wr_entry7_en),
.clk(clk));
//////////////////////////////////////////////////////////////////
// Generate L2 response for read requests
//////////////////////////////////////////////////////////////////
///////
// Generate chunk offset
///////
assign l2if_data_cnt_in = l2if_data_cnt + 2'h1;
assign l2if_data_cnt_en = l2if_data_cnt_val | l2if_dummy_data_cnt_val;
dffrle_ns #(2) ff_data8_cnt(
.din(l2if_data_cnt_in[1:0]),
.q(l2if_data_cnt[1:0]),
.rst_l(rst_l),
.en(l2if_data_cnt_en),
.clk(clk));
// Stage data valid
// Data correction and detection is for two cycles.
dff_ns #(1) ff_data_vld_d1(
.din(dp_data_valid_d1),
.q(l2if_data_valid_d1),
.clk(clk));
// This signal aligns with the data out of ecc_corection module
dff_ns #(1) ff_data_vld_d2(
.din(l2if_data_valid_d1),
.q(l2if_data_valid_d2),
.clk(clk));
// This signal aligns with the flopped data out of ecc_corection module
dff_ns #(1) ff_data_vld_d3(
.din(l2if_data_valid_d2),
.q(l2if_data_valid_d3),
.clk(clk));
// Because the valid signal in cpu clk domain is valid for multiple cycles, we
// have reset the valid after one cpu cycle. Also note that valid would not
// asserted back to back cycles as CAS is not picked back to back cycles.
assign l2if_add_fifo_valid = ~(l2if_dram_clk_toggle_d1 == l2if_dram_clk_toggle) & l2if_send_info[6];
assign l2if_add_scrb_valid = ~(l2if_dram_clk_toggle_d1 == l2if_dram_clk_toggle) & l2if_send_info[5];
// This part of code is keeping the 8 deep FIFO that expects the first data to come back
reg l2if_fifo_ent0_en;
reg l2if_fifo_ent1_en;
reg l2if_fifo_ent2_en;
reg l2if_fifo_ent3_en;
reg l2if_fifo_ent4_en;
reg l2if_fifo_ent5_en;
reg l2if_fifo_ent6_en;
reg l2if_fifo_ent7_en;
always @(l2if_add_fifo_valid or l2if_fifo_ent0 or l2if_fifo_ent1 or l2if_fifo_ent2 or
l2if_fifo_ent3 or l2if_fifo_ent4 or l2if_fifo_ent5 or l2if_fifo_ent6 or l2if_fifo_ent7)
begin
l2if_fifo_ent7_en = 1'b0;
l2if_fifo_ent6_en = 1'b0;
l2if_fifo_ent5_en = 1'b0;
l2if_fifo_ent4_en = 1'b0;
l2if_fifo_ent3_en = 1'b0;
l2if_fifo_ent2_en = 1'b0;
l2if_fifo_ent1_en = 1'b0;
l2if_fifo_ent0_en = 1'b0;
if(~l2if_fifo_ent7[6] & ~l2if_fifo_ent7[5]) begin
l2if_fifo_ent7_en = 1'b1;
l2if_fifo_ent6_en = 1'b1;
l2if_fifo_ent5_en = 1'b1;
l2if_fifo_ent4_en = 1'b1;
l2if_fifo_ent3_en = 1'b1;
l2if_fifo_ent2_en = 1'b1;
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(~l2if_fifo_ent6[6] & ~l2if_fifo_ent6[5]) begin
l2if_fifo_ent6_en = 1'b1;
l2if_fifo_ent5_en = 1'b1;
l2if_fifo_ent4_en = 1'b1;
l2if_fifo_ent3_en = 1'b1;
l2if_fifo_ent2_en = 1'b1;
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(~l2if_fifo_ent5[6] & ~l2if_fifo_ent5[5]) begin
l2if_fifo_ent5_en = 1'b1;
l2if_fifo_ent4_en = 1'b1;
l2if_fifo_ent3_en = 1'b1;
l2if_fifo_ent2_en = 1'b1;
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(~l2if_fifo_ent4[6] & ~l2if_fifo_ent4[5]) begin
l2if_fifo_ent4_en = 1'b1;
l2if_fifo_ent3_en = 1'b1;
l2if_fifo_ent2_en = 1'b1;
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(~l2if_fifo_ent3[6] & ~l2if_fifo_ent3[5]) begin
l2if_fifo_ent3_en = 1'b1;
l2if_fifo_ent2_en = 1'b1;
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(~l2if_fifo_ent2[6] & ~l2if_fifo_ent2[5]) begin
l2if_fifo_ent2_en = 1'b1;
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(~l2if_fifo_ent1[6] & ~l2if_fifo_ent1[5]) begin
l2if_fifo_ent1_en = 1'b1;
l2if_fifo_ent0_en = 1'b1;
end
else if(l2if_add_fifo_valid) begin
l2if_fifo_ent0_en = 1'b1;
end
end
dffrle_ns #(10) l2_fifo_ent0(
.din({l2if_send_info[9:7], l2if_add_fifo_valid, l2if_add_scrb_valid, l2if_send_info[4:0]}),
.q(l2if_fifo_ent0[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent0_en),
.clk(clk));
dffrle_ns #(10) l2_fifo_ent1(
.din(l2if_fifo_ent0[9:0]),
.q(l2if_fifo_ent1[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent1_en),
.clk(clk));
dffrle_ns #(10) l2_fifo_ent2(
.din(l2if_fifo_ent1[9:0]),
.q(l2if_fifo_ent2[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent2_en),
.clk(clk));
dffrle_ns #(10) l2_fifo_ent3(
.din(l2if_fifo_ent2[9:0]),
.q(l2if_fifo_ent3[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent3_en),
.clk(clk));
dffrle_ns #(10) l2_fifo_ent4(
.din(l2if_fifo_ent3[9:0]),
.q(l2if_fifo_ent4[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent4_en),
.clk(clk));
dffrle_ns #(10) l2_fifo_ent5(
.din(l2if_fifo_ent4[9:0]),
.q(l2if_fifo_ent5[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent5_en),
.clk(clk));
dffrle_ns #(10) l2_fifo_ent6(
.din(l2if_fifo_ent5[9:0]),
.q(l2if_fifo_ent6[9:0]),
.rst_l(rst_l),
.en(l2if_fifo_ent6_en),
.clk(clk));
assign l2if_data_valid_reset = l2if_fifo_reset | ~rst_l;
dffrle_ns #(10) l2_fifo_ent7(
.din(l2if_fifo_ent6[9:0]),
.q(l2if_fifo_ent7[9:0]),
.rst_l(~l2if_data_valid_reset),
.en(l2if_fifo_ent7_en),
.clk(clk));
///////
// Stage the toggle to detect the dram clk transition
// Three stages due to 2 for valids in one dram clk and one becuase
// data_valid is also delayed for one cycle due to data delay of 1 cycle to valid.
///////
dff_ns #(1) l2_data_valid(
.din(l2if_dram_clk_toggle),
.q(l2if_dram_clk_toggle_d1),
.clk(clk));
dff_ns #(1) l2_data_valid_d1(
.din(l2if_dram_clk_toggle_d1),
.q(l2if_dram_clk_toggle_d2),
.clk(clk));
//////////////////////////////////////
// VALID and OFFSET generation
//////////////////////////////////////
// To have 2 consecutive cycles of valid, got to use d1 and d3.
assign l2if_data_cnt_val = dp_data_valid_d1 &
~(l2if_dram_clk_toggle_d2 == l2if_dram_clk_toggle);
// Assert valid only when there is no data valid from dp and start of new cycle or data.
assign l2if_dummy_data_cnt_val = (~l2if_channel_disabled & ~dp_data_valid_d1 |
l2if_channel_disabled & ~ch0_dp_data_valid_d1) &
(l2if_dram_rx_sync_d1 & l2if_dram_rd_req &
l2if_rd_dummy_req_p1 | (|l2if_data_cnt) );
assign l2if_data_offset[1:0] = l2if_channel_disabled & ch0_dp_data_valid_d1 ?
ch0_dram_sctag_chunk_id :
(l2if_data_cnt[1:0] == 2'h0) & l2if_data_cnt_val ?
l2if_fifo_ent7[1:0] : (l2if_data_cnt[1:0] == 2'h0) &
~l2if_data_cnt_val & l2if_dummy_data_cnt_val ? l2if_rd_addr_p1[5:4] :
dram_sctag_chunk_id[1:0] + {1'b0,l2if_offset_inc};
assign l2if_data_mux_sel_en = l2if_data_cnt_val & (l2if_fifo_ent7[6] | l2if_fifo_ent7[5]) | // loads | scrub
l2if_dummy_data_cnt_val;
wire l2if_offset_inc_in = l2if_data_cnt_val & l2if_fifo_ent7[6] |
l2if_dummy_data_cnt_val;
assign l2if_l2_val = l2if_channel_disabled & ch0_dp_data_valid_d1 ?
ch0_dram_data_val_other_ch :
l2if_data_cnt_val & l2if_fifo_ent7[6] &
(l2if_channel_disabled == l2if_fifo_ent7[8]) |
l2if_dummy_data_cnt_val;
wire l2if_l2_val_other_ch = l2if_data_cnt_val & l2if_fifo_ent7[6] &
~(l2if_channel_disabled == l2if_fifo_ent7[8]);
wire [2:0] l2if_rd_req_id = l2if_channel_disabled & ch0_dp_data_valid_d1 ?
ch0_dram_sctag_rd_req_id[2:0] :
l2if_data_cnt_val ? l2if_fifo_ent7[4:2] :
l2if_rd_id_p1[2:0];
wire l2if_pa_err_val = l2if_data_cnt_val & l2if_fifo_ent7[7] |
l2if_dummy_data_cnt_val & l2if_split_rd_addr[32];
dffrl_ns #(9) l2_read_response(
.din({l2if_offset_inc_in, l2if_l2_val_other_ch, l2if_data_offset[1:0], l2if_l2_val,
l2if_pa_err_val, l2if_rd_req_id[2:0]}),
.q({l2if_offset_inc, dram_data_val_other_ch, dram_sctag_chunk_id[1:0], dram_sctag_data_vld,
l2if_addr_err, dram_sctag_rd_req_id[2:0]}),
.rst_l(rst_l),
.clk(clk));
// Generate l2if_data_cnt_val for dequeing the 8 deep fifo
assign l2if_fifo_reset = (l2if_data_cnt == 2'h3) & l2if_data_cnt_val;
// Generate scrb_val for dram clk domain to flop data
// Needed to stage for 3 cycles to aligning with data and error signals
wire l2if_scrb_val = l2if_data_cnt_val & l2if_fifo_ent7[5];
dff_ns #(1) ff_scrb_val(
.din(l2if_scrb_val),
.q(l2if_scrb_val_d1),
.clk(clk));
dff_ns #(1) ff_scrb_val_d1(
.din(l2if_scrb_val_d1),
.q(l2if_scrb_val_d2),
.clk(clk));
wire l2if_scrb_val_d3_in = l2if_scrb_val_d2 & ~(l2if_dram_tx_sync & l2if_scrb_val_d3) ;
wire l2if_scrb_val_en = l2if_scrb_val_d3_in | l2if_dram_tx_sync & l2if_scrb_val_d3;
dffrle_ns #(1) ff_scrb_val_d2(
.din(l2if_scrb_val_d3_in),
.q(l2if_scrb_val_d3),
.en(l2if_scrb_val_en),
.rst_l(rst_l),
.clk(clk));
/////////////////////////////////////////////////
// ECC Detect and Correct data
/////////////////////////////////////////////////
// Save addr parity for full dram cycle.
dffe_ns #(1) ff_addr_parity(
.din(l2if_fifo_ent7[9]),
.q(l2if_addr_parity),
.en(l2if_dram_rx_sync),
.clk(clk));
// XOR ecc with addr parity and make data to 0's on dummy loads
wire [31:0] l2if_addr_par_xor_ecc = ~dp_data_valid_d1 ? 32'h0 :
l2if_rd_ecc_p1[31:0] ^ {32{l2if_addr_parity}};
wire [255:0] l2if_data = ~dp_data_valid_d1 ? 256'h0 : l2if_rd_data_p1[255:0];
// Second chunk to L2
dram_ecc_cor dram_ecc_cor_lo(
// Outputs
.ecc_multi_err(ecc_multi_lo_err),
.ecc_single_err(ecc_single_lo_err),
.cor_data (ecc_cor_lo_data[127:0]),
.ecc_loc(ecc_loc_lo[35:0]),
.syndrome (l2if_rd_ecc_d1[15:0]),
// Inputs
.clk (clk),
.l2if_dram_fail_over_mode(l2if_dram_fail_over_mode),
.raw_data(l2if_data[127:0]),
.raw_ecc (l2if_addr_par_xor_ecc[15:0]));
// First chunk to L2
dram_ecc_cor dram_ecc_cor_hi(
// Outputs
.ecc_multi_err(ecc_multi_hi_err),
.ecc_single_err(ecc_single_hi_err),
.cor_data (ecc_cor_hi_data[127:0]),
.ecc_loc(ecc_loc_hi[35:0]),
.syndrome (l2if_rd_ecc_d1[31:16]),
// Inputs
.clk (clk),
.l2if_dram_fail_over_mode(l2if_dram_fail_over_mode),
.raw_data(l2if_data[255:128]),
.raw_ecc (l2if_addr_par_xor_ecc[31:16]));
// Qualify the ecc signals with the valid and also if there is dummy req we have to send 0.
// In normal read followed by dummy read the dummy read val is asserted 1 cycle earlier
// than normal read so need to do this by pass.
wire ecc_multi_hi_err_qual = l2if_data_valid_d2 ? ecc_multi_hi_err : 1'b0;
wire ecc_single_hi_err_qual = l2if_data_valid_d2 ? ecc_single_hi_err : 1'b0;
wire ecc_multi_lo_err_qual = l2if_data_valid_d2 ? ecc_multi_lo_err : 1'b0;
wire ecc_single_lo_err_qual = l2if_data_valid_d2 ? ecc_single_lo_err : 1'b0;
dff_ns #(4) ff_ecc_signals(
.din({ecc_multi_hi_err_qual, ecc_single_hi_err_qual, ecc_multi_lo_err_qual, ecc_single_lo_err_qual}),
.q({ecc_multi_hi_err_d1, ecc_single_hi_err_d1, ecc_multi_lo_err_d1, ecc_single_lo_err_d1}),
.clk(clk));
dff_ns #(256) ff_ecc_cor_data(
.din({ecc_cor_hi_data[127:0], ecc_cor_lo_data[127:0]}),
.q({ecc_cor_mux_hi_data[127:0], ecc_cor_mux_lo_data[127:0]}),
.clk(clk));
// Moved from before the flop to after flop instance ff_ecc_cor_data for timing.
assign ecc_cor_hi_data_d1 = l2if_data_valid_d3 ? ecc_cor_mux_hi_data : 128'h0;
assign ecc_cor_lo_data_d1 = l2if_data_valid_d3 ? ecc_cor_mux_lo_data : 128'h0;
dff_ns #(72) l2_ecc_err_loc(
.din({ecc_loc_hi[35:0], ecc_loc_lo[35:0]}),
.q({ecc_loc_hi_d1[35:0], ecc_loc_lo_d1[35:0]}),
.clk(clk));
// Generate L2 parity
assign l2if_l2_ecc_lo[6:0] = l2_ecc(ecc_cor_lo_data_d1[31:0]);
assign l2if_l2_ecc_lo[13:7] = l2_ecc(ecc_cor_lo_data_d1[63:32]);
assign l2if_l2_ecc_lo[20:14] = l2_ecc(ecc_cor_lo_data_d1[95:64]);
assign l2if_l2_ecc_lo[27:21] = l2_ecc(ecc_cor_lo_data_d1[127:96]);
assign l2if_l2_ecc_hi[6:0] = l2_ecc(ecc_cor_hi_data_d1[31:0]);
assign l2if_l2_ecc_hi[13:7] = l2_ecc(ecc_cor_hi_data_d1[63:32]);
assign l2if_l2_ecc_hi[20:14] = l2_ecc(ecc_cor_hi_data_d1[95:64]);
assign l2if_l2_ecc_hi[27:21] = l2_ecc(ecc_cor_hi_data_d1[127:96]);
////////////////////////////////////////////////
// MUX THE DATA to SEND 128bits at a time.
////////////////////////////////////////////////
dff_ns #(156) l2_read_data_d1(
.din({l2if_l2_ecc_lo[27:0], ecc_cor_lo_data_d1[127:0]}),
.q({l2if_rd_ecc_lo_d1[27:0], l2if_rd_data_d1[127:0]}),
.clk(clk));
// Because the data is 2 cycles after the valid, staging is needed for l2if_data_mux_sel_en
dff_ns #(2) ff_l2if_data_mux_sel_en(
.din({l2if_data_mux_sel_en, l2if_data_mux_sel_en_d1}),
.q({l2if_data_mux_sel_en_d1, l2if_data_mux_sel_en_d2}),
.clk(clk));
assign l2if_data_first_chunk_in = ~l2if_data_first_chunk;
dffrle_ns #(1) l2_data_mux_sel(
.din(l2if_data_first_chunk_in),
.q(l2if_data_first_chunk),
.rst_l(rst_l),
.en(l2if_data_mux_sel_en_d2),
.clk(clk));
assign l2if_ecc_cor_data = l2if_channel_disabled & other_ch_dp_data_valid_d2 ?
ch0_dram_sctag_data : l2if_data_first_chunk ?
ecc_cor_hi_data_d1[127:0] : l2if_rd_data_d1[127:0];
assign l2if_gen_ecc = l2if_channel_disabled & other_ch_dp_data_valid_d2 ? ch0_dram_sctag_ecc :
l2if_data_first_chunk ?
{l2if_l2_ecc_hi[27:23], {2{l2if_mecc_err_partial}} ^ l2if_l2_ecc_hi[22:21],
l2if_l2_ecc_hi[20:16], {2{l2if_mecc_err_partial}} ^ l2if_l2_ecc_hi[15:14],
l2if_l2_ecc_hi[13:9], {2{l2if_mecc_err_partial}} ^ l2if_l2_ecc_hi[8:7],
l2if_l2_ecc_hi[6:2], {2{l2if_mecc_err_partial}} ^ l2if_l2_ecc_hi[1:0]} :
{l2if_rd_ecc_lo_d1[27:23], {2{l2if_mecc_err_partial}} ^ l2if_rd_ecc_lo_d1[22:21],
l2if_rd_ecc_lo_d1[20:16], {2{l2if_mecc_err_partial}} ^ l2if_rd_ecc_lo_d1[15:14],
l2if_rd_ecc_lo_d1[13:9], {2{l2if_mecc_err_partial}} ^ l2if_rd_ecc_lo_d1[8:7],
l2if_rd_ecc_lo_d1[6:2], {2{l2if_mecc_err_partial}} ^ l2if_rd_ecc_lo_d1[1:0]};
dff_ns #(128) l2_read_data_p3(
.din(l2if_ecc_cor_data[127:0]),
.q(dram_sctag_data[127:0]),
.clk(clk));
dff_ns #(28) l2_read_ecc_p3(
.din(l2if_gen_ecc[27:0]),
.q(dram_sctag_ecc[27:0]),
.clk(clk));
// staging OUT OF BOUND error information
dff_ns #(1) addr_out_of_bound_err(
.din(l2if_addr_err),
.q(l2if_addr_err_d1),
.clk(clk));
dff_ns #(1) addr_out_of_bound_err_d1(
.din(l2if_addr_err_d1),
.q(l2if_addr_err_d2),
.clk(clk));
wire l2if_pa_err = l2if_channel_disabled & other_ch_dp_data_valid_d2 ?
ch0_dram_sctag_pa_err : l2if_addr_err_d2;
wire l2if_int_mecc_err_partial = l2if_data_first_chunk ? ecc_multi_hi_err_d1 | l2if_pa_err :
ecc_multi_lo_err_d1 | l2if_pa_err;
assign l2if_mecc_err_partial = l2if_channel_disabled & other_ch_dp_data_valid_d2 ?
ch0_dram_sctag_mecc_err : l2if_int_mecc_err_partial;
assign l2if_secc_err = ~(l2if_mecc_err_partial | l2if_pa_err) &
(l2if_channel_disabled & other_ch_dp_data_valid_d2 ?
ch0_dram_sctag_secc_err : l2if_data_first_chunk ?
ecc_single_hi_err_d1 : ecc_single_lo_err_d1);
dff_ns #(3) l2_mecc_secc(
.din({l2if_pa_err, l2if_mecc_err_partial, l2if_secc_err}),
.q({dram_sctag_pa_err, dram_sctag_mecc_err, dram_sctag_secc_err}),
.clk(clk));
////////////////////////////////////////////////
// Function to generate L2 ecc
////////////////////////////////////////////////
function [6:0] l2_ecc;
input [31:0] data;
begin
// l2 ecc generation
l2_ecc[0] = data[0] ^ data[1] ^ data[3] ^ data[4] ^ data[6] ^ data[8] ^
data[10] ^ data[11] ^ data[13] ^ data[15] ^ data[17] ^ data[19] ^
data[21] ^ data[23] ^ data[25] ^ data[26] ^ data[28] ^ data[30];
l2_ecc[1] = data[0] ^ data[2] ^ data[3] ^ data[5] ^ data[6] ^ data[9] ^
data[10] ^ data[12] ^ data[13] ^ data[16] ^ data[17] ^ data[20] ^
data[21] ^ data[24] ^ data[25] ^ data[27] ^ data[28] ^ data[31];
l2_ecc[2] = data[1] ^ data[2] ^ data[3] ^ data[7] ^ data[8] ^ data[9] ^
data[10] ^ data[14] ^ data[15] ^ data[16] ^ data[17] ^ data[22] ^
data[23] ^ data[24] ^ data[25] ^ data[29] ^ data[30] ^ data[31];
l2_ecc[3] = data[4] ^ data[5] ^data[6] ^data[7] ^data[8] ^data[9] ^data[10] ^
data[18] ^data[19] ^data[20] ^data[21] ^data[22] ^data[23] ^data[24] ^
data[25];
l2_ecc[4] = data[11] ^ data[12] ^ data[13] ^ data[14] ^ data[15] ^ data[16] ^
data[17] ^ data[18] ^ data[19] ^ data[20] ^ data[21] ^ data[22] ^
data[23] ^ data[24] ^ data[25];
l2_ecc[5] = data[26] ^ data[27] ^ data[28] ^ data[29] ^ data[30] ^ data[31];
//l2_ecc[6] = ^{l2_ecc[5:0],data[31:0]};
// Below is the same as above optimized.
l2_ecc[6] = data[0] ^ data[1] ^ data[2] ^ data[4] ^ data[5] ^ data[7] ^
data[10] ^ data[11] ^ data[12] ^ data[14] ^ data[17] ^ data[18] ^
data[21] ^ data[23] ^ data[24] ^ data[26] ^ data[27] ^ data[29];
end
endfunction
//////////////////////////////////////////////////////////////////
// Store the l2 poison bits which could be used later in dp for
// corrupting the data or ecc
//////////////////////////////////////////////////////////////////
// ent0
assign l2if_mecc0_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h0);
assign l2if_data_mecc0_in[0] = ~dram_cpu_wr_en[1] & data_mecc0[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc00 (
.din (l2if_data_mecc0_in[0]),
.q (data_mecc0[0]),
.rst_l (rst_l),
.en (l2if_mecc0_en[0]),
.clk(clk));
assign l2if_mecc0_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h0);
assign l2if_data_mecc0_in[1] = ~dram_cpu_wr_en[3] & data_mecc0[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc01 (
.din (l2if_data_mecc0_in[1]),
.q (data_mecc0[1]),
.rst_l (rst_l),
.en (l2if_mecc0_en[1]),
.clk(clk));
assign l2if_mecc0_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h1);
assign l2if_data_mecc0_in[2] = ~dram_cpu_wr_en[1] & data_mecc0[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc02 (
.din (l2if_data_mecc0_in[2]),
.q (data_mecc0[2]),
.rst_l (rst_l),
.en (l2if_mecc0_en[2]),
.clk(clk));
assign l2if_mecc0_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h1);
assign l2if_data_mecc0_in[3] = ~dram_cpu_wr_en[3] & data_mecc0[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc03 (
.din (l2if_data_mecc0_in[3]),
.q (data_mecc0[3]),
.rst_l (rst_l),
.en (l2if_mecc0_en[3]),
.clk(clk));
// ent1
assign l2if_mecc1_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h2);
assign l2if_data_mecc1_in[0] = ~dram_cpu_wr_en[1] & data_mecc1[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc10 (
.din (l2if_data_mecc1_in[0]),
.q (data_mecc1[0]),
.rst_l (rst_l),
.en (l2if_mecc1_en[0]),
.clk(clk));
assign l2if_mecc1_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h2);
assign l2if_data_mecc1_in[1] = ~dram_cpu_wr_en[3] & data_mecc1[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc11 (
.din (l2if_data_mecc1_in[1]),
.q (data_mecc1[1]),
.rst_l (rst_l),
.en (l2if_mecc1_en[1]),
.clk(clk));
assign l2if_mecc1_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h3);
assign l2if_data_mecc1_in[2] = ~dram_cpu_wr_en[1] & data_mecc1[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc12 (
.din (l2if_data_mecc1_in[2]),
.q (data_mecc1[2]),
.rst_l (rst_l),
.en (l2if_mecc1_en[2]),
.clk(clk));
assign l2if_mecc1_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h3);
assign l2if_data_mecc1_in[3] = ~dram_cpu_wr_en[3] & data_mecc1[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc13 (
.din (l2if_data_mecc1_in[3]),
.q (data_mecc1[3]),
.rst_l (rst_l),
.en (l2if_mecc1_en[3]),
.clk(clk));
// ent2
assign l2if_mecc2_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h4);
assign l2if_data_mecc2_in[0] = ~dram_cpu_wr_en[1] & data_mecc2[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc20 (
.din (l2if_data_mecc2_in[0]),
.q (data_mecc2[0]),
.rst_l (rst_l),
.en (l2if_mecc2_en[0]),
.clk(clk));
assign l2if_mecc2_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h4);
assign l2if_data_mecc2_in[1] = ~dram_cpu_wr_en[3] & data_mecc2[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc21 (
.din (l2if_data_mecc2_in[1]),
.q (data_mecc2[1]),
.rst_l (rst_l),
.en (l2if_mecc2_en[1]),
.clk(clk));
assign l2if_mecc2_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h5);
assign l2if_data_mecc2_in[2] = ~dram_cpu_wr_en[1] & data_mecc2[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc22 (
.din (l2if_data_mecc2_in[2]),
.q (data_mecc2[2]),
.rst_l (rst_l),
.en (l2if_mecc2_en[2]),
.clk(clk));
assign l2if_mecc2_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h5);
assign l2if_data_mecc2_in[3] = ~dram_cpu_wr_en[3] & data_mecc2[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc23 (
.din (l2if_data_mecc2_in[3]),
.q (data_mecc2[3]),
.rst_l (rst_l),
.en (l2if_mecc2_en[3]),
.clk(clk));
// ent3
assign l2if_mecc3_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h6);
assign l2if_data_mecc3_in[0] = ~dram_cpu_wr_en[1] & data_mecc3[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc30 (
.din (l2if_data_mecc3_in[0]),
.q (data_mecc3[0]),
.rst_l (rst_l),
.en (l2if_mecc3_en[0]),
.clk(clk));
assign l2if_mecc3_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h6);
assign l2if_data_mecc3_in[1] = ~dram_cpu_wr_en[3] & data_mecc3[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc31 (
.din (l2if_data_mecc3_in[1]),
.q (data_mecc3[1]),
.rst_l (rst_l),
.en (l2if_mecc3_en[1]),
.clk(clk));
assign l2if_mecc3_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h7);
assign l2if_data_mecc3_in[2] = ~dram_cpu_wr_en[1] & data_mecc3[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc32 (
.din (l2if_data_mecc3_in[2]),
.q (data_mecc3[2]),
.rst_l (rst_l),
.en (l2if_mecc3_en[2]),
.clk(clk));
assign l2if_mecc3_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h7);
assign l2if_data_mecc3_in[3] = ~dram_cpu_wr_en[3] & data_mecc3[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc33 (
.din (l2if_data_mecc3_in[3]),
.q (data_mecc3[3]),
.rst_l (rst_l),
.en (l2if_mecc3_en[3]),
.clk(clk));
// ent4
assign l2if_mecc4_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h8);
assign l2if_data_mecc4_in[0] = ~dram_cpu_wr_en[1] & data_mecc4[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc40 (
.din (l2if_data_mecc4_in[0]),
.q (data_mecc4[0]),
.rst_l (rst_l),
.en (l2if_mecc4_en[0]),
.clk(clk));
assign l2if_mecc4_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h8);
assign l2if_data_mecc4_in[1] = ~dram_cpu_wr_en[3] & data_mecc4[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc41 (
.din (l2if_data_mecc4_in[1]),
.q (data_mecc4[1]),
.rst_l (rst_l),
.en (l2if_mecc4_en[1]),
.clk(clk));
assign l2if_mecc4_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'h9);
assign l2if_data_mecc4_in[2] = ~dram_cpu_wr_en[1] & data_mecc4[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc42 (
.din (l2if_data_mecc4_in[2]),
.q (data_mecc4[2]),
.rst_l (rst_l),
.en (l2if_mecc4_en[2]),
.clk(clk));
assign l2if_mecc4_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'h9);
assign l2if_data_mecc4_in[3] = ~dram_cpu_wr_en[3] & data_mecc4[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc43 (
.din (l2if_data_mecc4_in[3]),
.q (data_mecc4[3]),
.rst_l (rst_l),
.en (l2if_mecc4_en[3]),
.clk(clk));
// ent5
assign l2if_mecc5_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'ha);
assign l2if_data_mecc5_in[0] = ~dram_cpu_wr_en[1] & data_mecc5[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc50 (
.din (l2if_data_mecc5_in[0]),
.q (data_mecc5[0]),
.rst_l (rst_l),
.en (l2if_mecc5_en[0]),
.clk(clk));
assign l2if_mecc5_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'ha);
assign l2if_data_mecc5_in[1] = ~dram_cpu_wr_en[3] & data_mecc5[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc51 (
.din (l2if_data_mecc5_in[1]),
.q (data_mecc5[1]),
.rst_l (rst_l),
.en (l2if_mecc5_en[1]),
.clk(clk));
assign l2if_mecc5_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'hb);
assign l2if_data_mecc5_in[2] = ~dram_cpu_wr_en[1] & data_mecc5[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc52 (
.din (l2if_data_mecc5_in[2]),
.q (data_mecc5[2]),
.rst_l (rst_l),
.en (l2if_mecc5_en[2]),
.clk(clk));
assign l2if_mecc5_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'hb);
assign l2if_data_mecc5_in[3] = ~dram_cpu_wr_en[3] & data_mecc5[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc53 (
.din (l2if_data_mecc5_in[3]),
.q (data_mecc5[3]),
.rst_l (rst_l),
.en (l2if_mecc5_en[3]),
.clk(clk));
// ent6
assign l2if_mecc6_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'hc);
assign l2if_data_mecc6_in[0] = ~dram_cpu_wr_en[1] & data_mecc6[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc60 (
.din (l2if_data_mecc6_in[0]),
.q (data_mecc6[0]),
.rst_l (rst_l),
.en (l2if_mecc6_en[0]),
.clk(clk));
assign l2if_mecc6_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'hc);
assign l2if_data_mecc6_in[1] = ~dram_cpu_wr_en[3] & data_mecc6[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc61 (
.din (l2if_data_mecc6_in[1]),
.q (data_mecc6[1]),
.rst_l (rst_l),
.en (l2if_mecc6_en[1]),
.clk(clk));
assign l2if_mecc6_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'hd);
assign l2if_data_mecc6_in[2] = ~dram_cpu_wr_en[1] & data_mecc6[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc62 (
.din (l2if_data_mecc6_in[2]),
.q (data_mecc6[2]),
.rst_l (rst_l),
.en (l2if_mecc6_en[2]),
.clk(clk));
assign l2if_mecc6_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'hd);
assign l2if_data_mecc6_in[3] = ~dram_cpu_wr_en[3] & data_mecc6[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc63 (
.din (l2if_data_mecc6_in[3]),
.q (data_mecc6[3]),
.rst_l (rst_l),
.en (l2if_mecc6_en[3]),
.clk(clk));
// ent7
assign l2if_mecc7_en[0] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'he);
assign l2if_data_mecc7_in[0] = ~dram_cpu_wr_en[1] & data_mecc7[0] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc70 (
.din (l2if_data_mecc7_in[0]),
.q (data_mecc7[0]),
.rst_l (rst_l),
.en (l2if_mecc7_en[0]),
.clk(clk));
assign l2if_mecc7_en[1] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'he);
assign l2if_data_mecc7_in[1] = ~dram_cpu_wr_en[3] & data_mecc7[1] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc71 (
.din (l2if_data_mecc7_in[1]),
.q (data_mecc7[1]),
.rst_l (rst_l),
.en (l2if_mecc7_en[1]),
.clk(clk));
assign l2if_mecc7_en[2] = |(~dram_cpu_wr_en[1:0]) & (l2if_wr_b0_data_addr[5:2] == 4'hf);
assign l2if_data_mecc7_in[2] = ~dram_cpu_wr_en[1] & data_mecc7[2] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc72 (
.din (l2if_data_mecc7_in[2]),
.q (data_mecc7[2]),
.rst_l (rst_l),
.en (l2if_mecc7_en[2]),
.clk(clk));
assign l2if_mecc7_en[3] = |(~dram_cpu_wr_en[3:2]) & (l2if_wr_b0_data_addr[5:2] == 4'hf);
assign l2if_data_mecc7_in[3] = ~dram_cpu_wr_en[3] & data_mecc7[3] | l2if_dram_data_mecc;
dffrle_ns #(1) l2_mecc73 (
.din (l2if_data_mecc7_in[3]),
.q (data_mecc7[3]),
.rst_l (rst_l),
.en (l2if_mecc7_en[3]),
.clk(clk));
//////////////////////////////////////
// DRAM ERROR STATUS REGISTER WRITE
//////////////////////////////////////
wire l2if_err_sts_reg_en6;
wire l2if_err_sts_reg_en5;
wire l2if_err_sts_reg_en4;
wire l2if_err_sts_reg_en3;
wire l2if_err_sts_reg_en2;
wire l2if_err_sts_reg_en1;
wire l2if_err_sts_reg_en0;
wire l2if_err_sts_reg_en;
wire [22:0] l2if_err_sts_reg_in;
// Because the data valid is three cycles ahead of data the valid is
// needed to be staged two more cyle.
dff_ns #(1) ff_sctag_data_vld_d1(
.din(dram_sctag_data_vld),
.q(dram_sctag_data_vld_d1),
.clk(clk));
dff_ns #(1) ff_sctag_data_vld_d2(
.din(dram_sctag_data_vld_d1),
.q(dram_sctag_data_vld_d2),
.clk(clk));
dff_ns #(6) ff_data_cnt_d1(
.din({l2if_data_cnt[1:0], l2if_data_cnt_d1[1:0], l2if_data_cnt_d2[1:0]}),
.q({l2if_data_cnt_d1[1:0], l2if_data_cnt_d2[1:0], l2if_data_cnt_d3[1:0]}),
.clk(clk));
///////
// Multiple uncorrected errors
// If s/w write and error occurs in same cycle h/w update has priority.
///////
assign l2if_err_sts_reg_en6 = (err_sts_reg[19] | err_sts_reg[17]) &
(l2if_scrb_data_val | dram_sctag_data_vld_d2) &
(l2if_mecc_err_partial & ~l2if_pa_err) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[22] = (err_sts_reg[19] | err_sts_reg[17]) &
(l2if_mecc_err_partial & ~l2if_pa_err) ?
1'b1 : ~l2if_ucb_data[63] & err_sts_reg[22];
dffe_ns #(1) ff_err_sts_bit40(
.din(l2if_err_sts_reg_in[22]),
.q(err_sts_reg[22]),
.en(l2if_err_sts_reg_en6),
.clk(clk));
///////
// Multiple corrected errors
///////
assign l2if_err_sts_reg_en5 = (err_sts_reg[20] | err_sts_reg[18]) &
(l2if_scrb_data_val | dram_sctag_data_vld_d2) &
(l2if_secc_err) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[21] = (err_sts_reg[20] | err_sts_reg[18]) & (l2if_secc_err) ?
1'b1 : ~l2if_ucb_data[62] & err_sts_reg[21];
dffe_ns #(1) ff_err_sts_bit39(
.din(l2if_err_sts_reg_in[21]),
.q(err_sts_reg[21]),
.en(l2if_err_sts_reg_en5),
.clk(clk));
// DRAM access correctable error
assign l2if_err_sts_reg_en4 = dram_sctag_data_vld_d2 & ~err_sts_reg[20] & (l2if_secc_err) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[20] = dram_sctag_data_vld_d2 & ~err_sts_reg[20] & (l2if_secc_err) ?
1'b1 : ~l2if_ucb_data[61] & err_sts_reg[20];
dffe_ns #(1) ff_err_sts_bit37(
.din(l2if_err_sts_reg_in[20]),
.q(err_sts_reg[20]),
.en(l2if_err_sts_reg_en4),
.clk(clk));
///////
// DRAM access uncorrectable error
///////
assign l2if_err_sts_reg_en3 = dram_sctag_data_vld_d2 & ~err_sts_reg[19] &
(l2if_mecc_err_partial & ~l2if_pa_err) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[19] = dram_sctag_data_vld_d2 & ~err_sts_reg[19] &
(l2if_mecc_err_partial & ~l2if_pa_err) ? 1'b1 :
~l2if_ucb_data[60] & err_sts_reg[19];
dffe_ns #(1) ff_err_sts_bit36(
.din(l2if_err_sts_reg_in[19]),
.q(err_sts_reg[19]),
.en(l2if_err_sts_reg_en3),
.clk(clk));
// Scrub access correctable error
assign l2if_err_sts_reg_en2 = l2if_scrb_data_val & ~err_sts_reg[18] & (l2if_secc_err) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[18] = l2if_scrb_data_val & ~err_sts_reg[18] & (l2if_secc_err) ?
1'b1 : ~l2if_ucb_data[59] & err_sts_reg[18];
dffe_ns #(1) ff_err_sts_bit33(
.din(l2if_err_sts_reg_in[18]),
.q(err_sts_reg[18]),
.en(l2if_err_sts_reg_en2),
.clk(clk));
///////
// Scrub access uncorrectable error
///////
assign l2if_err_sts_reg_en1 = l2if_scrb_data_val & ~err_sts_reg[17] & (l2if_mecc_err_partial & ~l2if_pa_err) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[17] = l2if_scrb_data_val & ~err_sts_reg[17] & (l2if_mecc_err_partial & ~l2if_pa_err) ?
1'b1 : ~l2if_ucb_data[58] & err_sts_reg[17];
dffe_ns #(1) ff_err_sts_bit32(
.din(l2if_err_sts_reg_in[17]),
.q(err_sts_reg[17]),
.en(l2if_err_sts_reg_en1),
.clk(clk));
///////
// OUT of BOUND PA error
///////
assign l2if_err_sts_reg_en = dram_sctag_data_vld_d2 & l2if_pa_err | l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[16] = dram_sctag_data_vld_d2 & l2if_pa_err ? 1'b1 : ~l2if_ucb_data[57] & err_sts_reg[16];
dffe_ns #(1) ff_err_sts_bit31(
.din(l2if_err_sts_reg_in[16]),
.q(err_sts_reg[16]),
.en(l2if_err_sts_reg_en),
.clk(clk));
// stage ecc with error signals to capture
dff_ns #(32) ff_ecc_d2(
.din(l2if_rd_ecc_d1[31:0]),
.q(l2if_rd_ecc_d2[31:0]),
.clk(clk));
dff_ns #(32) ff_ecc_d3(
.din(l2if_rd_ecc_d2[31:0]),
.q(l2if_rd_ecc_d3[31:0]),
.clk(clk));
// set it only if there is no prior uncorrectable error and a new uncorrectable one happens
// OR no prior uncorrectable and no prior correctable and new correctable happens
assign l2if_err_sts_reg_en0 = ((~(err_sts_reg[17] | err_sts_reg[19]) & l2if_mecc_err_partial & ~l2if_pa_err &
(l2if_scrb_data_val | dram_sctag_data_vld_d2)) |
(~(err_sts_reg[17] | err_sts_reg[18] | err_sts_reg[19] | err_sts_reg[20]) &
l2if_secc_err & (l2if_scrb_data_val | dram_sctag_data_vld_d2))) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h280);
assign l2if_err_sts_reg_in[15:0] = l2if_channel_disabled & other_ch_dp_data_valid_d2 ?
ch0_err_syn_d1 : ( (~(err_sts_reg[17] | err_sts_reg[19]) &
(l2if_mecc_err_partial & ~l2if_pa_err)) | (~(err_sts_reg[17] | err_sts_reg[18] |
err_sts_reg[19] | err_sts_reg[20]) & l2if_secc_err)) ?
(l2if_data_first_chunk ? l2if_rd_ecc_d3[31:16] : l2if_rd_ecc_d3[15:0]) :
l2if_ucb_data[15:0];
assign err_syn = l2if_data_first_chunk ? l2if_rd_ecc_d3[31:16] : l2if_rd_ecc_d3[15:0];
dffe_ns #(16) ff_err_syn(
.din(l2if_err_sts_reg_in[15:0]),
.q(err_sts_reg[15:0]),
.en(l2if_err_sts_reg_en0),
.clk(clk));
//////////////////////////////////////
// DRAM ERROR ADDRESS REGISTER WRITE
//////////////////////////////////////
wire [35:0] l2if_err_addr_reg_in;
// This address reg can only have scrub address as load address is not kept.
wire l2if_err_addr_reg_en = l2if_scrb_data_val & (l2if_mecc_err_partial & ~l2if_pa_err | l2if_secc_err) &
~(err_sts_reg[18] | err_sts_reg[17]) |
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h288);
assign l2if_err_addr_reg_in = l2if_scrb_data_val & (l2if_mecc_err_partial & ~l2if_pa_err | l2if_secc_err) ?
{3'h0, l2if_scrb_addr[32:2], l2if_data_cnt_d3[1:0]} : l2if_ucb_data[39:4];
dffe_ns #(36) ff_err_addr_reg(
.din(l2if_err_addr_reg_in[35:0]),
.q(err_addr_reg[35:0]),
.en(l2if_err_addr_reg_en),
.clk(clk));
////////////////////////////////////////
// SECC ERROR COUNTER
////////////////////////////////////////
wire [15:0] l2if_secc_cnt_in;
// interrupt enable bit - cleared @ reset and also at every error. S/W has to enable.
wire l2if_secc_int_en = l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h298);
wire l2if_secc_int_in = l2if_ucb_data[17];
dffrle_ns #(1) ff_secc_int_en(
.din(l2if_secc_int_in),
.q(l2if_secc_int_enabled),
.en(l2if_secc_int_en),
.rst_l(rst_l),
.clk(clk));
// counter valid
wire l2if_secc_vld_en = l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h298);
wire l2if_secc_vld_in = l2if_ucb_data[16];
wire l2if_secc_vld_rst_l = rst_l & ~(l2if_secc_vld & l2if_jbus_tx_sync & ~(|l2if_secc_cnt[15:0]));
dffrle_ns #(1) ff_secc_vld(
.din(l2if_secc_vld_in),
.q(l2if_secc_vld),
.en(l2if_secc_vld_en),
.rst_l(l2if_secc_vld_rst_l),
.clk(clk));
// counter value
assign l2if_secc_cnt_in = l2if_secc_err ? ((l2if_secc_cnt != 16'h0) ? (l2if_secc_cnt - 16'h1) :
l2if_secc_cnt) : l2if_ucb_data[15:0];
wire l2if_secc_cnt_en = l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h298) | (l2if_secc_err &
(l2if_scrb_data_val | dram_sctag_data_vld_d2) & l2if_secc_vld);
dffe_ns #(16) ff_secc_cnt(
.din(l2if_secc_cnt_in),
.q(l2if_secc_cnt),
.en(l2if_secc_cnt_en),
.clk(clk));
assign l2if_secc_cnt_intr = l2if_secc_int_enabled & l2if_secc_vld & ~(|l2if_secc_cnt[15:0]);
////////////////////////////////////////
// SECC DEBUG TRIGGER ENABLE REGISTER
////////////////////////////////////////
wire l2if_dbg_trig_in = ~rst_l ? l2if_dbg_trig :
l2if_secc_trig ? 1'b0 :
l2if_ucb_wr_req_vld & (l2if_ucb_addr == 32'h230) ? l2if_ucb_data[2] :
l2if_dbg_trig;
dffrl_async_ns #(1) ff_dbg_trig(
.din(l2if_dbg_trig_in),
.q(l2if_dbg_trig),
.rst_l(arst_l),
.clk(clk));
assign l2if_secc_trig = l2if_dbg_trig & ~(|l2if_secc_cnt[15:0]);
////////////////////////////////////////
// SECC ERROR LOCATION
// The interpretation of the parity is as following ecc[15:0] = {p0,p1,p2,p3} where p3 is not used
// failover mode.
// The error location is as = {err_in_p3, err_in_p2, ... err_in_d2, err_in_d1, err_in_d0}
// If the error location bit is 1, and to create mask in failover mode set all the bits left of 1 to 1
// (including the bit 1 set in err location) upto bit location 34.
// Also this error location once logged will not be over written when another error occurs till S/W
// resets.
////////////////////////////////////////
wire [35:0] l2if_secc_loc_in;
wire l2if_secc_loc_en = l2if_err_sts_reg_en2 & ~err_sts_reg[20] | l2if_err_sts_reg_en4 & ~err_sts_reg[18];
assign l2if_secc_loc_in = l2if_channel_disabled & other_ch_dp_data_valid_d2 ?
ch0_err_loc_d1 : l2if_data_first_chunk ? ecc_loc_hi_d1[35:0] : ecc_loc_lo_d1[35:0];
assign err_loc = l2if_data_first_chunk ? ecc_loc_hi_d1[35:0] : ecc_loc_lo_d1[35:0];
dffe_ns #(36) ff_secc_loc(
.din(l2if_secc_loc_in),
.q(l2if_secc_loc),
.en(l2if_secc_loc_en),
.clk(clk));
////////////////////////////////////////
// Asserting scrub ecc error to L2 cache
////////////////////////////////////////
// use aligned scrub data valid with mecc error as l2if_srb_val three cycle off with ecc.
// Could have used l2if_scrb_val_d3 but its longer than 2 cycles till sync pulse is asserted.
dffrl_ns #(1) ff_scrb_data_en(
.din(l2if_scrb_val_d2),
.q(l2if_scrb_data_val),
.rst_l(rst_l),
.clk(clk));
wire l2if_scb_mecc_err = l2if_scrb_data_val & l2if_mecc_err_partial & ~l2if_pa_err;
wire l2if_scb_secc_err = l2if_scrb_data_val & l2if_secc_err;
dffrl_ns #(1) ff_l2if_scrb_mecc_err(
.din(l2if_scb_mecc_err),
.q(dram_sctag_scb_mecc_err),
.rst_l(rst_l),
.clk(clk));
dffrl_ns #(1) ff_l2if_scrb_secc_err(
.din(l2if_scb_secc_err),
.q(dram_sctag_scb_secc_err),
.rst_l(rst_l),
.clk(clk));
endmodule // dram_l2if
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A211O_2_V
`define SKY130_FD_SC_HS__A211O_2_V
/**
* a211o: 2-input AND into first input of 3-input OR.
*
* X = ((A1 & A2) | B1 | C1)
*
* Verilog wrapper for a211o with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a211o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211o_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a211o_2 (
X ,
A1,
A2,
B1,
C1
);
output X ;
input A1;
input A2;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a211o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A211O_2_V
|
// DO NOT EDIT
// This file is automatically generated!
// $ smg.shen rtl/SMG/seq.smg
//
// https://github.com/sam-falvo/smg
module BottleneckSequencer(
input SAckI,
input ack3,
input ack2,
input ack1,
input MAdrI2,
input MAdrI1,
input MAdrI0,
input MSiz0,
input MSiz1,
input MStbI,
input MCycI,
input ResetI,
output SWeO_MWeI,
output SStbO_MStbI,
output SStbO_1,
output SSizO_MSizI0,
output SSizO_1,
output SSignedO_MSignedI,
output SDatO_MDatI63_48,
output SDatO_MDatI47_32,
output SDatO_MDatI31_16,
output SDatO_MDatI,
output plus6,
output plus4,
output plus2,
output SAdrO_MAdrI,
output MErrAlignO_1,
output MDatO_SDatI,
output MAckO_SAckI,
output MAckO_1,
output Hold3_SDatI,
output Hold2_SDatI,
output Hold1_SDatI,
output ack3_o,
output ack2_o,
output ack1_o
);
wire aligned;
wire R1391 = ~(|ResetI) & (|MCycI) & (|MStbI) & ~(|aligned) ;
wire R1392 = ~(|ResetI) & (|MCycI) & (|MStbI) & ~(|MSiz1) & ~(|MSiz0) ;
wire R1393 = ~(|ResetI) & (|MCycI) & (|MStbI) & ~(|MSiz1) & (|MSiz0) & ~(|MAdrI0) ;
wire R1394 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & ~(|MSiz0) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) ;
wire R1395 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & ~(|MSiz0) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & (|SAckI) ;
wire R1396 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & ~(|MSiz0) & ~(|MAdrI1) & ~(|MAdrI0) & (|ack1) ;
wire R1397 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & ~(|MSiz0) & ~(|MAdrI1) & ~(|MAdrI0) & (|ack1) & ~(|SAckI) ;
wire R1398 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & ~(|MSiz0) & ~(|MAdrI1) & ~(|MAdrI0) & (|ack1) & (|SAckI) ;
wire R1399 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & ~(|ack2) & ~(|ack3) ;
wire R1400 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & ~(|ack2) & ~(|ack3) & (|SAckI) ;
wire R1401 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & ~(|ack2) & (|ack3) ;
wire R1402 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & ~(|ack2) & (|ack3) & (|SAckI) ;
wire R1403 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & (|ack2) & (|ack3) ;
wire R1404 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & ~(|ack1) & (|ack2) & (|ack3) & (|SAckI) ;
wire R1405 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & (|ack1) & (|ack2) & (|ack3) ;
wire R1406 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & (|ack1) & (|ack2) & (|ack3) & ~(|SAckI) ;
wire R1407 = ~(|ResetI) & (|MCycI) & (|MStbI) & (|MSiz1) & (|MSiz0) & ~(|MAdrI2) & ~(|MAdrI1) & ~(|MAdrI0) & (|ack1) & (|ack2) & (|ack3) & (|SAckI) ;
wire out1408 = R1391 ? 1 : 0 ;
wire out1409 = R1392 ? 1 : 0 ;
wire out1410 = R1392 ? 1 : 0 ;
wire out1411 = R1392 ? 1 : 0 ;
wire out1412 = R1392 ? 1 : 0 ;
wire out1413 = R1392 ? 1 : 0 ;
wire out1414 = R1392 ? 1 : 0 ;
wire out1415 = R1392 ? 1 : 0 ;
wire out1416 = R1392 ? 1 : 0 ;
wire out1417 = R1392 ? 1 : 0 ;
wire out1418 = R1393 ? 1 : 0 ;
wire out1419 = R1393 ? 1 : 0 ;
wire out1420 = R1393 ? 1 : 0 ;
wire out1421 = R1393 ? 1 : 0 ;
wire out1422 = R1393 ? 1 : 0 ;
wire out1423 = R1393 ? 1 : 0 ;
wire out1424 = R1393 ? 1 : 0 ;
wire out1425 = R1393 ? 1 : 0 ;
wire out1426 = R1393 ? 1 : 0 ;
wire out1427 = R1394 ? 1 : 0 ;
wire out1428 = R1394 ? 1 : 0 ;
wire out1429 = R1394 ? 1 : 0 ;
wire out1430 = R1394 ? 1 : 0 ;
wire out1431 = R1394 ? 1 : 0 ;
wire out1432 = R1394 ? 1 : 0 ;
wire out1433 = R1394 ? 1 : 0 ;
wire out1434 = R1394 ? 1 : 0 ;
wire out1435 = R1394 ? 1 : 0 ;
wire out1436 = R1395 ? 1 : 0 ;
wire out1437 = R1395 ? 1 : 0 ;
wire out1438 = R1396 ? 1 : 0 ;
wire out1439 = R1396 ? 1 : 0 ;
wire out1440 = R1396 ? 1 : 0 ;
wire out1441 = R1396 ? 1 : 0 ;
wire out1442 = R1396 ? 1 : 0 ;
wire out1443 = R1396 ? 1 : 0 ;
wire out1444 = R1396 ? 1 : 0 ;
wire out1445 = R1396 ? 1 : 0 ;
wire out1446 = R1397 ? 1 : 0 ;
wire out1447 = R1398 ? 1 : 0 ;
wire out1448 = R1399 ? 1 : 0 ;
wire out1449 = R1399 ? 1 : 0 ;
wire out1450 = R1399 ? 1 : 0 ;
wire out1451 = R1399 ? 1 : 0 ;
wire out1452 = R1399 ? 1 : 0 ;
wire out1453 = R1399 ? 1 : 0 ;
wire out1454 = R1399 ? 1 : 0 ;
wire out1455 = R1399 ? 1 : 0 ;
wire out1456 = R1399 ? 1 : 0 ;
wire out1457 = R1400 ? 1 : 0 ;
wire out1458 = R1401 ? 1 : 0 ;
wire out1459 = R1401 ? 1 : 0 ;
wire out1460 = R1401 ? 1 : 0 ;
wire out1461 = R1401 ? 1 : 0 ;
wire out1462 = R1401 ? 1 : 0 ;
wire out1463 = R1401 ? 1 : 0 ;
wire out1464 = R1401 ? 1 : 0 ;
wire out1465 = R1401 ? 1 : 0 ;
wire out1466 = R1401 ? 1 : 0 ;
wire out1467 = R1401 ? 1 : 0 ;
wire out1468 = R1402 ? 1 : 0 ;
wire out1469 = R1402 ? 1 : 0 ;
wire out1470 = R1403 ? 1 : 0 ;
wire out1471 = R1403 ? 1 : 0 ;
wire out1472 = R1403 ? 1 : 0 ;
wire out1473 = R1403 ? 1 : 0 ;
wire out1474 = R1403 ? 1 : 0 ;
wire out1475 = R1403 ? 1 : 0 ;
wire out1476 = R1403 ? 1 : 0 ;
wire out1477 = R1403 ? 1 : 0 ;
wire out1478 = R1403 ? 1 : 0 ;
wire out1479 = R1403 ? 1 : 0 ;
wire out1480 = R1403 ? 1 : 0 ;
wire out1481 = R1404 ? 1 : 0 ;
wire out1482 = R1404 ? 1 : 0 ;
wire out1483 = R1404 ? 1 : 0 ;
wire out1484 = R1405 ? 1 : 0 ;
wire out1485 = R1405 ? 1 : 0 ;
wire out1486 = R1405 ? 1 : 0 ;
wire out1487 = R1405 ? 1 : 0 ;
wire out1488 = R1405 ? 1 : 0 ;
wire out1489 = R1405 ? 1 : 0 ;
wire out1490 = R1405 ? 1 : 0 ;
wire out1491 = R1405 ? 1 : 0 ;
wire out1492 = R1406 ? 1 : 0 ;
wire out1493 = R1406 ? 1 : 0 ;
wire out1494 = R1406 ? 1 : 0 ;
wire out1495 = R1407 ? 1 : 0 ;
assign SStbO_MStbI = out1422|out1413;
assign plus2 = out1471|out1428;
assign SStbO_1 = out1488|out1475|out1463|out1453|out1442|out1432;
assign plus4 = out1459;
assign plus6 = out1449;
assign SSignedO_MSignedI = out1486|out1473|out1461|out1451|out1440|out1430|out1420|out1411;
assign SSizO_1 = out1487|out1474|out1462|out1452|out1441|out1431;
assign aligned = out1491|out1478|out1466|out1456|out1445|out1437|out1435|out1426|out1417;
assign MAckO_SAckI = out1424|out1415;
assign ack1_o = out1492|out1481|out1446|out1436;
assign ack2_o = out1493|out1482|out1479|out1468;
assign ack3_o = out1494|out1483|out1480|out1469|out1467|out1457;
assign SAdrO_MAdrI = out1484|out1470|out1458|out1448|out1438|out1427|out1418|out1409;
assign SDatO_MDatI31_16 = out1472|out1429;
assign SDatO_MDatI = out1485|out1439|out1419|out1410;
assign MDatO_SDatI = out1490|out1444|out1425|out1416;
assign MAckO_1 = out1495|out1447;
assign Hold1_SDatI = out1477|out1434;
assign SDatO_MDatI47_32 = out1460;
assign Hold2_SDatI = out1465;
assign Hold3_SDatI = out1455;
assign SSizO_MSizI0 = out1421|out1412;
assign SDatO_MDatI63_48 = out1450;
assign SWeO_MWeI = out1489|out1476|out1464|out1454|out1443|out1433|out1423|out1414;
assign MErrAlignO_1 = out1408;
endmodule
|
module top
(
output wire MOSI,
output wire CSB,
output wire DRCK1,
input MISO
);
wire CAPTURE;
wire UPDATE;
wire TDI;
wire TDO1;
reg [47:0] header;
reg [15:0] len;
reg have_header = 0;
assign MOSI = TDI ;
wire SEL1;
wire SHIFT;
wire RESET;
reg CS_GO = 0;
reg CS_GO_PREP = 0;
reg CS_STOP = 0;
reg CS_STOP_PREP = 0;
reg [13:0] RAM_RADDR;
reg [13:0] RAM_WADDR;
wire DRCK1_INV = !DRCK1;
wire RAM_DO;
wire RAM_DI;
reg RAM_WE = 0;
RAMB16_S1_S1 RAMB16_S1_S1_inst
(
.DOA(RAM_DO),
.DOB(),
.ADDRA(RAM_RADDR),
.ADDRB(RAM_WADDR),
.CLKA(DRCK1_INV),
.CLKB(DRCK1),
.DIA(1'b0),
.DIB(RAM_DI),
.ENA(1'b1),
.ENB(1'b1),
.SSRA(1'b0),
.SSRB(1'b0),
.WEA(1'b0),
.WEB(RAM_WE)
);
BSCAN_SPARTAN6 BSCAN_SPARTAN6_inst
(
.CAPTURE(CAPTURE),
.DRCK(DRCK1),
.RESET(RESET),
.RUNTEST(),
.SEL(SEL1),
.SHIFT(SHIFT),
.TCK(),
.TDI(TDI),
.TMS(),
.UPDATE(UPDATE),
.TDO(TDO1)
);
`include "bscan_common.vh"
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21OI_BLACKBOX_V
`define SKY130_FD_SC_LS__A21OI_BLACKBOX_V
/**
* a21oi: 2-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2) | B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a21oi (
Y ,
A1,
A2,
B1
);
output Y ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21OI_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FAH_1_V
`define SKY130_FD_SC_HS__FAH_1_V
/**
* fah: Full adder.
*
* Verilog wrapper for fah with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fah.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fah_1 (
COUT,
SUM ,
A ,
B ,
CI ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fah_1 (
COUT,
SUM ,
A ,
B ,
CI
);
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fah base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CI(CI)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FAH_1_V
|
`include "defines.v"
module ex (
// 从 ID 输出
input wire rst,
input wire[`AluOpBus] aluop_i,
input wire[`AluSelBus] alusel_i,
input wire[`RegBus] reg1_i,
input wire[`RegBus] reg2_i,
input wire[`RegAddrBus] waddr_i,
input wire we_i,
input wire[`RegBus] link_address_i,
input wire is_in_delayslot_i,
input wire[`RegBus] inst_i,
input wire[`RegBus] excepttype_i,
input wire[`RegBus] current_inst_addr_i,
input wire current_inst_loaded_i,
// 从 EX/MEM 输入
input wire[`DoubleRegBus] hilo_temp_i,
input wire[1:0] cnt_i,
// 从 MEM 输入
input wire mem_whilo_i,
input wire[`RegBus] mem_hi_i,
input wire[`RegBus] mem_lo_i,
input wire[`RegBus] mem_cp0_reg_data,
input wire[`RegAddrBus] mem_cp0_reg_waddr,
input wire mem_cp0_reg_we,
// 从 WB 输入
input wire wb_whilo_i,
input wire[`RegBus] wb_hi_i,
input wire[`RegBus] wb_lo_i,
input wire[`RegBus] wb_cp0_reg_data,
input wire[`RegAddrBus] wb_cp0_reg_waddr,
input wire wb_cp0_reg_we,
// 从 hilo_reg 输入
input wire[`RegBus] hi_i,
input wire[`RegBus] lo_i,
// 从 DIV 输入
input wire[`DoubleRegBus] div_result_i,
input wire div_result_ready_i,
// 从 CP0 输入
input wire[`RegBus] cp0_reg_data_i,
// 输出给 EX/MEM
output reg[`RegAddrBus] waddr_o,
output reg we_o,
output reg[`RegBus] wdata_o,
output reg whilo_o,
output reg[`RegBus] hi_o,
output reg[`RegBus] lo_o,
output reg[`DoubleRegBus] hilo_temp_o,
output reg[1:0] cnt_o,
output wire[`AluOpBus] aluop_o,
output wire[`RegBus] mem_addr_o,
output wire[`RegBus] reg2_o,
output reg[`RegBus] cp0_reg_data_o,
output reg[`RegAddrBus] cp0_reg_waddr_o,
output reg cp0_reg_we_o,
output wire[`RegBus] excepttype_o,
output wire[`RegBus] current_inst_addr_o,
output wire current_inst_loaded_o,
output wire is_in_delayslot_o,
// 输出给 CTRL
output reg stallreq,
// 输出给 DIV
output reg signed_div_o,
output reg[`RegBus] div_opdata1_o, // 被除数
output reg[`RegBus] div_opdata2_o, // 除数
output reg div_start_o,
// 输出给 CP0
output reg[`RegAddrBus] cp0_reg_raddr_o
);
// 保存运算结果
reg[`RegBus] logicout;
reg[`RegBus] shiftout;
reg[`RegBus] moveout;
reg[`RegBus] mathout;
reg[`DoubleRegBus] mulout;
// 存放输入
reg[`RegBus] hi_i_reg;
reg[`RegBus] lo_i_reg;
// 算数运算的中间变量
wire overflow_sum;
wire reg1_lt_reg2;
wire[`RegBus] reg2_i_mux;
wire[`RegBus] reg1_i_not;
wire[`RegBus] result_sum;
wire[`RegBus] opdata1_mult;
wire[`RegBus] opdata2_mult;
wire[`DoubleRegBus] hilo_temp;
// stall
reg stallreq_for_madd_msub;
reg stallreq_for_div;
reg[`DoubleRegBus] hilo_temp_stall;
// exception
reg trapassert;
reg ovassert;
// 会传递到访存阶段，届时利用其确定加载、存储类型
assign aluop_o = aluop_i;
// mem_addr_o 是加载、存储指令对应的存储器地址
// reg1_i 是 base
assign mem_addr_o = reg1_i + {{16{inst_i[15]}}, inst_i[15:0]};
// 存储指令要存储的数据，和 LWL、LWR 中要使用的目的寄存器的值
assign reg2_o = reg2_i;
// 执行阶段的异常信息，就是在译码阶段的异常信息基础上加上自陷异常、溢出异常的信息
assign excepttype_o = {excepttype_i[31:12], ovassert, trapassert, excepttype_i[9:8], 8'h00};
assign is_in_delayslot_o = is_in_delayslot_i;
assign current_inst_addr_o = current_inst_addr_i;
assign current_inst_loaded_o = current_inst_loaded_i;
// 选择 HI LO 的输入
always @(*) begin
if (rst == `RstEnable) begin
hi_i_reg <= `ZeroWord;
lo_i_reg <= `ZeroWord;
end
else if (mem_whilo_i == `WriteEnable) begin
hi_i_reg <= mem_hi_i;
lo_i_reg <= mem_lo_i;
end
else if (wb_whilo_i == `WriteEnable) begin
hi_i_reg <= wb_hi_i;
lo_i_reg <= wb_lo_i;
end
else begin
hi_i_reg <= hi_i;
lo_i_reg <= lo_i;
end
end
// LOGIC
always @(*) begin
if (rst == `RstEnable) begin
logicout <= `ZeroWord;
end
else begin
case (aluop_i)
`EXE_OP_LOGIC_AND: begin
logicout <= reg1_i & reg2_i;
end
`EXE_OP_LOGIC_OR: begin
logicout <= reg1_i | reg2_i;
end
`EXE_OP_LOGIC_XOR: begin
logicout <= reg1_i ^ reg2_i;
end
`EXE_OP_LOGIC_NOR: begin
logicout <= ~(reg1_i | reg2_i);
end
default: begin
logicout <= `ZeroWord;
end
endcase
end
end
// SHIFT
always @(*) begin
if (rst == `RstEnable) begin
shiftout <= `ZeroWord;
end
else begin
case (aluop_i)
`EXE_OP_SHIFT_SLL: begin
shiftout <= reg2_i << reg1_i[4:0];
end
`EXE_OP_SHIFT_SRL: begin
shiftout <= reg2_i >> reg1_i[4:0];
end
`EXE_OP_SHIFT_SRA: begin
// 算数右移的操作相对复杂一些
shiftout <= (reg2_i >> reg1_i[4:0]) | ({32{reg2_i[31]}} << (6'd32 - {1'b0, reg1_i[4:0]}));
end
default: begin
shiftout <= `ZeroWord;
end
endcase
end
end
// MOVE
always @(*) begin
if (rst == `RstEnable) begin
moveout <= `ZeroWord;
end
else begin
case (aluop_i)
`EXE_OP_MOVE_MOVZ: begin
moveout <= reg1_i;
end
`EXE_OP_MOVE_MOVN: begin
moveout <= reg1_i;
end
`EXE_OP_MOVE_MFHI: begin
moveout <= hi_i_reg;
end
`EXE_OP_MOVE_MFLO: begin
moveout <= lo_i_reg;
end
`EXE_OP_MOVE_MFC0: begin
// 要从 CP0 中读取的寄存器的地址
cp0_reg_raddr_o <= inst_i[15:11];
// 读取到的值
moveout <= cp0_reg_data_i;
// 判断是否存在数据相关
if (mem_cp0_reg_we == `WriteEnable && mem_cp0_reg_waddr == cp0_reg_raddr_o) begin
moveout <= mem_cp0_reg_data;
end
else if (wb_cp0_reg_we == `WriteEnable && wb_cp0_reg_waddr == cp0_reg_raddr_o) begin
moveout <= mem_cp0_reg_data;
end
end
default: begin
moveout <= `ZeroWord;
end
endcase
end
end
always @(*) begin
if (rst == `RstEnable) begin
cp0_reg_waddr_o <= 5'b00000;
cp0_reg_we_o <= `WriteDisable;
cp0_reg_data_o <= `ZeroWord;
end
else if (aluop_i == `EXE_OP_MOVE_MTC0) begin
cp0_reg_waddr_o <= inst_i[15:11];
cp0_reg_we_o <= `WriteEnable;
cp0_reg_data_o <= reg1_i;
end
else begin
cp0_reg_waddr_o <= 5'b00000;
cp0_reg_we_o <= `WriteDisable;
cp0_reg_data_o <= `ZeroWord;
end
end
// MATH
// --- 第一段：计算以下 5 个变量的值 ---
// (1) 如果是减法或者大小比较，就把数字换成它的负数形式？用补码来表示。
assign reg2_i_mux = ((aluop_i == `EXE_OP_MATH_SUB) ||
(aluop_i == `EXE_OP_MATH_SUBU) ||
(aluop_i == `EXE_OP_MATH_SLT) ||
(aluop_i == `EXE_OP_EXCEPTION_TLT) ||
(aluop_i == `EXE_OP_EXCEPTION_TLTI) ||
(aluop_i == `EXE_OP_EXCEPTION_TGE) ||
(aluop_i == `EXE_OP_EXCEPTION_TGEI)) ?
(~reg2_i) + 1 : reg2_i;
// (2) 加法就是加法，减法就是减法，比较运算用减法
assign result_sum = reg1_i + reg2_i_mux;
// (3) 判断是不是溢出
// 1. 正 + 正变负
// 2. 负 + 负变正
assign overflow_sum = ((!reg1_i[31] && !reg2_i_mux[31]) && result_sum[31]) ||
((reg1_i[31] && reg2_i_mux[31]) && !result_sum[31]);
// (4) 计算操作数 1 是不是小于操作数 2
// 有符号时又几种情况
// 1. o1 < 0, o2 > 0
// 2. o1 > 0, o2 > 0, sub < 0
// 3. o1 < 0, o2 < 0, sub < 0
// 无符号时直接比较大小
assign reg1_lt_reg2 = (aluop_i == `EXE_OP_MATH_SLT) ||
(aluop_i == `EXE_OP_EXCEPTION_TLT) ||
(aluop_i == `EXE_OP_EXCEPTION_TLTI) ||
(aluop_i == `EXE_OP_EXCEPTION_TGE) ||
(aluop_i == `EXE_OP_EXCEPTION_TGEI) ?
((reg1_i[31] && !reg2_i[31]) || (!reg1_i[31] && !reg2_i[31] && result_sum[31]) || (reg1_i[31] && reg2_i[31] && result_sum[31])) : (reg1_i < reg2_i);
// (5) 对操作数 1 逐位取反，赋给 reg1_i_not
assign reg1_i_not = ~reg1_i;
// --- 第二段：对不同的算数运算进行赋值 ---
always @(*) begin
if (rst == `RstEnable) begin
mathout <= `ZeroWord;
end else begin
case (aluop_i)
`EXE_OP_MATH_ADD, `EXE_OP_MATH_ADDU, `EXE_OP_MATH_ADDI, `EXE_OP_MATH_ADDIU: begin
mathout <= result_sum;
end
`EXE_OP_MATH_SUB, `EXE_OP_MATH_SUBU: begin
mathout <= result_sum;
end
`EXE_OP_MATH_SLT, `EXE_OP_MATH_SLTU: begin
mathout <= reg1_lt_reg2;
end
`EXE_OP_MATH_CLO: begin
mathout <= reg1_i_not[31] ? 0 :
reg1_i_not[30] ? 1 :
reg1_i_not[29] ? 2 :
reg1_i_not[28] ? 3 :
reg1_i_not[27] ? 4 :
reg1_i_not[26] ? 5 :
reg1_i_not[25] ? 6 :
reg1_i_not[24] ? 7 :
reg1_i_not[23] ? 8 :
reg1_i_not[22] ? 9 :
reg1_i_not[21] ? 10 :
reg1_i_not[20] ? 11 :
reg1_i_not[19] ? 12 :
reg1_i_not[18] ? 13 :
reg1_i_not[17] ? 14 :
reg1_i_not[16] ? 15 :
reg1_i_not[15] ? 16 :
reg1_i_not[14] ? 17 :
reg1_i_not[13] ? 18 :
reg1_i_not[12] ? 19 :
reg1_i_not[11] ? 20 :
reg1_i_not[10] ? 21 :
reg1_i_not[9] ? 22 :
reg1_i_not[8] ? 23 :
reg1_i_not[7] ? 24 :
reg1_i_not[6] ? 25 :
reg1_i_not[5] ? 26 :
reg1_i_not[4] ? 27 :
reg1_i_not[3] ? 28 :
reg1_i_not[2] ? 29 :
reg1_i_not[1] ? 30 :
reg1_i_not[0] ? 31 : 32;
end
`EXE_OP_MATH_CLZ: begin
mathout <= reg1_i[31] ? 0 :
reg1_i[30] ? 1 :
reg1_i[29] ? 2 :
reg1_i[28] ? 3 :
reg1_i[27] ? 4 :
reg1_i[26] ? 5 :
reg1_i[25] ? 6 :
reg1_i[24] ? 7 :
reg1_i[23] ? 8 :
reg1_i[22] ? 9 :
reg1_i[21] ? 10 :
reg1_i[20] ? 11 :
reg1_i[19] ? 12 :
reg1_i[18] ? 13 :
reg1_i[17] ? 14 :
reg1_i[16] ? 15 :
reg1_i[15] ? 16 :
reg1_i[14] ? 17 :
reg1_i[13] ? 18 :
reg1_i[12] ? 19 :
reg1_i[11] ? 20 :
reg1_i[10] ? 21 :
reg1_i[9] ? 22 :
reg1_i[8] ? 23 :
reg1_i[7] ? 24 :
reg1_i[6] ? 25 :
reg1_i[5] ? 26 :
reg1_i[4] ? 27 :
reg1_i[3] ? 28 :
reg1_i[2] ? 29 :
reg1_i[1] ? 30 :
reg1_i[0] ? 31 : 32;
end
default: begin
mathout <= `ZeroWord;
end
endcase
end
end
// 判断是否发生自陷异常
always @(*) begin
if (rst == `RstEnable) begin
trapassert <= `TrapNotAssert;
end
else begin
trapassert <= `TrapNotAssert;
case (aluop_i)
// teg, tegi
`EXE_OP_EXCEPTION_TEQ, `EXE_OP_EXCEPTION_TEQI: begin
if (reg1_i == reg2_i) begin
trapassert <= `TrapAssert;
end
end
// tge, tgei, tgeiu, tgeu
`EXE_OP_EXCEPTION_TGE, `EXE_OP_EXCEPTION_TGEI, `EXE_OP_EXCEPTION_TGEIU, `EXE_OP_EXCEPTION_TGEU: begin
if (~reg1_lt_reg2) begin
trapassert <= `TrapAssert;
end
end
// tlt, tlti, tltiu, tltu
`EXE_OP_EXCEPTION_TLT, `EXE_OP_EXCEPTION_TLTI, `EXE_OP_EXCEPTION_TLTIU, `EXE_OP_EXCEPTION_TLTU: begin
if (reg1_lt_reg2) begin
trapassert <= `TrapAssert;
end
end
// tne, tnei
`EXE_OP_EXCEPTION_TNE, `EXE_OP_EXCEPTION_TNEI: begin
if (reg1_i != reg2_i) begin
trapassert <= `TrapAssert;
end
end
endcase
end
end
// 判断是否发生溢出异常
always @(*) begin
if ((aluop_i == `EXE_OP_MATH_ADD || aluop_i == `EXE_OP_MATH_ADDI || aluop_i == `EXE_OP_MATH_SUB) && overflow_sum == 1'b1) begin
we_o <= `WriteDisable;
ovassert <= 1'b1;
end
else begin
we_o <= we_i;
ovassert <= 1'b0;
end
end
// --- 第三段：进行乘法运算 ---
// (1) 取得乘法运算的被乘数，如果是有符号乘法且被乘数是负数，那么取补码
assign opdata1_mult = (((aluop_i == `EXE_OP_MATH_MUL) ||
(aluop_i == `EXE_OP_MATH_MULT) ||
(aluop_i == `EXE_OP_MATH_MADD) ||
(aluop_i == `EXE_OP_MATH_MSUB)) && (reg1_i[31] == 1'b1)) ? (~reg1_i + 1) : reg1_i;
// (2) 取得乘法运算的乘数，如果是有符号乘法且被乘数是负数，那么取补码
assign opdata2_mult = (((aluop_i == `EXE_OP_MATH_MUL) ||
(aluop_i == `EXE_OP_MATH_MULT) ||
(aluop_i == `EXE_OP_MATH_MADD) ||
(aluop_i == `EXE_OP_MATH_MSUB)) && (reg2_i[31] == 1'b1)) ? (~reg2_i + 1) : reg2_i;
// (3) 得到临时乘法结果，保存在变量 hilo_temp 中
assign hilo_temp = opdata1_mult * opdata2_mult;
// (4) 修正临时乘法结果的符号
always @(*) begin
if (rst == `RstEnable) begin
mulout <= {`ZeroWord, `ZeroWord};
end
else begin
if ((aluop_i == `EXE_OP_MATH_MULT) || (aluop_i == `EXE_OP_MATH_MUL) || (aluop_i == `EXE_OP_MATH_MADD) || (aluop_i == `EXE_OP_MATH_MSUB)) begin
if (reg1_i[31] ^ reg2_i[31] == 1'b1) begin
mulout <= ~hilo_temp + 1;
end
else begin
mulout <= hilo_temp;
end
end
else begin
mulout <= hilo_temp;
end
end
end
// MADD, MADDU, MSUB, MSUBU
always @(*) begin
if (rst == `RstEnable) begin
hilo_temp_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
stallreq_for_madd_msub <= `StallDisable;
end
else begin
case (aluop_i)
`EXE_OP_MATH_MADD, `EXE_OP_MATH_MADDU: begin
if (cnt_i == 2'b00) begin // 第一个时钟周期
hilo_temp_o <= mulout;
cnt_o <= 2'b01;
hilo_temp_stall <= {`ZeroWord, `ZeroWord};
stallreq_for_madd_msub <= `StallEnable;
end
else if (cnt_i == 2'b01) begin // 第二个时钟周期
hilo_temp_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b10;
hilo_temp_stall <= hilo_temp_i + {hi_i_reg, lo_i_reg};
stallreq_for_madd_msub <= `StallDisable;
end
end
`EXE_OP_MATH_MSUB, `EXE_OP_MATH_MSUBU: begin
if (cnt_i == 2'b00) begin
hilo_temp_o <= ~mulout + 1;
cnt_o <= 2'b01;
hilo_temp_stall <= {`ZeroWord, `ZeroWord};
stallreq_for_madd_msub <= `StallEnable;
end
else if (cnt_i == 2'b01) begin
hilo_temp_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b10;
hilo_temp_stall <= hilo_temp_i + {hi_i_reg, lo_i_reg};
stallreq_for_madd_msub <= `StallDisable;
end
end
default: begin
hilo_temp_o <= {`ZeroWord, `ZeroWord};
cnt_o <= 2'b00;
stallreq_for_madd_msub <= `StallDisable;
end
endcase
end
end
// DIV, DIVU
always @(*) begin
if (rst == `RstEnable) begin
stallreq_for_div <= `StallDisable;
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivNotStart;
signed_div_o <= `DivNotSigned;
end
else begin
stallreq_for_div <= `StallDisable;
div_opdata1_o <= `ZeroWord;
div_opdata2_o <= `ZeroWord;
div_start_o <= `DivNotStart;
signed_div_o <= `DivNotSigned;
case (aluop_i)
`EXE_OP_MATH_DIV: begin
if (div_result_ready_i <= `DivResultNotReady) begin
div_opdata1_o <= reg1_i; // 被除数
div_opdata2_o <= reg2_i; // 除数
div_start_o <= `DivStart;
signed_div_o <= `DivSigned;
stallreq_for_div <= `StallEnable;
end
else if (div_result_ready_i <= `DivResultNotReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivNotStart;
signed_div_o <= `DivSigned;
stallreq_for_div <= `StallDisable;
end
end
`EXE_OP_MATH_DIVU: begin
if (div_result_ready_i <= `DivResultNotReady) begin
div_opdata1_o <= reg1_i; // 被除数
div_opdata2_o <= reg2_i; // 除数
div_start_o <= `DivStart;
signed_div_o <= `DivNotSigned;
stallreq_for_div <= `StallEnable;
end
else if (div_result_ready_i <= `DivResultNotReady) begin
div_opdata1_o <= reg1_i;
div_opdata2_o <= reg2_i;
div_start_o <= `DivNotStart;
signed_div_o <= `DivNotSigned;
stallreq_for_div <= `StallDisable;
end
end
endcase
end
end
// HI LO 输出
always @(*) begin
if (rst == `RstEnable) begin
whilo_o <= `WriteDisable;
hi_o <= `ZeroWord;
lo_o <= `ZeroWord;
end
else begin
case (aluop_i)
`EXE_OP_OTHER_MTHI: begin
whilo_o <= `WriteEnable;
hi_o <= reg1_i;
lo_o <= lo_i_reg;
end
`EXE_OP_OTHER_MTLO: begin
whilo_o <= `WriteEnable;
hi_o <= hi_i_reg;
lo_o <= reg1_i;
end
`EXE_OP_MATH_MULT, `EXE_OP_MATH_MULTU: begin
whilo_o <= `WriteEnable;
hi_o <= mulout[63:32];
lo_o <= mulout[31:0];
end
`EXE_OP_MATH_MADD, `EXE_OP_MATH_MADDU: begin
whilo_o <= `WriteEnable;
hi_o <= hilo_temp_stall[63:32];
lo_o <= hilo_temp_stall[31:0];
end
`EXE_OP_MATH_MSUB, `EXE_OP_MATH_MSUBU: begin
whilo_o <= `WriteEnable;
hi_o <= hilo_temp_stall[63:32];
lo_o <= hilo_temp_stall[31:0];
end
`EXE_OP_MATH_DIV, `EXE_OP_MATH_DIVU: begin
whilo_o <= `WriteEnable;
hi_o <= div_result_i[63:32];
lo_o <= div_result_i[31:0];
end
default: begin
whilo_o <= `WriteDisable;
hi_o <= hi_i_reg;
lo_o <= lo_i_reg;
end
endcase
end
end
// 根据 alusel_i 指示的运算类型，选择一个运算结果作为最终结果
always @(*) begin
waddr_o <= waddr_i;
we_o <= we_i;
case (alusel_i)
`EXE_RES_LOGIC: begin
wdata_o <= logicout;
end
`EXE_RES_SHIFT: begin
wdata_o <= shiftout;
end
`EXE_RES_MOVE: begin
wdata_o <= moveout;
end
`EXE_RES_MATH: begin
wdata_o <= mathout;
end
`EXE_RES_MUL: begin
wdata_o <= mulout[31:0];
end
`EXE_RES_JUMP_BRANCH: begin
wdata_o <= link_address_i;
end
default: begin
wdata_o <= `ZeroWord;
end
endcase
end
always @ (*) begin
stallreq = stallreq_for_madd_msub || stallreq_for_div;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_BLACKBOX_V
/**
* clkdlyinv5sd3: Clock Delay Inverter 5-stage 0.50um length inner
* stage gate.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__clkdlyinv5sd3 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV5SD3_PP_BLACKBOX_V
|
// Generated by Cadence Encounter(r) RTL Compiler v06.20-s027_1
module increment_unsigned_12644(A, CI, Z);
input [15:0] A;
input CI;
output [16:0] Z;
wire [15:0] A;
wire CI;
wire [16:0] Z;
wire n_0, n_2, n_4, n_6, n_8, n_10, n_12, n_14;
wire n_16, n_18, n_20, n_22, n_24, n_26;
assign Z[0] = 1'b0;
assign Z[16] = 1'b0;
xor2pa_bbbbbbbcbd g46(.A (n_26), .B (A[15]), .Y (Z[15]));
addh_bbbcbcbcbbbd g47(.A (n_24), .B (A[14]), .CO (n_26), .S (Z[14]));
addh_bbbcbcbcbbbd g48(.A (n_22), .B (A[13]), .CO (n_24), .S (Z[13]));
addh_bbbcbcbcbbbd g49(.A (n_20), .B (A[12]), .CO (n_22), .S (Z[12]));
addh_bbbcbcbcbbbd g50(.A (n_18), .B (A[11]), .CO (n_20), .S (Z[11]));
addh_bbbcbcbcbbbd g51(.A (n_16), .B (A[10]), .CO (n_18), .S (Z[10]));
addh_bbbcbcbcbbbd g52(.A (n_14), .B (A[9]), .CO (n_16), .S (Z[9]));
addh_bbbcbcbcbbbd g53(.A (n_12), .B (A[8]), .CO (n_14), .S (Z[8]));
addh_bbbcbcbcbbbd g54(.A (n_10), .B (A[7]), .CO (n_12), .S (Z[7]));
addh_bbbcbcbcbbbd g55(.A (n_8), .B (A[6]), .CO (n_10), .S (Z[6]));
addh_bbbcbcbcbbbd g56(.A (n_6), .B (A[5]), .CO (n_8), .S (Z[5]));
addh_bbbcbcbcbbbd g57(.A (n_4), .B (A[4]), .CO (n_6), .S (Z[4]));
addh_bbbcbcbcbbbd g58(.A (n_2), .B (A[3]), .CO (n_4), .S (Z[3]));
addh_bbbcbcbcbbbd g59(.A (n_0), .B (A[2]), .CO (n_2), .S (Z[2]));
addh_bbbcbcbcbbbd g60(.A (A[1]), .B (A[0]), .CO (n_0), .S (Z[1]));
endmodule
module rfid_reader_rx(reset, clk, tag_backscatter, rx_done, rx_timeout,
miller, trext, divide_ratio, rtcal_counts, trcal_counts,
tari_counts, rx_data, rx_dataidx);
input reset, clk, tag_backscatter, trext, divide_ratio;
input [2:0] miller;
input [15:0] rtcal_counts, trcal_counts, tari_counts;
output rx_done, rx_timeout;
output [1023:0] rx_data;
output [9:0] rx_dataidx;
wire reset, clk, tag_backscatter, trext, divide_ratio;
wire [2:0] miller;
wire [15:0] rtcal_counts, trcal_counts, tari_counts;
wire rx_done, rx_timeout;
wire [1023:0] rx_data;
wire [9:0] rx_dataidx;
wire UNCONNECTED, UNCONNECTED0, \count[0] , \count[1] , \count[2] ,
\count[3] , \count[4] , \count[5] ;
wire \count[6] , \count[7] , \count[8] , \count[9] , \count[10] ,
\count[11] , \count[12] , \count[13] ;
wire \count[14] , \count[15] , edgeclk, n_2, n_3, n_4, n_5, n_6;
wire n_7, n_8, n_9, n_10, n_11, n_12, n_13, n_14;
wire n_15, n_16, n_17, n_18, n_19, n_20, n_21, n_22;
wire n_23, n_24, n_25, n_26, n_27, n_28, n_29, n_30;
wire n_31, n_33, n_34, n_36, n_37, n_38, n_39, n_40;
wire n_41, n_42, n_43, n_44, n_45, n_46, n_47, n_48;
wire n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_57;
wire n_58, n_59, n_60, n_61, n_62, n_63, n_64, n_65;
wire n_67, n_68, n_69, n_70, n_71, n_72, n_73, n_74;
wire n_75, n_76, n_77, n_78, n_80, n_81, n_82, n_83;
wire n_84, n_85, n_86, n_87, n_88, n_89, n_90, n_91;
wire n_92, n_93, n_94, n_95, n_96, n_97, n_98, n_100;
wire n_102, n_103, n_104, n_105, n_106, n_107, n_108, n_109;
wire n_110, n_111, n_112, n_113, n_114, n_115, n_116, n_117;
wire n_118, n_119, n_120, n_121, n_122, n_123, n_124, n_125;
wire n_126, n_127, n_128, n_129, n_130, n_131, n_132, n_133;
wire n_134, n_135, n_136, n_137, n_138, n_139, n_140, n_141;
wire n_142, n_143, n_144, n_145, n_146, n_148, n_149, n_150;
wire n_151, n_152, n_154, n_155, n_156, n_157, n_158, n_159;
wire n_160, n_161, n_162, n_164, n_165, n_166, n_167, n_168;
wire n_169, n_170, n_171, n_172, n_173, n_174, n_175, n_176;
wire n_177, n_178, n_179, n_180, n_181, n_182, n_183, n_184;
wire n_185, n_186, n_187, n_188, n_189, n_190, n_191, n_192;
wire n_193, n_194, n_195, n_196, n_197, n_198, n_199, n_200;
wire n_201, n_202, n_203, n_204, n_205, n_207, n_208, n_209;
wire n_210, n_211, n_212, n_213, n_214, n_215, n_216, n_217;
wire n_218, n_219, n_220, n_221, n_222, n_223, n_224, n_225;
wire n_226, n_227, n_228, n_229, n_230, n_231, n_232, n_233;
wire n_234, n_235, n_236, n_237, n_238, n_239, n_240, n_241;
wire n_242, n_243, n_244, n_245, n_246, n_247, n_248, n_249;
wire n_250, n_251, n_252, n_253, n_254, n_255, n_256, n_257;
wire n_258, n_259, n_260, n_261, n_262, n_263, n_264, n_265;
wire n_266, n_267, n_268, n_269, n_270, n_271, n_272, n_274;
wire n_276, n_277, n_278, n_279, n_280, n_281, n_282, n_283;
wire n_284, n_285, n_286, n_287, n_288, n_289, n_290, n_292;
wire n_293, n_294, n_295, n_296, n_297, n_298, n_299, n_300;
wire n_301, n_302, n_303, n_304, n_305, n_306, n_307, n_308;
wire n_309, n_310, n_311, n_312, n_313, n_314, n_315, n_316;
wire n_317, n_318, n_319, n_321, n_322, n_323, n_324, n_325;
wire n_326, n_327, n_328, n_329, n_330, n_331, n_332, n_333;
wire n_334, n_335, previousbit, \rx_counter[0] , \rx_counter[1] ,
\rx_counter[2] , \rx_counter[3] , \rx_counter[4] ;
wire \rx_counter[5] , \rx_counter[6] , \rx_counter[7] ,
\rx_counter[8] , \rx_counter[9] , \rx_counter[10] ,
\rx_counter[11] , \rx_counter[12] ;
wire \rx_counter[13] , \rx_counter[14] , \rx_counter[15] ,
\rx_period[0] , \rx_period[1] , \rx_period[2] , \rx_period[3] ,
\rx_period[4] ;
wire \rx_period[5] , \rx_period[6] , \rx_period[7] , \rx_period[8] ,
\rx_period[9] , \rx_period[10] , \rx_period[11] , \rx_period[12]
;
wire \rx_period[13] , \rx_period[14] , \rx_state[0] , \rx_state[1] ,
\rx_state[2] ;
assign rx_data[16] = 1'b0;
assign rx_data[17] = 1'b0;
assign rx_data[18] = 1'b0;
assign rx_data[19] = 1'b0;
assign rx_data[20] = 1'b0;
assign rx_data[21] = 1'b0;
assign rx_data[22] = 1'b0;
assign rx_data[23] = 1'b0;
assign rx_data[24] = 1'b0;
assign rx_data[25] = 1'b0;
assign rx_data[26] = 1'b0;
assign rx_data[27] = 1'b0;
assign rx_data[28] = 1'b0;
assign rx_data[29] = 1'b0;
assign rx_data[30] = 1'b0;
assign rx_data[31] = 1'b0;
assign rx_data[32] = 1'b0;
assign rx_data[33] = 1'b0;
assign rx_data[34] = 1'b0;
assign rx_data[35] = 1'b0;
assign rx_data[36] = 1'b0;
assign rx_data[37] = 1'b0;
assign rx_data[38] = 1'b0;
assign rx_data[39] = 1'b0;
assign rx_data[40] = 1'b0;
assign rx_data[41] = 1'b0;
assign rx_data[42] = 1'b0;
assign rx_data[43] = 1'b0;
assign rx_data[44] = 1'b0;
assign rx_data[45] = 1'b0;
assign rx_data[46] = 1'b0;
assign rx_data[47] = 1'b0;
assign rx_data[48] = 1'b0;
assign rx_data[49] = 1'b0;
assign rx_data[50] = 1'b0;
assign rx_data[51] = 1'b0;
assign rx_data[52] = 1'b0;
assign rx_data[53] = 1'b0;
assign rx_data[54] = 1'b0;
assign rx_data[55] = 1'b0;
assign rx_data[56] = 1'b0;
assign rx_data[57] = 1'b0;
assign rx_data[58] = 1'b0;
assign rx_data[59] = 1'b0;
assign rx_data[60] = 1'b0;
assign rx_data[61] = 1'b0;
assign rx_data[62] = 1'b0;
assign rx_data[63] = 1'b0;
assign rx_data[64] = 1'b0;
assign rx_data[65] = 1'b0;
assign rx_data[66] = 1'b0;
assign rx_data[67] = 1'b0;
assign rx_data[68] = 1'b0;
assign rx_data[69] = 1'b0;
assign rx_data[70] = 1'b0;
assign rx_data[71] = 1'b0;
assign rx_data[72] = 1'b0;
assign rx_data[73] = 1'b0;
assign rx_data[74] = 1'b0;
assign rx_data[75] = 1'b0;
assign rx_data[76] = 1'b0;
assign rx_data[77] = 1'b0;
assign rx_data[78] = 1'b0;
assign rx_data[79] = 1'b0;
assign rx_data[80] = 1'b0;
assign rx_data[81] = 1'b0;
assign rx_data[82] = 1'b0;
assign rx_data[83] = 1'b0;
assign rx_data[84] = 1'b0;
assign rx_data[85] = 1'b0;
assign rx_data[86] = 1'b0;
assign rx_data[87] = 1'b0;
assign rx_data[88] = 1'b0;
assign rx_data[89] = 1'b0;
assign rx_data[90] = 1'b0;
assign rx_data[91] = 1'b0;
assign rx_data[92] = 1'b0;
assign rx_data[93] = 1'b0;
assign rx_data[94] = 1'b0;
assign rx_data[95] = 1'b0;
assign rx_data[96] = 1'b0;
assign rx_data[97] = 1'b0;
assign rx_data[98] = 1'b0;
assign rx_data[99] = 1'b0;
assign rx_data[100] = 1'b0;
assign rx_data[101] = 1'b0;
assign rx_data[102] = 1'b0;
assign rx_data[103] = 1'b0;
assign rx_data[104] = 1'b0;
assign rx_data[105] = 1'b0;
assign rx_data[106] = 1'b0;
assign rx_data[107] = 1'b0;
assign rx_data[108] = 1'b0;
assign rx_data[109] = 1'b0;
assign rx_data[110] = 1'b0;
assign rx_data[111] = 1'b0;
assign rx_data[112] = 1'b0;
assign rx_data[113] = 1'b0;
assign rx_data[114] = 1'b0;
assign rx_data[115] = 1'b0;
assign rx_data[116] = 1'b0;
assign rx_data[117] = 1'b0;
assign rx_data[118] = 1'b0;
assign rx_data[119] = 1'b0;
assign rx_data[120] = 1'b0;
assign rx_data[121] = 1'b0;
assign rx_data[122] = 1'b0;
assign rx_data[123] = 1'b0;
assign rx_data[124] = 1'b0;
assign rx_data[125] = 1'b0;
assign rx_data[126] = 1'b0;
assign rx_data[127] = 1'b0;
assign rx_data[128] = 1'b0;
assign rx_data[129] = 1'b0;
assign rx_data[130] = 1'b0;
assign rx_data[131] = 1'b0;
assign rx_data[132] = 1'b0;
assign rx_data[133] = 1'b0;
assign rx_data[134] = 1'b0;
assign rx_data[135] = 1'b0;
assign rx_data[136] = 1'b0;
assign rx_data[137] = 1'b0;
assign rx_data[138] = 1'b0;
assign rx_data[139] = 1'b0;
assign rx_data[140] = 1'b0;
assign rx_data[141] = 1'b0;
assign rx_data[142] = 1'b0;
assign rx_data[143] = 1'b0;
assign rx_data[144] = 1'b0;
assign rx_data[145] = 1'b0;
assign rx_data[146] = 1'b0;
assign rx_data[147] = 1'b0;
assign rx_data[148] = 1'b0;
assign rx_data[149] = 1'b0;
assign rx_data[150] = 1'b0;
assign rx_data[151] = 1'b0;
assign rx_data[152] = 1'b0;
assign rx_data[153] = 1'b0;
assign rx_data[154] = 1'b0;
assign rx_data[155] = 1'b0;
assign rx_data[156] = 1'b0;
assign rx_data[157] = 1'b0;
assign rx_data[158] = 1'b0;
assign rx_data[159] = 1'b0;
assign rx_data[160] = 1'b0;
assign rx_data[161] = 1'b0;
assign rx_data[162] = 1'b0;
assign rx_data[163] = 1'b0;
assign rx_data[164] = 1'b0;
assign rx_data[165] = 1'b0;
assign rx_data[166] = 1'b0;
assign rx_data[167] = 1'b0;
assign rx_data[168] = 1'b0;
assign rx_data[169] = 1'b0;
assign rx_data[170] = 1'b0;
assign rx_data[171] = 1'b0;
assign rx_data[172] = 1'b0;
assign rx_data[173] = 1'b0;
assign rx_data[174] = 1'b0;
assign rx_data[175] = 1'b0;
assign rx_data[176] = 1'b0;
assign rx_data[177] = 1'b0;
assign rx_data[178] = 1'b0;
assign rx_data[179] = 1'b0;
assign rx_data[180] = 1'b0;
assign rx_data[181] = 1'b0;
assign rx_data[182] = 1'b0;
assign rx_data[183] = 1'b0;
assign rx_data[184] = 1'b0;
assign rx_data[185] = 1'b0;
assign rx_data[186] = 1'b0;
assign rx_data[187] = 1'b0;
assign rx_data[188] = 1'b0;
assign rx_data[189] = 1'b0;
assign rx_data[190] = 1'b0;
assign rx_data[191] = 1'b0;
assign rx_data[192] = 1'b0;
assign rx_data[193] = 1'b0;
assign rx_data[194] = 1'b0;
assign rx_data[195] = 1'b0;
assign rx_data[196] = 1'b0;
assign rx_data[197] = 1'b0;
assign rx_data[198] = 1'b0;
assign rx_data[199] = 1'b0;
assign rx_data[200] = 1'b0;
assign rx_data[201] = 1'b0;
assign rx_data[202] = 1'b0;
assign rx_data[203] = 1'b0;
assign rx_data[204] = 1'b0;
assign rx_data[205] = 1'b0;
assign rx_data[206] = 1'b0;
assign rx_data[207] = 1'b0;
assign rx_data[208] = 1'b0;
assign rx_data[209] = 1'b0;
assign rx_data[210] = 1'b0;
assign rx_data[211] = 1'b0;
assign rx_data[212] = 1'b0;
assign rx_data[213] = 1'b0;
assign rx_data[214] = 1'b0;
assign rx_data[215] = 1'b0;
assign rx_data[216] = 1'b0;
assign rx_data[217] = 1'b0;
assign rx_data[218] = 1'b0;
assign rx_data[219] = 1'b0;
assign rx_data[220] = 1'b0;
assign rx_data[221] = 1'b0;
assign rx_data[222] = 1'b0;
assign rx_data[223] = 1'b0;
assign rx_data[224] = 1'b0;
assign rx_data[225] = 1'b0;
assign rx_data[226] = 1'b0;
assign rx_data[227] = 1'b0;
assign rx_data[228] = 1'b0;
assign rx_data[229] = 1'b0;
assign rx_data[230] = 1'b0;
assign rx_data[231] = 1'b0;
assign rx_data[232] = 1'b0;
assign rx_data[233] = 1'b0;
assign rx_data[234] = 1'b0;
assign rx_data[235] = 1'b0;
assign rx_data[236] = 1'b0;
assign rx_data[237] = 1'b0;
assign rx_data[238] = 1'b0;
assign rx_data[239] = 1'b0;
assign rx_data[240] = 1'b0;
assign rx_data[241] = 1'b0;
assign rx_data[242] = 1'b0;
assign rx_data[243] = 1'b0;
assign rx_data[244] = 1'b0;
assign rx_data[245] = 1'b0;
assign rx_data[246] = 1'b0;
assign rx_data[247] = 1'b0;
assign rx_data[248] = 1'b0;
assign rx_data[249] = 1'b0;
assign rx_data[250] = 1'b0;
assign rx_data[251] = 1'b0;
assign rx_data[252] = 1'b0;
assign rx_data[253] = 1'b0;
assign rx_data[254] = 1'b0;
assign rx_data[255] = 1'b0;
assign rx_data[256] = 1'b0;
assign rx_data[257] = 1'b0;
assign rx_data[258] = 1'b0;
assign rx_data[259] = 1'b0;
assign rx_data[260] = 1'b0;
assign rx_data[261] = 1'b0;
assign rx_data[262] = 1'b0;
assign rx_data[263] = 1'b0;
assign rx_data[264] = 1'b0;
assign rx_data[265] = 1'b0;
assign rx_data[266] = 1'b0;
assign rx_data[267] = 1'b0;
assign rx_data[268] = 1'b0;
assign rx_data[269] = 1'b0;
assign rx_data[270] = 1'b0;
assign rx_data[271] = 1'b0;
assign rx_data[272] = 1'b0;
assign rx_data[273] = 1'b0;
assign rx_data[274] = 1'b0;
assign rx_data[275] = 1'b0;
assign rx_data[276] = 1'b0;
assign rx_data[277] = 1'b0;
assign rx_data[278] = 1'b0;
assign rx_data[279] = 1'b0;
assign rx_data[280] = 1'b0;
assign rx_data[281] = 1'b0;
assign rx_data[282] = 1'b0;
assign rx_data[283] = 1'b0;
assign rx_data[284] = 1'b0;
assign rx_data[285] = 1'b0;
assign rx_data[286] = 1'b0;
assign rx_data[287] = 1'b0;
assign rx_data[288] = 1'b0;
assign rx_data[289] = 1'b0;
assign rx_data[290] = 1'b0;
assign rx_data[291] = 1'b0;
assign rx_data[292] = 1'b0;
assign rx_data[293] = 1'b0;
assign rx_data[294] = 1'b0;
assign rx_data[295] = 1'b0;
assign rx_data[296] = 1'b0;
assign rx_data[297] = 1'b0;
assign rx_data[298] = 1'b0;
assign rx_data[299] = 1'b0;
assign rx_data[300] = 1'b0;
assign rx_data[301] = 1'b0;
assign rx_data[302] = 1'b0;
assign rx_data[303] = 1'b0;
assign rx_data[304] = 1'b0;
assign rx_data[305] = 1'b0;
assign rx_data[306] = 1'b0;
assign rx_data[307] = 1'b0;
assign rx_data[308] = 1'b0;
assign rx_data[309] = 1'b0;
assign rx_data[310] = 1'b0;
assign rx_data[311] = 1'b0;
assign rx_data[312] = 1'b0;
assign rx_data[313] = 1'b0;
assign rx_data[314] = 1'b0;
assign rx_data[315] = 1'b0;
assign rx_data[316] = 1'b0;
assign rx_data[317] = 1'b0;
assign rx_data[318] = 1'b0;
assign rx_data[319] = 1'b0;
assign rx_data[320] = 1'b0;
assign rx_data[321] = 1'b0;
assign rx_data[322] = 1'b0;
assign rx_data[323] = 1'b0;
assign rx_data[324] = 1'b0;
assign rx_data[325] = 1'b0;
assign rx_data[326] = 1'b0;
assign rx_data[327] = 1'b0;
assign rx_data[328] = 1'b0;
assign rx_data[329] = 1'b0;
assign rx_data[330] = 1'b0;
assign rx_data[331] = 1'b0;
assign rx_data[332] = 1'b0;
assign rx_data[333] = 1'b0;
assign rx_data[334] = 1'b0;
assign rx_data[335] = 1'b0;
assign rx_data[336] = 1'b0;
assign rx_data[337] = 1'b0;
assign rx_data[338] = 1'b0;
assign rx_data[339] = 1'b0;
assign rx_data[340] = 1'b0;
assign rx_data[341] = 1'b0;
assign rx_data[342] = 1'b0;
assign rx_data[343] = 1'b0;
assign rx_data[344] = 1'b0;
assign rx_data[345] = 1'b0;
assign rx_data[346] = 1'b0;
assign rx_data[347] = 1'b0;
assign rx_data[348] = 1'b0;
assign rx_data[349] = 1'b0;
assign rx_data[350] = 1'b0;
assign rx_data[351] = 1'b0;
assign rx_data[352] = 1'b0;
assign rx_data[353] = 1'b0;
assign rx_data[354] = 1'b0;
assign rx_data[355] = 1'b0;
assign rx_data[356] = 1'b0;
assign rx_data[357] = 1'b0;
assign rx_data[358] = 1'b0;
assign rx_data[359] = 1'b0;
assign rx_data[360] = 1'b0;
assign rx_data[361] = 1'b0;
assign rx_data[362] = 1'b0;
assign rx_data[363] = 1'b0;
assign rx_data[364] = 1'b0;
assign rx_data[365] = 1'b0;
assign rx_data[366] = 1'b0;
assign rx_data[367] = 1'b0;
assign rx_data[368] = 1'b0;
assign rx_data[369] = 1'b0;
assign rx_data[370] = 1'b0;
assign rx_data[371] = 1'b0;
assign rx_data[372] = 1'b0;
assign rx_data[373] = 1'b0;
assign rx_data[374] = 1'b0;
assign rx_data[375] = 1'b0;
assign rx_data[376] = 1'b0;
assign rx_data[377] = 1'b0;
assign rx_data[378] = 1'b0;
assign rx_data[379] = 1'b0;
assign rx_data[380] = 1'b0;
assign rx_data[381] = 1'b0;
assign rx_data[382] = 1'b0;
assign rx_data[383] = 1'b0;
assign rx_data[384] = 1'b0;
assign rx_data[385] = 1'b0;
assign rx_data[386] = 1'b0;
assign rx_data[387] = 1'b0;
assign rx_data[388] = 1'b0;
assign rx_data[389] = 1'b0;
assign rx_data[390] = 1'b0;
assign rx_data[391] = 1'b0;
assign rx_data[392] = 1'b0;
assign rx_data[393] = 1'b0;
assign rx_data[394] = 1'b0;
assign rx_data[395] = 1'b0;
assign rx_data[396] = 1'b0;
assign rx_data[397] = 1'b0;
assign rx_data[398] = 1'b0;
assign rx_data[399] = 1'b0;
assign rx_data[400] = 1'b0;
assign rx_data[401] = 1'b0;
assign rx_data[402] = 1'b0;
assign rx_data[403] = 1'b0;
assign rx_data[404] = 1'b0;
assign rx_data[405] = 1'b0;
assign rx_data[406] = 1'b0;
assign rx_data[407] = 1'b0;
assign rx_data[408] = 1'b0;
assign rx_data[409] = 1'b0;
assign rx_data[410] = 1'b0;
assign rx_data[411] = 1'b0;
assign rx_data[412] = 1'b0;
assign rx_data[413] = 1'b0;
assign rx_data[414] = 1'b0;
assign rx_data[415] = 1'b0;
assign rx_data[416] = 1'b0;
assign rx_data[417] = 1'b0;
assign rx_data[418] = 1'b0;
assign rx_data[419] = 1'b0;
assign rx_data[420] = 1'b0;
assign rx_data[421] = 1'b0;
assign rx_data[422] = 1'b0;
assign rx_data[423] = 1'b0;
assign rx_data[424] = 1'b0;
assign rx_data[425] = 1'b0;
assign rx_data[426] = 1'b0;
assign rx_data[427] = 1'b0;
assign rx_data[428] = 1'b0;
assign rx_data[429] = 1'b0;
assign rx_data[430] = 1'b0;
assign rx_data[431] = 1'b0;
assign rx_data[432] = 1'b0;
assign rx_data[433] = 1'b0;
assign rx_data[434] = 1'b0;
assign rx_data[435] = 1'b0;
assign rx_data[436] = 1'b0;
assign rx_data[437] = 1'b0;
assign rx_data[438] = 1'b0;
assign rx_data[439] = 1'b0;
assign rx_data[440] = 1'b0;
assign rx_data[441] = 1'b0;
assign rx_data[442] = 1'b0;
assign rx_data[443] = 1'b0;
assign rx_data[444] = 1'b0;
assign rx_data[445] = 1'b0;
assign rx_data[446] = 1'b0;
assign rx_data[447] = 1'b0;
assign rx_data[448] = 1'b0;
assign rx_data[449] = 1'b0;
assign rx_data[450] = 1'b0;
assign rx_data[451] = 1'b0;
assign rx_data[452] = 1'b0;
assign rx_data[453] = 1'b0;
assign rx_data[454] = 1'b0;
assign rx_data[455] = 1'b0;
assign rx_data[456] = 1'b0;
assign rx_data[457] = 1'b0;
assign rx_data[458] = 1'b0;
assign rx_data[459] = 1'b0;
assign rx_data[460] = 1'b0;
assign rx_data[461] = 1'b0;
assign rx_data[462] = 1'b0;
assign rx_data[463] = 1'b0;
assign rx_data[464] = 1'b0;
assign rx_data[465] = 1'b0;
assign rx_data[466] = 1'b0;
assign rx_data[467] = 1'b0;
assign rx_data[468] = 1'b0;
assign rx_data[469] = 1'b0;
assign rx_data[470] = 1'b0;
assign rx_data[471] = 1'b0;
assign rx_data[472] = 1'b0;
assign rx_data[473] = 1'b0;
assign rx_data[474] = 1'b0;
assign rx_data[475] = 1'b0;
assign rx_data[476] = 1'b0;
assign rx_data[477] = 1'b0;
assign rx_data[478] = 1'b0;
assign rx_data[479] = 1'b0;
assign rx_data[480] = 1'b0;
assign rx_data[481] = 1'b0;
assign rx_data[482] = 1'b0;
assign rx_data[483] = 1'b0;
assign rx_data[484] = 1'b0;
assign rx_data[485] = 1'b0;
assign rx_data[486] = 1'b0;
assign rx_data[487] = 1'b0;
assign rx_data[488] = 1'b0;
assign rx_data[489] = 1'b0;
assign rx_data[490] = 1'b0;
assign rx_data[491] = 1'b0;
assign rx_data[492] = 1'b0;
assign rx_data[493] = 1'b0;
assign rx_data[494] = 1'b0;
assign rx_data[495] = 1'b0;
assign rx_data[496] = 1'b0;
assign rx_data[497] = 1'b0;
assign rx_data[498] = 1'b0;
assign rx_data[499] = 1'b0;
assign rx_data[500] = 1'b0;
assign rx_data[501] = 1'b0;
assign rx_data[502] = 1'b0;
assign rx_data[503] = 1'b0;
assign rx_data[504] = 1'b0;
assign rx_data[505] = 1'b0;
assign rx_data[506] = 1'b0;
assign rx_data[507] = 1'b0;
assign rx_data[508] = 1'b0;
assign rx_data[509] = 1'b0;
assign rx_data[510] = 1'b0;
assign rx_data[511] = 1'b0;
assign rx_data[512] = 1'b0;
assign rx_data[513] = 1'b0;
assign rx_data[514] = 1'b0;
assign rx_data[515] = 1'b0;
assign rx_data[516] = 1'b0;
assign rx_data[517] = 1'b0;
assign rx_data[518] = 1'b0;
assign rx_data[519] = 1'b0;
assign rx_data[520] = 1'b0;
assign rx_data[521] = 1'b0;
assign rx_data[522] = 1'b0;
assign rx_data[523] = 1'b0;
assign rx_data[524] = 1'b0;
assign rx_data[525] = 1'b0;
assign rx_data[526] = 1'b0;
assign rx_data[527] = 1'b0;
assign rx_data[528] = 1'b0;
assign rx_data[529] = 1'b0;
assign rx_data[530] = 1'b0;
assign rx_data[531] = 1'b0;
assign rx_data[532] = 1'b0;
assign rx_data[533] = 1'b0;
assign rx_data[534] = 1'b0;
assign rx_data[535] = 1'b0;
assign rx_data[536] = 1'b0;
assign rx_data[537] = 1'b0;
assign rx_data[538] = 1'b0;
assign rx_data[539] = 1'b0;
assign rx_data[540] = 1'b0;
assign rx_data[541] = 1'b0;
assign rx_data[542] = 1'b0;
assign rx_data[543] = 1'b0;
assign rx_data[544] = 1'b0;
assign rx_data[545] = 1'b0;
assign rx_data[546] = 1'b0;
assign rx_data[547] = 1'b0;
assign rx_data[548] = 1'b0;
assign rx_data[549] = 1'b0;
assign rx_data[550] = 1'b0;
assign rx_data[551] = 1'b0;
assign rx_data[552] = 1'b0;
assign rx_data[553] = 1'b0;
assign rx_data[554] = 1'b0;
assign rx_data[555] = 1'b0;
assign rx_data[556] = 1'b0;
assign rx_data[557] = 1'b0;
assign rx_data[558] = 1'b0;
assign rx_data[559] = 1'b0;
assign rx_data[560] = 1'b0;
assign rx_data[561] = 1'b0;
assign rx_data[562] = 1'b0;
assign rx_data[563] = 1'b0;
assign rx_data[564] = 1'b0;
assign rx_data[565] = 1'b0;
assign rx_data[566] = 1'b0;
assign rx_data[567] = 1'b0;
assign rx_data[568] = 1'b0;
assign rx_data[569] = 1'b0;
assign rx_data[570] = 1'b0;
assign rx_data[571] = 1'b0;
assign rx_data[572] = 1'b0;
assign rx_data[573] = 1'b0;
assign rx_data[574] = 1'b0;
assign rx_data[575] = 1'b0;
assign rx_data[576] = 1'b0;
assign rx_data[577] = 1'b0;
assign rx_data[578] = 1'b0;
assign rx_data[579] = 1'b0;
assign rx_data[580] = 1'b0;
assign rx_data[581] = 1'b0;
assign rx_data[582] = 1'b0;
assign rx_data[583] = 1'b0;
assign rx_data[584] = 1'b0;
assign rx_data[585] = 1'b0;
assign rx_data[586] = 1'b0;
assign rx_data[587] = 1'b0;
assign rx_data[588] = 1'b0;
assign rx_data[589] = 1'b0;
assign rx_data[590] = 1'b0;
assign rx_data[591] = 1'b0;
assign rx_data[592] = 1'b0;
assign rx_data[593] = 1'b0;
assign rx_data[594] = 1'b0;
assign rx_data[595] = 1'b0;
assign rx_data[596] = 1'b0;
assign rx_data[597] = 1'b0;
assign rx_data[598] = 1'b0;
assign rx_data[599] = 1'b0;
assign rx_data[600] = 1'b0;
assign rx_data[601] = 1'b0;
assign rx_data[602] = 1'b0;
assign rx_data[603] = 1'b0;
assign rx_data[604] = 1'b0;
assign rx_data[605] = 1'b0;
assign rx_data[606] = 1'b0;
assign rx_data[607] = 1'b0;
assign rx_data[608] = 1'b0;
assign rx_data[609] = 1'b0;
assign rx_data[610] = 1'b0;
assign rx_data[611] = 1'b0;
assign rx_data[612] = 1'b0;
assign rx_data[613] = 1'b0;
assign rx_data[614] = 1'b0;
assign rx_data[615] = 1'b0;
assign rx_data[616] = 1'b0;
assign rx_data[617] = 1'b0;
assign rx_data[618] = 1'b0;
assign rx_data[619] = 1'b0;
assign rx_data[620] = 1'b0;
assign rx_data[621] = 1'b0;
assign rx_data[622] = 1'b0;
assign rx_data[623] = 1'b0;
assign rx_data[624] = 1'b0;
assign rx_data[625] = 1'b0;
assign rx_data[626] = 1'b0;
assign rx_data[627] = 1'b0;
assign rx_data[628] = 1'b0;
assign rx_data[629] = 1'b0;
assign rx_data[630] = 1'b0;
assign rx_data[631] = 1'b0;
assign rx_data[632] = 1'b0;
assign rx_data[633] = 1'b0;
assign rx_data[634] = 1'b0;
assign rx_data[635] = 1'b0;
assign rx_data[636] = 1'b0;
assign rx_data[637] = 1'b0;
assign rx_data[638] = 1'b0;
assign rx_data[639] = 1'b0;
assign rx_data[640] = 1'b0;
assign rx_data[641] = 1'b0;
assign rx_data[642] = 1'b0;
assign rx_data[643] = 1'b0;
assign rx_data[644] = 1'b0;
assign rx_data[645] = 1'b0;
assign rx_data[646] = 1'b0;
assign rx_data[647] = 1'b0;
assign rx_data[648] = 1'b0;
assign rx_data[649] = 1'b0;
assign rx_data[650] = 1'b0;
assign rx_data[651] = 1'b0;
assign rx_data[652] = 1'b0;
assign rx_data[653] = 1'b0;
assign rx_data[654] = 1'b0;
assign rx_data[655] = 1'b0;
assign rx_data[656] = 1'b0;
assign rx_data[657] = 1'b0;
assign rx_data[658] = 1'b0;
assign rx_data[659] = 1'b0;
assign rx_data[660] = 1'b0;
assign rx_data[661] = 1'b0;
assign rx_data[662] = 1'b0;
assign rx_data[663] = 1'b0;
assign rx_data[664] = 1'b0;
assign rx_data[665] = 1'b0;
assign rx_data[666] = 1'b0;
assign rx_data[667] = 1'b0;
assign rx_data[668] = 1'b0;
assign rx_data[669] = 1'b0;
assign rx_data[670] = 1'b0;
assign rx_data[671] = 1'b0;
assign rx_data[672] = 1'b0;
assign rx_data[673] = 1'b0;
assign rx_data[674] = 1'b0;
assign rx_data[675] = 1'b0;
assign rx_data[676] = 1'b0;
assign rx_data[677] = 1'b0;
assign rx_data[678] = 1'b0;
assign rx_data[679] = 1'b0;
assign rx_data[680] = 1'b0;
assign rx_data[681] = 1'b0;
assign rx_data[682] = 1'b0;
assign rx_data[683] = 1'b0;
assign rx_data[684] = 1'b0;
assign rx_data[685] = 1'b0;
assign rx_data[686] = 1'b0;
assign rx_data[687] = 1'b0;
assign rx_data[688] = 1'b0;
assign rx_data[689] = 1'b0;
assign rx_data[690] = 1'b0;
assign rx_data[691] = 1'b0;
assign rx_data[692] = 1'b0;
assign rx_data[693] = 1'b0;
assign rx_data[694] = 1'b0;
assign rx_data[695] = 1'b0;
assign rx_data[696] = 1'b0;
assign rx_data[697] = 1'b0;
assign rx_data[698] = 1'b0;
assign rx_data[699] = 1'b0;
assign rx_data[700] = 1'b0;
assign rx_data[701] = 1'b0;
assign rx_data[702] = 1'b0;
assign rx_data[703] = 1'b0;
assign rx_data[704] = 1'b0;
assign rx_data[705] = 1'b0;
assign rx_data[706] = 1'b0;
assign rx_data[707] = 1'b0;
assign rx_data[708] = 1'b0;
assign rx_data[709] = 1'b0;
assign rx_data[710] = 1'b0;
assign rx_data[711] = 1'b0;
assign rx_data[712] = 1'b0;
assign rx_data[713] = 1'b0;
assign rx_data[714] = 1'b0;
assign rx_data[715] = 1'b0;
assign rx_data[716] = 1'b0;
assign rx_data[717] = 1'b0;
assign rx_data[718] = 1'b0;
assign rx_data[719] = 1'b0;
assign rx_data[720] = 1'b0;
assign rx_data[721] = 1'b0;
assign rx_data[722] = 1'b0;
assign rx_data[723] = 1'b0;
assign rx_data[724] = 1'b0;
assign rx_data[725] = 1'b0;
assign rx_data[726] = 1'b0;
assign rx_data[727] = 1'b0;
assign rx_data[728] = 1'b0;
assign rx_data[729] = 1'b0;
assign rx_data[730] = 1'b0;
assign rx_data[731] = 1'b0;
assign rx_data[732] = 1'b0;
assign rx_data[733] = 1'b0;
assign rx_data[734] = 1'b0;
assign rx_data[735] = 1'b0;
assign rx_data[736] = 1'b0;
assign rx_data[737] = 1'b0;
assign rx_data[738] = 1'b0;
assign rx_data[739] = 1'b0;
assign rx_data[740] = 1'b0;
assign rx_data[741] = 1'b0;
assign rx_data[742] = 1'b0;
assign rx_data[743] = 1'b0;
assign rx_data[744] = 1'b0;
assign rx_data[745] = 1'b0;
assign rx_data[746] = 1'b0;
assign rx_data[747] = 1'b0;
assign rx_data[748] = 1'b0;
assign rx_data[749] = 1'b0;
assign rx_data[750] = 1'b0;
assign rx_data[751] = 1'b0;
assign rx_data[752] = 1'b0;
assign rx_data[753] = 1'b0;
assign rx_data[754] = 1'b0;
assign rx_data[755] = 1'b0;
assign rx_data[756] = 1'b0;
assign rx_data[757] = 1'b0;
assign rx_data[758] = 1'b0;
assign rx_data[759] = 1'b0;
assign rx_data[760] = 1'b0;
assign rx_data[761] = 1'b0;
assign rx_data[762] = 1'b0;
assign rx_data[763] = 1'b0;
assign rx_data[764] = 1'b0;
assign rx_data[765] = 1'b0;
assign rx_data[766] = 1'b0;
assign rx_data[767] = 1'b0;
assign rx_data[768] = 1'b0;
assign rx_data[769] = 1'b0;
assign rx_data[770] = 1'b0;
assign rx_data[771] = 1'b0;
assign rx_data[772] = 1'b0;
assign rx_data[773] = 1'b0;
assign rx_data[774] = 1'b0;
assign rx_data[775] = 1'b0;
assign rx_data[776] = 1'b0;
assign rx_data[777] = 1'b0;
assign rx_data[778] = 1'b0;
assign rx_data[779] = 1'b0;
assign rx_data[780] = 1'b0;
assign rx_data[781] = 1'b0;
assign rx_data[782] = 1'b0;
assign rx_data[783] = 1'b0;
assign rx_data[784] = 1'b0;
assign rx_data[785] = 1'b0;
assign rx_data[786] = 1'b0;
assign rx_data[787] = 1'b0;
assign rx_data[788] = 1'b0;
assign rx_data[789] = 1'b0;
assign rx_data[790] = 1'b0;
assign rx_data[791] = 1'b0;
assign rx_data[792] = 1'b0;
assign rx_data[793] = 1'b0;
assign rx_data[794] = 1'b0;
assign rx_data[795] = 1'b0;
assign rx_data[796] = 1'b0;
assign rx_data[797] = 1'b0;
assign rx_data[798] = 1'b0;
assign rx_data[799] = 1'b0;
assign rx_data[800] = 1'b0;
assign rx_data[801] = 1'b0;
assign rx_data[802] = 1'b0;
assign rx_data[803] = 1'b0;
assign rx_data[804] = 1'b0;
assign rx_data[805] = 1'b0;
assign rx_data[806] = 1'b0;
assign rx_data[807] = 1'b0;
assign rx_data[808] = 1'b0;
assign rx_data[809] = 1'b0;
assign rx_data[810] = 1'b0;
assign rx_data[811] = 1'b0;
assign rx_data[812] = 1'b0;
assign rx_data[813] = 1'b0;
assign rx_data[814] = 1'b0;
assign rx_data[815] = 1'b0;
assign rx_data[816] = 1'b0;
assign rx_data[817] = 1'b0;
assign rx_data[818] = 1'b0;
assign rx_data[819] = 1'b0;
assign rx_data[820] = 1'b0;
assign rx_data[821] = 1'b0;
assign rx_data[822] = 1'b0;
assign rx_data[823] = 1'b0;
assign rx_data[824] = 1'b0;
assign rx_data[825] = 1'b0;
assign rx_data[826] = 1'b0;
assign rx_data[827] = 1'b0;
assign rx_data[828] = 1'b0;
assign rx_data[829] = 1'b0;
assign rx_data[830] = 1'b0;
assign rx_data[831] = 1'b0;
assign rx_data[832] = 1'b0;
assign rx_data[833] = 1'b0;
assign rx_data[834] = 1'b0;
assign rx_data[835] = 1'b0;
assign rx_data[836] = 1'b0;
assign rx_data[837] = 1'b0;
assign rx_data[838] = 1'b0;
assign rx_data[839] = 1'b0;
assign rx_data[840] = 1'b0;
assign rx_data[841] = 1'b0;
assign rx_data[842] = 1'b0;
assign rx_data[843] = 1'b0;
assign rx_data[844] = 1'b0;
assign rx_data[845] = 1'b0;
assign rx_data[846] = 1'b0;
assign rx_data[847] = 1'b0;
assign rx_data[848] = 1'b0;
assign rx_data[849] = 1'b0;
assign rx_data[850] = 1'b0;
assign rx_data[851] = 1'b0;
assign rx_data[852] = 1'b0;
assign rx_data[853] = 1'b0;
assign rx_data[854] = 1'b0;
assign rx_data[855] = 1'b0;
assign rx_data[856] = 1'b0;
assign rx_data[857] = 1'b0;
assign rx_data[858] = 1'b0;
assign rx_data[859] = 1'b0;
assign rx_data[860] = 1'b0;
assign rx_data[861] = 1'b0;
assign rx_data[862] = 1'b0;
assign rx_data[863] = 1'b0;
assign rx_data[864] = 1'b0;
assign rx_data[865] = 1'b0;
assign rx_data[866] = 1'b0;
assign rx_data[867] = 1'b0;
assign rx_data[868] = 1'b0;
assign rx_data[869] = 1'b0;
assign rx_data[870] = 1'b0;
assign rx_data[871] = 1'b0;
assign rx_data[872] = 1'b0;
assign rx_data[873] = 1'b0;
assign rx_data[874] = 1'b0;
assign rx_data[875] = 1'b0;
assign rx_data[876] = 1'b0;
assign rx_data[877] = 1'b0;
assign rx_data[878] = 1'b0;
assign rx_data[879] = 1'b0;
assign rx_data[880] = 1'b0;
assign rx_data[881] = 1'b0;
assign rx_data[882] = 1'b0;
assign rx_data[883] = 1'b0;
assign rx_data[884] = 1'b0;
assign rx_data[885] = 1'b0;
assign rx_data[886] = 1'b0;
assign rx_data[887] = 1'b0;
assign rx_data[888] = 1'b0;
assign rx_data[889] = 1'b0;
assign rx_data[890] = 1'b0;
assign rx_data[891] = 1'b0;
assign rx_data[892] = 1'b0;
assign rx_data[893] = 1'b0;
assign rx_data[894] = 1'b0;
assign rx_data[895] = 1'b0;
assign rx_data[896] = 1'b0;
assign rx_data[897] = 1'b0;
assign rx_data[898] = 1'b0;
assign rx_data[899] = 1'b0;
assign rx_data[900] = 1'b0;
assign rx_data[901] = 1'b0;
assign rx_data[902] = 1'b0;
assign rx_data[903] = 1'b0;
assign rx_data[904] = 1'b0;
assign rx_data[905] = 1'b0;
assign rx_data[906] = 1'b0;
assign rx_data[907] = 1'b0;
assign rx_data[908] = 1'b0;
assign rx_data[909] = 1'b0;
assign rx_data[910] = 1'b0;
assign rx_data[911] = 1'b0;
assign rx_data[912] = 1'b0;
assign rx_data[913] = 1'b0;
assign rx_data[914] = 1'b0;
assign rx_data[915] = 1'b0;
assign rx_data[916] = 1'b0;
assign rx_data[917] = 1'b0;
assign rx_data[918] = 1'b0;
assign rx_data[919] = 1'b0;
assign rx_data[920] = 1'b0;
assign rx_data[921] = 1'b0;
assign rx_data[922] = 1'b0;
assign rx_data[923] = 1'b0;
assign rx_data[924] = 1'b0;
assign rx_data[925] = 1'b0;
assign rx_data[926] = 1'b0;
assign rx_data[927] = 1'b0;
assign rx_data[928] = 1'b0;
assign rx_data[929] = 1'b0;
assign rx_data[930] = 1'b0;
assign rx_data[931] = 1'b0;
assign rx_data[932] = 1'b0;
assign rx_data[933] = 1'b0;
assign rx_data[934] = 1'b0;
assign rx_data[935] = 1'b0;
assign rx_data[936] = 1'b0;
assign rx_data[937] = 1'b0;
assign rx_data[938] = 1'b0;
assign rx_data[939] = 1'b0;
assign rx_data[940] = 1'b0;
assign rx_data[941] = 1'b0;
assign rx_data[942] = 1'b0;
assign rx_data[943] = 1'b0;
assign rx_data[944] = 1'b0;
assign rx_data[945] = 1'b0;
assign rx_data[946] = 1'b0;
assign rx_data[947] = 1'b0;
assign rx_data[948] = 1'b0;
assign rx_data[949] = 1'b0;
assign rx_data[950] = 1'b0;
assign rx_data[951] = 1'b0;
assign rx_data[952] = 1'b0;
assign rx_data[953] = 1'b0;
assign rx_data[954] = 1'b0;
assign rx_data[955] = 1'b0;
assign rx_data[956] = 1'b0;
assign rx_data[957] = 1'b0;
assign rx_data[958] = 1'b0;
assign rx_data[959] = 1'b0;
assign rx_data[960] = 1'b0;
assign rx_data[961] = 1'b0;
assign rx_data[962] = 1'b0;
assign rx_data[963] = 1'b0;
assign rx_data[964] = 1'b0;
assign rx_data[965] = 1'b0;
assign rx_data[966] = 1'b0;
assign rx_data[967] = 1'b0;
assign rx_data[968] = 1'b0;
assign rx_data[969] = 1'b0;
assign rx_data[970] = 1'b0;
assign rx_data[971] = 1'b0;
assign rx_data[972] = 1'b0;
assign rx_data[973] = 1'b0;
assign rx_data[974] = 1'b0;
assign rx_data[975] = 1'b0;
assign rx_data[976] = 1'b0;
assign rx_data[977] = 1'b0;
assign rx_data[978] = 1'b0;
assign rx_data[979] = 1'b0;
assign rx_data[980] = 1'b0;
assign rx_data[981] = 1'b0;
assign rx_data[982] = 1'b0;
assign rx_data[983] = 1'b0;
assign rx_data[984] = 1'b0;
assign rx_data[985] = 1'b0;
assign rx_data[986] = 1'b0;
assign rx_data[987] = 1'b0;
assign rx_data[988] = 1'b0;
assign rx_data[989] = 1'b0;
assign rx_data[990] = 1'b0;
assign rx_data[991] = 1'b0;
assign rx_data[992] = 1'b0;
assign rx_data[993] = 1'b0;
assign rx_data[994] = 1'b0;
assign rx_data[995] = 1'b0;
assign rx_data[996] = 1'b0;
assign rx_data[997] = 1'b0;
assign rx_data[998] = 1'b0;
assign rx_data[999] = 1'b0;
assign rx_data[1000] = 1'b0;
assign rx_data[1001] = 1'b0;
assign rx_data[1002] = 1'b0;
assign rx_data[1003] = 1'b0;
assign rx_data[1004] = 1'b0;
assign rx_data[1005] = 1'b0;
assign rx_data[1006] = 1'b0;
assign rx_data[1007] = 1'b0;
assign rx_data[1008] = 1'b0;
assign rx_data[1009] = 1'b0;
assign rx_data[1010] = 1'b0;
assign rx_data[1011] = 1'b0;
assign rx_data[1012] = 1'b0;
assign rx_data[1013] = 1'b0;
assign rx_data[1014] = 1'b0;
assign rx_data[1015] = 1'b0;
assign rx_data[1016] = 1'b0;
assign rx_data[1017] = 1'b0;
assign rx_data[1018] = 1'b0;
assign rx_data[1019] = 1'b0;
assign rx_data[1020] = 1'b0;
assign rx_data[1021] = 1'b0;
assign rx_data[1022] = 1'b0;
assign rx_data[1023] = 1'b0;
increment_unsigned_12644 inc_add_59_27(.A ({\count[15] , \count[14] ,
\count[13] , \count[12] , \count[11] , \count[10] , \count[9] ,
\count[8] , \count[7] , \count[6] , \count[5] , \count[4] ,
\count[3] , \count[2] , \count[1] , \count[0] }), .CI (1'b1), .Z
({UNCONNECTED, n_321, n_322, n_323, n_324, n_325, n_326, n_327,
n_328, n_329, n_330, n_331, n_332, n_333, n_334, n_335,
UNCONNECTED0}));
nand4_dc g27025(.in0 (n_315), .in1 (n_308), .in2 (n_309), .in3
(n_311), .out0 (rx_timeout));
oai2bb1_bbbc g27026(.A0N (n_319), .A1N (n_314), .B0 (\rx_counter[9]
), .Y (n_315));
nor3_be g27027(.in0 (n_313), .in1 (\rx_counter[5] ), .in2
(\rx_counter[4] ), .out0 (n_314));
oai21_bdbc g27028(.in0 (n_312), .in1 (n_317), .in2 (n_310), .out0
(n_313));
oai21_bdbc g27029(.in0 (\rx_counter[1] ), .in1 (\rx_counter[0] ),
.in2 (\rx_counter[3] ), .out0 (n_312));
nor2_bd g27032(.in0 (\rx_counter[13] ), .in1 (\rx_counter[12] ),
.out0 (n_311));
nor2_bd g27030(.in0 (\rx_counter[7] ), .in1 (\rx_counter[6] ), .out0
(n_310));
nor2_bd g27033(.in0 (\rx_counter[15] ), .in1 (\rx_counter[14] ),
.out0 (n_309));
nor2_bd g27031(.in0 (\rx_counter[11] ), .in1 (\rx_counter[10] ),
.out0 (n_308));
inv1x_bc g27037(.in0 (\rx_counter[1] ), .out0 (n_316));
inv1x_bc g27035(.in0 (\rx_counter[2] ), .out0 (n_317));
inv1x_bc g27036(.in0 (\rx_counter[8] ), .out0 (n_319));
inv1x_bc g27038(.in0 (\rx_counter[3] ), .out0 (n_318));
ffrhq_x2 \rx_state_reg[0] (.RN (n_306), .CK (edgeclk), .D (n_307), .Q
(\rx_state[0] ));
oai2bb1_bbbc g27829(.A0N (\rx_state[0] ), .A1N (n_304), .B0 (n_305),
.Y (n_307));
ffrhq_x2 \rx_state_reg[1] (.RN (n_306), .CK (edgeclk), .D (n_303), .Q
(\rx_state[1] ));
nand4b_bbdc g27831(.AN (n_304), .B (n_269), .C (n_280), .D (n_302),
.Y (n_305));
ffrhq_x2 \rx_data_reg[12] (.RN (n_306), .CK (edgeclk), .D (n_290), .Q
(rx_data[12]));
ffrhq_x2 \rx_data_reg[13] (.RN (n_306), .CK (edgeclk), .D (n_288), .Q
(rx_data[13]));
ffrhq_x2 \rx_data_reg[14] (.RN (n_306), .CK (edgeclk), .D (n_287), .Q
(rx_data[14]));
ffrhq_x2 \rx_data_reg[15] (.RN (n_306), .CK (edgeclk), .D (n_296), .Q
(rx_data[15]));
ffrhq_x2 \rx_data_reg[1] (.RN (n_306), .CK (edgeclk), .D (n_294), .Q
(rx_data[1]));
ffrhq_x2 \rx_data_reg[2] (.RN (n_306), .CK (edgeclk), .D (n_293), .Q
(rx_data[2]));
ffrhq_x2 \rx_data_reg[3] (.RN (n_306), .CK (edgeclk), .D (n_292), .Q
(rx_data[3]));
ffrhq_x2 \rx_data_reg[4] (.RN (n_306), .CK (edgeclk), .D (n_301), .Q
(rx_data[4]));
ffrhq_x2 \rx_data_reg[5] (.RN (n_306), .CK (edgeclk), .D (n_300), .Q
(rx_data[5]));
ffrhq_x2 \rx_data_reg[6] (.RN (n_306), .CK (edgeclk), .D (n_299), .Q
(rx_data[6]));
ffrhq_x2 \rx_data_reg[0] (.RN (n_306), .CK (edgeclk), .D (n_298), .Q
(rx_data[0]));
ffrhq_x2 \rx_data_reg[11] (.RN (n_306), .CK (edgeclk), .D (n_297), .Q
(rx_data[11]));
ffrhq_x2 \rx_data_reg[10] (.RN (n_306), .CK (edgeclk), .D (n_285), .Q
(rx_data[10]));
ffrhq_x2 \rx_data_reg[7] (.RN (n_306), .CK (edgeclk), .D (n_281), .Q
(rx_data[7]));
ffrhq_x2 \rx_data_reg[8] (.RN (n_306), .CK (edgeclk), .D (n_283), .Q
(rx_data[8]));
ffrhq_x2 \rx_data_reg[9] (.RN (n_306), .CK (edgeclk), .D (n_282), .Q
(rx_data[9]));
oai2bb1_bbbc g27848(.A0N (n_302), .A1N (n_112), .B0 (n_289), .Y
(n_303));
inv1x_bc g27857(.in0 (n_276), .out0 (n_301));
inv1x_bc g27859(.in0 (n_274), .out0 (n_300));
inv1x_bc g27861(.in0 (n_286), .out0 (n_299));
oai2bb2_bbbdbc g27867(.A0N (rx_data[0]), .A1N (n_219), .B0 (n_295),
.B1 (n_218), .Y (n_298));
oai2bb2_bbbdbc g27868(.A0N (rx_data[11]), .A1N (n_203), .B0 (n_295),
.B1 (n_202), .Y (n_297));
oai2bb2_bbbdbc g27869(.A0N (rx_data[15]), .A1N (n_173), .B0 (n_295),
.B1 (n_172), .Y (n_296));
oai2bb2_bbbdbc g27870(.A0N (rx_data[1]), .A1N (n_230), .B0 (n_295),
.B1 (n_228), .Y (n_294));
oai2bb2_bbbdbc g27871(.A0N (rx_data[2]), .A1N (n_226), .B0 (n_295),
.B1 (n_225), .Y (n_293));
oai2bb2_bbbdbc g27872(.A0N (rx_data[3]), .A1N (n_205), .B0 (n_295),
.B1 (n_204), .Y (n_292));
inv1x_bc g27851(.in0 (n_279), .out0 (n_290));
inv1x_bc g27849(.in0 (n_289), .out0 (n_304));
inv1x_bc g27853(.in0 (n_278), .out0 (n_288));
inv1x_bc g27855(.in0 (n_277), .out0 (n_287));
aoi22_bdbd g27862(.in0 (n_284), .in1 (n_207), .in2 (n_208), .in3
(rx_data[6]), .out0 (n_286));
oai2bb1_bbbc g27863(.A0N (n_200), .A1N (n_284), .B0 (n_234), .Y
(n_285));
oai2bb1_bbbc g27864(.A0N (n_198), .A1N (n_284), .B0 (n_231), .Y
(n_283));
oai2bb1_bbbc g27865(.A0N (n_216), .A1N (n_284), .B0 (n_244), .Y
(n_282));
oai2bb1_bbbc g27866(.A0N (n_196), .A1N (n_284), .B0 (n_232), .Y
(n_281));
nand4_dc g27850(.in0 (n_272), .in1 (n_242), .in2 (n_280), .in3
(n_29), .out0 (n_289));
aoi22_bdbd g27852(.in0 (n_284), .in1 (n_213), .in2 (n_214), .in3
(rx_data[12]), .out0 (n_279));
aoi22_bdbd g27854(.in0 (n_284), .in1 (n_223), .in2 (n_224), .in3
(rx_data[13]), .out0 (n_278));
aoi22_bdbd g27856(.in0 (n_284), .in1 (n_211), .in2 (n_212), .in3
(rx_data[14]), .out0 (n_277));
aoi22_bdbd g27858(.in0 (n_284), .in1 (n_209), .in2 (n_210), .in3
(rx_data[4]), .out0 (n_276));
aoi22_bdbd g27860(.in0 (n_284), .in1 (n_221), .in2 (n_222), .in3
(rx_data[5]), .out0 (n_274));
ffrhq_x2 \rx_state_reg[2] (.RN (n_306), .CK (edgeclk), .D (n_271), .Q
(\rx_state[2] ));
inv1x_bc g27877(.in0 (n_295), .out0 (n_284));
inv1x_bc g27879(.in0 (n_271), .out0 (n_272));
nand3_cc g27878(.in0 (n_270), .in1 (n_227), .in2 (n_229), .out0
(n_295));
nor2_bd g27880(.in0 (n_270), .in1 (n_269), .out0 (n_271));
nor3b_bbbe g27881(.AN (n_268), .B (n_171), .C (n_20), .Y (n_270));
aoi22_bdbd g27882(.in0 (n_90), .in1 (n_48), .in2 (n_267), .in3
(n_62), .out0 (n_268));
ffrhq_x2 \rx_dataidx_reg[1] (.RN (n_306), .CK (edgeclk), .D (n_264),
.Q (rx_dataidx[1]));
ffrhq_x2 \rx_dataidx_reg[4] (.RN (n_306), .CK (edgeclk), .D (n_265),
.Q (rx_dataidx[4]));
ffrhq_x2 \rx_dataidx_reg[6] (.RN (n_306), .CK (edgeclk), .D (n_266),
.Q (rx_dataidx[6]));
ffrhq_x2 \rx_dataidx_reg[0] (.RN (n_306), .CK (edgeclk), .D (n_263),
.Q (rx_dataidx[0]));
nor3_be g27883(.in0 (n_262), .in1 (n_64), .in2 (n_30), .out0 (n_267));
inv1x_bc g27894(.in0 (n_261), .out0 (n_266));
oai2bb1_bbbc g27897(.A0N (rx_dataidx[4]), .A1N (n_251), .B0 (n_258),
.Y (n_265));
ffrhq_x2 \rx_dataidx_reg[2] (.RN (n_306), .CK (edgeclk), .D (n_257),
.Q (rx_dataidx[2]));
ffrhq_x2 \rx_dataidx_reg[3] (.RN (n_306), .CK (edgeclk), .D (n_256),
.Q (rx_dataidx[3]));
ffrhq_x2 \rx_dataidx_reg[9] (.RN (n_306), .CK (edgeclk), .D (n_252),
.Q (rx_dataidx[9]));
ffrhq_x2 \rx_dataidx_reg[7] (.RN (n_306), .CK (edgeclk), .D (n_254),
.Q (rx_dataidx[7]));
ffrhq_x2 \rx_dataidx_reg[8] (.RN (n_306), .CK (edgeclk), .D (n_253),
.Q (rx_dataidx[8]));
ffrhq_x2 \rx_dataidx_reg[5] (.RN (n_306), .CK (edgeclk), .D (n_255),
.Q (rx_dataidx[5]));
nand2_bc g27904(.in0 (n_260), .in1 (n_235), .out0 (n_264));
oai2bb2_bbbdbc g27905(.A0N (rx_dataidx[0]), .A1N (n_241), .B0
(n_245), .B1 (rx_dataidx[0]), .Y (n_263));
oai22_bdbd g27903(.in0 (n_319), .in1 (\rx_period[8] ), .in2 (n_249),
.in3 (n_47), .out0 (n_262));
aoi22_bdbd g27895(.in0 (n_248), .in1 (rx_dataidx[6]), .in2 (n_259),
.in3 (n_135), .out0 (n_261));
nand3b_bbcc g27914(.AN (rx_dataidx[1]), .B (n_259), .C
(rx_dataidx[0]), .Y (n_260));
nand3b_bbcc g27915(.AN (rx_dataidx[4]), .B (n_259), .C (n_250), .Y
(n_258));
oai2bb2_bbbdbc g27896(.A0N (n_11), .A1N (n_259), .B0 (n_237), .B1
(n_93), .Y (n_257));
oai2bb2_bbbdbc g27898(.A0N (n_71), .A1N (n_259), .B0 (n_236), .B1
(n_6), .Y (n_256));
oai2bb2_bbbdbc g27899(.A0N (n_92), .A1N (n_259), .B0 (n_243), .B1
(n_91), .Y (n_255));
oai2bb2_bbbdbc g27900(.A0N (n_169), .A1N (n_259), .B0 (n_240), .B1
(n_14), .Y (n_254));
oai2bb2_bbbdbc g27901(.A0N (n_195), .A1N (n_259), .B0 (n_239), .B1
(n_12), .Y (n_253));
oai2bb2_bbbdbc g27902(.A0N (n_167), .A1N (n_259), .B0 (n_238), .B1
(n_13), .Y (n_252));
oai21_bdbc g27912(.in0 (n_247), .in1 (n_250), .in2 (n_246), .out0
(n_251));
aoi21_bdbd g27913(.in0 (n_220), .in1 (n_89), .in2 (n_46), .out0
(n_249));
oai21_bdbc g27917(.in0 (n_247), .in1 (n_136), .in2 (n_246), .out0
(n_248));
inv1x_bc g27922(.in0 (n_259), .out0 (n_245));
oai21_bdbc g27906(.in0 (n_217), .in1 (n_233), .in2 (rx_data[9]),
.out0 (n_244));
aoi21_bdbd g27907(.in0 (n_242), .in1 (n_125), .in2 (n_241), .out0
(n_243));
aoi21_bdbd g27908(.in0 (n_242), .in1 (n_168), .in2 (n_241), .out0
(n_240));
aoi21_bdbd g27909(.in0 (n_242), .in1 (n_194), .in2 (n_241), .out0
(n_239));
aoi21_bdbd g27910(.in0 (n_242), .in1 (n_166), .in2 (n_241), .out0
(n_238));
aoi21_bdbd g27911(.in0 (n_242), .in1 (n_96), .in2 (n_241), .out0
(n_237));
aoi21_bdbd g27916(.in0 (n_242), .in1 (n_70), .in2 (n_241), .out0
(n_236));
aoi22_bdbd g27918(.in0 (n_241), .in1 (rx_dataidx[1]), .in2 (n_242),
.in3 (n_97), .out0 (n_235));
nor2_ce g27923(.in0 (n_247), .in1 (n_241), .out0 (n_259));
oai21_bdbc g27919(.in0 (n_201), .in1 (n_233), .in2 (rx_data[10]),
.out0 (n_234));
oai21_bdbc g27920(.in0 (n_197), .in1 (n_233), .in2 (rx_data[7]),
.out0 (n_232));
oai21_bdbc g27921(.in0 (n_199), .in1 (n_233), .in2 (rx_data[8]),
.out0 (n_231));
oai2bb1_bbbc g27926(.A0N (n_229), .A1N (n_228), .B0 (n_227), .Y
(n_230));
oai2bb1_bbbc g27938(.A0N (n_229), .A1N (n_225), .B0 (n_227), .Y
(n_226));
ffhq_x2 \rx_period_reg[9] (.CK (edgeclk), .D (n_181), .Q
(\rx_period[9] ));
ffhq_x2 \rx_period_reg[2] (.CK (edgeclk), .D (n_188), .Q
(\rx_period[2] ));
ffhq_x2 \rx_period_reg[11] (.CK (edgeclk), .D (n_178), .Q
(\rx_period[11] ));
ffhq_x2 \rx_period_reg[10] (.CK (edgeclk), .D (n_179), .Q
(\rx_period[10] ));
ffhq_x2 \rx_period_reg[0] (.CK (edgeclk), .D (n_180), .Q
(\rx_period[0] ));
ffhq_x2 \rx_period_reg[6] (.CK (edgeclk), .D (n_184), .Q
(\rx_period[6] ));
ffhq_x2 \rx_period_reg[13] (.CK (edgeclk), .D (n_191), .Q
(\rx_period[13] ));
ffhq_x2 \rx_period_reg[14] (.CK (edgeclk), .D (n_190), .Q
(\rx_period[14] ));
ffhq_x2 \rx_period_reg[1] (.CK (edgeclk), .D (n_189), .Q
(\rx_period[1] ));
ffhq_x2 \rx_period_reg[12] (.CK (edgeclk), .D (n_192), .Q
(\rx_period[12] ));
ffhq_x2 \rx_period_reg[7] (.CK (edgeclk), .D (n_183), .Q
(\rx_period[7] ));
ffhq_x2 \rx_period_reg[8] (.CK (edgeclk), .D (n_182), .Q
(\rx_period[8] ));
ffhq_x2 \rx_period_reg[4] (.CK (edgeclk), .D (n_186), .Q
(\rx_period[4] ));
ffhq_x2 \rx_period_reg[5] (.CK (edgeclk), .D (n_185), .Q
(\rx_period[5] ));
ffhq_x2 \rx_period_reg[3] (.CK (edgeclk), .D (n_187), .Q
(\rx_period[3] ));
oai21_bdbc g27924(.in0 (n_223), .in1 (n_215), .in2 (n_227), .out0
(n_224));
oai21_bdbc g27925(.in0 (n_221), .in1 (n_215), .in2 (n_227), .out0
(n_222));
inv1x_bc g27928(.in0 (n_242), .out0 (n_247));
nand3_cc g27930(.in0 (n_193), .in1 (n_36), .in2 (n_2), .out0 (n_220));
oai2bb1_bbbc g27937(.A0N (n_229), .A1N (n_218), .B0 (n_227), .Y
(n_219));
nor2_bd g27927(.in0 (n_216), .in1 (n_215), .out0 (n_217));
and2_bbcd g27929(.A (n_174), .B (n_63), .Y (n_242));
oai21_bdbc g27931(.in0 (n_213), .in1 (n_215), .in2 (n_227), .out0
(n_214));
oai21_bdbc g27932(.in0 (n_211), .in1 (n_269), .in2 (n_227), .out0
(n_212));
oai21_bdbc g27933(.in0 (n_209), .in1 (n_269), .in2 (n_227), .out0
(n_210));
oai21_bdbc g27934(.in0 (n_207), .in1 (n_215), .in2 (n_129), .out0
(n_208));
oai2bb1_bbbc g27935(.A0N (n_229), .A1N (n_204), .B0 (n_227), .Y
(n_205));
oai2bb1_bbbc g27936(.A0N (n_229), .A1N (n_202), .B0 (n_227), .Y
(n_203));
nor2_bd g27939(.in0 (n_200), .in1 (n_215), .out0 (n_201));
nand2_bc g27941(.in0 (n_143), .in1 (n_170), .out0 (n_228));
nor2_bd g27943(.in0 (n_198), .in1 (n_215), .out0 (n_199));
nor2_bd g27945(.in0 (n_196), .in1 (n_215), .out0 (n_197));
nor2_bd g27956(.in0 (n_194), .in1 (rx_dataidx[8]), .out0 (n_195));
oai21_bdbc g27961(.in0 (n_124), .in1 (n_26), .in2 (n_74), .out0
(n_193));
inv1x_bc g28013(.in0 (n_162), .out0 (n_192));
inv1x_bc g28015(.in0 (n_160), .out0 (n_191));
inv1x_bc g28017(.in0 (n_145), .out0 (n_190));
inv1x_bc g28019(.in0 (n_165), .out0 (n_189));
inv1x_bc g28021(.in0 (n_144), .out0 (n_188));
inv1x_bc g28023(.in0 (n_158), .out0 (n_187));
inv1x_bc g28025(.in0 (n_177), .out0 (n_186));
inv1x_bc g28027(.in0 (n_176), .out0 (n_185));
inv1x_bc g28029(.in0 (n_157), .out0 (n_184));
inv1x_bc g28031(.in0 (n_156), .out0 (n_183));
inv1x_bc g28033(.in0 (n_154), .out0 (n_182));
inv1x_bc g28035(.in0 (n_152), .out0 (n_181));
inv1x_bc g28037(.in0 (n_150), .out0 (n_180));
inv1x_bc g28039(.in0 (n_149), .out0 (n_179));
inv1x_bc g28041(.in0 (n_148), .out0 (n_178));
inv1x_bc g28059(.in0 (n_241), .out0 (n_246));
ffrhq_x2 previousbit_reg(.RN (n_306), .CK (clk), .D (n_131), .Q
(previousbit));
ffrhq_x2 \rx_counter_reg[13] (.RN (n_306), .CK (clk), .D (n_130), .Q
(\rx_counter[13] ));
ffrhq_x2 \rx_counter_reg[2] (.RN (n_306), .CK (clk), .D (n_118), .Q
(\rx_counter[2] ));
aoi22_bdbd g28026(.in0 (n_161), .in1 (\rx_period[4] ), .in2 (n_155),
.in3 (\rx_counter[5] ), .out0 (n_177));
aoi22_bdbd g28028(.in0 (n_164), .in1 (\rx_period[5] ), .in2 (n_69),
.in3 (\rx_counter[6] ), .out0 (n_176));
ffrhq_x2 \rx_counter_reg[6] (.RN (n_306), .CK (clk), .D (n_114), .Q
(\rx_counter[6] ));
nor2_bd g27940(.in0 (n_175), .in1 (n_139), .out0 (n_223));
nor2_bd g27942(.in0 (n_175), .in1 (n_141), .out0 (n_221));
nor2_bd g27944(.in0 (n_175), .in1 (n_142), .out0 (n_216));
ffrhq_x2 \rx_counter_reg[15] (.RN (n_306), .CK (clk), .D (n_120), .Q
(\rx_counter[15] ));
oai21_bdbc g27946(.in0 (n_95), .in1 (rx_dataidx[3]), .in2 (n_146),
.out0 (n_174));
oai2bb1_bbbc g27947(.A0N (n_229), .A1N (n_172), .B0 (n_227), .Y
(n_173));
nor2_bd g27948(.in0 (n_126), .in1 (n_61), .out0 (n_171));
nand2_bc g27951(.in0 (n_127), .in1 (n_170), .out0 (n_225));
nand2_bc g27955(.in0 (n_128), .in1 (n_170), .out0 (n_218));
nor2_bd g27982(.in0 (n_168), .in1 (rx_dataidx[7]), .out0 (n_169));
nor2_bd g27983(.in0 (n_166), .in1 (rx_dataidx[9]), .out0 (n_167));
aoi22_bdbd g28020(.in0 (n_164), .in1 (\rx_period[1] ), .in2 (n_69),
.in3 (\rx_counter[2] ), .out0 (n_165));
aoi22_bdbd g28014(.in0 (n_161), .in1 (\rx_period[12] ), .in2 (n_159),
.in3 (\rx_counter[13] ), .out0 (n_162));
aoi22_bdbd g28016(.in0 (n_100), .in1 (\rx_period[13] ), .in2 (n_159),
.in3 (\rx_counter[14] ), .out0 (n_160));
aoi22_bdbd g28024(.in0 (n_164), .in1 (\rx_period[3] ), .in2 (n_159),
.in3 (\rx_counter[4] ), .out0 (n_158));
aoi22_bdbd g28030(.in0 (n_161), .in1 (\rx_period[6] ), .in2 (n_151),
.in3 (\rx_counter[7] ), .out0 (n_157));
ffrhq_x2 \rx_counter_reg[12] (.RN (n_306), .CK (clk), .D (n_122), .Q
(\rx_counter[12] ));
ffrhq_x2 \rx_counter_reg[4] (.RN (n_306), .CK (clk), .D (n_116), .Q
(\rx_counter[4] ));
ffrhq_x2 \rx_counter_reg[1] (.RN (n_306), .CK (clk), .D (n_119), .Q
(\rx_counter[1] ));
aoi22_bdbd g28032(.in0 (n_161), .in1 (\rx_period[7] ), .in2 (n_155),
.in3 (\rx_counter[8] ), .out0 (n_156));
ffrhq_x2 \rx_counter_reg[3] (.RN (n_306), .CK (clk), .D (n_117), .Q
(\rx_counter[3] ));
ffrhq_x2 \rx_counter_reg[10] (.RN (n_306), .CK (clk), .D (n_123), .Q
(\rx_counter[10] ));
ffrhq_x2 \rx_counter_reg[11] (.RN (n_306), .CK (clk), .D (n_132), .Q
(\rx_counter[11] ));
ffrhq_x2 \rx_counter_reg[8] (.RN (n_306), .CK (clk), .D (n_134), .Q
(\rx_counter[8] ));
ffrhq_x2 \rx_counter_reg[9] (.RN (n_306), .CK (clk), .D (n_133), .Q
(\rx_counter[9] ));
aoi22_bdbd g28034(.in0 (n_100), .in1 (\rx_period[8] ), .in2 (n_155),
.in3 (\rx_counter[9] ), .out0 (n_154));
aoi22_bdbd g28036(.in0 (n_161), .in1 (\rx_period[9] ), .in2 (n_151),
.in3 (\rx_counter[10] ), .out0 (n_152));
aoi22_bdbd g28038(.in0 (n_161), .in1 (\rx_period[0] ), .in2 (n_151),
.in3 (\rx_counter[1] ), .out0 (n_150));
aoi22_bdbd g28040(.in0 (n_161), .in1 (\rx_period[10] ), .in2 (n_155),
.in3 (\rx_counter[11] ), .out0 (n_149));
aoi22_bdbd g28042(.in0 (n_100), .in1 (\rx_period[11] ), .in2 (n_69),
.in3 (\rx_counter[12] ), .out0 (n_148));
nor2b_bbce g28060(.AN (n_112), .B (n_146), .Y (n_241));
aoi22_bdbd g28018(.in0 (n_161), .in1 (\rx_period[14] ), .in2 (n_159),
.in3 (\rx_counter[15] ), .out0 (n_145));
aoi22_bdbd g28022(.in0 (n_164), .in1 (\rx_period[2] ), .in2 (n_151),
.in3 (\rx_counter[3] ), .out0 (n_144));
ffrhq_x2 \rx_counter_reg[5] (.RN (n_306), .CK (clk), .D (n_115), .Q
(\rx_counter[5] ));
ffrhq_x2 \rx_counter_reg[14] (.RN (n_306), .CK (clk), .D (n_121), .Q
(\rx_counter[14] ));
ffrhq_x2 \rx_counter_reg[7] (.RN (n_306), .CK (clk), .D (n_113), .Q
(\rx_counter[7] ));
inv1x_bc g27962(.in0 (n_175), .out0 (n_143));
nor2_bd g27957(.in0 (n_138), .in1 (n_142), .out0 (n_200));
nor2_bd g27953(.in0 (n_140), .in1 (n_141), .out0 (n_209));
nor2b_bbbd g27959(.AN (n_137), .B (n_141), .Y (n_196));
nor2_bd g27949(.in0 (n_140), .in1 (n_139), .out0 (n_213));
nor2_bd g27950(.in0 (n_138), .in1 (n_139), .out0 (n_211));
nand2_bc g27952(.in0 (n_137), .in1 (n_170), .out0 (n_204));
nor2_bd g27954(.in0 (n_138), .in1 (n_141), .out0 (n_207));
nor2_bd g27958(.in0 (n_140), .in1 (n_142), .out0 (n_198));
nand2_bc g27960(.in0 (n_137), .in1 (n_23), .out0 (n_202));
nand3_cc g27987(.in0 (n_136), .in1 (rx_dataidx[7]), .in2
(rx_dataidx[6]), .out0 (n_194));
nor2b_bbbd g28007(.AN (n_136), .B (rx_dataidx[6]), .Y (n_135));
ffrhq_x2 \rx_counter_reg[0] (.RN (n_306), .CK (clk), .D (n_102), .Q
(\rx_counter[0] ));
inv1x_bc g28089(.in0 (n_111), .out0 (n_134));
inv1x_bc g28091(.in0 (n_110), .out0 (n_133));
inv1x_bc g28093(.in0 (n_108), .out0 (n_132));
inv1x_bc g28095(.in0 (n_107), .out0 (n_131));
inv1x_bc g28097(.in0 (n_105), .out0 (n_130));
inv1x_bc g28133(.in0 (n_129), .out0 (n_233));
ffrhq_x2 \count_reg[0] (.RN (n_306), .CK (clk), .D (n_72), .Q
(\count[0] ));
nand3b_bbcc g27963(.AN (rx_dataidx[1]), .B (n_98), .C
(rx_dataidx[0]), .Y (n_175));
inv1x_bc g27980(.in0 (n_140), .out0 (n_128));
inv1x_bc g27984(.in0 (n_138), .out0 (n_127));
aoi21_bdbd g27989(.in0 (n_25), .in1 (n_33), .in2 (n_65), .out0
(n_126));
nand4bb_bbbbdc g28009(.AN (n_125), .BN (n_67), .C (rx_dataidx[7]), .D
(rx_dataidx[8]), .Y (n_166));
nand3_cc g28011(.in0 (n_68), .in1 (rx_dataidx[3]), .in2
(rx_dataidx[4]), .out0 (n_168));
oai21_bdbc g28012(.in0 (n_38), .in1 (n_316), .in2 (n_73), .out0
(n_124));
inv1x_bc g28067(.in0 (n_88), .out0 (n_123));
inv1x_bc g28069(.in0 (n_87), .out0 (n_122));
inv1x_bc g28071(.in0 (n_85), .out0 (n_121));
inv1x_bc g28073(.in0 (n_84), .out0 (n_120));
inv1x_bc g28075(.in0 (n_83), .out0 (n_119));
inv1x_bc g28077(.in0 (n_81), .out0 (n_118));
inv1x_bc g28079(.in0 (n_80), .out0 (n_117));
inv1x_bc g28081(.in0 (n_78), .out0 (n_116));
inv1x_bc g28083(.in0 (n_77), .out0 (n_115));
inv1x_bc g28085(.in0 (n_76), .out0 (n_114));
inv1x_bc g28087(.in0 (n_75), .out0 (n_113));
ffrhq_x2 \count_reg[12] (.RN (n_306), .CK (clk), .D (n_45), .Q
(\count[12] ));
ffrhq_x2 \count_reg[14] (.RN (n_306), .CK (clk), .D (n_51), .Q
(\count[14] ));
ffrhq_x2 \count_reg[5] (.RN (n_306), .CK (clk), .D (n_44), .Q
(\count[5] ));
ffrhq_x2 \count_reg[3] (.RN (n_306), .CK (clk), .D (n_53), .Q
(\count[3] ));
ffrhq_x2 \count_reg[13] (.RN (n_306), .CK (clk), .D (n_55), .Q
(\count[13] ));
ffrhq_x2 \count_reg[8] (.RN (n_306), .CK (clk), .D (n_43), .Q
(\count[8] ));
ffrhq_x2 \count_reg[1] (.RN (n_306), .CK (clk), .D (n_50), .Q
(\count[1] ));
ffrhq_x2 \count_reg[9] (.RN (n_306), .CK (clk), .D (n_42), .Q
(\count[9] ));
ffrhq_x2 \count_reg[6] (.RN (n_306), .CK (clk), .D (n_59), .Q
(\count[6] ));
ffrhq_x2 \count_reg[4] (.RN (n_306), .CK (clk), .D (n_60), .Q
(\count[4] ));
ffrhq_x2 \count_reg[10] (.RN (n_306), .CK (clk), .D (n_58), .Q
(\count[10] ));
ffrhq_x2 \count_reg[11] (.RN (n_306), .CK (clk), .D (n_57), .Q
(\count[11] ));
ffrhq_x2 \count_reg[2] (.RN (n_306), .CK (clk), .D (n_52), .Q
(\count[2] ));
ffrhq_x2 \count_reg[7] (.RN (n_306), .CK (clk), .D (n_49), .Q
(\count[7] ));
inv1x_bc g28128(.in0 (n_100), .out0 (n_159));
inv1x_bc g28134(.in0 (n_112), .out0 (n_129));
inv1x_bc g28135(.in0 (n_112), .out0 (n_227));
aoi22_bdbd g28090(.in0 (n_104), .in1 (\rx_counter[8] ), .in2 (n_328),
.in3 (n_109), .out0 (n_111));
aoi22_bdbd g28092(.in0 (n_28), .in1 (\rx_counter[9] ), .in2 (n_327),
.in3 (n_109), .out0 (n_110));
ffrhq_x2 \count_reg[15] (.RN (n_306), .CK (clk), .D (n_54), .Q
(\count[15] ));
aoi22_bdbd g28094(.in0 (n_106), .in1 (\rx_counter[11] ), .in2
(n_325), .in3 (n_109), .out0 (n_108));
aoi22_bdbd g28096(.in0 (n_103), .in1 (previousbit), .in2 (n_106),
.in3 (tag_backscatter), .out0 (n_107));
aoi22_bdbd g28098(.in0 (n_104), .in1 (\rx_counter[13] ), .in2
(n_323), .in3 (n_103), .out0 (n_105));
oai2bb2_bbbdbc g28099(.A0N (\rx_counter[0] ), .A1N (n_28), .B0
(n_82), .B1 (\count[0] ), .Y (n_102));
inv1x_bc g28124(.in0 (n_100), .out0 (n_151));
inv1x_bc g28127(.in0 (n_100), .out0 (n_155));
nand2_bc g27979(.in0 (n_98), .in1 (n_250), .out0 (n_172));
nand2_bc g27981(.in0 (n_98), .in1 (n_94), .out0 (n_140));
nand2_bc g27985(.in0 (n_98), .in1 (n_97), .out0 (n_138));
nor2b_bbbd g27986(.AN (n_98), .B (n_96), .Y (n_137));
oai21_bdbc g27988(.in0 (n_94), .in1 (n_93), .in2 (n_98), .out0
(n_95));
nor2_bd g28061(.in0 (n_125), .in1 (rx_dataidx[5]), .out0 (n_92));
nor2_bd g28062(.in0 (n_125), .in1 (n_91), .out0 (n_136));
oai22_bdbd g28065(.in0 (\rx_counter[13] ), .in1 (n_5), .in2 (n_41),
.in3 (\rx_counter[12] ), .out0 (n_90));
aoi2bb2_bbbdbd g28066(.A0N (n_37), .A1N (\rx_counter[4] ), .B0 (n_7),
.B1 (\rx_period[5] ), .Y (n_89));
aoi22_bdbd g28068(.in0 (n_86), .in1 (\rx_counter[10] ), .in2 (n_326),
.in3 (n_109), .out0 (n_88));
aoi22_bdbd g28070(.in0 (n_86), .in1 (\rx_counter[12] ), .in2 (n_324),
.in3 (n_103), .out0 (n_87));
aoi22_bdbd g28072(.in0 (n_104), .in1 (\rx_counter[14] ), .in2
(n_322), .in3 (n_103), .out0 (n_85));
aoi22_bdbd g28074(.in0 (n_86), .in1 (\rx_counter[15] ), .in2 (n_321),
.in3 (n_103), .out0 (n_84));
aoi22_bdbd g28076(.in0 (n_82), .in1 (\rx_counter[1] ), .in2 (n_109),
.in3 (n_335), .out0 (n_83));
aoi22_bdbd g28078(.in0 (n_104), .in1 (\rx_counter[2] ), .in2 (n_109),
.in3 (n_334), .out0 (n_81));
aoi22_bdbd g28080(.in0 (n_28), .in1 (\rx_counter[3] ), .in2 (n_109),
.in3 (n_333), .out0 (n_80));
aoi22_bdbd g28082(.in0 (n_86), .in1 (\rx_counter[4] ), .in2 (n_332),
.in3 (n_109), .out0 (n_78));
aoi22_bdbd g28084(.in0 (n_82), .in1 (\rx_counter[5] ), .in2 (n_331),
.in3 (n_109), .out0 (n_77));
aoi22_bdbd g28086(.in0 (n_82), .in1 (\rx_counter[6] ), .in2 (n_330),
.in3 (n_34), .out0 (n_76));
aoi22_bdbd g28088(.in0 (n_106), .in1 (\rx_counter[7] ), .in2 (n_329),
.in3 (n_103), .out0 (n_75));
aoi22_bdbd g28063(.in0 (n_318), .in1 (\rx_period[3] ), .in2 (n_27),
.in3 (\rx_period[2] ), .out0 (n_74));
aoi2bb1_bbbe g28064(.A0N (n_317), .A1N (\rx_period[2] ), .B0 (n_39),
.Y (n_73));
nor2_bd g28104(.in0 (n_106), .in1 (\count[0] ), .out0 (n_72));
nor2_bd g28114(.in0 (n_70), .in1 (rx_dataidx[3]), .out0 (n_71));
inv1x_bc g28122(.in0 (n_69), .out0 (n_161));
inv1x_bc g28125(.in0 (n_69), .out0 (n_100));
nor2_bd g28131(.in0 (n_70), .in1 (n_67), .out0 (n_68));
ffr_x2 edgeclk_reg(.RN (n_306), .CK (clk), .D (n_28), .Q (edgeclk),
.QN ());
aoi21_bdbd g28010(.in0 (n_31), .in1 (n_4), .in2 (n_64), .out0 (n_65));
and2_bbcd g28136(.A (n_269), .B (n_63), .Y (n_112));
inv1x_bc g28137(.in0 (n_61), .out0 (n_62));
inv1x_bc g28126(.in0 (n_69), .out0 (n_164));
and2_bbcd g28112(.A (n_332), .B (n_109), .Y (n_60));
and2_bbcd g28115(.A (n_330), .B (n_109), .Y (n_59));
nor3_be g28008(.in0 (n_15), .in1 (rx_dataidx[4]), .in2
(rx_dataidx[5]), .out0 (n_98));
and2_bbcd g28101(.A (n_326), .B (n_109), .Y (n_58));
and2_bbcd g28102(.A (n_325), .B (n_109), .Y (n_57));
and2_bbcd g28105(.A (n_323), .B (n_109), .Y (n_55));
and2_bbcd g28106(.A (n_321), .B (n_109), .Y (n_54));
and2_bbcd g28107(.A (n_109), .B (n_333), .Y (n_53));
and2_bbcd g28110(.A (n_109), .B (n_334), .Y (n_52));
and2_bbcd g28109(.A (n_322), .B (n_109), .Y (n_51));
and2_bbcd g28111(.A (n_109), .B (n_335), .Y (n_50));
and2_bbcd g28116(.A (n_329), .B (n_109), .Y (n_49));
nand3_cc g28138(.in0 (n_48), .in1 (n_40), .in2 (n_3), .out0 (n_61));
nor2_bd g28140(.in0 (n_17), .in1 (n_21), .out0 (n_47));
oai21_bdbc g28160(.in0 (n_16), .in1 (\rx_period[6] ), .in2 (n_22),
.out0 (n_46));
and2_bbcd g28103(.A (n_324), .B (n_109), .Y (n_45));
and2_bbcd g28113(.A (n_331), .B (n_109), .Y (n_44));
and2_bbcd g28119(.A (n_328), .B (n_109), .Y (n_43));
nand2_bc g28118(.in0 (n_250), .in1 (rx_dataidx[4]), .out0 (n_125));
nor2_bd g28130(.in0 (n_280), .in1 (reset), .out0 (n_69));
and2_bbcd g28117(.A (n_327), .B (n_109), .Y (n_42));
nand2_bc g28147(.in0 (n_40), .in1 (\rx_period[12] ), .out0 (n_41));
inv1x_bc g28154(.in0 (n_229), .out0 (n_215));
inv1x_bc g28165(.in0 (n_34), .out0 (n_104));
aoi21_bdbd g28139(.in0 (n_38), .in1 (n_316), .in2 (\rx_period[1] ),
.out0 (n_39));
nand2_bc g28142(.in0 (n_36), .in1 (\rx_period[4] ), .out0 (n_37));
inv1x_bc g28171(.in0 (n_109), .out0 (n_86));
inv1x_bc g28166(.in0 (n_34), .out0 (n_82));
oai21_bdbc g28159(.in0 (n_24), .in1 (\rx_period[10] ), .in2 (n_33),
.out0 (n_64));
nand2_bc g28146(.in0 (n_10), .in1 (rx_dataidx[2]), .out0 (n_70));
inv1x_bc g28169(.in0 (n_34), .out0 (n_106));
inv1x_bc g28152(.in0 (n_229), .out0 (n_269));
nand3b_bbcc g28141(.AN (n_30), .B (n_319), .C (\rx_period[8] ), .Y
(n_31));
and3_bbbd g28155(.A (n_29), .B (\rx_state[0] ), .C (\rx_state[1] ),
.Y (n_229));
nor2b_bbbd g28149(.AN (n_317), .B (n_26), .Y (n_27));
aoi21_bdbd g28150(.in0 (\rx_counter[14] ), .in1 (n_19), .in2
(\rx_counter[15] ), .out0 (n_48));
nand3b_bbcc g28157(.AN (\rx_state[1] ), .B (n_29), .C (\rx_state[0]
), .Y (n_280));
oai2bb2_bbbdbc g28162(.A0N (\rx_period[10] ), .A1N (n_24), .B0
(\rx_counter[11] ), .B1 (n_8), .Y (n_25));
inv1x_bc g28164(.in0 (n_28), .out0 (n_103));
inv1x_bc g28177(.in0 (n_142), .out0 (n_23));
inv1x_fg g28173(.in0 (n_28), .out0 (n_109));
nor2_bd g28143(.in0 (n_96), .in1 (n_139), .out0 (n_250));
inv1x_bc g28181(.in0 (n_21), .out0 (n_22));
or2_bbcd g28144(.A (n_18), .B (n_29), .Y (n_302));
nor3_be g28156(.in0 (\rx_counter[15] ), .in1 (\rx_counter[14] ), .in2
(n_19), .out0 (n_20));
nand2_bc g28145(.in0 (n_18), .in1 (n_29), .out0 (n_63));
aoi22_bdbd g28161(.in0 (n_16), .in1 (\rx_period[6] ), .in2 (n_9),
.in3 (\rx_period[7] ), .out0 (n_17));
inv1x_bc g28170(.in0 (n_28), .out0 (n_34));
nand4b_bbdc g28108(.AN (rx_dataidx[6]), .B (n_14), .C (n_13), .D
(n_12), .Y (n_15));
nor2_bd g28148(.in0 (n_96), .in1 (rx_dataidx[2]), .out0 (n_11));
inv1x_bc g28179(.in0 (n_96), .out0 (n_10));
nor3b_bbbe g28158(.AN (\rx_state[1] ), .B (\rx_state[2] ), .C
(\rx_state[0] ), .Y (n_146));
xor2pa_bbbbbbbcbd g28174(.A (previousbit), .B (tag_backscatter), .Y
(n_28));
nor2_bd g28182(.in0 (n_9), .in1 (\rx_period[7] ), .out0 (n_21));
nand2_bc g28186(.in0 (\rx_counter[11] ), .in1 (n_8), .out0 (n_33));
or2_bbcd g28193(.A (n_7), .B (\rx_period[5] ), .Y (n_36));
nand2_bc g28175(.in0 (rx_dataidx[2]), .in1 (n_6), .out0 (n_141));
nand2_bc g28185(.in0 (\rx_counter[13] ), .in1 (n_5), .out0 (n_40));
nand2_bc g28178(.in0 (rx_dataidx[3]), .in1 (n_93), .out0 (n_142));
nor2b_bbbd g28191(.AN (rx_dataidx[1]), .B (rx_dataidx[0]), .Y (n_97));
nor2_bd g28176(.in0 (n_318), .in1 (\rx_period[3] ), .out0 (n_26));
nand2b_bbbc g28195(.AN (\rx_counter[9] ), .B (\rx_period[9] ), .Y
(n_4));
nand2b_bbbc g28194(.AN (\rx_period[12] ), .B (\rx_counter[12] ), .Y
(n_3));
nor2b_bbbd g28188(.AN (\rx_counter[9] ), .B (\rx_period[9] ), .Y
(n_30));
nor2_bd g28187(.in0 (rx_dataidx[1]), .in1 (rx_dataidx[0]), .out0
(n_94));
nor2_bd g28190(.in0 (\rx_state[0] ), .in1 (\rx_state[1] ), .out0
(n_18));
nand2b_bbbc g28183(.AN (\rx_period[4] ), .B (\rx_counter[4] ), .Y
(n_2));
nand2_bc g28184(.in0 (rx_dataidx[2]), .in1 (rx_dataidx[3]), .out0
(n_139));
nand2_bc g28192(.in0 (rx_dataidx[5]), .in1 (rx_dataidx[6]), .out0
(n_67));
nand2_bc g28180(.in0 (rx_dataidx[0]), .in1 (rx_dataidx[1]), .out0
(n_96));
nor2_bd g28189(.in0 (rx_dataidx[3]), .in1 (rx_dataidx[2]), .out0
(n_170));
nand2b_bbbc g28196(.AN (\rx_period[0] ), .B (\rx_counter[0] ), .Y
(n_38));
inv1x_bc g28199(.in0 (\rx_counter[10] ), .out0 (n_24));
inv1x_bc g28201(.in0 (\rx_period[11] ), .out0 (n_8));
inv1x_bc g28203(.in0 (rx_dataidx[3]), .out0 (n_6));
inv1x_bc g28207(.in0 (rx_dataidx[9]), .out0 (n_13));
inv1x_bc g28213(.in0 (rx_dataidx[2]), .out0 (n_93));
inv1x_bc g28204(.in0 (rx_dataidx[7]), .out0 (n_14));
inv1x_bc g28211(.in0 (rx_dataidx[8]), .out0 (n_12));
inv1x_bc g28206(.in0 (rx_dataidx[5]), .out0 (n_91));
inv1x_bc g28205(.in0 (\rx_counter[5] ), .out0 (n_7));
inv1x_bc g28200(.in0 (\rx_counter[7] ), .out0 (n_9));
inv1x_bc g28210(.in0 (\rx_period[13] ), .out0 (n_5));
inv1x_bc g28209(.in0 (\rx_state[2] ), .out0 (n_29));
inv1x_bc g28198(.in0 (\rx_period[14] ), .out0 (n_19));
inv1x_bc g28202(.in0 (reset), .out0 (n_306));
inv1x_bc g28197(.in0 (\rx_counter[6] ), .out0 (n_16));
endmodule
module increment_unsigned_12645(A, CI, Z);
input [15:0] A;
input CI;
output [16:0] Z;
wire [15:0] A;
wire CI;
wire [16:0] Z;
wire n_0, n_2, n_4, n_6, n_8, n_10, n_12, n_14;
wire n_16, n_18, n_20, n_22, n_24, n_26;
assign Z[0] = 1'b0;
assign Z[16] = 1'b0;
xor2pa_bbbbbbbcbd g46(.A (A[15]), .B (n_26), .Y (Z[15]));
addh_bbbcbcbcbbbd g47(.A (n_24), .B (A[14]), .CO (n_26), .S (Z[14]));
addh_bbbcbcbcbbbd g48(.A (n_22), .B (A[13]), .CO (n_24), .S (Z[13]));
addh_bbbcbcbcbbbd g49(.A (n_20), .B (A[12]), .CO (n_22), .S (Z[12]));
addh_bbbcbcbcbbbd g50(.A (n_18), .B (A[11]), .CO (n_20), .S (Z[11]));
addh_bbbcbcbcbbbd g51(.A (n_16), .B (A[10]), .CO (n_18), .S (Z[10]));
addh_bbbcbcbcbbbd g52(.A (n_14), .B (A[9]), .CO (n_16), .S (Z[9]));
addh_bbbcbcbcbbbd g53(.A (n_12), .B (A[8]), .CO (n_14), .S (Z[8]));
addh_bbbcbcbcbbbd g54(.A (n_10), .B (A[7]), .CO (n_12), .S (Z[7]));
addh_bbbcbcbcbbbd g55(.A (n_8), .B (A[6]), .CO (n_10), .S (Z[6]));
addh_bbbcbcbcbbbd g56(.A (n_6), .B (A[5]), .CO (n_8), .S (Z[5]));
addh_bbbcbcbcbbbd g57(.A (n_4), .B (A[4]), .CO (n_6), .S (Z[4]));
addh_bbbcbcbcbbbd g58(.A (n_2), .B (A[3]), .CO (n_4), .S (Z[3]));
addh_bbbcbcbcbbbd g59(.A (n_0), .B (A[2]), .CO (n_2), .S (Z[2]));
addh_bbbcbcbcbbbd g60(.A (A[1]), .B (A[0]), .CO (n_0), .S (Z[1]));
endmodule
module rfid_reader_tx(reset, clk, reader_modulation, tx_done,
tx_running, tx_go, send_trcal, delim_counts, pw_counts,
rtcal_counts, trcal_counts, tari_counts, tx_packet_length,
tx_packet_data);
input reset, clk, tx_go, send_trcal;
input [15:0] delim_counts, pw_counts, rtcal_counts, trcal_counts,
tari_counts;
input [6:0] tx_packet_length;
input [127:0] tx_packet_data;
output reader_modulation, tx_done, tx_running;
wire reset, clk, tx_go, send_trcal;
wire [15:0] delim_counts, pw_counts, rtcal_counts, trcal_counts,
tari_counts;
wire [6:0] tx_packet_length;
wire [127:0] tx_packet_data;
wire reader_modulation, tx_done, tx_running;
wire UNCONNECTED1, UNCONNECTED2, \count[0] , \count[1] , \count[2] ,
\count[3] , \count[4] , \count[5] ;
wire \count[6] , \count[7] , \count[8] , \count[9] , \count[10] ,
\count[11] , \count[12] , \count[13] ;
wire \count[14] , \count[15] , \current_tx_bit[0] ,
\current_tx_bit[1] , \current_tx_bit[2] , \current_tx_bit[3] ,
\current_tx_bit[4] , \current_tx_bit[5] ;
wire \current_tx_bit[6] , n_0, n_1, n_2, n_5, n_6, n_7, n_8;
wire n_9, n_10, n_11, n_12, n_13, n_14, n_15, n_16;
wire n_17, n_18, n_19, n_20, n_21, n_22, n_23, n_24;
wire n_26, n_27, n_28, n_29, n_30, n_31, n_32, n_33;
wire n_34, n_35, n_36, n_37, n_38, n_39, n_40, n_41;
wire n_42, n_43, n_44, n_45, n_46, n_47, n_48, n_49;
wire n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57;
wire n_58, n_59, n_60, n_61, n_62, n_63, n_64, n_65;
wire n_66, n_67, n_68, n_69, n_70, n_71, n_72, n_73;
wire n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81;
wire n_82, n_83, n_84, n_85, n_86, n_87, n_88, n_89;
wire n_90, n_91, n_92, n_93, n_94, n_95, n_96, n_97;
wire n_98, n_99, n_100, n_101, n_102, n_103, n_104, n_105;
wire n_106, n_107, n_108, n_109, n_110, n_111, n_112, n_113;
wire n_114, n_115, n_116, n_117, n_118, n_119, n_120, n_121;
wire n_122, n_123, n_124, n_125, n_126, n_127, n_128, n_129;
wire n_130, n_131, n_132, n_133, n_134, n_135, n_136, n_137;
wire n_138, n_139, n_140, n_141, n_142, n_143, n_144, n_145;
wire n_146, n_147, n_148, n_149, n_150, n_151, n_152, n_153;
wire n_154, n_155, n_156, n_157, n_158, n_159, n_160, n_161;
wire n_162, n_163, n_164, n_165, n_166, n_167, n_168, n_169;
wire n_170, n_171, n_172, n_173, n_174, n_175, n_176, n_177;
wire n_178, n_179, n_180, n_181, n_182, n_183, n_184, n_185;
wire n_186, n_187, n_188, n_189, n_190, n_191, n_192, n_193;
wire n_195, n_196, n_197, n_198, n_199, n_200, n_201, n_202;
wire n_203, n_204, n_205, n_206, n_207, n_208, n_209, n_210;
wire n_211, n_212, n_213, n_214, n_215, n_216, n_217, n_218;
wire n_219, n_220, n_221, n_222, n_223, n_224, n_225, n_226;
wire n_227, n_228, n_230, n_231, n_232, n_233, n_234, n_235;
wire n_236, n_237, n_238, n_239, n_240, \tx_state[0] , \tx_state[1] ,
\tx_state[2] ;
increment_unsigned_12645 inc_add_97_29(.A ({\count[15] , \count[14] ,
\count[13] , \count[12] , \count[11] , \count[10] , \count[9] ,
\count[8] , \count[7] , \count[6] , \count[5] , \count[4] ,
\count[3] , \count[2] , \count[1] , \count[0] }), .CI (1'b1), .Z
({UNCONNECTED1, n_225, n_226, n_227, n_228, n_230, n_231, n_232,
n_233, n_234, n_235, n_236, n_237, n_238, n_239, n_240,
UNCONNECTED2}));
ffrhq_x2 modout_reg(.RN (n_223), .CK (clk), .D (n_224), .Q
(reader_modulation));
oai21_bdbc g3776(.in0 (n_217), .in1 (n_198), .in2 (n_218), .out0
(n_224));
ffrhq_x2 \current_tx_bit_reg[0] (.RN (n_223), .CK (clk), .D (n_221),
.Q (\current_tx_bit[0] ));
ffrhq_x2 \current_tx_bit_reg[2] (.RN (n_223), .CK (clk), .D (n_220),
.Q (\current_tx_bit[2] ));
ffrhq_x2 \current_tx_bit_reg[4] (.RN (n_223), .CK (clk), .D (n_222),
.Q (\current_tx_bit[4] ));
ffrhq_x2 \current_tx_bit_reg[1] (.RN (n_223), .CK (clk), .D (n_219),
.Q (\current_tx_bit[1] ));
nand3_cc g3775(.in0 (n_215), .in1 (n_199), .in2 (n_209), .out0
(n_222));
ffrhq_x2 \current_tx_bit_reg[3] (.RN (n_223), .CK (clk), .D (n_210),
.Q (\current_tx_bit[3] ));
ffrhq_x2 \current_tx_bit_reg[5] (.RN (n_223), .CK (clk), .D (n_212),
.Q (\current_tx_bit[5] ));
oai21_bdbc g3796(.in0 (n_211), .in1 (tx_packet_length[0]), .in2
(n_214), .out0 (n_221));
oai2bb1_bbbc g3797(.A0N (\current_tx_bit[2] ), .A1N (n_162), .B0
(n_208), .Y (n_220));
ffrhq_x2 \count_reg[0] (.RN (n_223), .CK (clk), .D (n_204), .Q
(\count[0] ));
ffrhq_x2 \current_tx_bit_reg[6] (.RN (n_223), .CK (clk), .D (n_205),
.Q (\current_tx_bit[6] ));
nand2_bc g3795(.in0 (n_207), .in1 (n_203), .out0 (n_219));
aoi2bb2_bbbdbd g3799(.A0N (n_154), .A1N (tx_go), .B0 (n_216), .B1
(reader_modulation), .Y (n_218));
nand4bb_bbbbdc g3802(.AN (n_216), .BN (n_152), .C (n_157), .D
(n_137), .Y (n_217));
ffrhq_x2 \count_reg[1] (.RN (n_223), .CK (clk), .D (n_187), .Q
(\count[1] ));
ffrhq_x2 \count_reg[5] (.RN (n_223), .CK (clk), .D (n_183), .Q
(\count[5] ));
ffrhq_x2 \count_reg[9] (.RN (n_223), .CK (clk), .D (n_201), .Q
(\count[9] ));
ffrhq_x2 \count_reg[3] (.RN (n_223), .CK (clk), .D (n_185), .Q
(\count[3] ));
ffrhq_x2 \count_reg[12] (.RN (n_223), .CK (clk), .D (n_193), .Q
(\count[12] ));
ffrhq_x2 \count_reg[13] (.RN (n_223), .CK (clk), .D (n_190), .Q
(\count[13] ));
ffrhq_x2 \count_reg[14] (.RN (n_223), .CK (clk), .D (n_189), .Q
(\count[14] ));
ffrhq_x2 \count_reg[2] (.RN (n_223), .CK (clk), .D (n_186), .Q
(\count[2] ));
ffrhq_x2 \count_reg[4] (.RN (n_223), .CK (clk), .D (n_184), .Q
(\count[4] ));
ffrhq_x2 \count_reg[6] (.RN (n_223), .CK (clk), .D (n_182), .Q
(\count[6] ));
ffrhq_x2 \count_reg[7] (.RN (n_223), .CK (clk), .D (n_200), .Q
(\count[7] ));
ffrhq_x2 \count_reg[8] (.RN (n_223), .CK (clk), .D (n_202), .Q
(\count[8] ));
ffrhq_x2 \count_reg[10] (.RN (n_223), .CK (clk), .D (n_192), .Q
(\count[10] ));
ffrhq_x2 \count_reg[11] (.RN (n_223), .CK (clk), .D (n_191), .Q
(\count[11] ));
aoi22_bdbd g3834(.in0 (n_213), .in1 (n_111), .in2 (n_168), .in3
(tx_packet_length[1]), .out0 (n_215));
ffrhq_x2 \count_reg[15] (.RN (n_223), .CK (clk), .D (n_188), .Q
(\count[15] ));
aoi22_bdbd g3838(.in0 (n_206), .in1 (\current_tx_bit[0] ), .in2
(n_213), .in3 (n_11), .out0 (n_214));
oai21_bdbc g3800(.in0 (n_211), .in1 (n_79), .in2 (n_197), .out0
(n_212));
nand2_bc g3801(.in0 (n_195), .in1 (n_209), .out0 (n_210));
aoi22_bdbd g3803(.in0 (n_196), .in1 (n_59), .in2 (n_213), .in3
(n_63), .out0 (n_208));
aoi2bb2_bbbdbd g3836(.A0N (n_211), .A1N (n_22), .B0 (n_206), .B1
(\current_tx_bit[1] ), .Y (n_207));
oai2bb2_bbbdbc g3837(.A0N (\current_tx_bit[6] ), .A1N (n_159), .B0
(n_209), .B1 (tx_packet_data[32]), .Y (n_205));
oai21_bdbc g3798(.in0 (n_179), .in1 (n_180), .in2 (n_169), .out0
(n_204));
oai21_bdbc g3842(.in0 (n_41), .in1 (n_160), .in2 (n_213), .out0
(n_203));
inv1x_bc g3828(.in0 (n_172), .out0 (n_202));
inv1x_bc g3830(.in0 (n_171), .out0 (n_201));
inv1x_bc g3832(.in0 (n_170), .out0 (n_200));
oai21_bdbc g3839(.in0 (n_206), .in1 (n_85), .in2 (\current_tx_bit[4]
), .out0 (n_199));
nor3_be g3840(.in0 (n_158), .in1 (n_151), .in2 (n_198), .out0
(n_216));
aoi22_bdbd g3841(.in0 (n_206), .in1 (\current_tx_bit[5] ), .in2
(n_196), .in3 (n_123), .out0 (n_197));
aoi22_bdbd g3843(.in0 (n_206), .in1 (\current_tx_bit[3] ), .in2
(n_196), .in3 (n_94), .out0 (n_195));
inv1x_bc g3806(.in0 (n_166), .out0 (n_193));
inv1x_bc g3804(.in0 (n_167), .out0 (n_192));
inv1x_bc g3808(.in0 (n_165), .out0 (n_191));
inv1x_bc g3810(.in0 (n_164), .out0 (n_190));
inv1x_bc g3812(.in0 (n_163), .out0 (n_189));
inv1x_bc g3814(.in0 (n_181), .out0 (n_188));
inv1x_bc g3816(.in0 (n_178), .out0 (n_187));
inv1x_bc g3818(.in0 (n_177), .out0 (n_186));
inv1x_bc g3820(.in0 (n_176), .out0 (n_185));
inv1x_bc g3822(.in0 (n_175), .out0 (n_184));
inv1x_bc g3824(.in0 (n_174), .out0 (n_183));
inv1x_bc g3826(.in0 (n_173), .out0 (n_182));
aoi22_bdbd g3815(.in0 (n_180), .in1 (\count[15] ), .in2 (n_179), .in3
(n_225), .out0 (n_181));
aoi22_bdbd g3817(.in0 (n_180), .in1 (\count[1] ), .in2 (n_179), .in3
(n_240), .out0 (n_178));
aoi22_bdbd g3819(.in0 (n_180), .in1 (\count[2] ), .in2 (n_179), .in3
(n_239), .out0 (n_177));
ffrhq_x2 tx_done_reg(.RN (n_223), .CK (clk), .D (n_155), .Q
(tx_done));
ffrhq_x2 \tx_state_reg[0] (.RN (n_223), .CK (clk), .D (n_156), .Q
(\tx_state[0] ));
aoi22_bdbd g3821(.in0 (n_180), .in1 (\count[3] ), .in2 (n_179), .in3
(n_238), .out0 (n_176));
aoi22_bdbd g3823(.in0 (n_180), .in1 (\count[4] ), .in2 (n_179), .in3
(n_237), .out0 (n_175));
aoi22_bdbd g3825(.in0 (n_180), .in1 (\count[5] ), .in2 (n_179), .in3
(n_236), .out0 (n_174));
aoi22_bdbd g3827(.in0 (n_180), .in1 (\count[6] ), .in2 (n_179), .in3
(n_235), .out0 (n_173));
aoi22_bdbd g3829(.in0 (n_180), .in1 (\count[8] ), .in2 (n_179), .in3
(n_233), .out0 (n_172));
aoi22_bdbd g3831(.in0 (n_180), .in1 (\count[9] ), .in2 (n_179), .in3
(n_232), .out0 (n_171));
aoi22_bdbd g3833(.in0 (n_180), .in1 (\count[7] ), .in2 (n_179), .in3
(n_234), .out0 (n_170));
aoi22_bdbd g3835(.in0 (n_180), .in1 (\count[0] ), .in2 (n_179), .in3
(n_1), .out0 (n_169));
nor2_bd g3847(.in0 (n_206), .in1 (n_161), .out0 (n_213));
inv1x_bc g3848(.in0 (n_211), .out0 (n_168));
aoi22_bdbd g3805(.in0 (n_180), .in1 (\count[10] ), .in2 (n_179), .in3
(n_231), .out0 (n_167));
aoi22_bdbd g3807(.in0 (n_180), .in1 (\count[12] ), .in2 (n_179), .in3
(n_228), .out0 (n_166));
aoi22_bdbd g3809(.in0 (n_180), .in1 (\count[11] ), .in2 (n_179), .in3
(n_230), .out0 (n_165));
aoi22_bdbd g3811(.in0 (n_180), .in1 (\count[13] ), .in2 (n_179), .in3
(n_227), .out0 (n_164));
aoi22_bdbd g3813(.in0 (n_180), .in1 (\count[14] ), .in2 (n_179), .in3
(n_226), .out0 (n_163));
nand2_bc g3846(.in0 (n_196), .in1 (n_82), .out0 (n_209));
nand2_bc g3849(.in0 (n_196), .in1 (n_198), .out0 (n_211));
oai21_bdbc g3850(.in0 (n_161), .in1 (n_160), .in2 (n_196), .out0
(n_162));
oai21_bdbc g3851(.in0 (n_114), .in1 (n_161), .in2 (n_196), .out0
(n_159));
nand4_dc g3853(.in0 (n_157), .in1 (n_141), .in2 (n_136), .in3 (n_56),
.out0 (n_158));
nand3_cc g3854(.in0 (n_153), .in1 (n_133), .in2 (n_140), .out0
(n_156));
oai2bb1_bbbc g3855(.A0N (tx_done), .A1N (n_154), .B0 (n_153), .Y
(n_155));
inv1x_bc g3856(.in0 (n_196), .out0 (n_206));
nand4b_bbee g3852(.AN (n_152), .B (n_150), .C (n_121), .D (n_108), .Y
(n_179));
oai2bb1_bbbc g3858(.A0N (n_149), .A1N (n_151), .B0 (n_143), .Y
(n_196));
nand2b_bbbc g3859(.AN (n_150), .B (n_146), .Y (n_157));
nand2b_bbbc g3860(.AN (n_149), .B (n_151), .Y (n_153));
nor2_bd g3861(.in0 (n_148), .in1 (n_161), .out0 (n_151));
nand2_bc g3862(.in0 (n_148), .in1 (n_26), .out0 (n_150));
nor2_bd g3864(.in0 (n_147), .in1 (n_105), .out0 (n_148));
oai21_bdbc g3866(.in0 (n_145), .in1 (n_134), .in2 (n_77), .out0
(n_147));
oai22_bdbd g3867(.in0 (n_145), .in1 (n_127), .in2 (n_14), .in3 (n_6),
.out0 (n_146));
ffrhq_x2 \tx_state_reg[1] (.RN (n_223), .CK (clk), .D (n_144), .Q
(\tx_state[1] ));
nor2_bd g3870(.in0 (n_142), .in1 (\current_tx_bit[6] ), .out0
(n_145));
ffrhq_x2 \tx_state_reg[2] (.RN (n_223), .CK (clk), .D (n_139), .Q
(\tx_state[2] ));
nand3_cc g3868(.in0 (n_132), .in1 (n_138), .in2 (n_143), .out0
(n_144));
oai22_bdbd g3874(.in0 (n_129), .in1 (\current_tx_bit[5] ), .in2
(n_122), .in3 (n_110), .out0 (n_142));
nor3b_bbbe g3876(.AN (n_140), .B (n_135), .C (n_115), .Y (n_141));
nand3_cc g3869(.in0 (n_128), .in1 (n_126), .in2 (n_138), .out0
(n_139));
aoi2bb2_bbbdbd g3875(.A0N (n_136), .A1N (n_120), .B0 (n_135), .B1
(n_134), .Y (n_137));
aoi22_bdbd g3871(.in0 (n_131), .in1 (send_trcal), .in2 (n_130), .in3
(\tx_state[0] ), .out0 (n_133));
aoi22_bdbd g3872(.in0 (n_131), .in1 (n_0), .in2 (n_130), .in3
(\tx_state[1] ), .out0 (n_132));
oai22_bdbd g3879(.in0 (n_117), .in1 (\current_tx_bit[2] ), .in2
(n_118), .in3 (n_21), .out0 (n_129));
nand2_bc g3873(.in0 (n_130), .in1 (\tx_state[2] ), .out0 (n_128));
nor2b_bbbd g3878(.AN (n_119), .B (n_127), .Y (n_135));
nor3b_bbbe g3877(.AN (n_126), .B (n_104), .C (n_57), .Y (n_130));
nor2_bd g3882(.in0 (n_125), .in1 (n_124), .out0 (n_131));
nor2b_bbbd g3883(.AN (n_125), .B (n_124), .Y (n_152));
oai22_bdbd g3886(.in0 (n_81), .in1 (tx_packet_data[32]), .in2
(n_112), .in3 (n_161), .out0 (n_123));
oai22_bdbd g3894(.in0 (n_109), .in1 (\current_tx_bit[4] ), .in2
(n_58), .in3 (\current_tx_bit[2] ), .out0 (n_122));
aoi2bb2_bbbdbd g3880(.A0N (n_120), .A1N (n_95), .B0 (n_134), .B1
(n_119), .Y (n_121));
aoi21_bdbd g3885(.in0 (n_76), .in1 (\count[5] ), .in2 (n_113), .out0
(n_127));
aoi22_bdbd g3895(.in0 (n_100), .in1 (n_116), .in2 (n_101), .in3
(\current_tx_bit[4] ), .out0 (n_118));
aoi22_bdbd g3896(.in0 (n_98), .in1 (n_116), .in2 (n_99), .in3
(\current_tx_bit[4] ), .out0 (n_117));
aoi21_bdbd g3891(.in0 (n_10), .in1 (\count[7] ), .in2 (n_103), .out0
(n_125));
nand2b_bbbc g3881(.AN (n_134), .B (n_119), .Y (n_126));
aoi21_bdbd g3884(.in0 (n_102), .in1 (n_46), .in2 (n_124), .out0
(n_115));
nand2b_bbbc g3887(.AN (\current_tx_bit[6] ), .B (n_114), .Y (n_149));
nand2b_bbbc g3889(.AN (n_107), .B (n_106), .Y (n_140));
inv1x_bc g3892(.in0 (n_134), .out0 (n_113));
aoi2bb1_bbbe g3913(.A0N (n_111), .A1N (n_110), .B0 (n_114), .Y
(n_112));
aoi22_bdbd g3915(.in0 (n_24), .in1 (\current_tx_bit[3] ), .in2
(n_88), .in3 (n_62), .out0 (n_109));
nand2_bc g3888(.in0 (n_107), .in1 (n_106), .out0 (n_108));
oai21_bdbc g3890(.in0 (n_96), .in1 (n_29), .in2 (n_97), .out0
(n_136));
nor3b_bbbe g3893(.AN (n_60), .B (n_105), .C (\count[6] ), .Y (n_134));
inv1x_bc g3897(.in0 (n_104), .out0 (n_138));
inv1x_bc g3900(.in0 (n_102), .out0 (n_103));
nand3_cc g3909(.in0 (n_92), .in1 (n_69), .in2 (n_54), .out0 (n_101));
nand3_cc g3910(.in0 (n_89), .in1 (n_66), .in2 (n_55), .out0 (n_100));
nand3_cc g3911(.in0 (n_90), .in1 (n_70), .in2 (n_52), .out0 (n_99));
nand3_cc g3912(.in0 (n_93), .in1 (n_65), .in2 (n_51), .out0 (n_98));
ffrhq_x2 tx_running_reg(.RN (n_223), .CK (clk), .D (n_83), .Q
(tx_running));
and2_bbcd g3898(.A (n_120), .B (n_97), .Y (n_104));
aoi21_bdbd g3899(.in0 (n_61), .in1 (\count[6] ), .in2 (n_105), .out0
(n_107));
aoi21_bdbd g3901(.in0 (n_43), .in1 (\count[7] ), .in2 (n_96), .out0
(n_102));
and4_bbcd g3914(.A (n_80), .B (n_161), .C (n_124), .D (n_95), .Y
(n_180));
and2_bbcd g3916(.A (n_111), .B (n_110), .Y (n_114));
oai22_bdbd g3902(.in0 (n_64), .in1 (n_161), .in2 (n_49), .in3
(n_154), .out0 (n_94));
aoi22_bdbd g3924(.in0 (n_72), .in1 (\current_tx_bit[3] ), .in2
(tx_packet_data[0]), .in3 (n_91), .out0 (n_93));
aoi22_bdbd g3925(.in0 (n_75), .in1 (\current_tx_bit[3] ), .in2
(n_91), .in3 (tx_packet_data[20]), .out0 (n_92));
aoi22_bdbd g3926(.in0 (n_74), .in1 (\current_tx_bit[3] ), .in2
(tx_packet_data[16]), .in3 (n_91), .out0 (n_90));
aoi22_bdbd g3927(.in0 (n_73), .in1 (\current_tx_bit[3] ), .in2
(tx_packet_data[4]), .in3 (n_91), .out0 (n_89));
oai2bb2_bbbdbc g3928(.A0N (\current_tx_bit[2] ), .A1N (n_71), .B0
(n_50), .B1 (\current_tx_bit[2] ), .Y (n_88));
nand2_bc g3903(.in0 (n_87), .in1 (n_86), .out0 (n_96));
nand2b_bbbc g3904(.AN (\count[7] ), .B (n_87), .Y (n_105));
oai21_bdbc g3908(.in0 (n_45), .in1 (n_86), .in2 (n_87), .out0
(n_120));
nor2_bd g3922(.in0 (n_84), .in1 (n_161), .out0 (n_85));
and2_bbcd g3923(.A (n_84), .B (n_116), .Y (n_111));
oai2bb2_bbbdbc g3932(.A0N (tx_running), .A1N (n_154), .B0 (n_143),
.B1 (n_154), .Y (n_83));
inv1x_bc g3905(.in0 (n_81), .out0 (n_82));
nor3b_bbbe g3930(.AN (n_143), .B (n_106), .C (n_119), .Y (n_80));
nand2_bc g3906(.in0 (n_78), .in1 (n_198), .out0 (n_81));
nand2b_bbbc g3907(.AN (n_78), .B (tx_packet_data[32]), .Y (n_79));
nor3_be g3919(.in0 (n_47), .in1 (\count[9] ), .in2 (\count[8] ),
.out0 (n_87));
aoi22_bdbd g3931(.in0 (\count[6] ), .in1 (\count[5] ), .in2 (n_76),
.in3 (n_7), .out0 (n_77));
nand2_bc g3934(.in0 (n_39), .in1 (n_32), .out0 (n_75));
nand2_bc g3935(.in0 (n_40), .in1 (n_33), .out0 (n_74));
nand2_bc g3937(.in0 (n_35), .in1 (n_37), .out0 (n_73));
nand2_bc g3938(.in0 (n_31), .in1 (n_36), .out0 (n_72));
oai21_bdbc g3941(.in0 (n_23), .in1 (\current_tx_bit[1] ), .in2
(n_42), .out0 (n_71));
aoi22_bdbd g3943(.in0 (n_68), .in1 (tx_packet_data[18]), .in2 (n_67),
.in3 (tx_packet_data[19]), .out0 (n_70));
aoi22_bdbd g3944(.in0 (n_68), .in1 (tx_packet_data[22]), .in2 (n_67),
.in3 (tx_packet_data[23]), .out0 (n_69));
aoi22_bdbd g3945(.in0 (tx_packet_data[6]), .in1 (n_68), .in2
(tx_packet_data[7]), .in3 (n_67), .out0 (n_66));
aoi22_bdbd g3946(.in0 (tx_packet_data[2]), .in1 (n_68), .in2
(tx_packet_data[3]), .in3 (n_67), .out0 (n_65));
addh_bbbcbcbcbbbd g3933(.A (n_63), .B (n_62), .CO (n_84), .S (n_64));
nor2_bd g3936(.in0 (n_30), .in1 (n_60), .out0 (n_61));
aoi21_bdbd g3920(.in0 (n_48), .in1 (n_19), .in2 (n_154), .out0
(n_59));
nand3_cc g3942(.in0 (tx_packet_data[48]), .in1 (n_12), .in2
(\current_tx_bit[4] ), .out0 (n_58));
oai22_bdbd g3947(.in0 (\tx_state[2] ), .in1 (\tx_state[1] ), .in2
(n_56), .in3 (tx_go), .out0 (n_57));
nand2_bc g3948(.in0 (n_198), .in1 (tx_go), .out0 (n_143));
nand2_bc g3949(.in0 (tx_packet_data[5]), .in1 (n_53), .out0 (n_55));
nand2_bc g3950(.in0 (n_53), .in1 (tx_packet_data[21]), .out0 (n_54));
nand2_bc g3951(.in0 (n_53), .in1 (tx_packet_data[17]), .out0 (n_52));
nand2_bc g3953(.in0 (tx_packet_data[1]), .in1 (n_53), .out0 (n_51));
aoi22_bdbd g3959(.in0 (tx_packet_data[32]), .in1 (n_160), .in2
(n_20), .in3 (\current_tx_bit[1] ), .out0 (n_50));
nand2_bc g3917(.in0 (n_48), .in1 (tx_packet_length[3]), .out0 (n_49));
nor2_bd g3918(.in0 (n_48), .in1 (tx_packet_length[3]), .out0 (n_78));
nand4bb_bbbbdc g3929(.AN (\count[11] ), .BN (\count[12] ), .C (n_8),
.D (n_2), .Y (n_47));
nand2_bc g3952(.in0 (n_44), .in1 (\count[7] ), .out0 (n_46));
nor2_bd g3954(.in0 (n_44), .in1 (n_43), .out0 (n_45));
aoi22_bdbd g3958(.in0 (n_38), .in1 (tx_packet_data[38]), .in2
(tx_packet_data[39]), .in3 (n_41), .out0 (n_42));
aoi22_bdbd g3960(.in0 (tx_packet_data[24]), .in1 (n_160), .in2
(tx_packet_data[25]), .in3 (n_34), .out0 (n_40));
aoi22_bdbd g3961(.in0 (tx_packet_data[30]), .in1 (n_38), .in2
(tx_packet_data[31]), .in3 (n_41), .out0 (n_39));
aoi22_bdbd g3962(.in0 (tx_packet_data[14]), .in1 (n_38), .in2
(tx_packet_data[15]), .in3 (n_41), .out0 (n_37));
aoi22_bdbd g3963(.in0 (tx_packet_data[10]), .in1 (n_38), .in2
(tx_packet_data[11]), .in3 (n_41), .out0 (n_36));
aoi22_bdbd g3964(.in0 (tx_packet_data[12]), .in1 (n_160), .in2
(tx_packet_data[13]), .in3 (n_34), .out0 (n_35));
aoi22_bdbd g3965(.in0 (tx_packet_data[26]), .in1 (n_38), .in2
(tx_packet_data[27]), .in3 (n_41), .out0 (n_33));
aoi22_bdbd g3966(.in0 (tx_packet_data[28]), .in1 (n_160), .in2
(tx_packet_data[29]), .in3 (n_34), .out0 (n_32));
aoi22_bdbd g3967(.in0 (tx_packet_data[8]), .in1 (n_160), .in2
(tx_packet_data[9]), .in3 (n_34), .out0 (n_31));
aoi21_bdbd g3955(.in0 (n_28), .in1 (\count[2] ), .in2 (\count[3] ),
.out0 (n_30));
nor3b_bbbe g3956(.AN (\count[7] ), .B (n_27), .C (n_60), .Y (n_29));
and2_bbcd g3982(.A (n_34), .B (n_62), .Y (n_53));
oai2bb1_bbbc g3957(.A0N (\count[3] ), .A1N (n_28), .B0 (n_27), .Y
(n_76));
and2_bbcd g3981(.A (n_38), .B (n_62), .Y (n_68));
inv1x_bc g3979(.in0 (n_161), .out0 (n_26));
inv1x_bc g3969(.in0 (n_154), .out0 (n_198));
nor2_bd g3976(.in0 (n_5), .in1 (\current_tx_bit[3] ), .out0 (n_67));
aoi21_bdbd g3985(.in0 (\current_tx_bit[1] ), .in1 (\current_tx_bit[2]
), .in2 (n_23), .out0 (n_24));
aoi21_bdbd g3983(.in0 (tx_packet_length[1]), .in1
(tx_packet_length[0]), .in2 (n_18), .out0 (n_22));
and2_bbcd g3975(.A (n_160), .B (n_62), .Y (n_91));
and2_bbcd g3977(.A (n_160), .B (n_21), .Y (n_63));
inv1x_bc g3995(.in0 (n_23), .out0 (n_20));
nand2_bc g3968(.in0 (n_16), .in1 (\tx_state[2] ), .out0 (n_124));
nor2_bd g3978(.in0 (n_13), .in1 (\tx_state[2] ), .out0 (n_106));
or2_bbcd g3974(.A (n_17), .B (n_15), .Y (n_56));
nand2b_bbbc g3939(.AN (n_18), .B (tx_packet_length[2]), .Y (n_19));
nand2b_bbbc g3940(.AN (tx_packet_length[2]), .B (n_18), .Y (n_48));
nor2_bd g3972(.in0 (n_17), .in1 (\tx_state[2] ), .out0 (n_119));
nand2_bc g3971(.in0 (n_16), .in1 (n_15), .out0 (n_154));
nor2b_bbbd g3973(.AN (n_9), .B (\count[1] ), .Y (n_14));
or2_bbcd g3980(.A (n_13), .B (n_15), .Y (n_161));
oai21_bdbc g3984(.in0 (\current_tx_bit[3] ), .in1 (n_11), .in2
(\current_tx_bit[1] ), .out0 (n_12));
oai2bb1_bbbc g3986(.A0N (\count[1] ), .A1N (\count[3] ), .B0 (n_27),
.Y (n_10));
oai2bb1_bbbc g3988(.A0N (\count[0] ), .A1N (\count[1] ), .B0 (n_9),
.Y (n_44));
inv1x_bc g3989(.in0 (n_95), .out0 (n_97));
nand3b_bbcc g3990(.AN (\tx_state[1] ), .B (\tx_state[2] ), .C
(\tx_state[0] ), .Y (n_95));
nor3_be g3987(.in0 (\count[14] ), .in1 (\count[13] ), .in2
(\count[15] ), .out0 (n_8));
and2_bbcd g3994(.A (\current_tx_bit[1] ), .B (n_11), .Y (n_38));
nand2_bc g3996(.in0 (tx_packet_data[34]), .in1 (n_11), .out0 (n_23));
inv1x_bc g4003(.in0 (n_6), .out0 (n_7));
nor2_bd g4001(.in0 (\current_tx_bit[1] ), .in1 (n_11), .out0 (n_34));
inv1x_bc g3992(.in0 (n_41), .out0 (n_5));
nor2_bd g4000(.in0 (tx_packet_length[1]), .in1 (tx_packet_length[0]),
.out0 (n_18));
nor2_ce g3998(.in0 (\current_tx_bit[1] ), .in1 (\current_tx_bit[0] ),
.out0 (n_160));
nand2_bc g4002(.in0 (\count[5] ), .in1 (\count[4] ), .out0 (n_60));
nand2_bc g4004(.in0 (\count[6] ), .in1 (\count[4] ), .out0 (n_6));
nor2_bd g3997(.in0 (\count[3] ), .in1 (\count[2] ), .out0 (n_9));
nor2_bd g3991(.in0 (\tx_state[1] ), .in1 (\tx_state[0] ), .out0
(n_16));
nand2_bc g4005(.in0 (\count[3] ), .in1 (\count[2] ), .out0 (n_27));
nand2_bc g4007(.in0 (\tx_state[1] ), .in1 (\tx_state[0] ), .out0
(n_17));
nand2_bc g3999(.in0 (\count[6] ), .in1 (\count[7] ), .out0 (n_86));
nand2b_bbbc g4008(.AN (\tx_state[0] ), .B (\tx_state[1] ), .Y (n_13));
and2_bbcd g3993(.A (\current_tx_bit[1] ), .B (\current_tx_bit[0] ),
.Y (n_41));
or2_bbcd g4009(.A (\count[5] ), .B (\count[4] ), .Y (n_43));
or2_bbcd g4006(.A (\count[1] ), .B (\count[0] ), .Y (n_28));
inv1x_bc g4019(.in0 (reset), .out0 (n_223));
inv1x_bc g4010(.in0 (\tx_state[2] ), .out0 (n_15));
inv1x_bc g4016(.in0 (\current_tx_bit[0] ), .out0 (n_11));
inv1x_bc g4013(.in0 (\current_tx_bit[3] ), .out0 (n_62));
inv1x_bc g4011(.in0 (\count[10] ), .out0 (n_2));
inv1x_bc g4015(.in0 (\count[0] ), .out0 (n_1));
inv1x_bc g4012(.in0 (\current_tx_bit[5] ), .out0 (n_110));
inv1x_bc g4018(.in0 (send_trcal), .out0 (n_0));
inv1x_bc g4014(.in0 (\current_tx_bit[2] ), .out0 (n_21));
inv1x_bc g4020(.in0 (\current_tx_bit[4] ), .out0 (n_116));
endmodule
module rfid_reader_packet_rxtx(reset, clk, tag_backscatter,
reader_modulation, miller, trext, divide_ratio, tari_ns, trcal_ns,
slot_q, q_adj, session, target, select, send_packet_type,
start_tx, reader_done, rx_timeout, rx_packet_complete,
reader_running, tx_handle, rx_handle);
input reset, clk, tag_backscatter, trext, divide_ratio, target,
start_tx;
input [2:0] miller, q_adj;
input [15:0] tari_ns, trcal_ns, tx_handle;
input [3:0] slot_q, send_packet_type;
input [1:0] session, select;
output reader_modulation, reader_done, rx_timeout,
rx_packet_complete, reader_running;
output [15:0] rx_handle;
wire reset, clk, tag_backscatter, trext, divide_ratio, target,
start_tx;
wire [2:0] miller, q_adj;
wire [15:0] tari_ns, trcal_ns, tx_handle;
wire [3:0] slot_q, send_packet_type;
wire [1:0] session, select;
wire reader_modulation, reader_done, rx_timeout, rx_packet_complete,
reader_running;
wire [15:0] rx_handle;
wire UNCONNECTED3, UNCONNECTED4, UNCONNECTED5, UNCONNECTED6,
UNCONNECTED7, UNCONNECTED8, UNCONNECTED9, UNCONNECTED10;
wire UNCONNECTED11, UNCONNECTED12, UNCONNECTED13, UNCONNECTED14,
UNCONNECTED15, UNCONNECTED16, UNCONNECTED17, UNCONNECTED18;
wire UNCONNECTED19, UNCONNECTED20, UNCONNECTED21, UNCONNECTED22,
UNCONNECTED23, UNCONNECTED24, UNCONNECTED25, UNCONNECTED26;
wire UNCONNECTED27, UNCONNECTED28, UNCONNECTED29, UNCONNECTED30,
UNCONNECTED31, UNCONNECTED32, UNCONNECTED33, UNCONNECTED34;
wire UNCONNECTED35, UNCONNECTED36, UNCONNECTED37, UNCONNECTED38,
UNCONNECTED39, UNCONNECTED40, UNCONNECTED41, UNCONNECTED42;
wire UNCONNECTED43, UNCONNECTED44, UNCONNECTED45, UNCONNECTED46,
UNCONNECTED47, UNCONNECTED48, UNCONNECTED49, UNCONNECTED50;
wire UNCONNECTED51, UNCONNECTED52, UNCONNECTED53, UNCONNECTED54,
UNCONNECTED55, UNCONNECTED56, UNCONNECTED57, UNCONNECTED58;
wire UNCONNECTED59, UNCONNECTED60, UNCONNECTED61, UNCONNECTED62,
UNCONNECTED63, UNCONNECTED64, UNCONNECTED65, UNCONNECTED66;
wire UNCONNECTED67, UNCONNECTED68, UNCONNECTED69, UNCONNECTED70,
UNCONNECTED71, UNCONNECTED72, UNCONNECTED73, UNCONNECTED74;
wire UNCONNECTED75, UNCONNECTED76, UNCONNECTED77, UNCONNECTED78,
UNCONNECTED79, UNCONNECTED80, UNCONNECTED81, UNCONNECTED82;
wire UNCONNECTED83, UNCONNECTED84, UNCONNECTED85, UNCONNECTED86,
UNCONNECTED87, UNCONNECTED88, UNCONNECTED89, UNCONNECTED90;
wire UNCONNECTED91, UNCONNECTED92, UNCONNECTED93, UNCONNECTED94,
UNCONNECTED95, UNCONNECTED96, UNCONNECTED97, UNCONNECTED98;
wire UNCONNECTED99, UNCONNECTED100, UNCONNECTED101, UNCONNECTED102,
UNCONNECTED103, UNCONNECTED104, UNCONNECTED105, UNCONNECTED106;
wire UNCONNECTED107, UNCONNECTED108, UNCONNECTED109, UNCONNECTED110,
UNCONNECTED111, UNCONNECTED112, UNCONNECTED113, UNCONNECTED114;
wire UNCONNECTED115, UNCONNECTED116, UNCONNECTED117, UNCONNECTED118,
UNCONNECTED119, UNCONNECTED120, UNCONNECTED121, UNCONNECTED122;
wire UNCONNECTED123, UNCONNECTED124, UNCONNECTED125, UNCONNECTED126,
UNCONNECTED127, UNCONNECTED128, UNCONNECTED129, UNCONNECTED130;
wire UNCONNECTED131, UNCONNECTED132, UNCONNECTED133, UNCONNECTED134,
UNCONNECTED135, UNCONNECTED136, UNCONNECTED137, UNCONNECTED138;
wire UNCONNECTED139, UNCONNECTED140, UNCONNECTED141, UNCONNECTED142,
UNCONNECTED143, UNCONNECTED144, UNCONNECTED145, UNCONNECTED146;
wire UNCONNECTED147, UNCONNECTED148, UNCONNECTED149, UNCONNECTED150,
UNCONNECTED151, UNCONNECTED152, UNCONNECTED153, UNCONNECTED154;
wire UNCONNECTED155, UNCONNECTED156, UNCONNECTED157, UNCONNECTED158,
UNCONNECTED159, UNCONNECTED160, UNCONNECTED161, UNCONNECTED162;
wire UNCONNECTED163, UNCONNECTED164, UNCONNECTED165, UNCONNECTED166,
UNCONNECTED167, UNCONNECTED168, UNCONNECTED169, UNCONNECTED170;
wire UNCONNECTED171, UNCONNECTED172, UNCONNECTED173, UNCONNECTED174,
UNCONNECTED175, UNCONNECTED176, UNCONNECTED177, UNCONNECTED178;
wire UNCONNECTED179, UNCONNECTED180, UNCONNECTED181, UNCONNECTED182,
UNCONNECTED183, UNCONNECTED184, UNCONNECTED185, UNCONNECTED186;
wire UNCONNECTED187, UNCONNECTED188, UNCONNECTED189, UNCONNECTED190,
UNCONNECTED191, UNCONNECTED192, UNCONNECTED193, UNCONNECTED194;
wire UNCONNECTED195, UNCONNECTED196, UNCONNECTED197, UNCONNECTED198,
UNCONNECTED199, UNCONNECTED200, UNCONNECTED201, UNCONNECTED202;
wire UNCONNECTED203, UNCONNECTED204, UNCONNECTED205, UNCONNECTED206,
UNCONNECTED207, UNCONNECTED208, UNCONNECTED209, UNCONNECTED210;
wire UNCONNECTED211, UNCONNECTED212, UNCONNECTED213, UNCONNECTED214,
UNCONNECTED215, UNCONNECTED216, UNCONNECTED217, UNCONNECTED218;
wire UNCONNECTED219, UNCONNECTED220, UNCONNECTED221, UNCONNECTED222,
UNCONNECTED223, UNCONNECTED224, UNCONNECTED225, UNCONNECTED226;
wire UNCONNECTED227, UNCONNECTED228, UNCONNECTED229, UNCONNECTED230,
UNCONNECTED231, UNCONNECTED232, UNCONNECTED233, UNCONNECTED234;
wire UNCONNECTED235, UNCONNECTED236, UNCONNECTED237, UNCONNECTED238,
UNCONNECTED239, UNCONNECTED240, UNCONNECTED241, UNCONNECTED242;
wire UNCONNECTED243, UNCONNECTED244, UNCONNECTED245, UNCONNECTED246,
UNCONNECTED247, UNCONNECTED248, UNCONNECTED249, UNCONNECTED250;
wire UNCONNECTED251, UNCONNECTED252, UNCONNECTED253, UNCONNECTED254,
UNCONNECTED255, UNCONNECTED256, UNCONNECTED257, UNCONNECTED258;
wire UNCONNECTED259, UNCONNECTED260, UNCONNECTED261, UNCONNECTED262,
UNCONNECTED263, UNCONNECTED264, UNCONNECTED265, UNCONNECTED266;
wire UNCONNECTED267, UNCONNECTED268, UNCONNECTED269, UNCONNECTED270,
UNCONNECTED271, UNCONNECTED272, UNCONNECTED273, UNCONNECTED274;
wire UNCONNECTED275, UNCONNECTED276, UNCONNECTED277, UNCONNECTED278,
UNCONNECTED279, UNCONNECTED280, UNCONNECTED281, UNCONNECTED282;
wire UNCONNECTED283, UNCONNECTED284, UNCONNECTED285, UNCONNECTED286,
UNCONNECTED287, UNCONNECTED288, UNCONNECTED289, UNCONNECTED290;
wire UNCONNECTED291, UNCONNECTED292, UNCONNECTED293, UNCONNECTED294,
UNCONNECTED295, UNCONNECTED296, UNCONNECTED297, UNCONNECTED298;
wire UNCONNECTED299, UNCONNECTED300, UNCONNECTED301, UNCONNECTED302,
UNCONNECTED303, UNCONNECTED304, UNCONNECTED305, UNCONNECTED306;
wire UNCONNECTED307, UNCONNECTED308, UNCONNECTED309, UNCONNECTED310,
UNCONNECTED311, UNCONNECTED312, UNCONNECTED313, UNCONNECTED314;
wire UNCONNECTED315, UNCONNECTED316, UNCONNECTED317, UNCONNECTED318,
UNCONNECTED319, UNCONNECTED320, UNCONNECTED321, UNCONNECTED322;
wire UNCONNECTED323, UNCONNECTED324, UNCONNECTED325, UNCONNECTED326,
UNCONNECTED327, UNCONNECTED328, UNCONNECTED329, UNCONNECTED330;
wire UNCONNECTED331, UNCONNECTED332, UNCONNECTED333, UNCONNECTED334,
UNCONNECTED335, UNCONNECTED336, UNCONNECTED337, UNCONNECTED338;
wire UNCONNECTED339, UNCONNECTED340, UNCONNECTED341, UNCONNECTED342,
UNCONNECTED343, UNCONNECTED344, UNCONNECTED345, UNCONNECTED346;
wire UNCONNECTED347, UNCONNECTED348, UNCONNECTED349, UNCONNECTED350,
UNCONNECTED351, UNCONNECTED352, UNCONNECTED353, UNCONNECTED354;
wire UNCONNECTED355, UNCONNECTED356, UNCONNECTED357, UNCONNECTED358,
UNCONNECTED359, UNCONNECTED360, UNCONNECTED361, UNCONNECTED362;
wire UNCONNECTED363, UNCONNECTED364, UNCONNECTED365, UNCONNECTED366,
UNCONNECTED367, UNCONNECTED368, UNCONNECTED369, UNCONNECTED370;
wire UNCONNECTED371, UNCONNECTED372, UNCONNECTED373, UNCONNECTED374,
UNCONNECTED375, UNCONNECTED376, UNCONNECTED377, UNCONNECTED378;
wire UNCONNECTED379, UNCONNECTED380, UNCONNECTED381, UNCONNECTED382,
UNCONNECTED383, UNCONNECTED384, UNCONNECTED385, UNCONNECTED386;
wire UNCONNECTED387, UNCONNECTED388, UNCONNECTED389, UNCONNECTED390,
UNCONNECTED391, UNCONNECTED392, UNCONNECTED393, UNCONNECTED394;
wire UNCONNECTED395, UNCONNECTED396, UNCONNECTED397, UNCONNECTED398,
UNCONNECTED399, UNCONNECTED400, UNCONNECTED401, UNCONNECTED402;
wire UNCONNECTED403, UNCONNECTED404, UNCONNECTED405, UNCONNECTED406,
UNCONNECTED407, UNCONNECTED408, UNCONNECTED409, UNCONNECTED410;
wire UNCONNECTED411, UNCONNECTED412, UNCONNECTED413, UNCONNECTED414,
UNCONNECTED415, UNCONNECTED416, UNCONNECTED417, UNCONNECTED418;
wire UNCONNECTED419, UNCONNECTED420, UNCONNECTED421, UNCONNECTED422,
UNCONNECTED423, UNCONNECTED424, UNCONNECTED425, UNCONNECTED426;
wire UNCONNECTED427, UNCONNECTED428, UNCONNECTED429, UNCONNECTED430,
UNCONNECTED431, UNCONNECTED432, UNCONNECTED433, UNCONNECTED434;
wire UNCONNECTED435, UNCONNECTED436, UNCONNECTED437, UNCONNECTED438,
UNCONNECTED439, UNCONNECTED440, UNCONNECTED441, UNCONNECTED442;
wire UNCONNECTED443, UNCONNECTED444, UNCONNECTED445, UNCONNECTED446,
UNCONNECTED447, UNCONNECTED448, UNCONNECTED449, UNCONNECTED450;
wire UNCONNECTED451, UNCONNECTED452, UNCONNECTED453, UNCONNECTED454,
UNCONNECTED455, UNCONNECTED456, UNCONNECTED457, UNCONNECTED458;
wire UNCONNECTED459, UNCONNECTED460, UNCONNECTED461, UNCONNECTED462,
UNCONNECTED463, UNCONNECTED464, UNCONNECTED465, UNCONNECTED466;
wire UNCONNECTED467, UNCONNECTED468, UNCONNECTED469, UNCONNECTED470,
UNCONNECTED471, UNCONNECTED472, UNCONNECTED473, UNCONNECTED474;
wire UNCONNECTED475, UNCONNECTED476, UNCONNECTED477, UNCONNECTED478,
UNCONNECTED479, UNCONNECTED480, UNCONNECTED481, UNCONNECTED482;
wire UNCONNECTED483, UNCONNECTED484, UNCONNECTED485, UNCONNECTED486,
UNCONNECTED487, UNCONNECTED488, UNCONNECTED489, UNCONNECTED490;
wire UNCONNECTED491, UNCONNECTED492, UNCONNECTED493, UNCONNECTED494,
UNCONNECTED495, UNCONNECTED496, UNCONNECTED497, UNCONNECTED498;
wire UNCONNECTED499, UNCONNECTED500, UNCONNECTED501, UNCONNECTED502,
UNCONNECTED503, UNCONNECTED504, UNCONNECTED505, UNCONNECTED506;
wire UNCONNECTED507, UNCONNECTED508, UNCONNECTED509, UNCONNECTED510,
UNCONNECTED511, UNCONNECTED512, UNCONNECTED513, UNCONNECTED514;
wire UNCONNECTED515, UNCONNECTED516, UNCONNECTED517, UNCONNECTED518,
UNCONNECTED519, UNCONNECTED520, UNCONNECTED521, UNCONNECTED522;
wire UNCONNECTED523, UNCONNECTED524, UNCONNECTED525, UNCONNECTED526,
UNCONNECTED527, UNCONNECTED528, UNCONNECTED529, UNCONNECTED530;
wire UNCONNECTED531, UNCONNECTED532, UNCONNECTED533, UNCONNECTED534,
UNCONNECTED535, UNCONNECTED536, UNCONNECTED537, UNCONNECTED538;
wire UNCONNECTED539, UNCONNECTED540, UNCONNECTED541, UNCONNECTED542,
UNCONNECTED543, UNCONNECTED544, UNCONNECTED545, UNCONNECTED546;
wire UNCONNECTED547, UNCONNECTED548, UNCONNECTED549, UNCONNECTED550,
UNCONNECTED551, UNCONNECTED552, UNCONNECTED553, UNCONNECTED554;
wire UNCONNECTED555, UNCONNECTED556, UNCONNECTED557, UNCONNECTED558,
UNCONNECTED559, UNCONNECTED560, UNCONNECTED561, UNCONNECTED562;
wire UNCONNECTED563, UNCONNECTED564, UNCONNECTED565, UNCONNECTED566,
UNCONNECTED567, UNCONNECTED568, UNCONNECTED569, UNCONNECTED570;
wire UNCONNECTED571, UNCONNECTED572, UNCONNECTED573, UNCONNECTED574,
UNCONNECTED575, UNCONNECTED576, UNCONNECTED577, UNCONNECTED578;
wire UNCONNECTED579, UNCONNECTED580, UNCONNECTED581, UNCONNECTED582,
UNCONNECTED583, UNCONNECTED584, UNCONNECTED585, UNCONNECTED586;
wire UNCONNECTED587, UNCONNECTED588, UNCONNECTED589, UNCONNECTED590,
UNCONNECTED591, UNCONNECTED592, UNCONNECTED593, UNCONNECTED594;
wire UNCONNECTED595, UNCONNECTED596, UNCONNECTED597, UNCONNECTED598,
UNCONNECTED599, UNCONNECTED600, UNCONNECTED601, UNCONNECTED602;
wire UNCONNECTED603, UNCONNECTED604, UNCONNECTED605, UNCONNECTED606,
UNCONNECTED607, UNCONNECTED608, UNCONNECTED609, UNCONNECTED610;
wire UNCONNECTED611, UNCONNECTED612, UNCONNECTED613, UNCONNECTED614,
UNCONNECTED615, UNCONNECTED616, UNCONNECTED617, UNCONNECTED618;
wire UNCONNECTED619, UNCONNECTED620, UNCONNECTED621, UNCONNECTED622,
UNCONNECTED623, UNCONNECTED624, UNCONNECTED625, UNCONNECTED626;
wire UNCONNECTED627, UNCONNECTED628, UNCONNECTED629, UNCONNECTED630,
UNCONNECTED631, UNCONNECTED632, UNCONNECTED633, UNCONNECTED634;
wire UNCONNECTED635, UNCONNECTED636, UNCONNECTED637, UNCONNECTED638,
UNCONNECTED639, UNCONNECTED640, UNCONNECTED641, UNCONNECTED642;
wire UNCONNECTED643, UNCONNECTED644, UNCONNECTED645, UNCONNECTED646,
UNCONNECTED647, UNCONNECTED648, UNCONNECTED649, UNCONNECTED650;
wire UNCONNECTED651, UNCONNECTED652, UNCONNECTED653, UNCONNECTED654,
UNCONNECTED655, UNCONNECTED656, UNCONNECTED657, UNCONNECTED658;
wire UNCONNECTED659, UNCONNECTED660, UNCONNECTED661, UNCONNECTED662,
UNCONNECTED663, UNCONNECTED664, UNCONNECTED665, UNCONNECTED666;
wire UNCONNECTED667, UNCONNECTED668, UNCONNECTED669, UNCONNECTED670,
UNCONNECTED671, UNCONNECTED672, UNCONNECTED673, UNCONNECTED674;
wire UNCONNECTED675, UNCONNECTED676, UNCONNECTED677, UNCONNECTED678,
UNCONNECTED679, UNCONNECTED680, UNCONNECTED681, UNCONNECTED682;
wire UNCONNECTED683, UNCONNECTED684, UNCONNECTED685, UNCONNECTED686,
UNCONNECTED687, UNCONNECTED688, UNCONNECTED689, UNCONNECTED690;
wire UNCONNECTED691, UNCONNECTED692, UNCONNECTED693, UNCONNECTED694,
UNCONNECTED695, UNCONNECTED696, UNCONNECTED697, UNCONNECTED698;
wire UNCONNECTED699, UNCONNECTED700, UNCONNECTED701, UNCONNECTED702,
UNCONNECTED703, UNCONNECTED704, UNCONNECTED705, UNCONNECTED706;
wire UNCONNECTED707, UNCONNECTED708, UNCONNECTED709, UNCONNECTED710,
UNCONNECTED711, UNCONNECTED712, UNCONNECTED713, UNCONNECTED714;
wire UNCONNECTED715, UNCONNECTED716, UNCONNECTED717, UNCONNECTED718,
UNCONNECTED719, UNCONNECTED720, UNCONNECTED721, UNCONNECTED722;
wire UNCONNECTED723, UNCONNECTED724, UNCONNECTED725, UNCONNECTED726,
UNCONNECTED727, UNCONNECTED728, UNCONNECTED729, UNCONNECTED730;
wire UNCONNECTED731, UNCONNECTED732, UNCONNECTED733, UNCONNECTED734,
UNCONNECTED735, UNCONNECTED736, UNCONNECTED737, UNCONNECTED738;
wire UNCONNECTED739, UNCONNECTED740, UNCONNECTED741, UNCONNECTED742,
UNCONNECTED743, UNCONNECTED744, UNCONNECTED745, UNCONNECTED746;
wire UNCONNECTED747, UNCONNECTED748, UNCONNECTED749, UNCONNECTED750,
UNCONNECTED751, UNCONNECTED752, UNCONNECTED753, UNCONNECTED754;
wire UNCONNECTED755, UNCONNECTED756, UNCONNECTED757, UNCONNECTED758,
UNCONNECTED759, UNCONNECTED760, UNCONNECTED761, UNCONNECTED762;
wire UNCONNECTED763, UNCONNECTED764, UNCONNECTED765, UNCONNECTED766,
UNCONNECTED767, UNCONNECTED768, UNCONNECTED769, UNCONNECTED770;
wire UNCONNECTED771, UNCONNECTED772, UNCONNECTED773, UNCONNECTED774,
UNCONNECTED775, UNCONNECTED776, UNCONNECTED777, UNCONNECTED778;
wire UNCONNECTED779, UNCONNECTED780, UNCONNECTED781, UNCONNECTED782,
UNCONNECTED783, UNCONNECTED784, UNCONNECTED785, UNCONNECTED786;
wire UNCONNECTED787, UNCONNECTED788, UNCONNECTED789, UNCONNECTED790,
UNCONNECTED791, UNCONNECTED792, UNCONNECTED793, UNCONNECTED794;
wire UNCONNECTED795, UNCONNECTED796, UNCONNECTED797, UNCONNECTED798,
UNCONNECTED799, UNCONNECTED800, UNCONNECTED801, UNCONNECTED802;
wire UNCONNECTED803, UNCONNECTED804, UNCONNECTED805, UNCONNECTED806,
UNCONNECTED807, UNCONNECTED808, UNCONNECTED809, UNCONNECTED810;
wire UNCONNECTED811, UNCONNECTED812, UNCONNECTED813, UNCONNECTED814,
UNCONNECTED815, UNCONNECTED816, UNCONNECTED817, UNCONNECTED818;
wire UNCONNECTED819, UNCONNECTED820, UNCONNECTED821, UNCONNECTED822,
UNCONNECTED823, UNCONNECTED824, UNCONNECTED825, UNCONNECTED826;
wire UNCONNECTED827, UNCONNECTED828, UNCONNECTED829, UNCONNECTED830,
UNCONNECTED831, UNCONNECTED832, UNCONNECTED833, UNCONNECTED834;
wire UNCONNECTED835, UNCONNECTED836, UNCONNECTED837, UNCONNECTED838,
UNCONNECTED839, UNCONNECTED840, UNCONNECTED841, UNCONNECTED842;
wire UNCONNECTED843, UNCONNECTED844, UNCONNECTED845, UNCONNECTED846,
UNCONNECTED847, UNCONNECTED848, UNCONNECTED849, UNCONNECTED850;
wire UNCONNECTED851, UNCONNECTED852, UNCONNECTED853, UNCONNECTED854,
UNCONNECTED855, UNCONNECTED856, UNCONNECTED857, UNCONNECTED858;
wire UNCONNECTED859, UNCONNECTED860, UNCONNECTED861, UNCONNECTED862,
UNCONNECTED863, UNCONNECTED864, UNCONNECTED865, UNCONNECTED866;
wire UNCONNECTED867, UNCONNECTED868, UNCONNECTED869, UNCONNECTED870,
UNCONNECTED871, UNCONNECTED872, UNCONNECTED873, UNCONNECTED874;
wire UNCONNECTED875, UNCONNECTED876, UNCONNECTED877, UNCONNECTED878,
UNCONNECTED879, UNCONNECTED880, UNCONNECTED881, UNCONNECTED882;
wire UNCONNECTED883, UNCONNECTED884, UNCONNECTED885, UNCONNECTED886,
UNCONNECTED887, UNCONNECTED888, UNCONNECTED889, UNCONNECTED890;
wire UNCONNECTED891, UNCONNECTED892, UNCONNECTED893, UNCONNECTED894,
UNCONNECTED895, UNCONNECTED896, UNCONNECTED897, UNCONNECTED898;
wire UNCONNECTED899, UNCONNECTED900, UNCONNECTED901, UNCONNECTED902,
UNCONNECTED903, UNCONNECTED904, UNCONNECTED905, UNCONNECTED906;
wire UNCONNECTED907, UNCONNECTED908, UNCONNECTED909, UNCONNECTED910,
UNCONNECTED911, UNCONNECTED912, UNCONNECTED913, UNCONNECTED914;
wire UNCONNECTED915, UNCONNECTED916, UNCONNECTED917, UNCONNECTED918,
UNCONNECTED919, UNCONNECTED920, UNCONNECTED921, UNCONNECTED922;
wire UNCONNECTED923, UNCONNECTED924, UNCONNECTED925, UNCONNECTED926,
UNCONNECTED927, UNCONNECTED928, UNCONNECTED929, UNCONNECTED930;
wire UNCONNECTED931, UNCONNECTED932, UNCONNECTED933, UNCONNECTED934,
UNCONNECTED935, UNCONNECTED936, UNCONNECTED937, UNCONNECTED938;
wire UNCONNECTED939, UNCONNECTED940, UNCONNECTED941, UNCONNECTED942,
UNCONNECTED943, UNCONNECTED944, UNCONNECTED945, UNCONNECTED946;
wire UNCONNECTED947, UNCONNECTED948, UNCONNECTED949, UNCONNECTED950,
UNCONNECTED951, UNCONNECTED952, UNCONNECTED953, UNCONNECTED954;
wire UNCONNECTED955, UNCONNECTED956, UNCONNECTED957, UNCONNECTED958,
UNCONNECTED959, UNCONNECTED960, UNCONNECTED961, UNCONNECTED962;
wire UNCONNECTED963, UNCONNECTED964, UNCONNECTED965, UNCONNECTED966,
UNCONNECTED967, UNCONNECTED968, UNCONNECTED969, UNCONNECTED970;
wire UNCONNECTED971, UNCONNECTED972, UNCONNECTED973, UNCONNECTED974,
UNCONNECTED975, UNCONNECTED976, UNCONNECTED977, UNCONNECTED978;
wire UNCONNECTED979, UNCONNECTED980, UNCONNECTED981, UNCONNECTED982,
UNCONNECTED983, UNCONNECTED984, UNCONNECTED985, UNCONNECTED986;
wire UNCONNECTED987, UNCONNECTED988, UNCONNECTED989, UNCONNECTED990,
UNCONNECTED991, UNCONNECTED992, UNCONNECTED993, UNCONNECTED994;
wire UNCONNECTED995, UNCONNECTED996, UNCONNECTED997, UNCONNECTED998,
UNCONNECTED999, UNCONNECTED1000, UNCONNECTED1001,
UNCONNECTED1002;
wire UNCONNECTED1003, UNCONNECTED1004, UNCONNECTED1005,
UNCONNECTED1006, UNCONNECTED1007, UNCONNECTED1008,
UNCONNECTED1009, UNCONNECTED1010;
wire UNCONNECTED1011, n_1, n_2, n_3, n_4, n_5, n_6, n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_16;
wire n_17, n_18, n_19, n_20, n_21, n_22, n_23, n_24;
wire n_25, n_26, n_27, n_28, n_29, n_30, n_31, n_32;
wire n_33, n_34, n_35, n_36, n_37, n_38, n_39, n_40;
wire n_41, n_42, n_43, n_44, n_45, n_46, n_47, n_48;
wire n_49, n_50, n_51, n_52, n_53, n_54, n_55, n_56;
wire n_57, n_58, n_59, n_60, n_61, n_63, n_64, n_65;
wire n_67, n_68, n_69, n_70, n_72, n_73, n_74, n_75;
wire n_76, n_78, n_79, n_80, n_81, n_82, n_83, n_84;
wire n_85, n_86, n_87, n_88, n_89, n_90, n_91, n_92;
wire n_93, n_94, n_95, n_96, n_97, n_98, n_99, n_100;
wire n_101, n_102, n_103, n_104, n_105, n_106, n_107, n_108;
wire n_109, n_111, n_112, n_113, n_114, n_116, n_117, n_118;
wire n_119, n_121, n_122, n_123, n_124, n_125, n_126, n_127;
wire n_128, n_129, n_130, n_131, n_132, n_133, n_134, n_135;
wire n_136, n_137, n_138, n_139, n_140, n_141, n_142, n_143;
wire n_144, n_145, n_146, n_147, n_148, n_149, n_150,
\reader_state[0] ;
wire \reader_state[1] , \rx_data[0] , \rx_data[1] , \rx_data[2] ,
\rx_data[3] , \rx_data[4] , \rx_data[5] , \rx_data[6] ;
wire \rx_data[7] , \rx_data[8] , \rx_data[9] , \rx_data[10] ,
\rx_data[11] , \rx_data[12] , \rx_data[13] , \rx_data[14] ;
wire \rx_data[15] , \rx_dataidx[0] , \rx_dataidx[1] , \rx_dataidx[2]
, \rx_dataidx[3] , \rx_dataidx[4] , \rx_dataidx[5] ,
\rx_dataidx[6] ;
wire \rx_dataidx[7] , \rx_dataidx[8] , \rx_dataidx[9] , rx_reset,
rx_timeout_180, tx_done, tx_go, tx_reader_running;
assign rx_timeout = 1'b0;
rfid_reader_rx U_RX(rx_reset, clk, tag_backscatter, UNCONNECTED3,
rx_timeout_180, 3'b000, 1'b0, 1'b0, 16'b0000000010000011,
16'b0000000000000000, 16'b0000000000000000, {UNCONNECTED4,
UNCONNECTED5, UNCONNECTED6, UNCONNECTED7, UNCONNECTED8,
UNCONNECTED9, UNCONNECTED10, UNCONNECTED11, UNCONNECTED12,
UNCONNECTED13, UNCONNECTED14, UNCONNECTED15, UNCONNECTED16,
UNCONNECTED17, UNCONNECTED18, UNCONNECTED19, UNCONNECTED20,
UNCONNECTED21, UNCONNECTED22, UNCONNECTED23, UNCONNECTED24,
UNCONNECTED25, UNCONNECTED26, UNCONNECTED27, UNCONNECTED28,
UNCONNECTED29, UNCONNECTED30, UNCONNECTED31, UNCONNECTED32,
UNCONNECTED33, UNCONNECTED34, UNCONNECTED35, UNCONNECTED36,
UNCONNECTED37, UNCONNECTED38, UNCONNECTED39, UNCONNECTED40,
UNCONNECTED41, UNCONNECTED42, UNCONNECTED43, UNCONNECTED44,
UNCONNECTED45, UNCONNECTED46, UNCONNECTED47, UNCONNECTED48,
UNCONNECTED49, UNCONNECTED50, UNCONNECTED51, UNCONNECTED52,
UNCONNECTED53, UNCONNECTED54, UNCONNECTED55, UNCONNECTED56,
UNCONNECTED57, UNCONNECTED58, UNCONNECTED59, UNCONNECTED60,
UNCONNECTED61, UNCONNECTED62, UNCONNECTED63, UNCONNECTED64,
UNCONNECTED65, UNCONNECTED66, UNCONNECTED67, UNCONNECTED68,
UNCONNECTED69, UNCONNECTED70, UNCONNECTED71, UNCONNECTED72,
UNCONNECTED73, UNCONNECTED74, UNCONNECTED75, UNCONNECTED76,
UNCONNECTED77, UNCONNECTED78, UNCONNECTED79, UNCONNECTED80,
UNCONNECTED81, UNCONNECTED82, UNCONNECTED83, UNCONNECTED84,
UNCONNECTED85, UNCONNECTED86, UNCONNECTED87, UNCONNECTED88,
UNCONNECTED89, UNCONNECTED90, UNCONNECTED91, UNCONNECTED92,
UNCONNECTED93, UNCONNECTED94, UNCONNECTED95, UNCONNECTED96,
UNCONNECTED97, UNCONNECTED98, UNCONNECTED99, UNCONNECTED100,
UNCONNECTED101, UNCONNECTED102, UNCONNECTED103, UNCONNECTED104,
UNCONNECTED105, UNCONNECTED106, UNCONNECTED107, UNCONNECTED108,
UNCONNECTED109, UNCONNECTED110, UNCONNECTED111, UNCONNECTED112,
UNCONNECTED113, UNCONNECTED114, UNCONNECTED115, UNCONNECTED116,
UNCONNECTED117, UNCONNECTED118, UNCONNECTED119, UNCONNECTED120,
UNCONNECTED121, UNCONNECTED122, UNCONNECTED123, UNCONNECTED124,
UNCONNECTED125, UNCONNECTED126, UNCONNECTED127, UNCONNECTED128,
UNCONNECTED129, UNCONNECTED130, UNCONNECTED131, UNCONNECTED132,
UNCONNECTED133, UNCONNECTED134, UNCONNECTED135, UNCONNECTED136,
UNCONNECTED137, UNCONNECTED138, UNCONNECTED139, UNCONNECTED140,
UNCONNECTED141, UNCONNECTED142, UNCONNECTED143, UNCONNECTED144,
UNCONNECTED145, UNCONNECTED146, UNCONNECTED147, UNCONNECTED148,
UNCONNECTED149, UNCONNECTED150, UNCONNECTED151, UNCONNECTED152,
UNCONNECTED153, UNCONNECTED154, UNCONNECTED155, UNCONNECTED156,
UNCONNECTED157, UNCONNECTED158, UNCONNECTED159, UNCONNECTED160,
UNCONNECTED161, UNCONNECTED162, UNCONNECTED163, UNCONNECTED164,
UNCONNECTED165, UNCONNECTED166, UNCONNECTED167, UNCONNECTED168,
UNCONNECTED169, UNCONNECTED170, UNCONNECTED171, UNCONNECTED172,
UNCONNECTED173, UNCONNECTED174, UNCONNECTED175, UNCONNECTED176,
UNCONNECTED177, UNCONNECTED178, UNCONNECTED179, UNCONNECTED180,
UNCONNECTED181, UNCONNECTED182, UNCONNECTED183, UNCONNECTED184,
UNCONNECTED185, UNCONNECTED186, UNCONNECTED187, UNCONNECTED188,
UNCONNECTED189, UNCONNECTED190, UNCONNECTED191, UNCONNECTED192,
UNCONNECTED193, UNCONNECTED194, UNCONNECTED195, UNCONNECTED196,
UNCONNECTED197, UNCONNECTED198, UNCONNECTED199, UNCONNECTED200,
UNCONNECTED201, UNCONNECTED202, UNCONNECTED203, UNCONNECTED204,
UNCONNECTED205, UNCONNECTED206, UNCONNECTED207, UNCONNECTED208,
UNCONNECTED209, UNCONNECTED210, UNCONNECTED211, UNCONNECTED212,
UNCONNECTED213, UNCONNECTED214, UNCONNECTED215, UNCONNECTED216,
UNCONNECTED217, UNCONNECTED218, UNCONNECTED219, UNCONNECTED220,
UNCONNECTED221, UNCONNECTED222, UNCONNECTED223, UNCONNECTED224,
UNCONNECTED225, UNCONNECTED226, UNCONNECTED227, UNCONNECTED228,
UNCONNECTED229, UNCONNECTED230, UNCONNECTED231, UNCONNECTED232,
UNCONNECTED233, UNCONNECTED234, UNCONNECTED235, UNCONNECTED236,
UNCONNECTED237, UNCONNECTED238, UNCONNECTED239, UNCONNECTED240,
UNCONNECTED241, UNCONNECTED242, UNCONNECTED243, UNCONNECTED244,
UNCONNECTED245, UNCONNECTED246, UNCONNECTED247, UNCONNECTED248,
UNCONNECTED249, UNCONNECTED250, UNCONNECTED251, UNCONNECTED252,
UNCONNECTED253, UNCONNECTED254, UNCONNECTED255, UNCONNECTED256,
UNCONNECTED257, UNCONNECTED258, UNCONNECTED259, UNCONNECTED260,
UNCONNECTED261, UNCONNECTED262, UNCONNECTED263, UNCONNECTED264,
UNCONNECTED265, UNCONNECTED266, UNCONNECTED267, UNCONNECTED268,
UNCONNECTED269, UNCONNECTED270, UNCONNECTED271, UNCONNECTED272,
UNCONNECTED273, UNCONNECTED274, UNCONNECTED275, UNCONNECTED276,
UNCONNECTED277, UNCONNECTED278, UNCONNECTED279, UNCONNECTED280,
UNCONNECTED281, UNCONNECTED282, UNCONNECTED283, UNCONNECTED284,
UNCONNECTED285, UNCONNECTED286, UNCONNECTED287, UNCONNECTED288,
UNCONNECTED289, UNCONNECTED290, UNCONNECTED291, UNCONNECTED292,
UNCONNECTED293, UNCONNECTED294, UNCONNECTED295, UNCONNECTED296,
UNCONNECTED297, UNCONNECTED298, UNCONNECTED299, UNCONNECTED300,
UNCONNECTED301, UNCONNECTED302, UNCONNECTED303, UNCONNECTED304,
UNCONNECTED305, UNCONNECTED306, UNCONNECTED307, UNCONNECTED308,
UNCONNECTED309, UNCONNECTED310, UNCONNECTED311, UNCONNECTED312,
UNCONNECTED313, UNCONNECTED314, UNCONNECTED315, UNCONNECTED316,
UNCONNECTED317, UNCONNECTED318, UNCONNECTED319, UNCONNECTED320,
UNCONNECTED321, UNCONNECTED322, UNCONNECTED323, UNCONNECTED324,
UNCONNECTED325, UNCONNECTED326, UNCONNECTED327, UNCONNECTED328,
UNCONNECTED329, UNCONNECTED330, UNCONNECTED331, UNCONNECTED332,
UNCONNECTED333, UNCONNECTED334, UNCONNECTED335, UNCONNECTED336,
UNCONNECTED337, UNCONNECTED338, UNCONNECTED339, UNCONNECTED340,
UNCONNECTED341, UNCONNECTED342, UNCONNECTED343, UNCONNECTED344,
UNCONNECTED345, UNCONNECTED346, UNCONNECTED347, UNCONNECTED348,
UNCONNECTED349, UNCONNECTED350, UNCONNECTED351, UNCONNECTED352,
UNCONNECTED353, UNCONNECTED354, UNCONNECTED355, UNCONNECTED356,
UNCONNECTED357, UNCONNECTED358, UNCONNECTED359, UNCONNECTED360,
UNCONNECTED361, UNCONNECTED362, UNCONNECTED363, UNCONNECTED364,
UNCONNECTED365, UNCONNECTED366, UNCONNECTED367, UNCONNECTED368,
UNCONNECTED369, UNCONNECTED370, UNCONNECTED371, UNCONNECTED372,
UNCONNECTED373, UNCONNECTED374, UNCONNECTED375, UNCONNECTED376,
UNCONNECTED377, UNCONNECTED378, UNCONNECTED379, UNCONNECTED380,
UNCONNECTED381, UNCONNECTED382, UNCONNECTED383, UNCONNECTED384,
UNCONNECTED385, UNCONNECTED386, UNCONNECTED387, UNCONNECTED388,
UNCONNECTED389, UNCONNECTED390, UNCONNECTED391, UNCONNECTED392,
UNCONNECTED393, UNCONNECTED394, UNCONNECTED395, UNCONNECTED396,
UNCONNECTED397, UNCONNECTED398, UNCONNECTED399, UNCONNECTED400,
UNCONNECTED401, UNCONNECTED402, UNCONNECTED403, UNCONNECTED404,
UNCONNECTED405, UNCONNECTED406, UNCONNECTED407, UNCONNECTED408,
UNCONNECTED409, UNCONNECTED410, UNCONNECTED411, UNCONNECTED412,
UNCONNECTED413, UNCONNECTED414, UNCONNECTED415, UNCONNECTED416,
UNCONNECTED417, UNCONNECTED418, UNCONNECTED419, UNCONNECTED420,
UNCONNECTED421, UNCONNECTED422, UNCONNECTED423, UNCONNECTED424,
UNCONNECTED425, UNCONNECTED426, UNCONNECTED427, UNCONNECTED428,
UNCONNECTED429, UNCONNECTED430, UNCONNECTED431, UNCONNECTED432,
UNCONNECTED433, UNCONNECTED434, UNCONNECTED435, UNCONNECTED436,
UNCONNECTED437, UNCONNECTED438, UNCONNECTED439, UNCONNECTED440,
UNCONNECTED441, UNCONNECTED442, UNCONNECTED443, UNCONNECTED444,
UNCONNECTED445, UNCONNECTED446, UNCONNECTED447, UNCONNECTED448,
UNCONNECTED449, UNCONNECTED450, UNCONNECTED451, UNCONNECTED452,
UNCONNECTED453, UNCONNECTED454, UNCONNECTED455, UNCONNECTED456,
UNCONNECTED457, UNCONNECTED458, UNCONNECTED459, UNCONNECTED460,
UNCONNECTED461, UNCONNECTED462, UNCONNECTED463, UNCONNECTED464,
UNCONNECTED465, UNCONNECTED466, UNCONNECTED467, UNCONNECTED468,
UNCONNECTED469, UNCONNECTED470, UNCONNECTED471, UNCONNECTED472,
UNCONNECTED473, UNCONNECTED474, UNCONNECTED475, UNCONNECTED476,
UNCONNECTED477, UNCONNECTED478, UNCONNECTED479, UNCONNECTED480,
UNCONNECTED481, UNCONNECTED482, UNCONNECTED483, UNCONNECTED484,
UNCONNECTED485, UNCONNECTED486, UNCONNECTED487, UNCONNECTED488,
UNCONNECTED489, UNCONNECTED490, UNCONNECTED491, UNCONNECTED492,
UNCONNECTED493, UNCONNECTED494, UNCONNECTED495, UNCONNECTED496,
UNCONNECTED497, UNCONNECTED498, UNCONNECTED499, UNCONNECTED500,
UNCONNECTED501, UNCONNECTED502, UNCONNECTED503, UNCONNECTED504,
UNCONNECTED505, UNCONNECTED506, UNCONNECTED507, UNCONNECTED508,
UNCONNECTED509, UNCONNECTED510, UNCONNECTED511, UNCONNECTED512,
UNCONNECTED513, UNCONNECTED514, UNCONNECTED515, UNCONNECTED516,
UNCONNECTED517, UNCONNECTED518, UNCONNECTED519, UNCONNECTED520,
UNCONNECTED521, UNCONNECTED522, UNCONNECTED523, UNCONNECTED524,
UNCONNECTED525, UNCONNECTED526, UNCONNECTED527, UNCONNECTED528,
UNCONNECTED529, UNCONNECTED530, UNCONNECTED531, UNCONNECTED532,
UNCONNECTED533, UNCONNECTED534, UNCONNECTED535, UNCONNECTED536,
UNCONNECTED537, UNCONNECTED538, UNCONNECTED539, UNCONNECTED540,
UNCONNECTED541, UNCONNECTED542, UNCONNECTED543, UNCONNECTED544,
UNCONNECTED545, UNCONNECTED546, UNCONNECTED547, UNCONNECTED548,
UNCONNECTED549, UNCONNECTED550, UNCONNECTED551, UNCONNECTED552,
UNCONNECTED553, UNCONNECTED554, UNCONNECTED555, UNCONNECTED556,
UNCONNECTED557, UNCONNECTED558, UNCONNECTED559, UNCONNECTED560,
UNCONNECTED561, UNCONNECTED562, UNCONNECTED563, UNCONNECTED564,
UNCONNECTED565, UNCONNECTED566, UNCONNECTED567, UNCONNECTED568,
UNCONNECTED569, UNCONNECTED570, UNCONNECTED571, UNCONNECTED572,
UNCONNECTED573, UNCONNECTED574, UNCONNECTED575, UNCONNECTED576,
UNCONNECTED577, UNCONNECTED578, UNCONNECTED579, UNCONNECTED580,
UNCONNECTED581, UNCONNECTED582, UNCONNECTED583, UNCONNECTED584,
UNCONNECTED585, UNCONNECTED586, UNCONNECTED587, UNCONNECTED588,
UNCONNECTED589, UNCONNECTED590, UNCONNECTED591, UNCONNECTED592,
UNCONNECTED593, UNCONNECTED594, UNCONNECTED595, UNCONNECTED596,
UNCONNECTED597, UNCONNECTED598, UNCONNECTED599, UNCONNECTED600,
UNCONNECTED601, UNCONNECTED602, UNCONNECTED603, UNCONNECTED604,
UNCONNECTED605, UNCONNECTED606, UNCONNECTED607, UNCONNECTED608,
UNCONNECTED609, UNCONNECTED610, UNCONNECTED611, UNCONNECTED612,
UNCONNECTED613, UNCONNECTED614, UNCONNECTED615, UNCONNECTED616,
UNCONNECTED617, UNCONNECTED618, UNCONNECTED619, UNCONNECTED620,
UNCONNECTED621, UNCONNECTED622, UNCONNECTED623, UNCONNECTED624,
UNCONNECTED625, UNCONNECTED626, UNCONNECTED627, UNCONNECTED628,
UNCONNECTED629, UNCONNECTED630, UNCONNECTED631, UNCONNECTED632,
UNCONNECTED633, UNCONNECTED634, UNCONNECTED635, UNCONNECTED636,
UNCONNECTED637, UNCONNECTED638, UNCONNECTED639, UNCONNECTED640,
UNCONNECTED641, UNCONNECTED642, UNCONNECTED643, UNCONNECTED644,
UNCONNECTED645, UNCONNECTED646, UNCONNECTED647, UNCONNECTED648,
UNCONNECTED649, UNCONNECTED650, UNCONNECTED651, UNCONNECTED652,
UNCONNECTED653, UNCONNECTED654, UNCONNECTED655, UNCONNECTED656,
UNCONNECTED657, UNCONNECTED658, UNCONNECTED659, UNCONNECTED660,
UNCONNECTED661, UNCONNECTED662, UNCONNECTED663, UNCONNECTED664,
UNCONNECTED665, UNCONNECTED666, UNCONNECTED667, UNCONNECTED668,
UNCONNECTED669, UNCONNECTED670, UNCONNECTED671, UNCONNECTED672,
UNCONNECTED673, UNCONNECTED674, UNCONNECTED675, UNCONNECTED676,
UNCONNECTED677, UNCONNECTED678, UNCONNECTED679, UNCONNECTED680,
UNCONNECTED681, UNCONNECTED682, UNCONNECTED683, UNCONNECTED684,
UNCONNECTED685, UNCONNECTED686, UNCONNECTED687, UNCONNECTED688,
UNCONNECTED689, UNCONNECTED690, UNCONNECTED691, UNCONNECTED692,
UNCONNECTED693, UNCONNECTED694, UNCONNECTED695, UNCONNECTED696,
UNCONNECTED697, UNCONNECTED698, UNCONNECTED699, UNCONNECTED700,
UNCONNECTED701, UNCONNECTED702, UNCONNECTED703, UNCONNECTED704,
UNCONNECTED705, UNCONNECTED706, UNCONNECTED707, UNCONNECTED708,
UNCONNECTED709, UNCONNECTED710, UNCONNECTED711, UNCONNECTED712,
UNCONNECTED713, UNCONNECTED714, UNCONNECTED715, UNCONNECTED716,
UNCONNECTED717, UNCONNECTED718, UNCONNECTED719, UNCONNECTED720,
UNCONNECTED721, UNCONNECTED722, UNCONNECTED723, UNCONNECTED724,
UNCONNECTED725, UNCONNECTED726, UNCONNECTED727, UNCONNECTED728,
UNCONNECTED729, UNCONNECTED730, UNCONNECTED731, UNCONNECTED732,
UNCONNECTED733, UNCONNECTED734, UNCONNECTED735, UNCONNECTED736,
UNCONNECTED737, UNCONNECTED738, UNCONNECTED739, UNCONNECTED740,
UNCONNECTED741, UNCONNECTED742, UNCONNECTED743, UNCONNECTED744,
UNCONNECTED745, UNCONNECTED746, UNCONNECTED747, UNCONNECTED748,
UNCONNECTED749, UNCONNECTED750, UNCONNECTED751, UNCONNECTED752,
UNCONNECTED753, UNCONNECTED754, UNCONNECTED755, UNCONNECTED756,
UNCONNECTED757, UNCONNECTED758, UNCONNECTED759, UNCONNECTED760,
UNCONNECTED761, UNCONNECTED762, UNCONNECTED763, UNCONNECTED764,
UNCONNECTED765, UNCONNECTED766, UNCONNECTED767, UNCONNECTED768,
UNCONNECTED769, UNCONNECTED770, UNCONNECTED771, UNCONNECTED772,
UNCONNECTED773, UNCONNECTED774, UNCONNECTED775, UNCONNECTED776,
UNCONNECTED777, UNCONNECTED778, UNCONNECTED779, UNCONNECTED780,
UNCONNECTED781, UNCONNECTED782, UNCONNECTED783, UNCONNECTED784,
UNCONNECTED785, UNCONNECTED786, UNCONNECTED787, UNCONNECTED788,
UNCONNECTED789, UNCONNECTED790, UNCONNECTED791, UNCONNECTED792,
UNCONNECTED793, UNCONNECTED794, UNCONNECTED795, UNCONNECTED796,
UNCONNECTED797, UNCONNECTED798, UNCONNECTED799, UNCONNECTED800,
UNCONNECTED801, UNCONNECTED802, UNCONNECTED803, UNCONNECTED804,
UNCONNECTED805, UNCONNECTED806, UNCONNECTED807, UNCONNECTED808,
UNCONNECTED809, UNCONNECTED810, UNCONNECTED811, UNCONNECTED812,
UNCONNECTED813, UNCONNECTED814, UNCONNECTED815, UNCONNECTED816,
UNCONNECTED817, UNCONNECTED818, UNCONNECTED819, UNCONNECTED820,
UNCONNECTED821, UNCONNECTED822, UNCONNECTED823, UNCONNECTED824,
UNCONNECTED825, UNCONNECTED826, UNCONNECTED827, UNCONNECTED828,
UNCONNECTED829, UNCONNECTED830, UNCONNECTED831, UNCONNECTED832,
UNCONNECTED833, UNCONNECTED834, UNCONNECTED835, UNCONNECTED836,
UNCONNECTED837, UNCONNECTED838, UNCONNECTED839, UNCONNECTED840,
UNCONNECTED841, UNCONNECTED842, UNCONNECTED843, UNCONNECTED844,
UNCONNECTED845, UNCONNECTED846, UNCONNECTED847, UNCONNECTED848,
UNCONNECTED849, UNCONNECTED850, UNCONNECTED851, UNCONNECTED852,
UNCONNECTED853, UNCONNECTED854, UNCONNECTED855, UNCONNECTED856,
UNCONNECTED857, UNCONNECTED858, UNCONNECTED859, UNCONNECTED860,
UNCONNECTED861, UNCONNECTED862, UNCONNECTED863, UNCONNECTED864,
UNCONNECTED865, UNCONNECTED866, UNCONNECTED867, UNCONNECTED868,
UNCONNECTED869, UNCONNECTED870, UNCONNECTED871, UNCONNECTED872,
UNCONNECTED873, UNCONNECTED874, UNCONNECTED875, UNCONNECTED876,
UNCONNECTED877, UNCONNECTED878, UNCONNECTED879, UNCONNECTED880,
UNCONNECTED881, UNCONNECTED882, UNCONNECTED883, UNCONNECTED884,
UNCONNECTED885, UNCONNECTED886, UNCONNECTED887, UNCONNECTED888,
UNCONNECTED889, UNCONNECTED890, UNCONNECTED891, UNCONNECTED892,
UNCONNECTED893, UNCONNECTED894, UNCONNECTED895, UNCONNECTED896,
UNCONNECTED897, UNCONNECTED898, UNCONNECTED899, UNCONNECTED900,
UNCONNECTED901, UNCONNECTED902, UNCONNECTED903, UNCONNECTED904,
UNCONNECTED905, UNCONNECTED906, UNCONNECTED907, UNCONNECTED908,
UNCONNECTED909, UNCONNECTED910, UNCONNECTED911, UNCONNECTED912,
UNCONNECTED913, UNCONNECTED914, UNCONNECTED915, UNCONNECTED916,
UNCONNECTED917, UNCONNECTED918, UNCONNECTED919, UNCONNECTED920,
UNCONNECTED921, UNCONNECTED922, UNCONNECTED923, UNCONNECTED924,
UNCONNECTED925, UNCONNECTED926, UNCONNECTED927, UNCONNECTED928,
UNCONNECTED929, UNCONNECTED930, UNCONNECTED931, UNCONNECTED932,
UNCONNECTED933, UNCONNECTED934, UNCONNECTED935, UNCONNECTED936,
UNCONNECTED937, UNCONNECTED938, UNCONNECTED939, UNCONNECTED940,
UNCONNECTED941, UNCONNECTED942, UNCONNECTED943, UNCONNECTED944,
UNCONNECTED945, UNCONNECTED946, UNCONNECTED947, UNCONNECTED948,
UNCONNECTED949, UNCONNECTED950, UNCONNECTED951, UNCONNECTED952,
UNCONNECTED953, UNCONNECTED954, UNCONNECTED955, UNCONNECTED956,
UNCONNECTED957, UNCONNECTED958, UNCONNECTED959, UNCONNECTED960,
UNCONNECTED961, UNCONNECTED962, UNCONNECTED963, UNCONNECTED964,
UNCONNECTED965, UNCONNECTED966, UNCONNECTED967, UNCONNECTED968,
UNCONNECTED969, UNCONNECTED970, UNCONNECTED971, UNCONNECTED972,
UNCONNECTED973, UNCONNECTED974, UNCONNECTED975, UNCONNECTED976,
UNCONNECTED977, UNCONNECTED978, UNCONNECTED979, UNCONNECTED980,
UNCONNECTED981, UNCONNECTED982, UNCONNECTED983, UNCONNECTED984,
UNCONNECTED985, UNCONNECTED986, UNCONNECTED987, UNCONNECTED988,
UNCONNECTED989, UNCONNECTED990, UNCONNECTED991, UNCONNECTED992,
UNCONNECTED993, UNCONNECTED994, UNCONNECTED995, UNCONNECTED996,
UNCONNECTED997, UNCONNECTED998, UNCONNECTED999, UNCONNECTED1000,
UNCONNECTED1001, UNCONNECTED1002, UNCONNECTED1003,
UNCONNECTED1004, UNCONNECTED1005, UNCONNECTED1006,
UNCONNECTED1007, UNCONNECTED1008, UNCONNECTED1009,
UNCONNECTED1010, UNCONNECTED1011, \rx_data[15] , \rx_data[14] ,
\rx_data[13] , \rx_data[12] , \rx_data[11] , \rx_data[10] ,
\rx_data[9] , \rx_data[8] , \rx_data[7] , \rx_data[6] ,
\rx_data[5] , \rx_data[4] , \rx_data[3] , \rx_data[2] ,
\rx_data[1] , \rx_data[0] }, {\rx_dataidx[9] , \rx_dataidx[8] ,
\rx_dataidx[7] , \rx_dataidx[6] , \rx_dataidx[5] ,
\rx_dataidx[4] , \rx_dataidx[3] , \rx_dataidx[2] ,
\rx_dataidx[1] , \rx_dataidx[0] });
rfid_reader_tx U_TX(reset, clk, reader_modulation, tx_done,
tx_reader_running, tx_go, n_100, 16'b0000000001110101,
16'b0000000000000111, 16'b0000000010000011,
16'b0000000010111100, 16'b0000000000101001, {3'b000, n_111,
n_119, n_116, n_118},
{79'b0000000000000000000000000000000000000000000000000000000000000000000000000000000,
n_104, 8'b00000000, n_101, n_109, 3'b000, n_114, 1'b0, n_117,
n_103, n_102, n_150, n_149, n_148, n_147, n_146, n_145, n_144,
n_143, n_142, n_141, n_140, n_139, n_138, n_137, n_136, n_135,
n_134, n_133, n_132, n_131, n_130, n_129, n_128, n_127, n_126,
n_125, n_124, n_123, n_122, n_121});
inv1x_bc g1806(.in0 (n_107), .out0 (n_101));
inv1x_bc g1805(.in0 (n_106), .out0 (n_100));
nand4_dc g2096(.in0 (n_99), .in1 (n_90), .in2 (n_95), .in3 (n_97),
.out0 (rx_packet_complete));
aoi2bb1_bbbe g2097(.A0N (n_107), .A1N (n_70), .B0 (n_98), .Y (n_99));
nand4_dc g2098(.in0 (n_96), .in1 (n_80), .in2 (n_78), .in3 (n_63),
.out0 (n_98));
nand3_cc g2099(.in0 (n_84), .in1 (n_106), .in2 (n_97), .out0 (n_127));
nand3b_bbcc g2107(.AN (n_104), .B (n_88), .C (n_106), .Y (n_116));
inv1x_bc g2101(.in0 (n_94), .out0 (n_129));
oai21_bdbc g2100(.in0 (n_76), .in1 (\rx_dataidx[6] ), .in2 (n_104),
.out0 (n_96));
inv1x_bc g2103(.in0 (n_93), .out0 (n_126));
oai2bb1_bbbc g2105(.A0N (tx_handle[7]), .A1N (n_86), .B0 (n_97), .Y
(n_128));
nand2_bc g2121(.in0 (n_95), .in1 (n_108), .out0 (n_118));
aoi21_bdbd g2102(.in0 (n_92), .in1 (tx_handle[8]), .in2 (n_91), .out0
(n_94));
aoi21_bdbd g2104(.in0 (n_92), .in1 (tx_handle[5]), .in2 (n_91), .out0
(n_93));
inv1x_bc g2125(.in0 (n_83), .out0 (n_103));
inv1x_bc g2127(.in0 (n_82), .out0 (n_102));
oai2bb1_bbbc g2106(.A0N (n_105), .A1N (n_108), .B0 (n_79), .Y (n_90));
oai2bb1_bbbc g2129(.A0N (tx_handle[5]), .A1N (n_89), .B0 (n_106), .Y
(n_142));
oai2bb1_bbbc g2130(.A0N (tx_handle[0]), .A1N (n_89), .B0 (n_88), .Y
(n_137));
and2_bbcd g2108(.A (n_87), .B (tx_handle[15]), .Y (n_136));
and2_bbcd g2109(.A (n_87), .B (tx_handle[14]), .Y (n_135));
and2_bbcd g2115(.A (n_85), .B (tx_handle[12]), .Y (n_133));
and2_bbcd g2111(.A (n_86), .B (tx_handle[11]), .Y (n_132));
and2_bbcd g2113(.A (n_92), .B (tx_handle[13]), .Y (n_134));
and2_bbcd g2114(.A (n_85), .B (tx_handle[9]), .Y (n_130));
and2_bbcd g2112(.A (n_87), .B (tx_handle[10]), .Y (n_131));
and2_bbcd g2117(.A (n_85), .B (tx_handle[4]), .Y (n_125));
and2_bbcd g2110(.A (n_86), .B (tx_handle[3]), .Y (n_124));
and2_bbcd g2118(.A (n_85), .B (tx_handle[2]), .Y (n_123));
and2_bbcd g2119(.A (n_87), .B (tx_handle[1]), .Y (n_122));
and2_bbcd g2120(.A (n_92), .B (tx_handle[0]), .Y (n_121));
nand2_bc g2116(.in0 (n_86), .in1 (tx_handle[6]), .out0 (n_84));
nor2_bd g2156(.in0 (n_75), .in1 (n_72), .out0 (n_104));
aoi21_bdbd g2126(.in0 (n_81), .in1 (tx_handle[15]), .in2 (n_114),
.out0 (n_83));
aoi21_bdbd g2128(.in0 (n_81), .in1 (tx_handle[14]), .in2 (n_114),
.out0 (n_82));
and2_bbcd g2139(.A (n_89), .B (tx_handle[6]), .Y (n_143));
and2_bbcd g2131(.A (n_89), .B (tx_handle[12]), .Y (n_149));
and2_bbcd g2132(.A (n_89), .B (tx_handle[11]), .Y (n_148));
and2_bbcd g2134(.A (n_89), .B (tx_handle[10]), .Y (n_147));
and2_bbcd g2137(.A (n_89), .B (tx_handle[8]), .Y (n_145));
nand2_bc g2136(.in0 (n_89), .in1 (n_72), .out0 (n_107));
and2_bbcd g2140(.A (n_89), .B (tx_handle[4]), .Y (n_141));
and2_bbcd g2142(.A (n_89), .B (tx_handle[3]), .Y (n_140));
and2_bbcd g2146(.A (n_89), .B (tx_handle[1]), .Y (n_138));
nand2b_bbbc g2123(.AN (n_106), .B (n_79), .Y (n_80));
and2_bbcd g2135(.A (n_89), .B (tx_handle[9]), .Y (n_146));
and2_bbcd g2133(.A (n_81), .B (tx_handle[7]), .Y (n_144));
nor2_bd g2157(.in0 (n_89), .in1 (send_packet_type[0]), .out0 (n_119));
aoi21_bdbd g2124(.in0 (n_69), .in1 (\rx_dataidx[6] ), .in2
(\rx_dataidx[8] ), .out0 (n_78));
and2_bbcd g2143(.A (n_89), .B (tx_handle[2]), .Y (n_139));
inv1x_bc g2152(.in0 (n_114), .out0 (n_95));
or2_bbcd g2158(.A (n_89), .B (n_109), .Y (n_117));
and2_bbcd g2155(.A (n_89), .B (tx_handle[13]), .Y (n_150));
inv1x_bc g2144(.in0 (n_91), .out0 (n_108));
inv1x_bc g2147(.in0 (n_88), .out0 (n_92));
aoi21_bdbd g2122(.in0 (n_65), .in1 (n_64), .in2 (n_68), .out0 (n_76));
inv1x_bc g2148(.in0 (n_88), .out0 (n_86));
inv1x_bc g2149(.in0 (n_88), .out0 (n_85));
inv1x_bc g2150(.in0 (n_88), .out0 (n_87));
nor2b_bbbd g2153(.AN (n_109), .B (send_packet_type[1]), .Y (n_114));
aoi21_bdbd g2159(.in0 (n_113), .in1 (n_112), .in2 (reader_done),
.out0 (reader_running));
inv1x_bc g2163(.in0 (n_75), .out0 (n_81));
nor2_bd g2145(.in0 (n_74), .in1 (send_packet_type[2]), .out0 (n_91));
nand2_bc g2154(.in0 (n_74), .in1 (n_67), .out0 (n_111));
nand2_bc g2151(.in0 (n_73), .in1 (send_packet_type[0]), .out0 (n_88));
nand2_bc g2141(.in0 (n_73), .in1 (n_72), .out0 (n_105));
nand3_cc g2160(.in0 (send_packet_type[1]), .in1 (n_67), .in2 (n_72),
.out0 (n_106));
nand2b_bbbc g2138(.AN (\rx_dataidx[4] ), .B (n_70), .Y (n_79));
or3_bccd g2161(.A (send_packet_type[1]), .B (n_67), .C (n_72), .Y
(n_97));
inv1x_bc g2165(.in0 (n_89), .out0 (n_75));
inv1x_bc g2171(.in0 (n_68), .out0 (n_69));
nor2_bd g2175(.in0 (send_packet_type[0]), .in1 (n_67), .out0 (n_109));
and2_bbcd g2166(.A (send_packet_type[1]), .B (send_packet_type[2]),
.Y (n_89));
nor2_bd g2167(.in0 (send_packet_type[1]), .in1 (send_packet_type[2]),
.out0 (n_73));
nor2_bd g2170(.in0 (\rx_dataidx[2] ), .in1 (\rx_dataidx[3] ), .out0
(n_65));
nor2_bd g2173(.in0 (\rx_dataidx[6] ), .in1 (\rx_dataidx[5] ), .out0
(n_70));
nand2_bc g2174(.in0 (send_packet_type[1]), .in1
(send_packet_type[0]), .out0 (n_74));
nor2_bd g2168(.in0 (\rx_dataidx[0] ), .in1 (\rx_dataidx[1] ), .out0
(n_64));
nand2_bc g2172(.in0 (\rx_dataidx[4] ), .in1 (\rx_dataidx[5] ), .out0
(n_68));
nor2_bd g2169(.in0 (\rx_dataidx[9] ), .in1 (\rx_dataidx[7] ), .out0
(n_63));
inv1x_bc g2180(.in0 (send_packet_type[0]), .out0 (n_72));
inv1x_bc g2177(.in0 (\reader_state[1] ), .out0 (n_113));
inv1x_bc g2179(.in0 (send_packet_type[2]), .out0 (n_67));
inv1x_bc g2176(.in0 (\reader_state[0] ), .out0 (n_112));
ffrhq_x2 \handlein_reg[0] (.RN (n_61), .CK (clk), .D (n_53), .Q
(rx_handle[15]));
ffrhq_x2 \handlein_reg[10] (.RN (n_61), .CK (clk), .D (n_46), .Q
(rx_handle[5]));
ffrhq_x2 \handlein_reg[11] (.RN (n_61), .CK (clk), .D (n_54), .Q
(rx_handle[4]));
ffrhq_x2 \handlein_reg[12] (.RN (n_61), .CK (clk), .D (n_55), .Q
(rx_handle[3]));
ffrhq_x2 \handlein_reg[13] (.RN (n_61), .CK (clk), .D (n_49), .Q
(rx_handle[2]));
ffrhq_x2 \handlein_reg[14] (.RN (n_61), .CK (clk), .D (n_47), .Q
(rx_handle[1]));
ffrhq_x2 \handlein_reg[15] (.RN (n_61), .CK (clk), .D (n_44), .Q
(rx_handle[0]));
ffrhq_x2 \handlein_reg[1] (.RN (n_61), .CK (clk), .D (n_43), .Q
(rx_handle[14]));
ffrhq_x2 \handlein_reg[2] (.RN (n_61), .CK (clk), .D (n_60), .Q
(rx_handle[13]));
ffrhq_x2 \handlein_reg[3] (.RN (n_61), .CK (clk), .D (n_52), .Q
(rx_handle[12]));
ffrhq_x2 \handlein_reg[4] (.RN (n_61), .CK (clk), .D (n_50), .Q
(rx_handle[11]));
ffrhq_x2 \handlein_reg[5] (.RN (n_61), .CK (clk), .D (n_48), .Q
(rx_handle[10]));
ffrhq_x2 \handlein_reg[6] (.RN (n_61), .CK (clk), .D (n_56), .Q
(rx_handle[9]));
ffrhq_x2 \handlein_reg[7] (.RN (n_61), .CK (clk), .D (n_51), .Q
(rx_handle[8]));
ffrhq_x2 \handlein_reg[8] (.RN (n_61), .CK (clk), .D (n_45), .Q
(rx_handle[7]));
ffrhq_x2 \handlein_reg[9] (.RN (n_61), .CK (clk), .D (n_59), .Q
(rx_handle[6]));
ffhq_x2 tx_go_reg(.CK (clk), .D (n_58), .Q (tx_go));
inv1x_bc g1911(.in0 (n_24), .out0 (n_60));
inv1x_bc g1929(.in0 (n_23), .out0 (n_59));
oai2bb2_bbbdbc g1931(.A0N (tx_go), .A1N (n_57), .B0 (n_57), .B1
(n_13), .Y (n_58));
inv1x_bc g1921(.in0 (n_38), .out0 (n_56));
inv1x_bc g1901(.in0 (n_36), .out0 (n_55));
inv1x_bc g1899(.in0 (n_42), .out0 (n_54));
inv1x_bc g1915(.in0 (n_31), .out0 (n_53));
inv1x_bc g1913(.in0 (n_39), .out0 (n_52));
inv1x_bc g1923(.in0 (n_28), .out0 (n_51));
inv1x_bc g1917(.in0 (n_29), .out0 (n_50));
inv1x_bc g1903(.in0 (n_34), .out0 (n_49));
inv1x_bc g1919(.in0 (n_41), .out0 (n_48));
inv1x_bc g1905(.in0 (n_33), .out0 (n_47));
inv1x_bc g1927(.in0 (n_25), .out0 (n_46));
inv1x_bc g1925(.in0 (n_26), .out0 (n_45));
inv1x_bc g1907(.in0 (n_22), .out0 (n_44));
inv1x_bc g1909(.in0 (n_27), .out0 (n_43));
aoi22_bdbd g1900(.in0 (n_35), .in1 (rx_handle[4]), .in2 (n_40), .in3
(\rx_data[11] ), .out0 (n_42));
aoi22_bdbd g1920(.in0 (n_37), .in1 (rx_handle[10]), .in2 (n_40), .in3
(\rx_data[5] ), .out0 (n_41));
aoi22_bdbd g1914(.in0 (n_30), .in1 (rx_handle[12]), .in2 (n_40), .in3
(\rx_data[3] ), .out0 (n_39));
aoi22_bdbd g1922(.in0 (n_37), .in1 (rx_handle[9]), .in2 (n_40), .in3
(\rx_data[6] ), .out0 (n_38));
aoi22_bdbd g1902(.in0 (n_35), .in1 (rx_handle[3]), .in2 (n_40), .in3
(\rx_data[12] ), .out0 (n_36));
aoi22_bdbd g1904(.in0 (n_32), .in1 (rx_handle[2]), .in2 (n_40), .in3
(\rx_data[13] ), .out0 (n_34));
aoi22_bdbd g1906(.in0 (n_32), .in1 (rx_handle[1]), .in2 (n_40), .in3
(\rx_data[14] ), .out0 (n_33));
aoi22_bdbd g1916(.in0 (n_30), .in1 (rx_handle[15]), .in2 (n_40), .in3
(\rx_data[0] ), .out0 (n_31));
aoi22_bdbd g1918(.in0 (n_30), .in1 (rx_handle[11]), .in2 (n_40), .in3
(\rx_data[4] ), .out0 (n_29));
aoi22_bdbd g1924(.in0 (n_35), .in1 (rx_handle[8]), .in2 (n_40), .in3
(\rx_data[7] ), .out0 (n_28));
ffrhq_x2 reader_done_reg(.RN (n_61), .CK (clk), .D (n_21), .Q
(reader_done));
aoi22_bdbd g1910(.in0 (n_37), .in1 (rx_handle[14]), .in2 (n_40), .in3
(\rx_data[1] ), .out0 (n_27));
aoi22_bdbd g1926(.in0 (n_35), .in1 (rx_handle[7]), .in2 (n_40), .in3
(\rx_data[8] ), .out0 (n_26));
aoi22_bdbd g1928(.in0 (n_32), .in1 (rx_handle[5]), .in2 (n_40), .in3
(\rx_data[10] ), .out0 (n_25));
aoi22_bdbd g1912(.in0 (n_30), .in1 (rx_handle[13]), .in2 (n_40), .in3
(\rx_data[2] ), .out0 (n_24));
aoi22_bdbd g1930(.in0 (n_32), .in1 (rx_handle[6]), .in2 (n_40), .in3
(\rx_data[9] ), .out0 (n_23));
aoi22_bdbd g1908(.in0 (n_37), .in1 (rx_handle[0]), .in2 (n_40), .in3
(\rx_data[15] ), .out0 (n_22));
ffrhq_x2 \reader_state_reg[0] (.RN (n_61), .CK (clk), .D (n_19), .Q
(\reader_state[0] ));
ffrhq_x2 \reader_state_reg[1] (.RN (n_61), .CK (clk), .D (n_18), .Q
(\reader_state[1] ));
oai2bb2_bbbdbc g1934(.A0N (reader_done), .A1N (n_20), .B0 (n_20), .B1
(n_11), .Y (n_21));
aoi21_bdbd g1936(.in0 (n_7), .in1 (tx_done), .in2 (n_14), .out0
(n_57));
oai2bb1_bbbc g1932(.A0N (\reader_state[0] ), .A1N (n_17), .B0 (n_10),
.Y (n_19));
oai2bb2_bbbdbc g1933(.A0N (\reader_state[1] ), .A1N (n_17), .B0
(n_6), .B1 (n_12), .Y (n_18));
inv1x_bc g1939(.in0 (n_16), .out0 (n_35));
inv1x_bc g1940(.in0 (n_16), .out0 (n_32));
inv1x_bc g1941(.in0 (n_16), .out0 (n_30));
ffrhq_x2 rx_reset_reg(.RN (n_61), .CK (clk), .D (n_9), .Q (rx_reset));
inv1x_bd g1937(.in0 (n_37), .out0 (n_40));
inv1x_bc g1942(.in0 (n_37), .out0 (n_16));
inv1x_bc g1945(.in0 (n_13), .out0 (n_14));
nand3b_bbcc g1943(.AN (n_4), .B (rx_packet_complete), .C (n_2), .Y
(n_37));
nand2_bc g1946(.in0 (n_3), .in1 (n_12), .out0 (n_13));
and2_bbcd g1947(.A (n_11), .B (n_10), .Y (n_20));
nor3b_bbbe g1944(.AN (n_1), .B (n_5), .C (n_8), .Y (n_17));
oai2bb2_bbbdbc g1948(.A0N (rx_reset), .A1N (n_8), .B0 (n_8), .B1
(\reader_state[1] ), .Y (n_9));
nor2_bd g1949(.in0 (n_6), .in1 (reset), .out0 (n_7));
nand2_bc g1950(.in0 (n_5), .in1 (n_113), .out0 (n_10));
nand2b_bbbc g1951(.AN (n_4), .B (rx_timeout_180), .Y (n_11));
nor3_be g1952(.in0 (n_6), .in1 (tx_reader_running), .in2 (reset),
.out0 (n_3));
nand4_dc g1953(.in0 (n_107), .in1 (n_108), .in2 (n_105), .in3
(n_106), .out0 (n_2));
nand2_bc g1954(.in0 (\reader_state[1] ), .in1 (n_112), .out0 (n_4));
nand2_bc g1955(.in0 (\reader_state[0] ), .in1 (tx_done), .out0 (n_1));
nand2_bc g1956(.in0 (\reader_state[0] ), .in1 (n_113), .out0 (n_6));
nor2_bd g1957(.in0 (n_112), .in1 (n_113), .out0 (n_8));
nor2b_bbbd g1958(.AN (start_tx), .B (\reader_state[0] ), .Y (n_5));
inv1x_bc g1959(.in0 (tx_done), .out0 (n_12));
inv1x_bc g1961(.in0 (reset), .out0 (n_61));
endmodule
module increment_unsigned(A, CI, Z);
input [15:0] A;
input CI;
output [16:0] Z;
wire [15:0] A;
wire CI;
wire [16:0] Z;
wire n_0, n_2, n_4, n_6, n_8, n_10, n_12, n_14;
wire n_16, n_18, n_20, n_22, n_24, n_26;
assign Z[0] = 1'b0;
assign Z[16] = 1'b0;
xor2pa_bbbbbbbcbd g46(.A (A[15]), .B (n_26), .Y (Z[15]));
addh_bbbcbcbcbbbd g47(.A (n_24), .B (A[14]), .CO (n_26), .S (Z[14]));
addh_bbbcbcbcbbbd g48(.A (n_22), .B (A[13]), .CO (n_24), .S (Z[13]));
addh_bbbcbcbcbbbd g49(.A (n_20), .B (A[12]), .CO (n_22), .S (Z[12]));
addh_bbbcbcbcbbbd g50(.A (n_18), .B (A[11]), .CO (n_20), .S (Z[11]));
addh_bbbcbcbcbbbd g51(.A (n_16), .B (A[10]), .CO (n_18), .S (Z[10]));
addh_bbbcbcbcbbbd g52(.A (n_14), .B (A[9]), .CO (n_16), .S (Z[9]));
addh_bbbcbcbcbbbd g53(.A (n_12), .B (A[8]), .CO (n_14), .S (Z[8]));
addh_bbbcbcbcbbbd g54(.A (n_10), .B (A[7]), .CO (n_12), .S (Z[7]));
addh_bbbcbcbcbbbd g55(.A (n_8), .B (A[6]), .CO (n_10), .S (Z[6]));
addh_bbbcbcbcbbbd g56(.A (n_6), .B (A[5]), .CO (n_8), .S (Z[5]));
addh_bbbcbcbcbbbd g57(.A (n_4), .B (A[4]), .CO (n_6), .S (Z[4]));
addh_bbbcbcbcbbbd g58(.A (n_2), .B (A[3]), .CO (n_4), .S (Z[3]));
addh_bbbcbcbcbbbd g59(.A (n_0), .B (A[2]), .CO (n_2), .S (Z[2]));
addh_bbbcbcbcbbbd g60(.A (A[1]), .B (A[0]), .CO (n_0), .S (Z[1]));
endmodule
module rfid_reader(reset, clk, tag_backscatter, reader_modulation);
input reset, clk, tag_backscatter;
output reader_modulation;
wire reset, clk, tag_backscatter;
wire reader_modulation;
wire UNCONNECTED1012, UNCONNECTED1013, UNCONNECTED1014, \counter[0] ,
\counter[1] , \counter[2] , \counter[3] , \counter[4] ;
wire \counter[5] , \counter[6] , \counter[7] , \counter[8] ,
\counter[9] , \counter[10] , \counter[11] , \counter[12] ;
wire \counter[13] , \counter[14] , \counter[15] , n_1, n_3, n_5, n_6,
n_7;
wire n_8, n_9, n_10, n_11, n_12, n_13, n_14, n_15;
wire n_16, n_17, n_19, n_20, n_21, n_22, n_23, n_24;
wire n_25, n_26, n_27, n_28, n_29, n_30, n_31, n_32;
wire n_33, n_34, n_35, n_37, n_38, n_39, n_40, n_41;
wire n_42, n_43, n_44, n_45, n_46, n_47, n_48, n_49;
wire n_50, n_51, n_52, n_53, n_54, n_55, n_56, n_57;
wire n_58, n_59, n_60, n_61, n_62, n_63, n_64, n_65;
wire n_66, n_67, n_68, n_69, n_70, n_71, n_72, n_73;
wire n_74, n_75, n_76, n_77, n_78, n_79, n_80, n_81;
wire n_82, n_83, n_84, n_85, n_86, n_87, n_88, n_89;
wire n_90, n_91, n_92, n_93, n_95, n_96, n_97, n_98;
wire n_99, n_100, n_101, n_102, n_103, n_104, n_105, n_106;
wire n_107, n_108, n_109, n_110, n_111, n_112, n_114, n_115;
wire n_116, n_117, n_118, n_119, n_120, n_121, n_122, n_123;
wire n_124, n_125, n_126, n_127, n_128, n_129, n_130, n_131;
wire n_132, n_133, n_134, n_135, n_136, n_137, n_138, n_139;
wire n_140, n_141, n_142, n_143, n_144, n_145, n_146, n_147;
wire n_148, n_149, n_150, n_151, n_152, n_153, n_154, reader_done;
wire reader_running, \reader_state[0] , \reader_state[1] ,
\reader_state[2] , \rx_handle[0] , \rx_handle[1] , \rx_handle[2]
, \rx_handle[3] ;
wire \rx_handle[4] , \rx_handle[5] , \rx_handle[6] , \rx_handle[7] ,
\rx_handle[8] , \rx_handle[9] , \rx_handle[10] , \rx_handle[11] ;
wire \rx_handle[12] , \rx_handle[13] , \rx_handle[14] ,
\rx_handle[15] , rx_packet_complete, \send_packet_type[0] ,
\send_packet_type[1] , \send_packet_type[2] ;
wire start_tx, started, \tx_handle[0] , \tx_handle[1] , \tx_handle[2]
, \tx_handle[3] , \tx_handle[4] , \tx_handle[5] ;
wire \tx_handle[6] , \tx_handle[7] , \tx_handle[8] , \tx_handle[9] ,
\tx_handle[10] , \tx_handle[11] , \tx_handle[12] ,
\tx_handle[13] ;
wire \tx_handle[14] , \tx_handle[15] ;
rfid_reader_packet_rxtx UREADER(reset, clk, tag_backscatter,
reader_modulation, 3'b000, 1'b0, 1'b0, 16'b0001100001101010,
16'b0110000110101000, 4'b0010, 3'b000, 2'b00, 1'b0, 2'b00,
{1'b0, \send_packet_type[2] , \send_packet_type[1] ,
\send_packet_type[0] }, start_tx, reader_done, UNCONNECTED1012,
rx_packet_complete, reader_running, {\tx_handle[15] ,
\tx_handle[14] , \tx_handle[13] , \tx_handle[12] ,
\tx_handle[11] , \tx_handle[10] , \tx_handle[9] , \tx_handle[8]
, \tx_handle[7] , \tx_handle[6] , \tx_handle[5] , \tx_handle[4]
, \tx_handle[3] , \tx_handle[2] , \tx_handle[1] , \tx_handle[0]
}, {\rx_handle[15] , \rx_handle[14] , \rx_handle[13] ,
\rx_handle[12] , \rx_handle[11] , \rx_handle[10] , \rx_handle[9]
, \rx_handle[8] , \rx_handle[7] , \rx_handle[6] , \rx_handle[5]
, \rx_handle[4] , \rx_handle[3] , \rx_handle[2] , \rx_handle[1]
, \rx_handle[0] });
increment_unsigned inc_add_135_32(.A ({\counter[15] , \counter[14] ,
\counter[13] , \counter[12] , \counter[11] , \counter[10] ,
\counter[9] , \counter[8] , \counter[7] , \counter[6] ,
\counter[5] , \counter[4] , \counter[3] , \counter[2] ,
\counter[1] , \counter[0] }), .CI (1'b1), .Z ({UNCONNECTED1013,
n_140, n_141, n_142, n_143, n_144, n_145, n_146, n_147, n_148,
n_149, n_150, n_151, n_152, n_153, n_154, UNCONNECTED1014}));
ffrhq_x2 \counter_reg[10] (.RN (n_139), .CK (clk), .D (n_138), .Q
(\counter[10] ));
ffrhq_x2 \counter_reg[11] (.RN (n_139), .CK (clk), .D (n_137), .Q
(\counter[11] ));
ffrhq_x2 \counter_reg[12] (.RN (n_139), .CK (clk), .D (n_134), .Q
(\counter[12] ));
ffrhq_x2 \counter_reg[13] (.RN (n_139), .CK (clk), .D (n_135), .Q
(\counter[13] ));
ffrhq_x2 \counter_reg[14] (.RN (n_139), .CK (clk), .D (n_133), .Q
(\counter[14] ));
ffrhq_x2 \counter_reg[15] (.RN (n_139), .CK (clk), .D (n_131), .Q
(\counter[15] ));
ffrhq_x2 \counter_reg[1] (.RN (n_139), .CK (clk), .D (n_129), .Q
(\counter[1] ));
ffrhq_x2 \counter_reg[2] (.RN (n_139), .CK (clk), .D (n_132), .Q
(\counter[2] ));
ffrhq_x2 \counter_reg[3] (.RN (n_139), .CK (clk), .D (n_130), .Q
(\counter[3] ));
ffrhq_x2 \counter_reg[4] (.RN (n_139), .CK (clk), .D (n_128), .Q
(\counter[4] ));
ffrhq_x2 \counter_reg[5] (.RN (n_139), .CK (clk), .D (n_125), .Q
(\counter[5] ));
ffrhq_x2 \counter_reg[6] (.RN (n_139), .CK (clk), .D (n_127), .Q
(\counter[6] ));
ffrhq_x2 \counter_reg[7] (.RN (n_139), .CK (clk), .D (n_126), .Q
(\counter[7] ));
ffrhq_x2 \counter_reg[8] (.RN (n_139), .CK (clk), .D (n_124), .Q
(\counter[8] ));
ffrhq_x2 \counter_reg[9] (.RN (n_139), .CK (clk), .D (n_136), .Q
(\counter[9] ));
ffrhq_x2 started_reg(.RN (n_139), .CK (clk), .D (n_123), .Q
(started));
ffrhq_x2 \counter_reg[0] (.RN (n_139), .CK (clk), .D (n_122), .Q
(\counter[0] ));
inv1x_bc g1893(.in0 (n_108), .out0 (n_138));
inv1x_bc g1895(.in0 (n_106), .out0 (n_137));
inv1x_bc g1891(.in0 (n_109), .out0 (n_136));
inv1x_bc g1897(.in0 (n_105), .out0 (n_135));
inv1x_bc g1899(.in0 (n_104), .out0 (n_134));
inv1x_bc g1901(.in0 (n_103), .out0 (n_133));
inv1x_bc g1875(.in0 (n_119), .out0 (n_132));
inv1x_bc g1903(.in0 (n_102), .out0 (n_131));
inv1x_bc g1877(.in0 (n_121), .out0 (n_130));
ffrhq_x2 \reader_state_reg[0] (.RN (n_139), .CK (clk), .D (n_101), .Q
(\reader_state[0] ));
inv1x_bc g1879(.in0 (n_117), .out0 (n_129));
inv1x_bc g1881(.in0 (n_116), .out0 (n_128));
inv1x_bc g1885(.in0 (n_114), .out0 (n_127));
inv1x_bc g1887(.in0 (n_112), .out0 (n_126));
inv1x_bc g1883(.in0 (n_115), .out0 (n_125));
inv1x_bc g1889(.in0 (n_111), .out0 (n_124));
or2_bbcd g1873(.A (n_100), .B (n_91), .Y (n_123));
oai2bb2_bbbdbc g1906(.A0N (\counter[0] ), .A1N (n_120), .B0 (n_95),
.B1 (\counter[0] ), .Y (n_122));
aoi22_bdbd g1878(.in0 (n_118), .in1 (n_152), .in2 (n_120), .in3
(\counter[3] ), .out0 (n_121));
aoi22_bdbd g1876(.in0 (n_118), .in1 (n_153), .in2 (n_120), .in3
(\counter[2] ), .out0 (n_119));
aoi22_bdbd g1880(.in0 (n_118), .in1 (n_154), .in2 (n_120), .in3
(\counter[1] ), .out0 (n_117));
aoi22_bdbd g1882(.in0 (n_110), .in1 (n_151), .in2 (n_120), .in3
(\counter[4] ), .out0 (n_116));
aoi22_bdbd g1884(.in0 (n_118), .in1 (n_150), .in2 (n_120), .in3
(\counter[5] ), .out0 (n_115));
aoi22_bdbd g1886(.in0 (n_118), .in1 (n_149), .in2 (n_120), .in3
(\counter[6] ), .out0 (n_114));
aoi22_bdbd g1888(.in0 (n_118), .in1 (n_148), .in2 (n_120), .in3
(\counter[7] ), .out0 (n_112));
aoi22_bdbd g1890(.in0 (n_110), .in1 (n_147), .in2 (n_120), .in3
(\counter[8] ), .out0 (n_111));
aoi22_bdbd g1892(.in0 (n_107), .in1 (n_146), .in2 (n_120), .in3
(\counter[9] ), .out0 (n_109));
aoi22_bdbd g1894(.in0 (n_145), .in1 (n_107), .in2 (n_120), .in3
(\counter[10] ), .out0 (n_108));
aoi22_bdbd g1896(.in0 (n_144), .in1 (n_107), .in2 (n_120), .in3
(\counter[11] ), .out0 (n_106));
aoi22_bdbd g1898(.in0 (n_142), .in1 (n_118), .in2 (n_120), .in3
(\counter[13] ), .out0 (n_105));
aoi22_bdbd g1900(.in0 (n_143), .in1 (n_107), .in2 (n_120), .in3
(\counter[12] ), .out0 (n_104));
aoi22_bdbd g1902(.in0 (n_141), .in1 (n_110), .in2 (n_120), .in3
(\counter[14] ), .out0 (n_103));
aoi22_bdbd g1904(.in0 (n_140), .in1 (n_110), .in2 (n_120), .in3
(\counter[15] ), .out0 (n_102));
oai21_bdbc g1907(.in0 (n_21), .in1 (n_23), .in2 (n_99), .out0
(n_101));
oai22_bdbd g1905(.in0 (n_96), .in1 (n_26), .in2 (n_98), .in3 (n_84),
.out0 (n_100));
or2_bbcd g1909(.A (n_93), .B (n_97), .Y (n_120));
aoi21_bdbd g1910(.in0 (n_89), .in1 (n_90), .in2 (n_85), .out0 (n_99));
ffrhq_x2 \reader_state_reg[1] (.RN (n_139), .CK (clk), .D (n_88), .Q
(\reader_state[1] ));
oai21_bdbc g1908(.in0 (n_92), .in1 (n_97), .in2 (n_96), .out0 (n_98));
inv1x_bc g1914(.in0 (n_95), .out0 (n_110));
inv1x_bc g1915(.in0 (n_95), .out0 (n_107));
inv1x_bc g1916(.in0 (n_95), .out0 (n_118));
ffrhq_x2 \reader_state_reg[2] (.RN (n_139), .CK (clk), .D (n_87), .Q
(\reader_state[2] ));
nor2_bd g1911(.in0 (n_92), .in1 (n_91), .out0 (n_93));
nand2_bc g1917(.in0 (n_92), .in1 (n_90), .out0 (n_95));
ffrhq_x2 \tx_handle_reg[15] (.RN (n_139), .CK (clk), .D (n_79), .Q
(\tx_handle[15] ));
ffrhq_x2 \tx_handle_reg[0] (.RN (n_139), .CK (clk), .D (n_70), .Q
(\tx_handle[0] ));
ffrhq_x2 \tx_handle_reg[11] (.RN (n_139), .CK (clk), .D (n_68), .Q
(\tx_handle[11] ));
ffrhq_x2 \tx_handle_reg[8] (.RN (n_139), .CK (clk), .D (n_73), .Q
(\tx_handle[8] ));
ffrhq_x2 \tx_handle_reg[3] (.RN (n_139), .CK (clk), .D (n_83), .Q
(\tx_handle[3] ));
ffrhq_x2 \tx_handle_reg[10] (.RN (n_139), .CK (clk), .D (n_69), .Q
(\tx_handle[10] ));
ffrhq_x2 \tx_handle_reg[12] (.RN (n_139), .CK (clk), .D (n_67), .Q
(\tx_handle[12] ));
ffrhq_x2 \tx_handle_reg[13] (.RN (n_139), .CK (clk), .D (n_81), .Q
(\tx_handle[13] ));
ffrhq_x2 \tx_handle_reg[6] (.RN (n_139), .CK (clk), .D (n_75), .Q
(\tx_handle[6] ));
ffrhq_x2 \tx_handle_reg[1] (.RN (n_139), .CK (clk), .D (n_78), .Q
(\tx_handle[1] ));
ffrhq_x2 \tx_handle_reg[2] (.RN (n_139), .CK (clk), .D (n_72), .Q
(\tx_handle[2] ));
ffrhq_x2 \tx_handle_reg[7] (.RN (n_139), .CK (clk), .D (n_74), .Q
(\tx_handle[7] ));
ffrhq_x2 \tx_handle_reg[5] (.RN (n_139), .CK (clk), .D (n_76), .Q
(\tx_handle[5] ));
ffrhq_x2 \tx_handle_reg[4] (.RN (n_139), .CK (clk), .D (n_77), .Q
(\tx_handle[4] ));
ffrhq_x2 \tx_handle_reg[14] (.RN (n_139), .CK (clk), .D (n_80), .Q
(\tx_handle[14] ));
ffrhq_x2 \tx_handle_reg[9] (.RN (n_139), .CK (clk), .D (n_71), .Q
(\tx_handle[9] ));
inv1x_bc g1918(.in0 (n_92), .out0 (n_89));
oai21_bdbc g1942(.in0 (n_86), .in1 (n_15), .in2 (n_82), .out0 (n_88));
nor3b_bbbe g1919(.AN (n_66), .B (\counter[9] ), .C (\counter[10] ),
.Y (n_92));
oai21_bdbc g1940(.in0 (n_86), .in1 (n_7), .in2 (n_33), .out0 (n_87));
oai22_bdbd g1941(.in0 (n_86), .in1 (n_30), .in2 (n_29), .in3 (n_84),
.out0 (n_85));
inv1x_bc g1955(.in0 (n_58), .out0 (n_83));
oai21_bdbc g1944(.in0 (n_13), .in1 (n_16), .in2 (n_86), .out0 (n_82));
inv1x_bc g1945(.in0 (n_60), .out0 (n_81));
inv1x_bc g1947(.in0 (n_62), .out0 (n_80));
inv1x_bc g1949(.in0 (n_65), .out0 (n_79));
inv1x_bc g1951(.in0 (n_59), .out0 (n_78));
inv1x_bc g1957(.in0 (n_57), .out0 (n_77));
inv1x_bc g1959(.in0 (n_55), .out0 (n_76));
inv1x_bc g1961(.in0 (n_54), .out0 (n_75));
inv1x_bc g1963(.in0 (n_52), .out0 (n_74));
inv1x_bc g1965(.in0 (n_50), .out0 (n_73));
inv1x_bc g1953(.in0 (n_64), .out0 (n_72));
inv1x_bc g1967(.in0 (n_49), .out0 (n_71));
inv1x_bc g1969(.in0 (n_48), .out0 (n_70));
inv1x_bc g1971(.in0 (n_47), .out0 (n_69));
inv1x_bc g1973(.in0 (n_46), .out0 (n_68));
inv1x_bc g1975(.in0 (n_45), .out0 (n_67));
ffrhq_x2 start_tx_reg(.RN (n_139), .CK (clk), .D (n_44), .Q
(start_tx));
nor3_be g1920(.in0 (n_43), .in1 (\counter[12] ), .in2 (\counter[11]
), .out0 (n_66));
aoi22_bdbd g1950(.in0 (n_61), .in1 (\tx_handle[15] ), .in2 (n_63),
.in3 (\rx_handle[15] ), .out0 (n_65));
aoi22_bdbd g1954(.in0 (n_51), .in1 (\tx_handle[2] ), .in2 (n_63),
.in3 (\rx_handle[2] ), .out0 (n_64));
aoi22_bdbd g1948(.in0 (n_61), .in1 (\tx_handle[14] ), .in2 (n_63),
.in3 (\rx_handle[14] ), .out0 (n_62));
aoi22_bdbd g1946(.in0 (n_61), .in1 (\tx_handle[13] ), .in2 (n_63),
.in3 (\rx_handle[13] ), .out0 (n_60));
aoi22_bdbd g1952(.in0 (n_56), .in1 (\tx_handle[1] ), .in2 (n_63),
.in3 (\rx_handle[1] ), .out0 (n_59));
aoi22_bdbd g1956(.in0 (n_53), .in1 (\tx_handle[3] ), .in2 (n_63),
.in3 (\rx_handle[3] ), .out0 (n_58));
aoi22_bdbd g1958(.in0 (n_56), .in1 (\tx_handle[4] ), .in2 (n_63),
.in3 (\rx_handle[4] ), .out0 (n_57));
aoi22_bdbd g1960(.in0 (n_56), .in1 (\tx_handle[5] ), .in2 (n_63),
.in3 (\rx_handle[5] ), .out0 (n_55));
aoi22_bdbd g1962(.in0 (n_53), .in1 (\tx_handle[6] ), .in2 (n_63),
.in3 (\rx_handle[6] ), .out0 (n_54));
aoi22_bdbd g1964(.in0 (n_51), .in1 (\tx_handle[7] ), .in2 (n_63),
.in3 (\rx_handle[7] ), .out0 (n_52));
aoi22_bdbd g1966(.in0 (n_61), .in1 (\tx_handle[8] ), .in2 (n_63),
.in3 (\rx_handle[8] ), .out0 (n_50));
aoi22_bdbd g1968(.in0 (n_53), .in1 (\tx_handle[9] ), .in2 (n_63),
.in3 (\rx_handle[9] ), .out0 (n_49));
aoi22_bdbd g1970(.in0 (n_56), .in1 (\tx_handle[0] ), .in2 (n_63),
.in3 (\rx_handle[0] ), .out0 (n_48));
aoi22_bdbd g1972(.in0 (n_51), .in1 (\tx_handle[10] ), .in2 (n_63),
.in3 (\rx_handle[10] ), .out0 (n_47));
aoi22_bdbd g1974(.in0 (n_51), .in1 (\tx_handle[11] ), .in2 (n_63),
.in3 (\rx_handle[11] ), .out0 (n_46));
aoi22_bdbd g1976(.in0 (n_53), .in1 (\tx_handle[12] ), .in2 (n_63),
.in3 (\rx_handle[12] ), .out0 (n_45));
ffrhq_x2 \send_packet_type_reg[1] (.RN (n_139), .CK (clk), .D (n_37),
.Q (\send_packet_type[1] ));
ffrhq_x2 \send_packet_type_reg[0] (.RN (n_139), .CK (clk), .D (n_40),
.Q (\send_packet_type[0] ));
ffrhq_x2 \send_packet_type_reg[2] (.RN (n_139), .CK (clk), .D (n_38),
.Q (\send_packet_type[2] ));
nor3b_bbbe g1981(.AN (n_97), .B (n_35), .C (n_5), .Y (n_86));
oai21_bdbc g1982(.in0 (n_28), .in1 (started), .in2 (n_42), .out0
(n_44));
nand4bb_bbbbdc g1923(.AN (\counter[14] ), .BN (\counter[15] ), .C
(n_34), .D (n_3), .Y (n_43));
oai21_bdbc g1998(.in0 (n_12), .in1 (reader_done), .in2 (n_25), .out0
(n_96));
oai21_bdbc g1983(.in0 (n_39), .in1 (started), .in2 (start_tx), .out0
(n_42));
inv1x_bc g1985(.in0 (n_41), .out0 (n_56));
inv1x_bc g1986(.in0 (n_41), .out0 (n_53));
inv1x_bc g1987(.in0 (n_41), .out0 (n_51));
oai2bb2_bbbdbc g1991(.A0N (\send_packet_type[0] ), .A1N (n_39), .B0
(n_39), .B1 (n_14), .Y (n_40));
oai2bb1_bbbc g1992(.A0N (\send_packet_type[2] ), .A1N (n_39), .B0
(n_20), .Y (n_38));
oai2bb2_bbbdbc g1994(.A0N (\send_packet_type[1] ), .A1N (n_39), .B0
(n_39), .B1 (\reader_state[1] ), .Y (n_37));
inv1x_bc g1989(.in0 (n_61), .out0 (n_41));
inv1x_bd g1984(.in0 (n_61), .out0 (n_63));
nor2_bd g1995(.in0 (n_39), .in1 (reader_done), .out0 (n_35));
nand3_cc g1980(.in0 (n_22), .in1 (\counter[7] ), .in2 (\counter[8] ),
.out0 (n_34));
nor3_be g1990(.in0 (n_32), .in1 (n_31), .in2 (n_17), .out0 (n_61));
aoi22_bdbd g1993(.in0 (n_32), .in1 (\reader_state[0] ), .in2 (n_31),
.in3 (n_30), .out0 (n_33));
nand3_cc g1997(.in0 (n_19), .in1 (n_27), .in2 (reader_done), .out0
(n_29));
aoi2bb2_bbbdbd g1999(.A0N (reader_running), .A1N (n_24), .B0 (n_27),
.B1 (n_26), .Y (n_28));
inv1x_bc g2001(.in0 (n_39), .out0 (n_25));
nor2b_bbbd g2002(.AN (n_24), .B (n_27), .Y (n_39));
oai2bb1_bbbc g2007(.A0N (n_11), .A1N (n_24), .B0 (n_9), .Y (n_23));
nor2_bd g2004(.in0 (n_97), .in1 (started), .out0 (n_91));
nand4bb_bbbbdc g1996(.AN (\counter[4] ), .BN (\counter[5] ), .C
(n_6), .D (n_1), .Y (n_22));
nor2_bd g2000(.in0 (n_21), .in1 (n_20), .out0 (n_31));
nor3_be g2003(.in0 (n_21), .in1 (\reader_state[2] ), .in2 (n_15),
.out0 (n_32));
nor3_be g2006(.in0 (n_8), .in1 (\reader_state[1] ), .in2
(\reader_state[0] ), .out0 (n_90));
aoi21_bdbd g2012(.in0 (rx_packet_complete), .in1 (\reader_state[1] ),
.in2 (n_10), .out0 (n_19));
oai21_bdbc g2014(.in0 (\reader_state[2] ), .in1 (n_15), .in2 (n_20),
.out0 (n_27));
nor2_bd g2005(.in0 (n_21), .in1 (n_24), .out0 (n_17));
nand2_bc g2008(.in0 (n_16), .in1 (n_15), .out0 (n_97));
or2_bbcd g2009(.A (n_13), .B (n_30), .Y (n_14));
inv1x_bc g2016(.in0 (n_26), .out0 (n_12));
inv1x_bc g2019(.in0 (n_10), .out0 (n_11));
inv1x_bc g2023(.in0 (n_8), .out0 (n_9));
nand2_bc g2017(.in0 (reader_running), .in1 (n_84), .out0 (n_26));
nor2_bd g2020(.in0 (\reader_state[0] ), .in1 (n_15), .out0 (n_10));
nand2_bc g2021(.in0 (\reader_state[0] ), .in1 (n_15), .out0 (n_24));
nand2_bc g2022(.in0 (\reader_state[2] ), .in1 (n_15), .out0 (n_20));
nand2_bc g2024(.in0 (started), .in1 (n_7), .out0 (n_8));
aoi21_bdbd g2010(.in0 (\counter[1] ), .in1 (\counter[2] ), .in2
(\counter[6] ), .out0 (n_6));
aoi21_bdbd g2011(.in0 (\reader_state[1] ), .in1 (\reader_state[2] ),
.in2 (started), .out0 (n_5));
nand3_cc g2013(.in0 (rx_packet_complete), .in1 (started), .in2
(reader_done), .out0 (n_21));
nor2_bd g2015(.in0 (\reader_state[2] ), .in1 (\reader_state[0] ),
.out0 (n_16));
nor2_bd g2018(.in0 (\reader_state[1] ), .in1 (\reader_state[2] ),
.out0 (n_13));
inv1x_bc g2030(.in0 (\counter[13] ), .out0 (n_3));
inv1x_bc g2025(.in0 (\reader_state[0] ), .out0 (n_30));
inv1x_bc g2031(.in0 (\counter[3] ), .out0 (n_1));
inv1x_bc g2032(.in0 (reset), .out0 (n_139));
inv1x_bc g2033(.in0 (\reader_state[1] ), .out0 (n_15));
inv1x_bc g2027(.in0 (\reader_state[2] ), .out0 (n_7));
inv1x_bc g2028(.in0 (started), .out0 (n_84));
endmodule
|
module premuat3(
inverse,
i_transize,
i_0 ,
i_1 ,
i_2 ,
i_3 ,
i_4 ,
i_5 ,
i_6 ,
i_7 ,
i_8 ,
i_9 ,
i_10,
i_11,
i_12,
i_13,
i_14,
i_15,
i_16,
i_17,
i_18,
i_19,
i_20,
i_21,
i_22,
i_23,
i_24,
i_25,
i_26,
i_27,
i_28,
i_29,
i_30,
i_31,
o_0 ,
o_1 ,
o_2 ,
o_3 ,
o_4 ,
o_5 ,
o_6 ,
o_7 ,
o_8 ,
o_9 ,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
// ****************************************************************
//
// INPUT / OUTPUT DECLARATION
//
// ****************************************************************
input inverse;
input [1:0] i_transize;
input signed [27:0] i_0 ;
input signed [27:0] i_1 ;
input signed [27:0] i_2 ;
input signed [27:0] i_3 ;
input signed [27:0] i_4 ;
input signed [27:0] i_5 ;
input signed [27:0] i_6 ;
input signed [27:0] i_7 ;
input signed [27:0] i_8 ;
input signed [27:0] i_9 ;
input signed [27:0] i_10;
input signed [27:0] i_11;
input signed [27:0] i_12;
input signed [27:0] i_13;
input signed [27:0] i_14;
input signed [27:0] i_15;
input signed [27:0] i_16;
input signed [27:0] i_17;
input signed [27:0] i_18;
input signed [27:0] i_19;
input signed [27:0] i_20;
input signed [27:0] i_21;
input signed [27:0] i_22;
input signed [27:0] i_23;
input signed [27:0] i_24;
input signed [27:0] i_25;
input signed [27:0] i_26;
input signed [27:0] i_27;
input signed [27:0] i_28;
input signed [27:0] i_29;
input signed [27:0] i_30;
input signed [27:0] i_31;
output signed [27:0] o_0 ;
output signed [27:0] o_1 ;
output signed [27:0] o_2 ;
output signed [27:0] o_3 ;
output signed [27:0] o_4 ;
output signed [27:0] o_5 ;
output signed [27:0] o_6 ;
output signed [27:0] o_7 ;
output signed [27:0] o_8 ;
output signed [27:0] o_9 ;
output signed [27:0] o_10;
output signed [27:0] o_11;
output signed [27:0] o_12;
output signed [27:0] o_13;
output signed [27:0] o_14;
output signed [27:0] o_15;
output signed [27:0] o_16;
output signed [27:0] o_17;
output signed [27:0] o_18;
output signed [27:0] o_19;
output signed [27:0] o_20;
output signed [27:0] o_21;
output signed [27:0] o_22;
output signed [27:0] o_23;
output signed [27:0] o_24;
output signed [27:0] o_25;
output signed [27:0] o_26;
output signed [27:0] o_27;
output signed [27:0] o_28;
output signed [27:0] o_29;
output signed [27:0] o_30;
output signed [27:0] o_31;
// ****************************************************************
//
// WIRE DECLARATION
//
// ****************************************************************
wire enable_80;
wire enable_81;
wire enable_82;
wire enable_160;
wire enable_161;
wire enable_320;
wire signed [27:0] in_0;
wire signed [27:0] in_1;
wire signed [27:0] in_2;
wire signed [27:0] in_3;
wire signed [27:0] in_4;
wire signed [27:0] in_5;
wire signed [27:0] in_6;
wire signed [27:0] in_7;
wire signed [27:0] in_8;
wire signed [27:0] in_9;
wire signed [27:0] in_10;
wire signed [27:0] in_11;
wire signed [27:0] in_12;
wire signed [27:0] in_13;
wire signed [27:0] in_14;
wire signed [27:0] in_15;
wire signed [27:0] in_16;
wire signed [27:0] in_17;
wire signed [27:0] in_18;
wire signed [27:0] in_19;
wire signed [27:0] in_20;
wire signed [27:0] in_21;
wire signed [27:0] in_22;
wire signed [27:0] in_23;
wire signed [27:0] in_24;
wire signed [27:0] in_25;
wire signed [27:0] in_26;
wire signed [27:0] in_27;
wire signed [27:0] in_28;
wire signed [27:0] in_29;
wire signed [27:0] in_30;
wire signed [27:0] in_31;
wire signed [27:0] o8_0;
wire signed [27:0] o8_1;
wire signed [27:0] o8_2;
wire signed [27:0] o8_3;
wire signed [27:0] o8_4;
wire signed [27:0] o8_5;
wire signed [27:0] o8_6;
wire signed [27:0] o8_7;
wire signed [27:0] o8_8;
wire signed [27:0] o8_9;
wire signed [27:0] o8_10;
wire signed [27:0] o8_11;
wire signed [27:0] o8_12;
wire signed [27:0] o8_13;
wire signed [27:0] o8_14;
wire signed [27:0] o8_15;
wire signed [27:0] o8_16;
wire signed [27:0] o8_17;
wire signed [27:0] o8_18;
wire signed [27:0] o8_19;
wire signed [27:0] o8_20;
wire signed [27:0] o8_21;
wire signed [27:0] o8_22;
wire signed [27:0] o8_23;
wire signed [27:0] o8_24;
wire signed [27:0] o8_25;
wire signed [27:0] o8_26;
wire signed [27:0] o8_27;
wire signed [27:0] o8_28;
wire signed [27:0] o8_29;
wire signed [27:0] o8_30;
wire signed [27:0] o8_31;
wire signed [27:0] o16_0;
wire signed [27:0] o16_1;
wire signed [27:0] o16_2;
wire signed [27:0] o16_3;
wire signed [27:0] o16_4;
wire signed [27:0] o16_5;
wire signed [27:0] o16_6;
wire signed [27:0] o16_7;
wire signed [27:0] o16_8;
wire signed [27:0] o16_9;
wire signed [27:0] o16_10;
wire signed [27:0] o16_11;
wire signed [27:0] o16_12;
wire signed [27:0] o16_13;
wire signed [27:0] o16_14;
wire signed [27:0] o16_15;
wire signed [27:0] o16_16;
wire signed [27:0] o16_17;
wire signed [27:0] o16_18;
wire signed [27:0] o16_19;
wire signed [27:0] o16_20;
wire signed [27:0] o16_21;
wire signed [27:0] o16_22;
wire signed [27:0] o16_23;
wire signed [27:0] o16_24;
wire signed [27:0] o16_25;
wire signed [27:0] o16_26;
wire signed [27:0] o16_27;
wire signed [27:0] o16_28;
wire signed [27:0] o16_29;
wire signed [27:0] o16_30;
wire signed [27:0] o16_31;
// ********************************************
//
// Combinational Logic
//
// ********************************************
assign enable_80=(i_transize[1]||i_transize[0]);
assign enable_81=((~i_transize[1])&i_transize[0]);
assign enable_82=(enable_81||enable_161);
assign enable_160=i_transize[1];
assign enable_161=((~i_transize[0])&i_transize[1]);
assign enable_320=(i_transize[1]&i_transize[0]);
assign in_0=inverse?'b0:i_0;
assign in_1=inverse?'b0:i_1;
assign in_2=inverse?'b0:i_2;
assign in_3=inverse?'b0:i_3;
assign in_4=inverse?'b0:i_4;
assign in_5=inverse?'b0:i_5;
assign in_6=inverse?'b0:i_6;
assign in_7=inverse?'b0:i_7;
assign in_8=inverse?'b0:i_8;
assign in_9=inverse?'b0:i_9;
assign in_10=inverse?'b0:i_10;
assign in_11=inverse?'b0:i_11;
assign in_12=inverse?'b0:i_12;
assign in_13=inverse?'b0:i_13;
assign in_14=inverse?'b0:i_14;
assign in_15=inverse?'b0:i_15;
assign in_16=inverse?'b0:i_16;
assign in_17=inverse?'b0:i_17;
assign in_18=inverse?'b0:i_18;
assign in_19=inverse?'b0:i_19;
assign in_20=inverse?'b0:i_20;
assign in_21=inverse?'b0:i_21;
assign in_22=inverse?'b0:i_22;
assign in_23=inverse?'b0:i_23;
assign in_24=inverse?'b0:i_24;
assign in_25=inverse?'b0:i_25;
assign in_26=inverse?'b0:i_26;
assign in_27=inverse?'b0:i_27;
assign in_28=inverse?'b0:i_28;
assign in_29=inverse?'b0:i_29;
assign in_30=inverse?'b0:i_30;
assign in_31=inverse?'b0:i_31;
// ********************************************
//
// Sub Modules
//
// ********************************************
premuat3_8 p3_80(
enable_80,
inverse,
in_0,
in_1,
in_2,
in_3,
in_4,
in_5,
in_6,
in_7,
o8_0,
o8_1,
o8_2,
o8_3,
o8_4,
o8_5,
o8_6,
o8_7
);
premuat3_8 p3_81(
enable_81,
inverse,
in_8 ,
in_9 ,
in_10,
in_11,
in_12,
in_13,
in_14,
in_15,
o8_8 ,
o8_9 ,
o8_10,
o8_11,
o8_12,
o8_13,
o8_14,
o8_15
);
premuat3_8 p3_82(
enable_82,
inverse,
in_16,
in_17,
in_18,
in_19,
in_20,
in_21,
in_22,
in_23,
o8_16,
o8_17,
o8_18,
o8_19,
o8_20,
o8_21,
o8_22,
o8_23
);
premuat3_8 p3_83(
enable_81,
inverse,
in_24,
in_25,
in_26,
in_27,
in_28,
in_29,
in_30,
in_31,
o8_24,
o8_25,
o8_26,
o8_27,
o8_28,
o8_29,
o8_30,
o8_31
);
premuat3_16 p3_160(
enable_160,
inverse,
o8_0,
o8_1,
o8_2,
o8_3,
o8_4,
o8_5,
o8_6,
o8_7,
o8_8,
o8_9 ,
o8_10,
o8_11,
o8_12,
o8_13,
o8_14,
o8_15,
o16_0,
o16_1,
o16_2,
o16_3,
o16_4,
o16_5,
o16_6,
o16_7,
o16_8,
o16_9,
o16_10,
o16_11,
o16_12,
o16_13,
o16_14,
o16_15
);
premuat3_16 p3_161(
enable_161,
inverse,
o8_16,
o8_17,
o8_18,
o8_19,
o8_20,
o8_21,
o8_22,
o8_23,
o8_24,
o8_25,
o8_26,
o8_27,
o8_28,
o8_29,
o8_30,
o8_31,
o16_16,
o16_17,
o16_18,
o16_19,
o16_20,
o16_21,
o16_22,
o16_23,
o16_24,
o16_25,
o16_26,
o16_27,
o16_28,
o16_29,
o16_30,
o16_31
);
premuat3_32 p3_320(
enable_320,
inverse,
o16_0 ,
o16_1 ,
o16_2 ,
o16_3 ,
o16_4 ,
o16_5 ,
o16_6 ,
o16_7 ,
o16_8 ,
o16_9 ,
o16_10,
o16_11,
o16_12,
o16_13,
o16_14,
o16_15,
o16_16,
o16_17,
o16_18,
o16_19,
o16_20,
o16_21,
o16_22,
o16_23,
o16_24,
o16_25,
o16_26,
o16_27,
o16_28,
o16_29,
o16_30,
o16_31,
o_0 ,
o_1 ,
o_2 ,
o_3 ,
o_4 ,
o_5 ,
o_6 ,
o_7 ,
o_8 ,
o_9 ,
o_10,
o_11,
o_12,
o_13,
o_14,
o_15,
o_16,
o_17,
o_18,
o_19,
o_20,
o_21,
o_22,
o_23,
o_24,
o_25,
o_26,
o_27,
o_28,
o_29,
o_30,
o_31
);
endmodule |
(*
* Copyright 2019 Jade Philipoom
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*)
Require Import Coq.Lists.List.
Require Import Coq.Arith.PeanoNat.
Require Import Hafnium.Util.List.
Require Import Hafnium.Util.Tactics.
Import ListNotations.
(*** High-level model : describes the abstract state of the Hafnium system ***)
Section Abstract.
(* Assume a type of addresses, and that their equality is decidable. The
addresses are in Hafnium's address space (physical addresses, if Hafnium
runs on bare metal). All addresses in this type are assumed to be aligned to
the page size; they're really more like "page addresses". *)
Context {addr : Type}
{addr_eq_dec : forall a1 a2 : addr, {a1 = a2} + {a1 <> a2}}.
(* assume a type of unique identifier for VMs, and that equality between VM ids
is decidable *)
Context {vm_id : Type}
{vm_id_eq_dec : forall id1 id2 : vm_id, {id1 = id2} + {id1 <> id2}}.
(* set the unique identifier for Hafnium to the [unit] type; since there is
only one member of this type (called [tt]), there is only one id for
Hafnium itself.*)
Definition hafnium_id : Type := unit.
Definition hid : hafnium_id := tt.
(* an entity is either a VM or Hafnium ("+" means "or") *)
Definition entity_id : Type := vm_id + hafnium_id.
(* boilerplate: convert vm_ids and hafnium_id to entity_id if needed *)
Local Definition inl_entity : vm_id -> entity_id := @inl vm_id hafnium_id.
Local Definition inr_entity : hafnium_id -> entity_id := @inr vm_id hafnium_id.
Local Coercion inl_entity : vm_id >-> entity_id.
Local Coercion inr_entity : hafnium_id >-> entity_id.
Hint Unfold inl_entity inr_entity.
Set Printing Coercions.
(* boilerplate: decidability for the entity_id type *)
Definition entity_id_eq_dec (i1 i2 : entity_id) : {i1 = i2} + {i1 <> i2}.
Proof.
destruct i1, i2;
repeat match goal with
| _ => progress subst
| _ => right; congruence
| _ => left; congruence
| x : hafnium_id |- _ => destruct x
| |- {inl ?v1 = inl ?v2} + { _ } => destruct (vm_id_eq_dec v1 v2)
end.
Defined.
(* unchanging starting parameters of the global state *)
Class abstract_state_parameters :=
{
vms : list vm_id;
hafnium_reserved : addr -> bool;
}.
(* Global abstract state : all addresses are owned by one particular entity (a
VM or Hafnium), and accessible by a certain set of entities. This
is a global way of capturing the V/O/X bits in Hafnium's page tables. For
reference, the description of these states given in the Hafnium source
is copied here:
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The states are made up of three parts:
1. V = valid/invalid : Whether the memory is part of the VM's address
space. A fault will be generated if accessed when
invalid.
2. O = owned/unowned : Whether the memory is owned by the VM.
3. X = exclusive/shared : Whether access is exclusive to the VM or shared
with at most one other.
These parts compose to form the following state:
- V O X : Owner of memory with exclusive access.
- V O !X : Owner of memory with access shared with at most one other VM.
- V !O X : Borrower of memory with exclusive access.
- V !O !X : Borrower of memory where access is shared with the owner.
- !V O X : Owner of memory lent to a VM that has exclusive access.
- !V O !X : Unused. Owner of shared memory always has access.
- !V !O X : Invalid memory. Memory is unrelated to the VM.
- !V !O !X : Invalid memory. Memory is unrelated to the VM.
~~~~~~~~~~~~~~~~~~~~~~
These codes, however, are all from the perspective of a single entity, while
this model needs to reason at a more global conceptual level about who can
access a piece of memory, and who owns it. Therefore, we translate these
attribute bits into global concepts according to the table below:
If entity "me" sees... | then the global state of that page is...
| [accessible_by] | [owned_by]
======================================================================
V O X | me | me
V O !X | me, <someone else> | me
V !O X | me | <someone else>
V !O !X | me, <someone else> | <same someone else>
!V O X | <someone else> | me
!V O !X | -----------------unused----------------------
!V !O X | <not me; 1 or 2 others> | <someone else>
!V !O !X | <not me; 1 or 2 others> | <someone else>
*)
Class abstract_state :=
{
(* accessible_by is a function from address to list of entity IDs *)
accessible_by : addr -> list entity_id;
(* owned_by is a function from address to list of entity IDs -- only
single-element lists are considered valid, but for intermediate steps
we leave other lengths representable *)
owned_by : addr -> list entity_id;
}.
(*** The following definitions describe some basic operations on the abstract
state. Each takes a current state as input and returns a new state. ***)
(* if VM with ID [from_id] has access to memory at address [a], revoke it. *)
Definition revoke_access
(s : abstract_state) (from_id : vm_id) (a : addr)
: abstract_state :=
{|
(* new accessibility state *)
accessible_by := (fun a' =>
(* to look up an address a', first check if a' == a *)
if addr_eq_dec a a'
then
(* a = a'; look up who could access a' in the
previous state, remove all occurrences of
[from_id] from the list, and return it *)
remove entity_id_eq_dec from_id (accessible_by a')
else
(* a != a'; return the list from previous state *)
accessible_by a');
(* owned_by doesn't change *)
owned_by := owned_by
|}.
(* add [to_id] to the list of entities that can access memory at address [a] *)
Definition allow_access
(s : abstract_state) (to_id : entity_id) (a : addr)
: abstract_state :=
{|
(* new accessibility state *)
accessible_by := (fun a' =>
(* to look up an address a', first check if a' == a *)
if addr_eq_dec a a'
then
(* a = a'; look up who could access a' in the
previous state, add [to_id] to the list, and
return it *)
to_id :: accessible_by a'
else
(* a != a'; return the list from previous state *)
accessible_by a');
(* owned_by doesn't change *)
owned_by := owned_by
|}.
(* set the entity with ID [to_id] as the owner of memory at address [a] *)
Definition set_owner
(s : abstract_state) (to_id : entity_id) (a : addr)
: abstract_state :=
{|
(* accessible_by doesn't change *)
accessible_by := accessible_by;
(* new ownership state *)
owned_by := (fun a' =>
(* to look up an address a', first check if a' == a *)
if addr_eq_dec a a'
then
(* a = a'; to_id is the owner *)
[to_id]
else
(* a != a'; get the owner from the old state*)
owned_by a')
|}.
(* tell [autounfold] to unfold these definitions *)
Hint Unfold revoke_access allow_access set_owner.
(*** Define giving/sharing/lending memory in terms of the basic operations ***)
Definition give (s : abstract_state) (from_id to_id : vm_id) (a : addr)
: abstract_state := set_owner (allow_access (revoke_access s from_id a) to_id a) to_id a.
Definition share (s : abstract_state) (from_id to_id : vm_id) (a : addr)
: abstract_state := allow_access s to_id a.
Definition lend (s : abstract_state) (from_id to_id : vm_id) (a : addr)
: abstract_state := allow_access (revoke_access s from_id a) to_id a.
(* tell [autounfold] to unfold these definitions *)
Hint Unfold give share lend.
(*** shortcut statements about the global state to make [is_valid] more
readable ***)
Local Definition has_access {s : abstract_state} (id : entity_id) (a : addr) :=
In id (accessible_by a).
Local Definition has_exclusive_access
{s : abstract_state} (id : entity_id) (a : addr) :=
accessible_by a = [id].
Local Definition owns {s : abstract_state} (id : entity_id) (a : addr) :=
In id (owned_by a).
(* tell [autounfold] to unfold these definitions *)
Hint Unfold has_access has_exclusive_access owns.
(* TODO: for now, Hafnium itself can't participate in lending/sharing/giving,
but eventually we will need to deal with send/recv buffers. *)
(* inductive definition of valid operations on an abstract state *)
Inductive is_valid {params : abstract_state_parameters}
: abstract_state -> Prop :=
(* initial state: no memory is shared *)
| AbstractInit :
forall (owned_by_init : addr -> entity_id),
(* precondition on the initial assignment *)
(forall a,
if hafnium_reserved a
then
(* if the address is marked as reserved for Hafnium, then it indeed
belongs to Hafnium (whose ID is [hid]) *)
owned_by_init a = inr hid
else
(* otherwise, it belongs to a VM whose ID is in the [vms] list *)
exists vid, owned_by_init a = inl vid /\ In vid vms) ->
is_valid
{|
(* only the owner has access *)
accessible_by := fun a => [owned_by_init a];
owned_by := fun a => [owned_by_init a];
|}
(* a VM can give memory it owns to another VM *)
| AbstractGive :
forall (state : abstract_state) (from_id to_id : vm_id) (a : addr),
(* if previous state is valid *)
is_valid state ->
(* ...and requesting VM has exclusive access *)
has_exclusive_access from_id a ->
(* ...and requesting VM owns the memory *)
owns from_id a ->
(* ...and the destination VM ID exists *)
In to_id vms ->
(* ...then state is valid after [give] *)
is_valid (state.(give) from_id to_id a)
(* a VM can give back memory previously shared/lent to it *)
| AbstractReturn :
forall (state : abstract_state) (from_id to_id : vm_id) (a : addr),
(* if previous state is valid *)
is_valid state ->
(* ...and requesting VM has access *)
has_access from_id a ->
(* ...and the *destination* VM owns the memory *)
owns to_id a ->
(* ...then state is valid after [give] *)
is_valid (state.(give) from_id to_id a)
(* a VM can give one other VM access to memory it owns *)
| AbstractShare :
forall (state : abstract_state) (from_id to_id : vm_id) (a : addr),
(* if previous state is valid *)
is_valid state ->
(* ...and requesting VM has exclusive access *)
has_exclusive_access from_id a ->
(* ...and requesting VM owns the memory *)
owns from_id a ->
(* ...and the destination VM ID exists *)
In to_id vms ->
(* ...then state is valid after [share] *)
is_valid (state.(share) from_id to_id a)
(* a VM can give exclusive access to one other VM *)
| AbstractLend :
forall (state : abstract_state) (from_id to_id : vm_id) (a : addr),
(* if previous state is valid *)
is_valid state ->
(* ...and requesting VM has exclusive access *)
has_exclusive_access from_id a ->
(* ...and requesting VM owns the memory *)
owns from_id a ->
(* ...and the destination VM ID exists *)
In to_id vms ->
(* ...then state is valid after [lend] *)
is_valid (state.(lend) from_id to_id a)
.
Definition obeys_invariants
{params : abstract_state_parameters}
(state : abstract_state) : Prop :=
(* all the VMs mentioned in accessibility state exist in the system *)
(forall (vid : vm_id) (a : addr), has_access vid a -> In vid vms)
(* ...and all the VMs mentioned in ownership state exist in the system *)
/\ (forall (vid : vm_id) (a : addr), owns vid a -> In vid vms)
(* ...and at least one entity always has access to memory *)
/\ (forall a, exists (e : entity_id), has_access e a)
(* ...and memory is always owned by exactly one VM *)
/\ (forall a, length (owned_by a) = 1)
(* ...and memory is accessible by at most 2 VMs *)
/\ (forall a, length (accessible_by a) <= 2)
(* ...and the set of memory owned by Hafnium never changes *)
/\ (forall a, owns hid a <-> hafnium_reserved a = true)
(* ...and no one has access to Hafnium's memory but Hafnium (id = [hid]) *)
/\ (forall a, hafnium_reserved a = true ->
forall (id : entity_id), has_access id a -> id = inr hid).
(* TODO: VMs only have access if another VM gave/shared/lent it to them in
the past -- requires reasoning about traces *)
(* tell [solver] to try solving goals with properties of [In] *)
Hint Resolve in_cons in_eq.
(* if the state is valid, then the state obeys the invariants *)
Lemma valid_obeys_invariants {params : abstract_state_parameters} :
forall s, is_valid s -> obeys_invariants s.
Proof.
cbv [obeys_invariants]; induction 1;
repeat match goal with
| _ => progress basics
| _ => progress break_match
| _ => progress autounfold in *
| _ => progress invert_list_properties
| _ => progress autorewrite with push_length
| _ => progress cbn [accessible_by owned_by] in *
| H : (forall a, if hafnium_reserved a then _ else _),
a : addr |- _ => specialize (H a)
| H : _ |- _ => apply In_remove in H
| H : accessible_by _ = cons _ _ |- _ => rewrite H
| H : _ |- context [length (remove ?dec ?x ?ls)] =>
pose proof (remove_length_lt dec x ls H); solver
| |- context [length (remove ?dec ?x ?ls)] =>
pose proof (remove_length_le dec x ls);
autorewrite with push_length in *; solver
| H : (forall a, hafnium_reserved a = true -> _),
H' : hafnium_reserved _ = true |- _ =>
eapply H in H'; [| try match goal with
H : accessible_by _ = _ |- _ =>
rewrite H end; solver]
| H : forall a, length (accessible_by a) <= _
|- context [accessible_by ?a] => specialize (H a)
| H : context [_ <-> _] |- _ => apply H; solver
| _ => eexists; cbn; repeat break_match; solver
| |- _ <-> _ => split
| _ => solver
end.
Qed.
End Abstract.
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:28:30 09/01/2017
// Design Name: messbauer_diff_discriminator_signals
// Module Name: E:/PLD/MessbauerTestEnvironment/messbaue_test_environment/tests/messbauer_diff_discriminator_testbench.v
// Project Name: messbaue_test_environment
// Target Device: Spartan6
// Tool versions: XILINX ISE 14.7
// Description:
//
// Verilog Test Fixture created by ISE for module: messbauer_diff_discriminator_signals
//
// Dependencies:
//
// Revision:
// Revision 1.0
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module messbauer_diff_discriminator_testbench;
// Inputs
reg aclk;
reg areset_n;
reg channel;
// Outputs
wire lower_threshold;
wire upper_threshold;
// Instantiate the Unit Under Test (UUT)
messbauer_diff_discriminator_signals
uut
(
.aclk(aclk),
.areset_n(areset_n),
.channel(channel),
.lower_threshold(lower_threshold),
.upper_threshold(upper_threshold)
);
localparam CHANNEL_WAIT_COUNTER_CYCLES = 10;
reg [7:0]channel_wait_counter;
reg channel_generation_enabled;
initial
begin
// Initialize Inputs
aclk = 0;
areset_n = 0;
channel = 0;
channel_wait_counter = 0;
channel_generation_enabled = 0;
// Wait 100 ns for global reset to finish
#100;
areset_n = 1;
// Add stimulus here
end
always
begin
#20 aclk <= ~aclk;
end
always
begin
if(channel_wait_counter < CHANNEL_WAIT_COUNTER_CYCLES)
#100 channel_wait_counter <= channel_wait_counter + 1;
else
begin
#64000 channel <= ~channel; // 128 us per messbauer channel
end
end
endmodule
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="HLS_accel,hls_ip_2014_4,{HLS_INPUT_TYPE=cxx,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7z020clg484-1,HLS_INPUT_CLOCK=10.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=8.626000,HLS_SYN_LAT=8280,HLS_SYN_TPT=none,HLS_SYN_MEM=6,HLS_SYN_DSP=26,HLS_SYN_FF=4447,HLS_SYN_LUT=7886}" *)
module HLS_accel (
s_axi_CONTROL_BUS_AWVALID,
s_axi_CONTROL_BUS_AWREADY,
s_axi_CONTROL_BUS_AWADDR,
s_axi_CONTROL_BUS_WVALID,
s_axi_CONTROL_BUS_WREADY,
s_axi_CONTROL_BUS_WDATA,
s_axi_CONTROL_BUS_WSTRB,
s_axi_CONTROL_BUS_ARVALID,
s_axi_CONTROL_BUS_ARREADY,
s_axi_CONTROL_BUS_ARADDR,
s_axi_CONTROL_BUS_RVALID,
s_axi_CONTROL_BUS_RREADY,
s_axi_CONTROL_BUS_RDATA,
s_axi_CONTROL_BUS_RRESP,
s_axi_CONTROL_BUS_BVALID,
s_axi_CONTROL_BUS_BREADY,
s_axi_CONTROL_BUS_BRESP,
ap_clk,
ap_rst_n,
INPUT_STREAM_TDATA,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
interrupt
);
parameter ap_const_logic_1 = 1'b1;
parameter ap_const_logic_0 = 1'b0;
parameter ap_ST_st1_fsm_0 = 10'b1;
parameter ap_ST_st2_fsm_1 = 10'b10;
parameter ap_ST_st3_fsm_2 = 10'b100;
parameter ap_ST_pp2_stg0_fsm_3 = 10'b1000;
parameter ap_ST_pp2_stg1_fsm_4 = 10'b10000;
parameter ap_ST_pp2_stg2_fsm_5 = 10'b100000;
parameter ap_ST_pp2_stg3_fsm_6 = 10'b1000000;
parameter ap_ST_pp2_stg4_fsm_7 = 10'b10000000;
parameter ap_ST_pp3_stg0_fsm_8 = 10'b100000000;
parameter ap_ST_st95_fsm_9 = 10'b1000000000;
parameter ap_const_lv32_0 = 32'b00000000000000000000000000000000;
parameter ap_const_lv1_1 = 1'b1;
parameter C_S_AXI_CONTROL_BUS_DATA_WIDTH = 32;
parameter ap_const_int64_8 = 8;
parameter C_S_AXI_CONTROL_BUS_ADDR_WIDTH = 5;
parameter C_DATA_WIDTH = 32;
parameter ap_const_lv32_4 = 32'b100;
parameter ap_const_lv32_5 = 32'b101;
parameter ap_const_lv1_0 = 1'b0;
parameter ap_const_lv32_6 = 32'b110;
parameter ap_const_lv32_7 = 32'b111;
parameter ap_const_lv32_3 = 32'b11;
parameter ap_const_lv32_1 = 32'b1;
parameter ap_const_lv32_2 = 32'b10;
parameter ap_const_lv32_8 = 32'b1000;
parameter ap_const_lv11_0 = 11'b00000000000;
parameter ap_const_lv6_0 = 6'b000000;
parameter ap_const_lv6_1 = 6'b1;
parameter ap_const_lv10_0 = 10'b0000000000;
parameter ap_const_lv4_F = 4'b1111;
parameter ap_const_lv4_0 = 4'b0000;
parameter ap_const_lv5_0 = 5'b00000;
parameter ap_const_lv32_3F800000 = 32'b111111100000000000000000000000;
parameter ap_const_lv32_41200000 = 32'b1000001001000000000000000000000;
parameter ap_const_lv32_40E00000 = 32'b1000000111000000000000000000000;
parameter ap_const_lv32_40800000 = 32'b1000000100000000000000000000000;
parameter ap_const_lv64_0 = 64'b0000000000000000000000000000000000000000000000000000000000000000;
parameter ap_const_lv64_3FE6A09EDBF8B9BB = 64'b11111111100110101000001001111011011011111110001011100110111011;
parameter ap_const_lv64_3F847AE147AE147B = 64'b11111110000100011110101110000101000111101011100001010001111011;
parameter ap_const_lv11_400 = 11'b10000000000;
parameter ap_const_lv11_1 = 11'b1;
parameter ap_const_lv6_20 = 6'b100000;
parameter ap_const_lv6_3F = 6'b111111;
parameter ap_const_lv32_17 = 32'b10111;
parameter ap_const_lv32_1E = 32'b11110;
parameter ap_const_lv8_FF = 8'b11111111;
parameter ap_const_lv23_0 = 23'b00000000000000000000000;
parameter ap_const_lv10_1 = 10'b1;
parameter ap_const_lv10_3FF = 10'b1111111111;
parameter ap_const_lv32_C2C80000 = 32'b11000010110010000000000000000000;
parameter ap_const_lv32_42C80000 = 32'b1000010110010000000000000000000;
parameter ap_const_lv2_0 = 2'b00;
parameter ap_const_lv2_1 = 2'b1;
parameter ap_const_lv5_2 = 5'b10;
parameter ap_const_lv5_1 = 5'b1;
parameter ap_const_lv32_9 = 32'b1001;
parameter ap_true = 1'b1;
parameter C_S_AXI_CONTROL_BUS_WSTRB_WIDTH = (C_S_AXI_CONTROL_BUS_DATA_WIDTH / ap_const_int64_8);
parameter C_WSTRB_WIDTH = (C_DATA_WIDTH / ap_const_int64_8);
input s_axi_CONTROL_BUS_AWVALID;
output s_axi_CONTROL_BUS_AWREADY;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CONTROL_BUS_AWADDR;
input s_axi_CONTROL_BUS_WVALID;
output s_axi_CONTROL_BUS_WREADY;
input [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1 : 0] s_axi_CONTROL_BUS_WDATA;
input [C_S_AXI_CONTROL_BUS_WSTRB_WIDTH - 1 : 0] s_axi_CONTROL_BUS_WSTRB;
input s_axi_CONTROL_BUS_ARVALID;
output s_axi_CONTROL_BUS_ARREADY;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1 : 0] s_axi_CONTROL_BUS_ARADDR;
output s_axi_CONTROL_BUS_RVALID;
input s_axi_CONTROL_BUS_RREADY;
output [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1 : 0] s_axi_CONTROL_BUS_RDATA;
output [1:0] s_axi_CONTROL_BUS_RRESP;
output s_axi_CONTROL_BUS_BVALID;
input s_axi_CONTROL_BUS_BREADY;
output [1:0] s_axi_CONTROL_BUS_BRESP;
input ap_clk;
input ap_rst_n;
input [31:0] INPUT_STREAM_TDATA;
input INPUT_STREAM_TVALID;
output INPUT_STREAM_TREADY;
input [3:0] INPUT_STREAM_TKEEP;
input [3:0] INPUT_STREAM_TSTRB;
input [3:0] INPUT_STREAM_TUSER;
input [0:0] INPUT_STREAM_TLAST;
input [4:0] INPUT_STREAM_TID;
input [4:0] INPUT_STREAM_TDEST;
output [31:0] OUTPUT_STREAM_TDATA;
output OUTPUT_STREAM_TVALID;
input OUTPUT_STREAM_TREADY;
output [3:0] OUTPUT_STREAM_TKEEP;
output [3:0] OUTPUT_STREAM_TSTRB;
output [3:0] OUTPUT_STREAM_TUSER;
output [0:0] OUTPUT_STREAM_TLAST;
output [4:0] OUTPUT_STREAM_TID;
output [4:0] OUTPUT_STREAM_TDEST;
output interrupt;
reg INPUT_STREAM_TREADY;
reg OUTPUT_STREAM_TVALID;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [9:0] ap_CS_fsm = 10'b1;
reg ap_sig_cseq_ST_st1_fsm_0;
reg ap_sig_bdd_51;
reg ap_ready;
wire HLS_accel_CONTROL_BUS_s_axi_U_ap_dummy_ce;
reg [5:0] p_reg_383;
reg [0:0] exitcond2_i_i1_reg_394;
reg [5:0] y_assign_s_reg_405;
reg [5:0] x_assign_5_reg_416;
reg [9:0] indvar_flatten1_reg_427;
reg [10:0] indvar_flatten2_reg_438;
reg [5:0] i4_0_i_reg_449;
reg [5:0] j5_0_i_reg_460;
wire [31:0] a_q0;
reg [31:0] reg_542;
reg ap_sig_cseq_ST_pp2_stg1_fsm_4;
reg ap_sig_bdd_112;
reg ap_reg_ppiten_pp2_it0 = 1'b0;
reg ap_reg_ppiten_pp2_it1 = 1'b0;
reg ap_reg_ppiten_pp2_it2 = 1'b0;
reg ap_reg_ppiten_pp2_it3 = 1'b0;
reg ap_reg_ppiten_pp2_it4 = 1'b0;
reg ap_reg_ppiten_pp2_it5 = 1'b0;
reg ap_reg_ppiten_pp2_it6 = 1'b0;
reg ap_reg_ppiten_pp2_it7 = 1'b0;
reg ap_reg_ppiten_pp2_it8 = 1'b0;
reg ap_reg_ppiten_pp2_it9 = 1'b0;
reg ap_reg_ppiten_pp2_it10 = 1'b0;
reg ap_reg_ppiten_pp2_it11 = 1'b0;
reg ap_reg_ppiten_pp2_it12 = 1'b0;
reg ap_reg_ppiten_pp2_it13 = 1'b0;
reg ap_reg_ppiten_pp2_it14 = 1'b0;
reg ap_reg_ppiten_pp2_it15 = 1'b0;
reg ap_reg_ppiten_pp2_it16 = 1'b0;
reg ap_reg_ppiten_pp2_it17 = 1'b0;
wire [31:0] a_q1;
reg ap_sig_cseq_ST_pp2_stg2_fsm_5;
reg ap_sig_bdd_156;
reg [0:0] tmp_37_reg_1708;
reg ap_sig_cseq_ST_pp2_stg3_fsm_6;
reg ap_sig_bdd_167;
reg [31:0] reg_548;
reg [0:0] tmp_53_reg_1724;
reg ap_sig_cseq_ST_pp2_stg4_fsm_7;
reg ap_sig_bdd_179;
reg [31:0] reg_555;
wire [63:0] grp_fu_532_p2;
reg [63:0] reg_560;
reg [0:0] tmp_10_reg_1693;
reg [0:0] ap_reg_ppstg_tmp_10_reg_1693_pp2_it1;
reg [0:0] ap_reg_ppstg_tmp_37_reg_1708_pp2_it1;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it1;
reg ap_sig_cseq_ST_pp2_stg0_fsm_3;
reg ap_sig_bdd_204;
wire [63:0] grp_fu_527_p2;
reg [63:0] reg_564;
reg [0:0] ap_reg_ppstg_tmp_10_reg_1693_pp2_it2;
reg [0:0] ap_reg_ppstg_tmp_37_reg_1708_pp2_it4;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it8;
wire [31:0] grp_fu_472_p2;
reg [31:0] reg_569;
reg [0:0] ap_reg_ppstg_tmp_37_reg_1708_pp2_it3;
wire [31:0] grp_fu_482_p2;
reg [31:0] reg_574;
wire [0:0] exitcond_flatten_fu_580_p2;
reg ap_sig_cseq_ST_st2_fsm_1;
reg ap_sig_bdd_238;
reg ap_sig_bdd_243;
wire [10:0] indvar_flatten_next_fu_586_p2;
wire [5:0] i_0_i_mid2_fu_612_p3;
wire [5:0] j_fu_652_p2;
wire [0:0] exitcond_flatten8_fu_658_p2;
reg ap_sig_cseq_ST_st3_fsm_2;
reg ap_sig_bdd_260;
reg ap_sig_bdd_264;
wire [10:0] indvar_flatten_next7_fu_664_p2;
wire [5:0] i1_0_i_mid2_fu_690_p3;
wire [5:0] j_1_fu_730_p2;
wire [5:0] y_assign_1_mid2_fu_736_p3;
reg [5:0] y_assign_1_mid2_reg_1677;
wire [5:0] x_assign_5_mid2_fu_744_p3;
reg [5:0] x_assign_5_mid2_reg_1682;
wire [5:0] y_assign_fu_758_p2;
reg [5:0] y_assign_reg_1688;
wire signed [11:0] p_addr4_cast_fu_790_p1;
reg signed [11:0] p_addr4_cast_reg_1698;
reg [0:0] ap_reg_ppstg_tmp_37_reg_1708_pp2_it2;
reg [0:0] ap_reg_ppstg_tmp_37_reg_1708_pp2_it5;
wire [11:0] tmp_44_0_1_trn_cast_fu_813_p1;
reg [11:0] tmp_44_0_1_trn_cast_reg_1714;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it2;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it3;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it4;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it5;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it6;
reg [0:0] ap_reg_ppstg_tmp_53_reg_1724_pp2_it7;
wire [10:0] tmp_58_fu_836_p3;
reg [10:0] tmp_58_reg_1730;
wire [11:0] p_addr8_cast1_fu_844_p1;
reg [11:0] p_addr8_cast1_reg_1735;
wire [63:0] tmp_84_fu_854_p1;
reg [63:0] tmp_84_reg_1740;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it1;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it2;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it3;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it4;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it5;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it6;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it7;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it8;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it9;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it10;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it11;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it12;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it13;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it14;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it15;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it16;
reg [63:0] ap_reg_ppstg_tmp_84_reg_1740_pp2_it17;
wire [63:0] grp_fu_499_p1;
reg [63:0] tmp_reg_1751;
wire [5:0] q_fu_862_p2;
reg [5:0] q_reg_1756;
wire [11:0] p_addr_fu_895_p2;
reg [11:0] p_addr_reg_1771;
wire [5:0] p_1_fu_900_p2;
reg [5:0] p_1_reg_1776;
wire signed [12:0] p_addr2_fu_921_p2;
reg signed [12:0] p_addr2_reg_1781;
wire [11:0] p_addr4_fu_927_p2;
reg [11:0] p_addr4_reg_1786;
wire [11:0] p_addr8_fu_932_p2;
reg [11:0] p_addr8_reg_1791;
wire [31:0] b_q0;
reg [31:0] b_load_reg_1796;
wire [0:0] exitcond2_i_i_fu_938_p2;
reg [0:0] exitcond2_i_i_reg_1802;
wire [0:0] tmp_30_fu_980_p2;
reg [0:0] tmp_30_reg_1807;
reg [0:0] ap_reg_ppstg_tmp_30_reg_1807_pp2_it1;
wire [0:0] grp_fu_515_p2;
reg [0:0] tmp_39_reg_1812;
reg [63:0] tmp_8_reg_1817;
wire [0:0] grp_fu_520_p2;
reg [0:0] tmp_75_reg_1832;
wire [31:0] x_assign_3_fu_1035_p3;
reg [31:0] x_assign_3_reg_1837;
reg [31:0] ap_reg_ppstg_x_assign_3_reg_1837_pp2_it1;
reg [31:0] ap_reg_ppstg_x_assign_3_reg_1837_pp2_it2;
wire [0:0] tmp_46_fu_1079_p2;
reg [0:0] tmp_46_reg_1842;
reg [0:0] ap_reg_ppstg_tmp_46_reg_1842_pp2_it1;
reg [0:0] tmp_50_reg_1847;
reg [63:0] tmp_33_reg_1852;
wire [0:0] tmp_94_fu_1093_p2;
reg [0:0] tmp_94_reg_1867;
wire [31:0] x_assign_7_fu_1139_p3;
reg [31:0] x_assign_7_reg_1872;
reg [31:0] ap_reg_ppstg_x_assign_7_reg_1872_pp2_it1;
reg [31:0] ap_reg_ppstg_x_assign_7_reg_1872_pp2_it2;
reg [31:0] ap_reg_ppstg_x_assign_7_reg_1872_pp2_it3;
reg [31:0] ap_reg_ppstg_x_assign_7_reg_1872_pp2_it4;
wire [0:0] grp_fu_510_p2;
reg [0:0] tmp_55_reg_1877;
wire [0:0] tmp_61_fu_1183_p2;
reg [0:0] tmp_61_reg_1882;
reg [0:0] ap_reg_ppstg_tmp_61_reg_1882_pp2_it1;
reg [63:0] tmp_36_reg_1887;
wire [0:0] or_cond_i8_fu_1224_p2;
reg [0:0] or_cond_i8_reg_1897;
wire [0:0] tmp_86_fu_1229_p2;
reg [0:0] tmp_86_reg_1903;
reg [0:0] ap_reg_ppstg_tmp_86_reg_1903_pp2_it1;
wire [9:0] indvar_flatten_next1_fu_1235_p2;
reg [9:0] indvar_flatten_next1_reg_1909;
wire [0:0] exitcond_flatten1_fu_1241_p2;
reg [0:0] exitcond_flatten1_reg_1914;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it1;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it2;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it3;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it4;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it5;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it6;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it7;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it8;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it9;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it10;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it11;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it12;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it13;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it14;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it15;
reg [0:0] ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it16;
wire [31:0] x_assign_9_fu_1288_p3;
reg [31:0] x_assign_9_reg_1918;
reg [31:0] ap_reg_ppstg_x_assign_9_reg_1918_pp2_it2;
reg [31:0] ap_reg_ppstg_x_assign_9_reg_1918_pp2_it3;
reg [31:0] ap_reg_ppstg_x_assign_9_reg_1918_pp2_it4;
reg [31:0] ap_reg_ppstg_x_assign_9_reg_1918_pp2_it5;
reg [31:0] ap_reg_ppstg_x_assign_9_reg_1918_pp2_it6;
reg [0:0] tmp_65_reg_1923;
wire [0:0] tmp_71_fu_1332_p2;
reg [0:0] tmp_71_reg_1928;
reg [0:0] ap_reg_ppstg_tmp_71_reg_1928_pp2_it2;
reg [31:0] a_load_reg_1933;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it2;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it3;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it4;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it5;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it6;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it7;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it8;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it9;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it10;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it11;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it12;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it13;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it14;
reg [31:0] ap_reg_ppstg_a_load_reg_1933_pp2_it15;
wire [31:0] x_assign_2_fu_1361_p3;
reg [31:0] x_assign_2_reg_1941;
wire [31:0] x_assign_1_fu_1410_p3;
reg [31:0] x_assign_1_reg_1948;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it2;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it3;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it4;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it5;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it6;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it7;
reg [31:0] ap_reg_ppstg_x_assign_1_reg_1948_pp2_it8;
reg [0:0] tmp_92_reg_1953;
wire [31:0] x_assign_4_fu_1458_p3;
reg [31:0] x_assign_4_reg_1958;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9;
reg [31:0] ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10;
wire [63:0] tmp_31_fu_1465_p3;
reg [63:0] tmp_31_reg_1963;
wire [31:0] grp_fu_486_p2;
reg [31:0] tmp_14_reg_1968;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it2;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it3;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it4;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it5;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it6;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it7;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it8;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it9;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it10;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it11;
reg [31:0] ap_reg_ppstg_tmp_14_reg_1968_pp2_it12;
wire [63:0] tmp_41_0_2_fu_1472_p3;
reg [63:0] tmp_41_0_2_reg_1973;
reg [63:0] ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it2;
reg [63:0] ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it3;
wire [63:0] tmp_41_2_fu_1479_p3;
reg [63:0] tmp_41_2_reg_1978;
reg [63:0] ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it3;
reg [63:0] ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it4;
reg [63:0] ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it5;
reg [63:0] ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it6;
reg [63:0] ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it7;
reg [31:0] tmp_15_reg_1983;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it3;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it4;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it5;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it6;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it7;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it8;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it9;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it10;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it11;
reg [31:0] ap_reg_ppstg_tmp_15_reg_1983_pp2_it12;
wire [31:0] grp_fu_477_p2;
reg [31:0] tmp_21_reg_1988;
wire [63:0] tmp_41_2_2_fu_1486_p3;
reg [63:0] tmp_41_2_2_reg_1993;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it3;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it4;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it5;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it6;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it7;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it8;
reg [63:0] ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it9;
wire [31:0] output_i_fu_1493_p3;
wire [31:0] sum_4_i_i_fu_1501_p3;
reg [31:0] sum_4_i_i_reg_2003;
reg [31:0] ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it3;
reg [31:0] ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it4;
reg [31:0] tmp_23_reg_2010;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it3;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it4;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it5;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it6;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it7;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it8;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it9;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it10;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it11;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it12;
reg [31:0] ap_reg_ppstg_tmp_23_reg_2010_pp2_it13;
reg [63:0] tmp_42_0_2_reg_2015;
wire [31:0] sum_4_i_i_0_2_fu_1515_p3;
reg [31:0] sum_4_i_i_0_2_reg_2020;
wire [31:0] sum_4_i_i_1_fu_1521_p3;
reg [31:0] sum_4_i_i_1_reg_2026;
reg [31:0] sum_1_1_2_reg_2031;
reg [31:0] ap_reg_ppstg_sum_1_1_2_reg_2031_pp2_it8;
wire [63:0] grp_fu_504_p1;
reg [63:0] tmp_42_2_reg_2037;
wire [31:0] sum_4_i_i_2_fu_1527_p3;
reg [31:0] sum_4_i_i_2_reg_2042;
reg [63:0] tmp_42_2_2_reg_2047;
wire [31:0] grp_fu_496_p1;
reg [31:0] sum_2_2_reg_2052;
wire [31:0] grp_fu_492_p2;
reg [31:0] tmp_19_reg_2057;
reg [31:0] tmp_20_reg_2062;
reg [63:0] tmp_25_reg_2067;
wire [63:0] tmp_24_fu_507_p1;
reg [63:0] tmp_24_reg_2072;
reg [63:0] tmp_26_reg_2077;
reg [31:0] tmp_28_reg_2082;
wire [0:0] exitcond_flatten2_fu_1533_p2;
reg [0:0] exitcond_flatten2_reg_2087;
reg ap_sig_cseq_ST_pp3_stg0_fsm_8;
reg ap_sig_bdd_617;
reg ap_reg_ppiten_pp3_it0 = 1'b0;
reg ap_sig_ioackin_OUTPUT_STREAM_TREADY;
reg ap_reg_ppiten_pp3_it1 = 1'b0;
wire [10:0] indvar_flatten_next2_fu_1539_p2;
wire [5:0] i4_0_i_mid2_fu_1565_p3;
reg [5:0] i4_0_i_mid2_reg_2096;
wire [0:0] last_assign_fu_1622_p2;
reg [0:0] last_assign_reg_2106;
wire [5:0] j_2_fu_1628_p2;
reg [9:0] a_address0;
reg a_ce0;
reg a_we0;
wire [31:0] a_d0;
reg [9:0] a_address1;
reg a_ce1;
reg [9:0] b_address0;
reg b_ce0;
reg b_we0;
wire [31:0] b_d0;
reg [9:0] out_address0;
reg out_ce0;
reg out_we0;
wire [31:0] out_d0;
wire [31:0] out_q0;
reg [10:0] indvar_flatten_reg_317;
reg [5:0] i_0_i_reg_328;
reg [5:0] j_0_i_reg_339;
reg [10:0] indvar_flatten6_reg_350;
reg [5:0] i1_0_i_reg_361;
reg [5:0] j2_0_i_reg_372;
reg [5:0] p_phi_fu_387_p4;
reg [0:0] exitcond2_i_i1_phi_fu_398_p4;
reg [5:0] y_assign_s_phi_fu_409_p4;
reg [5:0] x_assign_5_phi_fu_420_p4;
reg [9:0] indvar_flatten1_phi_fu_431_p4;
reg [5:0] i4_0_i_phi_fu_453_p4;
wire [63:0] tmp_4_fu_647_p1;
wire [63:0] tmp_7_fu_725_p1;
wire signed [63:0] tmp_12_fu_800_p1;
wire signed [63:0] tmp_34_fu_823_p1;
wire signed [63:0] tmp_41_fu_876_p1;
wire signed [63:0] tmp_63_fu_890_p1;
wire [63:0] tmp_73_fu_986_p1;
wire signed [63:0] tmp_78_fu_990_p1;
wire [63:0] tmp_81_fu_1085_p1;
wire [63:0] tmp_83_fu_1089_p1;
wire [63:0] tmp_97_fu_1617_p1;
reg ap_reg_ioackin_OUTPUT_STREAM_TREADY = 1'b0;
reg [31:0] grp_fu_472_p0;
reg [31:0] grp_fu_472_p1;
reg [31:0] grp_fu_477_p0;
reg [31:0] grp_fu_477_p1;
reg [31:0] grp_fu_482_p0;
reg [31:0] grp_fu_482_p1;
reg [31:0] grp_fu_486_p0;
reg [31:0] grp_fu_486_p1;
wire [31:0] grp_fu_492_p0;
wire [31:0] grp_fu_492_p1;
wire [63:0] grp_fu_496_p0;
reg [31:0] grp_fu_499_p0;
wire [31:0] sum_4_i_i_0_1_fu_1508_p3;
reg [31:0] grp_fu_504_p0;
wire [31:0] tmp_24_fu_507_p0;
reg [31:0] grp_fu_510_p0;
wire [31:0] grp_fu_510_p1;
reg [31:0] grp_fu_515_p0;
wire [31:0] grp_fu_515_p1;
wire [31:0] grp_fu_520_p0;
reg [31:0] grp_fu_520_p1;
reg [63:0] grp_fu_527_p0;
reg [63:0] grp_fu_527_p1;
reg [63:0] grp_fu_532_p0;
reg [63:0] grp_fu_532_p1;
wire [0:0] exitcond4_i_fu_592_p2;
wire [5:0] i_fu_606_p2;
wire [5:0] j_0_i_mid2_fu_598_p3;
wire [10:0] tmp_1_fu_629_p3;
wire [11:0] p_addr_cast_fu_637_p1;
wire [11:0] tmp_1_trn_cast_fu_625_p1;
wire [11:0] p_addr1_fu_641_p2;
wire [0:0] exitcond2_i_fu_670_p2;
wire [5:0] i_s_fu_684_p2;
wire [5:0] j2_0_i_mid2_fu_676_p3;
wire [10:0] tmp_6_fu_707_p3;
wire [11:0] p_addr2_cast_fu_715_p1;
wire [11:0] tmp_4_trn_cast_fu_703_p1;
wire [11:0] p_addr3_fu_719_p2;
wire [5:0] x_assign_fu_752_p2;
wire [5:0] tmp_9_fu_768_p2;
wire [10:0] tmp_11_fu_782_p3;
wire signed [11:0] y_assign_cast_cast_fu_764_p1;
wire signed [11:0] p_addr5_fu_794_p2;
wire signed [11:0] p_addr6_fu_817_p2;
wire [11:0] p_addr10_fu_848_p2;
wire [11:0] tmp_38_0_2_trn_cast_fu_867_p1;
wire signed [11:0] p_addr7_fu_871_p2;
wire [12:0] p_addr8_cast_fu_881_p1;
wire signed [12:0] y_assign_cast_cast1_fu_859_p1;
wire signed [12:0] p_addr9_fu_884_p2;
wire [10:0] tmp_77_fu_905_p3;
wire [12:0] p_addr11_cast_fu_917_p1;
wire [11:0] p_addr11_cast1_fu_913_p1;
wire [31:0] x_assign_1_to_int_fu_944_p1;
wire [7:0] tmp_13_fu_948_p4;
wire [22:0] tmp_17_fu_958_p1;
wire [0:0] notrhs_fu_968_p2;
wire [0:0] notlhs_fu_962_p2;
wire [0:0] tmp_22_fu_974_p2;
wire [31:0] x_assign_2_to_int_fu_994_p1;
wire [7:0] tmp_35_fu_998_p4;
wire [22:0] tmp_43_fu_1008_p1;
wire [0:0] notrhs1_fu_1018_p2;
wire [0:0] notlhs1_fu_1012_p2;
wire [0:0] tmp_38_fu_1024_p2;
wire [0:0] tmp_40_fu_1030_p2;
wire [31:0] x_assign_4_to_int_fu_1043_p1;
wire [7:0] tmp_42_fu_1047_p4;
wire [22:0] tmp_48_fu_1057_p1;
wire [0:0] notrhs2_fu_1067_p2;
wire [0:0] notlhs2_fu_1061_p2;
wire [0:0] tmp_44_fu_1073_p2;
wire [31:0] x_assign_6_to_int_fu_1098_p1;
wire [7:0] tmp_47_fu_1102_p4;
wire [22:0] tmp_68_fu_1112_p1;
wire [0:0] notrhs3_fu_1122_p2;
wire [0:0] notlhs3_fu_1116_p2;
wire [0:0] tmp_49_fu_1128_p2;
wire [0:0] tmp_51_fu_1134_p2;
wire [31:0] x_assign_11_to_int_fu_1147_p1;
wire [7:0] tmp_57_fu_1151_p4;
wire [22:0] tmp_79_fu_1161_p1;
wire [0:0] notrhs5_fu_1171_p2;
wire [0:0] notlhs5_fu_1165_p2;
wire [0:0] tmp_59_fu_1177_p2;
wire [31:0] m_assign_to_int_fu_1189_p1;
wire [7:0] tmp_72_fu_1192_p4;
wire [22:0] tmp_95_fu_1202_p1;
wire [0:0] notrhs8_fu_1212_p2;
wire [0:0] notlhs8_fu_1206_p2;
wire [0:0] tmp_74_fu_1218_p2;
wire [31:0] x_assign_8_to_int_fu_1247_p1;
wire [7:0] tmp_52_fu_1251_p4;
wire [22:0] tmp_76_fu_1261_p1;
wire [0:0] notrhs4_fu_1271_p2;
wire [0:0] notlhs4_fu_1265_p2;
wire [0:0] tmp_54_fu_1277_p2;
wire [0:0] tmp_56_fu_1283_p2;
wire [31:0] x_assign_14_to_int_fu_1296_p1;
wire [7:0] tmp_67_fu_1300_p4;
wire [22:0] tmp_90_fu_1310_p1;
wire [0:0] notrhs7_fu_1320_p2;
wire [0:0] notlhs7_fu_1314_p2;
wire [0:0] tmp_69_fu_1326_p2;
wire [0:0] sel_tmp1_fu_1338_p2;
wire [0:0] sel_tmp2_fu_1343_p2;
wire [0:0] tmp_88_fu_1356_p2;
wire [31:0] tmp_87_fu_1348_p3;
wire [31:0] x_assign_12_to_int_fu_1369_p1;
wire [7:0] tmp_62_fu_1373_p4;
wire [22:0] tmp_82_fu_1383_p1;
wire [0:0] notrhs6_fu_1393_p2;
wire [0:0] notlhs6_fu_1387_p2;
wire [0:0] tmp_64_fu_1399_p2;
wire [0:0] tmp_66_fu_1405_p2;
wire [31:0] x_assign_15_to_int_fu_1418_p1;
wire [7:0] tmp_89_fu_1421_p4;
wire [22:0] tmp_98_fu_1431_p1;
wire [0:0] notrhs9_fu_1441_p2;
wire [0:0] notlhs9_fu_1435_p2;
wire [0:0] tmp_91_fu_1447_p2;
wire [0:0] tmp_93_fu_1453_p2;
wire [0:0] exitcond_i_fu_1545_p2;
wire [5:0] i_1_fu_1559_p2;
wire [4:0] tmp_99_fu_1573_p1;
wire [5:0] j5_0_i_mid2_fu_1551_p3;
wire [9:0] j5_0_i_cast5_fu_1585_p1;
wire [9:0] tmp_5_fu_1577_p3;
wire [10:0] tmp_96_fu_1599_p3;
wire [11:0] p_addr16_cast_fu_1607_p1;
wire [11:0] tmp_11_trn_cast_fu_1595_p1;
wire [11:0] p_addr11_fu_1611_p2;
wire [9:0] k_fu_1589_p2;
reg [1:0] grp_fu_472_opcode;
wire grp_fu_472_ce;
reg [1:0] grp_fu_477_opcode;
wire grp_fu_477_ce;
reg [1:0] grp_fu_482_opcode;
wire grp_fu_482_ce;
wire grp_fu_486_ce;
wire grp_fu_492_ce;
wire [4:0] grp_fu_510_opcode;
wire [4:0] grp_fu_515_opcode;
wire [4:0] grp_fu_520_opcode;
wire grp_fu_527_ce;
wire grp_fu_532_ce;
reg ap_sig_cseq_ST_st95_fsm_9;
reg ap_sig_bdd_1567;
reg [9:0] ap_NS_fsm;
HLS_accel_CONTROL_BUS_s_axi #(
.C_ADDR_WIDTH( C_S_AXI_CONTROL_BUS_ADDR_WIDTH ),
.C_DATA_WIDTH( C_S_AXI_CONTROL_BUS_DATA_WIDTH ))
HLS_accel_CONTROL_BUS_s_axi_U(
.AWVALID( s_axi_CONTROL_BUS_AWVALID ),
.AWREADY( s_axi_CONTROL_BUS_AWREADY ),
.AWADDR( s_axi_CONTROL_BUS_AWADDR ),
.WVALID( s_axi_CONTROL_BUS_WVALID ),
.WREADY( s_axi_CONTROL_BUS_WREADY ),
.WDATA( s_axi_CONTROL_BUS_WDATA ),
.WSTRB( s_axi_CONTROL_BUS_WSTRB ),
.ARVALID( s_axi_CONTROL_BUS_ARVALID ),
.ARREADY( s_axi_CONTROL_BUS_ARREADY ),
.ARADDR( s_axi_CONTROL_BUS_ARADDR ),
.RVALID( s_axi_CONTROL_BUS_RVALID ),
.RREADY( s_axi_CONTROL_BUS_RREADY ),
.RDATA( s_axi_CONTROL_BUS_RDATA ),
.RRESP( s_axi_CONTROL_BUS_RRESP ),
.BVALID( s_axi_CONTROL_BUS_BVALID ),
.BREADY( s_axi_CONTROL_BUS_BREADY ),
.BRESP( s_axi_CONTROL_BUS_BRESP ),
.ACLK( ap_clk ),
.ARESET( ap_rst_n_inv ),
.ACLK_EN( HLS_accel_CONTROL_BUS_s_axi_U_ap_dummy_ce ),
.ap_start( ap_start ),
.interrupt( interrupt ),
.ap_ready( ap_ready ),
.ap_done( ap_done ),
.ap_idle( ap_idle )
);
HLS_accel_a #(
.DataWidth( 32 ),
.AddressRange( 1024 ),
.AddressWidth( 10 ))
a_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( a_address0 ),
.ce0( a_ce0 ),
.we0( a_we0 ),
.d0( a_d0 ),
.q0( a_q0 ),
.address1( a_address1 ),
.ce1( a_ce1 ),
.q1( a_q1 )
);
HLS_accel_b #(
.DataWidth( 32 ),
.AddressRange( 1024 ),
.AddressWidth( 10 ))
b_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( b_address0 ),
.ce0( b_ce0 ),
.we0( b_we0 ),
.d0( b_d0 ),
.q0( b_q0 )
);
HLS_accel_b #(
.DataWidth( 32 ),
.AddressRange( 1024 ),
.AddressWidth( 10 ))
out_U(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.address0( out_address0 ),
.ce0( out_ce0 ),
.we0( out_we0 ),
.d0( out_d0 ),
.q0( out_q0 )
);
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp_U0(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_472_p0 ),
.din1( grp_fu_472_p1 ),
.opcode( grp_fu_472_opcode ),
.ce( grp_fu_472_ce ),
.dout( grp_fu_472_p2 )
);
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp_U1(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_477_p0 ),
.din1( grp_fu_477_p1 ),
.opcode( grp_fu_477_opcode ),
.ce( grp_fu_477_ce ),
.dout( grp_fu_477_p2 )
);
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_faddfsub_32ns_32ns_32_5_full_dsp_U2(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_482_p0 ),
.din1( grp_fu_482_p1 ),
.opcode( grp_fu_482_opcode ),
.ce( grp_fu_482_ce ),
.dout( grp_fu_482_p2 )
);
HLS_accel_fmul_32ns_32ns_32_4_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_fmul_32ns_32ns_32_4_max_dsp_U3(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_486_p0 ),
.din1( grp_fu_486_p1 ),
.ce( grp_fu_486_ce ),
.dout( grp_fu_486_p2 )
);
HLS_accel_fmul_32ns_32ns_32_4_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 4 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 32 ))
HLS_accel_fmul_32ns_32ns_32_4_max_dsp_U4(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_492_p0 ),
.din1( grp_fu_492_p1 ),
.ce( grp_fu_492_ce ),
.dout( grp_fu_492_p2 )
);
HLS_accel_fptrunc_64ns_32_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 64 ),
.dout_WIDTH( 32 ))
HLS_accel_fptrunc_64ns_32_1_U5(
.din0( grp_fu_496_p0 ),
.dout( grp_fu_496_p1 )
);
HLS_accel_fpext_32ns_64_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
HLS_accel_fpext_32ns_64_1_U6(
.din0( grp_fu_499_p0 ),
.dout( grp_fu_499_p1 )
);
HLS_accel_fpext_32ns_64_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
HLS_accel_fpext_32ns_64_1_U7(
.din0( grp_fu_504_p0 ),
.dout( grp_fu_504_p1 )
);
HLS_accel_fpext_32ns_64_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.dout_WIDTH( 64 ))
HLS_accel_fpext_32ns_64_1_U8(
.din0( tmp_24_fu_507_p0 ),
.dout( tmp_24_fu_507_p1 )
);
HLS_accel_fcmp_32ns_32ns_1_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
HLS_accel_fcmp_32ns_32ns_1_1_U9(
.din0( grp_fu_510_p0 ),
.din1( grp_fu_510_p1 ),
.opcode( grp_fu_510_opcode ),
.dout( grp_fu_510_p2 )
);
HLS_accel_fcmp_32ns_32ns_1_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
HLS_accel_fcmp_32ns_32ns_1_1_U10(
.din0( grp_fu_515_p0 ),
.din1( grp_fu_515_p1 ),
.opcode( grp_fu_515_opcode ),
.dout( grp_fu_515_p2 )
);
HLS_accel_fcmp_32ns_32ns_1_1 #(
.ID( 1 ),
.NUM_STAGE( 1 ),
.din0_WIDTH( 32 ),
.din1_WIDTH( 32 ),
.dout_WIDTH( 1 ))
HLS_accel_fcmp_32ns_32ns_1_1_U11(
.din0( grp_fu_520_p0 ),
.din1( grp_fu_520_p1 ),
.opcode( grp_fu_520_opcode ),
.dout( grp_fu_520_p2 )
);
HLS_accel_dadd_64ns_64ns_64_5_full_dsp #(
.ID( 1 ),
.NUM_STAGE( 5 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
HLS_accel_dadd_64ns_64ns_64_5_full_dsp_U12(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_527_p0 ),
.din1( grp_fu_527_p1 ),
.ce( grp_fu_527_ce ),
.dout( grp_fu_527_p2 )
);
HLS_accel_dmul_64ns_64ns_64_6_max_dsp #(
.ID( 1 ),
.NUM_STAGE( 6 ),
.din0_WIDTH( 64 ),
.din1_WIDTH( 64 ),
.dout_WIDTH( 64 ))
HLS_accel_dmul_64ns_64ns_64_6_max_dsp_U13(
.clk( ap_clk ),
.reset( ap_rst_n_inv ),
.din0( grp_fu_532_p0 ),
.din1( grp_fu_532_p1 ),
.ce( grp_fu_532_ce ),
.dout( grp_fu_532_p2 )
);
/// the current state (ap_CS_fsm) of the state machine. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_CS_fsm
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_st1_fsm_0;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
/// ap_reg_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ioackin_OUTPUT_STREAM_TREADY
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_logic_1 == OUTPUT_STREAM_TREADY))) begin
ap_reg_ioackin_OUTPUT_STREAM_TREADY <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp2_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & ~(ap_const_lv1_0 == exitcond_flatten1_fu_1241_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
ap_reg_ppiten_pp2_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp2_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it1
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it1 <= ap_reg_ppiten_pp2_it0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
ap_reg_ppiten_pp2_it1 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it10 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it10
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it10 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it10 <= ap_reg_ppiten_pp2_it9;
end
end
end
/// ap_reg_ppiten_pp2_it11 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it11
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it11 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it11 <= ap_reg_ppiten_pp2_it10;
end
end
end
/// ap_reg_ppiten_pp2_it12 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it12
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it12 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it12 <= ap_reg_ppiten_pp2_it11;
end
end
end
/// ap_reg_ppiten_pp2_it13 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it13
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it13 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it13 <= ap_reg_ppiten_pp2_it12;
end
end
end
/// ap_reg_ppiten_pp2_it14 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it14
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it14 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it14 <= ap_reg_ppiten_pp2_it13;
end
end
end
/// ap_reg_ppiten_pp2_it15 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it15
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it15 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it15 <= ap_reg_ppiten_pp2_it14;
end
end
end
/// ap_reg_ppiten_pp2_it16 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it16
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it16 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it16 <= ap_reg_ppiten_pp2_it15;
end
end
end
/// ap_reg_ppiten_pp2_it17 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it17
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it17 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it17 <= ap_reg_ppiten_pp2_it16;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
ap_reg_ppiten_pp2_it17 <= ap_const_logic_0;
end
end
end
/// ap_reg_ppiten_pp2_it2 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it2
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it2 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it2 <= ap_reg_ppiten_pp2_it1;
end
end
end
/// ap_reg_ppiten_pp2_it3 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it3
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it3 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it3 <= ap_reg_ppiten_pp2_it2;
end
end
end
/// ap_reg_ppiten_pp2_it4 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it4
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it4 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it4 <= ap_reg_ppiten_pp2_it3;
end
end
end
/// ap_reg_ppiten_pp2_it5 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it5
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it5 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it5 <= ap_reg_ppiten_pp2_it4;
end
end
end
/// ap_reg_ppiten_pp2_it6 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it6
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it6 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it6 <= ap_reg_ppiten_pp2_it5;
end
end
end
/// ap_reg_ppiten_pp2_it7 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it7
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it7 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it7 <= ap_reg_ppiten_pp2_it6;
end
end
end
/// ap_reg_ppiten_pp2_it8 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it8
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it8 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it8 <= ap_reg_ppiten_pp2_it7;
end
end
end
/// ap_reg_ppiten_pp2_it9 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp2_it9
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp2_it9 <= ap_const_logic_0;
end else begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppiten_pp2_it9 <= ap_reg_ppiten_pp2_it8;
end
end
end
/// ap_reg_ppiten_pp3_it0 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it0
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it17) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & ~(ap_const_lv1_0 == ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it16))) begin
ap_reg_ppiten_pp3_it0 <= ap_const_logic_1;
end
end
end
/// ap_reg_ppiten_pp3_it1 assign process. ///
always @ (posedge ap_clk)
begin : ap_ret_ap_reg_ppiten_pp3_it1
if (ap_rst_n_inv == 1'b1) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end else begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it17) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & ~(ap_const_lv1_0 == ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it16)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2)))) begin
ap_reg_ppiten_pp3_it1 <= ap_const_logic_0;
end
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
exitcond2_i_i1_reg_394 <= ap_const_lv1_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
exitcond2_i_i1_reg_394 <= exitcond2_i_i_reg_1802;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_243 & ~(ap_const_lv1_0 == exitcond_flatten_fu_580_p2))) begin
i1_0_i_reg_361 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_658_p2) & ~ap_sig_bdd_264)) begin
i1_0_i_reg_361 <= i1_0_i_mid2_fu_690_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & ~(ap_const_lv1_0 == exitcond_flatten1_fu_1241_p2))) begin
i4_0_i_reg_449 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
i4_0_i_reg_449 <= i4_0_i_mid2_reg_2096;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_580_p2) & ~ap_sig_bdd_243)) begin
i_0_i_reg_328 <= i_0_i_mid2_fu_612_p3;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
i_0_i_reg_328 <= ap_const_lv6_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
indvar_flatten1_reg_427 <= ap_const_lv10_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
indvar_flatten1_reg_427 <= indvar_flatten_next1_reg_1909;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & ~(ap_const_lv1_0 == exitcond_flatten1_fu_1241_p2))) begin
indvar_flatten2_reg_438 <= ap_const_lv11_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
indvar_flatten2_reg_438 <= indvar_flatten_next2_fu_1539_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_243 & ~(ap_const_lv1_0 == exitcond_flatten_fu_580_p2))) begin
indvar_flatten6_reg_350 <= ap_const_lv11_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_658_p2) & ~ap_sig_bdd_264)) begin
indvar_flatten6_reg_350 <= indvar_flatten_next7_fu_664_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_580_p2) & ~ap_sig_bdd_243)) begin
indvar_flatten_reg_317 <= indvar_flatten_next_fu_586_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
indvar_flatten_reg_317 <= ap_const_lv11_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_243 & ~(ap_const_lv1_0 == exitcond_flatten_fu_580_p2))) begin
j2_0_i_reg_372 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_658_p2) & ~ap_sig_bdd_264)) begin
j2_0_i_reg_372 <= j_1_fu_730_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & ~(ap_const_lv1_0 == exitcond_flatten1_fu_1241_p2))) begin
j5_0_i_reg_460 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
j5_0_i_reg_460 <= j_2_fu_1628_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_580_p2) & ~ap_sig_bdd_243)) begin
j_0_i_reg_339 <= j_fu_652_p2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0) & ~(ap_start == ap_const_logic_0))) begin
j_0_i_reg_339 <= ap_const_lv6_0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
p_reg_383 <= ap_const_lv6_1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
p_reg_383 <= p_1_reg_1776;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (tmp_37_reg_1708 == ap_const_lv1_0)) | (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
reg_542 <= a_q1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4)) begin
reg_542 <= a_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & (ap_const_lv1_0 == tmp_53_reg_1724))) begin
reg_548 <= a_q0;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
reg_548 <= a_q1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
x_assign_5_reg_416 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
x_assign_5_reg_416 <= x_assign_5_mid2_reg_1682;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
y_assign_s_reg_405 <= ap_const_lv6_0;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
y_assign_s_reg_405 <= q_reg_1756;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)) begin
a_load_reg_1933 <= a_q1;
ap_reg_ppstg_a_load_reg_1933_pp2_it10 <= ap_reg_ppstg_a_load_reg_1933_pp2_it9;
ap_reg_ppstg_a_load_reg_1933_pp2_it11 <= ap_reg_ppstg_a_load_reg_1933_pp2_it10;
ap_reg_ppstg_a_load_reg_1933_pp2_it12 <= ap_reg_ppstg_a_load_reg_1933_pp2_it11;
ap_reg_ppstg_a_load_reg_1933_pp2_it13 <= ap_reg_ppstg_a_load_reg_1933_pp2_it12;
ap_reg_ppstg_a_load_reg_1933_pp2_it14 <= ap_reg_ppstg_a_load_reg_1933_pp2_it13;
ap_reg_ppstg_a_load_reg_1933_pp2_it15 <= ap_reg_ppstg_a_load_reg_1933_pp2_it14;
ap_reg_ppstg_a_load_reg_1933_pp2_it2 <= a_load_reg_1933;
ap_reg_ppstg_a_load_reg_1933_pp2_it3 <= ap_reg_ppstg_a_load_reg_1933_pp2_it2;
ap_reg_ppstg_a_load_reg_1933_pp2_it4 <= ap_reg_ppstg_a_load_reg_1933_pp2_it3;
ap_reg_ppstg_a_load_reg_1933_pp2_it5 <= ap_reg_ppstg_a_load_reg_1933_pp2_it4;
ap_reg_ppstg_a_load_reg_1933_pp2_it6 <= ap_reg_ppstg_a_load_reg_1933_pp2_it5;
ap_reg_ppstg_a_load_reg_1933_pp2_it7 <= ap_reg_ppstg_a_load_reg_1933_pp2_it6;
ap_reg_ppstg_a_load_reg_1933_pp2_it8 <= ap_reg_ppstg_a_load_reg_1933_pp2_it7;
ap_reg_ppstg_a_load_reg_1933_pp2_it9 <= ap_reg_ppstg_a_load_reg_1933_pp2_it8;
ap_reg_ppstg_tmp_10_reg_1693_pp2_it1 <= tmp_10_reg_1693;
ap_reg_ppstg_tmp_10_reg_1693_pp2_it2 <= ap_reg_ppstg_tmp_10_reg_1693_pp2_it1;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it10 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it9;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it11 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it10;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it12 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it11;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it3 <= tmp_15_reg_1983;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it4 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it3;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it5 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it4;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it6 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it5;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it7 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it6;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it8 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it7;
ap_reg_ppstg_tmp_15_reg_1983_pp2_it9 <= ap_reg_ppstg_tmp_15_reg_1983_pp2_it8;
ap_reg_ppstg_tmp_37_reg_1708_pp2_it1 <= tmp_37_reg_1708;
ap_reg_ppstg_tmp_37_reg_1708_pp2_it2 <= ap_reg_ppstg_tmp_37_reg_1708_pp2_it1;
ap_reg_ppstg_tmp_37_reg_1708_pp2_it3 <= ap_reg_ppstg_tmp_37_reg_1708_pp2_it2;
ap_reg_ppstg_tmp_37_reg_1708_pp2_it4 <= ap_reg_ppstg_tmp_37_reg_1708_pp2_it3;
ap_reg_ppstg_tmp_37_reg_1708_pp2_it5 <= ap_reg_ppstg_tmp_37_reg_1708_pp2_it4;
ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it3 <= tmp_41_2_reg_1978;
ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it4 <= ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it3;
ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it5 <= ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it4;
ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it6 <= ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it5;
ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it7 <= ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it6;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it1 <= tmp_53_reg_1724;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it2 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it1;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it3 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it2;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it4 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it3;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it5 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it4;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it6 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it5;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it7 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it6;
ap_reg_ppstg_tmp_53_reg_1724_pp2_it8 <= ap_reg_ppstg_tmp_53_reg_1724_pp2_it7;
ap_reg_ppstg_tmp_71_reg_1928_pp2_it2 <= tmp_71_reg_1928;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[0] <= tmp_84_reg_1740[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[1] <= tmp_84_reg_1740[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[2] <= tmp_84_reg_1740[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[3] <= tmp_84_reg_1740[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[4] <= tmp_84_reg_1740[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[5] <= tmp_84_reg_1740[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[6] <= tmp_84_reg_1740[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[7] <= tmp_84_reg_1740[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[8] <= tmp_84_reg_1740[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[9] <= tmp_84_reg_1740[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[10] <= tmp_84_reg_1740[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[11] <= tmp_84_reg_1740[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[11];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[0] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[0];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[1] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[1];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[2] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[2];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[3] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[3];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[4] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[4];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[5] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[5];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[6] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[6];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[7] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[7];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[8] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[8];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[9] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[9];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[10] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[10];
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[11] <= ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[11];
ap_reg_ppstg_x_assign_9_reg_1918_pp2_it2 <= x_assign_9_reg_1918;
ap_reg_ppstg_x_assign_9_reg_1918_pp2_it3 <= ap_reg_ppstg_x_assign_9_reg_1918_pp2_it2;
ap_reg_ppstg_x_assign_9_reg_1918_pp2_it4 <= ap_reg_ppstg_x_assign_9_reg_1918_pp2_it3;
ap_reg_ppstg_x_assign_9_reg_1918_pp2_it5 <= ap_reg_ppstg_x_assign_9_reg_1918_pp2_it4;
ap_reg_ppstg_x_assign_9_reg_1918_pp2_it6 <= ap_reg_ppstg_x_assign_9_reg_1918_pp2_it5;
p_addr4_cast_reg_1698[5] <= p_addr4_cast_fu_790_p1[5];
p_addr4_cast_reg_1698[6] <= p_addr4_cast_fu_790_p1[6];
p_addr4_cast_reg_1698[7] <= p_addr4_cast_fu_790_p1[7];
p_addr4_cast_reg_1698[8] <= p_addr4_cast_fu_790_p1[8];
p_addr4_cast_reg_1698[9] <= p_addr4_cast_fu_790_p1[9];
p_addr4_cast_reg_1698[10] <= p_addr4_cast_fu_790_p1[10];
p_addr4_cast_reg_1698[11] <= p_addr4_cast_fu_790_p1[11];
p_addr8_cast1_reg_1735[5] <= p_addr8_cast1_fu_844_p1[5];
p_addr8_cast1_reg_1735[6] <= p_addr8_cast1_fu_844_p1[6];
p_addr8_cast1_reg_1735[7] <= p_addr8_cast1_fu_844_p1[7];
p_addr8_cast1_reg_1735[8] <= p_addr8_cast1_fu_844_p1[8];
p_addr8_cast1_reg_1735[9] <= p_addr8_cast1_fu_844_p1[9];
p_addr8_cast1_reg_1735[10] <= p_addr8_cast1_fu_844_p1[10];
sum_2_2_reg_2052 <= grp_fu_496_p1;
tmp_10_reg_1693 <= tmp_9_fu_768_p2[ap_const_lv32_5];
tmp_15_reg_1983 <= grp_fu_472_p2;
tmp_21_reg_1988 <= grp_fu_477_p2;
tmp_24_reg_2072 <= tmp_24_fu_507_p1;
tmp_25_reg_2067 <= grp_fu_504_p1;
tmp_37_reg_1708 <= x_assign_fu_752_p2[ap_const_lv32_5];
tmp_44_0_1_trn_cast_reg_1714[0] <= tmp_44_0_1_trn_cast_fu_813_p1[0];
tmp_44_0_1_trn_cast_reg_1714[1] <= tmp_44_0_1_trn_cast_fu_813_p1[1];
tmp_44_0_1_trn_cast_reg_1714[2] <= tmp_44_0_1_trn_cast_fu_813_p1[2];
tmp_44_0_1_trn_cast_reg_1714[3] <= tmp_44_0_1_trn_cast_fu_813_p1[3];
tmp_44_0_1_trn_cast_reg_1714[4] <= tmp_44_0_1_trn_cast_fu_813_p1[4];
tmp_44_0_1_trn_cast_reg_1714[5] <= tmp_44_0_1_trn_cast_fu_813_p1[5];
tmp_53_reg_1724 <= y_assign_fu_758_p2[ap_const_lv32_5];
tmp_58_reg_1730[5] <= tmp_58_fu_836_p3[5];
tmp_58_reg_1730[6] <= tmp_58_fu_836_p3[6];
tmp_58_reg_1730[7] <= tmp_58_fu_836_p3[7];
tmp_58_reg_1730[8] <= tmp_58_fu_836_p3[8];
tmp_58_reg_1730[9] <= tmp_58_fu_836_p3[9];
tmp_58_reg_1730[10] <= tmp_58_fu_836_p3[10];
tmp_65_reg_1923 <= grp_fu_510_p2;
tmp_71_reg_1928 <= tmp_71_fu_1332_p2;
tmp_84_reg_1740[0] <= tmp_84_fu_854_p1[0];
tmp_84_reg_1740[1] <= tmp_84_fu_854_p1[1];
tmp_84_reg_1740[2] <= tmp_84_fu_854_p1[2];
tmp_84_reg_1740[3] <= tmp_84_fu_854_p1[3];
tmp_84_reg_1740[4] <= tmp_84_fu_854_p1[4];
tmp_84_reg_1740[5] <= tmp_84_fu_854_p1[5];
tmp_84_reg_1740[6] <= tmp_84_fu_854_p1[6];
tmp_84_reg_1740[7] <= tmp_84_fu_854_p1[7];
tmp_84_reg_1740[8] <= tmp_84_fu_854_p1[8];
tmp_84_reg_1740[9] <= tmp_84_fu_854_p1[9];
tmp_84_reg_1740[10] <= tmp_84_fu_854_p1[10];
tmp_84_reg_1740[11] <= tmp_84_fu_854_p1[11];
x_assign_2_reg_1941[19] <= x_assign_2_fu_1361_p3[19];
x_assign_2_reg_1941[22] <= x_assign_2_fu_1361_p3[22];
x_assign_2_reg_1941[23] <= x_assign_2_fu_1361_p3[23];
x_assign_2_reg_1941[25] <= x_assign_2_fu_1361_p3[25];
x_assign_2_reg_1941[30] <= x_assign_2_fu_1361_p3[30];
x_assign_2_reg_1941[31] <= x_assign_2_fu_1361_p3[31];
x_assign_9_reg_1918 <= x_assign_9_fu_1288_p3;
y_assign_1_mid2_reg_1677 <= y_assign_1_mid2_fu_736_p3;
y_assign_reg_1688 <= y_assign_fu_758_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it1 <= exitcond_flatten1_reg_1914;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it10 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it9;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it11 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it10;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it12 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it11;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it13 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it12;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it14 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it13;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it15 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it14;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it16 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it15;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it2 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it1;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it3 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it2;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it4 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it3;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it5 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it4;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it6 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it5;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it7 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it6;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it8 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it7;
ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it9 <= ap_reg_ppstg_exitcond_flatten1_reg_1914_pp2_it8;
ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it3 <= sum_4_i_i_reg_2003;
ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it4 <= ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it3;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it10 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it9;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it11 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it10;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it12 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it11;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it13 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it12;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it3 <= tmp_23_reg_2010;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it4 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it3;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it5 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it4;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it6 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it5;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it7 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it6;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it8 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it7;
ap_reg_ppstg_tmp_23_reg_2010_pp2_it9 <= ap_reg_ppstg_tmp_23_reg_2010_pp2_it8;
ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it2 <= tmp_41_0_2_reg_1973;
ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it3 <= ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it2;
ap_reg_ppstg_tmp_61_reg_1882_pp2_it1 <= tmp_61_reg_1882;
ap_reg_ppstg_tmp_86_reg_1903_pp2_it1 <= tmp_86_reg_1903;
ap_reg_ppstg_x_assign_7_reg_1872_pp2_it1 <= x_assign_7_reg_1872;
ap_reg_ppstg_x_assign_7_reg_1872_pp2_it2 <= ap_reg_ppstg_x_assign_7_reg_1872_pp2_it1;
ap_reg_ppstg_x_assign_7_reg_1872_pp2_it3 <= ap_reg_ppstg_x_assign_7_reg_1872_pp2_it2;
ap_reg_ppstg_x_assign_7_reg_1872_pp2_it4 <= ap_reg_ppstg_x_assign_7_reg_1872_pp2_it3;
exitcond_flatten1_reg_1914 <= exitcond_flatten1_fu_1241_p2;
or_cond_i8_reg_1897 <= or_cond_i8_fu_1224_p2;
sum_4_i_i_reg_2003 <= sum_4_i_i_fu_1501_p3;
tmp_19_reg_2057 <= grp_fu_492_p2;
tmp_20_reg_2062 <= grp_fu_477_p2;
tmp_23_reg_2010 <= grp_fu_486_p2;
tmp_36_reg_1887 <= grp_fu_499_p1;
tmp_42_2_2_reg_2047 <= grp_fu_504_p1;
tmp_55_reg_1877 <= grp_fu_510_p2;
tmp_86_reg_1903 <= tmp_86_fu_1229_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4)) begin
ap_reg_ppstg_sum_1_1_2_reg_2031_pp2_it8 <= sum_1_1_2_reg_2031;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it3 <= tmp_41_2_2_reg_1993;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it4 <= ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it3;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it5 <= ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it4;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it6 <= ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it5;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it7 <= ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it6;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it8 <= ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it7;
ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it9 <= ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it8;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it2 <= x_assign_1_reg_1948;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it3 <= ap_reg_ppstg_x_assign_1_reg_1948_pp2_it2;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it4 <= ap_reg_ppstg_x_assign_1_reg_1948_pp2_it3;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it5 <= ap_reg_ppstg_x_assign_1_reg_1948_pp2_it4;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it6 <= ap_reg_ppstg_x_assign_1_reg_1948_pp2_it5;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it7 <= ap_reg_ppstg_x_assign_1_reg_1948_pp2_it6;
ap_reg_ppstg_x_assign_1_reg_1948_pp2_it8 <= ap_reg_ppstg_x_assign_1_reg_1948_pp2_it7;
b_load_reg_1796 <= b_q0;
p_addr4_reg_1786 <= p_addr4_fu_927_p2;
p_addr8_reg_1791 <= p_addr8_fu_932_p2;
p_addr_reg_1771 <= p_addr_fu_895_p2;
sum_1_1_2_reg_2031 <= grp_fu_477_p2;
sum_4_i_i_0_2_reg_2020 <= sum_4_i_i_0_2_fu_1515_p3;
sum_4_i_i_1_reg_2026 <= sum_4_i_i_1_fu_1521_p3;
tmp_26_reg_2077 <= grp_fu_532_p2;
tmp_41_2_2_reg_1993 <= tmp_41_2_2_fu_1486_p3;
tmp_92_reg_1953 <= grp_fu_510_p2;
x_assign_1_reg_1948 <= x_assign_1_fu_1410_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)) begin
ap_reg_ppstg_tmp_14_reg_1968_pp2_it10 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it9;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it11 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it10;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it12 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it11;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it2 <= tmp_14_reg_1968;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it3 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it2;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it4 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it3;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it5 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it4;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it6 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it5;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it7 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it6;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it8 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it7;
ap_reg_ppstg_tmp_14_reg_1968_pp2_it9 <= ap_reg_ppstg_tmp_14_reg_1968_pp2_it8;
ap_reg_ppstg_tmp_46_reg_1842_pp2_it1 <= tmp_46_reg_1842;
ap_reg_ppstg_x_assign_3_reg_1837_pp2_it1 <= x_assign_3_reg_1837;
ap_reg_ppstg_x_assign_3_reg_1837_pp2_it2 <= ap_reg_ppstg_x_assign_3_reg_1837_pp2_it1;
sum_4_i_i_2_reg_2042 <= sum_4_i_i_2_fu_1527_p3;
tmp_14_reg_1968 <= grp_fu_486_p2;
tmp_94_reg_1867 <= tmp_94_fu_1093_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) begin
ap_reg_ppstg_tmp_30_reg_1807_pp2_it1 <= tmp_30_reg_1807;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[19] <= x_assign_4_reg_1958[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[22] <= x_assign_4_reg_1958[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[23] <= x_assign_4_reg_1958[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[25] <= x_assign_4_reg_1958[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[30] <= x_assign_4_reg_1958[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[31] <= x_assign_4_reg_1958[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[31];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[19] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[19];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[22] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[22];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[23] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[23];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[25] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[25];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[30] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[30];
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[31] <= ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[31];
tmp_28_reg_2082 <= grp_fu_496_p1;
tmp_75_reg_1832 <= grp_fu_520_p2;
x_assign_4_reg_1958[19] <= x_assign_4_fu_1458_p3[19];
x_assign_4_reg_1958[22] <= x_assign_4_fu_1458_p3[22];
x_assign_4_reg_1958[23] <= x_assign_4_fu_1458_p3[23];
x_assign_4_reg_1958[25] <= x_assign_4_fu_1458_p3[25];
x_assign_4_reg_1958[30] <= x_assign_4_fu_1458_p3[30];
x_assign_4_reg_1958[31] <= x_assign_4_fu_1458_p3[31];
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0))) begin
exitcond2_i_i_reg_1802 <= exitcond2_i_i_fu_938_p2;
p_1_reg_1776 <= p_1_fu_900_p2;
q_reg_1756 <= q_fu_862_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)))) begin
exitcond_flatten2_reg_2087 <= exitcond_flatten2_fu_1533_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
i4_0_i_mid2_reg_2096 <= i4_0_i_mid2_fu_1565_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
indvar_flatten_next1_reg_1909 <= indvar_flatten_next1_fu_1235_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & (ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
last_assign_reg_2106 <= last_assign_fu_1622_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_lv1_0 == tmp_53_reg_1724))) begin
p_addr2_reg_1781 <= p_addr2_fu_921_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (ap_const_lv1_0 == tmp_53_reg_1724)))) begin
reg_555 <= a_q0;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_10_reg_1693_pp2_it1)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_1708_pp2_it1)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_1724_pp2_it1)) | (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
reg_560 <= grp_fu_532_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) | (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_10_reg_1693_pp2_it2)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_1708_pp2_it4)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_1724_pp2_it8)))) begin
reg_564 <= grp_fu_527_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_1708_pp2_it3)))) begin
reg_569 <= grp_fu_472_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) | (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
reg_574 <= grp_fu_482_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (ap_const_lv1_0 == tmp_10_reg_1693))) begin
tmp_30_reg_1807 <= tmp_30_fu_980_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_10_reg_1693_pp2_it1))) begin
tmp_31_reg_1963 <= tmp_31_fu_1465_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & (ap_const_lv1_0 == tmp_53_reg_1724))) begin
tmp_33_reg_1852 <= grp_fu_499_p1;
tmp_50_reg_1847 <= grp_fu_515_p2;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (tmp_37_reg_1708 == ap_const_lv1_0))) begin
tmp_39_reg_1812 <= grp_fu_515_p2;
tmp_8_reg_1817 <= grp_fu_499_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_1708_pp2_it1))) begin
tmp_41_0_2_reg_1973 <= tmp_41_0_2_fu_1472_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_1724_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
tmp_41_2_reg_1978 <= tmp_41_2_fu_1479_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_1708_pp2_it3))) begin
tmp_42_0_2_reg_2015 <= grp_fu_499_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_1724_pp2_it7))) begin
tmp_42_2_reg_2037 <= grp_fu_504_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((tmp_37_reg_1708 == ap_const_lv1_0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
tmp_46_reg_1842 <= tmp_46_fu_1079_p2;
x_assign_3_reg_1837 <= x_assign_3_fu_1035_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_lv1_0 == tmp_53_reg_1724) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
tmp_61_reg_1882 <= tmp_61_fu_1183_p2;
x_assign_7_reg_1872 <= x_assign_7_fu_1139_p3;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_lv1_0 == tmp_10_reg_1693))) begin
tmp_reg_1751 <= grp_fu_499_p1;
end
end
/// assign process. ///
always @(posedge ap_clk)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
x_assign_5_mid2_reg_1682 <= x_assign_5_mid2_fu_744_p3;
end
end
/// INPUT_STREAM_TREADY assign process. ///
always @ (exitcond_flatten_fu_580_p2 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_243 or exitcond_flatten8_fu_658_p2 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_bdd_264)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_580_p2) & ~ap_sig_bdd_243) | ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_658_p2) & ~ap_sig_bdd_264))) begin
INPUT_STREAM_TREADY = ap_const_logic_1;
end else begin
INPUT_STREAM_TREADY = ap_const_logic_0;
end
end
/// OUTPUT_STREAM_TVALID assign process. ///
always @ (exitcond_flatten2_reg_2087 or ap_sig_cseq_ST_pp3_stg0_fsm_8 or ap_reg_ppiten_pp3_it1 or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1) & (ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY))) begin
OUTPUT_STREAM_TVALID = ap_const_logic_1;
end else begin
OUTPUT_STREAM_TVALID = ap_const_logic_0;
end
end
/// a_address0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_sig_cseq_ST_st2_fsm_1 or tmp_4_fu_647_p1 or tmp_12_fu_800_p1 or tmp_63_fu_890_p1 or tmp_78_fu_990_p1 or tmp_83_fu_1089_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1)) begin
a_address0 = tmp_4_fu_647_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
a_address0 = tmp_83_fu_1089_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
a_address0 = tmp_78_fu_990_p1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0))) begin
a_address0 = tmp_63_fu_890_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
a_address0 = tmp_12_fu_800_p1;
end else begin
a_address0 = 'bx;
end
end
/// a_address1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or tmp_84_reg_1740 or tmp_34_fu_823_p1 or tmp_41_fu_876_p1 or tmp_73_fu_986_p1 or tmp_81_fu_1085_p1)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
a_address1 = tmp_84_reg_1740;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)) begin
a_address1 = tmp_81_fu_1085_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) begin
a_address1 = tmp_73_fu_986_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4)) begin
a_address1 = tmp_41_fu_876_p1;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)) begin
a_address1 = tmp_34_fu_823_p1;
end else begin
a_address1 = 'bx;
end
end else begin
a_address1 = 'bx;
end
end
/// a_ce0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_243)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & ~ap_sig_bdd_243) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
a_ce0 = ap_const_logic_1;
end else begin
a_ce0 = ap_const_logic_0;
end
end
/// a_ce1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)) | ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
a_ce1 = ap_const_logic_1;
end else begin
a_ce1 = ap_const_logic_0;
end
end
/// a_we0 assign process. ///
always @ (exitcond_flatten_fu_580_p2 or ap_sig_cseq_ST_st2_fsm_1 or ap_sig_bdd_243)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st2_fsm_1) & (ap_const_lv1_0 == exitcond_flatten_fu_580_p2) & ~ap_sig_bdd_243)) begin
a_we0 = ap_const_logic_1;
end else begin
a_we0 = ap_const_logic_0;
end
end
/// ap_done assign process. ///
always @ (ap_sig_cseq_ST_st95_fsm_9)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st95_fsm_9)) begin
ap_done = ap_const_logic_1;
end else begin
ap_done = ap_const_logic_0;
end
end
/// ap_idle assign process. ///
always @ (ap_start or ap_sig_cseq_ST_st1_fsm_0)
begin
if ((~(ap_const_logic_1 == ap_start) & (ap_const_logic_1 == ap_sig_cseq_ST_st1_fsm_0))) begin
ap_idle = ap_const_logic_1;
end else begin
ap_idle = ap_const_logic_0;
end
end
/// ap_ready assign process. ///
always @ (ap_sig_cseq_ST_st95_fsm_9)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st95_fsm_9)) begin
ap_ready = ap_const_logic_1;
end else begin
ap_ready = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp2_stg0_fsm_3 assign process. ///
always @ (ap_sig_bdd_204)
begin
if (ap_sig_bdd_204) begin
ap_sig_cseq_ST_pp2_stg0_fsm_3 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp2_stg0_fsm_3 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp2_stg1_fsm_4 assign process. ///
always @ (ap_sig_bdd_112)
begin
if (ap_sig_bdd_112) begin
ap_sig_cseq_ST_pp2_stg1_fsm_4 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp2_stg1_fsm_4 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp2_stg2_fsm_5 assign process. ///
always @ (ap_sig_bdd_156)
begin
if (ap_sig_bdd_156) begin
ap_sig_cseq_ST_pp2_stg2_fsm_5 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp2_stg2_fsm_5 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp2_stg3_fsm_6 assign process. ///
always @ (ap_sig_bdd_167)
begin
if (ap_sig_bdd_167) begin
ap_sig_cseq_ST_pp2_stg3_fsm_6 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp2_stg3_fsm_6 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp2_stg4_fsm_7 assign process. ///
always @ (ap_sig_bdd_179)
begin
if (ap_sig_bdd_179) begin
ap_sig_cseq_ST_pp2_stg4_fsm_7 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp2_stg4_fsm_7 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_pp3_stg0_fsm_8 assign process. ///
always @ (ap_sig_bdd_617)
begin
if (ap_sig_bdd_617) begin
ap_sig_cseq_ST_pp3_stg0_fsm_8 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_pp3_stg0_fsm_8 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st1_fsm_0 assign process. ///
always @ (ap_sig_bdd_51)
begin
if (ap_sig_bdd_51) begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st1_fsm_0 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st2_fsm_1 assign process. ///
always @ (ap_sig_bdd_238)
begin
if (ap_sig_bdd_238) begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st2_fsm_1 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st3_fsm_2 assign process. ///
always @ (ap_sig_bdd_260)
begin
if (ap_sig_bdd_260) begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st3_fsm_2 = ap_const_logic_0;
end
end
/// ap_sig_cseq_ST_st95_fsm_9 assign process. ///
always @ (ap_sig_bdd_1567)
begin
if (ap_sig_bdd_1567) begin
ap_sig_cseq_ST_st95_fsm_9 = ap_const_logic_1;
end else begin
ap_sig_cseq_ST_st95_fsm_9 = ap_const_logic_0;
end
end
/// ap_sig_ioackin_OUTPUT_STREAM_TREADY assign process. ///
always @ (OUTPUT_STREAM_TREADY or ap_reg_ioackin_OUTPUT_STREAM_TREADY)
begin
if ((ap_const_logic_0 == ap_reg_ioackin_OUTPUT_STREAM_TREADY)) begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = OUTPUT_STREAM_TREADY;
end else begin
ap_sig_ioackin_OUTPUT_STREAM_TREADY = ap_const_logic_1;
end
end
/// b_address0 assign process. ///
always @ (ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_sig_cseq_ST_st3_fsm_2 or tmp_84_fu_854_p1 or tmp_7_fu_725_p1)
begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2)) begin
b_address0 = tmp_7_fu_725_p1;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
b_address0 = tmp_84_fu_854_p1;
end else begin
b_address0 = 'bx;
end
end
/// b_ce0 assign process. ///
always @ (ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_bdd_264)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & ~ap_sig_bdd_264) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)))) begin
b_ce0 = ap_const_logic_1;
end else begin
b_ce0 = ap_const_logic_0;
end
end
/// b_we0 assign process. ///
always @ (exitcond_flatten8_fu_658_p2 or ap_sig_cseq_ST_st3_fsm_2 or ap_sig_bdd_264)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_st3_fsm_2) & (ap_const_lv1_0 == exitcond_flatten8_fu_658_p2) & ~ap_sig_bdd_264)) begin
b_we0 = ap_const_logic_1;
end else begin
b_we0 = ap_const_logic_0;
end
end
/// exitcond2_i_i1_phi_fu_398_p4 assign process. ///
always @ (exitcond2_i_i1_reg_394 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or exitcond2_i_i_reg_1802 or exitcond_flatten1_reg_1914)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
exitcond2_i_i1_phi_fu_398_p4 = exitcond2_i_i_reg_1802;
end else begin
exitcond2_i_i1_phi_fu_398_p4 = exitcond2_i_i1_reg_394;
end
end
/// grp_fu_472_opcode assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it5 or ap_reg_ppiten_pp2_it8 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_reg_ppstg_tmp_37_reg_1708_pp2_it2 or ap_reg_ppstg_tmp_53_reg_1724_pp2_it5)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1))) begin
grp_fu_472_opcode = ap_const_lv2_1;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it8) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_37_reg_1708_pp2_it2)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5) & (ap_const_lv1_0 == ap_reg_ppstg_tmp_53_reg_1724_pp2_it5)))) begin
grp_fu_472_opcode = ap_const_lv2_0;
end else begin
grp_fu_472_opcode = 'bx;
end
end
/// grp_fu_472_p0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it5 or ap_reg_ppiten_pp2_it8 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or sum_4_i_i_reg_2003 or sum_4_i_i_0_2_reg_2020 or sum_4_i_i_2_reg_2042)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it8) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
grp_fu_472_p0 = sum_4_i_i_2_reg_2042;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_472_p0 = sum_4_i_i_0_2_reg_2020;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_472_p0 = sum_4_i_i_reg_2003;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1))) begin
grp_fu_472_p0 = ap_const_lv32_3F800000;
end else begin
grp_fu_472_p0 = 'bx;
end
end
/// grp_fu_472_p1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it3 or ap_reg_ppiten_pp2_it5 or ap_reg_ppiten_pp2_it8 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_reg_ppstg_x_assign_3_reg_1837_pp2_it2 or ap_reg_ppstg_x_assign_7_reg_1872_pp2_it4 or a_load_reg_1933 or ap_reg_ppstg_x_assign_1_reg_1948_pp2_it8)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it8) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
grp_fu_472_p1 = ap_reg_ppstg_x_assign_1_reg_1948_pp2_it8;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it5) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_472_p1 = ap_reg_ppstg_x_assign_7_reg_1872_pp2_it4;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it3) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_472_p1 = ap_reg_ppstg_x_assign_3_reg_1837_pp2_it2;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1))) begin
grp_fu_472_p1 = a_load_reg_1933;
end else begin
grp_fu_472_p1 = 'bx;
end
end
/// grp_fu_477_opcode assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp2_it13 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg0_fsm_3)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it13) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_477_opcode = ap_const_lv2_1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)))) begin
grp_fu_477_opcode = ap_const_lv2_0;
end else begin
grp_fu_477_opcode = 'bx;
end
end
/// grp_fu_477_p0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp2_it13 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or a_load_reg_1933 or sum_4_i_i_1_reg_2026 or tmp_19_reg_2057)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it13) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_477_p0 = tmp_19_reg_2057;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_477_p0 = sum_4_i_i_1_reg_2026;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1))) begin
grp_fu_477_p0 = a_load_reg_1933;
end else begin
grp_fu_477_p0 = 'bx;
end
end
/// grp_fu_477_p1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it6 or ap_reg_ppiten_pp2_it13 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_reg_ppstg_x_assign_9_reg_1918_pp2_it6 or ap_reg_ppstg_tmp_14_reg_1968_pp2_it12)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it13) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_477_p1 = ap_reg_ppstg_tmp_14_reg_1968_pp2_it12;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it6) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_477_p1 = ap_reg_ppstg_x_assign_9_reg_1918_pp2_it6;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1))) begin
grp_fu_477_p1 = ap_const_lv32_3F800000;
end else begin
grp_fu_477_p1 = 'bx;
end
end
/// grp_fu_482_opcode assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it11 or ap_reg_ppiten_pp2_it14 or ap_sig_cseq_ST_pp2_stg0_fsm_3)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it14) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_482_opcode = ap_const_lv2_1;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11))) begin
grp_fu_482_opcode = ap_const_lv2_0;
end else begin
grp_fu_482_opcode = 'bx;
end
end
/// grp_fu_482_p0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it11 or ap_reg_ppiten_pp2_it14 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10 or tmp_20_reg_2062)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it14) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_482_p0 = tmp_20_reg_2062;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11))) begin
grp_fu_482_p0 = ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10;
end else begin
grp_fu_482_p0 = 'bx;
end
end
/// grp_fu_482_p1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it11 or ap_reg_ppiten_pp2_it14 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_reg_ppstg_tmp_23_reg_2010_pp2_it13 or sum_2_2_reg_2052)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it14) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_482_p1 = ap_reg_ppstg_tmp_23_reg_2010_pp2_it13;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it11))) begin
grp_fu_482_p1 = sum_2_2_reg_2052;
end else begin
grp_fu_482_p1 = 'bx;
end
end
/// grp_fu_486_p0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it2 or a_q1 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or tmp_21_reg_1988)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2))) begin
grp_fu_486_p0 = tmp_21_reg_1988;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_486_p0 = a_q1;
end else begin
grp_fu_486_p0 = 'bx;
end
end
/// grp_fu_486_p1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it2 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or output_i_fu_1493_p3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it2))) begin
grp_fu_486_p1 = output_i_fu_1493_p3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_486_p1 = ap_const_lv32_41200000;
end else begin
grp_fu_486_p1 = 'bx;
end
end
/// grp_fu_499_p0 assign process. ///
always @ (a_q0 or ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it4 or a_q1 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or sum_4_i_i_0_1_fu_1508_p3)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it4) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_499_p0 = sum_4_i_i_0_1_fu_1508_p3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_499_p0 = a_q1;
end else if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it0)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
grp_fu_499_p0 = a_q0;
end else begin
grp_fu_499_p0 = 'bx;
end
end
/// grp_fu_504_p0 assign process. ///
always @ (ap_reg_ppiten_pp2_it7 or ap_reg_ppiten_pp2_it9 or ap_reg_ppiten_pp2_it15 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or reg_569 or reg_574 or sum_1_1_2_reg_2031)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it15) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_504_p0 = reg_574;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it9) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
grp_fu_504_p0 = reg_569;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_504_p0 = sum_1_1_2_reg_2031;
end else begin
grp_fu_504_p0 = 'bx;
end
end
/// grp_fu_510_p0 assign process. ///
always @ (reg_542 or ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or reg_548 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or x_assign_2_reg_1941)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it1))) begin
grp_fu_510_p0 = x_assign_2_reg_1941;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_510_p0 = reg_548;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
grp_fu_510_p0 = reg_542;
end else begin
grp_fu_510_p0 = 'bx;
end
end
/// grp_fu_515_p0 assign process. ///
always @ (ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or reg_548 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or reg_555 or ap_sig_cseq_ST_pp2_stg0_fsm_3)
begin
if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
grp_fu_515_p0 = reg_555;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)))) begin
grp_fu_515_p0 = reg_548;
end else begin
grp_fu_515_p0 = 'bx;
end
end
/// grp_fu_520_p1 assign process. ///
always @ (ap_reg_ppiten_pp2_it0 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7)
begin
if ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0)) begin
if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) begin
grp_fu_520_p1 = ap_const_lv32_40800000;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)) begin
grp_fu_520_p1 = ap_const_lv32_40E00000;
end else if ((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) begin
grp_fu_520_p1 = ap_const_lv32_0;
end else begin
grp_fu_520_p1 = 'bx;
end
end else begin
grp_fu_520_p1 = 'bx;
end
end
/// grp_fu_527_p0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it4 or ap_reg_ppiten_pp2_it7 or ap_reg_ppiten_pp2_it10 or ap_reg_ppiten_pp2_it16 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or tmp_31_reg_1963 or tmp_42_0_2_reg_2015 or tmp_42_2_reg_2037 or tmp_42_2_2_reg_2047 or tmp_24_reg_2072)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it16) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_527_p0 = tmp_24_reg_2072;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_527_p0 = tmp_42_2_2_reg_2047;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
grp_fu_527_p0 = tmp_42_2_reg_2037;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it4))) begin
grp_fu_527_p0 = tmp_42_0_2_reg_2015;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
grp_fu_527_p0 = tmp_31_reg_1963;
end else begin
grp_fu_527_p0 = 'bx;
end
end
/// grp_fu_527_p1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it4 or ap_reg_ppiten_pp2_it7 or ap_reg_ppiten_pp2_it10 or ap_reg_ppiten_pp2_it16 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it3 or ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it7 or ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it9 or tmp_26_reg_2077)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it16) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_527_p1 = tmp_26_reg_2077;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it10) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_527_p1 = ap_reg_ppstg_tmp_41_2_2_reg_1993_pp2_it9;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it7) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
grp_fu_527_p1 = ap_reg_ppstg_tmp_41_2_reg_1978_pp2_it7;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it4))) begin
grp_fu_527_p1 = ap_reg_ppstg_tmp_41_0_2_reg_1973_pp2_it3;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
grp_fu_527_p1 = ap_const_lv64_0;
end else begin
grp_fu_527_p1 = 'bx;
end
end
/// grp_fu_532_p0 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it15 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or tmp_reg_1751 or tmp_8_reg_1817 or tmp_33_reg_1852 or tmp_36_reg_1887 or tmp_25_reg_2067)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it15))) begin
grp_fu_532_p0 = tmp_25_reg_2067;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3))) begin
grp_fu_532_p0 = tmp_36_reg_1887;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7))) begin
grp_fu_532_p0 = tmp_33_reg_1852;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
grp_fu_532_p0 = tmp_8_reg_1817;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5))) begin
grp_fu_532_p0 = tmp_reg_1751;
end else begin
grp_fu_532_p0 = 'bx;
end
end
/// grp_fu_532_p1 assign process. ///
always @ (ap_sig_cseq_ST_pp2_stg1_fsm_4 or ap_reg_ppiten_pp2_it0 or ap_reg_ppiten_pp2_it1 or ap_reg_ppiten_pp2_it15 or ap_sig_cseq_ST_pp2_stg2_fsm_5 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or ap_sig_cseq_ST_pp2_stg0_fsm_3)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg1_fsm_4) & (ap_const_logic_1 == ap_reg_ppiten_pp2_it15))) begin
grp_fu_532_p1 = ap_const_lv64_3F847AE147AE147B;
end else if ((((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg2_fsm_5)) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it0) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
grp_fu_532_p1 = ap_const_lv64_3FE6A09EDBF8B9BB;
end else begin
grp_fu_532_p1 = 'bx;
end
end
/// i4_0_i_phi_fu_453_p4 assign process. ///
always @ (i4_0_i_reg_449 or exitcond_flatten2_reg_2087 or ap_sig_cseq_ST_pp3_stg0_fsm_8 or ap_reg_ppiten_pp3_it1 or i4_0_i_mid2_reg_2096)
begin
if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1))) begin
i4_0_i_phi_fu_453_p4 = i4_0_i_mid2_reg_2096;
end else begin
i4_0_i_phi_fu_453_p4 = i4_0_i_reg_449;
end
end
/// indvar_flatten1_phi_fu_431_p4 assign process. ///
always @ (indvar_flatten1_reg_427 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg4_fsm_7 or indvar_flatten_next1_reg_1909 or exitcond_flatten1_reg_1914)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg4_fsm_7) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
indvar_flatten1_phi_fu_431_p4 = indvar_flatten_next1_reg_1909;
end else begin
indvar_flatten1_phi_fu_431_p4 = indvar_flatten1_reg_427;
end
end
/// out_address0 assign process. ///
always @ (ap_reg_ppiten_pp2_it17 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or ap_reg_ppstg_tmp_84_reg_1740_pp2_it17 or ap_sig_cseq_ST_pp3_stg0_fsm_8 or ap_reg_ppiten_pp3_it0 or tmp_97_fu_1617_p1)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it17) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
out_address0 = ap_reg_ppstg_tmp_84_reg_1740_pp2_it17;
end else if (((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0))) begin
out_address0 = tmp_97_fu_1617_p1;
end else begin
out_address0 = 'bx;
end
end
/// out_ce0 assign process. ///
always @ (ap_reg_ppiten_pp2_it17 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or exitcond_flatten2_reg_2087 or ap_sig_cseq_ST_pp3_stg0_fsm_8 or ap_reg_ppiten_pp3_it0 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp3_it1)
begin
if ((((ap_const_logic_1 == ap_sig_cseq_ST_pp3_stg0_fsm_8) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1))) | ((ap_const_logic_1 == ap_reg_ppiten_pp2_it17) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6)))) begin
out_ce0 = ap_const_logic_1;
end else begin
out_ce0 = ap_const_logic_0;
end
end
/// out_we0 assign process. ///
always @ (ap_reg_ppiten_pp2_it17 or ap_sig_cseq_ST_pp2_stg3_fsm_6)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it17) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6))) begin
out_we0 = ap_const_logic_1;
end else begin
out_we0 = ap_const_logic_0;
end
end
/// p_phi_fu_387_p4 assign process. ///
always @ (p_reg_383 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or p_1_reg_1776 or exitcond_flatten1_reg_1914)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
p_phi_fu_387_p4 = p_1_reg_1776;
end else begin
p_phi_fu_387_p4 = p_reg_383;
end
end
/// x_assign_5_phi_fu_420_p4 assign process. ///
always @ (x_assign_5_reg_416 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or x_assign_5_mid2_reg_1682 or exitcond_flatten1_reg_1914)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
x_assign_5_phi_fu_420_p4 = x_assign_5_mid2_reg_1682;
end else begin
x_assign_5_phi_fu_420_p4 = x_assign_5_reg_416;
end
end
/// y_assign_s_phi_fu_409_p4 assign process. ///
always @ (y_assign_s_reg_405 or ap_reg_ppiten_pp2_it1 or ap_sig_cseq_ST_pp2_stg0_fsm_3 or q_reg_1756 or exitcond_flatten1_reg_1914)
begin
if (((ap_const_logic_1 == ap_reg_ppiten_pp2_it1) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg0_fsm_3) & (ap_const_lv1_0 == exitcond_flatten1_reg_1914))) begin
y_assign_s_phi_fu_409_p4 = q_reg_1756;
end else begin
y_assign_s_phi_fu_409_p4 = y_assign_s_reg_405;
end
end
/// the next state (ap_NS_fsm) of the state machine. ///
always @ (ap_start or ap_CS_fsm or ap_reg_ppiten_pp2_it16 or ap_reg_ppiten_pp2_it17 or ap_sig_cseq_ST_pp2_stg3_fsm_6 or exitcond_flatten_fu_580_p2 or ap_sig_bdd_243 or exitcond_flatten8_fu_658_p2 or ap_sig_bdd_264 or exitcond_flatten2_fu_1533_p2 or exitcond_flatten2_reg_2087 or ap_reg_ppiten_pp3_it0 or ap_sig_ioackin_OUTPUT_STREAM_TREADY or ap_reg_ppiten_pp3_it1)
begin
case (ap_CS_fsm)
ap_ST_st1_fsm_0 :
begin
if (~(ap_start == ap_const_logic_0)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
end
ap_ST_st2_fsm_1 :
begin
if (((ap_const_lv1_0 == exitcond_flatten_fu_580_p2) & ~ap_sig_bdd_243)) begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end else if ((~ap_sig_bdd_243 & ~(ap_const_lv1_0 == exitcond_flatten_fu_580_p2))) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else begin
ap_NS_fsm = ap_ST_st2_fsm_1;
end
end
ap_ST_st3_fsm_2 :
begin
if (((ap_const_lv1_0 == exitcond_flatten8_fu_658_p2) & ~ap_sig_bdd_264)) begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end else if ((~ap_sig_bdd_264 & ~(ap_const_lv1_0 == exitcond_flatten8_fu_658_p2))) begin
ap_NS_fsm = ap_ST_pp2_stg0_fsm_3;
end else begin
ap_NS_fsm = ap_ST_st3_fsm_2;
end
end
ap_ST_pp2_stg0_fsm_3 :
begin
ap_NS_fsm = ap_ST_pp2_stg1_fsm_4;
end
ap_ST_pp2_stg1_fsm_4 :
begin
ap_NS_fsm = ap_ST_pp2_stg2_fsm_5;
end
ap_ST_pp2_stg2_fsm_5 :
begin
ap_NS_fsm = ap_ST_pp2_stg3_fsm_6;
end
ap_ST_pp2_stg3_fsm_6 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp2_it17) & (ap_const_logic_1 == ap_sig_cseq_ST_pp2_stg3_fsm_6) & ~(ap_const_logic_1 == ap_reg_ppiten_pp2_it16))) begin
ap_NS_fsm = ap_ST_pp2_stg4_fsm_7;
end else begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_8;
end
end
ap_ST_pp2_stg4_fsm_7 :
begin
ap_NS_fsm = ap_ST_pp2_stg0_fsm_3;
end
ap_ST_pp3_stg0_fsm_8 :
begin
if (~((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_8;
end else if (((ap_const_logic_1 == ap_reg_ppiten_pp3_it0) & ~((ap_const_lv1_0 == exitcond_flatten2_reg_2087) & (ap_const_logic_0 == ap_sig_ioackin_OUTPUT_STREAM_TREADY) & (ap_const_logic_1 == ap_reg_ppiten_pp3_it1)) & ~(ap_const_lv1_0 == exitcond_flatten2_fu_1533_p2))) begin
ap_NS_fsm = ap_ST_st95_fsm_9;
end else begin
ap_NS_fsm = ap_ST_pp3_stg0_fsm_8;
end
end
ap_ST_st95_fsm_9 :
begin
ap_NS_fsm = ap_ST_st1_fsm_0;
end
default :
begin
ap_NS_fsm = 'bx;
end
endcase
end
assign HLS_accel_CONTROL_BUS_s_axi_U_ap_dummy_ce = ap_const_logic_1;
assign OUTPUT_STREAM_TDATA = out_q0;
assign OUTPUT_STREAM_TDEST = ap_const_lv5_0;
assign OUTPUT_STREAM_TID = ap_const_lv5_0;
assign OUTPUT_STREAM_TKEEP = ap_const_lv4_F;
assign OUTPUT_STREAM_TLAST = last_assign_reg_2106;
assign OUTPUT_STREAM_TSTRB = ap_const_lv4_F;
assign OUTPUT_STREAM_TUSER = ap_const_lv4_0;
assign a_d0 = INPUT_STREAM_TDATA;
/// ap_rst_n_inv assign process. ///
always @ (ap_rst_n)
begin
ap_rst_n_inv = ~ap_rst_n;
end
/// ap_sig_bdd_112 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_112 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_4]);
end
/// ap_sig_bdd_156 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_156 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_5]);
end
/// ap_sig_bdd_1567 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_1567 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_9]);
end
/// ap_sig_bdd_167 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_167 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_6]);
end
/// ap_sig_bdd_179 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_179 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_7]);
end
/// ap_sig_bdd_204 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_204 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_3]);
end
/// ap_sig_bdd_238 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_238 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_1]);
end
/// ap_sig_bdd_243 assign process. ///
always @ (INPUT_STREAM_TVALID or exitcond_flatten_fu_580_p2)
begin
ap_sig_bdd_243 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_flatten_fu_580_p2));
end
/// ap_sig_bdd_260 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_260 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_2]);
end
/// ap_sig_bdd_264 assign process. ///
always @ (INPUT_STREAM_TVALID or exitcond_flatten8_fu_658_p2)
begin
ap_sig_bdd_264 = ((INPUT_STREAM_TVALID == ap_const_logic_0) & (ap_const_lv1_0 == exitcond_flatten8_fu_658_p2));
end
/// ap_sig_bdd_51 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_51 = (ap_CS_fsm[ap_const_lv32_0] == ap_const_lv1_1);
end
/// ap_sig_bdd_617 assign process. ///
always @ (ap_CS_fsm)
begin
ap_sig_bdd_617 = (ap_const_lv1_1 == ap_CS_fsm[ap_const_lv32_8]);
end
assign b_d0 = INPUT_STREAM_TDATA;
assign exitcond2_i_fu_670_p2 = (j2_0_i_reg_372 == ap_const_lv6_20? 1'b1: 1'b0);
assign exitcond2_i_i_fu_938_p2 = (q_fu_862_p2 == ap_const_lv6_20? 1'b1: 1'b0);
assign exitcond4_i_fu_592_p2 = (j_0_i_reg_339 == ap_const_lv6_20? 1'b1: 1'b0);
assign exitcond_flatten1_fu_1241_p2 = (indvar_flatten1_phi_fu_431_p4 == ap_const_lv10_3FF? 1'b1: 1'b0);
assign exitcond_flatten2_fu_1533_p2 = (indvar_flatten2_reg_438 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond_flatten8_fu_658_p2 = (indvar_flatten6_reg_350 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond_flatten_fu_580_p2 = (indvar_flatten_reg_317 == ap_const_lv11_400? 1'b1: 1'b0);
assign exitcond_i_fu_1545_p2 = (j5_0_i_reg_460 == ap_const_lv6_20? 1'b1: 1'b0);
assign grp_fu_472_ce = ap_const_logic_1;
assign grp_fu_477_ce = ap_const_logic_1;
assign grp_fu_482_ce = ap_const_logic_1;
assign grp_fu_486_ce = ap_const_logic_1;
assign grp_fu_492_ce = ap_const_logic_1;
assign grp_fu_492_p0 = ap_reg_ppstg_tmp_15_reg_1983_pp2_it12;
assign grp_fu_492_p1 = reg_574;
assign grp_fu_496_p0 = reg_564;
assign grp_fu_510_opcode = ap_const_lv5_2;
assign grp_fu_510_p1 = ap_const_lv32_0;
assign grp_fu_515_opcode = ap_const_lv5_2;
assign grp_fu_515_p1 = ap_const_lv32_0;
assign grp_fu_520_opcode = ap_const_lv5_1;
assign grp_fu_520_p0 = b_load_reg_1796;
assign grp_fu_527_ce = ap_const_logic_1;
assign grp_fu_532_ce = ap_const_logic_1;
assign i1_0_i_mid2_fu_690_p3 = ((exitcond2_i_fu_670_p2)? i_s_fu_684_p2: i1_0_i_reg_361);
assign i4_0_i_mid2_fu_1565_p3 = ((exitcond_i_fu_1545_p2)? i_1_fu_1559_p2: i4_0_i_phi_fu_453_p4);
assign i_0_i_mid2_fu_612_p3 = ((exitcond4_i_fu_592_p2)? i_fu_606_p2: i_0_i_reg_328);
assign i_1_fu_1559_p2 = (i4_0_i_phi_fu_453_p4 + ap_const_lv6_1);
assign i_fu_606_p2 = (i_0_i_reg_328 + ap_const_lv6_1);
assign i_s_fu_684_p2 = (i1_0_i_reg_361 + ap_const_lv6_1);
assign indvar_flatten_next1_fu_1235_p2 = (indvar_flatten1_phi_fu_431_p4 + ap_const_lv10_1);
assign indvar_flatten_next2_fu_1539_p2 = (indvar_flatten2_reg_438 + ap_const_lv11_1);
assign indvar_flatten_next7_fu_664_p2 = (indvar_flatten6_reg_350 + ap_const_lv11_1);
assign indvar_flatten_next_fu_586_p2 = (indvar_flatten_reg_317 + ap_const_lv11_1);
assign j2_0_i_mid2_fu_676_p3 = ((exitcond2_i_fu_670_p2)? ap_const_lv6_0: j2_0_i_reg_372);
assign j5_0_i_cast5_fu_1585_p1 = j5_0_i_mid2_fu_1551_p3;
assign j5_0_i_mid2_fu_1551_p3 = ((exitcond_i_fu_1545_p2)? ap_const_lv6_0: j5_0_i_reg_460);
assign j_0_i_mid2_fu_598_p3 = ((exitcond4_i_fu_592_p2)? ap_const_lv6_0: j_0_i_reg_339);
assign j_1_fu_730_p2 = (j2_0_i_mid2_fu_676_p3 + ap_const_lv6_1);
assign j_2_fu_1628_p2 = (j5_0_i_mid2_fu_1551_p3 + ap_const_lv6_1);
assign j_fu_652_p2 = (j_0_i_mid2_fu_598_p3 + ap_const_lv6_1);
assign k_fu_1589_p2 = (j5_0_i_cast5_fu_1585_p1 + tmp_5_fu_1577_p3);
assign last_assign_fu_1622_p2 = (k_fu_1589_p2 == ap_const_lv10_3FF? 1'b1: 1'b0);
assign m_assign_to_int_fu_1189_p1 = b_load_reg_1796;
assign notlhs1_fu_1012_p2 = (tmp_35_fu_998_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs2_fu_1061_p2 = (tmp_42_fu_1047_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs3_fu_1116_p2 = (tmp_47_fu_1102_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs4_fu_1265_p2 = (tmp_52_fu_1251_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs5_fu_1165_p2 = (tmp_57_fu_1151_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs6_fu_1387_p2 = (tmp_62_fu_1373_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs7_fu_1314_p2 = (tmp_67_fu_1300_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs8_fu_1206_p2 = (tmp_72_fu_1192_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs9_fu_1435_p2 = (tmp_89_fu_1421_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notlhs_fu_962_p2 = (tmp_13_fu_948_p4 != ap_const_lv8_FF? 1'b1: 1'b0);
assign notrhs1_fu_1018_p2 = (tmp_43_fu_1008_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs2_fu_1067_p2 = (tmp_48_fu_1057_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs3_fu_1122_p2 = (tmp_68_fu_1112_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs4_fu_1271_p2 = (tmp_76_fu_1261_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs5_fu_1171_p2 = (tmp_79_fu_1161_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs6_fu_1393_p2 = (tmp_82_fu_1383_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs7_fu_1320_p2 = (tmp_90_fu_1310_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs8_fu_1212_p2 = (tmp_95_fu_1202_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs9_fu_1441_p2 = (tmp_98_fu_1431_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign notrhs_fu_968_p2 = (tmp_17_fu_958_p1 == ap_const_lv23_0? 1'b1: 1'b0);
assign or_cond_i8_fu_1224_p2 = (tmp_74_fu_1218_p2 & tmp_94_reg_1867);
assign out_d0 = tmp_28_reg_2082;
assign output_i_fu_1493_p3 = ((ap_reg_ppstg_tmp_86_reg_1903_pp2_it1)? ap_const_lv32_42C80000: ap_const_lv32_0);
assign p_1_fu_900_p2 = (x_assign_5_mid2_reg_1682 + ap_const_lv6_1);
assign p_addr10_fu_848_p2 = (p_addr8_cast1_fu_844_p1 + tmp_44_0_1_trn_cast_fu_813_p1);
assign p_addr11_cast1_fu_913_p1 = tmp_77_fu_905_p3;
assign p_addr11_cast_fu_917_p1 = tmp_77_fu_905_p3;
assign p_addr11_fu_1611_p2 = (p_addr16_cast_fu_1607_p1 + tmp_11_trn_cast_fu_1595_p1);
assign p_addr16_cast_fu_1607_p1 = tmp_96_fu_1599_p3;
assign p_addr1_fu_641_p2 = (p_addr_cast_fu_637_p1 + tmp_1_trn_cast_fu_625_p1);
assign p_addr2_cast_fu_715_p1 = tmp_6_fu_707_p3;
assign p_addr2_fu_921_p2 = ($signed(p_addr11_cast_fu_917_p1) + $signed(y_assign_cast_cast1_fu_859_p1));
assign p_addr3_fu_719_p2 = (p_addr2_cast_fu_715_p1 + tmp_4_trn_cast_fu_703_p1);
assign p_addr4_cast_fu_790_p1 = $signed(tmp_11_fu_782_p3);
assign p_addr4_fu_927_p2 = (p_addr11_cast1_fu_913_p1 + tmp_44_0_1_trn_cast_reg_1714);
assign p_addr5_fu_794_p2 = ($signed(p_addr4_cast_fu_790_p1) + $signed(y_assign_cast_cast_fu_764_p1));
assign p_addr6_fu_817_p2 = ($signed(p_addr4_cast_fu_790_p1) + $signed(tmp_44_0_1_trn_cast_fu_813_p1));
assign p_addr7_fu_871_p2 = ($signed(p_addr4_cast_reg_1698) + $signed(tmp_38_0_2_trn_cast_fu_867_p1));
assign p_addr8_cast1_fu_844_p1 = tmp_58_fu_836_p3;
assign p_addr8_cast_fu_881_p1 = tmp_58_reg_1730;
assign p_addr8_fu_932_p2 = (p_addr11_cast1_fu_913_p1 + tmp_38_0_2_trn_cast_fu_867_p1);
assign p_addr9_fu_884_p2 = ($signed(p_addr8_cast_fu_881_p1) + $signed(y_assign_cast_cast1_fu_859_p1));
assign p_addr_cast_fu_637_p1 = tmp_1_fu_629_p3;
assign p_addr_fu_895_p2 = (p_addr8_cast1_reg_1735 + tmp_38_0_2_trn_cast_fu_867_p1);
assign q_fu_862_p2 = (y_assign_1_mid2_reg_1677 + ap_const_lv6_1);
assign sel_tmp1_fu_1338_p2 = (or_cond_i8_reg_1897 ^ ap_const_lv1_1);
assign sel_tmp2_fu_1343_p2 = (tmp_86_reg_1903 & sel_tmp1_fu_1338_p2);
assign sum_4_i_i_0_1_fu_1508_p3 = ((ap_reg_ppstg_tmp_37_reg_1708_pp2_it3)? ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it3: reg_569);
assign sum_4_i_i_0_2_fu_1515_p3 = ((ap_reg_ppstg_tmp_37_reg_1708_pp2_it5)? ap_reg_ppstg_sum_4_i_i_reg_2003_pp2_it4: grp_fu_496_p1);
assign sum_4_i_i_1_fu_1521_p3 = ((ap_reg_ppstg_tmp_53_reg_1724_pp2_it6)? sum_4_i_i_0_2_reg_2020: grp_fu_472_p2);
assign sum_4_i_i_2_fu_1527_p3 = ((ap_reg_ppstg_tmp_53_reg_1724_pp2_it8)? ap_reg_ppstg_sum_1_1_2_reg_2031_pp2_it8: grp_fu_496_p1);
assign sum_4_i_i_fu_1501_p3 = ((ap_reg_ppstg_tmp_10_reg_1693_pp2_it2)? ap_const_lv32_0: grp_fu_496_p1);
assign tmp_11_fu_782_p3 = {{x_assign_fu_752_p2}, {ap_const_lv5_0}};
assign tmp_11_trn_cast_fu_1595_p1 = j5_0_i_mid2_fu_1551_p3;
assign tmp_12_fu_800_p1 = p_addr5_fu_794_p2;
assign tmp_13_fu_948_p4 = {{x_assign_1_to_int_fu_944_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_17_fu_958_p1 = x_assign_1_to_int_fu_944_p1[22:0];
assign tmp_1_fu_629_p3 = {{i_0_i_mid2_fu_612_p3}, {ap_const_lv5_0}};
assign tmp_1_trn_cast_fu_625_p1 = j_0_i_mid2_fu_598_p3;
assign tmp_22_fu_974_p2 = (notrhs_fu_968_p2 | notlhs_fu_962_p2);
assign tmp_24_fu_507_p0 = ap_reg_ppstg_a_load_reg_1933_pp2_it15;
assign tmp_30_fu_980_p2 = (tmp_22_fu_974_p2 & grp_fu_510_p2);
assign tmp_31_fu_1465_p3 = ((ap_reg_ppstg_tmp_30_reg_1807_pp2_it1)? reg_560: ap_const_lv64_0);
assign tmp_34_fu_823_p1 = p_addr6_fu_817_p2;
assign tmp_35_fu_998_p4 = {{x_assign_2_to_int_fu_994_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_38_0_2_trn_cast_fu_867_p1 = q_fu_862_p2;
assign tmp_38_fu_1024_p2 = (notrhs1_fu_1018_p2 | notlhs1_fu_1012_p2);
assign tmp_40_fu_1030_p2 = (tmp_38_fu_1024_p2 & tmp_39_reg_1812);
assign tmp_41_0_2_fu_1472_p3 = ((ap_reg_ppstg_tmp_46_reg_1842_pp2_it1)? reg_560: ap_const_lv64_0);
assign tmp_41_2_2_fu_1486_p3 = ((ap_reg_ppstg_tmp_71_reg_1928_pp2_it2)? reg_560: ap_const_lv64_0);
assign tmp_41_2_fu_1479_p3 = ((ap_reg_ppstg_tmp_61_reg_1882_pp2_it1)? reg_560: ap_const_lv64_0);
assign tmp_41_fu_876_p1 = p_addr7_fu_871_p2;
assign tmp_42_fu_1047_p4 = {{x_assign_4_to_int_fu_1043_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_43_fu_1008_p1 = x_assign_2_to_int_fu_994_p1[22:0];
assign tmp_44_0_1_trn_cast_fu_813_p1 = y_assign_1_mid2_fu_736_p3;
assign tmp_44_fu_1073_p2 = (notrhs2_fu_1067_p2 | notlhs2_fu_1061_p2);
assign tmp_46_fu_1079_p2 = (tmp_44_fu_1073_p2 & grp_fu_510_p2);
assign tmp_47_fu_1102_p4 = {{x_assign_6_to_int_fu_1098_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_48_fu_1057_p1 = x_assign_4_to_int_fu_1043_p1[22:0];
assign tmp_49_fu_1128_p2 = (notrhs3_fu_1122_p2 | notlhs3_fu_1116_p2);
assign tmp_4_fu_647_p1 = p_addr1_fu_641_p2;
assign tmp_4_trn_cast_fu_703_p1 = j2_0_i_mid2_fu_676_p3;
assign tmp_51_fu_1134_p2 = (tmp_49_fu_1128_p2 & tmp_50_reg_1847);
assign tmp_52_fu_1251_p4 = {{x_assign_8_to_int_fu_1247_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_54_fu_1277_p2 = (notrhs4_fu_1271_p2 | notlhs4_fu_1265_p2);
assign tmp_56_fu_1283_p2 = (tmp_54_fu_1277_p2 & tmp_55_reg_1877);
assign tmp_57_fu_1151_p4 = {{x_assign_11_to_int_fu_1147_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_58_fu_836_p3 = {{x_assign_5_mid2_fu_744_p3}, {ap_const_lv5_0}};
assign tmp_59_fu_1177_p2 = (notrhs5_fu_1171_p2 | notlhs5_fu_1165_p2);
assign tmp_5_fu_1577_p3 = {{tmp_99_fu_1573_p1}, {ap_const_lv5_0}};
assign tmp_61_fu_1183_p2 = (tmp_59_fu_1177_p2 & grp_fu_515_p2);
assign tmp_62_fu_1373_p4 = {{x_assign_12_to_int_fu_1369_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_63_fu_890_p1 = p_addr9_fu_884_p2;
assign tmp_64_fu_1399_p2 = (notrhs6_fu_1393_p2 | notlhs6_fu_1387_p2);
assign tmp_66_fu_1405_p2 = (tmp_64_fu_1399_p2 & tmp_65_reg_1923);
assign tmp_67_fu_1300_p4 = {{x_assign_14_to_int_fu_1296_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_68_fu_1112_p1 = x_assign_6_to_int_fu_1098_p1[22:0];
assign tmp_69_fu_1326_p2 = (notrhs7_fu_1320_p2 | notlhs7_fu_1314_p2);
assign tmp_6_fu_707_p3 = {{i1_0_i_mid2_fu_690_p3}, {ap_const_lv5_0}};
assign tmp_71_fu_1332_p2 = (tmp_69_fu_1326_p2 & grp_fu_515_p2);
assign tmp_72_fu_1192_p4 = {{m_assign_to_int_fu_1189_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_73_fu_986_p1 = p_addr_reg_1771;
assign tmp_74_fu_1218_p2 = (notrhs8_fu_1212_p2 | notlhs8_fu_1206_p2);
assign tmp_76_fu_1261_p1 = x_assign_8_to_int_fu_1247_p1[22:0];
assign tmp_77_fu_905_p3 = {{p_1_fu_900_p2}, {ap_const_lv5_0}};
assign tmp_78_fu_990_p1 = p_addr2_reg_1781;
assign tmp_79_fu_1161_p1 = x_assign_11_to_int_fu_1147_p1[22:0];
assign tmp_7_fu_725_p1 = p_addr3_fu_719_p2;
assign tmp_81_fu_1085_p1 = p_addr4_reg_1786;
assign tmp_82_fu_1383_p1 = x_assign_12_to_int_fu_1369_p1[22:0];
assign tmp_83_fu_1089_p1 = p_addr8_reg_1791;
assign tmp_84_fu_854_p1 = p_addr10_fu_848_p2;
assign tmp_86_fu_1229_p2 = (tmp_74_fu_1218_p2 & grp_fu_520_p2);
assign tmp_87_fu_1348_p3 = ((sel_tmp2_fu_1343_p2)? ap_const_lv32_C2C80000: ap_const_lv32_0);
assign tmp_88_fu_1356_p2 = (sel_tmp2_fu_1343_p2 | or_cond_i8_reg_1897);
assign tmp_89_fu_1421_p4 = {{x_assign_15_to_int_fu_1418_p1[ap_const_lv32_1E : ap_const_lv32_17]}};
assign tmp_90_fu_1310_p1 = x_assign_14_to_int_fu_1296_p1[22:0];
assign tmp_91_fu_1447_p2 = (notrhs9_fu_1441_p2 | notlhs9_fu_1435_p2);
assign tmp_93_fu_1453_p2 = (tmp_91_fu_1447_p2 & tmp_92_reg_1953);
assign tmp_94_fu_1093_p2 = (tmp_75_reg_1832 | grp_fu_520_p2);
assign tmp_95_fu_1202_p1 = m_assign_to_int_fu_1189_p1[22:0];
assign tmp_96_fu_1599_p3 = {{i4_0_i_mid2_fu_1565_p3}, {ap_const_lv5_0}};
assign tmp_97_fu_1617_p1 = p_addr11_fu_1611_p2;
assign tmp_98_fu_1431_p1 = x_assign_15_to_int_fu_1418_p1[22:0];
assign tmp_99_fu_1573_p1 = i4_0_i_mid2_fu_1565_p3[4:0];
assign tmp_9_fu_768_p2 = (x_assign_fu_752_p2 | y_assign_fu_758_p2);
assign x_assign_11_to_int_fu_1147_p1 = reg_548;
assign x_assign_12_to_int_fu_1369_p1 = reg_548;
assign x_assign_14_to_int_fu_1296_p1 = reg_555;
assign x_assign_15_to_int_fu_1418_p1 = x_assign_2_reg_1941;
assign x_assign_1_fu_1410_p3 = ((tmp_66_fu_1405_p2)? reg_548: ap_const_lv32_0);
assign x_assign_1_to_int_fu_944_p1 = reg_542;
assign x_assign_2_fu_1361_p3 = ((tmp_88_fu_1356_p2)? tmp_87_fu_1348_p3: ap_const_lv32_42C80000);
assign x_assign_2_to_int_fu_994_p1 = reg_548;
assign x_assign_3_fu_1035_p3 = ((tmp_40_fu_1030_p2)? reg_548: ap_const_lv32_0);
assign x_assign_4_fu_1458_p3 = ((tmp_93_fu_1453_p2)? x_assign_2_reg_1941: ap_const_lv32_0);
assign x_assign_4_to_int_fu_1043_p1 = reg_542;
assign x_assign_5_mid2_fu_744_p3 = ((exitcond2_i_i1_phi_fu_398_p4)? p_phi_fu_387_p4: x_assign_5_phi_fu_420_p4);
assign x_assign_6_to_int_fu_1098_p1 = reg_555;
assign x_assign_7_fu_1139_p3 = ((tmp_51_fu_1134_p2)? reg_555: ap_const_lv32_0);
assign x_assign_8_to_int_fu_1247_p1 = reg_542;
assign x_assign_9_fu_1288_p3 = ((tmp_56_fu_1283_p2)? reg_542: ap_const_lv32_0);
assign x_assign_fu_752_p2 = ($signed(x_assign_5_mid2_fu_744_p3) + $signed(ap_const_lv6_3F));
assign y_assign_1_mid2_fu_736_p3 = ((exitcond2_i_i1_phi_fu_398_p4)? ap_const_lv6_0: y_assign_s_phi_fu_409_p4);
assign y_assign_cast_cast1_fu_859_p1 = $signed(y_assign_reg_1688);
assign y_assign_cast_cast_fu_764_p1 = $signed(y_assign_fu_758_p2);
assign y_assign_fu_758_p2 = ($signed(y_assign_1_mid2_fu_736_p3) + $signed(ap_const_lv6_3F));
always @ (posedge ap_clk)
begin
p_addr4_cast_reg_1698[4:0] <= 5'b00000;
tmp_44_0_1_trn_cast_reg_1714[11:6] <= 6'b000000;
tmp_58_reg_1730[4:0] <= 5'b00000;
p_addr8_cast1_reg_1735[4:0] <= 5'b00000;
p_addr8_cast1_reg_1735[11] <= 1'b0;
tmp_84_reg_1740[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it1[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it2[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it3[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it4[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it5[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it6[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it7[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it8[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it9[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it10[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it11[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it12[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it13[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it14[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it15[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it16[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
ap_reg_ppstg_tmp_84_reg_1740_pp2_it17[63:12] <= 52'b0000000000000000000000000000000000000000000000000000;
x_assign_2_reg_1941[18:0] <= 19'b0000000000000000000;
x_assign_2_reg_1941[21:20] <= 2'b00;
x_assign_2_reg_1941[24:24] <= 1'b0;
x_assign_2_reg_1941[29:26] <= 4'b0000;
x_assign_4_reg_1958[18:0] <= 19'b0000000000000000000;
x_assign_4_reg_1958[21:20] <= 2'b00;
x_assign_4_reg_1958[24:24] <= 1'b0;
x_assign_4_reg_1958[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it2[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it3[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it4[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it5[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it6[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it7[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it8[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it9[29:26] <= 4'b0000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[18:0] <= 19'b0000000000000000000;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[21:20] <= 2'b00;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[24:24] <= 1'b0;
ap_reg_ppstg_x_assign_4_reg_1958_pp2_it10[29:26] <= 4'b0000;
end
endmodule //HLS_accel
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2010 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** * Euclidean Division for integers (Floor convention)
We use here the convention known as Floor, or Round-Toward-Bottom,
where [a/b] is the closest integer below the exact fraction.
It can be summarized by:
[a = bq+r /\ 0 <= |r| < |b| /\ Sign(r) = Sign(b)]
This is the convention followed historically by [Zdiv] in Coq, and
corresponds to convention "F" in the following paper:
R. Boute, "The Euclidean definition of the functions div and mod",
ACM Transactions on Programming Languages and Systems,
Vol. 14, No.2, pp. 127-144, April 1992.
See files [ZDivTrunc] and [ZDivEucl] for others conventions.
*)
Require Import ZAxioms ZProperties NZDiv.
Module Type ZDivSpecific (Import Z:ZAxiomsSig')(Import DM : DivMod' Z).
Axiom mod_pos_bound : forall a b, 0 < b -> 0 <= a mod b < b.
Axiom mod_neg_bound : forall a b, b < 0 -> b < a mod b <= 0.
End ZDivSpecific.
Module Type ZDiv (Z:ZAxiomsSig)
:= DivMod Z <+ NZDivCommon Z <+ ZDivSpecific Z.
Module Type ZDivSig := ZAxiomsSig <+ ZDiv.
Module Type ZDivSig' := ZAxiomsSig' <+ ZDiv <+ DivModNotation.
Module ZDivProp (Import Z : ZDivSig')(Import ZP : ZProp Z).
(** We benefit from what already exists for NZ *)
Module ZD <: NZDiv Z.
Definition div := div.
Definition modulo := modulo.
Definition div_wd := div_wd.
Definition mod_wd := mod_wd.
Definition div_mod := div_mod.
Lemma mod_bound : forall a b, 0<=a -> 0<b -> 0 <= a mod b < b.
Proof. intros. now apply mod_pos_bound. Qed.
End ZD.
Module Import NZDivP := NZDivProp Z ZP ZD.
(** Another formulation of the main equation *)
Lemma mod_eq :
forall a b, b~=0 -> a mod b == a - b*(a/b).
Proof.
intros.
rewrite <- add_move_l.
symmetry. now apply div_mod.
Qed.
(** Uniqueness theorems *)
Theorem div_mod_unique : forall b q1 q2 r1 r2 : t,
(0<=r1<b \/ b<r1<=0) -> (0<=r2<b \/ b<r2<=0) ->
b*q1+r1 == b*q2+r2 -> q1 == q2 /\ r1 == r2.
Proof.
intros b q1 q2 r1 r2 Hr1 Hr2 EQ.
destruct Hr1; destruct Hr2; try (intuition; order).
apply div_mod_unique with b; trivial.
rewrite <- (opp_inj_wd r1 r2).
apply div_mod_unique with (-b); trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
now rewrite 2 mul_opp_l, <- 2 opp_add_distr, opp_inj_wd.
Qed.
Theorem div_unique:
forall a b q r, (0<=r<b \/ b<r<=0) -> a == b*q + r -> q == a/b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0) by (destruct Hr; intuition; order).
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
destruct Hr; [left; apply mod_pos_bound|right; apply mod_neg_bound];
intuition order.
now rewrite <- div_mod.
Qed.
Theorem div_unique_pos:
forall a b q r, 0<=r<b -> a == b*q + r -> q == a/b.
Proof. intros; apply div_unique with r; auto. Qed.
Theorem div_unique_neg:
forall a b q r, 0<=r<b -> a == b*q + r -> q == a/b.
Proof. intros; apply div_unique with r; auto. Qed.
Theorem mod_unique:
forall a b q r, (0<=r<b \/ b<r<=0) -> a == b*q + r -> r == a mod b.
Proof.
intros a b q r Hr EQ.
assert (Hb : b~=0) by (destruct Hr; intuition; order).
destruct (div_mod_unique b q (a/b) r (a mod b)); trivial.
destruct Hr; [left; apply mod_pos_bound|right; apply mod_neg_bound];
intuition order.
now rewrite <- div_mod.
Qed.
Theorem mod_unique_pos:
forall a b q r, 0<=r<b -> a == b*q + r -> r == a mod b.
Proof. intros; apply mod_unique with q; auto. Qed.
Theorem mod_unique_neg:
forall a b q r, b<r<=0 -> a == b*q + r -> r == a mod b.
Proof. intros; apply mod_unique with q; auto. Qed.
(** Sign rules *)
Ltac pos_or_neg a :=
let LT := fresh "LT" in
let LE := fresh "LE" in
destruct (le_gt_cases 0 a) as [LE|LT]; [|rewrite <- opp_pos_neg in LT].
Fact mod_bound_or : forall a b, b~=0 -> 0<=a mod b<b \/ b<a mod b<=0.
Proof.
intros.
destruct (lt_ge_cases 0 b); [left|right].
apply mod_pos_bound; trivial. apply mod_neg_bound; order.
Qed.
Fact opp_mod_bound_or : forall a b, b~=0 ->
0 <= -(a mod b) < -b \/ -b < -(a mod b) <= 0.
Proof.
intros.
destruct (lt_ge_cases 0 b); [right|left].
rewrite <- opp_lt_mono, opp_nonpos_nonneg.
destruct (mod_pos_bound a b); intuition; order.
rewrite <- opp_lt_mono, opp_nonneg_nonpos.
destruct (mod_neg_bound a b); intuition; order.
Qed.
Lemma div_opp_opp : forall a b, b~=0 -> -a/-b == a/b.
Proof.
intros. symmetry. apply div_unique with (- (a mod b)).
now apply opp_mod_bound_or.
rewrite mul_opp_l, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma mod_opp_opp : forall a b, b~=0 -> (-a) mod (-b) == - (a mod b).
Proof.
intros. symmetry. apply mod_unique with (a/b).
now apply opp_mod_bound_or.
rewrite mul_opp_l, <- opp_add_distr, <- div_mod; order.
Qed.
(** With the current conventions, the other sign rules are rather complex. *)
Lemma div_opp_l_z :
forall a b, b~=0 -> a mod b == 0 -> (-a)/b == -(a/b).
Proof.
intros a b Hb H. symmetry. apply div_unique with 0.
destruct (lt_ge_cases 0 b); [left|right]; intuition; order.
rewrite <- opp_0, <- H.
rewrite mul_opp_r, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma div_opp_l_nz :
forall a b, b~=0 -> a mod b ~= 0 -> (-a)/b == -(a/b)-1.
Proof.
intros a b Hb H. symmetry. apply div_unique with (b - a mod b).
destruct (lt_ge_cases 0 b); [left|right].
rewrite le_0_sub. rewrite <- (sub_0_r b) at 5. rewrite <- sub_lt_mono_l.
destruct (mod_pos_bound a b); intuition; order.
rewrite le_sub_0. rewrite <- (sub_0_r b) at 1. rewrite <- sub_lt_mono_l.
destruct (mod_neg_bound a b); intuition; order.
rewrite <- (add_opp_r b), mul_sub_distr_l, mul_1_r, sub_add_simpl_r_l.
rewrite mul_opp_r, <-opp_add_distr, <-div_mod; order.
Qed.
Lemma mod_opp_l_z :
forall a b, b~=0 -> a mod b == 0 -> (-a) mod b == 0.
Proof.
intros a b Hb H. symmetry. apply mod_unique with (-(a/b)).
destruct (lt_ge_cases 0 b); [left|right]; intuition; order.
rewrite <- opp_0, <- H.
rewrite mul_opp_r, <- opp_add_distr, <- div_mod; order.
Qed.
Lemma mod_opp_l_nz :
forall a b, b~=0 -> a mod b ~= 0 -> (-a) mod b == b - a mod b.
Proof.
intros a b Hb H. symmetry. apply mod_unique with (-(a/b)-1).
destruct (lt_ge_cases 0 b); [left|right].
rewrite le_0_sub. rewrite <- (sub_0_r b) at 5. rewrite <- sub_lt_mono_l.
destruct (mod_pos_bound a b); intuition; order.
rewrite le_sub_0. rewrite <- (sub_0_r b) at 1. rewrite <- sub_lt_mono_l.
destruct (mod_neg_bound a b); intuition; order.
rewrite <- (add_opp_r b), mul_sub_distr_l, mul_1_r, sub_add_simpl_r_l.
rewrite mul_opp_r, <-opp_add_distr, <-div_mod; order.
Qed.
Lemma div_opp_r_z :
forall a b, b~=0 -> a mod b == 0 -> a/(-b) == -(a/b).
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite div_opp_opp; auto using div_opp_l_z.
Qed.
Lemma div_opp_r_nz :
forall a b, b~=0 -> a mod b ~= 0 -> a/(-b) == -(a/b)-1.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite div_opp_opp; auto using div_opp_l_nz.
Qed.
Lemma mod_opp_r_z :
forall a b, b~=0 -> a mod b == 0 -> a mod (-b) == 0.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
now rewrite mod_opp_opp, mod_opp_l_z, opp_0.
Qed.
Lemma mod_opp_r_nz :
forall a b, b~=0 -> a mod b ~= 0 -> a mod (-b) == (a mod b) - b.
Proof.
intros. rewrite <- (opp_involutive a) at 1.
rewrite mod_opp_opp, mod_opp_l_nz by trivial.
now rewrite opp_sub_distr, add_comm, add_opp_r.
Qed.
(** The sign of [a mod b] is the one of [b] *)
(* TODO: a proper sgn function and theory *)
Lemma mod_sign : forall a b, b~=0 -> (0 <= (a mod b) * b).
Proof.
intros. destruct (lt_ge_cases 0 b).
apply mul_nonneg_nonneg; destruct (mod_pos_bound a b); order.
apply mul_nonpos_nonpos; destruct (mod_neg_bound a b); order.
Qed.
(** A division by itself returns 1 *)
Lemma div_same : forall a, a~=0 -> a/a == 1.
Proof.
intros. pos_or_neg a. apply div_same; order.
rewrite <- div_opp_opp by trivial. now apply div_same.
Qed.
Lemma mod_same : forall a, a~=0 -> a mod a == 0.
Proof.
intros. rewrite mod_eq, div_same by trivial. nzsimpl. apply sub_diag.
Qed.
(** A division of a small number by a bigger one yields zero. *)
Theorem div_small: forall a b, 0<=a<b -> a/b == 0.
Proof. exact div_small. Qed.
(** Same situation, in term of modulo: *)
Theorem mod_small: forall a b, 0<=a<b -> a mod b == a.
Proof. exact mod_small. Qed.
(** * Basic values of divisions and modulo. *)
Lemma div_0_l: forall a, a~=0 -> 0/a == 0.
Proof.
intros. pos_or_neg a. apply div_0_l; order.
rewrite <- div_opp_opp, opp_0 by trivial. now apply div_0_l.
Qed.
Lemma mod_0_l: forall a, a~=0 -> 0 mod a == 0.
Proof.
intros; rewrite mod_eq, div_0_l; now nzsimpl.
Qed.
Lemma div_1_r: forall a, a/1 == a.
Proof.
intros. symmetry. apply div_unique with 0. left. split; order || apply lt_0_1.
now nzsimpl.
Qed.
Lemma mod_1_r: forall a, a mod 1 == 0.
Proof.
intros. rewrite mod_eq, div_1_r; nzsimpl; auto using sub_diag.
intro EQ; symmetry in EQ; revert EQ; apply lt_neq; apply lt_0_1.
Qed.
Lemma div_1_l: forall a, 1<a -> 1/a == 0.
Proof. exact div_1_l. Qed.
Lemma mod_1_l: forall a, 1<a -> 1 mod a == 1.
Proof. exact mod_1_l. Qed.
Lemma div_mul : forall a b, b~=0 -> (a*b)/b == a.
Proof.
intros. symmetry. apply div_unique with 0.
destruct (lt_ge_cases 0 b); [left|right]; split; order.
nzsimpl; apply mul_comm.
Qed.
Lemma mod_mul : forall a b, b~=0 -> (a*b) mod b == 0.
Proof.
intros. rewrite mod_eq, div_mul by trivial. rewrite mul_comm; apply sub_diag.
Qed.
(** * Order results about mod and div *)
(** A modulo cannot grow beyond its starting point. *)
Theorem mod_le: forall a b, 0<=a -> 0<b -> a mod b <= a.
Proof. exact mod_le. Qed.
Theorem div_pos : forall a b, 0<=a -> 0<b -> 0<= a/b.
Proof. exact div_pos. Qed.
Lemma div_str_pos : forall a b, 0<b<=a -> 0 < a/b.
Proof. exact div_str_pos. Qed.
Lemma div_small_iff : forall a b, b~=0 -> (a/b==0 <-> 0<=a<b \/ b<a<=0).
Proof.
intros a b Hb.
split.
intros EQ.
rewrite (div_mod a b Hb), EQ; nzsimpl.
now apply mod_bound_or.
destruct 1. now apply div_small.
rewrite <- div_opp_opp by trivial. apply div_small; trivial.
rewrite <- opp_lt_mono, opp_nonneg_nonpos; tauto.
Qed.
Lemma mod_small_iff : forall a b, b~=0 -> (a mod b == a <-> 0<=a<b \/ b<a<=0).
Proof.
intros.
rewrite <- div_small_iff, mod_eq by trivial.
rewrite sub_move_r, <- (add_0_r a) at 1. rewrite add_cancel_l.
rewrite eq_sym_iff, eq_mul_0. tauto.
Qed.
(** As soon as the divisor is strictly greater than 1,
the division is strictly decreasing. *)
Lemma div_lt : forall a b, 0<a -> 1<b -> a/b < a.
Proof. exact div_lt. Qed.
(** [le] is compatible with a positive division. *)
Lemma div_le_mono : forall a b c, 0<c -> a<=b -> a/c <= b/c.
Proof.
intros a b c Hc Hab.
rewrite lt_eq_cases in Hab. destruct Hab as [LT|EQ];
[|rewrite EQ; order].
rewrite <- lt_succ_r.
rewrite (mul_lt_mono_pos_l c) by order.
nzsimpl.
rewrite (add_lt_mono_r _ _ (a mod c)).
rewrite <- div_mod by order.
apply lt_le_trans with b; trivial.
rewrite (div_mod b c) at 1 by order.
rewrite <- add_assoc, <- add_le_mono_l.
apply le_trans with (c+0).
nzsimpl; destruct (mod_pos_bound b c); order.
rewrite <- add_le_mono_l. destruct (mod_pos_bound a c); order.
Qed.
(** In this convention, [div] performs Rounding-Toward-Bottom.
Since we cannot speak of rational values here, we express this
fact by multiplying back by [b], and this leads to separates
statements according to the sign of [b].
First, [a/b] is below the exact fraction ...
*)
Lemma mul_div_le : forall a b, 0<b -> b*(a/b) <= a.
Proof.
intros.
rewrite (div_mod a b) at 2; try order.
rewrite <- (add_0_r (b*(a/b))) at 1.
rewrite <- add_le_mono_l.
now destruct (mod_pos_bound a b).
Qed.
Lemma mul_div_ge : forall a b, b<0 -> a <= b*(a/b).
Proof.
intros. rewrite <- div_opp_opp, opp_le_mono, <-mul_opp_l by order.
apply mul_div_le. now rewrite opp_pos_neg.
Qed.
(** ... and moreover it is the larger such integer, since [S(a/b)]
is strictly above the exact fraction.
*)
Lemma mul_succ_div_gt: forall a b, 0<b -> a < b*(S (a/b)).
Proof.
intros.
nzsimpl.
rewrite (div_mod a b) at 1; try order.
rewrite <- add_lt_mono_l.
destruct (mod_pos_bound a b); order.
Qed.
Lemma mul_succ_div_lt: forall a b, b<0 -> b*(S (a/b)) < a.
Proof.
intros. rewrite <- div_opp_opp, opp_lt_mono, <-mul_opp_l by order.
apply mul_succ_div_gt. now rewrite opp_pos_neg.
Qed.
(** NB: The four previous properties could be used as
specifications for [div]. *)
(** Inequality [mul_div_le] is exact iff the modulo is zero. *)
Lemma div_exact : forall a b, b~=0 -> (a == b*(a/b) <-> a mod b == 0).
Proof.
intros.
rewrite (div_mod a b) at 1; try order.
rewrite <- (add_0_r (b*(a/b))) at 2.
apply add_cancel_l.
Qed.
(** Some additionnal inequalities about div. *)
Theorem div_lt_upper_bound:
forall a b q, 0<b -> a < b*q -> a/b < q.
Proof.
intros.
rewrite (mul_lt_mono_pos_l b) by trivial.
apply le_lt_trans with a; trivial.
now apply mul_div_le.
Qed.
Theorem div_le_upper_bound:
forall a b q, 0<b -> a <= b*q -> a/b <= q.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
Theorem div_le_lower_bound:
forall a b q, 0<b -> b*q <= a -> q <= a/b.
Proof.
intros.
rewrite <- (div_mul q b) by order.
apply div_le_mono; trivial. now rewrite mul_comm.
Qed.
(** A division respects opposite monotonicity for the divisor *)
Lemma div_le_compat_l: forall p q r, 0<=p -> 0<q<=r -> p/r <= p/q.
Proof. exact div_le_compat_l. Qed.
(** * Relations between usual operations and mod and div *)
Lemma mod_add : forall a b c, c~=0 ->
(a + b * c) mod c == a mod c.
Proof.
intros.
symmetry.
apply mod_unique with (a/c+b); trivial.
now apply mod_bound_or.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add : forall a b c, c~=0 ->
(a + b * c) / c == a / c + b.
Proof.
intros.
apply (mul_cancel_l _ _ c); try order.
apply (add_cancel_r _ _ ((a+b*c) mod c)).
rewrite <- div_mod, mod_add by order.
rewrite mul_add_distr_l, add_shuffle0, <- div_mod by order.
now rewrite mul_comm.
Qed.
Lemma div_add_l: forall a b c, b~=0 ->
(a * b + c) / b == a + c / b.
Proof.
intros a b c. rewrite (add_comm _ c), (add_comm a).
now apply div_add.
Qed.
(** Cancellations. *)
Lemma div_mul_cancel_r : forall a b c, b~=0 -> c~=0 ->
(a*c)/(b*c) == a/b.
Proof.
intros.
symmetry.
apply div_unique with ((a mod b)*c).
(* ineqs *)
destruct (lt_ge_cases 0 c).
rewrite <-(mul_0_l c), <-2mul_lt_mono_pos_r, <-2mul_le_mono_pos_r by trivial.
now apply mod_bound_or.
rewrite <-(mul_0_l c), <-2mul_lt_mono_neg_r, <-2mul_le_mono_neg_r by order.
destruct (mod_bound_or a b); tauto.
(* equation *)
rewrite (div_mod a b) at 1 by order.
rewrite mul_add_distr_r.
rewrite add_cancel_r.
rewrite <- 2 mul_assoc. now rewrite (mul_comm c).
Qed.
Lemma div_mul_cancel_l : forall a b c, b~=0 -> c~=0 ->
(c*a)/(c*b) == a/b.
Proof.
intros. rewrite !(mul_comm c); now apply div_mul_cancel_r.
Qed.
Lemma mul_mod_distr_l: forall a b c, b~=0 -> c~=0 ->
(c*a) mod (c*b) == c * (a mod b).
Proof.
intros.
rewrite <- (add_cancel_l _ _ ((c*b)* ((c*a)/(c*b)))).
rewrite <- div_mod.
rewrite div_mul_cancel_l by trivial.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
rewrite <- neq_mul_0; auto.
Qed.
Lemma mul_mod_distr_r: forall a b c, b~=0 -> c~=0 ->
(a*c) mod (b*c) == (a mod b) * c.
Proof.
intros. rewrite !(mul_comm _ c); now rewrite mul_mod_distr_l.
Qed.
(** Operations modulo. *)
Theorem mod_mod: forall a n, n~=0 ->
(a mod n) mod n == a mod n.
Proof.
intros. rewrite mod_small_iff by trivial.
now apply mod_bound_or.
Qed.
Lemma mul_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)*b) mod n == (a*b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite add_comm, (mul_comm n), (mul_comm _ b).
rewrite mul_add_distr_l, mul_assoc.
intros. rewrite mod_add by trivial.
now rewrite mul_comm.
Qed.
Lemma mul_mod_idemp_r : forall a b n, n~=0 ->
(a*(b mod n)) mod n == (a*b) mod n.
Proof.
intros. rewrite !(mul_comm a). now apply mul_mod_idemp_l.
Qed.
Theorem mul_mod: forall a b n, n~=0 ->
(a * b) mod n == ((a mod n) * (b mod n)) mod n.
Proof.
intros. now rewrite mul_mod_idemp_l, mul_mod_idemp_r.
Qed.
Lemma add_mod_idemp_l : forall a b n, n~=0 ->
((a mod n)+b) mod n == (a+b) mod n.
Proof.
intros a b n Hn. symmetry.
rewrite (div_mod a n) at 1 by order.
rewrite <- add_assoc, add_comm, mul_comm.
intros. now rewrite mod_add.
Qed.
Lemma add_mod_idemp_r : forall a b n, n~=0 ->
(a+(b mod n)) mod n == (a+b) mod n.
Proof.
intros. rewrite !(add_comm a). now apply add_mod_idemp_l.
Qed.
Theorem add_mod: forall a b n, n~=0 ->
(a+b) mod n == (a mod n + b mod n) mod n.
Proof.
intros. now rewrite add_mod_idemp_l, add_mod_idemp_r.
Qed.
(** With the current convention, the following result isn't always
true for negative divisors. For instance
[ 3/(-2)/(-2) = 1 <> 0 = 3 / (-2*-2) ]. *)
Lemma div_div : forall a b c, 0<b -> 0<c ->
(a/b)/c == a/(b*c).
Proof.
intros a b c Hb Hc.
apply div_unique with (b*((a/b) mod c) + a mod b).
(* begin 0<= ... <b*c \/ ... *)
left.
destruct (mod_pos_bound (a/b) c), (mod_pos_bound a b); trivial.
split.
apply add_nonneg_nonneg; trivial.
apply mul_nonneg_nonneg; order.
apply lt_le_trans with (b*((a/b) mod c) + b).
now rewrite <- add_lt_mono_l.
now rewrite <- mul_succ_r, <- mul_le_mono_pos_l, le_succ_l.
(* end 0<= ... < b*c \/ ... *)
rewrite (div_mod a b) at 1 by order.
rewrite add_assoc, add_cancel_r.
rewrite <- mul_assoc, <- mul_add_distr_l, mul_cancel_l by order.
apply div_mod; order.
Qed.
(** A last inequality: *)
Theorem div_mul_le:
forall a b c, 0<=a -> 0<b -> 0<=c -> c*(a/b) <= (c*a)/b.
Proof. exact div_mul_le. Qed.
(** mod is related to divisibility *)
Lemma mod_divides : forall a b, b~=0 ->
(a mod b == 0 <-> exists c, a == b*c).
Proof.
intros a b Hb. split.
intros Hab. exists (a/b). rewrite (div_mod a b Hb) at 1.
rewrite Hab. now nzsimpl.
intros (c,Hc).
rewrite Hc, mul_comm.
now apply mod_mul.
Qed.
End ZDivProp.
|
(* FASM_PARAMS="INV.TA1=TAS1;INV.TA2=TAS2;INV.TB1=TBS1;INV.TB2=TBS2;INV.BA1=BAS1;INV.BA2=BAS2;INV.BB1=BBS1;INV.BB2=BBS2" *)
(* whitebox *)
module C_FRAG (TBS, TAB, TSL, TA1, TA2, TB1, TB2, BAB, BSL, BA1, BA2, BB1, BB2, TZ, CZ);
// Routing ports
input wire TBS;
input wire TAB;
input wire TSL;
input wire TA1;
input wire TA2;
input wire TB1;
input wire TB2;
input wire BAB;
input wire BSL;
input wire BA1;
input wire BA2;
input wire BB1;
input wire BB2;
(* DELAY_CONST_TAB="{iopath_TAB_TZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_TZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_TZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_TZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_TZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_TZ}" *)
output wire TZ;
(* DELAY_CONST_TBS="{iopath_TBS_CZ}" *)
(* DELAY_CONST_TAB="{iopath_TAB_CZ}" *)
(* DELAY_CONST_TSL="{iopath_TSL_CZ}" *)
(* DELAY_CONST_TA1="{iopath_TA1_CZ}" *)
(* DELAY_CONST_TA2="{iopath_TA2_CZ}" *)
(* DELAY_CONST_TB1="{iopath_TB1_CZ}" *)
(* DELAY_CONST_TB2="{iopath_TB2_CZ}" *)
(* DELAY_CONST_BAB="{iopath_BAB_CZ}" *)
(* DELAY_CONST_BSL="{iopath_BSL_CZ}" *)
(* DELAY_CONST_BA1="{iopath_BA1_CZ}" *)
(* DELAY_CONST_BA2="{iopath_BA2_CZ}" *)
(* DELAY_CONST_BB1="{iopath_BB1_CZ}" *)
(* DELAY_CONST_BB2="{iopath_BB2_CZ}" *)
output wire CZ;
// Control parameters
parameter [0:0] TAS1 = 1'b0;
parameter [0:0] TAS2 = 1'b0;
parameter [0:0] TBS1 = 1'b0;
parameter [0:0] TBS2 = 1'b0;
parameter [0:0] BAS1 = 1'b0;
parameter [0:0] BAS2 = 1'b0;
parameter [0:0] BBS1 = 1'b0;
parameter [0:0] BBS2 = 1'b0;
// Input routing inverters
wire TAP1 = (TAS1) ? ~TA1 : TA1;
wire TAP2 = (TAS2) ? ~TA2 : TA2;
wire TBP1 = (TBS1) ? ~TB1 : TB1;
wire TBP2 = (TBS2) ? ~TB2 : TB2;
wire BAP1 = (BAS1) ? ~BA1 : BA1;
wire BAP2 = (BAS2) ? ~BA2 : BA2;
wire BBP1 = (BBS1) ? ~BB1 : BB1;
wire BBP2 = (BBS2) ? ~BB2 : BB2;
// 1st mux stage
wire TAI = TSL ? TAP2 : TAP1;
wire TBI = TSL ? TBP2 : TBP1;
wire BAI = BSL ? BAP2 : BAP1;
wire BBI = BSL ? BBP2 : BBP1;
// 2nd mux stage
wire TZI = TAB ? TBI : TAI;
wire BZI = BAB ? BBI : BAI;
// 3rd mux stage
wire CZI = TBS ? BZI : TZI;
// Output
assign TZ = TZI;
assign CZ = CZI;
specify
(TBS => CZ) = (0,0);
(TAB => CZ) = (0,0);
(TSL => CZ) = (0,0);
(TA1 => CZ) = (0,0);
(TA2 => CZ) = (0,0);
(TB1 => CZ) = (0,0);
(TB2 => CZ) = (0,0);
(BAB => CZ) = (0,0);
(BSL => CZ) = (0,0);
(BA1 => CZ) = (0,0);
(BA2 => CZ) = (0,0);
(BB1 => CZ) = (0,0);
(BB2 => CZ) = (0,0);
(TAB => TZ) = (0,0);
(TSL => TZ) = (0,0);
(TA1 => TZ) = (0,0);
(TA2 => TZ) = (0,0);
(TB1 => TZ) = (0,0);
(TB2 => TZ) = (0,0);
endspecify
endmodule
|
module counter_n (clk,sig,n_clk_out);
/*This module takes an input signal and implements a period counter,
taking the reciprocal to deliver the frequency in kHz.
USAGE:
counter c(clk,sig,f);
clk and sig are 1-bit inputs representing the clock and RF signal whose frequency
is to be measured.
f is a 4-bit output corresponding to the frequency of sig, IN UNITS OF HUNDREDS
OF Hz. This is because hundreds of Hz is the highest requeired frequency
resolution, and we want to use integer arithmetic.
Reference: Agilent Technologies. "Fundamentals of the Electronic Counters".
Application Note 200, Electronic Counter Series.
Design notes:
In a period counter, pulses of the clock are counted in a register, with the
totaling (counting) action gated by pulses from the RF input whose frequency
is being measured. Averaging over multiple RF cycles reduces error.
The total time elapsed between RF edges will be
n_clk*tau_c+err = m/f
=>f= m/(n_clk*tau_c+err)
where tau_c is the clock period, n_clk is the number of clock cycles actually counted
by the register, err is the error in the time estimate, m is the number of RF
positive edges, and f is the RF frequency.
Contributions to error include the +-1 count error, timebase deviations, etc.
The +-1 count error, or quantization error, arises because time is only measured
in discrete steps, and a measurement of four clock time units may be produced by
RF pulses which are acutally separated by 3+delta or 5-delta clock units.
The nominal frequency estimate
f_nominal=m/(n_clk*tau_c)
converges with the value that would arise from an average after many cycles
if n_clk is very large.
With just the +-1 count error, the spread in maximum and minimum possible
frequency estimates
fmax-fmin=m/tau_c*(1/(n_clk-1)-1/(n_clk+1))=2*m/tau_c * 1/(n_clk^2-1) ~= 2*f_nom^2*tau_c/m
=2*f_nom^2/(f_clk*m)
The error increases with frequency for a fixed number of RF pulses, but decreases
as the clock frequency increases and as the number of RF pulses averaged over
increases.
We require about 3 kHz resolution at the highest frequencies (around 300 kHz)
and about 500 Hz resolution at the lowest frequencies - these values are about
half the frequency interval between adjacent bins in these sub-bands. With
a clock speed of 4 MHz,
m=2*f_high^2/(f_clk*Delta_f_high)=2*(3E5^2)/(4E6*3E3)=18E10/(12E9)=15
with m=15, at the lower frequencies,
fmax-fmin=2*5E4^2/(4E6*15) = Delta_f_high/36 ~= 83 Hz
while m/5E4=15/5E4=3.0E-4=300 us is the maximum time elapsed per measurement.
At high frequency, Delta_t = m/300E3=50 us.
Since we are willing to accept a reaction time on the order of 1 ms, we can
actually improve accuracy by increasing m such that Delta_t_max = 1 ms = m/5E4
=>m=50.
So choose m=50, which gives fmax-fmin~=900 Hz at f_rf=300 kHz.
f_nom = m*f_clk/n_clk => n_clk = m*f_clk/f_nom,
n_clk_max=50*4E6/5E4=80E2=4000
=>n_clk needs to be at least 12 bits. Make 13.
13 Jan 2012
In general, the phase of clk edges relative sig edges will change. Some phases produce floor(M*tau_s/tau_c) clock counts, while others produce floor(M*tau_s/tau_c)+1 clock counts. This results in a jitter in n_clk. By itself, this might not be so bad, but when many bits are changing (since we are not using a Gray code), this can be problematic. Further, in practice, the spread in clock counts seems to reach +0+2, instead of +0+1.
The fix implemented is to compare the value of n_clk at the 50th sig interval to the value of n_clk used in the last frequency calculation. If the absolute value of the difference is larger than MIN_CHANGE=2, then the frequency is re-computed. Otherwise, the frequency is not changed. This seems to take care of the jitter.
//Error (10239): Verilog HDL Always Construct error at counter.v(102): event control cannot test for both positive and negative edges of variable "clk"
*/
parameter CLK_COUNTER_SIZE=14; //Number of bits in clock edge counter.
`define SIG_COUNTER_SIZE 7 //Number of bits in signal edge counter.
input clk,sig;
output reg [CLK_COUNTER_SIZE-1:0] n_clk_out; //Output clock counts.
reg [13:0] n_clk; //Register to hold number of clock counts between RF signal.
reg [13:0] n_clk_last; //Holds value of n_clk used in the last frequency computation. Compared with current value to determine whether frequency should be recomputed.
reg [6:0] n_sig; //Register to count the number of RF cycles.
reg cnt_flg; //Counter flag.
reg reset; //Internal flag to reset clock counter.
//Clock frequency in hundreds of Hz.
parameter F_CLK=40000;
//parameter F_CLK=35795; //This clock was used to test whether incorrect firing of state happens at different frequencies depending on clock frequency and precession of this with sync signal freq.
//Number of cycles of RF signal over which to average period.
parameter M=50;
//Define macros to set counter sizes for convenience (so that don't have to make multiple changes if counter size needs to be adjusted).
parameter MIN_CHANGE=2'b10; //n_clk must change by at least this amount (up or down) from last n_clk in order for a change in computed frequency to be allowed.
initial begin
#0
n_clk=1'b0; //Initialize clock edge counter.
n_sig=1'b0; //RF Cycle counter.
reset=1'b1; //Initialize reset flag to block clock counter until signal counter gate opens.
n_clk_last=1'b0;
cnt_flg=0;
end
//Clock loop
//always @(posedge clk) begin //Triggering on reset was there in case there were two sig edges before the next clk edge, in which case the reset call would get skipped. But maybe false triggers are causing clock count to drift or flicker. Remove this edge detector and see what happens. Result - no, that didn't fix the problem.
always @(posedge clk or posedge reset) begin
if (reset) begin
n_clk=1'b0; //Reset clk counter.
end else begin
n_clk=n_clk+1'b1; //Increment clk counter.
end
end
//Gate on positive edges of signal
always @(posedge sig) begin
//Initially, the gate is closed and n_sig=0.
//When the gate is opened, n_sig is incremented, so n_sig=1.
//The gate is closed again at the (M+1)th positive edge on n_sig, but before n_sig is incremented,
//so n_sig=M still.
//As such, the gate is open between the 1st and (M+1)th positive edges of n_sig, corresponding to M sig intervals.
//The gate is closed between the (M+1)th=0th and 1st signal edges.
//THEN dt = (M)*tau_sig = (M)/f_sig = (n_clk-1+[-0+2])/f_clk
//It is n_clk-1 because this is the number of clock time intervals in n_clk positive edges.
// [-0+2]=error on time measurement - time is at least (n_clk-1)*tau_c, but could be as much as
// (n_clk-1+2-delta)*tau_c, so on average, elapsed time is actually (n_clk-1 - (average error = (0+2)/2=1))*tau_c
// => f_sig = f_clk * (M)/(n_clk-1-(0+2)/2) = f_clk * (M)/n_clk
if (n_sig==M) begin //This is actually the M+1th edge, and the Mth interval
//After M sig edges and n_clk clock edges,
//Handle case where n_clk=0 by saturating frequency at f=M*F_CLK.
if(n_clk==1'b0) n_clk_out=n_clk; //Case where no counts on clock are registered.
//Disallow jitter from changes in n_clk by +-2; only update frequency
//when clock counter is different by a number other than +-MIN_CHANGE.
else if ((n_clk>n_clk_last && n_clk-n_clk_last>MIN_CHANGE) || ( n_clk_last>n_clk && n_clk_last-n_clk>MIN_CHANGE) ) begin
n_clk_last=n_clk; //Store clock counter at last frequency change.
n_clk_out=n_clk; //Re-compute RF frequency.
end
n_sig=1'b0; //Zero out rf cycle counter.
reset=1'b1; //Set reset flag high to restart clock counter.
end else begin //Start incrementing signal positive edge counter.
reset=1'b0; //Set reset low and start counting clock cycles again.
n_sig=n_sig+1'b1; //Increment RF cycle counter.
end
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of ent_ac
//
// Generated
// by: wig
// on: Mon Oct 24 10:52:44 2005
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../verilog.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: ent_ac.v,v 1.1 2005/10/25 13:15:36 wig Exp $
// $Date: 2005/10/25 13:15:36 $
// $Log: ent_ac.v,v $
// Revision 1.1 2005/10/25 13:15:36 wig
// Testcase result update
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.62 2005/10/19 15:40:06 wig Exp
//
// Generator: mix_0.pl Revision: 1.38 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of ent_ac
//
// No `defines in this module
module ent_ac
//
// Generated module inst_ac
//
(
output wire port_ac_2 // Use internally test2, no port generated
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of ent_ac
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/**
* bsg_cache_miss.v
*
* miss handling unit.
*
* @author tommy
*
*/
`include "bsg_defines.v"
`include "bsg_cache.vh"
module bsg_cache_miss
import bsg_cache_pkg::*;
#(parameter `BSG_INV_PARAM(addr_width_p)
,parameter `BSG_INV_PARAM(data_width_p)
,parameter `BSG_INV_PARAM(block_size_in_words_p)
,parameter `BSG_INV_PARAM(sets_p)
,parameter `BSG_INV_PARAM(ways_p)
,parameter lg_block_size_in_words_lp=`BSG_SAFE_CLOG2(block_size_in_words_p)
,parameter lg_sets_lp=`BSG_SAFE_CLOG2(sets_p)
,parameter lg_data_mask_width_lp=`BSG_SAFE_CLOG2(data_width_p>>3)
,parameter block_offset_width_lp=(block_size_in_words_p > 1) ? lg_data_mask_width_lp+lg_block_size_in_words_lp : lg_data_mask_width_lp
,parameter tag_width_lp=(addr_width_p-lg_sets_lp-block_offset_width_lp)
,parameter tag_info_width_lp=`bsg_cache_tag_info_width(tag_width_lp)
,parameter lg_ways_lp=`BSG_SAFE_CLOG2(ways_p)
,parameter stat_info_width_lp=`bsg_cache_stat_info_width(ways_p)
)
(
input clk_i
,input reset_i
// from tv stage
,input miss_v_i
,input bsg_cache_decode_s decode_v_i
,input [addr_width_p-1:0] addr_v_i
,input [ways_p-1:0][tag_width_lp-1:0] tag_v_i
,input [ways_p-1:0] valid_v_i
,input [ways_p-1:0] lock_v_i
,input [ways_p-1:0] tag_hit_v_i
,input [lg_ways_lp-1:0] tag_hit_way_id_i
,input tag_hit_found_i
// from store buffer
,input sbuf_empty_i
// to dma engine
,output bsg_cache_dma_cmd_e dma_cmd_o
,output logic [lg_ways_lp-1:0] dma_way_o
,output logic [addr_width_p-1:0] dma_addr_o
,input dma_done_i
// from stat_mem
,input [stat_info_width_lp-1:0] stat_info_i
// to stat_mem
,output logic stat_mem_v_o
,output logic stat_mem_w_o
,output logic [lg_sets_lp-1:0] stat_mem_addr_o
,output logic [stat_info_width_lp-1:0] stat_mem_data_o
,output logic [stat_info_width_lp-1:0] stat_mem_w_mask_o
// to tag_mem
,output logic tag_mem_v_o
,output logic tag_mem_w_o
,output logic [lg_sets_lp-1:0] tag_mem_addr_o
,output logic [ways_p-1:0][tag_info_width_lp-1:0] tag_mem_data_o
,output logic [ways_p-1:0][tag_info_width_lp-1:0] tag_mem_w_mask_o
// to pipeline
,output logic done_o
,output logic recover_o
,output logic [lg_ways_lp-1:0] chosen_way_o
,output logic select_snoop_data_r_o
,input ack_i
);
// stat/tag info
//
`declare_bsg_cache_tag_info_s(tag_width_lp);
`declare_bsg_cache_stat_info_s(ways_p);
bsg_cache_stat_info_s stat_info_in;
assign stat_info_in = stat_info_i;
bsg_cache_tag_info_s [ways_p-1:0] tag_mem_data_out, tag_mem_w_mask_out;
bsg_cache_stat_info_s stat_mem_data_out, stat_mem_w_mask_out;
assign tag_mem_data_o = tag_mem_data_out;
assign stat_mem_data_o = stat_mem_data_out;
assign tag_mem_w_mask_o = tag_mem_w_mask_out;
assign stat_mem_w_mask_o = stat_mem_w_mask_out;
// Find the way that is invalid.
//
logic [lg_ways_lp-1:0] invalid_way_id;
logic invalid_exist;
bsg_priority_encode #(
.width_p(ways_p)
,.lo_to_hi_p(1)
) invalid_way_pe (
.i(~valid_v_i & ~lock_v_i) // invalid and unlocked
,.addr_o(invalid_way_id)
,.v_o(invalid_exist)
);
// miss handler FSM
//
typedef enum logic [3:0] {
START
,FLUSH_OP
,LOCK_OP
,SEND_EVICT_ADDR
,SEND_FILL_ADDR
,SEND_EVICT_DATA
,GET_FILL_DATA
,RECOVER
,DONE
} miss_state_e;
miss_state_e miss_state_r;
miss_state_e miss_state_n;
logic [lg_ways_lp-1:0] chosen_way_r, chosen_way_n;
logic [lg_ways_lp-1:0] flush_way_r, flush_way_n;
logic select_snoop_data_r, select_snoop_data_n;
// for flush/inv ops, go to FLUSH_OP.
// for AUNLOCK, or ALOCK with tag hit, to go LOCK_OP.
logic goto_flush_op;
logic goto_lock_op;
assign goto_flush_op = decode_v_i.tagfl_op| decode_v_i.ainv_op| decode_v_i.afl_op| decode_v_i.aflinv_op;
assign goto_lock_op = decode_v_i.aunlock_op | (decode_v_i.alock_op & tag_hit_found_i);
logic [tag_width_lp-1:0] addr_tag_v;
logic [lg_sets_lp-1:0] addr_index_v;
logic [lg_ways_lp-1:0] addr_way_v;
logic [lg_block_size_in_words_lp-1:0] addr_block_offset_v;
assign addr_index_v
= addr_v_i[block_offset_width_lp+:lg_sets_lp];
assign addr_tag_v
= addr_v_i[block_offset_width_lp+lg_sets_lp+:tag_width_lp];
assign addr_way_v
= addr_v_i[block_offset_width_lp+lg_sets_lp+:lg_ways_lp];
assign addr_block_offset_v
= addr_v_i[lg_data_mask_width_lp+:lg_block_size_in_words_lp];
assign stat_mem_addr_o = addr_index_v;
assign tag_mem_addr_o = addr_index_v;
assign chosen_way_o = chosen_way_r;
assign dma_way_o = goto_flush_op
? flush_way_r
: chosen_way_r;
// chosen way lru decode
//
logic [ways_p-2:0] chosen_way_lru_data;
logic [ways_p-2:0] chosen_way_lru_mask;
bsg_lru_pseudo_tree_decode #(
.ways_p(ways_p)
) chosen_way_lru_decode (
.way_id_i(chosen_way_r)
,.data_o(chosen_way_lru_data)
,.mask_o(chosen_way_lru_mask)
);
// backup LRU
// When the LRU way designated by the stats_mem_info is locked, a backup way is required for
// cache line replacement. In the current design, bsg_lru_pseudo_tree_backup takes the way with
// the shortest distance from the locked LRU way in the tree, as the backup option by overriding
// some of the LRU bits, so that it avoids "LRU trap" from insufficient update on the LRU bits.
// For now, there is not hardware logic to detect and handle the issue that all the ways in the
// same set are lock. And it is a programmer's responsibility to make sure that there is at least
// one unlock way in a set at any time.
// For future backup LRU enhancement project: For pseudo tree LRU algorithm, an efficient backup
// LRU algorithm should update the active LRU bits as much as possible, otherwise, it is very possible
// that the LRU way falls back to the same locked way soon and then forms "LRU trap"
logic [lg_ways_lp-1:0] lru_way_id;
logic [ways_p-2:0] modify_mask_lo;
logic [ways_p-2:0] modify_data_lo;
logic [ways_p-2:0] modified_lru_bits;
bsg_lru_pseudo_tree_backup #(
.ways_p(ways_p)
) backup_lru (
.disabled_ways_i(lock_v_i)
,.modify_mask_o(modify_mask_lo)
,.modify_data_o(modify_data_lo)
);
bsg_mux_bitwise #(
.width_p(ways_p-1)
) lru_bit_mux (
.data0_i(stat_info_in.lru_bits)
,.data1_i(modify_data_lo)
,.sel_i(modify_mask_lo)
,.data_o(modified_lru_bits)
);
bsg_lru_pseudo_tree_encode #(
.ways_p(ways_p)
) lru_encode (
.lru_i(modified_lru_bits)
,.way_id_o(lru_way_id)
);
// chosen way demux
//
logic [ways_p-1:0] chosen_way_decode;
bsg_decode #(
.num_out_p(ways_p)
) chosen_way_demux (
.i(chosen_way_n)
,.o(chosen_way_decode)
);
// flush way demux
logic [ways_p-1:0] addr_way_v_decode;
bsg_decode #(
.num_out_p(ways_p)
) addr_way_v_demux (
.i(addr_way_v)
,.o(addr_way_v_decode)
);
logic [ways_p-1:0] flush_way_decode;
assign flush_way_decode = decode_v_i.tagfl_op
? addr_way_v_decode
: tag_hit_v_i;
assign select_snoop_data_r_o = select_snoop_data_r;
always_comb begin
stat_mem_v_o = 1'b0;
stat_mem_w_o = 1'b0;
stat_mem_data_out = '0;
stat_mem_w_mask_out = '0;
tag_mem_v_o = 1'b0;
tag_mem_w_o = 1'b0;
tag_mem_data_out = '0;
tag_mem_w_mask_out = '0;
chosen_way_n = chosen_way_r;
flush_way_n = flush_way_r;
dma_addr_o = '0;
dma_cmd_o = e_dma_nop;
recover_o = '0;
done_o = '0;
select_snoop_data_n = select_snoop_data_r;
case (miss_state_r)
// miss handler waits in this state, until the miss is detected in tv
// stage.
START: begin
stat_mem_v_o = miss_v_i;
miss_state_n = miss_v_i
? (goto_flush_op
? FLUSH_OP
: (goto_lock_op
? LOCK_OP
: SEND_FILL_ADDR))
: START;
end
// Send out the missing cache block address (to read).
// Choose a block to replace/fill.
// If the chosen block is dirty, then take evict route.
SEND_FILL_ADDR: begin
// Replacement Policy:
// if an invalid and unlocked way exists, pick that.
// if not, pick the LRU way. But if the LRU way designated
// by stats_mem_info is locked, it will be overridden by
// the bsg_lru_pseudo_tree_backup
chosen_way_n = invalid_exist ? invalid_way_id : lru_way_id;
dma_cmd_o = e_dma_send_fill_addr;
dma_addr_o = {
addr_tag_v,
addr_index_v,
{(block_offset_width_lp){1'b0}}
};
// if the chosen way is dirty and valid, then evict.
miss_state_n = dma_done_i
? ((stat_info_in.dirty[chosen_way_n] & valid_v_i[chosen_way_n])
? SEND_EVICT_ADDR
: GET_FILL_DATA)
: SEND_FILL_ADDR;
end
// Handling the cases for TAGFL, AINV, AFL, AFLINV.
FLUSH_OP: begin
// for TAGFL, pick whichever way set by the addr input.
// Otherwise, pick the way with the tag hit.
flush_way_n = decode_v_i.tagfl_op
? addr_way_v
: tag_hit_way_id_i;
// Clear the dirty bit for the chosen set.
// LRU bit does not need to be updated.
stat_mem_v_o = 1'b1;
stat_mem_w_o = 1'b1;
stat_mem_data_out.dirty = {ways_p{1'b0}};
stat_mem_data_out.lru_bits = {(ways_p-1){1'b0}};
stat_mem_w_mask_out.dirty = flush_way_decode;
stat_mem_w_mask_out.lru_bits = {(ways_p-1){1'b0}};
// If it's invalidate op, then clear the valid bit for the chosen way.
// Otherwise, do not touch the valid bits.
tag_mem_v_o = 1'b1;
tag_mem_w_o = 1'b1;
for (integer i = 0; i < ways_p; i++) begin
tag_mem_data_out[i].valid = 1'b0;
tag_mem_data_out[i].lock = 1'b0;
tag_mem_data_out[i].tag = {tag_width_lp{1'b0}};
tag_mem_w_mask_out[i].valid = (decode_v_i.ainv_op | decode_v_i.aflinv_op) & flush_way_decode[i];
tag_mem_w_mask_out[i].lock = (decode_v_i.ainv_op | decode_v_i.aflinv_op) & flush_way_decode[i];
tag_mem_w_mask_out[i].tag = {tag_width_lp{1'b0}};
end
// If it's not AINV, and the chosen set is dirty and valid, evict the
// block.
miss_state_n = (~decode_v_i.ainv_op & stat_info_in.dirty[flush_way_n] & valid_v_i[flush_way_n])
? SEND_EVICT_ADDR
: RECOVER;
end
// handling AUNLOCK, and ALOCK with line not missing.
LOCK_OP: begin
tag_mem_v_o = 1'b1;
tag_mem_w_o = 1'b1;
for (integer i = 0; i < ways_p; i++) begin
tag_mem_data_out[i].valid = 1'b0;
tag_mem_data_out[i].lock = decode_v_i.alock_op;
tag_mem_data_out[i].tag = {tag_width_lp{1'b0}};
tag_mem_w_mask_out[i].valid = 1'b0;
tag_mem_w_mask_out[i].lock = tag_hit_v_i[i];
tag_mem_w_mask_out[i].tag = {tag_width_lp{1'b0}};
end
miss_state_n = RECOVER;
end
// Send out the block addr for eviction, before initiating the eviction.
SEND_EVICT_ADDR: begin
dma_cmd_o = e_dma_send_evict_addr;
dma_addr_o = {
tag_v_i[dma_way_o],
addr_index_v,
{(block_offset_width_lp){1'b0}}
};
miss_state_n = dma_done_i
? SEND_EVICT_DATA
: SEND_EVICT_ADDR;
end
// Set the DMA engine to evict the dirty block.
// For the flush ops, go straight to RECOVER.
SEND_EVICT_DATA: begin
dma_cmd_o = sbuf_empty_i
? e_dma_send_evict_data
: e_dma_nop;
dma_addr_o = {
tag_v_i[dma_way_o],
addr_index_v,
{(block_offset_width_lp){1'b0}}
};
miss_state_n = dma_done_i
? ((decode_v_i.tagfl_op| decode_v_i.aflinv_op| decode_v_i.afl_op) ? RECOVER : GET_FILL_DATA)
: SEND_EVICT_DATA;
end
// Set the DMA engine to start writing the new block to the data_mem.
// Do not start until the store buffer is empty.
GET_FILL_DATA: begin
dma_cmd_o = sbuf_empty_i
? e_dma_get_fill_data
: e_dma_nop;
dma_addr_o = {
addr_tag_v,
addr_index_v,
{(block_size_in_words_p > 1){addr_block_offset_v}}, // used for snoop data in dma.
{(lg_data_mask_width_lp){1'b0}}
};
// For store miss, set the dirty bit for the chosen way.
// For load miss, clear the dirty bit for the chosen way.
// Set the lru_bits, so that the chosen way is not the LRU.
// We are choosing a way to bring in a new block, which is technically
// the MRU. lru decode unit generates the next state LRU bits, so that
// the input way is "not" the LRU way.
stat_mem_v_o = dma_done_i;
stat_mem_w_o = dma_done_i;
stat_mem_data_out.dirty = {ways_p{decode_v_i.st_op | decode_v_i.atomic_op}};
stat_mem_data_out.lru_bits = chosen_way_lru_data;
stat_mem_w_mask_out.dirty = chosen_way_decode;
stat_mem_w_mask_out.lru_bits = chosen_way_lru_mask;
// set the tag and the valid bit to 1'b1 for the chosen way.
tag_mem_v_o = dma_done_i;
tag_mem_w_o = dma_done_i;
for (integer i = 0; i < ways_p; i++) begin
tag_mem_data_out[i].tag = addr_tag_v;
tag_mem_data_out[i].lock = decode_v_i.alock_op;
tag_mem_data_out[i].valid = 1'b1;
tag_mem_w_mask_out[i].tag = {tag_width_lp{chosen_way_decode[i]}};
tag_mem_w_mask_out[i].lock = chosen_way_decode[i];
tag_mem_w_mask_out[i].valid = chosen_way_decode[i];
end
select_snoop_data_n = dma_done_i
? 1'b1
: select_snoop_data_r;
miss_state_n = dma_done_i
? RECOVER
: GET_FILL_DATA;
end
// Spend one cycle to recover the tl stage.
// By recovering, it means re-reading the data_mem and tag_mem for the tl
// stage.
RECOVER: begin
recover_o = 1'b1;
miss_state_n = DONE;
end
// Miss handling is done. Output is valid.
// Move onto next state, when the output data is taken.
DONE: begin
done_o = 1'b1;
miss_state_n = ack_i ? START : DONE;
select_snoop_data_n = ack_i ? 1'b0 : select_snoop_data_r;
end
// this should never happen, but if it does, go back to START;
default: begin
miss_state_n = START;
end
endcase
end
// synopsys sync_set_reset "reset_i"
always_ff @ (posedge clk_i) begin
if (reset_i) begin
miss_state_r <= START;
chosen_way_r <= '0;
flush_way_r <= '0;
select_snoop_data_r <= 1'b0;
// added to be a little more X pessimism conservative
end
else begin
miss_state_r <= miss_state_n;
chosen_way_r <= chosen_way_n;
flush_way_r <= flush_way_n;
select_snoop_data_r <= select_snoop_data_n;
end
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_cache_miss)
|
module dly50ns(input clk, input reset, input in, output p);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 2'b1;
if(in)
r <= 1;
end
end
assign p = r == 2;
endmodule
module dly70ns(input clk, input reset, input in, output p);
reg [2-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 2'b1;
if(in)
r <= 1;
end
end
assign p = r == 3;
endmodule
module dly100ns(input clk, input reset, input in, output p);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 3'b1;
if(in)
r <= 1;
end
end
assign p = r == 5;
endmodule
module dly150ns(input clk, input reset, input in, output p);
reg [3-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 3'b1;
if(in)
r <= 1;
end
end
assign p = r == 7;
endmodule
module dly200ns(input clk, input reset, input in, output p);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 4'b1;
if(in)
r <= 1;
end
end
assign p = r == 10;
endmodule
module dly250ns(input clk, input reset, input in, output p);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 4'b1;
if(in)
r <= 1;
end
end
assign p = r == 12;
endmodule
module dly300ns(input clk, input reset, input in, output p);
reg [4-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 4'b1;
if(in)
r <= 1;
end
end
assign p = r == 15;
endmodule
module dly400ns(input clk, input reset, input in, output p);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 5'b1;
if(in)
r <= 1;
end
end
assign p = r == 20;
endmodule
module dly450ns(input clk, input reset, input in, output p);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 5'b1;
if(in)
r <= 1;
end
end
assign p = r == 22;
endmodule
module dly500ns(input clk, input reset, input in, output p);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 5'b1;
if(in)
r <= 1;
end
end
assign p = r == 25;
endmodule
module ldly500ns(input clk, input reset, input in, output p, output reg l);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 5'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 25;
endmodule
module dly550ns(input clk, input reset, input in, output p);
reg [5-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 5'b1;
if(in)
r <= 1;
end
end
assign p = r == 27;
endmodule
module dly750ns(input clk, input reset, input in, output p);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 6'b1;
if(in)
r <= 1;
end
end
assign p = r == 37;
endmodule
module dly800ns(input clk, input reset, input in, output p);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 6'b1;
if(in)
r <= 1;
end
end
assign p = r == 40;
endmodule
module dly1us(input clk, input reset, input in, output p);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 6'b1;
if(in)
r <= 1;
end
end
assign p = r == 50;
endmodule
module ldly1us(input clk, input reset, input in, output p, output reg l);
reg [6-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 6'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 50;
endmodule
module ldly1_5us(input clk, input reset, input in, output p, output reg l);
reg [7-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 7'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 75;
endmodule
module ldly2us(input clk, input reset, input in, output p, output reg l);
reg [7-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 7'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 100;
endmodule
module dly2_8us(input clk, input reset, input in, output p);
reg [8-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 8'b1;
if(in)
r <= 1;
end
end
assign p = r == 140;
endmodule
module dly35us(input clk, input reset, input in, output p);
reg [11-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 11'b1;
if(in)
r <= 1;
end
end
assign p = r == 1750;
endmodule
module dly100us(input clk, input reset, input in, output p);
reg [13-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 13'b1;
if(in)
r <= 1;
end
end
assign p = r == 5000;
endmodule
module ldly100us(input clk, input reset, input in, output p, output reg l);
reg [13-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 13'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 5000;
endmodule
module dly2_1ms(input clk, input reset, input in, output p);
reg [17-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 17'b1;
if(in)
r <= 1;
end
end
assign p = r == 105000;
endmodule
module dly2_5ms(input clk, input reset, input in, output p);
reg [17-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 17'b1;
if(in)
r <= 1;
end
end
assign p = r == 125000;
endmodule
module dly5ms(input clk, input reset, input in, output p);
reg [18-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset)
r <= 0;
else begin
if(r)
r <= r + 18'b1;
if(in)
r <= 1;
end
end
assign p = r == 250000;
endmodule
module ldly5ms(input clk, input reset, input in, output p, output reg l);
reg [18-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 18'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 250000;
endmodule
module ldly1s(input clk, input reset, input in, output p, output reg l);
reg [26-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 26'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 50000000;
endmodule
module ldly5s(input clk, input reset, input in, output p, output reg l);
reg [28-1:0] r;
always @(posedge clk or posedge reset) begin
if(reset) begin
r <= 0;
l <= 0;
end else begin
if(r)
r <= r + 28'b1;
if(in) begin
r <= 1;
l <= 1;
end
if(p) begin
r <= 0;
l <= 0;
end
end
end
assign p = r == 250000000;
endmodule
|
module top(input clk, ce, sr, d, output q);
/*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
cliff didn't have constrained, also got annoyed
he is using slightly later version
ERROR: [Place 30-1008] Instance roi/ffs[0].genblk1.genblk1.ff
has an inverted D pin which is unsupported in the UltraScale and UltraScale+ architectures.
which is fine except...he's using 7 series
and now...
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
ERROR: [Place 30-488] Failed to commit 1 instances:
ff with block Id: 4 (FF) at SLICE_X0Y104
ERROR: [Place 30-99] Placer failed with error: 'failed to commit all instances'
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b1,
failed with same message
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
built!
diff design_fdce.segd design_fdce_inv.segd
> tag CLBLL_L.SLICEL_X0.CLKINV
expected
IS_C_INVERTED=1'b0, IS_D_INVERTED=1'b1, IS_CLR_INVERTED=1'b0,
ERROR: [Place 30-1008] Instance ff has an inverted D pin which is expected to be used as an I/O flop.
However, it is used as a regular flop.
ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer stopped due to earlier errors.
Implementation Feasibility check failed, Please see the previously displayed individual error or warning messages for more details.'
*/
(*
IS_C_INVERTED=1'b1, IS_D_INVERTED=1'b0, IS_CLR_INVERTED=1'b0,
LOC="SLICE_X16Y100", BEL="AFF", DONT_TOUCH
*)
FDCE ff (
.C(clk),
.CE(ce),
.CLR(sr),
.D(d),
.Q(q)
);
endmodule
|
// file: system_clk_wiz_1_0.v
//
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// Output Output Phase Duty Cycle Pk-to-Pk Phase
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
//----------------------------------------------------------------------------
// clk_out1___200.000______0.000______50.0______114.829_____98.575
//
//----------------------------------------------------------------------------
// Input Clock Freq (MHz) Input Jitter (UI)
//----------------------------------------------------------------------------
// __primary_________100.000____________0.010
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "system_clk_wiz_1_0,clk_wiz_v5_3_3_0,{component_name=system_clk_wiz_1_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
module system_clk_wiz_1_0
(
// Clock out ports
output clk_out1,
// Clock in ports
input clk_in1
);
system_clk_wiz_1_0_clk_wiz inst
(
// Clock out ports
.clk_out1(clk_out1),
// Clock in ports
.clk_in1(clk_in1)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__BUFKAPWR_2_V
`define SKY130_FD_SC_LP__BUFKAPWR_2_V
/**
* bufkapwr: Buffer on keep-alive power rail.
*
* Verilog wrapper for bufkapwr with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__bufkapwr.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufkapwr_2 (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
sky130_fd_sc_lp__bufkapwr base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.KAPWR(KAPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__bufkapwr_2 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__bufkapwr base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__BUFKAPWR_2_V
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Tue Sep 19 09:38:57 2017
// Host : DarkCube running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_xbar_0_sim_netlist.v
// Design : zynq_design_1_xbar_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter
(\s_axi_arready[0] ,
aa_mi_arvalid,
D,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
s_axi_rlast_i0,
\m_axi_arqos[7] ,
E,
\gen_axi.s_axi_rid_i_reg[11] ,
\gen_no_arbiter.m_valid_i_reg_0 ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ,
\gen_no_arbiter.m_target_hot_i_reg[0]_0 ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
m_axi_arvalid,
aresetn_d_reg,
aclk,
SR,
r_issuing_cnt,
\gen_axi.read_cnt_reg[5] ,
p_15_in,
mi_arready_2,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
s_axi_arvalid,
\chosen_reg[0] ,
\gen_multi_thread.accept_cnt_reg[3] ,
st_aa_artarget_hot,
\s_axi_arqos[3] ,
\s_axi_araddr[30] ,
\s_axi_araddr[28] ,
\s_axi_araddr[25] ,
\m_payload_i_reg[34] ,
m_axi_arready,
\m_payload_i_reg[34]_0 ,
s_axi_rready,
m_valid_i_reg,
Q,
m_valid_i,
aresetn_d,
aresetn_d_reg_0);
output \s_axi_arready[0] ;
output aa_mi_arvalid;
output [2:0]D;
output [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
output s_axi_rlast_i0;
output [68:0]\m_axi_arqos[7] ;
output [0:0]E;
output [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
output \gen_no_arbiter.m_valid_i_reg_0 ;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ;
output [0:0]\gen_no_arbiter.m_target_hot_i_reg[0]_0 ;
output [0:0]\gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [0:0]\gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [1:0]m_axi_arvalid;
input aresetn_d_reg;
input aclk;
input [0:0]SR;
input [7:0]r_issuing_cnt;
input \gen_axi.read_cnt_reg[5] ;
input p_15_in;
input mi_arready_2;
input \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input [0:0]s_axi_arvalid;
input \chosen_reg[0] ;
input \gen_multi_thread.accept_cnt_reg[3] ;
input [0:0]st_aa_artarget_hot;
input [68:0]\s_axi_arqos[3] ;
input \s_axi_araddr[30] ;
input \s_axi_araddr[28] ;
input \s_axi_araddr[25] ;
input \m_payload_i_reg[34] ;
input [1:0]m_axi_arready;
input \m_payload_i_reg[34]_0 ;
input [0:0]s_axi_rready;
input m_valid_i_reg;
input [0:0]Q;
input m_valid_i;
input aresetn_d;
input aresetn_d_reg_0;
wire [2:0]D;
wire [0:0]E;
wire [0:0]Q;
wire [0:0]SR;
wire [1:0]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire aresetn_d_reg_0;
wire \chosen_reg[0] ;
wire \gen_axi.read_cnt_reg[5] ;
wire [0:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_axi.s_axi_rlast_i_i_6_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ;
wire \gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ;
wire [0:0]\gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ;
wire [2:0]\gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [0:0]\gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ;
wire \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[0]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1__0_n_0 ;
wire \gen_no_arbiter.m_valid_i_reg_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire [68:0]\m_axi_arqos[7] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire \m_payload_i_reg[34] ;
wire \m_payload_i_reg[34]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire mi_arready_2;
wire p_15_in;
wire [7:0]r_issuing_cnt;
wire \s_axi_araddr[25] ;
wire \s_axi_araddr[28] ;
wire \s_axi_araddr[30] ;
wire [68:0]\s_axi_arqos[3] ;
wire \s_axi_arready[0] ;
wire [0:0]s_axi_arvalid;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire s_ready_i2;
wire [0:0]st_aa_artarget_hot;
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0080))
\gen_axi.s_axi_rid_i[11]_i_1
(.I0(aa_mi_arvalid),
.I1(\gen_axi.s_axi_rid_i_reg[11] ),
.I2(mi_arready_2),
.I3(p_15_in),
.O(E));
LUT6 #(
.INIT(64'h444444444444444F))
\gen_axi.s_axi_rlast_i_i_2
(.I0(\gen_axi.read_cnt_reg[5] ),
.I1(p_15_in),
.I2(\gen_axi.s_axi_rlast_i_i_6_n_0 ),
.I3(\m_axi_arqos[7] [44]),
.I4(\m_axi_arqos[7] [45]),
.I5(\m_axi_arqos[7] [47]),
.O(s_axi_rlast_i0));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_axi.s_axi_rlast_i_i_6
(.I0(\m_axi_arqos[7] [49]),
.I1(p_15_in),
.I2(\m_axi_arqos[7] [48]),
.I3(\m_axi_arqos[7] [46]),
.I4(\m_axi_arqos[7] [51]),
.I5(\m_axi_arqos[7] [50]),
.O(\gen_axi.s_axi_rlast_i_i_6_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[0].r_issuing_cnt[1]_i_1
(.I0(r_issuing_cnt[0]),
.I1(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I2(r_issuing_cnt[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].r_issuing_cnt[2]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.I1(r_issuing_cnt[0]),
.I2(r_issuing_cnt[1]),
.I3(r_issuing_cnt[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h6666666666666662))
\gen_master_slots[0].r_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ),
.I1(\m_payload_i_reg[34] ),
.I2(r_issuing_cnt[0]),
.I3(r_issuing_cnt[1]),
.I4(r_issuing_cnt[2]),
.I5(r_issuing_cnt[3]),
.O(\gen_master_slots[0].r_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[0].r_issuing_cnt[3]_i_2
(.I0(r_issuing_cnt[3]),
.I1(r_issuing_cnt[2]),
.I2(r_issuing_cnt[1]),
.I3(r_issuing_cnt[0]),
.I4(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[0].r_issuing_cnt[3]_i_3
(.I0(m_axi_arready[0]),
.I1(aa_mi_artarget_hot[0]),
.I2(aa_mi_arvalid),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0080))
\gen_master_slots[0].r_issuing_cnt[3]_i_5
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.I2(m_axi_arready[0]),
.I3(\m_payload_i_reg[34] ),
.O(\gen_master_slots[0].r_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].r_issuing_cnt[10]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I1(r_issuing_cnt[4]),
.I2(r_issuing_cnt[5]),
.I3(r_issuing_cnt[6]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [1]));
LUT6 #(
.INIT(64'h6666666666666662))
\gen_master_slots[1].r_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ),
.I1(\m_payload_i_reg[34]_0 ),
.I2(r_issuing_cnt[4]),
.I3(r_issuing_cnt[5]),
.I4(r_issuing_cnt[6]),
.I5(r_issuing_cnt[7]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[8] ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[1].r_issuing_cnt[11]_i_2
(.I0(r_issuing_cnt[7]),
.I1(r_issuing_cnt[6]),
.I2(r_issuing_cnt[5]),
.I3(r_issuing_cnt[4]),
.I4(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [2]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[1].r_issuing_cnt[11]_i_3
(.I0(m_axi_arready[1]),
.I1(aa_mi_artarget_hot[1]),
.I2(aa_mi_arvalid),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0080808080808080))
\gen_master_slots[1].r_issuing_cnt[11]_i_5
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[1]),
.I2(m_axi_arready[1]),
.I3(s_axi_rready),
.I4(m_valid_i_reg),
.I5(Q),
.O(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_master_slots[1].r_issuing_cnt[9]_i_1
(.I0(r_issuing_cnt[4]),
.I1(\gen_master_slots[1].r_issuing_cnt[11]_i_5_n_0 ),
.I2(r_issuing_cnt[5]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] [0]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h80))
\gen_master_slots[2].r_issuing_cnt[16]_i_2
(.I0(mi_arready_2),
.I1(\gen_axi.s_axi_rid_i_reg[11] ),
.I2(aa_mi_arvalid),
.O(\gen_no_arbiter.m_valid_i_reg_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'hE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4__0
(.I0(st_aa_artarget_hot),
.I1(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1__0
(.I0(aa_mi_arvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [0]),
.Q(\m_axi_arqos[7] [0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [10]),
.Q(\m_axi_arqos[7] [10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [11]),
.Q(\m_axi_arqos[7] [11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [12]),
.Q(\m_axi_arqos[7] [12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [13]),
.Q(\m_axi_arqos[7] [13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [14]),
.Q(\m_axi_arqos[7] [14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [15]),
.Q(\m_axi_arqos[7] [15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [16]),
.Q(\m_axi_arqos[7] [16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [17]),
.Q(\m_axi_arqos[7] [17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [18]),
.Q(\m_axi_arqos[7] [18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [19]),
.Q(\m_axi_arqos[7] [19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [1]),
.Q(\m_axi_arqos[7] [1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [20]),
.Q(\m_axi_arqos[7] [20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [21]),
.Q(\m_axi_arqos[7] [21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [22]),
.Q(\m_axi_arqos[7] [22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [23]),
.Q(\m_axi_arqos[7] [23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [24]),
.Q(\m_axi_arqos[7] [24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [25]),
.Q(\m_axi_arqos[7] [25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [26]),
.Q(\m_axi_arqos[7] [26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [27]),
.Q(\m_axi_arqos[7] [27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [28]),
.Q(\m_axi_arqos[7] [28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [29]),
.Q(\m_axi_arqos[7] [29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [2]),
.Q(\m_axi_arqos[7] [2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [30]),
.Q(\m_axi_arqos[7] [30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [31]),
.Q(\m_axi_arqos[7] [31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [32]),
.Q(\m_axi_arqos[7] [32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [33]),
.Q(\m_axi_arqos[7] [33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [34]),
.Q(\m_axi_arqos[7] [34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [35]),
.Q(\m_axi_arqos[7] [35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [36]),
.Q(\m_axi_arqos[7] [36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [37]),
.Q(\m_axi_arqos[7] [37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [38]),
.Q(\m_axi_arqos[7] [38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [39]),
.Q(\m_axi_arqos[7] [39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [3]),
.Q(\m_axi_arqos[7] [3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [40]),
.Q(\m_axi_arqos[7] [40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [41]),
.Q(\m_axi_arqos[7] [41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [42]),
.Q(\m_axi_arqos[7] [42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [43]),
.Q(\m_axi_arqos[7] [43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [44]),
.Q(\m_axi_arqos[7] [44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [45]),
.Q(\m_axi_arqos[7] [45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [46]),
.Q(\m_axi_arqos[7] [46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [47]),
.Q(\m_axi_arqos[7] [47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [48]),
.Q(\m_axi_arqos[7] [48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [49]),
.Q(\m_axi_arqos[7] [49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [4]),
.Q(\m_axi_arqos[7] [4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [50]),
.Q(\m_axi_arqos[7] [50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [51]),
.Q(\m_axi_arqos[7] [51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [52]),
.Q(\m_axi_arqos[7] [52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [53]),
.Q(\m_axi_arqos[7] [53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [54]),
.Q(\m_axi_arqos[7] [54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [55]),
.Q(\m_axi_arqos[7] [55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [56]),
.Q(\m_axi_arqos[7] [56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [57]),
.Q(\m_axi_arqos[7] [57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [58]),
.Q(\m_axi_arqos[7] [58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [5]),
.Q(\m_axi_arqos[7] [5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [59]),
.Q(\m_axi_arqos[7] [59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [60]),
.Q(\m_axi_arqos[7] [60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [61]),
.Q(\m_axi_arqos[7] [61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [62]),
.Q(\m_axi_arqos[7] [62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [63]),
.Q(\m_axi_arqos[7] [63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [64]),
.Q(\m_axi_arqos[7] [64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [6]),
.Q(\m_axi_arqos[7] [6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [65]),
.Q(\m_axi_arqos[7] [65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [66]),
.Q(\m_axi_arqos[7] [66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [67]),
.Q(\m_axi_arqos[7] [67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [68]),
.Q(\m_axi_arqos[7] [68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [7]),
.Q(\m_axi_arqos[7] [7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [8]),
.Q(\m_axi_arqos[7] [8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_arqos[3] [9]),
.Q(\m_axi_arqos[7] [9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_artarget_hot[0]),
.O(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00000080))
\gen_no_arbiter.m_target_hot_i[0]_i_2
(.I0(\s_axi_arqos[3] [33]),
.I1(\s_axi_arqos[3] [36]),
.I2(\s_axi_araddr[30] ),
.I3(\s_axi_araddr[28] ),
.I4(\s_axi_araddr[25] ),
.O(\gen_no_arbiter.m_target_hot_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(st_aa_artarget_hot),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_artarget_hot[1]),
.O(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ),
.Q(aa_mi_artarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ),
.Q(aa_mi_artarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg_0),
.Q(\gen_axi.s_axi_rid_i_reg[11] ),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFFFFF0000002A))
\gen_no_arbiter.m_valid_i_i_1__0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.I2(m_axi_arready[0]),
.I3(\gen_master_slots[1].r_issuing_cnt[11]_i_3_n_0 ),
.I4(\gen_no_arbiter.m_valid_i_reg_0 ),
.I5(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1__0_n_0 ),
.Q(aa_mi_arvalid),
.R(SR));
LUT6 #(
.INIT(64'hFFEFFFEFFFEFFFFF))
\gen_no_arbiter.s_ready_i[0]_i_7__0
(.I0(\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.I1(aa_mi_arvalid),
.I2(s_axi_arvalid),
.I3(\s_axi_arready[0] ),
.I4(\chosen_reg[0] ),
.I5(\gen_multi_thread.accept_cnt_reg[3] ),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg),
.Q(\s_axi_arready[0] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[0]_INST_0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[0]),
.O(m_axi_arvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\m_axi_arvalid[1]_INST_0
(.I0(aa_mi_arvalid),
.I1(aa_mi_artarget_hot[1]),
.O(m_axi_arvalid[1]));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_addr_arbiter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0
(ss_aa_awready,
aa_sa_awvalid,
\m_ready_d_reg[0] ,
\m_ready_d_reg[1] ,
aa_mi_awtarget_hot,
D,
\gen_master_slots[1].w_issuing_cnt_reg[9] ,
\gen_master_slots[0].w_issuing_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
E,
\gen_master_slots[0].w_issuing_cnt_reg[0] ,
m_axi_awvalid,
st_aa_awtarget_hot,
\gen_no_arbiter.m_target_hot_i_reg[2]_0 ,
\m_ready_d_reg[1]_0 ,
Q,
aresetn_d_reg,
aclk,
SR,
m_ready_d,
aresetn_d,
w_issuing_cnt,
\chosen_reg[1] ,
m_axi_awready,
\chosen_reg[0] ,
mi_awready_2,
m_valid_i_reg,
s_axi_bready,
\s_axi_awaddr[26] ,
\s_axi_awaddr[20] ,
\s_axi_awqos[3] ,
m_ready_d_0,
m_valid_i,
st_aa_awtarget_enc,
aresetn_d_reg_0);
output ss_aa_awready;
output aa_sa_awvalid;
output \m_ready_d_reg[0] ;
output \m_ready_d_reg[1] ;
output [2:0]aa_mi_awtarget_hot;
output [2:0]D;
output \gen_master_slots[1].w_issuing_cnt_reg[9] ;
output [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]E;
output [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
output [1:0]m_axi_awvalid;
output [0:0]st_aa_awtarget_hot;
output \gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
output \m_ready_d_reg[1]_0 ;
output [68:0]Q;
input aresetn_d_reg;
input aclk;
input [0:0]SR;
input [1:0]m_ready_d;
input aresetn_d;
input [7:0]w_issuing_cnt;
input \chosen_reg[1] ;
input [1:0]m_axi_awready;
input \chosen_reg[0] ;
input mi_awready_2;
input m_valid_i_reg;
input [0:0]s_axi_bready;
input \s_axi_awaddr[26] ;
input \s_axi_awaddr[20] ;
input [68:0]\s_axi_awqos[3] ;
input [0:0]m_ready_d_0;
input m_valid_i;
input [0:0]st_aa_awtarget_enc;
input aresetn_d_reg_0;
wire [2:0]D;
wire [0:0]E;
wire [68:0]Q;
wire [0:0]SR;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire aresetn_d_reg;
wire aresetn_d_reg_0;
wire \chosen_reg[0] ;
wire \chosen_reg[1] ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ;
wire \gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ;
wire [0:0]\gen_master_slots[0].w_issuing_cnt_reg[0] ;
wire [2:0]\gen_master_slots[0].w_issuing_cnt_reg[3] ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ;
wire \gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ;
wire \gen_master_slots[1].w_issuing_cnt_reg[9] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
wire \gen_no_arbiter.m_valid_i_i_1_n_0 ;
wire \gen_no_arbiter.m_valid_i_i_2_n_0 ;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [1:0]m_ready_d;
wire \m_ready_d[1]_i_4_n_0 ;
wire [0:0]m_ready_d_0;
wire \m_ready_d_reg[0] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire mi_awready_2;
wire \s_axi_awaddr[20] ;
wire \s_axi_awaddr[26] ;
wire [68:0]\s_axi_awqos[3] ;
wire [0:0]s_axi_bready;
wire s_ready_i2;
wire ss_aa_awready;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [7:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'h4000))
\gen_axi.s_axi_wready_i_i_2
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[2]),
.I3(mi_awready_2),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16] ));
LUT6 #(
.INIT(64'h6AAAAAAA95555555))
\gen_master_slots[0].w_issuing_cnt[1]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\chosen_reg[0] ),
.I2(m_axi_awready[0]),
.I3(aa_mi_awtarget_hot[0]),
.I4(\gen_master_slots[1].w_issuing_cnt_reg[9] ),
.I5(w_issuing_cnt[1]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[0].w_issuing_cnt[2]_i_1
(.I0(w_issuing_cnt[0]),
.I1(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [1]));
LUT6 #(
.INIT(64'hAAAAAAAA55555554))
\gen_master_slots[0].w_issuing_cnt[3]_i_1
(.I0(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ),
.I1(w_issuing_cnt[3]),
.I2(w_issuing_cnt[0]),
.I3(w_issuing_cnt[2]),
.I4(w_issuing_cnt[1]),
.I5(\chosen_reg[0] ),
.O(\gen_master_slots[0].w_issuing_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[0].w_issuing_cnt[3]_i_2
(.I0(w_issuing_cnt[3]),
.I1(w_issuing_cnt[0]),
.I2(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ),
.I3(w_issuing_cnt[1]),
.I4(w_issuing_cnt[2]),
.O(\gen_master_slots[0].w_issuing_cnt_reg[3] [2]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h4000))
\gen_master_slots[0].w_issuing_cnt[3]_i_3
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[0]),
.I3(m_axi_awready[0]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT5 #(
.INIT(32'h00008000))
\gen_master_slots[0].w_issuing_cnt[3]_i_5
(.I0(\chosen_reg[0] ),
.I1(m_axi_awready[0]),
.I2(aa_mi_awtarget_hot[0]),
.I3(aa_sa_awvalid),
.I4(m_ready_d[1]),
.O(\gen_master_slots[0].w_issuing_cnt[3]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h7E81))
\gen_master_slots[1].w_issuing_cnt[10]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I2(w_issuing_cnt[5]),
.I3(w_issuing_cnt[6]),
.O(D[1]));
LUT6 #(
.INIT(64'hAAAAAAAA55555554))
\gen_master_slots[1].w_issuing_cnt[11]_i_1
(.I0(\gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ),
.I1(w_issuing_cnt[7]),
.I2(w_issuing_cnt[4]),
.I3(w_issuing_cnt[6]),
.I4(w_issuing_cnt[5]),
.I5(\chosen_reg[1] ),
.O(E));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_master_slots[1].w_issuing_cnt[11]_i_2
(.I0(w_issuing_cnt[7]),
.I1(w_issuing_cnt[4]),
.I2(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ),
.I3(w_issuing_cnt[5]),
.I4(w_issuing_cnt[6]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h4000))
\gen_master_slots[1].w_issuing_cnt[11]_i_3
(.I0(m_ready_d[1]),
.I1(aa_sa_awvalid),
.I2(aa_mi_awtarget_hot[1]),
.I3(m_axi_awready[1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000070000000))
\gen_master_slots[1].w_issuing_cnt[11]_i_5
(.I0(m_valid_i_reg),
.I1(s_axi_bready),
.I2(m_axi_awready[1]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_sa_awvalid),
.I5(m_ready_d[1]),
.O(\gen_master_slots[1].w_issuing_cnt[11]_i_5_n_0 ));
LUT6 #(
.INIT(64'h6AAAAAAA95555555))
\gen_master_slots[1].w_issuing_cnt[9]_i_1
(.I0(w_issuing_cnt[4]),
.I1(\chosen_reg[1] ),
.I2(m_axi_awready[1]),
.I3(aa_mi_awtarget_hot[1]),
.I4(\gen_master_slots[1].w_issuing_cnt_reg[9] ),
.I5(w_issuing_cnt[5]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h2))
\gen_master_slots[1].w_issuing_cnt[9]_i_2
(.I0(aa_sa_awvalid),
.I1(m_ready_d[1]),
.O(\gen_master_slots[1].w_issuing_cnt_reg[9] ));
LUT5 #(
.INIT(32'h10000000))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ),
.I1(\s_axi_awaddr[26] ),
.I2(\s_axi_awaddr[20] ),
.I3(\s_axi_awqos[3] [33]),
.I4(\s_axi_awqos[3] [36]),
.O(st_aa_awtarget_hot));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9
(.I0(\s_axi_awqos[3] [35]),
.I1(\s_axi_awqos[3] [31]),
.I2(\s_axi_awqos[3] [28]),
.I3(\s_axi_awqos[3] [39]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_9_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_2
(.I0(aa_sa_awvalid),
.O(s_ready_i2));
FDRE \gen_no_arbiter.m_mesg_i_reg[0]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [0]),
.Q(Q[0]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[10]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [10]),
.Q(Q[10]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[11]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [11]),
.Q(Q[11]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[12]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [12]),
.Q(Q[12]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[13]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [13]),
.Q(Q[13]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[14]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [14]),
.Q(Q[14]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[15]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [15]),
.Q(Q[15]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[16]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [16]),
.Q(Q[16]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[17]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [17]),
.Q(Q[17]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[18]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [18]),
.Q(Q[18]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[19]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [19]),
.Q(Q[19]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[1]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [1]),
.Q(Q[1]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[20]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [20]),
.Q(Q[20]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[21]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [21]),
.Q(Q[21]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[22]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [22]),
.Q(Q[22]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[23]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [23]),
.Q(Q[23]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[24]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [24]),
.Q(Q[24]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[25]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [25]),
.Q(Q[25]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[26]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [26]),
.Q(Q[26]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[27]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [27]),
.Q(Q[27]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[28]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [28]),
.Q(Q[28]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[29]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [29]),
.Q(Q[29]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[2]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [2]),
.Q(Q[2]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[30]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [30]),
.Q(Q[30]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[31]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [31]),
.Q(Q[31]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[32]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [32]),
.Q(Q[32]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[33]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [33]),
.Q(Q[33]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[34]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [34]),
.Q(Q[34]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[35]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [35]),
.Q(Q[35]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[36]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [36]),
.Q(Q[36]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[37]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [37]),
.Q(Q[37]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[38]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [38]),
.Q(Q[38]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[39]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [39]),
.Q(Q[39]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[3]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [3]),
.Q(Q[3]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[40]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [40]),
.Q(Q[40]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[41]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [41]),
.Q(Q[41]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[42]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [42]),
.Q(Q[42]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[43]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [43]),
.Q(Q[43]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[44]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [44]),
.Q(Q[44]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[45]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [45]),
.Q(Q[45]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[46]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [46]),
.Q(Q[46]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[47]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [47]),
.Q(Q[47]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[48]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [48]),
.Q(Q[48]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[49]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [49]),
.Q(Q[49]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[4]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [4]),
.Q(Q[4]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[50]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [50]),
.Q(Q[50]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[51]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [51]),
.Q(Q[51]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[52]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [52]),
.Q(Q[52]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[53]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [53]),
.Q(Q[53]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[54]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [54]),
.Q(Q[54]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[55]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [55]),
.Q(Q[55]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[57]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [56]),
.Q(Q[56]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[58]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [57]),
.Q(Q[57]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[59]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [58]),
.Q(Q[58]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[5]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [5]),
.Q(Q[5]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[64]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [59]),
.Q(Q[59]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[65]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [60]),
.Q(Q[60]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[66]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [61]),
.Q(Q[61]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[67]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [62]),
.Q(Q[62]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[68]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [63]),
.Q(Q[63]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[69]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [64]),
.Q(Q[64]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[6]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [6]),
.Q(Q[6]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[70]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [65]),
.Q(Q[65]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[71]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [66]),
.Q(Q[66]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[72]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [67]),
.Q(Q[67]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[73]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [68]),
.Q(Q[68]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[7]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [7]),
.Q(Q[7]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[8]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [8]),
.Q(Q[8]),
.R(SR));
FDRE \gen_no_arbiter.m_mesg_i_reg[9]
(.C(aclk),
.CE(s_ready_i2),
.D(\s_axi_awqos[3] [9]),
.Q(Q[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[0]_i_1
(.I0(st_aa_awtarget_hot),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_awtarget_hot[0]),
.O(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ));
LUT4 #(
.INIT(16'hBF80))
\gen_no_arbiter.m_target_hot_i[1]_i_1
(.I0(st_aa_awtarget_enc),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(aa_mi_awtarget_hot[1]),
.O(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ));
FDRE \gen_no_arbiter.m_target_hot_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[0]_i_1_n_0 ),
.Q(aa_mi_awtarget_hot[0]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_target_hot_i[1]_i_1_n_0 ),
.Q(aa_mi_awtarget_hot[1]),
.R(1'b0));
FDRE \gen_no_arbiter.m_target_hot_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg_0),
.Q(aa_mi_awtarget_hot[2]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hF2))
\gen_no_arbiter.m_valid_i_i_1
(.I0(aa_sa_awvalid),
.I1(\gen_no_arbiter.m_valid_i_i_2_n_0 ),
.I2(m_valid_i),
.O(\gen_no_arbiter.m_valid_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT5 #(
.INIT(32'h0000FFFE))
\gen_no_arbiter.m_valid_i_i_2
(.I0(aa_mi_awtarget_hot[0]),
.I1(aa_mi_awtarget_hot[1]),
.I2(aa_mi_awtarget_hot[2]),
.I3(m_ready_d[0]),
.I4(\m_ready_d_reg[1] ),
.O(\gen_no_arbiter.m_valid_i_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_no_arbiter.m_valid_i_i_1_n_0 ),
.Q(aa_sa_awvalid),
.R(SR));
LUT2 #(
.INIT(4'hE))
\gen_no_arbiter.s_ready_i[0]_i_29
(.I0(ss_aa_awready),
.I1(m_ready_d_0),
.O(\gen_no_arbiter.m_target_hot_i_reg[2]_0 ));
FDRE #(
.INIT(1'b0))
\gen_no_arbiter.s_ready_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn_d_reg),
.Q(ss_aa_awready),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h20))
\m_axi_awvalid[0]_INST_0
(.I0(aa_mi_awtarget_hot[0]),
.I1(m_ready_d[1]),
.I2(aa_sa_awvalid),
.O(m_axi_awvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h20))
\m_axi_awvalid[1]_INST_0
(.I0(aa_mi_awtarget_hot[1]),
.I1(m_ready_d[1]),
.I2(aa_sa_awvalid),
.O(m_axi_awvalid[1]));
LUT6 #(
.INIT(64'h55555554FFFFFFFF))
\m_ready_d[0]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(m_ready_d[0]),
.I2(aa_mi_awtarget_hot[2]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_mi_awtarget_hot[0]),
.I5(aresetn_d),
.O(\m_ready_d_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hFFFE))
\m_ready_d[1]_i_2
(.I0(m_ready_d[0]),
.I1(aa_mi_awtarget_hot[2]),
.I2(aa_mi_awtarget_hot[1]),
.I3(aa_mi_awtarget_hot[0]),
.O(\m_ready_d_reg[1]_0 ));
LUT6 #(
.INIT(64'h0000000000000777))
\m_ready_d[1]_i_3
(.I0(m_axi_awready[1]),
.I1(aa_mi_awtarget_hot[1]),
.I2(mi_awready_2),
.I3(aa_mi_awtarget_hot[2]),
.I4(\m_ready_d[1]_i_4_n_0 ),
.I5(m_ready_d[1]),
.O(\m_ready_d_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h8))
\m_ready_d[1]_i_4
(.I0(m_axi_awready[0]),
.I1(aa_mi_awtarget_hot[0]),
.O(\m_ready_d[1]_i_4_n_0 ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
D,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
\chosen_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
SR,
E,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
s_axi_bvalid,
\chosen_reg[1]_0 ,
\gen_master_slots[1].w_issuing_cnt_reg[8] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ,
aresetn_d,
Q,
\m_ready_d_reg[1] ,
p_80_out,
s_axi_bready,
\s_axi_awaddr[26] ,
st_aa_awtarget_hot,
aa_mi_awtarget_hot,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ,
\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ,
\gen_master_slots[1].w_issuing_cnt_reg[10] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_1 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ,
CO,
\m_ready_d_reg[1]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ,
\m_ready_d_reg[1]_1 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
\m_ready_d_reg[1]_2 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
cmd_push_3,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ,
\m_ready_d_reg[1]_3 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
\m_ready_d_reg[1]_4 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
cmd_push_0,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ,
\gen_multi_thread.accept_cnt_reg[0] ,
aa_sa_awvalid,
s_axi_awvalid,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
m_valid_i_reg,
p_38_out,
p_60_out,
w_issuing_cnt,
\m_ready_d_reg[1]_5 ,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output [2:0]D;
output \gen_master_slots[0].w_issuing_cnt_reg[1] ;
output \chosen_reg[0]_0 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]SR;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
output [0:0]s_axi_bvalid;
output \chosen_reg[1]_0 ;
output \gen_master_slots[1].w_issuing_cnt_reg[8] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
input aresetn_d;
input [3:0]Q;
input \m_ready_d_reg[1] ;
input p_80_out;
input [0:0]s_axi_bready;
input [0:0]\s_axi_awaddr[26] ;
input [0:0]st_aa_awtarget_hot;
input [0:0]aa_mi_awtarget_hot;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ;
input \gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ;
input \gen_master_slots[1].w_issuing_cnt_reg[10] ;
input \gen_master_slots[2].w_issuing_cnt_reg[16]_1 ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ;
input [0:0]CO;
input \m_ready_d_reg[1]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
input \m_ready_d_reg[1]_1 ;
input \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input \m_ready_d_reg[1]_2 ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input cmd_push_3;
input \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
input \m_ready_d_reg[1]_3 ;
input \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input \m_ready_d_reg[1]_4 ;
input \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input cmd_push_0;
input \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
input [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
input \gen_multi_thread.accept_cnt_reg[0] ;
input aa_sa_awvalid;
input [0:0]s_axi_awvalid;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input m_valid_i_reg;
input p_38_out;
input p_60_out;
input [4:0]w_issuing_cnt;
input \m_ready_d_reg[1]_5 ;
input aclk;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [0:0]SR;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \chosen[0]_i_1__0_n_0 ;
wire \chosen[1]_i_1__0_n_0 ;
wire \chosen[2]_i_1__0_n_0 ;
wire \chosen_reg[0]_0 ;
wire \chosen_reg[1]_0 ;
wire cmd_push_0;
wire cmd_push_3;
wire \gen_master_slots[0].w_issuing_cnt_reg[1] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[10] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_1 ;
wire \gen_multi_thread.accept_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire \gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire \gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i[0]_i_24_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_25_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_7_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \last_rr_hot[0]_i_1_n_0 ;
wire \last_rr_hot[1]_i_1_n_0 ;
wire \last_rr_hot[2]_i_1_n_0 ;
wire \last_rr_hot[2]_i_6_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire \m_ready_d_reg[1]_1 ;
wire \m_ready_d_reg[1]_2 ;
wire \m_ready_d_reg[1]_3 ;
wire \m_ready_d_reg[1]_4 ;
wire \m_ready_d_reg[1]_5 ;
wire m_valid_i;
wire m_valid_i_reg;
wire need_arbitration;
wire [2:0]next_rr_hot;
wire p_38_out;
wire p_3_in;
wire p_4_in;
wire p_60_out;
wire p_80_out;
wire [0:0]\s_axi_awaddr[26] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]st_aa_awtarget_hot;
wire [4:0]w_issuing_cnt;
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\chosen[0]_i_1__0
(.I0(next_rr_hot[0]),
.I1(need_arbitration),
.I2(\chosen_reg[0]_0 ),
.O(\chosen[0]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\chosen[1]_i_1__0
(.I0(next_rr_hot[1]),
.I1(need_arbitration),
.I2(\chosen_reg[1]_0 ),
.O(\chosen[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair112" *)
LUT3 #(
.INIT(8'hB8))
\chosen[2]_i_1__0
(.I0(next_rr_hot[2]),
.I1(need_arbitration),
.I2(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.O(\chosen[2]_i_1__0_n_0 ));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\chosen[0]_i_1__0_n_0 ),
.Q(\chosen_reg[0]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\chosen[1]_i_1__0_n_0 ),
.Q(\chosen_reg[1]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\chosen[2]_i_1__0_n_0 ),
.Q(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.R(SR));
LUT3 #(
.INIT(8'h7F))
\gen_master_slots[0].w_issuing_cnt[3]_i_4
(.I0(\chosen_reg[0]_0 ),
.I1(p_80_out),
.I2(s_axi_bready),
.O(\gen_master_slots[0].w_issuing_cnt_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT3 #(
.INIT(8'h7F))
\gen_master_slots[1].w_issuing_cnt[11]_i_4
(.I0(s_axi_bready),
.I1(\chosen_reg[1]_0 ),
.I2(p_60_out),
.O(\gen_master_slots[1].w_issuing_cnt_reg[8] ));
LUT5 #(
.INIT(32'h807F7F00))
\gen_master_slots[2].w_issuing_cnt[16]_i_1
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(s_axi_bready),
.I3(\m_ready_d_reg[1]_5 ),
.I4(w_issuing_cnt[4]),
.O(\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT4 #(
.INIT(16'hA956))
\gen_multi_thread.accept_cnt[1]_i_1
(.I0(Q[0]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\m_ready_d_reg[1] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair110" *)
LUT5 #(
.INIT(32'hEFF1100E))
\gen_multi_thread.accept_cnt[2]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'hFFFE00000000FFFF))
\gen_multi_thread.accept_cnt[3]_i_1
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hAAA6AAAAAAAA999A))
\gen_multi_thread.accept_cnt[3]_i_2
(.I0(Q[3]),
.I1(Q[0]),
.I2(\m_ready_d_reg[1] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I4(Q[1]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1
(.I0(cmd_push_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1
(.I0(\m_ready_d_reg[1]_4 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1
(.I0(\m_ready_d_reg[1]_3 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1
(.I0(cmd_push_3),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1
(.I0(\m_ready_d_reg[1]_2 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1
(.I0(\m_ready_d_reg[1]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1
(.I0(\m_ready_d_reg[1]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] ),
.I3(CO),
.O(E));
LUT6 #(
.INIT(64'h00AAAA80AA80AA80))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3
(.I0(s_axi_bready),
.I1(\chosen_reg[0]_0 ),
.I2(p_80_out),
.I3(m_valid_i_reg),
.I4(p_38_out),
.I5(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_no_arbiter.m_mesg_i[11]_i_1
(.I0(aresetn_d),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT5 #(
.INIT(32'h1FFF1000))
\gen_no_arbiter.m_target_hot_i[2]_i_1
(.I0(\s_axi_awaddr[26] ),
.I1(st_aa_awtarget_hot),
.I2(m_valid_i),
.I3(aresetn_d),
.I4(aa_mi_awtarget_hot),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
(* SOFT_HLUTNM = "soft_lutpair109" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h000000000000F022))
\gen_no_arbiter.s_ready_i[0]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] ),
.I3(\s_axi_awaddr[26] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ),
.O(m_valid_i));
LUT6 #(
.INIT(64'hFFFFFFFFFF40FFFF))
\gen_no_arbiter.s_ready_i[0]_i_24
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3_n_0 ),
.I1(Q[3]),
.I2(\gen_multi_thread.accept_cnt_reg[0] ),
.I3(aa_sa_awvalid),
.I4(s_axi_awvalid),
.I5(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ));
LUT5 #(
.INIT(32'h00020000))
\gen_no_arbiter.s_ready_i[0]_i_25
(.I0(\gen_master_slots[0].w_issuing_cnt_reg[1] ),
.I1(w_issuing_cnt[2]),
.I2(w_issuing_cnt[1]),
.I3(w_issuing_cnt[0]),
.I4(w_issuing_cnt[3]),
.O(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ));
LUT6 #(
.INIT(64'hEFAAEFEFEFAAEAEA))
\gen_no_arbiter.s_ready_i[0]_i_7
(.I0(\gen_no_arbiter.s_ready_i[0]_i_24_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25_n_0 ),
.I2(st_aa_awtarget_hot),
.I3(\gen_master_slots[1].w_issuing_cnt_reg[10] ),
.I4(\s_axi_awaddr[26] ),
.I5(\gen_master_slots[2].w_issuing_cnt_reg[16]_1 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hFF57AA00))
\last_rr_hot[0]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hF5F7A0A0))
\last_rr_hot[1]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_3_in),
.O(\last_rr_hot[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hDDDF8888))
\last_rr_hot[2]_i_1
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_4_in),
.O(\last_rr_hot[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEE00000FEE))
\last_rr_hot[2]_i_2
(.I0(p_60_out),
.I1(p_38_out),
.I2(\chosen_reg[0]_0 ),
.I3(p_80_out),
.I4(\last_rr_hot[2]_i_6_n_0 ),
.I5(s_axi_bready),
.O(need_arbitration));
LUT6 #(
.INIT(64'hAAAAAAAA20222020))
\last_rr_hot[2]_i_3__0
(.I0(p_38_out),
.I1(p_60_out),
.I2(\last_rr_hot_reg_n_0_[0] ),
.I3(p_80_out),
.I4(p_4_in),
.I5(p_3_in),
.O(next_rr_hot[2]));
LUT6 #(
.INIT(64'hAAAAAAAA0A0A0008))
\last_rr_hot[2]_i_4__0
(.I0(p_60_out),
.I1(p_3_in),
.I2(p_80_out),
.I3(p_38_out),
.I4(p_4_in),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[1]));
LUT6 #(
.INIT(64'h8A8A8A8A88888A88))
\last_rr_hot[2]_i_5__0
(.I0(p_80_out),
.I1(p_4_in),
.I2(p_38_out),
.I3(\last_rr_hot_reg_n_0_[0] ),
.I4(p_60_out),
.I5(p_3_in),
.O(next_rr_hot[0]));
(* SOFT_HLUTNM = "soft_lutpair111" *)
LUT4 #(
.INIT(16'hF888))
\last_rr_hot[2]_i_6
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_60_out),
.O(\last_rr_hot[2]_i_6_n_0 ));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[0]_i_1_n_0 ),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[1]_i_1_n_0 ),
.Q(p_3_in),
.R(SR));
FDSE \last_rr_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[2]_i_1_n_0 ),
.Q(p_4_in),
.S(SR));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_bvalid[0]_INST_0
(.I0(\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.I1(p_38_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_60_out),
.I4(p_80_out),
.I5(\chosen_reg[0]_0 ),
.O(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_arbiter_resp" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5
(D,
\gen_multi_thread.accept_cnt_reg[2] ,
E,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
\m_payload_i_reg[0] ,
\m_payload_i_reg[0]_0 ,
s_axi_rlast,
s_axi_rvalid,
\chosen_reg[1]_0 ,
\m_payload_i_reg[34] ,
s_axi_rresp,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
s_axi_rid,
s_axi_rdata,
\m_payload_i_reg[34]_0 ,
Q,
\gen_no_arbiter.s_ready_i_reg[0] ,
cmd_push_3,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ,
CO,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ,
\gen_no_arbiter.s_ready_i_reg[0]_1 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ,
\gen_no_arbiter.s_ready_i_reg[0]_2 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ,
\gen_no_arbiter.s_ready_i_reg[0]_3 ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ,
\gen_no_arbiter.s_ready_i_reg[0]_4 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ,
\gen_no_arbiter.s_ready_i_reg[0]_5 ,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ,
cmd_push_0,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ,
p_74_out,
s_axi_rready,
p_54_out,
p_32_out,
\m_payload_i_reg[46] ,
\m_payload_i_reg[46]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ,
\m_payload_i_reg[46]_1 ,
SR,
aclk);
output [2:0]D;
output \gen_multi_thread.accept_cnt_reg[2] ;
output [0:0]E;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
output [0:0]\m_payload_i_reg[0] ;
output \m_payload_i_reg[0]_0 ;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output \chosen_reg[1]_0 ;
output \m_payload_i_reg[34] ;
output [0:0]s_axi_rresp;
output [3:0]S;
output [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [3:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output [11:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[34]_0 ;
input [3:0]Q;
input \gen_no_arbiter.s_ready_i_reg[0] ;
input cmd_push_3;
input \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
input [0:0]CO;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
input \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ;
input \gen_no_arbiter.s_ready_i_reg[0]_1 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
input \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
input \gen_no_arbiter.s_ready_i_reg[0]_2 ;
input \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
input \gen_no_arbiter.s_ready_i_reg[0]_3 ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
input \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ;
input \gen_no_arbiter.s_ready_i_reg[0]_4 ;
input \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
input \gen_no_arbiter.s_ready_i_reg[0]_5 ;
input \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
input cmd_push_0;
input \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
input [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
input p_74_out;
input [0:0]s_axi_rready;
input p_54_out;
input p_32_out;
input [25:0]\m_payload_i_reg[46] ;
input [25:0]\m_payload_i_reg[46]_0 ;
input [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
input [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
input [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
input [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
input [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
input [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
input [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
input [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
input [12:0]\m_payload_i_reg[46]_1 ;
input [0:0]SR;
input aclk;
wire [0:0]CO;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]S;
wire [0:0]SR;
wire aclk;
wire \chosen[0]_i_1_n_0 ;
wire \chosen[1]_i_1_n_0 ;
wire \chosen[2]_i_1_n_0 ;
wire \chosen_reg[1]_0 ;
wire cmd_push_0;
wire cmd_push_3;
wire \gen_multi_thread.accept_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [3:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_1 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_2 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_3 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_4 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_5 ;
wire i__carry_i_10_n_0;
wire i__carry_i_11_n_0;
wire i__carry_i_12_n_0;
wire i__carry_i_13_n_0;
wire i__carry_i_14_n_0;
wire i__carry_i_15_n_0;
wire i__carry_i_16_n_0;
wire i__carry_i_5_n_0;
wire i__carry_i_6_n_0;
wire i__carry_i_7_n_0;
wire i__carry_i_8_n_0;
wire i__carry_i_9_n_0;
wire \last_rr_hot[0]_i_1__0_n_0 ;
wire \last_rr_hot[1]_i_1__0_n_0 ;
wire \last_rr_hot[2]_i_1__0_n_0 ;
wire \last_rr_hot_reg_n_0_[0] ;
wire [0:0]\m_payload_i_reg[0] ;
wire \m_payload_i_reg[0]_0 ;
wire \m_payload_i_reg[34] ;
wire [0:0]\m_payload_i_reg[34]_0 ;
wire [25:0]\m_payload_i_reg[46] ;
wire [25:0]\m_payload_i_reg[46]_0 ;
wire [12:0]\m_payload_i_reg[46]_1 ;
wire need_arbitration;
wire [2:0]next_rr_hot;
wire p_32_out;
wire p_3_in;
wire p_4_in;
wire p_54_out;
wire p_74_out;
wire [11:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire \s_axi_rid[11]_INST_0_i_1_n_0 ;
wire \s_axi_rid[11]_INST_0_i_2_n_0 ;
wire \s_axi_rid[11]_INST_0_i_3_n_0 ;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\chosen[0]_i_1
(.I0(next_rr_hot[0]),
.I1(need_arbitration),
.I2(\m_payload_i_reg[0]_0 ),
.O(\chosen[0]_i_1_n_0 ));
LUT3 #(
.INIT(8'hB8))
\chosen[1]_i_1
(.I0(next_rr_hot[1]),
.I1(need_arbitration),
.I2(\chosen_reg[1]_0 ),
.O(\chosen[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\chosen[2]_i_1
(.I0(next_rr_hot[2]),
.I1(need_arbitration),
.I2(\m_payload_i_reg[34] ),
.O(\chosen[2]_i_1_n_0 ));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\chosen[0]_i_1_n_0 ),
.Q(\m_payload_i_reg[0]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\chosen[1]_i_1_n_0 ),
.Q(\chosen_reg[1]_0 ),
.R(SR));
(* use_clock_enable = "yes" *)
FDRE #(
.INIT(1'b0))
\chosen_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\chosen[2]_i_1_n_0 ),
.Q(\m_payload_i_reg[34] ),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT4 #(
.INIT(16'hA659))
\gen_multi_thread.accept_cnt[1]_i_1__0
(.I0(Q[0]),
.I1(\gen_no_arbiter.s_ready_i_reg[0] ),
.I2(\gen_multi_thread.accept_cnt_reg[2] ),
.I3(Q[1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT5 #(
.INIT(32'hBFF4400B))
\gen_multi_thread.accept_cnt[2]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg[2] ),
.I1(\gen_no_arbiter.s_ready_i_reg[0] ),
.I2(Q[0]),
.I3(Q[1]),
.I4(Q[2]),
.O(D[1]));
LUT6 #(
.INIT(64'h0000FFFFFFFE0000))
\gen_multi_thread.accept_cnt[3]_i_1__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[2]),
.I4(\gen_multi_thread.accept_cnt_reg[2] ),
.I5(\gen_no_arbiter.s_ready_i_reg[0] ),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'hA6AAAAAAAAAA9A99))
\gen_multi_thread.accept_cnt[3]_i_2__0
(.I0(Q[3]),
.I1(Q[0]),
.I2(\gen_multi_thread.accept_cnt_reg[2] ),
.I3(\gen_no_arbiter.s_ready_i_reg[0] ),
.I4(Q[1]),
.I5(Q[2]),
.O(D[2]));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_1__0
(.I0(cmd_push_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] ),
.I3(\gen_multi_thread.accept_cnt_reg[2] ),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_5 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_4 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT4 #(
.INIT(16'h9AAA))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_1__0
(.I0(cmd_push_3),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] ),
.I2(CO),
.I3(\gen_multi_thread.accept_cnt_reg[2] ),
.O(E));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_3 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT4 #(
.INIT(16'h5955))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_2 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT4 #(
.INIT(16'h9555))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.I1(\gen_multi_thread.accept_cnt_reg[2] ),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT5 #(
.INIT(32'hA8880000))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_3__0
(.I0(s_axi_rlast),
.I1(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(p_74_out),
.I4(s_axi_rready),
.O(\gen_multi_thread.accept_cnt_reg[2] ));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_10
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [9]),
.I2(\m_payload_i_reg[46]_0 [22]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [22]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_10_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_11
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [5]),
.I2(\m_payload_i_reg[46]_0 [18]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [18]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_11_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_12
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [17]),
.I2(\m_payload_i_reg[46]_1 [4]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46]_0 [17]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(i__carry_i_12_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_13
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [19]),
.I2(\m_payload_i_reg[46]_1 [6]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [19]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_13_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_14
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [2]),
.I2(\m_payload_i_reg[46]_0 [15]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [15]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_14_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_15
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [14]),
.I2(\m_payload_i_reg[46]_1 [1]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [14]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_15_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_16
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [3]),
.I2(\m_payload_i_reg[46]_0 [16]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [16]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_16_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [10]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [7]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [4]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_5
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [11]),
.I2(\m_payload_i_reg[46] [24]),
.I3(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I4(\m_payload_i_reg[46]_0 [24]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(i__carry_i_5_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_6
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [23]),
.I2(\m_payload_i_reg[46]_1 [10]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [23]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_6_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_7
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [25]),
.I2(\m_payload_i_reg[46]_1 [12]),
.I3(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I4(\m_payload_i_reg[46] [25]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_7_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_8
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [8]),
.I2(\m_payload_i_reg[46]_0 [21]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [21]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_8_n_0));
LUT6 #(
.INIT(64'hBB0BBB0B0000BB0B))
i__carry_i_9
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [7]),
.I2(\m_payload_i_reg[46]_0 [20]),
.I3(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I4(\m_payload_i_reg[46] [20]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(i__carry_i_9_n_0));
LUT5 #(
.INIT(32'hFF57AA00))
\last_rr_hot[0]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(\last_rr_hot_reg_n_0_[0] ),
.O(\last_rr_hot[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hF5F7A0A0))
\last_rr_hot[1]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_3_in),
.O(\last_rr_hot[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hDDDF8888))
\last_rr_hot[2]_i_1__0
(.I0(need_arbitration),
.I1(next_rr_hot[2]),
.I2(next_rr_hot[1]),
.I3(next_rr_hot[0]),
.I4(p_4_in),
.O(\last_rr_hot[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hABBBABBBABBBAB88))
\last_rr_hot[2]_i_2__0
(.I0(s_axi_rready),
.I1(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I2(\m_payload_i_reg[0]_0 ),
.I3(p_74_out),
.I4(p_54_out),
.I5(p_32_out),
.O(need_arbitration));
LUT6 #(
.INIT(64'hAAAAAAAA20222020))
\last_rr_hot[2]_i_3
(.I0(p_32_out),
.I1(p_54_out),
.I2(\last_rr_hot_reg_n_0_[0] ),
.I3(p_74_out),
.I4(p_4_in),
.I5(p_3_in),
.O(next_rr_hot[2]));
LUT6 #(
.INIT(64'hAAAAAAAA0A0A0008))
\last_rr_hot[2]_i_4
(.I0(p_54_out),
.I1(p_3_in),
.I2(p_74_out),
.I3(p_32_out),
.I4(p_4_in),
.I5(\last_rr_hot_reg_n_0_[0] ),
.O(next_rr_hot[1]));
LUT6 #(
.INIT(64'h8A8A8A8A88888A88))
\last_rr_hot[2]_i_5
(.I0(p_74_out),
.I1(p_4_in),
.I2(p_32_out),
.I3(\last_rr_hot_reg_n_0_[0] ),
.I4(p_54_out),
.I5(p_3_in),
.O(next_rr_hot[0]));
FDRE \last_rr_hot_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[0]_i_1__0_n_0 ),
.Q(\last_rr_hot_reg_n_0_[0] ),
.R(SR));
FDRE \last_rr_hot_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[1]_i_1__0_n_0 ),
.Q(p_3_in),
.R(SR));
FDSE \last_rr_hot_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\last_rr_hot[2]_i_1__0_n_0 ),
.Q(p_4_in),
.S(SR));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB3))
\m_payload_i[46]_i_1
(.I0(\m_payload_i_reg[0]_0 ),
.I1(p_74_out),
.I2(s_axi_rready),
.O(\m_payload_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'h8F))
\m_payload_i[46]_i_1__1
(.I0(s_axi_rready),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.O(\m_payload_i_reg[34]_0 ));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [10]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [7]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [4]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [7]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [4]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [10]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [11]),
.I5(i__carry_i_7_n_0),
.O(S[3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [7]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [8]),
.I5(i__carry_i_10_n_0),
.O(S[2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [4]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [5]),
.I5(i__carry_i_13_n_0),
.O(S[1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] [2]),
.I5(i__carry_i_16_n_0),
.O(S[0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [10]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [7]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [4]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [10]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [7]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [4]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [10]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [7]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [4]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_1__0
(.I0(i__carry_i_5_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [10]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [9]),
.I3(i__carry_i_6_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [11]),
.I5(i__carry_i_7_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [3]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_2__0
(.I0(i__carry_i_8_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [7]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [6]),
.I3(i__carry_i_9_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [8]),
.I5(i__carry_i_10_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [2]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_3__0
(.I0(i__carry_i_11_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [4]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [3]),
.I3(i__carry_i_12_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [5]),
.I5(i__carry_i_13_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [1]));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_4__0
(.I0(i__carry_i_14_n_0),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [0]),
.I3(i__carry_i_15_n_0),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] [2]),
.I5(i__carry_i_16_n_0),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] [0]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[0]_INST_0
(.I0(\m_payload_i_reg[46] [0]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [0]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[10]_INST_0
(.I0(\m_payload_i_reg[46] [5]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [5]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[11]_INST_0
(.I0(\m_payload_i_reg[46] [6]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [6]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[19]_INST_0
(.I0(\m_payload_i_reg[46] [7]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [7]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[20]_INST_0
(.I0(\m_payload_i_reg[46] [8]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [8]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[22]_INST_0
(.I0(\m_payload_i_reg[46] [9]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [9]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[27]_INST_0
(.I0(\m_payload_i_reg[46] [10]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [10]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[31]_INST_0
(.I0(\m_payload_i_reg[46] [11]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [11]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[4]_INST_0
(.I0(\m_payload_i_reg[46] [1]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [1]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[6]_INST_0
(.I0(\m_payload_i_reg[46] [2]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [2]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[8]_INST_0
(.I0(\m_payload_i_reg[46] [3]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [3]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'h3F2A2A2A002A2A2A))
\s_axi_rdata[9]_INST_0
(.I0(\m_payload_i_reg[46] [4]),
.I1(\m_payload_i_reg[34] ),
.I2(p_32_out),
.I3(\chosen_reg[1]_0 ),
.I4(p_54_out),
.I5(\m_payload_i_reg[46]_0 [4]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[0]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [14]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [1]),
.I4(\m_payload_i_reg[46]_0 [14]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[0]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[10]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [24]),
.I2(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I3(\m_payload_i_reg[46] [24]),
.I4(\m_payload_i_reg[46]_1 [11]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[10]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[11]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [25]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [12]),
.I4(\m_payload_i_reg[46]_0 [25]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[11]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'hF888))
\s_axi_rid[11]_INST_0_i_1
(.I0(\m_payload_i_reg[34] ),
.I1(p_32_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_54_out),
.O(\s_axi_rid[11]_INST_0_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT4 #(
.INIT(16'h8FFF))
\s_axi_rid[11]_INST_0_i_2
(.I0(\chosen_reg[1]_0 ),
.I1(p_54_out),
.I2(\m_payload_i_reg[34] ),
.I3(p_32_out),
.O(\s_axi_rid[11]_INST_0_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT4 #(
.INIT(16'h8FFF))
\s_axi_rid[11]_INST_0_i_3
(.I0(\m_payload_i_reg[34] ),
.I1(p_32_out),
.I2(\chosen_reg[1]_0 ),
.I3(p_54_out),
.O(\s_axi_rid[11]_INST_0_i_3_n_0 ));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[1]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [15]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [15]),
.I4(\m_payload_i_reg[46]_1 [2]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[1]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[2]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [16]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [16]),
.I4(\m_payload_i_reg[46]_1 [3]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[2]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[3]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I1(\m_payload_i_reg[46]_0 [17]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [4]),
.I4(\m_payload_i_reg[46] [17]),
.I5(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.O(s_axi_rid[3]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[4]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [18]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [18]),
.I4(\m_payload_i_reg[46]_1 [5]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[4]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[5]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [19]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [6]),
.I4(\m_payload_i_reg[46]_0 [19]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[5]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[6]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [20]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [20]),
.I4(\m_payload_i_reg[46]_1 [7]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[6]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[7]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [21]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [21]),
.I4(\m_payload_i_reg[46]_1 [8]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[7]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[8]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [22]),
.I2(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.I3(\m_payload_i_reg[46]_0 [22]),
.I4(\m_payload_i_reg[46]_1 [9]),
.I5(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.O(s_axi_rid[8]));
LUT6 #(
.INIT(64'h4F444F44FFFF4F44))
\s_axi_rid[9]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I1(\m_payload_i_reg[46] [23]),
.I2(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I3(\m_payload_i_reg[46]_1 [10]),
.I4(\m_payload_i_reg[46]_0 [23]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rid[9]));
LUT6 #(
.INIT(64'h44F444F4FFFF44F4))
\s_axi_rlast[0]_INST_0
(.I0(\s_axi_rid[11]_INST_0_i_2_n_0 ),
.I1(\m_payload_i_reg[46]_1 [0]),
.I2(\m_payload_i_reg[46] [13]),
.I3(\s_axi_rid[11]_INST_0_i_1_n_0 ),
.I4(\m_payload_i_reg[46]_0 [13]),
.I5(\s_axi_rid[11]_INST_0_i_3_n_0 ),
.O(s_axi_rlast));
LUT6 #(
.INIT(64'h3FEAEAEA00EAEAEA))
\s_axi_rresp[1]_INST_0
(.I0(\m_payload_i_reg[46] [12]),
.I1(p_32_out),
.I2(\m_payload_i_reg[34] ),
.I3(p_54_out),
.I4(\chosen_reg[1]_0 ),
.I5(\m_payload_i_reg[46]_0 [12]),
.O(s_axi_rresp));
LUT6 #(
.INIT(64'hFFFFF888F888F888))
\s_axi_rvalid[0]_INST_0
(.I0(p_54_out),
.I1(\chosen_reg[1]_0 ),
.I2(p_32_out),
.I3(\m_payload_i_reg[34] ),
.I4(\m_payload_i_reg[0]_0 ),
.I5(p_74_out),
.O(s_axi_rvalid));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_CONNECTIVITY_MODE = "1" *) (* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *) (* C_M_AXI_ADDR_WIDTH = "64'b0000000000000000000000000001000000000000000000000000000000010000" *) (* C_M_AXI_BASE_ADDR = "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *) (* C_M_AXI_READ_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *) (* C_M_AXI_SECURE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *) (* C_M_AXI_WRITE_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *) (* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "2" *) (* C_NUM_SLAVE_SLOTS = "1" *) (* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *) (* C_S_AXI_BASE_ID = "0" *) (* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *) (* C_S_AXI_THREAD_ID_WIDTH = "12" *) (* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *) (* P_ADDR_DECODE = "1" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *) (* P_INCR = "2'b01" *) (* P_LEN = "8" *)
(* P_LOCK = "1" *) (* P_M_AXI_ERR_MODE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_M_AXI_SUPPORTS_READ = "2'b11" *)
(* P_M_AXI_SUPPORTS_WRITE = "2'b11" *) (* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *) (* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *) (* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *) (* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [11:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [11:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wuser;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [11:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rlast;
output [0:0]s_axi_ruser;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [23:0]m_axi_awid;
output [63:0]m_axi_awaddr;
output [15:0]m_axi_awlen;
output [5:0]m_axi_awsize;
output [3:0]m_axi_awburst;
output [1:0]m_axi_awlock;
output [7:0]m_axi_awcache;
output [5:0]m_axi_awprot;
output [7:0]m_axi_awregion;
output [7:0]m_axi_awqos;
output [1:0]m_axi_awuser;
output [1:0]m_axi_awvalid;
input [1:0]m_axi_awready;
output [23:0]m_axi_wid;
output [63:0]m_axi_wdata;
output [7:0]m_axi_wstrb;
output [1:0]m_axi_wlast;
output [1:0]m_axi_wuser;
output [1:0]m_axi_wvalid;
input [1:0]m_axi_wready;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [1:0]m_axi_buser;
input [1:0]m_axi_bvalid;
output [1:0]m_axi_bready;
output [23:0]m_axi_arid;
output [63:0]m_axi_araddr;
output [15:0]m_axi_arlen;
output [5:0]m_axi_arsize;
output [3:0]m_axi_arburst;
output [1:0]m_axi_arlock;
output [7:0]m_axi_arcache;
output [5:0]m_axi_arprot;
output [7:0]m_axi_arregion;
output [7:0]m_axi_arqos;
output [1:0]m_axi_aruser;
output [1:0]m_axi_arvalid;
input [1:0]m_axi_arready;
input [23:0]m_axi_rid;
input [63:0]m_axi_rdata;
input [3:0]m_axi_rresp;
input [1:0]m_axi_rlast;
input [1:0]m_axi_ruser;
input [1:0]m_axi_rvalid;
output [1:0]m_axi_rready;
wire \<const0> ;
wire aclk;
wire aresetn;
wire [63:32]\^m_axi_araddr ;
wire [3:2]\^m_axi_arburst ;
wire [7:4]\^m_axi_arcache ;
wire [11:0]\^m_axi_arid ;
wire [7:0]\^m_axi_arlen ;
wire [1:1]\^m_axi_arlock ;
wire [5:3]\^m_axi_arprot ;
wire [7:4]\^m_axi_arqos ;
wire [1:0]m_axi_arready;
wire [5:3]\^m_axi_arsize ;
wire [1:0]m_axi_arvalid;
wire [63:32]\^m_axi_awaddr ;
wire [3:2]\^m_axi_awburst ;
wire [7:4]\^m_axi_awcache ;
wire [11:0]\^m_axi_awid ;
wire [15:8]\^m_axi_awlen ;
wire [1:1]\^m_axi_awlock ;
wire [5:3]\^m_axi_awprot ;
wire [7:4]\^m_axi_awqos ;
wire [1:0]m_axi_awready;
wire [5:3]\^m_axi_awsize ;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rready;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
assign m_axi_araddr[63:32] = \^m_axi_araddr [63:32];
assign m_axi_araddr[31:0] = \^m_axi_araddr [63:32];
assign m_axi_arburst[3:2] = \^m_axi_arburst [3:2];
assign m_axi_arburst[1:0] = \^m_axi_arburst [3:2];
assign m_axi_arcache[7:4] = \^m_axi_arcache [7:4];
assign m_axi_arcache[3:0] = \^m_axi_arcache [7:4];
assign m_axi_arid[23:12] = \^m_axi_arid [11:0];
assign m_axi_arid[11:0] = \^m_axi_arid [11:0];
assign m_axi_arlen[15:8] = \^m_axi_arlen [7:0];
assign m_axi_arlen[7:0] = \^m_axi_arlen [7:0];
assign m_axi_arlock[1] = \^m_axi_arlock [1];
assign m_axi_arlock[0] = \^m_axi_arlock [1];
assign m_axi_arprot[5:3] = \^m_axi_arprot [5:3];
assign m_axi_arprot[2:0] = \^m_axi_arprot [5:3];
assign m_axi_arqos[7:4] = \^m_axi_arqos [7:4];
assign m_axi_arqos[3:0] = \^m_axi_arqos [7:4];
assign m_axi_arregion[7] = \<const0> ;
assign m_axi_arregion[6] = \<const0> ;
assign m_axi_arregion[5] = \<const0> ;
assign m_axi_arregion[4] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[5:3] = \^m_axi_arsize [5:3];
assign m_axi_arsize[2:0] = \^m_axi_arsize [5:3];
assign m_axi_aruser[1] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awaddr[63:32] = \^m_axi_awaddr [63:32];
assign m_axi_awaddr[31:0] = \^m_axi_awaddr [63:32];
assign m_axi_awburst[3:2] = \^m_axi_awburst [3:2];
assign m_axi_awburst[1:0] = \^m_axi_awburst [3:2];
assign m_axi_awcache[7:4] = \^m_axi_awcache [7:4];
assign m_axi_awcache[3:0] = \^m_axi_awcache [7:4];
assign m_axi_awid[23:12] = \^m_axi_awid [11:0];
assign m_axi_awid[11:0] = \^m_axi_awid [11:0];
assign m_axi_awlen[15:8] = \^m_axi_awlen [15:8];
assign m_axi_awlen[7:0] = \^m_axi_awlen [15:8];
assign m_axi_awlock[1] = \^m_axi_awlock [1];
assign m_axi_awlock[0] = \^m_axi_awlock [1];
assign m_axi_awprot[5:3] = \^m_axi_awprot [5:3];
assign m_axi_awprot[2:0] = \^m_axi_awprot [5:3];
assign m_axi_awqos[7:4] = \^m_axi_awqos [7:4];
assign m_axi_awqos[3:0] = \^m_axi_awqos [7:4];
assign m_axi_awregion[7] = \<const0> ;
assign m_axi_awregion[6] = \<const0> ;
assign m_axi_awregion[5] = \<const0> ;
assign m_axi_awregion[4] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[5:3] = \^m_axi_awsize [5:3];
assign m_axi_awsize[2:0] = \^m_axi_awsize [5:3];
assign m_axi_awuser[1] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[63:32] = s_axi_wdata;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[23] = \<const0> ;
assign m_axi_wid[22] = \<const0> ;
assign m_axi_wid[21] = \<const0> ;
assign m_axi_wid[20] = \<const0> ;
assign m_axi_wid[19] = \<const0> ;
assign m_axi_wid[18] = \<const0> ;
assign m_axi_wid[17] = \<const0> ;
assign m_axi_wid[16] = \<const0> ;
assign m_axi_wid[15] = \<const0> ;
assign m_axi_wid[14] = \<const0> ;
assign m_axi_wid[13] = \<const0> ;
assign m_axi_wid[12] = \<const0> ;
assign m_axi_wid[11] = \<const0> ;
assign m_axi_wid[10] = \<const0> ;
assign m_axi_wid[9] = \<const0> ;
assign m_axi_wid[8] = \<const0> ;
assign m_axi_wid[7] = \<const0> ;
assign m_axi_wid[6] = \<const0> ;
assign m_axi_wid[5] = \<const0> ;
assign m_axi_wid[4] = \<const0> ;
assign m_axi_wid[3] = \<const0> ;
assign m_axi_wid[2] = \<const0> ;
assign m_axi_wid[1] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast[1] = s_axi_wlast;
assign m_axi_wlast[0] = s_axi_wlast;
assign m_axi_wstrb[7:4] = s_axi_wstrb;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[1] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar \gen_samd.crossbar_samd
(.D({s_axi_awqos,s_axi_awcache,s_axi_awburst,s_axi_awprot,s_axi_awlock,s_axi_awsize,s_axi_awlen,s_axi_awaddr}),
.M_AXI_RREADY(m_axi_rready),
.Q({\^m_axi_awqos ,\^m_axi_awcache ,\^m_axi_awburst ,\^m_axi_awprot ,\^m_axi_awlock ,\^m_axi_awsize ,\^m_axi_awlen ,\^m_axi_awaddr ,\^m_axi_awid }),
.S_AXI_ARREADY(s_axi_arready),
.aclk(aclk),
.aresetn(aresetn),
.\m_axi_arqos[7] ({\^m_axi_arqos ,\^m_axi_arcache ,\^m_axi_arburst ,\^m_axi_arprot ,\^m_axi_arlock ,\^m_axi_arsize ,\^m_axi_arlen ,\^m_axi_araddr ,\^m_axi_arid }),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_arid(s_axi_arid),
.\s_axi_arqos[3] ({s_axi_arqos,s_axi_arcache,s_axi_arburst,s_axi_arprot,s_axi_arlock,s_axi_arsize,s_axi_arlen,s_axi_araddr}),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awid(s_axi_awid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_crossbar
(S_AXI_ARREADY,
Q,
\m_axi_arqos[7] ,
m_axi_bready,
M_AXI_RREADY,
m_axi_awvalid,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_awready,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
m_axi_arvalid,
m_axi_wvalid,
s_axi_wready,
m_axi_awready,
m_axi_bvalid,
s_axi_bready,
aclk,
s_axi_arid,
s_axi_awid,
s_axi_awvalid,
m_axi_bid,
m_axi_bresp,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
aresetn,
D,
\s_axi_arqos[3] ,
s_axi_arvalid,
m_axi_rvalid,
s_axi_rready,
m_axi_arready,
s_axi_wvalid,
s_axi_wlast,
m_axi_wready);
output [0:0]S_AXI_ARREADY;
output [68:0]Q;
output [68:0]\m_axi_arqos[7] ;
output [1:0]m_axi_bready;
output [1:0]M_AXI_RREADY;
output [1:0]m_axi_awvalid;
output [11:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
output [0:0]s_axi_awready;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output [1:0]s_axi_rresp;
output [11:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]m_axi_arvalid;
output [1:0]m_axi_wvalid;
output [0:0]s_axi_wready;
input [1:0]m_axi_awready;
input [1:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input aclk;
input [11:0]s_axi_arid;
input [11:0]s_axi_awid;
input [0:0]s_axi_awvalid;
input [23:0]m_axi_bid;
input [3:0]m_axi_bresp;
input [23:0]m_axi_rid;
input [1:0]m_axi_rlast;
input [3:0]m_axi_rresp;
input [63:0]m_axi_rdata;
input aresetn;
input [56:0]D;
input [56:0]\s_axi_arqos[3] ;
input [0:0]s_axi_arvalid;
input [1:0]m_axi_rvalid;
input [0:0]s_axi_rready;
input [1:0]m_axi_arready;
input [0:0]s_axi_wvalid;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
wire [56:0]D;
wire [1:0]M_AXI_RREADY;
wire [68:0]Q;
wire [0:0]S_AXI_ARREADY;
wire [2:2]aa_mi_artarget_hot;
wire aa_mi_arvalid;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire addr_arbiter_ar_n_2;
wire addr_arbiter_ar_n_3;
wire addr_arbiter_ar_n_4;
wire addr_arbiter_ar_n_5;
wire addr_arbiter_ar_n_6;
wire addr_arbiter_ar_n_7;
wire addr_arbiter_ar_n_80;
wire addr_arbiter_ar_n_81;
wire addr_arbiter_ar_n_82;
wire addr_arbiter_ar_n_84;
wire addr_arbiter_ar_n_85;
wire addr_arbiter_aw_n_10;
wire addr_arbiter_aw_n_11;
wire addr_arbiter_aw_n_12;
wire addr_arbiter_aw_n_13;
wire addr_arbiter_aw_n_14;
wire addr_arbiter_aw_n_15;
wire addr_arbiter_aw_n_16;
wire addr_arbiter_aw_n_2;
wire addr_arbiter_aw_n_20;
wire addr_arbiter_aw_n_21;
wire addr_arbiter_aw_n_3;
wire addr_arbiter_aw_n_7;
wire addr_arbiter_aw_n_8;
wire addr_arbiter_aw_n_9;
wire aresetn;
wire aresetn_d;
wire \gen_decerr_slave.decerr_slave_inst_n_7 ;
wire \gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[0].reg_slice_mi_n_4 ;
wire \gen_master_slots[0].reg_slice_mi_n_5 ;
wire \gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ;
wire \gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[1].reg_slice_mi_n_12 ;
wire \gen_master_slots[1].reg_slice_mi_n_20 ;
wire \gen_master_slots[1].reg_slice_mi_n_21 ;
wire \gen_master_slots[1].reg_slice_mi_n_22 ;
wire \gen_master_slots[1].reg_slice_mi_n_23 ;
wire \gen_master_slots[1].reg_slice_mi_n_26 ;
wire \gen_master_slots[1].reg_slice_mi_n_27 ;
wire \gen_master_slots[1].reg_slice_mi_n_5 ;
wire \gen_master_slots[1].reg_slice_mi_n_6 ;
wire \gen_master_slots[1].reg_slice_mi_n_75 ;
wire \gen_master_slots[1].reg_slice_mi_n_76 ;
wire \gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ;
wire \gen_master_slots[2].reg_slice_mi_n_1 ;
wire \gen_master_slots[2].reg_slice_mi_n_13 ;
wire \gen_master_slots[2].reg_slice_mi_n_19 ;
wire \gen_master_slots[2].reg_slice_mi_n_20 ;
wire \gen_master_slots[2].reg_slice_mi_n_21 ;
wire \gen_master_slots[2].reg_slice_mi_n_22 ;
wire \gen_master_slots[2].reg_slice_mi_n_23 ;
wire \gen_master_slots[2].reg_slice_mi_n_24 ;
wire \gen_master_slots[2].reg_slice_mi_n_25 ;
wire \gen_master_slots[2].reg_slice_mi_n_26 ;
wire \gen_master_slots[2].reg_slice_mi_n_27 ;
wire \gen_master_slots[2].reg_slice_mi_n_28 ;
wire \gen_master_slots[2].reg_slice_mi_n_29 ;
wire \gen_master_slots[2].reg_slice_mi_n_30 ;
wire \gen_master_slots[2].reg_slice_mi_n_31 ;
wire \gen_master_slots[2].reg_slice_mi_n_45 ;
wire \gen_master_slots[2].reg_slice_mi_n_5 ;
wire [2:0]\gen_multi_thread.arbiter_resp_inst/chosen ;
wire [2:0]\gen_multi_thread.arbiter_resp_inst/chosen_1 ;
wire [8:6]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire [8:6]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ;
wire \gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ;
wire \gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ;
wire \gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ;
wire [68:0]\m_axi_arqos[7] ;
wire [1:0]m_axi_arready;
wire [1:0]m_axi_arvalid;
wire [1:0]m_axi_awready;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [1:0]m_ready_d;
wire [1:0]m_ready_d_3;
wire m_valid_i;
wire m_valid_i_2;
wire mi_arready_2;
wire mi_awready_2;
wire mi_bready_2;
wire mi_rready_2;
wire p_14_in;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire [11:0]p_20_in;
wire p_21_in;
wire [11:0]p_24_in;
wire p_32_out;
wire p_34_out;
wire p_38_out;
wire p_54_out;
wire p_56_out;
wire p_60_out;
wire p_74_out;
wire p_76_out;
wire p_80_out;
wire [16:0]r_issuing_cnt;
wire \r_pipe/p_1_in ;
wire \r_pipe/p_1_in_0 ;
wire reset;
wire [11:0]s_axi_arid;
wire [56:0]\s_axi_arqos[3] ;
wire [0:0]s_axi_arvalid;
wire [11:0]s_axi_awid;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire s_axi_rlast_i0;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire s_axi_rvalid_i;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [1:0]st_aa_artarget_hot;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [34:0]st_mr_bid;
wire [1:0]st_mr_bmesg;
wire [35:0]st_mr_rid;
wire [69:0]st_mr_rmesg;
wire [16:0]w_issuing_cnt;
wire [1:1]write_cs;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter addr_arbiter_ar
(.D({addr_arbiter_ar_n_2,addr_arbiter_ar_n_3,addr_arbiter_ar_n_4}),
.E(s_axi_rvalid_i),
.Q(p_56_out),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ),
.aresetn_d_reg_0(\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ),
.\chosen_reg[0] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ),
.\gen_axi.read_cnt_reg[5] (\gen_decerr_slave.decerr_slave_inst_n_7 ),
.\gen_axi.s_axi_rid_i_reg[11] (aa_mi_artarget_hot),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (addr_arbiter_ar_n_84),
.\gen_master_slots[1].r_issuing_cnt_reg[11] ({addr_arbiter_ar_n_5,addr_arbiter_ar_n_6,addr_arbiter_ar_n_7}),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (addr_arbiter_ar_n_85),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_31 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[57] (addr_arbiter_ar_n_82),
.\gen_no_arbiter.m_target_hot_i_reg[0]_0 (st_aa_artarget_hot[0]),
.\gen_no_arbiter.m_valid_i_reg_0 (addr_arbiter_ar_n_80),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_ar_n_81),
.\m_axi_arqos[7] (\m_axi_arqos[7] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[34] (\gen_master_slots[0].reg_slice_mi_n_5 ),
.\m_payload_i_reg[34]_0 (\gen_master_slots[1].reg_slice_mi_n_27 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_75 ),
.mi_arready_2(mi_arready_2),
.p_15_in(p_15_in),
.r_issuing_cnt({r_issuing_cnt[11:8],r_issuing_cnt[3:0]}),
.\s_axi_araddr[25] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ),
.\s_axi_araddr[28] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ),
.\s_axi_araddr[30] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ),
.\s_axi_arqos[3] ({\s_axi_arqos[3] ,s_axi_arid}),
.\s_axi_arready[0] (S_AXI_ARREADY),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_rlast_i0(s_axi_rlast_i0),
.s_axi_rready(s_axi_rready),
.st_aa_artarget_hot(st_aa_artarget_hot[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_addr_arbiter_0 addr_arbiter_aw
(.D({addr_arbiter_aw_n_7,addr_arbiter_aw_n_8,addr_arbiter_aw_n_9}),
.E(addr_arbiter_aw_n_15),
.Q(Q),
.SR(reset),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.aresetn_d_reg(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ),
.aresetn_d_reg_0(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ),
.\chosen_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ),
.\chosen_reg[1] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ),
.\gen_master_slots[0].w_issuing_cnt_reg[0] (addr_arbiter_aw_n_16),
.\gen_master_slots[0].w_issuing_cnt_reg[3] ({addr_arbiter_aw_n_11,addr_arbiter_aw_n_12,addr_arbiter_aw_n_13}),
.\gen_master_slots[1].w_issuing_cnt_reg[9] (addr_arbiter_aw_n_10),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (addr_arbiter_aw_n_14),
.\gen_no_arbiter.m_target_hot_i_reg[2]_0 (addr_arbiter_aw_n_20),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_ready_d(m_ready_d_3),
.m_ready_d_0(m_ready_d[0]),
.\m_ready_d_reg[0] (addr_arbiter_aw_n_2),
.\m_ready_d_reg[1] (addr_arbiter_aw_n_3),
.\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_21),
.m_valid_i(m_valid_i_2),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_6 ),
.mi_awready_2(mi_awready_2),
.\s_axi_awaddr[20] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ),
.\s_axi_awaddr[26] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ),
.\s_axi_awqos[3] ({D,s_axi_awid}),
.s_axi_bready(s_axi_bready),
.ss_aa_awready(ss_aa_awready),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt({w_issuing_cnt[11:8],w_issuing_cnt[3:0]}));
FDRE #(
.INIT(1'b0))
aresetn_d_reg
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(aresetn_d),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave \gen_decerr_slave.decerr_slave_inst
(.E(s_axi_rvalid_i),
.Q(p_24_in),
.SR(reset),
.aa_mi_arvalid(aa_mi_arvalid),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot[2]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_axi.s_axi_arready_i_reg_0 (\gen_decerr_slave.decerr_slave_inst_n_7 ),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.\gen_no_arbiter.m_mesg_i_reg[11] (Q[11:0]),
.\gen_no_arbiter.m_mesg_i_reg[51] ({\m_axi_arqos[7] [51:44],\m_axi_arqos[7] [11:0]}),
.\gen_no_arbiter.m_target_hot_i_reg[2] (aa_mi_artarget_hot),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_aw_n_10),
.m_ready_d(m_ready_d_3[1]),
.\m_ready_d_reg[1] (addr_arbiter_aw_n_14),
.mi_arready_2(mi_arready_2),
.mi_awready_2(mi_awready_2),
.mi_bready_2(mi_bready_2),
.mi_rready_2(mi_rready_2),
.p_14_in(p_14_in),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_21_in(p_21_in),
.s_axi_rlast_i0(s_axi_rlast_i0),
.\skid_buffer_reg[46] (p_20_in),
.\storage_data1_reg[0] (\gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].r_issuing_cnt[0]_i_1
(.I0(r_issuing_cnt[0]),
.O(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[0]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(\gen_master_slots[0].r_issuing_cnt[0]_i_1_n_0 ),
.Q(r_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[1]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_4),
.Q(r_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[2]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_3),
.Q(r_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].r_issuing_cnt_reg[3]
(.C(aclk),
.CE(addr_arbiter_ar_n_84),
.D(addr_arbiter_ar_n_2),
.Q(r_issuing_cnt[3]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice \gen_master_slots[0].reg_slice_mi
(.D({m_axi_bid[11:0],m_axi_bresp[1:0]}),
.E(\r_pipe/p_1_in_0 ),
.Q(r_issuing_cnt[3:0]),
.aclk(aclk),
.\aresetn_d_reg[1] (\gen_master_slots[2].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[2].reg_slice_mi_n_5 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [0]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [0]),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_5 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ({st_mr_bid[11:0],st_mr_bmesg}),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[11:0],p_76_out,st_mr_rmesg[1:0],st_mr_rmesg[34:3]}),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[0].reg_slice_mi_n_4 ),
.m_axi_bready(m_axi_bready[0]),
.m_axi_bvalid(m_axi_bvalid[0]),
.m_axi_rdata(m_axi_rdata[31:0]),
.m_axi_rid(m_axi_rid[11:0]),
.m_axi_rlast(m_axi_rlast[0]),
.\m_axi_rready[0] (M_AXI_RREADY[0]),
.m_axi_rresp(m_axi_rresp[1:0]),
.m_axi_rvalid(m_axi_rvalid[0]),
.p_1_in(p_1_in),
.p_74_out(p_74_out),
.p_80_out(p_80_out),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[0].w_issuing_cnt[0]_i_1
(.I0(w_issuing_cnt[0]),
.O(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[0]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(\gen_master_slots[0].w_issuing_cnt[0]_i_1_n_0 ),
.Q(w_issuing_cnt[0]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[1]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_13),
.Q(w_issuing_cnt[1]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[2]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_12),
.Q(w_issuing_cnt[2]),
.R(reset));
FDRE \gen_master_slots[0].w_issuing_cnt_reg[3]
(.C(aclk),
.CE(addr_arbiter_aw_n_16),
.D(addr_arbiter_aw_n_11),
.Q(w_issuing_cnt[3]),
.R(reset));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].r_issuing_cnt[8]_i_1
(.I0(r_issuing_cnt[8]),
.O(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[10]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_6),
.Q(r_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[11]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_5),
.Q(r_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[8]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(\gen_master_slots[1].r_issuing_cnt[8]_i_1_n_0 ),
.Q(r_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].r_issuing_cnt_reg[9]
(.C(aclk),
.CE(addr_arbiter_ar_n_85),
.D(addr_arbiter_ar_n_7),
.Q(r_issuing_cnt[9]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1 \gen_master_slots[1].reg_slice_mi
(.D({m_axi_bid[23:12],m_axi_bresp[3:2]}),
.Q(w_issuing_cnt[11:8]),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\gen_master_slots[1].reg_slice_mi_n_76 ),
.\aresetn_d_reg[1]_0 (\gen_master_slots[2].reg_slice_mi_n_1 ),
.\aresetn_d_reg[1]_1 (\gen_master_slots[2].reg_slice_mi_n_5 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [2:1]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [2:1]),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].reg_slice_mi_n_75 ),
.\gen_master_slots[1].r_issuing_cnt_reg[11]_0 (r_issuing_cnt[11:8]),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_27 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_master_slots[1].reg_slice_mi_n_6 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_master_slots[1].reg_slice_mi_n_12 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ({st_mr_bid[23],st_mr_bid[21:18],st_mr_bid[16],st_mr_bid[12]}),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_master_slots[1].reg_slice_mi_n_20 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_master_slots[1].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 (\gen_master_slots[1].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 (\gen_master_slots[1].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ({st_mr_rid[23:12],p_56_out,st_mr_rmesg[36],st_mr_rmesg[69],st_mr_rmesg[65],st_mr_rmesg[60],st_mr_rmesg[58:57],st_mr_rmesg[49:46],st_mr_rmesg[44],st_mr_rmesg[42],st_mr_rmesg[38]}),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_master_slots[1].reg_slice_mi_n_5 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[1].reg_slice_mi_n_26 ),
.m_axi_bready(m_axi_bready[1]),
.m_axi_bvalid(m_axi_bvalid[1]),
.m_axi_rdata(m_axi_rdata[63:32]),
.m_axi_rid(m_axi_rid[23:12]),
.m_axi_rlast(m_axi_rlast[1]),
.\m_axi_rready[1] (M_AXI_RREADY[1]),
.m_axi_rresp(m_axi_rresp[3:2]),
.m_axi_rvalid(m_axi_rvalid[1]),
.\m_payload_i_reg[12] ({st_mr_bid[34],st_mr_bid[29],st_mr_bid[27:25],st_mr_bid[10],st_mr_bid[5],st_mr_bid[3:1]}),
.\m_payload_i_reg[1] (st_mr_bmesg),
.\m_payload_i_reg[32] ({st_mr_rmesg[0],st_mr_rmesg[33:31],st_mr_rmesg[29:26],st_mr_rmesg[24],st_mr_rmesg[21:15],st_mr_rmesg[10],st_mr_rmesg[8],st_mr_rmesg[6:4]}),
.p_1_in(p_1_in),
.p_32_out(p_32_out),
.p_38_out(p_38_out),
.p_54_out(p_54_out),
.p_60_out(p_60_out),
.s_axi_bid({s_axi_bid[10],s_axi_bid[5],s_axi_bid[3:1]}),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_rdata({s_axi_rdata[30:28],s_axi_rdata[26:23],s_axi_rdata[21],s_axi_rdata[18:12],s_axi_rdata[7],s_axi_rdata[5],s_axi_rdata[3:1]}),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp[0]));
LUT1 #(
.INIT(2'h1))
\gen_master_slots[1].w_issuing_cnt[8]_i_1
(.I0(w_issuing_cnt[8]),
.O(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[10]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_8),
.Q(w_issuing_cnt[10]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[11]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_7),
.Q(w_issuing_cnt[11]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[8]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(\gen_master_slots[1].w_issuing_cnt[8]_i_1_n_0 ),
.Q(w_issuing_cnt[8]),
.R(reset));
FDRE \gen_master_slots[1].w_issuing_cnt_reg[9]
(.C(aclk),
.CE(addr_arbiter_aw_n_15),
.D(addr_arbiter_aw_n_9),
.Q(w_issuing_cnt[9]),
.R(reset));
FDRE \gen_master_slots[2].r_issuing_cnt_reg[16]
(.C(aclk),
.CE(1'b1),
.D(\gen_master_slots[2].reg_slice_mi_n_45 ),
.Q(r_issuing_cnt[16]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2 \gen_master_slots[2].reg_slice_mi
(.D(p_24_in),
.E(\r_pipe/p_1_in ),
.Q({st_mr_bid[34],st_mr_bid[29],st_mr_bid[27:25]}),
.S(\gen_master_slots[2].reg_slice_mi_n_20 ),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_master_slots[1].reg_slice_mi_n_76 ),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 [2]),
.chosen_0(\gen_multi_thread.arbiter_resp_inst/chosen [2]),
.\gen_axi.s_axi_arready_i_reg (addr_arbiter_ar_n_80),
.\gen_axi.s_axi_rid_i_reg[11] (p_20_in),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].reg_slice_mi_n_4 ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].reg_slice_mi_n_26 ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].reg_slice_mi_n_45 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_master_slots[2].reg_slice_mi_n_13 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_master_slots[2].reg_slice_mi_n_19 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_master_slots[2].reg_slice_mi_n_28 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_master_slots[2].reg_slice_mi_n_29 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] (\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_master_slots[2].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_master_slots[2].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_master_slots[2].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_master_slots[2].reg_slice_mi_n_24 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_master_slots[2].reg_slice_mi_n_25 ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_master_slots[2].reg_slice_mi_n_26 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_master_slots[2].reg_slice_mi_n_27 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({st_mr_rid[35:24],p_34_out}),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_master_slots[2].reg_slice_mi_n_30 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_master_slots[2].reg_slice_mi_n_31 ),
.\m_payload_i_reg[13] ({st_mr_bid[23],st_mr_bid[21:18],st_mr_bid[16],st_mr_bid[12:11],st_mr_bid[9:6],st_mr_bid[4],st_mr_bid[0]}),
.m_valid_i_reg(\gen_master_slots[2].reg_slice_mi_n_1 ),
.m_valid_i_reg_0(\gen_master_slots[1].reg_slice_mi_n_6 ),
.mi_bready_2(mi_bready_2),
.mi_rready_2(mi_rready_2),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.p_21_in(p_21_in),
.p_32_out(p_32_out),
.p_38_out(p_38_out),
.r_issuing_cnt(r_issuing_cnt[16]),
.s_axi_bid({s_axi_bid[11],s_axi_bid[9:6],s_axi_bid[4],s_axi_bid[0]}),
.s_axi_bready(s_axi_bready),
.s_axi_rready(s_axi_rready),
.s_ready_i_reg(\gen_master_slots[2].reg_slice_mi_n_5 ),
.st_aa_artarget_hot(st_aa_artarget_hot),
.w_issuing_cnt(w_issuing_cnt[16]));
FDRE \gen_master_slots[2].w_issuing_cnt_reg[16]
(.C(aclk),
.CE(1'b1),
.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ),
.Q(w_issuing_cnt[16]),
.R(reset));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor \gen_slave_slots[0].gen_si_read.si_transactor_ar
(.E(\r_pipe/p_1_in_0 ),
.SR(reset),
.aclk(aclk),
.aresetn_d(aresetn_d),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen ),
.\gen_multi_thread.accept_cnt_reg[2]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_5 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_6 ),
.\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_7 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_3 ),
.\gen_no_arbiter.m_target_hot_i_reg[2]_0 (aa_mi_artarget_hot),
.\gen_no_arbiter.m_valid_i_reg (addr_arbiter_ar_n_81),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_slave_slots[0].gen_si_read.si_transactor_ar_n_8 ),
.\gen_no_arbiter.s_ready_i_reg[0]_1 (S_AXI_ARREADY),
.\m_payload_i_reg[34] (\r_pipe/p_1_in ),
.\m_payload_i_reg[46] ({st_mr_rid[11:0],p_76_out,st_mr_rmesg[1],st_mr_rmesg[34],st_mr_rmesg[30],st_mr_rmesg[25],st_mr_rmesg[23:22],st_mr_rmesg[14:11],st_mr_rmesg[9],st_mr_rmesg[7],st_mr_rmesg[3]}),
.\m_payload_i_reg[46]_0 ({st_mr_rid[23:12],p_56_out,st_mr_rmesg[36],st_mr_rmesg[69],st_mr_rmesg[65],st_mr_rmesg[60],st_mr_rmesg[58:57],st_mr_rmesg[49:46],st_mr_rmesg[44],st_mr_rmesg[42],st_mr_rmesg[38]}),
.\m_payload_i_reg[46]_1 ({st_mr_rid[35:24],p_34_out}),
.m_valid_i(m_valid_i),
.p_32_out(p_32_out),
.p_54_out(p_54_out),
.p_74_out(p_74_out),
.\s_axi_araddr[25] (st_aa_artarget_hot[0]),
.\s_axi_araddr[25]_0 (addr_arbiter_ar_n_82),
.\s_axi_araddr[31] ({\s_axi_arqos[3] [31:16],s_axi_arid}),
.s_axi_rdata({s_axi_rdata[31],s_axi_rdata[27],s_axi_rdata[22],s_axi_rdata[20:19],s_axi_rdata[11:8],s_axi_rdata[6],s_axi_rdata[4],s_axi_rdata[0]}),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp[1]),
.s_axi_rvalid(s_axi_rvalid),
.st_aa_artarget_hot(st_aa_artarget_hot[1]));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0 \gen_slave_slots[0].gen_si_write.si_transactor_aw
(.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg ),
.S(\gen_master_slots[2].reg_slice_mi_n_20 ),
.SR(reset),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot[2]),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.chosen(\gen_multi_thread.arbiter_resp_inst/chosen_1 ),
.\gen_master_slots[0].w_issuing_cnt_reg[1] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_2 ),
.\gen_master_slots[1].w_issuing_cnt_reg[10] (\gen_master_slots[1].reg_slice_mi_n_5 ),
.\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_37 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_38 ),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_0 (\gen_master_slots[2].reg_slice_mi_n_30 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 (\gen_multi_thread.gen_thread_loop[1].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 (\gen_master_slots[2].reg_slice_mi_n_21 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 (\gen_multi_thread.gen_thread_loop[2].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 (\gen_master_slots[2].reg_slice_mi_n_22 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 (\gen_multi_thread.gen_thread_loop[3].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 (\gen_master_slots[2].reg_slice_mi_n_23 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 (\gen_multi_thread.gen_thread_loop[4].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 (\gen_master_slots[2].reg_slice_mi_n_24 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 (\gen_multi_thread.gen_thread_loop[5].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 (\gen_master_slots[2].reg_slice_mi_n_25 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 (\gen_multi_thread.gen_thread_loop[6].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 (\gen_master_slots[2].reg_slice_mi_n_26 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 (\gen_multi_thread.gen_thread_loop[7].active_id_reg ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 (\gen_master_slots[2].reg_slice_mi_n_27 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_10 ),
.\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_11 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_6 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (addr_arbiter_aw_n_20),
.\m_payload_i_reg[11] (\gen_master_slots[2].reg_slice_mi_n_28 ),
.\m_payload_i_reg[12] (\gen_master_slots[1].reg_slice_mi_n_23 ),
.\m_payload_i_reg[13] (\gen_master_slots[2].reg_slice_mi_n_29 ),
.\m_payload_i_reg[2] (\gen_master_slots[2].reg_slice_mi_n_13 ),
.\m_payload_i_reg[3] (\gen_master_slots[1].reg_slice_mi_n_12 ),
.\m_payload_i_reg[4] (\gen_master_slots[1].reg_slice_mi_n_20 ),
.\m_payload_i_reg[5] (\gen_master_slots[1].reg_slice_mi_n_21 ),
.\m_payload_i_reg[6] (\gen_master_slots[2].reg_slice_mi_n_19 ),
.\m_payload_i_reg[7] (\gen_master_slots[1].reg_slice_mi_n_22 ),
.\m_ready_d_reg[1] (\gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ),
.\m_ready_d_reg[1]_0 (addr_arbiter_aw_n_14),
.m_valid_i(m_valid_i_2),
.m_valid_i_reg(\gen_master_slots[1].reg_slice_mi_n_6 ),
.p_38_out(p_38_out),
.p_60_out(p_60_out),
.p_80_out(p_80_out),
.\s_axi_awaddr[31] ({D[31:16],s_axi_awid}),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt({w_issuing_cnt[16],w_issuing_cnt[3:0]}));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter \gen_slave_slots[0].gen_si_write.splitter_aw_si
(.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_slave_slots[0].gen_si_write.splitter_aw_si_n_3 ),
.m_ready_d(m_ready_d),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.ss_aa_awready(ss_aa_awready),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router \gen_slave_slots[0].gen_si_write.wdata_router_w
(.D(\gen_slave_slots[0].gen_si_write.si_transactor_aw_n_8 ),
.SR(reset),
.aclk(aclk),
.\gen_axi.write_cs_reg[1] (\gen_slave_slots[0].gen_si_write.wdata_router_w_n_3 ),
.\gen_axi.write_cs_reg[1]_0 (write_cs),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d[1]),
.p_14_in(p_14_in),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.ss_wr_awready(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3 splitter_aw_mi
(.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\gen_no_arbiter.m_target_hot_i_reg[1] (addr_arbiter_aw_n_3),
.m_ready_d(m_ready_d_3),
.\m_ready_d_reg[0]_0 (addr_arbiter_aw_n_21),
.\m_ready_d_reg[0]_1 (addr_arbiter_aw_n_2));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_decerr_slave
(mi_awready_2,
p_14_in,
p_21_in,
p_15_in,
p_17_in,
\gen_axi.write_cs_reg[1]_0 ,
mi_arready_2,
\gen_axi.s_axi_arready_i_reg_0 ,
Q,
\skid_buffer_reg[46] ,
SR,
aclk,
aa_mi_awtarget_hot,
aa_sa_awvalid,
m_ready_d,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
aa_mi_arvalid,
mi_rready_2,
\gen_no_arbiter.m_mesg_i_reg[51] ,
\gen_no_arbiter.m_valid_i_reg ,
mi_bready_2,
\m_ready_d_reg[1] ,
\storage_data1_reg[0] ,
s_axi_rlast_i0,
E,
\gen_no_arbiter.m_mesg_i_reg[11] ,
aresetn_d);
output mi_awready_2;
output p_14_in;
output p_21_in;
output p_15_in;
output p_17_in;
output [0:0]\gen_axi.write_cs_reg[1]_0 ;
output mi_arready_2;
output \gen_axi.s_axi_arready_i_reg_0 ;
output [11:0]Q;
output [11:0]\skid_buffer_reg[46] ;
input [0:0]SR;
input aclk;
input [0:0]aa_mi_awtarget_hot;
input aa_sa_awvalid;
input [0:0]m_ready_d;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[2] ;
input aa_mi_arvalid;
input mi_rready_2;
input [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
input \gen_no_arbiter.m_valid_i_reg ;
input mi_bready_2;
input \m_ready_d_reg[1] ;
input \storage_data1_reg[0] ;
input s_axi_rlast_i0;
input [0:0]E;
input [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
input aresetn_d;
wire [0:0]E;
wire [11:0]Q;
wire [0:0]SR;
wire aa_mi_arvalid;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_axi.read_cnt[4]_i_2_n_0 ;
wire \gen_axi.read_cnt[7]_i_1_n_0 ;
wire \gen_axi.read_cnt[7]_i_3_n_0 ;
wire [0:0]\gen_axi.read_cnt_reg ;
wire [7:1]\gen_axi.read_cnt_reg__0 ;
wire \gen_axi.read_cs[0]_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_i_1_n_0 ;
wire \gen_axi.s_axi_arready_i_reg_0 ;
wire \gen_axi.s_axi_awready_i_i_1_n_0 ;
wire \gen_axi.s_axi_bid_i[11]_i_1_n_0 ;
wire \gen_axi.s_axi_bvalid_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_1_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_3_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_4_n_0 ;
wire \gen_axi.s_axi_rlast_i_i_5_n_0 ;
wire \gen_axi.s_axi_wready_i_i_1_n_0 ;
wire \gen_axi.write_cs[0]_i_1_n_0 ;
wire \gen_axi.write_cs[1]_i_1_n_0 ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire [11:0]\gen_no_arbiter.m_mesg_i_reg[11] ;
wire [19:0]\gen_no_arbiter.m_mesg_i_reg[51] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire [0:0]m_ready_d;
wire \m_ready_d_reg[1] ;
wire mi_arready_2;
wire mi_awready_2;
wire mi_bready_2;
wire mi_rready_2;
wire [7:0]p_0_in;
wire p_14_in;
wire p_15_in;
wire p_17_in;
wire p_21_in;
wire s_axi_rlast_i0;
wire [11:0]\skid_buffer_reg[46] ;
wire \storage_data1_reg[0] ;
wire [0:0]write_cs;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h74))
\gen_axi.read_cnt[0]_i_1
(.I0(\gen_axi.read_cnt_reg ),
.I1(p_15_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [12]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h9F90))
\gen_axi.read_cnt[1]_i_1
(.I0(\gen_axi.read_cnt_reg ),
.I1(\gen_axi.read_cnt_reg__0 [1]),
.I2(p_15_in),
.I3(\gen_no_arbiter.m_mesg_i_reg[51] [13]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hA9FFA900))
\gen_axi.read_cnt[2]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [2]),
.I1(\gen_axi.read_cnt_reg__0 [1]),
.I2(\gen_axi.read_cnt_reg ),
.I3(p_15_in),
.I4(\gen_no_arbiter.m_mesg_i_reg[51] [14]),
.O(p_0_in[2]));
LUT6 #(
.INIT(64'hAAA9FFFFAAA90000))
\gen_axi.read_cnt[3]_i_1
(.I0(\gen_axi.read_cnt_reg__0 [3]),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg ),
.I3(\gen_axi.read_cnt_reg__0 [1]),
.I4(p_15_in),
.I5(\gen_no_arbiter.m_mesg_i_reg[51] [15]),
.O(p_0_in[3]));
LUT6 #(
.INIT(64'hFACAFAFACACACACA))
\gen_axi.read_cnt[4]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [16]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(p_15_in),
.I3(\gen_axi.read_cnt_reg__0 [3]),
.I4(\gen_axi.read_cnt[4]_i_2_n_0 ),
.I5(\gen_axi.read_cnt_reg__0 [4]),
.O(p_0_in[4]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h01))
\gen_axi.read_cnt[4]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [1]),
.I1(\gen_axi.read_cnt_reg ),
.I2(\gen_axi.read_cnt_reg__0 [2]),
.O(\gen_axi.read_cnt[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h3CAA))
\gen_axi.read_cnt[5]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [17]),
.I1(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.I3(p_15_in),
.O(p_0_in[5]));
LUT5 #(
.INIT(32'hEE2E22E2))
\gen_axi.read_cnt[6]_i_1
(.I0(\gen_no_arbiter.m_mesg_i_reg[51] [18]),
.I1(p_15_in),
.I2(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I3(\gen_axi.read_cnt_reg__0 [5]),
.I4(\gen_axi.read_cnt_reg__0 [6]),
.O(p_0_in[6]));
LUT6 #(
.INIT(64'h00800080FF800080))
\gen_axi.read_cnt[7]_i_1
(.I0(mi_arready_2),
.I1(\gen_no_arbiter.m_target_hot_i_reg[2] ),
.I2(aa_mi_arvalid),
.I3(p_15_in),
.I4(mi_rready_2),
.I5(\gen_axi.s_axi_arready_i_reg_0 ),
.O(\gen_axi.read_cnt[7]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8B8B8B8B8B874B8))
\gen_axi.read_cnt[7]_i_2
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(p_15_in),
.I2(\gen_no_arbiter.m_mesg_i_reg[51] [19]),
.I3(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I4(\gen_axi.read_cnt_reg__0 [5]),
.I5(\gen_axi.read_cnt_reg__0 [6]),
.O(p_0_in[7]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h00000001))
\gen_axi.read_cnt[7]_i_3
(.I0(\gen_axi.read_cnt_reg ),
.I1(\gen_axi.read_cnt_reg__0 [2]),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [4]),
.I4(\gen_axi.read_cnt_reg__0 [3]),
.O(\gen_axi.read_cnt[7]_i_3_n_0 ));
FDRE \gen_axi.read_cnt_reg[0]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[0]),
.Q(\gen_axi.read_cnt_reg ),
.R(SR));
FDRE \gen_axi.read_cnt_reg[1]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[1]),
.Q(\gen_axi.read_cnt_reg__0 [1]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[2]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[2]),
.Q(\gen_axi.read_cnt_reg__0 [2]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[3]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[3]),
.Q(\gen_axi.read_cnt_reg__0 [3]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[4]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[4]),
.Q(\gen_axi.read_cnt_reg__0 [4]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[5]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[5]),
.Q(\gen_axi.read_cnt_reg__0 [5]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[6]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[6]),
.Q(\gen_axi.read_cnt_reg__0 [6]),
.R(SR));
FDRE \gen_axi.read_cnt_reg[7]
(.C(aclk),
.CE(\gen_axi.read_cnt[7]_i_1_n_0 ),
.D(p_0_in[7]),
.Q(\gen_axi.read_cnt_reg__0 [7]),
.R(SR));
LUT6 #(
.INIT(64'h0080FF80FF80FF80))
\gen_axi.read_cs[0]_i_1
(.I0(mi_arready_2),
.I1(\gen_no_arbiter.m_target_hot_i_reg[2] ),
.I2(aa_mi_arvalid),
.I3(p_15_in),
.I4(mi_rready_2),
.I5(\gen_axi.s_axi_arready_i_reg_0 ),
.O(\gen_axi.read_cs[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.read_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.read_cs[0]_i_1_n_0 ),
.Q(p_15_in),
.R(SR));
LUT6 #(
.INIT(64'h00000000FBBB0000))
\gen_axi.s_axi_arready_i_i_1
(.I0(mi_arready_2),
.I1(p_15_in),
.I2(mi_rready_2),
.I3(\gen_axi.s_axi_arready_i_reg_0 ),
.I4(aresetn_d),
.I5(E),
.O(\gen_axi.s_axi_arready_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h0002))
\gen_axi.s_axi_arready_i_i_2
(.I0(\gen_axi.read_cnt[7]_i_3_n_0 ),
.I1(\gen_axi.read_cnt_reg__0 [5]),
.I2(\gen_axi.read_cnt_reg__0 [6]),
.I3(\gen_axi.read_cnt_reg__0 [7]),
.O(\gen_axi.s_axi_arready_i_reg_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_arready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_arready_i_i_1_n_0 ),
.Q(mi_arready_2),
.R(1'b0));
LUT6 #(
.INIT(64'hFFFFF7F70F000F0F))
\gen_axi.s_axi_awready_i_i_1
(.I0(\gen_no_arbiter.m_valid_i_reg ),
.I1(aa_mi_awtarget_hot),
.I2(write_cs),
.I3(mi_bready_2),
.I4(\gen_axi.write_cs_reg[1]_0 ),
.I5(mi_awready_2),
.O(\gen_axi.s_axi_awready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_awready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_awready_i_i_1_n_0 ),
.Q(mi_awready_2),
.R(SR));
LUT6 #(
.INIT(64'h0000000010000000))
\gen_axi.s_axi_bid_i[11]_i_1
(.I0(write_cs),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(mi_awready_2),
.I3(aa_mi_awtarget_hot),
.I4(aa_sa_awvalid),
.I5(m_ready_d),
.O(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ));
FDRE \gen_axi.s_axi_bid_i_reg[0]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [0]),
.Q(Q[0]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[10]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [10]),
.Q(Q[10]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[11]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [11]),
.Q(Q[11]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[1]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [1]),
.Q(Q[1]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[2]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [2]),
.Q(Q[2]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[3]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [3]),
.Q(Q[3]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[4]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [4]),
.Q(Q[4]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[5]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [5]),
.Q(Q[5]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[6]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [6]),
.Q(Q[6]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[7]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [7]),
.Q(Q[7]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[8]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [8]),
.Q(Q[8]),
.R(SR));
FDRE \gen_axi.s_axi_bid_i_reg[9]
(.C(aclk),
.CE(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.D(\gen_no_arbiter.m_mesg_i_reg[11] [9]),
.Q(Q[9]),
.R(SR));
LUT5 #(
.INIT(32'hEFFFA888))
\gen_axi.s_axi_bvalid_i_i_1
(.I0(\storage_data1_reg[0] ),
.I1(write_cs),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(mi_bready_2),
.I4(p_21_in),
.O(\gen_axi.s_axi_bvalid_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_bvalid_i_i_1_n_0 ),
.Q(p_21_in),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[0]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [0]),
.Q(\skid_buffer_reg[46] [0]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[10]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [10]),
.Q(\skid_buffer_reg[46] [10]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[11]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [11]),
.Q(\skid_buffer_reg[46] [11]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[1]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [1]),
.Q(\skid_buffer_reg[46] [1]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[2]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [2]),
.Q(\skid_buffer_reg[46] [2]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[3]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [3]),
.Q(\skid_buffer_reg[46] [3]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[4]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [4]),
.Q(\skid_buffer_reg[46] [4]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[5]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [5]),
.Q(\skid_buffer_reg[46] [5]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[6]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [6]),
.Q(\skid_buffer_reg[46] [6]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[7]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [7]),
.Q(\skid_buffer_reg[46] [7]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[8]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [8]),
.Q(\skid_buffer_reg[46] [8]),
.R(SR));
FDRE \gen_axi.s_axi_rid_i_reg[9]
(.C(aclk),
.CE(E),
.D(\gen_no_arbiter.m_mesg_i_reg[51] [9]),
.Q(\skid_buffer_reg[46] [9]),
.R(SR));
LUT6 #(
.INIT(64'hBBBBBBBA8888888A))
\gen_axi.s_axi_rlast_i_i_1
(.I0(s_axi_rlast_i0),
.I1(E),
.I2(\gen_axi.s_axi_rlast_i_i_3_n_0 ),
.I3(\gen_axi.s_axi_rlast_i_i_4_n_0 ),
.I4(\gen_axi.s_axi_rlast_i_i_5_n_0 ),
.I5(p_17_in),
.O(\gen_axi.s_axi_rlast_i_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\gen_axi.s_axi_rlast_i_i_3
(.I0(\gen_axi.read_cnt_reg__0 [7]),
.I1(\gen_axi.read_cnt_reg__0 [6]),
.I2(\gen_axi.read_cnt_reg__0 [5]),
.O(\gen_axi.s_axi_rlast_i_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h7))
\gen_axi.s_axi_rlast_i_i_4
(.I0(p_15_in),
.I1(mi_rready_2),
.O(\gen_axi.s_axi_rlast_i_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_axi.s_axi_rlast_i_i_5
(.I0(\gen_axi.read_cnt_reg__0 [3]),
.I1(\gen_axi.read_cnt_reg__0 [4]),
.I2(\gen_axi.read_cnt_reg__0 [1]),
.I3(\gen_axi.read_cnt_reg__0 [2]),
.O(\gen_axi.s_axi_rlast_i_i_5_n_0 ));
FDRE \gen_axi.s_axi_rlast_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_rlast_i_i_1_n_0 ),
.Q(p_17_in),
.R(SR));
LUT5 #(
.INIT(32'h0FFF0202))
\gen_axi.s_axi_wready_i_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(write_cs),
.I3(\storage_data1_reg[0] ),
.I4(p_14_in),
.O(\gen_axi.s_axi_wready_i_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_axi.s_axi_wready_i_reg
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.s_axi_wready_i_i_1_n_0 ),
.Q(p_14_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h0252))
\gen_axi.write_cs[0]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(\gen_axi.write_cs_reg[1]_0 ),
.I2(write_cs),
.I3(\storage_data1_reg[0] ),
.O(\gen_axi.write_cs[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'hFF10FA10))
\gen_axi.write_cs[1]_i_1
(.I0(\gen_axi.s_axi_bid_i[11]_i_1_n_0 ),
.I1(mi_bready_2),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(write_cs),
.I4(\storage_data1_reg[0] ),
.O(\gen_axi.write_cs[1]_i_1_n_0 ));
FDRE \gen_axi.write_cs_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[0]_i_1_n_0 ),
.Q(write_cs),
.R(SR));
FDRE \gen_axi.write_cs_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_axi.write_cs[1]_i_1_n_0 ),
.Q(\gen_axi.write_cs_reg[1]_0 ),
.R(SR));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_multi_thread.accept_cnt_reg[2]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_artarget_hot,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
E,
chosen,
s_axi_rlast,
s_axi_rvalid,
s_axi_rresp,
s_axi_rid,
s_axi_rdata,
\m_payload_i_reg[34] ,
aresetn_d,
\s_axi_araddr[25] ,
\gen_no_arbiter.s_ready_i_reg[0]_1 ,
\s_axi_araddr[25]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[2]_0 ,
\gen_no_arbiter.m_valid_i_reg ,
\s_axi_araddr[31] ,
p_74_out,
s_axi_rready,
p_54_out,
p_32_out,
\m_payload_i_reg[46] ,
\m_payload_i_reg[46]_0 ,
\m_payload_i_reg[46]_1 ,
SR,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \gen_multi_thread.accept_cnt_reg[2]_0 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]st_aa_artarget_hot;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ;
output \gen_no_arbiter.s_ready_i_reg[0]_0 ;
output [0:0]E;
output [2:0]chosen;
output [0:0]s_axi_rlast;
output [0:0]s_axi_rvalid;
output [0:0]s_axi_rresp;
output [11:0]s_axi_rid;
output [11:0]s_axi_rdata;
output [0:0]\m_payload_i_reg[34] ;
input aresetn_d;
input [0:0]\s_axi_araddr[25] ;
input \gen_no_arbiter.s_ready_i_reg[0]_1 ;
input \s_axi_araddr[25]_0 ;
input [0:0]\gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
input \gen_no_arbiter.m_valid_i_reg ;
input [27:0]\s_axi_araddr[31] ;
input p_74_out;
input [0:0]s_axi_rready;
input p_54_out;
input p_32_out;
input [25:0]\m_payload_i_reg[46] ;
input [25:0]\m_payload_i_reg[46]_0 ;
input [12:0]\m_payload_i_reg[46]_1 ;
input [0:0]SR;
input aclk;
wire [0:0]E;
wire [0:0]SR;
wire aclk;
wire [59:0]active_cnt;
wire [57:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1_n_0;
wire aid_match_00_carry_i_2_n_0;
wire aid_match_00_carry_i_3_n_0;
wire aid_match_00_carry_i_4_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_10;
wire aid_match_10_carry_i_1_n_0;
wire aid_match_10_carry_i_2_n_0;
wire aid_match_10_carry_i_3_n_0;
wire aid_match_10_carry_i_4_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_20;
wire aid_match_20_carry_i_1_n_0;
wire aid_match_20_carry_i_2_n_0;
wire aid_match_20_carry_i_3_n_0;
wire aid_match_20_carry_i_4_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_30;
wire aid_match_30_carry_i_1_n_0;
wire aid_match_30_carry_i_2_n_0;
wire aid_match_30_carry_i_3_n_0;
wire aid_match_30_carry_i_4_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_40;
wire aid_match_40_carry_i_1_n_0;
wire aid_match_40_carry_i_2_n_0;
wire aid_match_40_carry_i_3_n_0;
wire aid_match_40_carry_i_4_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_50;
wire aid_match_50_carry_i_1_n_0;
wire aid_match_50_carry_i_2_n_0;
wire aid_match_50_carry_i_3_n_0;
wire aid_match_50_carry_i_4_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_60;
wire aid_match_60_carry_i_1_n_0;
wire aid_match_60_carry_i_2_n_0;
wire aid_match_60_carry_i_3_n_0;
wire aid_match_60_carry_i_4_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_70;
wire aid_match_70_carry_i_1_n_0;
wire aid_match_70_carry_i_2_n_0;
wire aid_match_70_carry_i_3_n_0;
wire aid_match_70_carry_i_4_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aresetn_d;
wire [2:0]chosen;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire \gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.accept_cnt_reg[2]_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg__0 ;
wire \gen_multi_thread.arbiter_resp_inst_n_0 ;
wire \gen_multi_thread.arbiter_resp_inst_n_1 ;
wire \gen_multi_thread.arbiter_resp_inst_n_10 ;
wire \gen_multi_thread.arbiter_resp_inst_n_11 ;
wire \gen_multi_thread.arbiter_resp_inst_n_12 ;
wire \gen_multi_thread.arbiter_resp_inst_n_2 ;
wire \gen_multi_thread.arbiter_resp_inst_n_20 ;
wire \gen_multi_thread.arbiter_resp_inst_n_21 ;
wire \gen_multi_thread.arbiter_resp_inst_n_22 ;
wire \gen_multi_thread.arbiter_resp_inst_n_23 ;
wire \gen_multi_thread.arbiter_resp_inst_n_24 ;
wire \gen_multi_thread.arbiter_resp_inst_n_25 ;
wire \gen_multi_thread.arbiter_resp_inst_n_26 ;
wire \gen_multi_thread.arbiter_resp_inst_n_27 ;
wire \gen_multi_thread.arbiter_resp_inst_n_28 ;
wire \gen_multi_thread.arbiter_resp_inst_n_29 ;
wire \gen_multi_thread.arbiter_resp_inst_n_30 ;
wire \gen_multi_thread.arbiter_resp_inst_n_31 ;
wire \gen_multi_thread.arbiter_resp_inst_n_32 ;
wire \gen_multi_thread.arbiter_resp_inst_n_33 ;
wire \gen_multi_thread.arbiter_resp_inst_n_34 ;
wire \gen_multi_thread.arbiter_resp_inst_n_35 ;
wire \gen_multi_thread.arbiter_resp_inst_n_36 ;
wire \gen_multi_thread.arbiter_resp_inst_n_37 ;
wire \gen_multi_thread.arbiter_resp_inst_n_38 ;
wire \gen_multi_thread.arbiter_resp_inst_n_39 ;
wire \gen_multi_thread.arbiter_resp_inst_n_4 ;
wire \gen_multi_thread.arbiter_resp_inst_n_40 ;
wire \gen_multi_thread.arbiter_resp_inst_n_41 ;
wire \gen_multi_thread.arbiter_resp_inst_n_42 ;
wire \gen_multi_thread.arbiter_resp_inst_n_43 ;
wire \gen_multi_thread.arbiter_resp_inst_n_44 ;
wire \gen_multi_thread.arbiter_resp_inst_n_45 ;
wire \gen_multi_thread.arbiter_resp_inst_n_46 ;
wire \gen_multi_thread.arbiter_resp_inst_n_47 ;
wire \gen_multi_thread.arbiter_resp_inst_n_48 ;
wire \gen_multi_thread.arbiter_resp_inst_n_49 ;
wire \gen_multi_thread.arbiter_resp_inst_n_5 ;
wire \gen_multi_thread.arbiter_resp_inst_n_50 ;
wire \gen_multi_thread.arbiter_resp_inst_n_51 ;
wire \gen_multi_thread.arbiter_resp_inst_n_6 ;
wire \gen_multi_thread.arbiter_resp_inst_n_7 ;
wire \gen_multi_thread.arbiter_resp_inst_n_8 ;
wire \gen_multi_thread.arbiter_resp_inst_n_9 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire [0:0]\gen_no_arbiter.m_target_hot_i_reg[2]_0 ;
wire \gen_no_arbiter.m_valid_i_reg ;
wire \gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_13_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0]_1 ;
wire [0:0]\m_payload_i_reg[34] ;
wire [25:0]\m_payload_i_reg[46] ;
wire [25:0]\m_payload_i_reg[46]_0 ;
wire [12:0]\m_payload_i_reg[46]_1 ;
wire m_valid_i;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_10_out;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_12_out;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_32_out;
wire p_4_out;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_54_out;
wire p_6_out;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_74_out;
wire p_8_out;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [0:0]\s_axi_araddr[25] ;
wire \s_axi_araddr[25]_0 ;
wire [27:0]\s_axi_araddr[31] ;
wire [11:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [0:0]st_aa_artarget_hot;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1_n_0,aid_match_00_carry_i_2_n_0,aid_match_00_carry_i_3_n_0,aid_match_00_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.O(aid_match_00_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.I1(\s_axi_araddr[31] [7]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.O(aid_match_00_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.O(aid_match_00_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.O(aid_match_00_carry_i_4_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1_n_0,aid_match_10_carry_i_2_n_0,aid_match_10_carry_i_3_n_0,aid_match_10_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1
(.I0(\s_axi_araddr[31] [10]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.I3(\s_axi_araddr[31] [9]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.I5(\s_axi_araddr[31] [11]),
.O(aid_match_10_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2
(.I0(\s_axi_araddr[31] [7]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.I3(\s_axi_araddr[31] [8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.I5(\s_axi_araddr[31] [6]),
.O(aid_match_10_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3
(.I0(\s_axi_araddr[31] [3]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.I3(\s_axi_araddr[31] [5]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.I5(\s_axi_araddr[31] [4]),
.O(aid_match_10_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4
(.I0(\s_axi_araddr[31] [0]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.I3(\s_axi_araddr[31] [2]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.I5(\s_axi_araddr[31] [1]),
.O(aid_match_10_carry_i_4_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1_n_0,aid_match_20_carry_i_2_n_0,aid_match_20_carry_i_3_n_0,aid_match_20_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.O(aid_match_20_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.I1(\s_axi_araddr[31] [7]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.O(aid_match_20_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.O(aid_match_20_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.O(aid_match_20_carry_i_4_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1_n_0,aid_match_30_carry_i_2_n_0,aid_match_30_carry_i_3_n_0,aid_match_30_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.I1(\s_axi_araddr[31] [10]),
.I2(\s_axi_araddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.I4(\s_axi_araddr[31] [9]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.O(aid_match_30_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.O(aid_match_30_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.O(aid_match_30_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.I4(\s_axi_araddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.O(aid_match_30_carry_i_4_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1_n_0,aid_match_40_carry_i_2_n_0,aid_match_40_carry_i_3_n_0,aid_match_40_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.O(aid_match_40_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.O(aid_match_40_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3
(.I0(\s_axi_araddr[31] [5]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.I2(\s_axi_araddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.I5(\s_axi_araddr[31] [4]),
.O(aid_match_40_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.O(aid_match_40_carry_i_4_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1_n_0,aid_match_50_carry_i_2_n_0,aid_match_50_carry_i_3_n_0,aid_match_50_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.O(aid_match_50_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.O(aid_match_50_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.O(aid_match_50_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.O(aid_match_50_carry_i_4_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1_n_0,aid_match_60_carry_i_2_n_0,aid_match_60_carry_i_3_n_0,aid_match_60_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.I1(\s_axi_araddr[31] [9]),
.I2(\s_axi_araddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.I4(\s_axi_araddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.O(aid_match_60_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.I4(\s_axi_araddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.O(aid_match_60_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.I4(\s_axi_araddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.O(aid_match_60_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.I1(\s_axi_araddr[31] [0]),
.I2(\s_axi_araddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.O(aid_match_60_carry_i_4_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1_n_0,aid_match_70_carry_i_2_n_0,aid_match_70_carry_i_3_n_0,aid_match_70_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.I1(\s_axi_araddr[31] [10]),
.I2(\s_axi_araddr[31] [9]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.I4(\s_axi_araddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.O(aid_match_70_carry_i_1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.I1(\s_axi_araddr[31] [6]),
.I2(\s_axi_araddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.I4(\s_axi_araddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.O(aid_match_70_carry_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.I1(\s_axi_araddr[31] [3]),
.I2(\s_axi_araddr[31] [4]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.I4(\s_axi_araddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.O(aid_match_70_carry_i_3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.I1(\s_axi_araddr[31] [1]),
.I2(\s_axi_araddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.I4(\s_axi_araddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.O(aid_match_70_carry_i_4_n_0));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1__0_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_2 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_1 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 [3]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp_5 \gen_multi_thread.arbiter_resp_inst
(.CO(p_8_out),
.D({\gen_multi_thread.arbiter_resp_inst_n_0 ,\gen_multi_thread.arbiter_resp_inst_n_1 ,\gen_multi_thread.arbiter_resp_inst_n_2 }),
.E(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.Q(\gen_multi_thread.accept_cnt_reg__0 ),
.S({\gen_multi_thread.arbiter_resp_inst_n_20 ,\gen_multi_thread.arbiter_resp_inst_n_21 ,\gen_multi_thread.arbiter_resp_inst_n_22 ,\gen_multi_thread.arbiter_resp_inst_n_23 }),
.SR(SR),
.aclk(aclk),
.\chosen_reg[1]_0 (chosen[1]),
.cmd_push_0(cmd_push_0),
.cmd_push_3(cmd_push_3),
.\gen_multi_thread.accept_cnt_reg[2] (\gen_multi_thread.accept_cnt_reg[2]_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.arbiter_resp_inst_n_12 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.arbiter_resp_inst_n_11 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] (p_14_out),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[11] (\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.arbiter_resp_inst_n_10 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]_0 ({\gen_multi_thread.arbiter_resp_inst_n_24 ,\gen_multi_thread.arbiter_resp_inst_n_25 ,\gen_multi_thread.arbiter_resp_inst_n_26 ,\gen_multi_thread.arbiter_resp_inst_n_27 }),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[23] (\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] (\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.arbiter_resp_inst_n_9 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ({\gen_multi_thread.arbiter_resp_inst_n_28 ,\gen_multi_thread.arbiter_resp_inst_n_29 ,\gen_multi_thread.arbiter_resp_inst_n_30 ,\gen_multi_thread.arbiter_resp_inst_n_31 }),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[35] (\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] (\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ({\gen_multi_thread.arbiter_resp_inst_n_32 ,\gen_multi_thread.arbiter_resp_inst_n_33 ,\gen_multi_thread.arbiter_resp_inst_n_34 ,\gen_multi_thread.arbiter_resp_inst_n_35 }),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[47] (\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.arbiter_resp_inst_n_8 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ({\gen_multi_thread.arbiter_resp_inst_n_36 ,\gen_multi_thread.arbiter_resp_inst_n_37 ,\gen_multi_thread.arbiter_resp_inst_n_38 ,\gen_multi_thread.arbiter_resp_inst_n_39 }),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35] (\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[59] (\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] (\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.arbiter_resp_inst_n_7 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ({\gen_multi_thread.arbiter_resp_inst_n_40 ,\gen_multi_thread.arbiter_resp_inst_n_41 ,\gen_multi_thread.arbiter_resp_inst_n_42 ,\gen_multi_thread.arbiter_resp_inst_n_43 }),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[71] (\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.arbiter_resp_inst_n_6 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ({\gen_multi_thread.arbiter_resp_inst_n_44 ,\gen_multi_thread.arbiter_resp_inst_n_45 ,\gen_multi_thread.arbiter_resp_inst_n_46 ,\gen_multi_thread.arbiter_resp_inst_n_47 }),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] (\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[83] (\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.arbiter_resp_inst_n_5 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ({\gen_multi_thread.arbiter_resp_inst_n_48 ,\gen_multi_thread.arbiter_resp_inst_n_49 ,\gen_multi_thread.arbiter_resp_inst_n_50 ,\gen_multi_thread.arbiter_resp_inst_n_51 }),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59] (\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[94] (p_0_out),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[95] (\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_1 (\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_2 (\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_3 (\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_4 (\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.\gen_no_arbiter.s_ready_i_reg[0]_5 (\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[0]_0 (chosen[0]),
.\m_payload_i_reg[34] (chosen[2]),
.\m_payload_i_reg[34]_0 (\m_payload_i_reg[34] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] ),
.\m_payload_i_reg[46]_0 (\m_payload_i_reg[46]_0 ),
.\m_payload_i_reg[46]_1 (\m_payload_i_reg[46]_1 ),
.p_32_out(p_32_out),
.p_54_out(p_54_out),
.p_74_out(p_74_out),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0
(.I0(active_cnt[2]),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(cmd_push_0),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0
(.I0(active_cnt[3]),
.I1(active_cnt[2]),
.I2(cmd_push_0),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1__0_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1__0_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2__0_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg__0 [9]),
.R(SR));
LUT6 #(
.INIT(64'h00000F0088888888))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1__0
(.I0(aid_match_00),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.O(cmd_push_0));
LUT6 #(
.INIT(64'hAAAAAAA8FFFFFFFF))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0
(.I0(aid_match_30),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(st_aa_artarget_hot),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0
(.I0(active_cnt[10]),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0
(.I0(active_cnt[11]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFF55FF55CF55FF55))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3__0_n_0 ),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1__0_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2__0_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1__0_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'h3B080808))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I3(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I4(aid_match_10),
.O(cmd_push_1));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT4 #(
.INIT(16'h0080))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(st_aa_artarget_hot),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair108" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0
(.I0(active_cnt[18]),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0
(.I0(active_cnt[19]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1__0_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1__0_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2__0_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ),
.O(cmd_push_2));
LUT6 #(
.INIT(64'hFF77FF77F077FF77))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0
(.I0(aid_match_20),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(st_aa_artarget_hot),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[17]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0
(.I0(active_cnt[26]),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(cmd_push_3),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0
(.I0(active_cnt[27]),
.I1(active_cnt[26]),
.I2(cmd_push_3),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1__0_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1__0_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2__0_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg__0 [11]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10
(.I0(active_cnt[2]),
.I1(active_cnt[3]),
.I2(active_cnt[1]),
.I3(active_cnt[0]),
.I4(aid_match_00),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11
(.I0(aid_match_60),
.I1(active_cnt[49]),
.I2(active_cnt[48]),
.I3(active_cnt[50]),
.I4(active_cnt[51]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(aid_match_20),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ));
LUT6 #(
.INIT(64'h0A0A0A0A3A0A0A0A))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(cmd_push_3));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.I1(active_cnt[26]),
.I2(active_cnt[27]),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(aid_match_30),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(aid_match_10),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0
(.I0(aid_match_70),
.I1(active_cnt[57]),
.I2(active_cnt[56]),
.I3(active_cnt[58]),
.I4(active_cnt[59]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h7FFFFFFFFFFFFFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0
(.I0(aid_match_40),
.I1(active_cnt[33]),
.I2(active_cnt[32]),
.I3(active_cnt[34]),
.I4(active_cnt[35]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(aid_match_50),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(st_aa_artarget_hot),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[25]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0
(.I0(active_cnt[34]),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0
(.I0(active_cnt[35]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0
(.I0(active_cnt[35]),
.I1(active_cnt[34]),
.I2(active_cnt[32]),
.I3(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1__0_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1__0_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_8 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2__0_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'h5545FFFFFFEFFFFF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I5(aid_match_40),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_12_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_11_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(st_aa_artarget_hot),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[33]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0
(.I0(active_cnt[42]),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0
(.I0(active_cnt[43]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1__0_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1__0_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_7 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2__0_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ),
.O(cmd_push_5));
LUT6 #(
.INIT(64'hFF77FF77F077FF77))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0
(.I0(aid_match_50),
.I1(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAABFFFFFFFF))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7__0_n_0 ),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(active_cnt[27]),
.I4(active_cnt[26]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'h80))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_4_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(st_aa_artarget_hot),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[41]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0
(.I0(active_cnt[50]),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0
(.I0(active_cnt[51]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0
(.I0(active_cnt[51]),
.I1(active_cnt[50]),
.I2(active_cnt[48]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1__0_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1__0_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_6 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2__0_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg__0 [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ),
.O(cmd_push_6));
LUT6 #(
.INIT(64'h5555555545555555))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA800000000))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(active_cnt[51]),
.I2(active_cnt[50]),
.I3(active_cnt[48]),
.I4(active_cnt[49]),
.I5(aid_match_60),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I1(active_cnt[51]),
.I2(active_cnt[50]),
.I3(active_cnt[48]),
.I4(active_cnt[49]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(st_aa_artarget_hot),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[49]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0
(.I0(active_cnt[58]),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0
(.I0(active_cnt[59]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0
(.I0(active_cnt[59]),
.I1(active_cnt[58]),
.I2(active_cnt[56]),
.I3(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1__0_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1__0_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_5 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2__0_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [6]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [7]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_araddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg__0 [11]),
.R(SR));
LUT5 #(
.INIT(32'h00000010))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1__0
(.I0(\s_axi_araddr[31] [17]),
.I1(\s_axi_araddr[31] [20]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ),
.I3(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ),
.O(st_aa_artarget_hot));
LUT6 #(
.INIT(64'h0000000100000000))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2__0
(.I0(\s_axi_araddr[31] [13]),
.I1(\s_axi_araddr[31] [22]),
.I2(\s_axi_araddr[31] [15]),
.I3(\s_axi_araddr[31] [12]),
.I4(\s_axi_araddr[31] [14]),
.I5(\s_axi_araddr[31] [26]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_0 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_3
(.I0(\s_axi_araddr[31] [25]),
.I1(\s_axi_araddr[31] [27]),
.I2(\s_axi_araddr[31] [23]),
.I3(\s_axi_araddr[31] [24]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_1 ));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_4
(.I0(\s_axi_araddr[31] [18]),
.I1(\s_axi_araddr[31] [19]),
.I2(\s_axi_araddr[31] [16]),
.I3(\s_axi_araddr[31] [21]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target_reg[0]_2 ));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ),
.O(cmd_push_7));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2
(.I0(\s_axi_araddr[25]_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFF5555CFFF5555))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i_reg[0]_1 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'hFFEF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5__0_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(st_aa_artarget_hot),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2_n_0 ),
.Q(active_target[57]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT4 #(
.INIT(16'h7F40))
\gen_no_arbiter.m_target_hot_i[2]_i_1__0
(.I0(\s_axi_araddr[25]_0 ),
.I1(m_valid_i),
.I2(aresetn_d),
.I3(\gen_no_arbiter.m_target_hot_i_reg[2]_0 ),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT5 #(
.INIT(32'hDDDDFFFD))
\gen_no_arbiter.s_ready_i[0]_i_10__0
(.I0(aid_match_30),
.I1(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[25]),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ));
LUT5 #(
.INIT(32'h88880008))
\gen_no_arbiter.s_ready_i[0]_i_11
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[49]),
.I4(active_target[48]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ));
LUT5 #(
.INIT(32'h22220002))
\gen_no_arbiter.s_ready_i[0]_i_12__0
(.I0(aid_match_50),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I2(\s_axi_araddr[25] ),
.I3(active_target[41]),
.I4(active_target[40]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ));
LUT6 #(
.INIT(64'h40FF404040404040))
\gen_no_arbiter.s_ready_i[0]_i_13
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I1(aid_match_10),
.I2(active_target[8]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I4(aid_match_00),
.I5(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_13_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_14__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I1(aid_match_50),
.I2(active_target[40]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I4(aid_match_10),
.I5(active_target[8]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ));
LUT6 #(
.INIT(64'h1010101010FF1010))
\gen_no_arbiter.s_ready_i[0]_i_15__0
(.I0(active_target[16]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I2(aid_match_20),
.I3(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I4(aid_match_30),
.I5(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ));
LUT6 #(
.INIT(64'h00000000AAAAAAA8))
\gen_no_arbiter.s_ready_i[0]_i_16__0
(.I0(aid_match_00),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(active_cnt[3]),
.I4(active_cnt[2]),
.I5(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ));
LUT6 #(
.INIT(64'h08080808FF080808))
\gen_no_arbiter.s_ready_i[0]_i_17__0
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(active_target[48]),
.I3(aid_match_40),
.I4(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I5(active_target[32]),
.O(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ));
LUT6 #(
.INIT(64'h00000000F1000000))
\gen_no_arbiter.s_ready_i[0]_i_18__0
(.I0(active_target[33]),
.I1(\s_axi_araddr[25] ),
.I2(active_target[32]),
.I3(aid_match_40),
.I4(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I5(st_aa_artarget_hot),
.O(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_19__0
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3__0_n_0 ),
.I2(active_target[49]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(aid_match_20),
.I5(active_target[17]),
.O(\gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT2 #(
.INIT(4'h8))
\gen_no_arbiter.s_ready_i[0]_i_1__0
(.I0(m_valid_i),
.I1(aresetn_d),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT6 #(
.INIT(64'h7F007F7F7F7F7F7F))
\gen_no_arbiter.s_ready_i[0]_i_20__0
(.I0(active_target[33]),
.I1(aid_match_40),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3__0_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3__0_n_0 ),
.I4(aid_match_50),
.I5(active_target[41]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_21__0
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[57]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_3_n_0 ),
.I4(aid_match_30),
.I5(active_target[25]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ));
LUT6 #(
.INIT(64'h40FF404040404040))
\gen_no_arbiter.s_ready_i[0]_i_22__0
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3__0_n_0 ),
.I1(aid_match_10),
.I2(active_target[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4__0_n_0 ),
.I4(aid_match_00),
.I5(active_target[1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT4 #(
.INIT(16'hFFFD))
\gen_no_arbiter.s_ready_i[0]_i_24__0
(.I0(\gen_multi_thread.accept_cnt_reg__0 [3]),
.I1(\gen_multi_thread.accept_cnt_reg__0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg__0 [1]),
.I3(\gen_multi_thread.accept_cnt_reg__0 [0]),
.O(\gen_no_arbiter.s_ready_i_reg[0]_0 ));
LUT6 #(
.INIT(64'h00000000000002F2))
\gen_no_arbiter.s_ready_i[0]_i_2__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ),
.I2(st_aa_artarget_hot),
.I3(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ),
.I5(\gen_no_arbiter.m_valid_i_reg ),
.O(m_valid_i));
LUT6 #(
.INIT(64'h0000000000000E00))
\gen_no_arbiter.s_ready_i[0]_i_3__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ),
.I1(\s_axi_araddr[25] ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_10__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_11_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_12__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF0000111F))
\gen_no_arbiter.s_ready_i[0]_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4__0_n_0 ),
.I1(active_target[9]),
.I2(active_target[1]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_10_n_0 ),
.I4(\s_axi_araddr[25] ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_13_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEEEF))
\gen_no_arbiter.s_ready_i[0]_i_5__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_14__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_15__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5__0_n_0 ),
.I3(active_target[56]),
.I4(\gen_no_arbiter.s_ready_i[0]_i_16__0_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_17__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFEFAAAAAAAA))
\gen_no_arbiter.s_ready_i[0]_i_6__0
(.I0(\gen_no_arbiter.s_ready_i[0]_i_18__0_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_19__0_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_20__0_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_21__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_22__0_n_0 ),
.I5(\s_axi_araddr[25]_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hF7F7F700F7F7F7F7))
\gen_no_arbiter.s_ready_i[0]_i_8
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[57]),
.I3(active_target[17]),
.I4(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I5(aid_match_20),
.O(\gen_no_arbiter.s_ready_i[0]_i_8_n_0 ));
LUT6 #(
.INIT(64'h80FF808080808080))
\gen_no_arbiter.s_ready_i[0]_i_9
(.I0(aid_match_70),
.I1(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4__0_n_0 ),
.I2(active_target[56]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3__0_n_0 ),
.I4(aid_match_20),
.I5(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9_n_0 ));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_48 ,\gen_multi_thread.arbiter_resp_inst_n_49 ,\gen_multi_thread.arbiter_resp_inst_n_50 ,\gen_multi_thread.arbiter_resp_inst_n_51 }));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_28 ,\gen_multi_thread.arbiter_resp_inst_n_29 ,\gen_multi_thread.arbiter_resp_inst_n_30 ,\gen_multi_thread.arbiter_resp_inst_n_31 }));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_24 ,\gen_multi_thread.arbiter_resp_inst_n_25 ,\gen_multi_thread.arbiter_resp_inst_n_26 ,\gen_multi_thread.arbiter_resp_inst_n_27 }));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_20 ,\gen_multi_thread.arbiter_resp_inst_n_21 ,\gen_multi_thread.arbiter_resp_inst_n_22 ,\gen_multi_thread.arbiter_resp_inst_n_23 }));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_44 ,\gen_multi_thread.arbiter_resp_inst_n_45 ,\gen_multi_thread.arbiter_resp_inst_n_46 ,\gen_multi_thread.arbiter_resp_inst_n_47 }));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_40 ,\gen_multi_thread.arbiter_resp_inst_n_41 ,\gen_multi_thread.arbiter_resp_inst_n_42 ,\gen_multi_thread.arbiter_resp_inst_n_43 }));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_36 ,\gen_multi_thread.arbiter_resp_inst_n_37 ,\gen_multi_thread.arbiter_resp_inst_n_38 ,\gen_multi_thread.arbiter_resp_inst_n_39 }));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({\gen_multi_thread.arbiter_resp_inst_n_32 ,\gen_multi_thread.arbiter_resp_inst_n_33 ,\gen_multi_thread.arbiter_resp_inst_n_34 ,\gen_multi_thread.arbiter_resp_inst_n_35 }));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_si_transactor" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_si_transactor__parameterized0
(\gen_no_arbiter.s_ready_i_reg[0] ,
m_valid_i,
\gen_master_slots[0].w_issuing_cnt_reg[1] ,
chosen,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
st_aa_awtarget_enc,
D,
SR,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ,
Q,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
s_axi_bvalid,
\gen_master_slots[1].w_issuing_cnt_reg[8] ,
\gen_master_slots[2].w_issuing_cnt_reg[16] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ,
S,
aresetn_d,
st_aa_awtarget_hot,
\m_ready_d_reg[1] ,
p_80_out,
s_axi_bready,
aa_mi_awtarget_hot,
\gen_master_slots[1].w_issuing_cnt_reg[10] ,
\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ,
\s_axi_awaddr[31] ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[2] ,
\m_payload_i_reg[4] ,
\m_payload_i_reg[6] ,
\m_payload_i_reg[5] ,
\m_payload_i_reg[7] ,
\m_payload_i_reg[12] ,
\m_payload_i_reg[11] ,
\m_payload_i_reg[13] ,
aa_sa_awvalid,
s_axi_awvalid,
\gen_no_arbiter.s_ready_i_reg[0]_0 ,
m_valid_i_reg,
p_38_out,
p_60_out,
w_issuing_cnt,
\m_ready_d_reg[1]_0 ,
aclk);
output \gen_no_arbiter.s_ready_i_reg[0] ;
output m_valid_i;
output \gen_master_slots[0].w_issuing_cnt_reg[1] ;
output [2:0]chosen;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [0:0]st_aa_awtarget_enc;
output [0:0]D;
output [0:0]SR;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ;
output \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ;
output [2:0]Q;
output [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
output [2:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output [0:0]s_axi_bvalid;
output \gen_master_slots[1].w_issuing_cnt_reg[8] ;
output \gen_master_slots[2].w_issuing_cnt_reg[16] ;
input [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ;
input [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ;
input [0:0]S;
input aresetn_d;
input [0:0]st_aa_awtarget_hot;
input \m_ready_d_reg[1] ;
input p_80_out;
input [0:0]s_axi_bready;
input [0:0]aa_mi_awtarget_hot;
input \gen_master_slots[1].w_issuing_cnt_reg[10] ;
input \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
input [27:0]\s_axi_awaddr[31] ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[2] ;
input \m_payload_i_reg[4] ;
input \m_payload_i_reg[6] ;
input \m_payload_i_reg[5] ;
input \m_payload_i_reg[7] ;
input \m_payload_i_reg[12] ;
input \m_payload_i_reg[11] ;
input \m_payload_i_reg[13] ;
input aa_sa_awvalid;
input [0:0]s_axi_awvalid;
input \gen_no_arbiter.s_ready_i_reg[0]_0 ;
input m_valid_i_reg;
input p_38_out;
input p_60_out;
input [4:0]w_issuing_cnt;
input \m_ready_d_reg[1]_0 ;
input aclk;
wire [0:0]D;
wire [2:0]Q;
wire [0:0]S;
wire [0:0]SR;
wire [0:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire [59:0]active_cnt;
wire [57:0]active_target;
wire aid_match_00;
wire aid_match_00_carry_i_1__0_n_0;
wire aid_match_00_carry_i_2__0_n_0;
wire aid_match_00_carry_i_3__0_n_0;
wire aid_match_00_carry_i_4__0_n_0;
wire aid_match_00_carry_n_1;
wire aid_match_00_carry_n_2;
wire aid_match_00_carry_n_3;
wire aid_match_10;
wire aid_match_10_carry_i_1__0_n_0;
wire aid_match_10_carry_i_2__0_n_0;
wire aid_match_10_carry_i_3__0_n_0;
wire aid_match_10_carry_i_4__0_n_0;
wire aid_match_10_carry_n_1;
wire aid_match_10_carry_n_2;
wire aid_match_10_carry_n_3;
wire aid_match_20;
wire aid_match_20_carry_i_1__0_n_0;
wire aid_match_20_carry_i_2__0_n_0;
wire aid_match_20_carry_i_3__0_n_0;
wire aid_match_20_carry_i_4__0_n_0;
wire aid_match_20_carry_n_1;
wire aid_match_20_carry_n_2;
wire aid_match_20_carry_n_3;
wire aid_match_30;
wire aid_match_30_carry_i_1__0_n_0;
wire aid_match_30_carry_i_2__0_n_0;
wire aid_match_30_carry_i_3__0_n_0;
wire aid_match_30_carry_i_4__0_n_0;
wire aid_match_30_carry_n_1;
wire aid_match_30_carry_n_2;
wire aid_match_30_carry_n_3;
wire aid_match_40;
wire aid_match_40_carry_i_1__0_n_0;
wire aid_match_40_carry_i_2__0_n_0;
wire aid_match_40_carry_i_3__0_n_0;
wire aid_match_40_carry_i_4__0_n_0;
wire aid_match_40_carry_n_1;
wire aid_match_40_carry_n_2;
wire aid_match_40_carry_n_3;
wire aid_match_50;
wire aid_match_50_carry_i_1__0_n_0;
wire aid_match_50_carry_i_2__0_n_0;
wire aid_match_50_carry_i_3__0_n_0;
wire aid_match_50_carry_i_4__0_n_0;
wire aid_match_50_carry_n_1;
wire aid_match_50_carry_n_2;
wire aid_match_50_carry_n_3;
wire aid_match_60;
wire aid_match_60_carry_i_1__0_n_0;
wire aid_match_60_carry_i_2__0_n_0;
wire aid_match_60_carry_i_3__0_n_0;
wire aid_match_60_carry_i_4__0_n_0;
wire aid_match_60_carry_n_1;
wire aid_match_60_carry_n_2;
wire aid_match_60_carry_n_3;
wire aid_match_70;
wire aid_match_70_carry_i_1__0_n_0;
wire aid_match_70_carry_i_2__0_n_0;
wire aid_match_70_carry_i_3__0_n_0;
wire aid_match_70_carry_i_4__0_n_0;
wire aid_match_70_carry_n_1;
wire aid_match_70_carry_n_2;
wire aid_match_70_carry_n_3;
wire aresetn_d;
wire [2:0]chosen;
wire cmd_push_0;
wire cmd_push_1;
wire cmd_push_2;
wire cmd_push_3;
wire cmd_push_4;
wire cmd_push_5;
wire cmd_push_6;
wire cmd_push_7;
wire \gen_master_slots[0].w_issuing_cnt_reg[1] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[10] ;
wire \gen_master_slots[1].w_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16] ;
wire \gen_master_slots[2].w_issuing_cnt_reg[16]_0 ;
wire \gen_multi_thread.accept_cnt[0]_i_1_n_0 ;
wire [3:0]\gen_multi_thread.accept_cnt_reg ;
wire \gen_multi_thread.arbiter_resp_inst_n_10 ;
wire \gen_multi_thread.arbiter_resp_inst_n_11 ;
wire \gen_multi_thread.arbiter_resp_inst_n_12 ;
wire \gen_multi_thread.arbiter_resp_inst_n_13 ;
wire \gen_multi_thread.arbiter_resp_inst_n_14 ;
wire \gen_multi_thread.arbiter_resp_inst_n_15 ;
wire \gen_multi_thread.arbiter_resp_inst_n_16 ;
wire \gen_multi_thread.arbiter_resp_inst_n_17 ;
wire \gen_multi_thread.arbiter_resp_inst_n_2 ;
wire \gen_multi_thread.arbiter_resp_inst_n_3 ;
wire \gen_multi_thread.arbiter_resp_inst_n_4 ;
wire \gen_multi_thread.arbiter_resp_inst_n_9 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ;
wire \gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ;
wire \gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ;
wire \gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire [11:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ;
wire \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i[0]_i_10_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_12_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_14_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_15_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_16_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_17_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_18_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_19_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_20_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_21_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_22_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_23_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_28_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_3_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_4_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_5_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_6_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ;
wire \gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire \gen_no_arbiter.s_ready_i_reg[0]_0 ;
wire i__carry_i_1_n_0;
wire i__carry_i_3_n_0;
wire i__carry_i_4_n_0;
wire \m_payload_i_reg[11] ;
wire \m_payload_i_reg[12] ;
wire \m_payload_i_reg[13] ;
wire \m_payload_i_reg[2] ;
wire \m_payload_i_reg[3] ;
wire \m_payload_i_reg[4] ;
wire \m_payload_i_reg[5] ;
wire \m_payload_i_reg[6] ;
wire \m_payload_i_reg[7] ;
wire \m_ready_d_reg[1] ;
wire \m_ready_d_reg[1]_0 ;
wire m_valid_i;
wire m_valid_i_reg;
wire p_0_out;
wire \p_0_out_inferred__9/i__carry_n_1 ;
wire \p_0_out_inferred__9/i__carry_n_2 ;
wire \p_0_out_inferred__9/i__carry_n_3 ;
wire p_10_out;
wire p_10_out_carry_i_1_n_0;
wire p_10_out_carry_i_3_n_0;
wire p_10_out_carry_i_4_n_0;
wire p_10_out_carry_n_1;
wire p_10_out_carry_n_2;
wire p_10_out_carry_n_3;
wire p_12_out;
wire p_12_out_carry_i_1_n_0;
wire p_12_out_carry_i_3_n_0;
wire p_12_out_carry_i_4_n_0;
wire p_12_out_carry_n_1;
wire p_12_out_carry_n_2;
wire p_12_out_carry_n_3;
wire p_14_out;
wire p_14_out_carry_i_1_n_0;
wire p_14_out_carry_i_3_n_0;
wire p_14_out_carry_i_4_n_0;
wire p_14_out_carry_n_1;
wire p_14_out_carry_n_2;
wire p_14_out_carry_n_3;
wire p_2_out;
wire p_2_out_carry_i_1_n_0;
wire p_2_out_carry_i_3_n_0;
wire p_2_out_carry_i_4_n_0;
wire p_2_out_carry_n_1;
wire p_2_out_carry_n_2;
wire p_2_out_carry_n_3;
wire p_38_out;
wire p_4_out;
wire p_4_out_carry_i_1_n_0;
wire p_4_out_carry_i_3_n_0;
wire p_4_out_carry_i_4_n_0;
wire p_4_out_carry_n_1;
wire p_4_out_carry_n_2;
wire p_4_out_carry_n_3;
wire p_60_out;
wire p_6_out;
wire p_6_out_carry_i_1_n_0;
wire p_6_out_carry_i_3_n_0;
wire p_6_out_carry_i_4_n_0;
wire p_6_out_carry_n_1;
wire p_6_out_carry_n_2;
wire p_6_out_carry_n_3;
wire p_80_out;
wire p_8_out;
wire p_8_out_carry_i_1_n_0;
wire p_8_out_carry_i_3_n_0;
wire p_8_out_carry_i_4_n_0;
wire p_8_out_carry_n_1;
wire p_8_out_carry_n_2;
wire p_8_out_carry_n_3;
wire [27:0]\s_axi_awaddr[31] ;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_bvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire [4:0]w_issuing_cnt;
wire [3:0]NLW_aid_match_00_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_10_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_20_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_30_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_40_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_50_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_60_carry_O_UNCONNECTED;
wire [3:0]NLW_aid_match_70_carry_O_UNCONNECTED;
wire [3:0]\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED ;
wire [3:0]NLW_p_10_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_12_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_14_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_2_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_4_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_6_out_carry_O_UNCONNECTED;
wire [3:0]NLW_p_8_out_carry_O_UNCONNECTED;
CARRY4 aid_match_00_carry
(.CI(1'b0),
.CO({aid_match_00,aid_match_00_carry_n_1,aid_match_00_carry_n_2,aid_match_00_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_00_carry_O_UNCONNECTED[3:0]),
.S({aid_match_00_carry_i_1__0_n_0,aid_match_00_carry_i_2__0_n_0,aid_match_00_carry_i_3__0_n_0,aid_match_00_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.O(aid_match_00_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_2__0
(.I0(Q[0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [7]),
.I3(Q[1]),
.I4(\s_axi_awaddr[31] [8]),
.I5(Q[2]),
.O(aid_match_00_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I4(\s_axi_awaddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.O(aid_match_00_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_00_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [1]),
.I5(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.O(aid_match_00_carry_i_4__0_n_0));
CARRY4 aid_match_10_carry
(.CI(1'b0),
.CO({aid_match_10,aid_match_10_carry_n_1,aid_match_10_carry_n_2,aid_match_10_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_10_carry_O_UNCONNECTED[3:0]),
.S({aid_match_10_carry_i_1__0_n_0,aid_match_10_carry_i_2__0_n_0,aid_match_10_carry_i_3__0_n_0,aid_match_10_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_1__0
(.I0(\s_axi_awaddr[31] [9]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I3(\s_axi_awaddr[31] [10]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\s_axi_awaddr[31] [11]),
.O(aid_match_10_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_2__0
(.I0(\s_axi_awaddr[31] [6]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [2]),
.I3(\s_axi_awaddr[31] [8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [1]),
.I5(\s_axi_awaddr[31] [7]),
.O(aid_match_10_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_3__0
(.I0(\s_axi_awaddr[31] [3]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I3(\s_axi_awaddr[31] [4]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\s_axi_awaddr[31] [5]),
.O(aid_match_10_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_10_carry_i_4__0
(.I0(\s_axi_awaddr[31] [0]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I3(\s_axi_awaddr[31] [2]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I5(\s_axi_awaddr[31] [1]),
.O(aid_match_10_carry_i_4__0_n_0));
CARRY4 aid_match_20_carry
(.CI(1'b0),
.CO({aid_match_20,aid_match_20_carry_n_1,aid_match_20_carry_n_2,aid_match_20_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_20_carry_O_UNCONNECTED[3:0]),
.S({aid_match_20_carry_i_1__0_n_0,aid_match_20_carry_i_2__0_n_0,aid_match_20_carry_i_3__0_n_0,aid_match_20_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.O(aid_match_20_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]),
.I4(\s_axi_awaddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]),
.O(aid_match_20_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.O(aid_match_20_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_20_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [0]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.O(aid_match_20_carry_i_4__0_n_0));
CARRY4 aid_match_30_carry
(.CI(1'b0),
.CO({aid_match_30,aid_match_30_carry_n_1,aid_match_30_carry_n_2,aid_match_30_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_30_carry_O_UNCONNECTED[3:0]),
.S({aid_match_30_carry_i_1__0_n_0,aid_match_30_carry_i_2__0_n_0,aid_match_30_carry_i_3__0_n_0,aid_match_30_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I1(\s_axi_awaddr[31] [10]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [9]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.O(aid_match_30_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [7]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [1]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [2]),
.O(aid_match_30_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I1(\s_axi_awaddr[31] [3]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.O(aid_match_30_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_30_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.O(aid_match_30_carry_i_4__0_n_0));
CARRY4 aid_match_40_carry
(.CI(1'b0),
.CO({aid_match_40,aid_match_40_carry_n_1,aid_match_40_carry_n_2,aid_match_40_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_40_carry_O_UNCONNECTED[3:0]),
.S({aid_match_40_carry_i_1__0_n_0,aid_match_40_carry_i_2__0_n_0,aid_match_40_carry_i_3__0_n_0,aid_match_40_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.O(aid_match_40_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [6]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]),
.O(aid_match_40_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [3]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I4(\s_axi_awaddr[31] [5]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.O(aid_match_40_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_40_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.O(aid_match_40_carry_i_4__0_n_0));
CARRY4 aid_match_50_carry
(.CI(1'b0),
.CO({aid_match_50,aid_match_50_carry_n_1,aid_match_50_carry_n_2,aid_match_50_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_50_carry_O_UNCONNECTED[3:0]),
.S({aid_match_50_carry_i_1__0_n_0,aid_match_50_carry_i_2__0_n_0,aid_match_50_carry_i_3__0_n_0,aid_match_50_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I1(\s_axi_awaddr[31] [10]),
.I2(\s_axi_awaddr[31] [9]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.O(aid_match_50_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]),
.I4(\s_axi_awaddr[31] [6]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]),
.O(aid_match_50_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.O(aid_match_50_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_50_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.O(aid_match_50_carry_i_4__0_n_0));
CARRY4 aid_match_60_carry
(.CI(1'b0),
.CO({aid_match_60,aid_match_60_carry_n_1,aid_match_60_carry_n_2,aid_match_60_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_60_carry_O_UNCONNECTED[3:0]),
.S({aid_match_60_carry_i_1__0_n_0,aid_match_60_carry_i_2__0_n_0,aid_match_60_carry_i_3__0_n_0,aid_match_60_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [11]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.I4(\s_axi_awaddr[31] [10]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.O(aid_match_60_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]),
.I1(\s_axi_awaddr[31] [6]),
.I2(\s_axi_awaddr[31] [8]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]),
.I4(\s_axi_awaddr[31] [7]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]),
.O(aid_match_60_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I1(\s_axi_awaddr[31] [3]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [4]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.O(aid_match_60_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_60_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I1(\s_axi_awaddr[31] [0]),
.I2(\s_axi_awaddr[31] [1]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I4(\s_axi_awaddr[31] [2]),
.I5(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.O(aid_match_60_carry_i_4__0_n_0));
CARRY4 aid_match_70_carry
(.CI(1'b0),
.CO({aid_match_70,aid_match_70_carry_n_1,aid_match_70_carry_n_2,aid_match_70_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_aid_match_70_carry_O_UNCONNECTED[3:0]),
.S({aid_match_70_carry_i_1__0_n_0,aid_match_70_carry_i_2__0_n_0,aid_match_70_carry_i_3__0_n_0,aid_match_70_carry_i_4__0_n_0}));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_1__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I1(\s_axi_awaddr[31] [9]),
.I2(\s_axi_awaddr[31] [10]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I4(\s_axi_awaddr[31] [11]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.O(aid_match_70_carry_i_1__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_2__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]),
.I1(\s_axi_awaddr[31] [7]),
.I2(\s_axi_awaddr[31] [6]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]),
.I4(\s_axi_awaddr[31] [8]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]),
.O(aid_match_70_carry_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I1(\s_axi_awaddr[31] [4]),
.I2(\s_axi_awaddr[31] [5]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.I4(\s_axi_awaddr[31] [3]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.O(aid_match_70_carry_i_3__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
aid_match_70_carry_i_4__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I1(\s_axi_awaddr[31] [1]),
.I2(\s_axi_awaddr[31] [2]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.I4(\s_axi_awaddr[31] [0]),
.I5(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.O(aid_match_70_carry_i_4__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.accept_cnt[0]_i_1
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.O(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.accept_cnt[0]_i_1_n_0 ),
.Q(\gen_multi_thread.accept_cnt_reg [0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_4 ),
.Q(\gen_multi_thread.accept_cnt_reg [1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_3 ),
.Q(\gen_multi_thread.accept_cnt_reg [2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.accept_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_17 ),
.D(\gen_multi_thread.arbiter_resp_inst_n_2 ),
.Q(\gen_multi_thread.accept_cnt_reg [3]),
.R(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_arbiter_resp \gen_multi_thread.arbiter_resp_inst
(.CO(p_0_out),
.D({\gen_multi_thread.arbiter_resp_inst_n_2 ,\gen_multi_thread.arbiter_resp_inst_n_3 ,\gen_multi_thread.arbiter_resp_inst_n_4 }),
.E(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.Q(\gen_multi_thread.accept_cnt_reg ),
.SR(SR),
.aa_mi_awtarget_hot(aa_mi_awtarget_hot),
.aa_sa_awvalid(aa_sa_awvalid),
.aclk(aclk),
.aresetn_d(aresetn_d),
.\chosen_reg[0]_0 (chosen[0]),
.\chosen_reg[1]_0 (chosen[1]),
.cmd_push_0(cmd_push_0),
.cmd_push_3(cmd_push_3),
.\gen_master_slots[0].w_issuing_cnt_reg[1] (\gen_master_slots[0].w_issuing_cnt_reg[1] ),
.\gen_master_slots[1].w_issuing_cnt_reg[10] (\gen_master_slots[1].w_issuing_cnt_reg[10] ),
.\gen_master_slots[1].w_issuing_cnt_reg[8] (\gen_master_slots[1].w_issuing_cnt_reg[8] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16] (chosen[2]),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_0 (\gen_master_slots[2].w_issuing_cnt_reg[16] ),
.\gen_master_slots[2].w_issuing_cnt_reg[16]_1 (\gen_master_slots[2].w_issuing_cnt_reg[16]_0 ),
.\gen_multi_thread.accept_cnt_reg[0] (\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.arbiter_resp_inst_n_17 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.arbiter_resp_inst_n_16 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[10] (p_14_out),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.arbiter_resp_inst_n_15 ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8] (\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[22] (p_12_out),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16] (\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.arbiter_resp_inst_n_14 ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[34] (p_10_out),
.\gen_multi_thread.gen_thread_loop[2].active_target_reg[17] (\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24] (\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.arbiter_resp_inst_n_13 ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[46] (p_8_out),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32] (\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.arbiter_resp_inst_n_12 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 (\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_1 (\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[58] (p_6_out),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40] (\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.arbiter_resp_inst_n_11 ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[70] (p_4_out),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.arbiter_resp_inst_n_10 ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51] (\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[82] (p_2_out),
.\gen_multi_thread.gen_thread_loop[6].active_target_reg[48] (\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56] (\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.\gen_no_arbiter.s_ready_i_reg[0]_0 (\gen_no_arbiter.s_ready_i_reg[0]_0 ),
.\m_ready_d_reg[1] (\m_ready_d_reg[1] ),
.\m_ready_d_reg[1]_0 (\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.\m_ready_d_reg[1]_1 (\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.\m_ready_d_reg[1]_2 (\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.\m_ready_d_reg[1]_3 (\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.\m_ready_d_reg[1]_4 (\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.\m_ready_d_reg[1]_5 (\m_ready_d_reg[1]_0 ),
.m_valid_i(m_valid_i),
.m_valid_i_reg(m_valid_i_reg),
.p_38_out(p_38_out),
.p_60_out(p_60_out),
.p_80_out(p_80_out),
.\s_axi_awaddr[26] (st_aa_awtarget_enc),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.w_issuing_cnt(w_issuing_cnt));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0
(.I0(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair138" *)
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1
(.I0(cmd_push_0),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1
(.I0(active_cnt[2]),
.I1(active_cnt[0]),
.I2(active_cnt[1]),
.I3(cmd_push_0),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair122" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2
(.I0(active_cnt[3]),
.I1(active_cnt[2]),
.I2(cmd_push_0),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[0]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[0]_i_1__0_n_0 ),
.Q(active_cnt[0]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[1]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[1]_i_1_n_0 ),
.Q(active_cnt[1]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[2]_i_1_n_0 ),
.Q(active_cnt[2]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[3]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_16 ),
.D(\gen_multi_thread.gen_thread_loop[0].active_cnt[3]_i_2_n_0 ),
.Q(active_cnt[3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[10]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[11]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[2]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[3]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[4]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[5]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[6]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [6]),
.Q(Q[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[7]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [7]),
.Q(Q[1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[8]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [8]),
.Q(Q[2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_id_reg[9]
(.C(aclk),
.CE(cmd_push_0),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.R(SR));
LUT6 #(
.INIT(64'h0500050035300500))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(aid_match_00),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(cmd_push_0));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2
(.I0(aid_match_40),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3
(.I0(active_cnt[42]),
.I1(active_cnt[43]),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(aid_match_50),
.O(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[0]
(.C(aclk),
.CE(cmd_push_0),
.D(st_aa_awtarget_enc),
.Q(active_target[0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[0].active_target_reg[1]
(.C(aclk),
.CE(cmd_push_0),
.D(D),
.Q(active_target[1]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1
(.I0(active_cnt[10]),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.I3(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair126" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2
(.I0(active_cnt[11]),
.I1(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFBBFFBBF0BBFFBB))
\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3
(.I0(\m_ready_d_reg[1] ),
.I1(aid_match_10),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0
(.I0(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_3_n_0 ),
.I1(active_cnt[8]),
.I2(active_cnt[9]),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[10]_i_1_n_0 ),
.Q(active_cnt[10]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[11]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[11]_i_2_n_0 ),
.Q(active_cnt[11]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[8]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[8]_i_1__0_n_0 ),
.Q(active_cnt[8]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[9]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_15 ),
.D(\gen_multi_thread.gen_thread_loop[1].active_cnt[9]_i_1_n_0 ),
.Q(active_cnt[9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[12]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[13]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[14]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[15]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[16]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[17]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[18]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[19]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[20]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg[12]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[21]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[22]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_id_reg[23]
(.C(aclk),
.CE(cmd_push_1),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.R(SR));
LUT5 #(
.INIT(32'h08083B08))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I3(aid_match_10),
.I4(\m_ready_d_reg[1] ),
.O(cmd_push_1));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT4 #(
.INIT(16'h0010))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3
(.I0(active_cnt[8]),
.I1(active_cnt[9]),
.I2(active_cnt[11]),
.I3(active_cnt[10]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4
(.I0(active_cnt[0]),
.I1(active_cnt[1]),
.I2(active_cnt[3]),
.I3(active_cnt[2]),
.O(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[8]
(.C(aclk),
.CE(cmd_push_1),
.D(st_aa_awtarget_enc),
.Q(active_target[8]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[1].active_target_reg[9]
(.C(aclk),
.CE(cmd_push_1),
.D(D),
.Q(active_target[9]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0
(.I0(active_cnt[16]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair135" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1
(.I0(active_cnt[18]),
.I1(active_cnt[16]),
.I2(active_cnt[17]),
.I3(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair123" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2
(.I0(active_cnt[19]),
.I1(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3
(.I0(active_cnt[16]),
.I1(active_cnt[17]),
.I2(active_cnt[19]),
.I3(active_cnt[18]),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[16]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[16]_i_1__0_n_0 ),
.Q(active_cnt[16]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[17]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[17]_i_1_n_0 ),
.Q(active_cnt[17]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[18]_i_1_n_0 ),
.Q(active_cnt[18]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[19]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_14 ),
.D(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_2_n_0 ),
.Q(active_cnt[19]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[24]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[25]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[26]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[27]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[28]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[29]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[30]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[31]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[32]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[33]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[34]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_id_reg[35]
(.C(aclk),
.CE(cmd_push_2),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ),
.O(cmd_push_2));
LUT6 #(
.INIT(64'hFFDDFFDDF0DDFFDD))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2
(.I0(aid_match_20),
.I1(\m_ready_d_reg[1] ),
.I2(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair129" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3
(.I0(active_cnt[10]),
.I1(active_cnt[11]),
.I2(active_cnt[9]),
.I3(active_cnt[8]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_target[17]_i_3_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[16]
(.C(aclk),
.CE(cmd_push_2),
.D(st_aa_awtarget_enc),
.Q(active_target[16]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[2].active_target_reg[17]
(.C(aclk),
.CE(cmd_push_2),
.D(D),
.Q(active_target[17]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0
(.I0(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h69))
\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1
(.I0(cmd_push_3),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT4 #(
.INIT(16'h6AA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1
(.I0(active_cnt[26]),
.I1(active_cnt[24]),
.I2(active_cnt[25]),
.I3(cmd_push_3),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair119" *)
LUT5 #(
.INIT(32'h6AAAAAA9))
\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2
(.I0(active_cnt[27]),
.I1(active_cnt[26]),
.I2(cmd_push_3),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[24]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[24]_i_1__0_n_0 ),
.Q(active_cnt[24]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[25]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[25]_i_1_n_0 ),
.Q(active_cnt[25]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[26]_i_1_n_0 ),
.Q(active_cnt[26]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[27]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_13 ),
.D(\gen_multi_thread.gen_thread_loop[3].active_cnt[27]_i_2_n_0 ),
.Q(active_cnt[27]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[36]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[37]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[38]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[39]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[40]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[41]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[42]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[43]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[44]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg[36]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[45]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[46]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_id_reg[47]
(.C(aclk),
.CE(cmd_push_3),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.R(SR));
LUT6 #(
.INIT(64'h004400440F440044))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_1
(.I0(\m_ready_d_reg[1] ),
.I1(aid_match_30),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(cmd_push_3));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4
(.I0(active_cnt[24]),
.I1(active_cnt[25]),
.I2(active_cnt[27]),
.I3(active_cnt[26]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair132" *)
LUT3 #(
.INIT(8'h02))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFEFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair128" *)
LUT5 #(
.INIT(32'h0001FFFF))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7
(.I0(active_cnt[18]),
.I1(active_cnt[19]),
.I2(active_cnt[17]),
.I3(active_cnt[16]),
.I4(aid_match_20),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair115" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8
(.I0(aid_match_10),
.I1(active_cnt[10]),
.I2(active_cnt[11]),
.I3(active_cnt[9]),
.I4(active_cnt[8]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair124" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9
(.I0(aid_match_30),
.I1(active_cnt[26]),
.I2(active_cnt[27]),
.I3(active_cnt[25]),
.I4(active_cnt[24]),
.O(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[24]
(.C(aclk),
.CE(cmd_push_3),
.D(st_aa_awtarget_enc),
.Q(active_target[24]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[3].active_target_reg[25]
(.C(aclk),
.CE(cmd_push_3),
.D(D),
.Q(active_target[25]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0
(.I0(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1
(.I0(active_cnt[34]),
.I1(active_cnt[32]),
.I2(active_cnt[33]),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair120" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2
(.I0(active_cnt[35]),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair114" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[32]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[32]_i_1__0_n_0 ),
.Q(active_cnt[32]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[33]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[33]_i_1_n_0 ),
.Q(active_cnt[33]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[34]_i_1_n_0 ),
.Q(active_cnt[34]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[35]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_12 ),
.D(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_2_n_0 ),
.Q(active_cnt[35]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[48]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[49]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[50]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[51]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[52]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[53]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[54]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[55]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[56]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[57]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[58]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_id_reg[59]
(.C(aclk),
.CE(cmd_push_4),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ),
.O(cmd_push_4));
LUT6 #(
.INIT(64'hAFAFAFAFAFACAFAF))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair127" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0
(.I0(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ),
.I1(active_cnt[34]),
.I2(active_cnt[35]),
.I3(active_cnt[33]),
.I4(active_cnt[32]),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair113" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4
(.I0(aid_match_00),
.I1(active_cnt[2]),
.I2(active_cnt[3]),
.I3(active_cnt[1]),
.I4(active_cnt[0]),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair130" *)
LUT5 #(
.INIT(32'hFFFF0001))
\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5
(.I0(active_cnt[26]),
.I1(active_cnt[27]),
.I2(active_cnt[25]),
.I3(active_cnt[24]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_5_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[32]
(.C(aclk),
.CE(cmd_push_4),
.D(st_aa_awtarget_enc),
.Q(active_target[32]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[4].active_target_reg[33]
(.C(aclk),
.CE(cmd_push_4),
.D(D),
.Q(active_target[33]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0
(.I0(active_cnt[40]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair133" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1
(.I0(active_cnt[42]),
.I1(active_cnt[40]),
.I2(active_cnt[41]),
.I3(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair117" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2
(.I0(active_cnt[43]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.I2(active_cnt[41]),
.I3(active_cnt[40]),
.I4(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair116" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3
(.I0(active_cnt[40]),
.I1(active_cnt[41]),
.I2(active_cnt[43]),
.I3(active_cnt[42]),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[40]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[40]_i_1__0_n_0 ),
.Q(active_cnt[40]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[41]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[41]_i_1_n_0 ),
.Q(active_cnt[41]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[42]_i_1_n_0 ),
.Q(active_cnt[42]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[43]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_11 ),
.D(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_2_n_0 ),
.Q(active_cnt[43]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[60]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[61]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[62]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[63]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[64]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[65]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[66]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[67]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[68]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[69]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[70]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_id_reg[71]
(.C(aclk),
.CE(cmd_push_5),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ),
.O(cmd_push_5));
LUT6 #(
.INIT(64'hFAFAFFFFFACAFFCF))
\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ),
.I4(aid_match_50),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_target[41]_i_2_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[40]
(.C(aclk),
.CE(cmd_push_5),
.D(st_aa_awtarget_enc),
.Q(active_target[40]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[5].active_target_reg[41]
(.C(aclk),
.CE(cmd_push_5),
.D(D),
.Q(active_target[41]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0
(.I0(active_cnt[48]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair134" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1
(.I0(active_cnt[50]),
.I1(active_cnt[48]),
.I2(active_cnt[49]),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair118" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2
(.I0(active_cnt[51]),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.I2(active_cnt[49]),
.I3(active_cnt[48]),
.I4(active_cnt[50]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3
(.I0(active_cnt[51]),
.I1(active_cnt[50]),
.I2(active_cnt[48]),
.I3(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[48]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[48]_i_1__0_n_0 ),
.Q(active_cnt[48]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[49]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[49]_i_1_n_0 ),
.Q(active_cnt[49]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[50]_i_1_n_0 ),
.Q(active_cnt[50]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[51]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_10 ),
.D(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_2_n_0 ),
.Q(active_cnt[51]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[72]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[73]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[74]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[75]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[76]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[77]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[78]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[79]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[80]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[81]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[82]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_id_reg[83]
(.C(aclk),
.CE(cmd_push_6),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.R(SR));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ),
.O(cmd_push_6));
LUT6 #(
.INIT(64'hEEEEEEEEEEE0EEEE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2
(.I0(\m_ready_d_reg[1] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_6_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair121" *)
LUT5 #(
.INIT(32'h55555557))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3
(.I0(aid_match_60),
.I1(active_cnt[49]),
.I2(active_cnt[48]),
.I3(active_cnt[50]),
.I4(active_cnt[51]),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(active_cnt[51]),
.I3(active_cnt[50]),
.I4(active_cnt[48]),
.I5(active_cnt[49]),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFE0000))
\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5
(.I0(active_cnt[32]),
.I1(active_cnt[33]),
.I2(active_cnt[35]),
.I3(active_cnt[34]),
.I4(aid_match_40),
.I5(\gen_multi_thread.gen_thread_loop[4].active_target[33]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_5_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[48]
(.C(aclk),
.CE(cmd_push_6),
.D(st_aa_awtarget_enc),
.Q(active_target[48]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[6].active_target_reg[49]
(.C(aclk),
.CE(cmd_push_6),
.D(D),
.Q(active_target[49]),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0
(.I0(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair137" *)
LUT3 #(
.INIT(8'h96))
\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT4 #(
.INIT(16'hA96A))
\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1
(.I0(active_cnt[58]),
.I1(active_cnt[56]),
.I2(active_cnt[57]),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair131" *)
LUT5 #(
.INIT(32'h9AAAAAA6))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2
(.I0(active_cnt[59]),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.I2(active_cnt[57]),
.I3(active_cnt[56]),
.I4(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT4 #(
.INIT(16'h0001))
\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[56]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[56]_i_1__0_n_0 ),
.Q(active_cnt[56]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[57]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[57]_i_1_n_0 ),
.Q(active_cnt[57]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[58]_i_1_n_0 ),
.Q(active_cnt[58]),
.R(SR));
FDRE #(
.INIT(1'b0))
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[59]
(.C(aclk),
.CE(\gen_multi_thread.arbiter_resp_inst_n_9 ),
.D(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_2_n_0 ),
.Q(active_cnt[59]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[84]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[85]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[86]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[87]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[88]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[89]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[90]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [0]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[91]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [1]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[92]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 [2]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[93]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[94]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_id_reg[95]
(.C(aclk),
.CE(cmd_push_7),
.D(\s_axi_awaddr[31] [11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.R(SR));
LUT3 #(
.INIT(8'h02))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ),
.I1(\s_axi_awaddr[31] [17]),
.I2(\s_axi_awaddr[31] [20]),
.O(st_aa_awtarget_enc));
LUT6 #(
.INIT(64'h0000000000000002))
\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ),
.I2(\s_axi_awaddr[31] [19]),
.I3(\s_axi_awaddr[31] [15]),
.I4(\s_axi_awaddr[31] [12]),
.I5(\s_axi_awaddr[31] [23]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[56]_i_2_n_0 ));
LUT1 #(
.INIT(2'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_1
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ),
.O(cmd_push_7));
LUT4 #(
.INIT(16'hFFFE))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_10
(.I0(\s_axi_awaddr[31] [14]),
.I1(\s_axi_awaddr[31] [25]),
.I2(\s_axi_awaddr[31] [21]),
.I3(\s_axi_awaddr[31] [22]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_1 ));
LUT6 #(
.INIT(64'h0000000000000100))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_11
(.I0(\s_axi_awaddr[31] [24]),
.I1(\s_axi_awaddr[31] [27]),
.I2(\s_axi_awaddr[31] [13]),
.I3(\s_axi_awaddr[31] [26]),
.I4(\s_axi_awaddr[31] [18]),
.I5(\s_axi_awaddr[31] [16]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target_reg[56]_0 ));
LUT2 #(
.INIT(4'h1))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_2__0
(.I0(st_aa_awtarget_enc),
.I1(st_aa_awtarget_hot),
.O(D));
LUT6 #(
.INIT(64'hFFFFFFFF0000FFEF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_5_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I5(\m_ready_d_reg[1] ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF0001))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5
(.I0(active_cnt[34]),
.I1(active_cnt[35]),
.I2(active_cnt[33]),
.I3(active_cnt[32]),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_3_n_0 ),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_5_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFD))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6
(.I0(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(active_cnt[58]),
.I3(active_cnt[59]),
.I4(active_cnt[57]),
.I5(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_6_n_0 ));
LUT4 #(
.INIT(16'hEFFF))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_9_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_7_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair125" *)
LUT5 #(
.INIT(32'hAAAAAAA8))
\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8
(.I0(aid_match_70),
.I1(active_cnt[58]),
.I2(active_cnt[59]),
.I3(active_cnt[57]),
.I4(active_cnt[56]),
.O(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[56]
(.C(aclk),
.CE(cmd_push_7),
.D(st_aa_awtarget_enc),
.Q(active_target[56]),
.R(SR));
FDRE \gen_multi_thread.gen_thread_loop[7].active_target_reg[57]
(.C(aclk),
.CE(cmd_push_7),
.D(D),
.Q(active_target[57]),
.R(SR));
LUT5 #(
.INIT(32'h0000F100))
\gen_no_arbiter.s_ready_i[0]_i_10
(.I0(active_target[41]),
.I1(st_aa_awtarget_hot),
.I2(active_target[40]),
.I3(aid_match_50),
.I4(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_10_n_0 ));
LUT5 #(
.INIT(32'h22220002))
\gen_no_arbiter.s_ready_i[0]_i_11__0
(.I0(aid_match_20),
.I1(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I2(active_target[17]),
.I3(st_aa_awtarget_hot),
.I4(active_target[16]),
.O(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_12
(.I0(active_target[56]),
.I1(st_aa_awtarget_hot),
.I2(active_target[57]),
.O(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair139" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_13__0
(.I0(active_target[8]),
.I1(st_aa_awtarget_hot),
.I2(active_target[9]),
.O(\gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ));
LUT5 #(
.INIT(32'h44440004))
\gen_no_arbiter.s_ready_i[0]_i_14
(.I0(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I1(aid_match_00),
.I2(active_target[1]),
.I3(st_aa_awtarget_hot),
.I4(active_target[0]),
.O(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ));
LUT5 #(
.INIT(32'h44440004))
\gen_no_arbiter.s_ready_i[0]_i_15
(.I0(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I1(aid_match_30),
.I2(active_target[25]),
.I3(st_aa_awtarget_hot),
.I4(active_target[24]),
.O(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_16
(.I0(active_target[32]),
.I1(aid_match_40),
.I2(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.I3(active_target[8]),
.I4(aid_match_10),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_16_n_0 ));
LUT6 #(
.INIT(64'hFBFBFBFBFB00FBFB))
\gen_no_arbiter.s_ready_i[0]_i_17
(.I0(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I1(aid_match_50),
.I2(active_target[40]),
.I3(active_target[24]),
.I4(aid_match_30),
.I5(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ));
LUT6 #(
.INIT(64'h0404040404FF0404))
\gen_no_arbiter.s_ready_i[0]_i_18
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I1(aid_match_20),
.I2(active_target[16]),
.I3(active_target[0]),
.I4(aid_match_00),
.I5(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFE0000))
\gen_no_arbiter.s_ready_i[0]_i_19
(.I0(active_cnt[56]),
.I1(active_cnt[57]),
.I2(active_cnt[59]),
.I3(active_cnt[58]),
.I4(aid_match_70),
.I5(active_target[56]),
.O(\gen_no_arbiter.s_ready_i[0]_i_19_n_0 ));
LUT6 #(
.INIT(64'h4040FF4040404040))
\gen_no_arbiter.s_ready_i[0]_i_20
(.I0(\gen_multi_thread.gen_thread_loop[2].active_cnt[19]_i_3_n_0 ),
.I1(aid_match_20),
.I2(active_target[17]),
.I3(aid_match_00),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_4_n_0 ),
.I5(active_target[1]),
.O(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ));
LUT6 #(
.INIT(64'h2020FF2020202020))
\gen_no_arbiter.s_ready_i[0]_i_21
(.I0(aid_match_40),
.I1(\gen_multi_thread.gen_thread_loop[4].active_cnt[35]_i_3_n_0 ),
.I2(active_target[33]),
.I3(aid_match_70),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt[59]_i_4_n_0 ),
.I5(active_target[57]),
.O(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ));
LUT6 #(
.INIT(64'hDFDF00DFDFDFDFDF))
\gen_no_arbiter.s_ready_i[0]_i_22
(.I0(active_target[41]),
.I1(\gen_multi_thread.gen_thread_loop[5].active_cnt[43]_i_3_n_0 ),
.I2(aid_match_50),
.I3(aid_match_10),
.I4(\gen_multi_thread.gen_thread_loop[1].active_target[9]_i_3_n_0 ),
.I5(active_target[9]),
.O(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ));
LUT6 #(
.INIT(64'h8080FF8080808080))
\gen_no_arbiter.s_ready_i[0]_i_23
(.I0(aid_match_60),
.I1(\gen_multi_thread.gen_thread_loop[6].active_cnt[51]_i_3_n_0 ),
.I2(active_target[49]),
.I3(aid_match_30),
.I4(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_4_n_0 ),
.I5(active_target[25]),
.O(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair136" *)
LUT3 #(
.INIT(8'h01))
\gen_no_arbiter.s_ready_i[0]_i_28
(.I0(\gen_multi_thread.accept_cnt_reg [0]),
.I1(\gen_multi_thread.accept_cnt_reg [1]),
.I2(\gen_multi_thread.accept_cnt_reg [2]),
.O(\gen_no_arbiter.s_ready_i[0]_i_28_n_0 ));
LUT6 #(
.INIT(64'h000000000000DDD0))
\gen_no_arbiter.s_ready_i[0]_i_3
(.I0(\gen_multi_thread.gen_thread_loop[0].active_target[1]_i_2_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_10_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_11__0_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF22F2))
\gen_no_arbiter.s_ready_i[0]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_target[57]_i_8_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_12_n_0 ),
.I2(\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_8_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_13__0_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_14_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_15_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h0000000004040400))
\gen_no_arbiter.s_ready_i[0]_i_5
(.I0(\gen_no_arbiter.s_ready_i[0]_i_16_n_0 ),
.I1(\gen_no_arbiter.s_ready_i[0]_i_17_n_0 ),
.I2(\gen_no_arbiter.s_ready_i[0]_i_18_n_0 ),
.I3(\gen_multi_thread.gen_thread_loop[6].active_target[49]_i_3_n_0 ),
.I4(active_target[48]),
.I5(\gen_no_arbiter.s_ready_i[0]_i_19_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_5_n_0 ));
LUT6 #(
.INIT(64'hEEEEEEEEEEE0EEEE))
\gen_no_arbiter.s_ready_i[0]_i_6
(.I0(st_aa_awtarget_hot),
.I1(st_aa_awtarget_enc),
.I2(\gen_no_arbiter.s_ready_i[0]_i_20_n_0 ),
.I3(\gen_no_arbiter.s_ready_i[0]_i_21_n_0 ),
.I4(\gen_no_arbiter.s_ready_i[0]_i_22_n_0 ),
.I5(\gen_no_arbiter.s_ready_i[0]_i_23_n_0 ),
.O(\gen_no_arbiter.s_ready_i[0]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_8__0
(.I0(active_target[32]),
.I1(st_aa_awtarget_hot),
.I2(active_target[33]),
.O(\gen_no_arbiter.s_ready_i[0]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair140" *)
LUT3 #(
.INIT(8'h54))
\gen_no_arbiter.s_ready_i[0]_i_9__0
(.I0(active_target[48]),
.I1(st_aa_awtarget_hot),
.I2(active_target[49]),
.O(\gen_no_arbiter.s_ready_i[0]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(i__carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(i__carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(i__carry_i_4_n_0));
CARRY4 \p_0_out_inferred__9/i__carry
(.CI(1'b0),
.CO({p_0_out,\p_0_out_inferred__9/i__carry_n_1 ,\p_0_out_inferred__9/i__carry_n_2 ,\p_0_out_inferred__9/i__carry_n_3 }),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\NLW_p_0_out_inferred__9/i__carry_O_UNCONNECTED [3:0]),
.S({i__carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[7].active_id_reg[91]_0 ,i__carry_i_3_n_0,i__carry_i_4_n_0}));
CARRY4 p_10_out_carry
(.CI(1'b0),
.CO({p_10_out,p_10_out_carry_n_1,p_10_out_carry_n_2,p_10_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_10_out_carry_O_UNCONNECTED[3:0]),
.S({p_10_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[2].active_id_reg[31]_0 ,p_10_out_carry_i_3_n_0,p_10_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_10_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_10_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_10_out_carry_i_4_n_0));
CARRY4 p_12_out_carry
(.CI(1'b0),
.CO({p_12_out,p_12_out_carry_n_1,p_12_out_carry_n_2,p_12_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_12_out_carry_O_UNCONNECTED[3:0]),
.S({p_12_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[1].active_id_reg[19]_0 ,p_12_out_carry_i_3_n_0,p_12_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_12_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_12_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_12_out_carry_i_4_n_0));
CARRY4 p_14_out_carry
(.CI(1'b0),
.CO({p_14_out,p_14_out_carry_n_1,p_14_out_carry_n_2,p_14_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_14_out_carry_O_UNCONNECTED[3:0]),
.S({p_14_out_carry_i_1_n_0,S,p_14_out_carry_i_3_n_0,p_14_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_14_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_14_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_14_out_carry_i_4_n_0));
CARRY4 p_2_out_carry
(.CI(1'b0),
.CO({p_2_out,p_2_out_carry_n_1,p_2_out_carry_n_2,p_2_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_2_out_carry_O_UNCONNECTED[3:0]),
.S({p_2_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[6].active_id_reg[79]_0 ,p_2_out_carry_i_3_n_0,p_2_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_2_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_2_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_2_out_carry_i_4_n_0));
CARRY4 p_4_out_carry
(.CI(1'b0),
.CO({p_4_out,p_4_out_carry_n_1,p_4_out_carry_n_2,p_4_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_4_out_carry_O_UNCONNECTED[3:0]),
.S({p_4_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[5].active_id_reg[67]_0 ,p_4_out_carry_i_3_n_0,p_4_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_4_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_4_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_4_out_carry_i_4_n_0));
CARRY4 p_6_out_carry
(.CI(1'b0),
.CO({p_6_out,p_6_out_carry_n_1,p_6_out_carry_n_2,p_6_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_6_out_carry_O_UNCONNECTED[3:0]),
.S({p_6_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[4].active_id_reg[55]_0 ,p_6_out_carry_i_3_n_0,p_6_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_6_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_6_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_6_out_carry_i_4_n_0));
CARRY4 p_8_out_carry
(.CI(1'b0),
.CO({p_8_out,p_8_out_carry_n_1,p_8_out_carry_n_2,p_8_out_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_p_8_out_carry_O_UNCONNECTED[3:0]),
.S({p_8_out_carry_i_1_n_0,\gen_multi_thread.gen_thread_loop[3].active_id_reg[43]_0 ,p_8_out_carry_i_3_n_0,p_8_out_carry_i_4_n_0}));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_1
(.I0(\m_payload_i_reg[12] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [10]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [9]),
.I3(\m_payload_i_reg[11] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [11]),
.I5(\m_payload_i_reg[13] ),
.O(p_8_out_carry_i_1_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_3
(.I0(\m_payload_i_reg[6] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [4]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [3]),
.I3(\m_payload_i_reg[5] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [5]),
.I5(\m_payload_i_reg[7] ),
.O(p_8_out_carry_i_3_n_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_4
(.I0(\m_payload_i_reg[3] ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg [0]),
.I3(\m_payload_i_reg[2] ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg [2]),
.I5(\m_payload_i_reg[4] ),
.O(p_8_out_carry_i_4_n_0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter
(s_axi_awready,
m_ready_d,
\gen_multi_thread.accept_cnt_reg[3] ,
ss_wr_awvalid,
ss_aa_awready,
ss_wr_awready,
s_axi_awvalid,
aresetn_d,
aclk);
output [0:0]s_axi_awready;
output [1:0]m_ready_d;
output \gen_multi_thread.accept_cnt_reg[3] ;
output ss_wr_awvalid;
input ss_aa_awready;
input ss_wr_awready;
input [0:0]s_axi_awvalid;
input aresetn_d;
input aclk;
wire aclk;
wire aresetn_d;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire [0:0]s_axi_awready;
wire [0:0]s_axi_awvalid;
wire ss_aa_awready;
wire ss_wr_awready;
wire ss_wr_awvalid;
LUT2 #(
.INIT(4'h2))
\FSM_onehot_state[3]_i_4
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.O(ss_wr_awvalid));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'h111F))
\gen_multi_thread.gen_thread_loop[3].active_target[25]_i_2
(.I0(m_ready_d[1]),
.I1(ss_wr_awready),
.I2(m_ready_d[0]),
.I3(ss_aa_awready),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT6 #(
.INIT(64'h0302030000000000))
\m_ready_d[0]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.I2(ss_wr_awready),
.I3(m_ready_d[0]),
.I4(ss_aa_awready),
.I5(aresetn_d),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h000000EC00000000))
\m_ready_d[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d[1]),
.I2(ss_wr_awready),
.I3(m_ready_d[0]),
.I4(ss_aa_awready),
.I5(aresetn_d),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair141" *)
LUT4 #(
.INIT(16'hEEE0))
\s_axi_awready[0]_INST_0
(.I0(ss_aa_awready),
.I1(m_ready_d[0]),
.I2(ss_wr_awready),
.I3(m_ready_d[1]),
.O(s_axi_awready));
endmodule
(* ORIG_REF_NAME = "axi_crossbar_v2_1_14_splitter" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_splitter_3
(m_ready_d,
aa_sa_awvalid,
aresetn_d,
\m_ready_d_reg[0]_0 ,
\gen_no_arbiter.m_target_hot_i_reg[1] ,
aa_mi_awtarget_hot,
\m_ready_d_reg[0]_1 ,
aclk);
output [1:0]m_ready_d;
input aa_sa_awvalid;
input aresetn_d;
input \m_ready_d_reg[0]_0 ;
input \gen_no_arbiter.m_target_hot_i_reg[1] ;
input [2:0]aa_mi_awtarget_hot;
input \m_ready_d_reg[0]_1 ;
input aclk;
wire [2:0]aa_mi_awtarget_hot;
wire aa_sa_awvalid;
wire aclk;
wire aresetn_d;
wire \gen_no_arbiter.m_target_hot_i_reg[1] ;
wire [1:0]m_ready_d;
wire \m_ready_d[0]_i_1_n_0 ;
wire \m_ready_d[1]_i_1_n_0 ;
wire \m_ready_d_reg[0]_0 ;
wire \m_ready_d_reg[0]_1 ;
LUT6 #(
.INIT(64'h00000000EEEEEEEC))
\m_ready_d[0]_i_1
(.I0(aa_sa_awvalid),
.I1(m_ready_d[0]),
.I2(aa_mi_awtarget_hot[2]),
.I3(aa_mi_awtarget_hot[1]),
.I4(aa_mi_awtarget_hot[0]),
.I5(\m_ready_d_reg[0]_1 ),
.O(\m_ready_d[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E0))
\m_ready_d[1]_i_1
(.I0(aa_sa_awvalid),
.I1(m_ready_d[1]),
.I2(aresetn_d),
.I3(\m_ready_d_reg[0]_0 ),
.I4(\gen_no_arbiter.m_target_hot_i_reg[1] ),
.O(\m_ready_d[1]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[0]_i_1_n_0 ),
.Q(m_ready_d[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\m_ready_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_ready_d[1]_i_1_n_0 ),
.Q(m_ready_d[1]),
.R(1'b0));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_wdata_router
(ss_wr_awready,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlast,
m_axi_wready,
p_14_in,
ss_wr_awvalid);
output ss_wr_awready;
output [1:0]m_axi_wvalid;
output \gen_axi.write_cs_reg[1] ;
output [0:0]s_axi_wready;
input [0:0]st_aa_awtarget_enc;
input aclk;
input [0:0]D;
input [0:0]SR;
input [0:0]st_aa_awtarget_hot;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wvalid;
input [0:0]\gen_axi.write_cs_reg[1]_0 ;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
input p_14_in;
input ss_wr_awvalid;
wire [0:0]D;
wire [0:0]SR;
wire aclk;
wire \gen_axi.write_cs_reg[1] ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire p_14_in;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire ss_wr_awready;
wire ss_wr_awvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo wrouter_aw_fifo
(.D(D),
.SR(SR),
.aclk(aclk),
.\gen_axi.write_cs_reg[1] (\gen_axi.write_cs_reg[1] ),
.\gen_axi.write_cs_reg[1]_0 (\gen_axi.write_cs_reg[1]_0 ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.m_ready_d(m_ready_d),
.p_14_in(p_14_in),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg_0(ss_wr_awready),
.ss_wr_awvalid(ss_wr_awvalid),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_axic_reg_srl_fifo
(s_ready_i_reg_0,
m_axi_wvalid,
\gen_axi.write_cs_reg[1] ,
s_axi_wready,
st_aa_awtarget_enc,
aclk,
D,
SR,
st_aa_awtarget_hot,
m_ready_d,
s_axi_awvalid,
s_axi_wvalid,
\gen_axi.write_cs_reg[1]_0 ,
s_axi_wlast,
m_axi_wready,
p_14_in,
ss_wr_awvalid);
output s_ready_i_reg_0;
output [1:0]m_axi_wvalid;
output \gen_axi.write_cs_reg[1] ;
output [0:0]s_axi_wready;
input [0:0]st_aa_awtarget_enc;
input aclk;
input [0:0]D;
input [0:0]SR;
input [0:0]st_aa_awtarget_hot;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wvalid;
input [0:0]\gen_axi.write_cs_reg[1]_0 ;
input [0:0]s_axi_wlast;
input [1:0]m_axi_wready;
input p_14_in;
input ss_wr_awvalid;
wire \/FSM_onehot_state[0]_i_1_n_0 ;
wire \/FSM_onehot_state[1]_i_1_n_0 ;
wire \/FSM_onehot_state[2]_i_1_n_0 ;
wire \/FSM_onehot_state[3]_i_2_n_0 ;
wire [0:0]D;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[2] ;
(* RTL_KEEP = "yes" *) wire \FSM_onehot_state_reg_n_0_[3] ;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire [2:0]fifoaddr;
wire \gen_axi.write_cs_reg[1] ;
wire [0:0]\gen_axi.write_cs_reg[1]_0 ;
wire \gen_rep[0].fifoaddr[0]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[1]_i_1_n_0 ;
wire \gen_rep[0].fifoaddr[2]_i_1_n_0 ;
wire \gen_srls[0].gen_rep[0].srl_nx1_n_0 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_1 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_2 ;
wire \gen_srls[0].gen_rep[1].srl_nx1_n_3 ;
wire load_s1;
wire m_avalid;
wire [1:0]m_axi_wready;
wire [1:0]m_axi_wvalid;
wire [0:0]m_ready_d;
wire m_valid_i;
wire m_valid_i_i_1_n_0;
wire p_0_in5_out;
(* RTL_KEEP = "yes" *) wire p_0_in8_in;
wire p_14_in;
(* RTL_KEEP = "yes" *) wire p_9_in;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [0:0]s_axi_wvalid;
wire s_ready_i_i_1__2_n_0;
wire s_ready_i_i_2_n_0;
wire s_ready_i_reg_0;
wire ss_wr_awvalid;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire \storage_data1[0]_i_1_n_0 ;
wire \storage_data1_reg_n_0_[0] ;
wire \storage_data1_reg_n_0_[1] ;
LUT5 #(
.INIT(32'h40440000))
\/FSM_onehot_state[0]_i_1
(.I0(p_9_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(m_ready_d),
.I3(s_axi_awvalid),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h20202F20))
\/FSM_onehot_state[1]_i_1
(.I0(s_axi_awvalid),
.I1(m_ready_d),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB0B0B0BF))
\/FSM_onehot_state[2]_i_1
(.I0(m_ready_d),
.I1(s_axi_awvalid),
.I2(p_9_in),
.I3(p_0_in5_out),
.I4(p_0_in8_in),
.O(\/FSM_onehot_state[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'h00002A22))
\/FSM_onehot_state[3]_i_2
(.I0(p_0_in8_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(m_ready_d),
.I3(s_axi_awvalid),
.I4(p_9_in),
.O(\/FSM_onehot_state[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFFFFF488F488F488))
\FSM_onehot_state[3]_i_1
(.I0(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i));
LUT6 #(
.INIT(64'h0000000010000000))
\FSM_onehot_state[3]_i_5
(.I0(fifoaddr[1]),
.I1(fifoaddr[0]),
.I2(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I5(fifoaddr[2]),
.O(p_0_in5_out));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\FSM_onehot_state_reg[0]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[0]_i_1_n_0 ),
.Q(p_9_in),
.S(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[1]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[1]_i_1_n_0 ),
.Q(p_0_in8_in),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[2]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[2]_i_1_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[2] ),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\FSM_onehot_state_reg[3]
(.C(aclk),
.CE(m_valid_i),
.D(\/FSM_onehot_state[3]_i_2_n_0 ),
.Q(\FSM_onehot_state_reg_n_0_[3] ),
.R(areset_d1));
FDRE areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(SR),
.Q(areset_d1),
.R(1'b0));
LUT6 #(
.INIT(64'h0400000000000000))
\gen_axi.write_cs[1]_i_2
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(\gen_axi.write_cs_reg[1]_0 ),
.I3(s_axi_wlast),
.I4(s_axi_wvalid),
.I5(m_avalid),
.O(\gen_axi.write_cs_reg[1] ));
LUT6 #(
.INIT(64'hC133DDFF3ECC2200))
\gen_rep[0].fifoaddr[0]_i_1
(.I0(p_0_in8_in),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(s_ready_i_reg_0),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(fifoaddr[0]),
.O(\gen_rep[0].fifoaddr[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hBFD5402A))
\gen_rep[0].fifoaddr[1]_i_1
(.I0(fifoaddr[0]),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(\FSM_onehot_state_reg_n_0_[3] ),
.I3(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I4(fifoaddr[1]),
.O(\gen_rep[0].fifoaddr[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFFFF77710000888))
\gen_rep[0].fifoaddr[2]_i_1
(.I0(fifoaddr[0]),
.I1(fifoaddr[1]),
.I2(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I3(\FSM_onehot_state_reg_n_0_[3] ),
.I4(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I5(fifoaddr[2]),
.O(\gen_rep[0].fifoaddr[2]_i_1_n_0 ));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[0]_i_1_n_0 ),
.Q(fifoaddr[0]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[1]_i_1_n_0 ),
.Q(fifoaddr[1]),
.S(SR));
(* syn_keep = "1" *)
FDSE \gen_rep[0].fifoaddr_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\gen_rep[0].fifoaddr[2]_i_1_n_0 ),
.Q(fifoaddr[2]),
.S(SR));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0 \gen_srls[0].gen_rep[0].srl_nx1
(.aclk(aclk),
.fifoaddr(fifoaddr),
.push(push),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.\storage_data1_reg[0] (\gen_srls[0].gen_rep[0].srl_nx1_n_0 ));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4 \gen_srls[0].gen_rep[1].srl_nx1
(.D(D),
.aclk(aclk),
.fifoaddr(fifoaddr),
.\gen_rep[0].fifoaddr_reg[0] (\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.load_s1(load_s1),
.m_avalid(m_avalid),
.m_axi_wready(m_axi_wready),
.m_ready_d(m_ready_d),
.out0({p_0_in8_in,\FSM_onehot_state_reg_n_0_[3] }),
.p_14_in(p_14_in),
.push(push),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_ready_i_reg(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.s_ready_i_reg_0(s_ready_i_reg_0),
.st_aa_awtarget_enc(st_aa_awtarget_enc),
.st_aa_awtarget_hot(st_aa_awtarget_hot),
.\storage_data1_reg[0] (\storage_data1_reg_n_0_[0] ),
.\storage_data1_reg[1] (\gen_srls[0].gen_rep[1].srl_nx1_n_1 ),
.\storage_data1_reg[1]_0 (\storage_data1_reg_n_0_[1] ));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h1000))
\m_axi_wvalid[0]_INST_0
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(m_avalid),
.I3(s_axi_wvalid),
.O(m_axi_wvalid[0]));
(* SOFT_HLUTNM = "soft_lutpair142" *)
LUT4 #(
.INIT(16'h2000))
\m_axi_wvalid[1]_INST_0
(.I0(\storage_data1_reg_n_0_[0] ),
.I1(\storage_data1_reg_n_0_[1] ),
.I2(m_avalid),
.I3(s_axi_wvalid),
.O(m_axi_wvalid[1]));
LUT6 #(
.INIT(64'hFFFFF400F400F400))
m_valid_i_i_1
(.I0(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I1(p_0_in8_in),
.I2(p_9_in),
.I3(ss_wr_awvalid),
.I4(\FSM_onehot_state_reg_n_0_[3] ),
.I5(p_0_in5_out),
.O(m_valid_i_i_1_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(m_valid_i),
.D(m_valid_i_i_1_n_0),
.Q(m_avalid),
.R(areset_d1));
LUT6 #(
.INIT(64'h0A8A008A0A800080))
\s_axi_wready[0]_INST_0
(.I0(m_avalid),
.I1(m_axi_wready[1]),
.I2(\storage_data1_reg_n_0_[0] ),
.I3(\storage_data1_reg_n_0_[1] ),
.I4(p_14_in),
.I5(m_axi_wready[0]),
.O(s_axi_wready));
LUT6 #(
.INIT(64'hFEFFFFFFAAAAAAAA))
s_ready_i_i_1__2
(.I0(s_ready_i_i_2_n_0),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_2 ),
.I2(fifoaddr[0]),
.I3(fifoaddr[1]),
.I4(fifoaddr[2]),
.I5(s_ready_i_reg_0),
.O(s_ready_i_i_1__2_n_0));
LUT3 #(
.INIT(8'hEA))
s_ready_i_i_2
(.I0(areset_d1),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(\FSM_onehot_state_reg_n_0_[3] ),
.O(s_ready_i_i_2_n_0));
FDRE s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(s_ready_i_reg_0),
.R(SR));
LUT5 #(
.INIT(32'hB8FFB800))
\storage_data1[0]_i_1
(.I0(\gen_srls[0].gen_rep[0].srl_nx1_n_0 ),
.I1(\FSM_onehot_state_reg_n_0_[3] ),
.I2(st_aa_awtarget_enc),
.I3(load_s1),
.I4(\storage_data1_reg_n_0_[0] ),
.O(\storage_data1[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h88888888FFC88888))
\storage_data1[1]_i_2
(.I0(\FSM_onehot_state_reg_n_0_[3] ),
.I1(\gen_srls[0].gen_rep[1].srl_nx1_n_3 ),
.I2(p_0_in8_in),
.I3(p_9_in),
.I4(s_axi_awvalid),
.I5(m_ready_d),
.O(load_s1));
FDRE \storage_data1_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\storage_data1[0]_i_1_n_0 ),
.Q(\storage_data1_reg_n_0_[0] ),
.R(1'b0));
FDRE \storage_data1_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\gen_srls[0].gen_rep[1].srl_nx1_n_1 ),
.Q(\storage_data1_reg_n_0_[1] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0
(\storage_data1_reg[0] ,
push,
st_aa_awtarget_enc,
fifoaddr,
aclk);
output \storage_data1_reg[0] ;
input push;
input [0:0]st_aa_awtarget_enc;
input [2:0]fifoaddr;
input aclk;
wire aclk;
wire [2:0]fifoaddr;
wire push;
wire [0:0]st_aa_awtarget_enc;
wire \storage_data1_reg[0] ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[0].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(st_aa_awtarget_enc),
.Q(\storage_data1_reg[0] ),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
endmodule
(* ORIG_REF_NAME = "axi_data_fifo_v2_1_12_ndeep_srl" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_data_fifo_v2_1_12_ndeep_srl__parameterized0_4
(push,
\storage_data1_reg[1] ,
s_ready_i_reg,
\gen_rep[0].fifoaddr_reg[0] ,
D,
fifoaddr,
aclk,
st_aa_awtarget_enc,
st_aa_awtarget_hot,
out0,
load_s1,
\storage_data1_reg[1]_0 ,
s_ready_i_reg_0,
m_ready_d,
s_axi_awvalid,
s_axi_wlast,
s_axi_wvalid,
m_avalid,
m_axi_wready,
p_14_in,
\storage_data1_reg[0] );
output push;
output \storage_data1_reg[1] ;
output s_ready_i_reg;
output \gen_rep[0].fifoaddr_reg[0] ;
input [0:0]D;
input [2:0]fifoaddr;
input aclk;
input [0:0]st_aa_awtarget_enc;
input [0:0]st_aa_awtarget_hot;
input [1:0]out0;
input load_s1;
input \storage_data1_reg[1]_0 ;
input s_ready_i_reg_0;
input [0:0]m_ready_d;
input [0:0]s_axi_awvalid;
input [0:0]s_axi_wlast;
input [0:0]s_axi_wvalid;
input m_avalid;
input [1:0]m_axi_wready;
input p_14_in;
input \storage_data1_reg[0] ;
wire [0:0]D;
wire \FSM_onehot_state[3]_i_6_n_0 ;
wire aclk;
wire [2:0]fifoaddr;
wire \gen_rep[0].fifoaddr_reg[0] ;
wire load_s1;
wire m_avalid;
wire [1:0]m_axi_wready;
wire [0:0]m_ready_d;
wire [1:0]out0;
wire p_14_in;
wire p_2_out;
wire push;
wire [0:0]s_axi_awvalid;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wvalid;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire [0:0]st_aa_awtarget_enc;
wire [0:0]st_aa_awtarget_hot;
wire \storage_data1_reg[0] ;
wire \storage_data1_reg[1] ;
wire \storage_data1_reg[1]_0 ;
wire \NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ;
LUT4 #(
.INIT(16'h4000))
\FSM_onehot_state[3]_i_3
(.I0(\FSM_onehot_state[3]_i_6_n_0 ),
.I1(s_axi_wlast),
.I2(s_axi_wvalid),
.I3(m_avalid),
.O(\gen_rep[0].fifoaddr_reg[0] ));
LUT5 #(
.INIT(32'hF035FF35))
\FSM_onehot_state[3]_i_6
(.I0(m_axi_wready[0]),
.I1(p_14_in),
.I2(\storage_data1_reg[1]_0 ),
.I3(\storage_data1_reg[0] ),
.I4(m_axi_wready[1]),
.O(\FSM_onehot_state[3]_i_6_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* srl_bus_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls " *)
(* srl_name = "inst/\gen_samd.crossbar_samd/gen_slave_slots[0].gen_si_write.wdata_router_w/wrouter_aw_fifo/gen_srls[0].gen_rep[1].srl_nx1/gen_primitive_shifter.gen_srls[0].srl_inst " *)
SRLC32E #(
.INIT(32'h00000000),
.IS_CLK_INVERTED(1'b0))
\gen_primitive_shifter.gen_srls[0].srl_inst
(.A({1'b0,1'b0,fifoaddr}),
.CE(push),
.CLK(aclk),
.D(D),
.Q(p_2_out),
.Q31(\NLW_gen_primitive_shifter.gen_srls[0].srl_inst_Q31_UNCONNECTED ));
LUT1 #(
.INIT(2'h1))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_1
(.I0(s_ready_i_reg),
.O(push));
LUT6 #(
.INIT(64'hFF0DFFFFFFDDFFFF))
\gen_primitive_shifter.gen_srls[0].srl_inst_i_2
(.I0(out0[1]),
.I1(\gen_rep[0].fifoaddr_reg[0] ),
.I2(s_ready_i_reg_0),
.I3(m_ready_d),
.I4(s_axi_awvalid),
.I5(out0[0]),
.O(s_ready_i_reg));
LUT6 #(
.INIT(64'hF011FFFFF0110000))
\storage_data1[1]_i_1
(.I0(st_aa_awtarget_enc),
.I1(st_aa_awtarget_hot),
.I2(p_2_out),
.I3(out0[0]),
.I4(load_s1),
.I5(\storage_data1_reg[1]_0 ),
.O(\storage_data1_reg[1] ));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
(p_80_out,
m_axi_bready,
p_74_out,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
m_axi_rvalid,
chosen_0,
s_axi_rready,
Q,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D,
E);
output p_80_out;
output [0:0]m_axi_bready;
output p_74_out;
output \m_axi_rready[0] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]chosen;
input [0:0]s_axi_bready;
input \aresetn_d_reg[1]_0 ;
input [0:0]m_axi_rvalid;
input [0:0]chosen_0;
input [0:0]s_axi_rready;
input [3:0]Q;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
input [0:0]E;
wire [13:0]D;
wire [0:0]E;
wire [3:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]chosen;
wire [0:0]chosen_0;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire p_1_in;
wire p_74_out;
wire p_80_out;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8 b_pipe
(.D(D),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.chosen(chosen),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_80_out),
.p_1_in(p_1_in),
.s_axi_bready(s_axi_bready));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9 r_pipe
(.E(E),
.Q(Q),
.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.chosen_0(chosen_0),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[0] (\m_axi_rready[0] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.m_valid_i_reg_0(p_74_out),
.p_1_in(p_1_in),
.s_axi_rready(s_axi_rready));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_1
(p_60_out,
m_axi_bready,
p_1_in,
p_54_out,
\m_axi_rready[1] ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ,
s_axi_bresp,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\aresetn_d_reg[1] ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
chosen,
\aresetn_d_reg[1]_1 ,
Q,
\m_payload_i_reg[12] ,
p_38_out,
\m_payload_i_reg[1] ,
s_axi_rready,
chosen_0,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ,
\m_payload_i_reg[32] ,
p_32_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
D);
output p_60_out;
output [0:0]m_axi_bready;
output p_1_in;
output p_54_out;
output \m_axi_rready[1] ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_multi_thread.accept_cnt_reg[3] ;
output [4:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
output [1:0]s_axi_bresp;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]s_axi_rresp;
output [19:0]s_axi_rdata;
output \gen_master_slots[1].r_issuing_cnt_reg[11] ;
output \aresetn_d_reg[1] ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [1:0]chosen;
input \aresetn_d_reg[1]_1 ;
input [3:0]Q;
input [9:0]\m_payload_i_reg[12] ;
input p_38_out;
input [1:0]\m_payload_i_reg[1] ;
input [0:0]s_axi_rready;
input [1:0]chosen_0;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
input [20:0]\m_payload_i_reg[32] ;
input p_32_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [13:0]D;
wire [13:0]D;
wire [3:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [1:0]chosen;
wire [1:0]chosen_0;
wire \gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
wire [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire [9:0]\m_payload_i_reg[12] ;
wire [1:0]\m_payload_i_reg[1] ;
wire [20:0]\m_payload_i_reg[32] ;
wire p_1_in;
wire p_32_out;
wire p_38_out;
wire p_54_out;
wire p_60_out;
wire [4:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [19:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6 b_pipe
(.D(D),
.Q(Q),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1] (\aresetn_d_reg[1] ),
.\aresetn_d_reg[1]_0 (\aresetn_d_reg[1]_0 ),
.\aresetn_d_reg[1]_1 (\aresetn_d_reg[1]_1 ),
.chosen(chosen),
.\gen_multi_thread.accept_cnt_reg[3] (\gen_multi_thread.accept_cnt_reg[3] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.\m_payload_i_reg[0]_0 (p_60_out),
.\m_payload_i_reg[12]_0 (\m_payload_i_reg[12] ),
.\m_payload_i_reg[1]_0 (\m_payload_i_reg[1] ),
.p_1_in(p_1_in),
.p_38_out(p_38_out),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7 r_pipe
(.aclk(aclk),
.\aresetn_d_reg[1] (\aresetn_d_reg[1]_0 ),
.chosen_0(chosen_0),
.\gen_master_slots[1].r_issuing_cnt_reg[11] (\gen_master_slots[1].r_issuing_cnt_reg[11] ),
.\gen_master_slots[1].r_issuing_cnt_reg[11]_0 (\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.\m_axi_rready[1] (\m_axi_rready[1] ),
.m_axi_rresp(m_axi_rresp),
.m_axi_rvalid(m_axi_rvalid),
.\m_payload_i_reg[32]_0 (\m_payload_i_reg[32] ),
.p_1_in(p_1_in),
.p_32_out(p_32_out),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_ready_i_reg_0(p_54_out));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axi_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice_2
(p_38_out,
m_valid_i_reg,
mi_bready_2,
p_32_out,
mi_rready_2,
s_ready_i_reg,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
Q,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_21_in,
chosen,
s_axi_bready,
\m_payload_i_reg[13] ,
m_valid_i_reg_0,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ,
w_issuing_cnt,
r_issuing_cnt,
st_aa_artarget_hot,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
p_15_in,
s_axi_rready,
chosen_0,
\gen_axi.s_axi_rid_i_reg[11] ,
p_17_in,
\gen_axi.s_axi_arready_i_reg ,
D,
E);
output p_38_out;
output m_valid_i_reg;
output mi_bready_2;
output p_32_out;
output mi_rready_2;
output s_ready_i_reg;
output [6:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output [4:0]Q;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output [0:0]S;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
output \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_21_in;
input [0:0]chosen;
input [0:0]s_axi_bready;
input [13:0]\m_payload_i_reg[13] ;
input m_valid_i_reg_0;
input [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
input [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
input [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
input [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
input [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
input [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
input [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
input [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
input [0:0]w_issuing_cnt;
input [0:0]r_issuing_cnt;
input [1:0]st_aa_artarget_hot;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input p_15_in;
input [0:0]s_axi_rready;
input [0:0]chosen_0;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_17_in;
input \gen_axi.s_axi_arready_i_reg ;
input [11:0]D;
input [0:0]E;
wire [11:0]D;
wire [0:0]E;
wire [4:0]Q;
wire [0:0]S;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]chosen;
wire [0:0]chosen_0;
wire \gen_axi.s_axi_arready_i_reg ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [13:0]\m_payload_i_reg[13] ;
wire m_valid_i_reg;
wire m_valid_i_reg_0;
wire mi_bready_2;
wire mi_rready_2;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire p_21_in;
wire p_32_out;
wire p_38_out;
wire [0:0]r_issuing_cnt;
wire [6:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [0:0]s_axi_rready;
wire s_ready_i_reg;
wire [1:0]st_aa_artarget_hot;
wire [0:0]w_issuing_cnt;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1 b_pipe
(.D(D),
.Q(Q),
.S(S),
.aclk(aclk),
.\aresetn_d_reg[0] (\aresetn_d_reg[0] ),
.chosen(chosen),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 (\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] (\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ),
.\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] (\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ),
.\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] (\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ),
.\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] (\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ),
.\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] (\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ),
.\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] (\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ),
.\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] (\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ),
.\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] (\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ),
.\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] (\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ),
.\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] (\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ),
.\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] (\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ),
.\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] (\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ),
.\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] (\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ),
.\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] (\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ),
.\gen_no_arbiter.m_target_hot_i_reg[2] (\gen_no_arbiter.m_target_hot_i_reg[2] ),
.\m_payload_i_reg[13]_0 (\m_payload_i_reg[13] ),
.\m_payload_i_reg[2]_0 (p_38_out),
.m_valid_i_reg_0(m_valid_i_reg),
.m_valid_i_reg_1(m_valid_i_reg_0),
.mi_bready_2(mi_bready_2),
.p_1_in(p_1_in),
.p_21_in(p_21_in),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_ready_i_reg_0(s_ready_i_reg),
.w_issuing_cnt(w_issuing_cnt));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2 r_pipe
(.E(E),
.aclk(aclk),
.\aresetn_d_reg[1] (m_valid_i_reg),
.chosen_0(chosen_0),
.\gen_axi.s_axi_arready_i_reg (\gen_axi.s_axi_arready_i_reg ),
.\gen_axi.s_axi_rid_i_reg[11] (\gen_axi.s_axi_rid_i_reg[11] ),
.\gen_master_slots[0].r_issuing_cnt_reg[0] (\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.\gen_master_slots[1].r_issuing_cnt_reg[8] (\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.\gen_master_slots[2].r_issuing_cnt_reg[16] (\gen_master_slots[2].r_issuing_cnt_reg[16] ),
.\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] (\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58]_0 ),
.\gen_no_arbiter.s_ready_i_reg[0] (\gen_no_arbiter.s_ready_i_reg[0] ),
.m_valid_i_reg_0(p_32_out),
.p_15_in(p_15_in),
.p_17_in(p_17_in),
.p_1_in(p_1_in),
.r_issuing_cnt(r_issuing_cnt),
.s_axi_rready(s_axi_rready),
.\skid_buffer_reg[34]_0 (mi_rready_2),
.st_aa_artarget_hot(st_aa_artarget_hot));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1
(\m_payload_i_reg[2]_0 ,
m_valid_i_reg_0,
mi_bready_2,
s_ready_i_reg_0,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
S,
\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ,
\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ,
\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ,
\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ,
\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ,
\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
Q,
aclk,
p_1_in,
\aresetn_d_reg[0] ,
p_21_in,
chosen,
s_axi_bready,
\m_payload_i_reg[13]_0 ,
m_valid_i_reg_1,
\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ,
\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ,
\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ,
\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ,
\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ,
\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ,
\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ,
\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ,
w_issuing_cnt,
D);
output \m_payload_i_reg[2]_0 ;
output m_valid_i_reg_0;
output mi_bready_2;
output s_ready_i_reg_0;
output [6:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output [0:0]S;
output [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
output [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
output [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
output [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
output [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
output [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
output [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output [4:0]Q;
input aclk;
input p_1_in;
input \aresetn_d_reg[0] ;
input p_21_in;
input [0:0]chosen;
input [0:0]s_axi_bready;
input [13:0]\m_payload_i_reg[13]_0 ;
input m_valid_i_reg_1;
input [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
input [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
input [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
input [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
input [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
input [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
input [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
input [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
input [0:0]w_issuing_cnt;
input [11:0]D;
wire [11:0]D;
wire [4:0]Q;
wire [0:0]S;
wire aclk;
wire \aresetn_d_reg[0] ;
wire [0:0]chosen;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire [2:0]\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] ;
wire [0:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire [2:0]\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ;
wire [13:0]\m_payload_i_reg[13]_0 ;
wire \m_payload_i_reg[2]_0 ;
wire m_valid_i_i_1__1_n_0;
wire m_valid_i_reg_0;
wire m_valid_i_reg_1;
wire mi_bready_2;
wire p_1_in;
wire p_21_in;
wire [6:0]s_axi_bid;
wire \s_axi_bid[6]_INST_0_i_1_n_0 ;
wire \s_axi_bid[7]_INST_0_i_1_n_0 ;
wire \s_axi_bid[8]_INST_0_i_1_n_0 ;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__5_n_0;
wire s_ready_i_reg_0;
wire [35:24]st_mr_bid;
wire [0:0]w_issuing_cnt;
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0] ),
.Q(s_ready_i_reg_0),
.R(1'b0));
LUT4 #(
.INIT(16'h2AAA))
\gen_no_arbiter.s_ready_i[0]_i_27
(.I0(w_issuing_cnt),
.I1(s_axi_bready),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT6 #(
.INIT(64'h0000066006600000))
i__carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [1]),
.I2(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[7].active_id_reg[92] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__0
(.I0(\m_payload_i_reg[2]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[8]),
.Q(st_mr_bid[32]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[9]),
.Q(st_mr_bid[33]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[10]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[11]),
.Q(st_mr_bid[35]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[0]),
.Q(st_mr_bid[24]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[1]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[2]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[3]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[4]),
.Q(st_mr_bid[28]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[5]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[6]),
.Q(st_mr_bid[30]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen40_in ),
.D(D[7]),
.Q(st_mr_bid[31]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__1
(.I0(p_21_in),
.I1(mi_bready_2),
.I2(s_axi_bready),
.I3(\m_payload_i_reg[2]_0 ),
.I4(chosen),
.O(m_valid_i_i_1__1_n_0));
LUT1 #(
.INIT(2'h1))
m_valid_i_i_1__5
(.I0(s_ready_i_reg_0),
.O(m_valid_i_reg_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__1_n_0),
.Q(\m_payload_i_reg[2]_0 ),
.R(m_valid_i_reg_0));
LUT6 #(
.INIT(64'h0000066006600000))
p_10_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [1]),
.I2(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[2].active_id_reg[32] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[2].active_cnt_reg[18] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_12_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [1]),
.I2(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[1].active_id_reg[20] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[1].active_cnt_reg[10] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_14_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [1]),
.I2(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[0].active_id_reg[8] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(S));
LUT6 #(
.INIT(64'h0000066006600000))
p_2_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [1]),
.I2(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[6].active_id_reg[80] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[6].active_cnt_reg[50] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_4_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [1]),
.I2(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[5].active_id_reg[68] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[5].active_cnt_reg[42] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_6_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [1]),
.I2(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[4].active_id_reg[56] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[4].active_cnt_reg[34] ));
LUT6 #(
.INIT(64'h0000066006600000))
p_8_out_carry_i_2
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.I1(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [1]),
.I2(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [0]),
.I3(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.I4(\gen_multi_thread.gen_thread_loop[3].active_id_reg[44] [2]),
.I5(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(\gen_multi_thread.gen_thread_loop[3].active_cnt_reg[26] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[0]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.O(s_axi_bid[0]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[0]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [0]),
.I1(st_mr_bid[24]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [7]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[11]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.O(s_axi_bid[6]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[11]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [6]),
.I1(st_mr_bid[35]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [13]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[4]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.O(s_axi_bid[1]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[4]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [1]),
.I1(st_mr_bid[28]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [8]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[6]_INST_0
(.I0(\s_axi_bid[6]_INST_0_i_1_n_0 ),
.O(s_axi_bid[2]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[6]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [2]),
.I1(st_mr_bid[30]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [9]),
.O(\s_axi_bid[6]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[7]_INST_0
(.I0(\s_axi_bid[7]_INST_0_i_1_n_0 ),
.O(s_axi_bid[3]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[7]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [3]),
.I1(st_mr_bid[31]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [10]),
.O(\s_axi_bid[7]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[8]_INST_0
(.I0(\s_axi_bid[8]_INST_0_i_1_n_0 ),
.O(s_axi_bid[4]));
LUT6 #(
.INIT(64'hF5303030F53F3F3F))
\s_axi_bid[8]_INST_0_i_1
(.I0(st_mr_bid[32]),
.I1(\m_payload_i_reg[13]_0 [11]),
.I2(m_valid_i_reg_1),
.I3(\m_payload_i_reg[2]_0 ),
.I4(chosen),
.I5(\m_payload_i_reg[13]_0 [4]),
.O(\s_axi_bid[8]_INST_0_i_1_n_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[9]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.O(s_axi_bid[5]));
LUT6 #(
.INIT(64'hF0003555FFFF3555))
\s_axi_bid[9]_INST_0_i_1
(.I0(\m_payload_i_reg[13]_0 [5]),
.I1(st_mr_bid[33]),
.I2(\m_payload_i_reg[2]_0 ),
.I3(chosen),
.I4(m_valid_i_reg_1),
.I5(\m_payload_i_reg[13]_0 [12]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__5
(.I0(\m_payload_i_reg[2]_0 ),
.I1(p_21_in),
.I2(chosen),
.I3(s_axi_bready),
.I4(s_ready_i_reg_0),
.O(s_ready_i_i_1__5_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__5_n_0),
.Q(mi_bready_2),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_6
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
p_1_in,
\gen_no_arbiter.m_target_hot_i_reg[2] ,
\gen_multi_thread.accept_cnt_reg[3] ,
s_axi_bid,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ,
s_axi_bresp,
\aresetn_d_reg[1] ,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ,
\aresetn_d_reg[1]_0 ,
aclk,
aresetn,
m_axi_bvalid,
s_axi_bready,
chosen,
\aresetn_d_reg[1]_1 ,
Q,
\m_payload_i_reg[12]_0 ,
p_38_out,
\m_payload_i_reg[1]_0 ,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output p_1_in;
output \gen_no_arbiter.m_target_hot_i_reg[2] ;
output \gen_multi_thread.accept_cnt_reg[3] ;
output [4:0]s_axi_bid;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
output \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
output [1:0]s_axi_bresp;
output \aresetn_d_reg[1] ;
output [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
input \aresetn_d_reg[1]_0 ;
input aclk;
input aresetn;
input [0:0]m_axi_bvalid;
input [0:0]s_axi_bready;
input [1:0]chosen;
input \aresetn_d_reg[1]_1 ;
input [3:0]Q;
input [9:0]\m_payload_i_reg[12]_0 ;
input p_38_out;
input [1:0]\m_payload_i_reg[1]_0 ;
input [13:0]D;
wire [13:0]D;
wire [3:0]Q;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire \aresetn_d_reg[1]_1 ;
wire [1:0]chosen;
wire \gen_multi_thread.accept_cnt_reg[3] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ;
wire \gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ;
wire [6:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 ;
wire \gen_no_arbiter.m_target_hot_i_reg[2] ;
wire \gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i_reg[0]_0 ;
wire [9:0]\m_payload_i_reg[12]_0 ;
wire [1:0]\m_payload_i_reg[1]_0 ;
wire m_valid_i_i_1__0_n_0;
wire [1:1]p_0_in;
wire p_1_in;
wire p_38_out;
wire [4:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_ready_i_i_2__0_n_0;
wire [22:13]st_mr_bid;
wire [4:3]st_mr_bmesg;
LUT2 #(
.INIT(4'h8))
\aresetn_d[1]_i_1
(.I0(p_0_in),
.I1(aresetn),
.O(\aresetn_d_reg[1] ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(p_0_in),
.R(1'b0));
LUT6 #(
.INIT(64'h0000000700000000))
\gen_no_arbiter.s_ready_i[0]_i_26
(.I0(\gen_multi_thread.accept_cnt_reg[3] ),
.I1(s_axi_bready),
.I2(Q[2]),
.I3(Q[1]),
.I4(Q[0]),
.I5(Q[3]),
.O(\gen_no_arbiter.m_target_hot_i_reg[2] ));
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[0]),
.Q(st_mr_bmesg[3]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [4]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [5]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[12]),
.Q(st_mr_bid[22]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [6]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[1]),
.Q(st_mr_bmesg[4]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [0]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[3]),
.Q(st_mr_bid[13]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[4]),
.Q(st_mr_bid[14]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[5]),
.Q(st_mr_bid[15]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [1]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[7]),
.Q(st_mr_bid[17]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [2]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\gen_slave_slots[0].gen_si_write.si_transactor_aw/gen_multi_thread.arbiter_resp_inst/chosen4 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_4 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_1__0
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(s_axi_bready),
.I3(chosen[0]),
.I4(\m_payload_i_reg[0]_0 ),
.O(m_valid_i_i_1__0_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__0_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[10]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ),
.O(s_axi_bid[4]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[10]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [4]),
.I1(st_mr_bid[22]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [9]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_3 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT2 #(
.INIT(4'h8))
\s_axi_bid[11]_INST_0_i_2
(.I0(\m_payload_i_reg[0]_0 ),
.I1(chosen[0]),
.O(\gen_multi_thread.accept_cnt_reg[3] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[1]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ),
.O(s_axi_bid[0]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[1]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [0]),
.I1(st_mr_bid[13]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [5]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[2]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ),
.O(s_axi_bid[1]));
LUT6 #(
.INIT(64'hF0535353FF535353))
\s_axi_bid[2]_INST_0_i_1
(.I0(st_mr_bid[14]),
.I1(\m_payload_i_reg[12]_0 [1]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [6]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_0 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[3]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ),
.O(s_axi_bid[2]));
LUT6 #(
.INIT(64'hF0535353FF535353))
\s_axi_bid[3]_INST_0_i_1
(.I0(st_mr_bid[15]),
.I1(\m_payload_i_reg[12]_0 [2]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [7]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_1 ));
LUT1 #(
.INIT(2'h1))
\s_axi_bid[5]_INST_0
(.I0(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ),
.O(s_axi_bid[3]));
LUT6 #(
.INIT(64'hF0353535FF353535))
\s_axi_bid[5]_INST_0_i_1
(.I0(\m_payload_i_reg[12]_0 [3]),
.I1(st_mr_bid[17]),
.I2(\gen_multi_thread.accept_cnt_reg[3] ),
.I3(p_38_out),
.I4(chosen[1]),
.I5(\m_payload_i_reg[12]_0 [8]),
.O(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2]_2 ));
LUT6 #(
.INIT(64'h3FBFBFBF3F808080))
\s_axi_bresp[0]_INST_0
(.I0(st_mr_bmesg[3]),
.I1(chosen[0]),
.I2(\m_payload_i_reg[0]_0 ),
.I3(chosen[1]),
.I4(p_38_out),
.I5(\m_payload_i_reg[1]_0 [0]),
.O(s_axi_bresp[0]));
LUT6 #(
.INIT(64'h0CCCFAAAFAAAFAAA))
\s_axi_bresp[1]_INST_0
(.I0(\m_payload_i_reg[1]_0 [1]),
.I1(st_mr_bmesg[4]),
.I2(chosen[1]),
.I3(p_38_out),
.I4(\m_payload_i_reg[0]_0 ),
.I5(chosen[0]),
.O(s_axi_bresp[1]));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__3
(.I0(p_0_in),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_2__0
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(s_axi_bready),
.I3(chosen[0]),
.I4(\aresetn_d_reg[1]_1 ),
.O(s_ready_i_i_2__0_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_2__0_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1_8
(\m_payload_i_reg[0]_0 ,
m_axi_bready,
\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_bvalid,
chosen,
s_axi_bready,
\aresetn_d_reg[1]_0 ,
D);
output \m_payload_i_reg[0]_0 ;
output [0:0]m_axi_bready;
output [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_bvalid;
input [0:0]chosen;
input [0:0]s_axi_bready;
input \aresetn_d_reg[1]_0 ;
input [13:0]D;
wire [13:0]D;
wire aclk;
wire \aresetn_d_reg[1] ;
wire \aresetn_d_reg[1]_0 ;
wire [0:0]chosen;
wire [13:0]\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] ;
wire [0:0]m_axi_bready;
wire [0:0]m_axi_bvalid;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i_reg[0]_0 ;
wire m_valid_i_i_2_n_0;
wire p_1_in;
wire [0:0]s_axi_bready;
wire s_ready_i_i_1__4_n_0;
LUT1 #(
.INIT(2'h1))
\m_payload_i[13]_i_1__1
(.I0(\m_payload_i_reg[0]_0 ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[0]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[10]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[11]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[12]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[13]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[1]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[2]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[3]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[4]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[5]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[6]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[7]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[8]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(\m_payload_i[13]_i_1__1_n_0 ),
.D(D[9]),
.Q(\gen_multi_thread.gen_thread_loop[0].active_cnt_reg[2] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'h8BBBBBBB))
m_valid_i_i_2
(.I0(m_axi_bvalid),
.I1(m_axi_bready),
.I2(chosen),
.I3(\m_payload_i_reg[0]_0 ),
.I4(s_axi_bready),
.O(m_valid_i_i_2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_2_n_0),
.Q(\m_payload_i_reg[0]_0 ),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hB111FFFF))
s_ready_i_i_1__4
(.I0(\m_payload_i_reg[0]_0 ),
.I1(m_axi_bvalid),
.I2(chosen),
.I3(s_axi_bready),
.I4(\aresetn_d_reg[1]_0 ),
.O(s_ready_i_i_1__4_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__4_n_0),
.Q(m_axi_bready),
.R(p_1_in));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2
(m_valid_i_reg_0,
\skid_buffer_reg[34]_0 ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\gen_master_slots[2].r_issuing_cnt_reg[16] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
r_issuing_cnt,
st_aa_artarget_hot,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
p_15_in,
s_axi_rready,
chosen_0,
\gen_axi.s_axi_rid_i_reg[11] ,
p_17_in,
\gen_axi.s_axi_arready_i_reg ,
E);
output m_valid_i_reg_0;
output \skid_buffer_reg[34]_0 ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output \gen_master_slots[2].r_issuing_cnt_reg[16] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]r_issuing_cnt;
input [1:0]st_aa_artarget_hot;
input \gen_master_slots[0].r_issuing_cnt_reg[0] ;
input \gen_master_slots[1].r_issuing_cnt_reg[8] ;
input p_15_in;
input [0:0]s_axi_rready;
input [0:0]chosen_0;
input [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
input p_17_in;
input \gen_axi.s_axi_arready_i_reg ;
input [0:0]E;
wire [0:0]E;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]chosen_0;
wire \gen_axi.s_axi_arready_i_reg ;
wire [11:0]\gen_axi.s_axi_rid_i_reg[11] ;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire \gen_master_slots[2].r_issuing_cnt_reg[16] ;
wire [12:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_15_in;
wire p_17_in;
wire p_1_in;
wire [0:0]r_issuing_cnt;
wire [0:0]s_axi_rready;
wire s_ready_i0;
wire [46:34]skid_buffer;
wire \skid_buffer_reg[34]_0 ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire [1:0]st_aa_artarget_hot;
LUT6 #(
.INIT(64'h955555552AAAAAAA))
\gen_master_slots[2].r_issuing_cnt[16]_i_1
(.I0(\gen_axi.s_axi_arready_i_reg ),
.I1(s_axi_rready),
.I2(chosen_0),
.I3(m_valid_i_reg_0),
.I4(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I5(r_issuing_cnt),
.O(\gen_master_slots[2].r_issuing_cnt_reg[16] ));
LUT6 #(
.INIT(64'hFF0FF2020000F202))
\gen_no_arbiter.s_ready_i[0]_i_23__0
(.I0(r_issuing_cnt),
.I1(\gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ),
.I2(st_aa_artarget_hot[0]),
.I3(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.I4(st_aa_artarget_hot[1]),
.I5(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT4 #(
.INIT(16'h8000))
\gen_no_arbiter.s_ready_i[0]_i_25__0
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.I1(m_valid_i_reg_0),
.I2(chosen_0),
.I3(s_axi_rready),
.O(\gen_no_arbiter.s_ready_i[0]_i_25__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(p_17_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [0]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [1]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [2]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [3]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [4]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [5]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [6]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [7]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [8]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [9]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [10]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__1
(.I0(\gen_axi.s_axi_rid_i_reg[11] [11]),
.I1(\skid_buffer_reg[34]_0 ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF70FFFF))
m_valid_i_i_1__4
(.I0(s_axi_rready),
.I1(chosen_0),
.I2(m_valid_i_reg_0),
.I3(p_15_in),
.I4(\skid_buffer_reg[34]_0 ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__1
(.I0(p_15_in),
.I1(\skid_buffer_reg[34]_0 ),
.I2(s_axi_rready),
.I3(chosen_0),
.I4(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\skid_buffer_reg[34]_0 ),
.R(p_1_in));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(p_17_in),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\skid_buffer_reg[34]_0 ),
.D(\gen_axi.s_axi_rid_i_reg[11] [11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_7
(s_ready_i_reg_0,
\m_axi_rready[1] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[1].r_issuing_cnt_reg[8] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
s_axi_rresp,
s_axi_rdata,
\gen_master_slots[1].r_issuing_cnt_reg[11] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
s_axi_rready,
chosen_0,
m_axi_rvalid,
\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ,
\m_payload_i_reg[32]_0 ,
p_32_out,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata);
output s_ready_i_reg_0;
output \m_axi_rready[1] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[1].r_issuing_cnt_reg[8] ;
output [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
output [0:0]s_axi_rresp;
output [19:0]s_axi_rdata;
output \gen_master_slots[1].r_issuing_cnt_reg[11] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]s_axi_rready;
input [1:0]chosen_0;
input [0:0]m_axi_rvalid;
input [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
input [20:0]\m_payload_i_reg[32]_0 ;
input p_32_out;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [1:0]chosen_0;
wire \gen_master_slots[1].r_issuing_cnt_reg[11] ;
wire [3:0]\gen_master_slots[1].r_issuing_cnt_reg[11]_0 ;
wire \gen_master_slots[1].r_issuing_cnt_reg[8] ;
wire [25:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[1] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire [20:0]\m_payload_i_reg[32]_0 ;
wire m_valid_i0;
wire p_1_in;
wire p_1_in_0;
wire p_32_out;
wire [19:0]s_axi_rdata;
wire [0:0]s_axi_rready;
wire [0:0]s_axi_rresp;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire [68:35]st_mr_rmesg;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[1].r_issuing_cnt[11]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.I1(s_ready_i_reg_0),
.I2(chosen_0[0]),
.I3(s_axi_rready),
.O(\gen_master_slots[1].r_issuing_cnt_reg[8] ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT2 #(
.INIT(4'h8))
\gen_master_slots[1].r_issuing_cnt[11]_i_6
(.I0(s_ready_i_reg_0),
.I1(chosen_0[0]),
.O(\gen_master_slots[1].r_issuing_cnt_reg[11] ));
LUT5 #(
.INIT(32'h00000100))
\gen_no_arbiter.s_ready_i[0]_i_27__0
(.I0(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [0]),
.I1(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [1]),
.I2(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [2]),
.I3(\gen_master_slots[1].r_issuing_cnt_reg[11]_0 [3]),
.I4(\gen_master_slots[1].r_issuing_cnt_reg[8] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__3
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__0
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(m_axi_rlast),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1__0
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1__0
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1__0
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1__0
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1__0
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
LUT3 #(
.INIT(8'hD5))
\m_payload_i[46]_i_1__0
(.I0(s_ready_i_reg_0),
.I1(s_axi_rready),
.I2(chosen_0[0]),
.O(p_1_in_0));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2__0
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[1] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[12]),
.Q(st_mr_rmesg[50]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[13]),
.Q(st_mr_rmesg[51]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[14]),
.Q(st_mr_rmesg[52]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[15]),
.Q(st_mr_rmesg[53]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[16]),
.Q(st_mr_rmesg[54]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[17]),
.Q(st_mr_rmesg[55]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[18]),
.Q(st_mr_rmesg[56]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[1]),
.Q(st_mr_rmesg[39]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[21]),
.Q(st_mr_rmesg[59]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[23]),
.Q(st_mr_rmesg[61]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[24]),
.Q(st_mr_rmesg[62]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[25]),
.Q(st_mr_rmesg[63]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[26]),
.Q(st_mr_rmesg[64]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[28]),
.Q(st_mr_rmesg[66]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[29]),
.Q(st_mr_rmesg[67]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[2]),
.Q(st_mr_rmesg[40]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[30]),
.Q(st_mr_rmesg[68]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[32]),
.Q(st_mr_rmesg[35]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[3]),
.Q(st_mr_rmesg[41]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[5]),
.Q(st_mr_rmesg[43]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[7]),
.Q(st_mr_rmesg[45]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in_0),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hFF2AFFFF))
m_valid_i_i_1__3
(.I0(s_ready_i_reg_0),
.I1(s_axi_rready),
.I2(chosen_0[0]),
.I3(m_axi_rvalid),
.I4(\m_axi_rready[1] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[12]_INST_0
(.I0(st_mr_rmesg[50]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [5]),
.O(s_axi_rdata[5]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[13]_INST_0
(.I0(st_mr_rmesg[51]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [6]),
.O(s_axi_rdata[6]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[14]_INST_0
(.I0(st_mr_rmesg[52]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [7]),
.O(s_axi_rdata[7]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[15]_INST_0
(.I0(st_mr_rmesg[53]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [8]),
.O(s_axi_rdata[8]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[16]_INST_0
(.I0(st_mr_rmesg[54]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [9]),
.O(s_axi_rdata[9]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[17]_INST_0
(.I0(st_mr_rmesg[55]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [10]),
.O(s_axi_rdata[10]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[18]_INST_0
(.I0(st_mr_rmesg[56]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [11]),
.O(s_axi_rdata[11]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[1]_INST_0
(.I0(st_mr_rmesg[39]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [0]),
.O(s_axi_rdata[0]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[21]_INST_0
(.I0(st_mr_rmesg[59]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [12]),
.O(s_axi_rdata[12]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[23]_INST_0
(.I0(st_mr_rmesg[61]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [13]),
.O(s_axi_rdata[13]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[24]_INST_0
(.I0(st_mr_rmesg[62]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [14]),
.O(s_axi_rdata[14]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[25]_INST_0
(.I0(st_mr_rmesg[63]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [15]),
.O(s_axi_rdata[15]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[26]_INST_0
(.I0(st_mr_rmesg[64]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [16]),
.O(s_axi_rdata[16]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[28]_INST_0
(.I0(st_mr_rmesg[66]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [17]),
.O(s_axi_rdata[17]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[29]_INST_0
(.I0(st_mr_rmesg[67]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [18]),
.O(s_axi_rdata[18]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[2]_INST_0
(.I0(st_mr_rmesg[40]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [1]),
.O(s_axi_rdata[1]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[30]_INST_0
(.I0(st_mr_rmesg[68]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [19]),
.O(s_axi_rdata[19]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[3]_INST_0
(.I0(st_mr_rmesg[41]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [2]),
.O(s_axi_rdata[2]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[5]_INST_0
(.I0(st_mr_rmesg[43]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [3]),
.O(s_axi_rdata[3]));
LUT6 #(
.INIT(64'h2A3F3F3F2A000000))
\s_axi_rdata[7]_INST_0
(.I0(st_mr_rmesg[45]),
.I1(chosen_0[1]),
.I2(p_32_out),
.I3(chosen_0[0]),
.I4(s_ready_i_reg_0),
.I5(\m_payload_i_reg[32]_0 [4]),
.O(s_axi_rdata[4]));
LUT6 #(
.INIT(64'h0FFFACCCACCCACCC))
\s_axi_rresp[0]_INST_0
(.I0(st_mr_rmesg[35]),
.I1(\m_payload_i_reg[32]_0 [20]),
.I2(s_ready_i_reg_0),
.I3(chosen_0[0]),
.I4(p_32_out),
.I5(chosen_0[1]),
.O(s_axi_rresp));
LUT5 #(
.INIT(32'hFF4F4F4F))
s_ready_i_i_1__0
(.I0(m_axi_rvalid),
.I1(\m_axi_rready[1] ),
.I2(s_ready_i_reg_0),
.I3(s_axi_rready),
.I4(chosen_0[0]),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\m_axi_rready[1] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[1] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_13_axic_register_slice" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2_9
(m_valid_i_reg_0,
\m_axi_rready[0] ,
\gen_no_arbiter.s_ready_i_reg[0] ,
\gen_master_slots[0].r_issuing_cnt_reg[0] ,
\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ,
\aresetn_d_reg[1] ,
aclk,
p_1_in,
m_axi_rvalid,
chosen_0,
s_axi_rready,
Q,
m_axi_rid,
m_axi_rlast,
m_axi_rresp,
m_axi_rdata,
E);
output m_valid_i_reg_0;
output \m_axi_rready[0] ;
output \gen_no_arbiter.s_ready_i_reg[0] ;
output \gen_master_slots[0].r_issuing_cnt_reg[0] ;
output [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
input \aresetn_d_reg[1] ;
input aclk;
input p_1_in;
input [0:0]m_axi_rvalid;
input [0:0]chosen_0;
input [0:0]s_axi_rready;
input [3:0]Q;
input [11:0]m_axi_rid;
input [0:0]m_axi_rlast;
input [1:0]m_axi_rresp;
input [31:0]m_axi_rdata;
input [0:0]E;
wire [0:0]E;
wire [3:0]Q;
wire aclk;
wire \aresetn_d_reg[1] ;
wire [0:0]chosen_0;
wire \gen_master_slots[0].r_issuing_cnt_reg[0] ;
wire [46:0]\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] ;
wire \gen_no_arbiter.s_ready_i_reg[0] ;
wire [31:0]m_axi_rdata;
wire [11:0]m_axi_rid;
wire [0:0]m_axi_rlast;
wire \m_axi_rready[0] ;
wire [1:0]m_axi_rresp;
wire [0:0]m_axi_rvalid;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire p_1_in;
wire [0:0]s_axi_rready;
wire s_ready_i0;
wire [46:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[37] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[40] ;
wire \skid_buffer_reg_n_0_[41] ;
wire \skid_buffer_reg_n_0_[42] ;
wire \skid_buffer_reg_n_0_[43] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
LUT4 #(
.INIT(16'h8000))
\gen_master_slots[0].r_issuing_cnt[3]_i_4
(.I0(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.I1(s_axi_rready),
.I2(m_valid_i_reg_0),
.I3(chosen_0),
.O(\gen_master_slots[0].r_issuing_cnt_reg[0] ));
LUT5 #(
.INIT(32'h00000100))
\gen_no_arbiter.s_ready_i[0]_i_26__0
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.I3(Q[3]),
.I4(\gen_master_slots[0].r_issuing_cnt_reg[0] ),
.O(\gen_no_arbiter.s_ready_i_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(m_axi_rdata[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(m_axi_rdata[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(m_axi_rdata[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(m_axi_rdata[12]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__2
(.I0(m_axi_rdata[13]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(m_axi_rdata[14]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(m_axi_rdata[15]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(m_axi_rdata[16]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(m_axi_rdata[17]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(m_axi_rdata[18]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(m_axi_rdata[19]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(m_axi_rdata[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(m_axi_rdata[20]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(m_axi_rdata[21]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(m_axi_rdata[22]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(m_axi_rdata[23]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(m_axi_rdata[24]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(m_axi_rdata[25]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(m_axi_rdata[26]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(m_axi_rdata[27]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(m_axi_rdata[28]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(m_axi_rdata[29]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(m_axi_rdata[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(m_axi_rdata[30]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1
(.I0(m_axi_rdata[31]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(m_axi_rresp[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(m_axi_rresp[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(m_axi_rlast),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1
(.I0(m_axi_rid[0]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(m_axi_rid[1]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[37]_i_1
(.I0(m_axi_rid[2]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[37] ),
.O(skid_buffer[37]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(m_axi_rid[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(m_axi_rid[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(m_axi_rdata[3]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[40]_i_1
(.I0(m_axi_rid[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[40] ),
.O(skid_buffer[40]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[41]_i_1
(.I0(m_axi_rid[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[41] ),
.O(skid_buffer[41]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[42]_i_1
(.I0(m_axi_rid[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[42] ),
.O(skid_buffer[42]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[43]_i_1
(.I0(m_axi_rid[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[43] ),
.O(skid_buffer[43]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(m_axi_rid[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(m_axi_rid[10]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_2
(.I0(m_axi_rid[11]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(m_axi_rdata[4]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(m_axi_rdata[5]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(m_axi_rdata[6]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(m_axi_rdata[7]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(m_axi_rdata[8]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(m_axi_rdata[9]),
.I1(\m_axi_rready[0] ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [36]),
.R(1'b0));
FDRE \m_payload_i_reg[37]
(.C(aclk),
.CE(E),
.D(skid_buffer[37]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [37]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [38]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [39]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[40]
(.C(aclk),
.CE(E),
.D(skid_buffer[40]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [40]),
.R(1'b0));
FDRE \m_payload_i_reg[41]
(.C(aclk),
.CE(E),
.D(skid_buffer[41]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [41]),
.R(1'b0));
FDRE \m_payload_i_reg[42]
(.C(aclk),
.CE(E),
.D(skid_buffer[42]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [42]),
.R(1'b0));
FDRE \m_payload_i_reg[43]
(.C(aclk),
.CE(E),
.D(skid_buffer[43]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [43]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [44]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [45]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [46]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(\gen_multi_thread.gen_thread_loop[7].active_cnt_reg[58] [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hFF4CFFFF))
m_valid_i_i_1__2
(.I0(chosen_0),
.I1(m_valid_i_reg_0),
.I2(s_axi_rready),
.I3(m_axi_rvalid),
.I4(\m_axi_rready[0] ),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1] ));
LUT5 #(
.INIT(32'hF4FF44FF))
s_ready_i_i_1
(.I0(m_axi_rvalid),
.I1(\m_axi_rready[0] ),
.I2(chosen_0),
.I3(m_valid_i_reg_0),
.I4(s_axi_rready),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(\m_axi_rready[0] ),
.R(p_1_in));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rresp[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rlast),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[37]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[2]),
.Q(\skid_buffer_reg_n_0_[37] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[3]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[4]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[40]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[5]),
.Q(\skid_buffer_reg_n_0_[40] ),
.R(1'b0));
FDRE \skid_buffer_reg[41]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[6]),
.Q(\skid_buffer_reg_n_0_[41] ),
.R(1'b0));
FDRE \skid_buffer_reg[42]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[7]),
.Q(\skid_buffer_reg_n_0_[42] ),
.R(1'b0));
FDRE \skid_buffer_reg[43]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[8]),
.Q(\skid_buffer_reg_n_0_[43] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[9]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[10]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rid[11]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\m_axi_rready[0] ),
.D(m_axi_rdata[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "zynq_design_1_xbar_0,axi_crossbar_v2_1_14_axi_crossbar,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_crossbar_v2_1_14_axi_crossbar,Vivado 2017.2" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID" *) input [11:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID" *) input [0:0]s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY" *) output [0:0]s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST" *) input [0:0]s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID" *) input [0:0]s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY" *) output [0:0]s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID" *) output [11:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID" *) output [0:0]s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY" *) input [0:0]s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID" *) input [11:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID" *) input [0:0]s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY" *) output [0:0]s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID" *) output [11:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST" *) output [0:0]s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID" *) output [0:0]s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY" *) input [0:0]s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI AWID [11:0] [23:12]" *) output [23:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI AWADDR [31:0] [63:32]" *) output [63:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLEN [7:0] [15:8]" *) output [15:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWSIZE [2:0] [5:3]" *) output [5:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI AWBURST [1:0] [3:2]" *) output [3:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWLOCK [0:0] [1:1]" *) output [1:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWCACHE [3:0] [7:4]" *) output [7:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI AWPROT [2:0] [5:3]" *) output [5:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREGION [3:0] [7:4]" *) output [7:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI AWQOS [3:0] [7:4]" *) output [7:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWVALID [0:0] [1:1]" *) output [1:0]m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI AWREADY [0:0] [1:1]" *) input [1:0]m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI WDATA [31:0] [63:32]" *) output [63:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI WSTRB [3:0] [7:4]" *) output [7:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WLAST [0:0] [1:1]" *) output [1:0]m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WVALID [0:0] [1:1]" *) output [1:0]m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI WREADY [0:0] [1:1]" *) input [1:0]m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI BID [11:0] [23:12]" *) input [23:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI BRESP [1:0] [3:2]" *) input [3:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BVALID [0:0] [1:1]" *) input [1:0]m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI BREADY [0:0] [1:1]" *) output [1:0]m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI ARID [11:0] [23:12]" *) output [23:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI ARADDR [31:0] [63:32]" *) output [63:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLEN [7:0] [15:8]" *) output [15:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARSIZE [2:0] [5:3]" *) output [5:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI ARBURST [1:0] [3:2]" *) output [3:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARLOCK [0:0] [1:1]" *) output [1:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARCACHE [3:0] [7:4]" *) output [7:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 M01_AXI ARPROT [2:0] [5:3]" *) output [5:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREGION [3:0] [7:4]" *) output [7:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 M01_AXI ARQOS [3:0] [7:4]" *) output [7:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARVALID [0:0] [1:1]" *) output [1:0]m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI ARREADY [0:0] [1:1]" *) input [1:0]m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID [11:0] [11:0], xilinx.com:interface:aximm:1.0 M01_AXI RID [11:0] [23:12]" *) input [23:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA [31:0] [31:0], xilinx.com:interface:aximm:1.0 M01_AXI RDATA [31:0] [63:32]" *) input [63:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 M01_AXI RRESP [1:0] [3:2]" *) input [3:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RLAST [0:0] [1:1]" *) input [1:0]m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RVALID [0:0] [1:1]" *) input [1:0]m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 M01_AXI RREADY [0:0] [1:1]" *) output [1:0]m_axi_rready;
wire aclk;
wire aresetn;
wire [63:0]m_axi_araddr;
wire [3:0]m_axi_arburst;
wire [7:0]m_axi_arcache;
wire [23:0]m_axi_arid;
wire [15:0]m_axi_arlen;
wire [1:0]m_axi_arlock;
wire [5:0]m_axi_arprot;
wire [7:0]m_axi_arqos;
wire [1:0]m_axi_arready;
wire [7:0]m_axi_arregion;
wire [5:0]m_axi_arsize;
wire [1:0]m_axi_arvalid;
wire [63:0]m_axi_awaddr;
wire [3:0]m_axi_awburst;
wire [7:0]m_axi_awcache;
wire [23:0]m_axi_awid;
wire [15:0]m_axi_awlen;
wire [1:0]m_axi_awlock;
wire [5:0]m_axi_awprot;
wire [7:0]m_axi_awqos;
wire [1:0]m_axi_awready;
wire [7:0]m_axi_awregion;
wire [5:0]m_axi_awsize;
wire [1:0]m_axi_awvalid;
wire [23:0]m_axi_bid;
wire [1:0]m_axi_bready;
wire [3:0]m_axi_bresp;
wire [1:0]m_axi_bvalid;
wire [63:0]m_axi_rdata;
wire [23:0]m_axi_rid;
wire [1:0]m_axi_rlast;
wire [1:0]m_axi_rready;
wire [3:0]m_axi_rresp;
wire [1:0]m_axi_rvalid;
wire [63:0]m_axi_wdata;
wire [1:0]m_axi_wlast;
wire [1:0]m_axi_wready;
wire [7:0]m_axi_wstrb;
wire [1:0]m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [11:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire [0:0]s_axi_arready;
wire [2:0]s_axi_arsize;
wire [0:0]s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [11:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire [0:0]s_axi_awready;
wire [2:0]s_axi_awsize;
wire [0:0]s_axi_awvalid;
wire [11:0]s_axi_bid;
wire [0:0]s_axi_bready;
wire [1:0]s_axi_bresp;
wire [0:0]s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [11:0]s_axi_rid;
wire [0:0]s_axi_rlast;
wire [0:0]s_axi_rready;
wire [1:0]s_axi_rresp;
wire [0:0]s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [0:0]s_axi_wlast;
wire [0:0]s_axi_wready;
wire [3:0]s_axi_wstrb;
wire [0:0]s_axi_wvalid;
wire [1:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [23:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "12" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_CONNECTIVITY_MODE = "1" *)
(* C_DEBUG = "1" *)
(* C_FAMILY = "zynq" *)
(* C_M_AXI_ADDR_WIDTH = "64'b0000000000000000000000000001000000000000000000000000000000010000" *)
(* C_M_AXI_BASE_ADDR = "128'b00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000001000001001000000000000000000000" *)
(* C_M_AXI_READ_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *)
(* C_M_AXI_READ_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *)
(* C_M_AXI_SECURE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* C_M_AXI_WRITE_CONNECTIVITY = "64'b1111111111111111111111111111111111111111111111111111111111111111" *)
(* C_M_AXI_WRITE_ISSUING = "64'b0000000000000000000000000000100000000000000000000000000000001000" *)
(* C_NUM_ADDR_RANGES = "1" *)
(* C_NUM_MASTER_SLOTS = "2" *)
(* C_NUM_SLAVE_SLOTS = "1" *)
(* C_R_REGISTER = "0" *)
(* C_S_AXI_ARB_PRIORITY = "0" *)
(* C_S_AXI_BASE_ID = "0" *)
(* C_S_AXI_READ_ACCEPTANCE = "8" *)
(* C_S_AXI_SINGLE_THREAD = "0" *)
(* C_S_AXI_THREAD_ID_WIDTH = "12" *)
(* C_S_AXI_WRITE_ACCEPTANCE = "8" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_ADDR_DECODE = "1" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_FAMILY = "zynq" *)
(* P_INCR = "2'b01" *)
(* P_LEN = "8" *)
(* P_LOCK = "1" *)
(* P_M_AXI_ERR_MODE = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_M_AXI_SUPPORTS_READ = "2'b11" *)
(* P_M_AXI_SUPPORTS_WRITE = "2'b11" *)
(* P_ONES = "65'b11111111111111111111111111111111111111111111111111111111111111111" *)
(* P_RANGE_CHECK = "1" *)
(* P_S_AXI_BASE_ID = "64'b0000000000000000000000000000000000000000000000000000000000000000" *)
(* P_S_AXI_HIGH_ID = "64'b0000000000000000000000000000000000000000000000000000111111111111" *)
(* P_S_AXI_SUPPORTS_READ = "1'b1" *)
(* P_S_AXI_SUPPORTS_WRITE = "1'b1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_crossbar_v2_1_14_axi_crossbar inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[1:0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[1:0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser({1'b0,1'b0}),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser({1'b0,1'b0}),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[23:0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[1:0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O2111A_2_V
`define SKY130_FD_SC_MS__O2111A_2_V
/**
* o2111a: 2-input OR into first input of 4-input AND.
*
* X = ((A1 | A2) & B1 & C1 & D1)
*
* Verilog wrapper for o2111a with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__o2111a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111a_2 (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__o2111a_2 (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__o2111a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__O2111A_2_V
|
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
//
// Revision Control Information
//
// $RCSfile: altera_tse_mac_pcs.v,v $
// $Source: /ipbu/cvs/sio/projects/TriSpeedEthernet/src/RTL/Top_level_modules/altera_tse_mac_pcs.v,v $
//
// $Revision: #1 $
// $Date: 2011/08/15 $
// Check in by : $Author: max $
// Author : Arul Paniandi
//
// Project : Triple Speed Ethernet
//
// Description :
//
// Top level module for Triple Speed Ethernet MAC + PCS
//
// ALTERA Confidential and Proprietary
// Copyright 2006 (c) Altera Corporation
// All rights reserved
//
// -------------------------------------------------------------------------
// -------------------------------------------------------------------------
(*altera_attribute = {"-name SYNCHRONIZER_IDENTIFICATION OFF" } *)
module altera_tse_mac_pcs /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"R102,R105,D102,D101,D103\"" */(
clk, // Avalon slave - clock
read, // Avalon slave - read
write, // Avalon slave - write
address, // Avalon slave - address
writedata, // Avalon slave - writedata
readdata, // Avalon slave - readdata
waitrequest, // Avalon slave - waitrequest
reset, // Avalon slave - reset
reset_rx_clk,
reset_tx_clk,
reset_ff_rx_clk,
reset_ff_tx_clk,
ff_rx_clk, // AtlanticII source - clk
ff_rx_data, // AtlanticII source - data
ff_rx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_rx_sop, // AtlanticII source - startofpacket
ff_rx_eop, // AtlanticII source - endofpacket
rx_err, // AtlanticII source - error
rx_err_stat, // AtlanticII source - component_specific_signal(eop)
rx_frm_type, // AtlanticII source - component_specific_signal(data)
ff_rx_rdy, // AtlanticII source - ready
ff_rx_dval, // AtlanticII source - valid
ff_rx_dsav, // Will not exists in SoPC Model (leave unconnected)
ff_tx_clk, // AtlanticII sink - clk
ff_tx_data, // AtlanticII sink - data
ff_tx_mod, // Will not exists in SoPC Model as the 8-bit version is used
ff_tx_sop, // AtlanticII sink - startofpacket
ff_tx_eop, // AtlanticII sink - endofpacket
ff_tx_err, // AtlanticII sink - error
ff_tx_wren, // AtlanticII sink - valid
ff_tx_crc_fwd, // AtlanticII sink - component_specific_signal(eop)
ff_tx_rdy, // AtlanticII sink - ready
ff_tx_septy, // Will not exists in SoPC Model (leave unconnected)
tx_ff_uflow, // Will not exists in SoPC Model (leave unconnected)
ff_rx_a_full,
ff_rx_a_empty,
ff_tx_a_full,
ff_tx_a_empty,
xoff_gen,
xon_gen,
magic_sleep_n,
magic_wakeup,
mdc,
mdio_in,
mdio_out,
mdio_oen,
tbi_rx_clk,
tbi_tx_clk,
tbi_rx_d,
tbi_tx_d,
sd_loopback,
powerdown,
led_col,
led_an,
led_char_err,
led_disp_err,
led_crs,
led_link
);
parameter ENABLE_ENA = 8; // Enable n-Bit Local Interface
parameter ENABLE_GMII_LOOPBACK = 1; // GMII_LOOPBACK_ENA : Enable GMII Loopback Logic
parameter ENABLE_HD_LOGIC = 1; // HD_LOGIC_ENA : Enable Half Duplex Logic
parameter USE_SYNC_RESET = 1; // Use Synchronized Reset Inputs
parameter ENABLE_SUP_ADDR = 1; // SUP_ADDR_ENA : Enable Supplemental Addresses
parameter ENA_HASH = 1; // ENA_HASH Enable Hash Table
parameter STAT_CNT_ENA = 1; // STAT_CNT_ENA Enable Statistic Counters
parameter ENABLE_EXTENDED_STAT_REG = 0; // Enable a few extended statistic registers
parameter EG_FIFO = 256 ; // Egress FIFO Depth
parameter EG_ADDR = 8 ; // Egress FIFO Depth
parameter ING_FIFO = 256 ; // Ingress FIFO Depth
parameter ING_ADDR = 8 ; // Egress FIFO Depth
parameter RESET_LEVEL = 1'b 1 ; // Reset Active Level
parameter MDIO_CLK_DIV = 40 ; // Host Clock Division - MDC Generation
parameter CORE_VERSION = 16'h3; // ALTERA Core Version
parameter CUST_VERSION = 1 ; // Customer Core Version
parameter REDUCED_INTERFACE_ENA = 0; // Enable the RGMII / MII Interface
parameter ENABLE_MDIO = 1; // Enable the MDIO Interface
parameter ENABLE_MAGIC_DETECT = 1; // Enable magic packet detection
parameter ENABLE_MIN_FIFO = 1; // Enable minimun FIFO (Reduced functionality)
parameter ENABLE_MACLITE = 0; // Enable MAC LITE operation
parameter MACLITE_GIGE = 0; // Enable/Disable Gigabit MAC operation for MAC LITE.
parameter CRC32DWIDTH = 4'b 1000; // input data width (informal, not for change)
parameter CRC32GENDELAY = 3'b 110; // when the data from the generator is valid
parameter CRC32CHECK16BIT = 1'b 0; // 1 compare two times 16 bit of the CRC (adds one pipeline step)
parameter CRC32S1L2_EXTERN = 1'b0; // false: merge enable
parameter ENABLE_SHIFT16 = 0; // Enable byte stuffing at packet header
parameter RAM_TYPE = "AUTO"; // Specify the RAM type
parameter INSERT_TA = 0; // Option to insert timing adapter for SOPC systems
parameter PHY_IDENTIFIER = 32'h 00000000;
parameter DEV_VERSION = 16'h 0001 ; // Customer Phy's Core Version
parameter ENABLE_SGMII = 1; // Enable SGMII logic for synthesis
parameter ENABLE_MAC_FLOW_CTRL = 1'b1; // Option to enable flow control
parameter ENABLE_MAC_TXADDR_SET = 1'b1; // Option to enable MAC address insertion onto 'to-be-transmitted' Ethernet frames on MAC TX data path
parameter ENABLE_MAC_RX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC RX data path
parameter ENABLE_MAC_TX_VLAN = 1'b1; // Option to enable VLAN tagged Ethernet frames on MAC TX data path
parameter SYNCHRONIZER_DEPTH = 3; // Number of synchronizer
input clk; // 25MHz Host Interface Clock
input read; // Register Read Strobe
input write; // Register Write Strobe
input [7:0] address; // Register Address
input [31:0] writedata; // Write Data for Host Bus
output [31:0] readdata; // Read Data to Host Bus
output waitrequest; // Interface Busy
input reset; // Asynchronous Reset
input reset_rx_clk; // Asynchronous Reset - rx_clk Domain
input reset_tx_clk; // Asynchronous Reset - tx_clk Domain
input reset_ff_rx_clk; // Asynchronous Reset - ff_rx_clk Domain
input reset_ff_tx_clk; // Asynchronous Reset - ff_tx_clk Domain
input ff_rx_clk; // Transmit Local Clock
output [ENABLE_ENA-1:0] ff_rx_data; // Data Out
output [1:0] ff_rx_mod; // Data Modulo
output ff_rx_sop; // Start of Packet
output ff_rx_eop; // End of Packet
output [5:0] rx_err; // Errored Packet Indication
output [17:0] rx_err_stat; // Packet Length and Status Word
output [3:0] rx_frm_type; // Unicast Frame Indication
input ff_rx_rdy; // PHY Application Ready
output ff_rx_dval; // Data Valid Strobe
output ff_rx_dsav; // Data Available
input ff_tx_clk; // Transmit Local Clock
input [ENABLE_ENA-1:0] ff_tx_data; // Data Out
input [1:0] ff_tx_mod; // Data Modulo
input ff_tx_sop; // Start of Packet
input ff_tx_eop; // End of Packet
input ff_tx_err; // Errored Packet
input ff_tx_wren; // Write Enable
input ff_tx_crc_fwd; // Forward Current Frame with CRC from Application
output ff_tx_rdy; // FIFO Ready
output ff_tx_septy; // FIFO has space for at least one section
output tx_ff_uflow; // TX FIFO underflow occured (Synchronous with tx_clk)
output ff_rx_a_full; // Receive FIFO Almost Full
output ff_rx_a_empty; // Receive FIFO Almost Empty
output ff_tx_a_full; // Transmit FIFO Almost Full
output ff_tx_a_empty; // Transmit FIFO Almost Empty
input xoff_gen; // Xoff Pause frame generate
input xon_gen; // Xon Pause frame generate
input magic_sleep_n; // Enable Sleep Mode
output magic_wakeup; // Wake Up Request
output mdc; // 2.5MHz Inteface
input mdio_in; // MDIO Input
output mdio_out; // MDIO Output
output mdio_oen; // MDIO Output Enable
input tbi_rx_clk; // 125MHz Recoved Clock
input tbi_tx_clk; // 125MHz Transmit Clock
input [9:0] tbi_rx_d; // Non Aligned 10-Bit Characters
output [9:0] tbi_tx_d; // Transmit TBI Interface
output sd_loopback; // SERDES Loopback Enable
output powerdown; // Powerdown Enable
output led_crs; // Carrier Sense
output led_link; // Valid Link
output led_col; // Collision Indication
output led_an; // Auto-Negotiation Status
output led_char_err; // Character Error
output led_disp_err; // Disparity Error
wire [31:0] reg_data_out;
wire reg_busy;
wire [ENABLE_ENA-1:0] ff_rx_data;
wire [1:0] ff_rx_mod;
wire ff_rx_sop;
wire ff_rx_eop;
wire ff_rx_dval;
wire ff_rx_dsav;
wire ff_tx_rdy;
wire ff_tx_septy;
wire tx_ff_uflow;
wire magic_wakeup;
wire ff_rx_a_full;
wire ff_rx_a_empty;
wire ff_tx_a_full;
wire ff_tx_a_empty;
wire mdc;
wire mdio_out;
wire mdio_oen;
wire [9:0] tbi_tx_d;
wire sd_loopback;
wire powerdown;
wire led_crs;
wire led_link;
wire led_col;
wire led_an;
wire led_char_err;
wire led_disp_err;
wire rx_clk;
wire tx_clk;
wire rx_clkena;
wire tx_clkena;
wire [7:0] gm_rx_d; // GMII Receive Data
wire gm_rx_dv; // GMII Receive Frame Enable
wire gm_rx_err; // GMII Receive Frame Error
wire [7:0] gm_tx_d; // GMII Transmit Data
wire gm_tx_en; // GMII Transmit Frame Enable
wire gm_tx_err; // GMII Transmit Frame Error
wire [3:0] m_rx_d; // MII Receive Data
wire m_rx_dv; // MII Receive Frame Enable
wire m_rx_err; // MII Receive Drame Error
wire [3:0] m_tx_d; // MII Transmit Data
wire m_tx_en; // MII Transmit Frame Enable
wire m_tx_err; // MII Transmit Frame Error
wire m_rx_crs; // Carrier Sense
wire m_rx_col; // Collition
wire set_1000; // Gigabit Mode Enable
wire set_10; // 10Mbps Mode Enable
wire pcs_en;
wire [31:0]readdata_mac;
wire waitrequest_mac;
wire [31:0]readdata_pcs;
wire waitrequest_pcs;
wire write_pcs;
wire read_pcs;
wire write_mac;
wire read_mac;
wire [5:0] rx_err;
wire [17:0] rx_err_stat;
wire [3:0] rx_frm_type;
// Reset Lines
// -----------
wire reset_rx_clk_int; // Asynchronous Reset - rx_clk Domain
wire reset_tx_clk_int; // Asynchronous Reset - tx_clk Domain
wire reset_ff_rx_clk_int; // Asynchronous Reset - ff_rx_clk Domain
wire reset_ff_tx_clk_int; // Asynchronous Reset - ff_tx_clk Domain
wire reset_reg_clk_int; // Asynchronous Reset - reg_clk Domain
// This is done because the PCS address space is from 0x80 to 0x9F
// ---------------------------------------------------------------
assign pcs_en = address[7] & !address[6] & !address[5];
assign write_pcs = pcs_en? write : 1'b0;
assign read_pcs = pcs_en? read : 1'b0;
assign write_mac = pcs_en? 1'b0 : write;
assign read_mac = pcs_en? 1'b0 : read;
assign readdata = pcs_en? readdata_pcs : readdata_mac;
assign waitrequest = pcs_en? waitrequest_pcs : waitrequest_mac;
assign readdata_pcs[31:16] = {16{1'b0}};
// Programmable Reset Options
// --------------------------
generate if (USE_SYNC_RESET == 1)
begin
altera_tse_reset_synchronizer reset_sync_0 (
.clk(rx_clk),
.reset_in(reset),
.reset_out(reset_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_1 (
.clk(tx_clk),
.reset_in(reset),
.reset_out(reset_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_2 (
.clk(ff_rx_clk),
.reset_in(reset),
.reset_out(reset_ff_rx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_3 (
.clk(ff_tx_clk),
.reset_in(reset),
.reset_out(reset_ff_tx_clk_int)
);
altera_tse_reset_synchronizer reset_sync_4 (
.clk(clk),
.reset_in(reset),
.reset_out(reset_reg_clk_int)
);
end
else
begin
assign reset_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_rx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_ff_tx_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
assign reset_reg_clk_int = RESET_LEVEL == 1'b 1 ? reset : !reset ;
end
endgenerate
// --------------------------
altera_tse_top_gen_host top_gen_host_inst(
.reset_ff_rx_clk(reset_ff_rx_clk_int),
.reset_ff_tx_clk(reset_ff_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.gm_rx_dv(gm_rx_dv),
.gm_rx_d(gm_rx_d),
.gm_rx_err(gm_rx_err),
.m_rx_en(m_rx_dv),
.m_rx_d(m_rx_d),
.m_rx_err(m_rx_err),
.m_rx_col(m_rx_col),
.m_rx_crs(m_rx_crs),
.set_1000(set_1000),
.set_10(set_10),
.ff_rx_clk(ff_rx_clk),
.ff_rx_rdy(ff_rx_rdy),
.ff_tx_clk(ff_tx_clk),
.ff_tx_wren(ff_tx_wren),
.ff_tx_data(ff_tx_data),
.ff_tx_mod(ff_tx_mod),
.ff_tx_sop(ff_tx_sop),
.ff_tx_eop(ff_tx_eop),
.ff_tx_err(ff_tx_err),
.ff_tx_crc_fwd(ff_tx_crc_fwd),
.reg_clk(clk),
.reg_addr(address),
.reg_data_in(writedata),
.reg_rd(read_mac),
.reg_wr(write_mac),
.mdio_in(mdio_in),
.gm_tx_en(gm_tx_en),
.gm_tx_d(gm_tx_d),
.gm_tx_err(gm_tx_err),
.m_tx_en(m_tx_en),
.m_tx_d(m_tx_d),
.m_tx_err(m_tx_err),
.eth_mode(),
.ena_10(),
.ff_rx_dval(ff_rx_dval),
.ff_rx_data(ff_rx_data),
.ff_rx_mod(ff_rx_mod),
.ff_rx_sop(ff_rx_sop),
.ff_rx_eop(ff_rx_eop),
.ff_rx_dsav(ff_rx_dsav),
.rx_err(rx_err),
.rx_err_stat(rx_err_stat),
.rx_frm_type(rx_frm_type),
.ff_tx_rdy(ff_tx_rdy),
.ff_tx_septy(ff_tx_septy),
.tx_ff_uflow(tx_ff_uflow),
.rx_a_full(ff_rx_a_full),
.rx_a_empty(ff_rx_a_empty),
.tx_a_full(ff_tx_a_full),
.tx_a_empty(ff_tx_a_empty),
.xoff_gen(xoff_gen),
.xon_gen(xon_gen),
.reg_data_out(readdata_mac),
.reg_busy(waitrequest_mac),
.reg_sleepN(magic_sleep_n),
.reg_wakeup(magic_wakeup),
.mdc(mdc),
.mdio_out(mdio_out),
.mdio_oen(mdio_oen));
defparam
top_gen_host_inst.EG_FIFO = EG_FIFO,
top_gen_host_inst.ENABLE_SUP_ADDR = ENABLE_SUP_ADDR,
top_gen_host_inst.CORE_VERSION = CORE_VERSION,
top_gen_host_inst.CRC32GENDELAY = CRC32GENDELAY,
top_gen_host_inst.MDIO_CLK_DIV = MDIO_CLK_DIV,
top_gen_host_inst.EG_ADDR = EG_ADDR,
top_gen_host_inst.ENA_HASH = ENA_HASH,
top_gen_host_inst.STAT_CNT_ENA = STAT_CNT_ENA,
top_gen_host_inst.ENABLE_EXTENDED_STAT_REG = ENABLE_EXTENDED_STAT_REG,
top_gen_host_inst.ING_FIFO = ING_FIFO,
top_gen_host_inst.ENABLE_ENA = ENABLE_ENA,
top_gen_host_inst.ENABLE_HD_LOGIC = ENABLE_HD_LOGIC,
top_gen_host_inst.REDUCED_INTERFACE_ENA = REDUCED_INTERFACE_ENA,
top_gen_host_inst.ENABLE_MDIO = ENABLE_MDIO,
top_gen_host_inst.ENABLE_MAGIC_DETECT = ENABLE_MAGIC_DETECT,
top_gen_host_inst.ENABLE_MIN_FIFO = ENABLE_MIN_FIFO,
top_gen_host_inst.ENABLE_PADDING = !ENABLE_MACLITE,
top_gen_host_inst.ENABLE_LGTH_CHECK = !ENABLE_MACLITE,
top_gen_host_inst.GBIT_ONLY = !ENABLE_MACLITE | MACLITE_GIGE,
top_gen_host_inst.MBIT_ONLY = !ENABLE_MACLITE | !MACLITE_GIGE,
top_gen_host_inst.REDUCED_CONTROL = ENABLE_MACLITE,
top_gen_host_inst.CRC32S1L2_EXTERN = CRC32S1L2_EXTERN,
top_gen_host_inst.ENABLE_GMII_LOOPBACK = ENABLE_GMII_LOOPBACK,
top_gen_host_inst.ING_ADDR = ING_ADDR,
top_gen_host_inst.CRC32DWIDTH = CRC32DWIDTH,
top_gen_host_inst.CUST_VERSION = CUST_VERSION,
top_gen_host_inst.CRC32CHECK16BIT = CRC32CHECK16BIT,
top_gen_host_inst.ENABLE_SHIFT16 = ENABLE_SHIFT16,
top_gen_host_inst.INSERT_TA = INSERT_TA,
top_gen_host_inst.RAM_TYPE = RAM_TYPE,
top_gen_host_inst.ENABLE_MAC_FLOW_CTRL = ENABLE_MAC_FLOW_CTRL,
top_gen_host_inst.ENABLE_MAC_TXADDR_SET = ENABLE_MAC_TXADDR_SET,
top_gen_host_inst.ENABLE_MAC_RX_VLAN = ENABLE_MAC_RX_VLAN,
top_gen_host_inst.SYNCHRONIZER_DEPTH = SYNCHRONIZER_DEPTH,
top_gen_host_inst.ENABLE_MAC_TX_VLAN = ENABLE_MAC_TX_VLAN;
altera_tse_top_1000_base_x top_1000_base_x_inst(
.reset_rx_clk(reset_rx_clk_int),
.reset_tx_clk(reset_tx_clk_int),
.reset_reg_clk(reset_reg_clk_int),
.rx_clk(rx_clk),
.tx_clk(tx_clk),
.rx_clkena(rx_clkena),
.tx_clkena(tx_clkena),
.ref_clk(1'b0),
.gmii_rx_dv(gm_rx_dv),
.gmii_rx_d(gm_rx_d),
.gmii_rx_err(gm_rx_err),
.gmii_tx_en(gm_tx_en),
.gmii_tx_d(gm_tx_d),
.gmii_tx_err(gm_tx_err),
.mii_rx_dv(m_rx_dv),
.mii_rx_d(m_rx_d),
.mii_rx_err(m_rx_err),
.mii_tx_en(m_tx_en),
.mii_tx_d(m_tx_d),
.mii_tx_err(m_tx_err),
.mii_col(m_rx_col),
.mii_crs(m_rx_crs),
.tbi_rx_clk(tbi_rx_clk),
.tbi_tx_clk(tbi_tx_clk),
.tbi_rx_d(tbi_rx_d),
.tbi_tx_d(tbi_tx_d),
.sd_loopback(sd_loopback),
.reg_clk(clk),
.reg_rd(read_pcs),
.reg_wr(write_pcs),
.reg_addr(address[4:0]),
.reg_data_in(writedata[15:0]),
.reg_data_out(readdata_pcs[15:0]),
.reg_busy(waitrequest_pcs),
.powerdown(powerdown),
.set_10(set_10),
.set_100(),
.set_1000(set_1000),
.hd_ena(),
.led_col(led_col),
.led_an(led_an),
.led_char_err(led_char_err),
.led_disp_err(led_disp_err),
.led_crs(led_crs),
.led_link(led_link));
defparam
top_1000_base_x_inst.PHY_IDENTIFIER = PHY_IDENTIFIER,
top_1000_base_x_inst.DEV_VERSION = DEV_VERSION,
top_1000_base_x_inst.ENABLE_SGMII = ENABLE_SGMII;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:45:00 05/22/2016
// Design Name: RICPU
// Module Name: Y:/TEOCOA/EXPR9/TESTRICPU.v
// Project Name: EXPR9
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: RICPU
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module TESTRICPU;
// Inputs
reg clk;
reg clk_ram;
reg rst;
// Outputs
wire [31:0] ALU_F;
wire FR_ZF;
wire FR_OF;
wire [31:0] A, B;
wire [31:0] Mem_R_Data;
wire [6:0] MW;
// Instantiate the Unit Under Test (UUT)
RICPU uut (
.clk(clk),
.clk_ram(clk_ram),
.rst(rst),
.ALU_F(ALU_F),
.FR_ZF(FR_ZF),
.FR_OF(FR_OF),
.A(A),
.B(B),
.MW(MW),
.Mem_R_Data(Mem_R_Data)
);
always #4 clk = ~clk;
always #1 clk_ram = ~clk_ram;
initial begin
// Initialize Inputs
clk = 0;
clk_ram = 0;
rst = 0;
// Wait 100 ns for global reset to finish
#4;
rst = 1;
#4;
rst = 0;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3_FUNCTIONAL_V
`define SKY130_FD_SC_LP__NOR3_FUNCTIONAL_V
/**
* nor3: 3-input NOR.
*
* Y = !(A | B | C | !D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__nor3 (
Y,
A,
B,
C
);
// Module ports
output Y;
input A;
input B;
input C;
// Local signals
wire nor0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y, C, A, B );
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3_FUNCTIONAL_V |
/* This file is part of JT12.
JT12 program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
JT12 program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with JT12. If not, see <http://www.gnu.org/licenses/>.
Author: Jose Tejada Gomez. Twitter: @topapate
Version: 1.0
Date: 15-11-2018
*/
// Use for YM2203
// no left/right channels
// full operator resolution
// clamped to maximum output of signed 16 bits
// This version does not clamp each channel individually
// That does not correspond to real hardware behaviour. I should
// change it.
module jt03_acc
(
input rst,
input clk,
input clk_en /* synthesis direct_enable */,
input signed [13:0] op_result,
input s1_enters,
input s2_enters,
input s3_enters,
input s4_enters,
input zero,
input [2:0] alg,
// combined output
output signed [15:0] snd
);
reg sum_en;
always @(*) begin
case ( alg )
default: sum_en = s4_enters;
3'd4: sum_en = s2_enters | s4_enters;
3'd5,3'd6: sum_en = ~s1_enters;
3'd7: sum_en = 1'b1;
endcase
end
localparam res=18;
wire [res-1:0] hires;
assign snd = hires[res-1:res-16];
jt12_single_acc #(.win(14),.wout(res)) u_mono(
.clk ( clk ),
.clk_en ( clk_en ),
.op_result ( op_result ),
.sum_en ( sum_en ),
.zero ( zero ),
.snd ( hires )
);
endmodule
|
module soc_system (
button_pio_external_connection_export,
clk_clk,
dipsw_pio_external_connection_export,
hps_0_f2h_cold_reset_req_reset_n,
hps_0_f2h_debug_reset_req_reset_n,
hps_0_f2h_stm_hw_events_stm_hwevents,
hps_0_f2h_warm_reset_req_reset_n,
hps_0_h2f_reset_reset_n,
hps_0_hps_io_hps_io_emac1_inst_TX_CLK,
hps_0_hps_io_hps_io_emac1_inst_TXD0,
hps_0_hps_io_hps_io_emac1_inst_TXD1,
hps_0_hps_io_hps_io_emac1_inst_TXD2,
hps_0_hps_io_hps_io_emac1_inst_TXD3,
hps_0_hps_io_hps_io_emac1_inst_RXD0,
hps_0_hps_io_hps_io_emac1_inst_MDIO,
hps_0_hps_io_hps_io_emac1_inst_MDC,
hps_0_hps_io_hps_io_emac1_inst_RX_CTL,
hps_0_hps_io_hps_io_emac1_inst_TX_CTL,
hps_0_hps_io_hps_io_emac1_inst_RX_CLK,
hps_0_hps_io_hps_io_emac1_inst_RXD1,
hps_0_hps_io_hps_io_emac1_inst_RXD2,
hps_0_hps_io_hps_io_emac1_inst_RXD3,
hps_0_hps_io_hps_io_sdio_inst_CMD,
hps_0_hps_io_hps_io_sdio_inst_D0,
hps_0_hps_io_hps_io_sdio_inst_D1,
hps_0_hps_io_hps_io_sdio_inst_CLK,
hps_0_hps_io_hps_io_sdio_inst_D2,
hps_0_hps_io_hps_io_sdio_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D0,
hps_0_hps_io_hps_io_usb1_inst_D1,
hps_0_hps_io_hps_io_usb1_inst_D2,
hps_0_hps_io_hps_io_usb1_inst_D3,
hps_0_hps_io_hps_io_usb1_inst_D4,
hps_0_hps_io_hps_io_usb1_inst_D5,
hps_0_hps_io_hps_io_usb1_inst_D6,
hps_0_hps_io_hps_io_usb1_inst_D7,
hps_0_hps_io_hps_io_usb1_inst_CLK,
hps_0_hps_io_hps_io_usb1_inst_STP,
hps_0_hps_io_hps_io_usb1_inst_DIR,
hps_0_hps_io_hps_io_usb1_inst_NXT,
hps_0_hps_io_hps_io_spim1_inst_CLK,
hps_0_hps_io_hps_io_spim1_inst_MOSI,
hps_0_hps_io_hps_io_spim1_inst_MISO,
hps_0_hps_io_hps_io_spim1_inst_SS0,
hps_0_hps_io_hps_io_uart0_inst_RX,
hps_0_hps_io_hps_io_uart0_inst_TX,
hps_0_hps_io_hps_io_i2c0_inst_SDA,
hps_0_hps_io_hps_io_i2c0_inst_SCL,
hps_0_hps_io_hps_io_i2c1_inst_SDA,
hps_0_hps_io_hps_io_i2c1_inst_SCL,
hps_0_hps_io_hps_io_gpio_inst_GPIO09,
hps_0_hps_io_hps_io_gpio_inst_GPIO35,
hps_0_hps_io_hps_io_gpio_inst_GPIO40,
hps_0_hps_io_hps_io_gpio_inst_GPIO53,
hps_0_hps_io_hps_io_gpio_inst_GPIO54,
hps_0_hps_io_hps_io_gpio_inst_GPIO61,
led_pio_external_connection_export,
memory_mem_a,
memory_mem_ba,
memory_mem_ck,
memory_mem_ck_n,
memory_mem_cke,
memory_mem_cs_n,
memory_mem_ras_n,
memory_mem_cas_n,
memory_mem_we_n,
memory_mem_reset_n,
memory_mem_dq,
memory_mem_dqs,
memory_mem_dqs_n,
memory_mem_odt,
memory_mem_dm,
memory_oct_rzqin,
reset_reset_n);
input [3:0] button_pio_external_connection_export;
input clk_clk;
input [3:0] dipsw_pio_external_connection_export;
input hps_0_f2h_cold_reset_req_reset_n;
input hps_0_f2h_debug_reset_req_reset_n;
input [27:0] hps_0_f2h_stm_hw_events_stm_hwevents;
input hps_0_f2h_warm_reset_req_reset_n;
output hps_0_h2f_reset_reset_n;
output hps_0_hps_io_hps_io_emac1_inst_TX_CLK;
output hps_0_hps_io_hps_io_emac1_inst_TXD0;
output hps_0_hps_io_hps_io_emac1_inst_TXD1;
output hps_0_hps_io_hps_io_emac1_inst_TXD2;
output hps_0_hps_io_hps_io_emac1_inst_TXD3;
input hps_0_hps_io_hps_io_emac1_inst_RXD0;
inout hps_0_hps_io_hps_io_emac1_inst_MDIO;
output hps_0_hps_io_hps_io_emac1_inst_MDC;
input hps_0_hps_io_hps_io_emac1_inst_RX_CTL;
output hps_0_hps_io_hps_io_emac1_inst_TX_CTL;
input hps_0_hps_io_hps_io_emac1_inst_RX_CLK;
input hps_0_hps_io_hps_io_emac1_inst_RXD1;
input hps_0_hps_io_hps_io_emac1_inst_RXD2;
input hps_0_hps_io_hps_io_emac1_inst_RXD3;
inout hps_0_hps_io_hps_io_sdio_inst_CMD;
inout hps_0_hps_io_hps_io_sdio_inst_D0;
inout hps_0_hps_io_hps_io_sdio_inst_D1;
output hps_0_hps_io_hps_io_sdio_inst_CLK;
inout hps_0_hps_io_hps_io_sdio_inst_D2;
inout hps_0_hps_io_hps_io_sdio_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D0;
inout hps_0_hps_io_hps_io_usb1_inst_D1;
inout hps_0_hps_io_hps_io_usb1_inst_D2;
inout hps_0_hps_io_hps_io_usb1_inst_D3;
inout hps_0_hps_io_hps_io_usb1_inst_D4;
inout hps_0_hps_io_hps_io_usb1_inst_D5;
inout hps_0_hps_io_hps_io_usb1_inst_D6;
inout hps_0_hps_io_hps_io_usb1_inst_D7;
input hps_0_hps_io_hps_io_usb1_inst_CLK;
output hps_0_hps_io_hps_io_usb1_inst_STP;
input hps_0_hps_io_hps_io_usb1_inst_DIR;
input hps_0_hps_io_hps_io_usb1_inst_NXT;
output hps_0_hps_io_hps_io_spim1_inst_CLK;
output hps_0_hps_io_hps_io_spim1_inst_MOSI;
input hps_0_hps_io_hps_io_spim1_inst_MISO;
output hps_0_hps_io_hps_io_spim1_inst_SS0;
input hps_0_hps_io_hps_io_uart0_inst_RX;
output hps_0_hps_io_hps_io_uart0_inst_TX;
inout hps_0_hps_io_hps_io_i2c0_inst_SDA;
inout hps_0_hps_io_hps_io_i2c0_inst_SCL;
inout hps_0_hps_io_hps_io_i2c1_inst_SDA;
inout hps_0_hps_io_hps_io_i2c1_inst_SCL;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO09;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO35;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO40;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO53;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO54;
inout hps_0_hps_io_hps_io_gpio_inst_GPIO61;
output [7:0] led_pio_external_connection_export;
output [14:0] memory_mem_a;
output [2:0] memory_mem_ba;
output memory_mem_ck;
output memory_mem_ck_n;
output memory_mem_cke;
output memory_mem_cs_n;
output memory_mem_ras_n;
output memory_mem_cas_n;
output memory_mem_we_n;
output memory_mem_reset_n;
inout [31:0] memory_mem_dq;
inout [3:0] memory_mem_dqs;
inout [3:0] memory_mem_dqs_n;
output memory_mem_odt;
output [3:0] memory_mem_dm;
input memory_oct_rzqin;
input reset_reset_n;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_PP_SYMBOL_V
`define SKY130_FD_SC_LS__DLRTP_PP_SYMBOL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input GATE ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_PP_SYMBOL_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_dwidth_converter:2.1
// IP Revision: 14
(* X_CORE_INFO = "axi_dwidth_converter_v2_1_14_top,Vivado 2017.3" *)
(* CHECK_LICENSE_TYPE = "design_1_auto_ds_1,axi_dwidth_converter_v2_1_14_top,{}" *)
(* CORE_GENERATION_INFO = "design_1_auto_ds_1,axi_dwidth_converter_v2_1_14_top,{x_ipProduct=Vivado 2017.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_dwidth_converter,x_ipVersion=2.1,x_ipCoreRevision=14,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_AXI_PROTOCOL=0,C_S_AXI_ID_WIDTH=1,C_SUPPORTS_ID=0,C_AXI_ADDR_WIDTH=13,C_S_AXI_DATA_WIDTH=64,C_M_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_FIFO_MODE=0,C_S_AXI_ACLK_RATIO=1,C_M_AXI_ACLK_RATIO=2,C_AXI_IS_ACLK_ASYNC=0,C_MAX_SPLIT_BEATS=256,\
C_PACKING_LEVEL=1,C_SYNCHRONIZER_STAGE=3}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_auto_ds_1 (
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_CLK, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET S_AXI_ARESETN" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *)
input wire s_axi_aclk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME SI_RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *)
input wire s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [12 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [12 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 64, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 128, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [12 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [12 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 100000000, ID_WIDTH 0, ADDR_WIDTH 13, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.000, CLK_DOMAIN design_1_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_dwidth_converter_v2_1_14_top #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(0),
.C_S_AXI_ID_WIDTH(1),
.C_SUPPORTS_ID(0),
.C_AXI_ADDR_WIDTH(13),
.C_S_AXI_DATA_WIDTH(64),
.C_M_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_FIFO_MODE(0),
.C_S_AXI_ACLK_RATIO(1),
.C_M_AXI_ACLK_RATIO(2),
.C_AXI_IS_ACLK_ASYNC(0),
.C_MAX_SPLIT_BEATS(256),
.C_PACKING_LEVEL(1),
.C_SYNCHRONIZER_STAGE(3)
) inst (
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_aclk(1'H0),
.m_axi_aresetn(1'H0),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
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