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// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_engine.v
// Version: 1.0
// Verilog Standard: Verilog-2001
// Description: The tx_engine module takes a formatted header, number of alignment
// blanks and a payloa and concatenates all three (in that order) to form a
// packet. These packets must meet max-request, max-payload, and payload
// termination requirements (see Read Completion Boundary). The tx_engine does
// not check these requirements during operation, but may do so during simulation.
// This Engine is capable of operating at "line rate".
// Author: Dustin Richmond (@darichmond)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh" // Defines the user-facing signal widths.
module tx_engine
#(parameter C_DATA_WIDTH = 128,
parameter C_DEPTH_PACKETS = 10,
parameter C_PIPELINE_INPUT = 1,
parameter C_PIPELINE_OUTPUT = 0,
parameter C_FORMATTER_DELAY = 1,
parameter C_MAX_HDR_WIDTH = 128,
parameter C_MAX_PAYLOAD_DWORDS = 64,
parameter C_VENDOR = "ALTERA"
)
(
// Interface: Clocks
input CLK,
// Interface: Reset
input RST_IN,
// Interface: TX HDR
input TX_HDR_VALID,
input [C_MAX_HDR_WIDTH-1:0] TX_HDR,
input [`SIG_LEN_W-1:0] TX_HDR_PAYLOAD_LEN,
input [`SIG_NONPAY_W-1:0] TX_HDR_NONPAY_LEN,
input [`SIG_PACKETLEN_W-1:0] TX_HDR_PACKET_LEN,
input TX_HDR_NOPAYLOAD,
output TX_HDR_READY,
// Interface: TX_DATA
input TX_DATA_VALID,
input [C_DATA_WIDTH-1:0] TX_DATA,
input TX_DATA_START_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET,
input TX_DATA_END_FLAG,
input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET,
output TX_DATA_READY,
// Interface: TX_PKT
input TX_PKT_READY,
output [C_DATA_WIDTH-1:0] TX_PKT,
output TX_PKT_START_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET,
output TX_PKT_END_FLAG,
output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET,
output TX_PKT_VALID
);
`include "functions.vh"
localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT;
localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT;
localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT;
localparam C_ACTUAL_HDR_FIFO_DEPTH = clog2s(C_DEPTH_PACKETS);
localparam C_USE_COMPUTE_REG = 1;
localparam C_USE_READY_REG = 1;
localparam C_USE_FWFT_HDR_FIFO = 1;
localparam C_DATA_FIFO_DEPTH = C_ACTUAL_HDR_FIFO_DEPTH + C_FORMATTER_DELAY +
C_PIPELINE_HDR_FIFO_INPUT + C_PIPELINE_HDR_FIFO_OUTPUT + C_USE_FWFT_HDR_FIFO + // Header Fifo
C_PIPELINE_HDR_INPUT + C_USE_COMPUTE_REG + C_USE_READY_REG + C_PIPELINE_OUTPUT; // Aligner
wire wTxHdrReady;
wire wTxHdrValid;
wire [C_MAX_HDR_WIDTH-1:0] wTxHdr;
wire [`SIG_NONPAY_W-1:0] wTxHdrNonpayLen;
wire [`SIG_PACKETLEN_W-1:0] wTxHdrPacketLen;
wire [`SIG_LEN_W-1:0] wTxHdrPayloadLen;
wire wTxHdrNoPayload;
wire wTxDataReady;
wire [C_DATA_WIDTH-1:0] wTxData;
wire [clog2s(C_DATA_WIDTH/32)-1:0] wTxDataEndOffset;
wire wTxDataStartFlag;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataEndFlags;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordValid;
wire [(C_DATA_WIDTH/32)-1:0] wTxDataWordReady;
tx_data_pipeline
#(
.C_MAX_PAYLOAD (C_MAX_PAYLOAD_DWORDS*32),
.C_DEPTH_PACKETS (C_DATA_FIFO_DEPTH),
/*AUTOINSTPARAM*/
// Parameters
.C_DATA_WIDTH (C_DATA_WIDTH),
.C_PIPELINE_INPUT (C_PIPELINE_INPUT),
.C_PIPELINE_OUTPUT (C_PIPELINE_OUTPUT),
.C_VENDOR (C_VENDOR))
tx_data_pipeline_inst
(
// Outputs
.RD_TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.RD_TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.RD_TX_DATA_START_FLAG (wTxDataStartFlag),
.RD_TX_DATA_END_FLAGS (wTxDataEndFlags[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_READY (TX_DATA_READY),
// Inputs
.RD_TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA (TX_DATA),
.WR_TX_DATA_VALID (TX_DATA_VALID),
.WR_TX_DATA_START_FLAG (TX_DATA_START_FLAG),
.WR_TX_DATA_START_OFFSET (TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.WR_TX_DATA_END_FLAG (TX_DATA_END_FLAG),
.WR_TX_DATA_END_OFFSET (TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_hdr_fifo
#(
.C_PIPELINE_OUTPUT (C_PIPELINE_HDR_FIFO_OUTPUT),
.C_PIPELINE_INPUT (C_PIPELINE_HDR_FIFO_INPUT),
/*AUTOINSTPARAM*/
// Parameters
.C_DEPTH_PACKETS (C_ACTUAL_HDR_FIFO_DEPTH),
.C_MAX_HDR_WIDTH (C_MAX_HDR_WIDTH),
.C_VENDOR (C_VENDOR))
txhf_inst
(
// Outputs
.WR_TX_HDR_READY (TX_HDR_READY),
.RD_TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.RD_TX_HDR_VALID (wTxHdrValid),
.RD_TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.RD_TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.RD_TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.RD_TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
// Inputs
.WR_TX_HDR (TX_HDR[C_MAX_HDR_WIDTH-1:0]),
.WR_TX_HDR_VALID (TX_HDR_VALID),
.WR_TX_HDR_NOPAYLOAD (TX_HDR_NOPAYLOAD),
.WR_TX_HDR_PAYLOAD_LEN (TX_HDR_PAYLOAD_LEN[`SIG_LEN_W-1:0]),
.WR_TX_HDR_NONPAY_LEN (TX_HDR_NONPAY_LEN[`SIG_NONPAY_W-1:0]),
.WR_TX_HDR_PACKET_LEN (TX_HDR_PACKET_LEN[`SIG_PACKETLEN_W-1:0]),
.RD_TX_HDR_READY (wTxHdrReady),
/*AUTOINST*/
// Outputs
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
// TX Header Fifo
tx_alignment_pipeline
#(
// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_DATA_INPUT (1),
.C_PIPELINE_HDR_INPUT (C_PIPELINE_HDR_INPUT),
.C_DATA_WIDTH (C_DATA_WIDTH),
// Parameters
/*AUTOINSTPARAM*/
// Parameters
.C_USE_COMPUTE_REG (C_USE_COMPUTE_REG),
.C_USE_READY_REG (C_USE_READY_REG),
.C_VENDOR (C_VENDOR))
tx_alignment_inst
(
// Outputs
.TX_DATA_WORD_READY (wTxDataWordReady[(C_DATA_WIDTH/32)-1:0]),
.TX_HDR_READY (wTxHdrReady),
.TX_PKT (TX_PKT[C_DATA_WIDTH-1:0]),
.TX_PKT_VALID (TX_PKT_VALID),
.TX_PKT_START_FLAG (TX_PKT_START_FLAG),
.TX_PKT_START_OFFSET (TX_PKT_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
.TX_PKT_END_FLAG (TX_PKT_END_FLAG),
.TX_PKT_END_OFFSET (TX_PKT_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]),
// Inputs
.TX_DATA_START_FLAG (wTxDataStartFlag),
.TX_DATA_END_FLAGS (wTxDataEndFlags),
.TX_DATA_WORD_VALID (wTxDataWordValid[(C_DATA_WIDTH/32)-1:0]),
.TX_DATA (wTxData[C_DATA_WIDTH-1:0]),
.TX_HDR (wTxHdr[C_MAX_HDR_WIDTH-1:0]),
.TX_HDR_VALID (wTxHdrValid),
.TX_HDR_NOPAYLOAD (wTxHdrNoPayload),
.TX_HDR_PAYLOAD_LEN (wTxHdrPayloadLen[`SIG_LEN_W-1:0]),
.TX_HDR_NONPAY_LEN (wTxHdrNonpayLen[`SIG_NONPAY_W-1:0]),
.TX_HDR_PACKET_LEN (wTxHdrPacketLen[`SIG_PACKETLEN_W-1:0]),
.TX_PKT_READY (TX_PKT_READY),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.RST_IN (RST_IN));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_FUNCTIONAL_V
`define SKY130_FD_SC_LP__AND3_FUNCTIONAL_V
/**
* and3: 3-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__and3 (
X,
A,
B,
C
);
// Module ports
output X;
input A;
input B;
input C;
// Local signals
wire and0_out_X;
// Name Output Other arguments
and and0 (and0_out_X, C, A, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:49:22 12/17/2012
// Design Name:
// Module Name: getID_4digits
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module getID_4digits(
input enable,
input [44:0] digits45,
output reg [15:0] iddecimal4
);
integer ID;
integer temp0, temp1;
always @(posedge enable) begin
ID = digits45[16:1];
//ID = 'b0001000010100000;
if(ID>=9000) iddecimal4[15:12] = 9;
else if(ID>=8000) iddecimal4[15:12] = 8;
else if(ID>=7000) iddecimal4[15:12] = 7;
else if(ID>=6000) iddecimal4[15:12] = 6;
else if(ID>=5000) iddecimal4[15:12] = 5;
else if(ID>=4000) iddecimal4[15:12] = 4;
else if(ID>=3000) iddecimal4[15:12] = 3;
else if(ID>=2000) iddecimal4[15:12] = 2;
else if(ID>=1000) iddecimal4[15:12] = 1;
else iddecimal4[15:12] = 0;
temp0 = ID-(iddecimal4[15:12]*1000);
if(temp0>=900) iddecimal4[11:8] = 9;
else if(temp0>=800) iddecimal4[11:8] = 8;
else if(temp0>=700) iddecimal4[11:8] = 7;
else if(temp0>=600) iddecimal4[11:8] = 6;
else if(temp0>=500) iddecimal4[11:8] = 5;
else if(temp0>=400) iddecimal4[11:8] = 4;
else if(temp0>=300) iddecimal4[11:8] = 3;
else if(temp0>=200) iddecimal4[11:8] = 2;
else if(temp0>=100) iddecimal4[11:8] = 1;
else iddecimal4[11:8] = 0;
temp1 = temp0-(iddecimal4[11:8]*100);
if(temp1>=90) iddecimal4[7:4] = 9;
else if(temp1>=80) iddecimal4[7:4] = 8;
else if(temp1>=70) iddecimal4[7:4] = 7;
else if(temp1>=60) iddecimal4[7:4] = 6;
else if(temp1>=50) iddecimal4[7:4] = 5;
else if(temp1>=40) iddecimal4[7:4] = 4;
else if(temp1>=30) iddecimal4[7:4] = 3;
else if(temp1>=20) iddecimal4[7:4] = 2;
else if(temp1>=10) iddecimal4[7:4] = 1;
else iddecimal4[7:4] = 0;
iddecimal4[3:0] = temp1-(iddecimal4[7:4]*10);
end
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__XOR2_BEHAVIORAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_BEHAVIORAL_PP_V |
/*
* This file is part of the DSLogic-hdl project.
*
* Copyright (C) 2014 DreamSourceLab <[email protected]>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
`timescale 1ns/100ps
`define D #1
module cons_buf (
// -- Clock & Reset
input core_clk,
input core_rst,
input sdram_clk,
input sd_rst,
// --
input cons_mode,
// -- data in
input sample_en,
input capture_done,
input capture_valid,
input [15:0] capture_data,
input wr_done,
// -- dread
input rd_req,
output rd_valid,
input [31:0] rd_addr,
output rd_rdy,
output [15:0] rd_data,
// -- DSO config
input [23:0] dso_sampleDivider,
input [23:0] dso_triggerPos,
input [7:0] dso_triggerSlope,
input [7:0] dso_triggerSource,
input [16:0] dso_triggerValue,
// -- sdram
// -- dread
output read_start,
output sd_rd_req,
input sd_rd_valid,
output [31:0] sd_rd_addr,
input sd_rd_rdy,
input [15:0] sd_rd_data
);
`define DP_MAXBIT 12
`define FPS_MAX 24'd5000000
// --
// internal signals definition
// --
reg buf_rd_valid;
reg buf_rd_rdy;
wire [15:0] buf_rd_data;
wire cfifo_full;
wire cfifo_empty;
reg cfifo_wr;
wire cfifo_wr_nxt;
reg capture_wr;
wire capture_wr_nxt;
reg [`DP_MAXBIT:0] cfifo_wr_cnt;
wire [`DP_MAXBIT:0] cfifo_wr_cnt_nxt;
wire [`DP_MAXBIT:0] cfifo_cnt;
reg [15:0] cfifo_din;
wire [15:0] cfifo_din_nxt;
wire cfifo_rd;
reg cfifo_rd_1T;
wire [15:0] cfifo_dout;
reg [23:0] div_cnt;
wire [23:0] div_cnt_nxt;
reg sample_en_1T;
reg [23:0] fps_cnt;
wire [23:0] fps_cnt_nxt;
assign sd_rd_req = cons_mode ? 1'b0 : rd_req;
assign sd_rd_addr = cons_mode ? 32'b0 : rd_addr;
assign rd_valid = cons_mode ? buf_rd_valid : sd_rd_valid;
assign rd_rdy = cons_mode ? buf_rd_rdy : sd_rd_rdy;
assign rd_data = cons_mode ? buf_rd_data : sd_rd_data;
// --
// detection
// --
reg rising0;
wire rising0_nxt;
reg falling0;
wire falling0_nxt;
reg rising1;
wire rising1_nxt;
reg falling1;
wire falling1_nxt;
reg [16:0] capture_data_1T;
reg [16:0] capture_data_2T;
reg [16:0] capture_data_4T;
reg [16:0] capture_data_8T;
reg [16:0] capture_data_16T;
reg [3:0] slope01_log;
wire [3:0] slope01_log_nxt;
reg [3:0] slope02_log;
wire [3:0] slope02_log_nxt;
reg [3:0] slope04_log;
wire [3:0] slope04_log_nxt;
reg [3:0] slope08_log;
wire [3:0] slope08_log_nxt;
reg [3:0] slope016_log;
wire [3:0] slope016_log_nxt;
reg [3:0] slope11_log;
wire [3:0] slope11_log_nxt;
reg [3:0] slope12_log;
wire [3:0] slope12_log_nxt;
reg [3:0] slope14_log;
wire [3:0] slope14_log_nxt;
reg [3:0] slope18_log;
wire [3:0] slope18_log_nxt;
reg [3:0] slope116_log;
wire [3:0] slope116_log_nxt;
assign slope01_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[7:0] > capture_data_1T[7:0])) ? {slope01_log[2:0], 1'b1} :
(capture_wr & (capture_data[7:0] < capture_data_1T[7:0])) ? {slope01_log[2:0], 1'b0} : slope01_log;
assign slope02_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[7:0] > capture_data_2T[7:0])) ? {slope02_log[2:0], 1'b1} :
(capture_wr & (capture_data[7:0] < capture_data_2T[7:0])) ? {slope02_log[2:0], 1'b0} : slope02_log;
assign slope04_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[7:0] > capture_data_4T[7:0])) ? {slope04_log[2:0], 1'b1} :
(capture_wr & (capture_data[7:0] < capture_data_4T[7:0])) ? {slope04_log[2:0], 1'b0} : slope04_log;
assign slope08_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[7:0] > capture_data_8T[7:0])) ? {slope08_log[2:0], 1'b1} :
(capture_wr & (capture_data[7:0] < capture_data_8T[7:0])) ? {slope08_log[2:0], 1'b0} : slope08_log;
assign slope016_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[7:0] > capture_data_16T[7:0])) ? {slope016_log[2:0], 1'b1} :
(capture_wr & (capture_data[7:0] < capture_data_16T[7:0])) ? {slope016_log[2:0], 1'b0} : slope016_log;
assign slope11_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[15:8] > capture_data_1T[15:8])) ? {slope11_log[2:0], 1'b1} :
(capture_wr & (capture_data[15:8] < capture_data_1T[15:8])) ? {slope11_log[2:0], 1'b0} : slope11_log;
assign slope12_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[15:8] > capture_data_2T[15:8])) ? {slope12_log[2:0], 1'b1} :
(capture_wr & (capture_data[15:8] < capture_data_2T[15:8])) ? {slope12_log[2:0], 1'b0} : slope12_log;
assign slope14_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[15:8] > capture_data_4T[15:8])) ? {slope14_log[2:0], 1'b1} :
(capture_wr & (capture_data[15:8] < capture_data_4T[15:8])) ? {slope14_log[2:0], 1'b0} : slope14_log;
assign slope18_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[15:8] > capture_data_8T[15:8])) ? {slope18_log[2:0], 1'b1} :
(capture_wr & (capture_data[15:8] < capture_data_8T[15:8])) ? {slope18_log[2:0], 1'b0} : slope18_log;
assign slope116_log_nxt = (sample_en & ~sample_en_1T) ? 'b0101 :
(capture_wr & (capture_data[15:8] > capture_data_16T[15:8])) ? {slope116_log[2:0], 1'b1} :
(capture_wr & (capture_data[15:8] < capture_data_16T[15:8])) ? {slope116_log[2:0], 1'b0} : slope116_log;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
capture_data_1T <= `D 'b0;
capture_data_2T <= `D 'b0;
capture_data_4T <= `D 'b0;
capture_data_8T <= `D 'b0;
capture_data_16T <= `D 'b0;
slope01_log <= `D 'b0101;
slope02_log <= `D 'b0101;
slope04_log <= `D 'b0101;
slope08_log <= `D 'b0101;
slope016_log <= `D 'b0101;
slope11_log <= `D 'b0101;
slope12_log <= `D 'b0101;
slope14_log <= `D 'b0101;
slope18_log <= `D 'b0101;
slope116_log <= `D 'b0101;
end else begin
capture_data_1T <= `D capture_wr ? capture_data : capture_data_1T;
capture_data_2T <= `D capture_wr & cfifo_wr_cnt[0] ? capture_data : capture_data_2T;
capture_data_4T <= `D capture_wr & &cfifo_wr_cnt[1:0] ? capture_data : capture_data_4T;
capture_data_8T <= `D capture_wr & &cfifo_wr_cnt[2:0] ? capture_data : capture_data_8T;
capture_data_16T <= `D capture_wr & &cfifo_wr_cnt[3:0] ? capture_data : capture_data_16T;
slope01_log <= `D slope01_log_nxt;
slope02_log <= `D slope02_log_nxt;
slope04_log <= `D slope04_log_nxt;
slope08_log <= `D slope08_log_nxt;
slope016_log <= `D slope016_log_nxt;
slope11_log <= `D slope11_log_nxt;
slope12_log <= `D slope12_log_nxt;
slope14_log <= `D slope14_log_nxt;
slope18_log <= `D slope18_log_nxt;
slope116_log <= `D slope116_log_nxt;
end
end
assign rising0_nxt = &slope01_log | &slope02_log | &slope04_log |
&slope08_log | &slope016_log;
assign rising1_nxt = &slope11_log | &slope12_log | &slope14_log |
&slope18_log | &slope116_log;
assign falling0_nxt = ~|slope01_log | ~|slope02_log | ~|slope04_log |
~|slope08_log | ~|slope016_log;
assign falling1_nxt = ~|slope11_log | ~|slope12_log | ~|slope14_log |
~|slope18_log | ~|slope116_log;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
rising0 <= `D 1'b0;
rising1 <= `D 1'b0;
falling0 <= `D 1'b0;
falling1 <= `D 1'b0;
end else begin
rising0 <= `D rising0_nxt;
rising1 <= `D rising1_nxt;
falling0 <= `D falling0_nxt;
falling1 <= `D falling1_nxt;
end
end
// --
// trigger
// --
reg [`DP_MAXBIT:0] redunt_cnt;
wire [`DP_MAXBIT:0] redunt_cnt_nxt;
reg redunt_rd;
wire redunt_rd_nxt;
wire cfifo_almost_full;
reg buf_rdy;
wire buf_rdy_nxt;
reg buf_rdy_1T;
reg trigger_hit;
wire trigger_hit_nxt;
reg trigger_hit_1T;
reg rising0_hit;
reg falling0_hit;
reg rising1_hit;
reg falling1_hit;
wire rising0_hit_nxt;
wire falling0_hit_nxt;
wire rising1_hit_nxt;
wire falling1_hit_nxt;
reg auto_req;
reg rising0_req;
reg falling0_req;
reg rising1_req;
reg falling1_req;
reg rising0a1_req;
reg falling0a1_req;
reg rising0o1_req;
reg falling0o1_req;
wire auto_req_nxt;
wire rising0_req_nxt;
wire falling0_req_nxt;
wire rising1_req_nxt;
wire falling1_req_nxt;
wire rising0a1_req_nxt;
wire falling0a1_req_nxt;
wire rising0o1_req_nxt;
wire falling0o1_req_nxt;
// -- hit condition
assign rising0_hit_nxt = (capture_data[7:0] >= dso_triggerValue[7:0]) &
(capture_data_1T[7:0] <= dso_triggerValue[7:0]) &
(rising0 | (~rising0 & ~falling0));
assign rising1_hit_nxt = (capture_data[15:8] >= dso_triggerValue[15:8]) &
(capture_data_1T[15:8] <= dso_triggerValue[15:8]) &
(rising1 | (~rising1 & ~falling1));
assign falling0_hit_nxt = (capture_data[7:0] <= dso_triggerValue[7:0]) &
(capture_data_1T[7:0] >= dso_triggerValue[7:0]) &
(falling0 | (~rising0 & ~falling0));
assign falling1_hit_nxt = (capture_data[15:8] <= dso_triggerValue[15:8]) &
(capture_data_1T[15:8] >= dso_triggerValue[15:8]) &
(falling1 | (~rising1 & ~falling1));
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
rising0_hit <= `D 1'b0;
rising1_hit <= `D 1'b0;
falling0_hit <= `D 1'b0;
falling1_hit <= `D 1'b0;
end else begin
rising0_hit <= `D rising0_hit_nxt;
rising1_hit <= `D rising1_hit_nxt;
falling0_hit <= `D falling0_hit_nxt;
falling1_hit <= `D falling1_hit_nxt;
end
end
// -- trigger setting
assign auto_req_nxt = (dso_triggerSource == 'd0);
assign rising0_req_nxt = (dso_triggerSource == 'd1) & (dso_triggerSlope == 'b0);
assign falling0_req_nxt = (dso_triggerSource == 'd1) & (dso_triggerSlope == 'b1);
assign rising1_req_nxt = (dso_triggerSource == 'd2) & (dso_triggerSlope == 'b0);
assign falling1_req_nxt = (dso_triggerSource == 'd2) & (dso_triggerSlope == 'b1);
assign rising0a1_req_nxt = (dso_triggerSource == 'd3) & (dso_triggerSlope == 'b0);
assign falling0a1_req_nxt = (dso_triggerSource == 'd3) & (dso_triggerSlope == 'b1);
assign rising0o1_req_nxt = (dso_triggerSource == 'd4) & (dso_triggerSlope == 'b0);
assign falling0o1_req_nxt = (dso_triggerSource == 'd4) & (dso_triggerSlope == 'b1);
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
auto_req <= `D 1'b0;
rising0_req <= `D 1'b0;
falling0_req <= `D 1'b0;
rising1_req <= `D 1'b0;
falling1_req <= `D 1'b0;
rising0a1_req <= `D 1'b0;
falling0a1_req <= `D 1'b0;
rising0o1_req <= `D 1'b0;
falling0o1_req <= `D 1'b0;
end else begin
auto_req <= `D auto_req_nxt;
rising0_req <= `D rising0_req_nxt;
falling0_req <= `D falling0_req_nxt;
rising1_req <= `D rising1_req_nxt;
falling1_req <= `D falling1_req_nxt;
rising0a1_req <= `D rising0a1_req_nxt;
falling0a1_req <= `D falling0a1_req_nxt;
rising0o1_req <= `D rising0o1_req_nxt;
falling0o1_req <= `D falling0o1_req_nxt;
end
end
assign trigger_hit_nxt = (cfifo_wr & auto_req) ? 1'b1 :
(cfifo_wr & rising0_req & rising0_hit & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & falling0_req & falling0_hit & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & rising1_req & rising1_hit & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & falling1_req & falling1_hit & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & rising0a1_req & rising0_hit & rising1_hit & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & falling0a1_req & falling0_hit & falling1_hit & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & rising0o1_req & (rising0_hit | rising1_hit) & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(cfifo_wr & falling0o1_req & (falling0_hit | falling1_hit) & cfifo_cnt >= dso_triggerPos) ? 1'b1 :
(buf_rdy_1T & ~buf_rdy) ? 1'b0 : trigger_hit;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
trigger_hit <= `D 1'b0;
trigger_hit_1T <= `D 1'b0;
end else begin
trigger_hit <= `D trigger_hit_nxt;
trigger_hit_1T <= `D trigger_hit;
end
end
// -- trigger position processing
assign redunt_rd_nxt = ((trigger_hit & ~trigger_hit_1T) | (redunt_rd & redunt_cnt == 'b10)) ? 1'b0 :
((cfifo_almost_full & ~trigger_hit) | (trigger_hit_1T & redunt_cnt > 'b1)) ? 1'b1 : redunt_rd;
assign redunt_cnt_nxt = (sample_en & ~sample_en_1T) ? dso_triggerPos :
(trigger_hit & ~trigger_hit_1T) ? cfifo_cnt - dso_triggerPos :
(redunt_rd & trigger_hit_1T & redunt_cnt != 'b0) ? redunt_cnt - 1'b1 : redunt_cnt;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
redunt_rd <= `D 1'b0;
redunt_cnt <= `D 'b0;
end else begin
redunt_rd <= `D redunt_rd_nxt;
redunt_cnt <= `D redunt_cnt_nxt;
end
end
assign buf_rdy_nxt = (trigger_hit & redunt_cnt == 'b1 & cfifo_full) ? 1'b1 :
cfifo_empty ? 1'b0 : buf_rdy;
assign cfifo_rd = buf_rdy & ~afifo_prog_full & ~cfifo_empty & ~|fps_cnt;
assign fps_cnt_nxt = ((sample_en & ~sample_en_1T) | (~buf_rdy & buf_rdy_1T)) ? `FPS_MAX :
|fps_cnt ? fps_cnt - 1'b1 : fps_cnt;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
buf_rdy <= `D 1'b0;
buf_rdy_1T <= `D 1'b0;
cfifo_rd_1T <= `D 1'b0;
fps_cnt <= `D 'b0;
end else begin
buf_rdy <= `D buf_rdy_nxt;
buf_rdy_1T <= `D buf_rdy;
cfifo_rd_1T <= `D cfifo_rd;
fps_cnt <= `D fps_cnt_nxt;
end
end
reg [`DP_MAXBIT:0] cfifo_rd_cnt;
wire [`DP_MAXBIT:0] cfifo_rd_cnt_nxt;
assign cfifo_rd_cnt_nxt = cfifo_rd ? cfifo_rd_cnt + 1'b1 :
cfifo_full ? 'b0 : cfifo_rd_cnt;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst)
cfifo_rd_cnt <= `D 'b0;
else
cfifo_rd_cnt <= `D cfifo_rd_cnt_nxt;
end
// --
// continous buffer
// --
always @(posedge core_clk)
begin
sample_en_1T <= `D sample_en;
end
assign div_cnt_nxt = (sample_en & ~sample_en_1T) ? 23'b0 :
(capture_valid & (div_cnt == dso_sampleDivider)) ? 23'b0 :
buf_rdy ? 23'b0 :
(capture_valid & ~buf_rdy) ? div_cnt + 1'b1 : div_cnt;
assign capture_wr_nxt = capture_valid & (div_cnt == dso_sampleDivider);
assign cfifo_wr_nxt = capture_wr_nxt & ~buf_rdy;
assign cfifo_wr_cnt_nxt = (~buf_rdy & buf_rdy_1T) ? 'b0 :
(cfifo_wr & ~&cfifo_wr_cnt) ? cfifo_wr_cnt + 1'b1 : cfifo_wr_cnt;
assign cfifo_din_nxt = capture_data_1T;
always @(posedge core_clk or posedge core_rst)
begin
if (core_rst) begin
div_cnt <= `D 24'b0;
capture_wr <= `D 1'b0;
cfifo_wr <= `D 1'b0;
cfifo_wr_cnt <= `D 'b0;
cfifo_din <= `D 16'b0;
end else begin
div_cnt <= `D div_cnt_nxt;
capture_wr <= `D capture_wr_nxt;
cfifo_wr <= `D cfifo_wr_nxt;
cfifo_wr_cnt <= `D cfifo_wr_cnt_nxt;
cfifo_din <= `D cfifo_din_nxt;
end
end
cfifo cfifo (
.clk(core_clk), // input clk
.rst(core_rst), // input rst
.din(cfifo_din), // input [15 : 0] din
.wr_en(cfifo_wr), // input wr_en
.rd_en(redunt_rd | cfifo_rd), // input rd_en
.dout(cfifo_dout), // output [15 : 0] dout
.full(cfifo_full), // output full
.empty(cfifo_empty), // output empty
.prog_full(cfifo_almost_full),
.data_count(cfifo_cnt)
);
// --
// core --> sdram domain
// --
wire afifo_empty;
wire afifo_full;
wire afifo_prog_empty;
wire afifo_prog_full;
asyncfifo asyncfifo(
.wr_clk(core_clk), // input wr_clk
.wr_rst(core_rst), // input wr_rst
.rd_clk(sdram_clk), // input rd_clk
.rd_rst(sd_rst), // input rd_rst
.din(cfifo_dout), // input [15 : 0] din
.wr_en(cfifo_rd_1T), // input wr_en
.rd_en(rd_req & ~afifo_empty), // input rd_en
.dout(buf_rd_data), // output [15 : 0] dout
.full(afifo_full), // output full
.empty(afifo_empty), // output empty
.prog_full(afifo_prog_full), // output prog_full
.prog_empty(afifo_prog_empty) // output prog_empty
);
always @(posedge sdram_clk or posedge sd_rst)
begin
if (sd_rst) begin
buf_rd_valid <= `D 1'b0;
buf_rd_rdy <= `D 1'b0;
end else begin
buf_rd_valid <= `D rd_req & ~afifo_empty;
buf_rd_rdy <= `D rd_req & ~afifo_empty;
end
end
reg read_rdy;
wire read_rdy_nxt;
reg read_rdy_1T;
assign read_rdy_nxt = afifo_prog_full ? 1'b1 : read_rdy;
always @(posedge sdram_clk or posedge sd_rst)
begin
if (sd_rst) begin
read_rdy <= `D 1'b0;
read_rdy_1T <= `D 1'b0;
end else begin
read_rdy <= `D read_rdy_nxt;
read_rdy_1T <= `D read_rdy;
end
end
assign read_start = ~cons_mode ? wr_done : (read_rdy & ~read_rdy_1T);
endmodule /* module cons_buf (*/
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: cx4_datrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module cx4_datrom (
address,
clock,
q);
input [9:0] address;
input clock;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({24{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "cx4_datrom.mif",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 1024,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 10,
altsyncram_component.width_a = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "cx4_datrom.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
// Retrieval info: PRIVATE: WidthData NUMERIC "24"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "cx4_datrom.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_a 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL cx4_datrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
(** * References: Typing Mutable References *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
Require Export Smallstep.
(** So far, we have considered a variety of _pure_ language features,
including functional abstraction, basic types such as numbers and
booleans, and structured types such as records and variants. These
features form the backbone of most programming languages -- including
purely functional languages such as Haskell, "mostly functional"
languages such as ML, imperative languages such as C, and
object-oriented languages such as Java.
Most practical programming languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, evaluation of terms in these languages may assign to
mutable variables (reference cells, arrays, mutable record fields,
etc.), perform input and output to files, displays, or network
connections, make non-local transfers of control via exceptions,
jumps, or continuations, engage in inter-process synchronization
and communication, and so on. In the literature on programming
languages, such "side effects" of computation are more generally
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational
effect -- mutable references -- can be added to the calculi we have
studied. The main extension will be dealing explicitly with a
_store_ (or _heap_). This extension is straightforward to define;
the most interesting part is the refinement we need to make to the
statement of the type preservation theorem. *)
(* ###################################################################### *)
(** ** Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language is a rare
exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] directly to assign a new
value to the cell that it points to (by writing [y:=84]), but we
cannot use it directly as an argument to an operation like [+].
Instead, we must explicitly _dereference_ it, writing [!y] to
obtain its current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a mutable
cell, and the operation of dereferencing a variable to obtain its
current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit.
In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
(* ###################################################################### *)
(** ** Syntax *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and evaluates to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] evaluates
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. However, [r := 7]
evaluates to the trivial value [unit]; it exists only to have
the _side effect_ of modifying the contents of a cell. *)
(* ################################### *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. To the base natural number type and arrow types
we need to add two more types to deal with references. First, we
need the _unit type_, which we will use as the result type of an
assignment operation. We then add _reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references which
point to a cell holding values of type [T].
T ::= Nat
| Unit
| T -> T
| Ref T
*)
Inductive ty : Type :=
| TNat : ty
| TUnit : ty
| TArrow : ty -> ty -> ty
| TRef : ty -> ty.
(* ################################### *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
<<
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
>>
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* New terms: *)
| tunit : tm
| tref : tm -> tm
| tderef : tm -> tm
| tassign : tm -> tm -> tm
| tloc : nat -> tm.
(** Intuitively...
- [ref t] (formally, [tref t]) allocates a new reference cell
with the value [t] and evaluates to the location of the newly
allocated cell;
- [!t] (formally, [tderef t]) evaluates to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [tassign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [tloc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. It
would be easy to do so, since there are no very interesting
interactions between those features and references. *)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "tzero"
| Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tunit" | Case_aux c "tref"
| Case_aux c "tderef" | Case_aux c "tassign"
| Case_aux c "tloc" ].
Module ExampleVariables.
Definition x := Id 0.
Definition y := Id 1.
Definition r := Id 2.
Definition s := Id 3.
End ExampleVariables.
(* ################################### *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T11
--------------------- (T_Deref)
Gamma |- !t1 : T11
Gamma |- t1 : Ref T11
Gamma |- t2 : T11
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ################################### *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall n,
value (tnat n)
| v_unit :
value tunit
| v_loc : forall l,
value (tloc l).
Hint Constructors value.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tabs x' T t1 =>
if eq_id_dec x x' then t else tabs x' T (subst x s t1)
| tnat n =>
t
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
t
| tref t1 =>
tref (subst x s t1)
| tderef t1 =>
tderef (subst x s t1)
| tassign t1 t2 =>
tassign (subst x s t1) (subst x s t2)
| tloc _ =>
t
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** * Pragmatics *)
(* ################################### *)
(** ** Side Effects and Sequencing *)
(** The fact that the result of an assignment expression is the
trivial value [unit] allows us to use a nice abbreviation for
_sequencing_. For example, we can write
<<
r:=succ(!r); !r
>>
as an abbreviation for
<<
(\x:Unit. !r) (r := succ(!r)).
>>
This has the effect of evaluating two expressions in order and
returning the value of the second. Restricting the type of the first
expression to [Unit] helps the typechecker to catch some silly
errors by permitting us to throw away the first value only if it
is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
<<
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
>>
*)
(** Formally, we introduce sequencing as a "derived form"
[tseq] that expands into an abstraction and an application. *)
Definition tseq t1 t2 :=
tapp (tabs (Id 0) TUnit t2) t1.
(* ################################### *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to [r] and the _cell_ in the store that
is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after evaluating
<<
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
>>
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
<<
r := 5; r := !s
>>
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
<<
r := !s
>>
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ################################### *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
<<
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
>>
*)
(** Note that, since their argument types are [Unit], the
abstractions in the definitions of [incc] and [decc] are not
providing any useful information to the bodies of the
functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose is to
"slow down" the execution of the function bodies: since function
abstractions are values, the two [let]s are executed simply by
binding these functions to the names [incc] and [decc], rather
than by actually incrementing or decrementing [c]. Later, each
call to one of these functions results in its body being executed
once and performing the appropriate mutation on [c]. Such
functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
<<
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
>>
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
<<
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
>>
*)
(** **** Exercise: 1 star (store_draw) *)
(** Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(* 0::0::nil *)
(** [] *)
(* ################################### *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give a (not very efficient) implementation of arrays
of numbers, as follows. Write [NatArray] for the type
[Ref (Nat->Nat)].
Recall the [equal] function from the [MoreStlc] chapter:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
Now, to build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
<<
newarray = \_:Unit. ref (\n:Nat.0)
>>
To look up an element of an array, we simply apply
the function to the desired index.
<<
lookup = \a:NatArray. \n:Nat. (!a) n
>>
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], and on all other indices passes the
lookup to the function that was previously stored in the reference.
<<
update = \a:NatArray. \m:Nat. \v:Nat.
let oldf = !a in
a := (\n:Nat. if equal m n then v else oldf n);
>>
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars (compact_update) *)
(** If we defined [update] more compactly like this
<<
update = \a:NatArray. \m:Nat. \v:Nat.
a := (\n:Nat. if equal m n then v else (!a) n)
>>
would it behave the same? *)
(* It would not behave the same, the difference is in when the
dereference operation will be evaluated. In the case with the
extra let it is evaluated _before_ the new function is
assigned to a. In the later case it is evaluate after it is
bound again, this efectively creates an infinite loop if m
and n are not equal.*)
(** [] *)
(* ################################### *)
(** ** Null References *)
(** There is one more difference between our references and C-style
mutable variables: in C-like languages, variables holding pointers
into the heap may sometimes have the value [NULL]. Dereferencing
such a "null pointer" is an error, and results in an
exception (Java) or in termination of the program (C).
Null pointers cause significant trouble in C-like languages: the
fact that any pointer might be null means that any dereference
operation in the program can potentially fail. However, even in
ML-like languages, there are occasionally situations where we may
or may not have a valid pointer in our hands. Fortunately, there
is no need to extend the basic mechanisms of references to achieve
this: the sum types introduced in the [MoreStlc] chapter already
give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter. Define [Option T] to be an
abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ################################### *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, collecting and reusing cells that can no longer be
reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. The reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Nat] and the
other with type [Ref Bool]. *)
(** **** Exercise: 1 star (type_safety_violation) *)
(** Show how this can lead to a violation of type safety. *)
(* If an existing location is reused for something with a different
type (say Nat) and a dangeling reference exists that assumes that
there is a Bool is stored in its place it will try to use a nat
value in a place where a bool is expected, which in our language
would mean that evaluation would be stuck.
*)
(** [] *)
(* ###################################################################### *)
(** * Operational Semantics *)
(* ################################### *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that evaluating a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming language implementations is
essentially just a big array of bytes. The run-time system keeps track
of which parts of this array are currently in use; when we need to
allocate a new reference cell, we allocate a large enough segment from
the free region of the store (4 bytes for integer cells, 8 bytes for
cells storing [Float]s, etc.), mark it as being used, and return the
index (typically, a 32- or 64-bit integer) of the start of the newly
allocated region. These indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is a bit more convenient
to use numbers.) We'll use the word _location_ instead of
_reference_ or _pointer_ from now on to emphasize this abstract
quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type safety violations. *)
(* ################################### *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
IMP, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in IMP, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we couldn't use this representation
before is that, in IMP, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [tref t1], which puts the value of [t1]
in a new reference cell and evaluates to the location of the newly
created reference cell. When evaluating such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
it will of course require some work!) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st tunit.
(** To add a new reference cell to the store, we use [snoc]. *)
Fixpoint snoc {A:Type} (l:list A) (x:A) : list A :=
match l with
| nil => x :: nil
| h :: t => h :: snoc t x
end.
(** We will need some boring lemmas about [snoc]. The proofs are
routine inductions. *)
Lemma length_snoc : forall A (l:list A) x,
length (snoc l x) = S (length l).
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ]. Qed.
(* The "solve by inversion" tactic is explained in Stlc.v. *)
Lemma nth_lt_snoc : forall A (l:list A) x d n,
n < length l ->
nth n l d = nth n (snoc l x) d.
Proof.
induction l as [|a l']; intros; try solve by inversion.
Case "l = a :: l'".
destruct n; auto.
simpl. apply IHl'.
simpl in H. apply lt_S_n in H. assumption.
Qed.
Lemma nth_eq_snoc : forall A (l:list A) x d,
nth (length l) (snoc l x) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** Of course, we also need some boring lemmas about [replace], which
are also fairly straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x nil = nil.
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
Case "st = []".
inversion Hlen.
Case "st = t' :: st'".
destruct l; simpl...
apply IHst'. simpl in Hlen. omega.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
Case "l1 = 0".
destruct st.
SCase "st = []". rewrite replace_nil...
SCase "st = _ :: _". destruct l2... contradict Hneq...
Case "l1 = S l1'".
destruct st as [|t2 st2].
SCase "st = []". destruct l2...
SCase "st = t2 :: st2".
destruct l2...
simpl; apply IHl1'...
Qed.
(* ################################### *)
(** ** Reduction *)
(** Next, we need to extend our operational semantics to take stores
into account. Since the result of evaluating an expression will
in general depend on the contents of the store in which it is
evaluated, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the evaluation of a
term may cause side effects on the store that may affect the
evaluation of other terms in the future, the evaluation rules need
to return a new store. Thus, the shape of the single-step
evaluation relation changes from [t ==> t'] to [t / st ==> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing evaluation rules with stores:
value v2
-------------------------------------- (ST_AppAbs)
(\x:T.t12) v2 / st ==> [x:=v2]t12 / st
t1 / st ==> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st ==> t1' t2 / st'
value v1 t2 / st ==> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st ==> v1 t2' / st'
Note that the first rule here returns the store unchanged:
function application, in itself, has no side effects. The other two
rules simply propagate side effects from premise to conclusion.
Now, the result of evaluating a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values.
It is crucial to note that making this extension to the syntax of
terms does not mean that we intend _programmers_ to write terms
involving explicit, concrete locations: such terms will arise only
as intermediate results of evaluation. This may initially seem
odd, but really it follows naturally from our design decision to
represent the result of every evaluation step by a modified
term. If we had chosen a more "machine-like" model for evaluation,
e.g. with an explicit stack to contain values of bound
identifiers, then the idea of adding locations to the set of
allowed values would probably seem more obvious.
In terms of this expanded syntax, we can state evaluation rules for
the new constructs that manipulate locations and the store. First, to
evaluate a dereferencing expression [!t1], we must first reduce [t1]
until it becomes a value:
t1 / st ==> t1' / st'
----------------------- (ST_Deref)
!t1 / st ==> !t1' / st'
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to derefence a
location that is larger than the size [|st|] of the currently
allocated store; the evaluation rules simply get stuck in this
case. The type safety properties that we'll establish below
assure us that well-typed terms will never misbehave in this way.)
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st ==> lookup l st / st
Next, to evaluate an assignment expression [t1:=t2], we must first
evaluate [t1] until it becomes a value (a location), and then
evaluate [t2] until it becomes a value (of any sort):
t1 / st ==> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st ==> t1' := t2 / st'
t2 / st ==> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st ==> v1 := t2' / st'
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v2], which we execute by updating the store to make
location [l] contain [v2]:
l < |st|
------------------------------------- (ST_Assign)
loc l := v2 / st ==> unit / [l:=v2]st
The notation [[l:=v2]st] means "the store that maps [l] to [v2]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this evaluation step is just [unit];
the interesting result is the updated store.)
Finally, to evaluate an expression of the form [ref t1], we first
evaluate [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------------- (ST_Ref)
ref t1 / st ==> ref t1' / st'
Then, to evaluate the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v1].
-------------------------------- (ST_RefValue)
ref v1 / st ==> loc |st| / st,v1
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v1] means [snoc st v1].)
Note that these evaluation rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as evaluation proceeds. This does not affect the
correctness of the results of evaluation (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
evaluation), but it means that a naive implementation of our
evaluator might sometimes run out of memory where a more
sophisticated evaluator would be able to continue by reusing
locations whose contents have become garbage.
Formally... *)
Reserved Notation "t1 '/' st1 '==>' t2 '/' st2"
(at level 40, st1 at level 39, t2 at level 39).
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T t12 v2 st,
value v2 ->
tapp (tabs x T t12) v2 / st ==> [x:=v2]t12 / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tapp t1 t2 / st ==> tapp t1' t2 / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tapp v1 t2 / st ==> tapp v1 t2'/ st'
| ST_SuccNat : forall n st,
tsucc (tnat n) / st ==> tnat (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tsucc t1 / st ==> tsucc t1' / st'
| ST_PredNat : forall n st,
tpred (tnat n) / st ==> tnat (pred n) / st
| ST_Pred : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tpred t1 / st ==> tpred t1' / st'
| ST_MultNats : forall n1 n2 st,
tmult (tnat n1) (tnat n2) / st ==> tnat (mult n1 n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st ==> t1' / st' ->
tmult t1 t2 / st ==> tmult t1' t2 / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tmult v1 t2 / st ==> tmult v1 t2' / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st ==> t1' / st' ->
tif0 t1 t2 t3 / st ==> tif0 t1' t2 t3 / st'
| ST_If0_Zero : forall t2 t3 st,
tif0 (tnat 0) t2 t3 / st ==> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
tif0 (tnat (S n)) t2 t3 / st ==> t3 / st
| ST_RefValue : forall v1 st,
value v1 ->
tref v1 / st ==> tloc (length st) / snoc st v1
| ST_Ref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tref t1 / st ==> tref t1' / st'
| ST_DerefLoc : forall st l,
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
| ST_Deref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tderef t1 / st ==> tderef t1' / st'
| ST_Assign : forall v2 l st,
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tassign t1 t2 / st ==> tassign t1' t2 / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tassign v1 t2 / st ==> tassign v1 t2' / st'
where "t1 '/' st1 '==>' t2 '/' st2" := (step (t1,st1) (t2,st2)).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Succ" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Pred" | Case_aux c "ST_MultNats"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_If0" | Case_aux c "ST_If0_Zero"
| Case_aux c "ST_If0_Nonzero" | Case_aux c "ST_RefValue"
| Case_aux c "ST_Ref" | Case_aux c "ST_DerefLoc"
| Case_aux c "ST_Deref" | Case_aux c "ST_Assign"
| Case_aux c "ST_Assign1" | Case_aux c "ST_Assign2" ].
Hint Constructors step.
Definition multistep := (multi step).
Notation "t1 '/' st '==>*' t2 '/' st'" := (multistep (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(* ################################### *)
(** * Typing *)
(** Our contexts for free variables will be exactly the same as for
the STLC, partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ################################### *)
(** ** Store typings *)
(** Having extended our syntax and evaluation rules to accommodate
references, our last job is to write down typing rules for the new
constructs -- and, of course, to check that they are sound.
Naturally, the key question is, "What is the type of a location?"
First of all, notice that we do _not_ need to answer this question
for purposes of typechecking the terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of evaluation; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of an evaluation
sequence, e.g. trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we evaluate a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we evaluate the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we evaluate the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
and all the rest of the typing rules in the system are extended
similarly with stores. The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.
However, there are two problems with this rule. First, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear.
Second, the proposed typing rule for locations may not allow us to
derive anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
<<
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
>>
*)
(** **** Exercise: 2 stars (cyclic_store) *)
(** Can you find a term whose evaluation will create this particular
cyclic store? *)
(*
let a = ref (\x:Nat . x) in
let b = ref (\x:Nat . x) in
a := \x:Nat. (!b) x ;
b := \x:Nat. (!a) x
*)
(** [] *)
(** Both of these problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ ---a finite function
mapping locations to types.
As usual, this _conservative_ typing restriction on allowed
updates means that we will rule out as ill-typed some programs
that could evaluate perfectly well without getting stuck.
*)
(** Just like we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
value stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_Tlookup] function retrieves the type at a particular
index. *)
Definition store_Tlookup (n:nat) (ST:store_ty) :=
nth n ST TUnit.
(** Suppose we are _given_ a store typing [ST] describing the store
[st] in which some term [t] will be evaluated. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we may immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
That is, as long as [l] is a valid location (it is less than the
length of [ST]), we can compute the type of [l] just by looking it
up in [ST]. Typing is again a four-place relation, but it is
parameterized on a store _typing_ rather than a concrete store.
The rest of the typing rules are analogously augmented with store
typings. *)
(* ################################### *)
(** ** The Typing Relation *)
(** We can now give the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T11
------------------------- (T_Deref)
Gamma; ST |- !t1 : T11
Gamma; ST |- t1 : Ref T11
Gamma; ST |- t2 : T11
----------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
*)
Reserved Notation "Gamma ';' ST '|-' t '\in' T" (at level 40).
Inductive has_type : context -> store_ty -> tm -> ty -> Prop :=
| T_Var : forall Gamma ST x T,
Gamma x = Some T ->
Gamma; ST |- (tvar x) \in T
| T_Abs : forall Gamma ST x T11 T12 t12,
(extend Gamma x T11); ST |- t12 \in T12 ->
Gamma; ST |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma ST t1 t2,
Gamma; ST |- t1 \in (TArrow T1 T2) ->
Gamma; ST |- t2 \in T1 ->
Gamma; ST |- (tapp t1 t2) \in T2
| T_Nat : forall Gamma ST n,
Gamma; ST |- (tnat n) \in TNat
| T_Succ : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tsucc t1) \in TNat
| T_Pred : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tpred t1) \in TNat
| T_Mult : forall Gamma ST t1 t2,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in TNat ->
Gamma; ST |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma ST t1 t2 t3 T,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in T ->
Gamma; ST |- t3 \in T ->
Gamma; ST |- (tif0 t1 t2 t3) \in T
| T_Unit : forall Gamma ST,
Gamma; ST |- tunit \in TUnit
| T_Loc : forall Gamma ST l,
l < length ST ->
Gamma; ST |- (tloc l) \in (TRef (store_Tlookup l ST))
| T_Ref : forall Gamma ST t1 T1,
Gamma; ST |- t1 \in T1 ->
Gamma; ST |- (tref t1) \in (TRef T1)
| T_Deref : forall Gamma ST t1 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- (tderef t1) \in T11
| T_Assign : forall Gamma ST t1 t2 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- t2 \in T11 ->
Gamma; ST |- (tassign t1 t2) \in TUnit
where "Gamma ';' ST '|-' t '\in' T" := (has_type Gamma ST t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Unit" | Case_aux c "T_Loc"
| Case_aux c "T_Ref" | Case_aux c "T_Deref"
| Case_aux c "T_Assign" ].
(** Of course, these typing rules will accurately predict the results
of evaluation only if the concrete store used during evaluation
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the STLC: the substitution lemma promises
us that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will evaluate to a final result of type [T] if it yields
any result at all. (We will see later how to formalize an
analogous intuition for stores and store typings.)
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Recall that concrete location
constants arise only in terms that are the intermediate results of
evaluation; they are not in the language that programmers write.
Thus, we can simply typecheck the programmer's terms with respect
to the _empty_ store typing. As evaluation proceeds and new
locations are created, we will always be able to see how to extend
the store typing by looking at the type of the initial values
being placed in newly allocated cells; this intuition is
formalized in the statement of the type preservation theorem
below. *)
(* ################################### *)
(** * Properties *)
(** Our final task is to check that standard type safety properties
continue to hold for the STLC with references. The progress
theorem ("well-typed terms are not stuck") can be stated and
proved almost as for the STLC; we just need to add a few
straightforward cases to the proof, dealing with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ################################### *)
(** ** Well-Typed Stores *)
(** Since we have extended both the evaluation relation (with initial
and final stores) and the typing relation (with a store typing),
we need to change the statement of preservation to include these
parameters. Clearly, though, we cannot just add stores and store
typings without saying anything about how they are related: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
empty; ST |- t' \in T.
Abort.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then evaluate with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
empty; ST |- (store_lookup l st) \in (store_Tlookup l ST)).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. (The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation! This allows us to type circular
stores.) *)
(** **** Exercise: 2 stars (store_not_unique) *)
(** Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
(*
st = [\x:Nat. !(loc 1) x ; \x:Nat. !(loc 0) x]
ST1 = [TArrow TNat TBool ; TArrow TNat TBool]
ST2 = [TArrow TNat TNat ; TArrow TNat TNat]
*)
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Theorem preservation_wrong2 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
empty; ST |- t' \in T.
Abort.
(** This statement is fine for all of the evaluation rules except the
allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st']
includes a binding for a fresh location [l], then [l] cannot be in
the domain of [ST], and it will not be the case that [t']
(which definitely mentions [l]) is typable under [ST]. *)
(* ############################################ *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during evaluation,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_Tlookup l ST' = store_Tlookup l ST.
Proof with auto.
intros l ST ST' Hlen H.
generalize dependent ST'. generalize dependent l.
induction ST as [|a ST2]; intros l Hlen ST' HST'.
Case "nil". inversion Hlen.
Case "cons". unfold store_Tlookup in *.
destruct ST'.
SCase "ST' = nil". inversion HST'.
SCase "ST' = a' :: ST'2".
inversion HST'; subst.
destruct l as [|l'].
SSCase "l = 0"...
SSCase "l = S l'". simpl. apply IHST2...
simpl in Hlen; omega.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
inversion Hlen.
simpl in *.
destruct l; try omega.
apply lt_n_S. apply IHextends. omega.
Qed.
(** Finally, [snoc ST T] extends [ST], and [extends] is reflexive. *)
Lemma extends_snoc : forall ST T,
extends (snoc ST T) ST.
Proof with auto.
induction ST; intros T...
simpl...
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ################################### *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else it is exactly [snoc ST T1], where
[T1] is the type of the value [v1] in the extended store [snoc st
v1], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of evaluation steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ################################### *)
(** ** Substitution lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_succ : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tsucc t1)
| afi_pred : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tpred t1)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_ref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tref t1)
| afi_deref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tderef t1)
| afi_assign1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tassign t1 t2)
| afi_assign2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tassign t1 t2).
Tactic Notation "afi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "afi_var"
| Case_aux c "afi_app1" | Case_aux c "afi_app2" | Case_aux c "afi_abs"
| Case_aux c "afi_succ" | Case_aux c "afi_pred"
| Case_aux c "afi_mult1" | Case_aux c "afi_mult2"
| Case_aux c "afi_if0_1" | Case_aux c "afi_if0_2" | Case_aux c "afi_if0_3"
| Case_aux c "afi_ref" | Case_aux c "afi_deref"
| Case_aux c "afi_assign1" | Case_aux c "afi_assign2" ].
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma ST,
appears_free_in x t ->
Gamma; ST |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros. generalize dependent Gamma. generalize dependent T.
afi_cases (induction H) Case;
intros; (try solve [ inversion H0; subst; eauto ]).
Case "afi_abs".
inversion H1; subst.
apply IHappears_free_in in H8.
rewrite extend_neq in H8; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' ST t T,
Gamma; ST |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma'; ST |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
has_type_cases (induction H) Case; intros...
Case "T_Var".
apply T_Var. symmetry. rewrite <- H...
Case "T_Abs".
apply T_Abs. apply IHhas_type; intros.
unfold extend.
destruct (eq_id_dec x x0)...
Case "T_App".
eapply T_App.
apply IHhas_type1...
apply IHhas_type2...
Case "T_Mult".
eapply T_Mult.
apply IHhas_type1...
apply IHhas_type2...
Case "T_If0".
eapply T_If0.
apply IHhas_type1...
apply IHhas_type2...
apply IHhas_type3...
Case "T_Assign".
eapply T_Assign.
apply IHhas_type1...
apply IHhas_type2...
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x s S t T,
empty; ST |- s \in S ->
(extend Gamma x S); ST |- t \in T ->
Gamma; ST |- ([x:=s]t) \in T.
Proof with eauto.
intros Gamma ST x s S t T Hs Ht.
generalize dependent Gamma. generalize dependent T.
t_cases (induction t) Case; intros T Gamma H;
inversion H; subst; simpl...
Case "tvar".
rename i into y.
destruct (eq_id_dec x y).
SCase "x = y".
subst.
rewrite extend_eq in H3.
inversion H3; subst.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ _ _ _ Hcontra Hs) as [T' HT'].
inversion HT'.
SCase "x <> y".
apply T_Var.
rewrite extend_neq in H3...
Case "tabs". subst.
rename i into y.
destruct (eq_id_dec x y).
SCase "x = y".
subst.
apply T_Abs. eapply context_invariance...
intros. apply extend_shadow.
SCase "x <> x0".
apply T_Abs. apply IHt.
eapply context_invariance...
intros. unfold extend.
destruct (eq_id_dec y x0)...
subst.
rewrite neq_id...
Qed.
(* ################################### *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
empty; ST |- t \in (store_Tlookup l ST) ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
destruct (beq_nat l' l) eqn: Heqll'.
Case "l' = l".
apply beq_nat_true in Heqll'; subst.
rewrite lookup_replace_eq...
Case "l' <> l".
apply beq_nat_false in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ######################################## *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
Gamma; ST |- t \in T ->
Gamma; ST' |- t \in T.
Proof with eauto.
intros. has_type_cases (induction H0) Case; eauto.
Case "T_Loc".
erewrite <- extends_lookup...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well typed with respect to a store typing, then the store extended
with a new term [t] will still be well typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_snoc : forall ST st t1 T1,
store_well_typed ST st ->
empty; ST |- t1 \in T1 ->
store_well_typed (snoc ST T1) (snoc st t1).
Proof with auto.
intros.
unfold store_well_typed in *.
inversion H as [Hlen Hmatch]; clear H.
rewrite !length_snoc.
split...
Case "types match.".
intros l Hl.
unfold store_lookup, store_Tlookup.
apply le_lt_eq_dec in Hl; inversion Hl as [Hlt | Heq].
SCase "l < length st".
apply lt_S_n in Hlt.
rewrite <- !nth_lt_snoc...
apply store_weakening with ST. apply extends_snoc.
apply Hmatch...
rewrite Hlen...
SCase "l = length st".
inversion Heq.
rewrite nth_eq_snoc.
rewrite <- Hlen. rewrite nth_eq_snoc...
apply store_weakening with ST... apply extends_snoc.
Qed.
(* ################################### *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
Theorem preservation : forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
Proof with eauto using store_weakening, extends_refl.
remember (@empty ty) as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
has_type_cases (induction Ht) Case; intros t' HST Hstep;
subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
Case "T_App".
SCase "ST_AppAbs". exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
SCase "ST_App1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_App2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Succ".
SCase "ST_Succ".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Pred".
SCase "ST_Pred".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Mult".
SCase "ST_Mult1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Mult2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_If0".
SCase "ST_If0_1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... split...
Case "T_Ref".
SCase "ST_RefValue".
exists (snoc ST T1).
inversion HST; subst.
split.
apply extends_snoc.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (snoc ST T1))).
apply T_Loc.
rewrite <- H. rewrite length_snoc. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_snoc...
apply store_well_typed_snoc; assumption.
SCase "ST_Ref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Deref".
SCase "ST_DerefLoc".
exists ST. split; try split...
inversion HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst...
SCase "ST_Deref".
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Case "T_Assign".
SCase "ST_Assign".
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
SCase "ST_Assign1".
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
SCase "ST_Assign2".
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
(** **** Exercise: 3 stars (preservation_informal) *)
(** Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
*)
(*
By induction on the derivation of the type of t.
- If the last rule to show that [Gamma; ST |- t \in T] was
T_App we know that there exist [x t12 t2 T1] such that
t = tapp (tabs x T1 t12) t2
[] *)
(* ################################### *)
(** ** Progress *)
(** Fortunately, progress for this system is pretty easy to prove; the
proof is very similar to the proof of progress for the STLC, with
a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
empty; ST |- t \in T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember (@empty ty) as Gamma.
has_type_cases (induction Ht) Case; subst; try solve by inversion...
Case "T_App".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tapp (tabs x T t) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tapp t1' t2). exists st'...
Case "T_Succ".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [ inversion Ht ].
SSCase "t1 is a tnat".
exists (tnat (S n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tsucc t1'). exists st'...
Case "T_Pred".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht ].
SSCase "t1 is a tnat".
exists (tnat (pred n)). exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tpred t1'). exists st'...
Case "T_Mult".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
SSCase "t2 is a value".
inversion Ht2p; subst; try solve [inversion Ht2].
exists (tnat (mult n n0)). exists st...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tmult (tnat n) t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tmult t1' t2). exists st'...
Case "T_If0".
right. destruct IHHt1 as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
SSCase "n = 0". exists t2. exists st...
SSCase "n = S n'". exists t3. exists st...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tif0 t1' t2 t3). exists st'...
Case "T_Ref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tref t1'). exists st'...
Case "T_Deref".
right. destruct IHHt as [Ht1p | Ht1p]...
SCase "t1 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tderef t1'). exists st'...
Case "T_Assign".
right. destruct IHHt1 as [Ht1p|Ht1p]...
SCase "t1 is a value".
destruct IHHt2 as [Ht2p|Ht2p]...
SSCase "t2 is a value".
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H5...
SSCase "t2 steps".
inversion Ht2p as [t2' [st' Hstep]].
exists (tassign t1 t2'). exists st'...
SCase "t1 steps".
inversion Ht1p as [t1' [st' Hstep]].
exists (tassign t1' t2). exists st'...
Qed.
(* ################################### *)
(** * References and Nontermination *)
Section RefsAndNontermination.
Import ExampleVariables.
(** We know that the simply typed lambda calculus is _normalizing_,
that is, every well-typed term can be reduced to a value in a
finite number of steps. What about STLC + references?
Surprisingly, adding references causes us to lose the
normalization property: there exist well-typed terms in the STLC +
references which can continue to reduce forever, without ever
reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
<<
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
>>
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function (\x:Unit.(!r) unit) -- that is, the function which
ignores its argument and calls the function stored in [r] on the
argument [unit]; but of course, that function is itself! To get
the ball rolling we finally execute this function with [(!r)
unit].
*)
Definition loop_fun :=
tabs x TUnit (tapp (tderef (tvar r)) tunit).
Definition loop :=
tapp
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit)))
(tref (tabs x TUnit tunit)).
(** This term is well typed: *)
Lemma loop_typeable : exists T, empty; nil |- loop \in T.
Proof with eauto.
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
unfold extend. simpl. reflexivity. auto.
eapply T_Assign.
eapply T_Var. unfold extend. simpl. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[==>+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [==>*]), except
that it is not reflexive: [t ==>+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition multistep1 := (step_closure step).
Notation "t1 '/' st '==>+' t2 '/' st'" := (multistep1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store [ [r:=(loc 0)]
loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[multi_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply multi_refl]).
Lemma loop_steps_to_loop_fun :
loop / nil ==>*
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop.
reduce.
Qed.
(** Finally, the latter expression reduces in two steps to itself! *)
Lemma loop_fun_step_self :
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil ==>+
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
(** **** Exercise: 4 stars (factorial_ref) *)
(** Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just use the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition fact_inner :=
tabs y TNat (tif0 (tvar y) (tnat 1) (tmult (tvar y) (tapp (tderef (tvar r)) (tpred (tvar y))))).
Definition factorial : tm :=
tapp
(tabs r (TRef (TArrow TNat TNat))
(tabs y TNat
(tseq (tassign (tvar r) fact_inner) (tapp fact_inner (tvar y)))))
(tref (tabs y TNat (tnat 1))).
Lemma factorial_type : empty; nil |- factorial \in (TArrow TNat TNat).
Proof with eauto.
unfold factorial... unfold fact_inner...
apply T_App with (T1:= TRef (TArrow TNat TNat))...
apply T_Abs... apply T_Abs... unfold tseq.
eapply T_App... apply T_Abs...
eapply T_App... apply T_Abs...
apply T_If0... apply T_Mult... eapply T_App... apply T_Deref. apply T_Var...
apply T_Var...
eapply T_Assign... apply T_Var... rewrite extend_neq... rewrite extend_eq... unfold y, r. intro. inversion H.
eapply T_Abs... eapply T_If0... eapply T_Mult... eapply T_App... apply T_Deref. apply T_Var.
rewrite extend_neq... unfold y,r. intro. inversion H.
Qed.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
Lemma factorial_4 : exists st,
tapp factorial (tnat 4) / nil ==>* tnat 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
(** [] *)
(* ################################### *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, optional (garabage_collector) *)
(** Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(** [] *)
End RefsAndNontermination.
End STLCRef.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 14:35:11 11/08/2015
// Design Name:
// Module Name: prf_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module prf_tb( );
reg clk, rst, RegDest_compl, tbclk2x; //clk, rst, write enable, testbench 2x clk
reg [5:0] p_rs, p_rt, p_rd; //reg addresses
reg [31:0] wr_data_in;
wire [31:0] rd_data_rs, rd_data_rt;
phy_reg_file prf(
clk,
rst,
//Read interface
p_rs, //Read Address 1
p_rt, //Read Address 2
rd_data_rs, //Read Data out1
rd_data_rt, //Read Data out2
//Write interface
p_rd, //From CDB.Tag (complete stage)
wr_data_in, //From CDB.Value (complete stage)
RegDest_compl //RegDest from complete stage, it is 1 if this instruction writes register
);
always #5 clk = ~clk;
//always #2.5 tbclk2x = ~tbclk2x;
initial begin
clk = 0;
rst = 1;
RegDest_compl = 0;
p_rs = 6'b0;
p_rt = 6'b0;
p_rd = 6'b0;
wr_data_in = 32'h0;
@(posedge clk);
repeat (2) @(posedge clk); //rst needs to be asserted for 3 cycles
@(negedge clk) rst = 0;
repeat (10) @(posedge clk); //wait 10 clk cycles before clk2x is valid
p_rs = 6'h1;
@(posedge clk)
wr_data_in = 32'hDEADBEEF;
RegDest_compl = 1'b1;
p_rs = 6'h0;
@(posedge clk) //RegDest_compl = 1'b0;
p_rt = 6'h2;
p_rd = 6'h4;
p_rs = 6'h4;
wr_data_in = 32'habababab;
@(posedge clk) RegDest_compl = 1'b0;
//repeat (3) @(posedge clk);
//p_rt = 6'h0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
bit global_bit;
module t (clk);
input clk;
integer cyc=0;
typedef struct packed {
bit b1;
bit b0;
} strp_t;
typedef struct packed {
strp_t x1;
strp_t x0;
} strp_strp_t;
typedef union packed {
strp_t x1;
strp_t x0;
} unip_strp_t;
typedef bit [2:1] arrp_t;
typedef arrp_t [4:3] arrp_arrp_t;
typedef strp_t [4:3] arrp_strp_t;
typedef bit arru_t [2:1];
typedef arru_t arru_arru_t [4:3];
typedef arrp_t arru_arrp_t [4:3];
typedef strp_t arru_strp_t [4:3];
strp_t v_strp;
strp_strp_t v_strp_strp;
unip_strp_t v_unip_strp;
arrp_t v_arrp;
arrp_arrp_t v_arrp_arrp;
arrp_strp_t v_arrp_strp;
arru_t v_arru;
arru_arru_t v_arru_arru;
arru_arrp_t v_arru_arrp;
arru_strp_t v_arru_strp;
real v_real;
real v_arr_real [2];
string v_string;
typedef struct packed {
logic [31:0] data;
} str32_t;
str32_t [1:0] v_str32x2; // If no --trace-struct, this packed array is traced as 63:0
initial v_str32x2[0] = 32'hff;
initial v_str32x2[1] = 0;
typedef enum int { ZERO=0, ONE, TWO, THREE } enumed_t;
enumed_t v_enumed;
enumed_t v_enumed2;
typedef enum logic [2:0] { BZERO=0, BONE, BTWO, BTHREE } enumb_t;
enumb_t v_enumb;
p #(.PARAM(2)) p2 ();
p #(.PARAM(3)) p3 ();
always @ (posedge clk) begin
cyc <= cyc + 1;
v_strp <= ~v_strp;
v_strp_strp <= ~v_strp_strp;
v_unip_strp <= ~v_unip_strp;
v_arrp_strp <= ~v_arrp_strp;
v_arrp <= ~v_arrp;
v_arrp_arrp <= ~v_arrp_arrp;
v_real <= v_real + 0.1;
v_string <= cyc[0] ? "foo" : "bar";
v_arr_real[0] <= v_arr_real[0] + 0.2;
v_arr_real[1] <= v_arr_real[1] + 0.3;
v_enumed <= v_enumed + 1;
v_enumed2 <= v_enumed2 + 2;
v_enumb <= v_enumb - 1;
for (integer b=3; b<=4; b++) begin
v_arru[b] <= ~v_arru[b];
v_arru_strp[b] <= ~v_arru_strp[b];
v_arru_arrp[b] <= ~v_arru_arrp[b];
for (integer a=3; a<=4; a++) begin
v_arru_arru[a][b] = ~v_arru_arru[a][b];
end
end
v_str32x2[0] <= v_str32x2[0] - 1;
v_str32x2[1] <= v_str32x2[1] + 1;
if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module p;
parameter PARAM = 1;
initial global_bit = 1;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V
/**
* dfstp: Delay flop, inverted set, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_ps_pp_pg_n/sky130_fd_sc_ls__udp_dff_ps_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dfstp (
Q ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire SET ;
reg notifier ;
wire D_delayed ;
wire SET_B_delayed;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (SET , SET_B_delayed );
sky130_fd_sc_ls__udp_dff$PS_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, SET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( SET_B_delayed === 1'b1 );
assign cond1 = ( SET_B === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DFSTP_BEHAVIORAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A31OI_2_V
`define SKY130_FD_SC_HS__A31OI_2_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a31oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31oi_2 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a31oi_2 (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a31oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A31OI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_PP_V
/**
* srsdfxtp: Scan flop with sleep mode, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`include "../../models/udp_dff_p_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_p_pp_pkg_sn.v"
`celldefine
module sky130_fd_sc_lp__srsdfxtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
wire mux_out ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$P_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( SLEEP_B === 1'b0 );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFXTP_BEHAVIORAL_PP_V |
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: jbi_min_rq_issue.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
/////////////////////////////////////////////////////////////////////////
/*
// Description: Request Issue Block (Control logic)
// Top level Module: jbi_min_rq_issue
// Where Instantiated: jbi_min_rq
//
*/
////////////////////////////////////////////////////////////////////////
// Global header file includes
////////////////////////////////////////////////////////////////////////
`include "sys.h" // system level definition file which contains the
// time scale definition
`include "iop.h"
`include "jbi.h"
module jbi_min_rq_issue (/*AUTOARG*/
// Outputs
issue_rhq_pop, issue_rdq_pop, rhq_rdata_rw, issue_biq_data_pop,
issue_biq_hdr_pop, jbi_sctag_req_vld, jbi_sctag_req, jbi_scbuf_ecc,
// Inputs
clk, rst_l, cpu_clk, cpu_rst_l, cpu_rx_en, csr_jbi_config2_max_wris,
rhq_drdy, rhq_rdata, rdq_rdata, biq_drdy, biq_rdata_data,
biq_rdata_ecc, sctag_jbi_iq_dequeue, sctag_jbi_wib_dequeue
);
input clk;
input rst_l;
input cpu_clk;
input cpu_rst_l;
input cpu_rx_en;
// CSR Interface
input [1:0] csr_jbi_config2_max_wris;
// Request Header Queue Interface
input rhq_drdy;
input [`JBI_RHQ_WIDTH-1:0] rhq_rdata;
output issue_rhq_pop;
// Request Data Queue Interface
input [`JBI_RDQ_WIDTH-1:0] rdq_rdata;
output issue_rdq_pop;
output rhq_rdata_rw;
// BSC Inbound Queue Interface
input biq_drdy;
input [`JBI_BIQ_DATA_WIDTH-1:0] biq_rdata_data;
input [`JBI_BIQ_ECC_WIDTH-1:0] biq_rdata_ecc;
output issue_biq_data_pop;
output issue_biq_hdr_pop;
// SCTAG Interface
input sctag_jbi_iq_dequeue;
input sctag_jbi_wib_dequeue;
output jbi_sctag_req_vld;
output [31:0] jbi_sctag_req;
output [6:0] jbi_scbuf_ecc;
////////////////////////////////////////////////////////////////////////
// Interface signal type declarations
////////////////////////////////////////////////////////////////////////
wire issue_rhq_pop;
wire rhq_rdata_rw;
wire issue_rdq_pop;
wire issue_biq_data_pop;
wire issue_biq_hdr_pop;
wire jbi_sctag_req_vld;
wire [31:0] jbi_sctag_req;
wire [6:0] jbi_scbuf_ecc;
////////////////////////////////////////////////////////////////////////
// Local signal declarations
////////////////////////////////////////////////////////////////////////
parameter POP_IDLE = 8'b00000001,
POP_HDR0 = 8'b00000010,
POP_HDR1 = 8'b00000100,
POP_WRI_D = 8'b00001000,
POP_WRM_D0 = 8'b00010000,
POP_WRM_D1 = 8'b00100000,
POP_RD_WAIT0 = 8'b01000000,
POP_RD_WAIT1 = 8'b10000000;
parameter POP_IDLE_BIT = 0,
POP_HDR0_BIT = 1,
POP_HDR1_BIT = 2,
POP_WRI_D_BIT = 3,
POP_WRM_D0_BIT = 4,
POP_WRM_D1_BIT = 5,
POP_SM_WIDTH = 8;
//
// Code start here
//
wire [POP_SM_WIDTH-1:0] pop_sm;
wire driving_bsc;
wire priority_bsc;
wire [3:0] pop_data_cnt;
wire [1:0] ib_cnt;
wire [2:0] wib_cnt;
wire pop_ib;
wire incr_wib_cnt;
reg [POP_SM_WIDTH-1:0] next_pop_sm;
wire next_driving_bsc;
reg next_priority_bsc;
reg [3:0] next_pop_data_cnt;
reg [1:0] next_iq_cnt;
reg [2:0] next_wib_cnt;
wire next_pop_ib;
wire next_incr_wib_cnt;
wire pop_data_cnt_en;
wire driving_bsc_en;
wire sctag_jbi_iq_dequeue_ff;
wire sctag_jbi_wib_dequeue_ff;
wire next_jbi_sctag_req_vld;
reg [31:0] next_jbi_sctag_req;
reg [6:0] next_jbi_scbuf_ecc;
wire bsc_drdy_ok;
wire rhq_drdy_ok;
wire driving_data;
wire stall_ib;
wire stall_wib;
wire issue_txn;
reg [31:0] biq_data;
reg [6:0] biq_ecc;
reg [3:0] pop_data_sel;
wire [31:0] rq_wr_data;
wire [6:0] rq_ecc;
reg [31:0] rq_hdr;
reg [31:0] rq_data;
wire biq_rdata_rw;
wire [2:0] rhq_rdata_req;
wire [11:0] rhq_rdata_tag;
wire [2:0] next_jbi_sctag_req_req;
wire jbi_sctag_req_vld_dup;
wire [1:0] csr_jbi_config2_max_wris_ff;
wire [1:0] c_csr_jbi_config2_max_wris;
//*******************************************************************************
// Pop Transaction From Request Queue
//*******************************************************************************
// Pop State Machine
always @ ( /*AUTOSENSE*/biq_rdata_rw or driving_bsc or issue_txn
or pop_data_cnt or pop_sm or rhq_rdata_req or rhq_rdata_rw) begin
case (pop_sm)
POP_IDLE: begin
if (issue_txn)
next_pop_sm = POP_HDR0;
else
next_pop_sm = POP_IDLE;
end
POP_HDR0: next_pop_sm = POP_HDR1;
POP_HDR1: begin
if ( ( driving_bsc & biq_rdata_rw)
| (~driving_bsc & rhq_rdata_rw))
next_pop_sm = POP_RD_WAIT0;
else if (~driving_bsc
& rhq_rdata_req[`JBI_SCTAG_REQ_WR8_BIT])
next_pop_sm = POP_WRM_D0;
else
next_pop_sm = POP_WRI_D;
end
POP_WRI_D: begin
if (&pop_data_cnt[3:0])
next_pop_sm = POP_IDLE;
else
next_pop_sm = POP_WRI_D;
end
POP_WRM_D0: next_pop_sm = POP_WRM_D1;
POP_WRM_D1: next_pop_sm = POP_IDLE;
POP_RD_WAIT0: next_pop_sm = POP_RD_WAIT1;
POP_RD_WAIT1: next_pop_sm = POP_IDLE;
// CoverMeter line_off
default: begin
next_pop_sm = {POP_SM_WIDTH{1'bx}};
//synopsys translate_off
$dispmon ("jbi_min_rq_issue", 49,"%d %m: pop_sm=%b", $time, pop_sm);
//synopsys translate_on
end
// CoverMeter line_on
endcase
end
assign driving_data = pop_sm[POP_WRI_D_BIT]
| pop_sm[POP_WRM_D0_BIT]
| pop_sm[POP_WRM_D1_BIT];
assign pop_data_cnt_en = pop_sm[POP_HDR1_BIT] | driving_data;
always @ ( /*AUTOSENSE*/driving_bsc or pop_data_cnt or pop_sm
or rhq_rdata) begin
if (pop_sm[POP_HDR1_BIT]) begin
// CoverMeter line_off
if (driving_bsc)
next_pop_data_cnt = 4'd0;
// CoverMeter line_on
else
next_pop_data_cnt = {rhq_rdata[5:3], 1'b0};
end
else
next_pop_data_cnt = pop_data_cnt + 1'b1;
end
assign issue_rhq_pop = pop_sm[POP_HDR0_BIT]
& rhq_drdy_ok
& ~driving_bsc;
assign issue_rdq_pop = ~driving_bsc
& ( (pop_data_cnt[1:0] == 2'd2 // pop data after every quadword
& pop_sm[POP_WRI_D_BIT]) // and allow for 2cycle delay
| pop_sm[POP_WRM_D0_BIT]);
assign issue_biq_data_pop = ~pop_data_cnt[0] // pop data after every double word
& driving_data // and allow for 2cycle delay
& driving_bsc;
assign issue_biq_hdr_pop = pop_sm[POP_HDR0_BIT] // pop header
& bsc_drdy_ok
& driving_bsc;
//*******************************************************************************
// Arbitration
// - round robin
//*******************************************************************************
assign biq_rdata_rw = biq_rdata_data[`JBI_SCTAG_IN_RSV0_RW];
assign rhq_rdata_req = rhq_rdata[`JBI_SCTAG_IN_REQ_HI:`JBI_SCTAG_IN_REQ_LO];
assign rhq_rdata_tag = rhq_rdata[`JBI_SCTAG_IN_TAG_HI:`JBI_SCTAG_IN_TAG_LO];
assign rhq_rdata_rw = rhq_rdata_tag[`JBI_SCTAG_TAG_RW];
assign bsc_drdy_ok = biq_drdy
& ~stall_ib
& ~(stall_wib & ~biq_rdata_rw);
assign rhq_drdy_ok = rhq_drdy
& ~stall_ib
& ~(stall_wib & rhq_rdata_req[`JBI_SCTAG_REQ_WRI_BIT]);
assign issue_txn = bsc_drdy_ok | rhq_drdy_ok;
assign driving_bsc_en = next_pop_sm[POP_HDR0_BIT];
assign next_driving_bsc = bsc_drdy_ok
& ( priority_bsc
| ~rhq_drdy_ok);
always @ ( /*AUTOSENSE*/driving_bsc_en or next_driving_bsc
or priority_bsc) begin
if (driving_bsc_en)
next_priority_bsc = ~next_driving_bsc;
else
next_priority_bsc = priority_bsc;
end
//*******************************************************************************
// Flow Control
//*******************************************************************************
//----------------------------------------
// ?Invalidate? Buffer (IB)
// - applies to WRI, WR8, and RDD
//----------------------------------------
assign next_pop_ib = next_jbi_sctag_req_vld;
always @ ( /*AUTOSENSE*/cpu_rst_l or ib_cnt or pop_ib
or sctag_jbi_iq_dequeue_ff) begin
if (~cpu_rst_l)
next_iq_cnt = 2'd2;
else begin
case({sctag_jbi_iq_dequeue_ff, pop_ib})
2'b00,
2'b11: next_iq_cnt = ib_cnt;
2'b01: next_iq_cnt = ib_cnt - 1'b1;
2'b10: next_iq_cnt = ib_cnt + 1'b1;
// CoverMeter line_off
default: begin
next_iq_cnt = 2'bxx;
//synopsys translate_off
$dispmon ("jbi_min_rq_issue", 49,"%d %m: sctag_jbi_iq_dequeue_ff=%b pop_ib=%b",
$time, sctag_jbi_iq_dequeue_ff, pop_ib);
//synopsys translate_on
end
// CoverMeter line_on
endcase
end
end
assign stall_ib = ib_cnt == 2'd0;
//----------------------------------------
// Write Invalidate Buffer (WIB)
// - applies to WRI
//----------------------------------------
assign next_jbi_sctag_req_req[2:0] = next_jbi_sctag_req[`JBI_SCTAG_IN_REQ_HI-32:`JBI_SCTAG_IN_REQ_LO-32];
assign next_incr_wib_cnt= jbi_sctag_req_vld_dup
& next_jbi_sctag_req_req[`JBI_SCTAG_REQ_WRI_BIT];
always @ ( /*AUTOSENSE*/incr_wib_cnt or sctag_jbi_wib_dequeue_ff
or wib_cnt) begin
case({incr_wib_cnt, sctag_jbi_wib_dequeue_ff})
2'b00,
2'b11: next_wib_cnt = wib_cnt;
2'b01: next_wib_cnt = wib_cnt - 1'b1;
2'b10: next_wib_cnt = wib_cnt + 1'b1;
default: begin
next_wib_cnt = 3'bxxx;
//synopsys translate_off
$dispmon ("jbi_min_rq_issue", 49,"%d %m: sctag_jbi_wib_dequeue_ff=%b incr_wib_cnt=%b",
$time, sctag_jbi_wib_dequeue_ff, incr_wib_cnt);
//synopsys translate_on
end
endcase
end
assign stall_wib = wib_cnt > {1'b0, c_csr_jbi_config2_max_wris[1:0]};
//*******************************************************************************
// Mux SCTAG Data
//*******************************************************************************
//----------------------------------------
// BSC data
//----------------------------------------
always @ ( /*AUTOSENSE*/biq_rdata_data or biq_rdata_ecc
or driving_data or pop_data_cnt or pop_sm) begin
if ( (driving_data & pop_data_cnt[0])
| pop_sm[POP_HDR1_BIT]) begin
biq_data = biq_rdata_data[31:0];
biq_ecc = biq_rdata_ecc[6:0];
end
else begin
biq_data = biq_rdata_data[63:32];
biq_ecc = biq_rdata_ecc[13:7];
end
end
//----------------------------------------
// RQ data
//----------------------------------------
// WRI/WR8 data
always @ ( /*AUTOSENSE*/pop_data_cnt) begin
case(pop_data_cnt[1:0])
2'b00: pop_data_sel = 4'b0001;
2'b01: pop_data_sel = 4'b0010;
2'b10: pop_data_sel = 4'b0100;
2'b11: pop_data_sel = 4'b1000;
// CoverMeter line_off
default: pop_data_sel = {4{1'bx}};
// CoverMeter line_on
endcase
end
mux4ds #(32) u_mux4ds_rq_wr_data
(.dout(rq_wr_data),
.in0(rdq_rdata[127:96]),
.in1(rdq_rdata[ 95:64]),
.in2(rdq_rdata[ 63:32]),
.in3(rdq_rdata[ 31: 0]),
.sel0(pop_data_sel[0]),
.sel1(pop_data_sel[1]),
.sel2(pop_data_sel[2]),
.sel3(pop_data_sel[3])
);
mux4ds #(7) u_mux4ds_rq_ecc
(.dout(rq_ecc),
.in0(rdq_rdata[155:149]),
.in1(rdq_rdata[148:142]),
.in2(rdq_rdata[141:135]),
.in3(rdq_rdata[134:128]),
.sel0(pop_data_sel[0]),
.sel1(pop_data_sel[1]),
.sel2(pop_data_sel[2]),
.sel3(pop_data_sel[3])
);
// header
always @ ( /*AUTOSENSE*/pop_sm or rhq_rdata) begin
if (pop_sm[POP_HDR1_BIT])
rq_hdr = rhq_rdata[31:0];
else
rq_hdr = rhq_rdata[63:32];
end
always @ ( /*AUTOSENSE*/driving_data or rq_hdr or rq_wr_data) begin
if (driving_data)
rq_data = rq_wr_data;
else
rq_data = rq_hdr;
end
//----------------------------------------
// SCTAG Data
//----------------------------------------
always @ ( /*AUTOSENSE*/biq_data or biq_ecc or driving_bsc or rq_data
or rq_ecc) begin
// CoverMeter line_off
if (driving_bsc) begin
next_jbi_sctag_req = biq_data;
next_jbi_scbuf_ecc = biq_ecc;
end
// CoverMeter line_on
else begin
next_jbi_sctag_req = rq_data;
next_jbi_scbuf_ecc = rq_ecc;
end
end
assign next_jbi_sctag_req_vld = next_pop_sm[POP_HDR0_BIT];
//*******************************************************************************
// Synchronization DFFRLEs
//*******************************************************************************
//----------------------
// JBUS -> CPU
//----------------------
// csr_jbi_config2_max_wris
dffrl_ns #(2) u_dffrl_csr_jbi_config2_max_wris_ff
(.din(csr_jbi_config2_max_wris),
.clk(clk),
.rst_l(rst_l),
.q(csr_jbi_config2_max_wris_ff)
);
dffrle_ns #(2) u_dffrle_c_csr_jbi_config2_max_wris
(.din(csr_jbi_config2_max_wris_ff),
.clk(cpu_clk),
.en(cpu_rx_en),
.rst_l(cpu_rst_l),
.q(c_csr_jbi_config2_max_wris)
);
//*******************************************************************************
// DFF Instantiations
//*******************************************************************************
dff_ns #(2) u_dff_iq_cnt
(.din(next_iq_cnt),
.clk(cpu_clk),
.q(ib_cnt)
);
dff_ns #(1) u_dff_sctag_jbi_iq_dequeue_ff
(.din(sctag_jbi_iq_dequeue),
.clk(cpu_clk),
.q(sctag_jbi_iq_dequeue_ff)
);
dff_ns #(1) u_dff_sctag_jbi_wib_dequeue_ff
(.din(sctag_jbi_wib_dequeue),
.clk(cpu_clk),
.q(sctag_jbi_wib_dequeue_ff)
);
dff_ns #(32) u_dff_jbi_sctag_req
(.din(next_jbi_sctag_req),
.clk(cpu_clk),
.q(jbi_sctag_req)
);
dff_ns #(7) u_dff_jbi_scbuf_ecc
(.din(next_jbi_scbuf_ecc),
.clk(cpu_clk),
.q(jbi_scbuf_ecc)
);
//*******************************************************************************
// DFFRL Instantiations
//*******************************************************************************
dffrl_ns #(POP_SM_WIDTH-1) u_dff_pop_sm
(.din(next_pop_sm[POP_SM_WIDTH-1:1]),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(pop_sm[POP_SM_WIDTH-1:1])
);
dffsl_ns #(1) u_dff_pop_sm0
(.din(next_pop_sm[POP_IDLE_BIT]),
.clk(cpu_clk),
.set_l(cpu_rst_l),
.q(pop_sm[POP_IDLE_BIT])
);
dffrl_ns #(1) u_dffrl_priority_bsc
(.din(next_priority_bsc),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(priority_bsc)
);
dffrl_ns #(1) u_dffrl_pop_ib
(.din(next_pop_ib),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(pop_ib)
);
dffrl_ns #(1) u_dffrl_incr_wib_cnt
(.din(next_incr_wib_cnt),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(incr_wib_cnt)
);
dffrl_ns #(1) u_dffrl_jbi_sctag_req_vld
(.din(next_jbi_sctag_req_vld),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(jbi_sctag_req_vld)
);
dffrl_ns #(1) u_dffrl_jbi_sctag_req_vld_dup
(.din(next_jbi_sctag_req_vld),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(jbi_sctag_req_vld_dup)
);
dffrl_ns #(3) u_dffrl_wib_cnt
(.din(next_wib_cnt),
.clk(cpu_clk),
.rst_l(cpu_rst_l),
.q(wib_cnt)
);
//*******************************************************************************
// DFFRLE Instantiations
//*******************************************************************************
dffrle_ns #(4) u_dffrle_pop_data_cnt
(.din(next_pop_data_cnt),
.clk(cpu_clk),
.en(pop_data_cnt_en),
.rst_l(cpu_rst_l),
.q(pop_data_cnt)
);
dffrle_ns #(1) u_dffrle_driving_bsc
(.din(next_driving_bsc),
.clk(cpu_clk),
.en(driving_bsc_en),
.rst_l(cpu_rst_l),
.q(driving_bsc)
);
//*******************************************************************************
// Rule Checks
//*******************************************************************************
//synopsys translate_off
//-------------------------------
always @ ( /*AUTOSENSE*/driving_bsc or pop_sm) begin
@cpu_clk;
if (pop_sm[POP_WRM_D0_BIT] && driving_bsc)
$dispmon ("jbi_min_rq_issue", 49,"%d %m: ERROR - thinks bsc is driving WRM txn", $time);
end
//-------------------------------
always @ ( /*AUTOSENSE*/driving_bsc or next_pop_sm or pop_sm
or rhq_rdata) begin
@cpu_clk;
if (pop_sm[POP_HDR1_BIT]
&& next_pop_sm[POP_WRI_D_BIT]
&& ~driving_bsc
&& rhq_rdata[5:0] != 6'd0)
$dispmon ("jbi_min_rq_issue", 49,"%d %m: ERROR - WRI addr from Jbus not cacheline alligned",
$time);
end
//synopsys translate_on
endmodule
// Local Variables:
// verilog-library-directories:(".")
// verilog-auto-sense-defines-constant:t
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr_pp_pg_n/sky130_fd_sc_hd__udp_dff_nsr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfbbp (
Q ,
Q_N ,
D ,
CLK ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input CLK ;
input SET_B ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire RESET ;
wire SET ;
wire buf_Q ;
wire CLK_delayed ;
wire RESET_B_delayed;
wire SET_B_delayed ;
reg notifier ;
wire D_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire condb ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (SET , SET_B_delayed );
sky130_fd_sc_hd__udp_dff$NSR_pp$PG$N dff0 (buf_Q , SET, RESET, CLK_delayed, D_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( SET_B_delayed === 1'b1 ) );
assign condb = ( cond0 & cond1 );
buf buf0 (Q , buf_Q );
not not2 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFBBP_BEHAVIORAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:40:21 03/23/2015
// Design Name:
// Module Name: serial_interface
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module serial_interface #(
parameter CLK_RATE = 50000000,
parameter SERIAL_BAUD_RATE = 500000
)(
input clk,
input rst,
//Serial Signals
output tx,
input rx,
// Serial TX User Interface
input [7:0] tx_data,
input new_tx_data,
output tx_busy,
input tx_block,
// Serial Rx User Interface
output [7:0] rx_data,
output new_rx_data
);
// CLK_PER_BIT is the number of cycles each 'bit' lasts for
// rtoi converts a 'real' number to an 'integer'
parameter CLK_PER_BIT = $rtoi($ceil(CLK_RATE/SERIAL_BAUD_RATE));
serial_rx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_rx (
.clk(clk),
.rst(rst),
.rx(rx),
.data(rx_data),
.new_data(new_rx_data)
);
serial_tx #(.CLK_PER_BIT(CLK_PER_BIT)) serial_tx (
.clk(clk),
.rst(rst),
.tx(tx),
.block(tx_block),
.busy(tx_busy),
.data(tx_data),
.new_data(new_tx_data)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__UDP_DFF_P_TB_V
`define SKY130_FD_SC_HVL__UDP_DFF_P_TB_V
/**
* udp_dff$P: Positive edge triggered D flip-flop (Q output UDP).
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hvl__udp_dff_p.v"
module top();
// Inputs are registered
reg D;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
#20 D = 1'b0;
#40 D = 1'b1;
#60 D = 1'b0;
#80 D = 1'b1;
#100 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_hvl__udp_dff$P dut (.D(D), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__UDP_DFF_P_TB_V
|
module FreqCounter(rst_n, clk, refer, ready, sck, cs, miso);
input rst_n, clk, refer, sck, cs;
output miso;
output ready;
wire [31:0] sum;
wire [31:0] latchedSum;
Counter counter(rst_n, clk, refer, sum);
D_FF dff(rst_n, refer, cs, sum, latchedSum);
SpiSlave spi(rst_n, latchedSum, sck, cs, miso);
assign ready = refer;
endmodule
// Counter
module Counter(rst_n, clk, clr, sum);
input rst_n, clk, clr;
output reg [31:0] sum;
reg lastClr;
always @(negedge rst_n or posedge clk)
begin
if (~rst_n)
begin
sum <= 32'b0;
lastClr <= 1'b0;
end
else
if (clr && lastClr == ~clr)
begin // posedge clr
sum <= 32'b0;
lastClr <= clr;
end
else
begin
sum <= sum + 32'b1;
lastClr <= clr;
end
end
endmodule
// DFF
module D_FF(rst_n, trig, en, d, q);
input rst_n, trig, en;
input [31:0] d;
output reg [31:0] q;
always @(negedge rst_n or posedge trig)
begin
if (~rst_n)
q <= 32'b0;
else
begin
if (en)
q <= d;
else
q <= q;
end
end
endmodule
// SPI Slave
// MSB first, CPOL = 1, CPHA = 1
module SpiSlave(rst_n, sum, sck, cs, miso);
input rst_n, sck, cs;
input [31:0] sum;
output reg miso;
reg [4:0] i;
always @(negedge rst_n or posedge cs or negedge sck)
begin
if (~rst_n)
begin
miso <= 1'b0;
i <= 5'b11111;
end
else if (cs)
begin
miso <= 1'b0;
i <= 5'b11111;
end
else // if (~cs)
begin
miso <= sum[i];
i <= i - 5'b1;
end
end
endmodule
|
/*
########################################################################
EPIPHANY eMesh Arbiter
########################################################################
This block takes three FIFO inputs (write, read request, read response)
and the DMA channel, arbitrates between the active channels, and forwards
the result to the transmit output pins.
Arbitration Priority:
1) host writes (highest)
2) read requests from host
3) read responses
*/
module etx_arbiter (/*AUTOARG*/
// Outputs
txwr_wait, txrd_wait, txrr_wait, etx_access, etx_packet, etx_rr,
// Inputs
clk, reset, txwr_access, txwr_packet, txrd_access, txrd_packet,
txrr_access, txrr_packet, etx_rd_wait, etx_wr_wait, etx_cfg_wait,
ctrlmode_bypass, ctrlmode
);
parameter PW = 104;
parameter ID = 0;
//tx clock and reset
input clk;
input reset;
//Write Request (from slave)
input txwr_access;
input [PW-1:0] txwr_packet;
output txwr_wait;
//Read Request (from slave)
input txrd_access;
input [PW-1:0] txrd_packet;
output txrd_wait;
//Read Response (from master)
input txrr_access;
input [PW-1:0] txrr_packet;
output txrr_wait;
//Wait signal inputs
input etx_rd_wait;
input etx_wr_wait;
input etx_cfg_wait;
//ctrlmode for rd/wr transactions
input ctrlmode_bypass;
input [3:0] ctrlmode;
//Transaction for IO protocol
output etx_access;
output [PW-1:0] etx_packet;
output etx_rr; //bypass translation on read response
//regs
reg etx_access;
reg [PW-1:0] etx_packet;
reg etx_rr; //bypass translation on read response
//wires
wire [3:0] txrd_ctrlmode;
wire [3:0] txwr_ctrlmode;
wire access_in;
wire [PW-1:0] etx_packet_mux;
wire txrr_grant;
wire txrd_grant;
wire txwr_grant;
wire txrr_arb_wait;
wire txrd_arb_wait;
wire txwr_arb_wait;
wire [PW-1:0] txrd_data;
wire [PW-1:0] txwr_data;
wire [PW-1:0] etx_mux;
wire write_in;
//##########################################################################
//# Insert special control mode
//##########################################################################
assign txrd_ctrlmode[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
txrd_packet[7:4];
assign txrd_data[PW-1:0] = {txrd_packet[PW-1:8],
txrd_ctrlmode[3:0],
txrd_packet[3:0]};
assign txwr_ctrlmode[3:0] = ctrlmode_bypass ? ctrlmode[3:0] :
txwr_packet[7:4];
assign txwr_data[PW-1:0] = {txwr_packet[PW-1:8],
txwr_ctrlmode[3:0],
txwr_packet[3:0]};
//##########################################################################
//# Arbiter
//##########################################################################
arbiter_priority #(.ARW(3)) arbiter (.grant({txrr_grant,
txrd_grant,
txwr_grant //highest priority
}),
.await({txrr_arb_wait,
txrd_arb_wait,
txwr_arb_wait
}),
.request({txrr_access,
txrd_access,
txwr_access
})
);
//Priority Mux
assign etx_mux[PW-1:0] =({(PW){txwr_grant}} & txwr_data[PW-1:0]) |
({(PW){txrd_grant}} & txrd_data[PW-1:0]) |
({(PW){txrr_grant}} & txrr_packet[PW-1:0]);
//######################################################################
//Pushback (stall) Signals
//######################################################################
//Write waits on pin wr wait or cfg_wait
assign txwr_wait = etx_wr_wait |
etx_cfg_wait;
//Host read request (self throttling, one read at a time)
assign txrd_wait = etx_rd_wait |
etx_cfg_wait |
txrd_arb_wait;
//Read response
assign txrr_wait = etx_wr_wait |
etx_cfg_wait |
txrr_arb_wait;
//#####################################################################
//# Pipeline stage (arbiter+mux takes time..)
//#####################################################################
assign access_in = (txwr_grant & ~txwr_wait) |
(txrd_grant & ~txrd_wait) |
(txrr_grant & ~txrr_wait);
//Pipeline + stall
assign write_in = etx_mux[1];
//access
always @ (posedge clk)
if (reset)
begin
etx_access <= 1'b0;
etx_rr <= 1'b0;
end
else if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
begin
etx_access <= access_in;
etx_rr <= txrr_grant;
end
//packet
always @ (posedge clk)
if (access_in & (write_in & ~etx_wr_wait) | (~write_in & ~etx_rd_wait))
etx_packet[PW-1:0] <= etx_mux[PW-1:0];
endmodule // etx_arbiter
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")
// End:
/*
Copyright (C) 2015 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
//Test bench for 32 bit ripple carry adder
`include "lab6_6.v"
module ripple_carry_adder_test(); /* test bench module for first_module() */
reg [31:0] A, B;
reg C0;
wire [31:0] S;
wire Cout;
ripple_carry_adder_32bit test(S,Cout,A,B,C0);
initial begin
$monitor($time, "\tA=%d\tB=%d\tCin=%b\tS=%d\tCout=%b", A, B, C0, S, Cout);
A = 0; B = 0; C0 = 0;
#1
A = 0; B = 0; C0 = 1;
#1
A = 0; B = 1; C0 = 0;
#1
A = 1; B = 0; C0 = 0;
#1
A = 1; B = 1; C0 = 0;
#1
A = 1; B = 1; C0 = 1;
#1
A = 16777215; B = 16777215; C0 = 0;
#1
A = 16777215; B = 16777215; C0 = 1;
#1
A = 4294967295; B = 0; C0 = 0;
#1
A = 4294967295; B = 0; C0 = 1;
#1
A = 4294967295; B = 1; C0 = 0;
#1
A = 4294967295; B = 1; C0 = 1;
#1
A = 0; B = 4294967295; C0 = 0;
#1
A = 0; B = 4294967295; C0 = 1;
#1
A = 1; B = 4294967295; C0 = 0;
#1
A = 1; B = 4294967295; C0 = 1;
#1
A = 4294967295; B = 4294967295; C0 = 0;
#1
A = 4294967295; B = 4294967295; C0 = 1;
#1
$finish;
end
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The CPU module to implement Core and other top level glue logics
//
// ====================================================================
`include "e203_defines.v"
module e203_cpu #(
parameter MASTER = 1
)(
output [`E203_PC_SIZE-1:0] inspect_pc,
output inspect_dbg_irq ,
output inspect_mem_cmd_valid,
output inspect_mem_cmd_ready,
output inspect_mem_rsp_valid,
output inspect_mem_rsp_ready,
output inspect_core_clk ,
output core_csr_clk ,
`ifdef E203_HAS_ITCM
output rst_itcm,
`endif
`ifdef E203_HAS_DTCM
output rst_dtcm,
`endif
output core_wfi,
output tm_stop,
input [`E203_PC_SIZE-1:0] pc_rtvec,
///////////////////////////////////////
// With the interface to debug module
//
// The interface with commit stage
output [`E203_PC_SIZE-1:0] cmt_dpc,
output cmt_dpc_ena,
output [3-1:0] cmt_dcause,
output cmt_dcause_ena,
output dbg_irq_r,
// The interface with CSR control
output wr_dcsr_ena ,
output wr_dpc_ena ,
output wr_dscratch_ena,
output [32-1:0] wr_csr_nxt ,
input [32-1:0] dcsr_r ,
input [`E203_PC_SIZE-1:0] dpc_r ,
input [32-1:0] dscratch_r,
input dbg_mode,
input dbg_halt_r,
input dbg_step_r,
input dbg_ebreakm_r,
input dbg_stopcycle,
/////////////////////////////////////////////////////
input [`E203_HART_ID_W-1:0] core_mhartid,
input dbg_irq_a,
input ext_irq_a,
input sft_irq_a,
input tmr_irq_a,
`ifdef E203_HAS_ITCM //{
//input [`E203_ADDR_SIZE-1:0] itcm_region_indic,
`endif//}
`ifdef E203_HAS_DTCM //{
//input [`E203_ADDR_SIZE-1:0] dtcm_region_indic,
`endif//}
`ifdef E203_HAS_ITCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to ITCM
// * Bus cmd channel
input ext2itcm_icb_cmd_valid,
output ext2itcm_icb_cmd_ready,
input [`E203_ITCM_ADDR_WIDTH-1:0] ext2itcm_icb_cmd_addr,
input ext2itcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2itcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2itcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2itcm_icb_rsp_valid,
input ext2itcm_icb_rsp_ready,
output ext2itcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2itcm_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_DTCM_EXTITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// External-agent ICB to DTCM
// * Bus cmd channel
input ext2dtcm_icb_cmd_valid,
output ext2dtcm_icb_cmd_ready,
input [`E203_DTCM_ADDR_WIDTH-1:0] ext2dtcm_icb_cmd_addr,
input ext2dtcm_icb_cmd_read,
input [`E203_XLEN-1:0] ext2dtcm_icb_cmd_wdata,
input [`E203_XLEN/8-1:0] ext2dtcm_icb_cmd_wmask,
//
// * Bus RSP channel
output ext2dtcm_icb_rsp_valid,
input ext2dtcm_icb_rsp_ready,
output ext2dtcm_icb_rsp_err ,
output [`E203_XLEN-1:0] ext2dtcm_icb_rsp_rdata,
`endif//}
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Private Peripheral Interface
input [`E203_ADDR_SIZE-1:0] ppi_region_indic,
//
input ppi_icb_enable,
// * Bus cmd channel
output ppi_icb_cmd_valid,
input ppi_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] ppi_icb_cmd_addr,
output ppi_icb_cmd_read,
output [`E203_XLEN-1:0] ppi_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] ppi_icb_cmd_wmask,
output ppi_icb_cmd_lock,
output ppi_icb_cmd_excl,
output [1:0] ppi_icb_cmd_size,
//
// * Bus RSP channel
input ppi_icb_rsp_valid,
output ppi_icb_rsp_ready,
input ppi_icb_rsp_err ,
input ppi_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] ppi_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] clint_region_indic,
input clint_icb_enable,
output clint_icb_cmd_valid,
input clint_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] clint_icb_cmd_addr,
output clint_icb_cmd_read,
output [`E203_XLEN-1:0] clint_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] clint_icb_cmd_wmask,
output clint_icb_cmd_lock,
output clint_icb_cmd_excl,
output [1:0] clint_icb_cmd_size,
//
// * Bus RSP channel
input clint_icb_rsp_valid,
output clint_icb_rsp_ready,
input clint_icb_rsp_err ,
input clint_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] clint_icb_rsp_rdata,
input [`E203_ADDR_SIZE-1:0] plic_region_indic,
input plic_icb_enable,
output plic_icb_cmd_valid,
input plic_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] plic_icb_cmd_addr,
output plic_icb_cmd_read,
output [`E203_XLEN-1:0] plic_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] plic_icb_cmd_wmask,
output plic_icb_cmd_lock,
output plic_icb_cmd_excl,
output [1:0] plic_icb_cmd_size,
//
// * Bus RSP channel
input plic_icb_rsp_valid,
output plic_icb_rsp_ready,
input plic_icb_rsp_err ,
input plic_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] plic_icb_rsp_rdata,
`ifdef E203_HAS_FIO //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface to Fast I/O
input [`E203_ADDR_SIZE-1:0] fio_region_indic,
//
input fio_icb_enable,
// * Bus cmd channel
output fio_icb_cmd_valid,
input fio_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] fio_icb_cmd_addr,
output fio_icb_cmd_read,
output [`E203_XLEN-1:0] fio_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] fio_icb_cmd_wmask,
output fio_icb_cmd_lock,
output fio_icb_cmd_excl,
output [1:0] fio_icb_cmd_size,
//
// * Bus RSP channel
input fio_icb_rsp_valid,
output fio_icb_rsp_ready,
input fio_icb_rsp_err ,
input fio_icb_rsp_excl_ok ,
input [`E203_XLEN-1:0] fio_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_MEM_ITF //{
//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////
// The ICB Interface from Ifetch
//
input mem_icb_enable,
// * Bus cmd channel
output mem_icb_cmd_valid,
input mem_icb_cmd_ready,
output [`E203_ADDR_SIZE-1:0] mem_icb_cmd_addr,
output mem_icb_cmd_read,
output [`E203_XLEN-1:0] mem_icb_cmd_wdata,
output [`E203_XLEN/8-1:0] mem_icb_cmd_wmask,
output mem_icb_cmd_lock,
output mem_icb_cmd_excl,
output [1:0] mem_icb_cmd_size,
output [1:0] mem_icb_cmd_burst,
output [1:0] mem_icb_cmd_beat,
//
// * Bus RSP channel
input mem_icb_rsp_valid,
output mem_icb_rsp_ready,
input mem_icb_rsp_err ,
input mem_icb_rsp_excl_ok,
input [`E203_XLEN-1:0] mem_icb_rsp_rdata,
`endif//}
`ifdef E203_HAS_ITCM//{
output itcm_ls,
output itcm_ram_cs,
output itcm_ram_we,
output [`E203_ITCM_RAM_AW-1:0] itcm_ram_addr,
output [`E203_ITCM_RAM_MW-1:0] itcm_ram_wem,
output [`E203_ITCM_RAM_DW-1:0] itcm_ram_din,
input [`E203_ITCM_RAM_DW-1:0] itcm_ram_dout,
output clk_itcm_ram,
`endif//}
`ifdef E203_HAS_DTCM//{
output dtcm_ls,
output dtcm_ram_cs,
output dtcm_ram_we,
output [`E203_DTCM_RAM_AW-1:0] dtcm_ram_addr,
output [`E203_DTCM_RAM_MW-1:0] dtcm_ram_wem,
output [`E203_DTCM_RAM_DW-1:0] dtcm_ram_din,
input [`E203_DTCM_RAM_DW-1:0] dtcm_ram_dout,
output clk_dtcm_ram,
`endif//}
input test_mode,
input clk,
input rst_n
);
wire core_cgstop;
wire tcm_cgstop;
wire core_ifu_active;
wire core_exu_active;
wire core_lsu_active;
wire core_biu_active;
// The core's clk and rst
wire rst_core;
wire clk_core_ifu;
wire clk_core_exu;
wire clk_core_lsu;
wire clk_core_biu;
// The ITCM/DTCM clk and rst
`ifdef E203_HAS_ITCM
wire clk_itcm;
wire itcm_active;
`endif
`ifdef E203_HAS_DTCM
wire clk_dtcm;
wire dtcm_active;
`endif
// The Top always on clk and rst
wire rst_aon;
wire clk_aon;
// The reset ctrl and clock ctrl should be in the power always-on domain
e203_reset_ctrl #(.MASTER(MASTER)) u_e203_reset_ctrl (
.clk (clk_aon ),
.rst_n (rst_n ),
.test_mode (test_mode),
.rst_core (rst_core),
`ifdef E203_HAS_ITCM
.rst_itcm (rst_itcm),
`endif
`ifdef E203_HAS_DTCM
.rst_dtcm (rst_dtcm),
`endif
.rst_aon (rst_aon)
);
e203_clk_ctrl u_e203_clk_ctrl(
.clk (clk ),
.rst_n (rst_aon ),
.test_mode (test_mode ),
.clk_aon (clk_aon ),
.core_cgstop (core_cgstop),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
`ifdef E203_HAS_ITCM
.clk_itcm (clk_itcm ),
.itcm_active (itcm_active),
.itcm_ls (itcm_ls ),
`endif
`ifdef E203_HAS_DTCM
.clk_dtcm (clk_dtcm ),
.dtcm_active (dtcm_active),
.dtcm_ls (dtcm_ls ),
`endif
.core_ifu_active(core_ifu_active),
.core_exu_active(core_exu_active),
.core_lsu_active(core_lsu_active),
.core_biu_active(core_biu_active),
.core_wfi (core_wfi )
);
wire ext_irq_r;
wire sft_irq_r;
wire tmr_irq_r;
e203_irq_sync #(.MASTER(MASTER)) u_e203_irq_sync(
.clk (clk_aon ),
.rst_n (rst_aon ),
.dbg_irq_a (dbg_irq_a),
.dbg_irq_r (dbg_irq_r),
.ext_irq_a (ext_irq_a),
.sft_irq_a (sft_irq_a),
.tmr_irq_a (tmr_irq_a),
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r)
);
`ifdef E203_HAS_ITCM //{
wire ifu2itcm_holdup;
//wire ifu2itcm_replay;
wire ifu2itcm_icb_cmd_valid;
wire ifu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] ifu2itcm_icb_cmd_addr;
wire ifu2itcm_icb_rsp_valid;
wire ifu2itcm_icb_rsp_ready;
wire ifu2itcm_icb_rsp_err;
wire [`E203_ITCM_DATA_WIDTH-1:0] ifu2itcm_icb_rsp_rdata;
wire lsu2itcm_icb_cmd_valid;
wire lsu2itcm_icb_cmd_ready;
wire [`E203_ITCM_ADDR_WIDTH-1:0] lsu2itcm_icb_cmd_addr;
wire lsu2itcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2itcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2itcm_icb_cmd_wmask;
wire lsu2itcm_icb_cmd_lock;
wire lsu2itcm_icb_cmd_excl;
wire [1:0] lsu2itcm_icb_cmd_size;
wire lsu2itcm_icb_rsp_valid;
wire lsu2itcm_icb_rsp_ready;
wire lsu2itcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2itcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_DTCM //{
wire lsu2dtcm_icb_cmd_valid;
wire lsu2dtcm_icb_cmd_ready;
wire [`E203_DTCM_ADDR_WIDTH-1:0] lsu2dtcm_icb_cmd_addr;
wire lsu2dtcm_icb_cmd_read;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_cmd_wdata;
wire [`E203_XLEN/8-1:0] lsu2dtcm_icb_cmd_wmask;
wire lsu2dtcm_icb_cmd_lock;
wire lsu2dtcm_icb_cmd_excl;
wire [1:0] lsu2dtcm_icb_cmd_size;
wire lsu2dtcm_icb_rsp_valid;
wire lsu2dtcm_icb_rsp_ready;
wire lsu2dtcm_icb_rsp_err ;
wire [`E203_XLEN-1:0] lsu2dtcm_icb_rsp_rdata;
`endif//}
`ifdef E203_HAS_CSR_EAI//{
wire eai_csr_valid;
wire eai_csr_ready;
wire [31:0] eai_csr_addr;
wire eai_csr_wr;
wire [31:0] eai_csr_wdata;
wire [31:0] eai_csr_rdata;
// This is an empty module to just connect the EAI CSR interface,
// user can hack it to become a real one
e203_extend_csr u_e203_extend_csr(
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
.clk (clk_core_exu ),
.rst_n (rst_core )
);
`endif//}
e203_core u_e203_core(
.inspect_pc (inspect_pc),
`ifdef E203_HAS_CSR_EAI//{
.eai_csr_valid (eai_csr_valid),
.eai_csr_ready (eai_csr_ready),
.eai_csr_addr (eai_csr_addr ),
.eai_csr_wr (eai_csr_wr ),
.eai_csr_wdata (eai_csr_wdata),
.eai_csr_rdata (eai_csr_rdata),
`endif//}
.tcm_cgstop (tcm_cgstop),
.core_cgstop (core_cgstop),
.tm_stop (tm_stop),
.pc_rtvec (pc_rtvec),
.ifu_active (core_ifu_active),
.exu_active (core_exu_active),
.lsu_active (core_lsu_active),
.biu_active (core_biu_active),
.core_wfi (core_wfi),
.core_mhartid (core_mhartid),
.dbg_irq_r (dbg_irq_r),
.lcl_irq_r (`E203_LIRQ_NUM'b0),// Not implemented now
.ext_irq_r (ext_irq_r),
.sft_irq_r (sft_irq_r),
.tmr_irq_r (tmr_irq_r),
.evt_r (`E203_EVT_NUM'b0),// Not implemented now
.cmt_dpc (cmt_dpc ),
.cmt_dpc_ena (cmt_dpc_ena ),
.cmt_dcause (cmt_dcause ),
.cmt_dcause_ena (cmt_dcause_ena ),
.wr_dcsr_ena (wr_dcsr_ena ),
.wr_dpc_ena (wr_dpc_ena ),
.wr_dscratch_ena (wr_dscratch_ena),
.wr_csr_nxt (wr_csr_nxt ),
.dcsr_r (dcsr_r ),
.dpc_r (dpc_r ),
.dscratch_r (dscratch_r ),
.dbg_mode (dbg_mode ),
.dbg_halt_r (dbg_halt_r ),
.dbg_step_r (dbg_step_r ),
.dbg_ebreakm_r (dbg_ebreakm_r),
.dbg_stopcycle (dbg_stopcycle),
`ifdef E203_HAS_ITCM //{
//.itcm_region_indic (itcm_region_indic),
.itcm_region_indic (`E203_ITCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_DTCM //{
//.dtcm_region_indic (dtcm_region_indic),
.dtcm_region_indic (`E203_DTCM_ADDR_BASE),
`endif//}
`ifdef E203_HAS_ITCM //{
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_cmd_lock (lsu2itcm_icb_cmd_lock ),
.lsu2itcm_icb_cmd_excl (lsu2itcm_icb_cmd_excl ),
.lsu2itcm_icb_cmd_size (lsu2itcm_icb_cmd_size ),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_excl_ok(1'b0),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_DTCM //{
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_cmd_lock (lsu2dtcm_icb_cmd_lock ),
.lsu2dtcm_icb_cmd_excl (lsu2dtcm_icb_cmd_excl ),
.lsu2dtcm_icb_cmd_size (lsu2dtcm_icb_cmd_size ),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_excl_ok(1'b0),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
`endif//}
.ppi_icb_enable (ppi_icb_enable),
.ppi_region_indic (ppi_region_indic ),
.ppi_icb_cmd_valid (ppi_icb_cmd_valid),
.ppi_icb_cmd_ready (ppi_icb_cmd_ready),
.ppi_icb_cmd_addr (ppi_icb_cmd_addr ),
.ppi_icb_cmd_read (ppi_icb_cmd_read ),
.ppi_icb_cmd_wdata (ppi_icb_cmd_wdata),
.ppi_icb_cmd_wmask (ppi_icb_cmd_wmask),
.ppi_icb_cmd_lock (ppi_icb_cmd_lock ),
.ppi_icb_cmd_excl (ppi_icb_cmd_excl ),
.ppi_icb_cmd_size (ppi_icb_cmd_size ),
.ppi_icb_rsp_valid (ppi_icb_rsp_valid),
.ppi_icb_rsp_ready (ppi_icb_rsp_ready),
.ppi_icb_rsp_err (ppi_icb_rsp_err ),
.ppi_icb_rsp_excl_ok (ppi_icb_rsp_excl_ok),
.ppi_icb_rsp_rdata (ppi_icb_rsp_rdata),
.plic_icb_enable (plic_icb_enable),
.plic_region_indic (plic_region_indic ),
.plic_icb_cmd_valid (plic_icb_cmd_valid),
.plic_icb_cmd_ready (plic_icb_cmd_ready),
.plic_icb_cmd_addr (plic_icb_cmd_addr ),
.plic_icb_cmd_read (plic_icb_cmd_read ),
.plic_icb_cmd_wdata (plic_icb_cmd_wdata),
.plic_icb_cmd_wmask (plic_icb_cmd_wmask),
.plic_icb_cmd_lock (plic_icb_cmd_lock ),
.plic_icb_cmd_excl (plic_icb_cmd_excl ),
.plic_icb_cmd_size (plic_icb_cmd_size ),
.plic_icb_rsp_valid (plic_icb_rsp_valid),
.plic_icb_rsp_ready (plic_icb_rsp_ready),
.plic_icb_rsp_err (plic_icb_rsp_err ),
.plic_icb_rsp_excl_ok (plic_icb_rsp_excl_ok),
.plic_icb_rsp_rdata (plic_icb_rsp_rdata),
.clint_icb_enable (clint_icb_enable),
.clint_region_indic (clint_region_indic ),
.clint_icb_cmd_valid (clint_icb_cmd_valid),
.clint_icb_cmd_ready (clint_icb_cmd_ready),
.clint_icb_cmd_addr (clint_icb_cmd_addr ),
.clint_icb_cmd_read (clint_icb_cmd_read ),
.clint_icb_cmd_wdata (clint_icb_cmd_wdata),
.clint_icb_cmd_wmask (clint_icb_cmd_wmask),
.clint_icb_cmd_lock (clint_icb_cmd_lock ),
.clint_icb_cmd_excl (clint_icb_cmd_excl ),
.clint_icb_cmd_size (clint_icb_cmd_size ),
.clint_icb_rsp_valid (clint_icb_rsp_valid),
.clint_icb_rsp_ready (clint_icb_rsp_ready),
.clint_icb_rsp_err (clint_icb_rsp_err ),
.clint_icb_rsp_excl_ok (clint_icb_rsp_excl_ok),
.clint_icb_rsp_rdata (clint_icb_rsp_rdata),
`ifdef E203_HAS_FIO //{
.fio_icb_enable (fio_icb_enable),
.fio_region_indic (fio_region_indic ),
.fio_icb_cmd_valid (fio_icb_cmd_valid),
.fio_icb_cmd_ready (fio_icb_cmd_ready),
.fio_icb_cmd_addr (fio_icb_cmd_addr ),
.fio_icb_cmd_read (fio_icb_cmd_read ),
.fio_icb_cmd_wdata (fio_icb_cmd_wdata),
.fio_icb_cmd_wmask (fio_icb_cmd_wmask),
.fio_icb_cmd_lock (fio_icb_cmd_lock ),
.fio_icb_cmd_excl (fio_icb_cmd_excl ),
.fio_icb_cmd_size (fio_icb_cmd_size ),
.fio_icb_rsp_valid (fio_icb_rsp_valid),
.fio_icb_rsp_ready (fio_icb_rsp_ready),
.fio_icb_rsp_err (fio_icb_rsp_err ),
.fio_icb_rsp_excl_ok (fio_icb_rsp_excl_ok),
.fio_icb_rsp_rdata (fio_icb_rsp_rdata),
`endif//}
`ifdef E203_HAS_MEM_ITF //{
.mem_icb_enable (mem_icb_enable),
.mem_icb_cmd_valid (mem_icb_cmd_valid),
.mem_icb_cmd_ready (mem_icb_cmd_ready),
.mem_icb_cmd_addr (mem_icb_cmd_addr ),
.mem_icb_cmd_read (mem_icb_cmd_read ),
.mem_icb_cmd_wdata (mem_icb_cmd_wdata),
.mem_icb_cmd_wmask (mem_icb_cmd_wmask),
.mem_icb_cmd_lock (mem_icb_cmd_lock ),
.mem_icb_cmd_excl (mem_icb_cmd_excl ),
.mem_icb_cmd_size (mem_icb_cmd_size ),
.mem_icb_cmd_burst (mem_icb_cmd_burst ),
.mem_icb_cmd_beat (mem_icb_cmd_beat ),
.mem_icb_rsp_valid (mem_icb_rsp_valid),
.mem_icb_rsp_ready (mem_icb_rsp_ready),
.mem_icb_rsp_err (mem_icb_rsp_err ),
.mem_icb_rsp_excl_ok(mem_icb_rsp_excl_ok ),
.mem_icb_rsp_rdata (mem_icb_rsp_rdata),
`endif//}
.clk_aon (clk_aon ),
.clk_core_ifu (clk_core_ifu ),
.clk_core_exu (clk_core_exu ),
.clk_core_lsu (clk_core_lsu ),
.clk_core_biu (clk_core_biu ),
.test_mode (test_mode),
.rst_n (rst_core )
);
`ifdef E203_HAS_ITCM //{
e203_itcm_ctrl u_e203_itcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.itcm_active (itcm_active),
.ifu2itcm_icb_cmd_valid (ifu2itcm_icb_cmd_valid),
.ifu2itcm_icb_cmd_ready (ifu2itcm_icb_cmd_ready),
.ifu2itcm_icb_cmd_addr (ifu2itcm_icb_cmd_addr ),
.ifu2itcm_icb_cmd_read (1'b1 ),
.ifu2itcm_icb_cmd_wdata ({`E203_ITCM_DATA_WIDTH{1'b0}}),
.ifu2itcm_icb_cmd_wmask ({`E203_ITCM_DATA_WIDTH/8{1'b0}}),
.ifu2itcm_icb_rsp_valid (ifu2itcm_icb_rsp_valid),
.ifu2itcm_icb_rsp_ready (ifu2itcm_icb_rsp_ready),
.ifu2itcm_icb_rsp_err (ifu2itcm_icb_rsp_err ),
.ifu2itcm_icb_rsp_rdata (ifu2itcm_icb_rsp_rdata),
.ifu2itcm_holdup (ifu2itcm_holdup ),
//.ifu2itcm_replay (ifu2itcm_replay ),
.lsu2itcm_icb_cmd_valid (lsu2itcm_icb_cmd_valid),
.lsu2itcm_icb_cmd_ready (lsu2itcm_icb_cmd_ready),
.lsu2itcm_icb_cmd_addr (lsu2itcm_icb_cmd_addr ),
.lsu2itcm_icb_cmd_read (lsu2itcm_icb_cmd_read ),
.lsu2itcm_icb_cmd_wdata (lsu2itcm_icb_cmd_wdata),
.lsu2itcm_icb_cmd_wmask (lsu2itcm_icb_cmd_wmask),
.lsu2itcm_icb_rsp_valid (lsu2itcm_icb_rsp_valid),
.lsu2itcm_icb_rsp_ready (lsu2itcm_icb_rsp_ready),
.lsu2itcm_icb_rsp_err (lsu2itcm_icb_rsp_err ),
.lsu2itcm_icb_rsp_rdata (lsu2itcm_icb_rsp_rdata),
.itcm_ram_cs (itcm_ram_cs ),
.itcm_ram_we (itcm_ram_we ),
.itcm_ram_addr (itcm_ram_addr),
.itcm_ram_wem (itcm_ram_wem ),
.itcm_ram_din (itcm_ram_din ),
.itcm_ram_dout (itcm_ram_dout),
.clk_itcm_ram (clk_itcm_ram ),
`ifdef E203_HAS_ITCM_EXTITF //{
.ext2itcm_icb_cmd_valid (ext2itcm_icb_cmd_valid),
.ext2itcm_icb_cmd_ready (ext2itcm_icb_cmd_ready),
.ext2itcm_icb_cmd_addr (ext2itcm_icb_cmd_addr ),
.ext2itcm_icb_cmd_read (ext2itcm_icb_cmd_read ),
.ext2itcm_icb_cmd_wdata (ext2itcm_icb_cmd_wdata),
.ext2itcm_icb_cmd_wmask (ext2itcm_icb_cmd_wmask),
.ext2itcm_icb_rsp_valid (ext2itcm_icb_rsp_valid),
.ext2itcm_icb_rsp_ready (ext2itcm_icb_rsp_ready),
.ext2itcm_icb_rsp_err (ext2itcm_icb_rsp_err ),
.ext2itcm_icb_rsp_rdata (ext2itcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_itcm),
.rst_n (rst_itcm)
);
`endif//}
`ifdef E203_HAS_DTCM //{
e203_dtcm_ctrl u_e203_dtcm_ctrl(
.tcm_cgstop (tcm_cgstop),
.dtcm_active (dtcm_active),
.lsu2dtcm_icb_cmd_valid (lsu2dtcm_icb_cmd_valid),
.lsu2dtcm_icb_cmd_ready (lsu2dtcm_icb_cmd_ready),
.lsu2dtcm_icb_cmd_addr (lsu2dtcm_icb_cmd_addr ),
.lsu2dtcm_icb_cmd_read (lsu2dtcm_icb_cmd_read ),
.lsu2dtcm_icb_cmd_wdata (lsu2dtcm_icb_cmd_wdata),
.lsu2dtcm_icb_cmd_wmask (lsu2dtcm_icb_cmd_wmask),
.lsu2dtcm_icb_rsp_valid (lsu2dtcm_icb_rsp_valid),
.lsu2dtcm_icb_rsp_ready (lsu2dtcm_icb_rsp_ready),
.lsu2dtcm_icb_rsp_err (lsu2dtcm_icb_rsp_err ),
.lsu2dtcm_icb_rsp_rdata (lsu2dtcm_icb_rsp_rdata),
.dtcm_ram_cs (dtcm_ram_cs ),
.dtcm_ram_we (dtcm_ram_we ),
.dtcm_ram_addr (dtcm_ram_addr),
.dtcm_ram_wem (dtcm_ram_wem ),
.dtcm_ram_din (dtcm_ram_din ),
.dtcm_ram_dout (dtcm_ram_dout),
.clk_dtcm_ram (clk_dtcm_ram ),
`ifdef E203_HAS_DTCM_EXTITF //{
.ext2dtcm_icb_cmd_valid (ext2dtcm_icb_cmd_valid),
.ext2dtcm_icb_cmd_ready (ext2dtcm_icb_cmd_ready),
.ext2dtcm_icb_cmd_addr (ext2dtcm_icb_cmd_addr ),
.ext2dtcm_icb_cmd_read (ext2dtcm_icb_cmd_read ),
.ext2dtcm_icb_cmd_wdata (ext2dtcm_icb_cmd_wdata),
.ext2dtcm_icb_cmd_wmask (ext2dtcm_icb_cmd_wmask),
.ext2dtcm_icb_rsp_valid (ext2dtcm_icb_rsp_valid),
.ext2dtcm_icb_rsp_ready (ext2dtcm_icb_rsp_ready),
.ext2dtcm_icb_rsp_err (ext2dtcm_icb_rsp_err ),
.ext2dtcm_icb_rsp_rdata (ext2dtcm_icb_rsp_rdata),
`endif//}
.test_mode (test_mode),
.clk (clk_dtcm),
.rst_n (rst_dtcm)
);
`endif//}
assign inspect_dbg_irq = dbg_irq_a;
assign inspect_mem_cmd_valid = mem_icb_cmd_valid;
assign inspect_mem_cmd_ready = mem_icb_cmd_ready;
assign inspect_mem_rsp_valid = mem_icb_rsp_valid;
assign inspect_mem_rsp_ready = mem_icb_rsp_ready;
assign inspect_core_clk = clk;
assign core_csr_clk = clk_core_exu;
endmodule
|
// NeoGeo logic definition (simulation only)
// Copyright (C) 2018 Sean Gonsalves
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <https://www.gnu.org/licenses/>.
`timescale 1ns/1ns
module upd4990(
input XTAL,
input CS, OE,
input CLK,
input DATA_IN,
input STROBE,
output reg TP,
output DATA_OUT // Open drain (is this important ?)
);
// Todo, low priority for now
parameter TIME_REG = 48'h892424113000; // Sould be 1989/03/24 11:30:00
reg [3:0] COMMAND_SR;
wire [51:0] TIME_SR;
wire CLKG, STROBEG; // Gated by CS
assign TIME_SR = { COMMAND_SR, TIME_REG }; // 4 + 48 = 52 bits
assign DATA_OUT = 1'b0; // TODO
assign CLKG = CS & CLK;
assign STROBEG = CS & STROBE;
initial
TP = 1'b0;
// DEBUG
always
#5000 TP = !TP; // 10ms to make startup test quicker - Should be 1Hz -> 500000ns half period
always @(posedge CLKG)
begin
$stop;
if (CS)
begin
$display("RTC clocked in data bit '%B'", DATA_IN); // DEBUG
COMMAND_SR[2:0] <= COMMAND_SR[3:1];
COMMAND_SR[3] <= DATA_IN;
end
end
always @(posedge STROBEG)
if (CS) $display("RTC strobed, data = %H", COMMAND_SR); // DEBUG
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A31O_1_V
`define SKY130_FD_SC_LP__A31O_1_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog wrapper for a31o with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a31o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_1 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a31o_1 (
X ,
A1,
A2,
A3,
B1
);
output X ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a31o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A31O_1_V
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_3_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_3_e.v,v 1.3 2006/06/26 08:39:42 wig Exp $
// $Date: 2006/06/26 08:39:42 $
// $Log: inst_3_e.v,v $
// Revision 1.3 2006/06/26 08:39:42 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_3_e
//
// No `defines in this module
module inst_3_e
//
// Generated Module inst_3
//
(
);
// Module parameters:
parameter FOO = 10;
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_3_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:18:56 06/07/2015
// Design Name: UART_IP
// Module Name: /home/sadique/Work/Verilog/Spartan6/USB-uart/uart_test.v
// Project Name: USB-uart
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: UART_IP
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module uart_test;
// Inputs
reg sys_clk;
reg RTS;
reg RX;
wire [7:0] RxD_par;
wire RxD_start;
// Outputs
wire CTS;
wire TX;
wire [7:0] TxD_par;
wire TxD_ready;
// Instantiate the Unit Under Test (UUT)
UART_IP uut (
.sys_clk(sys_clk),
.CTS(CTS),
.RTS(RTS),
.TX(TX),
.RX(RX),
.TxD_par(TxD_par),
.TxD_ready(TxD_ready),
.RxD_par(RxD_par),
.RxD_start(RxD_start)
);
// Loop parallel ouput as input
assign RxD_par = TxD_par;
assign RxD_start = TxD_ready;
initial begin
// Initialize Inputs
sys_clk = 0;
RTS = 0; // active low
RX = 1;
//RxD_par = 0;
//RxD_start = 0;
// Wait 100 ns for global reset to finish
#5000;
// Add stimulus here
#0 RX = 0; //Start bit
#8680 RX = 0; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 0; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
#20000
#8680 RX = 0; //Start bit
#8680 RX = 1; //bit 0
#8680 RX = 1; //bit 1
#8680 RX = 0; //bit 2
#8680 RX = 1; //bit 3
#8680 RX = 0; //bit 4
#8680 RX = 1; //bit 5
#8680 RX = 0; //bit 6
#8680 RX = 1; //bit 7
#8680 RX = 1; //Stop bit
end
always begin
#2.5 sys_clk <= !sys_clk;
end
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module fifo (
clock,
data,
rdreq,
wrreq,
empty,
q);
input clock;
input [7:0] data;
input rdreq;
input wrreq;
output empty;
output [7:0] q;
wire sub_wire0;
wire [7:0] sub_wire1;
wire empty = sub_wire0;
wire [7:0] q = sub_wire1[7:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.wrreq (wrreq),
.empty (sub_wire0),
.q (sub_wire1),
.aclr (),
.almost_empty (),
.almost_full (),
.full (),
.sclr (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone III",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 8,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2B_TB_V
`define SKY130_FD_SC_HDLL__OR2B_TB_V
/**
* or2b: 2-input OR, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2b.v"
module top();
// Inputs are registered
reg A;
reg B_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B_N = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B_N = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B_N = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B_N = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B_N = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__or2b dut (.A(A), .B_N(B_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2B_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_V
`define SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_nsr/sky130_fd_sc_ls__udp_dff_nsr.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`celldefine
module sky130_fd_sc_ls__sdfbbn (
Q ,
Q_N ,
D ,
SCD ,
SCE ,
CLK_N ,
SET_B ,
RESET_B
);
// Module ports
output Q ;
output Q_N ;
input D ;
input SCD ;
input SCE ;
input CLK_N ;
input SET_B ;
input RESET_B;
// Local signals
wire RESET ;
wire SET ;
wire CLK ;
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
not not1 (SET , SET_B );
not not2 (CLK , CLK_N );
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_ls__udp_dff$NSR `UNIT_DELAY dff0 (buf_Q , SET, RESET, CLK, mux_out);
buf buf0 (Q , buf_Q );
not not3 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__SDFBBN_FUNCTIONAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.4.1 (win64) Build 2117270 Tue Jan 30 15:32:00 MST 2018
// Date : Thu Apr 5 01:27:52 2018
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode funcsim
// d:/github/Digital-Hardware-Modelling/xilinx-vivado/snickerdoodle_try/snickerdoodle_try.srcs/sources_1/bd/design_1/ip/design_1_processing_system7_0_0/design_1_processing_system7_0_0_sim_netlist.v
// Design : design_1_processing_system7_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg400-3
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "design_1_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4.1" *)
(* NotValidForBitStream *)
module design_1_processing_system7_0_0
(FCLK_RESET0_N,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n;
(* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK;
(* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire FCLK_RESET0_N;
wire [53:0]MIO;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire NLW_inst_CAN0_PHY_TX_UNCONNECTED;
wire NLW_inst_CAN1_PHY_TX_UNCONNECTED;
wire NLW_inst_DMA0_DAVALID_UNCONNECTED;
wire NLW_inst_DMA0_DRREADY_UNCONNECTED;
wire NLW_inst_DMA0_RSTN_UNCONNECTED;
wire NLW_inst_DMA1_DAVALID_UNCONNECTED;
wire NLW_inst_DMA1_DRREADY_UNCONNECTED;
wire NLW_inst_DMA1_RSTN_UNCONNECTED;
wire NLW_inst_DMA2_DAVALID_UNCONNECTED;
wire NLW_inst_DMA2_DRREADY_UNCONNECTED;
wire NLW_inst_DMA2_RSTN_UNCONNECTED;
wire NLW_inst_DMA3_DAVALID_UNCONNECTED;
wire NLW_inst_DMA3_DRREADY_UNCONNECTED;
wire NLW_inst_DMA3_RSTN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET0_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET0_SOF_TX_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED;
wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_O_UNCONNECTED;
wire NLW_inst_ENET1_MDIO_T_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED;
wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_RX_UNCONNECTED;
wire NLW_inst_ENET1_SOF_TX_UNCONNECTED;
wire NLW_inst_EVENT_EVENTO_UNCONNECTED;
wire NLW_inst_FCLK_CLK0_UNCONNECTED;
wire NLW_inst_FCLK_CLK1_UNCONNECTED;
wire NLW_inst_FCLK_CLK2_UNCONNECTED;
wire NLW_inst_FCLK_CLK3_UNCONNECTED;
wire NLW_inst_FCLK_RESET1_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET2_N_UNCONNECTED;
wire NLW_inst_FCLK_RESET3_N_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED;
wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED;
wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED;
wire NLW_inst_I2C0_SCL_O_UNCONNECTED;
wire NLW_inst_I2C0_SCL_T_UNCONNECTED;
wire NLW_inst_I2C0_SDA_O_UNCONNECTED;
wire NLW_inst_I2C0_SDA_T_UNCONNECTED;
wire NLW_inst_I2C1_SCL_O_UNCONNECTED;
wire NLW_inst_I2C1_SCL_T_UNCONNECTED;
wire NLW_inst_I2C1_SDA_O_UNCONNECTED;
wire NLW_inst_I2C1_SDA_T_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED;
wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED;
wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED;
wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED;
wire NLW_inst_PJTAG_TDO_UNCONNECTED;
wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO0_CLK_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO0_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO0_LED_UNCONNECTED;
wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED;
wire NLW_inst_SDIO1_CLK_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_O_UNCONNECTED;
wire NLW_inst_SDIO1_CMD_T_UNCONNECTED;
wire NLW_inst_SDIO1_LED_UNCONNECTED;
wire NLW_inst_SPI0_MISO_O_UNCONNECTED;
wire NLW_inst_SPI0_MISO_T_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI0_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI0_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI0_SS1_O_UNCONNECTED;
wire NLW_inst_SPI0_SS2_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_O_UNCONNECTED;
wire NLW_inst_SPI0_SS_T_UNCONNECTED;
wire NLW_inst_SPI1_MISO_O_UNCONNECTED;
wire NLW_inst_SPI1_MISO_T_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_O_UNCONNECTED;
wire NLW_inst_SPI1_MOSI_T_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_O_UNCONNECTED;
wire NLW_inst_SPI1_SCLK_T_UNCONNECTED;
wire NLW_inst_SPI1_SS1_O_UNCONNECTED;
wire NLW_inst_SPI1_SS2_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_O_UNCONNECTED;
wire NLW_inst_SPI1_SS_T_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED;
wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED;
wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED;
wire NLW_inst_TRACE_CTL_UNCONNECTED;
wire NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED;
wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED;
wire NLW_inst_UART0_DTRN_UNCONNECTED;
wire NLW_inst_UART0_RTSN_UNCONNECTED;
wire NLW_inst_UART0_TX_UNCONNECTED;
wire NLW_inst_UART1_DTRN_UNCONNECTED;
wire NLW_inst_UART1_RTSN_UNCONNECTED;
wire NLW_inst_UART1_TX_UNCONNECTED;
wire NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED;
wire NLW_inst_WDT_RST_OUT_UNCONNECTED;
wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED;
wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED;
wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED;
wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED;
wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED;
wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_O_UNCONNECTED;
wire [63:0]NLW_inst_GPIO_T_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP0_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED;
wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED;
wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED;
wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED;
wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED;
wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED;
wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED;
wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED;
wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED;
wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED;
wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED;
wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED;
wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED;
wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED;
wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED;
wire [1:0]NLW_inst_USB0_PORT_INDCTL_UNCONNECTED;
wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED;
(* C_DM_WIDTH = "4" *)
(* C_DQS_WIDTH = "4" *)
(* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *)
(* C_EN_EMIO_ENET0 = "0" *)
(* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *)
(* C_EN_EMIO_TRACE = "0" *)
(* C_FCLK_CLK0_BUF = "FALSE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *)
(* C_FCLK_CLK2_BUF = "FALSE" *)
(* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *)
(* C_GP1_EN_MODIFIABLE_TXN = "1" *)
(* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *)
(* C_IRQ_F2P_MODE = "DIRECT" *)
(* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP0_ID_WIDTH = "12" *)
(* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *)
(* C_M_AXI_GP1_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *)
(* C_PACKAGE_NAME = "clg400" *)
(* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *)
(* C_S_AXI_ACP_AWUSER_VAL = "31" *)
(* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *)
(* C_S_AXI_GP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *)
(* C_S_AXI_HP1_DATA_WIDTH = "64" *)
(* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *)
(* C_S_AXI_HP2_ID_WIDTH = "6" *)
(* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *)
(* C_TRACE_BUFFER_CLOCK_DELAY = "12" *)
(* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *)
(* C_TRACE_PIPELINE_WIDTH = "8" *)
(* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *)
(* C_USE_M_AXI_GP0 = "0" *)
(* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *)
(* C_USE_S_AXI_GP0 = "0" *)
(* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *)
(* C_USE_S_AXI_HP1 = "0" *)
(* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *)
(* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} />/>" *)
(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst
(.CAN0_PHY_RX(1'b0),
.CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED),
.CAN1_PHY_RX(1'b0),
.CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED),
.Core0_nFIQ(1'b0),
.Core0_nIRQ(1'b0),
.Core1_nFIQ(1'b0),
.Core1_nIRQ(1'b0),
.DDR_ARB({1'b0,1'b0,1'b0,1'b0}),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.DDR_WEB(DDR_WEB),
.DMA0_ACLK(1'b0),
.DMA0_DAREADY(1'b0),
.DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]),
.DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED),
.DMA0_DRLAST(1'b0),
.DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED),
.DMA0_DRTYPE({1'b0,1'b0}),
.DMA0_DRVALID(1'b0),
.DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED),
.DMA1_ACLK(1'b0),
.DMA1_DAREADY(1'b0),
.DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]),
.DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED),
.DMA1_DRLAST(1'b0),
.DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED),
.DMA1_DRTYPE({1'b0,1'b0}),
.DMA1_DRVALID(1'b0),
.DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED),
.DMA2_ACLK(1'b0),
.DMA2_DAREADY(1'b0),
.DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]),
.DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED),
.DMA2_DRLAST(1'b0),
.DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED),
.DMA2_DRTYPE({1'b0,1'b0}),
.DMA2_DRVALID(1'b0),
.DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED),
.DMA3_ACLK(1'b0),
.DMA3_DAREADY(1'b0),
.DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]),
.DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED),
.DMA3_DRLAST(1'b0),
.DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED),
.DMA3_DRTYPE({1'b0,1'b0}),
.DMA3_DRVALID(1'b0),
.DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED),
.ENET0_EXT_INTIN(1'b0),
.ENET0_GMII_COL(1'b0),
.ENET0_GMII_CRS(1'b0),
.ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET0_GMII_RX_CLK(1'b0),
.ENET0_GMII_RX_DV(1'b0),
.ENET0_GMII_RX_ER(1'b0),
.ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]),
.ENET0_GMII_TX_CLK(1'b0),
.ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED),
.ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED),
.ENET0_MDIO_I(1'b0),
.ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED),
.ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED),
.ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED),
.ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED),
.ENET1_EXT_INTIN(1'b0),
.ENET1_GMII_COL(1'b0),
.ENET1_GMII_CRS(1'b0),
.ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.ENET1_GMII_RX_CLK(1'b0),
.ENET1_GMII_RX_DV(1'b0),
.ENET1_GMII_RX_ER(1'b0),
.ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]),
.ENET1_GMII_TX_CLK(1'b0),
.ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED),
.ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED),
.ENET1_MDIO_I(1'b0),
.ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED),
.ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED),
.ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED),
.ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED),
.ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED),
.ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED),
.ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED),
.EVENT_EVENTI(1'b0),
.EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED),
.EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]),
.EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]),
.FCLK_CLK0(NLW_inst_FCLK_CLK0_UNCONNECTED),
.FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED),
.FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED),
.FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED),
.FCLK_CLKTRIG0_N(1'b0),
.FCLK_CLKTRIG1_N(1'b0),
.FCLK_CLKTRIG2_N(1'b0),
.FCLK_CLKTRIG3_N(1'b0),
.FCLK_RESET0_N(FCLK_RESET0_N),
.FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED),
.FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED),
.FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED),
.FPGA_IDLE_N(1'b0),
.FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_CLK(1'b0),
.FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMD_TRACEIN_VALID(1'b0),
.FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED),
.FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED),
.FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED),
.FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED),
.FTMT_F2P_TRIG_0(1'b0),
.FTMT_F2P_TRIG_1(1'b0),
.FTMT_F2P_TRIG_2(1'b0),
.FTMT_F2P_TRIG_3(1'b0),
.FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]),
.FTMT_P2F_TRIGACK_0(1'b0),
.FTMT_P2F_TRIGACK_1(1'b0),
.FTMT_P2F_TRIGACK_2(1'b0),
.FTMT_P2F_TRIGACK_3(1'b0),
.FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED),
.FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED),
.FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED),
.FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED),
.GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]),
.GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]),
.I2C0_SCL_I(1'b0),
.I2C0_SCL_O(NLW_inst_I2C0_SCL_O_UNCONNECTED),
.I2C0_SCL_T(NLW_inst_I2C0_SCL_T_UNCONNECTED),
.I2C0_SDA_I(1'b0),
.I2C0_SDA_O(NLW_inst_I2C0_SDA_O_UNCONNECTED),
.I2C0_SDA_T(NLW_inst_I2C0_SDA_T_UNCONNECTED),
.I2C1_SCL_I(1'b0),
.I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED),
.I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED),
.I2C1_SDA_I(1'b0),
.I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED),
.I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED),
.IRQ_F2P(1'b0),
.IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED),
.IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED),
.IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED),
.IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED),
.IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED),
.IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED),
.IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED),
.IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED),
.IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED),
.IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED),
.IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED),
.IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED),
.IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED),
.IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED),
.IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED),
.IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED),
.IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED),
.IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED),
.IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED),
.IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED),
.IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED),
.IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED),
.IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED),
.IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED),
.IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED),
.IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED),
.IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED),
.IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED),
.IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED),
.MIO(MIO),
.M_AXI_GP0_ACLK(1'b0),
.M_AXI_GP0_ARADDR(NLW_inst_M_AXI_GP0_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP0_ARBURST(NLW_inst_M_AXI_GP0_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP0_ARCACHE(NLW_inst_M_AXI_GP0_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED),
.M_AXI_GP0_ARID(NLW_inst_M_AXI_GP0_ARID_UNCONNECTED[11:0]),
.M_AXI_GP0_ARLEN(NLW_inst_M_AXI_GP0_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP0_ARLOCK(NLW_inst_M_AXI_GP0_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP0_ARPROT(NLW_inst_M_AXI_GP0_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP0_ARQOS(NLW_inst_M_AXI_GP0_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP0_ARREADY(1'b0),
.M_AXI_GP0_ARSIZE(NLW_inst_M_AXI_GP0_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP0_ARVALID(NLW_inst_M_AXI_GP0_ARVALID_UNCONNECTED),
.M_AXI_GP0_AWADDR(NLW_inst_M_AXI_GP0_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP0_AWBURST(NLW_inst_M_AXI_GP0_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP0_AWCACHE(NLW_inst_M_AXI_GP0_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP0_AWID(NLW_inst_M_AXI_GP0_AWID_UNCONNECTED[11:0]),
.M_AXI_GP0_AWLEN(NLW_inst_M_AXI_GP0_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP0_AWLOCK(NLW_inst_M_AXI_GP0_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP0_AWPROT(NLW_inst_M_AXI_GP0_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP0_AWQOS(NLW_inst_M_AXI_GP0_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP0_AWREADY(1'b0),
.M_AXI_GP0_AWSIZE(NLW_inst_M_AXI_GP0_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP0_AWVALID(NLW_inst_M_AXI_GP0_AWVALID_UNCONNECTED),
.M_AXI_GP0_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_BREADY(NLW_inst_M_AXI_GP0_BREADY_UNCONNECTED),
.M_AXI_GP0_BRESP({1'b0,1'b0}),
.M_AXI_GP0_BVALID(1'b0),
.M_AXI_GP0_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP0_RLAST(1'b0),
.M_AXI_GP0_RREADY(NLW_inst_M_AXI_GP0_RREADY_UNCONNECTED),
.M_AXI_GP0_RRESP({1'b0,1'b0}),
.M_AXI_GP0_RVALID(1'b0),
.M_AXI_GP0_WDATA(NLW_inst_M_AXI_GP0_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP0_WID(NLW_inst_M_AXI_GP0_WID_UNCONNECTED[11:0]),
.M_AXI_GP0_WLAST(NLW_inst_M_AXI_GP0_WLAST_UNCONNECTED),
.M_AXI_GP0_WREADY(1'b0),
.M_AXI_GP0_WSTRB(NLW_inst_M_AXI_GP0_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP0_WVALID(NLW_inst_M_AXI_GP0_WVALID_UNCONNECTED),
.M_AXI_GP1_ACLK(1'b0),
.M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED),
.M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]),
.M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_ARREADY(1'b0),
.M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED),
.M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]),
.M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]),
.M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]),
.M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]),
.M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]),
.M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]),
.M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]),
.M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]),
.M_AXI_GP1_AWREADY(1'b0),
.M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]),
.M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED),
.M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED),
.M_AXI_GP1_BRESP({1'b0,1'b0}),
.M_AXI_GP1_BVALID(1'b0),
.M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.M_AXI_GP1_RLAST(1'b0),
.M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED),
.M_AXI_GP1_RRESP({1'b0,1'b0}),
.M_AXI_GP1_RVALID(1'b0),
.M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]),
.M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]),
.M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED),
.M_AXI_GP1_WREADY(1'b0),
.M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]),
.M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED),
.PJTAG_TCK(1'b0),
.PJTAG_TDI(1'b0),
.PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED),
.PJTAG_TMS(1'b0),
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED),
.SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]),
.SDIO0_CDN(1'b0),
.SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED),
.SDIO0_CLK_FB(1'b0),
.SDIO0_CMD_I(1'b0),
.SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED),
.SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED),
.SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]),
.SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]),
.SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED),
.SDIO0_WP(1'b0),
.SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED),
.SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]),
.SDIO1_CDN(1'b0),
.SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED),
.SDIO1_CLK_FB(1'b0),
.SDIO1_CMD_I(1'b0),
.SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED),
.SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED),
.SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}),
.SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]),
.SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]),
.SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED),
.SDIO1_WP(1'b0),
.SPI0_MISO_I(1'b0),
.SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED),
.SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED),
.SPI0_MOSI_I(1'b0),
.SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED),
.SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED),
.SPI0_SCLK_I(1'b0),
.SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED),
.SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED),
.SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED),
.SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED),
.SPI0_SS_I(1'b0),
.SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED),
.SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED),
.SPI1_MISO_I(1'b0),
.SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED),
.SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED),
.SPI1_MOSI_I(1'b0),
.SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED),
.SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED),
.SPI1_SCLK_I(1'b0),
.SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED),
.SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED),
.SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED),
.SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED),
.SPI1_SS_I(1'b0),
.SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED),
.SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED),
.SRAM_INTIN(1'b0),
.S_AXI_ACP_ACLK(1'b0),
.S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARBURST({1'b0,1'b0}),
.S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED),
.S_AXI_ACP_ARID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARLOCK({1'b0,1'b0}),
.S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED),
.S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_ARVALID(1'b0),
.S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWBURST({1'b0,1'b0}),
.S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWLOCK({1'b0,1'b0}),
.S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED),
.S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_AWVALID(1'b0),
.S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]),
.S_AXI_ACP_BREADY(1'b0),
.S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED),
.S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]),
.S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]),
.S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED),
.S_AXI_ACP_RREADY(1'b0),
.S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]),
.S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED),
.S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WID({1'b0,1'b0,1'b0}),
.S_AXI_ACP_WLAST(1'b0),
.S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED),
.S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_ACP_WVALID(1'b0),
.S_AXI_GP0_ACLK(1'b0),
.S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARBURST({1'b0,1'b0}),
.S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED),
.S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARLOCK({1'b0,1'b0}),
.S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED),
.S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_ARVALID(1'b0),
.S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWBURST({1'b0,1'b0}),
.S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWLOCK({1'b0,1'b0}),
.S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED),
.S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP0_AWVALID(1'b0),
.S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]),
.S_AXI_GP0_BREADY(1'b0),
.S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED),
.S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]),
.S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED),
.S_AXI_GP0_RREADY(1'b0),
.S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED),
.S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WLAST(1'b0),
.S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED),
.S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP0_WVALID(1'b0),
.S_AXI_GP1_ACLK(1'b0),
.S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARBURST({1'b0,1'b0}),
.S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED),
.S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARLOCK({1'b0,1'b0}),
.S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED),
.S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_ARVALID(1'b0),
.S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWBURST({1'b0,1'b0}),
.S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWLOCK({1'b0,1'b0}),
.S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED),
.S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_GP1_AWVALID(1'b0),
.S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]),
.S_AXI_GP1_BREADY(1'b0),
.S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED),
.S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]),
.S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]),
.S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED),
.S_AXI_GP1_RREADY(1'b0),
.S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED),
.S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WLAST(1'b0),
.S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED),
.S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_GP1_WVALID(1'b0),
.S_AXI_HP0_ACLK(1'b0),
.S_AXI_HP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARBURST({1'b0,1'b0}),
.S_AXI_HP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED),
.S_AXI_HP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARLOCK({1'b0,1'b0}),
.S_AXI_HP0_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARREADY(NLW_inst_S_AXI_HP0_ARREADY_UNCONNECTED),
.S_AXI_HP0_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_ARVALID(1'b0),
.S_AXI_HP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWBURST({1'b0,1'b0}),
.S_AXI_HP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWLOCK({1'b0,1'b0}),
.S_AXI_HP0_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWREADY(NLW_inst_S_AXI_HP0_AWREADY_UNCONNECTED),
.S_AXI_HP0_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP0_AWVALID(1'b0),
.S_AXI_HP0_BID(NLW_inst_S_AXI_HP0_BID_UNCONNECTED[5:0]),
.S_AXI_HP0_BREADY(1'b0),
.S_AXI_HP0_BRESP(NLW_inst_S_AXI_HP0_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_BVALID(NLW_inst_S_AXI_HP0_BVALID_UNCONNECTED),
.S_AXI_HP0_RACOUNT(NLW_inst_S_AXI_HP0_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP0_RCOUNT(NLW_inst_S_AXI_HP0_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_RDATA(NLW_inst_S_AXI_HP0_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP0_RDISSUECAP1_EN(1'b0),
.S_AXI_HP0_RID(NLW_inst_S_AXI_HP0_RID_UNCONNECTED[5:0]),
.S_AXI_HP0_RLAST(NLW_inst_S_AXI_HP0_RLAST_UNCONNECTED),
.S_AXI_HP0_RREADY(1'b0),
.S_AXI_HP0_RRESP(NLW_inst_S_AXI_HP0_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP0_RVALID(NLW_inst_S_AXI_HP0_RVALID_UNCONNECTED),
.S_AXI_HP0_WACOUNT(NLW_inst_S_AXI_HP0_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP0_WCOUNT(NLW_inst_S_AXI_HP0_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WLAST(1'b0),
.S_AXI_HP0_WREADY(NLW_inst_S_AXI_HP0_WREADY_UNCONNECTED),
.S_AXI_HP0_WRISSUECAP1_EN(1'b0),
.S_AXI_HP0_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP0_WVALID(1'b0),
.S_AXI_HP1_ACLK(1'b0),
.S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARBURST({1'b0,1'b0}),
.S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED),
.S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARLOCK({1'b0,1'b0}),
.S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED),
.S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_ARVALID(1'b0),
.S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWBURST({1'b0,1'b0}),
.S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWLOCK({1'b0,1'b0}),
.S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED),
.S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP1_AWVALID(1'b0),
.S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]),
.S_AXI_HP1_BREADY(1'b0),
.S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED),
.S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP1_RDISSUECAP1_EN(1'b0),
.S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]),
.S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED),
.S_AXI_HP1_RREADY(1'b0),
.S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED),
.S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WLAST(1'b0),
.S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED),
.S_AXI_HP1_WRISSUECAP1_EN(1'b0),
.S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP1_WVALID(1'b0),
.S_AXI_HP2_ACLK(1'b0),
.S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARBURST({1'b0,1'b0}),
.S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED),
.S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARLOCK({1'b0,1'b0}),
.S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED),
.S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_ARVALID(1'b0),
.S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWBURST({1'b0,1'b0}),
.S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWLOCK({1'b0,1'b0}),
.S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED),
.S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP2_AWVALID(1'b0),
.S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]),
.S_AXI_HP2_BREADY(1'b0),
.S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED),
.S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP2_RDISSUECAP1_EN(1'b0),
.S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]),
.S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED),
.S_AXI_HP2_RREADY(1'b0),
.S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED),
.S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WLAST(1'b0),
.S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED),
.S_AXI_HP2_WRISSUECAP1_EN(1'b0),
.S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP2_WVALID(1'b0),
.S_AXI_HP3_ACLK(1'b0),
.S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARBURST({1'b0,1'b0}),
.S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED),
.S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARLOCK({1'b0,1'b0}),
.S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED),
.S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_ARVALID(1'b0),
.S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWBURST({1'b0,1'b0}),
.S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWLOCK({1'b0,1'b0}),
.S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED),
.S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}),
.S_AXI_HP3_AWVALID(1'b0),
.S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]),
.S_AXI_HP3_BREADY(1'b0),
.S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED),
.S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]),
.S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]),
.S_AXI_HP3_RDISSUECAP1_EN(1'b0),
.S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]),
.S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED),
.S_AXI_HP3_RREADY(1'b0),
.S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]),
.S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED),
.S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]),
.S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]),
.S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WLAST(1'b0),
.S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED),
.S_AXI_HP3_WRISSUECAP1_EN(1'b0),
.S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.S_AXI_HP3_WVALID(1'b0),
.TRACE_CLK(1'b0),
.TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED),
.TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED),
.TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]),
.TTC0_CLK0_IN(1'b0),
.TTC0_CLK1_IN(1'b0),
.TTC0_CLK2_IN(1'b0),
.TTC0_WAVE0_OUT(NLW_inst_TTC0_WAVE0_OUT_UNCONNECTED),
.TTC0_WAVE1_OUT(NLW_inst_TTC0_WAVE1_OUT_UNCONNECTED),
.TTC0_WAVE2_OUT(NLW_inst_TTC0_WAVE2_OUT_UNCONNECTED),
.TTC1_CLK0_IN(1'b0),
.TTC1_CLK1_IN(1'b0),
.TTC1_CLK2_IN(1'b0),
.TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED),
.TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED),
.TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED),
.UART0_CTSN(1'b0),
.UART0_DCDN(1'b0),
.UART0_DSRN(1'b0),
.UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED),
.UART0_RIN(1'b0),
.UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED),
.UART0_RX(1'b1),
.UART0_TX(NLW_inst_UART0_TX_UNCONNECTED),
.UART1_CTSN(1'b0),
.UART1_DCDN(1'b0),
.UART1_DSRN(1'b0),
.UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED),
.UART1_RIN(1'b0),
.UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED),
.UART1_RX(1'b1),
.UART1_TX(NLW_inst_UART1_TX_UNCONNECTED),
.USB0_PORT_INDCTL(NLW_inst_USB0_PORT_INDCTL_UNCONNECTED[1:0]),
.USB0_VBUS_PWRFAULT(1'b0),
.USB0_VBUS_PWRSELECT(NLW_inst_USB0_VBUS_PWRSELECT_UNCONNECTED),
.USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]),
.USB1_VBUS_PWRFAULT(1'b0),
.USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED),
.WDT_CLK_IN(1'b0),
.WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED));
endmodule
(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *)
(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *)
(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "FALSE" *)
(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *)
(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *)
(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *)
(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *)
(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *)
(* C_NUM_F2P_INTR_INPUTS = "1" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *)
(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *)
(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *)
(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *)
(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *)
(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *)
(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *)
(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "0" *) (* C_USE_M_AXI_GP1 = "0" *)
(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *)
(* C_USE_S_AXI_HP0 = "0" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *)
(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "design_1_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *)
(* POWER = "<PROCESSOR name={system} numA9Cores={2} clockFreq={867} load={0.5} /><MEMORY name={code} memType={LPDDR2} dataWidth={32} clockFreq={400} readRate={0.5} writeRate={0.5} /><IO interface={UART} ioStandard={LVCMOS18} bidis={2} ioBank={Vcco_p1} clockFreq={49.999947} usageRate={0.5} /><IO interface={SD} ioStandard={LVCMOS18} bidis={6} ioBank={Vcco_p1} clockFreq={99.999893} usageRate={0.5} /><PLL domain={Processor} vco={1733.332} /><PLL domain={Memory} vco={1599.998} /><PLL domain={IO} vco={1999.998} />/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *)
module design_1_processing_system7_0_0_processing_system7_v5_5_processing_system7
(CAN0_PHY_TX,
CAN0_PHY_RX,
CAN1_PHY_TX,
CAN1_PHY_RX,
ENET0_GMII_TX_EN,
ENET0_GMII_TX_ER,
ENET0_MDIO_MDC,
ENET0_MDIO_O,
ENET0_MDIO_T,
ENET0_PTP_DELAY_REQ_RX,
ENET0_PTP_DELAY_REQ_TX,
ENET0_PTP_PDELAY_REQ_RX,
ENET0_PTP_PDELAY_REQ_TX,
ENET0_PTP_PDELAY_RESP_RX,
ENET0_PTP_PDELAY_RESP_TX,
ENET0_PTP_SYNC_FRAME_RX,
ENET0_PTP_SYNC_FRAME_TX,
ENET0_SOF_RX,
ENET0_SOF_TX,
ENET0_GMII_TXD,
ENET0_GMII_COL,
ENET0_GMII_CRS,
ENET0_GMII_RX_CLK,
ENET0_GMII_RX_DV,
ENET0_GMII_RX_ER,
ENET0_GMII_TX_CLK,
ENET0_MDIO_I,
ENET0_EXT_INTIN,
ENET0_GMII_RXD,
ENET1_GMII_TX_EN,
ENET1_GMII_TX_ER,
ENET1_MDIO_MDC,
ENET1_MDIO_O,
ENET1_MDIO_T,
ENET1_PTP_DELAY_REQ_RX,
ENET1_PTP_DELAY_REQ_TX,
ENET1_PTP_PDELAY_REQ_RX,
ENET1_PTP_PDELAY_REQ_TX,
ENET1_PTP_PDELAY_RESP_RX,
ENET1_PTP_PDELAY_RESP_TX,
ENET1_PTP_SYNC_FRAME_RX,
ENET1_PTP_SYNC_FRAME_TX,
ENET1_SOF_RX,
ENET1_SOF_TX,
ENET1_GMII_TXD,
ENET1_GMII_COL,
ENET1_GMII_CRS,
ENET1_GMII_RX_CLK,
ENET1_GMII_RX_DV,
ENET1_GMII_RX_ER,
ENET1_GMII_TX_CLK,
ENET1_MDIO_I,
ENET1_EXT_INTIN,
ENET1_GMII_RXD,
GPIO_I,
GPIO_O,
GPIO_T,
I2C0_SDA_I,
I2C0_SDA_O,
I2C0_SDA_T,
I2C0_SCL_I,
I2C0_SCL_O,
I2C0_SCL_T,
I2C1_SDA_I,
I2C1_SDA_O,
I2C1_SDA_T,
I2C1_SCL_I,
I2C1_SCL_O,
I2C1_SCL_T,
PJTAG_TCK,
PJTAG_TMS,
PJTAG_TDI,
PJTAG_TDO,
SDIO0_CLK,
SDIO0_CLK_FB,
SDIO0_CMD_O,
SDIO0_CMD_I,
SDIO0_CMD_T,
SDIO0_DATA_I,
SDIO0_DATA_O,
SDIO0_DATA_T,
SDIO0_LED,
SDIO0_CDN,
SDIO0_WP,
SDIO0_BUSPOW,
SDIO0_BUSVOLT,
SDIO1_CLK,
SDIO1_CLK_FB,
SDIO1_CMD_O,
SDIO1_CMD_I,
SDIO1_CMD_T,
SDIO1_DATA_I,
SDIO1_DATA_O,
SDIO1_DATA_T,
SDIO1_LED,
SDIO1_CDN,
SDIO1_WP,
SDIO1_BUSPOW,
SDIO1_BUSVOLT,
SPI0_SCLK_I,
SPI0_SCLK_O,
SPI0_SCLK_T,
SPI0_MOSI_I,
SPI0_MOSI_O,
SPI0_MOSI_T,
SPI0_MISO_I,
SPI0_MISO_O,
SPI0_MISO_T,
SPI0_SS_I,
SPI0_SS_O,
SPI0_SS1_O,
SPI0_SS2_O,
SPI0_SS_T,
SPI1_SCLK_I,
SPI1_SCLK_O,
SPI1_SCLK_T,
SPI1_MOSI_I,
SPI1_MOSI_O,
SPI1_MOSI_T,
SPI1_MISO_I,
SPI1_MISO_O,
SPI1_MISO_T,
SPI1_SS_I,
SPI1_SS_O,
SPI1_SS1_O,
SPI1_SS2_O,
SPI1_SS_T,
UART0_DTRN,
UART0_RTSN,
UART0_TX,
UART0_CTSN,
UART0_DCDN,
UART0_DSRN,
UART0_RIN,
UART0_RX,
UART1_DTRN,
UART1_RTSN,
UART1_TX,
UART1_CTSN,
UART1_DCDN,
UART1_DSRN,
UART1_RIN,
UART1_RX,
TTC0_WAVE0_OUT,
TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT,
TTC0_CLK0_IN,
TTC0_CLK1_IN,
TTC0_CLK2_IN,
TTC1_WAVE0_OUT,
TTC1_WAVE1_OUT,
TTC1_WAVE2_OUT,
TTC1_CLK0_IN,
TTC1_CLK1_IN,
TTC1_CLK2_IN,
WDT_CLK_IN,
WDT_RST_OUT,
TRACE_CLK,
TRACE_CTL,
TRACE_DATA,
TRACE_CLK_OUT,
USB0_PORT_INDCTL,
USB0_VBUS_PWRSELECT,
USB0_VBUS_PWRFAULT,
USB1_PORT_INDCTL,
USB1_VBUS_PWRSELECT,
USB1_VBUS_PWRFAULT,
SRAM_INTIN,
M_AXI_GP0_ARESETN,
M_AXI_GP0_ARVALID,
M_AXI_GP0_AWVALID,
M_AXI_GP0_BREADY,
M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST,
M_AXI_GP0_WVALID,
M_AXI_GP0_ARID,
M_AXI_GP0_AWID,
M_AXI_GP0_WID,
M_AXI_GP0_ARBURST,
M_AXI_GP0_ARLOCK,
M_AXI_GP0_ARSIZE,
M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK,
M_AXI_GP0_AWSIZE,
M_AXI_GP0_ARPROT,
M_AXI_GP0_AWPROT,
M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR,
M_AXI_GP0_WDATA,
M_AXI_GP0_ARCACHE,
M_AXI_GP0_ARLEN,
M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE,
M_AXI_GP0_AWLEN,
M_AXI_GP0_AWQOS,
M_AXI_GP0_WSTRB,
M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY,
M_AXI_GP0_AWREADY,
M_AXI_GP0_BVALID,
M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID,
M_AXI_GP0_WREADY,
M_AXI_GP0_BID,
M_AXI_GP0_RID,
M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP,
M_AXI_GP0_RDATA,
M_AXI_GP1_ARESETN,
M_AXI_GP1_ARVALID,
M_AXI_GP1_AWVALID,
M_AXI_GP1_BREADY,
M_AXI_GP1_RREADY,
M_AXI_GP1_WLAST,
M_AXI_GP1_WVALID,
M_AXI_GP1_ARID,
M_AXI_GP1_AWID,
M_AXI_GP1_WID,
M_AXI_GP1_ARBURST,
M_AXI_GP1_ARLOCK,
M_AXI_GP1_ARSIZE,
M_AXI_GP1_AWBURST,
M_AXI_GP1_AWLOCK,
M_AXI_GP1_AWSIZE,
M_AXI_GP1_ARPROT,
M_AXI_GP1_AWPROT,
M_AXI_GP1_ARADDR,
M_AXI_GP1_AWADDR,
M_AXI_GP1_WDATA,
M_AXI_GP1_ARCACHE,
M_AXI_GP1_ARLEN,
M_AXI_GP1_ARQOS,
M_AXI_GP1_AWCACHE,
M_AXI_GP1_AWLEN,
M_AXI_GP1_AWQOS,
M_AXI_GP1_WSTRB,
M_AXI_GP1_ACLK,
M_AXI_GP1_ARREADY,
M_AXI_GP1_AWREADY,
M_AXI_GP1_BVALID,
M_AXI_GP1_RLAST,
M_AXI_GP1_RVALID,
M_AXI_GP1_WREADY,
M_AXI_GP1_BID,
M_AXI_GP1_RID,
M_AXI_GP1_BRESP,
M_AXI_GP1_RRESP,
M_AXI_GP1_RDATA,
S_AXI_GP0_ARESETN,
S_AXI_GP0_ARREADY,
S_AXI_GP0_AWREADY,
S_AXI_GP0_BVALID,
S_AXI_GP0_RLAST,
S_AXI_GP0_RVALID,
S_AXI_GP0_WREADY,
S_AXI_GP0_BRESP,
S_AXI_GP0_RRESP,
S_AXI_GP0_RDATA,
S_AXI_GP0_BID,
S_AXI_GP0_RID,
S_AXI_GP0_ACLK,
S_AXI_GP0_ARVALID,
S_AXI_GP0_AWVALID,
S_AXI_GP0_BREADY,
S_AXI_GP0_RREADY,
S_AXI_GP0_WLAST,
S_AXI_GP0_WVALID,
S_AXI_GP0_ARBURST,
S_AXI_GP0_ARLOCK,
S_AXI_GP0_ARSIZE,
S_AXI_GP0_AWBURST,
S_AXI_GP0_AWLOCK,
S_AXI_GP0_AWSIZE,
S_AXI_GP0_ARPROT,
S_AXI_GP0_AWPROT,
S_AXI_GP0_ARADDR,
S_AXI_GP0_AWADDR,
S_AXI_GP0_WDATA,
S_AXI_GP0_ARCACHE,
S_AXI_GP0_ARLEN,
S_AXI_GP0_ARQOS,
S_AXI_GP0_AWCACHE,
S_AXI_GP0_AWLEN,
S_AXI_GP0_AWQOS,
S_AXI_GP0_WSTRB,
S_AXI_GP0_ARID,
S_AXI_GP0_AWID,
S_AXI_GP0_WID,
S_AXI_GP1_ARESETN,
S_AXI_GP1_ARREADY,
S_AXI_GP1_AWREADY,
S_AXI_GP1_BVALID,
S_AXI_GP1_RLAST,
S_AXI_GP1_RVALID,
S_AXI_GP1_WREADY,
S_AXI_GP1_BRESP,
S_AXI_GP1_RRESP,
S_AXI_GP1_RDATA,
S_AXI_GP1_BID,
S_AXI_GP1_RID,
S_AXI_GP1_ACLK,
S_AXI_GP1_ARVALID,
S_AXI_GP1_AWVALID,
S_AXI_GP1_BREADY,
S_AXI_GP1_RREADY,
S_AXI_GP1_WLAST,
S_AXI_GP1_WVALID,
S_AXI_GP1_ARBURST,
S_AXI_GP1_ARLOCK,
S_AXI_GP1_ARSIZE,
S_AXI_GP1_AWBURST,
S_AXI_GP1_AWLOCK,
S_AXI_GP1_AWSIZE,
S_AXI_GP1_ARPROT,
S_AXI_GP1_AWPROT,
S_AXI_GP1_ARADDR,
S_AXI_GP1_AWADDR,
S_AXI_GP1_WDATA,
S_AXI_GP1_ARCACHE,
S_AXI_GP1_ARLEN,
S_AXI_GP1_ARQOS,
S_AXI_GP1_AWCACHE,
S_AXI_GP1_AWLEN,
S_AXI_GP1_AWQOS,
S_AXI_GP1_WSTRB,
S_AXI_GP1_ARID,
S_AXI_GP1_AWID,
S_AXI_GP1_WID,
S_AXI_ACP_ARESETN,
S_AXI_ACP_ARREADY,
S_AXI_ACP_AWREADY,
S_AXI_ACP_BVALID,
S_AXI_ACP_RLAST,
S_AXI_ACP_RVALID,
S_AXI_ACP_WREADY,
S_AXI_ACP_BRESP,
S_AXI_ACP_RRESP,
S_AXI_ACP_BID,
S_AXI_ACP_RID,
S_AXI_ACP_RDATA,
S_AXI_ACP_ACLK,
S_AXI_ACP_ARVALID,
S_AXI_ACP_AWVALID,
S_AXI_ACP_BREADY,
S_AXI_ACP_RREADY,
S_AXI_ACP_WLAST,
S_AXI_ACP_WVALID,
S_AXI_ACP_ARID,
S_AXI_ACP_ARPROT,
S_AXI_ACP_AWID,
S_AXI_ACP_AWPROT,
S_AXI_ACP_WID,
S_AXI_ACP_ARADDR,
S_AXI_ACP_AWADDR,
S_AXI_ACP_ARCACHE,
S_AXI_ACP_ARLEN,
S_AXI_ACP_ARQOS,
S_AXI_ACP_AWCACHE,
S_AXI_ACP_AWLEN,
S_AXI_ACP_AWQOS,
S_AXI_ACP_ARBURST,
S_AXI_ACP_ARLOCK,
S_AXI_ACP_ARSIZE,
S_AXI_ACP_AWBURST,
S_AXI_ACP_AWLOCK,
S_AXI_ACP_AWSIZE,
S_AXI_ACP_ARUSER,
S_AXI_ACP_AWUSER,
S_AXI_ACP_WDATA,
S_AXI_ACP_WSTRB,
S_AXI_HP0_ARESETN,
S_AXI_HP0_ARREADY,
S_AXI_HP0_AWREADY,
S_AXI_HP0_BVALID,
S_AXI_HP0_RLAST,
S_AXI_HP0_RVALID,
S_AXI_HP0_WREADY,
S_AXI_HP0_BRESP,
S_AXI_HP0_RRESP,
S_AXI_HP0_BID,
S_AXI_HP0_RID,
S_AXI_HP0_RDATA,
S_AXI_HP0_RCOUNT,
S_AXI_HP0_WCOUNT,
S_AXI_HP0_RACOUNT,
S_AXI_HP0_WACOUNT,
S_AXI_HP0_ACLK,
S_AXI_HP0_ARVALID,
S_AXI_HP0_AWVALID,
S_AXI_HP0_BREADY,
S_AXI_HP0_RDISSUECAP1_EN,
S_AXI_HP0_RREADY,
S_AXI_HP0_WLAST,
S_AXI_HP0_WRISSUECAP1_EN,
S_AXI_HP0_WVALID,
S_AXI_HP0_ARBURST,
S_AXI_HP0_ARLOCK,
S_AXI_HP0_ARSIZE,
S_AXI_HP0_AWBURST,
S_AXI_HP0_AWLOCK,
S_AXI_HP0_AWSIZE,
S_AXI_HP0_ARPROT,
S_AXI_HP0_AWPROT,
S_AXI_HP0_ARADDR,
S_AXI_HP0_AWADDR,
S_AXI_HP0_ARCACHE,
S_AXI_HP0_ARLEN,
S_AXI_HP0_ARQOS,
S_AXI_HP0_AWCACHE,
S_AXI_HP0_AWLEN,
S_AXI_HP0_AWQOS,
S_AXI_HP0_ARID,
S_AXI_HP0_AWID,
S_AXI_HP0_WID,
S_AXI_HP0_WDATA,
S_AXI_HP0_WSTRB,
S_AXI_HP1_ARESETN,
S_AXI_HP1_ARREADY,
S_AXI_HP1_AWREADY,
S_AXI_HP1_BVALID,
S_AXI_HP1_RLAST,
S_AXI_HP1_RVALID,
S_AXI_HP1_WREADY,
S_AXI_HP1_BRESP,
S_AXI_HP1_RRESP,
S_AXI_HP1_BID,
S_AXI_HP1_RID,
S_AXI_HP1_RDATA,
S_AXI_HP1_RCOUNT,
S_AXI_HP1_WCOUNT,
S_AXI_HP1_RACOUNT,
S_AXI_HP1_WACOUNT,
S_AXI_HP1_ACLK,
S_AXI_HP1_ARVALID,
S_AXI_HP1_AWVALID,
S_AXI_HP1_BREADY,
S_AXI_HP1_RDISSUECAP1_EN,
S_AXI_HP1_RREADY,
S_AXI_HP1_WLAST,
S_AXI_HP1_WRISSUECAP1_EN,
S_AXI_HP1_WVALID,
S_AXI_HP1_ARBURST,
S_AXI_HP1_ARLOCK,
S_AXI_HP1_ARSIZE,
S_AXI_HP1_AWBURST,
S_AXI_HP1_AWLOCK,
S_AXI_HP1_AWSIZE,
S_AXI_HP1_ARPROT,
S_AXI_HP1_AWPROT,
S_AXI_HP1_ARADDR,
S_AXI_HP1_AWADDR,
S_AXI_HP1_ARCACHE,
S_AXI_HP1_ARLEN,
S_AXI_HP1_ARQOS,
S_AXI_HP1_AWCACHE,
S_AXI_HP1_AWLEN,
S_AXI_HP1_AWQOS,
S_AXI_HP1_ARID,
S_AXI_HP1_AWID,
S_AXI_HP1_WID,
S_AXI_HP1_WDATA,
S_AXI_HP1_WSTRB,
S_AXI_HP2_ARESETN,
S_AXI_HP2_ARREADY,
S_AXI_HP2_AWREADY,
S_AXI_HP2_BVALID,
S_AXI_HP2_RLAST,
S_AXI_HP2_RVALID,
S_AXI_HP2_WREADY,
S_AXI_HP2_BRESP,
S_AXI_HP2_RRESP,
S_AXI_HP2_BID,
S_AXI_HP2_RID,
S_AXI_HP2_RDATA,
S_AXI_HP2_RCOUNT,
S_AXI_HP2_WCOUNT,
S_AXI_HP2_RACOUNT,
S_AXI_HP2_WACOUNT,
S_AXI_HP2_ACLK,
S_AXI_HP2_ARVALID,
S_AXI_HP2_AWVALID,
S_AXI_HP2_BREADY,
S_AXI_HP2_RDISSUECAP1_EN,
S_AXI_HP2_RREADY,
S_AXI_HP2_WLAST,
S_AXI_HP2_WRISSUECAP1_EN,
S_AXI_HP2_WVALID,
S_AXI_HP2_ARBURST,
S_AXI_HP2_ARLOCK,
S_AXI_HP2_ARSIZE,
S_AXI_HP2_AWBURST,
S_AXI_HP2_AWLOCK,
S_AXI_HP2_AWSIZE,
S_AXI_HP2_ARPROT,
S_AXI_HP2_AWPROT,
S_AXI_HP2_ARADDR,
S_AXI_HP2_AWADDR,
S_AXI_HP2_ARCACHE,
S_AXI_HP2_ARLEN,
S_AXI_HP2_ARQOS,
S_AXI_HP2_AWCACHE,
S_AXI_HP2_AWLEN,
S_AXI_HP2_AWQOS,
S_AXI_HP2_ARID,
S_AXI_HP2_AWID,
S_AXI_HP2_WID,
S_AXI_HP2_WDATA,
S_AXI_HP2_WSTRB,
S_AXI_HP3_ARESETN,
S_AXI_HP3_ARREADY,
S_AXI_HP3_AWREADY,
S_AXI_HP3_BVALID,
S_AXI_HP3_RLAST,
S_AXI_HP3_RVALID,
S_AXI_HP3_WREADY,
S_AXI_HP3_BRESP,
S_AXI_HP3_RRESP,
S_AXI_HP3_BID,
S_AXI_HP3_RID,
S_AXI_HP3_RDATA,
S_AXI_HP3_RCOUNT,
S_AXI_HP3_WCOUNT,
S_AXI_HP3_RACOUNT,
S_AXI_HP3_WACOUNT,
S_AXI_HP3_ACLK,
S_AXI_HP3_ARVALID,
S_AXI_HP3_AWVALID,
S_AXI_HP3_BREADY,
S_AXI_HP3_RDISSUECAP1_EN,
S_AXI_HP3_RREADY,
S_AXI_HP3_WLAST,
S_AXI_HP3_WRISSUECAP1_EN,
S_AXI_HP3_WVALID,
S_AXI_HP3_ARBURST,
S_AXI_HP3_ARLOCK,
S_AXI_HP3_ARSIZE,
S_AXI_HP3_AWBURST,
S_AXI_HP3_AWLOCK,
S_AXI_HP3_AWSIZE,
S_AXI_HP3_ARPROT,
S_AXI_HP3_AWPROT,
S_AXI_HP3_ARADDR,
S_AXI_HP3_AWADDR,
S_AXI_HP3_ARCACHE,
S_AXI_HP3_ARLEN,
S_AXI_HP3_ARQOS,
S_AXI_HP3_AWCACHE,
S_AXI_HP3_AWLEN,
S_AXI_HP3_AWQOS,
S_AXI_HP3_ARID,
S_AXI_HP3_AWID,
S_AXI_HP3_WID,
S_AXI_HP3_WDATA,
S_AXI_HP3_WSTRB,
IRQ_P2F_DMAC_ABORT,
IRQ_P2F_DMAC0,
IRQ_P2F_DMAC1,
IRQ_P2F_DMAC2,
IRQ_P2F_DMAC3,
IRQ_P2F_DMAC4,
IRQ_P2F_DMAC5,
IRQ_P2F_DMAC6,
IRQ_P2F_DMAC7,
IRQ_P2F_SMC,
IRQ_P2F_QSPI,
IRQ_P2F_CTI,
IRQ_P2F_GPIO,
IRQ_P2F_USB0,
IRQ_P2F_ENET0,
IRQ_P2F_ENET_WAKE0,
IRQ_P2F_SDIO0,
IRQ_P2F_I2C0,
IRQ_P2F_SPI0,
IRQ_P2F_UART0,
IRQ_P2F_CAN0,
IRQ_P2F_USB1,
IRQ_P2F_ENET1,
IRQ_P2F_ENET_WAKE1,
IRQ_P2F_SDIO1,
IRQ_P2F_I2C1,
IRQ_P2F_SPI1,
IRQ_P2F_UART1,
IRQ_P2F_CAN1,
IRQ_F2P,
Core0_nFIQ,
Core0_nIRQ,
Core1_nFIQ,
Core1_nIRQ,
DMA0_DATYPE,
DMA0_DAVALID,
DMA0_DRREADY,
DMA0_RSTN,
DMA1_DATYPE,
DMA1_DAVALID,
DMA1_DRREADY,
DMA1_RSTN,
DMA2_DATYPE,
DMA2_DAVALID,
DMA2_DRREADY,
DMA2_RSTN,
DMA3_DATYPE,
DMA3_DAVALID,
DMA3_DRREADY,
DMA3_RSTN,
DMA0_ACLK,
DMA0_DAREADY,
DMA0_DRLAST,
DMA0_DRVALID,
DMA1_ACLK,
DMA1_DAREADY,
DMA1_DRLAST,
DMA1_DRVALID,
DMA2_ACLK,
DMA2_DAREADY,
DMA2_DRLAST,
DMA2_DRVALID,
DMA3_ACLK,
DMA3_DAREADY,
DMA3_DRLAST,
DMA3_DRVALID,
DMA0_DRTYPE,
DMA1_DRTYPE,
DMA2_DRTYPE,
DMA3_DRTYPE,
FCLK_CLK3,
FCLK_CLK2,
FCLK_CLK1,
FCLK_CLK0,
FCLK_CLKTRIG3_N,
FCLK_CLKTRIG2_N,
FCLK_CLKTRIG1_N,
FCLK_CLKTRIG0_N,
FCLK_RESET3_N,
FCLK_RESET2_N,
FCLK_RESET1_N,
FCLK_RESET0_N,
FTMD_TRACEIN_DATA,
FTMD_TRACEIN_VALID,
FTMD_TRACEIN_CLK,
FTMD_TRACEIN_ATID,
FTMT_F2P_TRIG_0,
FTMT_F2P_TRIGACK_0,
FTMT_F2P_TRIG_1,
FTMT_F2P_TRIGACK_1,
FTMT_F2P_TRIG_2,
FTMT_F2P_TRIGACK_2,
FTMT_F2P_TRIG_3,
FTMT_F2P_TRIGACK_3,
FTMT_F2P_DEBUG,
FTMT_P2F_TRIGACK_0,
FTMT_P2F_TRIG_0,
FTMT_P2F_TRIGACK_1,
FTMT_P2F_TRIG_1,
FTMT_P2F_TRIGACK_2,
FTMT_P2F_TRIG_2,
FTMT_P2F_TRIGACK_3,
FTMT_P2F_TRIG_3,
FTMT_P2F_DEBUG,
FPGA_IDLE_N,
EVENT_EVENTO,
EVENT_STANDBYWFE,
EVENT_STANDBYWFI,
EVENT_EVENTI,
DDR_ARB,
MIO,
DDR_CAS_n,
DDR_CKE,
DDR_Clk_n,
DDR_Clk,
DDR_CS_n,
DDR_DRSTB,
DDR_ODT,
DDR_RAS_n,
DDR_WEB,
DDR_BankAddr,
DDR_Addr,
DDR_VRN,
DDR_VRP,
DDR_DM,
DDR_DQ,
DDR_DQS_n,
DDR_DQS,
PS_SRSTB,
PS_CLK,
PS_PORB);
output CAN0_PHY_TX;
input CAN0_PHY_RX;
output CAN1_PHY_TX;
input CAN1_PHY_RX;
output ENET0_GMII_TX_EN;
output ENET0_GMII_TX_ER;
output ENET0_MDIO_MDC;
output ENET0_MDIO_O;
output ENET0_MDIO_T;
output ENET0_PTP_DELAY_REQ_RX;
output ENET0_PTP_DELAY_REQ_TX;
output ENET0_PTP_PDELAY_REQ_RX;
output ENET0_PTP_PDELAY_REQ_TX;
output ENET0_PTP_PDELAY_RESP_RX;
output ENET0_PTP_PDELAY_RESP_TX;
output ENET0_PTP_SYNC_FRAME_RX;
output ENET0_PTP_SYNC_FRAME_TX;
output ENET0_SOF_RX;
output ENET0_SOF_TX;
output [7:0]ENET0_GMII_TXD;
input ENET0_GMII_COL;
input ENET0_GMII_CRS;
input ENET0_GMII_RX_CLK;
input ENET0_GMII_RX_DV;
input ENET0_GMII_RX_ER;
input ENET0_GMII_TX_CLK;
input ENET0_MDIO_I;
input ENET0_EXT_INTIN;
input [7:0]ENET0_GMII_RXD;
output ENET1_GMII_TX_EN;
output ENET1_GMII_TX_ER;
output ENET1_MDIO_MDC;
output ENET1_MDIO_O;
output ENET1_MDIO_T;
output ENET1_PTP_DELAY_REQ_RX;
output ENET1_PTP_DELAY_REQ_TX;
output ENET1_PTP_PDELAY_REQ_RX;
output ENET1_PTP_PDELAY_REQ_TX;
output ENET1_PTP_PDELAY_RESP_RX;
output ENET1_PTP_PDELAY_RESP_TX;
output ENET1_PTP_SYNC_FRAME_RX;
output ENET1_PTP_SYNC_FRAME_TX;
output ENET1_SOF_RX;
output ENET1_SOF_TX;
output [7:0]ENET1_GMII_TXD;
input ENET1_GMII_COL;
input ENET1_GMII_CRS;
input ENET1_GMII_RX_CLK;
input ENET1_GMII_RX_DV;
input ENET1_GMII_RX_ER;
input ENET1_GMII_TX_CLK;
input ENET1_MDIO_I;
input ENET1_EXT_INTIN;
input [7:0]ENET1_GMII_RXD;
input [63:0]GPIO_I;
output [63:0]GPIO_O;
output [63:0]GPIO_T;
input I2C0_SDA_I;
output I2C0_SDA_O;
output I2C0_SDA_T;
input I2C0_SCL_I;
output I2C0_SCL_O;
output I2C0_SCL_T;
input I2C1_SDA_I;
output I2C1_SDA_O;
output I2C1_SDA_T;
input I2C1_SCL_I;
output I2C1_SCL_O;
output I2C1_SCL_T;
input PJTAG_TCK;
input PJTAG_TMS;
input PJTAG_TDI;
output PJTAG_TDO;
output SDIO0_CLK;
input SDIO0_CLK_FB;
output SDIO0_CMD_O;
input SDIO0_CMD_I;
output SDIO0_CMD_T;
input [3:0]SDIO0_DATA_I;
output [3:0]SDIO0_DATA_O;
output [3:0]SDIO0_DATA_T;
output SDIO0_LED;
input SDIO0_CDN;
input SDIO0_WP;
output SDIO0_BUSPOW;
output [2:0]SDIO0_BUSVOLT;
output SDIO1_CLK;
input SDIO1_CLK_FB;
output SDIO1_CMD_O;
input SDIO1_CMD_I;
output SDIO1_CMD_T;
input [3:0]SDIO1_DATA_I;
output [3:0]SDIO1_DATA_O;
output [3:0]SDIO1_DATA_T;
output SDIO1_LED;
input SDIO1_CDN;
input SDIO1_WP;
output SDIO1_BUSPOW;
output [2:0]SDIO1_BUSVOLT;
input SPI0_SCLK_I;
output SPI0_SCLK_O;
output SPI0_SCLK_T;
input SPI0_MOSI_I;
output SPI0_MOSI_O;
output SPI0_MOSI_T;
input SPI0_MISO_I;
output SPI0_MISO_O;
output SPI0_MISO_T;
input SPI0_SS_I;
output SPI0_SS_O;
output SPI0_SS1_O;
output SPI0_SS2_O;
output SPI0_SS_T;
input SPI1_SCLK_I;
output SPI1_SCLK_O;
output SPI1_SCLK_T;
input SPI1_MOSI_I;
output SPI1_MOSI_O;
output SPI1_MOSI_T;
input SPI1_MISO_I;
output SPI1_MISO_O;
output SPI1_MISO_T;
input SPI1_SS_I;
output SPI1_SS_O;
output SPI1_SS1_O;
output SPI1_SS2_O;
output SPI1_SS_T;
output UART0_DTRN;
output UART0_RTSN;
output UART0_TX;
input UART0_CTSN;
input UART0_DCDN;
input UART0_DSRN;
input UART0_RIN;
input UART0_RX;
output UART1_DTRN;
output UART1_RTSN;
output UART1_TX;
input UART1_CTSN;
input UART1_DCDN;
input UART1_DSRN;
input UART1_RIN;
input UART1_RX;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
input TTC0_CLK0_IN;
input TTC0_CLK1_IN;
input TTC0_CLK2_IN;
output TTC1_WAVE0_OUT;
output TTC1_WAVE1_OUT;
output TTC1_WAVE2_OUT;
input TTC1_CLK0_IN;
input TTC1_CLK1_IN;
input TTC1_CLK2_IN;
input WDT_CLK_IN;
output WDT_RST_OUT;
input TRACE_CLK;
output TRACE_CTL;
output [1:0]TRACE_DATA;
output TRACE_CLK_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output [1:0]USB1_PORT_INDCTL;
output USB1_VBUS_PWRSELECT;
input USB1_VBUS_PWRFAULT;
input SRAM_INTIN;
output M_AXI_GP0_ARESETN;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
output M_AXI_GP1_ARESETN;
output M_AXI_GP1_ARVALID;
output M_AXI_GP1_AWVALID;
output M_AXI_GP1_BREADY;
output M_AXI_GP1_RREADY;
output M_AXI_GP1_WLAST;
output M_AXI_GP1_WVALID;
output [11:0]M_AXI_GP1_ARID;
output [11:0]M_AXI_GP1_AWID;
output [11:0]M_AXI_GP1_WID;
output [1:0]M_AXI_GP1_ARBURST;
output [1:0]M_AXI_GP1_ARLOCK;
output [2:0]M_AXI_GP1_ARSIZE;
output [1:0]M_AXI_GP1_AWBURST;
output [1:0]M_AXI_GP1_AWLOCK;
output [2:0]M_AXI_GP1_AWSIZE;
output [2:0]M_AXI_GP1_ARPROT;
output [2:0]M_AXI_GP1_AWPROT;
output [31:0]M_AXI_GP1_ARADDR;
output [31:0]M_AXI_GP1_AWADDR;
output [31:0]M_AXI_GP1_WDATA;
output [3:0]M_AXI_GP1_ARCACHE;
output [3:0]M_AXI_GP1_ARLEN;
output [3:0]M_AXI_GP1_ARQOS;
output [3:0]M_AXI_GP1_AWCACHE;
output [3:0]M_AXI_GP1_AWLEN;
output [3:0]M_AXI_GP1_AWQOS;
output [3:0]M_AXI_GP1_WSTRB;
input M_AXI_GP1_ACLK;
input M_AXI_GP1_ARREADY;
input M_AXI_GP1_AWREADY;
input M_AXI_GP1_BVALID;
input M_AXI_GP1_RLAST;
input M_AXI_GP1_RVALID;
input M_AXI_GP1_WREADY;
input [11:0]M_AXI_GP1_BID;
input [11:0]M_AXI_GP1_RID;
input [1:0]M_AXI_GP1_BRESP;
input [1:0]M_AXI_GP1_RRESP;
input [31:0]M_AXI_GP1_RDATA;
output S_AXI_GP0_ARESETN;
output S_AXI_GP0_ARREADY;
output S_AXI_GP0_AWREADY;
output S_AXI_GP0_BVALID;
output S_AXI_GP0_RLAST;
output S_AXI_GP0_RVALID;
output S_AXI_GP0_WREADY;
output [1:0]S_AXI_GP0_BRESP;
output [1:0]S_AXI_GP0_RRESP;
output [31:0]S_AXI_GP0_RDATA;
output [5:0]S_AXI_GP0_BID;
output [5:0]S_AXI_GP0_RID;
input S_AXI_GP0_ACLK;
input S_AXI_GP0_ARVALID;
input S_AXI_GP0_AWVALID;
input S_AXI_GP0_BREADY;
input S_AXI_GP0_RREADY;
input S_AXI_GP0_WLAST;
input S_AXI_GP0_WVALID;
input [1:0]S_AXI_GP0_ARBURST;
input [1:0]S_AXI_GP0_ARLOCK;
input [2:0]S_AXI_GP0_ARSIZE;
input [1:0]S_AXI_GP0_AWBURST;
input [1:0]S_AXI_GP0_AWLOCK;
input [2:0]S_AXI_GP0_AWSIZE;
input [2:0]S_AXI_GP0_ARPROT;
input [2:0]S_AXI_GP0_AWPROT;
input [31:0]S_AXI_GP0_ARADDR;
input [31:0]S_AXI_GP0_AWADDR;
input [31:0]S_AXI_GP0_WDATA;
input [3:0]S_AXI_GP0_ARCACHE;
input [3:0]S_AXI_GP0_ARLEN;
input [3:0]S_AXI_GP0_ARQOS;
input [3:0]S_AXI_GP0_AWCACHE;
input [3:0]S_AXI_GP0_AWLEN;
input [3:0]S_AXI_GP0_AWQOS;
input [3:0]S_AXI_GP0_WSTRB;
input [5:0]S_AXI_GP0_ARID;
input [5:0]S_AXI_GP0_AWID;
input [5:0]S_AXI_GP0_WID;
output S_AXI_GP1_ARESETN;
output S_AXI_GP1_ARREADY;
output S_AXI_GP1_AWREADY;
output S_AXI_GP1_BVALID;
output S_AXI_GP1_RLAST;
output S_AXI_GP1_RVALID;
output S_AXI_GP1_WREADY;
output [1:0]S_AXI_GP1_BRESP;
output [1:0]S_AXI_GP1_RRESP;
output [31:0]S_AXI_GP1_RDATA;
output [5:0]S_AXI_GP1_BID;
output [5:0]S_AXI_GP1_RID;
input S_AXI_GP1_ACLK;
input S_AXI_GP1_ARVALID;
input S_AXI_GP1_AWVALID;
input S_AXI_GP1_BREADY;
input S_AXI_GP1_RREADY;
input S_AXI_GP1_WLAST;
input S_AXI_GP1_WVALID;
input [1:0]S_AXI_GP1_ARBURST;
input [1:0]S_AXI_GP1_ARLOCK;
input [2:0]S_AXI_GP1_ARSIZE;
input [1:0]S_AXI_GP1_AWBURST;
input [1:0]S_AXI_GP1_AWLOCK;
input [2:0]S_AXI_GP1_AWSIZE;
input [2:0]S_AXI_GP1_ARPROT;
input [2:0]S_AXI_GP1_AWPROT;
input [31:0]S_AXI_GP1_ARADDR;
input [31:0]S_AXI_GP1_AWADDR;
input [31:0]S_AXI_GP1_WDATA;
input [3:0]S_AXI_GP1_ARCACHE;
input [3:0]S_AXI_GP1_ARLEN;
input [3:0]S_AXI_GP1_ARQOS;
input [3:0]S_AXI_GP1_AWCACHE;
input [3:0]S_AXI_GP1_AWLEN;
input [3:0]S_AXI_GP1_AWQOS;
input [3:0]S_AXI_GP1_WSTRB;
input [5:0]S_AXI_GP1_ARID;
input [5:0]S_AXI_GP1_AWID;
input [5:0]S_AXI_GP1_WID;
output S_AXI_ACP_ARESETN;
output S_AXI_ACP_ARREADY;
output S_AXI_ACP_AWREADY;
output S_AXI_ACP_BVALID;
output S_AXI_ACP_RLAST;
output S_AXI_ACP_RVALID;
output S_AXI_ACP_WREADY;
output [1:0]S_AXI_ACP_BRESP;
output [1:0]S_AXI_ACP_RRESP;
output [2:0]S_AXI_ACP_BID;
output [2:0]S_AXI_ACP_RID;
output [63:0]S_AXI_ACP_RDATA;
input S_AXI_ACP_ACLK;
input S_AXI_ACP_ARVALID;
input S_AXI_ACP_AWVALID;
input S_AXI_ACP_BREADY;
input S_AXI_ACP_RREADY;
input S_AXI_ACP_WLAST;
input S_AXI_ACP_WVALID;
input [2:0]S_AXI_ACP_ARID;
input [2:0]S_AXI_ACP_ARPROT;
input [2:0]S_AXI_ACP_AWID;
input [2:0]S_AXI_ACP_AWPROT;
input [2:0]S_AXI_ACP_WID;
input [31:0]S_AXI_ACP_ARADDR;
input [31:0]S_AXI_ACP_AWADDR;
input [3:0]S_AXI_ACP_ARCACHE;
input [3:0]S_AXI_ACP_ARLEN;
input [3:0]S_AXI_ACP_ARQOS;
input [3:0]S_AXI_ACP_AWCACHE;
input [3:0]S_AXI_ACP_AWLEN;
input [3:0]S_AXI_ACP_AWQOS;
input [1:0]S_AXI_ACP_ARBURST;
input [1:0]S_AXI_ACP_ARLOCK;
input [2:0]S_AXI_ACP_ARSIZE;
input [1:0]S_AXI_ACP_AWBURST;
input [1:0]S_AXI_ACP_AWLOCK;
input [2:0]S_AXI_ACP_AWSIZE;
input [4:0]S_AXI_ACP_ARUSER;
input [4:0]S_AXI_ACP_AWUSER;
input [63:0]S_AXI_ACP_WDATA;
input [7:0]S_AXI_ACP_WSTRB;
output S_AXI_HP0_ARESETN;
output S_AXI_HP0_ARREADY;
output S_AXI_HP0_AWREADY;
output S_AXI_HP0_BVALID;
output S_AXI_HP0_RLAST;
output S_AXI_HP0_RVALID;
output S_AXI_HP0_WREADY;
output [1:0]S_AXI_HP0_BRESP;
output [1:0]S_AXI_HP0_RRESP;
output [5:0]S_AXI_HP0_BID;
output [5:0]S_AXI_HP0_RID;
output [63:0]S_AXI_HP0_RDATA;
output [7:0]S_AXI_HP0_RCOUNT;
output [7:0]S_AXI_HP0_WCOUNT;
output [2:0]S_AXI_HP0_RACOUNT;
output [5:0]S_AXI_HP0_WACOUNT;
input S_AXI_HP0_ACLK;
input S_AXI_HP0_ARVALID;
input S_AXI_HP0_AWVALID;
input S_AXI_HP0_BREADY;
input S_AXI_HP0_RDISSUECAP1_EN;
input S_AXI_HP0_RREADY;
input S_AXI_HP0_WLAST;
input S_AXI_HP0_WRISSUECAP1_EN;
input S_AXI_HP0_WVALID;
input [1:0]S_AXI_HP0_ARBURST;
input [1:0]S_AXI_HP0_ARLOCK;
input [2:0]S_AXI_HP0_ARSIZE;
input [1:0]S_AXI_HP0_AWBURST;
input [1:0]S_AXI_HP0_AWLOCK;
input [2:0]S_AXI_HP0_AWSIZE;
input [2:0]S_AXI_HP0_ARPROT;
input [2:0]S_AXI_HP0_AWPROT;
input [31:0]S_AXI_HP0_ARADDR;
input [31:0]S_AXI_HP0_AWADDR;
input [3:0]S_AXI_HP0_ARCACHE;
input [3:0]S_AXI_HP0_ARLEN;
input [3:0]S_AXI_HP0_ARQOS;
input [3:0]S_AXI_HP0_AWCACHE;
input [3:0]S_AXI_HP0_AWLEN;
input [3:0]S_AXI_HP0_AWQOS;
input [5:0]S_AXI_HP0_ARID;
input [5:0]S_AXI_HP0_AWID;
input [5:0]S_AXI_HP0_WID;
input [63:0]S_AXI_HP0_WDATA;
input [7:0]S_AXI_HP0_WSTRB;
output S_AXI_HP1_ARESETN;
output S_AXI_HP1_ARREADY;
output S_AXI_HP1_AWREADY;
output S_AXI_HP1_BVALID;
output S_AXI_HP1_RLAST;
output S_AXI_HP1_RVALID;
output S_AXI_HP1_WREADY;
output [1:0]S_AXI_HP1_BRESP;
output [1:0]S_AXI_HP1_RRESP;
output [5:0]S_AXI_HP1_BID;
output [5:0]S_AXI_HP1_RID;
output [63:0]S_AXI_HP1_RDATA;
output [7:0]S_AXI_HP1_RCOUNT;
output [7:0]S_AXI_HP1_WCOUNT;
output [2:0]S_AXI_HP1_RACOUNT;
output [5:0]S_AXI_HP1_WACOUNT;
input S_AXI_HP1_ACLK;
input S_AXI_HP1_ARVALID;
input S_AXI_HP1_AWVALID;
input S_AXI_HP1_BREADY;
input S_AXI_HP1_RDISSUECAP1_EN;
input S_AXI_HP1_RREADY;
input S_AXI_HP1_WLAST;
input S_AXI_HP1_WRISSUECAP1_EN;
input S_AXI_HP1_WVALID;
input [1:0]S_AXI_HP1_ARBURST;
input [1:0]S_AXI_HP1_ARLOCK;
input [2:0]S_AXI_HP1_ARSIZE;
input [1:0]S_AXI_HP1_AWBURST;
input [1:0]S_AXI_HP1_AWLOCK;
input [2:0]S_AXI_HP1_AWSIZE;
input [2:0]S_AXI_HP1_ARPROT;
input [2:0]S_AXI_HP1_AWPROT;
input [31:0]S_AXI_HP1_ARADDR;
input [31:0]S_AXI_HP1_AWADDR;
input [3:0]S_AXI_HP1_ARCACHE;
input [3:0]S_AXI_HP1_ARLEN;
input [3:0]S_AXI_HP1_ARQOS;
input [3:0]S_AXI_HP1_AWCACHE;
input [3:0]S_AXI_HP1_AWLEN;
input [3:0]S_AXI_HP1_AWQOS;
input [5:0]S_AXI_HP1_ARID;
input [5:0]S_AXI_HP1_AWID;
input [5:0]S_AXI_HP1_WID;
input [63:0]S_AXI_HP1_WDATA;
input [7:0]S_AXI_HP1_WSTRB;
output S_AXI_HP2_ARESETN;
output S_AXI_HP2_ARREADY;
output S_AXI_HP2_AWREADY;
output S_AXI_HP2_BVALID;
output S_AXI_HP2_RLAST;
output S_AXI_HP2_RVALID;
output S_AXI_HP2_WREADY;
output [1:0]S_AXI_HP2_BRESP;
output [1:0]S_AXI_HP2_RRESP;
output [5:0]S_AXI_HP2_BID;
output [5:0]S_AXI_HP2_RID;
output [63:0]S_AXI_HP2_RDATA;
output [7:0]S_AXI_HP2_RCOUNT;
output [7:0]S_AXI_HP2_WCOUNT;
output [2:0]S_AXI_HP2_RACOUNT;
output [5:0]S_AXI_HP2_WACOUNT;
input S_AXI_HP2_ACLK;
input S_AXI_HP2_ARVALID;
input S_AXI_HP2_AWVALID;
input S_AXI_HP2_BREADY;
input S_AXI_HP2_RDISSUECAP1_EN;
input S_AXI_HP2_RREADY;
input S_AXI_HP2_WLAST;
input S_AXI_HP2_WRISSUECAP1_EN;
input S_AXI_HP2_WVALID;
input [1:0]S_AXI_HP2_ARBURST;
input [1:0]S_AXI_HP2_ARLOCK;
input [2:0]S_AXI_HP2_ARSIZE;
input [1:0]S_AXI_HP2_AWBURST;
input [1:0]S_AXI_HP2_AWLOCK;
input [2:0]S_AXI_HP2_AWSIZE;
input [2:0]S_AXI_HP2_ARPROT;
input [2:0]S_AXI_HP2_AWPROT;
input [31:0]S_AXI_HP2_ARADDR;
input [31:0]S_AXI_HP2_AWADDR;
input [3:0]S_AXI_HP2_ARCACHE;
input [3:0]S_AXI_HP2_ARLEN;
input [3:0]S_AXI_HP2_ARQOS;
input [3:0]S_AXI_HP2_AWCACHE;
input [3:0]S_AXI_HP2_AWLEN;
input [3:0]S_AXI_HP2_AWQOS;
input [5:0]S_AXI_HP2_ARID;
input [5:0]S_AXI_HP2_AWID;
input [5:0]S_AXI_HP2_WID;
input [63:0]S_AXI_HP2_WDATA;
input [7:0]S_AXI_HP2_WSTRB;
output S_AXI_HP3_ARESETN;
output S_AXI_HP3_ARREADY;
output S_AXI_HP3_AWREADY;
output S_AXI_HP3_BVALID;
output S_AXI_HP3_RLAST;
output S_AXI_HP3_RVALID;
output S_AXI_HP3_WREADY;
output [1:0]S_AXI_HP3_BRESP;
output [1:0]S_AXI_HP3_RRESP;
output [5:0]S_AXI_HP3_BID;
output [5:0]S_AXI_HP3_RID;
output [63:0]S_AXI_HP3_RDATA;
output [7:0]S_AXI_HP3_RCOUNT;
output [7:0]S_AXI_HP3_WCOUNT;
output [2:0]S_AXI_HP3_RACOUNT;
output [5:0]S_AXI_HP3_WACOUNT;
input S_AXI_HP3_ACLK;
input S_AXI_HP3_ARVALID;
input S_AXI_HP3_AWVALID;
input S_AXI_HP3_BREADY;
input S_AXI_HP3_RDISSUECAP1_EN;
input S_AXI_HP3_RREADY;
input S_AXI_HP3_WLAST;
input S_AXI_HP3_WRISSUECAP1_EN;
input S_AXI_HP3_WVALID;
input [1:0]S_AXI_HP3_ARBURST;
input [1:0]S_AXI_HP3_ARLOCK;
input [2:0]S_AXI_HP3_ARSIZE;
input [1:0]S_AXI_HP3_AWBURST;
input [1:0]S_AXI_HP3_AWLOCK;
input [2:0]S_AXI_HP3_AWSIZE;
input [2:0]S_AXI_HP3_ARPROT;
input [2:0]S_AXI_HP3_AWPROT;
input [31:0]S_AXI_HP3_ARADDR;
input [31:0]S_AXI_HP3_AWADDR;
input [3:0]S_AXI_HP3_ARCACHE;
input [3:0]S_AXI_HP3_ARLEN;
input [3:0]S_AXI_HP3_ARQOS;
input [3:0]S_AXI_HP3_AWCACHE;
input [3:0]S_AXI_HP3_AWLEN;
input [3:0]S_AXI_HP3_AWQOS;
input [5:0]S_AXI_HP3_ARID;
input [5:0]S_AXI_HP3_AWID;
input [5:0]S_AXI_HP3_WID;
input [63:0]S_AXI_HP3_WDATA;
input [7:0]S_AXI_HP3_WSTRB;
output IRQ_P2F_DMAC_ABORT;
output IRQ_P2F_DMAC0;
output IRQ_P2F_DMAC1;
output IRQ_P2F_DMAC2;
output IRQ_P2F_DMAC3;
output IRQ_P2F_DMAC4;
output IRQ_P2F_DMAC5;
output IRQ_P2F_DMAC6;
output IRQ_P2F_DMAC7;
output IRQ_P2F_SMC;
output IRQ_P2F_QSPI;
output IRQ_P2F_CTI;
output IRQ_P2F_GPIO;
output IRQ_P2F_USB0;
output IRQ_P2F_ENET0;
output IRQ_P2F_ENET_WAKE0;
output IRQ_P2F_SDIO0;
output IRQ_P2F_I2C0;
output IRQ_P2F_SPI0;
output IRQ_P2F_UART0;
output IRQ_P2F_CAN0;
output IRQ_P2F_USB1;
output IRQ_P2F_ENET1;
output IRQ_P2F_ENET_WAKE1;
output IRQ_P2F_SDIO1;
output IRQ_P2F_I2C1;
output IRQ_P2F_SPI1;
output IRQ_P2F_UART1;
output IRQ_P2F_CAN1;
input [0:0]IRQ_F2P;
input Core0_nFIQ;
input Core0_nIRQ;
input Core1_nFIQ;
input Core1_nIRQ;
output [1:0]DMA0_DATYPE;
output DMA0_DAVALID;
output DMA0_DRREADY;
output DMA0_RSTN;
output [1:0]DMA1_DATYPE;
output DMA1_DAVALID;
output DMA1_DRREADY;
output DMA1_RSTN;
output [1:0]DMA2_DATYPE;
output DMA2_DAVALID;
output DMA2_DRREADY;
output DMA2_RSTN;
output [1:0]DMA3_DATYPE;
output DMA3_DAVALID;
output DMA3_DRREADY;
output DMA3_RSTN;
input DMA0_ACLK;
input DMA0_DAREADY;
input DMA0_DRLAST;
input DMA0_DRVALID;
input DMA1_ACLK;
input DMA1_DAREADY;
input DMA1_DRLAST;
input DMA1_DRVALID;
input DMA2_ACLK;
input DMA2_DAREADY;
input DMA2_DRLAST;
input DMA2_DRVALID;
input DMA3_ACLK;
input DMA3_DAREADY;
input DMA3_DRLAST;
input DMA3_DRVALID;
input [1:0]DMA0_DRTYPE;
input [1:0]DMA1_DRTYPE;
input [1:0]DMA2_DRTYPE;
input [1:0]DMA3_DRTYPE;
output FCLK_CLK3;
output FCLK_CLK2;
output FCLK_CLK1;
output FCLK_CLK0;
input FCLK_CLKTRIG3_N;
input FCLK_CLKTRIG2_N;
input FCLK_CLKTRIG1_N;
input FCLK_CLKTRIG0_N;
output FCLK_RESET3_N;
output FCLK_RESET2_N;
output FCLK_RESET1_N;
output FCLK_RESET0_N;
input [31:0]FTMD_TRACEIN_DATA;
input FTMD_TRACEIN_VALID;
input FTMD_TRACEIN_CLK;
input [3:0]FTMD_TRACEIN_ATID;
input FTMT_F2P_TRIG_0;
output FTMT_F2P_TRIGACK_0;
input FTMT_F2P_TRIG_1;
output FTMT_F2P_TRIGACK_1;
input FTMT_F2P_TRIG_2;
output FTMT_F2P_TRIGACK_2;
input FTMT_F2P_TRIG_3;
output FTMT_F2P_TRIGACK_3;
input [31:0]FTMT_F2P_DEBUG;
input FTMT_P2F_TRIGACK_0;
output FTMT_P2F_TRIG_0;
input FTMT_P2F_TRIGACK_1;
output FTMT_P2F_TRIG_1;
input FTMT_P2F_TRIGACK_2;
output FTMT_P2F_TRIG_2;
input FTMT_P2F_TRIGACK_3;
output FTMT_P2F_TRIG_3;
output [31:0]FTMT_P2F_DEBUG;
input FPGA_IDLE_N;
output EVENT_EVENTO;
output [1:0]EVENT_STANDBYWFE;
output [1:0]EVENT_STANDBYWFI;
input EVENT_EVENTI;
input [3:0]DDR_ARB;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
wire \<const0> ;
wire \<const1> ;
wire CAN0_PHY_RX;
wire CAN0_PHY_TX;
wire CAN1_PHY_RX;
wire CAN1_PHY_TX;
wire Core0_nFIQ;
wire Core0_nIRQ;
wire Core1_nFIQ;
wire Core1_nIRQ;
wire [3:0]DDR_ARB;
wire [14:0]DDR_Addr;
wire [2:0]DDR_BankAddr;
wire DDR_CAS_n;
wire DDR_CKE;
wire DDR_CS_n;
wire DDR_Clk;
wire DDR_Clk_n;
wire [3:0]DDR_DM;
wire [31:0]DDR_DQ;
wire [3:0]DDR_DQS;
wire [3:0]DDR_DQS_n;
wire DDR_DRSTB;
wire DDR_ODT;
wire DDR_RAS_n;
wire DDR_VRN;
wire DDR_VRP;
wire DDR_WEB;
wire DMA0_ACLK;
wire DMA0_DAREADY;
wire [1:0]DMA0_DATYPE;
wire DMA0_DAVALID;
wire DMA0_DRLAST;
wire DMA0_DRREADY;
wire [1:0]DMA0_DRTYPE;
wire DMA0_DRVALID;
wire DMA0_RSTN;
wire DMA1_ACLK;
wire DMA1_DAREADY;
wire [1:0]DMA1_DATYPE;
wire DMA1_DAVALID;
wire DMA1_DRLAST;
wire DMA1_DRREADY;
wire [1:0]DMA1_DRTYPE;
wire DMA1_DRVALID;
wire DMA1_RSTN;
wire DMA2_ACLK;
wire DMA2_DAREADY;
wire [1:0]DMA2_DATYPE;
wire DMA2_DAVALID;
wire DMA2_DRLAST;
wire DMA2_DRREADY;
wire [1:0]DMA2_DRTYPE;
wire DMA2_DRVALID;
wire DMA2_RSTN;
wire DMA3_ACLK;
wire DMA3_DAREADY;
wire [1:0]DMA3_DATYPE;
wire DMA3_DAVALID;
wire DMA3_DRLAST;
wire DMA3_DRREADY;
wire [1:0]DMA3_DRTYPE;
wire DMA3_DRVALID;
wire DMA3_RSTN;
wire ENET0_EXT_INTIN;
wire ENET0_GMII_RX_CLK;
wire ENET0_GMII_TX_CLK;
wire ENET0_MDIO_I;
wire ENET0_MDIO_MDC;
wire ENET0_MDIO_O;
wire ENET0_MDIO_T;
wire ENET0_MDIO_T_n;
wire ENET0_PTP_DELAY_REQ_RX;
wire ENET0_PTP_DELAY_REQ_TX;
wire ENET0_PTP_PDELAY_REQ_RX;
wire ENET0_PTP_PDELAY_REQ_TX;
wire ENET0_PTP_PDELAY_RESP_RX;
wire ENET0_PTP_PDELAY_RESP_TX;
wire ENET0_PTP_SYNC_FRAME_RX;
wire ENET0_PTP_SYNC_FRAME_TX;
wire ENET0_SOF_RX;
wire ENET0_SOF_TX;
wire ENET1_EXT_INTIN;
wire ENET1_GMII_RX_CLK;
wire ENET1_GMII_TX_CLK;
wire ENET1_MDIO_I;
wire ENET1_MDIO_MDC;
wire ENET1_MDIO_O;
wire ENET1_MDIO_T;
wire ENET1_MDIO_T_n;
wire ENET1_PTP_DELAY_REQ_RX;
wire ENET1_PTP_DELAY_REQ_TX;
wire ENET1_PTP_PDELAY_REQ_RX;
wire ENET1_PTP_PDELAY_REQ_TX;
wire ENET1_PTP_PDELAY_RESP_RX;
wire ENET1_PTP_PDELAY_RESP_TX;
wire ENET1_PTP_SYNC_FRAME_RX;
wire ENET1_PTP_SYNC_FRAME_TX;
wire ENET1_SOF_RX;
wire ENET1_SOF_TX;
wire EVENT_EVENTI;
wire EVENT_EVENTO;
wire [1:0]EVENT_STANDBYWFE;
wire [1:0]EVENT_STANDBYWFI;
wire FCLK_CLK0;
wire FCLK_CLK1;
wire FCLK_CLK2;
wire FCLK_CLK3;
wire FCLK_RESET0_N;
wire FCLK_RESET1_N;
wire FCLK_RESET2_N;
wire FCLK_RESET3_N;
wire FPGA_IDLE_N;
wire FTMD_TRACEIN_CLK;
wire [31:0]FTMT_F2P_DEBUG;
wire FTMT_F2P_TRIGACK_0;
wire FTMT_F2P_TRIGACK_1;
wire FTMT_F2P_TRIGACK_2;
wire FTMT_F2P_TRIGACK_3;
wire FTMT_F2P_TRIG_0;
wire FTMT_F2P_TRIG_1;
wire FTMT_F2P_TRIG_2;
wire FTMT_F2P_TRIG_3;
wire [31:0]FTMT_P2F_DEBUG;
wire FTMT_P2F_TRIGACK_0;
wire FTMT_P2F_TRIGACK_1;
wire FTMT_P2F_TRIGACK_2;
wire FTMT_P2F_TRIGACK_3;
wire FTMT_P2F_TRIG_0;
wire FTMT_P2F_TRIG_1;
wire FTMT_P2F_TRIG_2;
wire FTMT_P2F_TRIG_3;
wire [63:0]GPIO_I;
wire [63:0]GPIO_O;
wire [63:0]GPIO_T;
wire I2C0_SCL_I;
wire I2C0_SCL_O;
wire I2C0_SCL_T;
wire I2C0_SCL_T_n;
wire I2C0_SDA_I;
wire I2C0_SDA_O;
wire I2C0_SDA_T;
wire I2C0_SDA_T_n;
wire I2C1_SCL_I;
wire I2C1_SCL_O;
wire I2C1_SCL_T;
wire I2C1_SCL_T_n;
wire I2C1_SDA_I;
wire I2C1_SDA_O;
wire I2C1_SDA_T;
wire I2C1_SDA_T_n;
wire [0:0]IRQ_F2P;
wire IRQ_P2F_CAN0;
wire IRQ_P2F_CAN1;
wire IRQ_P2F_CTI;
wire IRQ_P2F_DMAC0;
wire IRQ_P2F_DMAC1;
wire IRQ_P2F_DMAC2;
wire IRQ_P2F_DMAC3;
wire IRQ_P2F_DMAC4;
wire IRQ_P2F_DMAC5;
wire IRQ_P2F_DMAC6;
wire IRQ_P2F_DMAC7;
wire IRQ_P2F_DMAC_ABORT;
wire IRQ_P2F_ENET0;
wire IRQ_P2F_ENET1;
wire IRQ_P2F_ENET_WAKE0;
wire IRQ_P2F_ENET_WAKE1;
wire IRQ_P2F_GPIO;
wire IRQ_P2F_I2C0;
wire IRQ_P2F_I2C1;
wire IRQ_P2F_QSPI;
wire IRQ_P2F_SDIO0;
wire IRQ_P2F_SDIO1;
wire IRQ_P2F_SMC;
wire IRQ_P2F_SPI0;
wire IRQ_P2F_SPI1;
wire IRQ_P2F_UART0;
wire IRQ_P2F_UART1;
wire IRQ_P2F_USB0;
wire IRQ_P2F_USB1;
wire [53:0]MIO;
wire M_AXI_GP0_ACLK;
wire [31:0]M_AXI_GP0_ARADDR;
wire [1:0]M_AXI_GP0_ARBURST;
wire [3:0]\^M_AXI_GP0_ARCACHE ;
wire M_AXI_GP0_ARESETN;
wire [11:0]M_AXI_GP0_ARID;
wire [3:0]M_AXI_GP0_ARLEN;
wire [1:0]M_AXI_GP0_ARLOCK;
wire [2:0]M_AXI_GP0_ARPROT;
wire [3:0]M_AXI_GP0_ARQOS;
wire M_AXI_GP0_ARREADY;
wire [1:0]\^M_AXI_GP0_ARSIZE ;
wire M_AXI_GP0_ARVALID;
wire [31:0]M_AXI_GP0_AWADDR;
wire [1:0]M_AXI_GP0_AWBURST;
wire [3:0]\^M_AXI_GP0_AWCACHE ;
wire [11:0]M_AXI_GP0_AWID;
wire [3:0]M_AXI_GP0_AWLEN;
wire [1:0]M_AXI_GP0_AWLOCK;
wire [2:0]M_AXI_GP0_AWPROT;
wire [3:0]M_AXI_GP0_AWQOS;
wire M_AXI_GP0_AWREADY;
wire [1:0]\^M_AXI_GP0_AWSIZE ;
wire M_AXI_GP0_AWVALID;
wire [11:0]M_AXI_GP0_BID;
wire M_AXI_GP0_BREADY;
wire [1:0]M_AXI_GP0_BRESP;
wire M_AXI_GP0_BVALID;
wire [31:0]M_AXI_GP0_RDATA;
wire [11:0]M_AXI_GP0_RID;
wire M_AXI_GP0_RLAST;
wire M_AXI_GP0_RREADY;
wire [1:0]M_AXI_GP0_RRESP;
wire M_AXI_GP0_RVALID;
wire [31:0]M_AXI_GP0_WDATA;
wire [11:0]M_AXI_GP0_WID;
wire M_AXI_GP0_WLAST;
wire M_AXI_GP0_WREADY;
wire [3:0]M_AXI_GP0_WSTRB;
wire M_AXI_GP0_WVALID;
wire M_AXI_GP1_ACLK;
wire [31:0]M_AXI_GP1_ARADDR;
wire [1:0]M_AXI_GP1_ARBURST;
wire [3:0]\^M_AXI_GP1_ARCACHE ;
wire M_AXI_GP1_ARESETN;
wire [11:0]M_AXI_GP1_ARID;
wire [3:0]M_AXI_GP1_ARLEN;
wire [1:0]M_AXI_GP1_ARLOCK;
wire [2:0]M_AXI_GP1_ARPROT;
wire [3:0]M_AXI_GP1_ARQOS;
wire M_AXI_GP1_ARREADY;
wire [1:0]\^M_AXI_GP1_ARSIZE ;
wire M_AXI_GP1_ARVALID;
wire [31:0]M_AXI_GP1_AWADDR;
wire [1:0]M_AXI_GP1_AWBURST;
wire [3:0]\^M_AXI_GP1_AWCACHE ;
wire [11:0]M_AXI_GP1_AWID;
wire [3:0]M_AXI_GP1_AWLEN;
wire [1:0]M_AXI_GP1_AWLOCK;
wire [2:0]M_AXI_GP1_AWPROT;
wire [3:0]M_AXI_GP1_AWQOS;
wire M_AXI_GP1_AWREADY;
wire [1:0]\^M_AXI_GP1_AWSIZE ;
wire M_AXI_GP1_AWVALID;
wire [11:0]M_AXI_GP1_BID;
wire M_AXI_GP1_BREADY;
wire [1:0]M_AXI_GP1_BRESP;
wire M_AXI_GP1_BVALID;
wire [31:0]M_AXI_GP1_RDATA;
wire [11:0]M_AXI_GP1_RID;
wire M_AXI_GP1_RLAST;
wire M_AXI_GP1_RREADY;
wire [1:0]M_AXI_GP1_RRESP;
wire M_AXI_GP1_RVALID;
wire [31:0]M_AXI_GP1_WDATA;
wire [11:0]M_AXI_GP1_WID;
wire M_AXI_GP1_WLAST;
wire M_AXI_GP1_WREADY;
wire [3:0]M_AXI_GP1_WSTRB;
wire M_AXI_GP1_WVALID;
wire PJTAG_TCK;
wire PJTAG_TDI;
wire PJTAG_TMS;
wire PS_CLK;
wire PS_PORB;
wire PS_SRSTB;
wire SDIO0_BUSPOW;
wire [2:0]SDIO0_BUSVOLT;
wire SDIO0_CDN;
wire SDIO0_CLK;
wire SDIO0_CLK_FB;
wire SDIO0_CMD_I;
wire SDIO0_CMD_O;
wire SDIO0_CMD_T;
wire SDIO0_CMD_T_n;
wire [3:0]SDIO0_DATA_I;
wire [3:0]SDIO0_DATA_O;
wire [3:0]SDIO0_DATA_T;
wire [3:0]SDIO0_DATA_T_n;
wire SDIO0_LED;
wire SDIO0_WP;
wire SDIO1_BUSPOW;
wire [2:0]SDIO1_BUSVOLT;
wire SDIO1_CDN;
wire SDIO1_CLK;
wire SDIO1_CLK_FB;
wire SDIO1_CMD_I;
wire SDIO1_CMD_O;
wire SDIO1_CMD_T;
wire SDIO1_CMD_T_n;
wire [3:0]SDIO1_DATA_I;
wire [3:0]SDIO1_DATA_O;
wire [3:0]SDIO1_DATA_T;
wire [3:0]SDIO1_DATA_T_n;
wire SDIO1_LED;
wire SDIO1_WP;
wire SPI0_MISO_I;
wire SPI0_MISO_O;
wire SPI0_MISO_T;
wire SPI0_MISO_T_n;
wire SPI0_MOSI_I;
wire SPI0_MOSI_O;
wire SPI0_MOSI_T;
wire SPI0_MOSI_T_n;
wire SPI0_SCLK_I;
wire SPI0_SCLK_O;
wire SPI0_SCLK_T;
wire SPI0_SCLK_T_n;
wire SPI0_SS1_O;
wire SPI0_SS2_O;
wire SPI0_SS_I;
wire SPI0_SS_O;
wire SPI0_SS_T;
wire SPI0_SS_T_n;
wire SPI1_MISO_I;
wire SPI1_MISO_O;
wire SPI1_MISO_T;
wire SPI1_MISO_T_n;
wire SPI1_MOSI_I;
wire SPI1_MOSI_O;
wire SPI1_MOSI_T;
wire SPI1_MOSI_T_n;
wire SPI1_SCLK_I;
wire SPI1_SCLK_O;
wire SPI1_SCLK_T;
wire SPI1_SCLK_T_n;
wire SPI1_SS1_O;
wire SPI1_SS2_O;
wire SPI1_SS_I;
wire SPI1_SS_O;
wire SPI1_SS_T;
wire SPI1_SS_T_n;
wire SRAM_INTIN;
wire S_AXI_ACP_ACLK;
wire [31:0]S_AXI_ACP_ARADDR;
wire [1:0]S_AXI_ACP_ARBURST;
wire [3:0]S_AXI_ACP_ARCACHE;
wire S_AXI_ACP_ARESETN;
wire [2:0]S_AXI_ACP_ARID;
wire [3:0]S_AXI_ACP_ARLEN;
wire [1:0]S_AXI_ACP_ARLOCK;
wire [2:0]S_AXI_ACP_ARPROT;
wire [3:0]S_AXI_ACP_ARQOS;
wire S_AXI_ACP_ARREADY;
wire [2:0]S_AXI_ACP_ARSIZE;
wire [4:0]S_AXI_ACP_ARUSER;
wire S_AXI_ACP_ARVALID;
wire [31:0]S_AXI_ACP_AWADDR;
wire [1:0]S_AXI_ACP_AWBURST;
wire [3:0]S_AXI_ACP_AWCACHE;
wire [2:0]S_AXI_ACP_AWID;
wire [3:0]S_AXI_ACP_AWLEN;
wire [1:0]S_AXI_ACP_AWLOCK;
wire [2:0]S_AXI_ACP_AWPROT;
wire [3:0]S_AXI_ACP_AWQOS;
wire S_AXI_ACP_AWREADY;
wire [2:0]S_AXI_ACP_AWSIZE;
wire [4:0]S_AXI_ACP_AWUSER;
wire S_AXI_ACP_AWVALID;
wire [2:0]S_AXI_ACP_BID;
wire S_AXI_ACP_BREADY;
wire [1:0]S_AXI_ACP_BRESP;
wire S_AXI_ACP_BVALID;
wire [63:0]S_AXI_ACP_RDATA;
wire [2:0]S_AXI_ACP_RID;
wire S_AXI_ACP_RLAST;
wire S_AXI_ACP_RREADY;
wire [1:0]S_AXI_ACP_RRESP;
wire S_AXI_ACP_RVALID;
wire [63:0]S_AXI_ACP_WDATA;
wire [2:0]S_AXI_ACP_WID;
wire S_AXI_ACP_WLAST;
wire S_AXI_ACP_WREADY;
wire [7:0]S_AXI_ACP_WSTRB;
wire S_AXI_ACP_WVALID;
wire S_AXI_GP0_ACLK;
wire [31:0]S_AXI_GP0_ARADDR;
wire [1:0]S_AXI_GP0_ARBURST;
wire [3:0]S_AXI_GP0_ARCACHE;
wire S_AXI_GP0_ARESETN;
wire [5:0]S_AXI_GP0_ARID;
wire [3:0]S_AXI_GP0_ARLEN;
wire [1:0]S_AXI_GP0_ARLOCK;
wire [2:0]S_AXI_GP0_ARPROT;
wire [3:0]S_AXI_GP0_ARQOS;
wire S_AXI_GP0_ARREADY;
wire [2:0]S_AXI_GP0_ARSIZE;
wire S_AXI_GP0_ARVALID;
wire [31:0]S_AXI_GP0_AWADDR;
wire [1:0]S_AXI_GP0_AWBURST;
wire [3:0]S_AXI_GP0_AWCACHE;
wire [5:0]S_AXI_GP0_AWID;
wire [3:0]S_AXI_GP0_AWLEN;
wire [1:0]S_AXI_GP0_AWLOCK;
wire [2:0]S_AXI_GP0_AWPROT;
wire [3:0]S_AXI_GP0_AWQOS;
wire S_AXI_GP0_AWREADY;
wire [2:0]S_AXI_GP0_AWSIZE;
wire S_AXI_GP0_AWVALID;
wire [5:0]S_AXI_GP0_BID;
wire S_AXI_GP0_BREADY;
wire [1:0]S_AXI_GP0_BRESP;
wire S_AXI_GP0_BVALID;
wire [31:0]S_AXI_GP0_RDATA;
wire [5:0]S_AXI_GP0_RID;
wire S_AXI_GP0_RLAST;
wire S_AXI_GP0_RREADY;
wire [1:0]S_AXI_GP0_RRESP;
wire S_AXI_GP0_RVALID;
wire [31:0]S_AXI_GP0_WDATA;
wire [5:0]S_AXI_GP0_WID;
wire S_AXI_GP0_WLAST;
wire S_AXI_GP0_WREADY;
wire [3:0]S_AXI_GP0_WSTRB;
wire S_AXI_GP0_WVALID;
wire S_AXI_GP1_ACLK;
wire [31:0]S_AXI_GP1_ARADDR;
wire [1:0]S_AXI_GP1_ARBURST;
wire [3:0]S_AXI_GP1_ARCACHE;
wire S_AXI_GP1_ARESETN;
wire [5:0]S_AXI_GP1_ARID;
wire [3:0]S_AXI_GP1_ARLEN;
wire [1:0]S_AXI_GP1_ARLOCK;
wire [2:0]S_AXI_GP1_ARPROT;
wire [3:0]S_AXI_GP1_ARQOS;
wire S_AXI_GP1_ARREADY;
wire [2:0]S_AXI_GP1_ARSIZE;
wire S_AXI_GP1_ARVALID;
wire [31:0]S_AXI_GP1_AWADDR;
wire [1:0]S_AXI_GP1_AWBURST;
wire [3:0]S_AXI_GP1_AWCACHE;
wire [5:0]S_AXI_GP1_AWID;
wire [3:0]S_AXI_GP1_AWLEN;
wire [1:0]S_AXI_GP1_AWLOCK;
wire [2:0]S_AXI_GP1_AWPROT;
wire [3:0]S_AXI_GP1_AWQOS;
wire S_AXI_GP1_AWREADY;
wire [2:0]S_AXI_GP1_AWSIZE;
wire S_AXI_GP1_AWVALID;
wire [5:0]S_AXI_GP1_BID;
wire S_AXI_GP1_BREADY;
wire [1:0]S_AXI_GP1_BRESP;
wire S_AXI_GP1_BVALID;
wire [31:0]S_AXI_GP1_RDATA;
wire [5:0]S_AXI_GP1_RID;
wire S_AXI_GP1_RLAST;
wire S_AXI_GP1_RREADY;
wire [1:0]S_AXI_GP1_RRESP;
wire S_AXI_GP1_RVALID;
wire [31:0]S_AXI_GP1_WDATA;
wire [5:0]S_AXI_GP1_WID;
wire S_AXI_GP1_WLAST;
wire S_AXI_GP1_WREADY;
wire [3:0]S_AXI_GP1_WSTRB;
wire S_AXI_GP1_WVALID;
wire S_AXI_HP0_ACLK;
wire [31:0]S_AXI_HP0_ARADDR;
wire [1:0]S_AXI_HP0_ARBURST;
wire [3:0]S_AXI_HP0_ARCACHE;
wire S_AXI_HP0_ARESETN;
wire [5:0]S_AXI_HP0_ARID;
wire [3:0]S_AXI_HP0_ARLEN;
wire [1:0]S_AXI_HP0_ARLOCK;
wire [2:0]S_AXI_HP0_ARPROT;
wire [3:0]S_AXI_HP0_ARQOS;
wire S_AXI_HP0_ARREADY;
wire [2:0]S_AXI_HP0_ARSIZE;
wire S_AXI_HP0_ARVALID;
wire [31:0]S_AXI_HP0_AWADDR;
wire [1:0]S_AXI_HP0_AWBURST;
wire [3:0]S_AXI_HP0_AWCACHE;
wire [5:0]S_AXI_HP0_AWID;
wire [3:0]S_AXI_HP0_AWLEN;
wire [1:0]S_AXI_HP0_AWLOCK;
wire [2:0]S_AXI_HP0_AWPROT;
wire [3:0]S_AXI_HP0_AWQOS;
wire S_AXI_HP0_AWREADY;
wire [2:0]S_AXI_HP0_AWSIZE;
wire S_AXI_HP0_AWVALID;
wire [5:0]S_AXI_HP0_BID;
wire S_AXI_HP0_BREADY;
wire [1:0]S_AXI_HP0_BRESP;
wire S_AXI_HP0_BVALID;
wire [2:0]S_AXI_HP0_RACOUNT;
wire [7:0]S_AXI_HP0_RCOUNT;
wire [63:0]S_AXI_HP0_RDATA;
wire S_AXI_HP0_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP0_RID;
wire S_AXI_HP0_RLAST;
wire S_AXI_HP0_RREADY;
wire [1:0]S_AXI_HP0_RRESP;
wire S_AXI_HP0_RVALID;
wire [5:0]S_AXI_HP0_WACOUNT;
wire [7:0]S_AXI_HP0_WCOUNT;
wire [63:0]S_AXI_HP0_WDATA;
wire [5:0]S_AXI_HP0_WID;
wire S_AXI_HP0_WLAST;
wire S_AXI_HP0_WREADY;
wire S_AXI_HP0_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP0_WSTRB;
wire S_AXI_HP0_WVALID;
wire S_AXI_HP1_ACLK;
wire [31:0]S_AXI_HP1_ARADDR;
wire [1:0]S_AXI_HP1_ARBURST;
wire [3:0]S_AXI_HP1_ARCACHE;
wire S_AXI_HP1_ARESETN;
wire [5:0]S_AXI_HP1_ARID;
wire [3:0]S_AXI_HP1_ARLEN;
wire [1:0]S_AXI_HP1_ARLOCK;
wire [2:0]S_AXI_HP1_ARPROT;
wire [3:0]S_AXI_HP1_ARQOS;
wire S_AXI_HP1_ARREADY;
wire [2:0]S_AXI_HP1_ARSIZE;
wire S_AXI_HP1_ARVALID;
wire [31:0]S_AXI_HP1_AWADDR;
wire [1:0]S_AXI_HP1_AWBURST;
wire [3:0]S_AXI_HP1_AWCACHE;
wire [5:0]S_AXI_HP1_AWID;
wire [3:0]S_AXI_HP1_AWLEN;
wire [1:0]S_AXI_HP1_AWLOCK;
wire [2:0]S_AXI_HP1_AWPROT;
wire [3:0]S_AXI_HP1_AWQOS;
wire S_AXI_HP1_AWREADY;
wire [2:0]S_AXI_HP1_AWSIZE;
wire S_AXI_HP1_AWVALID;
wire [5:0]S_AXI_HP1_BID;
wire S_AXI_HP1_BREADY;
wire [1:0]S_AXI_HP1_BRESP;
wire S_AXI_HP1_BVALID;
wire [2:0]S_AXI_HP1_RACOUNT;
wire [7:0]S_AXI_HP1_RCOUNT;
wire [63:0]S_AXI_HP1_RDATA;
wire S_AXI_HP1_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP1_RID;
wire S_AXI_HP1_RLAST;
wire S_AXI_HP1_RREADY;
wire [1:0]S_AXI_HP1_RRESP;
wire S_AXI_HP1_RVALID;
wire [5:0]S_AXI_HP1_WACOUNT;
wire [7:0]S_AXI_HP1_WCOUNT;
wire [63:0]S_AXI_HP1_WDATA;
wire [5:0]S_AXI_HP1_WID;
wire S_AXI_HP1_WLAST;
wire S_AXI_HP1_WREADY;
wire S_AXI_HP1_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP1_WSTRB;
wire S_AXI_HP1_WVALID;
wire S_AXI_HP2_ACLK;
wire [31:0]S_AXI_HP2_ARADDR;
wire [1:0]S_AXI_HP2_ARBURST;
wire [3:0]S_AXI_HP2_ARCACHE;
wire S_AXI_HP2_ARESETN;
wire [5:0]S_AXI_HP2_ARID;
wire [3:0]S_AXI_HP2_ARLEN;
wire [1:0]S_AXI_HP2_ARLOCK;
wire [2:0]S_AXI_HP2_ARPROT;
wire [3:0]S_AXI_HP2_ARQOS;
wire S_AXI_HP2_ARREADY;
wire [2:0]S_AXI_HP2_ARSIZE;
wire S_AXI_HP2_ARVALID;
wire [31:0]S_AXI_HP2_AWADDR;
wire [1:0]S_AXI_HP2_AWBURST;
wire [3:0]S_AXI_HP2_AWCACHE;
wire [5:0]S_AXI_HP2_AWID;
wire [3:0]S_AXI_HP2_AWLEN;
wire [1:0]S_AXI_HP2_AWLOCK;
wire [2:0]S_AXI_HP2_AWPROT;
wire [3:0]S_AXI_HP2_AWQOS;
wire S_AXI_HP2_AWREADY;
wire [2:0]S_AXI_HP2_AWSIZE;
wire S_AXI_HP2_AWVALID;
wire [5:0]S_AXI_HP2_BID;
wire S_AXI_HP2_BREADY;
wire [1:0]S_AXI_HP2_BRESP;
wire S_AXI_HP2_BVALID;
wire [2:0]S_AXI_HP2_RACOUNT;
wire [7:0]S_AXI_HP2_RCOUNT;
wire [63:0]S_AXI_HP2_RDATA;
wire S_AXI_HP2_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP2_RID;
wire S_AXI_HP2_RLAST;
wire S_AXI_HP2_RREADY;
wire [1:0]S_AXI_HP2_RRESP;
wire S_AXI_HP2_RVALID;
wire [5:0]S_AXI_HP2_WACOUNT;
wire [7:0]S_AXI_HP2_WCOUNT;
wire [63:0]S_AXI_HP2_WDATA;
wire [5:0]S_AXI_HP2_WID;
wire S_AXI_HP2_WLAST;
wire S_AXI_HP2_WREADY;
wire S_AXI_HP2_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP2_WSTRB;
wire S_AXI_HP2_WVALID;
wire S_AXI_HP3_ACLK;
wire [31:0]S_AXI_HP3_ARADDR;
wire [1:0]S_AXI_HP3_ARBURST;
wire [3:0]S_AXI_HP3_ARCACHE;
wire S_AXI_HP3_ARESETN;
wire [5:0]S_AXI_HP3_ARID;
wire [3:0]S_AXI_HP3_ARLEN;
wire [1:0]S_AXI_HP3_ARLOCK;
wire [2:0]S_AXI_HP3_ARPROT;
wire [3:0]S_AXI_HP3_ARQOS;
wire S_AXI_HP3_ARREADY;
wire [2:0]S_AXI_HP3_ARSIZE;
wire S_AXI_HP3_ARVALID;
wire [31:0]S_AXI_HP3_AWADDR;
wire [1:0]S_AXI_HP3_AWBURST;
wire [3:0]S_AXI_HP3_AWCACHE;
wire [5:0]S_AXI_HP3_AWID;
wire [3:0]S_AXI_HP3_AWLEN;
wire [1:0]S_AXI_HP3_AWLOCK;
wire [2:0]S_AXI_HP3_AWPROT;
wire [3:0]S_AXI_HP3_AWQOS;
wire S_AXI_HP3_AWREADY;
wire [2:0]S_AXI_HP3_AWSIZE;
wire S_AXI_HP3_AWVALID;
wire [5:0]S_AXI_HP3_BID;
wire S_AXI_HP3_BREADY;
wire [1:0]S_AXI_HP3_BRESP;
wire S_AXI_HP3_BVALID;
wire [2:0]S_AXI_HP3_RACOUNT;
wire [7:0]S_AXI_HP3_RCOUNT;
wire [63:0]S_AXI_HP3_RDATA;
wire S_AXI_HP3_RDISSUECAP1_EN;
wire [5:0]S_AXI_HP3_RID;
wire S_AXI_HP3_RLAST;
wire S_AXI_HP3_RREADY;
wire [1:0]S_AXI_HP3_RRESP;
wire S_AXI_HP3_RVALID;
wire [5:0]S_AXI_HP3_WACOUNT;
wire [7:0]S_AXI_HP3_WCOUNT;
wire [63:0]S_AXI_HP3_WDATA;
wire [5:0]S_AXI_HP3_WID;
wire S_AXI_HP3_WLAST;
wire S_AXI_HP3_WREADY;
wire S_AXI_HP3_WRISSUECAP1_EN;
wire [7:0]S_AXI_HP3_WSTRB;
wire S_AXI_HP3_WVALID;
wire TRACE_CLK;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ;
(* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ;
(* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ;
wire TTC0_CLK0_IN;
wire TTC0_CLK1_IN;
wire TTC0_CLK2_IN;
wire TTC0_WAVE0_OUT;
wire TTC0_WAVE1_OUT;
wire TTC0_WAVE2_OUT;
wire TTC1_CLK0_IN;
wire TTC1_CLK1_IN;
wire TTC1_CLK2_IN;
wire TTC1_WAVE0_OUT;
wire TTC1_WAVE1_OUT;
wire TTC1_WAVE2_OUT;
wire UART0_CTSN;
wire UART0_DCDN;
wire UART0_DSRN;
wire UART0_DTRN;
wire UART0_RIN;
wire UART0_RTSN;
wire UART0_RX;
wire UART0_TX;
wire UART1_CTSN;
wire UART1_DCDN;
wire UART1_DSRN;
wire UART1_DTRN;
wire UART1_RIN;
wire UART1_RTSN;
wire UART1_RX;
wire UART1_TX;
wire [1:0]USB0_PORT_INDCTL;
wire USB0_VBUS_PWRFAULT;
wire USB0_VBUS_PWRSELECT;
wire [1:0]USB1_PORT_INDCTL;
wire USB1_VBUS_PWRFAULT;
wire USB1_VBUS_PWRSELECT;
wire WDT_CLK_IN;
wire WDT_RST_OUT;
wire [14:0]buffered_DDR_Addr;
wire [2:0]buffered_DDR_BankAddr;
wire buffered_DDR_CAS_n;
wire buffered_DDR_CKE;
wire buffered_DDR_CS_n;
wire buffered_DDR_Clk;
wire buffered_DDR_Clk_n;
wire [3:0]buffered_DDR_DM;
wire [31:0]buffered_DDR_DQ;
wire [3:0]buffered_DDR_DQS;
wire [3:0]buffered_DDR_DQS_n;
wire buffered_DDR_DRSTB;
wire buffered_DDR_ODT;
wire buffered_DDR_RAS_n;
wire buffered_DDR_VRN;
wire buffered_DDR_VRP;
wire buffered_DDR_WEB;
wire [53:0]buffered_MIO;
wire buffered_PS_CLK;
wire buffered_PS_PORB;
wire buffered_PS_SRSTB;
wire [63:0]gpio_out_t_n;
wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED;
wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED;
wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED;
wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED;
wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED;
wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED;
wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED;
assign ENET0_GMII_TXD[7] = \<const0> ;
assign ENET0_GMII_TXD[6] = \<const0> ;
assign ENET0_GMII_TXD[5] = \<const0> ;
assign ENET0_GMII_TXD[4] = \<const0> ;
assign ENET0_GMII_TXD[3] = \<const0> ;
assign ENET0_GMII_TXD[2] = \<const0> ;
assign ENET0_GMII_TXD[1] = \<const0> ;
assign ENET0_GMII_TXD[0] = \<const0> ;
assign ENET0_GMII_TX_EN = \<const0> ;
assign ENET0_GMII_TX_ER = \<const0> ;
assign ENET1_GMII_TXD[7] = \<const0> ;
assign ENET1_GMII_TXD[6] = \<const0> ;
assign ENET1_GMII_TXD[5] = \<const0> ;
assign ENET1_GMII_TXD[4] = \<const0> ;
assign ENET1_GMII_TXD[3] = \<const0> ;
assign ENET1_GMII_TXD[2] = \<const0> ;
assign ENET1_GMII_TXD[1] = \<const0> ;
assign ENET1_GMII_TXD[0] = \<const0> ;
assign ENET1_GMII_TX_EN = \<const0> ;
assign ENET1_GMII_TX_ER = \<const0> ;
assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2];
assign M_AXI_GP0_ARCACHE[1] = \<const1> ;
assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0];
assign M_AXI_GP0_ARSIZE[2] = \<const0> ;
assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0];
assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2];
assign M_AXI_GP0_AWCACHE[1] = \<const1> ;
assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0];
assign M_AXI_GP0_AWSIZE[2] = \<const0> ;
assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0];
assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2];
assign M_AXI_GP1_ARCACHE[1] = \<const1> ;
assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0];
assign M_AXI_GP1_ARSIZE[2] = \<const0> ;
assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0];
assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2];
assign M_AXI_GP1_AWCACHE[1] = \<const1> ;
assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0];
assign M_AXI_GP1_AWSIZE[2] = \<const0> ;
assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0];
assign PJTAG_TDO = \<const0> ;
assign TRACE_CLK_OUT = \<const0> ;
assign TRACE_CTL = \TRACE_CTL_PIPE[0] ;
assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ;
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CAS_n_BIBUF
(.IO(buffered_DDR_CAS_n),
.PAD(DDR_CAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CKE_BIBUF
(.IO(buffered_DDR_CKE),
.PAD(DDR_CKE));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_CS_n_BIBUF
(.IO(buffered_DDR_CS_n),
.PAD(DDR_CS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_BIBUF
(.IO(buffered_DDR_Clk),
.PAD(DDR_Clk));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_Clk_n_BIBUF
(.IO(buffered_DDR_Clk_n),
.PAD(DDR_Clk_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_DRSTB_BIBUF
(.IO(buffered_DDR_DRSTB),
.PAD(DDR_DRSTB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_ODT_BIBUF
(.IO(buffered_DDR_ODT),
.PAD(DDR_ODT));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_RAS_n_BIBUF
(.IO(buffered_DDR_RAS_n),
.PAD(DDR_RAS_n));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRN_BIBUF
(.IO(buffered_DDR_VRN),
.PAD(DDR_VRN));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_VRP_BIBUF
(.IO(buffered_DDR_VRP),
.PAD(DDR_VRP));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF DDR_WEB_BIBUF
(.IO(buffered_DDR_WEB),
.PAD(DDR_WEB));
LUT1 #(
.INIT(2'h1))
ENET0_MDIO_T_INST_0
(.I0(ENET0_MDIO_T_n),
.O(ENET0_MDIO_T));
LUT1 #(
.INIT(2'h1))
ENET1_MDIO_T_INST_0
(.I0(ENET1_MDIO_T_n),
.O(ENET1_MDIO_T));
GND GND
(.G(\<const0> ));
LUT1 #(
.INIT(2'h1))
\GPIO_T[0]_INST_0
(.I0(gpio_out_t_n[0]),
.O(GPIO_T[0]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[10]_INST_0
(.I0(gpio_out_t_n[10]),
.O(GPIO_T[10]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[11]_INST_0
(.I0(gpio_out_t_n[11]),
.O(GPIO_T[11]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[12]_INST_0
(.I0(gpio_out_t_n[12]),
.O(GPIO_T[12]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[13]_INST_0
(.I0(gpio_out_t_n[13]),
.O(GPIO_T[13]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[14]_INST_0
(.I0(gpio_out_t_n[14]),
.O(GPIO_T[14]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[15]_INST_0
(.I0(gpio_out_t_n[15]),
.O(GPIO_T[15]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[16]_INST_0
(.I0(gpio_out_t_n[16]),
.O(GPIO_T[16]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[17]_INST_0
(.I0(gpio_out_t_n[17]),
.O(GPIO_T[17]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[18]_INST_0
(.I0(gpio_out_t_n[18]),
.O(GPIO_T[18]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[19]_INST_0
(.I0(gpio_out_t_n[19]),
.O(GPIO_T[19]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[1]_INST_0
(.I0(gpio_out_t_n[1]),
.O(GPIO_T[1]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[20]_INST_0
(.I0(gpio_out_t_n[20]),
.O(GPIO_T[20]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[21]_INST_0
(.I0(gpio_out_t_n[21]),
.O(GPIO_T[21]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[22]_INST_0
(.I0(gpio_out_t_n[22]),
.O(GPIO_T[22]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[23]_INST_0
(.I0(gpio_out_t_n[23]),
.O(GPIO_T[23]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[24]_INST_0
(.I0(gpio_out_t_n[24]),
.O(GPIO_T[24]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[25]_INST_0
(.I0(gpio_out_t_n[25]),
.O(GPIO_T[25]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[26]_INST_0
(.I0(gpio_out_t_n[26]),
.O(GPIO_T[26]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[27]_INST_0
(.I0(gpio_out_t_n[27]),
.O(GPIO_T[27]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[28]_INST_0
(.I0(gpio_out_t_n[28]),
.O(GPIO_T[28]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[29]_INST_0
(.I0(gpio_out_t_n[29]),
.O(GPIO_T[29]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[2]_INST_0
(.I0(gpio_out_t_n[2]),
.O(GPIO_T[2]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[30]_INST_0
(.I0(gpio_out_t_n[30]),
.O(GPIO_T[30]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[31]_INST_0
(.I0(gpio_out_t_n[31]),
.O(GPIO_T[31]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[32]_INST_0
(.I0(gpio_out_t_n[32]),
.O(GPIO_T[32]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[33]_INST_0
(.I0(gpio_out_t_n[33]),
.O(GPIO_T[33]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[34]_INST_0
(.I0(gpio_out_t_n[34]),
.O(GPIO_T[34]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[35]_INST_0
(.I0(gpio_out_t_n[35]),
.O(GPIO_T[35]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[36]_INST_0
(.I0(gpio_out_t_n[36]),
.O(GPIO_T[36]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[37]_INST_0
(.I0(gpio_out_t_n[37]),
.O(GPIO_T[37]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[38]_INST_0
(.I0(gpio_out_t_n[38]),
.O(GPIO_T[38]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[39]_INST_0
(.I0(gpio_out_t_n[39]),
.O(GPIO_T[39]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[3]_INST_0
(.I0(gpio_out_t_n[3]),
.O(GPIO_T[3]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[40]_INST_0
(.I0(gpio_out_t_n[40]),
.O(GPIO_T[40]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[41]_INST_0
(.I0(gpio_out_t_n[41]),
.O(GPIO_T[41]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[42]_INST_0
(.I0(gpio_out_t_n[42]),
.O(GPIO_T[42]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[43]_INST_0
(.I0(gpio_out_t_n[43]),
.O(GPIO_T[43]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[44]_INST_0
(.I0(gpio_out_t_n[44]),
.O(GPIO_T[44]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[45]_INST_0
(.I0(gpio_out_t_n[45]),
.O(GPIO_T[45]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[46]_INST_0
(.I0(gpio_out_t_n[46]),
.O(GPIO_T[46]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[47]_INST_0
(.I0(gpio_out_t_n[47]),
.O(GPIO_T[47]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[48]_INST_0
(.I0(gpio_out_t_n[48]),
.O(GPIO_T[48]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[49]_INST_0
(.I0(gpio_out_t_n[49]),
.O(GPIO_T[49]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[4]_INST_0
(.I0(gpio_out_t_n[4]),
.O(GPIO_T[4]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[50]_INST_0
(.I0(gpio_out_t_n[50]),
.O(GPIO_T[50]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[51]_INST_0
(.I0(gpio_out_t_n[51]),
.O(GPIO_T[51]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[52]_INST_0
(.I0(gpio_out_t_n[52]),
.O(GPIO_T[52]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[53]_INST_0
(.I0(gpio_out_t_n[53]),
.O(GPIO_T[53]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[54]_INST_0
(.I0(gpio_out_t_n[54]),
.O(GPIO_T[54]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[55]_INST_0
(.I0(gpio_out_t_n[55]),
.O(GPIO_T[55]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[56]_INST_0
(.I0(gpio_out_t_n[56]),
.O(GPIO_T[56]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[57]_INST_0
(.I0(gpio_out_t_n[57]),
.O(GPIO_T[57]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[58]_INST_0
(.I0(gpio_out_t_n[58]),
.O(GPIO_T[58]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[59]_INST_0
(.I0(gpio_out_t_n[59]),
.O(GPIO_T[59]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[5]_INST_0
(.I0(gpio_out_t_n[5]),
.O(GPIO_T[5]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[60]_INST_0
(.I0(gpio_out_t_n[60]),
.O(GPIO_T[60]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[61]_INST_0
(.I0(gpio_out_t_n[61]),
.O(GPIO_T[61]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[62]_INST_0
(.I0(gpio_out_t_n[62]),
.O(GPIO_T[62]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[63]_INST_0
(.I0(gpio_out_t_n[63]),
.O(GPIO_T[63]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[6]_INST_0
(.I0(gpio_out_t_n[6]),
.O(GPIO_T[6]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[7]_INST_0
(.I0(gpio_out_t_n[7]),
.O(GPIO_T[7]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[8]_INST_0
(.I0(gpio_out_t_n[8]),
.O(GPIO_T[8]));
LUT1 #(
.INIT(2'h1))
\GPIO_T[9]_INST_0
(.I0(gpio_out_t_n[9]),
.O(GPIO_T[9]));
LUT1 #(
.INIT(2'h1))
I2C0_SCL_T_INST_0
(.I0(I2C0_SCL_T_n),
.O(I2C0_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C0_SDA_T_INST_0
(.I0(I2C0_SDA_T_n),
.O(I2C0_SDA_T));
LUT1 #(
.INIT(2'h1))
I2C1_SCL_T_INST_0
(.I0(I2C1_SCL_T_n),
.O(I2C1_SCL_T));
LUT1 #(
.INIT(2'h1))
I2C1_SDA_T_INST_0
(.I0(I2C1_SDA_T_n),
.O(I2C1_SDA_T));
(* BOX_TYPE = "PRIMITIVE" *)
PS7 PS7_i
(.DDRA(buffered_DDR_Addr),
.DDRARB(DDR_ARB),
.DDRBA(buffered_DDR_BankAddr),
.DDRCASB(buffered_DDR_CAS_n),
.DDRCKE(buffered_DDR_CKE),
.DDRCKN(buffered_DDR_Clk_n),
.DDRCKP(buffered_DDR_Clk),
.DDRCSB(buffered_DDR_CS_n),
.DDRDM(buffered_DDR_DM),
.DDRDQ(buffered_DDR_DQ),
.DDRDQSN(buffered_DDR_DQS_n),
.DDRDQSP(buffered_DDR_DQS),
.DDRDRSTB(buffered_DDR_DRSTB),
.DDRODT(buffered_DDR_ODT),
.DDRRASB(buffered_DDR_RAS_n),
.DDRVRN(buffered_DDR_VRN),
.DDRVRP(buffered_DDR_VRP),
.DDRWEB(buffered_DDR_WEB),
.DMA0ACLK(DMA0_ACLK),
.DMA0DAREADY(DMA0_DAREADY),
.DMA0DATYPE(DMA0_DATYPE),
.DMA0DAVALID(DMA0_DAVALID),
.DMA0DRLAST(DMA0_DRLAST),
.DMA0DRREADY(DMA0_DRREADY),
.DMA0DRTYPE(DMA0_DRTYPE),
.DMA0DRVALID(DMA0_DRVALID),
.DMA0RSTN(DMA0_RSTN),
.DMA1ACLK(DMA1_ACLK),
.DMA1DAREADY(DMA1_DAREADY),
.DMA1DATYPE(DMA1_DATYPE),
.DMA1DAVALID(DMA1_DAVALID),
.DMA1DRLAST(DMA1_DRLAST),
.DMA1DRREADY(DMA1_DRREADY),
.DMA1DRTYPE(DMA1_DRTYPE),
.DMA1DRVALID(DMA1_DRVALID),
.DMA1RSTN(DMA1_RSTN),
.DMA2ACLK(DMA2_ACLK),
.DMA2DAREADY(DMA2_DAREADY),
.DMA2DATYPE(DMA2_DATYPE),
.DMA2DAVALID(DMA2_DAVALID),
.DMA2DRLAST(DMA2_DRLAST),
.DMA2DRREADY(DMA2_DRREADY),
.DMA2DRTYPE(DMA2_DRTYPE),
.DMA2DRVALID(DMA2_DRVALID),
.DMA2RSTN(DMA2_RSTN),
.DMA3ACLK(DMA3_ACLK),
.DMA3DAREADY(DMA3_DAREADY),
.DMA3DATYPE(DMA3_DATYPE),
.DMA3DAVALID(DMA3_DAVALID),
.DMA3DRLAST(DMA3_DRLAST),
.DMA3DRREADY(DMA3_DRREADY),
.DMA3DRTYPE(DMA3_DRTYPE),
.DMA3DRVALID(DMA3_DRVALID),
.DMA3RSTN(DMA3_RSTN),
.EMIOCAN0PHYRX(CAN0_PHY_RX),
.EMIOCAN0PHYTX(CAN0_PHY_TX),
.EMIOCAN1PHYRX(CAN1_PHY_RX),
.EMIOCAN1PHYTX(CAN1_PHY_TX),
.EMIOENET0EXTINTIN(ENET0_EXT_INTIN),
.EMIOENET0GMIICOL(1'b0),
.EMIOENET0GMIICRS(1'b0),
.EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK),
.EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET0GMIIRXDV(1'b0),
.EMIOENET0GMIIRXER(1'b0),
.EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK),
.EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]),
.EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED),
.EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED),
.EMIOENET0MDIOI(ENET0_MDIO_I),
.EMIOENET0MDIOMDC(ENET0_MDIO_MDC),
.EMIOENET0MDIOO(ENET0_MDIO_O),
.EMIOENET0MDIOTN(ENET0_MDIO_T_n),
.EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX),
.EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX),
.EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX),
.EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX),
.EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX),
.EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX),
.EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX),
.EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX),
.EMIOENET0SOFRX(ENET0_SOF_RX),
.EMIOENET0SOFTX(ENET0_SOF_TX),
.EMIOENET1EXTINTIN(ENET1_EXT_INTIN),
.EMIOENET1GMIICOL(1'b0),
.EMIOENET1GMIICRS(1'b0),
.EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK),
.EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.EMIOENET1GMIIRXDV(1'b0),
.EMIOENET1GMIIRXER(1'b0),
.EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK),
.EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]),
.EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED),
.EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED),
.EMIOENET1MDIOI(ENET1_MDIO_I),
.EMIOENET1MDIOMDC(ENET1_MDIO_MDC),
.EMIOENET1MDIOO(ENET1_MDIO_O),
.EMIOENET1MDIOTN(ENET1_MDIO_T_n),
.EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX),
.EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX),
.EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX),
.EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX),
.EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX),
.EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX),
.EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX),
.EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX),
.EMIOENET1SOFRX(ENET1_SOF_RX),
.EMIOENET1SOFTX(ENET1_SOF_TX),
.EMIOGPIOI(GPIO_I),
.EMIOGPIOO(GPIO_O),
.EMIOGPIOTN(gpio_out_t_n),
.EMIOI2C0SCLI(I2C0_SCL_I),
.EMIOI2C0SCLO(I2C0_SCL_O),
.EMIOI2C0SCLTN(I2C0_SCL_T_n),
.EMIOI2C0SDAI(I2C0_SDA_I),
.EMIOI2C0SDAO(I2C0_SDA_O),
.EMIOI2C0SDATN(I2C0_SDA_T_n),
.EMIOI2C1SCLI(I2C1_SCL_I),
.EMIOI2C1SCLO(I2C1_SCL_O),
.EMIOI2C1SCLTN(I2C1_SCL_T_n),
.EMIOI2C1SDAI(I2C1_SDA_I),
.EMIOI2C1SDAO(I2C1_SDA_O),
.EMIOI2C1SDATN(I2C1_SDA_T_n),
.EMIOPJTAGTCK(PJTAG_TCK),
.EMIOPJTAGTDI(PJTAG_TDI),
.EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED),
.EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED),
.EMIOPJTAGTMS(PJTAG_TMS),
.EMIOSDIO0BUSPOW(SDIO0_BUSPOW),
.EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT),
.EMIOSDIO0CDN(SDIO0_CDN),
.EMIOSDIO0CLK(SDIO0_CLK),
.EMIOSDIO0CLKFB(SDIO0_CLK_FB),
.EMIOSDIO0CMDI(SDIO0_CMD_I),
.EMIOSDIO0CMDO(SDIO0_CMD_O),
.EMIOSDIO0CMDTN(SDIO0_CMD_T_n),
.EMIOSDIO0DATAI(SDIO0_DATA_I),
.EMIOSDIO0DATAO(SDIO0_DATA_O),
.EMIOSDIO0DATATN(SDIO0_DATA_T_n),
.EMIOSDIO0LED(SDIO0_LED),
.EMIOSDIO0WP(SDIO0_WP),
.EMIOSDIO1BUSPOW(SDIO1_BUSPOW),
.EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT),
.EMIOSDIO1CDN(SDIO1_CDN),
.EMIOSDIO1CLK(SDIO1_CLK),
.EMIOSDIO1CLKFB(SDIO1_CLK_FB),
.EMIOSDIO1CMDI(SDIO1_CMD_I),
.EMIOSDIO1CMDO(SDIO1_CMD_O),
.EMIOSDIO1CMDTN(SDIO1_CMD_T_n),
.EMIOSDIO1DATAI(SDIO1_DATA_I),
.EMIOSDIO1DATAO(SDIO1_DATA_O),
.EMIOSDIO1DATATN(SDIO1_DATA_T_n),
.EMIOSDIO1LED(SDIO1_LED),
.EMIOSDIO1WP(SDIO1_WP),
.EMIOSPI0MI(SPI0_MISO_I),
.EMIOSPI0MO(SPI0_MOSI_O),
.EMIOSPI0MOTN(SPI0_MOSI_T_n),
.EMIOSPI0SCLKI(SPI0_SCLK_I),
.EMIOSPI0SCLKO(SPI0_SCLK_O),
.EMIOSPI0SCLKTN(SPI0_SCLK_T_n),
.EMIOSPI0SI(SPI0_MOSI_I),
.EMIOSPI0SO(SPI0_MISO_O),
.EMIOSPI0SSIN(SPI0_SS_I),
.EMIOSPI0SSNTN(SPI0_SS_T_n),
.EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}),
.EMIOSPI0STN(SPI0_MISO_T_n),
.EMIOSPI1MI(SPI1_MISO_I),
.EMIOSPI1MO(SPI1_MOSI_O),
.EMIOSPI1MOTN(SPI1_MOSI_T_n),
.EMIOSPI1SCLKI(SPI1_SCLK_I),
.EMIOSPI1SCLKO(SPI1_SCLK_O),
.EMIOSPI1SCLKTN(SPI1_SCLK_T_n),
.EMIOSPI1SI(SPI1_MOSI_I),
.EMIOSPI1SO(SPI1_MISO_O),
.EMIOSPI1SSIN(SPI1_SS_I),
.EMIOSPI1SSNTN(SPI1_SS_T_n),
.EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}),
.EMIOSPI1STN(SPI1_MISO_T_n),
.EMIOSRAMINTIN(SRAM_INTIN),
.EMIOTRACECLK(TRACE_CLK),
.EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED),
.EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]),
.EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}),
.EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}),
.EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}),
.EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}),
.EMIOUART0CTSN(UART0_CTSN),
.EMIOUART0DCDN(UART0_DCDN),
.EMIOUART0DSRN(UART0_DSRN),
.EMIOUART0DTRN(UART0_DTRN),
.EMIOUART0RIN(UART0_RIN),
.EMIOUART0RTSN(UART0_RTSN),
.EMIOUART0RX(UART0_RX),
.EMIOUART0TX(UART0_TX),
.EMIOUART1CTSN(UART1_CTSN),
.EMIOUART1DCDN(UART1_DCDN),
.EMIOUART1DSRN(UART1_DSRN),
.EMIOUART1DTRN(UART1_DTRN),
.EMIOUART1RIN(UART1_RIN),
.EMIOUART1RTSN(UART1_RTSN),
.EMIOUART1RX(UART1_RX),
.EMIOUART1TX(UART1_TX),
.EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL),
.EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT),
.EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT),
.EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL),
.EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT),
.EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT),
.EMIOWDTCLKI(WDT_CLK_IN),
.EMIOWDTRSTO(WDT_RST_OUT),
.EVENTEVENTI(EVENT_EVENTI),
.EVENTEVENTO(EVENT_EVENTO),
.EVENTSTANDBYWFE(EVENT_STANDBYWFE),
.EVENTSTANDBYWFI(EVENT_STANDBYWFI),
.FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK0}),
.FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}),
.FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}),
.FPGAIDLEN(FPGA_IDLE_N),
.FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK),
.FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.FTMDTRACEINVALID(1'b0),
.FTMTF2PDEBUG(FTMT_F2P_DEBUG),
.FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}),
.FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}),
.FTMTP2FDEBUG(FTMT_P2F_DEBUG),
.FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}),
.FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}),
.IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}),
.IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}),
.MAXIGP0ACLK(M_AXI_GP0_ACLK),
.MAXIGP0ARADDR(M_AXI_GP0_ARADDR),
.MAXIGP0ARBURST(M_AXI_GP0_ARBURST),
.MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ),
.MAXIGP0ARESETN(M_AXI_GP0_ARESETN),
.MAXIGP0ARID(M_AXI_GP0_ARID),
.MAXIGP0ARLEN(M_AXI_GP0_ARLEN),
.MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK),
.MAXIGP0ARPROT(M_AXI_GP0_ARPROT),
.MAXIGP0ARQOS(M_AXI_GP0_ARQOS),
.MAXIGP0ARREADY(M_AXI_GP0_ARREADY),
.MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ),
.MAXIGP0ARVALID(M_AXI_GP0_ARVALID),
.MAXIGP0AWADDR(M_AXI_GP0_AWADDR),
.MAXIGP0AWBURST(M_AXI_GP0_AWBURST),
.MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ),
.MAXIGP0AWID(M_AXI_GP0_AWID),
.MAXIGP0AWLEN(M_AXI_GP0_AWLEN),
.MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK),
.MAXIGP0AWPROT(M_AXI_GP0_AWPROT),
.MAXIGP0AWQOS(M_AXI_GP0_AWQOS),
.MAXIGP0AWREADY(M_AXI_GP0_AWREADY),
.MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ),
.MAXIGP0AWVALID(M_AXI_GP0_AWVALID),
.MAXIGP0BID(M_AXI_GP0_BID),
.MAXIGP0BREADY(M_AXI_GP0_BREADY),
.MAXIGP0BRESP(M_AXI_GP0_BRESP),
.MAXIGP0BVALID(M_AXI_GP0_BVALID),
.MAXIGP0RDATA(M_AXI_GP0_RDATA),
.MAXIGP0RID(M_AXI_GP0_RID),
.MAXIGP0RLAST(M_AXI_GP0_RLAST),
.MAXIGP0RREADY(M_AXI_GP0_RREADY),
.MAXIGP0RRESP(M_AXI_GP0_RRESP),
.MAXIGP0RVALID(M_AXI_GP0_RVALID),
.MAXIGP0WDATA(M_AXI_GP0_WDATA),
.MAXIGP0WID(M_AXI_GP0_WID),
.MAXIGP0WLAST(M_AXI_GP0_WLAST),
.MAXIGP0WREADY(M_AXI_GP0_WREADY),
.MAXIGP0WSTRB(M_AXI_GP0_WSTRB),
.MAXIGP0WVALID(M_AXI_GP0_WVALID),
.MAXIGP1ACLK(M_AXI_GP1_ACLK),
.MAXIGP1ARADDR(M_AXI_GP1_ARADDR),
.MAXIGP1ARBURST(M_AXI_GP1_ARBURST),
.MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ),
.MAXIGP1ARESETN(M_AXI_GP1_ARESETN),
.MAXIGP1ARID(M_AXI_GP1_ARID),
.MAXIGP1ARLEN(M_AXI_GP1_ARLEN),
.MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK),
.MAXIGP1ARPROT(M_AXI_GP1_ARPROT),
.MAXIGP1ARQOS(M_AXI_GP1_ARQOS),
.MAXIGP1ARREADY(M_AXI_GP1_ARREADY),
.MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ),
.MAXIGP1ARVALID(M_AXI_GP1_ARVALID),
.MAXIGP1AWADDR(M_AXI_GP1_AWADDR),
.MAXIGP1AWBURST(M_AXI_GP1_AWBURST),
.MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ),
.MAXIGP1AWID(M_AXI_GP1_AWID),
.MAXIGP1AWLEN(M_AXI_GP1_AWLEN),
.MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK),
.MAXIGP1AWPROT(M_AXI_GP1_AWPROT),
.MAXIGP1AWQOS(M_AXI_GP1_AWQOS),
.MAXIGP1AWREADY(M_AXI_GP1_AWREADY),
.MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ),
.MAXIGP1AWVALID(M_AXI_GP1_AWVALID),
.MAXIGP1BID(M_AXI_GP1_BID),
.MAXIGP1BREADY(M_AXI_GP1_BREADY),
.MAXIGP1BRESP(M_AXI_GP1_BRESP),
.MAXIGP1BVALID(M_AXI_GP1_BVALID),
.MAXIGP1RDATA(M_AXI_GP1_RDATA),
.MAXIGP1RID(M_AXI_GP1_RID),
.MAXIGP1RLAST(M_AXI_GP1_RLAST),
.MAXIGP1RREADY(M_AXI_GP1_RREADY),
.MAXIGP1RRESP(M_AXI_GP1_RRESP),
.MAXIGP1RVALID(M_AXI_GP1_RVALID),
.MAXIGP1WDATA(M_AXI_GP1_WDATA),
.MAXIGP1WID(M_AXI_GP1_WID),
.MAXIGP1WLAST(M_AXI_GP1_WLAST),
.MAXIGP1WREADY(M_AXI_GP1_WREADY),
.MAXIGP1WSTRB(M_AXI_GP1_WSTRB),
.MAXIGP1WVALID(M_AXI_GP1_WVALID),
.MIO(buffered_MIO),
.PSCLK(buffered_PS_CLK),
.PSPORB(buffered_PS_PORB),
.PSSRSTB(buffered_PS_SRSTB),
.SAXIACPACLK(S_AXI_ACP_ACLK),
.SAXIACPARADDR(S_AXI_ACP_ARADDR),
.SAXIACPARBURST(S_AXI_ACP_ARBURST),
.SAXIACPARCACHE(S_AXI_ACP_ARCACHE),
.SAXIACPARESETN(S_AXI_ACP_ARESETN),
.SAXIACPARID(S_AXI_ACP_ARID),
.SAXIACPARLEN(S_AXI_ACP_ARLEN),
.SAXIACPARLOCK(S_AXI_ACP_ARLOCK),
.SAXIACPARPROT(S_AXI_ACP_ARPROT),
.SAXIACPARQOS(S_AXI_ACP_ARQOS),
.SAXIACPARREADY(S_AXI_ACP_ARREADY),
.SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]),
.SAXIACPARUSER(S_AXI_ACP_ARUSER),
.SAXIACPARVALID(S_AXI_ACP_ARVALID),
.SAXIACPAWADDR(S_AXI_ACP_AWADDR),
.SAXIACPAWBURST(S_AXI_ACP_AWBURST),
.SAXIACPAWCACHE(S_AXI_ACP_AWCACHE),
.SAXIACPAWID(S_AXI_ACP_AWID),
.SAXIACPAWLEN(S_AXI_ACP_AWLEN),
.SAXIACPAWLOCK(S_AXI_ACP_AWLOCK),
.SAXIACPAWPROT(S_AXI_ACP_AWPROT),
.SAXIACPAWQOS(S_AXI_ACP_AWQOS),
.SAXIACPAWREADY(S_AXI_ACP_AWREADY),
.SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]),
.SAXIACPAWUSER(S_AXI_ACP_AWUSER),
.SAXIACPAWVALID(S_AXI_ACP_AWVALID),
.SAXIACPBID(S_AXI_ACP_BID),
.SAXIACPBREADY(S_AXI_ACP_BREADY),
.SAXIACPBRESP(S_AXI_ACP_BRESP),
.SAXIACPBVALID(S_AXI_ACP_BVALID),
.SAXIACPRDATA(S_AXI_ACP_RDATA),
.SAXIACPRID(S_AXI_ACP_RID),
.SAXIACPRLAST(S_AXI_ACP_RLAST),
.SAXIACPRREADY(S_AXI_ACP_RREADY),
.SAXIACPRRESP(S_AXI_ACP_RRESP),
.SAXIACPRVALID(S_AXI_ACP_RVALID),
.SAXIACPWDATA(S_AXI_ACP_WDATA),
.SAXIACPWID(S_AXI_ACP_WID),
.SAXIACPWLAST(S_AXI_ACP_WLAST),
.SAXIACPWREADY(S_AXI_ACP_WREADY),
.SAXIACPWSTRB(S_AXI_ACP_WSTRB),
.SAXIACPWVALID(S_AXI_ACP_WVALID),
.SAXIGP0ACLK(S_AXI_GP0_ACLK),
.SAXIGP0ARADDR(S_AXI_GP0_ARADDR),
.SAXIGP0ARBURST(S_AXI_GP0_ARBURST),
.SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE),
.SAXIGP0ARESETN(S_AXI_GP0_ARESETN),
.SAXIGP0ARID(S_AXI_GP0_ARID),
.SAXIGP0ARLEN(S_AXI_GP0_ARLEN),
.SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK),
.SAXIGP0ARPROT(S_AXI_GP0_ARPROT),
.SAXIGP0ARQOS(S_AXI_GP0_ARQOS),
.SAXIGP0ARREADY(S_AXI_GP0_ARREADY),
.SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]),
.SAXIGP0ARVALID(S_AXI_GP0_ARVALID),
.SAXIGP0AWADDR(S_AXI_GP0_AWADDR),
.SAXIGP0AWBURST(S_AXI_GP0_AWBURST),
.SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE),
.SAXIGP0AWID(S_AXI_GP0_AWID),
.SAXIGP0AWLEN(S_AXI_GP0_AWLEN),
.SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK),
.SAXIGP0AWPROT(S_AXI_GP0_AWPROT),
.SAXIGP0AWQOS(S_AXI_GP0_AWQOS),
.SAXIGP0AWREADY(S_AXI_GP0_AWREADY),
.SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]),
.SAXIGP0AWVALID(S_AXI_GP0_AWVALID),
.SAXIGP0BID(S_AXI_GP0_BID),
.SAXIGP0BREADY(S_AXI_GP0_BREADY),
.SAXIGP0BRESP(S_AXI_GP0_BRESP),
.SAXIGP0BVALID(S_AXI_GP0_BVALID),
.SAXIGP0RDATA(S_AXI_GP0_RDATA),
.SAXIGP0RID(S_AXI_GP0_RID),
.SAXIGP0RLAST(S_AXI_GP0_RLAST),
.SAXIGP0RREADY(S_AXI_GP0_RREADY),
.SAXIGP0RRESP(S_AXI_GP0_RRESP),
.SAXIGP0RVALID(S_AXI_GP0_RVALID),
.SAXIGP0WDATA(S_AXI_GP0_WDATA),
.SAXIGP0WID(S_AXI_GP0_WID),
.SAXIGP0WLAST(S_AXI_GP0_WLAST),
.SAXIGP0WREADY(S_AXI_GP0_WREADY),
.SAXIGP0WSTRB(S_AXI_GP0_WSTRB),
.SAXIGP0WVALID(S_AXI_GP0_WVALID),
.SAXIGP1ACLK(S_AXI_GP1_ACLK),
.SAXIGP1ARADDR(S_AXI_GP1_ARADDR),
.SAXIGP1ARBURST(S_AXI_GP1_ARBURST),
.SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE),
.SAXIGP1ARESETN(S_AXI_GP1_ARESETN),
.SAXIGP1ARID(S_AXI_GP1_ARID),
.SAXIGP1ARLEN(S_AXI_GP1_ARLEN),
.SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK),
.SAXIGP1ARPROT(S_AXI_GP1_ARPROT),
.SAXIGP1ARQOS(S_AXI_GP1_ARQOS),
.SAXIGP1ARREADY(S_AXI_GP1_ARREADY),
.SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]),
.SAXIGP1ARVALID(S_AXI_GP1_ARVALID),
.SAXIGP1AWADDR(S_AXI_GP1_AWADDR),
.SAXIGP1AWBURST(S_AXI_GP1_AWBURST),
.SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE),
.SAXIGP1AWID(S_AXI_GP1_AWID),
.SAXIGP1AWLEN(S_AXI_GP1_AWLEN),
.SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK),
.SAXIGP1AWPROT(S_AXI_GP1_AWPROT),
.SAXIGP1AWQOS(S_AXI_GP1_AWQOS),
.SAXIGP1AWREADY(S_AXI_GP1_AWREADY),
.SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]),
.SAXIGP1AWVALID(S_AXI_GP1_AWVALID),
.SAXIGP1BID(S_AXI_GP1_BID),
.SAXIGP1BREADY(S_AXI_GP1_BREADY),
.SAXIGP1BRESP(S_AXI_GP1_BRESP),
.SAXIGP1BVALID(S_AXI_GP1_BVALID),
.SAXIGP1RDATA(S_AXI_GP1_RDATA),
.SAXIGP1RID(S_AXI_GP1_RID),
.SAXIGP1RLAST(S_AXI_GP1_RLAST),
.SAXIGP1RREADY(S_AXI_GP1_RREADY),
.SAXIGP1RRESP(S_AXI_GP1_RRESP),
.SAXIGP1RVALID(S_AXI_GP1_RVALID),
.SAXIGP1WDATA(S_AXI_GP1_WDATA),
.SAXIGP1WID(S_AXI_GP1_WID),
.SAXIGP1WLAST(S_AXI_GP1_WLAST),
.SAXIGP1WREADY(S_AXI_GP1_WREADY),
.SAXIGP1WSTRB(S_AXI_GP1_WSTRB),
.SAXIGP1WVALID(S_AXI_GP1_WVALID),
.SAXIHP0ACLK(S_AXI_HP0_ACLK),
.SAXIHP0ARADDR(S_AXI_HP0_ARADDR),
.SAXIHP0ARBURST(S_AXI_HP0_ARBURST),
.SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE),
.SAXIHP0ARESETN(S_AXI_HP0_ARESETN),
.SAXIHP0ARID(S_AXI_HP0_ARID),
.SAXIHP0ARLEN(S_AXI_HP0_ARLEN),
.SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK),
.SAXIHP0ARPROT(S_AXI_HP0_ARPROT),
.SAXIHP0ARQOS(S_AXI_HP0_ARQOS),
.SAXIHP0ARREADY(S_AXI_HP0_ARREADY),
.SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]),
.SAXIHP0ARVALID(S_AXI_HP0_ARVALID),
.SAXIHP0AWADDR(S_AXI_HP0_AWADDR),
.SAXIHP0AWBURST(S_AXI_HP0_AWBURST),
.SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE),
.SAXIHP0AWID(S_AXI_HP0_AWID),
.SAXIHP0AWLEN(S_AXI_HP0_AWLEN),
.SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK),
.SAXIHP0AWPROT(S_AXI_HP0_AWPROT),
.SAXIHP0AWQOS(S_AXI_HP0_AWQOS),
.SAXIHP0AWREADY(S_AXI_HP0_AWREADY),
.SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]),
.SAXIHP0AWVALID(S_AXI_HP0_AWVALID),
.SAXIHP0BID(S_AXI_HP0_BID),
.SAXIHP0BREADY(S_AXI_HP0_BREADY),
.SAXIHP0BRESP(S_AXI_HP0_BRESP),
.SAXIHP0BVALID(S_AXI_HP0_BVALID),
.SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT),
.SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT),
.SAXIHP0RDATA(S_AXI_HP0_RDATA),
.SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN),
.SAXIHP0RID(S_AXI_HP0_RID),
.SAXIHP0RLAST(S_AXI_HP0_RLAST),
.SAXIHP0RREADY(S_AXI_HP0_RREADY),
.SAXIHP0RRESP(S_AXI_HP0_RRESP),
.SAXIHP0RVALID(S_AXI_HP0_RVALID),
.SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT),
.SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT),
.SAXIHP0WDATA(S_AXI_HP0_WDATA),
.SAXIHP0WID(S_AXI_HP0_WID),
.SAXIHP0WLAST(S_AXI_HP0_WLAST),
.SAXIHP0WREADY(S_AXI_HP0_WREADY),
.SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN),
.SAXIHP0WSTRB(S_AXI_HP0_WSTRB),
.SAXIHP0WVALID(S_AXI_HP0_WVALID),
.SAXIHP1ACLK(S_AXI_HP1_ACLK),
.SAXIHP1ARADDR(S_AXI_HP1_ARADDR),
.SAXIHP1ARBURST(S_AXI_HP1_ARBURST),
.SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE),
.SAXIHP1ARESETN(S_AXI_HP1_ARESETN),
.SAXIHP1ARID(S_AXI_HP1_ARID),
.SAXIHP1ARLEN(S_AXI_HP1_ARLEN),
.SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK),
.SAXIHP1ARPROT(S_AXI_HP1_ARPROT),
.SAXIHP1ARQOS(S_AXI_HP1_ARQOS),
.SAXIHP1ARREADY(S_AXI_HP1_ARREADY),
.SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]),
.SAXIHP1ARVALID(S_AXI_HP1_ARVALID),
.SAXIHP1AWADDR(S_AXI_HP1_AWADDR),
.SAXIHP1AWBURST(S_AXI_HP1_AWBURST),
.SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE),
.SAXIHP1AWID(S_AXI_HP1_AWID),
.SAXIHP1AWLEN(S_AXI_HP1_AWLEN),
.SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK),
.SAXIHP1AWPROT(S_AXI_HP1_AWPROT),
.SAXIHP1AWQOS(S_AXI_HP1_AWQOS),
.SAXIHP1AWREADY(S_AXI_HP1_AWREADY),
.SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]),
.SAXIHP1AWVALID(S_AXI_HP1_AWVALID),
.SAXIHP1BID(S_AXI_HP1_BID),
.SAXIHP1BREADY(S_AXI_HP1_BREADY),
.SAXIHP1BRESP(S_AXI_HP1_BRESP),
.SAXIHP1BVALID(S_AXI_HP1_BVALID),
.SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT),
.SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT),
.SAXIHP1RDATA(S_AXI_HP1_RDATA),
.SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN),
.SAXIHP1RID(S_AXI_HP1_RID),
.SAXIHP1RLAST(S_AXI_HP1_RLAST),
.SAXIHP1RREADY(S_AXI_HP1_RREADY),
.SAXIHP1RRESP(S_AXI_HP1_RRESP),
.SAXIHP1RVALID(S_AXI_HP1_RVALID),
.SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT),
.SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT),
.SAXIHP1WDATA(S_AXI_HP1_WDATA),
.SAXIHP1WID(S_AXI_HP1_WID),
.SAXIHP1WLAST(S_AXI_HP1_WLAST),
.SAXIHP1WREADY(S_AXI_HP1_WREADY),
.SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN),
.SAXIHP1WSTRB(S_AXI_HP1_WSTRB),
.SAXIHP1WVALID(S_AXI_HP1_WVALID),
.SAXIHP2ACLK(S_AXI_HP2_ACLK),
.SAXIHP2ARADDR(S_AXI_HP2_ARADDR),
.SAXIHP2ARBURST(S_AXI_HP2_ARBURST),
.SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE),
.SAXIHP2ARESETN(S_AXI_HP2_ARESETN),
.SAXIHP2ARID(S_AXI_HP2_ARID),
.SAXIHP2ARLEN(S_AXI_HP2_ARLEN),
.SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK),
.SAXIHP2ARPROT(S_AXI_HP2_ARPROT),
.SAXIHP2ARQOS(S_AXI_HP2_ARQOS),
.SAXIHP2ARREADY(S_AXI_HP2_ARREADY),
.SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]),
.SAXIHP2ARVALID(S_AXI_HP2_ARVALID),
.SAXIHP2AWADDR(S_AXI_HP2_AWADDR),
.SAXIHP2AWBURST(S_AXI_HP2_AWBURST),
.SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE),
.SAXIHP2AWID(S_AXI_HP2_AWID),
.SAXIHP2AWLEN(S_AXI_HP2_AWLEN),
.SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK),
.SAXIHP2AWPROT(S_AXI_HP2_AWPROT),
.SAXIHP2AWQOS(S_AXI_HP2_AWQOS),
.SAXIHP2AWREADY(S_AXI_HP2_AWREADY),
.SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]),
.SAXIHP2AWVALID(S_AXI_HP2_AWVALID),
.SAXIHP2BID(S_AXI_HP2_BID),
.SAXIHP2BREADY(S_AXI_HP2_BREADY),
.SAXIHP2BRESP(S_AXI_HP2_BRESP),
.SAXIHP2BVALID(S_AXI_HP2_BVALID),
.SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT),
.SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT),
.SAXIHP2RDATA(S_AXI_HP2_RDATA),
.SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN),
.SAXIHP2RID(S_AXI_HP2_RID),
.SAXIHP2RLAST(S_AXI_HP2_RLAST),
.SAXIHP2RREADY(S_AXI_HP2_RREADY),
.SAXIHP2RRESP(S_AXI_HP2_RRESP),
.SAXIHP2RVALID(S_AXI_HP2_RVALID),
.SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT),
.SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT),
.SAXIHP2WDATA(S_AXI_HP2_WDATA),
.SAXIHP2WID(S_AXI_HP2_WID),
.SAXIHP2WLAST(S_AXI_HP2_WLAST),
.SAXIHP2WREADY(S_AXI_HP2_WREADY),
.SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN),
.SAXIHP2WSTRB(S_AXI_HP2_WSTRB),
.SAXIHP2WVALID(S_AXI_HP2_WVALID),
.SAXIHP3ACLK(S_AXI_HP3_ACLK),
.SAXIHP3ARADDR(S_AXI_HP3_ARADDR),
.SAXIHP3ARBURST(S_AXI_HP3_ARBURST),
.SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE),
.SAXIHP3ARESETN(S_AXI_HP3_ARESETN),
.SAXIHP3ARID(S_AXI_HP3_ARID),
.SAXIHP3ARLEN(S_AXI_HP3_ARLEN),
.SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK),
.SAXIHP3ARPROT(S_AXI_HP3_ARPROT),
.SAXIHP3ARQOS(S_AXI_HP3_ARQOS),
.SAXIHP3ARREADY(S_AXI_HP3_ARREADY),
.SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]),
.SAXIHP3ARVALID(S_AXI_HP3_ARVALID),
.SAXIHP3AWADDR(S_AXI_HP3_AWADDR),
.SAXIHP3AWBURST(S_AXI_HP3_AWBURST),
.SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE),
.SAXIHP3AWID(S_AXI_HP3_AWID),
.SAXIHP3AWLEN(S_AXI_HP3_AWLEN),
.SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK),
.SAXIHP3AWPROT(S_AXI_HP3_AWPROT),
.SAXIHP3AWQOS(S_AXI_HP3_AWQOS),
.SAXIHP3AWREADY(S_AXI_HP3_AWREADY),
.SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]),
.SAXIHP3AWVALID(S_AXI_HP3_AWVALID),
.SAXIHP3BID(S_AXI_HP3_BID),
.SAXIHP3BREADY(S_AXI_HP3_BREADY),
.SAXIHP3BRESP(S_AXI_HP3_BRESP),
.SAXIHP3BVALID(S_AXI_HP3_BVALID),
.SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT),
.SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT),
.SAXIHP3RDATA(S_AXI_HP3_RDATA),
.SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN),
.SAXIHP3RID(S_AXI_HP3_RID),
.SAXIHP3RLAST(S_AXI_HP3_RLAST),
.SAXIHP3RREADY(S_AXI_HP3_RREADY),
.SAXIHP3RRESP(S_AXI_HP3_RRESP),
.SAXIHP3RVALID(S_AXI_HP3_RVALID),
.SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT),
.SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT),
.SAXIHP3WDATA(S_AXI_HP3_WDATA),
.SAXIHP3WID(S_AXI_HP3_WID),
.SAXIHP3WLAST(S_AXI_HP3_WLAST),
.SAXIHP3WREADY(S_AXI_HP3_WREADY),
.SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN),
.SAXIHP3WSTRB(S_AXI_HP3_WSTRB),
.SAXIHP3WVALID(S_AXI_HP3_WVALID));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_CLK_BIBUF
(.IO(buffered_PS_CLK),
.PAD(PS_CLK));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_PORB_BIBUF
(.IO(buffered_PS_PORB),
.PAD(PS_PORB));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF PS_SRSTB_BIBUF
(.IO(buffered_PS_SRSTB),
.PAD(PS_SRSTB));
LUT1 #(
.INIT(2'h1))
SDIO0_CMD_T_INST_0
(.I0(SDIO0_CMD_T_n),
.O(SDIO0_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[0]_INST_0
(.I0(SDIO0_DATA_T_n[0]),
.O(SDIO0_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[1]_INST_0
(.I0(SDIO0_DATA_T_n[1]),
.O(SDIO0_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[2]_INST_0
(.I0(SDIO0_DATA_T_n[2]),
.O(SDIO0_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO0_DATA_T[3]_INST_0
(.I0(SDIO0_DATA_T_n[3]),
.O(SDIO0_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SDIO1_CMD_T_INST_0
(.I0(SDIO1_CMD_T_n),
.O(SDIO1_CMD_T));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[0]_INST_0
(.I0(SDIO1_DATA_T_n[0]),
.O(SDIO1_DATA_T[0]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[1]_INST_0
(.I0(SDIO1_DATA_T_n[1]),
.O(SDIO1_DATA_T[1]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[2]_INST_0
(.I0(SDIO1_DATA_T_n[2]),
.O(SDIO1_DATA_T[2]));
LUT1 #(
.INIT(2'h1))
\SDIO1_DATA_T[3]_INST_0
(.I0(SDIO1_DATA_T_n[3]),
.O(SDIO1_DATA_T[3]));
LUT1 #(
.INIT(2'h1))
SPI0_MISO_T_INST_0
(.I0(SPI0_MISO_T_n),
.O(SPI0_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI0_MOSI_T_INST_0
(.I0(SPI0_MOSI_T_n),
.O(SPI0_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI0_SCLK_T_INST_0
(.I0(SPI0_SCLK_T_n),
.O(SPI0_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI0_SS_T_INST_0
(.I0(SPI0_SS_T_n),
.O(SPI0_SS_T));
LUT1 #(
.INIT(2'h1))
SPI1_MISO_T_INST_0
(.I0(SPI1_MISO_T_n),
.O(SPI1_MISO_T));
LUT1 #(
.INIT(2'h1))
SPI1_MOSI_T_INST_0
(.I0(SPI1_MOSI_T_n),
.O(SPI1_MOSI_T));
LUT1 #(
.INIT(2'h1))
SPI1_SCLK_T_INST_0
(.I0(SPI1_SCLK_T_n),
.O(SPI1_SCLK_T));
LUT1 #(
.INIT(2'h1))
SPI1_SS_T_INST_0
(.I0(SPI1_SS_T_n),
.O(SPI1_SS_T));
VCC VCC
(.P(\<const1> ));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[0].MIO_BIBUF
(.IO(buffered_MIO[0]),
.PAD(MIO[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[10].MIO_BIBUF
(.IO(buffered_MIO[10]),
.PAD(MIO[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[11].MIO_BIBUF
(.IO(buffered_MIO[11]),
.PAD(MIO[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[12].MIO_BIBUF
(.IO(buffered_MIO[12]),
.PAD(MIO[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[13].MIO_BIBUF
(.IO(buffered_MIO[13]),
.PAD(MIO[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[14].MIO_BIBUF
(.IO(buffered_MIO[14]),
.PAD(MIO[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[15].MIO_BIBUF
(.IO(buffered_MIO[15]),
.PAD(MIO[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[16].MIO_BIBUF
(.IO(buffered_MIO[16]),
.PAD(MIO[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[17].MIO_BIBUF
(.IO(buffered_MIO[17]),
.PAD(MIO[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[18].MIO_BIBUF
(.IO(buffered_MIO[18]),
.PAD(MIO[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[19].MIO_BIBUF
(.IO(buffered_MIO[19]),
.PAD(MIO[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[1].MIO_BIBUF
(.IO(buffered_MIO[1]),
.PAD(MIO[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[20].MIO_BIBUF
(.IO(buffered_MIO[20]),
.PAD(MIO[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[21].MIO_BIBUF
(.IO(buffered_MIO[21]),
.PAD(MIO[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[22].MIO_BIBUF
(.IO(buffered_MIO[22]),
.PAD(MIO[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[23].MIO_BIBUF
(.IO(buffered_MIO[23]),
.PAD(MIO[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[24].MIO_BIBUF
(.IO(buffered_MIO[24]),
.PAD(MIO[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[25].MIO_BIBUF
(.IO(buffered_MIO[25]),
.PAD(MIO[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[26].MIO_BIBUF
(.IO(buffered_MIO[26]),
.PAD(MIO[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[27].MIO_BIBUF
(.IO(buffered_MIO[27]),
.PAD(MIO[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[28].MIO_BIBUF
(.IO(buffered_MIO[28]),
.PAD(MIO[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[29].MIO_BIBUF
(.IO(buffered_MIO[29]),
.PAD(MIO[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[2].MIO_BIBUF
(.IO(buffered_MIO[2]),
.PAD(MIO[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[30].MIO_BIBUF
(.IO(buffered_MIO[30]),
.PAD(MIO[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[31].MIO_BIBUF
(.IO(buffered_MIO[31]),
.PAD(MIO[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[32].MIO_BIBUF
(.IO(buffered_MIO[32]),
.PAD(MIO[32]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[33].MIO_BIBUF
(.IO(buffered_MIO[33]),
.PAD(MIO[33]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[34].MIO_BIBUF
(.IO(buffered_MIO[34]),
.PAD(MIO[34]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[35].MIO_BIBUF
(.IO(buffered_MIO[35]),
.PAD(MIO[35]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[36].MIO_BIBUF
(.IO(buffered_MIO[36]),
.PAD(MIO[36]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[37].MIO_BIBUF
(.IO(buffered_MIO[37]),
.PAD(MIO[37]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[38].MIO_BIBUF
(.IO(buffered_MIO[38]),
.PAD(MIO[38]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[39].MIO_BIBUF
(.IO(buffered_MIO[39]),
.PAD(MIO[39]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[3].MIO_BIBUF
(.IO(buffered_MIO[3]),
.PAD(MIO[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[40].MIO_BIBUF
(.IO(buffered_MIO[40]),
.PAD(MIO[40]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[41].MIO_BIBUF
(.IO(buffered_MIO[41]),
.PAD(MIO[41]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[42].MIO_BIBUF
(.IO(buffered_MIO[42]),
.PAD(MIO[42]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[43].MIO_BIBUF
(.IO(buffered_MIO[43]),
.PAD(MIO[43]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[44].MIO_BIBUF
(.IO(buffered_MIO[44]),
.PAD(MIO[44]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[45].MIO_BIBUF
(.IO(buffered_MIO[45]),
.PAD(MIO[45]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[46].MIO_BIBUF
(.IO(buffered_MIO[46]),
.PAD(MIO[46]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[47].MIO_BIBUF
(.IO(buffered_MIO[47]),
.PAD(MIO[47]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[48].MIO_BIBUF
(.IO(buffered_MIO[48]),
.PAD(MIO[48]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[49].MIO_BIBUF
(.IO(buffered_MIO[49]),
.PAD(MIO[49]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[4].MIO_BIBUF
(.IO(buffered_MIO[4]),
.PAD(MIO[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[50].MIO_BIBUF
(.IO(buffered_MIO[50]),
.PAD(MIO[50]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[51].MIO_BIBUF
(.IO(buffered_MIO[51]),
.PAD(MIO[51]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[52].MIO_BIBUF
(.IO(buffered_MIO[52]),
.PAD(MIO[52]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[53].MIO_BIBUF
(.IO(buffered_MIO[53]),
.PAD(MIO[53]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[5].MIO_BIBUF
(.IO(buffered_MIO[5]),
.PAD(MIO[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[6].MIO_BIBUF
(.IO(buffered_MIO[6]),
.PAD(MIO[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[7].MIO_BIBUF
(.IO(buffered_MIO[7]),
.PAD(MIO[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[8].MIO_BIBUF
(.IO(buffered_MIO[8]),
.PAD(MIO[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk13[9].MIO_BIBUF
(.IO(buffered_MIO[9]),
.PAD(MIO[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[0].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[0]),
.PAD(DDR_BankAddr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[1].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[1]),
.PAD(DDR_BankAddr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk14[2].DDR_BankAddr_BIBUF
(.IO(buffered_DDR_BankAddr[2]),
.PAD(DDR_BankAddr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[0].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[0]),
.PAD(DDR_Addr[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[10].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[10]),
.PAD(DDR_Addr[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[11].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[11]),
.PAD(DDR_Addr[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[12].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[12]),
.PAD(DDR_Addr[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[13].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[13]),
.PAD(DDR_Addr[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[14].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[14]),
.PAD(DDR_Addr[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[1].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[1]),
.PAD(DDR_Addr[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[2].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[2]),
.PAD(DDR_Addr[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[3].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[3]),
.PAD(DDR_Addr[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[4].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[4]),
.PAD(DDR_Addr[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[5].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[5]),
.PAD(DDR_Addr[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[6].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[6]),
.PAD(DDR_Addr[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[7].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[7]),
.PAD(DDR_Addr[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[8].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[8]),
.PAD(DDR_Addr[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk15[9].DDR_Addr_BIBUF
(.IO(buffered_DDR_Addr[9]),
.PAD(DDR_Addr[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[0].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[0]),
.PAD(DDR_DM[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[1].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[1]),
.PAD(DDR_DM[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[2].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[2]),
.PAD(DDR_DM[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk16[3].DDR_DM_BIBUF
(.IO(buffered_DDR_DM[3]),
.PAD(DDR_DM[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[0].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[0]),
.PAD(DDR_DQ[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[10].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[10]),
.PAD(DDR_DQ[10]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[11].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[11]),
.PAD(DDR_DQ[11]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[12].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[12]),
.PAD(DDR_DQ[12]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[13].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[13]),
.PAD(DDR_DQ[13]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[14].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[14]),
.PAD(DDR_DQ[14]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[15].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[15]),
.PAD(DDR_DQ[15]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[16].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[16]),
.PAD(DDR_DQ[16]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[17].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[17]),
.PAD(DDR_DQ[17]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[18].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[18]),
.PAD(DDR_DQ[18]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[19].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[19]),
.PAD(DDR_DQ[19]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[1].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[1]),
.PAD(DDR_DQ[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[20].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[20]),
.PAD(DDR_DQ[20]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[21].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[21]),
.PAD(DDR_DQ[21]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[22].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[22]),
.PAD(DDR_DQ[22]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[23].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[23]),
.PAD(DDR_DQ[23]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[24].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[24]),
.PAD(DDR_DQ[24]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[25].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[25]),
.PAD(DDR_DQ[25]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[26].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[26]),
.PAD(DDR_DQ[26]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[27].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[27]),
.PAD(DDR_DQ[27]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[28].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[28]),
.PAD(DDR_DQ[28]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[29].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[29]),
.PAD(DDR_DQ[29]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[2].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[2]),
.PAD(DDR_DQ[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[30].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[30]),
.PAD(DDR_DQ[30]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[31].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[31]),
.PAD(DDR_DQ[31]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[3].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[3]),
.PAD(DDR_DQ[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[4].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[4]),
.PAD(DDR_DQ[4]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[5].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[5]),
.PAD(DDR_DQ[5]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[6].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[6]),
.PAD(DDR_DQ[6]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[7].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[7]),
.PAD(DDR_DQ[7]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[8].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[8]),
.PAD(DDR_DQ[8]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk17[9].DDR_DQ_BIBUF
(.IO(buffered_DDR_DQ[9]),
.PAD(DDR_DQ[9]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[0].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[0]),
.PAD(DDR_DQS_n[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[1].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[1]),
.PAD(DDR_DQS_n[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[2].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[2]),
.PAD(DDR_DQS_n[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk18[3].DDR_DQS_n_BIBUF
(.IO(buffered_DDR_DQS_n[3]),
.PAD(DDR_DQS_n[3]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[0].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[0]),
.PAD(DDR_DQS[0]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[1].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[1]),
.PAD(DDR_DQS[1]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[2].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[2]),
.PAD(DDR_DQS[2]));
(* BOX_TYPE = "PRIMITIVE" *)
BIBUF \genblk19[3].DDR_DQS_BIBUF
(.IO(buffered_DDR_DQS[3]),
.PAD(DDR_DQS[3]));
LUT1 #(
.INIT(2'h2))
i_0
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[0] ));
LUT1 #(
.INIT(2'h2))
i_1
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [1]));
LUT1 #(
.INIT(2'h2))
i_10
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [1]));
LUT1 #(
.INIT(2'h2))
i_11
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[7] [0]));
LUT1 #(
.INIT(2'h2))
i_12
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [1]));
LUT1 #(
.INIT(2'h2))
i_13
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[6] [0]));
LUT1 #(
.INIT(2'h2))
i_14
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [1]));
LUT1 #(
.INIT(2'h2))
i_15
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[5] [0]));
LUT1 #(
.INIT(2'h2))
i_16
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [1]));
LUT1 #(
.INIT(2'h2))
i_17
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[4] [0]));
LUT1 #(
.INIT(2'h2))
i_18
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [1]));
LUT1 #(
.INIT(2'h2))
i_19
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[3] [0]));
LUT1 #(
.INIT(2'h2))
i_2
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[0] [0]));
LUT1 #(
.INIT(2'h2))
i_20
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [1]));
LUT1 #(
.INIT(2'h2))
i_21
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[2] [0]));
LUT1 #(
.INIT(2'h2))
i_22
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [1]));
LUT1 #(
.INIT(2'h2))
i_23
(.I0(1'b0),
.O(\TRACE_DATA_PIPE[1] [0]));
LUT1 #(
.INIT(2'h2))
i_3
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[7] ));
LUT1 #(
.INIT(2'h2))
i_4
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[6] ));
LUT1 #(
.INIT(2'h2))
i_5
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[5] ));
LUT1 #(
.INIT(2'h2))
i_6
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[4] ));
LUT1 #(
.INIT(2'h2))
i_7
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[3] ));
LUT1 #(
.INIT(2'h2))
i_8
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[2] ));
LUT1 #(
.INIT(2'h2))
i_9
(.I0(1'b0),
.O(\TRACE_CTL_PIPE[1] ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module bbram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4 localram0(
.DO (data_out[3:0]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[3:0]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram0.INIT_00 = 256'hEECCCBABCBAA98061EDEFEDDDCBDFFDDDCBCDCBBA94307555385689665A70303;
defparam localram0.INIT_01 = 256'h05B3709AD059097099D960BC70BAD06BA70BADCB65BAF147587D0DCDEDCCCBAC;
defparam localram0.INIT_02 = 256'h01808B850770550A3077B3607C0677ABD00808B850770550A3077B3070577AAD;
defparam localram0.INIT_03 = 256'hA70983040A609B50A70983040A609B50A70954040A7DD8DCAAD706CE0AAA7ABD;
defparam localram0.INIT_04 = 256'h50A70983040A609B50A70983040A609B50A70954040AB50AA50976040A60AB50;
defparam localram0.INIT_05 = 256'hBB40780576C4078057670C7D76DD056B7ECAE0506BCAAD706BCA7098040A609B;
defparam localram0.INIT_06 = 256'hDD4D60C70ABDA0AB70080950FA4078056670BBDC4C0780586BA70BBDC60ACC30;
defparam localram0.INIT_07 = 256'h457754688450B650B80CBD70C90B3BDACC4D74688450C650C80DCE70D90C3CEB;
defparam localram0.INIT_08 = 256'h86A5018440ABB50A60563AA436ACB664A40561568640AB05AB09A0BC4580CD9C;
defparam localram0.INIT_09 = 256'h00000000000000000021232123212308D7470564BB9709DD960AB70AADA07805;
defparam localram0.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram1(
.DO (data_out[7:4]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[7:4]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram1.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram2(
.DO (data_out[11:8]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[11:8]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram2.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram3(
.DO (data_out[15:12]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[15:12]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram3.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram4(
.DO (data_out[19:16]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[19:16]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram4.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram5(
.DO (data_out[23:20]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[23:20]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram5.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram6(
.DO (data_out[27:24]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[27:24]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram6.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram7(
.DO (data_out[31:28]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[31:28]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram7.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O31AI_BLACKBOX_V
`define SKY130_FD_SC_HS__O31AI_BLACKBOX_V
/**
* o31ai: 3-input OR into 2-input NAND.
*
* Y = !((A1 | A2 | A3) & B1)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o31ai (
Y ,
A1,
A2,
A3,
B1
);
output Y ;
input A1;
input A2;
input A3;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O31AI_BLACKBOX_V
|
/* == HW1 P11 & P12 == */
/* 11: Develope a small set of test patterns that will (1) test a half-adder
* circuit, (2) test a full-adder circuit, (3) exahausively test a 4-bit ripple
* carry adder, and (4) test a 16 bit ripple carry adder by verifying that the
* conectivity between the 4-bit slices are connected correctly, given that the
* 4-bit slices themselves have been verified
*/
/* 12: Develop and exercise a testbench (including a test plan) to verify
* a gate-level model of a full adder
*/
/* For problem 11 & 12, please develop the verilog code for a 4 bit ripple
* carry adder first and verify it by simulation. Then develop the rest of the
* code to answer question 11 and 12
*/
module half_adder(output S, C, input A, B);
xor sum(S,A,B);
and carry(C,A,B);
endmodule
module full_adder(output S, Cout, input A,B,Cin);
wire s1, c1, c2;
half_adder ha1(s1,c1, A ,B ),
ha2(S ,c2, s1,Cin);
or carry(Cout, c1,c2);
endmodule
module r4_adder(output [3:0]S, output Cout, input [3:0]A, B, input Cin);
wire c1, c2, c3;
full_adder fa1(S[0], c1, A[0], B[0], Cin),
fa2(S[1], c2, A[1], B[1], c1),
fa3(S[2], c3, A[2], B[2], c2),
fa4(S[3], Cout, A[3], B[3], c3);
endmodule
module r16_adder(output [15:0]S, output Cout, input [15:0] A, B, input Cin);
wire c1, c2, c3;
r4_adder a1(S[ 3: 0], c1, A[ 3: 0], B[ 3: 0], Cin),
a2(S[ 7: 4], c2, A[ 7: 4], B[ 7: 4], c1),
a3(S[11: 8], c3, A[11: 8], B[11: 8], c2),
a4(S[15:12], Cout, A[15:12], B[15:12], c3);
endmodule
|
// (C) 2001-2017 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Intel Program License Subscription
// Agreement, Intel MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Intel and sold by
// Intel or its authorized distributors. Please refer to the applicable
// agreement for further details.
// THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
// FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS
// IN THIS FILE.
module altera_up_video_dma_to_memory (
// Inputs
clk,
reset,
stream_data,
stream_startofpacket,
stream_endofpacket,
stream_empty,
stream_valid,
master_waitrequest,
// Bidirectional
// Outputs
stream_ready,
master_write,
master_writedata,
inc_address,
reset_address
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DW = 15; // Frame's datawidth
parameter EW = 0; // Frame's empty width
parameter MDW = 15; // Avalon master's datawidth
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input clk;
input reset;
input [DW: 0] stream_data;
input stream_startofpacket;
input stream_endofpacket;
input [EW: 0] stream_empty;
input stream_valid;
input master_waitrequest;
// Bidirectional
// Outputs
output stream_ready;
output master_write;
output [MDW:0] master_writedata;
output inc_address;
output reset_address;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
// Internal Registers
reg [DW: 0] temp_data;
reg temp_valid;
// State Machine Registers
// Integers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
always @(posedge clk)
begin
if (reset & ~master_waitrequest)
begin
temp_data <= 'h0;
temp_valid <= 1'b0;
end
else if (stream_ready)
begin
temp_data <= stream_data;
temp_valid <= stream_valid;
end
end
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign stream_ready = ~reset & (~temp_valid | ~master_waitrequest);
assign master_write = temp_valid;
assign master_writedata = temp_data;
assign inc_address = stream_ready & stream_valid;
assign reset_address = inc_address & stream_startofpacket;
// Internal Assignments
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nor4b (
Y ,
A ,
B ,
C ,
D_N
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire nor0_out_Y;
// Name Output Other arguments
not not0 (not0_out , D_N );
nor nor0 (nor0_out_Y, A, B, C, not0_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4B_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21A_1_V
`define SKY130_FD_SC_LS__O21A_1_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog wrapper for o21a with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21a.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21a_1 (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__o21a_1 (
X ,
A1,
A2,
B1
);
output X ;
input A1;
input A2;
input B1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__o21a base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21A_1_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD,
AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H,
DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO
);
wire mode_vcchib;
output XRES_H_N;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout PAD;
input DISABLE_PULLUP_H;
input ENABLE_H;
input EN_VDDIO_SIG_H;
input INP_SEL_H;
input FILT_IN_H;
inout PULLUP_H;
input ENABLE_VDDIO;
supply1 vccd;
supply1 vcchib;
supply1 vdda;
supply1 vddio;
supply1 vddio_q;
supply0 vssa;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply1 vswitch;
wire pwr_good_xres_tmp = 1;
wire pwr_good_xres_h_n = 1;
wire pwr_good_pullup = 1;
inout PAD_A_ESD_H;
output TIE_HI_ESD;
output TIE_LO_ESD;
inout TIE_WEAK_HI_H;
wire tmp1;
pullup (pull1) p1 (tmp1); tranif1 x_pull_1 (TIE_WEAK_HI_H, tmp1, pwr_good_pullup===0 ? 1'bx : 1);
tran p2 (PAD, PAD_A_ESD_H);
buf p4 (TIE_HI_ESD, vddio);
buf p5 (TIE_LO_ESD, vssio);
wire tmp;
pullup (pull1) p3 (tmp); tranif0 x_pull (PULLUP_H, tmp, pwr_good_pullup===0 || ^DISABLE_PULLUP_H===1'bx ? 1'bx : DISABLE_PULLUP_H);
parameter MAX_WARNING_COUNT = 100;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
parameter MIN_DELAY = 0;
parameter MAX_DELAY = 0;
`else
parameter MIN_DELAY = 50;
parameter MAX_DELAY = 600;
`endif
integer min_delay, max_delay;
initial begin
min_delay = MIN_DELAY;
max_delay = MAX_DELAY;
end
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_ENABLE_VDDIO_CHANGE_X
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 1;
`else
parameter DISABLE_ENABLE_VDDIO_CHANGE_X = 0;
`endif
integer disable_enable_vddio_change_x = DISABLE_ENABLE_VDDIO_CHANGE_X;
reg notifier_enable_h;
specify
`ifdef SKY130_FD_IO_TOP_XRES4V2_DISABLE_DELAY
specparam DELAY = 0;
`else
specparam DELAY = 50;
`endif
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==1) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==1 & ENABLE_VDDIO==1 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==0 & ENABLE_H==0 & ENABLE_VDDIO==0 & EN_VDDIO_SIG_H==0) (PAD => XRES_H_N) = (0:0:0 , 0:0:0);
if (INP_SEL_H==1) (FILT_IN_H => XRES_H_N) = (0:0:0 , 0:0:0);
specparam tsetup = 0;
specparam thold = 5;
endspecify
reg corrupt_enable;
always @(notifier_enable_h)
begin
corrupt_enable <= 1'bx;
end
initial
begin
corrupt_enable = 1'b0;
end
always @(PAD or ENABLE_H or EN_VDDIO_SIG_H or ENABLE_VDDIO or INP_SEL_H or FILT_IN_H or pwr_good_xres_tmp or DISABLE_PULLUP_H or PULLUP_H or TIE_WEAK_HI_H)
begin
corrupt_enable <= 1'b0;
end
assign mode_vcchib = ENABLE_H && !EN_VDDIO_SIG_H;
wire xres_tmp = (pwr_good_xres_tmp===0 || ^PAD===1'bx || (mode_vcchib===1'bx ) ||(mode_vcchib!==1'b0 && ^ENABLE_VDDIO===1'bx) || (corrupt_enable===1'bx) ||
(mode_vcchib===1'b1 && ENABLE_VDDIO===0 && (disable_enable_vddio_change_x===0)))
? 1'bx : PAD;
wire x_on_xres_h_n = (pwr_good_xres_h_n===0
|| ^INP_SEL_H===1'bx
|| INP_SEL_H===1 && ^FILT_IN_H===1'bx
|| INP_SEL_H===0 && xres_tmp===1'bx);
assign #1 XRES_H_N = x_on_xres_h_n===1 ? 1'bx : (INP_SEL_H===1 ? FILT_IN_H : xres_tmp);
realtime t_pad_current_transition,t_pad_prev_transition;
realtime t_filt_in_h_current_transition,t_filt_in_h_prev_transition;
realtime pad_pulse_width, filt_in_h_pulse_width;
always @(PAD)
begin
if (^PAD !== 1'bx)
begin
t_pad_prev_transition = t_pad_current_transition;
t_pad_current_transition = $realtime;
pad_pulse_width = t_pad_current_transition - t_pad_prev_transition;
end
else
begin
t_pad_prev_transition = 0;
t_pad_current_transition = 0;
pad_pulse_width = 0;
end
end
always @(FILT_IN_H)
begin
if (^FILT_IN_H !== 1'bx)
begin
t_filt_in_h_prev_transition = t_filt_in_h_current_transition;
t_filt_in_h_current_transition = $realtime;
filt_in_h_pulse_width = t_filt_in_h_current_transition - t_filt_in_h_prev_transition;
end
else
begin
t_filt_in_h_prev_transition = 0;
t_filt_in_h_current_transition = 0;
filt_in_h_pulse_width = 0;
end
end
reg dis_err_msgs;
integer msg_count_pad, msg_count_filt_in_h;
event event_errflag_pad_pulse_width, event_errflag_filt_in_h_pulse_width;
initial
begin
dis_err_msgs = 1'b1;
msg_count_pad = 0; msg_count_filt_in_h = 0;
`ifdef SKY130_FD_IO_TOP_XRES4V2_DIS_ERR_MSGS
`else
#1;
dis_err_msgs = 1'b0;
`endif
end
always @(pad_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===0 && (pad_pulse_width > min_delay) && (pad_pulse_width < max_delay))
begin
msg_count_pad = msg_count_pad + 1;
->event_errflag_pad_pulse_width;
if (msg_count_pad <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for PAD input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",pad_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_pad == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
always @(filt_in_h_pulse_width)
begin
if (!dis_err_msgs)
begin
if (INP_SEL_H===1 && (filt_in_h_pulse_width > min_delay) && (filt_in_h_pulse_width < max_delay))
begin
msg_count_filt_in_h = msg_count_filt_in_h + 1;
->event_errflag_filt_in_h_pulse_width;
if (msg_count_filt_in_h <= MAX_WARNING_COUNT)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Width of Input pulse for FILT_IN_H input (= %3.2f ns) is found to be in \the range: %3d ns - %3d ns. In this range, the delay and pulse suppression of the input pulse are PVT dependent. : \%m",filt_in_h_pulse_width,min_delay,max_delay,$stime);
end
else
if (msg_count_filt_in_h == MAX_WARNING_COUNT+1)
begin
$display(" ===WARNING=== sky130_fd_io__top_xres4v2 : Further WARNING messages will be suppressed as the \message count has exceeded 100 %m",$stime);
end
end
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__XNOR2_TB_V
`define SKY130_FD_SC_HDLL__XNOR2_TB_V
/**
* xnor2: 2-input exclusive NOR.
*
* Y = !(A ^ B)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__xnor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_hdll__xnor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__XNOR2_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__INV_TB_V
`define SKY130_FD_SC_LS__INV_TB_V
/**
* inv: Inverter.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__inv.v"
module top();
// Inputs are registered
reg A;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 VGND = 1'b0;
#60 VNB = 1'b0;
#80 VPB = 1'b0;
#100 VPWR = 1'b0;
#120 A = 1'b1;
#140 VGND = 1'b1;
#160 VNB = 1'b1;
#180 VPB = 1'b1;
#200 VPWR = 1'b1;
#220 A = 1'b0;
#240 VGND = 1'b0;
#260 VNB = 1'b0;
#280 VPB = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VPB = 1'b1;
#360 VNB = 1'b1;
#380 VGND = 1'b1;
#400 A = 1'b1;
#420 VPWR = 1'bx;
#440 VPB = 1'bx;
#460 VNB = 1'bx;
#480 VGND = 1'bx;
#500 A = 1'bx;
end
sky130_fd_sc_ls__inv dut (.A(A), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__INV_TB_V
|
// Module: altera_tse_xcvr_resync
//
// Description:
// A general purpose resynchronization module.
//
// Parameters:
// SYNC_CHAIN_LENGTH
// - Specifies the length of the synchronizer chain for metastability
// retiming.
// WIDTH
// - Specifies the number of bits you want to synchronize. Controls the width of the
// d and q ports.
// SLOW_CLOCK - USE WITH CAUTION.
// - Leaving this setting at its default will create a standard resynch circuit that
// merely passes the input data through a chain of flip-flops. This setting assumes
// that the input data has a pulse width longer than one clock cycle sufficient to
// satisfy setup and hold requirements on at least one clock edge.
// - By setting this to 1 (USE CAUTION) you are creating an asynchronous
// circuit that will capture the input data regardless of the pulse width and
// its relationship to the clock. However it is more difficult to apply static
// timing constraints as it ties the data input to the clock input of the flop.
// This implementation assumes the data rate is slow enough
//
module altera_tse_xcvr_resync #(
parameter SYNC_CHAIN_LENGTH = 2, // Number of flip-flops for retiming
parameter WIDTH = 1, // Number of bits to resync
parameter SLOW_CLOCK = 0 // See description above
) (
input wire clk,
input wire [WIDTH-1:0] d,
output wire [WIDTH-1:0] q
);
localparam INT_LEN = (SYNC_CHAIN_LENGTH > 0) ? SYNC_CHAIN_LENGTH : 1;
genvar ig;
// Generate a synchronizer chain for each bit
generate begin
for(ig=0;ig<WIDTH;ig=ig+1) begin : resync_chains
wire d_in; // Input to sychronization chain.
reg [INT_LEN-1:0] r = {INT_LEN{1'b0}};
wire [INT_LEN :0] next_r; // One larger real chain
assign q[ig] = r[INT_LEN-1]; // Output signal
assign next_r = {r,d_in};
always @(posedge clk)
r <= next_r[INT_LEN-1:0];
// Generate asynchronous capture circuit if specified.
if(SLOW_CLOCK == 0) begin
assign d_in = d[ig];
end else begin
wire d_clk;
reg d_r;
wire clr_n;
assign d_clk = d[ig];
assign d_in = d_r;
assign clr_n = ~q[ig] | d_clk; // Clear when output is logic 1 and input is logic 0
// Asynchronously latch the input signal.
always @(posedge d_clk or negedge clr_n)
if(!clr_n) d_r <= 1'b0;
else if(d_clk) d_r <= 1'b1;
end // SLOW_CLOCK
end // for loop
end // generate
endgenerate
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
// developed independently, and may be accompanied by separate and unique license
// terms.
//
// The user should read each of these license terms, and understand the
// freedoms and responsibilities that he or she has by using this source/core.
//
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
// A PARTICULAR PURPOSE.
//
// Redistribution and use of source or resulting binaries, with or without modification
// of this file, are permitted under one of the following two license terms:
//
// 1. The GNU General Public License version 2 as published by the
// Free Software Foundation, which can be found in the top level directory
// of this repository (LICENSE_GPL2), and also online at:
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
//
// OR
//
// 2. An ADI specific BSD license, which can be found in the top level directory
// of this repository (LICENSE_ADIBSD), and also on-line at:
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
// This will allow to generate bit files and not release the source code,
// as long as it attaches to an ADI device.
//
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module dmac_src_mm_axi #(
parameter ID_WIDTH = 3,
parameter DMA_DATA_WIDTH = 64,
parameter DMA_ADDR_WIDTH = 32,
parameter BYTES_PER_BEAT_WIDTH = 3,
parameter BEATS_PER_BURST_WIDTH = 4,
parameter AXI_LENGTH_WIDTH = 8)(
input m_axi_aclk,
input m_axi_aresetn,
input req_valid,
output req_ready,
input [DMA_ADDR_WIDTH-1:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input enable,
output reg enabled = 1'b0,
output bl_valid,
input bl_ready,
output [BEATS_PER_BURST_WIDTH-1:0] measured_last_burst_length,
/*
output response_valid,
input response_ready,
output [1:0] response_resp,
*/
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input address_eot,
output fifo_valid,
output [DMA_DATA_WIDTH-1:0] fifo_data,
output fifo_last,
// Read address
input m_axi_arready,
output m_axi_arvalid,
output [DMA_ADDR_WIDTH-1:0] m_axi_araddr,
output [AXI_LENGTH_WIDTH-1:0] m_axi_arlen,
output [ 2:0] m_axi_arsize,
output [ 1:0] m_axi_arburst,
output [ 2:0] m_axi_arprot,
output [ 3:0] m_axi_arcache,
// Read data and response
input [DMA_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input m_axi_rlast,
input [ 1:0] m_axi_rresp
);
`include "inc_id.vh"
reg [ID_WIDTH-1:0] id = 'h00;
wire address_enabled;
wire req_ready_ag;
wire req_valid_ag;
wire bl_ready_ag;
wire bl_valid_ag;
assign data_id = id;
assign response_id = id;
assign measured_last_burst_length = req_last_burst_length;
splitter #(
.NUM_M(3)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
bl_valid,
bl_valid_ag,
req_valid_ag
}),
.m_ready({
bl_ready,
bl_ready_ag,
req_ready_ag
})
);
dmac_address_generator #(
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH),
.LENGTH_WIDTH(AXI_LENGTH_WIDTH),
.DMA_ADDR_WIDTH(DMA_ADDR_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(enable),
.enabled(address_enabled),
.request_id(request_id),
.id(address_id),
.req_valid(req_valid_ag),
.req_ready(req_ready_ag),
.req_address(req_address),
.bl_valid(bl_valid_ag),
.bl_ready(bl_ready_ag),
.measured_last_burst_length(req_last_burst_length),
.eot(address_eot),
.addr_ready(m_axi_arready),
.addr_valid(m_axi_arvalid),
.addr(m_axi_araddr),
.len(m_axi_arlen),
.size(m_axi_arsize),
.burst(m_axi_arburst),
.prot(m_axi_arprot),
.cache(m_axi_arcache)
);
assign fifo_valid = m_axi_rvalid;
assign fifo_data = m_axi_rdata;
assign fifo_last = m_axi_rlast;
/*
* There is a requirement that data_id <= address_id (modulo 2**ID_WIDTH). We
* know that we will never receive data before we have requested it so there is
* an implicit dependency between data_id and address_id and no need to
* explicitly track it.
*/
always @(posedge m_axi_aclk) begin
if (m_axi_aresetn == 1'b0) begin
id <= 'h00;
end else if (m_axi_rvalid == 1'b1 && m_axi_rlast == 1'b1) begin
id <= inc_id(id);
end
end
/*
* We won't be receiving data before we've requested it and we won't request
* data unless there is room in the store-and-forward memory.
*/
assign m_axi_rready = 1'b1;
/*
* We need to complete all bursts for which an address has been put onto the
* AXI-MM interface.
*/
always @(posedge m_axi_aclk) begin
if (m_axi_aresetn == 1'b0) begin
enabled <= 1'b0;
end else if (address_enabled == 1'b1) begin
enabled <= 1'b1;
end else if (id == address_id) begin
enabled <= 1'b0;
end
end
/* TODO
`include "resp.vh"
assign response_valid = 1'b0;
assign response_resp = RESP_OKAY;
reg [1:0] rresp;
always @(posedge m_axi_aclk)
begin
if (m_axi_rvalid && m_axi_rready) begin
if (m_axi_rresp != 2'b0)
rresp <= m_axi_rresp;
end
end
*/
endmodule
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
Require Export CoRN.ftc.Continuity.
From Coq Require Import Lia.
(** printing Partition_Sum %\ensuremath{\sum_P}% #∑<sub>P</sub># *)
Section Definitions.
(**
* Partitions
We now begin to lay the way for the definition of Riemann integral. This will
be done through the definition of a sequence of
sums that is proved to be convergent; in order to do that, we first
need to do a bit of work on partitions.
** Definitions
A partition is defined as a record type. For each compact interval [[a,b]]
and each natural number [n], a partition of [[a,b]] with [n+1] points is a
choice of real numbers [a [=] a0 [<=] a1 [<=] an [=] b]; the following
specification works as follows:
- [Pts] is the function that chooses the points (it is declared as a
coercion);
- [prf1] states that [Pts] is a setoid function;
- [prf2] states that the points are ordered;
- [start] requires that [a0 [=] a] and
- [finish] requires that [an [=] b].
*)
Record Partition (a b : IR) (Hab : a [<=] b) (lng : nat) : Type :=
{Pts :> forall i, i <= lng -> IR;
prf1 : forall i j, i = j -> forall Hi Hj, Pts i Hi [=] Pts j Hj;
prf2 : forall i Hi HSi, Pts i Hi [<=] Pts (S i) HSi;
start : forall H, Pts 0 H [=] a;
finish : forall H, Pts lng H [=] b}.
(** Two immediate consequences of this are that [ai [<=] aj] whenever
[i < j] and that [ai] is in [[a,b]] for all [i].
*)
Lemma Partition_mon : forall a b Hab lng (P : Partition a b Hab lng) i j Hi Hj,
i <= j -> P i Hi [<=] P j Hj.
Proof.
intros; induction j as [| j Hrecj].
cut (i = 0); [ intro | auto with arith ].
apply eq_imp_leEq; apply prf1; auto.
elim (le_lt_eq_dec _ _ H); intro H1.
cut (j <= lng); [ intro | clear Hrecj; lia ].
apply leEq_transitive with (Pts _ _ _ _ P j H0).
apply Hrecj; clear Hrecj; auto with arith.
apply prf2.
apply eq_imp_leEq; apply prf1; assumption.
Qed.
Lemma Partition_in_compact : forall a b Hab lng (P : Partition a b Hab lng) i Hi,
compact a b Hab (P i Hi).
Proof.
intros.
split.
apply leEq_wdl with (P _ (le_O_n _)).
apply Partition_mon; auto with arith.
apply start.
apply leEq_wdr with (P _ (le_n _)).
apply Partition_mon; auto with arith.
apply finish.
Qed.
(**
Each partition of [[a,b]] implies a partition of the interval
$[a,a_{n-1}]$#[a,a<sub>n-1</sub>]#. This partition will play an
important role in much of our future work, so we take some care to
define it.
*)
Lemma part_pred_lemma : forall a b Hab lng (P : Partition a b Hab lng) i Hi, a [<=] P i Hi.
Proof.
intros.
apply leEq_wdl with (P 0 (le_O_n _)).
apply Partition_mon; auto with arith.
apply start.
Qed.
Definition Partition_Dom a b Hab n P :
Partition a _ (part_pred_lemma a b Hab (S n) P n (le_n_Sn n)) n.
Proof.
intros.
apply Build_Partition with (fun (i : nat) (Hi : i <= n) => P i (le_S _ _ Hi)).
intros; simpl in |- *; apply prf1; assumption.
intros; simpl in |- *; apply prf2.
intros; simpl in |- *; apply start.
intros; simpl in |- *; apply prf1; auto.
Defined.
(**
The mesh of a partition is the greatest distance between two
consecutive points. For convenience's sake we also define the dual
concept, which is very helpful in some situations. In order to do
this, we begin by building a list with all the distances between
consecutive points; next we only need to extract the maximum and the
minimum of this list. Notice that this list is nonempty except in the
case when [a [=] b] and [n = 0]; this means that the convention we took
of defining the minimum and maximum of the empty list to be [0] actually
helps us in this case.
*)
Definition Part_Mesh_List n a b Hab (P : Partition a b Hab n) : list IR.
Proof.
revert a b Hab P; induction n as [| n Hrecn]; intros.
apply (@nil IR).
apply cons.
apply (P _ (le_n (S n)) [-]P _ (le_S _ _ (le_n n))).
apply Hrecn with a (P _ (le_n_Sn n)) (part_pred_lemma _ _ _ _ P n (le_n_Sn n)).
apply Partition_Dom.
Defined.
Definition Mesh a b Hab n P := maxlist (Part_Mesh_List n a b Hab P).
Definition AntiMesh a b Hab n P := minlist (Part_Mesh_List n a b Hab P).
(**
Even partitions (partitions where all the points are evenly spaced)
will also play a central role in our work; the first two lemmas are
presented simply to make the definition of even partition lighter.
*)
Lemma even_part_1 : forall a b n Hn, a[+]nring 0[*] (b[-]a[/] _[//]nring_ap_zero' IR n Hn) [=] a.
Proof.
intros; rational.
Qed.
Lemma even_part_2 : forall a b n Hn, a[+]nring n[*] (b[-]a[/] _[//]nring_ap_zero' IR n Hn) [=] b.
Proof.
intros; rational.
Qed.
Definition Even_Partition a b Hab n (Hn : 0 <> n) : Partition a b Hab n.
Proof.
intros.
apply Build_Partition with (fun (i : nat) (Hi : i <= n) =>
a[+]nring i[*] (b[-]a[/] _[//]nring_ap_zero' _ n Hn)).
intros; simpl in |- *.
rewrite H; algebra.
intros; simpl in |- *.
apply plus_resp_leEq_lft.
apply mult_resp_leEq_rht.
apply less_leEq; apply less_plusOne.
apply shift_leEq_div.
apply nring_pos; clear Hi; apply neq_O_lt; auto.
apply shift_leEq_minus.
astepl ([0][+]a).
astepl a; assumption.
intros; simpl in |- *; apply even_part_1; auto.
intros; simpl in |- *; apply even_part_2; auto.
Defined.
Section Refinements.
Variables a b : IR.
Hypothesis Hab : a [<=] b.
Variables m n : nat.
Variable P : (Partition a b Hab n).
Variable Q : (Partition a b Hab m).
(**
We now define what it means for a partition [Q] to be a refinement of
[P] and prove the main property of refinements.
*)
Definition Refinement := {f : nat -> nat |
f 0 = 0 /\ f n = m /\ (forall i j, i < j -> f i < f j) |
forall i Hi, {H' : f i <= m | P i Hi [=] Q (f i) H'}}.
Lemma Refinement_prop : Refinement -> forall i (Hi : i <= m) (HSi : (S i) <= m),
{j : nat | {Hj : j <= n | {HSj : S j <= n | P _ Hj [<=] Q _ Hi | Q _ HSi [<=] P _ HSj}}}.
Proof.
intros H i Hi Hi'.
elim H; clear H; intros f Hf.
elim Hf; clear Hf; intros Hf0 Hf.
elim Hf; clear Hf; intros Hfn Hfmon.
intro Hf.
cut {j : nat | f j <= i | S i <= f (S j)}.
intro H.
elim H; clear H; intros j Hj Hj'.
exists j.
cut (j < n).
intro.
cut (j <= n); [ intro Hj1 | auto with arith ].
exists Hj1.
elim (Hf j Hj1); intros H' HPts.
cut (S j <= n); [ intro Hj2 | apply H ].
elim (Hf (S j) Hj2); intros H'' HPts'.
exists Hj2.
eapply leEq_wdl.
2: eapply eq_transitive_unfolded.
2: apply eq_symmetric_unfolded; apply HPts.
apply Partition_mon; assumption.
apply prf1; auto.
eapply leEq_wdr.
2: eapply eq_transitive_unfolded.
2: apply eq_symmetric_unfolded; apply HPts'.
apply Partition_mon; assumption.
apply prf1; auto.
clear Hj' Hf Hf0.
cut (i < f n).
intro.
cut (f j < f n); [ intro | apply le_lt_trans with i; auto ].
apply not_ge.
intro; red in H1.
apply (le_not_lt (f j) (f n)); auto with arith.
apply Hfmon.
elim (le_lt_eq_dec _ _ H1); intro; auto.
rewrite b0 in H0; elim (lt_irrefl (f j)); auto.
rewrite <- Hfn in Hi'; auto.
apply mon_fun_covers; auto.
exists n; clear Hf Hfmon.
rewrite Hfn; assumption.
Qed.
(**
We will also need to consider arbitrary sums %of the form
\[\sum_{i=0}^{n-1}f(x_i)(a_{i+1}-a_i)\]%#of
f(x<sub>i</sub>)(a<sub>i+1</sub>-a<sub>i</sub>)# where
$x_i\in[a_i,a_{i+1}]$#x<sub>i</sub>∈[a<sub>i</sub>,a<sub>i+1</sub>]#.
For this, we again need a choice function [x] which has to satisfy
some condition. We define the condition and the sum for a fixed [P]:
*)
Definition Points_in_Partition (g : forall i, i < n -> IR) : CProp :=
forall i Hi, Compact (prf2 _ _ _ _ P i (lt_le_weak _ _ Hi) Hi) (g i Hi).
Lemma Pts_part_lemma : forall g, Points_in_Partition g -> forall i Hi, compact a b Hab (g i Hi).
Proof.
intros g H i H0.
elim (H i H0); intros.
split.
eapply leEq_transitive.
2: apply a0.
apply leEq_wdl with (P 0 (le_O_n _)).
apply Partition_mon; auto with arith.
apply start.
eapply leEq_transitive.
apply b0.
apply leEq_wdr with (P n (le_n _)).
apply Partition_mon; auto with arith.
apply finish.
Qed.
Definition Partition_Sum g F (H : Points_in_Partition g) (incF : included (Compact Hab) (Dom F)) :=
Sumx (fun i Hi => F (g i Hi) (incF _ (Pts_part_lemma _ H i Hi)) [*]
(P (S i) Hi[-]P i (lt_le_weak _ _ Hi))).
End Refinements.
Arguments Points_in_Partition [a b Hab n].
Arguments Partition_Sum [a b Hab n P g F].
(**
** Constructions
We now formalize some trivial and helpful constructions.
%\begin{convention}% We will assume a fixed compact interval [[a,b]], denoted by [I].
%\end{convention}%
*)
Variables a b : IR.
Hypothesis Hab : a [<=] b.
(* begin hide *)
Let I := compact a b Hab.
(* end hide *)
Section Getting_Points.
(**
From a partition we always have a canonical choice of points at which
to evaluate a function: just take all but the last points of the
partition.
%\begin{convention}% Let [Q] be a partition of [I] with [m] points.
%\end{convention}%
*)
Variable m : nat.
Variable Q : Partition a b Hab m.
Definition Partition_imp_points : forall i : nat, i < m -> IR.
Proof.
intros.
apply (Q i (lt_le_weak _ _ H)).
Defined.
Lemma Partition_imp_points_1 : Points_in_Partition Q Partition_imp_points.
Proof.
red in |- *; intros.
unfold Partition_imp_points in |- *; split.
apply leEq_reflexive.
apply prf2.
Qed.
Lemma Partition_imp_points_2 : nat_less_n_fun Partition_imp_points.
Proof.
red in |- *; intros.
unfold Partition_imp_points in |- *; simpl in |- *.
apply prf1; auto.
Qed.
End Getting_Points.
(**
As a corollary, given any continuous function [F] and a natural number we have an immediate choice of a sum of [F] in [[a,b]].
*)
Variable F : PartIR.
Hypothesis contF : Continuous_I Hab F.
Definition Even_Partition_Sum (n : nat) (Hn : 0 <> n) : IR.
Proof.
intros.
apply Partition_Sum with a b Hab n (Even_Partition a b Hab n Hn)
(Partition_imp_points _ (Even_Partition a b Hab n Hn)) F.
apply Partition_imp_points_1.
apply contin_imp_inc; assumption.
Defined.
End Definitions.
Arguments Partition [a b].
Arguments Partition_Dom [a b Hab n].
Arguments Mesh [a b Hab n].
Arguments AntiMesh [a b Hab n].
Arguments Pts [a b Hab lng].
Arguments Part_Mesh_List [n a b Hab].
Arguments Points_in_Partition [a b Hab n].
Arguments Partition_Sum [a b Hab n P g F].
Arguments Even_Partition [a b].
Arguments Even_Partition_Sum [a b].
Arguments Refinement [a b Hab m n].
Hint Resolve start finish: algebra.
Section Lemmas.
(**
** Properties of the mesh
If a partition has more than one point then its mesh list is nonempty.
*)
Lemma length_Part_Mesh_List : forall n (a b : IR) (Hab : a [<=] b) (P : Partition Hab n),
0 < n -> 0 < length (Part_Mesh_List P).
Proof.
intro; case n; intros.
elimtype False; inversion H.
simpl in |- *; auto with arith.
Qed.
(**
Any element of the auxiliary list defined to calculate the mesh of a partition has a very specific form.
*)
Lemma Part_Mesh_List_lemma : forall n (a b : IR) (Hab : a [<=] b) (P : Partition Hab n) x,
member x (Part_Mesh_List P) ->
{i : nat | {Hi : i <= n | {Hi' : S i <= n | x [=] P _ Hi'[-]P _ Hi}}}.
Proof.
intro; induction n as [| n Hrecn].
simpl in |- *; intros.
easy.
intros a b Hab P x H.
simpl in H; elim H; clear H; intro H0.
elim (Hrecn _ _ _ _ _ H0); clear Hrecn.
intros i H; elim H; clear H.
intros Hi H; elim H; clear H.
intros Hi' H.
simpl in H.
exists i; exists (le_S _ _ Hi); exists (le_S _ _ Hi').
eapply eq_transitive_unfolded.
apply H.
apply cg_minus_wd; apply prf1; auto.
exists n.
exists (le_S _ _ (le_n n)).
exists (le_n (S n)).
eapply eq_transitive_unfolded.
apply H0.
apply cg_minus_wd; apply prf1; auto.
Qed.
(**
Mesh and antimesh are always nonnegative.
*)
Lemma Mesh_nonneg : forall n (a b : IR) (Hab : a [<=] b) (P : Partition Hab n), [0] [<=] Mesh P.
Proof.
simple induction n.
intros; unfold Mesh in |- *; simpl in |- *.
apply leEq_reflexive.
clear n; intros.
unfold Mesh in |- *.
apply leEq_transitive with (P _ (le_n (S n)) [-]P _ (le_S _ _ (le_n n))).
apply shift_leEq_minus; astepl (P _ (le_S _ _ (le_n n))).
apply prf2.
apply maxlist_greater.
right; algebra.
Qed.
Lemma AntiMesh_nonneg : forall n (a b : IR) (Hab : a [<=] b) (P : Partition Hab n),
[0] [<=] AntiMesh P.
Proof.
intro; induction n as [| n Hrecn].
intros; unfold AntiMesh in |- *; simpl in |- *.
apply leEq_reflexive.
intros.
unfold AntiMesh in |- *.
apply leEq_minlist.
simpl in |- *; auto with arith.
intros y H.
simpl in H; elim H; clear H; intro H0.
unfold AntiMesh in Hrecn.
apply leEq_transitive with (minlist (Part_Mesh_List (Partition_Dom P))).
2: apply minlist_smaller; assumption.
apply Hrecn.
eapply leEq_wdr.
2: apply eq_symmetric_unfolded; apply H0.
apply shift_leEq_minus; astepl (P _ (le_S _ _ (le_n n))).
apply prf2.
Qed.
(**
Most important, [AntiMesh] and [Mesh] provide lower and upper bounds
for the distance between any two consecutive points in a partition.
%\begin{convention}% Let [I] be [[a,b]] and [P] be a partition of [I]
with [n] points.
%\end{convention}%
*)
Variables a b : IR.
(* begin hide *)
Let I := compact a b.
(* end hide *)
Hypothesis Hab : a [<=] b.
Variable n : nat.
Variable P : Partition Hab n.
Lemma Mesh_lemma : forall i H H', P (S i) H'[-]P i H [<=] Mesh P.
Proof.
clear I; generalize n a b Hab P; clear P n Hab a b.
simple induction n.
intros; elimtype False; inversion H'.
clear n; intro m; intros.
induction m as [| m Hrecm].
cut (0 = i); [ intro | inversion H'; auto; inversion H2 ].
generalize H0 H'; clear H0 H'; rewrite <- H1.
intros.
unfold Mesh in |- *; simpl in |- *.
apply eq_imp_leEq; apply cg_minus_wd; apply prf1; auto.
elim (le_lt_eq_dec _ _ H'); intro H1.
cut (i <= S m); [ intro | auto with arith ].
cut (S i <= S m); [ intro | auto with arith ].
set (P' := Partition_Dom P) in *.
apply leEq_wdl with (P' _ H3[-]P' _ H2).
2: simpl in |- *; apply cg_minus_wd; apply prf1; auto.
apply leEq_transitive with (Mesh P').
apply H.
unfold Mesh in |- *; simpl in |- *; apply rht_leEq_Max.
cut (i = S m); [ intro | auto with arith ].
generalize H' H0; clear H0 H'.
rewrite H2; intros.
unfold Mesh in |- *; apply maxlist_greater; right.
apply cg_minus_wd; apply prf1; auto.
Qed.
Lemma AntiMesh_lemma : forall i H H', AntiMesh P [<=] P (S i) H'[-]P i H.
Proof.
clear I; generalize n a b Hab P; clear P n Hab a b.
simple induction n.
intros; elimtype False; inversion H'.
clear n; intro m; intros.
induction m as [| m Hrecm].
cut (0 = i); [ intro | inversion H'; auto; inversion H2 ].
generalize H0 H'; clear H0 H'; rewrite <- H1.
intros.
unfold AntiMesh in |- *; simpl in |- *.
apply eq_imp_leEq; apply cg_minus_wd; apply prf1; auto.
elim (le_lt_eq_dec _ _ H'); intro H1.
cut (i <= S m); [ intro | auto with arith ].
cut (S i <= S m); [ intro | auto with arith ].
set (P' := Partition_Dom P) in *.
apply leEq_wdr with (P' _ H3[-]P' _ H2).
2: simpl in |- *; apply cg_minus_wd; apply prf1; auto.
apply leEq_transitive with (AntiMesh P').
2: apply H.
unfold AntiMesh in |- *; simpl in |- *. unfold MIN.
eapply leEq_wdr.
2: apply cg_inv_inv.
apply inv_resp_leEq; apply rht_leEq_Max.
cut (i = S m); [ intro | auto with arith ].
generalize H' H0; clear H0 H'.
rewrite H2; intros.
unfold AntiMesh in |- *; apply minlist_smaller; right.
apply cg_minus_wd; apply prf1; auto.
Qed.
Lemma Mesh_leEq : forall m (Q : Partition Hab m), Refinement P Q -> Mesh Q [<=] Mesh P.
Proof.
intro; case m.
intros Q H.
unfold Mesh at 1 in |- *; simpl in |- *.
apply Mesh_nonneg.
clear m; intros m Q H.
unfold Mesh at 1 in |- *.
apply maxlist_leEq.
simpl in |- *; auto with arith.
intros x H0.
elim (Part_Mesh_List_lemma _ _ _ _ _ _ H0).
clear H0. intros i H0.
elim H0; clear H0; intros Hi H0.
elim H0; clear H0; intros Hi' H0.
eapply leEq_wdl.
2: apply eq_symmetric_unfolded; apply H0.
elim H; intros f Hf.
elim Hf; clear Hf; intros Hf' Hf.
cut {j : nat | {Hj : j <= n | {Hj' : S j <= n | P _ Hj [<=] Q _ Hi | Q _ Hi' [<=] P _ Hj'}}}.
intro H1.
elim H1; intros j Hj.
elim Hj; clear H1 Hj; intros Hj Hjaux.
elim Hjaux; clear Hjaux; intros Hj' Hjaux.
intros HPts HPts'.
apply leEq_transitive with (P _ Hj'[-]P _ Hj).
unfold cg_minus in |- *; apply plus_resp_leEq_both.
assumption.
apply inv_resp_leEq; assumption.
apply Mesh_lemma.
apply Refinement_prop; assumption.
Qed.
End Lemmas.
Section Even_Partitions.
(** More technical stuff. Two equal partitions have the same mesh.
*)
Lemma Mesh_wd : forall n a b b' (Hab : a [<=] b) (Hab' : a [<=] b')
(P : Partition Hab n) (Q : Partition Hab' n),
(forall i Hi, P i Hi [=] Q i Hi) -> Mesh P [=] Mesh Q.
Proof.
simple induction n.
intros.
unfold Mesh in |- *; simpl in |- *; algebra.
clear n; intro.
case n.
intros.
unfold Mesh in |- *; simpl in |- *.
apply cg_minus_wd; apply H0.
clear n; intros.
unfold Mesh in |- *.
apply eq_transitive_unfolded with (Max (P _ (le_n (S (S n))) [-]P _ (le_S _ _ (le_n (S n))))
(maxlist (Part_Mesh_List (Partition_Dom P)))).
simpl in |- *; algebra.
apply eq_transitive_unfolded with (Max (Q _ (le_n (S (S n))) [-]Q _ (le_S _ _ (le_n (S n))))
(maxlist (Part_Mesh_List (Partition_Dom Q)))).
2: simpl in |- *; algebra.
apply Max_wd_unfolded.
apply cg_minus_wd; apply H0.
apply eq_transitive_unfolded with (Mesh (Partition_Dom P)).
unfold Mesh in |- *; algebra.
apply eq_transitive_unfolded with (Mesh (Partition_Dom Q)).
apply H.
intros.
unfold Partition_Dom in |- *; simpl in |- *.
apply H0.
unfold Mesh in |- *; algebra.
Qed.
Lemma Mesh_wd' : forall n a b (Hab : a [<=] b) (P Q : Partition Hab n),
(forall i Hi, P i Hi [=] Q i Hi) -> Mesh P [=] Mesh Q.
Proof.
intros.
apply Mesh_wd.
intros; apply H.
Qed.
(**
The mesh of an even partition is easily calculated.
*)
Lemma even_partition_Mesh : forall m Hm a b (Hab : a [<=] b),
Mesh (Even_Partition Hab m Hm) [=] (b[-]a[/] _[//]nring_ap_zero' _ _ Hm).
Proof.
simple induction m.
intros; elimtype False; apply Hm; auto.
intros.
unfold Mesh in |- *.
elim (le_lt_dec n 0); intro.
cut (0 = n); [ intro | auto with arith ].
generalize Hm; clear H a0 Hm.
rewrite <- H0; intros.
simpl in |- *.
rational.
apply eq_transitive_unfolded with (Max (a[+]nring (S n) [*] (b[-]a[/] _[//]nring_ap_zero' _ _ Hm) [-]
(a[+]nring n[*] (b[-]a[/] _[//]nring_ap_zero' _ _ Hm)))
(maxlist (Part_Mesh_List (Partition_Dom (Even_Partition Hab _ Hm))))).
cut (n = S (pred n)); [ intro | apply S_pred with 0; auto ].
generalize Hm; rewrite H0; clear Hm; intro.
simpl in |- *; algebra.
eapply eq_transitive_unfolded.
apply Max_comm.
simpl in |- *.
eapply eq_transitive_unfolded.
apply leEq_imp_Max_is_rht.
2: rational.
apply eq_imp_leEq.
rstepr (b[-]a[/] nring n[+][1][//]nring_ap_zero' _ _ Hm).
apply eq_transitive_unfolded with (Mesh (Partition_Dom (Even_Partition Hab _ Hm))).
simpl in |- *; algebra.
cut (0 <> n); intro.
eapply eq_transitive_unfolded.
apply Mesh_wd' with (Q := Even_Partition (part_pred_lemma _ _ Hab (S n) (Even_Partition Hab _ Hm) n
(le_n_Sn n)) _ H0).
intros; simpl in |- *; rational.
eapply eq_transitive_unfolded.
apply H.
simpl in |- *; rational.
apply (lt_O_neq n); auto.
Qed.
(**
** Miscellaneous
%\begin{convention}% Throughout this section, let [a,b:IR] and [I] be [[a,b]].
%\end{convention}%
*)
Variables a b : IR.
(* begin hide *)
Let I := compact a b.
(* end hide *)
Hypothesis Hab : a [<=] b.
(**
An interesting property: in a partition, if [ai [<] aj] then [i < j].
*)
Lemma Partition_Points_mon : forall n (P : Partition Hab n) i j Hi Hj,
P i Hi [<] P j Hj -> i < j.
Proof.
intros.
cut (~ j <= i); intro.
apply not_ge; auto.
elimtype False.
apply less_irreflexive_unfolded with (x := P i Hi).
apply less_leEq_trans with (P j Hj).
assumption.
apply local_mon'_imp_mon'_le with (f := fun (i : nat) (Hi : i <= n) => P i Hi).
intros; apply prf2.
intro; intros; apply prf1; assumption.
assumption.
Qed.
Lemma refinement_resp_mult : forall m n Hm Hn, {k : nat | m = n * k} ->
Refinement (Even_Partition Hab n Hn) (Even_Partition Hab m Hm).
Proof.
intros m n Hm Hn H.
elim H; intros k Hk.
red in |- *.
cut (0 <> k); intro.
exists (fun i : nat => i * k); repeat split.
symmetry in |- *; assumption.
intros.
apply mult_lt_compat_r.
assumption.
apply neq_O_lt; auto.
intros.
cut (i * k <= m).
intro.
exists H1.
simpl in |- *.
apply bin_op_wd_unfolded.
algebra.
generalize Hm; rewrite Hk.
clear Hm; intro.
rstepl (nring i[*]nring k[*] (b[-]a[/] _[//]
mult_resp_ap_zero _ _ _ (nring_ap_zero' _ _ Hn) (nring_ap_zero' _ _ H0))).
apply mult_wd.
apply eq_symmetric_unfolded; apply nring_comm_mult.
apply div_wd.
algebra.
apply eq_symmetric_unfolded; apply nring_comm_mult.
rewrite Hk.
apply mult_le_compat_r; assumption.
apply Hm.
rewrite Hk.
rewrite <- H0.
auto.
Qed.
(**
%\begin{convention}% Assume [m,n] are positive natural numbers and
denote by [P] and [Q] the even partitions with, respectively, [m] and
[n] points.
%\end{convention}%
Even partitions always have a common refinement.
*)
Variables m n : nat.
Hypothesis Hm : 0 <> m.
Hypothesis Hn : 0 <> n.
(* begin hide *)
Let P := Even_Partition Hab m Hm.
Let Q := Even_Partition Hab n Hn.
(* end hide *)
Lemma even_partition_refinement : {N : nat | {HN : 0 <> N |
Refinement P (Even_Partition Hab N HN) |
Refinement Q (Even_Partition Hab N HN)}}.
Proof.
exists (m * n).
cut (0 <> m * n); intro.
exists H.
unfold P in |- *; apply refinement_resp_mult.
exists n; auto.
unfold Q in |- *; apply refinement_resp_mult.
exists m; auto with arith.
clear P Q.
cut (nring (R:=IR) (m * n) [#] [0]).
rewrite <- H; simpl in |- *.
apply ap_irreflexive_unfolded.
astepl (nring m[*]nring (R:=IR) n).
apply mult_resp_ap_zero; apply Greater_imp_ap; astepl (nring (R:=IR) 0);
apply nring_less; apply neq_O_lt; auto.
Qed.
End Even_Partitions.
Section More_Definitions.
(**
** Separation
Some auxiliary definitions. A partition is said to be separated if all its points are distinct.
*)
Variables a b : IR.
Hypothesis Hab : a [<=] b.
Definition _Separated n (P : Partition Hab n) := forall i Hi H', P i Hi [<] P (S i) H'.
(**
Two partitions are said to be (mutually) separated if they are both
separated and all their points are distinct (except for the
endpoints).
%\begin{convention}% Let [P,Q] be partitions of [I] with,
respectively, [n] and [m] points.
%\end{convention}%
*)
Variables n m : nat.
Variable P : Partition Hab n.
Variable Q : Partition Hab m.
Definition Separated := _Separated _ P and _Separated _ Q and
(forall i j, 0 < i -> 0 < j -> i < n -> j < m -> forall Hi Hj, P i Hi [#] Q j Hj).
End More_Definitions.
Arguments _Separated [a b Hab n].
Arguments Separated [a b Hab n m].
Section Sep_Partitions.
Variables a b : IR.
(* begin hide *)
Let I := compact a b.
(* end hide *)
Hypothesis Hab : a [<=] b.
(**
The antimesh of a separated partition is always positive.
*)
Lemma pos_AntiMesh : forall n (P : Partition Hab n),
0 < n -> _Separated P -> [0] [<] AntiMesh P.
Proof.
intro; case n; clear n.
intros P H H0; elimtype False; apply (lt_irrefl _ H).
intros n P H H0.
unfold AntiMesh in |- *.
apply less_minlist.
simpl in |- *; auto with arith.
intros y H1.
elim (Part_Mesh_List_lemma _ _ _ _ _ _ H1); intros i Hi.
elim Hi; clear Hi; intros Hi Hi'.
elim Hi'; clear Hi'; intros Hi' H'.
eapply less_wdr.
2: apply eq_symmetric_unfolded; apply H'.
apply shift_less_minus; astepl (P i Hi).
apply H0.
Qed.
(**
A partition can have only one point iff the endpoints of the interval
are the same; moreover, if the partition is separated and the
endpoints of the interval are the same then it must have one point.
*)
Lemma partition_length_zero : Partition Hab 0 -> a [=] b.
Proof.
intro H.
Step_final (H 0 (le_O_n 0)).
Qed.
Lemma _Separated_imp_length_zero : forall n (P : Partition Hab n),
_Separated P -> a [=] b -> 0 = n.
Proof.
intros n P H H0.
cut (~ 0 <> n); [ auto with zarith | intro ].
cut (0 < n); [ intro | apply neq_O_lt; auto ].
cut (a [#] b).
exact (eq_imp_not_ap _ _ _ H0).
astepl (P _ (le_O_n _)).
astepr (P _ (le_n _)).
apply less_imp_ap.
apply local_mon_imp_mon_le with (f := fun (i : nat) (H : i <= n) => P i H).
exact H.
assumption.
Qed.
Lemma partition_less_imp_gt_zero : forall n (P : Partition Hab n), a [<] b -> 0 < n.
Proof.
intros n P H.
cut (0 <> n); intro.
apply neq_O_lt; auto.
elimtype False.
cut (a [=] b).
intro; apply less_irreflexive_unfolded with (x := a).
astepr b; assumption.
apply partition_length_zero.
rewrite H0; apply P.
Qed.
End Sep_Partitions.
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Tue May 30 22:27:54 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_dual_fusion/zed_dual_fusion.srcs/sources_1/bd/system/ip/system_rgb565_to_rgb888_1_0/system_rgb565_to_rgb888_1_0_stub.v
// Design : system_rgb565_to_rgb888_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "rgb565_to_rgb888,Vivado 2016.4" *)
module system_rgb565_to_rgb888_1_0(clk, rgb_565, rgb_888)
/* synthesis syn_black_box black_box_pad_pin="clk,rgb_565[15:0],rgb_888[23:0]" */;
input clk;
input [15:0]rgb_565;
output [23:0]rgb_888;
endmodule
|
// Texas A&M University //
// cpsc350 Computer Architecture //
// $Id: IdealMemory.v,v 1.3 2002/11/19 00:58:22 miket Exp miket $ //
// InstrMem is an asynchronous read memory model //
// MemSize Wordise parameterize the memory module at instantiation time //
module InstrMem (Mem_Addr, Dout);
parameter T_rd = 10;
parameter MemSize = 1024, WordSize = 32;
input [WordSize-1:0] Mem_Addr;
output [WordSize-1:0] Dout;
reg [WordSize-1:0] Dout;
reg [WordSize-1:0] Mem[0:MemSize-1]; // register array (SRAM)
//`include "imeminit.v"
// Include your test program file here instead of "imeminit.v"
`include "imeminit_simple_test.v"
always
#T_rd assign Dout = Mem[ Mem_Addr >> 2 ];
endmodule // Imem
// DataMem is an asynchronous read, synchronous write memory model //
// This memory cannot be read and written to simultaneously //
module DataMem (Mem_Addr, CLK, Mem_rd, Mem_wr, Mem_DIN, Mem_DOUT);
parameter T_rd = 10, T_wr = 10;
parameter MemSize = 1024, WordSize = 32;
input [WordSize-1:0] Mem_Addr;
input CLK, Mem_rd, Mem_wr;
input [WordSize-1:0] Mem_DIN;
output [WordSize-1:0] Mem_DOUT;
reg [WordSize-1:0] Mem_DOUT;
reg [WordSize-1:0] Mem[0:MemSize-1];
integer i;
`include "dmeminit.v"
always @( Mem_Addr or Mem_rd )
if ( ~Mem_wr && Mem_rd )
Mem_DOUT <= #T_rd Mem[Mem_Addr >> 2];
always @(negedge CLK)
if (Mem_wr == 1)
begin
// $display ($time, " . . . ", ..., Mem_DIN);
Mem[Mem_Addr >> 2] <= #T_wr Mem_DIN;
end
endmodule // Dmem |
`timescale 1ns/1ns
module dtc
#(parameter INVERT_CURRENT_DIRECTION = 1'b1,
parameter MIN_PULSE = 16'd2500, // this is 10 usec => 25 kHz
parameter MAX_PULSE = 16'd5000, // this is 40 usec
parameter MIN_DEAD = 16'd62) // this is 500 nsec
(input c, // clock input
input [15:0] i_tgt, // target current
input [15:0] i_est, // estimated current
input i_est_valid, // flag indicating that i_est is valid
input [15:0] max_t, // maximum state pulse time, in 125 MHz ticks
input [15:0] min_t, // minimum state pulse time, in 125 MHz ticks
input [15:0] dead, // dead time, in 125 MHz ticks
output hi, // high-side MOSFET
output lo); // low-side MOSFET
// we have to re-register the input signals, since they are taking
// too long to go cross-chip from the UDP RX registers
wire [15:0] i_tgt_i;
d1 #(16) i_tgt_i_r(.c(c), .d(i_tgt), .q(i_tgt_i));
localparam ST_HI = 2'd0;
localparam ST_DEAD_0 = 2'd1;
localparam ST_LO = 2'd2;
localparam ST_DEAD_1 = 2'd3;
localparam SW=2, CW=3;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r(.c(c), .rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire [15:0] min_i, max_i, dead_i;
d1 #(16) min_i_r (.c(c), .d(min_t>MIN_PULSE ? min_t : MIN_PULSE), .q(min_i));
d1 #(16) max_i_r (.c(c), .d(max_t>MAX_PULSE ? max_t : MAX_PULSE), .q(max_i));
d1 #(16) dead_i_r(.c(c), .d(dead >MIN_DEAD ? dead : MIN_DEAD ), .q(dead_i));
wire cnt_rst;
wire [15:0] cnt;
r #(16) cnt_r(.c(c), .rst(cnt_rst), .en(1'b1), .d(cnt+1'b1), .q(cnt));
wire overcurrent = (i_est_valid & (i_est > i_tgt_i)) & (cnt >= min_i);
wire undercurrent = (i_est_valid & (i_est < i_tgt_i)) & (cnt >= min_i);
wire timeout = cnt > max_i;
always @* begin
case (state)
ST_HI:
if (overcurrent | timeout) ctrl = { ST_DEAD_0, 3'b100 };
else ctrl = { ST_HI , 3'b010 };
ST_DEAD_0:
if (cnt > dead_i) ctrl = { ST_LO , 3'b101 };
else ctrl = { ST_DEAD_0, 3'b000 };
ST_LO:
if (undercurrent | timeout) ctrl = { ST_DEAD_1, 3'b100 };
else ctrl = { ST_LO , 3'b001 };
ST_DEAD_1:
if (cnt > dead_i) ctrl = { ST_HI , 3'b110 };
else ctrl = { ST_DEAD_1, 3'b000 };
endcase
end
assign cnt_rst = ctrl[2];
assign hi = INVERT_CURRENT_DIRECTION ? ctrl[0] : ctrl[1];
assign lo = INVERT_CURRENT_DIRECTION ? ctrl[1] : ctrl[0];
endmodule
`ifdef TEST_DTC
module tb();
wire c;
sim_clk #(125) clk_125(c);
reg [15:0] i_est;
reg i_est_valid;
wire mosfet_hi, mosfet_lo;
dtc #(.MIN_PULSE(50),
.MAX_PULSE(200),
.MIN_DEAD(10)) dtc_inst
(.c(c), .i_tgt(16'h4300), .i_est(i_est), .i_est_valid(i_est_valid),
.max_t(16'd0), .min_t(16'd0), .dead(16'd0),
.hi(mosfet_hi), .lo(mosfet_lo));
initial begin
$dumpfile("dtc.lxt");
$dumpvars();
#100000;
$finish();
end
initial begin
i_est = 16'h4000;
forever begin
#100;
if (mosfet_hi)
i_est = i_est - 4;
else if (mosfet_lo)
i_est = i_est + 4;
wait(~c);
wait(c);
i_est_valid = 1;
wait(~c);
wait(c);
i_est_valid = 0;
end
end
endmodule
`endif
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_register_slice:2.1
// IP Revision: 7
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module zc702_m00_regslice_0 (
aclk,
aresetn,
s_axi_awaddr,
s_axi_awprot,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arprot,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [12 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [12 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [12 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [12 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_register_slice_v2_1_7_axi_register_slice #(
.C_FAMILY("zynq"),
.C_AXI_PROTOCOL(2),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(13),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_REG_CONFIG_AW(7),
.C_REG_CONFIG_W(7),
.C_REG_CONFIG_B(7),
.C_REG_CONFIG_AR(7),
.C_REG_CONFIG_R(7)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(1'H0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(8'H00),
.s_axi_awsize(3'H0),
.s_axi_awburst(2'H0),
.s_axi_awlock(1'H0),
.s_axi_awcache(4'H0),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(4'H0),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(1'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(1'H1),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(1'H0),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(8'H00),
.s_axi_arsize(3'H0),
.s_axi_arburst(2'H0),
.s_axi_arlock(1'H0),
.s_axi_arcache(4'H0),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(4'H0),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(1'H0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(1'H0),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_nios2_qsys_0_cpu_oci_test_bench (
// inputs:
dct_buffer,
dct_count,
test_ending,
test_has_ended
)
;
input [ 29: 0] dct_buffer;
input [ 3: 0] dct_count;
input test_ending;
input test_has_ended;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__MUX2I_FUNCTIONAL_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_hdll__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_hdll__mux2i (
Y ,
A0,
A1,
S
);
// Module ports
output Y ;
input A0;
input A1;
input S ;
// Local signals
wire mux_2to1_n0_out_Y;
// Name Output Other arguments
sky130_fd_sc_hdll__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
buf buf0 (Y , mux_2to1_n0_out_Y);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_FUNCTIONAL_V |
// megafunction wizard: %Altera PLL v14.1%
// GENERATION: XML
// pll.v
// Generated using ACDS version 14.1 186 at 2014.12.24.17:11:16
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2014 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="normal" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="5.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_4_V
`define SKY130_FD_SC_HDLL__AND2_4_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_4_V
|
(* %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *)
(* Simply Typed Lambda Calculus with simple Concept Parameters
:: version a
Definitions
Definitions of STLC are based on
Sofware Foundations, v.4
Last Update: Mon, 5 Jun 2017
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% *)
(* ***************************************************************** *)
(** * cpSTLCa Syntax and Semantics Definition
(Simply Typed Lambda Calculus with simple Concept Parameters
:: version a) *)
(* ***************************************************************** *)
(* ***************************************************************** *)
Add LoadPath "../..".
Require Import ConceptParams.BasicPLDefs.Identifier.
Require Import ConceptParams.BasicPLDefs.Maps.
Require Import ConceptParams.BasicPLDefs.Relations.
Require Import ConceptParams.BasicPLDefs.Utils.
Require Import ConceptParams.AuxTactics.LibTactics.
Require Import ConceptParams.AuxTactics.BasicTactics.
Require Import ConceptParams.SetMapLib.List2Set.
Require Import ConceptParams.SetMapLib.ListPair2FMap.
Require Import ConceptParams.GenericModuleLib.SharedDataDefs.
Require Import ConceptParams.GenericModuleLib.SimpleModule.
Require Import ConceptParams.GenericModuleLib.SinglePassModule.
Require Import ConceptParams.GenericModuleLib.SinglePassImplModule.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import Coq.Bool.Bool.
Require Import Coq.omega.Omega.
Require Import Coq.FSets.FMapInterface.
(** We will use list-2-set and list-pair-2-map machinery
** when dealing with modules. *)
(** [List2MSet] module for [id] type of identifiers. *)
Module IdLS' := MList2MSetAVL IdUOT.
Module IdLS := IdLS'.M.
Definition id_set := IdLS.id_set.
(** [ListPair2FMap] module for [id] type of identifiers. *)
Module IdLPM' := MListPair2FMapAVL IdUOTOrig.
Module IdLPM := IdLPM'.M.
Definition id_map := IdLPM.id_map.
Definition set_of_keys {X : Type} (m : id_map X) : id_set :=
IdLS.set_from_list (map fst (IdLPM.IdMap.elements m)).
(** Identifier Data Module *)
Module MId <: IdentifiersBase.
Module IdDT := IdLS'.M.IdDT.
Module IdSET := IdLS'.IdSetAVL.
Module IdLS := IdLS.
Module IdDT' := IdLPM'.M.IdDT.
Module IdMAP := IdLPM'.IdMapAVL.
Module IdLPM := IdLPM.
Definition id := id.
End MId.
(* ################################################################# *)
(** ** Syntax *)
(* ################################################################# *)
(** cpSTLCa — Symply Typed Lambda Calculus
with simple _concept parameters_.
Types are STLC types with the type [C # T],
where [C] is a concept name, [T] is a type.
Terms are STLC terms with the terms:
- [\c#C. t] (concept parametrization) where [c] is a concept parameter;
- [t # M] (model application) where [M] is a model.
- [c.f] (method invocation) where [f] is a field of the concept [c]
- [m.f] (method invocation) where [f] is a field of the model [m]
<<
CSec ::= Concept declarations
| <empty>
| CDef CSec
CDef ::= Concept definition
| concept Id NameDecls endc
MSec ::= Model declarations
| <empty>
| MDef MSec
MDef ::=
| model Id of Id NameDefs endm
NameDecls ::= List of name declarations
| <empty>
| NameDecl ; NameDecls
NameDefs ::= List of name definitions
| <empty>
| NameDef ; NameDefs
NameDecl ::= Name declaration
| Id : T
NameDef ::= Name definition
| Id = t
C metavariable means concept name (Id)
T ::= Types
| Nat
| Bool
| T -> T function
| C # T concept dependency
x metavariable means variable name (Id)
n metavariable means nat constant
c metavariable means concept parameter name (Id)
M metavariable means model name (Id)
t ::= Terms
| x variable
| \x:T.t function
| t t function application
| \c#C.t concept parameter
| t # M model application
| c.f concept element invocation
| true
| false
| if t then t else t
| n
| succ t
| pred t
| plus t t
| minus t t
| mult t t
| eqnat t t nat equality
| le t t nat less-than
| let x = t in t let binding
>>
_Program_ consists of concept and model declarations,
and a term.
<<
p ::=
| CSec MSec t
>>
*)
(* ----------------------------------------------------------------- *)
(** **** Types *)
(* ----------------------------------------------------------------- *)
Inductive ty : Type :=
| TBool : ty
| TNat : ty
| TArrow : ty -> ty -> ty (* T1 -> T2 *)
| TConceptPrm : id -> ty -> ty (* C # T *)
.
(* ----------------------------------------------------------------- *)
(** **** Terms *)
(* ----------------------------------------------------------------- *)
Inductive tm : Type :=
| tvar : id -> tm (* x *)
| tapp : tm -> tm -> tm (* t1 t2 *)
| tabs : id -> ty -> tm -> tm (* \x:T11.t12 *)
| tmapp : tm -> id -> tm (* t1 # M *)
| tcabs : id -> id -> tm -> tm (* \c#C.t1 *)
| tcinvk : id -> id -> tm (* c.f *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm (* if t1 then t2 else t3 *)
| tnat : nat -> tm (* n *)
| tsucc : tm -> tm (* succ t1 *)
| tpred : tm -> tm (* pred t1 *)
| tplus : tm -> tm -> tm (* plus t1 t2 *)
| tminus : tm -> tm -> tm (* minus t1 t2 *)
| tmult : tm -> tm -> tm (* mult t1 t2 *)
| teqnat : tm -> tm -> tm (* eqnat t1 t2 *)
| tlenat : tm -> tm -> tm (* lenat t1 t2 *)
| tlet : id -> tm -> tm -> tm (* let x = t1 in t2 *)
.
(* ----------------------------------------------------------------- *)
(** **** Concepts *)
(* ----------------------------------------------------------------- *)
(** Name declaration *)
Inductive namedecl : Type :=
| nm_decl : id -> ty -> namedecl (* f : T *)
.
(** Auxiliary function to transform name declaration into pair *)
Definition namedecl_to_pair (nmdecl : namedecl) : (id * ty) :=
match nmdecl with
nm_decl fname ftype => (fname, ftype)
end.
(** List of name declarations *)
Definition namedecl_list : Type := list namedecl.
Hint Unfold namedecl_list.
(** Concept definition *)
Inductive conceptdef : Type :=
| cpt_def : id -> namedecl_list -> conceptdef (* concept Id NameDefs endc *)
.
(** Auxiliary function to transform concept definition into pair *)
Definition conceptdef_to_pair (C : conceptdef) : (id * namedecl_list) :=
match C with
cpt_def Cname Cbody => (Cname, Cbody)
end.
Definition conceptdef__get_name (C : conceptdef) : id :=
match C with cpt_def nm nmdecls => nm end.
(** Concept declarations Section *)
Definition conceptsec : Type := list conceptdef.
Hint Unfold conceptsec.
(* ----------------------------------------------------------------- *)
(** **** Models *)
(* ----------------------------------------------------------------- *)
(** Name definition *)
Inductive namedef : Type :=
| nm_def : id -> tm -> namedef (* f = t *)
.
(** Auxiliary function to transform name defintion into pair *)
Definition namedef_to_pair (nmdef : namedef) : (id * tm) :=
match nmdef with
nm_def fname fdef => (fname, fdef)
end.
(** List of name definitions *)
Definition namedef_list : Type := list namedef.
Hint Unfold namedef_list.
(** Model definition *)
Inductive modeldef : Type :=
(* model Id of Id NameDefs endm *)
| mdl_def : id -> id -> namedef_list -> modeldef
.
Definition modeldef__get_name (M : modeldef) : id :=
match M with mdl_def nm C nmdefs => nm end.
(** Model declarations Section *)
Definition modelsec : Type := list modeldef.
Hint Unfold modelsec.
(* ----------------------------------------------------------------- *)
(** **** Program *)
(* ----------------------------------------------------------------- *)
Inductive program : Type :=
| tprog : conceptsec -> modelsec -> tm -> program
.
(** There are examples of concepts and programs in [cpSTLCa_Examples.v]. *)
(* ################################################################# *)
(** ** Typing *)
(* ################################################################# *)
(** To typecheck terms with concept parameters, we need
information about concepts and models.
So we need a kind of a _symbol table_. It is defined later.
We start with defining types of concepts and models.
*)
(** [tycontext] is a typing context: a map from ids to types. *)
Definition tycontext := partial_map ty.
Hint Unfold tycontext.
(** Concept type [cty] contains information about members' types.
To check welldefinedness of a concept, it is enough to use
[tycontext] (functional map from ids to types) to store
information about names and types of concept members.
But we also need to check welldefinedness of models. To do so,
we have to check that a model defines all concept members.
Thus, there must be a way to extract information about all
concept members from [cty].
Therefore, we will use AVL Map from ids to types to express
information about concept members.
*)
(** AVL map from [id] to [ty]. *)
Definition id_ty_map := IdLPM.id_map ty.
Hint Unfold id_ty_map.
(** Concept type (AVL-map from ids into types) *)
Inductive cty : Type := CTdef : id_ty_map -> cty.
(** Lookup of types in a map *)
Definition find_ty := @IdLPM.IdMap.find ty.
Hint Unfold find_ty.
(** Models are always defined for some concepts. Therefore,
a list of members and their types must be the same as in
the corresponding concept.
For simplicity, we do not allow any extra members in the model.
The only thing we need to know about a model to typecheck
model application, is its concept.
But to implement terms reduction, we have to provide
information about members' implementation.
Thus, model type [mty] will contain both concept name
and a map from ids to terms. *)
(** AVL map from [id] to [tm]. *)
Definition id_tm_map := IdLPM.id_map tm.
Hint Unfold id_tm_map.
(** Model type *)
Inductive mty : Type := MTdef : id -> id_tm_map -> mty.
(** Lookup of terms in a map *)
Definition find_tm := @IdLPM.IdMap.find tm.
Hint Unfold find_tm.
(** For further checks we need a _symbol table_ to store
information about concepts and models. We can either
store both in one table, or have separate tables
for concepts and models.
For simplicity, we choose the second option. *)
(** Concept symbol table is a map from concept names
to concept types [Ci -> CTi]. *)
Definition cptcontext : Type := IdLPM.id_map cty.
Definition cstempty : cptcontext := IdLPM.IdMap.empty cty.
(** Model symbol table is a map from model names
to model types [Mi -> MTi]. *)
Definition mdlcontext : Type := IdLPM.id_map mty.
Definition mstempty : mdlcontext := @IdLPM.IdMap.empty mty.
(* ================================================================= *)
(** *** Checking Types Validity *)
(* ================================================================= *)
(* ----------------------------------------------------------------- *)
(** **** Checking Concept Definitions *)
(* ----------------------------------------------------------------- *)
(** Concept definition is Ok if names of concept elements are
distinct, and types of elements are valid.
The only problem in types is with concept dependency [C # T]:
if C is undefined concept name, type is not valid.
So to check types validity, we need symbol table already.
*)
(** Now let's define a property "type is valid".
This property must be checked againts concrete symbol table.
*)
Definition concept_defined (st : cptcontext) (nm : id) : Prop :=
IdLPM.IdMap.find nm st <> None.
Inductive type_valid (st : cptcontext) : ty -> Prop :=
| type_valid_nat : type_valid st TNat
| type_valid_bool : type_valid st TBool
| type_valid_arrow : forall T1 T2,
type_valid st T1 ->
type_valid st T2 ->
type_valid st (TArrow T1 T2)
| type_valid_cpt : forall C T,
concept_defined st C ->
type_valid st T ->
type_valid st (TConceptPrm C T)
.
Hint Constructors type_valid.
(* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! *)
(** This part is using GenericModulesLib *)
(* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! *)
Module IdModuleBase <: ModuleBase.
Module MId := MId.
Definition id := MId.id.
Definition id_set := MId.IdLS.id_set.
Definition id_map := MId.IdLPM.id_map.
End IdModuleBase.
(** Here we are going to use SimpleModule generic module
to check concept definitions. *)
Module MCptMem_DataC <: DataC.
(** Type of Data *)
Definition t := ty.
(** Type of Context *)
Definition ctx := cptcontext.
End MCptMem_DataC.
Module MCptMem_DataCOkDef <: DataCOkDef MCptMem_DataC.
Definition is_ok := type_valid.
End MCptMem_DataCOkDef.
Module MCptMem_SimpleMBase <: SimpleModuleBase.
Include IdModuleBase.
Module MD := MCptMem_DataC.
End MCptMem_SimpleMBase.
(** SimpleModule definitions for checking concept members. *)
Module MCptMem_Defs := SimpleModuleDefs MCptMem_SimpleMBase MCptMem_DataCOkDef.
(** Now we are ready to define a property "concept is well defined" *)
Definition concept_welldefined (st : cptcontext) (C : conceptdef) : Prop :=
match C with
cpt_def cname cbody =>
let pnds := map namedecl_to_pair cbody in
MCptMem_Defs.module_ok st pnds
end.
Hint Unfold concept_welldefined.
(** We have a symbol table for concepts, concept types, but
we have not defined yet a relation on concept definitions and
concept types. *)
Definition concept_has_type (cst : cptcontext) (C : conceptdef) (CT : cty) : Prop :=
(** concept def must be well-defined *)
concept_welldefined cst C
/\ match CT with CTdef cnmtys =>
match C with cpt_def cname cbody =>
let pnds := map namedecl_to_pair cbody in
(** and the map [cnmtys] has to be equal to the AST [cbody] *)
IdLPM.eq_list_map pnds cnmtys
end end.
(** Concept section (list of concept definitions) must also be well-formed.
As further concept definitions can refer to previously defined ones,
we need SinglePass Module Machinery.
*)
Module MCptDef_DataLC <: DataLC.
(** One concept definition is a member in this case. *)
Definition t := conceptdef.
(** We have no global context, only local. *)
Definition ctx := unit.
(** Local context contains information about previously defined
concepts. *)
Definition ctxloc := cptcontext.
End MCptDef_DataLC.
Module MCptDef_DataLCOkDef <: DataLCOkDef MCptDef_DataLC.
Definition is_ok (c : unit) (cl : cptcontext) (cpt : conceptdef) : Prop
:= concept_welldefined cl cpt.
End MCptDef_DataLCOkDef.
Module MCptDef_SinglePassMBase <: SinglePassModuleBase.
Include IdModuleBase.
Module MD := MCptDef_DataLC.
(** Initial local context *)
Definition ctxl_init : cptcontext := cstempty.
(** Update local context *)
Definition upd_ctxloc (cl : cptcontext) (c : unit)
(nm : id) (cpt : conceptdef) : cptcontext :=
match cpt with
cpt_def Cname Cbody =>
let nmtys := map namedecl_to_pair Cbody in
(* convert declarations into finite map,
and add this map into the context *)
IdLPM.IdMap.add Cname (CTdef (IdLPM.map_from_list nmtys)) cl
end.
End MCptDef_SinglePassMBase.
Module MCptDef_SinglePassMDefs :=
SinglePassModuleDefs MCptDef_SinglePassMBase MCptDef_DataLCOkDef.
Definition conceptdef_pair_with_id (C : conceptdef) : id * conceptdef :=
match C with cpt_def Cname _ => (Cname, C) end.
(** What it means for a concept section to be well-defined. *)
Definition conceptsec_welldefined (cpts : conceptsec) : Prop :=
let pcpts := map conceptdef_pair_with_id cpts in
MCptDef_SinglePassMDefs.module_ok tt pcpts.
Definition namedecl_list_to_cty (decls : namedecl_list) : cty :=
let nmtys := map namedecl_to_pair decls in
CTdef (IdLPM.map_from_list nmtys).
Definition conceptdef_to_pair_id_cty (C : conceptdef) : id * cty :=
match C with
cpt_def Cname Cbody => (Cname, namedecl_list_to_cty Cbody)
end.
(** What it means for a concept context to be well-defined.
** [cst] is well-defined if exists a well-defined AST
** equal to the concept context.*)
Definition cptcontext_welldefined (cst : cptcontext) : Prop :=
exists (cpts : conceptsec),
conceptsec_welldefined cpts
/\ let pctys := map conceptdef_to_pair_id_cty cpts in
IdLPM.IdMap.Equal cst (IdLPM.map_from_list pctys).
(* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! *)
(** At this point we cannot do more on contexts. To check models,
we have to be able to typecheck terms (function definitions).
But terms may conist of model applications.
*)
(* ================================================================= *)
(** *** Typing of Terms *)
(* ================================================================= *)
(** To typecheck terms we need:
- context [Gamma], which (in contrast to STLC) contains not only
variables, but also concept variables;
- concept symbol table [CTable];
- model symbol table [MTable].
*)
(** Informal typing rules are listed below.
We can read the five-place relation
[CTable * MTable ; Gamma |- t \in T] as:
"to the term [t] we can assign the type [T],
if types of free variables of [t] are specified in [Gamma],
free concept variables of [t] are specified in [Gamma],
context types are specified in [CTable],
model types are specified in [MTable]."
[dom( * )] is a domain of a map (map keys -- ids),
[range( * )] is a range of a map (map values -- types).
Gamma \has x:T
-------------------------------- (T_Var)
CTable * MTable ; Gamma |- x : T
CTable * MTable ; Gamma |- t1 : T11->T12
CTable * MTable ; Gamma |- t2 : T11
---------------------------------------- (T_App)
CTable * MTable ; Gamma |- t1 t2 : T12
CTable * MTable ; (Gamma , x:T11) |- t12 : T12
------------------------------------------------ (T_Abs)
CTable * MTable ; Gamma |- \x:T11.t12 : T11->T12
- MTable contains info about model M
- Model M implements concept C
(MTable(M) = ... of C ...)
M \in dom(MTable)
MTable(M) = ... of C ...
CTable * MTable ; Gamma |- t1 : (C # T1)
---------------------------------------- (T_MApp)
CTable * MTable ; Gamma |- (t1 # M) : T1
C \in dom(CTable)
CTable * MTable ; (Gamma , c#C) |- t1 : T1
-------------------------------------------------- (T_CAbs)
CTable * MTable ; Gamma |- \c#C.t1 : (C # T1)
- CTable contains info about concept C;
- C contains member f and its type is TF
(CTable(C) = ... f : TF ... )
Gamma \has c#C
C \in dom(CTable)
CTable(C) = ... f : TF ...
----------------------------------- (T_CInvk)
CTable * MTable ; Gamma |- c.f : TF
M#C \notin Gamma
M \in dom(MTable)
MTable(M) = ... of C ...
C \in dom(CTable)
CTable(C) = ... f : TF ...
----------------------------------- (T_MInvk)
CTable * MTable ; Gamma |- M.f : TF
------------------------------------ (T_True)
CTable * MTable ; Gamma |- true : Bool
------------------------------------ (T_False)
CTable * MTable ; Gamma |- false : Bool
CTable * MTable ; Gamma |- t1 : Bool
CTable * MTable ; Gamma |- t2 : T
CTable * MTable ; Gamma |- t3 : T
--------------------------------------------------- (T_If)
CTable * MTable ; Gamma |- if t1 then t2 else t3 : T
------------------------------------- (T_Nat)
CTable * MTable ; Gamma |- tnat n : Nat
CTable * MTable ; Gamma |- t1 : Nat
------------------------------------------ (T_Succ)
CTable * MTable ; Gamma |- succ t1 : Nat
CTable * MTable ; Gamma |- t1 : Nat
------------------------------------------ (T_Pred)
CTable * MTable ; Gamma |- pred t1 : Nat
CTable * MTable ; Gamma |- t1 : Nat
CTable * MTable ; Gamma |- t2 : Nat
---------------------------------------- (T_Plus)
CTable * MTable ; Gamma |- t1 + t2 : Nat
CTable * MTable ; Gamma |- t1 : Nat
CTable * MTable ; Gamma |- t2 : Nat
---------------------------------------- (T_Minus)
CTable * MTable ; Gamma |- t1 - t2 : Nat
CTable * MTable ; Gamma |- t1 : Nat
CTable * MTable ; Gamma |- t2 : Nat
--------------------------------------- (T_Mult)
CTable * MTable ; Gamma |- t1 * t2 : Nat
CTable * MTable ; Gamma |- t1 : Nat
CTable * MTable ; Gamma |- t2 : Nat
------------------------------------------ (T_EqNat)
CTable * MTable ; Gamma |- t1 = t2 : Bool
CTable * MTable ; Gamma |- t1 : Nat
CTable * MTable ; Gamma |- t2 : Nat
------------------------------------------ (T_LeNat)
CTable * MTable ; Gamma |- t1 <= t2 : Bool
CTable * MTable ; Gamma |- t1 : T1
CTable * MTable ; (Gamma , x:T1) |- t2 : T2
---------------------------------------------- (T_Let)
CTable * MTable ; Gamma |- let x=t1 in t2 : T2
*)
(** In SLTC Gamma consists of only variable types,
but now it can also have information about concept parameters.
*)
Inductive ctxvarty : Type :=
(* type of term variable [x : T] -- normal type *)
| tmtype : ty -> ctxvarty
(* type of concept parameter [c # C] -- concept name *)
| cpttype : id -> ctxvarty
.
Definition context : Type := partial_map ctxvarty.
Definition ctxempty : context := @empty ctxvarty.
(** Aux function for typing relation *)
Definition concept_fun_member (CTable : cptcontext)
(C : id) (f : id) (TF : ty) : Prop :=
match IdLPM.IdMap.find C CTable with
| None => False
| Some (CTdef fundefs) => find_ty f fundefs = Some TF
end.
Reserved Notation "CTable '$' MTable ';' Gamma '|-' t '\in' T" (at level 50).
(** Here is our typing relation for cpSTLCa terms. *)
Inductive has_type : cptcontext -> mdlcontext -> context -> tm -> ty -> Prop :=
| T_Var : forall CTable MTable Gamma x T,
Gamma x = Some (tmtype T) ->
CTable $ MTable ; Gamma |- tvar x \in T
| T_App : forall CTable MTable Gamma t1 t2 T11 T12,
CTable $ MTable ; Gamma |- t1 \in (TArrow T11 T12) ->
CTable $ MTable ; Gamma |- t2 \in T11 ->
CTable $ MTable ; Gamma |- tapp t1 t2 \in T12
| T_Abs : forall CTable MTable Gamma x t12 T11 T12,
CTable $ MTable ; (update Gamma x (tmtype T11)) |- t12 \in T12 ->
CTable $ MTable ; Gamma |- tabs x T11 t12 \in (TArrow T11 T12)
| T_MApp : forall CTable MTable Gamma t1 M C Mbody T1,
IdLPM.IdMap.find M MTable = Some (MTdef C Mbody) ->
CTable $ MTable ; Gamma |- t1 \in TConceptPrm C T1 ->
CTable $ MTable ; Gamma |- tmapp t1 M \in T1
| T_CAbs : forall CTable MTable Gamma c t1 C Cbody T1,
IdLPM.IdMap.find C CTable = Some (CTdef Cbody) ->
CTable $ MTable ; (update Gamma c (cpttype C)) |- t1 \in T1 ->
CTable $ MTable ; Gamma |- tcabs c C t1 \in TConceptPrm C T1
| T_CInvk : forall CTable MTable Gamma c f C TF,
Gamma c = Some (cpttype C) ->
concept_fun_member CTable C f TF ->
CTable $ MTable ; Gamma |- tcinvk c f \in TF
| T_MInvk : forall CTable MTable Gamma M C Mbody f TF,
(~ exists MC, Gamma M = Some (cpttype MC)) ->
IdLPM.IdMap.find M MTable = Some (MTdef C Mbody) ->
concept_fun_member CTable C f TF ->
CTable $ MTable ; Gamma |- tcinvk M f \in TF
| T_True : forall CTable MTable Gamma,
CTable $ MTable ; Gamma |- ttrue \in TBool
| T_False : forall CTable MTable Gamma,
CTable $ MTable ; Gamma |- tfalse \in TBool
| T_If : forall CTable MTable Gamma t1 t2 t3 T,
CTable $ MTable ; Gamma |- t1 \in TBool ->
CTable $ MTable ; Gamma |- t2 \in T ->
CTable $ MTable ; Gamma |- t3 \in T ->
CTable $ MTable ; Gamma |- tif t1 t2 t3 \in T
| T_Nat : forall CTable MTable Gamma n,
CTable $ MTable ; Gamma |- tnat n \in TNat
| T_Succ : forall CTable MTable Gamma t1,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- tsucc t1 \in TNat
| T_Pred : forall CTable MTable Gamma t1,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- tpred t1 \in TNat
| T_Plus : forall CTable MTable Gamma t1 t2,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- t2 \in TNat ->
CTable $ MTable ; Gamma |- tplus t1 t2 \in TNat
| T_Minus : forall CTable MTable Gamma t1 t2,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- t2 \in TNat ->
CTable $ MTable ; Gamma |- tminus t1 t2 \in TNat
| T_Mult : forall CTable MTable Gamma t1 t2,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- t2 \in TNat ->
CTable $ MTable ; Gamma |- tmult t1 t2 \in TNat
| T_EqNat : forall CTable MTable Gamma t1 t2,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- t2 \in TNat ->
CTable $ MTable ; Gamma |- teqnat t1 t2 \in TBool
| T_LeNat : forall CTable MTable Gamma t1 t2,
CTable $ MTable ; Gamma |- t1 \in TNat ->
CTable $ MTable ; Gamma |- t2 \in TNat ->
CTable $ MTable ; Gamma |- tlenat t1 t2 \in TBool
| T_Let : forall CTable MTable Gamma x t1 t2 T1 T2,
CTable $ MTable ; Gamma |- t1 \in T1 ->
CTable $ MTable ; (update Gamma x (tmtype T1)) |- t2 \in T2 ->
CTable $ MTable ; Gamma |- tlet x t1 t2 \in T2
where "CTable '$' MTable ';' Gamma '|-' t '\in' T"
:= (has_type CTable MTable Gamma t T) : stlca_scope.
Hint Constructors has_type.
(* ----------------------------------------------------------------- *)
(** **** Checking Model Definitions *)
(* ----------------------------------------------------------------- *)
(** Model definition is Ok if:
- concept name is defined;
- all concept members are defined in a model;
- model member types coincide with concept member types.
*)
Definition model_defined (st : mdlcontext) (nm : id) : Prop :=
IdLPM.IdMap.find nm st <> None.
(** [model_member_valid] is a proposition stating that the given
model member [nd] (name definition, [f := t]) is valid against
the concept [cpt] (name declarations, [f : T])
and previously defined members of the model.
*)
(** UPD
As we found out when trying to prove soundness,
bound variables in terms should not have names
that interfere with model names.
As we check model members before we "know" all the models,
there is not enough information about models names
in the context yet.
So we have to:
* provide information on all forbidden (model) names;
* check that bound variables do not use these names.
*)
(** Returns set of names of all bound concept variables used in the term. *)
Fixpoint bound_cvars (t : tm) : id_set :=
match t with
(* BCV(x) = {} *)
| tvar x => IdLS.IdSet.empty
(* BCV(t1 t2) = BCV(t1) \union BCV(t2) *)
| tapp t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
(* BCV(\x:T.t) = BCV(t) *)
| tabs x T t => bound_cvars t
(* BCV(t # M) = BCV(t) *)
| tmapp t M => bound_cvars t
(* BCV(\c#C.t) = BCV(t) \union {c} *)
| tcabs c C t => IdLS.IdSet.add c (bound_cvars t)
(* BCV(c.f) = {} *)
| tcinvk c f => IdLS.IdSet.empty
(* BCV(true) = {} *)
| ttrue => IdLS.IdSet.empty
(* BCV(false) = {} *)
| tfalse => IdLS.IdSet.empty
(* BCV(if t1 then t2 else t3) = BCV(t1) \union BCV(t2) \union BCV(t3) *)
| tif t1 t2 t3 => IdLS.IdSet.union
(IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2))
(bound_cvars t3)
(* BCV(n) = {} *)
| tnat n => IdLS.IdSet.empty
(* BCV(succ t) = BCV(t) *)
| tsucc t => bound_cvars t
(* BCV(pred t) = BCV(t) *)
| tpred t => bound_cvars t
(* BCV(plus t1 t2) = BCV(t1) \union BCV(t2) *)
| tplus t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
(* BCV(minus t1 t2) = BCV(t1) \union BCV(t2) *)
| tminus t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
(* BCV(mult t1 t2) = BCV(t1) \union BCV(t2) *)
| tmult t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
(* BCV(eqnat t1 t2) = BCV(t1) \union BCV(t2) *)
| teqnat t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
(* BCV(lenat t1 t2) = BCV(t1) \union BCV(t2) *)
| tlenat t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
(* BCV(let x=t1 in t2) = BCV(t1) \union BCV(t2) \union {x} *)
| tlet x t1 t2 => IdLS.IdSet.union (bound_cvars t1) (bound_cvars t2)
end.
(*
(** Returns set of names of all bound variables used in the term. *)
Fixpoint bound_vars (t : tm) : id_set :=
match t with
(* BV(x) = {} *)
| tvar x => IdLS.IdSet.empty
(* BV(t1 t2) = BV(t1) \union BV(t2) *)
| tapp t1 t2 => IdLS.IdSet.union (bound_vars t1) (bound_vars t2)
(* BV(\x:T.t) = BV(t) \union {x} *)
| tabs x T t => IdLS.IdSet.union (IdLS.IdSet.singleton x) (bound_vars t)
(* BV(t # M) = BV(t) *)
| tmapp t M => bound_vars t
(* BV(\c#C.t) = BV(t) \union {c} *)
| tcabs c C t => IdLS.IdSet.union (IdLS.IdSet.singleton c) (bound_vars t)
(* BV(c.f) = {} *)
| tcinvk c f => IdLS.IdSet.empty
(* BV(true) = {} *)
| ttrue => IdLS.IdSet.empty
(* BV(false) = {} *)
| tfalse => IdLS.IdSet.empty
(* BV(if t1 then t2 else t3) = BV(t1) \union BV(t2) \union BV(t3) *)
| tif t1 t2 t3 => IdLS.IdSet.union
(IdLS.IdSet.union (bound_vars t1) (bound_vars t2))
(bound_vars t3)
(* BV(n) = {} *)
| tnat n => IdLS.IdSet.empty
(* BV(succ t) = BV(t) *)
| tsucc t => bound_vars t
(* BV(pred t) = BV(t) *)
| tpred t => bound_vars t
(* BV(plus t1 t2) = BV(t1) \union BV(t2) *)
| tplus t1 t2 => IdLS.IdSet.union (bound_vars t1) (bound_vars t2)
(* BV(minus t1 t2) = BV(t1) \union BV(t2) *)
| tminus t1 t2 => IdLS.IdSet.union (bound_vars t1) (bound_vars t2)
(* BV(mult t1 t2) = BV(t1) \union BV(t2) *)
| tmult t1 t2 => IdLS.IdSet.union (bound_vars t1) (bound_vars t2)
(* BV(eqnat t1 t2) = BV(t1) \union BV(t2) *)
| teqnat t1 t2 => IdLS.IdSet.union (bound_vars t1) (bound_vars t2)
(* BV(lenat t1 t2) = BV(t1) \union BV(t2) *)
| tlenat t1 t2 => IdLS.IdSet.union (bound_vars t1) (bound_vars t2)
(* BV(let x=t1 in t2) = BV(t1) \union BV(t2) \union {x} *)
| tlet x t1 t2 => IdLS.IdSet.union
(IdLS.IdSet.singleton x)
(IdLS.IdSet.union (bound_vars t1) (bound_vars t2))
end.
*)
(** There are no bound concept variables in [t]
** with names from [badnames]. *)
Definition no_bound_cvar_names_in_term
(badnames : id_set) (t : tm) : Prop :=
forall (x : id),
IdLS.IdSet.In x badnames ->
~ IdLS.IdSet.In x (bound_cvars t).
(*
(** There are no bound variables in [t] with names from [badnames]. *)
Definition no_bound_var_names_in_term
(badnames : id_set) (t : tm) : Prop :=
forall (x : id),
IdLS.IdSet.In x badnames ->
~ IdLS.IdSet.In x (bound_vars t).
*)
Definition model_member_valid (CTbl : cptcontext) (MTbl : mdlcontext)
(mdlnames : id_set) (cpt : id_ty_map) (Gamma : context)
(nm : id) (t : tm) : Prop :=
exists (T : ty),
(** there is [nm : T] in a concept *)
find_ty nm cpt = Some T
(** no model names from [mdlnames] are used for names
of bound concept vars *)
/\ no_bound_cvar_names_in_term mdlnames t
(** and [T] is a type of [t], that is
[CTbl $ MTbl ; Gamma |- t : T] *)
/\ has_type CTbl MTbl Gamma t T.
(* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! *)
(** This part is using GenericModulesLib *)
(* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! *)
(** Here we are going to use [SinglePassImplModule] generic module. *)
Module MMdlMem_DataLCI <: DataLCI.
(** Type of Data -- term *)
Definition t := tm.
(** Type of Context needed for checking WD of terms.
We need both concept and model table,
and also forbidden model names. *)
Definition ctx := (cptcontext * mdlcontext * id_set) % type.
(** Type of Local Context which is needed for checking WD of terms
(here we need types of previously defined members). *)
Definition ctxloc := context.
(** Type of Concept representation in symbol table *)
Definition intrfs := id_ty_map.
End MMdlMem_DataLCI.
Module MMdlMem_DataLCIOkDef <: DataLCIOkDef MId MMdlMem_DataLCI.
(* Element [t] must be ok with respect
to global [ctx] and local [ctxloc] contexts. *)
Definition is_ok (cm_nms : cptcontext * mdlcontext * id_set)
(cpt : id_ty_map) (Gamma : context)
(nm : id) (t : tm) : Prop :=
let (cm, mdlnms) := cm_nms in
let (c, m) := cm in
model_member_valid c m mdlnms cpt Gamma nm t.
End MMdlMem_DataLCIOkDef.
Module MMdlMem_SinglePassImplMBase <: SinglePassImplModuleBase.
Include IdModuleBase.
Module MD := MMdlMem_DataLCI.
(** Initial local context (Gamma) *)
Definition ctxl_init := ctxempty.
(** Update local context *)
Definition upd_ctxloc (Gamma : context)
(cm_nms : cptcontext * mdlcontext * id_set)
(cpt : id_ty_map) (nm : id) (t : tm) : context :=
match find_ty nm cpt with
| Some tp => update Gamma nm (tmtype tp)
| None => Gamma
end.
(** Members which have to be defined by an interface *)
Definition members_to_define (cpt : id_ty_map) : list id
:= map fst (IdLPM.IdMap.elements cpt).
End MMdlMem_SinglePassImplMBase.
Module MMdlMem_SinglePassImplMDefs :=
SinglePassImplModuleDefs MMdlMem_SinglePassImplMBase MMdlMem_DataLCIOkDef.
(** Now we are ready to formally define what it means for a model
to be well-defined. *)
Definition model_welldefined (CTbl : cptcontext) (MTbl : mdlcontext)
(mdlnames : id_set) (M : modeldef) : Prop :=
match M with
mdl_def Mname C Mbody =>
let decls := map namedef_to_pair Mbody in
(** concept [C] is defined in symbol table,
and model is ok with respect to this concept *)
exists (fnmtys : id_ty_map),
IdLPM.IdMap.find C CTbl = Some (CTdef fnmtys)
/\ MMdlMem_SinglePassImplMDefs.module_ok (CTbl, MTbl, mdlnames) fnmtys decls
end.
(** And we also need typing relation for models. *)
Definition model_has_type (CTbl : cptcontext) (MTbl : mdlcontext)
(mdlnames : id_set) (M : modeldef) (MT : mty) : Prop :=
(** model def must be well-defined *)
model_welldefined CTbl MTbl mdlnames M
/\ match MT with MTdef _ mnmtms =>
match M with mdl_def _ _ Mbody =>
let pnds := map namedef_to_pair Mbody in
(** and the map [mnmtms] has to be equal to the AST [mbody] *)
IdLPM.eq_list_map pnds mnmtms
end end.
Hint Unfold model_welldefined.
(** _Note!_ No evaluation is applied to model members (terms).
Thus, model members have to be exactly reflected in the model type
that has exactly the same syntactic structure. *)
(* ----------------------------------------------------------------- *)
(** **** Checking Programs *)
(* ----------------------------------------------------------------- *)
(** Now we can write down what it means for the whole program
to be well-defined. *)
(* Inductive program : Type := tprog : conceptsec -> modelsec -> tm -> program *)
(** We can again use Single-Pass Modules to define well-definedness
of model section. *)
Module MMdlDef_DataLC <: DataLC.
(** One model definition is a member of models section. *)
Definition t := modeldef.
(** Global context in this case is concept symbol table
plus information about forbidden bound vars' names. *)
Definition ctx := (cptcontext * id_set) % type.
(** Local context contains information about previously defined
models. *)
Definition ctxloc := mdlcontext.
End MMdlDef_DataLC.
Module MMdlDef_DataLCOkDef <: DataLCOkDef MMdlDef_DataLC.
Definition is_ok (c_mdlnms : cptcontext * id_set)
(cl : mdlcontext) (mdl : modeldef) : Prop :=
let (c, mdlnms) := c_mdlnms in
model_welldefined c cl mdlnms mdl.
End MMdlDef_DataLCOkDef.
Module MMdlDef_SinglePassMBase <: SinglePassModuleBase.
Include IdModuleBase.
Module MD := MMdlDef_DataLC.
(** Initial local context *)
Definition ctxl_init : mdlcontext := mstempty.
(** Update local context *)
Definition upd_ctxloc (cl : mdlcontext) (c_mdlnms : cptcontext * id_set)
(nm : id) (mdl : modeldef) : mdlcontext :=
match mdl with
mdl_def Mname C Mbody =>
let nmtms := map namedef_to_pair Mbody in
(* convert declarations into finite map,
and add this map into the context *)
IdLPM.IdMap.add Mname (MTdef C (IdLPM.map_from_list nmtms)) cl
end.
End MMdlDef_SinglePassMBase.
Module MMdlDef_SinglePassMDefs :=
SinglePassModuleDefs MMdlDef_SinglePassMBase MMdlDef_DataLCOkDef.
Definition modeldef_pair_with_id (M : modeldef) : id * modeldef :=
match M with mdl_def Mname _ _ => (Mname, M) end.
(** What it means for a model section to be well-defined. *)
Definition modelsec_welldefined (CTbl : cptcontext) (mdls : modelsec)
(mdlnames : id_set) : Prop :=
let pmdls := map modeldef_pair_with_id mdls in
MMdlDef_SinglePassMDefs.module_ok (CTbl, mdlnames) pmdls.
Definition namedef_list_to_mty (C : id) (defs : namedef_list) : mty :=
let nmtms := map namedef_to_pair defs in
MTdef C (IdLPM.map_from_list nmtms).
Definition modeldef_to_pair_id_mty (M : modeldef) : id * mty :=
match M with
mdl_def Mname C Mbody => (Mname, namedef_list_to_mty C Mbody)
end.
Definition model_names (MTbl : mdlcontext) : id_set :=
IdLS.set_from_list (map fst (IdLPM.IdMap.elements MTbl)).
(** What it means for a model context to be well-defined
** in the given concept context.
** [mst] is well-defined if exists a well-defined AST
** equal to the model context.*)
Definition mdlcontext_welldefined
(CTbl : cptcontext) (MTbl : mdlcontext) : Prop :=
let mdlnames := model_names MTbl in
exists (mdls : modelsec),
(** exists well-defined model section *)
modelsec_welldefined CTbl mdls mdlnames
(** such that model context corresponds to this section *)
/\ let pmtys := map modeldef_to_pair_id_mty mdls in
IdLPM.IdMap.Equal MTbl (IdLPM.map_from_list pmtys).
(*
(** Model section (list of model definitions) has to be well-formed.
That is there is a symbol table of models such that
- all models in the section are well-defined against it;
- symbol table contains appropriate concept types. *)
Definition modelsec_welldefined
(mdlsec : modelsec) (cst : cptcontext) (mst : mdlcontext) : Prop :=
Forall (fun (M : modeldef) =>
(* model is welldefined *)
(model_welldefined cst mst M)
/\ (exists (MT : mty),
(* model symb. table contains info about type of M *)
IdLPM.IdMap.find (modeldef__get_name M) mst = Some MT
(* and M indeed has this type *)
/\ model_has_type cst mst M MT)
) mdlsec.
*)
(** Finally, we can define what it means for the whole _program_
to be well-typed (correct). *)
(*
Definition program_has_type (cst : cptcontext) (mst : mdlcontext)
(prg : program) (T : ty) : Prop :=
match prg with tprog cptsec mdlsec t =>
(** All concepts are well defined *)
conceptsec_welldefined cptsec
(** All models are well defined *)
/\ modelsec_welldefined mdlsec cst mst
(** Term is well typed *)
/\ has_type cst mst ctxempty t T
end.
*)
(** Now we can define a typing judgement where all
components are well-defined. *)
Definition has_type_WD
(cst : cptcontext) (mst : mdlcontext)
(Gamma : context) (t : tm) (T : ty) : Prop :=
cptcontext_welldefined cst
/\ mdlcontext_welldefined cst mst
/\ has_type cst mst Gamma t T.
Notation "CTable '$' MTable ';' Gamma '||-' t '\in' T"
:= (has_type_WD CTable MTable Gamma t T) (at level 50) : stlca_scope.
(* ################################################################# *)
(** ** Operational Semantics *)
(* ################################################################# *)
(* ================================================================= *)
(** *** Values *)
(* ================================================================= *)
(** We start with defining the values of our language. *)
(** There are several "standard" categories of values:
- boolean constants [true] and [false];
- numbers [nat n];
- abstractions (functions) [\x:T.t].
But in cpSTLCa there is one more kind of abstraction:
concept parameters. We consider it as a value too.
*)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_cabs : forall c C t,
value (tcabs c C t)
| v_true :
value ttrue
| v_false :
value tfalse
| v_nat : forall n,
value (tnat n).
Hint Constructors value.
(* ================================================================= *)
(** *** Substitution *)
(* ================================================================= *)
(** Apparently, to evaluate terms of cpSTLCa we need not only usual
terms substitution, but also models subsitution. *)
(* ----------------------------------------------------------------- *)
(** **** Free Variables *)
(* ----------------------------------------------------------------- *)
(** To correctly apply substitution(s), we will need free variables.
Both normal and concept-parameters. *)
(** The only source of free vars is [tvar] constructor.
Lambda binds its variable.
The only source of free concept vars is [tcinvk] constructor.
Concept abstraction binds its parameter.
Oooops, t # M also gives us free model variable M.
All other forms of term needs recursive search of free vars. *)
Fixpoint free_vars (CTbl : cptcontext) (MTbl : mdlcontext)
(t : tm) : IdLS.id_set :=
match t with
(* FV(x) = {x} *)
| tvar x => IdLS.IdSet.singleton x
(* FV(t1 t2) = FV(t1) \union FV(t2) *)
| tapp t1 t2 => IdLS.IdSet.union (free_vars CTbl MTbl t1)
(free_vars CTbl MTbl t2)
(* FV(\x:T.t) = FV(t) \ {x} *)
| tabs x T t => let t_fv := free_vars CTbl MTbl t in
IdLS.IdSet.remove x t_fv
(* FV(t # M) = FV(t) because M refers to MTable, not term itself *)
| tmapp t M => free_vars CTbl MTbl t
(*
(* FV(t # M) = FV(t) \union {M} *)
| tmapp t M => IdLS.IdSet.union (free_vars t) (IdLS.IdSet.singleton M)
*)
(* FV(\c#C.t) = FV(t) \ {c}
No C because C is not subject for substitution *)
| tcabs c C t => let t_fv := free_vars CTbl MTbl t in
IdLS.IdSet.remove c t_fv
(* FV(c.f) = {c} *)
| tcinvk c f => IdLS.IdSet.singleton c
(*match IdLPM.IdMap.find c MTbl with
| None => IdLS.IdSet.singleton c
| _ => IdLS.IdSet.empty (* this is M.f where M \in MTbl *)
end*)
(* FV(true) = {} *)
| ttrue => IdLS.IdSet.empty
(* FV(false) = {} *)
| tfalse => IdLS.IdSet.empty
(* FV(if t1 then t2 else t3) = FV(t1) \union FV(t2) \union FV(t3) *)
| tif t1 t2 t3 => IdLS.IdSet.union
(IdLS.IdSet.union
(free_vars CTbl MTbl t1) (free_vars CTbl MTbl t2))
(free_vars CTbl MTbl t3)
(* FV(n) = {} *)
| tnat n => IdLS.IdSet.empty
(* FV(succ t) = FV(t) *)
| tsucc t => free_vars CTbl MTbl t
(* FV(pred t) = FV(t) *)
| tpred t => free_vars CTbl MTbl t
(* FV(plus t1 t2) = FV(t1) \union FV(t2) *)
| tplus t1 t2 => IdLS.IdSet.union (free_vars CTbl MTbl t1)
(free_vars CTbl MTbl t2)
(* FV(minus t1 t2) = FV(t1) \union FV(t2) *)
| tminus t1 t2 => IdLS.IdSet.union (free_vars CTbl MTbl t1)
(free_vars CTbl MTbl t2)
(* FV(mult t1 t2) = FV(t1) \union FV(t2) *)
| tmult t1 t2 => IdLS.IdSet.union (free_vars CTbl MTbl t1)
(free_vars CTbl MTbl t2)
(* FV(eqnat t1 t2) = FV(t1) \union FV(t2) *)
| teqnat t1 t2 => IdLS.IdSet.union (free_vars CTbl MTbl t1)
(free_vars CTbl MTbl t2)
(* FV(lenat t1 t2) = FV(t1) \union FV(t2) *)
| tlenat t1 t2 => IdLS.IdSet.union (free_vars CTbl MTbl t1)
(free_vars CTbl MTbl t2)
(* FV(let x=t1 in t2) = FV(t1) \union (FV(t2) \ {x}) *)
| tlet x t1 t2 => let t2_fv := free_vars CTbl MTbl t2 in
IdLS.IdSet.union (free_vars CTbl MTbl t1) (IdLS.IdSet.remove x t2_fv)
end.
(* ----------------------------------------------------------------- *)
(** **** Alpha Conversion ??? *)
(* ----------------------------------------------------------------- *)
(** We will only work with nicely defined terms, which satisfy
Barendregt variable convention:
all bindings introduce different variables *)
(** We'll come back to this later... *)
(* ----------------------------------------------------------------- *)
(** **** Substitution Function *)
(* ----------------------------------------------------------------- *)
(** Note!
As normal parameters and concept-parameters lie in the same Gamma,
later binding hides the earlier one even if they are of different kinds.
Thus, in the example below
[\c:Nat.\c#MonoidNat. if c = c.ident ...]
we cannot type this term, because [c] becomes concept.
*)
(** Question:
Is it true that if we start with closed term,
nothing bad can happen?
Answer:
Probably. Consider
(\c#MonoidNat.(\x:Nat.\c:Nat. if x = c ...) c.ident) # Plus
-->
(\x:Nat.\c:Nat. if x = c ...) Plus.ident
-->
\c:Nat. if Plus.ident = c ...
But
(\c#MonoidNat.(\Plus#MonoidNat. if c.ident = ...)) Plus
-->
\Plus.MonoidNat. if Plus.ident...
(captured)
*)
(** Let us first define a substitution informally.
For simplicity, we assume that all variables binded in different
lambdas (and let-bindings)
are distinct (and we calculate closed terms only,
or free vars do not appear in bindings),
so we don't need renaming.
The same should also be applied to concept parameters,
and, probably, concept names and model names:
no repetitions and no intersections with variables.
*)
(** Note that since M and C are not first-class, they have
syntax-directed positions and do not interfere with Gamma.
[x:=s] x = s
[x:=s] y = y if x <> y
[x:=s] (t1 t2) = ([x:=s] t1) ([x:=s] t2)
[x:=s] (\x:T11. t12) = \x:T11. t12
[x:=s] (\y:T11. t12) = \y:T11. [x:=s]t12 if x <> y
Check: y \notin FV(s)
Note! The situation when y \in FV(s) must be impossible
under our assumptions.
[x:=s] (t1 # M) = ([x:=s] t1) # M
Note! The situation M = x must be impossible
under our assumptions. Or we do not care about this...
[x:=s] (\x#C.t1) = \x#C.t1
[x:=s] (\c#C.t1) = \c#C.([x:=s] t1) if x <> c
[x:=s] (c.f) = c.f (independently of x <> c)
[x:=s] true = true
[x:=s] false = false
[x:=s] (if t1 then t2 else t3)
=
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
[x:=s] n = n
[x:=s] (succ t) = succ ([x:=s] t)
[x:=s] (pred t) = pred ([x:=s] t)
[x:=s] (plus t1 t2) = plus ([x:=s] t1) ([x:=s] t2)
[x:=s] (minus t1 t2) = minus ([x:=s] t1) ([x:=s] t2)
[x:=s] (mult t1 t2) = mult ([x:=s] t1) ([x:=s] t2)
[x:=s] (eqnat t1 t2) = eqnat ([x:=s] t1) ([x:=s] t2)
[x:=s] (lenat t1 t2) = lenat ([x:=s] t1) ([x:=s] t2)
[x:=s] (let x = t1 in t2)
=
let x = ([x:=s] t1) t2
[x:=s] (let y = t1 in t2) if y <> x
= (and y \notin FV(s))
let y = ([x:=s] t1) ([x:=s] t2)
*)
(** Function [subst] takes var [x], terms [s] and [t].
It replaces all free occurences of [x] in term [t] with term [s]. *)
Fixpoint subst (x : id) (s : tm) (t : tm) : tm :=
match t with
| tvar y =>
if beq_id x y then s else t
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
(* We assume that y \notin FV(s) *)
| tabs y T t1 =>
tabs y T (if beq_id x y then t1 else (subst x s t1))
| tmapp t1 M =>
tmapp (subst x s t1) M
| tcabs c C t1 =>
tcabs c C (if beq_id c x then t1 else (subst x s t1))
| tcinvk c f =>
tcinvk c f
| ttrue => ttrue
| tfalse => tfalse
| tif t1 t2 t3 =>
tif (subst x s t1) (subst x s t2) (subst x s t3)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tplus t1 t2 =>
tplus (subst x s t1) (subst x s t2)
| tminus t1 t2 =>
tminus (subst x s t1) (subst x s t2)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| teqnat t1 t2 =>
teqnat (subst x s t1) (subst x s t2)
| tlenat t1 t2 =>
tlenat (subst x s t1) (subst x s t2)
| tlet y t1 t2 =>
tlet y (subst x s t1) (if beq_id x y then t2 else (subst x s t2))
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20) : stlca_scope.
(** We will also need concept parameters substitution.
Let us first define it informally.
For simplicity, we assume that all concept-parameters
binded in different concept abstractions
are distinct.
[#c:=M] x = x (we do not touch variables)
[#c:=M] (t1 t2) = ([#c:=M] t1) ([#c:=M] t2)
[#c:=M] (\c:T11. t12) = \c:T11. t12
[#c:=M] (\x:T11. t12) = \x:T11. ([#c:=M] t12) if c <> x
[#c:=M] (t1 # N) = ([#c:=M] t1) # N
[x:=s] (\c#C.t1) = \c#C.([#c:=M] t1)
[#c:=M] (\c#C.t1) = \c#C.t1
[#c:=M] (\d#C.t1) = \d#C.([#c:=M] t1) if c <> d
Check: M <> d
Note! The situation when M = d must be impossible
under our assumptions.
[#c:=M] (c.f) = M.f
[#c:=M] (d.f) = d.f if c <> d
[#c:=M] true = true
[#c:=M] false = false
[#c:=M] (if t1 then t2 else t3)
=
if [#c:=M]t1 then [#c:=M]t2 else [#c:=M]t3
[#c:=M] n = n
[#c:=M] (succ t) = succ ([#c:=M] t)
[#c:=M] (pred t) = pred ([#c:=M] t)
[#c:=M] (plus t1 t2) = plus ([#c:=M] t1) ([#c:=M] t2)
[#c:=M] (minus t1 t2) = minus ([#c:=M] t1) ([#c:=M] t2)
[#c:=M] (mult t1 t2) = mult ([#c:=M] t1) ([#c:=M] t2)
[#c:=M] (eqnat t1 t2) = eqnat ([#c:=M] t1) ([#c:=M] t2)
[#c:=M] (lenat t1 t2) = lenat ([#c:=M] t1) ([#c:=M] t2)
[#c:=M] (let c = t1 in t2)
=
let c = ([#c:=M] t1) in t2
[#c:=M] (let x = t1 in t2) if c <> x
= Check: M <> x
let x = ([#c:=M] t1) in ([#c:=M] t2)
*)
(** Function [substc] takes concept parameter name [c],
model name [M], and terms [t].
It replaces all free occurences of [c] in term [t] with term [s]. *)
Fixpoint substc (c : id) (M : id) (t : tm) : tm :=
match t with
| tvar x => tvar x
| tapp t1 t2 =>
tapp (substc c M t1) (substc c M t2)
| tabs x T t1 =>
tabs x T (if beq_id c x then t1 else (substc c M t1))
| tmapp t1 N =>
tmapp (substc c M t1) N
(* We assume that M <> d *)
| tcabs d C t1 =>
tcabs d C (if beq_id c d then t1 else (substc c M t1))
| tcinvk d f =>
tcinvk (if beq_id c d then M else d) f
| ttrue => ttrue
| tfalse => tfalse
| tif t1 t2 t3 =>
tif (substc c M t1) (substc c M t2) (substc c M t3)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (substc c M t1)
| tpred t1 =>
tpred (substc c M t1)
| tplus t1 t2 =>
tplus (substc c M t1) (substc c M t2)
| tminus t1 t2 =>
tminus (substc c M t1) (substc c M t2)
| tmult t1 t2 =>
tmult (substc c M t1) (substc c M t2)
| teqnat t1 t2 =>
teqnat (substc c M t1) (substc c M t2)
| tlenat t1 t2 =>
tlenat (substc c M t1) (substc c M t2)
(* We assume that M <> x *)
| tlet x t1 t2 =>
tlet x (substc c M t1) (if beq_id c x then t2 else (substc c M t2))
end.
Notation "'[#' c ':=' M ']' t" := (substc c M t) (at level 20) : stlca_scope.
(** Looks for element in an id set. *)
Definition id_mem := IdLS.IdSet.mem.
Fixpoint qualify_model_members' (M : id) (toQual : IdLS.id_set) (t : tm) : tm :=
match t with
| tvar x => if id_mem x toQual
(* if [x] is a model member, we qualify it *)
then tcinvk M x
(* otherwise do not touch *)
else tvar x
| tapp t1 t2 =>
tapp (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
| tabs x T t1 =>
(* no need to qualify bound variable *)
let toQual' := (IdLS.IdSet.remove x toQual) in
tabs x T (qualify_model_members' M toQual' t1)
| tmapp t1 N =>
tmapp (qualify_model_members' M toQual t1) N
| tcabs c C t1 =>
(* no need to qualify bound variable *)
let toQual' := IdLS.IdSet.remove c toQual in
tcabs c C (qualify_model_members' M toQual' t1)
| tcinvk c f =>
tcinvk c f
| ttrue => ttrue
| tfalse => tfalse
| tif t1 t2 t3 =>
tif (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
(qualify_model_members' M toQual t3)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (qualify_model_members' M toQual t1)
| tpred t1 =>
tpred (qualify_model_members' M toQual t1)
| tplus t1 t2 =>
tplus (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
| tminus t1 t2 =>
tminus (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
| tmult t1 t2 =>
tmult (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
| teqnat t1 t2 =>
teqnat (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
| tlenat t1 t2 =>
tlenat (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual t2)
| tlet x t1 t2 =>
let toQual' := IdLS.IdSet.remove x toQual in
tlet x (qualify_model_members' M toQual t1)
(qualify_model_members' M toQual' t2)
end.
Definition qualify_model_members (M : id) (Mbody : id_tm_map) (t : tm) : tm :=
let toQual := set_of_keys Mbody in
qualify_model_members' M toQual t.
(* ================================================================= *)
(** *** Reduction (Small-step operational semantics) *)
(* ================================================================= *)
(** What is the form of reduction relation in cpSTLCa?
We will definitely need to keep track the information from
symbol tables of concept and models.
So, instead of usual [t ==> t']
we have
[CTable * MTable ; t ==> t']
In the inference rules we use two kinds of substitution:
[x:=s] t -- substitution, variable substitution
(variable [x] is substituted with term [s] in term [t])
[#c:=M] t -- concept substitution
(concept parameter [c] is substituted with
model [M] in term [t])
Here are the rules:
tvar x
no rules
tapp t1 t2
value v2
------------------------------------------- (ST_AppAbs)
CTbl * MTbl ; (\x:T.t12) v2 ==> [x:=v2] t12
CTble * MTbl ; t1 ==> t1'
------------------------------ (ST_App1)
CTbl * MTbl ; t1 t2 ==> t1' t2
value v1
CTbl * MTbl ; t2 ==> t2'
------------------------------ (ST_App2)
CTbl * MTbl ; v1 t2 ==> v1 t2'
tabs x T11 t12 (\x:T11.t12)
no rules
tmapp t1 M (t1 # M)
M \in dom(MTbl)
MTble(M) implements C
------------------------------------------ (ST_MAppCAbs)
CTbl * MTbl ; (\c#C.t) M ==> [#c:=M] t
CTble * MTbl ; t1 ==> t1'
-------------------------------- (ST_MApp1)
CTbl * MTbl ; t1 # M ==> t1' # M
tcabs c C t1 (\c#C.t1)
no rules
tcinvk M f (M.f)
member invocation can be evaluated only if a model name
is used as a receiver, so we write M.f instead of c.f
M \in dom(MTbl)
f \in names(MTbl(M))
MTble(M)(f) = tf
------------------------------- (ST_CInvk)
CTbl * MTbl ; M.f ==> QMM(tf)
where QMM is a function, which takes a term and
replaces all model members into their qualified names.
ttrue
no rules
tfalse
no rules
tif t1 t2 t3 (if t1 then t2 else t3)
---------------------------------------------- (ST_IfTrue)
CTbl * MTbl ; if true then t1 else t2 ==> t1
----------------------------------------------- (ST_IfFalse)
CTbl * MTbl ; if false then t1 else t2 ==> t2
CTbl * MTbl ; t1 ==> t1'
------------------------------------------------------------------ (ST_If)
CTbl * MTbl ; (if t1 then t2 else t3) ==> (if t1' then t2 else t3)
tnat n
no rules
tsucc t1 (succ t1)
------------------------------------------ (ST_SuccNV)
CTbl * MTbl ; succ (tnat n) ==> tnat (S n)
CTbl * MTbl ; t1 ==> t1'
------------------------------------ (ST_Succ)
CTbl * MTbl ; succ t1 ==> succ t1'
tpred t1 (pred t1)
-------------------------------------- (ST_PredZero)
CTbl * MTbl ; pred (tnat 0) ==> tnat 0
------------------------------------------ (ST_PredSucc)
CTbl * MTbl ; pred (tnat (S n)) ==> tnat n
CTbl * MTbl ; t1 ==> t1'
------------------------------------ (ST_Pred)
CTbl * MTbl ; pred t1 ==> pred t1'
tplus t1 t2 (plus t1 t2)
--------------------------------------------------------- (ST_PlusNV)
CTbl * MTbl ; plus (tnat n1) (tnat n2) ==> tnat (n1 + n2)
CTbl * MTbl ; t1 ==> t1'
---------------------------------------- (ST_Plus1)
CTbl * MTbl ; plus t1 t2 ==> plus t1' t2
value v1
CTbl * MTbl ; t2 ==> t2'
---------------------------------------- (ST_Plus2)
CTbl * MTbl ; plus v1 t2 ==> plus v1 t2'
tminus t1 t2 (minus t1 t2)
---------------------------------------------------------- (ST_MinusNV)
CTbl * MTbl ; minus (tnat n1) (tnat n2) ==> tnat (n1 - n2)
CTbl * MTbl ; t1 ==> t1'
------------------------------------------ (ST_Minus1)
CTbl * MTbl ; minus t1 t2 ==> minus t1' t2
value v1
CTbl * MTbl ; t2 ==> t2'
------------------------------------------ (ST_Minus2)
CTbl * MTbl ; minus v1 t2 ==> minus v1 t2'
tmult t1 t2 (mult t1 t2)
--------------------------------------------------------- (ST_MultNV)
CTbl * MTbl ; mult (tnat n1) (tnat n2) ==> tnat (n1 * n2)
CTbl * MTbl ; t1 ==> t1'
---------------------------------------- (ST_Mult1)
CTbl * MTbl ; mult t1 t2 ==> mult t1' t2
value v1
CTbl * MTbl ; t2 ==> t2'
---------------------------------------- (ST_Mult2)
CTbl * MTbl ; mult v1 t2 ==> mult v1 t2'
teqnat t1 t2 (eqnat t1 t2)
---------------------------------------------------------- (ST_EqnatNV)
CTbl * MTbl ; eqnat (tnat n1) (tnat n2) ==> tnat (n1 = n2)
CTbl * MTbl ; t1 ==> t1'
------------------------------------------ (ST_Eqnat1)
CTbl * MTbl ; eqnat t1 t2 ==> eqnat t1' t2
value v1
CTbl * MTbl ; t2 ==> t2'
------------------------------------------ (ST_Eqnat2)
CTbl * MTbl ; eqnat v1 t2 ==> eqnat v1 t2'
tlenat t1 t2 (lenat t1 t2)
---------------------------------------------------------- (ST_LenatNV)
CTbl * MTbl ; lenat (tnat n1) (tnat n2) ==> tnat (n1 < n2)
CTbl * MTbl ; t1 ==> t1'
------------------------------------------ (ST_Lenat1)
CTbl * MTbl ; lenat t1 t2 ==> lenat t1' t2
value v1
CTbl * MTbl ; t2 ==> t2'
------------------------------------------ (ST_Lenat2)
CTbl * MTbl ; lenat v1 t2 ==> lenat v1 t2'
tlet x t1 t2 (let x = t1 in t2)
CTbl * MTbl ; t1 ==> t1'
------------------------------------------------ (ST_Let)
CTbl * MTbl ; let x=t1 in t2 ==> let x=t1' in t2
value v1
------------------------------------------- (ST_LetValue)
CTbl * MTbl ; let x=v1 in t2 ==> [x:=v1] t2
*)
(** Here is a formal definition [step] of the
* small-step reduction relation. *)
Reserved Notation "CTbl '$' MTbl ';' t1 '#==>' t2" (at level 50).
Inductive step (CTbl : cptcontext) (MTbl : mdlcontext) : tm -> tm -> Prop :=
(* app *)
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
CTbl $ MTbl ; (tapp (tabs x T11 t12) v2) #==> ([x:=v2] t12)
| ST_App1 : forall t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tapp t1 t2) #==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
CTbl $ MTbl ; t2 #==> t2' ->
CTbl $ MTbl ; (tapp v1 t2) #==> (tapp v1 t2')
(* mapp *)
| ST_MAppCAbs : forall c C t M Mbody,
IdLPM.IdMap.find M MTbl = Some (MTdef C Mbody) ->
CTbl $ MTbl ; (tmapp (tcabs c C t) M) #==> ([#c:=M] t)
| ST_MApp1 : forall t1 t1' M,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tmapp t1 M) #==> (tmapp t1' M)
(* cinvk *)
| ST_CInvk : forall M f C Mbody tf,
IdLPM.IdMap.find M MTbl = Some (MTdef C Mbody) ->
find_tm f Mbody = Some tf ->
CTbl $ MTbl ; (tcinvk M f) #==> (qualify_model_members M Mbody tf)
(* if *)
| ST_IfTrue : forall t2 t3,
CTbl $ MTbl ; (tif ttrue t2 t3) #==> t2
| ST_IfFalse : forall t2 t3,
CTbl $ MTbl ; (tif tfalse t2 t3) #==> t3
| ST_If : forall t1 t1' t2 t3,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tif t1 t2 t3) #==> (tif t1' t2 t3)
(* succ *)
| ST_SuccNV : forall n,
CTbl $ MTbl ; (tsucc (tnat n)) #==> tnat (S n)
| ST_Succ : forall t1 t1',
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tsucc t1) #==> (tsucc t1')
(* pred *)
| ST_PredZero :
CTbl $ MTbl ; (tpred (tnat 0)) #==> tnat 0
| ST_PredSucc : forall n,
CTbl $ MTbl ; (tpred (tnat (S n))) #==> tnat n
| ST_Pred : forall t1 t1',
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tpred t1) #==> (tpred t1')
(* plus *)
| ST_PlusNV : forall n1 n2,
CTbl $ MTbl ; (tplus (tnat n1) (tnat n2)) #==> tnat (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tplus t1 t2) #==> (tplus t1' t2)
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
CTbl $ MTbl ; t2 #==> t2' ->
CTbl $ MTbl ; (tplus v1 t2) #==> (tplus v1 t2')
(* minus *)
| ST_MinusNV : forall n1 n2,
CTbl $ MTbl ; (tminus (tnat n1) (tnat n2)) #==> tnat (n1 - n2)
| ST_Minus1 : forall t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tminus t1 t2) #==> (tminus t1' t2)
| ST_Minus2 : forall v1 t2 t2',
value v1 ->
CTbl $ MTbl ; t2 #==> t2' ->
CTbl $ MTbl ; (tminus v1 t2) #==> (tminus v1 t2')
(* mult *)
| ST_MultNV : forall n1 n2,
CTbl $ MTbl ; (tmult (tnat n1) (tnat n2)) #==> tnat (n1 * n2)
| ST_Mult1 : forall t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tmult t1 t2) #==> (tmult t1' t2)
| ST_Mult2 : forall v1 t2 t2',
value v1 ->
CTbl $ MTbl ; t2 #==> t2' ->
CTbl $ MTbl ; (tmult v1 t2) #==> (tmult v1 t2')
(* eqnat *)
| ST_EqnatNVTrue : forall n1 n2,
n1 = n2 ->
CTbl $ MTbl ; (teqnat (tnat n1) (tnat n2)) #==> ttrue
| ST_EqnatNVFalse : forall n1 n2,
n1 <> n2 ->
CTbl $ MTbl ; (teqnat (tnat n1) (tnat n2)) #==> tfalse
| ST_Eqnat1 : forall t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (teqnat t1 t2) #==> (teqnat t1' t2)
| ST_Eqnat2 : forall v1 t2 t2',
value v1 ->
CTbl $ MTbl ; t2 #==> t2' ->
CTbl $ MTbl ; (teqnat v1 t2) #==> (teqnat v1 t2')
(* lenat *)
| ST_LenatNVTrue : forall n1 n2,
n1 < n2 ->
CTbl $ MTbl ; (tlenat (tnat n1) (tnat n2)) #==> ttrue
| ST_LenatNVFalse : forall n1 n2,
n2 <= n1 ->
CTbl $ MTbl ; (tlenat (tnat n1) (tnat n2)) #==> tfalse
| ST_Lenat1 : forall t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tlenat t1 t2) #==> (tlenat t1' t2)
| ST_Lenat2 : forall v1 t2 t2',
value v1 ->
CTbl $ MTbl ; t2 #==> t2' ->
CTbl $ MTbl ; (tlenat v1 t2) #==> (tlenat v1 t2')
(* let *)
| ST_Let : forall x t1 t1' t2,
CTbl $ MTbl ; t1 #==> t1' ->
CTbl $ MTbl ; (tlet x t1 t2) #==> (tlet x t1' t2)
| ST_LetValue : forall x v1 t2,
CTbl $ MTbl ; (tlet x v1 t2) #==> ([x:=v1] t2)
where "CTbl '$' MTbl ';' t1 '#==>' t2" := (step CTbl MTbl t1 t2) : stlca_scope.
Hint Constructors step.
(* ----------------------------------------------------------------- *)
(** **** Multi-Step Reduction *)
(* ----------------------------------------------------------------- *)
(** [multi_step] is a usual definition of multi-step relation.
The only reason we define it manually is because it's not in
the form [(t, t)], but [(CTbl, MTbl, t, t)]. *)
Reserved Notation "CTbl '$$' MTbl ';;' t1 '#==>*' t2" (at level 50).
Inductive multistep (CTbl : cptcontext) (MTbl : mdlcontext)
: tm -> tm -> Prop :=
| MST_Refl : forall (t : tm),
CTbl $$ MTbl ;; t #==>* t
| MST_Step : forall t1 t2 t3,
CTbl $ MTbl ; t1 #==> t2 ->
CTbl $$ MTbl ;; t2 #==>* t3 ->
CTbl $$ MTbl ;; t1 #==>* t3
where "CTbl '$$' MTbl ';;' t1 '#==>*' t2" := (multistep CTbl MTbl t1 t2)
: stlca_scope.
Open Scope stlca_scope.
Theorem multistep_step :
forall (CTbl : cptcontext) (MTbl : mdlcontext) (t t' : tm),
CTbl $ MTbl ; t #==> t' ->
CTbl $$ MTbl ;; t #==>* t'.
Proof.
intros CT MT t t' H.
apply MST_Step with t'. apply H. apply MST_Refl.
Qed.
Theorem multistep_trans :
forall (CTbl : cptcontext) (MTbl : mdlcontext) (t1 t2 t3 : tm),
CTbl $$ MTbl ;; t1 #==>* t2 ->
CTbl $$ MTbl ;; t2 #==>* t3 ->
CTbl $$ MTbl ;; t1 #==>* t3.
Proof.
intros CT MT t1 t2 t3 H12.
induction H12; intros H23.
- (* refl *) assumption.
- (* step *)
specialize (IHmultistep H23).
apply MST_Step with t2; assumption.
Qed.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xor2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire xor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XOR2_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CONB_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__CONB_PP_BLACKBOX_V
/**
* conb: Constant value, low, high outputs.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__conb (
HI ,
LO ,
VPWR,
VGND,
VPB ,
VNB
);
output HI ;
output LO ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__CONB_PP_BLACKBOX_V
|
`timescale 1ns/10ps
module pll_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("normal"),
.number_of_clocks(1),
.output_clock_frequency0("40.0 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("0 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.outclk ({outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.rst (rst),
.refclk (refclk)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR4B_BLACKBOX_V
`define SKY130_FD_SC_HDLL__OR4B_BLACKBOX_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__or4b (
X ,
A ,
B ,
C ,
D_N
);
output X ;
input A ;
input B ;
input C ;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR4B_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_TB_V
`define SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_TB_V
/**
* udp_dlatch$P_pp$PG$N: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__udp_dlatch_p_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 VGND = 1'b0;
#80 VPWR = 1'b0;
#100 D = 1'b1;
#120 NOTIFIER = 1'b1;
#140 VGND = 1'b1;
#160 VPWR = 1'b1;
#180 D = 1'b0;
#200 NOTIFIER = 1'b0;
#220 VGND = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VGND = 1'b1;
#300 NOTIFIER = 1'b1;
#320 D = 1'b1;
#340 VPWR = 1'bx;
#360 VGND = 1'bx;
#380 NOTIFIER = 1'bx;
#400 D = 1'bx;
end
// Create a clock
reg GATE;
initial
begin
GATE = 1'b0;
end
always
begin
#5 GATE = ~GATE;
end
sky130_fd_sc_hd__udp_dlatch$P_pp$PG$N dut (.D(D), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .GATE(GATE));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_DLATCH_P_PP_PG_N_TB_V
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.68d
// \ \ Application: netgen
// / / Filename: mult12x12.v
// /___/ /\ Timestamp: Thu Sep 25 20:29:26 2014
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog "C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab5/ipcore_dir/tmp/_cg/mult12x12.ngc" "C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab5/ipcore_dir/tmp/_cg/mult12x12.v"
// Device : 3s100ecp132-5
// Input file : C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab5/ipcore_dir/tmp/_cg/mult12x12.ngc
// Output file : C:/Users/James/Desktop/iDriveSync/IDrive-Sync/DSD LAB/Lab5/ipcore_dir/tmp/_cg/mult12x12.v
// # of Modules : 1
// Design Name : mult12x12
// Xilinx : C:\Xilinx\14.6\ISE_DS\ISE\
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module mult12x12 (
p, a, b
)/* synthesis syn_black_box syn_noprune=1 */;
output [23 : 0] p;
input [11 : 0] a;
input [11 : 0] b;
// synthesis translate_off
wire \blk00000001/sig0000001a ;
wire \blk00000001/sig00000019 ;
wire \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<32>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<29>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<26>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_P<23>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED ;
wire \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED ;
MULT18X18SIO #(
.AREG ( 0 ),
.BREG ( 0 ),
.B_INPUT ( "DIRECT" ),
.PREG ( 0 ))
\blk00000001/blk00000004 (
.CEA(\blk00000001/sig0000001a ),
.CEB(\blk00000001/sig0000001a ),
.CEP(\blk00000001/sig0000001a ),
.CLK(\blk00000001/sig0000001a ),
.RSTA(\blk00000001/sig00000019 ),
.RSTB(\blk00000001/sig00000019 ),
.RSTP(\blk00000001/sig00000019 ),
.A({a[11], a[11], a[11], a[11], a[11], a[11], a[11], a[10], a[9], a[8], a[7], a[6], a[5], a[4], a[3], a[2], a[1], a[0]}),
.B({b[11], b[11], b[11], b[11], b[11], b[11], b[11], b[10], b[9], b[8], b[7], b[6], b[5], b[4], b[3], b[2], b[1], b[0]}),
.BCIN({\blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 ,
\blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 ,
\blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 ,
\blk00000001/sig00000019 , \blk00000001/sig00000019 , \blk00000001/sig00000019 }),
.P({p[23], \NLW_blk00000001/blk00000004_P<34>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<33>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<32>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<31>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<30>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<29>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<28>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<27>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<26>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<25>_UNCONNECTED , \NLW_blk00000001/blk00000004_P<24>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_P<23>_UNCONNECTED , p[22], p[21], p[20], p[19], p[18], p[17], p[16], p[15], p[14], p[13], p[12], p[11], p[10], p[9], p[8]
, p[7], p[6], p[5], p[4], p[3], p[2], p[1], p[0]}),
.BCOUT({\NLW_blk00000001/blk00000004_BCOUT<17>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<16>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<15>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<14>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<13>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<12>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<11>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<10>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<9>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<8>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<7>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<6>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<5>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<4>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<3>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<2>_UNCONNECTED ,
\NLW_blk00000001/blk00000004_BCOUT<1>_UNCONNECTED , \NLW_blk00000001/blk00000004_BCOUT<0>_UNCONNECTED })
);
VCC \blk00000001/blk00000003 (
.P(\blk00000001/sig0000001a )
);
GND \blk00000001/blk00000002 (
.G(\blk00000001/sig00000019 )
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
// system_acl_iface_acl_kernel_interface.v
// Generated using ACDS version 14.0 200 at 2015.04.28.12:23:11
`timescale 1 ps / 1 ps
module system_acl_iface_acl_kernel_interface (
input wire clk_clk, // clk.clk
input wire reset_reset_n, // reset.reset_n
output wire kernel_cntrl_waitrequest, // kernel_cntrl.waitrequest
output wire [31:0] kernel_cntrl_readdata, // .readdata
output wire kernel_cntrl_readdatavalid, // .readdatavalid
input wire [0:0] kernel_cntrl_burstcount, // .burstcount
input wire [31:0] kernel_cntrl_writedata, // .writedata
input wire [13:0] kernel_cntrl_address, // .address
input wire kernel_cntrl_write, // .write
input wire kernel_cntrl_read, // .read
input wire [3:0] kernel_cntrl_byteenable, // .byteenable
input wire kernel_cntrl_debugaccess, // .debugaccess
input wire kernel_cra_waitrequest, // kernel_cra.waitrequest
input wire [63:0] kernel_cra_readdata, // .readdata
input wire kernel_cra_readdatavalid, // .readdatavalid
output wire [0:0] kernel_cra_burstcount, // .burstcount
output wire [63:0] kernel_cra_writedata, // .writedata
output wire [29:0] kernel_cra_address, // .address
output wire kernel_cra_write, // .write
output wire kernel_cra_read, // .read
output wire [7:0] kernel_cra_byteenable, // .byteenable
output wire kernel_cra_debugaccess, // .debugaccess
input wire [0:0] kernel_irq_from_kernel_irq, // kernel_irq_from_kernel.irq
output wire [1:0] acl_bsp_memorg_kernel_mode, // acl_bsp_memorg_kernel.mode
output wire [1:0] acl_bsp_memorg_host_mode, // acl_bsp_memorg_host.mode
input wire sw_reset_in_reset, // sw_reset_in.reset
input wire kernel_clk_clk, // kernel_clk.clk
output wire sw_reset_export_reset_n, // sw_reset_export.reset_n
output wire kernel_reset_reset_n, // kernel_reset.reset_n
output wire kernel_irq_to_host_irq // kernel_irq_to_host.irq
);
wire reset_controller_sw_reset_out_reset; // reset_controller_sw:reset_out -> [irq_bridge_0:reset, kernel_cra:reset, mm_interconnect_0:kernel_cra_reset_reset_bridge_in_reset_reset, reset_controller_sw_reset_out_reset:in]
wire [0:0] address_span_extender_0_expanded_master_burstcount; // address_span_extender_0:avm_m0_burstcount -> mm_interconnect_0:address_span_extender_0_expanded_master_burstcount
wire address_span_extender_0_expanded_master_waitrequest; // mm_interconnect_0:address_span_extender_0_expanded_master_waitrequest -> address_span_extender_0:avm_m0_waitrequest
wire [31:0] address_span_extender_0_expanded_master_writedata; // address_span_extender_0:avm_m0_writedata -> mm_interconnect_0:address_span_extender_0_expanded_master_writedata
wire [29:0] address_span_extender_0_expanded_master_address; // address_span_extender_0:avm_m0_address -> mm_interconnect_0:address_span_extender_0_expanded_master_address
wire address_span_extender_0_expanded_master_write; // address_span_extender_0:avm_m0_write -> mm_interconnect_0:address_span_extender_0_expanded_master_write
wire address_span_extender_0_expanded_master_read; // address_span_extender_0:avm_m0_read -> mm_interconnect_0:address_span_extender_0_expanded_master_read
wire [31:0] address_span_extender_0_expanded_master_readdata; // mm_interconnect_0:address_span_extender_0_expanded_master_readdata -> address_span_extender_0:avm_m0_readdata
wire [3:0] address_span_extender_0_expanded_master_byteenable; // address_span_extender_0:avm_m0_byteenable -> mm_interconnect_0:address_span_extender_0_expanded_master_byteenable
wire address_span_extender_0_expanded_master_readdatavalid; // mm_interconnect_0:address_span_extender_0_expanded_master_readdatavalid -> address_span_extender_0:avm_m0_readdatavalid
wire mm_interconnect_0_kernel_cra_s0_waitrequest; // kernel_cra:s0_waitrequest -> mm_interconnect_0:kernel_cra_s0_waitrequest
wire [0:0] mm_interconnect_0_kernel_cra_s0_burstcount; // mm_interconnect_0:kernel_cra_s0_burstcount -> kernel_cra:s0_burstcount
wire [63:0] mm_interconnect_0_kernel_cra_s0_writedata; // mm_interconnect_0:kernel_cra_s0_writedata -> kernel_cra:s0_writedata
wire [29:0] mm_interconnect_0_kernel_cra_s0_address; // mm_interconnect_0:kernel_cra_s0_address -> kernel_cra:s0_address
wire mm_interconnect_0_kernel_cra_s0_write; // mm_interconnect_0:kernel_cra_s0_write -> kernel_cra:s0_write
wire mm_interconnect_0_kernel_cra_s0_read; // mm_interconnect_0:kernel_cra_s0_read -> kernel_cra:s0_read
wire [63:0] mm_interconnect_0_kernel_cra_s0_readdata; // kernel_cra:s0_readdata -> mm_interconnect_0:kernel_cra_s0_readdata
wire mm_interconnect_0_kernel_cra_s0_debugaccess; // mm_interconnect_0:kernel_cra_s0_debugaccess -> kernel_cra:s0_debugaccess
wire mm_interconnect_0_kernel_cra_s0_readdatavalid; // kernel_cra:s0_readdatavalid -> mm_interconnect_0:kernel_cra_s0_readdatavalid
wire [7:0] mm_interconnect_0_kernel_cra_s0_byteenable; // mm_interconnect_0:kernel_cra_s0_byteenable -> kernel_cra:s0_byteenable
wire [0:0] kernel_cntrl_m0_burstcount; // kernel_cntrl:m0_burstcount -> mm_interconnect_1:kernel_cntrl_m0_burstcount
wire kernel_cntrl_m0_waitrequest; // mm_interconnect_1:kernel_cntrl_m0_waitrequest -> kernel_cntrl:m0_waitrequest
wire [13:0] kernel_cntrl_m0_address; // kernel_cntrl:m0_address -> mm_interconnect_1:kernel_cntrl_m0_address
wire [31:0] kernel_cntrl_m0_writedata; // kernel_cntrl:m0_writedata -> mm_interconnect_1:kernel_cntrl_m0_writedata
wire kernel_cntrl_m0_write; // kernel_cntrl:m0_write -> mm_interconnect_1:kernel_cntrl_m0_write
wire kernel_cntrl_m0_read; // kernel_cntrl:m0_read -> mm_interconnect_1:kernel_cntrl_m0_read
wire [31:0] kernel_cntrl_m0_readdata; // mm_interconnect_1:kernel_cntrl_m0_readdata -> kernel_cntrl:m0_readdata
wire kernel_cntrl_m0_debugaccess; // kernel_cntrl:m0_debugaccess -> mm_interconnect_1:kernel_cntrl_m0_debugaccess
wire [3:0] kernel_cntrl_m0_byteenable; // kernel_cntrl:m0_byteenable -> mm_interconnect_1:kernel_cntrl_m0_byteenable
wire kernel_cntrl_m0_readdatavalid; // mm_interconnect_1:kernel_cntrl_m0_readdatavalid -> kernel_cntrl:m0_readdatavalid
wire mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest; // address_span_extender_0:avs_s0_waitrequest -> mm_interconnect_1:address_span_extender_0_windowed_slave_waitrequest
wire [0:0] mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount; // mm_interconnect_1:address_span_extender_0_windowed_slave_burstcount -> address_span_extender_0:avs_s0_burstcount
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_writedata; // mm_interconnect_1:address_span_extender_0_windowed_slave_writedata -> address_span_extender_0:avs_s0_writedata
wire [9:0] mm_interconnect_1_address_span_extender_0_windowed_slave_address; // mm_interconnect_1:address_span_extender_0_windowed_slave_address -> address_span_extender_0:avs_s0_address
wire mm_interconnect_1_address_span_extender_0_windowed_slave_write; // mm_interconnect_1:address_span_extender_0_windowed_slave_write -> address_span_extender_0:avs_s0_write
wire mm_interconnect_1_address_span_extender_0_windowed_slave_read; // mm_interconnect_1:address_span_extender_0_windowed_slave_read -> address_span_extender_0:avs_s0_read
wire [31:0] mm_interconnect_1_address_span_extender_0_windowed_slave_readdata; // address_span_extender_0:avs_s0_readdata -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdata
wire mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid; // address_span_extender_0:avs_s0_readdatavalid -> mm_interconnect_1:address_span_extender_0_windowed_slave_readdatavalid
wire [3:0] mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable; // mm_interconnect_1:address_span_extender_0_windowed_slave_byteenable -> address_span_extender_0:avs_s0_byteenable
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_writedata; // mm_interconnect_1:address_span_extender_0_cntl_writedata -> address_span_extender_0:avs_cntl_writedata
wire mm_interconnect_1_address_span_extender_0_cntl_write; // mm_interconnect_1:address_span_extender_0_cntl_write -> address_span_extender_0:avs_cntl_write
wire mm_interconnect_1_address_span_extender_0_cntl_read; // mm_interconnect_1:address_span_extender_0_cntl_read -> address_span_extender_0:avs_cntl_read
wire [63:0] mm_interconnect_1_address_span_extender_0_cntl_readdata; // address_span_extender_0:avs_cntl_readdata -> mm_interconnect_1:address_span_extender_0_cntl_readdata
wire [7:0] mm_interconnect_1_address_span_extender_0_cntl_byteenable; // mm_interconnect_1:address_span_extender_0_cntl_byteenable -> address_span_extender_0:avs_cntl_byteenable
wire [63:0] mm_interconnect_1_sys_description_rom_s1_writedata; // mm_interconnect_1:sys_description_rom_s1_writedata -> sys_description_rom:writedata
wire [8:0] mm_interconnect_1_sys_description_rom_s1_address; // mm_interconnect_1:sys_description_rom_s1_address -> sys_description_rom:address
wire mm_interconnect_1_sys_description_rom_s1_chipselect; // mm_interconnect_1:sys_description_rom_s1_chipselect -> sys_description_rom:chipselect
wire mm_interconnect_1_sys_description_rom_s1_clken; // mm_interconnect_1:sys_description_rom_s1_clken -> sys_description_rom:clken
wire mm_interconnect_1_sys_description_rom_s1_write; // mm_interconnect_1:sys_description_rom_s1_write -> sys_description_rom:write
wire [63:0] mm_interconnect_1_sys_description_rom_s1_readdata; // sys_description_rom:readdata -> mm_interconnect_1:sys_description_rom_s1_readdata
wire mm_interconnect_1_sys_description_rom_s1_debugaccess; // mm_interconnect_1:sys_description_rom_s1_debugaccess -> sys_description_rom:debugaccess
wire [7:0] mm_interconnect_1_sys_description_rom_s1_byteenable; // mm_interconnect_1:sys_description_rom_s1_byteenable -> sys_description_rom:byteenable
wire mm_interconnect_1_sw_reset_s_waitrequest; // sw_reset:slave_waitrequest -> mm_interconnect_1:sw_reset_s_waitrequest
wire [63:0] mm_interconnect_1_sw_reset_s_writedata; // mm_interconnect_1:sw_reset_s_writedata -> sw_reset:slave_writedata
wire mm_interconnect_1_sw_reset_s_write; // mm_interconnect_1:sw_reset_s_write -> sw_reset:slave_write
wire mm_interconnect_1_sw_reset_s_read; // mm_interconnect_1:sw_reset_s_read -> sw_reset:slave_read
wire [63:0] mm_interconnect_1_sw_reset_s_readdata; // sw_reset:slave_readdata -> mm_interconnect_1:sw_reset_s_readdata
wire [7:0] mm_interconnect_1_sw_reset_s_byteenable; // mm_interconnect_1:sw_reset_s_byteenable -> sw_reset:slave_byteenable
wire mm_interconnect_1_mem_org_mode_s_waitrequest; // mem_org_mode:slave_waitrequest -> mm_interconnect_1:mem_org_mode_s_waitrequest
wire [31:0] mm_interconnect_1_mem_org_mode_s_writedata; // mm_interconnect_1:mem_org_mode_s_writedata -> mem_org_mode:slave_writedata
wire mm_interconnect_1_mem_org_mode_s_write; // mm_interconnect_1:mem_org_mode_s_write -> mem_org_mode:slave_write
wire mm_interconnect_1_mem_org_mode_s_read; // mm_interconnect_1:mem_org_mode_s_read -> mem_org_mode:slave_read
wire [31:0] mm_interconnect_1_mem_org_mode_s_readdata; // mem_org_mode:slave_readdata -> mm_interconnect_1:mem_org_mode_s_readdata
wire mm_interconnect_1_version_id_0_s_read; // mm_interconnect_1:version_id_0_s_read -> version_id_0:slave_read
wire [31:0] mm_interconnect_1_version_id_0_s_readdata; // version_id_0:slave_readdata -> mm_interconnect_1:version_id_0_s_readdata
wire mm_interconnect_1_irq_ena_0_s_waitrequest; // irq_ena_0:slave_waitrequest -> mm_interconnect_1:irq_ena_0_s_waitrequest
wire [31:0] mm_interconnect_1_irq_ena_0_s_writedata; // mm_interconnect_1:irq_ena_0_s_writedata -> irq_ena_0:slave_writedata
wire mm_interconnect_1_irq_ena_0_s_write; // mm_interconnect_1:irq_ena_0_s_write -> irq_ena_0:slave_write
wire mm_interconnect_1_irq_ena_0_s_read; // mm_interconnect_1:irq_ena_0_s_read -> irq_ena_0:slave_read
wire [31:0] mm_interconnect_1_irq_ena_0_s_readdata; // irq_ena_0:slave_readdata -> mm_interconnect_1:irq_ena_0_s_readdata
wire [3:0] mm_interconnect_1_irq_ena_0_s_byteenable; // mm_interconnect_1:irq_ena_0_s_byteenable -> irq_ena_0:slave_byteenable
wire irq_mapper_receiver0_irq; // irq_bridge_0:sender0_irq -> irq_mapper:receiver0_irq
wire irq_ena_0_my_irq_in_irq; // irq_mapper:sender_irq -> irq_ena_0:irq
wire rst_controller_reset_out_reset; // rst_controller:reset_out -> [irq_ena_0:resetn, kernel_cntrl:reset, mem_org_mode:resetn, mm_interconnect_1:kernel_cntrl_reset_reset_bridge_in_reset_reset, rst_translator:in_reset, sys_description_rom:reset, version_id_0:resetn]
wire rst_controller_reset_out_reset_req; // rst_controller:reset_req -> [rst_translator:reset_req_in, sys_description_rom:reset_req]
wire rst_controller_001_reset_out_reset; // rst_controller_001:reset_out -> [address_span_extender_0:reset, mm_interconnect_0:address_span_extender_0_reset_reset_bridge_in_reset_reset, mm_interconnect_1:address_span_extender_0_reset_reset_bridge_in_reset_reset]
wire rst_controller_002_reset_out_reset; // rst_controller_002:reset_out -> [mm_interconnect_1:sw_reset_clk_reset_reset_bridge_in_reset_reset, sw_reset:resetn]
system_acl_iface_acl_kernel_interface_sys_description_rom sys_description_rom (
.clk (clk_clk), // clk1.clk
.address (mm_interconnect_1_sys_description_rom_s1_address), // s1.address
.debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.reset (rst_controller_reset_out_reset), // reset1.reset
.reset_req (rst_controller_reset_out_reset_req) // .reset_req
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (64),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (30),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cra (
.clk (kernel_clk_clk), // clk.clk
.reset (reset_controller_sw_reset_out_reset), // reset.reset
.s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // s0.waitrequest
.s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.s0_address (mm_interconnect_0_kernel_cra_s0_address), // .address
.s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cra_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cra_readdata), // .readdata
.m0_readdatavalid (kernel_cra_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cra_burstcount), // .burstcount
.m0_writedata (kernel_cra_writedata), // .writedata
.m0_address (kernel_cra_address), // .address
.m0_write (kernel_cra_write), // .write
.m0_read (kernel_cra_read), // .read
.m0_byteenable (kernel_cra_byteenable), // .byteenable
.m0_debugaccess (kernel_cra_debugaccess) // .debugaccess
);
altera_address_span_extender #(
.DATA_WIDTH (32),
.BYTEENABLE_WIDTH (4),
.MASTER_ADDRESS_WIDTH (30),
.SLAVE_ADDRESS_WIDTH (10),
.SLAVE_ADDRESS_SHIFT (2),
.BURSTCOUNT_WIDTH (1),
.CNTL_ADDRESS_WIDTH (1),
.SUB_WINDOW_COUNT (1),
.MASTER_ADDRESS_DEF (64'b0000000000000000000000000000000000000000000000000000000000000000)
) address_span_extender_0 (
.clk (kernel_clk_clk), // clock.clk
.reset (rst_controller_001_reset_out_reset), // reset.reset
.avs_s0_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // windowed_slave.address
.avs_s0_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.avs_s0_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.avs_s0_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.avs_s0_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.avs_s0_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.avs_s0_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.avs_s0_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.avs_s0_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.avm_m0_address (address_span_extender_0_expanded_master_address), // expanded_master.address
.avm_m0_read (address_span_extender_0_expanded_master_read), // .read
.avm_m0_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.avm_m0_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.avm_m0_write (address_span_extender_0_expanded_master_write), // .write
.avm_m0_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.avm_m0_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.avm_m0_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.avm_m0_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.avs_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // cntl.read
.avs_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.avs_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // .write
.avs_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.avs_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.avs_cntl_address (1'b0) // (terminated)
);
sw_reset #(
.WIDTH (64),
.LOG2_RESET_CYCLES (10)
) sw_reset (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_002_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_sw_reset_s_write), // s.write
.slave_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_sw_reset_s_read), // .read
.slave_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sw_reset_n_out (sw_reset_export_reset_n) // sw_reset.reset_n
);
altera_avalon_mm_bridge #(
.DATA_WIDTH (32),
.SYMBOL_WIDTH (8),
.HDL_ADDR_WIDTH (14),
.BURSTCOUNT_WIDTH (1),
.PIPELINE_COMMAND (1),
.PIPELINE_RESPONSE (1)
) kernel_cntrl (
.clk (clk_clk), // clk.clk
.reset (rst_controller_reset_out_reset), // reset.reset
.s0_waitrequest (kernel_cntrl_waitrequest), // s0.waitrequest
.s0_readdata (kernel_cntrl_readdata), // .readdata
.s0_readdatavalid (kernel_cntrl_readdatavalid), // .readdatavalid
.s0_burstcount (kernel_cntrl_burstcount), // .burstcount
.s0_writedata (kernel_cntrl_writedata), // .writedata
.s0_address (kernel_cntrl_address), // .address
.s0_write (kernel_cntrl_write), // .write
.s0_read (kernel_cntrl_read), // .read
.s0_byteenable (kernel_cntrl_byteenable), // .byteenable
.s0_debugaccess (kernel_cntrl_debugaccess), // .debugaccess
.m0_waitrequest (kernel_cntrl_m0_waitrequest), // m0.waitrequest
.m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.m0_address (kernel_cntrl_m0_address), // .address
.m0_write (kernel_cntrl_m0_write), // .write
.m0_read (kernel_cntrl_m0_read), // .read
.m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.m0_debugaccess (kernel_cntrl_m0_debugaccess) // .debugaccess
);
mem_org_mode #(
.WIDTH (32)
) mem_org_mode (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_mem_org_mode_s_write), // s.write
.slave_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.slave_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.slave_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.mem_organization_kernel (acl_bsp_memorg_kernel_mode), // mem_organization_kernel.mode
.mem_organization_host (acl_bsp_memorg_host_mode) // mem_organization_host.mode
);
altera_irq_bridge #(
.IRQ_WIDTH (1)
) irq_bridge_0 (
.clk (kernel_clk_clk), // clk.clk
.receiver_irq (kernel_irq_from_kernel_irq), // receiver_irq.irq
.reset (reset_controller_sw_reset_out_reset), // clk_reset.reset
.sender0_irq (irq_mapper_receiver0_irq), // sender0_irq.irq
.sender1_irq (), // (terminated)
.sender2_irq (), // (terminated)
.sender3_irq (), // (terminated)
.sender4_irq (), // (terminated)
.sender5_irq (), // (terminated)
.sender6_irq (), // (terminated)
.sender7_irq (), // (terminated)
.sender8_irq (), // (terminated)
.sender9_irq (), // (terminated)
.sender10_irq (), // (terminated)
.sender11_irq (), // (terminated)
.sender12_irq (), // (terminated)
.sender13_irq (), // (terminated)
.sender14_irq (), // (terminated)
.sender15_irq (), // (terminated)
.sender16_irq (), // (terminated)
.sender17_irq (), // (terminated)
.sender18_irq (), // (terminated)
.sender19_irq (), // (terminated)
.sender20_irq (), // (terminated)
.sender21_irq (), // (terminated)
.sender22_irq (), // (terminated)
.sender23_irq (), // (terminated)
.sender24_irq (), // (terminated)
.sender25_irq (), // (terminated)
.sender26_irq (), // (terminated)
.sender27_irq (), // (terminated)
.sender28_irq (), // (terminated)
.sender29_irq (), // (terminated)
.sender30_irq (), // (terminated)
.sender31_irq () // (terminated)
);
version_id #(
.WIDTH (32),
.VERSION_ID (-1598029823)
) version_id_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_read (mm_interconnect_1_version_id_0_s_read), // s.read
.slave_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) reset_controller_sw (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (~sw_reset_export_reset_n), // reset_in1.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (reset_controller_sw_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
irq_ena irq_ena_0 (
.clk (clk_clk), // clk.clk
.resetn (~rst_controller_reset_out_reset), // clk_reset.reset_n
.slave_write (mm_interconnect_1_irq_ena_0_s_write), // s.write
.slave_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.slave_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.slave_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.slave_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.slave_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.irq (irq_ena_0_my_irq_in_irq), // my_irq_in.irq
.irq_out (kernel_irq_to_host_irq) // my_irq_out.irq
);
system_acl_iface_acl_kernel_interface_mm_interconnect_0 mm_interconnect_0 (
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cra_reset_reset_bridge_in_reset_reset (reset_controller_sw_reset_out_reset), // kernel_cra_reset_reset_bridge_in_reset.reset
.address_span_extender_0_expanded_master_address (address_span_extender_0_expanded_master_address), // address_span_extender_0_expanded_master.address
.address_span_extender_0_expanded_master_waitrequest (address_span_extender_0_expanded_master_waitrequest), // .waitrequest
.address_span_extender_0_expanded_master_burstcount (address_span_extender_0_expanded_master_burstcount), // .burstcount
.address_span_extender_0_expanded_master_byteenable (address_span_extender_0_expanded_master_byteenable), // .byteenable
.address_span_extender_0_expanded_master_read (address_span_extender_0_expanded_master_read), // .read
.address_span_extender_0_expanded_master_readdata (address_span_extender_0_expanded_master_readdata), // .readdata
.address_span_extender_0_expanded_master_readdatavalid (address_span_extender_0_expanded_master_readdatavalid), // .readdatavalid
.address_span_extender_0_expanded_master_write (address_span_extender_0_expanded_master_write), // .write
.address_span_extender_0_expanded_master_writedata (address_span_extender_0_expanded_master_writedata), // .writedata
.kernel_cra_s0_address (mm_interconnect_0_kernel_cra_s0_address), // kernel_cra_s0.address
.kernel_cra_s0_write (mm_interconnect_0_kernel_cra_s0_write), // .write
.kernel_cra_s0_read (mm_interconnect_0_kernel_cra_s0_read), // .read
.kernel_cra_s0_readdata (mm_interconnect_0_kernel_cra_s0_readdata), // .readdata
.kernel_cra_s0_writedata (mm_interconnect_0_kernel_cra_s0_writedata), // .writedata
.kernel_cra_s0_burstcount (mm_interconnect_0_kernel_cra_s0_burstcount), // .burstcount
.kernel_cra_s0_byteenable (mm_interconnect_0_kernel_cra_s0_byteenable), // .byteenable
.kernel_cra_s0_readdatavalid (mm_interconnect_0_kernel_cra_s0_readdatavalid), // .readdatavalid
.kernel_cra_s0_waitrequest (mm_interconnect_0_kernel_cra_s0_waitrequest), // .waitrequest
.kernel_cra_s0_debugaccess (mm_interconnect_0_kernel_cra_s0_debugaccess) // .debugaccess
);
system_acl_iface_acl_kernel_interface_mm_interconnect_1 mm_interconnect_1 (
.clk_reset_clk_clk (clk_clk), // clk_reset_clk.clk
.kernel_clk_out_clk_clk (kernel_clk_clk), // kernel_clk_out_clk.clk
.address_span_extender_0_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset), // address_span_extender_0_reset_reset_bridge_in_reset.reset
.kernel_cntrl_reset_reset_bridge_in_reset_reset (rst_controller_reset_out_reset), // kernel_cntrl_reset_reset_bridge_in_reset.reset
.sw_reset_clk_reset_reset_bridge_in_reset_reset (rst_controller_002_reset_out_reset), // sw_reset_clk_reset_reset_bridge_in_reset.reset
.kernel_cntrl_m0_address (kernel_cntrl_m0_address), // kernel_cntrl_m0.address
.kernel_cntrl_m0_waitrequest (kernel_cntrl_m0_waitrequest), // .waitrequest
.kernel_cntrl_m0_burstcount (kernel_cntrl_m0_burstcount), // .burstcount
.kernel_cntrl_m0_byteenable (kernel_cntrl_m0_byteenable), // .byteenable
.kernel_cntrl_m0_read (kernel_cntrl_m0_read), // .read
.kernel_cntrl_m0_readdata (kernel_cntrl_m0_readdata), // .readdata
.kernel_cntrl_m0_readdatavalid (kernel_cntrl_m0_readdatavalid), // .readdatavalid
.kernel_cntrl_m0_write (kernel_cntrl_m0_write), // .write
.kernel_cntrl_m0_writedata (kernel_cntrl_m0_writedata), // .writedata
.kernel_cntrl_m0_debugaccess (kernel_cntrl_m0_debugaccess), // .debugaccess
.address_span_extender_0_cntl_write (mm_interconnect_1_address_span_extender_0_cntl_write), // address_span_extender_0_cntl.write
.address_span_extender_0_cntl_read (mm_interconnect_1_address_span_extender_0_cntl_read), // .read
.address_span_extender_0_cntl_readdata (mm_interconnect_1_address_span_extender_0_cntl_readdata), // .readdata
.address_span_extender_0_cntl_writedata (mm_interconnect_1_address_span_extender_0_cntl_writedata), // .writedata
.address_span_extender_0_cntl_byteenable (mm_interconnect_1_address_span_extender_0_cntl_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_address (mm_interconnect_1_address_span_extender_0_windowed_slave_address), // address_span_extender_0_windowed_slave.address
.address_span_extender_0_windowed_slave_write (mm_interconnect_1_address_span_extender_0_windowed_slave_write), // .write
.address_span_extender_0_windowed_slave_read (mm_interconnect_1_address_span_extender_0_windowed_slave_read), // .read
.address_span_extender_0_windowed_slave_readdata (mm_interconnect_1_address_span_extender_0_windowed_slave_readdata), // .readdata
.address_span_extender_0_windowed_slave_writedata (mm_interconnect_1_address_span_extender_0_windowed_slave_writedata), // .writedata
.address_span_extender_0_windowed_slave_burstcount (mm_interconnect_1_address_span_extender_0_windowed_slave_burstcount), // .burstcount
.address_span_extender_0_windowed_slave_byteenable (mm_interconnect_1_address_span_extender_0_windowed_slave_byteenable), // .byteenable
.address_span_extender_0_windowed_slave_readdatavalid (mm_interconnect_1_address_span_extender_0_windowed_slave_readdatavalid), // .readdatavalid
.address_span_extender_0_windowed_slave_waitrequest (mm_interconnect_1_address_span_extender_0_windowed_slave_waitrequest), // .waitrequest
.irq_ena_0_s_write (mm_interconnect_1_irq_ena_0_s_write), // irq_ena_0_s.write
.irq_ena_0_s_read (mm_interconnect_1_irq_ena_0_s_read), // .read
.irq_ena_0_s_readdata (mm_interconnect_1_irq_ena_0_s_readdata), // .readdata
.irq_ena_0_s_writedata (mm_interconnect_1_irq_ena_0_s_writedata), // .writedata
.irq_ena_0_s_byteenable (mm_interconnect_1_irq_ena_0_s_byteenable), // .byteenable
.irq_ena_0_s_waitrequest (mm_interconnect_1_irq_ena_0_s_waitrequest), // .waitrequest
.mem_org_mode_s_write (mm_interconnect_1_mem_org_mode_s_write), // mem_org_mode_s.write
.mem_org_mode_s_read (mm_interconnect_1_mem_org_mode_s_read), // .read
.mem_org_mode_s_readdata (mm_interconnect_1_mem_org_mode_s_readdata), // .readdata
.mem_org_mode_s_writedata (mm_interconnect_1_mem_org_mode_s_writedata), // .writedata
.mem_org_mode_s_waitrequest (mm_interconnect_1_mem_org_mode_s_waitrequest), // .waitrequest
.sw_reset_s_write (mm_interconnect_1_sw_reset_s_write), // sw_reset_s.write
.sw_reset_s_read (mm_interconnect_1_sw_reset_s_read), // .read
.sw_reset_s_readdata (mm_interconnect_1_sw_reset_s_readdata), // .readdata
.sw_reset_s_writedata (mm_interconnect_1_sw_reset_s_writedata), // .writedata
.sw_reset_s_byteenable (mm_interconnect_1_sw_reset_s_byteenable), // .byteenable
.sw_reset_s_waitrequest (mm_interconnect_1_sw_reset_s_waitrequest), // .waitrequest
.sys_description_rom_s1_address (mm_interconnect_1_sys_description_rom_s1_address), // sys_description_rom_s1.address
.sys_description_rom_s1_write (mm_interconnect_1_sys_description_rom_s1_write), // .write
.sys_description_rom_s1_readdata (mm_interconnect_1_sys_description_rom_s1_readdata), // .readdata
.sys_description_rom_s1_writedata (mm_interconnect_1_sys_description_rom_s1_writedata), // .writedata
.sys_description_rom_s1_byteenable (mm_interconnect_1_sys_description_rom_s1_byteenable), // .byteenable
.sys_description_rom_s1_chipselect (mm_interconnect_1_sys_description_rom_s1_chipselect), // .chipselect
.sys_description_rom_s1_clken (mm_interconnect_1_sys_description_rom_s1_clken), // .clken
.sys_description_rom_s1_debugaccess (mm_interconnect_1_sys_description_rom_s1_debugaccess), // .debugaccess
.version_id_0_s_read (mm_interconnect_1_version_id_0_s_read), // version_id_0_s.read
.version_id_0_s_readdata (mm_interconnect_1_version_id_0_s_readdata) // .readdata
);
system_irq_mapper irq_mapper (
.clk (), // clk.clk
.reset (), // clk_reset.reset
.receiver0_irq (irq_mapper_receiver0_irq), // receiver0.irq
.sender_irq (irq_ena_0_my_irq_in_irq) // sender.irq
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (1),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_reset_out_reset), // reset_out.reset
.reset_req (rst_controller_reset_out_reset_req), // .reset_req
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (1),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_001 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.clk (kernel_clk_clk), // clk.clk
.reset_out (rst_controller_001_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_in1 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
altera_reset_controller #(
.NUM_RESET_INPUTS (2),
.OUTPUT_RESET_SYNC_EDGES ("deassert"),
.SYNC_DEPTH (2),
.RESET_REQUEST_PRESENT (0),
.RESET_REQ_WAIT_TIME (1),
.MIN_RST_ASSERTION_TIME (3),
.RESET_REQ_EARLY_DSRT_TIME (1),
.USE_RESET_REQUEST_IN0 (0),
.USE_RESET_REQUEST_IN1 (0),
.USE_RESET_REQUEST_IN2 (0),
.USE_RESET_REQUEST_IN3 (0),
.USE_RESET_REQUEST_IN4 (0),
.USE_RESET_REQUEST_IN5 (0),
.USE_RESET_REQUEST_IN6 (0),
.USE_RESET_REQUEST_IN7 (0),
.USE_RESET_REQUEST_IN8 (0),
.USE_RESET_REQUEST_IN9 (0),
.USE_RESET_REQUEST_IN10 (0),
.USE_RESET_REQUEST_IN11 (0),
.USE_RESET_REQUEST_IN12 (0),
.USE_RESET_REQUEST_IN13 (0),
.USE_RESET_REQUEST_IN14 (0),
.USE_RESET_REQUEST_IN15 (0),
.ADAPT_RESET_REQUEST (0)
) rst_controller_002 (
.reset_in0 (~reset_reset_n), // reset_in0.reset
.reset_in1 (sw_reset_in_reset), // reset_in1.reset
.clk (clk_clk), // clk.clk
.reset_out (rst_controller_002_reset_out_reset), // reset_out.reset
.reset_req (), // (terminated)
.reset_req_in0 (1'b0), // (terminated)
.reset_req_in1 (1'b0), // (terminated)
.reset_in2 (1'b0), // (terminated)
.reset_req_in2 (1'b0), // (terminated)
.reset_in3 (1'b0), // (terminated)
.reset_req_in3 (1'b0), // (terminated)
.reset_in4 (1'b0), // (terminated)
.reset_req_in4 (1'b0), // (terminated)
.reset_in5 (1'b0), // (terminated)
.reset_req_in5 (1'b0), // (terminated)
.reset_in6 (1'b0), // (terminated)
.reset_req_in6 (1'b0), // (terminated)
.reset_in7 (1'b0), // (terminated)
.reset_req_in7 (1'b0), // (terminated)
.reset_in8 (1'b0), // (terminated)
.reset_req_in8 (1'b0), // (terminated)
.reset_in9 (1'b0), // (terminated)
.reset_req_in9 (1'b0), // (terminated)
.reset_in10 (1'b0), // (terminated)
.reset_req_in10 (1'b0), // (terminated)
.reset_in11 (1'b0), // (terminated)
.reset_req_in11 (1'b0), // (terminated)
.reset_in12 (1'b0), // (terminated)
.reset_req_in12 (1'b0), // (terminated)
.reset_in13 (1'b0), // (terminated)
.reset_req_in13 (1'b0), // (terminated)
.reset_in14 (1'b0), // (terminated)
.reset_req_in14 (1'b0), // (terminated)
.reset_in15 (1'b0), // (terminated)
.reset_req_in15 (1'b0) // (terminated)
);
assign kernel_reset_reset_n = ~reset_controller_sw_reset_out_reset;
endmodule
|
module DC_8_databanks #(parameter Width = 36, Size =512, Forward=0, REQ_BITS=7)
// 36 bit data per data bank= 32 bit data+4 bit valid bits
//tag 10+counter 2[19,20]+states 3[21,22,23] =15 for tag bank
//data bank gets pos+ data to write or output data from read
(
input clk
,input reset
,input req_valid
,input write
,input [2:0] bank_sel
,input ack_retry
,input [2:0] way
,input row_even_odd
,input[4:0] req_Index
,input [35:0] req_data //32 bit data+4 bit valid bit
,input [4:0] Load_req
,input Load_req_valid
,output Load_req_retry
,input [6:0] STD_req
,input STD_req_valid
,output STD_req_retry
,input write_musk_reset //when Invalidate
,output ack_valid
,output req_retry
,output [35:0] ack_data //64 bit data output for sign extension
);
logic [4:0] req_Index_add_to_1_bank;
assign req_Index_add_to_1_bank= req_Index;
logic [35:0] req_data_bank=req_data;
logic bank_sel0,write_bank;
logic bank_sel1,bank_sel2,bank_sel3,bank_sel4,bank_sel5,bank_sel6,bank_sel7;
logic [2:0] bank_sel_8bank;
assign bank_sel_8bank=bank_sel;
assign write_bank=write;
always@(bank_sel) begin
bank_sel_8bank=bank_sel;//3 bit select for 8 banks in a bank;VA[1:0] byte selection
end
always@(bank_sel_8bank) begin
case(bank_sel_8bank)
0: begin bank_sel0=1;bank_sel1=0;;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
1: begin bank_sel0=0;bank_sel1=1;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
2: begin bank_sel0=0;bank_sel1=0;bank_sel2=1;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
3: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=1;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
4: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=1;bank_sel5=0;bank_sel6=0;bank_sel7=0;end
5: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=1;bank_sel6=0;bank_sel7=0;end
6: begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=1;bank_sel7=0;end
7:begin bank_sel0=0;bank_sel1=0;bank_sel2=0;bank_sel3=0;bank_sel4=0;bank_sel5=0;bank_sel6=0;bank_sel7=1;end
endcase
end
DC_1_databank #(.Width(Width), .Size(Size))
databank0 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel0)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank1 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel1)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank2 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel2)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank3 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel3)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank4 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel4)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank5(
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel5)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
DC_1_databank #(.Width(Width), .Size(Size))
databank6 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel6)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);DC_1_databank #(.Width(Width), .Size(Size))
databank7 (
.clk (clk)
,.reset (reset)
,.req_valid (req_valid)
,.req_retry (req_retry)
,.write (write_bank)//we=0 for read
,.way_no (way)
,.row_even_odd (row_even_odd)
,.req_Index (req_Index_add_to_1_bank)//search for Tag only while reading
,.req_data (req_data_bank)//data+4 bit valid
,.Load_req (Load_req)
,.Load_req_valid(Load_req_valid)
,.Load_req_retry(Load_req_retry)
,.STD_req(STD_req)
,.STD_req_valid(STD_req_valid)
,.STD_req_retry(STD_req_retry)
,.write_musk_reset(write_musk_reset)
,.ack_valid (ack_valid)
,.bank_sel (bank_sel7)//bank0 is the signal connected to enable bank0
,.ack_retry (ack_retry)
,.ack_data (ack_data)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V
/**
* and4: 4-input AND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__and4 (
X ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out_X , A, B, C, D );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4_FUNCTIONAL_PP_V |
///////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2014 Francis Bruno, All Rights Reserved
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 3 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but
// WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
// or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License along with
// this program; if not, see <http://www.gnu.org/licenses>.
//
// This code is available under licenses for commercial use. Please contact
// Francis Bruno for more information.
//
// http://www.gplgpu.com
// http://www.asicsolutions.com
//
// Title : CRT Registers decoding logic
// File : crt_reg_dec.v
// Author : Frank Bruno
// Created : 29-Dec-2005
// RCS File : $Source:$
// Status : $Id:$
//
///////////////////////////////////////////////////////////////////////////////
//
// Description :
// This module does rd/wr decoding for CR registers.
// The decoding supports 16-bit and 8-bit writes.
//
//////////////////////////////////////////////////////////////////////////////
//
// Modules Instantiated:
//
///////////////////////////////////////////////////////////////////////////////
//
// Modification History:
//
// $Log:$
//
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ns / 10 ps
module crt_reg_dec
(
input h_reset_n,
input h_iord,
input h_iowr,
input h_hclk,
input h_io_16,
input h_io_8,
input misc_b0, // 0- 3bx, 1- 3dx
input h_dec_3bx,
input h_dec_3cx,
input h_dec_3dx,
input m_dec_sr07,
input m_dec_sr00_sr06,
input [15:0] h_io_addr,
input [15:0] h_io_dbus,
output [7:0] crtc_index, // crtc index register
output reg [7:0] ext_index, // extension index register
output trim_wr, // delayed write strobe to load data reg
output c_gr_ext_en,
output [3:0] c_ext_index_b,
output crt_mod_rd_en_hb,
output crt_mod_rd_en_lb,
output c_ready_n,
output sr_00_06_wr, // any iowrite to 3C5 index = 00 thru 06.
output sr07_wr,
output cr24_rd,
output cr26_rd,
output c_dec_3ba_or_3da,
output c_cr0c_f13_22_hit
);
reg [7:0] int_io_dbus;
reg [5:0] store_index;
reg rd_or_wr_d;
reg h_iowr_d; // h_iowr is delayed by one h_hclk
wire fcr_rd, fcr_wr; // for generating ready_n
wire ins0_rd, ins1_rd;
wire crt_index_hit;
wire ext_index_hit;
wire crt_reg_hit;
wire crt_index_wr;
wire crt_reg_en;
wire crt_index_rd;
wire rd_or_wr;
wire dec_3bx_or_3dx;
wire cr_reg_hit;
wire crt_io_hit_hb;
wire crt_io_hit_lb;
wire index_from_crtc;
wire addr_sel = misc_b0;
// Instantiating crtc index registers
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) begin
store_index <= 6'h0;
ext_index <= 8'h0;
end else if (h_iowr) begin
if (crt_index_hit) store_index <= h_io_dbus[5:0];
if (ext_index_hit) ext_index <= {4'b0, h_io_dbus[3:0]};
end
assign crtc_index = {2'b0, store_index};
assign c_ext_index_b[3:0] = ext_index[3:0];
assign c_gr_ext_en = 1'b1;
// We need to delay h_iowr signal by one h_hclk to support 16 bit writing.
// To avoid wr glitches, we first write into index register(lower byte) and
// then with one h_hclk delay, data will be written into the data
// register(upper byte). During one h_hclk delay, the decoder output will
// become stable and clean.
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) h_iowr_d <= 1'b0;
else h_iowr_d <= h_iowr;
// iowrite pulse for data register writes.
assign trim_wr = h_iowr & h_iowr_d;
assign crt_index_hit = addr_sel ? (h_io_addr == 16'h3d4) :
(h_io_addr == 16'h3b4);
assign crt_reg_hit = addr_sel ? (h_io_addr == 16'h3d5) :
(h_io_addr == 16'h3b5);
assign crt_index_wr = crt_index_hit & h_iowr;
assign crt_index_rd = crt_index_hit & h_iord;
assign crt_reg_en = ( (crt_index_hit & h_io_16) | crt_reg_hit );
assign cr24_rd = (crtc_index == 36) & h_iord;
assign cr26_rd = (crtc_index == 38) & h_iord;
// Decode for Extension registers
assign ext_index_hit = (h_io_addr == 16'h3ce) ;
// Write into extension index register when ext_index_hit is true and h_iowr
// is true.
// The password must be set before any writes can take place to the
// extension data registers.
assign sr_00_06_wr = m_dec_sr00_sr06 & h_iowr;
assign sr07_wr = m_dec_sr07 & h_iowr;
assign dec_3bx_or_3dx = h_dec_3bx | h_dec_3dx;
// Generating crt_io_hit by checking that the address range falls into one
// of the IO register of crt module
assign cr_reg_hit = crt_reg_en
& ( ((crtc_index >= 8'h00) & (crtc_index <= 8'h0b))
| ((crtc_index >= 8'h10) & (crtc_index <= 8'h18) &
(crtc_index != 8'h13)) );
assign crt_io_hit_hb = cr_reg_hit;
// Lower byte bus is enabled for all 16-bit operations and even addressed
// 8-bit operations.
// Whenever there is a read for er30 to er39, cr0c to cr0f, cr13, cr24 , cr26
// and if that is 16-bit operation, index has to come from crtc module.
// crt_index_hit & h_io_8 - 8-bit read to CR index register
// ext_index_hit & h_io_8 - 8-bit read to ER index register
// 3CC: misc rd or write
assign c_dec_3ba_or_3da = addr_sel ? (h_io_addr == 16'h03da) :
(h_io_addr == 16'h03ba);
assign fcr_wr = c_dec_3ba_or_3da & h_iowr;
assign fcr_rd = (h_io_addr == 16'h03ca) & h_iord;
assign ins0_rd = (h_io_addr == 16'h03c2) & h_iord;
assign ins1_rd = c_dec_3ba_or_3da & h_iord;
assign crt_io_hit_lb = (h_io_addr == 16'h3cc & h_iord) |
(h_io_addr == 16'h3c2 & h_iowr) |
ins0_rd | ins1_rd |
fcr_rd | fcr_wr |
(ext_index_hit & (h_io_16 | h_io_8)) |
(crt_index_hit & (h_io_16 | h_io_8));
// delay (h_iowr | h_iord) by one h_hclk and then give it out as c_ready_n
assign rd_or_wr = h_iowr | h_iord;
always @(posedge h_hclk or negedge h_reset_n)
if (!h_reset_n) rd_or_wr_d <= 1'b0;
else rd_or_wr_d <= rd_or_wr;
assign c_ready_n = (~(rd_or_wr_d & (crt_io_hit_hb |
crt_io_hit_lb)));
// Decoding for io hit for any of cr00 to cr0b, cr10 to cr18, misc, ins0,
// ins1 and fcr .
assign crt_mod_rd_en_hb = crt_io_hit_hb & h_iord;
assign crt_mod_rd_en_lb = (crt_io_hit_lb |
(index_from_crtc & h_io_16)) & h_iord;
// Decoding for io hit for any of cr0c to cr0f or cr13
assign c_cr0c_f13_22_hit = crt_reg_en & ( ((crtc_index >= 8'h0c) &
(crtc_index <= 8'h0f))
| (crtc_index == 19)
| (crtc_index == 34));
assign index_from_crtc = c_cr0c_f13_22_hit |
cr24_rd | cr26_rd ;
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: FIFO_ADC.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_ADC (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q);
input clock;
input [15:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [15:0] q;
wire sub_wire0;
wire sub_wire1;
wire [15:0] sub_wire2;
wire empty = sub_wire0;
wire full = sub_wire1;
wire [15:0] q = sub_wire2[15:0];
scfifo scfifo_component (
.clock (clock),
.data (data),
.rdreq (rdreq),
.sclr (sclr),
.wrreq (wrreq),
.empty (sub_wire0),
.full (sub_wire1),
.q (sub_wire2),
.aclr (),
.almost_empty (),
.almost_full (),
.usedw ());
defparam
scfifo_component.add_ram_output_register = "ON",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = 16,
scfifo_component.lpm_showahead = "OFF",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = 16,
scfifo_component.lpm_widthu = 4,
scfifo_component.overflow_checking = "ON",
scfifo_component.underflow_checking = "ON",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "16"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "1"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "0"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "16"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "ON"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL "data[15..0]"
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL "sclr"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ADC.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ADC.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ADC.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ADC.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ADC_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_ADC_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_V
/**
* lsbufiso0p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso0p (
X ,
SLEEP,
A
);
// Module ports
output X ;
input SLEEP;
input A ;
// Module supplies
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire sleepb ;
wire and0_out_X;
// Name Output Other arguments
not not0 (sleepb , SLEEP );
and and0 (and0_out_X, sleepb, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , and0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO0P_BEHAVIORAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__UDP_DFF_PS_PP_PG_N_TB_V
`define SKY130_FD_SC_LP__UDP_DFF_PS_PP_PG_N_TB_V
/**
* udp_dff$PS_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__udp_dff_ps_pp_pg_n.v"
module top();
// Inputs are registered
reg D;
reg SET;
reg NOTIFIER;
reg VPWR;
reg VGND;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
NOTIFIER = 1'bX;
SET = 1'bX;
VGND = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 NOTIFIER = 1'b0;
#60 SET = 1'b0;
#80 VGND = 1'b0;
#100 VPWR = 1'b0;
#120 D = 1'b1;
#140 NOTIFIER = 1'b1;
#160 SET = 1'b1;
#180 VGND = 1'b1;
#200 VPWR = 1'b1;
#220 D = 1'b0;
#240 NOTIFIER = 1'b0;
#260 SET = 1'b0;
#280 VGND = 1'b0;
#300 VPWR = 1'b0;
#320 VPWR = 1'b1;
#340 VGND = 1'b1;
#360 SET = 1'b1;
#380 NOTIFIER = 1'b1;
#400 D = 1'b1;
#420 VPWR = 1'bx;
#440 VGND = 1'bx;
#460 SET = 1'bx;
#480 NOTIFIER = 1'bx;
#500 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_lp__udp_dff$PS_pp$PG$N dut (.D(D), .SET(SET), .NOTIFIER(NOTIFIER), .VPWR(VPWR), .VGND(VGND), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__UDP_DFF_PS_PP_PG_N_TB_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_1_V
`define SKY130_FD_SC_LP__O21BA_1_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_1 (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_1_V
|
/*
* Copyright 2010, Aleksander Osman, [email protected]. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are
* permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of
* conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice, this list
* of conditions and the following disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module serial_txd(
input CLK_I,
input RST_I,
//slave
input [7:0] DAT_I,
output reg ACK_O,
input CYC_I,
input STB_I,
input WE_I,
//serial output
input uart_rxd,
input uart_rts,
output reg uart_txd,
output uart_cts
);
assign uart_cts = uart_rts;
reg [12:0] counter;
always @(posedge CLK_I) begin
if(RST_I == 1'b1) begin
ACK_O <= 1'b0;
uart_txd <= 1'b1;
counter <= 13'd0;
end
else if(CYC_I == 1'b1 && STB_I == 1'b1 && WE_I == 1'b1 && ACK_O == 1'b0) begin
if(counter < 13'd8191) counter <= counter + 13'd1;
if(counter < 434*1) uart_txd <= 1'b0;
else if(counter < 434*2) uart_txd <= DAT_I[0];
else if(counter < 434*3) uart_txd <= DAT_I[1];
else if(counter < 434*4) uart_txd <= DAT_I[2];
else if(counter < 434*5) uart_txd <= DAT_I[3];
else if(counter < 434*6) uart_txd <= DAT_I[4];
else if(counter < 434*7) uart_txd <= DAT_I[5];
else if(counter < 434*8) uart_txd <= DAT_I[6];
else if(counter < 434*9) uart_txd <= DAT_I[7];
else if(counter < 434*10) uart_txd <= 1'b1;
else begin
uart_txd <= 1'b1;
ACK_O <= 1'b1;
end
end
else begin
ACK_O <= 1'b0;
uart_txd <= 1'b1;
counter <= 13'd0;
end
end
endmodule
|
//
// rcv.v -- serial line receiver
//
module rcv(clk, reset, full, parallel_out, serial_in);
input clk;
input reset;
output reg full;
output [7:0] parallel_out;
input serial_in;
reg serial_p;
reg serial_s;
reg [3:0] state;
reg [8:0] shift;
reg [10:0] count;
assign parallel_out[7:0] = shift[7:0];
always @(posedge clk) begin
serial_p <= serial_in;
serial_s <= serial_p;
end
always @(posedge clk) begin
if (reset == 1) begin
state <= 4'h0;
full <= 0;
end else begin
if (state == 4'h0) begin
full <= 0;
if (serial_s == 0) begin
state <= 4'h1;
count <= 651;
end
end else
if (state == 4'hb) begin
state <= 4'h0;
full <= 1;
end else begin
if (count == 0) begin
state <= state + 1;
shift[8:0] <= { serial_s, shift[8:1] };
count <= 1302;
end else begin
count <= count - 1;
end
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////////////
//// ////
//// FPU ////
//// Floating Point Unit (Double precision) ////
//// ////
//// Author: David Lundgren ////
//// [email protected] ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2009 David Lundgren ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
// rmode = 00 (nearest), 01 (to zero), 10 (+ infinity), 11 (- infinity)
`timescale 1ns / 100ps
module fpu_mul( clk, rst, enable, rmode, opa, opb, ready, outfp);
input clk;
input rst;
input enable;
input [1:0] rmode;
input [63:0] opa, opb;
output ready;
output [63:0] outfp;
/* verilator lint_off WIDTH */
reg product_shift;
reg [1:0] rm_1, rm_2, rm_3, rm_4, rm_5, rm_6, rm_7, rm_8, rm_9;
reg [1:0] rm_10, rm_11, rm_12, rm_13, rm_14, rm_15;
reg sign, sign_1, sign_2, sign_3, sign_4, sign_5, sign_6, sign_7, sign_8;
reg sign_9, sign_10, sign_11, sign_12, sign_13, sign_14, sign_15, sign_16, sign_17;
reg sign_18, sign_19, sign_20;
reg [51:0] mantissa_a1, mantissa_a2;
reg [51:0] mantissa_b1, mantissa_b2;
reg [10:0] exponent_a;
reg [10:0] exponent_b;
reg ready, count_ready, count_ready_0;
reg [4:0] count;
reg a_is_zero, b_is_zero, a_is_inf, b_is_inf, in_inf_1, in_inf_2;
reg in_zero_1;
reg [11:0] exponent_terms_1, exponent_terms_2, exponent_terms_3, exponent_terms_4;
reg [11:0] exponent_terms_5, exponent_terms_6, exponent_terms_7;
reg [11:0] exponent_terms_8, exponent_terms_9;
reg exponent_gt_expoffset;
reg [11:0] exponent_1;
wire [11:0] exponent = 0;
reg [11:0] exponent_2, exponent_2_0, exponent_2_1;
reg exponent_gt_prodshift, exponent_is_infinity;
reg [11:0] exponent_3, exponent_4;
reg set_mantissa_zero, set_mz_1;
reg [52:0] mul_a, mul_a1, mul_a2, mul_a3, mul_a4, mul_a5, mul_a6, mul_a7, mul_a8;
reg [52:0] mul_b, mul_b1, mul_b2, mul_b3, mul_b4, mul_b5, mul_b6, mul_b7, mul_b8;
reg [40:0] product_a;
reg [16:0] product_a_2, product_a_3, product_a_4, product_a_5, product_a_6;
reg [16:0] product_a_7, product_a_8, product_a_9, product_a_10;
reg [40:0] product_b;
reg [40:0] product_c;
reg [25:0] product_d;
reg [33:0] product_e;
reg [33:0] product_f;
reg [35:0] product_g;
reg [28:0] product_h;
reg [28:0] product_i;
reg [30:0] product_j;
reg [41:0] sum_0;
reg [6:0] sum_0_2, sum_0_3, sum_0_4, sum_0_5, sum_0_6, sum_0_7, sum_0_8, sum_0_9;
reg [35:0] sum_1;
reg [9:0] sum_1_2, sum_1_3, sum_1_4, sum_1_5, sum_1_6, sum_1_7, sum_1_8;
reg [41:0] sum_2;
reg [6:0] sum_2_2, sum_2_3, sum_2_4, sum_2_5, sum_2_6, sum_2_7;
reg [35:0] sum_3;
reg [36:0] sum_4;
reg [9:0] sum_4_2, sum_4_3, sum_4_4, sum_4_5;
reg [27:0] sum_5;
reg [6:0] sum_5_2, sum_5_3, sum_5_4;
reg [29:0] sum_6;
reg [36:0] sum_7;
reg [16:0] sum_7_2;
reg [30:0] sum_8;
reg [105:0] product;
reg [105:0] product_1;
reg [52:0] product_2, product_3;
reg [53:0] product_4, product_5, product_6, product_7;
reg product_overflow;
reg [11:0] exponent_5, exponent_6, exponent_7, exponent_8, exponent_9;
reg round_nearest_mode, round_posinf_mode, round_neginf_mode;
reg round_nearest_trigger, round_nearest_exception;
reg round_nearest_enable, round_posinf_trigger, round_posinf_enable;
reg round_neginf_trigger, round_neginf_enable, round_enable;
wire [63:0] outfp = { sign, exponent_9[10:0], product_7[51:0]};
always @(posedge clk, posedge rst)
begin
if (rst) begin
sign <= 0; sign_1 <= 0; sign_2 <= 0; sign_3 <= 0; sign_4 <= 0;
sign_5 <= 0; sign_6 <= 0; sign_7 <= 0; sign_8 <= 0; sign_9 <= 0;
sign_10 <= 0; sign_11 <= 0; sign_12 <= 0; sign_13 <= 0;
sign_14 <= 0; sign_15 <= 0; sign_16 <= 0; sign_17 <= 0; sign_18 <= 0; sign_19 <= 0;
sign_20 <= 0; mantissa_a1 <= 0; mantissa_b1 <= 0; mantissa_a2 <= 0; mantissa_b2 <= 0;
exponent_a <= 0; exponent_b <= 0; rm_1 <= 0; rm_2 <= 0; rm_3 <= 0; rm_4 <= 0; rm_5 <= 0;
rm_6 <= 0; rm_7 <= 0; rm_8 <= 0; rm_9 <= 0; rm_10 <= 0; rm_11 <= 0;
rm_12 <= 0; rm_13 <= 0; rm_14 <= 0; rm_15 <= 0;
a_is_zero <= 0; b_is_zero <= 0; a_is_inf <= 0; b_is_inf <= 0; in_inf_1 <= 0; in_inf_2 <= 0;
in_zero_1 <= 0; exponent_terms_1 <= 0; exponent_terms_2 <= 0; exponent_terms_3 <= 0;
exponent_terms_4 <= 0; exponent_terms_5 <= 0; exponent_terms_6 <= 0; exponent_terms_7 <= 0;
exponent_terms_8 <= 0; exponent_terms_9 <= 0; exponent_gt_expoffset <= 0; exponent_1 <= 0;
exponent_2_0 <= 0; exponent_2_1 <= 0; exponent_2 <= 0; exponent_gt_prodshift <= 0;
exponent_is_infinity <= 0; exponent_3 <= 0; exponent_4 <= 0;
set_mantissa_zero <= 0; set_mz_1 <= 0; mul_a <= 0; mul_b <= 0; mul_a1 <= 0; mul_b1 <= 0;
mul_a2 <= 0; mul_b2 <= 0; mul_a3 <= 0; mul_b3 <= 0; mul_a4 <= 0; mul_b4 <= 0; mul_a5 <= 0;
mul_b5 <= 0; mul_a6 <= 0; mul_b6 <= 0; mul_a7 <= 0; mul_b7 <= 0; mul_a8 <= 0; mul_b8 <= 0;
product_a <= 0; product_a_2 <= 0; product_a_3 <= 0; product_a_4 <= 0; product_a_5 <= 0;
product_a_6 <= 0; product_a_7 <= 0; product_a_8 <= 0; product_a_9 <= 0; product_a_10 <= 0;
product_b <= 0; product_c <= 0; product_d <= 0; product_e <= 0; product_f <= 0;
product_g <= 0; product_h <= 0; product_i <= 0; product_j <= 0;
sum_0 <= 0; sum_0_2 <= 0; sum_0_3 <= 0; sum_0_4 <= 0; sum_0_5 <= 0; sum_0_6 <= 0;
sum_0_7 <= 0; sum_0_8 <= 0; sum_0_9 <= 0; sum_1 <= 0; sum_1_2 <= 0; sum_1_3 <= 0; sum_1_4 <= 0;
sum_1_5 <= 0; sum_1_6 <= 0; sum_1_7 <= 0; sum_1_8 <= 0; sum_2 <= 0; sum_2_2 <= 0; sum_2_3 <= 0;
sum_2_4 <= 0; sum_2_5 <= 0; sum_2_6 <= 0; sum_2_7 <= 0; sum_3 <= 0; sum_4 <= 0; sum_4_2 <= 0;
sum_4_3 <= 0; sum_4_4 <= 0; sum_4_5 <= 0; sum_5 <= 0; sum_5_2 <= 0; sum_5_3 <= 0; sum_5_4 <= 0;
sum_6 <= 0; sum_7 <= 0; sum_7_2 <= 0; sum_8 <= 0; product <= 0; product_1 <= 0; product_2 <= 0;
product_3 <= 0; product_4 <= 0; product_5 <= 0; product_overflow <= 0; product_6 <= 0;
exponent_5 <= 0; exponent_6 <= 0; exponent_7 <= 0; exponent_8 <= 0; product_shift <= 0;
product_7 <= 0; exponent_9 <= 0;
round_nearest_mode <= 0; round_posinf_mode <= 0; round_neginf_mode <= 0; round_nearest_trigger <= 0;
round_nearest_exception <= 0; round_nearest_enable <= 0; round_posinf_trigger <= 0; round_posinf_enable <= 0;
round_neginf_trigger <= 0; round_neginf_enable <= 0; round_enable <= 0;
end
else if (enable) begin
sign_1 <= opa[63] ^ opb[63]; sign_2 <= sign_1; sign_3 <= sign_2; sign_4 <= sign_3;
sign_5 <= sign_4; sign_6 <= sign_5; sign_7 <= sign_6; sign_8 <= sign_7; sign_9 <= sign_8;
sign_10 <= sign_9; sign_11 <= sign_10; sign_12 <= sign_11; sign_13 <= sign_12;
sign_14 <= sign_13; sign_15 <= sign_14; sign_16 <= sign_15; sign_17 <= sign_16;
sign_18 <= sign_17; sign_19 <= sign_18; sign_20 <= sign_19; sign <= sign_20;
mantissa_a1 <= opa[51:0]; mantissa_b1 <= opb[51:0]; mantissa_a2 <= mantissa_a1;
mantissa_b2 <= mantissa_b1; exponent_a <= opa[62:52]; exponent_b <= opb[62:52];
rm_1 <= rmode; rm_2 <= rm_1; rm_3 <= rm_2; rm_4 <= rm_3;
rm_5 <= rm_4; rm_6 <= rm_5; rm_7 <= rm_6; rm_8 <= rm_7; rm_9 <= rm_8;
rm_10 <= rm_9; rm_11 <= rm_10; rm_12 <= rm_11; rm_13 <= rm_12; rm_14 <= rm_13;
rm_15 <= rm_14;
a_is_zero <= !(|exponent_a); b_is_zero <= !(|exponent_b);
a_is_inf <= exponent_a == 2047; b_is_inf <= exponent_b == 2047;
in_inf_1 <= a_is_inf | b_is_inf; in_inf_2 <= in_inf_1;
in_zero_1 <= a_is_zero | b_is_zero;
exponent_terms_1 <= exponent_a + exponent_b;
exponent_terms_2 <= exponent_terms_1;
exponent_terms_3 <= in_zero_1 ? 12'b0 : exponent_terms_2;
exponent_terms_4 <= in_inf_2 ? 12'b110000000000 : exponent_terms_3;
exponent_terms_5 <= exponent_terms_4; exponent_terms_6 <= exponent_terms_5;
exponent_terms_7 <= exponent_terms_6; exponent_terms_8 <= exponent_terms_7;
exponent_terms_9 <= exponent_terms_8;
exponent_gt_expoffset <= exponent_terms_9 > 1022;
exponent_1 <= exponent_terms_9 - 1022;
exponent_2_0 <= exponent_gt_expoffset ? exponent_1 : exponent;
exponent_2_1 <= exponent_2_0;
exponent_2 <= exponent_2_1;
exponent_is_infinity <= (exponent_3 > 2046) & exponent_gt_prodshift;
exponent_3 <= exponent_2 - product_shift;
exponent_gt_prodshift <= exponent_2 >= product_shift;
exponent_4 <= exponent_gt_prodshift ? exponent_3 : exponent;
exponent_5 <= exponent_is_infinity ? 12'b011111111111 : exponent_4;
set_mantissa_zero <= exponent_4 == 0 | exponent_is_infinity;
set_mz_1 <= set_mantissa_zero;
exponent_6 <= exponent_5;
mul_a <= { !a_is_zero, mantissa_a2 }; mul_b <= { !b_is_zero, mantissa_b2 };
mul_a1 <= mul_a; mul_b1 <= mul_b;
mul_a2 <= mul_a1; mul_b2 <= mul_b1; mul_a3 <= mul_a2; mul_b3 <= mul_b2;
mul_a4 <= mul_a3; mul_b4 <= mul_b3; mul_a5 <= mul_a4; mul_b5 <= mul_b4;
mul_a6 <= mul_a5; mul_b6 <= mul_b5; mul_a7 <= mul_a6; mul_b7 <= mul_b6;
mul_a8 <= mul_a7; mul_b8 <= mul_b7;
product_a <= mul_a[23:0] * mul_b[16:0]; product_a_2 <= product_a[16:0];
product_a_3 <= product_a_2; product_a_4 <= product_a_3; product_a_5 <= product_a_4;
product_a_6 <= product_a_5; product_a_7 <= product_a_6; product_a_8 <= product_a_7;
product_a_9 <= product_a_8; product_a_10 <= product_a_9;
product_b <= mul_a[23:0] * mul_b[33:17];
product_c <= mul_a2[23:0] * mul_b2[50:34];
product_d <= mul_a5[23:0] * mul_b5[52:51];
product_e <= mul_a1[40:24] * mul_b1[16:0];
product_f <= mul_a4[40:24] * mul_b4[33:17];
product_g <= mul_a7[40:24] * mul_b7[52:34];
product_h <= mul_a3[52:41] * mul_b3[16:0];
product_i <= mul_a6[52:41] * mul_b6[33:17];
product_j <= mul_a8[52:41] * mul_b8[52:34];
sum_0 <= product_a[40:17] + product_b; sum_0_2 <= sum_0[6:0]; sum_0_3 <= sum_0_2;
sum_0_4 <= sum_0_3; sum_0_5 <= sum_0_4; sum_0_6 <= sum_0_5; sum_0_7 <= sum_0_6;
sum_0_8 <= sum_0_7; sum_0_9 <= sum_0_8;
sum_1 <= sum_0[41:7] + product_e; sum_1_2 <= sum_1[9:0]; sum_1_3 <= sum_1_2;
sum_1_4 <= sum_1_3; sum_1_5 <= sum_1_4; sum_1_6 <= sum_1_5; sum_1_7 <= sum_1_6;
sum_1_8 <= sum_1_7;
sum_2 <= sum_1[35:10] + product_c; sum_2_2 <= sum_2[6:0]; sum_2_3 <= sum_2_2;
sum_2_4 <= sum_2_3; sum_2_5 <= sum_2_4; sum_2_6 <= sum_2_5; sum_2_7 <= sum_2_6;
sum_3 <= sum_2[41:7] + product_h;
sum_4 <= sum_3 + product_f; sum_4_2 <= sum_4[9:0]; sum_4_3 <= sum_4_2;
sum_4_4 <= sum_4_3; sum_4_5 <= sum_4_4;
sum_5 <= sum_4[36:10] + product_d; sum_5_2 <= sum_5[6:0];
sum_5_3 <= sum_5_2; sum_5_4 <= sum_5_3;
sum_6 <= sum_5[27:7] + product_i;
sum_7 <= sum_6 + product_g; sum_7_2 <= sum_7[16:0];
sum_8 <= sum_7[36:17] + product_j;
product <= { sum_8, sum_7_2[16:0], sum_5_4[6:0], sum_4_5[9:0], sum_2_7[6:0],
sum_1_8[9:0], sum_0_9[6:0], product_a_10[16:0] };
product_1 <= product << product_shift;
product_2 <= product_1[105:53]; product_3 <= product_2;
product_4 <= set_mantissa_zero ? 54'b0 : { 1'b0, product_3};
product_shift <= !sum_8[30];
round_nearest_mode <= rm_15 == 2'b00;
round_posinf_mode <= rm_15 == 2'b10;
round_neginf_mode <= rm_15 == 2'b11;
round_nearest_trigger <= product_1[52];
round_nearest_exception <= !(|product_1[51:0]) & (product_1[53] == 0);
round_nearest_enable <= round_nearest_mode & round_nearest_trigger & !round_nearest_exception;
round_posinf_trigger <= |product_1[52:0] & !sign_15;
round_posinf_enable <= round_posinf_mode & round_posinf_trigger;
round_neginf_trigger <= |product_1[52:0] & sign_15;
round_neginf_enable <= round_neginf_mode & round_neginf_trigger;
round_enable <= round_posinf_enable | round_neginf_enable | round_nearest_enable;
product_5 <= round_enable & !set_mz_1 ? product_4 + 1 : product_4;
product_overflow <= product_5[53];
product_6 <= product_5;
product_7 <= product_overflow ? product_6 >> 1 : product_6;
exponent_7 <= exponent_6; exponent_8 <= exponent_7;
exponent_9 <= product_overflow ? exponent_8 + 1 : exponent_8;
end
end
always @(posedge clk, posedge rst)
begin
if (rst) begin
ready <= 0;
count_ready_0 <= 0;
count_ready <= 0;
end
else if (enable) begin
ready <= count_ready;
count_ready_0 <= count == 18;
count_ready <= count == 19;
end
end
always @(posedge clk, posedge rst)
begin
if (rst)
count <= 0;
else if (enable & !count_ready_0 & !count_ready)
count <= count + 1;
end
/* verilator lint_on WIDTH */
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFSBP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFSBP_PP_SYMBOL_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfsbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input SET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFSBP_PP_SYMBOL_V
|
module balldetector(
input inclk,
input ahref,
input avsync,
input apclk,
output xclk,
input [7:0] adata,
input spi_clk,
output spi_miso,
input spi_mosi,
input cs,
output [7:0] led,
output i2c_clk,
inout i2c_sda,
output busy,
input key0,
input key1,
output [9:0] pwm
);
wire write;
wire [15:0] wrdata;
wire done;
wire hue_invalid;
wire [4:0] saturation;
wire [4:0] value;
wire [8:0] hue;
reg [1:0] cdiv;
reg href;
reg vsync;
reg [7:0] data;
reg loaded;
reg sync_href;
reg sync_vsync;
reg sync_spi_clk;
reg sync_spi_mosi;
reg [8:0] hue_buf;
reg [4:0] value_buf;
reg [4:0] satbuf;
wire [7:0] paraspi;
wire [7:0] ledshadow;
wire acapture;
wire newframe;
wire [9:0] horiz_address;
wire clk;
wire locked_sig;
wire res;
//red
assign ledshadow[0] = ((9'd300 < hue_buf) || (hue_buf < 9'd50));
//blue
assign ledshadow[1] = ((9'd160 < hue_buf) && (hue_buf < 9'd250));
//yellow
assign ledshadow[2] = ((9'd50 < hue_buf) && (hue_buf < 9'd80));
//
assign ledshadow[3] = (value_buf > 5'ha && value_buf < 5'h1a);
assign ledshadow[4] = (satbuf > 5'h10);
assign led = key1 ? (key0 ? paraspi : hue_buf[8:1]) : ledshadow;
assign res = ~(locked_sig);
/* data readable
* v
* ____ ____
* ____/ \____/ \_
* ^
* data clr&set
*/
/* async data capture */
always @(posedge clk or posedge res)
begin
if (res) begin
cdiv <= 0;
loaded <= 0;
sync_href <= 0;
sync_vsync <= 1;
end else begin
cdiv <= cdiv + 2'b01;
sync_href <= ahref;
sync_vsync <= avsync;
sync_spi_clk <= spi_clk;
sync_spi_mosi <= spi_mosi;
if ((horiz_address == 320)) begin
hue_buf <= hue;
value_buf <= value;
satbuf <= saturation;
end
if (apclk) begin
if (!loaded) begin
loaded <= 1'b1;
data <= adata;
end
end else begin
loaded <= 1'b0;
end
end
end
assign busy = acapture;
vline_capture ld0 (
ahref,
avsync,
acapture,
newframe
);
pixcopy pc0 (
clk,
(sync_href & loaded),
data,
acapture,
write,
wrdata,
horiz_address
);
rgb2hsv rh0(
clk,
sync_vsync,
write,
wrdata,
saturation,
value,
hue,
hue_invalid,
done
);
/*
pipette_center pp0 (
.clk (clk),
.write (done),
.hue (hue),
.shot (button),
.indicate (ind)
);
*/
wire ioclk;
function turlet;
input [1:0] encode;
begin
case (encode)
2'b00: turlet = 128;
2'b01: turlet = 192;
2'b10: turlet = 64;
2'b11: turlet = 128;
endcase
end
endfunction
servo_timer st0 (
.ioclk(ioclk),
.write_enable(1'b1),
.duty0(paraspi[0] ? 167 : 33 ),
.duty1(paraspi[1] ? 17 : 128 ),
.duty2(paraspi[0] ? 89 : 223 ),
.duty3(paraspi[2] ? 167 : 33 ),
.duty4(paraspi[3] ? 17 : 128 ),
.duty5(paraspi[2] ? 89 : 223 ),
.duty6(paraspi[4] ? 167 : 33 ),
.duty7(paraspi[5] ? 17 : 128 ),
.duty8(paraspi[4] ? 89 : 223 ),
.duty9(turlet(paraspi[7:6])),
.res(res),
.pwm_out(pwm)
);
spi_module sm0 ( .clk (clk),
.cs (cs),
.mclk (sync_spi_clk),
.miso (spi_miso),
.mosi (sync_spi_mosi),
.paraout(paraspi),
.parain(8'hca)
);
pll pll_inst (
.inclk0 ( inclk ),
.c0 ( clk ),
.c1 ( ioclk ),
.c2 ( xclk ),
.locked ( locked_sig )
);
i2c_test it0 (
res,
ioclk,
wreq,
dreq
);
i2c_control ic0 (
res,
clk,
ioclk,
0,
0,
8'h30,
i2c_clk,
i2c_sda
);
//assign clk = inclk;
endmodule
module i2c_test (
input res,
input ioclk,
output reg wreq,
output reg dreq);
reg [29:0] counter;
always @(ioclk) begin
if (res) begin
wreq <= 0;
dreq <= 0;
counter <= 0;
end
counter <= counter + 1'b1;
if (counter == 30'h100_0000) begin
dreq <= 1;
end
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 05:23:20 12/08/2016
// Design Name: Claps
// Module Name: X:/Desktop/music-fpga-master/music-fpga-master/ClapTest.v
// Project Name: Enlightened
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Claps
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module ClapTest;
// Inputs
reg clk_48;
reg rst;
reg [9:0] mic_sample;
// Outputs
wire home_state;
// Instantiate the Unit Under Test (UUT)
Claps uut (
.clk_48(clk_48),
.rst(rst),
.mic_sample(mic_sample),
.home_state(home_state)
);
always begin
#10 clk_48 = ~clk_48;
end
initial begin
// Initialize Inputs
clk_48 = 0;
rst = 1;
mic_sample = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
rst = 0;
mic_sample = 10'h27F;
#100;
mic_sample = 10'h1FF;
#40;
mic_sample = 10'h27F;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_PP_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__a21boi (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire b ;
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
not not0 (b , B1_N );
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , b, and0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__A21BOI_FUNCTIONAL_PP_V |
/**
* @module IF_ID
* @author sabertazimi
* @email [email protected]
* @brief IF_ID pipeline register
* @input clk clock signal
* @input rst reset signal
* @input en load enable signal
* @input IF_PC PC value in IF stage
* @input IF_IR instruction value in IF stage
* @output ID_PC PC value in ID stage
* @output ID_IR instruction value in ID stage
*/
module IF_ID
#(parameter DATA_WIDTH = 32)
(
input clk,
input rst,
input en,
input [DATA_WIDTH-1:0] IF_PC,
input [DATA_WIDTH-1:0] IF_IR,
input IF_taken,
output [DATA_WIDTH-1:0] ID_PC,
output [DATA_WIDTH-1:0] ID_IR,
output ID_taken
);
wire real_rst = rst && en;
register #(
.DATA_WIDTH(DATA_WIDTH)
) PC (
.clk(clk),
.rst(real_rst),
.en(en),
.din(IF_PC),
.dout(ID_PC)
);
register #(
.DATA_WIDTH(DATA_WIDTH)
) IR (
.clk(clk),
.rst(real_rst),
.en(en),
.din(IF_IR),
.dout(ID_IR)
);
register #(
.DATA_WIDTH(1)
) taken (
.clk(clk),
.rst(real_rst),
.en(en),
.din(IF_taken),
.dout(ID_taken)
);
endmodule // IF_ID
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_TB_V
`define SKY130_FD_SC_MS__SDFSTP_TB_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfstp.v"
module top();
// Inputs are registered
reg D;
reg SCD;
reg SCE;
reg SET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
SCD = 1'bX;
SCE = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 SCD = 1'b0;
#60 SCE = 1'b0;
#80 SET_B = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 D = 1'b1;
#200 SCD = 1'b1;
#220 SCE = 1'b1;
#240 SET_B = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 D = 1'b0;
#360 SCD = 1'b0;
#380 SCE = 1'b0;
#400 SET_B = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 SET_B = 1'b1;
#600 SCE = 1'b1;
#620 SCD = 1'b1;
#640 D = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 SET_B = 1'bx;
#760 SCE = 1'bx;
#780 SCD = 1'bx;
#800 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__sdfstp dut (.D(D), .SCD(SCD), .SCE(SCE), .SET_B(SET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_TB_V
|
module test_mem_dev #(
parameter READ_FIFO_SIZE = 8,
parameter WRITE_FIFO_SIZE = 8,
parameter ADDRESS_WIDTH = 8,
parameter ENABLE_ERROR_CHECK = 1,
parameter INITIALIZE_MEM = 1
)(
input clk,
input rst,
//BRAM Style Interface
input bram_en,
input bram_we,
input [(ADDRESS_WIDTH - 1):0] bram_address,
input [31:0] bram_data_in,
output [31:0] bram_data_out,
output initializing,
//Write Side
input write_enable,
input [63:0] write_addr,
input write_addr_inc,
input write_addr_dec,
output write_finished,
input [23:0] write_count,
input write_flush,
output [1:0] write_ready,
input [1:0] write_activate,
output [23:0] write_size,
input write_strobe,
input [31:0] write_data,
//Read Side
input read_enable,
input [63:0] read_addr,
input read_addr_inc,
input read_addr_dec,
output read_busy,
output read_error,
input [23:0] read_count,
input read_flush,
output read_ready,
input read_activate,
output [23:0] read_size,
output [31:0] read_data,
input read_strobe
);
//Local Parameters
//Registers/Wires
reg [ADDRESS_WIDTH - 1:0] mem_addr_in;
reg [ADDRESS_WIDTH - 1:0] mem_addr_out;
reg [23:0] mem_write_count;
wire mem_write_overflow;
reg [23:0] local_read_size;
reg [23:0] mem_read_count;
reg mem_read_strobe;
reg mem_write_strobe;
reg prev_write_enable;
wire posedge_write_enable;
reg prev_read_enable;
wire posedge_read_enable;
reg [31:0] prev_f2m_data;
reg f2m_data_error;
reg [31:0] prev_m2f_data;
reg m2f_data_error;
reg f2m_strobe;
wire f2m_ready;
reg f2m_activate;
wire [23:0] f2m_size;
wire [31:0] f2m_data;
reg [23:0] f2m_count;
wire [1:0] m2f_ready;
reg [1:0] m2f_activate;
wire [23:0] m2f_size;
reg m2f_strobe;
wire [31:0] m2f_data;
reg [23:0] m2f_count;
reg first_write;
wire [31:0] din;
wire wea;
reg fill_mem;
reg [31:0] fill_mem_data;
reg fill_mem_wea;
wire write_fifo_empty;
wire blk_mem_we;
wire blk_mem_en;
wire [(ADDRESS_WIDTH - 1):0] blk_mem_wr_addr;
wire [(ADDRESS_WIDTH - 1):0] blk_mem_rd_addr;
wire [31:0] blk_mem_data_in;
wire enable_error_check;
//Submodules
blk_mem #(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (ADDRESS_WIDTH )
) mem (
.clka (clk ),
.wea (blk_mem_we ),
.dina (blk_mem_data_in),
.addra (blk_mem_wr_addr),
.clkb (clk ),
.doutb (m2f_data ),
.addrb (blk_mem_rd_addr)
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (WRITE_FIFO_SIZE)
)fifo_to_mem (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (write_ready ),
.write_activate (write_activate ),
.write_fifo_size (write_size ),
.write_strobe (write_strobe ),
.write_data (write_data ),
.starved (write_fifo_empty),
//Read
.read_clock (clk ),
.read_strobe (f2m_strobe ),
.read_ready (f2m_ready ),
.read_activate (f2m_activate ),
.read_count (f2m_size ),
.read_data (f2m_data )
//.inactive ( )
);
ppfifo#(
.DATA_WIDTH (32 ),
.ADDRESS_WIDTH (READ_FIFO_SIZE )
)mem_to_fifo (
.reset (rst ),
//Write
.write_clock (clk ),
.write_ready (m2f_ready ),
.write_activate (m2f_activate ),
.write_fifo_size (m2f_size ),
.write_strobe (m2f_strobe ),
.write_data (m2f_data ),
//.starved ( ),
//Read
.read_clock (clk ),
.read_strobe (read_strobe ),
.read_ready (read_ready ),
.read_activate (read_activate ),
.read_count (read_size ),
.read_data (read_data )
//.inactive ( )
);
//Asynchronous Logic
assign posedge_write_enable = !prev_write_enable && write_enable;
assign posedge_read_enable = !prev_read_enable && read_enable;
assign mem_write_overflow = ((write_count > 0) && (mem_write_count > write_count));
assign write_finished = ((write_count > 0) && (mem_write_count >= write_count) && write_fifo_empty);
assign mem_read_overflow = ((local_read_size > 0) && (mem_read_count > local_read_size));
assign read_finished = ((local_read_size > 0) && (mem_read_count >= local_read_size));
assign din = fill_mem ? fill_mem_data: f2m_data;
assign wea = fill_mem ? fill_mem_wea: f2m_strobe;
assign read_error = m2f_data_error;
assign blk_mem_we = bram_en ? bram_we : wea;
assign blk_mem_wr_addr = bram_en ? bram_address : mem_addr_in;
assign blk_mem_rd_addr = bram_en ? bram_address : mem_addr_out;
assign blk_mem_data_in = bram_en ? bram_data_in : din;
assign bram_data_out = m2f_data;
assign initializing = fill_mem_wea;
assign enable_error_check = ENABLE_ERROR_CHECK;
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
mem_addr_in <= 0;
mem_addr_out <= 0;
f2m_strobe <= 0;
f2m_activate <= 0;
f2m_count <= 0;
m2f_activate <= 0;
m2f_strobe <= 0;
m2f_count <= 0;
prev_write_enable <= 0;
prev_read_enable <= 0;
local_read_size <= 0;
mem_write_count <= 0;
mem_read_count <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
m2f_data_error <= 0;
prev_f2m_data <= 0;
first_write <= 0;
fill_mem <= INITIALIZE_MEM;
fill_mem_data <= 0;
fill_mem_wea <= INITIALIZE_MEM;
prev_m2f_data <= 0;
end
//Fill Memory Device
else if (fill_mem) begin
fill_mem_wea <= 1;
if (mem_addr_in < (2 ** ADDRESS_WIDTH - 1)) begin
fill_mem_data <= mem_addr_in + 1;
mem_addr_in <= mem_addr_in + 1;
end
else begin
fill_mem <= 0;
fill_mem_wea <= 0;
end
end
else begin
//Strobes
f2m_strobe <= 0;
m2f_strobe <= 0;
mem_read_strobe <= 0;
mem_write_strobe <= 0;
f2m_data_error <= 0;
first_write <= 0;
m2f_data_error <= 0;
//Errors (Incomming)
if ((f2m_count > 0) && mem_write_strobe && !write_flush) begin
if ((prev_f2m_data == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
//if ((mem_addr_in == (2 ** ADDRESS_WIDTH) - 1) && (f2m_data != 0)) begin
f2m_data_error <= 1;
if (enable_error_check) begin
$display ("Write: Wrap Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
else if ((prev_f2m_data + 1) != f2m_data) begin
if (first_write) begin
if (prev_f2m_data != f2m_data) begin
f2m_data_error <= 1;
if (enable_error_check) begin
$display ("Write: First Write Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
end
else begin
f2m_data_error <= 1;
if (enable_error_check) begin
$display ("Write: Error @ 0x%h: 0x%h != 0x%h", mem_addr_in, prev_f2m_data + 1, f2m_data);
end
end
end
end
//Error (Outgoing)
//if ((m2f_count > 0) && mem_read_strobe && !read_flush) begin
if ((m2f_count > 0) && m2f_strobe && !read_flush && ((m2f_activate & m2f_ready) == 0)) begin
if (((prev_m2f_data + 1)== (2 ** ADDRESS_WIDTH)) && (m2f_data != 0))begin
m2f_data_error <= 1;
if (enable_error_check) begin
$display ("Read: Wrap Error @ 0x%h should be 0", prev_m2f_data);
end
end
else if ((prev_m2f_data + 1) != m2f_data) begin
m2f_data_error <= 1;
if (enable_error_check) begin
$display ("Read: Error @ 0x%h: 0x%h != 0x%h", mem_addr_out, m2f_data, (prev_m2f_data + 1));
end
end
end
//Store Memory Address
if (posedge_write_enable) begin
mem_addr_in <= write_addr[ADDRESS_WIDTH - 1: 0];
mem_write_count <= 0;
end
if (posedge_read_enable) begin
mem_addr_out <= read_addr[ADDRESS_WIDTH - 1: 0];
local_read_size <= read_count;
mem_read_count <= 0;
end
if (!read_enable) begin
local_read_size <= 0;
end
//If available get a peice of the FIFO that I can write data to the memory
if (!f2m_activate && f2m_ready) begin
f2m_activate <= 1;
f2m_count <= 0;
end
//If there is an available FIFO to write to grab it
if ((m2f_activate == 0) && (m2f_ready > 0)) begin
m2f_count <= 0;
if (m2f_ready[0]) begin
m2f_activate[0] <= 1;
end
else begin
m2f_activate[1] <= 1;
end
end
if (mem_read_strobe) begin
if (read_addr_inc) begin
mem_addr_out <= mem_addr_out + 1;
end
else if (read_addr_dec) begin
mem_addr_out <= mem_addr_out - 1;
end
m2f_strobe <= 1;
end
if (!m2f_strobe &&
!mem_read_strobe && (m2f_activate > 0) &&
((m2f_count >= m2f_size) ||
(mem_read_count > 0 &&
mem_read_count >= local_read_size))) begin
m2f_activate <= 0;
end
if (mem_write_strobe) begin
mem_write_count <= mem_write_count + 1;
if (write_addr_inc) begin
mem_addr_in <= mem_addr_in + 1;
end
else if (write_addr_dec) begin
mem_addr_in <= mem_addr_in - 1;
end
end
//if (write_enable) begin
if (f2m_count < f2m_size) begin
if (f2m_activate) begin
f2m_strobe <= 1;
mem_write_strobe <= 1;
f2m_count <= f2m_count + 1;
if (f2m_count == 0) begin
first_write <= 1;
end
end
end
else begin
f2m_activate <= 0;
end
//end
if (mem_read_count < local_read_size) begin
if (read_enable) begin
if ((m2f_activate > 0) && (m2f_count < m2f_size)) begin
m2f_count <= m2f_count + 1;
mem_read_strobe <= 1;
mem_read_count <= mem_read_count + 1;
end
end
end
if (m2f_strobe) begin
prev_m2f_data <= m2f_data;
end
prev_f2m_data <= f2m_data;
prev_write_enable <= write_enable;
prev_read_enable <= read_enable;
end
end
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*/
// IMPORTANT: This requires an input text file named "rf1.fill"
// Include definition of the control signals
`include "control.h"
// Non-synthesizable behavioral RTL model for the instruction memory
module data_mem (data_out,data_in,mem_ctrl_addr,clk,dm_ctrl_sig);
// load instr - take data out
// store - put data into the memory
// ===============================================================
// Output signals...
// Data output read from the data memory
output [0:127] data_out;
// ===============================================================
// Input signals
// Data input stored into the data memory
input [0:127] data_in;
/**
* Enable signal to indicate that the instruction memory shall be
* from an input text file named "rf1.fill"
*/
input [0:31] mem_ctrl_addr;
// Clock signal
input clk;
// Control signals for the data memory
input [0:1] dm_ctrl_sig;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Definitions for the constants the instruction memory
// parameter PARAM_NAME = VALUE;
// ===============================================================
// Declare "reg" signals:
reg [0:127] data_out; // Output signals
/**
* (256 word) depth and (31 bits per word) width
*/
reg [127:0] data_mem [255:0]; // Store the data here
// Store instruction address in the instruction memory
// ===============================================================
initial
begin
/**
* Read the input data for r from an input file named
* "rf1.fill"'
*
* The system task to read data from the file must be placed
* in an INITIAL block
*/
$readmemh("rf1.fill",data_mem);
end
// A change in the instruction address activates this...
always @(posedge clk)
begin
/**
* Check the control signal and implement the appropriate
* function
*/
case(dm_ctrl_sig)
`memwld:
begin
// Read the data from the memory
data_out<=data_mem[mem_ctrl_addr];
end
`memwst:
begin
// Write the data to the memory
data_mem[mem_ctrl_addr]<=data_in;
$display("Value written to data mem",data_mem[mem_ctrl_addr],"#");
end
`memnop:
begin
data_out<=128'd0;
end
default:
begin
data_out<=128'd0;
end
endcase
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A221O_TB_V
`define SKY130_FD_SC_LP__A221O_TB_V
/**
* a221o: 2-input AND into first two inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | C1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a221o.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1;
reg B2;
reg C1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
C1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 C1 = 1'b0;
#120 VGND = 1'b0;
#140 VNB = 1'b0;
#160 VPB = 1'b0;
#180 VPWR = 1'b0;
#200 A1 = 1'b1;
#220 A2 = 1'b1;
#240 B1 = 1'b1;
#260 B2 = 1'b1;
#280 C1 = 1'b1;
#300 VGND = 1'b1;
#320 VNB = 1'b1;
#340 VPB = 1'b1;
#360 VPWR = 1'b1;
#380 A1 = 1'b0;
#400 A2 = 1'b0;
#420 B1 = 1'b0;
#440 B2 = 1'b0;
#460 C1 = 1'b0;
#480 VGND = 1'b0;
#500 VNB = 1'b0;
#520 VPB = 1'b0;
#540 VPWR = 1'b0;
#560 VPWR = 1'b1;
#580 VPB = 1'b1;
#600 VNB = 1'b1;
#620 VGND = 1'b1;
#640 C1 = 1'b1;
#660 B2 = 1'b1;
#680 B1 = 1'b1;
#700 A2 = 1'b1;
#720 A1 = 1'b1;
#740 VPWR = 1'bx;
#760 VPB = 1'bx;
#780 VNB = 1'bx;
#800 VGND = 1'bx;
#820 C1 = 1'bx;
#840 B2 = 1'bx;
#860 B1 = 1'bx;
#880 A2 = 1'bx;
#900 A1 = 1'bx;
end
sky130_fd_sc_lp__a221o dut (.A1(A1), .A2(A2), .B1(B1), .B2(B2), .C1(C1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A221O_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__MUX2I_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__MUX2I_FUNCTIONAL_PP_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`include "../../models/udp_mux_2to1_n/sky130_fd_sc_ms__udp_mux_2to1_n.v"
`celldefine
module sky130_fd_sc_ms__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire mux_2to1_n0_out_Y;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
sky130_fd_sc_ms__udp_mux_2to1_N mux_2to1_n0 (mux_2to1_n0_out_Y, A0, A1, S );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, mux_2to1_n0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__MUX2I_FUNCTIONAL_PP_V |
// this test was yanked from another file and may require
// a few syntax error fixes.
//
module test_mesh_to_ring_stitch
#(
parameter cycle_time_p = 20,
localparam num_tiles_x_p = 8,
localparam num_tiles_y_p = 8,
parameter reset_cycles_lo_p=1,
parameter reset_cycles_hi_p=5
);
import bsg_noc_pkg ::*; // {P=0, W, E, N, S}
// clock and reset generation
wire clk;
wire reset;
bsg_nonsynth_clock_gen #( .cycle_time_p(cycle_time_p)
) clock_gen
( .o(clk)
);
bsg_nonsynth_reset_gen #( .num_clocks_p (1)
, .reset_cycles_lo_p(reset_cycles_lo_p)
, .reset_cycles_hi_p(reset_cycles_hi_p)
) reset_gen
( .clk_i (clk)
, .async_reset_o(reset)
);
localparam b_lp = 1;
localparam f_lp = 1;
localparam x_lp = (num_tiles_x_p);
localparam y_lp = (num_tiles_y_p);
logic [x_lp-1:0][y_lp-1:0][$clog2(x_lp*y_lp)-1:0] ids;
logic [x_lp-1:0][y_lp-1:0][b_lp-1:0] back_in, back_out;
logic [x_lp-1:0][y_lp-1:0][f_lp-1:0] fwd_in, fwd_out;
bsg_mesh_to_ring_stitch #(.y_max_p(y_lp)
,.x_max_p(x_lp)
,.width_back_p(b_lp)
,.width_fwd_p(f_lp)
) m2r
(.id_o (ids )
,.back_data_in_o (back_in )
,.back_data_out_i(back_out)
,.fwd_data_in_o (fwd_in )
,.fwd_data_out_i (fwd_out )
);
always @(posedge clk)
begin
if (reset)
begin
back_out <= $bits(back_in) ' (1);
fwd_out <= $bits(fwd_in) ' (1);
end
else
begin
back_out <= back_in;
fwd_out <= fwd_in;
end
end
integer xx,yy;
always @(negedge clk)
begin
for (yy = 0; yy < y_lp; yy=yy+1)
begin
for (xx = 0; xx < x_lp; xx=xx+1)
$write("%b", fwd_in[xx][yy]);
$write(" ");
for (xx = 0; xx < x_lp; xx=xx+1)
$write("%b", back_in[xx][yy]);
$write("\n");
end
$write("\n");
end
endmodule
|
/**
# SmallBpf - 2-pole IIR Bandpass Filter #
Small 2-Pole IIR band-pass filter, made using just adders and bit shifts. Set
the frequency using the K0_SHIFT and K1_SHIFT parameters. It can be slowed down by
strobing the `en` bit to run at a lower rate.
By using power of two feedback terms, this filter is alsways stable and is
immune to limit cycling.
Clamping is necessary if the full input range will be used. Clamping is
unnecessary if the input word will never go beyond '+/- (2^(WIDTH-2)-1)'. Keep
in mind that clamping will cause nonlinear distortion in high-amplitude signals.
## Design Equations ##
Let w0 be the desired center frequency in radians/second, let f_clk be the
filter run rate (defined by clk and en), and let Q be the desired quality
factor. Quality factor can be defined as the center frequency divided by the
bandwidth.
```
(w0/Q)*s
H(s) = -----------------------
s^2 + (w0/Q)*s + w0^2
w0 = 2*pi*f0
Q = f0 / f_bandwidth
K0_SHIFT = -log2(w0/Q / f_clk)
K1_SHIFT = -log2(w0*Q / f_clk)
w0/Q = 2^-K0_SHIFT * f_clk
w0*Q = 2^-K1_SHIFT * f_clk
w0 = sqrt(2^-K0_SHIFT * 2^-K1_SHIFT * f_clk^2)
Q = sqrt(2^-K1_SHIFT / 2^-K0_SHIFT)
```
Since the SHIFT parameters must be integers, the final filter will not perfectly
match the desired one. The true filter response will also be different from the
continuous-time approximation.
## Block Diagram ##
Key:
- ACCUM: accumulator
- SUB: subtract signal on bottom from the signal on the left
- 2^-X: Right arithmetic shift by X
```
dataIn --->(SUB)--->(SUB)--->[ACCUM]--->[2^-K0_SHIFT]--+--> dataOut
^ ^ |
| | |
| \----[2^-K1_SHIFT]<---[ACCUM]<---+
| |
\-----------------------------------------/
```
*/
module SmallBpf #(
parameter WIDTH = 16, ///< Data width
parameter K0_SHIFT = 10, ///< Gain on forward path accumulator
parameter K1_SHIFT = 18, ///< Gain on feedback path accumulator
parameter CLAMP = 1 ///< Set to 1 to clamp the accumulators
)
(
input clk, ///< System clock
input rst, ///< Reset, active high and synchronous
input en, ///< Filter enable
input signed [WIDTH-1:0] dataIn, ///< Filter input
output signed [WIDTH-1:0] dataOut ///< Filter output
);
reg signed [WIDTH+K0_SHIFT-1:0] acc0;
reg signed [WIDTH+K1_SHIFT-1:0] acc1;
reg signed [WIDTH+1:0] forwardIn;
wire signed [WIDTH-1:0] feedbackOut;
wire signed [WIDTH+K0_SHIFT:0] acc0In;
wire signed [WIDTH+K1_SHIFT:0] acc1In;
assign acc0In = acc0 + forwardIn;
assign acc1In = acc1 + dataOut;
always @(posedge clk) begin
if (rst) begin
forwardIn <= 'd0;
acc0 <= 'd0;
acc1 <= 'd0;
end
else if (en) begin
forwardIn <= dataIn - dataOut - feedbackOut;
if (CLAMP) begin
acc0 <= (^acc0In[WIDTH+K0_SHIFT-:2])
? {acc0In[WIDTH+K0_SHIFT], {(WIDTH+K0_SHIFT-1){acc0In[WIDTH+K0_SHIFT-1]}}}
: acc0In;
acc1 <= (^acc1In[WIDTH+K1_SHIFT-:2])
? {acc1In[WIDTH+K1_SHIFT], {(WIDTH+K1_SHIFT-1){acc1In[WIDTH+K1_SHIFT-1]}}}
: acc1In;
end
else begin
acc0 <= acc0In;
acc1 <= acc1In;
end
end
end
assign dataOut = acc0 >>> K0_SHIFT;
assign feedbackOut = acc1 >>> K1_SHIFT;
// Test Code: Check to see if clamping ever occurs
/*
reg clamp0;
reg clamp1;
always @(posedge clk) begin
if (rst) begin
clamp0 <= 1'b0;
clamp1 <= 1'b0;
end
else begin
clamp0 <= clamp0 | (^acc0In[WIDTH+K0_SHIFT-:2]);
clamp1 <= clamp1 | (^acc1In[WIDTH+K1_SHIFT-:2]);
end
end
*/
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A31O_SYMBOL_V
`define SKY130_FD_SC_MS__A31O_SYMBOL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__a31o (
//# {{data|Data Signals}}
input A1,
input A2,
input A3,
input B1,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__A31O_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 17:28:36 09/26/2015
// Design Name: Short Hamming Decoder
// Module Name: NewHammingDecoder
//////////////////////////////////////////////////////////////////////////////////
module NewHammingDecoder(H, D);
input [6:0] H;
output [3:0] D;
//assign D[3] =
//assign D[2] =
//assign D[1] =
assign D[3] = (H[6]^H[5]^H[4]^H[2])&(H[6]^H[5]^H[3]^H[1])&(H[6]^H[4]^H[3]^H[0]) ? ~H[6] : H[6];
assign D[2] = (H[6]^H[5]^H[4]^H[2])&(H[6]^H[5]^H[3]^H[1])&!(H[6]^H[4]^H[3]^H[0]) ? ~H[5] : H[5];
assign D[1] = (H[6]^H[5]^H[4]^H[2])&!(H[6]^H[5]^H[3]^H[1])&(H[6]^H[4]^H[3]^H[0]) ? ~H[4] : H[4];
assign D[0] = !(H[6]^H[5]^H[4]^H[2])&(H[6]^H[5]^H[3]^H[1])&(H[6]^H[4]^H[3]^H[0]) ? ~H[3] : H[3];
// assign syndrome[2] = code[6] ^ code[5] ^ code[4] ^ code[2];
// assign syndrome[1] = code[6] ^ code[5] ^ code[3] ^ code[1];
// assign syndrome[0] = code[6] ^ code[4] ^ code[3] ^ code[0];
// assign data = (syndrome == 3'b111) ? { ~code[6], code[5], code[4], code[3] } :
// (syndrome == 3'b110) ? { code[6], ~code[5], code[4], code[3] } :
// (syndrome == 3'b101) ? { code[6], code[5], ~code[4], code[3] } :
// (syndrome == 3'b011) ? { code[6], code[5], code[4], ~code[3] } :
// { code[6], code[5], code[4], code[3] };
endmodule
|
//wb_master_test.v
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x800000000000C594
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: 19 UNICODE characters
SDB_NAME:wb_master_test
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x0F
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2016/06/02
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:3
*/
module wb_master_test (
input clk,
input rst,
//Add signals to control your device here
//Wishbone Bus Signals
input i_wbs_we,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_dat,
input i_wbs_stb,
output reg o_wbs_ack,
output reg [31:0] o_wbs_dat,
input [31:0] i_wbs_adr,
//This interrupt can be controlled from this module or a submodule
output reg o_wbs_int
//output o_wbs_int
);
//Local Parameters
localparam ADDR_0 = 32'h00000000;
localparam ADDR_1 = 32'h00000001;
localparam ADDR_2 = 32'h00000002;
//Local Registers/Wires
reg [31:0] r_control;
//Submodules
//Asynchronous Logic
//Synchronous Logic
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
r_control <= 2;
end
else begin
//when the master acks our ack, then put our ack down
if (o_wbs_ack && ~i_wbs_stb)begin
o_wbs_ack <= 0;
end
if (i_wbs_stb && i_wbs_cyc) begin
//master is requesting somethign
if (!o_wbs_ack) begin
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_0: begin
//writing something to address 0
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
r_control <= i_wbs_dat;
o_wbs_int <= i_wbs_dat[1];
end
ADDR_1: begin
//writing something to address 1
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
ADDR_2: begin
//writing something to address 3
//do something
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("ADDR: %h user wrote %h", i_wbs_adr, i_wbs_dat);
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
else begin
//read request
case (i_wbs_adr)
ADDR_0: begin
//reading something from address 0
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_0);
o_wbs_dat <= r_control;
end
ADDR_1: begin
//reading something from address 1
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_1);
o_wbs_dat <= ADDR_1;
end
ADDR_2: begin
//reading soething from address 2
//NOTE THE FOLLOWING LINE IS AN EXAMPLE
// THIS IS WHAT THE USER WILL READ FROM ADDRESS 0
$display("user read %h", ADDR_2);
o_wbs_dat <= ADDR_2;
end
//add as many ADDR_X you need here
default: begin
end
endcase
end
o_wbs_ack <= 1;
end
end
end
end
endmodule
|
/*
Copyright (c) 2017 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* FPGA core logic
*/
module fpga_core #
(
parameter TARGET = "XILINX"
)
(
/*
* Clock: 125MHz
* Synchronous reset
*/
input wire clk,
input wire rst,
/*
* GPIO
*/
input wire btnu,
input wire btnl,
input wire btnd,
input wire btnr,
input wire btnc,
input wire [7:0] sw,
output wire [7:0] led,
/*
* Ethernet: 1000BASE-T GMII
*/
input wire phy_rx_clk,
input wire [7:0] phy_rxd,
input wire phy_rx_dv,
input wire phy_rx_er,
output wire phy_gtx_clk,
input wire phy_tx_clk,
output wire [7:0] phy_txd,
output wire phy_tx_en,
output wire phy_tx_er,
output wire phy_reset_n,
/*
* UART: 115200 bps, 8N1
*/
input wire uart_rxd,
output wire uart_txd
);
// XFCP UART interface
wire [7:0] xfcp_uart_interface_down_tdata;
wire xfcp_uart_interface_down_tvalid;
wire xfcp_uart_interface_down_tready;
wire xfcp_uart_interface_down_tlast;
wire xfcp_uart_interface_down_tuser;
wire [7:0] xfcp_uart_interface_up_tdata;
wire xfcp_uart_interface_up_tvalid;
wire xfcp_uart_interface_up_tready;
wire xfcp_uart_interface_up_tlast;
wire xfcp_uart_interface_up_tuser;
xfcp_interface_uart
xfcp_interface_uart_inst (
.clk(clk),
.rst(rst),
.uart_rxd(uart_rxd),
.uart_txd(uart_txd),
.down_xfcp_in_tdata(xfcp_uart_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_uart_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_uart_interface_up_tready),
.down_xfcp_in_tlast(xfcp_uart_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_uart_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_uart_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_uart_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_uart_interface_down_tready),
.down_xfcp_out_tlast(xfcp_uart_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_uart_interface_down_tuser),
.prescale(125000000/(115200*8))
);
// XFCP Ethernet interface
wire [7:0] xfcp_udp_interface_down_tdata;
wire xfcp_udp_interface_down_tvalid;
wire xfcp_udp_interface_down_tready;
wire xfcp_udp_interface_down_tlast;
wire xfcp_udp_interface_down_tuser;
wire [7:0] xfcp_udp_interface_up_tdata;
wire xfcp_udp_interface_up_tvalid;
wire xfcp_udp_interface_up_tready;
wire xfcp_udp_interface_up_tlast;
wire xfcp_udp_interface_up_tuser;
// AXI between MAC and Ethernet modules
wire [7:0] rx_eth_axis_tdata;
wire rx_eth_axis_tvalid;
wire rx_eth_axis_tready;
wire rx_eth_axis_tlast;
wire rx_eth_axis_tuser;
wire [7:0] tx_eth_axis_tdata;
wire tx_eth_axis_tvalid;
wire tx_eth_axis_tready;
wire tx_eth_axis_tlast;
wire tx_eth_axis_tuser;
// Configuration
wire [47:0] local_mac = 48'h02_00_00_00_00_00;
wire [31:0] local_ip = {8'd192, 8'd168, 8'd1, 8'd128};
wire [15:0] local_port = 16'd14000;
wire [31:0] gateway_ip = {8'd192, 8'd168, 8'd1, 8'd1};
wire [31:0] subnet_mask = {8'd255, 8'd255, 8'd255, 8'd0};
assign phy_reset_n = ~rst;
assign led = 0;
eth_mac_1g_gmii_fifo #(
.TARGET(TARGET),
.IODDR_STYLE("IODDR2"),
.CLOCK_INPUT_STYLE("BUFIO2"),
.ENABLE_PADDING(1),
.MIN_FRAME_LENGTH(64),
.TX_FIFO_DEPTH(4096),
.TX_FRAME_FIFO(1),
.RX_FIFO_DEPTH(4096),
.RX_FRAME_FIFO(1)
)
eth_mac_inst (
.gtx_clk(clk),
.gtx_rst(rst),
.logic_clk(clk),
.logic_rst(rst),
.tx_axis_tdata(tx_eth_axis_tdata),
.tx_axis_tvalid(tx_eth_axis_tvalid),
.tx_axis_tready(tx_eth_axis_tready),
.tx_axis_tlast(tx_eth_axis_tlast),
.tx_axis_tuser(tx_eth_axis_tuser),
.rx_axis_tdata(rx_eth_axis_tdata),
.rx_axis_tvalid(rx_eth_axis_tvalid),
.rx_axis_tready(rx_eth_axis_tready),
.rx_axis_tlast(rx_eth_axis_tlast),
.rx_axis_tuser(rx_eth_axis_tuser),
.gmii_rx_clk(phy_rx_clk),
.gmii_rxd(phy_rxd),
.gmii_rx_dv(phy_rx_dv),
.gmii_rx_er(phy_rx_er),
.gmii_tx_clk(phy_gtx_clk),
.mii_tx_clk(phy_tx_clk),
.gmii_txd(phy_txd),
.gmii_tx_en(phy_tx_en),
.gmii_tx_er(phy_tx_er),
.tx_fifo_overflow(),
.tx_fifo_bad_frame(),
.tx_fifo_good_frame(),
.rx_error_bad_frame(),
.rx_error_bad_fcs(),
.rx_fifo_overflow(),
.rx_fifo_bad_frame(),
.rx_fifo_good_frame(),
.speed(),
.ifg_delay(12)
);
xfcp_interface_udp
xfcp_interface_udp_inst (
.clk(clk),
.rst(rst),
.s_eth_axis_tdata(rx_eth_axis_tdata),
.s_eth_axis_tvalid(rx_eth_axis_tvalid),
.s_eth_axis_tready(rx_eth_axis_tready),
.s_eth_axis_tlast(rx_eth_axis_tlast),
.s_eth_axis_tuser(rx_eth_axis_tuser),
.m_eth_axis_tdata(tx_eth_axis_tdata),
.m_eth_axis_tvalid(tx_eth_axis_tvalid),
.m_eth_axis_tready(tx_eth_axis_tready),
.m_eth_axis_tlast(tx_eth_axis_tlast),
.m_eth_axis_tuser(tx_eth_axis_tuser),
.down_xfcp_in_tdata(xfcp_udp_interface_up_tdata),
.down_xfcp_in_tvalid(xfcp_udp_interface_up_tvalid),
.down_xfcp_in_tready(xfcp_udp_interface_up_tready),
.down_xfcp_in_tlast(xfcp_udp_interface_up_tlast),
.down_xfcp_in_tuser(xfcp_udp_interface_up_tuser),
.down_xfcp_out_tdata(xfcp_udp_interface_down_tdata),
.down_xfcp_out_tvalid(xfcp_udp_interface_down_tvalid),
.down_xfcp_out_tready(xfcp_udp_interface_down_tready),
.down_xfcp_out_tlast(xfcp_udp_interface_down_tlast),
.down_xfcp_out_tuser(xfcp_udp_interface_down_tuser),
.local_mac(local_mac),
.local_ip(local_ip),
.local_port(local_port),
.gateway_ip(gateway_ip),
.subnet_mask(subnet_mask)
);
// XFCP 2x1 switch
wire [7:0] xfcp_interface_switch_down_tdata;
wire xfcp_interface_switch_down_tvalid;
wire xfcp_interface_switch_down_tready;
wire xfcp_interface_switch_down_tlast;
wire xfcp_interface_switch_down_tuser;
wire [7:0] xfcp_interface_switch_up_tdata;
wire xfcp_interface_switch_up_tvalid;
wire xfcp_interface_switch_up_tready;
wire xfcp_interface_switch_up_tlast;
wire xfcp_interface_switch_up_tuser;
xfcp_arb #(
.PORTS(2)
)
xfcp_interface_arb_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata({xfcp_udp_interface_down_tdata, xfcp_uart_interface_down_tdata}),
.up_xfcp_in_tvalid({xfcp_udp_interface_down_tvalid, xfcp_uart_interface_down_tvalid}),
.up_xfcp_in_tready({xfcp_udp_interface_down_tready, xfcp_uart_interface_down_tready}),
.up_xfcp_in_tlast({xfcp_udp_interface_down_tlast, xfcp_uart_interface_down_tlast}),
.up_xfcp_in_tuser({xfcp_udp_interface_down_tuser, xfcp_uart_interface_down_tuser}),
.up_xfcp_out_tdata({xfcp_udp_interface_up_tdata, xfcp_uart_interface_up_tdata}),
.up_xfcp_out_tvalid({xfcp_udp_interface_up_tvalid, xfcp_uart_interface_up_tvalid}),
.up_xfcp_out_tready({xfcp_udp_interface_up_tready, xfcp_uart_interface_up_tready}),
.up_xfcp_out_tlast({xfcp_udp_interface_up_tlast, xfcp_uart_interface_up_tlast}),
.up_xfcp_out_tuser({xfcp_udp_interface_up_tuser, xfcp_uart_interface_up_tuser}),
.down_xfcp_in_tdata(xfcp_interface_switch_up_tdata),
.down_xfcp_in_tvalid(xfcp_interface_switch_up_tvalid),
.down_xfcp_in_tready(xfcp_interface_switch_up_tready),
.down_xfcp_in_tlast(xfcp_interface_switch_up_tlast),
.down_xfcp_in_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_out_tdata(xfcp_interface_switch_down_tdata),
.down_xfcp_out_tvalid(xfcp_interface_switch_down_tvalid),
.down_xfcp_out_tready(xfcp_interface_switch_down_tready),
.down_xfcp_out_tlast(xfcp_interface_switch_down_tlast),
.down_xfcp_out_tuser(xfcp_interface_switch_down_tuser)
);
// XFCP 1x4 switch
wire [7:0] xfcp_switch_port_0_down_tdata;
wire xfcp_switch_port_0_down_tvalid;
wire xfcp_switch_port_0_down_tready;
wire xfcp_switch_port_0_down_tlast;
wire xfcp_switch_port_0_down_tuser;
wire [7:0] xfcp_switch_port_0_up_tdata;
wire xfcp_switch_port_0_up_tvalid;
wire xfcp_switch_port_0_up_tready;
wire xfcp_switch_port_0_up_tlast;
wire xfcp_switch_port_0_up_tuser;
wire [7:0] xfcp_switch_port_1_down_tdata;
wire xfcp_switch_port_1_down_tvalid;
wire xfcp_switch_port_1_down_tready;
wire xfcp_switch_port_1_down_tlast;
wire xfcp_switch_port_1_down_tuser;
wire [7:0] xfcp_switch_port_1_up_tdata;
wire xfcp_switch_port_1_up_tvalid;
wire xfcp_switch_port_1_up_tready;
wire xfcp_switch_port_1_up_tlast;
wire xfcp_switch_port_1_up_tuser;
wire [7:0] xfcp_switch_port_2_down_tdata;
wire xfcp_switch_port_2_down_tvalid;
wire xfcp_switch_port_2_down_tready;
wire xfcp_switch_port_2_down_tlast;
wire xfcp_switch_port_2_down_tuser;
wire [7:0] xfcp_switch_port_2_up_tdata;
wire xfcp_switch_port_2_up_tvalid;
wire xfcp_switch_port_2_up_tready;
wire xfcp_switch_port_2_up_tlast;
wire xfcp_switch_port_2_up_tuser;
wire [7:0] xfcp_switch_port_3_down_tdata;
wire xfcp_switch_port_3_down_tvalid;
wire xfcp_switch_port_3_down_tready;
wire xfcp_switch_port_3_down_tlast;
wire xfcp_switch_port_3_down_tuser;
wire [7:0] xfcp_switch_port_3_up_tdata;
wire xfcp_switch_port_3_up_tvalid;
wire xfcp_switch_port_3_up_tready;
wire xfcp_switch_port_3_up_tlast;
wire xfcp_switch_port_3_up_tuser;
xfcp_switch #(
.PORTS(4),
.XFCP_ID_TYPE(16'h0100),
.XFCP_ID_STR("XFCP switch"),
.XFCP_EXT_ID(0),
.XFCP_EXT_ID_STR("Atlys")
)
xfcp_switch_inst (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_interface_switch_down_tdata),
.up_xfcp_in_tvalid(xfcp_interface_switch_down_tvalid),
.up_xfcp_in_tready(xfcp_interface_switch_down_tready),
.up_xfcp_in_tlast(xfcp_interface_switch_down_tlast),
.up_xfcp_in_tuser(xfcp_interface_switch_down_tuser),
.up_xfcp_out_tdata(xfcp_interface_switch_up_tdata),
.up_xfcp_out_tvalid(xfcp_interface_switch_up_tvalid),
.up_xfcp_out_tready(xfcp_interface_switch_up_tready),
.up_xfcp_out_tlast(xfcp_interface_switch_up_tlast),
.up_xfcp_out_tuser(xfcp_interface_switch_up_tuser),
.down_xfcp_in_tdata( {xfcp_switch_port_3_up_tdata, xfcp_switch_port_2_up_tdata, xfcp_switch_port_1_up_tdata, xfcp_switch_port_0_up_tdata }),
.down_xfcp_in_tvalid( {xfcp_switch_port_3_up_tvalid, xfcp_switch_port_2_up_tvalid, xfcp_switch_port_1_up_tvalid, xfcp_switch_port_0_up_tvalid }),
.down_xfcp_in_tready( {xfcp_switch_port_3_up_tready, xfcp_switch_port_2_up_tready, xfcp_switch_port_1_up_tready, xfcp_switch_port_0_up_tready }),
.down_xfcp_in_tlast( {xfcp_switch_port_3_up_tlast, xfcp_switch_port_2_up_tlast, xfcp_switch_port_1_up_tlast, xfcp_switch_port_0_up_tlast }),
.down_xfcp_in_tuser( {xfcp_switch_port_3_up_tuser, xfcp_switch_port_2_up_tuser, xfcp_switch_port_1_up_tuser, xfcp_switch_port_0_up_tuser }),
.down_xfcp_out_tdata( {xfcp_switch_port_3_down_tdata, xfcp_switch_port_2_down_tdata, xfcp_switch_port_1_down_tdata, xfcp_switch_port_0_down_tdata }),
.down_xfcp_out_tvalid({xfcp_switch_port_3_down_tvalid, xfcp_switch_port_2_down_tvalid, xfcp_switch_port_1_down_tvalid, xfcp_switch_port_0_down_tvalid}),
.down_xfcp_out_tready({xfcp_switch_port_3_down_tready, xfcp_switch_port_2_down_tready, xfcp_switch_port_1_down_tready, xfcp_switch_port_0_down_tready}),
.down_xfcp_out_tlast( {xfcp_switch_port_3_down_tlast, xfcp_switch_port_2_down_tlast, xfcp_switch_port_1_down_tlast, xfcp_switch_port_0_down_tlast }),
.down_xfcp_out_tuser( {xfcp_switch_port_3_down_tuser, xfcp_switch_port_2_down_tuser, xfcp_switch_port_1_down_tuser, xfcp_switch_port_0_down_tuser })
);
// XFCP WB RAM 0
wire [7:0] ram_0_wb_adr_i;
wire [31:0] ram_0_wb_dat_i;
wire [31:0] ram_0_wb_dat_o;
wire ram_0_wb_we_i;
wire [3:0] ram_0_wb_sel_i;
wire ram_0_wb_stb_i;
wire ram_0_wb_ack_o;
wire ram_0_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 0"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_0 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_0_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_0_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_0_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_0_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_0_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_0_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_0_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_0_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_0_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_0_up_tuser),
.wb_adr_o(ram_0_wb_adr_i),
.wb_dat_i(ram_0_wb_dat_o),
.wb_dat_o(ram_0_wb_dat_i),
.wb_we_o(ram_0_wb_we_i),
.wb_sel_o(ram_0_wb_sel_i),
.wb_stb_o(ram_0_wb_stb_i),
.wb_ack_i(ram_0_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_0_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_0_inst (
.clk(clk),
.adr_i(ram_0_wb_adr_i),
.dat_i(ram_0_wb_dat_i),
.dat_o(ram_0_wb_dat_o),
.we_i(ram_0_wb_we_i),
.sel_i(ram_0_wb_sel_i),
.stb_i(ram_0_wb_stb_i),
.ack_o(ram_0_wb_ack_o),
.cyc_i(ram_0_wb_cyc_i)
);
// XFCP WB RAM 1
wire [7:0] ram_1_wb_adr_i;
wire [31:0] ram_1_wb_dat_i;
wire [31:0] ram_1_wb_dat_o;
wire ram_1_wb_we_i;
wire [3:0] ram_1_wb_sel_i;
wire ram_1_wb_stb_i;
wire ram_1_wb_ack_o;
wire ram_1_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 1"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_1 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_1_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_1_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_1_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_1_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_1_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_1_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_1_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_1_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_1_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_1_up_tuser),
.wb_adr_o(ram_1_wb_adr_i),
.wb_dat_i(ram_1_wb_dat_o),
.wb_dat_o(ram_1_wb_dat_i),
.wb_we_o(ram_1_wb_we_i),
.wb_sel_o(ram_1_wb_sel_i),
.wb_stb_o(ram_1_wb_stb_i),
.wb_ack_i(ram_1_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_1_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_1_inst (
.clk(clk),
.adr_i(ram_1_wb_adr_i),
.dat_i(ram_1_wb_dat_i),
.dat_o(ram_1_wb_dat_o),
.we_i(ram_1_wb_we_i),
.sel_i(ram_1_wb_sel_i),
.stb_i(ram_1_wb_stb_i),
.ack_o(ram_1_wb_ack_o),
.cyc_i(ram_1_wb_cyc_i)
);
// XFCP WB RAM 2
wire [7:0] ram_2_wb_adr_i;
wire [31:0] ram_2_wb_dat_i;
wire [31:0] ram_2_wb_dat_o;
wire ram_2_wb_we_i;
wire [3:0] ram_2_wb_sel_i;
wire ram_2_wb_stb_i;
wire ram_2_wb_ack_o;
wire ram_2_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 2"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_2 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_2_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_2_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_2_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_2_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_2_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_2_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_2_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_2_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_2_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_2_up_tuser),
.wb_adr_o(ram_2_wb_adr_i),
.wb_dat_i(ram_2_wb_dat_o),
.wb_dat_o(ram_2_wb_dat_i),
.wb_we_o(ram_2_wb_we_i),
.wb_sel_o(ram_2_wb_sel_i),
.wb_stb_o(ram_2_wb_stb_i),
.wb_ack_i(ram_2_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_2_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_2_inst (
.clk(clk),
.adr_i(ram_2_wb_adr_i),
.dat_i(ram_2_wb_dat_i),
.dat_o(ram_2_wb_dat_o),
.we_i(ram_2_wb_we_i),
.sel_i(ram_2_wb_sel_i),
.stb_i(ram_2_wb_stb_i),
.ack_o(ram_2_wb_ack_o),
.cyc_i(ram_2_wb_cyc_i)
);
// XFCP WB RAM 3
wire [7:0] ram_3_wb_adr_i;
wire [31:0] ram_3_wb_dat_i;
wire [31:0] ram_3_wb_dat_o;
wire ram_3_wb_we_i;
wire [3:0] ram_3_wb_sel_i;
wire ram_3_wb_stb_i;
wire ram_3_wb_ack_o;
wire ram_3_wb_cyc_i;
xfcp_mod_wb #(
.XFCP_ID_STR("XFCP RAM 3"),
.COUNT_SIZE(16),
.WB_DATA_WIDTH(32),
.WB_ADDR_WIDTH(8),
.WB_SELECT_WIDTH(4)
)
xfcp_mod_wb_ram_3 (
.clk(clk),
.rst(rst),
.up_xfcp_in_tdata(xfcp_switch_port_3_down_tdata),
.up_xfcp_in_tvalid(xfcp_switch_port_3_down_tvalid),
.up_xfcp_in_tready(xfcp_switch_port_3_down_tready),
.up_xfcp_in_tlast(xfcp_switch_port_3_down_tlast),
.up_xfcp_in_tuser(xfcp_switch_port_3_down_tuser),
.up_xfcp_out_tdata(xfcp_switch_port_3_up_tdata),
.up_xfcp_out_tvalid(xfcp_switch_port_3_up_tvalid),
.up_xfcp_out_tready(xfcp_switch_port_3_up_tready),
.up_xfcp_out_tlast(xfcp_switch_port_3_up_tlast),
.up_xfcp_out_tuser(xfcp_switch_port_3_up_tuser),
.wb_adr_o(ram_3_wb_adr_i),
.wb_dat_i(ram_3_wb_dat_o),
.wb_dat_o(ram_3_wb_dat_i),
.wb_we_o(ram_3_wb_we_i),
.wb_sel_o(ram_3_wb_sel_i),
.wb_stb_o(ram_3_wb_stb_i),
.wb_ack_i(ram_3_wb_ack_o),
.wb_err_i(1'b0),
.wb_cyc_o(ram_3_wb_cyc_i)
);
wb_ram #(
.DATA_WIDTH(32),
.ADDR_WIDTH(8),
.SELECT_WIDTH(4)
)
ram_3_inst (
.clk(clk),
.adr_i(ram_3_wb_adr_i),
.dat_i(ram_3_wb_dat_i),
.dat_o(ram_3_wb_dat_o),
.we_i(ram_3_wb_we_i),
.sel_i(ram_3_wb_sel_i),
.stb_i(ram_3_wb_stb_i),
.ack_o(ram_3_wb_ack_o),
.cyc_i(ram_3_wb_cyc_i)
);
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 20 02:55:16 2016
/////////////////////////////////////////////////////////////
module GeAr_N8_R2_P2 ( in1, in2, res );
input [7:0] in1;
input [7:0] in2;
output [8:0] res;
wire n14, n15, n16, n17, n18, n19, n20, n21, n22, n23, n24;
CLKAND2X2TS U18 ( .A(in1[0]), .B(in2[0]), .Y(n20) );
XOR2XLTS U19 ( .A(in1[3]), .B(in2[3]), .Y(n17) );
XOR2XLTS U20 ( .A(in1[5]), .B(in2[5]), .Y(n15) );
OAI211XLTS U21 ( .A0(in2[5]), .A1(in1[5]), .B0(in2[4]), .C0(in1[4]), .Y(n22)
);
OAI211XLTS U22 ( .A0(in2[3]), .A1(in1[3]), .B0(in2[2]), .C0(in1[2]), .Y(n14)
);
AOI2BB1XLTS U23 ( .A0N(in1[0]), .A1N(in2[0]), .B0(n20), .Y(res[0]) );
OAI2BB1X1TS U24 ( .A0N(in1[3]), .A1N(in2[3]), .B0(n14), .Y(n19) );
XOR2XLTS U25 ( .A(n16), .B(n15), .Y(res[5]) );
XOR2XLTS U26 ( .A(n18), .B(n17), .Y(res[3]) );
CMPR32X2TS U27 ( .A(in2[4]), .B(in1[4]), .C(n19), .CO(n16), .S(res[4]) );
CMPR32X2TS U28 ( .A(in1[1]), .B(in2[1]), .C(n20), .CO(n21), .S(res[1]) );
CMPR32X2TS U29 ( .A(in1[2]), .B(in2[2]), .C(n21), .CO(n18), .S(res[2]) );
OAI2BB1X1TS U30 ( .A0N(in1[5]), .A1N(in2[5]), .B0(n22), .Y(n23) );
CMPR32X2TS U31 ( .A(in1[6]), .B(in2[6]), .C(n23), .CO(n24), .S(res[6]) );
CMPR32X2TS U32 ( .A(in1[7]), .B(in2[7]), .C(n24), .CO(res[8]), .S(res[7]) );
initial $sdf_annotate("GeAr_N8_R2_P2_syn.sdf");
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLXBN_1_V
`define SKY130_FD_SC_LS__DLXBN_1_V
/**
* dlxbn: Delay latch, inverted enable, complementary outputs.
*
* Verilog wrapper for dlxbn with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__dlxbn.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ls__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__dlxbn_1 (
Q ,
Q_N ,
D ,
GATE_N
);
output Q ;
output Q_N ;
input D ;
input GATE_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__dlxbn base (
.Q(Q),
.Q_N(Q_N),
.D(D),
.GATE_N(GATE_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLXBN_1_V
|
// Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:47:07 MST 2014
// Date : Fri May 6 14:51:06 2016
// Host : graviton running 64-bit Debian GNU/Linux 7.10 (wheezy)
// Command : write_verilog -force -mode synth_stub /home/guest/cae/fpga/ntpserver/ip/ocxo_clk_pll/ocxo_clk_pll_stub.v
// Design : ocxo_clk_pll
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module ocxo_clk_pll(clk_in1, clk_out1, resetn, locked)
/* synthesis syn_black_box black_box_pad_pin="clk_in1,clk_out1,resetn,locked" */;
input clk_in1;
output clk_out1;
input resetn;
output locked;
endmodule
|
`timescale 1ns/1ns
module usb_rx_nrzi
(input c_48,
input vp,
input vm,
input oe,
output d,
output dv,
output eop);
localparam J = 2'b10;
localparam K = 2'b01;
localparam SE0 = 2'b00;
// sharpen the inbound edges. synchronize them to c48
wire [1:0] rx;
sync #(2) input_sync(.in({vp, vm}), .clk(c_48), .out(rx));
// first task: when our driver is not enabled, watch for falling VP which
// implies start-of-packet
localparam ST_IDLE = 4'd0;
localparam ST_INIT = 4'd1;
localparam ST_K = 4'd2;
localparam ST_J = 4'd3;
localparam ST_SE0 = 4'd4;
localparam ST_EOP = 4'd5;
localparam ST_DONE = 4'd6;
localparam ST_ERROR = 4'd7;
localparam SW=4, CW=5;
reg [CW+SW-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CW-1:CW];
r #(SW) state_r
(.c(c_48), .rst(oe), .en(1'b1), .d(next_state), .q(state));
wire [1:0] cnt;
wire cnt_rst;
r #(2) cnt_r
(.c(c_48), .en(1'b1), .rst(cnt_rst), .d(cnt+1'b1), .q(cnt));
wire sample = cnt == 2'd1; // todo: shift this as needed to track tx clock?
wire num_ones_en, num_ones_rst;
wire [2:0] num_ones;
r #(3) num_ones_r
(.c(c_48), .en(num_ones_en), .rst(state == ST_IDLE | (num_ones_rst & sample)),
.d(num_ones+1'b1), .q(num_ones));
always @* begin
case (state)
ST_IDLE:
if (~oe & rx == K) ctrl = { ST_INIT , 5'b00100 };
else ctrl = { ST_IDLE , 5'b00000 };
ST_INIT:
if (sample)
if (rx == K) ctrl = { ST_K , 5'b00001 };
else ctrl = { ST_ERROR, 5'b00000 };
else ctrl = { ST_INIT , 5'b00000 };
ST_K:
if (sample) begin
if (rx == SE0) ctrl = { ST_SE0 , 5'b00000 };
else if (rx == K) ctrl = { ST_K , 5'b01011 }; // same = 1
else if (rx == J) ctrl = { ST_J , 5'b10001 }; // flip = 0
else ctrl = { ST_ERROR, 5'b00000 };
end else ctrl = { ST_K , 5'b00000 };
ST_J:
if (sample) begin
if (rx == SE0) ctrl = { ST_SE0 , 5'b00000 };
else if (rx == J) ctrl = { ST_J , 5'b01011 }; // same = 1
else if (rx == K) ctrl = { ST_K , 5'b10001 }; // flip = 0
else ctrl = { ST_ERROR, 5'b00000 };
end else ctrl = { ST_J , 5'b00000 };
ST_SE0:
if (sample & rx == J) ctrl = { ST_EOP , 5'b00000 };
else ctrl = { ST_SE0 , 5'b00000 };
ST_EOP:
if (sample) ctrl = { ST_DONE , 5'b00000 };
else ctrl = { ST_EOP , 5'b00000 };
ST_DONE: ctrl = { ST_IDLE , 5'b00000 };
ST_ERROR: ctrl = { ST_ERROR, 5'b00000 };
default: ctrl = { ST_IDLE , 5'b00000 };
endcase
end
assign cnt_rst = ctrl[2];
assign dv = ctrl[0] & num_ones != 3'd6;
assign d = ctrl[1];
assign num_ones_en = ctrl[3];
assign num_ones_rst = ctrl[4] | num_ones == 3'd6;
assign eop = state == ST_SE0;
endmodule
|
//=================================================
// PEAK FINDER MODULE
//=================================================
// Returns true detection @ absolute peak, instead of at threshold
// Results are stored in FIFO buffers
module PEAKFINDER # (
parameter taps = 7'd65)(
input SYS_CLK,
input RST,
input NIOS_ADC_ON,
input CLK_EN,
input DETECTION,
input [59:0] Yn_NUM,
input [49:0] Yn_DEN,
input [13:0] TIMER,
input ABS_PEAK_FLAG,
input NIOS_RD_PEAK,
output VALID_PEAK_FOUND,
output [109:0] FIFO_DETECTION_YN1_OUTPUT, FIFO_DETECTION_YN2_OUTPUT, FIFO_DETECTION_YN3_OUTPUT,
output [13:0] FIFO_DETECTION_TIME_OUTPUT
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// LOCAL PEAK FINDER
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Peak is when Yn2 > Yn1, & Yn2 > Yn3:
// Order of point: n1 -> n2 -> n3
wire LOCAL_PEAK, LOCAL_PEAK_Yn2_Yn1, LOCAL_PEAK_Yn2_Yn3;
assign LOCAL_PEAK_Yn2_Yn1 = Shift1Ynum > Shift0Ynum;//( (Shift1Ynum*Shift0Ydensmall) > (Shift1Ydensmall*Shift0Ynum) );
assign LOCAL_PEAK_Yn2_Yn3 = Shift1Ynum > Shift2Ynum;//( (Shift1Ynum*Shift2Ydensmall) > (Shift1Ydensmall*Shift2Ynum) );
assign LOCAL_PEAK = LOCAL_PEAK_Yn2_Yn1 & LOCAL_PEAK_Yn2_Yn3 & DETECTION;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ABSOLUTE PEAK FINDER
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// If the current peak is greater than the previous peak, this is the new Absolute Peak:
wire ABSPeak;
assign ABSPeak = LOCAL_PEAK & (Shift1Ynum > AbsPeak1Num);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// Shift Register:
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// CLK = SYS_CLK
// CLK_EN = FIFO_ADC_RD
// [-->Shift2][Shift1][Shift0-->]
// Yn3 Yn2 Yn1
reg [13:0] TIME_DETECTION, TIME;
reg [59:0] Shift2Ynum, Shift1Ynum, Shift0Ynum;
reg [49:0] Shift2Yden, Shift1Yden, Shift0Yden;
reg [59:0] AbsPeak2Num, AbsPeak1Num, AbsPeak0Num;
reg [49:0] AbsPeak2Den, AbsPeak1Den, AbsPeak0Den;
always @(posedge SYS_CLK) begin
if (RST) begin
Shift2Ynum <= 0;
Shift2Yden <= 0;
Shift1Ynum <= 0;
Shift1Yden <= 0;
Shift0Ynum <= 0;
Shift0Yden <= 0;
TIME_DETECTION <= 0;
AbsPeak2Num <= 0;
AbsPeak2Den <= 0;
AbsPeak1Num <= 0;
AbsPeak1Den <= 0;
AbsPeak0Num <= 0;
AbsPeak0Den <= 0;
end
else begin
Shift2Ynum <= CLK_EN ? Yn_NUM : Shift2Ynum;
Shift2Yden <= CLK_EN ? Yn_DEN : Shift2Yden;
Shift1Ynum <= CLK_EN ? Shift2Ynum : Shift1Ynum;
Shift1Yden <= CLK_EN ? Shift2Yden : Shift1Yden;
Shift0Ynum <= CLK_EN ? Shift1Ynum : Shift0Ynum;
Shift0Yden <= CLK_EN ? Shift1Yden : Shift0Yden;
TIME_DETECTION <= CLK_EN ? TIMER : TIME_DETECTION;
AbsPeak2Num <= ABSPeak ? Shift2Ynum : AbsPeak2Num;
AbsPeak2Den <= ABSPeak ? Shift2Yden : AbsPeak2Den;
AbsPeak1Num <= ABSPeak ? Shift1Ynum : AbsPeak1Num;
AbsPeak1Den <= ABSPeak ? Shift1Yden : AbsPeak1Den;
AbsPeak0Num <= ABSPeak ? Shift0Ynum : AbsPeak0Num;
AbsPeak0Den <= ABSPeak ? Shift0Yden : AbsPeak0Den;
TIME <= ABSPeak ? TIME_DETECTION+1-taps : TIME;
end
end
wire valid_peak_logic1 = ~FIFO_DETECTION_YN1_EMPTY & ~FIFO_DETECTION_YN2_EMPTY;
wire valid_peak_logic2 = ~FIFO_DETECTION_YN3_EMPTY & ~FIFO_DETECTION_TIME_EMPTY;
assign VALID_PEAK_FOUND = valid_peak_logic1 & valid_peak_logic2;
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DETECTION FIFO - Yn: 110-bits wide, 8 words depth
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire FIFO_DETECTION_YN1_EMPTY, FIFO_DETECTION_YN1_FULL;
FIFO_DETECTION_YN FIFO_DETECTION_YN1_instant (
.clock ( SYS_CLK ),
.sclr ( RST ),
.rdreq ( NIOS_RD_PEAK ),
.wrreq ( ABS_PEAK_FLAG ),
.data ( {AbsPeak0Num, AbsPeak0Den} ),
.empty ( FIFO_DETECTION_YN1_EMPTY ),
.full ( FIFO_DETECTION_YN1_FULL ),
.q ( FIFO_DETECTION_YN1_OUTPUT )
);
wire FIFO_DETECTION_YN2_EMPTY, FIFO_DETECTION_YN2_FULL;
FIFO_DETECTION_YN FIFO_DETECTION_YN2_instant (
.clock ( SYS_CLK ),
.sclr ( RST ),
.rdreq ( NIOS_RD_PEAK ),
.wrreq ( ABS_PEAK_FLAG ),
.data ( {AbsPeak1Num, AbsPeak1Den} ),
.empty ( FIFO_DETECTION_YN2_EMPTY ),
.full ( FIFO_DETECTION_YN2_FULL ),
.q ( FIFO_DETECTION_YN2_OUTPUT )
);
wire FIFO_DETECTION_YN3_EMPTY, FIFO_DETECTION_YN3_FULL;
FIFO_DETECTION_YN FIFO_DETECTION_YN3_instant (
.clock ( SYS_CLK ),
.sclr ( RST ),
.rdreq ( NIOS_RD_PEAK ),
.wrreq ( ABS_PEAK_FLAG ),
.data ( {AbsPeak2Num, AbsPeak2Den} ),
.empty ( FIFO_DETECTION_YN3_EMPTY ),
.full ( FIFO_DETECTION_YN3_FULL ),
.q ( FIFO_DETECTION_YN3_OUTPUT )
);
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// DETECTION FIFO - Time: 14-bits wide, 8 words depth
//~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire FIFO_DETECTION_TIME_EMPTY, FIFO_DETECTION_TIME_FULL;
FIFO_DETECTION_TIME FIFO_DETECTION_TIME_instant (
.clock ( SYS_CLK ),
.sclr ( RST ),
.rdreq ( NIOS_RD_PEAK ),
.wrreq ( ABS_PEAK_FLAG ),
.data ( TIME ),
.empty ( FIFO_DETECTION_TIME_EMPTY ),
.full ( FIFO_DETECTION_TIME_FULL ),
.q ( FIFO_DETECTION_TIME_OUTPUT )
);
endmodule
//=================================================
// END PEAK FINDER MODULE
//=================================================
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module burst_converter
#(
parameter IADDR = 32,
parameter OADDR = 32
)
(
input wire clk_sys,
input wire rst,
input wire [IADDR-1:0] addr_in,
input wire write_in,
input wire [31:0] writedata_in,
input wire read_in,
output wire [31:0] readdata_out,
output wire readdatavalid_out,
input wire [3:0] byteenable_in,
input wire [2:0] burstcount_in,
output wire waitrequest_out,
output wire [OADDR-1:0] addr_out,
output wire write_out,
output wire [31:0] writedata_out,
output wire read_out,
input wire [31:0] readdata_in,
input wire readdatavalid_in,
output wire [3:0] byteenable_out,
input wire waitrequest_in
);
// data
// data[8] = valid bit
reg [IADDR-1:0] raddr, waddr;
reg [3:0] rcount, wcount;
assign addr_out = (rcount[1]) ? raddr + 4 :
(rcount[2]) ? raddr + 8 :
(rcount[3]) ? raddr + 12 :
(wcount[1]) ? waddr + 4 :
(wcount[2]) ? waddr + 8 :
(wcount[3]) ? waddr + 12 : addr_in;
assign writedata_out = writedata_in;
assign byteenable_out = byteenable_in;
assign write_out = write_in;
assign read_out = (read_in && burstcount_in != 0) || rcount;
assign readdata_out = readdata_in;
assign readdatavalid_out = readdatavalid_in;
assign waitrequest_out = waitrequest_in;
/////////////////////////////////////////////////////////////////////////
// burst write
/////////////////////////////////////////////////////////////////////////
always @(posedge clk_sys) begin
if(rst) begin
wcount <= 0;
waddr <= 0;
end else if(wcount[1] && !waitrequest_in) begin
wcount[1] <= 0;
end else if(wcount[2] && !waitrequest_in) begin
wcount[2] <= 0;
end else if(wcount[3] && !waitrequest_in) begin
wcount[3] <= 0;
end else if(burstcount_in > 1 && write_in && !waitrequest_out) begin
waddr <= addr_in;
wcount <= (burstcount_in == 4) ? 4'b1110 :
(burstcount_in == 3) ? 4'b0110 :
(burstcount_in == 2) ? 4'b0010 : 0;
end
end
/////////////////////////////////////////////////////////////////////////
// burst read
/////////////////////////////////////////////////////////////////////////
always @(posedge clk_sys) begin
if(rst) begin
rcount <= 0;
raddr <= 0;
end else if(rcount[1] && !waitrequest_in) begin
rcount[1] <= 0;
end else if(rcount[2] && !waitrequest_in) begin
rcount[2] <= 0;
end else if(rcount[3] && !waitrequest_in) begin
rcount[3] <= 0;
end else if(burstcount_in > 1 && read_in && !waitrequest_out) begin
raddr <= addr_in;
rcount <= (burstcount_in == 4) ? 4'b1110 :
(burstcount_in == 3) ? 4'b0110 :
(burstcount_in == 2) ? 4'b0010 : 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_SYMBOL_V
`define SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_SYMBOL_V
/**
* UDP_OUT :=x when VPWR!=1 or VGND!=0
* UDP_OUT :=UDP_IN when VPWR==1 and VGND==0
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__udp_pwrgood$l_pp$PG$S (
//# {{data|Data Signals}}
input UDP_IN ,
output UDP_OUT,
//# {{power|Power}}
input SLEEP ,
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__UDP_PWRGOOD_L_PP_PG_S_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRBP_LP_V
`define SKY130_FD_SC_LP__DLRBP_LP_V
/**
* dlrbp: Delay latch, inverted reset, non-inverted enable,
* complementary outputs.
*
* Verilog wrapper for dlrbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrbp_lp (
Q ,
Q_N ,
RESET_B,
D ,
GATE
);
output Q ;
output Q_N ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrbp base (
.Q(Q),
.Q_N(Q_N),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRBP_LP_V
|
//uart_io_handler.v
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
06/24/2012
-Added host interface reset to reset the state machine
12/16/2011
-fixed a bug in the data output count where it was sending
5 bits instead of 4
*/
//generalize the uart handler
`include "cbuilder_defines.v"
module uart_io_handler #(
parameter BAUDRATE = 115200
)(
//input/output signals
input clk,
input rst,
//input handler
output reg o_ih_ready,
output o_ih_reset,
input i_master_ready,
output reg [31:0] o_in_command,
output reg [31:0] o_in_address,
output reg [31:0] o_in_data,
output reg [27:0] o_in_data_count,
//output handler
output reg o_oh_ready,
input i_oh_en,
input [31:0] i_out_status,
input [31:0] i_out_address,
input [31:0] i_out_data,
input [27:0] i_out_data_count,
//these are the only thing that are different between xxx_io_handler
input i_phy_uart_in,
output o_phy_uart_out
);
//STATES
localparam IDLE = 4'h0;
localparam READ_DATA_COUNT = 4'h1;
localparam READ_CONTROL = 4'h2;
localparam READ_ADDRESS = 4'h3;
localparam READ_DATA = 4'h4;
localparam WRITE_TO_MASTER = 4'h5;
localparam WRITE_DATA_COUNT = 4'h1;
localparam WRITE_STATUS = 4'h2;
localparam WRITE_ADDRESS = 4'h3;
localparam WRITE_DATA = 4'h4;
localparam SEND_DATA_TO_HOST= 4'h5;
localparam CHAR_L = 8'h4C;
localparam CHAR_0 = 8'h30;
localparam CHAR_HEX_OFFSET = 8'h37;
localparam CHAR_A = 8'h41;
localparam CHAR_F = 8'h46;
localparam CHAR_S = 8'h53;
//Registers/Wires
reg [3:0] in_state;
reg [3:0] out_state;
reg [3:0] in_nibble_count;
reg [3:0] out_nibble_count;
reg [15:0] r_count;
wire [15:0] user_command;
wire is_writing;
wire is_reading;
reg [7:0] out_byte;
wire in_byte_available;
wire [7:0] in_byte;
wire uart_in_busy;
reg [27:0] in_data_count;
wire uart_out_busy;
wire uart_tx_ready;
reg uart_out_byte_en;
reg oh_finished;
reg uart_wait_for_tx;
reg [27:0] li_out_data_count;
reg [27:0] li_out_data_count_buf;
reg [27:0] out_data_count;
reg [27:0] out_data_pos;
reg [31:0] li_out_data;
reg [31:0] li_out_status;
reg [31:0] li_out_address;
wire [3:0] in_nibble;
wire illegal_value;
wire [7:0] gen_data_count;
wire [7:0] gen_status;
wire [7:0] gen_addr;
wire [7:0] gen_data;
//Submodules
uart #(
.DEFAULT_BAUDRATE (BAUDRATE )
)uart(
.clk (clk ),
.rst (rst ),
.tx (o_phy_uart_out ),
.transmit (uart_out_byte_en ),
.tx_byte (out_byte ),
.is_transmitting (uart_out_busy ),
.rx (i_phy_uart_in ),
.rx_error ( ),
.rx_byte (in_byte ),
.received (in_byte_available ),
.is_receiving (uart_in_busy ),
.prescaler ( ),
.set_clock_div (1'b0 ),
.user_clock_div (def_clock_div ),
.default_clock_div (def_clock_div )
);
//Asynchronous Logic
assign user_command = o_in_command[15:0];
assign is_writing = (user_command == `COMMAND_WRITE);
assign is_reading = (user_command == `COMMAND_READ);
assign o_ih_reset = 0;
assign uart_tx_ready = ~uart_out_busy;
assign in_nibble = (in_byte >= CHAR_A) ? (in_byte - CHAR_HEX_OFFSET) :
(in_byte - CHAR_0);
assign illegal_value = (in_byte < CHAR_0) || ((in_byte > CHAR_0 + 10) && (in_byte < CHAR_A)) || (in_byte > CHAR_F);
assign gen_data_count = (li_out_data_count_buf[27:24] < 10) ? li_out_data_count_buf[27:24] + CHAR_0 : li_out_data_count_buf[27:24] + CHAR_HEX_OFFSET;
assign gen_status = (li_out_status[31:28] < 10) ? li_out_status[31:28] + CHAR_0 : li_out_status + CHAR_HEX_OFFSET;
assign gen_address = (li_out_address[31:28] < 10) ? li_out_address[31:28] + CHAR_0 : li_out_address[31:28] + CHAR_HEX_OFFSET;
assign gen_data = (li_out_data[31:28] < 10) ? li_out_data[31:28] + CHAR_0 : li_out_data[31:28] + CHAR_HEX_OFFSET;
//Synchronous Logic
//input handler
always @ (posedge clk) begin
o_ih_ready <= 0;
if (rst) begin
o_in_command <= 32'h0000;
o_in_address <= 32'h0000;
o_in_data <= 32'h0000;
in_state <= IDLE;
in_nibble_count <= 4'h0;
o_in_data_count <= 27'h0;
in_data_count <= 0;
end
else begin
//main state machine goes here
case (in_state)
IDLE: begin
//putting this here lets master hold onto the data for
//a longer time
if (in_byte_available) begin
if (in_byte == CHAR_L) begin
//read the first of in_byte
in_state <= READ_DATA_COUNT;
o_in_command <= 32'h0000;
o_in_address <= 32'h0000;
o_in_data <= 32'h0000;
o_in_data_count <= 27'h000;
in_data_count <= 0;
in_nibble_count <= 4'h0;
end
end
end
READ_DATA_COUNT: begin
if (in_byte_available) begin
if (illegal_value) begin
//invalid character go back to IDLE
in_state <= IDLE;
end
else begin
//valid character
o_in_data_count <= {o_in_data_count[23:0], in_nibble};
in_nibble_count <= in_nibble_count + 1;
end
end
if (in_nibble_count > 6) begin
in_nibble_count <= 4'h0;
in_state <= READ_CONTROL;
end
end
READ_CONTROL: begin
if (in_byte_available) begin
if (illegal_value) begin
in_state <= IDLE;
end
else begin
o_in_command <= {o_in_command[27:0], in_nibble};
in_nibble_count <= in_nibble_count + 1;
end
end
if (in_nibble_count > 7) begin
in_state <= READ_ADDRESS;
in_nibble_count <= 4'h0;
end
end
READ_ADDRESS: begin
//read the size
if (in_byte_available) begin
if (illegal_value) begin
in_state <= IDLE;
end
else begin
o_in_address <= {o_in_address[27:0], in_nibble};
in_nibble_count <= in_nibble_count + 1;
end
end
if (in_nibble_count > 7) begin
in_state <= READ_DATA;
in_nibble_count <= 4'h0;
end
end
READ_DATA : begin
if (in_byte_available) begin
if (illegal_value) begin
in_state <= IDLE;
end
else begin
o_in_data <= {o_in_data[27:0], in_nibble};
in_nibble_count <= in_nibble_count + 1;
end
end //if in byte available
if (in_nibble_count > 7) begin
in_state <= WRITE_TO_MASTER;
in_nibble_count <= 4'h0;
in_data_count <= in_data_count + 1;
end
end
WRITE_TO_MASTER: begin
if (i_master_ready) begin
o_ih_ready <= 1;
if (is_writing && (in_data_count < o_in_data_count)) begin
in_state <= READ_DATA;
end
else begin
in_state <= IDLE;
end
end
end
default: begin
o_in_command <= 8'h0;
in_state <= IDLE;
end
endcase
end
end
//output handler
always @ (posedge clk) begin
//uart_out_byte_en should only be high for one clock cycle
oh_finished <= 0;
uart_out_byte_en <= 0;
o_oh_ready <= 0;
if (rst) begin
out_state <= IDLE;
out_nibble_count <= 4'h0;
out_byte <= 8'h0;
li_out_data_count <= 27'h0;
li_out_data_count_buf <= 27'h0;
li_out_data <= 32'h0;
li_out_status <= 32'h0;
li_out_address <= 32'h0;
uart_wait_for_tx <= 0;
o_oh_ready <= 0;
out_data_count <= 0;
out_data_pos <= 0;
end
else begin
//don't do anything until the UART is ready
if (~uart_wait_for_tx & uart_tx_ready) begin
case (out_state)
IDLE: begin
out_byte <= 8'h0;
out_nibble_count <= 4'h0;
o_oh_ready <= 1'h1;
out_data_pos <= 0;
if (i_oh_en) begin
//moved this outside because by the time it reaches this part, the out data_count is
//changed
li_out_status <= i_out_status;
li_out_address <= i_out_address;
li_out_data <= i_out_data;
out_byte <= CHAR_S;
out_state <= WRITE_DATA_COUNT;
o_oh_ready <= 0;
uart_out_byte_en <= 1;
uart_wait_for_tx <= 1;
end
else begin
li_out_data_count <= 0;
li_out_data_count_buf <= i_out_data_count;
out_data_count <= i_out_data_count;
end
end
WRITE_DATA_COUNT: begin
out_byte <= gen_data_count;
li_out_data_count_buf <= li_out_data_count_buf[27:0] << 4;
uart_out_byte_en <= 1;
uart_wait_for_tx <= 1;
if (out_nibble_count >= 6) begin
out_state <= WRITE_STATUS;
out_nibble_count <= 4'h0;
end
else begin
out_nibble_count <= out_nibble_count + 1;
end
end
WRITE_STATUS: begin
out_byte <= gen_status;
li_out_status <= (li_out_status[31:0] << 4);
uart_out_byte_en <= 1;
uart_wait_for_tx <= 1;
if (out_nibble_count >= 7) begin
out_state <= WRITE_ADDRESS;
out_nibble_count <= 4'h0;
end
else begin
out_nibble_count <= out_nibble_count + 1;
end
end
WRITE_ADDRESS: begin
out_byte <= gen_address;
li_out_address <= (li_out_address[31:0] << 4);
uart_out_byte_en <= 1;
uart_wait_for_tx <= 1;
if (out_nibble_count >= 7) begin
out_state <= WRITE_DATA;
out_nibble_count <= 4'h0;
end
else begin
out_nibble_count <= out_nibble_count + 1;
end
end
WRITE_DATA: begin
out_byte <= gen_data;
li_out_data <= (li_out_data[28:0] << 4);
uart_out_byte_en <= 1;
uart_wait_for_tx <= 1;
out_nibble_count <= out_nibble_count + 1;
if (out_nibble_count >= 7) begin
out_state <= SEND_DATA_TO_HOST;
out_data_pos <= out_data_pos + 1;
out_nibble_count <= 4'h0;
end
end
SEND_DATA_TO_HOST: begin
if (out_data_pos < out_data_count) begin
o_oh_ready <= 1;
if (i_oh_en && o_oh_ready) begin
li_out_data <= i_out_data;
out_state <= WRITE_DATA;
end
end
else begin
oh_finished <= 1;
out_state <= IDLE;
end
end
default: begin
out_state <= IDLE;
end
endcase
end
end
if (~uart_tx_ready) begin
uart_wait_for_tx <= 0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21BOI_2_V
`define SKY130_FD_SC_HDLL__A21BOI_2_V
/**
* a21boi: 2-input AND into first input of 2-input NOR,
* 2nd input inverted.
*
* Y = !((A1 & A2) | (!B1_N))
*
* Verilog wrapper for a21boi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a21boi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a21boi_2 (
Y ,
A1 ,
A2 ,
B1_N
);
output Y ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a21boi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21BOI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
`define SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a221oi (
Y ,
A1,
A2,
B1,
B2,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
// Local signals
wire and0_out ;
wire and1_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
and and1 (and1_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, C1, and1_out);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A221OI_FUNCTIONAL_V |
//#############################################################################
//# Function: Parametrized asynchronous clock FIFO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_async # (parameter DW = 104, // FIFO width
parameter DEPTH = 32, // FIFO depth (entries)
parameter TARGET = "GENERIC",// XILINX,ALTERA,GENERIC,ASIC
parameter PROG_FULL = (DEPTH/2),// program full threshold
parameter AW = $clog2(DEPTH) // binary read count width
)
(
input nreset, // async reset
//Write Side
input wr_clk, // write clock
input wr_en, // write fifo
input [DW-1:0] din, // data to write
//Read Side
input rd_clk, // read clock
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
//Status
output full, // fifo is full
output prog_full, // fifo reaches full threshold
output empty, // fifo is empty
output [AW-1:0] rd_count // # of valid entries in fifo
);
//local wires
wire [AW-1:0] wr_count; // valid entries in fifo
generate
if (TARGET=="XILINX") begin : xilinx
if((DW==104) & (DEPTH==32))
begin : g104x32
fifo_async_104x32
fifo (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_data_count (rd_count[AW-1:0]),
// Inputs
.rst (~nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end // if ((DW==104) & (DEPTH==32))
end
else begin : generic
oh_fifo_generic #(.DEPTH(DEPTH),
.DW(DW))
fifo_generic (
// Outputs
.full (full),
.prog_full (prog_full),
.dout (dout[DW-1:0]),
.empty (empty),
.rd_count (rd_count[AW-1:0]),
.wr_count (wr_count[AW-1:0]),
// Inputs
.nreset (nreset),
.wr_clk (wr_clk),
.rd_clk (rd_clk),
.wr_en (wr_en),
.din (din[DW-1:0]),
.rd_en (rd_en));
end
endgenerate
endmodule // oh_fifo_async
// Local Variables:
// verilog-library-directories:("." "../fpga/" "../dv")
// End:
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__A21O_FUNCTIONAL_V
`define SKY130_FD_SC_HVL__A21O_FUNCTIONAL_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hvl__a21o (
X ,
A1,
A2,
B1
);
// Module ports
output X ;
input A1;
input A2;
input B1;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HVL__A21O_FUNCTIONAL_V |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/03 11:36:14
// Design Name:
// Module Name: full_adder_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module full_adder_tb(
);
parameter TIME = 600;
parameter DELAY = 50;
reg Ai,Bi,Ci_1;
wire F,Si,Ci;
integer i, j;
// full_adder DUT (.Ai(Ai), .Bi(Bi), .Ci_1(Ci_1), .F(F), .Ci(Ci), .Si(Si));
full_adder_fix DUT (.Ai(Ai), .Bi(Bi), .Ci_1(Ci_1), .F(F), .Ci(Ci), .Si(Si));
initial begin
#TIME $finish;
end
initial
begin
Ai = 0; Bi = 0;
Ci_1 = 0;
for (i = 0;i < 2; i = i + 1) begin
#DELAY Ai = i;
for (j = 0;j < 2;j = j + 1) begin
#DELAY Bi = j;
end
end
Ci_1 = 1;
for (i = 0;i < 2; i = i + 1) begin
#DELAY Ai = i;
for (j = 0;j < 2;j = j + 1) begin
#DELAY Bi = j;
end
end
end
endmodule
|
/* Generated by Yosys 0.3.0+ (git sha1 3b52121) */
(* src = "../../verilog/max6682.v:133" *)
module MAX6682(Reset_n_i, Clk_i, Enable_i, CpuIntr_o, MAX6682CS_n_o, SPI_Data_i, SPI_Write_o, SPI_ReadNext_o, SPI_Data_o, SPI_FIFOFull_i, SPI_FIFOEmpty_i, SPI_Transmission_i, PeriodCounterPresetH_i, PeriodCounterPresetL_i, SensorValue_o, Threshold_i, SPI_CPOL_o, SPI_CPHA_o, SPI_LSBFE_o);
(* src = "../../verilog/max6682.v:297" *)
wire [31:0] \$0\SensorFSM_Timer[31:0] ;
(* src = "../../verilog/max6682.v:327" *)
wire [15:0] \$0\Word0[15:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SPI_FSM_Start[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SensorFSM_StoreNewValue[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$2\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$3\SensorFSM_TimerPreset[0:0] ;
(* src = "../../verilog/max6682.v:231" *)
wire \$4\SensorFSM_TimerPreset[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$732 ;
wire \$procmux$118_CMP ;
wire \$procmux$123_CMP ;
wire \$procmux$126_CMP ;
wire [31:0] \$procmux$449_Y ;
(* src = "../../verilog/max6682.v:311" *)
wire [31:0] \$sub$../../verilog/max6682.v:311$18_Y ;
(* src = "../../verilog/max6682.v:323" *)
wire [15:0] AbsDiffResult;
(* src = "../../verilog/max6682.v:184" *)
wire [7:0] Byte0;
(* src = "../../verilog/max6682.v:185" *)
wire [7:0] Byte1;
(* intersynth_port = "Clk_i" *)
(* src = "../../verilog/max6682.v:137" *)
input Clk_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIRQs_s" *)
(* src = "../../verilog/max6682.v:141" *)
output CpuIntr_o;
(* src = "../../verilog/max6682.v:342" *)
wire [16:0] DiffAB;
(* src = "../../verilog/max6682.v:343" *)
wire [15:0] DiffBA;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "ReconfModuleIn_s" *)
(* src = "../../verilog/max6682.v:139" *)
input Enable_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "Outputs_o" *)
(* src = "../../verilog/max6682.v:143" *)
output MAX6682CS_n_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetH_i" *)
(* src = "../../verilog/max6682.v:159" *)
input [15:0] PeriodCounterPresetH_i;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "PeriodCounterPresetL_i" *)
(* src = "../../verilog/max6682.v:161" *)
input [15:0] PeriodCounterPresetL_i;
(* intersynth_port = "Reset_n_i" *)
(* src = "../../verilog/max6682.v:135" *)
input Reset_n_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPHA" *)
(* src = "../../verilog/max6682.v:169" *)
output SPI_CPHA_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_CPOL" *)
(* src = "../../verilog/max6682.v:167" *)
output SPI_CPOL_o;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataOut" *)
(* src = "../../verilog/max6682.v:145" *)
input [7:0] SPI_Data_i;
(* intersynth_conntype = "Byte" *)
(* intersynth_port = "SPI_DataIn" *)
(* src = "../../verilog/max6682.v:151" *)
output [7:0] SPI_Data_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOEmpty" *)
(* src = "../../verilog/max6682.v:155" *)
input SPI_FIFOEmpty_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_FIFOFull" *)
(* src = "../../verilog/max6682.v:153" *)
input SPI_FIFOFull_i;
(* src = "../../verilog/max6682.v:183" *)
wire SPI_FSM_Done;
(* src = "../../verilog/max6682.v:182" *)
wire SPI_FSM_Start;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_LSBFE" *)
(* src = "../../verilog/max6682.v:171" *)
output SPI_LSBFE_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_ReadNext" *)
(* src = "../../verilog/max6682.v:149" *)
output SPI_ReadNext_o;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Transmission" *)
(* src = "../../verilog/max6682.v:157" *)
input SPI_Transmission_i;
(* intersynth_conntype = "Bit" *)
(* intersynth_port = "SPI_Write" *)
(* src = "../../verilog/max6682.v:147" *)
output SPI_Write_o;
(* src = "../../verilog/max6682.v:215" *)
wire SensorFSM_DiffTooLarge;
(* src = "../../verilog/max6682.v:216" *)
wire SensorFSM_StoreNewValue;
(* src = "../../verilog/max6682.v:295" *)
wire [31:0] SensorFSM_Timer;
(* src = "../../verilog/max6682.v:214" *)
wire SensorFSM_TimerEnable;
(* src = "../../verilog/max6682.v:212" *)
wire SensorFSM_TimerOvfl;
(* src = "../../verilog/max6682.v:213" *)
wire SensorFSM_TimerPreset;
(* src = "../../verilog/max6682.v:321" *)
wire [15:0] SensorValue;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "SensorValue_o" *)
(* src = "../../verilog/max6682.v:163" *)
output [15:0] SensorValue_o;
(* intersynth_conntype = "Word" *)
(* intersynth_param = "Threshold_i" *)
(* src = "../../verilog/max6682.v:165" *)
input [15:0] Threshold_i;
(* src = "../../verilog/max6682.v:322" *)
wire [15:0] Word0;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000011),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$733 (
.A({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$732 )
);
(* src = "../../verilog/max6682.v:316" *)
\$eq #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000100000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$eq$../../verilog/max6682.v:316$19 (
.A(SensorFSM_Timer),
.B(0),
.Y(SensorFSM_TimerOvfl)
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:210" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000100),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000011),
.NAME("\\SensorFSM_State"),
.STATE_BITS(32'b00000000000000000000000000000010),
.STATE_NUM(32'b00000000000000000000000000000100),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(8'b11011000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(117'b011zzzz0100000100zz10100100101zz1001010010zzz0000010001z11z011001001z01z010001001zz0z001001000zzz1010100000zzz0000100)
) \$fsm$\SensorFSM_State$738 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SensorFSM_TimerOvfl, SensorFSM_DiffTooLarge, SPI_FSM_Done, Enable_i }),
.CTRL_OUT({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP })
);
(* src = "../../verilog/max6682.v:348" *)
\$gt #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$gt$../../verilog/max6682.v:348$26 (
.A(AbsDiffResult),
.B(Threshold_i),
.Y(SensorFSM_DiffTooLarge)
);
(* src = "../../verilog/max6682.v:297" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(32'b00000000000000000000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000100000)
) \$procdff$727 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\SensorFSM_Timer[31:0] ),
.Q(SensorFSM_Timer)
);
(* src = "../../verilog/max6682.v:327" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(16'b0000000000000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000010000)
) \$procdff$728 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Word0[15:0] ),
.Q(Word0)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$117 (
.A(\$auto$opt_reduce.cc:126:opt_mux$732 ),
.Y(CpuIntr_o)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$137 (
.A(\$procmux$123_CMP ),
.B(\$2\SPI_FSM_Start[0:0] ),
.Y(SPI_FSM_Start)
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$147 (
.A(\$procmux$118_CMP ),
.B(\$2\SensorFSM_StoreNewValue[0:0] ),
.Y(SensorFSM_StoreNewValue)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$177 (
.A(1'b0),
.B({ Enable_i, 1'b1, \$2\SensorFSM_StoreNewValue[0:0] }),
.S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(SensorFSM_TimerEnable)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000011),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$192 (
.A(1'b1),
.B({ \$2\SensorFSM_TimerPreset[0:0] , 1'b0, \$3\SensorFSM_TimerPreset[0:0] }),
.S({ \$procmux$126_CMP , \$procmux$123_CMP , \$procmux$118_CMP }),
.Y(SensorFSM_TimerPreset)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$230 (
.A(Enable_i),
.Y(\$2\SensorFSM_TimerPreset[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$259 (
.A(Enable_i),
.B(SensorFSM_TimerOvfl),
.Y(\$2\SPI_FSM_Start[0:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$336 (
.A(SPI_FSM_Done),
.B(SensorFSM_DiffTooLarge),
.Y(\$2\SensorFSM_StoreNewValue[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$368 (
.A(1'b1),
.B(\$4\SensorFSM_TimerPreset[0:0] ),
.S(SPI_FSM_Done),
.Y(\$3\SensorFSM_TimerPreset[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$400 (
.A(SensorFSM_DiffTooLarge),
.Y(\$4\SensorFSM_TimerPreset[0:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$449 (
.A(SensorFSM_Timer),
.B(\$sub$../../verilog/max6682.v:311$18_Y ),
.S(SensorFSM_TimerEnable),
.Y(\$procmux$449_Y )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000100000)
) \$procmux$452 (
.A(\$procmux$449_Y ),
.B({ PeriodCounterPresetH_i, PeriodCounterPresetL_i }),
.S(SensorFSM_TimerPreset),
.Y(\$0\SensorFSM_Timer[31:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$procmux$455 (
.A(Word0),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.S(SensorFSM_StoreNewValue),
.Y(\$0\Word0[15:0] )
);
(* src = "../../verilog/max6682.v:311" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000100000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000100000)
) \$sub$../../verilog/max6682.v:311$18 (
.A(SensorFSM_Timer),
.B(1'b1),
.Y(\$sub$../../verilog/max6682.v:311$18_Y )
);
(* src = "../../verilog/max6682.v:344" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010001),
.Y_WIDTH(32'b00000000000000000000000000010001)
) \$sub$../../verilog/max6682.v:344$23 (
.A({ 6'b000000, Byte1, Byte0[7:5] }),
.B({ 1'b0, Word0 }),
.Y(DiffAB)
);
(* src = "../../verilog/max6682.v:345" *)
\$sub #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000010000),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000010000),
.Y_WIDTH(32'b00000000000000000000000000010000)
) \$sub$../../verilog/max6682.v:345$24 (
.A(Word0),
.B({ 5'b00000, Byte1, Byte0[7:5] }),
.Y(DiffBA)
);
(* src = "../../verilog/max6682.v:346" *)
\$mux #(
.WIDTH(32'b00000000000000000000000000010000)
) \$ternary$../../verilog/max6682.v:346$25 (
.A(DiffAB[15:0]),
.B(DiffBA),
.S(DiffAB[16]),
.Y(AbsDiffResult)
);
(* src = "../../verilog/max6682.v:187" *)
MAX6682_SPI_FSM MAX6682_SPI_FSM_1 (
.Byte0(Byte0),
.Byte1(Byte1),
.Clk_i(Clk_i),
.MAX6682CS_n_o(MAX6682CS_n_o),
.Reset_n_i(Reset_n_i),
.SPI_Data_i(SPI_Data_i),
.SPI_FSM_Done(SPI_FSM_Done),
.SPI_FSM_Start(SPI_FSM_Start),
.SPI_ReadNext_o(SPI_ReadNext_o),
.SPI_Transmission_i(SPI_Transmission_i),
.SPI_Write_o(SPI_Write_o)
);
assign SPI_CPHA_o = 1'b0;
assign SPI_CPOL_o = 1'b0;
assign SPI_Data_o = 8'b00000000;
assign SPI_LSBFE_o = 1'b0;
assign SensorValue = { 5'b00000, Byte1, Byte0[7:5] };
assign SensorValue_o = Word0;
endmodule
(* src = "../../verilog/max6682.v:1" *)
module MAX6682_SPI_FSM(Reset_n_i, Clk_i, SPI_FSM_Start, SPI_Transmission_i, MAX6682CS_n_o, SPI_Write_o, SPI_ReadNext_o, SPI_FSM_Done, SPI_Data_i, Byte0, Byte1);
(* src = "../../verilog/max6682.v:111" *)
wire [7:0] \$0\Byte0[7:0] ;
(* src = "../../verilog/max6682.v:111" *)
wire [7:0] \$0\Byte1[7:0] ;
(* src = "../../verilog/max6682.v:50" *)
wire \$2\MAX6682CS_n_o[0:0] ;
(* src = "../../verilog/max6682.v:50" *)
wire \$2\SPI_FSM_Wr1[0:0] ;
wire \$auto$opt_reduce.cc:126:opt_mux$736 ;
wire \$procmux$553_CMP ;
wire \$procmux$554_CMP ;
wire \$procmux$558_CMP ;
wire \$procmux$559_CMP ;
wire \$procmux$560_CMP ;
wire \$procmux$563_CMP ;
(* src = "../../verilog/max6682.v:11" *)
output [7:0] Byte0;
(* src = "../../verilog/max6682.v:12" *)
output [7:0] Byte1;
(* src = "../../verilog/max6682.v:3" *)
input Clk_i;
(* src = "../../verilog/max6682.v:6" *)
output MAX6682CS_n_o;
(* src = "../../verilog/max6682.v:2" *)
input Reset_n_i;
(* src = "../../verilog/max6682.v:10" *)
input [7:0] SPI_Data_i;
(* src = "../../verilog/max6682.v:9" *)
output SPI_FSM_Done;
(* src = "../../verilog/max6682.v:4" *)
input SPI_FSM_Start;
(* src = "../../verilog/max6682.v:24" *)
wire SPI_FSM_Wr0;
(* src = "../../verilog/max6682.v:23" *)
wire SPI_FSM_Wr1;
(* src = "../../verilog/max6682.v:8" *)
output SPI_ReadNext_o;
(* src = "../../verilog/max6682.v:5" *)
input SPI_Transmission_i;
(* src = "../../verilog/max6682.v:7" *)
output SPI_Write_o;
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000010),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$735 (
.A({ \$procmux$554_CMP , \$procmux$553_CMP }),
.Y(SPI_FSM_Done)
);
\$reduce_or #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000100),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$auto$opt_reduce.cc:130:opt_mux$737 (
.A({ SPI_FSM_Wr0, \$procmux$560_CMP , \$procmux$559_CMP , \$procmux$558_CMP }),
.Y(\$auto$opt_reduce.cc:126:opt_mux$736 )
);
(* fsm_encoding = "auto" *)
(* src = "../../verilog/max6682.v:21" *)
\$fsm #(
.ARST_POLARITY(1'b0),
.CLK_POLARITY(1'b1),
.CTRL_IN_WIDTH(32'b00000000000000000000000000000010),
.CTRL_OUT_WIDTH(32'b00000000000000000000000000000111),
.NAME("\\SPI_FSM_State"),
.STATE_BITS(32'b00000000000000000000000000000011),
.STATE_NUM(32'b00000000000000000000000000000111),
.STATE_NUM_LOG2(32'b00000000000000000000000000000011),
.STATE_RST(32'b00000000000000000000000000000000),
.STATE_TABLE(21'b011101001110010100000),
.TRANS_NUM(32'b00000000000000000000000000001001),
.TRANS_TABLE(135'b1101z11000001001100z0010000100101zz0110000010100zz0100010000011zz0000000001010zz1100001000001zz1011000000000z11000100000000z00000100000)
) \$fsm$\SPI_FSM_State$743 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.CTRL_IN({ SPI_Transmission_i, SPI_FSM_Start }),
.CTRL_OUT({ SPI_FSM_Wr0, \$procmux$563_CMP , \$procmux$560_CMP , \$procmux$559_CMP , \$procmux$558_CMP , \$procmux$554_CMP , \$procmux$553_CMP })
);
(* src = "../../verilog/max6682.v:111" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$729 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte0[7:0] ),
.Q(Byte0)
);
(* src = "../../verilog/max6682.v:111" *)
\$adff #(
.ARST_POLARITY(1'b0),
.ARST_VALUE(8'b00000000),
.CLK_POLARITY(1'b1),
.WIDTH(32'b00000000000000000000000000001000)
) \$procdff$730 (
.ARST(Reset_n_i),
.CLK(Clk_i),
.D(\$0\Byte1[7:0] ),
.Q(Byte1)
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$458 (
.A(Byte0),
.B(SPI_Data_i),
.S(SPI_FSM_Wr0),
.Y(\$0\Byte0[7:0] )
);
\$mux #(
.WIDTH(32'b00000000000000000000000000001000)
) \$procmux$465 (
.A(Byte1),
.B(SPI_Data_i),
.S(SPI_FSM_Wr1),
.Y(\$0\Byte1[7:0] )
);
\$and #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.B_SIGNED(32'b00000000000000000000000000000000),
.B_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$583 (
.A(\$procmux$558_CMP ),
.B(\$2\SPI_FSM_Wr1[0:0] ),
.Y(SPI_FSM_Wr1)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$593 (
.A(1'b0),
.B({ \$2\SPI_FSM_Wr1[0:0] , 1'b1 }),
.S({ \$procmux$558_CMP , SPI_FSM_Wr0 }),
.Y(SPI_ReadNext_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$606 (
.A(1'b1),
.B({ \$2\MAX6682CS_n_o[0:0] , 1'b0 }),
.S({ \$procmux$563_CMP , \$auto$opt_reduce.cc:126:opt_mux$736 }),
.Y(MAX6682CS_n_o)
);
\$pmux #(
.S_WIDTH(32'b00000000000000000000000000000010),
.WIDTH(32'b00000000000000000000000000000001)
) \$procmux$637 (
.A(1'b0),
.B({ SPI_FSM_Start, 1'b1 }),
.S({ \$procmux$563_CMP , \$procmux$560_CMP }),
.Y(SPI_Write_o)
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$666 (
.A(SPI_FSM_Start),
.Y(\$2\MAX6682CS_n_o[0:0] )
);
\$not #(
.A_SIGNED(32'b00000000000000000000000000000000),
.A_WIDTH(32'b00000000000000000000000000000001),
.Y_WIDTH(32'b00000000000000000000000000000001)
) \$procmux$703 (
.A(SPI_Transmission_i),
.Y(\$2\SPI_FSM_Wr1[0:0] )
);
endmodule
|
// Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
// Date : Sun Sep 22 02:34:38 2019
// Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub
// D:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_processing_system7_0_0/zybo_zynq_design_processing_system7_0_0_stub.v
// Design : zybo_zynq_design_processing_system7_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2018.2" *)
module zybo_zynq_design_processing_system7_0_0(SDIO0_WP, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT,
TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT,
M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY,
M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID,
M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, M_AXI_GP0_AWBURST,
M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR,
M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS,
M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK,
M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, M_AXI_GP0_RLAST,
M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, M_AXI_GP0_BRESP,
M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE,
DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr,
DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB)
/* synthesis syn_black_box black_box_pad_pin="SDIO0_WP,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */;
input SDIO0_WP;
output TTC0_WAVE0_OUT;
output TTC0_WAVE1_OUT;
output TTC0_WAVE2_OUT;
output [1:0]USB0_PORT_INDCTL;
output USB0_VBUS_PWRSELECT;
input USB0_VBUS_PWRFAULT;
output M_AXI_GP0_ARVALID;
output M_AXI_GP0_AWVALID;
output M_AXI_GP0_BREADY;
output M_AXI_GP0_RREADY;
output M_AXI_GP0_WLAST;
output M_AXI_GP0_WVALID;
output [11:0]M_AXI_GP0_ARID;
output [11:0]M_AXI_GP0_AWID;
output [11:0]M_AXI_GP0_WID;
output [1:0]M_AXI_GP0_ARBURST;
output [1:0]M_AXI_GP0_ARLOCK;
output [2:0]M_AXI_GP0_ARSIZE;
output [1:0]M_AXI_GP0_AWBURST;
output [1:0]M_AXI_GP0_AWLOCK;
output [2:0]M_AXI_GP0_AWSIZE;
output [2:0]M_AXI_GP0_ARPROT;
output [2:0]M_AXI_GP0_AWPROT;
output [31:0]M_AXI_GP0_ARADDR;
output [31:0]M_AXI_GP0_AWADDR;
output [31:0]M_AXI_GP0_WDATA;
output [3:0]M_AXI_GP0_ARCACHE;
output [3:0]M_AXI_GP0_ARLEN;
output [3:0]M_AXI_GP0_ARQOS;
output [3:0]M_AXI_GP0_AWCACHE;
output [3:0]M_AXI_GP0_AWLEN;
output [3:0]M_AXI_GP0_AWQOS;
output [3:0]M_AXI_GP0_WSTRB;
input M_AXI_GP0_ACLK;
input M_AXI_GP0_ARREADY;
input M_AXI_GP0_AWREADY;
input M_AXI_GP0_BVALID;
input M_AXI_GP0_RLAST;
input M_AXI_GP0_RVALID;
input M_AXI_GP0_WREADY;
input [11:0]M_AXI_GP0_BID;
input [11:0]M_AXI_GP0_RID;
input [1:0]M_AXI_GP0_BRESP;
input [1:0]M_AXI_GP0_RRESP;
input [31:0]M_AXI_GP0_RDATA;
input [0:0]IRQ_F2P;
output FCLK_CLK0;
output FCLK_RESET0_N;
inout [53:0]MIO;
inout DDR_CAS_n;
inout DDR_CKE;
inout DDR_Clk_n;
inout DDR_Clk;
inout DDR_CS_n;
inout DDR_DRSTB;
inout DDR_ODT;
inout DDR_RAS_n;
inout DDR_WEB;
inout [2:0]DDR_BankAddr;
inout [14:0]DDR_Addr;
inout DDR_VRN;
inout DDR_VRP;
inout [3:0]DDR_DM;
inout [31:0]DDR_DQ;
inout [3:0]DDR_DQS_n;
inout [3:0]DDR_DQS;
inout PS_SRSTB;
inout PS_CLK;
inout PS_PORB;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O41A_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__O41A_PP_BLACKBOX_V
/**
* o41a: 4-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3 | A4) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__o41a (
X ,
A1 ,
A2 ,
A3 ,
A4 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input A4 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O41A_PP_BLACKBOX_V
|
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