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// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:50:58 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_xbar_0_stub.v
// Design : ip_design_xbar_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "axi_crossbar_v2_1_15_axi_crossbar,Vivado 2017.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(aclk, aresetn, s_axi_awaddr, s_axi_awprot,
s_axi_awvalid, s_axi_awready, s_axi_wdata, s_axi_wstrb, s_axi_wvalid, s_axi_wready,
s_axi_bresp, s_axi_bvalid, s_axi_bready, s_axi_araddr, s_axi_arprot, s_axi_arvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rvalid, s_axi_rready, m_axi_awaddr,
m_axi_awprot, m_axi_awvalid, m_axi_awready, m_axi_wdata, m_axi_wstrb, m_axi_wvalid,
m_axi_wready, m_axi_bresp, m_axi_bvalid, m_axi_bready, m_axi_araddr, m_axi_arprot,
m_axi_arvalid, m_axi_arready, m_axi_rdata, m_axi_rresp, m_axi_rvalid, m_axi_rready)
/* synthesis syn_black_box black_box_pad_pin="aclk,aresetn,s_axi_awaddr[31:0],s_axi_awprot[2:0],s_axi_awvalid[0:0],s_axi_awready[0:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wvalid[0:0],s_axi_wready[0:0],s_axi_bresp[1:0],s_axi_bvalid[0:0],s_axi_bready[0:0],s_axi_araddr[31:0],s_axi_arprot[2:0],s_axi_arvalid[0:0],s_axi_arready[0:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rvalid[0:0],s_axi_rready[0:0],m_axi_awaddr[191:0],m_axi_awprot[17:0],m_axi_awvalid[5:0],m_axi_awready[5:0],m_axi_wdata[191:0],m_axi_wstrb[23:0],m_axi_wvalid[5:0],m_axi_wready[5:0],m_axi_bresp[11:0],m_axi_bvalid[5:0],m_axi_bready[5:0],m_axi_araddr[191:0],m_axi_arprot[17:0],m_axi_arvalid[5:0],m_axi_arready[5:0],m_axi_rdata[191:0],m_axi_rresp[11:0],m_axi_rvalid[5:0],m_axi_rready[5:0]" */;
input aclk;
input aresetn;
input [31:0]s_axi_awaddr;
input [2:0]s_axi_awprot;
input [0:0]s_axi_awvalid;
output [0:0]s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input [0:0]s_axi_wvalid;
output [0:0]s_axi_wready;
output [1:0]s_axi_bresp;
output [0:0]s_axi_bvalid;
input [0:0]s_axi_bready;
input [31:0]s_axi_araddr;
input [2:0]s_axi_arprot;
input [0:0]s_axi_arvalid;
output [0:0]s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output [0:0]s_axi_rvalid;
input [0:0]s_axi_rready;
output [191:0]m_axi_awaddr;
output [17:0]m_axi_awprot;
output [5:0]m_axi_awvalid;
input [5:0]m_axi_awready;
output [191:0]m_axi_wdata;
output [23:0]m_axi_wstrb;
output [5:0]m_axi_wvalid;
input [5:0]m_axi_wready;
input [11:0]m_axi_bresp;
input [5:0]m_axi_bvalid;
output [5:0]m_axi_bready;
output [191:0]m_axi_araddr;
output [17:0]m_axi_arprot;
output [5:0]m_axi_arvalid;
input [5:0]m_axi_arready;
input [191:0]m_axi_rdata;
input [11:0]m_axi_rresp;
input [5:0]m_axi_rvalid;
output [5:0]m_axi_rready;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V
/**
* o2111ai: 2-input OR into first input of 4-input NAND.
*
* Y = !((A1 | A2) & B1 & C1 & D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hd__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hd__o2111ai (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire nand0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
nand nand0 (nand0_out_Y , C1, B1, D1, or0_out );
sky130_fd_sc_hd__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nand0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__O2111AI_FUNCTIONAL_PP_V |
module rx_frontend
#(parameter BASE = 0,
parameter IQCOMP_EN = 1)
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [15:0] adc_a, input adc_ovf_a,
input [15:0] adc_b, input adc_ovf_b,
output [23:0] i_out, output [23:0] q_out,
input run,
output [31:0] debug
);
reg [15:0] adc_i, adc_q;
wire [17:0] adc_i_ofs, adc_q_ofs;
wire [35:0] corr_i, corr_q; wire [17:0] mag_corr,phase_corr;
wire swap_iq;
setting_reg #(.my_addr(BASE), .width(1)) sr_8
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(swap_iq),.changed());
always @(posedge clk)
if(swap_iq) // Swap
{adc_i,adc_q} <= {adc_b,adc_a};
else
{adc_i,adc_q} <= {adc_a,adc_b};
setting_reg #(.my_addr(BASE+1),.width(18)) sr_1
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(mag_corr),.changed());
setting_reg #(.my_addr(BASE+2),.width(18)) sr_2
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(phase_corr),.changed());
generate
if(IQCOMP_EN == 1)
begin
rx_dcoffset #(.WIDTH(18),.ADDR(BASE+3)) rx_dcoffset_i
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_i,2'b00}),.out(adc_i_ofs));
rx_dcoffset #(.WIDTH(18),.ADDR(BASE+4)) rx_dcoffset_q
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_q,2'b00}),.out(adc_q_ofs));
MULT18X18S mult_mag_corr
(.P(corr_i), .A(adc_i_ofs), .B(mag_corr), .C(clk), .CE(1), .R(rst) );
MULT18X18S mult_phase_corr
(.P(corr_q), .A(adc_i_ofs), .B(phase_corr), .C(clk), .CE(1), .R(rst) );
add2_and_clip_reg #(.WIDTH(24)) add_clip_i
(.clk(clk), .rst(rst),
.in1({adc_i_ofs,6'd0}), .in2(corr_i[35:12]), .strobe_in(1'b1),
.sum(i_out), .strobe_out());
add2_and_clip_reg #(.WIDTH(24)) add_clip_q
(.clk(clk), .rst(rst),
.in1({adc_q_ofs,6'd0}), .in2(corr_q[35:12]), .strobe_in(1'b1),
.sum(q_out), .strobe_out());
end // if (IQCOMP_EN == 1)
else
begin
rx_dcoffset #(.WIDTH(24),.ADDR(BASE+3)) rx_dcoffset_i
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_i,8'b00}),.out(i_out));
rx_dcoffset #(.WIDTH(24),.ADDR(BASE+4)) rx_dcoffset_q
(.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
.in({adc_q,8'b00}),.out(q_out));
end // else: !if(IQCOMP_EN == 1)
endgenerate
endmodule // rx_frontend
|
////////////////////////////////////////////////////////////////////////////////
//
// Filename: ../demo-out/toplevel.v
// {{{
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
//
// DO NOT EDIT THIS FILE!
// Computer Generated: This file is computer generated by AUTOFPGA. DO NOT EDIT.
// DO NOT EDIT THIS FILE!
//
// CmdLine: ./autofpga ./autofpga -d -o ../demo-out -I ../auto-data bkram.txt buserr.txt clkcounter.txt clock.txt enet.txt flash.txt global.txt gpio.txt gps.txt hdmi.txt icape.txt legalgen.txt mdio.txt pic.txt pwrcount.txt rtcdate.txt rtcgps.txt sdram.txt sdspi.txt spio.txt version.txt wbmouse.txt wboledbw.txt wbpmic.txt wbscopc.txt wbscope.txt wbubus.txt xpander.txt zipmaster.txt
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2021, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
`default_nettype none
//
// Here we declare our toplevel.v (toplevel) design module.
// All design logic must take place beneath this top level.
//
// The port declarations just copy data from the @TOP.PORTLIST
// key, or equivalently from the @MAIN.PORTLIST key if
// @TOP.PORTLIST is absent. For those peripherals that don't need
// any top level logic, the @MAIN.PORTLIST should be sufficent,
// so the @TOP.PORTLIST key may be left undefined.
//
// The only exception is that any clocks with CLOCK.TOP tags will
// also appear in this list
//
module toplevel(i_clk,
// HDMI output clock
o_hdmi_out_clk_n, o_hdmi_out_clk_p,
// HDMI output pixels
o_hdmi_out_p, o_hdmi_out_n,
// GPIO ports
io_hdmi_in_cec,
o_hdmi_in_hpa, // Hotplug assert
o_hdmi_in_txen,
io_hdmi_out_cec,
i_hdmi_out_hpd_n, // Hotplug detect
o_sd_reset,
i_gps_3df,
// Top level Quad-SPI I/O ports
o_qspi_cs_n, io_qspi_dat,
// The GPS-UART
i_gpsu_rx, o_gpsu_tx,
// Ethernet control (packets) lines
o_net_reset_n,
// eth_int_b // Interrupt, leave floating
// eth_pme_b // Power management event, leave floating
i_net_rx_clk, i_net_rx_ctl, i_net_rxd,
o_net_tx_clk, o_net_tx_ctl, o_net_txd,
// SD Card
o_sd_sck, io_sd_cmd, io_sd, i_sd_cd_n,
// HDMI input clock, and then data
i_hdmi_in_clk_n, i_hdmi_in_clk_p,
i_hdmi_in_p, i_hdmi_in_n,
// The GPS 1PPS signal port
i_gps_pps,
// Toplevel ethernet MDIO ports
o_eth_mdclk, io_eth_mdio,
// HDMI output EDID I2C ports
io_hdmi_out_scl, io_hdmi_out_sda,
// SDRAM I/O port wires
ddr3_reset_n, ddr3_cke, ddr3_ck_p, ddr3_ck_n,
ddr3_ras_n, ddr3_cas_n, ddr3_we_n,
ddr3_dqs_p, ddr3_dqs_n,
ddr3_addr, ddr3_ba,
ddr3_dq, ddr3_dm, ddr3_odt,
// SPIO interface
i_sw, i_btnc, i_btnd, i_btnl, i_btnr, i_btnu, o_led,
// The PS/2 Mouse
io_ps2_clk, io_ps2_data,
// OLED control interface (roughly SPI)
o_oled_sck, o_oled_mosi, o_oled_dcn,
o_oled_reset_n, o_oled_panel_en, o_oled_logic_en,
// The PMic3 microphone wires
o_mic_csn, o_mic_sck, i_mic_din,
// UART/host to wishbone interface
i_host_uart_rx, o_host_uart_tx,
// HDMI input EDID I2C ports
io_hdmi_in_scl, io_hdmi_in_sda);
//
// Declaring our input and output ports. We listed these above,
// now we are declaring them here.
//
// These declarations just copy data from the @TOP.IODECLS key,
// or from the @MAIN.IODECL key if @TOP.IODECL is absent. For
// those peripherals that don't do anything at the top level,
// the @MAIN.IODECL key should be sufficient, so the @TOP.IODECL
// key may be left undefined.
//
// We start with any @CLOCK.TOP keys
//
input wire i_clk;
// HDMI output clock
output wire o_hdmi_out_clk_n, o_hdmi_out_clk_p;
// HDMI output pixels
output [2:0] o_hdmi_out_p, o_hdmi_out_n;
// GPIO wires
inout wire io_hdmi_in_cec;
output wire o_hdmi_in_hpa;
output wire o_hdmi_in_txen;
inout wire io_hdmi_out_cec;
input wire i_hdmi_out_hpd_n;
output wire o_sd_reset;
input wire i_gps_3df;
// Quad SPI flash
output wire o_qspi_cs_n;
inout wire [3:0] io_qspi_dat;
input wire i_gpsu_rx;
output wire o_gpsu_tx;
// Ethernet (RGMII) port wires
output wire o_net_reset_n;
input wire i_net_rx_clk, i_net_rx_ctl;
input wire [3:0] i_net_rxd;
output wire o_net_tx_clk, o_net_tx_ctl;
output wire [3:0] o_net_txd;
// SD Card
output wire o_sd_sck;
inout wire io_sd_cmd;
inout wire [3:0] io_sd;
input wire i_sd_cd_n;
// HDMI input clock
input wire i_hdmi_in_clk_n, i_hdmi_in_clk_p;
input [2:0] i_hdmi_in_p, i_hdmi_in_n;
//The GPS Clock
input wire i_gps_pps;
// Ethernet control (MDIO)
output wire o_eth_mdclk;
inout wire io_eth_mdio;
// HDMI output EDID I2C ports
inout wire io_hdmi_out_scl, io_hdmi_out_sda;
// I/O declarations for the DDR3 SDRAM
output wire ddr3_reset_n;
output wire [0:0] ddr3_cke;
output wire [0:0] ddr3_ck_p, ddr3_ck_n;
// output wire [0:0] ddr3_cs_n; // This design has no CS pin
output wire ddr3_ras_n, ddr3_cas_n, ddr3_we_n;
output wire [2:0] ddr3_ba;
output wire [14:0] ddr3_addr;
output wire [0:0] ddr3_odt;
output wire [1:0] ddr3_dm;
inout wire [1:0] ddr3_dqs_p, ddr3_dqs_n;
inout wire [15:0] ddr3_dq;
// SPIO interface
input wire [8-1:0] i_sw;
input wire i_btnc, i_btnd, i_btnl, i_btnr, i_btnu;
output wire [8-1:0] o_led;
inout wire io_ps2_clk, io_ps2_data;
// OLEDBW interface
output wire o_oled_sck, o_oled_mosi,
o_oled_dcn, o_oled_reset_n, o_oled_panel_en,
o_oled_logic_en;
output wire o_mic_csn, o_mic_sck;
input wire i_mic_din;
input wire i_host_uart_rx;
output wire o_host_uart_tx;
// HDMI input EDID I2C ports
inout wire io_hdmi_in_scl, io_hdmi_in_sda;
//
// Declaring component data, internal wires and registers
//
// These declarations just copy data from the @TOP.DEFNS key
// within the component data files.
//
wire w_hdmi_out_hsclk, w_hdmi_out_logic_clk;
wire [9:0] w_hdmi_out_r, w_hdmi_out_g, w_hdmi_out_b;
// GPIO declarations. The two wire busses are just virtual lists of
// input (or output) ports.
wire [15:0] i_gpio, o_gpio;
wire w_hdmi_out_en;
wire w_hdmi_bypass_sda;
wire w_hdmi_bypass_scl;
wire s_clk, s_reset;
wire w_qspi_sck, w_qspi_cs_n;
wire [1:0] qspi_bmod;
wire [3:0] qspi_dat;
// Ethernet (RGMII) port wires
wire [7:0] w_net_rxd, w_net_txd;
wire w_net_rxdv, w_net_rxerr,
w_net_txctl;
wire [1:0] w_net_tx_clk;
wire w_sd_cmd;
wire [3:0] w_sd_data;
wire i_sd_cmd;
wire [3:0] i_sd;
wire w_hdmi_in_logic_clk, w_hdmi_in_hsclk,
w_hdmi_in_clk_no_buf, w_hdmi_in_clk_no_delay,
w_hdmi_in_clk_raw;
wire [9:0] w_hdmi_in_red, w_hdmi_in_green, w_hdmi_in_blue;
// HDMI input (sink) delay definition(s)
wire [4:0] w_hdmi_in_delay, w_hdmi_in_actual_delay_r,
w_hdmi_in_actual_delay_g, w_hdmi_in_actual_delay_b;
//
wire w_hdmi_in_pll_locked;
// Ethernet control (MDIO)
wire w_mdio, w_mdwe;
// HDMI command I2C wires, to support the EDID protocol
// These are used to determine if the bus wires are to be set to zero
// or not
wire w_hdmi_out_scl, w_hdmi_out_sda;
// Wires necessary to run the SDRAM
//
wire sdram_cyc, sdram_stb, sdram_we,
sdram_stall, sdram_ack, sdram_err;
wire [(29-4-1):0] sdram_addr;
wire [(128-1):0] sdram_wdata,
sdram_rdata;
wire [(128/8-1):0] sdram_sel;
wire [31:0] sdram_dbg;
//
// Wires coming back from the SDRAM
wire s_clk, s_reset;
wire [8-1:0] w_led;
wire [1:0] w_ps2;
// HDMI command I2C wires, to support the EDID protocol
// These are used to determine if the bus wires are to be set to zero
// or not
wire w_hdmi_in_scl, w_hdmi_in_sda;
//
// Time to call the main module within main.v. Remember, the purpose
// of the main.v module is to contain all of our portable logic.
// Things that are Xilinx (or even Altera) specific, or for that
// matter anything that requires something other than on-off logic,
// such as the high impedence states required by many wires, is
// kept in this (toplevel.v) module. Everything else goes in
// main.v.
//
// We automatically place s_clk, and s_reset here. You may need
// to define those above. (You did, didn't you?) Other
// component descriptions come from the keys @TOP.MAIN (if it
// exists), or @MAIN.PORTLIST if it does not.
//
main thedesign(s_clk, s_reset,
// Reset wire for the ZipCPU
s_reset,
// HDMI output ports
w_hdmi_out_logic_clk,
// HDMI output pixels, set within the main module
w_hdmi_out_r, w_hdmi_out_g, w_hdmi_out_b,
// GPIO wires
i_gpio, o_gpio,
// Quad SPI flash
w_qspi_cs_n, w_qspi_sck, qspi_dat, io_qspi_dat, qspi_bmod,
// The GPS-UART
i_gpsu_rx, o_gpsu_tx,
// Ethernet (RGMII) connections
o_net_reset_n,
i_net_rx_clk, w_net_rxdv, w_net_rxdv ^ w_net_rxerr, w_net_rxd,
w_net_tx_clk, w_net_txctl, w_net_txd,
// SD Card
o_sd_sck, w_sd_cmd, w_sd_data, i_sd_cmd, i_sd, !i_sd_cd_n,
// HDMI input clock
w_hdmi_in_logic_clk,
w_hdmi_in_red, w_hdmi_in_green, w_hdmi_in_blue,
w_hdmi_in_hsclk,
// HDMI input (sink) delay
w_hdmi_in_actual_delay_r, w_hdmi_in_actual_delay_g,
w_hdmi_in_actual_delay_b, w_hdmi_in_delay,
// The GPS 1PPS signal port
i_gps_pps,
o_eth_mdclk, w_mdio, w_mdwe, io_eth_mdio,
// EDID port for the HDMI source
io_hdmi_out_scl, io_hdmi_out_sda, w_hdmi_out_scl, w_hdmi_out_sda,
// The SDRAM interface to an toplevel AXI4 module
//
sdram_cyc, sdram_stb, sdram_we,
sdram_addr, sdram_wdata, sdram_sel,
sdram_stall, sdram_ack, sdram_rdata,
sdram_err
, sdram_dbg,
i_sw, i_btnc, i_btnd, i_btnl, i_btnr, i_btnu, w_led,
// The PS/2 Mouse
{ io_ps2_clk, io_ps2_data }, w_ps2,
// OLED control interface (roughly SPI)
o_oled_sck, o_oled_mosi, o_oled_dcn,
o_oled_reset_n, o_oled_panel_en, o_oled_logic_en,
// The PMic3 microphone wires
o_mic_csn, o_mic_sck, i_mic_din,
// UART/host to wishbone interface
i_host_uart_rx, o_host_uart_tx,
// HDMI input EDID I2C ports
io_hdmi_in_scl, io_hdmi_in_sda, w_hdmi_in_scl, w_hdmi_in_sda);
//
// Our final section to the toplevel is used to provide all of
// that special logic that couldnt fit in main. This logic is
// given by the @TOP.INSERT tag in our data files.
//
assign w_hdmi_out_hsclk = w_hdmi_in_hsclk;
assign w_hdmi_out_logic_clk = w_hdmi_in_logic_clk;
xhdmiout ohdmick(w_hdmi_out_logic_clk, w_hdmi_out_hsclk, w_hdmi_out_en,
10'h3e0,
{ o_hdmi_out_clk_p, o_hdmi_out_clk_n });
xhdmiout ohdmir(w_hdmi_out_logic_clk, w_hdmi_out_hsclk, w_hdmi_out_en,
w_hdmi_out_r,
{ o_hdmi_out_p[2], o_hdmi_out_n[2] });
xhdmiout ohdmig(w_hdmi_out_logic_clk, w_hdmi_out_hsclk, w_hdmi_out_en,
w_hdmi_out_g,
{ o_hdmi_out_p[1], o_hdmi_out_n[1] });
xhdmiout ohdmib(w_hdmi_out_logic_clk, w_hdmi_out_hsclk, w_hdmi_out_en,
w_hdmi_out_b,
{ o_hdmi_out_p[0], o_hdmi_out_n[0] });
assign i_gpio = { 10'h0,
w_hdmi_in_pll_locked,
sysclk_locked, i_gps_3df,
!i_hdmi_out_hpd_n, !i_sd_cd_n,
io_hdmi_out_cec, io_hdmi_in_cec };
assign io_hdmi_in_cec = o_gpio[0] ? 1'bz : 1'b0;
assign io_hdmi_out_cec = o_gpio[1] ? 1'bz : 1'b0;
assign w_hdmi_bypass_scl=o_gpio[2];
assign w_hdmi_bypass_sda=o_gpio[3];
assign o_hdmi_in_txen = o_gpio[4];
assign o_hdmi_in_hpa = o_gpio[5]; // Hotplug assert
assign o_sd_reset = o_gpio[6];
assign w_hdmi_out_en = o_gpio[7];
assign s_clk = i_clk;
// assign s_reset = 1'b0; // This design requires local, not global resets
//
//
// Wires for setting up the QSPI flash wishbone peripheral
//
//
// QSPI)BMOD, Quad SPI bus mode, Bus modes are:
// 0? Normal serial mode, one bit in one bit out
// 10 Quad SPI mode, going out
// 11 Quad SPI mode coming from the device (read mode)
assign io_qspi_dat = (~qspi_bmod[1])?({2'b11,1'bz,qspi_dat[0]})
:((qspi_bmod[0])?(4'bzzzz):(qspi_dat[3:0]));
assign o_qspi_cs_n = w_qspi_cs_n;
// The following primitive is necessary in many designs order to gain
// access to the o_qspi_sck pin. It's not necessary on the Arty,
// simply because they provide two pins that can drive the QSPI
// clock pin.
wire [3:0] su_nc; // Startup primitive, no connect
STARTUPE2 #(
// Leave PROG_USR false to avoid activating the program
// event security feature. Notes state that such a feature
// requires encrypted bitstreams.
.PROG_USR("FALSE"),
// Sets the configuration clock frequency (in ns) for
// simulation.
.SIM_CCLK_FREQ(0.0)
) STARTUPE2_inst (
// CFGCLK, 1'b output: Configuration main clock output -- no connect
.CFGCLK(su_nc[0]),
// CFGMCLK, 1'b output: Configuration internal oscillator clock output
.CFGMCLK(su_nc[1]),
// EOS, 1'b output: Active high output indicating the End Of Startup.
.EOS(su_nc[2]),
// PREQ, 1'b output: PROGRAM request to fabric output
// Only enabled if PROG_USR is set. This lets the fabric know
// that a request has been made (either JTAG or pin pulled low)
// to program the device
.PREQ(su_nc[3]),
// CLK, 1'b input: User start-up clock input
.CLK(1'b0),
// GSR, 1'b input: Global Set/Reset input
.GSR(1'b0),
// GTS, 1'b input: Global 3-state input
.GTS(1'b0),
// KEYCLEARB, 1'b input: Clear AES Decrypter Key input from BBRAM
.KEYCLEARB(1'b0),
// PACK, 1-bit input: PROGRAM acknowledge input
// This pin is only enabled if PROG_USR is set. This allows the
// FPGA to acknowledge a request for reprogram to allow the FPGA
// to get itself into a reprogrammable state first.
.PACK(1'b0),
// USRCLKO, 1-bit input: User CCLK input -- This is why I am using this
// module at all.
.USRCCLKO(w_qspi_sck),
// USRCCLKTS, 1'b input: User CCLK 3-state enable input
// An active high here places the clock into a high impedence
// state. Since we wish to use the clock as an active output
// always, we drive this pin low.
.USRCCLKTS(1'b0),
// USRDONEO, 1'b input: User DONE pin output control
// Set this to "high" to make sure that the DONE LED pin is
// high.
.USRDONEO(1'b1),
// USRDONETS, 1'b input: User DONE 3-state enable output
// This enables the FPGA DONE pin to be active. Setting this
// active high sets the DONE pin to high impedence, setting it
// low allows the output of this pin to be as stated above.
.USRDONETS(1'b1)
);
xiddr rx0(i_net_rx_clk, i_net_rxd[0], { w_net_rxd[4], w_net_rxd[0] });
xiddr rx1(i_net_rx_clk, i_net_rxd[1], { w_net_rxd[5], w_net_rxd[1] });
xiddr rx2(i_net_rx_clk, i_net_rxd[2], { w_net_rxd[6], w_net_rxd[2] });
xiddr rx3(i_net_rx_clk, i_net_rxd[3], { w_net_rxd[7], w_net_rxd[3] });
xiddr rxc(i_net_rx_clk, i_net_rx_ctl, { w_net_rxdv, w_net_rxerr });
xoddr tx0(s_clk_125mhz, { w_net_txd[0], w_net_txd[4] }, o_net_txd[0]);
xoddr tx1(s_clk_125mhz, { w_net_txd[1], w_net_txd[5] }, o_net_txd[1]);
xoddr tx2(s_clk_125mhz, { w_net_txd[2], w_net_txd[6] }, o_net_txd[2]);
xoddr tx3(s_clk_125mhz, { w_net_txd[3], w_net_txd[7] }, o_net_txd[3]);
xoddr txc(s_clk_125mhz, { w_net_txctl, w_net_txctl }, o_net_tx_ctl);
xoddr txck(s_clk_125d,{w_net_tx_clk[1],w_net_tx_clk[0]},o_net_tx_clk);
//
//
// Wires for setting up the SD Card Controller
//
//
// IOBUF sd_cmd_buf(.T(w_sd_cmd),.O(i_sd_cmd), .I(1'b0), .IO(io_sd_cmd));
IOBUF sd_dat0_bf(.T(1'b1),.O(i_sd[0]),.I(1'b1),.IO(io_sd[0]));
IOBUF sd_dat1_bf(.T(1'b1),.O(i_sd[1]),.I(1'b1),.IO(io_sd[1]));
IOBUF sd_dat2_bf(.T(1'b1),.O(i_sd[2]),.I(1'b1),.IO(io_sd[2]));
// IOBUF sd_dat3_bf(.T(w_sd_data[3]),.O(i_sd[3]),.I(1'b0),.IO(io_sd[3]));
IOBUF sd_cmd_buf(.T(1'b0),.O(i_sd_cmd), .I(w_sd_cmd), .IO(io_sd_cmd));
IOBUF sd_dat3_bf(.T(1'b0),.O(i_sd[3]),.I(w_sd_data[3]),.IO(io_sd[3]));
// First, let's get our clock up and running
// 1. Convert from differential to single
IBUFDS hdmi_in_clk_ibuf(
.I(i_hdmi_in_clk_p), .IB(i_hdmi_in_clk_n),
.O(w_hdmi_in_clk_raw));
BUFG rawckbuf(.I(w_hdmi_in_clk_raw), .O(w_hdmi_in_clk_no_buf));
// 3. Use that signal to generate a clock
xhdmiiclk xhclkin(s_clk, w_hdmi_in_clk_no_buf, o_hdmi_in_txen,
w_hdmi_in_hsclk, w_hdmi_in_logic_clk,
w_hdmi_in_pll_locked);
xhdmiin xhin_r(w_hdmi_in_logic_clk, w_hdmi_in_hsclk,
o_hdmi_in_txen,
w_hdmi_in_delay, w_hdmi_in_actual_delay_r,
{ i_hdmi_in_p[2], i_hdmi_in_n[2] }, w_hdmi_in_red);
xhdmiin xhin_g(w_hdmi_in_logic_clk, w_hdmi_in_hsclk,
o_hdmi_in_txen,
w_hdmi_in_delay, w_hdmi_in_actual_delay_g,
{ i_hdmi_in_p[1], i_hdmi_in_n[1] }, w_hdmi_in_green);
xhdmiin xhin_b(w_hdmi_in_logic_clk, w_hdmi_in_hsclk,
o_hdmi_in_txen,
w_hdmi_in_delay, w_hdmi_in_actual_delay_b,
{ i_hdmi_in_p[0], i_hdmi_in_n[0] }, w_hdmi_in_blue);
// Xilinx requires an IDELAYCTRL to be added any time the IDELAY
// element is included in the design. Strangely, this doesn't need
// to be conencted to the IDELAY in any fashion, it just needs to be
// provided with a clock.
//
// I should associate this delay with a delay group --- just haven't
// done that yet.
wire delay_reset;
assign delay_reset = 1'b0;
/*
always @(posedge s_clk)
delay_reset <= !sys_clk_locked;
*/
IDELAYCTRL dlyctrl(.REFCLK(s_clk_200mhz), .RDY(), .RST(delay_reset));
assign io_eth_mdio = (w_mdwe)?w_mdio : 1'bz;
// The EDID I2C port for the HDMI source port
//
// We need to make certain we only force the pin to a zero (drain)
// when trying to do so. Otherwise we let it float (back) high.
assign io_hdmi_out_scl = ((w_hdmi_bypass_scl)&&(w_hdmi_out_scl)) ? 1'bz : 1'b0;
assign io_hdmi_out_sda = ((w_hdmi_bypass_sda)&&(w_hdmi_out_sda)) ? 1'bz : 1'b0;
wire [31:0] sdram_debug;
migsdram #(.AXIDWIDTH(1), .WBDATAWIDTH(128),
.DDRWIDTH(16),
.RAMABITS(29)) sdrami(
.i_clk(i_clk_buffered),
.i_clk_200mhz(s_clk_200mhz),
.o_sys_clk(s_clk),
// .i_rst(!i_cpu_resetn),
.i_rst(upper_plls_stable[3:2] != 2'b11),
.o_sys_reset(s_reset),
//
.i_wb_cyc(sdram_cyc), .i_wb_stb(sdram_stb),
.i_wb_we(sdram_we), .i_wb_addr(sdram_addr),
.i_wb_data(sdram_wdata), .i_wb_sel(sdram_sel),
.o_wb_stall(sdram_stall), .o_wb_ack(sdram_ack),
.o_wb_data(sdram_rdata), .o_wb_err(sdram_err),
//
.o_ddr_ck_p(ddr3_ck_p), .o_ddr_ck_n(ddr3_ck_n),
.o_ddr_reset_n(ddr3_reset_n), .o_ddr_cke(ddr3_cke),
// .o_ddr_cs_n(ddr3_cs_n), // No CS on this chip
.o_ddr_ras_n(ddr3_ras_n),
.o_ddr_cas_n(ddr3_cas_n), .o_ddr_we_n(ddr3_we_n),
.o_ddr_ba(ddr3_ba), .o_ddr_addr(ddr3_addr),
.o_ddr_odt(ddr3_odt), .o_ddr_dm(ddr3_dm),
.io_ddr_dqs_p(ddr3_dqs_p), .io_ddr_dqs_n(ddr3_dqs_n),
.io_ddr_data(ddr3_dq)
, .o_ram_dbg(sdram_dbg)
);
assign o_led = { w_led[8-1:2], (w_led[1] || !clocks_locked),
w_led[0] | s_reset };
// WB-Mouse
//
// Adjustments necessary to turn the PS/2 logic to pull-up logic,
// with a high impedence state if not used.
assign io_ps2_clk = (w_ps2[1])? 1'bz:1'b0;
assign io_ps2_data = (w_ps2[0])? 1'bz:1'b0;
// The EDID I2C port for the HDMI source port
//
// We need to make certain we only force the pin to a zero (drain)
// when trying to do so. Otherwise we let it float (back) high.
assign io_hdmi_in_scl = (w_hdmi_in_scl) ? 1'bz : 1'b0;
assign io_hdmi_in_sda = (w_hdmi_in_sda) ? 1'bz : 1'b0;
endmodule // end of toplevel.v module definition
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A31O_BEHAVIORAL_V
/**
* a31o: 3-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a31o (
X ,
A1,
A2,
A3,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A31O_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__XOR2_FUNCTIONAL_PP_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__xor2 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire xor0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
xor xor0 (xor0_out_X , B, A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, xor0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_FUNCTIONAL_PP_V |
// nios_dut_mm_interconnect_0_avalon_st_adapter_010.v
// This file was auto-generated from altera_avalon_st_adapter_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module nios_dut_mm_interconnect_0_avalon_st_adapter_010 #(
parameter inBitsPerSymbol = 130,
parameter inUsePackets = 0,
parameter inDataWidth = 130,
parameter inChannelWidth = 0,
parameter inErrorWidth = 0,
parameter inUseEmptyPort = 0,
parameter inUseValid = 1,
parameter inUseReady = 1,
parameter inReadyLatency = 0,
parameter outDataWidth = 130,
parameter outChannelWidth = 0,
parameter outErrorWidth = 1,
parameter outUseEmptyPort = 0,
parameter outUseValid = 1,
parameter outUseReady = 1,
parameter outReadyLatency = 0
) (
input wire in_clk_0_clk, // in_clk_0.clk
input wire in_rst_0_reset, // in_rst_0.reset
input wire [129:0] in_0_data, // in_0.data
input wire in_0_valid, // .valid
output wire in_0_ready, // .ready
output wire [129:0] out_0_data, // out_0.data
output wire out_0_valid, // .valid
input wire out_0_ready, // .ready
output wire [0:0] out_0_error // .error
);
generate
// If any of the display statements (or deliberately broken
// instantiations) within this generate block triggers then this module
// has been instantiated this module with a set of parameters different
// from those it was generated for. This will usually result in a
// non-functioning system.
if (inBitsPerSymbol != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inbitspersymbol_check ( .error(1'b1) );
end
if (inUsePackets != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusepackets_check ( .error(1'b1) );
end
if (inDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
indatawidth_check ( .error(1'b1) );
end
if (inChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inchannelwidth_check ( .error(1'b1) );
end
if (inErrorWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inerrorwidth_check ( .error(1'b1) );
end
if (inUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseemptyport_check ( .error(1'b1) );
end
if (inUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inusevalid_check ( .error(1'b1) );
end
if (inUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inuseready_check ( .error(1'b1) );
end
if (inReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
inreadylatency_check ( .error(1'b1) );
end
if (outDataWidth != 130)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outdatawidth_check ( .error(1'b1) );
end
if (outChannelWidth != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outchannelwidth_check ( .error(1'b1) );
end
if (outErrorWidth != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outerrorwidth_check ( .error(1'b1) );
end
if (outUseEmptyPort != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseemptyport_check ( .error(1'b1) );
end
if (outUseValid != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outusevalid_check ( .error(1'b1) );
end
if (outUseReady != 1)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outuseready_check ( .error(1'b1) );
end
if (outReadyLatency != 0)
begin
initial begin
$display("Generated module instantiated with wrong parameters");
$stop;
end
instantiated_with_wrong_parameters_error_see_comment_above
outreadylatency_check ( .error(1'b1) );
end
endgenerate
nios_dut_mm_interconnect_0_avalon_st_adapter_010_error_adapter_0 error_adapter_0 (
.clk (in_clk_0_clk), // clk.clk
.reset_n (~in_rst_0_reset), // reset.reset_n
.in_data (in_0_data), // in.data
.in_valid (in_0_valid), // .valid
.in_ready (in_0_ready), // .ready
.out_data (out_0_data), // out.data
.out_valid (out_0_valid), // .valid
.out_ready (out_0_ready), // .ready
.out_error (out_0_error) // .error
);
endmodule
|
/******************************************************************************
* File Name : mod.v
* Package Module Name : Elliptic Curve Cryptoprocessor for GF(2^233)
* Author : Chester Rebeiro
* Date of Creation : 1/Apr/2008
* Type of file : Verilog source code
* Synopsis : Automatically generated code for modulo operation
* with the irreducible polynomial x^233 + x^74 + 1
******************************************************************************/
`ifndef __MOD_V__
`define __MOD_V__
module mod(a, d);
input wire [464:0] a;
output wire [232:0] d;
assign d[0] = a[0] ^ a[233] ^ a[392];
assign d[1] = a[1] ^ a[234] ^ a[393];
assign d[2] = a[2] ^ a[235] ^ a[394];
assign d[3] = a[3] ^ a[236] ^ a[395];
assign d[4] = a[4] ^ a[237] ^ a[396];
assign d[5] = a[5] ^ a[238] ^ a[397];
assign d[6] = a[6] ^ a[239] ^ a[398];
assign d[7] = a[7] ^ a[240] ^ a[399];
assign d[8] = a[8] ^ a[241] ^ a[400];
assign d[9] = a[9] ^ a[242] ^ a[401];
assign d[10] = a[10] ^ a[243] ^ a[402];
assign d[11] = a[11] ^ a[244] ^ a[403];
assign d[12] = a[12] ^ a[245] ^ a[404];
assign d[13] = a[13] ^ a[246] ^ a[405];
assign d[14] = a[14] ^ a[247] ^ a[406];
assign d[15] = a[15] ^ a[248] ^ a[407];
assign d[16] = a[16] ^ a[249] ^ a[408];
assign d[17] = a[17] ^ a[250] ^ a[409];
assign d[18] = a[18] ^ a[251] ^ a[410];
assign d[19] = a[19] ^ a[252] ^ a[411];
assign d[20] = a[20] ^ a[253] ^ a[412];
assign d[21] = a[21] ^ a[254] ^ a[413];
assign d[22] = a[22] ^ a[255] ^ a[414];
assign d[23] = a[23] ^ a[256] ^ a[415];
assign d[24] = a[24] ^ a[257] ^ a[416];
assign d[25] = a[25] ^ a[258] ^ a[417];
assign d[26] = a[26] ^ a[259] ^ a[418];
assign d[27] = a[27] ^ a[260] ^ a[419];
assign d[28] = a[28] ^ a[261] ^ a[420];
assign d[29] = a[29] ^ a[262] ^ a[421];
assign d[30] = a[30] ^ a[263] ^ a[422];
assign d[31] = a[31] ^ a[264] ^ a[423];
assign d[32] = a[32] ^ a[265] ^ a[424];
assign d[33] = a[33] ^ a[266] ^ a[425];
assign d[34] = a[34] ^ a[267] ^ a[426];
assign d[35] = a[35] ^ a[268] ^ a[427];
assign d[36] = a[36] ^ a[269] ^ a[428];
assign d[37] = a[37] ^ a[270] ^ a[429];
assign d[38] = a[38] ^ a[271] ^ a[430];
assign d[39] = a[39] ^ a[272] ^ a[431];
assign d[40] = a[40] ^ a[273] ^ a[432];
assign d[41] = a[41] ^ a[274] ^ a[433];
assign d[42] = a[42] ^ a[275] ^ a[434];
assign d[43] = a[43] ^ a[276] ^ a[435];
assign d[44] = a[44] ^ a[277] ^ a[436];
assign d[45] = a[45] ^ a[278] ^ a[437];
assign d[46] = a[46] ^ a[279] ^ a[438];
assign d[47] = a[47] ^ a[280] ^ a[439];
assign d[48] = a[48] ^ a[281] ^ a[440];
assign d[49] = a[49] ^ a[282] ^ a[441];
assign d[50] = a[50] ^ a[283] ^ a[442];
assign d[51] = a[51] ^ a[284] ^ a[443];
assign d[52] = a[52] ^ a[285] ^ a[444];
assign d[53] = a[53] ^ a[286] ^ a[445];
assign d[54] = a[54] ^ a[287] ^ a[446];
assign d[55] = a[55] ^ a[288] ^ a[447];
assign d[56] = a[56] ^ a[289] ^ a[448];
assign d[57] = a[57] ^ a[290] ^ a[449];
assign d[58] = a[58] ^ a[291] ^ a[450];
assign d[59] = a[59] ^ a[292] ^ a[451];
assign d[60] = a[60] ^ a[293] ^ a[452];
assign d[61] = a[61] ^ a[294] ^ a[453];
assign d[62] = a[62] ^ a[295] ^ a[454];
assign d[63] = a[63] ^ a[296] ^ a[455];
assign d[64] = a[64] ^ a[297] ^ a[456];
assign d[65] = a[65] ^ a[298] ^ a[457];
assign d[66] = a[66] ^ a[299] ^ a[458];
assign d[67] = a[67] ^ a[300] ^ a[459];
assign d[68] = a[68] ^ a[301] ^ a[460];
assign d[69] = a[69] ^ a[302] ^ a[461];
assign d[70] = a[70] ^ a[303] ^ a[462];
assign d[71] = a[71] ^ a[304] ^ a[463];
assign d[72] = a[72] ^ a[305] ^ a[464];
assign d[73] = a[73] ^ a[306];
assign d[74] = a[74] ^ a[233] ^ a[307] ^ a[392];
assign d[75] = a[75] ^ a[234] ^ a[308] ^ a[393];
assign d[76] = a[76] ^ a[235] ^ a[309] ^ a[394];
assign d[77] = a[77] ^ a[236] ^ a[310] ^ a[395];
assign d[78] = a[78] ^ a[237] ^ a[311] ^ a[396];
assign d[79] = a[79] ^ a[238] ^ a[312] ^ a[397];
assign d[80] = a[80] ^ a[239] ^ a[313] ^ a[398];
assign d[81] = a[81] ^ a[240] ^ a[314] ^ a[399];
assign d[82] = a[82] ^ a[241] ^ a[315] ^ a[400];
assign d[83] = a[83] ^ a[242] ^ a[316] ^ a[401];
assign d[84] = a[84] ^ a[243] ^ a[317] ^ a[402];
assign d[85] = a[85] ^ a[244] ^ a[318] ^ a[403];
assign d[86] = a[86] ^ a[245] ^ a[319] ^ a[404];
assign d[87] = a[87] ^ a[246] ^ a[320] ^ a[405];
assign d[88] = a[88] ^ a[247] ^ a[321] ^ a[406];
assign d[89] = a[89] ^ a[248] ^ a[322] ^ a[407];
assign d[90] = a[90] ^ a[249] ^ a[323] ^ a[408];
assign d[91] = a[91] ^ a[250] ^ a[324] ^ a[409];
assign d[92] = a[92] ^ a[251] ^ a[325] ^ a[410];
assign d[93] = a[93] ^ a[252] ^ a[326] ^ a[411];
assign d[94] = a[94] ^ a[253] ^ a[327] ^ a[412];
assign d[95] = a[95] ^ a[254] ^ a[328] ^ a[413];
assign d[96] = a[96] ^ a[255] ^ a[329] ^ a[414];
assign d[97] = a[97] ^ a[256] ^ a[330] ^ a[415];
assign d[98] = a[98] ^ a[257] ^ a[331] ^ a[416];
assign d[99] = a[99] ^ a[258] ^ a[332] ^ a[417];
assign d[100] = a[100] ^ a[259] ^ a[333] ^ a[418];
assign d[101] = a[101] ^ a[260] ^ a[334] ^ a[419];
assign d[102] = a[102] ^ a[261] ^ a[335] ^ a[420];
assign d[103] = a[103] ^ a[262] ^ a[336] ^ a[421];
assign d[104] = a[104] ^ a[263] ^ a[337] ^ a[422];
assign d[105] = a[105] ^ a[264] ^ a[338] ^ a[423];
assign d[106] = a[106] ^ a[265] ^ a[339] ^ a[424];
assign d[107] = a[107] ^ a[266] ^ a[340] ^ a[425];
assign d[108] = a[108] ^ a[267] ^ a[341] ^ a[426];
assign d[109] = a[109] ^ a[268] ^ a[342] ^ a[427];
assign d[110] = a[110] ^ a[269] ^ a[343] ^ a[428];
assign d[111] = a[111] ^ a[270] ^ a[344] ^ a[429];
assign d[112] = a[112] ^ a[271] ^ a[345] ^ a[430];
assign d[113] = a[113] ^ a[272] ^ a[346] ^ a[431];
assign d[114] = a[114] ^ a[273] ^ a[347] ^ a[432];
assign d[115] = a[115] ^ a[274] ^ a[348] ^ a[433];
assign d[116] = a[116] ^ a[275] ^ a[349] ^ a[434];
assign d[117] = a[117] ^ a[276] ^ a[350] ^ a[435];
assign d[118] = a[118] ^ a[277] ^ a[351] ^ a[436];
assign d[119] = a[119] ^ a[278] ^ a[352] ^ a[437];
assign d[120] = a[120] ^ a[279] ^ a[353] ^ a[438];
assign d[121] = a[121] ^ a[280] ^ a[354] ^ a[439];
assign d[122] = a[122] ^ a[281] ^ a[355] ^ a[440];
assign d[123] = a[123] ^ a[282] ^ a[356] ^ a[441];
assign d[124] = a[124] ^ a[283] ^ a[357] ^ a[442];
assign d[125] = a[125] ^ a[284] ^ a[358] ^ a[443];
assign d[126] = a[126] ^ a[285] ^ a[359] ^ a[444];
assign d[127] = a[127] ^ a[286] ^ a[360] ^ a[445];
assign d[128] = a[128] ^ a[287] ^ a[361] ^ a[446];
assign d[129] = a[129] ^ a[288] ^ a[362] ^ a[447];
assign d[130] = a[130] ^ a[289] ^ a[363] ^ a[448];
assign d[131] = a[131] ^ a[290] ^ a[364] ^ a[449];
assign d[132] = a[132] ^ a[291] ^ a[365] ^ a[450];
assign d[133] = a[133] ^ a[292] ^ a[366] ^ a[451];
assign d[134] = a[134] ^ a[293] ^ a[367] ^ a[452];
assign d[135] = a[135] ^ a[294] ^ a[368] ^ a[453];
assign d[136] = a[136] ^ a[295] ^ a[369] ^ a[454];
assign d[137] = a[137] ^ a[296] ^ a[370] ^ a[455];
assign d[138] = a[138] ^ a[297] ^ a[371] ^ a[456];
assign d[139] = a[139] ^ a[298] ^ a[372] ^ a[457];
assign d[140] = a[140] ^ a[299] ^ a[373] ^ a[458];
assign d[141] = a[141] ^ a[300] ^ a[374] ^ a[459];
assign d[142] = a[142] ^ a[301] ^ a[375] ^ a[460];
assign d[143] = a[143] ^ a[302] ^ a[376] ^ a[461];
assign d[144] = a[144] ^ a[303] ^ a[377] ^ a[462];
assign d[145] = a[145] ^ a[304] ^ a[378] ^ a[463];
assign d[146] = a[146] ^ a[305] ^ a[379] ^ a[464];
assign d[147] = a[147] ^ a[306] ^ a[380];
assign d[148] = a[148] ^ a[307] ^ a[381];
assign d[149] = a[149] ^ a[308] ^ a[382];
assign d[150] = a[150] ^ a[309] ^ a[383];
assign d[151] = a[151] ^ a[310] ^ a[384];
assign d[152] = a[152] ^ a[311] ^ a[385];
assign d[153] = a[153] ^ a[312] ^ a[386];
assign d[154] = a[154] ^ a[313] ^ a[387];
assign d[155] = a[155] ^ a[314] ^ a[388];
assign d[156] = a[156] ^ a[315] ^ a[389];
assign d[157] = a[157] ^ a[316] ^ a[390];
assign d[158] = a[158] ^ a[317] ^ a[391];
assign d[159] = a[159] ^ a[318] ^ a[392];
assign d[160] = a[160] ^ a[319] ^ a[393];
assign d[161] = a[161] ^ a[320] ^ a[394];
assign d[162] = a[162] ^ a[321] ^ a[395];
assign d[163] = a[163] ^ a[322] ^ a[396];
assign d[164] = a[164] ^ a[323] ^ a[397];
assign d[165] = a[165] ^ a[324] ^ a[398];
assign d[166] = a[166] ^ a[325] ^ a[399];
assign d[167] = a[167] ^ a[326] ^ a[400];
assign d[168] = a[168] ^ a[327] ^ a[401];
assign d[169] = a[169] ^ a[328] ^ a[402];
assign d[170] = a[170] ^ a[329] ^ a[403];
assign d[171] = a[171] ^ a[330] ^ a[404];
assign d[172] = a[172] ^ a[331] ^ a[405];
assign d[173] = a[173] ^ a[332] ^ a[406];
assign d[174] = a[174] ^ a[333] ^ a[407];
assign d[175] = a[175] ^ a[334] ^ a[408];
assign d[176] = a[176] ^ a[335] ^ a[409];
assign d[177] = a[177] ^ a[336] ^ a[410];
assign d[178] = a[178] ^ a[337] ^ a[411];
assign d[179] = a[179] ^ a[338] ^ a[412];
assign d[180] = a[180] ^ a[339] ^ a[413];
assign d[181] = a[181] ^ a[340] ^ a[414];
assign d[182] = a[182] ^ a[341] ^ a[415];
assign d[183] = a[183] ^ a[342] ^ a[416];
assign d[184] = a[184] ^ a[343] ^ a[417];
assign d[185] = a[185] ^ a[344] ^ a[418];
assign d[186] = a[186] ^ a[345] ^ a[419];
assign d[187] = a[187] ^ a[346] ^ a[420];
assign d[188] = a[188] ^ a[347] ^ a[421];
assign d[189] = a[189] ^ a[348] ^ a[422];
assign d[190] = a[190] ^ a[349] ^ a[423];
assign d[191] = a[191] ^ a[350] ^ a[424];
assign d[192] = a[192] ^ a[351] ^ a[425];
assign d[193] = a[193] ^ a[352] ^ a[426];
assign d[194] = a[194] ^ a[353] ^ a[427];
assign d[195] = a[195] ^ a[354] ^ a[428];
assign d[196] = a[196] ^ a[355] ^ a[429];
assign d[197] = a[197] ^ a[356] ^ a[430];
assign d[198] = a[198] ^ a[357] ^ a[431];
assign d[199] = a[199] ^ a[358] ^ a[432];
assign d[200] = a[200] ^ a[359] ^ a[433];
assign d[201] = a[201] ^ a[360] ^ a[434];
assign d[202] = a[202] ^ a[361] ^ a[435];
assign d[203] = a[203] ^ a[362] ^ a[436];
assign d[204] = a[204] ^ a[363] ^ a[437];
assign d[205] = a[205] ^ a[364] ^ a[438];
assign d[206] = a[206] ^ a[365] ^ a[439];
assign d[207] = a[207] ^ a[366] ^ a[440];
assign d[208] = a[208] ^ a[367] ^ a[441];
assign d[209] = a[209] ^ a[368] ^ a[442];
assign d[210] = a[210] ^ a[369] ^ a[443];
assign d[211] = a[211] ^ a[370] ^ a[444];
assign d[212] = a[212] ^ a[371] ^ a[445];
assign d[213] = a[213] ^ a[372] ^ a[446];
assign d[214] = a[214] ^ a[373] ^ a[447];
assign d[215] = a[215] ^ a[374] ^ a[448];
assign d[216] = a[216] ^ a[375] ^ a[449];
assign d[217] = a[217] ^ a[376] ^ a[450];
assign d[218] = a[218] ^ a[377] ^ a[451];
assign d[219] = a[219] ^ a[378] ^ a[452];
assign d[220] = a[220] ^ a[379] ^ a[453];
assign d[221] = a[221] ^ a[380] ^ a[454];
assign d[222] = a[222] ^ a[381] ^ a[455];
assign d[223] = a[223] ^ a[382] ^ a[456];
assign d[224] = a[224] ^ a[383] ^ a[457];
assign d[225] = a[225] ^ a[384] ^ a[458];
assign d[226] = a[226] ^ a[385] ^ a[459];
assign d[227] = a[227] ^ a[386] ^ a[460];
assign d[228] = a[228] ^ a[387] ^ a[461];
assign d[229] = a[229] ^ a[388] ^ a[462];
assign d[230] = a[230] ^ a[389] ^ a[463];
assign d[231] = a[231] ^ a[390] ^ a[464];
assign d[232] = a[232] ^ a[391];
endmodule
`endif
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Mar 12 17:11:28 2017
/////////////////////////////////////////////////////////////
module Approx_adder_W16 ( add_sub, in1, in2, res );
input [15:0] in1;
input [15:0] in2;
output [16:0] res;
input add_sub;
wire n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87,
n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165;
NAND2XLTS U62 ( .A(n49), .B(n133), .Y(n135) );
NAND2XLTS U63 ( .A(n48), .B(n136), .Y(n138) );
NOR2X4TS U64 ( .A(n70), .B(n75), .Y(n134) );
NAND2X4TS U65 ( .A(n132), .B(n99), .Y(n71) );
OR2X2TS U66 ( .A(n102), .B(in1[15]), .Y(n99) );
BUFX3TS U67 ( .A(n77), .Y(n75) );
OA21XLTS U68 ( .A0(n163), .A1(in1[3]), .B0(in1[2]), .Y(n152) );
NOR2X4TS U69 ( .A(n77), .B(n133), .Y(n76) );
OR2X2TS U70 ( .A(n105), .B(in1[14]), .Y(n49) );
AND2X2TS U71 ( .A(in1[0]), .B(in2[0]), .Y(n160) );
INVX3TS U72 ( .A(n46), .Y(n74) );
CLKXOR2X2TS U73 ( .A(n107), .B(in2[13]), .Y(n108) );
NOR2XLTS U74 ( .A(n106), .B(n145), .Y(n107) );
NOR2XLTS U75 ( .A(n111), .B(n145), .Y(n112) );
NAND2XLTS U76 ( .A(n122), .B(add_sub), .Y(n123) );
INVX2TS U77 ( .A(n130), .Y(n62) );
INVX2TS U78 ( .A(in1[7]), .Y(n61) );
NOR2X2TS U79 ( .A(n115), .B(n145), .Y(n116) );
NAND2X6TS U80 ( .A(n88), .B(in1[5]), .Y(n87) );
INVX6TS U81 ( .A(n92), .Y(n88) );
NAND2X6TS U82 ( .A(n69), .B(in1[4]), .Y(n92) );
NOR2X2TS U83 ( .A(n119), .B(n145), .Y(n90) );
INVX4TS U84 ( .A(add_sub), .Y(n145) );
INVX8TS U85 ( .A(in2[4]), .Y(n93) );
CLKINVX3TS U86 ( .A(in2[6]), .Y(n78) );
NOR2X1TS U87 ( .A(n122), .B(in2[10]), .Y(n111) );
OAI21XLTS U88 ( .A0(in2[0]), .A1(in2[1]), .B0(add_sub), .Y(n149) );
XNOR2X2TS U89 ( .A(n110), .B(in2[12]), .Y(n127) );
AND2X8TS U90 ( .A(n137), .B(n48), .Y(n46) );
OR2X4TS U91 ( .A(n108), .B(in1[13]), .Y(n48) );
NAND2BX2TS U92 ( .AN(n55), .B(n127), .Y(n52) );
NAND2X4TS U93 ( .A(n62), .B(n61), .Y(n60) );
NAND2X4TS U94 ( .A(n113), .B(n84), .Y(n122) );
NOR2X4TS U95 ( .A(n120), .B(in2[8]), .Y(n113) );
NAND2X6TS U96 ( .A(n76), .B(n74), .Y(n73) );
AND2X2TS U97 ( .A(n99), .B(n131), .Y(n47) );
NAND2X2TS U98 ( .A(n102), .B(in1[15]), .Y(n131) );
NAND2X2TS U99 ( .A(n105), .B(in1[14]), .Y(n133) );
XNOR2X2TS U100 ( .A(n101), .B(in2[15]), .Y(n102) );
NAND2X2TS U101 ( .A(n108), .B(in1[13]), .Y(n136) );
XNOR2X2TS U102 ( .A(n104), .B(in2[14]), .Y(n105) );
NAND2X6TS U103 ( .A(n64), .B(n60), .Y(n59) );
NAND2X2TS U104 ( .A(n103), .B(add_sub), .Y(n104) );
OAI21X2TS U105 ( .A0(n103), .A1(in2[14]), .B0(add_sub), .Y(n101) );
NAND2BX2TS U106 ( .AN(in2[13]), .B(n106), .Y(n103) );
NAND2X2TS U107 ( .A(n111), .B(n83), .Y(n109) );
XOR2X1TS U108 ( .A(n157), .B(n156), .Y(res[5]) );
XOR2X1TS U109 ( .A(n165), .B(n164), .Y(res[3]) );
XOR2XLTS U110 ( .A(n154), .B(n153), .Y(res[4]) );
XOR2XLTS U111 ( .A(n160), .B(n148), .Y(res[1]) );
NAND2X6TS U112 ( .A(n50), .B(add_sub), .Y(n117) );
XOR2X1TS U113 ( .A(n163), .B(in1[3]), .Y(n164) );
OAI21X1TS U114 ( .A0(n160), .A1(in1[1]), .B0(n158), .Y(n159) );
NAND2X6TS U115 ( .A(n80), .B(n51), .Y(n50) );
XOR2X1TS U116 ( .A(n158), .B(in1[1]), .Y(n148) );
AOI2BB1XLTS U117 ( .A0N(in2[0]), .A1N(in1[0]), .B0(n160), .Y(res[0]) );
INVX3TS U118 ( .A(in2[5]), .Y(n98) );
INVX16TS U119 ( .A(in2[2]), .Y(n95) );
NAND2X4TS U120 ( .A(n118), .B(add_sub), .Y(n94) );
NAND2X4TS U121 ( .A(n59), .B(n58), .Y(n144) );
NAND4X8TS U122 ( .A(n96), .B(n100), .C(n146), .D(n95), .Y(n118) );
NOR2X8TS U123 ( .A(n137), .B(n136), .Y(n77) );
NAND2X8TS U124 ( .A(n53), .B(n52), .Y(n137) );
NAND3X8TS U125 ( .A(n93), .B(n146), .C(n95), .Y(n82) );
XOR2X2TS U126 ( .A(n132), .B(n47), .Y(res[15]) );
NAND2BX4TS U127 ( .AN(in2[7]), .B(n115), .Y(n120) );
NOR2X4TS U128 ( .A(n109), .B(in2[12]), .Y(n106) );
OR3X1TS U129 ( .A(in2[2]), .B(in2[0]), .C(in2[1]), .Y(n150) );
NOR2X4TS U130 ( .A(n82), .B(n81), .Y(n119) );
NAND2X4TS U131 ( .A(n96), .B(n100), .Y(n81) );
CLKINVX3TS U132 ( .A(n82), .Y(n51) );
INVX2TS U133 ( .A(in2[11]), .Y(n83) );
NAND2X1TS U134 ( .A(n130), .B(in1[7]), .Y(n58) );
INVX2TS U135 ( .A(in2[9]), .Y(n84) );
INVX2TS U136 ( .A(in1[12]), .Y(n55) );
BUFX3TS U137 ( .A(n46), .Y(n70) );
XNOR2X1TS U138 ( .A(n155), .B(in1[5]), .Y(n156) );
NOR2BX1TS U139 ( .AN(n86), .B(n154), .Y(n85) );
INVX2TS U140 ( .A(in1[6]), .Y(n68) );
XOR2XLTS U141 ( .A(n64), .B(n63), .Y(res[7]) );
XOR2X1TS U142 ( .A(n130), .B(in1[7]), .Y(n63) );
XOR2X1TS U143 ( .A(n126), .B(n56), .Y(res[12]) );
XNOR2X1TS U144 ( .A(n138), .B(n137), .Y(res[13]) );
AFHCINX4TS U145 ( .CIN(n141), .B(n142), .A(in1[9]), .S(res[9]), .CO(n140) );
XNOR2X2TS U146 ( .A(n151), .B(in2[3]), .Y(n163) );
XOR2X1TS U147 ( .A(n127), .B(in1[12]), .Y(n56) );
INVX2TS U148 ( .A(n127), .Y(n54) );
NAND2X2TS U149 ( .A(n109), .B(add_sub), .Y(n110) );
OR2X8TS U150 ( .A(n125), .B(in1[6]), .Y(n67) );
NAND2X8TS U151 ( .A(n72), .B(n73), .Y(n132) );
OAI2BB1X4TS U152 ( .A0N(n55), .A1N(n54), .B0(n126), .Y(n53) );
XNOR2X1TS U153 ( .A(n124), .B(n57), .Y(res[6]) );
XOR2X1TS U154 ( .A(n125), .B(n68), .Y(n57) );
NAND2X8TS U155 ( .A(n66), .B(n65), .Y(n64) );
NAND2X2TS U156 ( .A(n125), .B(in1[6]), .Y(n65) );
NAND2X8TS U157 ( .A(n124), .B(n67), .Y(n66) );
OR2X1TS U158 ( .A(n69), .B(in1[4]), .Y(n86) );
XNOR2X1TS U159 ( .A(n69), .B(in1[4]), .Y(n153) );
XOR2X4TS U160 ( .A(n94), .B(n93), .Y(n69) );
OAI21X2TS U161 ( .A0(n132), .A1(n131), .B0(n71), .Y(res[16]) );
OAI21X4TS U162 ( .A0(n46), .A1(n77), .B0(n49), .Y(n72) );
INVX16TS U163 ( .A(in2[1]), .Y(n146) );
NAND4X8TS U164 ( .A(n98), .B(n96), .C(n78), .D(n100), .Y(n79) );
NOR2X8TS U165 ( .A(n82), .B(n79), .Y(n115) );
NOR2X8TS U166 ( .A(n81), .B(in2[5]), .Y(n80) );
NOR2BX1TS U167 ( .AN(n92), .B(n85), .Y(n157) );
NAND2X8TS U168 ( .A(n89), .B(n87), .Y(n124) );
NAND2X8TS U169 ( .A(n91), .B(n155), .Y(n89) );
XOR2X4TS U170 ( .A(n90), .B(in2[5]), .Y(n155) );
NAND2X8TS U171 ( .A(n92), .B(n97), .Y(n91) );
INVX12TS U172 ( .A(in2[3]), .Y(n96) );
INVX16TS U173 ( .A(in2[0]), .Y(n100) );
INVX2TS U174 ( .A(in1[5]), .Y(n97) );
XOR2X2TS U175 ( .A(n135), .B(n134), .Y(res[14]) );
ADDFHX4TS U176 ( .A(n140), .B(in1[10]), .CI(n139), .CO(n128), .S(res[10]) );
XOR2X4TS U177 ( .A(n116), .B(in2[7]), .Y(n130) );
NOR2XLTS U178 ( .A(n145), .B(n100), .Y(n147) );
XOR2X1TS U179 ( .A(n114), .B(in2[9]), .Y(n142) );
CLKXOR2X2TS U180 ( .A(n112), .B(in2[11]), .Y(n129) );
NOR2X1TS U181 ( .A(n113), .B(n145), .Y(n114) );
XNOR2X4TS U182 ( .A(n117), .B(in2[6]), .Y(n125) );
NAND2X1TS U183 ( .A(n120), .B(add_sub), .Y(n121) );
XNOR2X1TS U184 ( .A(n121), .B(in2[8]), .Y(n143) );
XNOR2X1TS U185 ( .A(n123), .B(in2[10]), .Y(n139) );
ADDFHX4TS U186 ( .A(n129), .B(in1[11]), .CI(n128), .CO(n126), .S(res[11]) );
AFHCONX2TS U187 ( .A(in1[8]), .B(n144), .CI(n143), .CON(n141), .S(res[8]) );
XNOR2X1TS U188 ( .A(n147), .B(n146), .Y(n158) );
XNOR2X1TS U189 ( .A(n149), .B(in2[2]), .Y(n161) );
NAND2X1TS U190 ( .A(add_sub), .B(n150), .Y(n151) );
AOI22X1TS U191 ( .A0(n161), .A1(n152), .B0(in1[3]), .B1(n163), .Y(n154) );
OAI2BB1X1TS U192 ( .A0N(n160), .A1N(in1[1]), .B0(n159), .Y(n162) );
CMPR32X2TS U193 ( .A(in1[2]), .B(n162), .C(n161), .CO(n165), .S(res[2]) );
initial $sdf_annotate("Approx_adder_ACAIIN8Q4_syn.sdf");
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_FUNCTIONAL_PP_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__dlybuf4s25kapwr (
X ,
A ,
VPWR ,
VGND ,
KAPWR,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input VPWR ;
input VGND ;
input KAPWR;
input VPB ;
input VNB ;
// Local signals
wire buf0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X , A );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, buf0_out_X, KAPWR, VGND);
buf buf1 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
`define SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
/**
* udp_dff$PR_pp$PG$N: Positive edge triggered D flip-flop with active
* high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__udp_dff$PR_pp$PG$N (
Q ,
D ,
CLK ,
RESET ,
NOTIFIER,
VPWR ,
VGND
);
output Q ;
input D ;
input CLK ;
input RESET ;
input NOTIFIER;
input VPWR ;
input VGND ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__UDP_DFF_PR_PP_PG_N_BLACKBOX_V
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module AESL_automem_b (
clk,
rst,
ce0,
we0,
address0,
din0,
dout0,
ce1,
we1,
address1,
din1,
dout1,
ready,
done
);
//------------------------Parameter----------------------
localparam
TV_IN = "c.matrix_mult.autotvin_b.dat",
TV_OUT = "impl_rtl.matrix_mult.autotvout_b.dat";
//------------------------Local signal-------------------
parameter DATA_WIDTH = 32'd 8;
parameter ADDR_WIDTH = 32'd 5;
parameter DEPTH = 32'd 25;
parameter DLY = 0.1;
// Input and Output
input clk;
input rst;
input ce0, ce1;
input we0, we1;
input [ADDR_WIDTH - 1 : 0] address0, address1;
input [DATA_WIDTH - 1 : 0] din0, din1;
output reg [DATA_WIDTH - 1 : 0] dout0, dout1;
input ready;
input done;
// Inner signals
reg [DATA_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
initial begin : initialize_mem
integer i;
for (i = 0; i < DEPTH; i = i + 1) begin
mem[i] = 0;
end
end
reg writed_flag;
event write_process_done;
//------------------------Task and function--------------
task read_token;
input integer fp;
output reg [127 :0] token;
integer ret;
begin
token = "";
ret = 0;
ret = $fscanf(fp,"%s",token);
end
endtask
//------------------------Read array-------------------
// Read data form file to array
initial begin : read_file_process
integer fp;
integer err;
integer ret;
reg [127 : 0] token;
reg [ 8*5 : 1] str;
reg [ DATA_WIDTH - 1 : 0 ] mem_tmp;
integer transaction_idx;
integer i;
transaction_idx = 0;
wait(rst === 0);
@(write_process_done);
fp = $fopen(TV_IN,"r");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_IN);
$finish;
end
read_token(fp, token);
if (token != "[[[runtime]]]") begin // Illegal format
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
while (token != "[[[/runtime]]]") begin
if (token != "[[transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token); // skip transaction number
while(ready == 0) begin
@(write_process_done);
end
for(i = 0; i < DEPTH; i = i + 1) begin
read_token(fp, token);
ret = $sscanf(token, "0x%x", mem_tmp);
mem[i] = mem_tmp;
if (ret != 1) begin
$display("Failed to parse token!");
$finish;
end
end
@(write_process_done);
read_token(fp, token);
if(token != "[[/transaction]]") begin
$display("ERROR: Simulation using HLS TB failed.");
$finish;
end
read_token(fp, token);
transaction_idx = transaction_idx + 1;
end
$fclose(fp);
end
// Read data from array to RTL
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout0 <= 0;
end
else begin
if((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
dout0 <= #DLY din1;
else if(ce0 == 1)
dout0 <= #DLY mem[address0];
else ;
end
end
always @ (posedge clk or rst) begin
if(rst === 1) begin
dout1 <= 0;
end
else begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
dout1 <= #DLY din0;
else if(ce1 == 1)
dout1 <= #DLY mem[address1];
else ;
end
end
//------------------------Write array-------------------
// Write data from RTL to array
always @ (posedge clk) begin
if((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
mem[address0] <= #DLY din1;
else if ((we0 == 1) && (ce0 == 1))
mem[address0] <= #DLY din0;
end
always @ (posedge clk) begin
if((ce1 == 1) && (we1 == 1))
mem[address1] <= #DLY din1;
end
// Write data from array to file
initial begin : write_file_proc
integer fp;
integer transaction_num;
reg [ 8*5 : 1] str;
integer i;
transaction_num = 0;
writed_flag = 1;
wait(rst === 0);
@(negedge clk);
while(1) begin
while(done == 0) begin
-> write_process_done;
@(negedge clk);
end
fp = $fopen(TV_OUT, "a");
if(fp == 0) begin // Failed to open file
$display("Failed to open file \"%s\"!", TV_OUT);
$finish;
end
$fdisplay(fp, "[[transaction]] %d", transaction_num);
for (i = 0; i < DEPTH; i = i + 1) begin
$fdisplay(fp,"0x%x",mem[i]);
end
$fdisplay(fp, "[[/transaction]]");
transaction_num = transaction_num + 1;
$fclose(fp);
writed_flag = 1;
-> write_process_done;
@(negedge clk);
end
end
//------------------------conflict check-------------------
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"WARNING:write conflict----port0 and port1 write to the same address:%h at the same clock. Port1 has the high priority.",address0);
end
always @ (posedge clk) begin
if ((we0 == 1) && (ce0 == 1) && (ce1 == 1) && (we1 == 0) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 write and port1 read to the same address:%h at the same clock. Write first Mode.",address0);
end
always @ (posedge clk) begin
if ((we0 == 0) && (ce0 == 1) && (ce1 == 1) && (we1 == 1) && (address0 == address1))
$display($time,"NOTE:read & write conflict----port0 read and port1 write to the same address:%h at the same clock. Write first Mode.",address0);
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND3_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__AND3_PP_BLACKBOX_V
/**
* and3: 3-input AND.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__and3 (
X ,
A ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND3_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A221OI_SYMBOL_V
`define SKY130_FD_SC_HS__A221OI_SYMBOL_V
/**
* a221oi: 2-input AND into first two inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | C1)
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__a221oi (
//# {{data|Data Signals}}
input A1,
input A2,
input B1,
input B2,
input C1,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__A221OI_SYMBOL_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A311O_4_V
`define SKY130_FD_SC_HD__A311O_4_V
/**
* a311o: 3-input AND into first input of 3-input OR.
*
* X = ((A1 & A2 & A3) | B1 | C1)
*
* Verilog wrapper for a311o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__a311o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_4 (
X ,
A1 ,
A2 ,
A3 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__a311o_4 (
X ,
A1,
A2,
A3,
B1,
C1
);
output X ;
input A1;
input A2;
input A3;
input B1;
input C1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__a311o base (
.X(X),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.C1(C1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__A311O_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_1_V
`define SKY130_FD_SC_LP__MUX2_1_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_1 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_1 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_1_V
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Sun Nov 13 08:55:56 2016
/////////////////////////////////////////////////////////////
module SNPS_CLOCK_GATE_HIGH_counter_d_W4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W8 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_0 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_5 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_7 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_10 ( CLK, EN, ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5_1 ( CLK, EN,
ENCLK, TE );
input CLK, EN, TE;
output ENCLK;
TLATNTSCAX2TS latch ( .E(EN), .SE(TE), .CK(CLK), .ECK(ENCLK) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
module CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5 ( clk, rst, beg_fsm_cordic,
ack_cordic, operation, data_in, shift_region_flag, r_mode,
ready_cordic, overflow_flag, underflow_flag, data_output );
input [31:0] data_in;
input [1:0] shift_region_flag;
input [1:0] r_mode;
output [31:0] data_output;
input clk, rst, beg_fsm_cordic, ack_cordic, operation;
output ready_cordic, overflow_flag, underflow_flag;
wire d_ff1_operation_out, enab_cont_iter, load_cont_iter, load_cont_var,
enab_d_ff2_RB2, enab_d_ff4_Xn, enab_d_ff4_Yn, enab_d_ff4_Zn,
enab_d_ff5_data_out, enab_dff_5, sel_mux_1_reg, d_ff3_sign_out,
sel_mux_3_reg, data_output2_31_, cordic_FSM_state_next_1_,
cont_iter_net3522673, add_subt_module_sign_final_result,
add_subt_module_FSM_selector_D, add_subt_module_FSM_LZA_load,
add_subt_module_FSM_Add_Subt_Sgf_load,
add_subt_module_FSM_barrel_shifter_load,
add_subt_module_FSM_exp_operation_load_diff,
add_subt_module_add_overflow_flag, add_subt_module_FSM_selector_C,
d_ff5_data_out_net3522529, reg_Z0_net3522529,
reg_val_muxZ_2stage_net3522529, reg_shift_y_net3522529,
d_ff4_Xn_net3522529, d_ff4_Yn_net3522529, d_ff4_Zn_net3522529,
d_ff5_net3522529, add_subt_module_FS_Module_net3522637,
add_subt_module_final_result_ieee_Module_Sign_S_mux,
add_subt_module_YRegister_net3522547,
add_subt_module_Exp_Operation_Module_exp_result_net3522601,
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565,
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547,
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583,
add_subt_module_Oper_Start_in_module_MRegister_net3522619,
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583, n580,
n582, n584, n585, n590, n591, n593, n594, n595, n596, n597, n600,
n601, n602, n604, n610, n612, n621, n636, n638, n639, n641, n642,
n644, n646, n649, n652, n660, n667, n669, intadd_391_B_0_,
intadd_391_CI, intadd_391_n3, intadd_391_n2, intadd_391_n1,
intadd_392_CI, intadd_392_n3, intadd_392_n2, intadd_392_n1, n678,
n679, n680, n681, n682, n683, n684, n685, n686, n687, n688, n689,
n690, n691, n692, n693, n694, n695, n696, n697, n698, n699, n700,
n701, n702, n703, n704, n705, n706, n707, n708, n709, n710, n711,
n712, n713, n714, n715, n716, n717, n718, n719, n720, n721, n722,
n723, n724, n725, n726, n727, n728, n729, n730, n731, n732, n733,
n734, n735, n736, n737, n738, n739, n740, n741, n742, n743, n744,
n745, n746, n747, n748, n749, n750, n751, n752, n753, n754, n755,
n756, n757, n758, n759, n760, n761, n762, n763, n764, n765, n766,
n767, n768, n769, n770, n771, n772, n773, n774, n775, n776, n777,
n778, n779, n780, n781, n782, n783, n784, n785, n786, n787, n788,
n789, n790, n791, n792, n793, n794, n795, n796, n797, n798, n799,
n800, n801, n802, n803, n804, n805, n806, n807, n808, n809, n810,
n811, n812, n813, n814, n815, n816, n817, n818, n819, n820, n821,
n822, n823, n824, n825, n826, n827, n828, n829, n830, n831, n832,
n833, n834, n835, n836, n837, n838, n839, n840, n841, n842, n843,
n844, n845, n846, n847, n848, n849, n850, n851, n852, n853, n854,
n855, n856, n857, n858, n859, n860, n861, n862, n863, n864, n865,
n866, n867, n868, n869, n870, n871, n872, n873, n874, n875, n876,
n877, n878, n879, n880, n881, n882, n883, n884, n885, n886, n887,
n888, n889, n890, n891, n892, n893, n894, n895, n896, n897, n898,
n899, n900, n901, n902, n903, n904, n905, n906, n907, n908, n909,
n910, n911, n912, n913, n914, n915, n916, n917, n918, n919, n920,
n921, n922, n923, n924, n925, n926, n927, n928, n929, n930, n931,
n932, n933, n934, n935, n936, n937, n938, n939, n940, n941, n942,
n943, n944, n945, n946, n947, n948, n949, n950, n951, n952, n953,
n954, n955, n956, n957, n958, n959, n960, n961, n962, n963, n964,
n965, n966, n967, n968, n969, n970, n971, n972, n973, n974, n975,
n976, n977, n978, n979, n980, n981, n982, n983, n984, n985, n986,
n987, n988, n989, n990, n991, n992, n993, n994, n995, n996, n997,
n998, n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007,
n1008, n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017,
n1018, n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027,
n1028, n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037,
n1038, n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047,
n1048, n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057,
n1058, n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067,
n1068, n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077,
n1078, n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087,
n1088, n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097,
n1098, n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107,
n1108, n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117,
n1118, n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127,
n1128, n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137,
n1138, n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147,
n1148, n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157,
n1158, n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167,
n1168, n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177,
n1178, n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187,
n1188, n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197,
n1198, n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207,
n1208, n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217,
n1218, n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227,
n1228, n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237,
n1238, n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247,
n1248, n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257,
n1258, n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267,
n1268, n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277,
n1278, n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287,
n1288, n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297,
n1298, n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307,
n1308, n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317,
n1318, n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327,
n1328, n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337,
n1338, n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347,
n1348, n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357,
n1358, n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367,
n1368, n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377,
n1378, n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387,
n1388, n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397,
n1398, n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407,
n1408, n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417,
n1418, n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427,
n1428, n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437,
n1438, n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447,
n1448, n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457,
n1458, n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467,
n1468, n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477,
n1478, n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487,
n1488, n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497,
n1498, n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507,
n1508, n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517,
n1518, n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527,
n1528, n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537,
n1538, n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547,
n1548, n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557,
n1558, n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567,
n1568, n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577,
n1578, n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587,
n1588, n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597,
n1598, n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607,
n1608, n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617,
n1618, n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627,
n1628, n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637,
n1638, n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647,
n1648, n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657,
n1658, n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667,
n1668, n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677,
n1678, n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687,
n1688, n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697,
n1698, n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707,
n1708, n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717,
n1718, n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727,
n1728, n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737,
n1738, n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747,
n1748, n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757,
n1758, n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767,
n1768, n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777,
n1778, n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787,
n1788, n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797,
n1798, n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807,
n1808, n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817,
n1818, n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827,
n1828, n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837,
n1838, n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847,
n1848, n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857,
n1858, n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867,
n1868, n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877,
n1878, n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887,
n1888, n1889, n1890, n1891, n1892, n1893, n1894, n1895, n1896, n1897,
n1898, n1899, n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907,
n1908, n1909, n1910, n1911, n1912, n1913, n1914, n1915, n1916, n1917,
n1918, n1919, n1920, n1921, n1922, n1923, n1924, n1925, n1926, n1927,
n1928, n1929, n1930, n1931, n1932, n1933, n1934, n1935, n1936, n1937,
n1938, n1939, n1940, n1941, n1942, n1943, n1944, n1945, n1946, n1947,
n1948, n1949, n1950, n1951, n1952, n1953, n1954, n1955, n1956, n1957,
n1958, n1959, n1960, n1961, n1962, n1963, n1964, n1965, n1966, n1967,
n1968, n1969, n1970, n1971, n1972, n1973, n1974, n1975, n1976, n1977,
n1978, n1979, n1980, n1981, n1983, n1984, n1985, n1986, n1987, n1988,
n1989, n1990, n1991, n1992, n1993, n1994, n1995, n1996, n1997, n1998,
n1999, n2000, n2001, n2002, n2003, n2004, n2005, n2006, n2007, n2008,
n2009, n2010, n2011, n2012, n2013;
wire [1:0] d_ff1_shift_region_flag_out;
wire [1:0] cont_var_out;
wire [3:0] cont_iter_out;
wire [31:0] d_ff1_Z;
wire [31:0] d_ff_Xn;
wire [31:0] first_mux_X;
wire [31:0] d_ff_Yn;
wire [31:0] first_mux_Y;
wire [31:0] d_ff_Zn;
wire [31:0] first_mux_Z;
wire [31:0] d_ff2_X;
wire [31:0] d_ff2_Y;
wire [31:0] d_ff2_Z;
wire [7:0] sh_exp_x;
wire [7:0] sh_exp_y;
wire [26:0] data_out_LUT;
wire [31:0] d_ff3_sh_x_out;
wire [31:0] d_ff3_sh_y_out;
wire [27:0] d_ff3_LUT_out;
wire [1:0] sel_mux_2_reg;
wire [31:0] result_add_subt;
wire [31:0] mux_sal;
wire [31:0] sign_inv_out;
wire [3:0] cordic_FSM_state_reg;
wire [25:0] add_subt_module_Sgf_normalized_result;
wire [25:0] add_subt_module_Add_Subt_result;
wire [4:0] add_subt_module_LZA_output;
wire [7:0] add_subt_module_exp_oper_result;
wire [30:0] add_subt_module_DmP;
wire [30:0] add_subt_module_DMP;
wire [30:0] add_subt_module_intDY;
wire [31:0] add_subt_module_intDX;
wire [1:0] add_subt_module_FSM_selector_B;
wire [3:0] add_subt_module_FS_Module_state_next;
wire [3:0] add_subt_module_FS_Module_state_reg;
wire [30:0] add_subt_module_Oper_Start_in_module_intm;
wire [30:0] add_subt_module_Oper_Start_in_module_intM;
wire [7:0] add_subt_module_Exp_Operation_Module_Data_S;
wire [26:3] add_subt_module_Add_Subt_Sgf_module_S_to_D;
wire [4:0] add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg;
wire [22:9] add_subt_module_final_result_ieee_Module_Sgf_S_mux;
wire [7:0] add_subt_module_final_result_ieee_Module_Exp_S_mux;
wire [48:0] add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array;
SNPS_CLOCK_GATE_HIGH_counter_d_W4 cont_iter_clk_gate_count_reg ( .CLK(clk),
.EN(enab_cont_iter), .ENCLK(cont_iter_net3522673), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_0 d_ff5_data_out_clk_gate_Q_reg ( .CLK(
clk), .EN(enab_d_ff5_data_out), .ENCLK(d_ff5_data_out_net3522529),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_10 reg_Z0_clk_gate_Q_reg ( .CLK(clk),
.EN(load_cont_iter), .ENCLK(reg_Z0_net3522529), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_7 reg_val_muxZ_2stage_clk_gate_Q_reg (
.CLK(clk), .EN(enab_d_ff2_RB2), .ENCLK(reg_val_muxZ_2stage_net3522529),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_5 reg_shift_y_clk_gate_Q_reg ( .CLK(clk),
.EN(load_cont_var), .ENCLK(reg_shift_y_net3522529), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_4 d_ff4_Xn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Xn), .ENCLK(d_ff4_Xn_net3522529), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_3 d_ff4_Yn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Yn), .ENCLK(d_ff4_Yn_net3522529), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_2 d_ff4_Zn_clk_gate_Q_reg ( .CLK(clk),
.EN(enab_d_ff4_Zn), .ENCLK(d_ff4_Zn_net3522529), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_d_ff_en_W32_0_1 d_ff5_clk_gate_Q_reg ( .CLK(clk), .EN(
enab_dff_5), .ENCLK(d_ff5_net3522529), .TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_FSM_Add_Subtract add_subt_module_FS_Module_clk_gate_state_reg_reg (
.CLK(clk), .EN(n604), .ENCLK(add_subt_module_FS_Module_net3522637),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_1 add_subt_module_YRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n669), .ENCLK(add_subt_module_YRegister_net3522547),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W8 add_subt_module_Exp_Operation_Module_exp_result_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_exp_operation_load_diff), .ENCLK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W5 add_subt_module_Leading_Zero_Detector_Module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_LZA_load), .ENCLK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W32_0_0 add_subt_module_final_result_ieee_Module_Final_Result_IEEE_clk_gate_Q_reg (
.CLK(clk), .EN(n1856), .ENCLK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.TE(1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_0 add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_Add_Subt_Sgf_load), .ENCLK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .TE(
1'b0) );
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W31_0_1 add_subt_module_Oper_Start_in_module_MRegister_clk_gate_Q_reg (
.CLK(clk), .EN(n1952), .ENCLK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .TE(1'b0)
);
SNPS_CLOCK_GATE_HIGH_RegisterAdd_W26_1_1 add_subt_module_Barrel_Shifter_module_Output_Reg_clk_gate_Q_reg (
.CLK(clk), .EN(add_subt_module_FSM_barrel_shifter_load), .ENCLK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .TE(1'b0) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_1_ ( .D(
add_subt_module_FS_Module_state_next[1]), .CK(
add_subt_module_FS_Module_net3522637), .RN(n1900), .Q(
add_subt_module_FS_Module_state_reg[1]), .QN(n1784) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_7_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[7]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1897), .Q(add_subt_module_exp_oper_result[7]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_6_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[6]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1897), .Q(add_subt_module_exp_oper_result[6]) );
DFFRXLTS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_5_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[5]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1897), .Q(add_subt_module_exp_oper_result[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Zn_net3522529), .RN(n1903), .Q(d_ff_Zn[22]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_22_ ( .D(first_mux_Z[22]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1903), .Q(d_ff2_Z[22]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_22_ ( .D(
add_subt_module_Oper_Start_in_module_intm[22]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1876),
.Q(add_subt_module_DmP[22]) );
DFFRXLTS d_ff4_Zn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Zn_net3522529), .RN(n1903), .Q(d_ff_Zn[15]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_15_ ( .D(first_mux_Z[15]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1903), .Q(d_ff2_Z[15]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_15_ ( .D(
add_subt_module_Oper_Start_in_module_intm[15]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1876),
.Q(add_subt_module_DmP[15]) );
DFFRXLTS d_ff4_Zn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Zn_net3522529), .RN(n1903), .Q(d_ff_Zn[18]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_18_ ( .D(first_mux_Z[18]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1903), .Q(d_ff2_Z[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_18_ ( .D(
add_subt_module_Oper_Start_in_module_intm[18]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1876),
.Q(add_subt_module_DmP[18]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_4_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]),
.CK(clk), .RN(n1877), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]), .QN(
n1859) );
DFFRXLTS d_ff4_Zn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Zn_net3522529), .RN(n1903), .Q(d_ff_Zn[19]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_19_ ( .D(first_mux_Z[19]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1903), .Q(d_ff2_Z[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_19_ ( .D(
add_subt_module_Oper_Start_in_module_intm[19]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1877),
.Q(add_subt_module_DmP[19]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_2_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]),
.CK(clk), .RN(n1877), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]), .QN(
n1860) );
DFFRXLTS d_ff4_Zn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Zn_net3522529), .RN(n1903), .Q(d_ff_Zn[21]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_21_ ( .D(first_mux_Z[21]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1903), .Q(d_ff2_Z[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_21_ ( .D(
add_subt_module_Oper_Start_in_module_intm[21]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1877),
.Q(add_subt_module_DmP[21]) );
DFFRXLTS d_ff4_Zn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Zn_net3522529), .RN(n1904), .Q(d_ff_Zn[6]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_6_ ( .D(first_mux_Z[6]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1912), .Q(d_ff2_Z[6]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_6_ ( .D(
add_subt_module_Oper_Start_in_module_intm[6]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1877),
.Q(add_subt_module_DmP[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Zn_net3522529), .RN(n1932), .Q(d_ff_Zn[13]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_13_ ( .D(first_mux_Z[13]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1935), .Q(d_ff2_Z[13]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_13_ ( .D(
add_subt_module_Oper_Start_in_module_intm[13]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1878),
.Q(add_subt_module_DmP[13]) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_3_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]),
.CK(clk), .RN(n1878), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]), .QN(
n1861) );
DFFRXLTS d_ff4_Zn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Zn_net3522529), .RN(n1904), .Q(d_ff_Zn[20]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_20_ ( .D(first_mux_Z[20]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1912), .Q(d_ff2_Z[20]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_20_ ( .D(
add_subt_module_Oper_Start_in_module_intm[20]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1878),
.Q(add_subt_module_DmP[20]) );
DFFRXLTS d_ff4_Zn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Zn_net3522529), .RN(n1932), .Q(d_ff_Zn[16]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_16_ ( .D(first_mux_Z[16]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1935), .Q(d_ff2_Z[16]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_16_ ( .D(
add_subt_module_Oper_Start_in_module_intm[16]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1879),
.Q(add_subt_module_DmP[16]) );
DFFRXLTS d_ff4_Zn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Zn_net3522529), .RN(n1904), .Q(d_ff_Zn[17]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_17_ ( .D(first_mux_Z[17]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1912), .Q(d_ff2_Z[17]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_17_ ( .D(
add_subt_module_Oper_Start_in_module_intm[17]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1879),
.Q(add_subt_module_DmP[17]) );
DFFRXLTS d_ff4_Zn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Zn_net3522529), .RN(n1906), .Q(d_ff_Zn[11]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_11_ ( .D(first_mux_Z[11]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1922), .Q(d_ff2_Z[11]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_11_ ( .D(
add_subt_module_Oper_Start_in_module_intm[11]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1879),
.Q(add_subt_module_DmP[11]) );
DFFRXLTS d_ff4_Zn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Zn_net3522529), .RN(n1905), .Q(d_ff_Zn[14]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_14_ ( .D(first_mux_Z[14]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1906), .Q(d_ff2_Z[14]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_14_ ( .D(
add_subt_module_Oper_Start_in_module_intm[14]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1880),
.Q(add_subt_module_DmP[14]) );
DFFRXLTS d_ff4_Zn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Zn_net3522529), .RN(n1922), .Q(d_ff_Zn[10]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_10_ ( .D(first_mux_Z[10]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1905), .Q(d_ff2_Z[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_10_ ( .D(
add_subt_module_Oper_Start_in_module_intm[10]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1880),
.Q(add_subt_module_DmP[10]) );
DFFRXLTS d_ff4_Zn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Zn_net3522529), .RN(n1906), .Q(d_ff_Zn[12]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_12_ ( .D(first_mux_Z[12]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1922), .Q(d_ff2_Z[12]) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_3_ ( .D(
add_subt_module_FS_Module_state_next[3]), .CK(
add_subt_module_FS_Module_net3522637), .RN(n1899), .Q(
add_subt_module_FS_Module_state_reg[3]), .QN(n1748) );
DFFRX2TS add_subt_module_FS_Module_state_reg_reg_2_ ( .D(
add_subt_module_FS_Module_state_next[2]), .CK(
add_subt_module_FS_Module_net3522637), .RN(n1900), .Q(
add_subt_module_FS_Module_state_reg[2]), .QN(n1745) );
DFFRX2TS cordic_FSM_state_reg_reg_3_ ( .D(n600), .CK(n1981), .RN(n1882), .Q(
cordic_FSM_state_reg[3]), .QN(n1808) );
DFFRXLTS cont_iter_count_reg_0_ ( .D(n1987), .CK(cont_iter_net3522673), .RN(
n1905), .Q(cont_iter_out[0]), .QN(n715) );
DFFRXLTS cont_iter_count_reg_2_ ( .D(n1986), .CK(cont_iter_net3522673), .RN(
n1906), .Q(cont_iter_out[2]), .QN(n714) );
DFFRXLTS reg_region_flag_Q_reg_0_ ( .D(shift_region_flag[0]), .CK(
reg_Z0_net3522529), .RN(n1922), .Q(d_ff1_shift_region_flag_out[0]),
.QN(n681) );
DFFRXLTS reg_LUT_Q_reg_26_ ( .D(data_out_LUT[26]), .CK(
reg_shift_y_net3522529), .RN(n1906), .Q(d_ff3_LUT_out[26]) );
DFFRXLTS reg_LUT_Q_reg_25_ ( .D(data_out_LUT[25]), .CK(
reg_shift_y_net3522529), .RN(n1922), .Q(d_ff3_LUT_out[25]) );
DFFRXLTS reg_LUT_Q_reg_24_ ( .D(data_out_LUT[24]), .CK(
reg_shift_y_net3522529), .RN(n1905), .Q(d_ff3_LUT_out[24]) );
DFFRXLTS reg_LUT_Q_reg_23_ ( .D(data_out_LUT[23]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[23]) );
DFFRXLTS reg_LUT_Q_reg_21_ ( .D(data_out_LUT[21]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[21]) );
DFFRXLTS reg_LUT_Q_reg_19_ ( .D(data_out_LUT[22]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[19]) );
DFFRXLTS reg_LUT_Q_reg_15_ ( .D(data_out_LUT[20]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[15]) );
DFFRXLTS reg_LUT_Q_reg_13_ ( .D(data_out_LUT[18]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[13]) );
DFFRXLTS reg_LUT_Q_reg_12_ ( .D(data_out_LUT[12]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[12]) );
DFFRXLTS reg_LUT_Q_reg_10_ ( .D(data_out_LUT[10]), .CK(
reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[10]) );
DFFRXLTS reg_LUT_Q_reg_9_ ( .D(data_out_LUT[9]), .CK(reg_shift_y_net3522529),
.RN(n1907), .Q(d_ff3_LUT_out[9]) );
DFFRXLTS reg_LUT_Q_reg_8_ ( .D(data_out_LUT[8]), .CK(reg_shift_y_net3522529),
.RN(n1907), .Q(d_ff3_LUT_out[8]) );
DFFRXLTS reg_LUT_Q_reg_7_ ( .D(data_out_LUT[11]), .CK(reg_shift_y_net3522529), .RN(n1907), .Q(d_ff3_LUT_out[7]) );
DFFRXLTS reg_LUT_Q_reg_6_ ( .D(data_out_LUT[6]), .CK(reg_shift_y_net3522529),
.RN(n1908), .Q(d_ff3_LUT_out[6]) );
DFFRXLTS reg_LUT_Q_reg_5_ ( .D(data_out_LUT[14]), .CK(reg_shift_y_net3522529), .RN(n1908), .Q(d_ff3_LUT_out[5]) );
DFFRXLTS reg_LUT_Q_reg_4_ ( .D(data_out_LUT[4]), .CK(reg_shift_y_net3522529),
.RN(n1908), .Q(d_ff3_LUT_out[4]) );
DFFRXLTS reg_LUT_Q_reg_3_ ( .D(data_out_LUT[16]), .CK(reg_shift_y_net3522529), .RN(n1908), .Q(d_ff3_LUT_out[3]) );
DFFRXLTS reg_LUT_Q_reg_2_ ( .D(data_out_LUT[2]), .CK(reg_shift_y_net3522529),
.RN(n1908), .Q(d_ff3_LUT_out[2]) );
DFFRXLTS reg_LUT_Q_reg_1_ ( .D(data_out_LUT[1]), .CK(reg_shift_y_net3522529),
.RN(n1908), .Q(d_ff3_LUT_out[1]) );
DFFRXLTS reg_LUT_Q_reg_0_ ( .D(data_out_LUT[0]), .CK(reg_shift_y_net3522529),
.RN(n1908), .Q(d_ff3_LUT_out[0]) );
DFFRXLTS reg_Z0_Q_reg_30_ ( .D(data_in[30]), .CK(reg_Z0_net3522529), .RN(
n1908), .Q(d_ff1_Z[30]) );
DFFRXLTS reg_Z0_Q_reg_29_ ( .D(data_in[29]), .CK(reg_Z0_net3522529), .RN(
n1908), .Q(d_ff1_Z[29]) );
DFFRXLTS reg_Z0_Q_reg_28_ ( .D(data_in[28]), .CK(reg_Z0_net3522529), .RN(
n1908), .Q(d_ff1_Z[28]) );
DFFRXLTS reg_Z0_Q_reg_27_ ( .D(data_in[27]), .CK(reg_Z0_net3522529), .RN(
n1934), .Q(d_ff1_Z[27]) );
DFFRXLTS reg_Z0_Q_reg_26_ ( .D(data_in[26]), .CK(reg_Z0_net3522529), .RN(
n1914), .Q(d_ff1_Z[26]) );
DFFRXLTS reg_Z0_Q_reg_25_ ( .D(data_in[25]), .CK(reg_Z0_net3522529), .RN(
n1917), .Q(d_ff1_Z[25]) );
DFFRXLTS reg_Z0_Q_reg_24_ ( .D(data_in[24]), .CK(reg_Z0_net3522529), .RN(
n1924), .Q(d_ff1_Z[24]) );
DFFRXLTS reg_Z0_Q_reg_23_ ( .D(data_in[23]), .CK(reg_Z0_net3522529), .RN(
n1909), .Q(d_ff1_Z[23]) );
DFFRXLTS reg_Z0_Q_reg_22_ ( .D(data_in[22]), .CK(reg_Z0_net3522529), .RN(
n1910), .Q(d_ff1_Z[22]) );
DFFRXLTS reg_Z0_Q_reg_21_ ( .D(data_in[21]), .CK(reg_Z0_net3522529), .RN(
n1911), .Q(d_ff1_Z[21]) );
DFFRXLTS reg_Z0_Q_reg_20_ ( .D(data_in[20]), .CK(reg_Z0_net3522529), .RN(
n1934), .Q(d_ff1_Z[20]) );
DFFRXLTS reg_Z0_Q_reg_19_ ( .D(data_in[19]), .CK(reg_Z0_net3522529), .RN(
n1914), .Q(d_ff1_Z[19]) );
DFFRXLTS reg_Z0_Q_reg_18_ ( .D(data_in[18]), .CK(reg_Z0_net3522529), .RN(
n1917), .Q(d_ff1_Z[18]) );
DFFRXLTS reg_Z0_Q_reg_17_ ( .D(data_in[17]), .CK(reg_Z0_net3522529), .RN(
n1914), .Q(d_ff1_Z[17]) );
DFFRXLTS reg_Z0_Q_reg_16_ ( .D(data_in[16]), .CK(reg_Z0_net3522529), .RN(
n1917), .Q(d_ff1_Z[16]) );
DFFRXLTS reg_Z0_Q_reg_15_ ( .D(data_in[15]), .CK(reg_Z0_net3522529), .RN(
n1924), .Q(d_ff1_Z[15]) );
DFFRXLTS reg_Z0_Q_reg_14_ ( .D(data_in[14]), .CK(reg_Z0_net3522529), .RN(
n1909), .Q(d_ff1_Z[14]) );
DFFRXLTS reg_Z0_Q_reg_13_ ( .D(data_in[13]), .CK(reg_Z0_net3522529), .RN(
n1910), .Q(d_ff1_Z[13]) );
DFFRXLTS reg_Z0_Q_reg_12_ ( .D(data_in[12]), .CK(reg_Z0_net3522529), .RN(
n1911), .Q(d_ff1_Z[12]) );
DFFRXLTS reg_Z0_Q_reg_11_ ( .D(data_in[11]), .CK(reg_Z0_net3522529), .RN(
n1934), .Q(d_ff1_Z[11]) );
DFFRXLTS reg_Z0_Q_reg_10_ ( .D(data_in[10]), .CK(reg_Z0_net3522529), .RN(
n1914), .Q(d_ff1_Z[10]) );
DFFRXLTS reg_Z0_Q_reg_9_ ( .D(data_in[9]), .CK(reg_Z0_net3522529), .RN(n1917), .Q(d_ff1_Z[9]) );
DFFRXLTS reg_Z0_Q_reg_8_ ( .D(data_in[8]), .CK(reg_Z0_net3522529), .RN(n1924), .Q(d_ff1_Z[8]) );
DFFRXLTS reg_Z0_Q_reg_7_ ( .D(data_in[7]), .CK(reg_Z0_net3522529), .RN(n1909), .Q(d_ff1_Z[7]) );
DFFRXLTS reg_Z0_Q_reg_6_ ( .D(data_in[6]), .CK(reg_Z0_net3522529), .RN(n1910), .Q(d_ff1_Z[6]) );
DFFRXLTS reg_Z0_Q_reg_5_ ( .D(data_in[5]), .CK(reg_Z0_net3522529), .RN(n1911), .Q(d_ff1_Z[5]) );
DFFRXLTS reg_Z0_Q_reg_4_ ( .D(data_in[4]), .CK(reg_Z0_net3522529), .RN(n1934), .Q(d_ff1_Z[4]) );
DFFRXLTS reg_Z0_Q_reg_3_ ( .D(data_in[3]), .CK(reg_Z0_net3522529), .RN(n1914), .Q(d_ff1_Z[3]) );
DFFRXLTS reg_Z0_Q_reg_2_ ( .D(data_in[2]), .CK(reg_Z0_net3522529), .RN(n1917), .Q(d_ff1_Z[2]) );
DFFRXLTS reg_Z0_Q_reg_1_ ( .D(data_in[1]), .CK(reg_Z0_net3522529), .RN(n1924), .Q(d_ff1_Z[1]) );
DFFRXLTS reg_Z0_Q_reg_0_ ( .D(data_in[0]), .CK(reg_Z0_net3522529), .RN(n1909), .Q(d_ff1_Z[0]) );
DFFRXLTS reg_Z0_Q_reg_31_ ( .D(data_in[31]), .CK(reg_Z0_net3522529), .RN(
n1910), .Q(d_ff1_Z[31]) );
DFFRXLTS reg_shift_x_Q_reg_30_ ( .D(sh_exp_x[7]), .CK(reg_shift_y_net3522529), .RN(n1911), .Q(d_ff3_sh_x_out[30]) );
DFFRXLTS reg_shift_x_Q_reg_29_ ( .D(sh_exp_x[6]), .CK(reg_shift_y_net3522529), .RN(n1932), .Q(d_ff3_sh_x_out[29]) );
DFFRXLTS reg_shift_x_Q_reg_28_ ( .D(sh_exp_x[5]), .CK(reg_shift_y_net3522529), .RN(n1935), .Q(d_ff3_sh_x_out[28]) );
DFFRXLTS reg_shift_x_Q_reg_27_ ( .D(sh_exp_x[4]), .CK(reg_shift_y_net3522529), .RN(n1904), .Q(d_ff3_sh_x_out[27]) );
DFFRXLTS reg_shift_x_Q_reg_26_ ( .D(sh_exp_x[3]), .CK(reg_shift_y_net3522529), .RN(n1912), .Q(d_ff3_sh_x_out[26]) );
DFFRXLTS reg_shift_x_Q_reg_25_ ( .D(sh_exp_x[2]), .CK(reg_shift_y_net3522529), .RN(n1932), .Q(d_ff3_sh_x_out[25]) );
DFFRXLTS reg_shift_x_Q_reg_24_ ( .D(sh_exp_x[1]), .CK(reg_shift_y_net3522529), .RN(n1935), .Q(d_ff3_sh_x_out[24]) );
DFFRXLTS reg_shift_x_Q_reg_23_ ( .D(sh_exp_x[0]), .CK(reg_shift_y_net3522529), .RN(n1932), .Q(d_ff3_sh_x_out[23]) );
DFFRXLTS reg_shift_y_Q_reg_30_ ( .D(sh_exp_y[7]), .CK(reg_shift_y_net3522529), .RN(n1935), .Q(d_ff3_sh_y_out[30]) );
DFFRXLTS reg_shift_y_Q_reg_29_ ( .D(sh_exp_y[6]), .CK(reg_shift_y_net3522529), .RN(n1904), .Q(d_ff3_sh_y_out[29]) );
DFFRXLTS reg_shift_y_Q_reg_28_ ( .D(sh_exp_y[5]), .CK(reg_shift_y_net3522529), .RN(n1912), .Q(d_ff3_sh_y_out[28]) );
DFFRXLTS reg_shift_y_Q_reg_27_ ( .D(sh_exp_y[4]), .CK(reg_shift_y_net3522529), .RN(n1913), .Q(d_ff3_sh_y_out[27]) );
DFFRXLTS reg_shift_y_Q_reg_26_ ( .D(sh_exp_y[3]), .CK(reg_shift_y_net3522529), .RN(n1916), .Q(d_ff3_sh_y_out[26]) );
DFFRXLTS reg_shift_y_Q_reg_25_ ( .D(sh_exp_y[2]), .CK(reg_shift_y_net3522529), .RN(n1913), .Q(d_ff3_sh_y_out[25]) );
DFFRXLTS reg_shift_y_Q_reg_24_ ( .D(sh_exp_y[1]), .CK(reg_shift_y_net3522529), .RN(n1916), .Q(d_ff3_sh_y_out[24]) );
DFFRXLTS reg_shift_y_Q_reg_23_ ( .D(sh_exp_y[0]), .CK(reg_shift_y_net3522529), .RN(n1913), .Q(d_ff3_sh_y_out[23]) );
DFFRXLTS d_ff4_Xn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Xn_net3522529), .RN(n1916), .Q(d_ff_Xn[30]) );
DFFRXLTS d_ff4_Xn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Xn_net3522529), .RN(n1913), .Q(d_ff_Xn[29]) );
DFFRXLTS d_ff4_Xn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Xn_net3522529), .RN(n1916), .Q(d_ff_Xn[28]) );
DFFRXLTS d_ff4_Xn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Xn_net3522529), .RN(n1916), .Q(d_ff_Xn[27]) );
DFFRXLTS d_ff4_Xn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Xn_net3522529), .RN(n1913), .Q(d_ff_Xn[26]) );
DFFRXLTS d_ff4_Xn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Xn_net3522529), .RN(n1917), .Q(d_ff_Xn[25]) );
DFFRXLTS d_ff4_Xn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Xn_net3522529), .RN(n1924), .Q(d_ff_Xn[24]) );
DFFRXLTS d_ff4_Xn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Xn_net3522529), .RN(n1909), .Q(d_ff_Xn[23]) );
DFFRXLTS d_ff4_Xn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Xn_net3522529), .RN(n1910), .Q(d_ff_Xn[22]) );
DFFRXLTS d_ff4_Xn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Xn_net3522529), .RN(n1911), .Q(d_ff_Xn[21]) );
DFFRXLTS d_ff4_Xn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Xn_net3522529), .RN(n1934), .Q(d_ff_Xn[20]) );
DFFRXLTS d_ff4_Xn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Xn_net3522529), .RN(n1914), .Q(d_ff_Xn[19]) );
DFFRXLTS d_ff4_Xn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Xn_net3522529), .RN(n1917), .Q(d_ff_Xn[18]) );
DFFRXLTS d_ff4_Xn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Xn_net3522529), .RN(n1924), .Q(d_ff_Xn[17]) );
DFFRXLTS d_ff4_Xn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Xn_net3522529), .RN(n1909), .Q(d_ff_Xn[16]) );
DFFRXLTS d_ff4_Xn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Xn_net3522529), .RN(n1920), .Q(d_ff_Xn[15]) );
DFFRXLTS d_ff4_Xn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Xn_net3522529), .RN(n1915), .Q(d_ff_Xn[14]) );
DFFRXLTS d_ff4_Xn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Xn_net3522529), .RN(n688), .Q(d_ff_Xn[13]) );
DFFRXLTS d_ff4_Xn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Xn_net3522529), .RN(n688), .Q(d_ff_Xn[12]) );
DFFRXLTS d_ff4_Xn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Xn_net3522529), .RN(n687), .Q(d_ff_Xn[11]) );
DFFRXLTS d_ff4_Xn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Xn_net3522529), .RN(n688), .Q(d_ff_Xn[10]) );
DFFRXLTS d_ff4_Xn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Xn_net3522529), .RN(n1918), .Q(d_ff_Xn[6]) );
DFFRXLTS d_ff4_Yn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Yn_net3522529), .RN(n1921), .Q(d_ff_Yn[30]) );
DFFRXLTS d_ff4_Yn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Yn_net3522529), .RN(n1921), .Q(d_ff_Yn[29]) );
DFFRXLTS d_ff4_Yn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Yn_net3522529), .RN(n1919), .Q(d_ff_Yn[28]) );
DFFRXLTS d_ff4_Yn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Yn_net3522529), .RN(n1913), .Q(d_ff_Yn[27]) );
DFFRXLTS d_ff4_Yn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Yn_net3522529), .RN(n1916), .Q(d_ff_Yn[26]) );
DFFRXLTS d_ff4_Yn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Yn_net3522529), .RN(n1913), .Q(d_ff_Yn[25]) );
DFFRXLTS d_ff4_Yn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Yn_net3522529), .RN(n1916), .Q(d_ff_Yn[24]) );
DFFRXLTS d_ff4_Yn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Yn_net3522529), .RN(n1913), .Q(d_ff_Yn[23]) );
DFFRXLTS d_ff4_Yn_Q_reg_22_ ( .D(result_add_subt[22]), .CK(
d_ff4_Yn_net3522529), .RN(n1916), .Q(d_ff_Yn[22]) );
DFFRXLTS d_ff4_Yn_Q_reg_21_ ( .D(result_add_subt[21]), .CK(
d_ff4_Yn_net3522529), .RN(n1913), .Q(d_ff_Yn[21]) );
DFFRXLTS d_ff4_Yn_Q_reg_20_ ( .D(result_add_subt[20]), .CK(
d_ff4_Yn_net3522529), .RN(n1916), .Q(d_ff_Yn[20]) );
DFFRXLTS d_ff4_Yn_Q_reg_19_ ( .D(result_add_subt[19]), .CK(
d_ff4_Yn_net3522529), .RN(n1913), .Q(d_ff_Yn[19]) );
DFFRXLTS d_ff4_Yn_Q_reg_18_ ( .D(result_add_subt[18]), .CK(
d_ff4_Yn_net3522529), .RN(n1916), .Q(d_ff_Yn[18]) );
DFFRXLTS d_ff4_Yn_Q_reg_17_ ( .D(result_add_subt[17]), .CK(
d_ff4_Yn_net3522529), .RN(n1911), .Q(d_ff_Yn[17]) );
DFFRXLTS d_ff4_Yn_Q_reg_16_ ( .D(result_add_subt[16]), .CK(
d_ff4_Yn_net3522529), .RN(n1934), .Q(d_ff_Yn[16]) );
DFFRXLTS d_ff4_Yn_Q_reg_15_ ( .D(result_add_subt[15]), .CK(
d_ff4_Yn_net3522529), .RN(n1914), .Q(d_ff_Yn[15]) );
DFFRXLTS d_ff4_Yn_Q_reg_14_ ( .D(result_add_subt[14]), .CK(
d_ff4_Yn_net3522529), .RN(n1917), .Q(d_ff_Yn[14]) );
DFFRXLTS d_ff4_Yn_Q_reg_13_ ( .D(result_add_subt[13]), .CK(
d_ff4_Yn_net3522529), .RN(n1924), .Q(d_ff_Yn[13]) );
DFFRXLTS d_ff4_Yn_Q_reg_12_ ( .D(result_add_subt[12]), .CK(
d_ff4_Yn_net3522529), .RN(n1909), .Q(d_ff_Yn[12]) );
DFFRXLTS d_ff4_Yn_Q_reg_11_ ( .D(result_add_subt[11]), .CK(
d_ff4_Yn_net3522529), .RN(n1910), .Q(d_ff_Yn[11]) );
DFFRXLTS d_ff4_Yn_Q_reg_10_ ( .D(result_add_subt[10]), .CK(
d_ff4_Yn_net3522529), .RN(n1911), .Q(d_ff_Yn[10]) );
DFFRXLTS d_ff4_Yn_Q_reg_6_ ( .D(result_add_subt[6]), .CK(d_ff4_Yn_net3522529), .RN(n1934), .Q(d_ff_Yn[6]) );
DFFRXLTS d_ff4_Zn_Q_reg_30_ ( .D(result_add_subt[30]), .CK(
d_ff4_Zn_net3522529), .RN(n1914), .Q(d_ff_Zn[30]) );
DFFRXLTS d_ff4_Zn_Q_reg_29_ ( .D(result_add_subt[29]), .CK(
d_ff4_Zn_net3522529), .RN(n1921), .Q(d_ff_Zn[29]) );
DFFRXLTS d_ff4_Zn_Q_reg_28_ ( .D(result_add_subt[28]), .CK(
d_ff4_Zn_net3522529), .RN(n1920), .Q(d_ff_Zn[28]) );
DFFRXLTS d_ff4_Zn_Q_reg_27_ ( .D(result_add_subt[27]), .CK(
d_ff4_Zn_net3522529), .RN(n1919), .Q(d_ff_Zn[27]) );
DFFRXLTS d_ff4_Zn_Q_reg_26_ ( .D(result_add_subt[26]), .CK(
d_ff4_Zn_net3522529), .RN(n1923), .Q(d_ff_Zn[26]) );
DFFRXLTS d_ff4_Zn_Q_reg_25_ ( .D(result_add_subt[25]), .CK(
d_ff4_Zn_net3522529), .RN(n1915), .Q(d_ff_Zn[25]) );
DFFRXLTS d_ff4_Zn_Q_reg_24_ ( .D(result_add_subt[24]), .CK(
d_ff4_Zn_net3522529), .RN(n1918), .Q(d_ff_Zn[24]) );
DFFRXLTS d_ff4_Zn_Q_reg_23_ ( .D(result_add_subt[23]), .CK(
d_ff4_Zn_net3522529), .RN(n1915), .Q(d_ff_Zn[23]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_6_ ( .D(first_mux_Y[6]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1920), .Q(d_ff2_Y[6]) );
DFFRXLTS reg_shift_y_Q_reg_6_ ( .D(d_ff2_Y[6]), .CK(reg_shift_y_net3522529),
.RN(n688), .Q(d_ff3_sh_y_out[6]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_10_ ( .D(first_mux_Y[10]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1918), .Q(d_ff2_Y[10]) );
DFFRXLTS reg_shift_y_Q_reg_10_ ( .D(d_ff2_Y[10]), .CK(reg_shift_y_net3522529), .RN(n1915), .Q(d_ff3_sh_y_out[10]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_11_ ( .D(first_mux_Y[11]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1915), .Q(d_ff2_Y[11]) );
DFFRXLTS reg_shift_y_Q_reg_11_ ( .D(d_ff2_Y[11]), .CK(reg_shift_y_net3522529), .RN(n1918), .Q(d_ff3_sh_y_out[11]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_12_ ( .D(first_mux_Y[12]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1915), .Q(d_ff2_Y[12]) );
DFFRXLTS reg_shift_y_Q_reg_12_ ( .D(d_ff2_Y[12]), .CK(reg_shift_y_net3522529), .RN(n688), .Q(d_ff3_sh_y_out[12]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_13_ ( .D(first_mux_Y[13]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1920), .Q(d_ff2_Y[13]) );
DFFRXLTS reg_shift_y_Q_reg_13_ ( .D(d_ff2_Y[13]), .CK(reg_shift_y_net3522529), .RN(n1920), .Q(d_ff3_sh_y_out[13]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_14_ ( .D(first_mux_Y[14]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1921), .Q(d_ff2_Y[14]) );
DFFRXLTS reg_shift_y_Q_reg_14_ ( .D(d_ff2_Y[14]), .CK(reg_shift_y_net3522529), .RN(n1926), .Q(d_ff3_sh_y_out[14]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_15_ ( .D(first_mux_Y[15]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1920), .Q(d_ff2_Y[15]) );
DFFRXLTS reg_shift_y_Q_reg_15_ ( .D(d_ff2_Y[15]), .CK(reg_shift_y_net3522529), .RN(n1920), .Q(d_ff3_sh_y_out[15]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_16_ ( .D(first_mux_Y[16]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1926), .Q(d_ff2_Y[16]) );
DFFRXLTS reg_shift_y_Q_reg_16_ ( .D(d_ff2_Y[16]), .CK(reg_shift_y_net3522529), .RN(n1923), .Q(d_ff3_sh_y_out[16]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_17_ ( .D(first_mux_Y[17]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1919), .Q(d_ff2_Y[17]) );
DFFRXLTS reg_shift_y_Q_reg_17_ ( .D(d_ff2_Y[17]), .CK(reg_shift_y_net3522529), .RN(n688), .Q(d_ff3_sh_y_out[17]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_18_ ( .D(first_mux_Y[18]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1920), .Q(d_ff2_Y[18]) );
DFFRXLTS reg_shift_y_Q_reg_18_ ( .D(d_ff2_Y[18]), .CK(reg_shift_y_net3522529), .RN(n687), .Q(d_ff3_sh_y_out[18]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_19_ ( .D(first_mux_Y[19]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1923), .Q(d_ff2_Y[19]) );
DFFRXLTS reg_shift_y_Q_reg_19_ ( .D(d_ff2_Y[19]), .CK(reg_shift_y_net3522529), .RN(n1926), .Q(d_ff3_sh_y_out[19]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_20_ ( .D(first_mux_Y[20]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1919), .Q(d_ff2_Y[20]) );
DFFRXLTS reg_shift_y_Q_reg_20_ ( .D(d_ff2_Y[20]), .CK(reg_shift_y_net3522529), .RN(n1926), .Q(d_ff3_sh_y_out[20]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_21_ ( .D(first_mux_Y[21]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1920), .Q(d_ff2_Y[21]) );
DFFRXLTS reg_shift_y_Q_reg_21_ ( .D(d_ff2_Y[21]), .CK(reg_shift_y_net3522529), .RN(n1923), .Q(d_ff3_sh_y_out[21]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_22_ ( .D(first_mux_Y[22]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1918), .Q(d_ff2_Y[22]) );
DFFRXLTS reg_shift_y_Q_reg_22_ ( .D(d_ff2_Y[22]), .CK(reg_shift_y_net3522529), .RN(n1918), .Q(d_ff3_sh_y_out[22]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_23_ ( .D(first_mux_Y[23]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1918), .Q(d_ff2_Y[23]), .QN(
n1803) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_28_ ( .D(first_mux_Y[28]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1906), .Q(d_ff2_Y[28]), .QN(
n1863) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_30_ ( .D(first_mux_Y[30]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1922), .Q(d_ff2_Y[30]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_23_ ( .D(first_mux_Z[23]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1905), .Q(d_ff2_Z[23]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_24_ ( .D(first_mux_Z[24]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1906), .Q(d_ff2_Z[24]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_25_ ( .D(first_mux_Z[25]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1922), .Q(d_ff2_Z[25]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_26_ ( .D(first_mux_Z[26]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1905), .Q(d_ff2_Z[26]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_27_ ( .D(first_mux_Z[27]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1906), .Q(d_ff2_Z[27]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_28_ ( .D(first_mux_Z[28]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1922), .Q(d_ff2_Z[28]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_29_ ( .D(first_mux_Z[29]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1923), .Q(d_ff2_Z[29]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_30_ ( .D(first_mux_Z[30]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1926), .Q(d_ff2_Z[30]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_6_ ( .D(first_mux_X[6]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1915), .Q(d_ff2_X[6]) );
DFFRXLTS reg_shift_x_Q_reg_6_ ( .D(d_ff2_X[6]), .CK(reg_shift_y_net3522529),
.RN(n1921), .Q(d_ff3_sh_x_out[6]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_10_ ( .D(first_mux_X[10]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1923), .Q(d_ff2_X[10]) );
DFFRXLTS reg_shift_x_Q_reg_10_ ( .D(d_ff2_X[10]), .CK(reg_shift_y_net3522529), .RN(n687), .Q(d_ff3_sh_x_out[10]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_11_ ( .D(first_mux_X[11]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1926), .Q(d_ff2_X[11]) );
DFFRXLTS reg_shift_x_Q_reg_11_ ( .D(d_ff2_X[11]), .CK(reg_shift_y_net3522529), .RN(n1926), .Q(d_ff3_sh_x_out[11]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_12_ ( .D(first_mux_X[12]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n687), .Q(d_ff2_X[12]) );
DFFRXLTS reg_shift_x_Q_reg_12_ ( .D(d_ff2_X[12]), .CK(reg_shift_y_net3522529), .RN(n688), .Q(d_ff3_sh_x_out[12]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_13_ ( .D(first_mux_X[13]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1924), .Q(d_ff2_X[13]) );
DFFRXLTS reg_shift_x_Q_reg_13_ ( .D(d_ff2_X[13]), .CK(reg_shift_y_net3522529), .RN(n1909), .Q(d_ff3_sh_x_out[13]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_14_ ( .D(first_mux_X[14]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1910), .Q(d_ff2_X[14]) );
DFFRXLTS reg_shift_x_Q_reg_14_ ( .D(d_ff2_X[14]), .CK(reg_shift_y_net3522529), .RN(n1911), .Q(d_ff3_sh_x_out[14]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_15_ ( .D(first_mux_X[15]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1934), .Q(d_ff2_X[15]) );
DFFRXLTS reg_shift_x_Q_reg_15_ ( .D(d_ff2_X[15]), .CK(reg_shift_y_net3522529), .RN(n1914), .Q(d_ff3_sh_x_out[15]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_16_ ( .D(first_mux_X[16]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1917), .Q(d_ff2_X[16]) );
DFFRXLTS reg_shift_x_Q_reg_16_ ( .D(d_ff2_X[16]), .CK(reg_shift_y_net3522529), .RN(n1924), .Q(d_ff3_sh_x_out[16]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_17_ ( .D(first_mux_X[17]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1909), .Q(d_ff2_X[17]) );
DFFRXLTS reg_shift_x_Q_reg_17_ ( .D(d_ff2_X[17]), .CK(reg_shift_y_net3522529), .RN(n1910), .Q(d_ff3_sh_x_out[17]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_18_ ( .D(first_mux_X[18]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1928), .Q(d_ff2_X[18]) );
DFFRXLTS reg_shift_x_Q_reg_18_ ( .D(d_ff2_X[18]), .CK(reg_shift_y_net3522529), .RN(n1931), .Q(d_ff3_sh_x_out[18]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_19_ ( .D(first_mux_X[19]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1930), .Q(d_ff2_X[19]) );
DFFRXLTS reg_shift_x_Q_reg_19_ ( .D(d_ff2_X[19]), .CK(reg_shift_y_net3522529), .RN(n1929), .Q(d_ff3_sh_x_out[19]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_20_ ( .D(first_mux_X[20]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1927), .Q(d_ff2_X[20]) );
DFFRXLTS reg_shift_x_Q_reg_20_ ( .D(d_ff2_X[20]), .CK(reg_shift_y_net3522529), .RN(n1925), .Q(d_ff3_sh_x_out[20]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_21_ ( .D(first_mux_X[21]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1933), .Q(d_ff2_X[21]) );
DFFRXLTS reg_shift_x_Q_reg_21_ ( .D(d_ff2_X[21]), .CK(reg_shift_y_net3522529), .RN(n1928), .Q(d_ff3_sh_x_out[21]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_22_ ( .D(first_mux_X[22]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1931), .Q(d_ff2_X[22]) );
DFFRXLTS reg_shift_x_Q_reg_22_ ( .D(d_ff2_X[22]), .CK(reg_shift_y_net3522529), .RN(n1930), .Q(d_ff3_sh_x_out[22]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_23_ ( .D(first_mux_X[23]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1921), .Q(d_ff2_X[23]), .QN(
n1804) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_28_ ( .D(first_mux_X[28]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1919), .Q(d_ff2_X[28]), .QN(
n1864) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_30_ ( .D(first_mux_X[30]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1919), .Q(d_ff2_X[30]) );
DFFRXLTS d_ff5_Q_reg_6_ ( .D(mux_sal[6]), .CK(d_ff5_net3522529), .RN(n1929),
.Q(sign_inv_out[6]) );
DFFRXLTS d_ff5_Q_reg_10_ ( .D(mux_sal[10]), .CK(d_ff5_net3522529), .RN(n1927), .Q(sign_inv_out[10]) );
DFFRXLTS d_ff5_Q_reg_11_ ( .D(mux_sal[11]), .CK(d_ff5_net3522529), .RN(n1925), .Q(sign_inv_out[11]) );
DFFRXLTS d_ff5_Q_reg_12_ ( .D(mux_sal[12]), .CK(d_ff5_net3522529), .RN(n1933), .Q(sign_inv_out[12]) );
DFFRXLTS d_ff5_Q_reg_13_ ( .D(mux_sal[13]), .CK(d_ff5_net3522529), .RN(n1928), .Q(sign_inv_out[13]) );
DFFRXLTS d_ff5_Q_reg_14_ ( .D(mux_sal[14]), .CK(d_ff5_net3522529), .RN(n1925), .Q(sign_inv_out[14]) );
DFFRXLTS d_ff5_Q_reg_15_ ( .D(mux_sal[15]), .CK(d_ff5_net3522529), .RN(n1933), .Q(sign_inv_out[15]) );
DFFRXLTS d_ff5_Q_reg_16_ ( .D(mux_sal[16]), .CK(d_ff5_net3522529), .RN(n1928), .Q(sign_inv_out[16]) );
DFFRXLTS d_ff5_Q_reg_17_ ( .D(mux_sal[17]), .CK(d_ff5_net3522529), .RN(n1931), .Q(sign_inv_out[17]) );
DFFRXLTS d_ff5_Q_reg_18_ ( .D(mux_sal[18]), .CK(d_ff5_net3522529), .RN(n1930), .Q(sign_inv_out[18]) );
DFFRXLTS d_ff5_Q_reg_19_ ( .D(mux_sal[19]), .CK(d_ff5_net3522529), .RN(n1931), .Q(sign_inv_out[19]) );
DFFRXLTS d_ff5_Q_reg_20_ ( .D(mux_sal[20]), .CK(d_ff5_net3522529), .RN(n1930), .Q(sign_inv_out[20]) );
DFFRXLTS d_ff5_Q_reg_21_ ( .D(mux_sal[21]), .CK(d_ff5_net3522529), .RN(n1929), .Q(sign_inv_out[21]) );
DFFRXLTS d_ff5_Q_reg_22_ ( .D(mux_sal[22]), .CK(d_ff5_net3522529), .RN(n1927), .Q(sign_inv_out[22]) );
DFFRXLTS d_ff5_Q_reg_23_ ( .D(mux_sal[23]), .CK(d_ff5_net3522529), .RN(n1925), .Q(sign_inv_out[23]) );
DFFRXLTS d_ff5_Q_reg_24_ ( .D(mux_sal[24]), .CK(d_ff5_net3522529), .RN(n1927), .Q(sign_inv_out[24]) );
DFFRXLTS d_ff5_Q_reg_25_ ( .D(mux_sal[25]), .CK(d_ff5_net3522529), .RN(n1925), .Q(sign_inv_out[25]) );
DFFRXLTS d_ff5_Q_reg_26_ ( .D(mux_sal[26]), .CK(d_ff5_net3522529), .RN(n1933), .Q(sign_inv_out[26]) );
DFFRXLTS d_ff5_Q_reg_27_ ( .D(mux_sal[27]), .CK(d_ff5_net3522529), .RN(n1928), .Q(sign_inv_out[27]) );
DFFRXLTS d_ff5_Q_reg_28_ ( .D(mux_sal[28]), .CK(d_ff5_net3522529), .RN(n1931), .Q(sign_inv_out[28]) );
DFFRXLTS d_ff5_Q_reg_29_ ( .D(mux_sal[29]), .CK(d_ff5_net3522529), .RN(n1928), .Q(sign_inv_out[29]) );
DFFRXLTS d_ff5_Q_reg_30_ ( .D(mux_sal[30]), .CK(d_ff5_net3522529), .RN(n1931), .Q(sign_inv_out[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_30_ ( .D(
add_subt_module_Oper_Start_in_module_intM[30]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1897),
.Q(add_subt_module_DMP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_29_ ( .D(
add_subt_module_Oper_Start_in_module_intM[29]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1897),
.Q(add_subt_module_DMP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_28_ ( .D(
add_subt_module_Oper_Start_in_module_intM[28]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1897),
.Q(add_subt_module_DMP[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_27_ ( .D(
add_subt_module_Oper_Start_in_module_intM[27]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1897),
.Q(add_subt_module_DMP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_26_ ( .D(
add_subt_module_Oper_Start_in_module_intM[26]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DMP[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_25_ ( .D(
add_subt_module_Oper_Start_in_module_intM[25]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DMP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_24_ ( .D(
add_subt_module_Oper_Start_in_module_intM[24]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DMP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_23_ ( .D(
add_subt_module_Oper_Start_in_module_intM[23]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DMP[23]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_30_ ( .D(
add_subt_module_Oper_Start_in_module_intm[30]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DmP[30]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_29_ ( .D(
add_subt_module_Oper_Start_in_module_intm[29]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DmP[29]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_28_ ( .D(
add_subt_module_Oper_Start_in_module_intm[28]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1896),
.Q(add_subt_module_DmP[28]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_27_ ( .D(
add_subt_module_Oper_Start_in_module_intm[27]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1895),
.Q(add_subt_module_DmP[27]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_26_ ( .D(
add_subt_module_Oper_Start_in_module_intm[26]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1895),
.Q(add_subt_module_DmP[26]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_25_ ( .D(
add_subt_module_Oper_Start_in_module_intm[25]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1895),
.Q(add_subt_module_DmP[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_24_ ( .D(
add_subt_module_Oper_Start_in_module_intm[24]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1895),
.Q(add_subt_module_DmP[24]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_23_ ( .D(
add_subt_module_Oper_Start_in_module_intm[23]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1894),
.Q(add_subt_module_DmP[23]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_2_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[2]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565),
.RN(n1897), .Q(add_subt_module_LZA_output[2]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_1_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[1]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565),
.RN(n1894), .Q(add_subt_module_LZA_output[1]) );
DFFRXLTS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_0_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[0]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565),
.RN(n1894), .Q(add_subt_module_LZA_output[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Xn_net3522529), .RN(n1930), .Q(d_ff_Xn[31]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_31_ ( .D(first_mux_X[31]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1929), .Q(d_ff2_X[31]) );
DFFRXLTS reg_shift_x_Q_reg_31_ ( .D(d_ff2_X[31]), .CK(reg_shift_y_net3522529), .RN(n1927), .Q(d_ff3_sh_x_out[31]) );
DFFRXLTS d_ff4_Yn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Yn_net3522529), .RN(n1925), .Q(d_ff_Yn[31]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_31_ ( .D(first_mux_Y[31]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1933), .Q(d_ff2_Y[31]) );
DFFRXLTS reg_shift_y_Q_reg_31_ ( .D(d_ff2_Y[31]), .CK(reg_shift_y_net3522529), .RN(n1904), .Q(d_ff3_sh_y_out[31]) );
DFFRXLTS d_ff5_Q_reg_31_ ( .D(mux_sal[31]), .CK(d_ff5_net3522529), .RN(n1912), .Q(data_output2_31_) );
DFFRXLTS d_ff4_Zn_Q_reg_31_ ( .D(result_add_subt[31]), .CK(
d_ff4_Zn_net3522529), .RN(n1932), .Q(d_ff_Zn[31]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_31_ ( .D(first_mux_Z[31]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1935), .Q(d_ff2_Z[31]) );
DFFRX4TS add_subt_module_XRegister_Q_reg_31_ ( .D(n636), .CK(
add_subt_module_YRegister_net3522547), .RN(n1900), .Q(
add_subt_module_intDX[31]), .QN(n1780) );
DFFRXLTS reg_sign_Q_reg_0_ ( .D(d_ff2_Z[31]), .CK(reg_shift_y_net3522529),
.RN(n1904), .Q(d_ff3_sign_out) );
DFFRXLTS d_ff4_Xn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Xn_net3522529), .RN(n1912), .Q(d_ff_Xn[2]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_2_ ( .D(first_mux_X[2]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1932), .Q(d_ff2_X[2]) );
DFFRXLTS reg_shift_x_Q_reg_2_ ( .D(d_ff2_X[2]), .CK(reg_shift_y_net3522529),
.RN(n1935), .Q(d_ff3_sh_x_out[2]) );
DFFRXLTS d_ff4_Yn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Yn_net3522529), .RN(n1904), .Q(d_ff_Yn[2]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_2_ ( .D(first_mux_Y[2]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1927), .Q(d_ff2_Y[2]) );
DFFRXLTS reg_shift_y_Q_reg_2_ ( .D(d_ff2_Y[2]), .CK(reg_shift_y_net3522529),
.RN(n1925), .Q(d_ff3_sh_y_out[2]) );
DFFRXLTS d_ff5_Q_reg_2_ ( .D(mux_sal[2]), .CK(d_ff5_net3522529), .RN(n1933),
.Q(sign_inv_out[2]) );
DFFRXLTS d_ff4_Zn_Q_reg_2_ ( .D(result_add_subt[2]), .CK(d_ff4_Zn_net3522529), .RN(n1931), .Q(d_ff_Zn[2]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_2_ ( .D(first_mux_Z[2]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1930), .Q(d_ff2_Z[2]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_2_ ( .D(
add_subt_module_Oper_Start_in_module_intm[2]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1885),
.Q(add_subt_module_DmP[2]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_2_ ( .D(
add_subt_module_Oper_Start_in_module_intM[2]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1015),
.Q(add_subt_module_DMP[2]) );
DFFRXLTS d_ff4_Xn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Xn_net3522529), .RN(n1929), .Q(d_ff_Xn[7]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_7_ ( .D(first_mux_X[7]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1928), .Q(d_ff2_X[7]) );
DFFRXLTS reg_shift_x_Q_reg_7_ ( .D(d_ff2_X[7]), .CK(reg_shift_y_net3522529),
.RN(n1927), .Q(d_ff3_sh_x_out[7]) );
DFFRXLTS d_ff4_Yn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Yn_net3522529), .RN(n1925), .Q(d_ff_Yn[7]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_7_ ( .D(first_mux_Y[7]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1910), .Q(d_ff2_Y[7]) );
DFFRXLTS reg_shift_y_Q_reg_7_ ( .D(d_ff2_Y[7]), .CK(reg_shift_y_net3522529),
.RN(n1911), .Q(d_ff3_sh_y_out[7]) );
DFFRXLTS d_ff5_Q_reg_7_ ( .D(mux_sal[7]), .CK(d_ff5_net3522529), .RN(n1934),
.Q(sign_inv_out[7]) );
DFFRXLTS d_ff4_Zn_Q_reg_7_ ( .D(result_add_subt[7]), .CK(d_ff4_Zn_net3522529), .RN(n1914), .Q(d_ff_Zn[7]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_7_ ( .D(first_mux_Z[7]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1917), .Q(d_ff2_Z[7]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_7_ ( .D(
add_subt_module_Oper_Start_in_module_intm[7]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1891),
.Q(add_subt_module_DmP[7]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_7_ ( .D(
add_subt_module_Oper_Start_in_module_intM[7]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1014),
.Q(add_subt_module_DMP[7]) );
DFFRXLTS d_ff4_Xn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Xn_net3522529), .RN(n1924), .Q(d_ff_Xn[3]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_3_ ( .D(first_mux_X[3]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1909), .Q(d_ff2_X[3]) );
DFFRXLTS reg_shift_x_Q_reg_3_ ( .D(d_ff2_X[3]), .CK(reg_shift_y_net3522529),
.RN(n1910), .Q(d_ff3_sh_x_out[3]) );
DFFRXLTS d_ff4_Yn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Yn_net3522529), .RN(n1911), .Q(d_ff_Yn[3]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_3_ ( .D(first_mux_Y[3]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1932), .Q(d_ff2_Y[3]) );
DFFRXLTS reg_shift_y_Q_reg_3_ ( .D(d_ff2_Y[3]), .CK(reg_shift_y_net3522529),
.RN(n1935), .Q(d_ff3_sh_y_out[3]) );
DFFRXLTS d_ff5_Q_reg_3_ ( .D(mux_sal[3]), .CK(d_ff5_net3522529), .RN(n1904),
.Q(sign_inv_out[3]) );
DFFRXLTS d_ff4_Zn_Q_reg_3_ ( .D(result_add_subt[3]), .CK(d_ff4_Zn_net3522529), .RN(n1912), .Q(d_ff_Zn[3]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_3_ ( .D(first_mux_Z[3]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1932), .Q(d_ff2_Z[3]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_3_ ( .D(
add_subt_module_Oper_Start_in_module_intm[3]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1890),
.Q(add_subt_module_DmP[3]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_3_ ( .D(
add_subt_module_Oper_Start_in_module_intM[3]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1888),
.Q(add_subt_module_DMP[3]) );
DFFRXLTS d_ff4_Xn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Xn_net3522529), .RN(n1935), .Q(d_ff_Xn[8]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_8_ ( .D(first_mux_X[8]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1904), .Q(d_ff2_X[8]) );
DFFRXLTS reg_shift_x_Q_reg_8_ ( .D(d_ff2_X[8]), .CK(reg_shift_y_net3522529),
.RN(n1912), .Q(d_ff3_sh_x_out[8]) );
DFFRXLTS d_ff4_Yn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Yn_net3522529), .RN(n1932), .Q(d_ff_Yn[8]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_8_ ( .D(first_mux_Y[8]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1937), .Q(d_ff2_Y[8]) );
DFFRXLTS reg_shift_y_Q_reg_8_ ( .D(d_ff2_Y[8]), .CK(reg_shift_y_net3522529),
.RN(n1938), .Q(d_ff3_sh_y_out[8]) );
DFFRXLTS d_ff5_Q_reg_8_ ( .D(mux_sal[8]), .CK(d_ff5_net3522529), .RN(n1939),
.Q(sign_inv_out[8]) );
DFFRXLTS d_ff4_Zn_Q_reg_8_ ( .D(result_add_subt[8]), .CK(d_ff4_Zn_net3522529), .RN(n704), .Q(d_ff_Zn[8]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_8_ ( .D(first_mux_Z[8]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1936), .Q(d_ff2_Z[8]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_8_ ( .D(
add_subt_module_Oper_Start_in_module_intm[8]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1886),
.Q(add_subt_module_DmP[8]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_8_ ( .D(
add_subt_module_Oper_Start_in_module_intM[8]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1891),
.Q(add_subt_module_DMP[8]) );
DFFRXLTS d_ff4_Xn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Xn_net3522529), .RN(n687), .Q(d_ff_Xn[0]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_0_ ( .D(first_mux_X[0]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1937), .Q(d_ff2_X[0]) );
DFFRXLTS reg_shift_x_Q_reg_0_ ( .D(d_ff2_X[0]), .CK(reg_shift_y_net3522529),
.RN(n1938), .Q(d_ff3_sh_x_out[0]) );
DFFRXLTS d_ff4_Yn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Yn_net3522529), .RN(n1939), .Q(d_ff_Yn[0]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_0_ ( .D(first_mux_Y[0]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1936), .Q(d_ff2_Y[0]) );
DFFRXLTS reg_shift_y_Q_reg_0_ ( .D(d_ff2_Y[0]), .CK(reg_shift_y_net3522529),
.RN(n687), .Q(d_ff3_sh_y_out[0]) );
DFFRXLTS d_ff5_Q_reg_0_ ( .D(mux_sal[0]), .CK(d_ff5_net3522529), .RN(n1937),
.Q(sign_inv_out[0]) );
DFFRXLTS d_ff4_Zn_Q_reg_0_ ( .D(result_add_subt[0]), .CK(d_ff4_Zn_net3522529), .RN(n1938), .Q(d_ff_Zn[0]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_0_ ( .D(first_mux_Z[0]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1939), .Q(d_ff2_Z[0]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_0_ ( .D(
add_subt_module_Oper_Start_in_module_intm[0]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1889),
.Q(add_subt_module_DmP[0]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_0_ ( .D(
add_subt_module_Oper_Start_in_module_intM[0]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1887),
.Q(add_subt_module_DMP[0]) );
DFFRXLTS d_ff4_Xn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Xn_net3522529), .RN(n704), .Q(d_ff_Xn[4]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_4_ ( .D(first_mux_X[4]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1936), .Q(d_ff2_X[4]) );
DFFRXLTS reg_shift_x_Q_reg_4_ ( .D(d_ff2_X[4]), .CK(reg_shift_y_net3522529),
.RN(n688), .Q(d_ff3_sh_x_out[4]) );
DFFRXLTS d_ff4_Yn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Yn_net3522529), .RN(n1937), .Q(d_ff_Yn[4]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_4_ ( .D(first_mux_Y[4]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1939), .Q(d_ff2_Y[4]) );
DFFRXLTS reg_shift_y_Q_reg_4_ ( .D(d_ff2_Y[4]), .CK(reg_shift_y_net3522529),
.RN(n704), .Q(d_ff3_sh_y_out[4]) );
DFFRXLTS d_ff5_Q_reg_4_ ( .D(mux_sal[4]), .CK(d_ff5_net3522529), .RN(n1936),
.Q(sign_inv_out[4]) );
DFFRXLTS d_ff4_Zn_Q_reg_4_ ( .D(result_add_subt[4]), .CK(d_ff4_Zn_net3522529), .RN(n1921), .Q(d_ff_Zn[4]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_4_ ( .D(first_mux_Z[4]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1937), .Q(d_ff2_Z[4]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_4_ ( .D(
add_subt_module_Oper_Start_in_module_intm[4]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1891),
.Q(add_subt_module_DmP[4]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_4_ ( .D(
add_subt_module_Oper_Start_in_module_intM[4]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1888),
.Q(add_subt_module_DMP[4]) );
DFFRXLTS d_ff4_Xn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Xn_net3522529), .RN(n1938), .Q(d_ff_Xn[1]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_1_ ( .D(first_mux_X[1]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1939), .Q(d_ff2_X[1]) );
DFFRXLTS reg_shift_x_Q_reg_1_ ( .D(d_ff2_X[1]), .CK(reg_shift_y_net3522529),
.RN(n704), .Q(d_ff3_sh_x_out[1]) );
DFFRXLTS d_ff4_Yn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Yn_net3522529), .RN(n1936), .Q(d_ff_Yn[1]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_1_ ( .D(first_mux_Y[1]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1937), .Q(d_ff2_Y[1]) );
DFFRXLTS reg_shift_y_Q_reg_1_ ( .D(d_ff2_Y[1]), .CK(reg_shift_y_net3522529),
.RN(n1938), .Q(d_ff3_sh_y_out[1]) );
DFFRXLTS d_ff5_Q_reg_1_ ( .D(mux_sal[1]), .CK(d_ff5_net3522529), .RN(n1939),
.Q(sign_inv_out[1]) );
DFFRXLTS d_ff4_Zn_Q_reg_1_ ( .D(result_add_subt[1]), .CK(d_ff4_Zn_net3522529), .RN(n704), .Q(d_ff_Zn[1]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_1_ ( .D(first_mux_Z[1]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1936), .Q(d_ff2_Z[1]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_1_ ( .D(
add_subt_module_Oper_Start_in_module_intm[1]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1890),
.Q(add_subt_module_DmP[1]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_1_ ( .D(
add_subt_module_Oper_Start_in_module_intM[1]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1886),
.Q(add_subt_module_DMP[1]) );
DFFRXLTS d_ff4_Xn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Xn_net3522529), .RN(n1921), .Q(d_ff_Xn[5]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_5_ ( .D(first_mux_X[5]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1937), .Q(d_ff2_X[5]) );
DFFRXLTS reg_shift_x_Q_reg_5_ ( .D(d_ff2_X[5]), .CK(reg_shift_y_net3522529),
.RN(n1938), .Q(d_ff3_sh_x_out[5]) );
DFFRXLTS d_ff4_Yn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Yn_net3522529), .RN(n1939), .Q(d_ff_Yn[5]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_5_ ( .D(first_mux_Y[5]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1940), .Q(d_ff2_Y[5]) );
DFFRXLTS reg_shift_y_Q_reg_5_ ( .D(d_ff2_Y[5]), .CK(reg_shift_y_net3522529),
.RN(n1940), .Q(d_ff3_sh_y_out[5]) );
DFFRXLTS d_ff5_Q_reg_5_ ( .D(mux_sal[5]), .CK(d_ff5_net3522529), .RN(n1940),
.Q(sign_inv_out[5]) );
DFFRXLTS d_ff4_Zn_Q_reg_5_ ( .D(result_add_subt[5]), .CK(d_ff4_Zn_net3522529), .RN(n1937), .Q(d_ff_Zn[5]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_5_ ( .D(first_mux_Z[5]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1938), .Q(d_ff2_Z[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_5_ ( .D(
add_subt_module_Oper_Start_in_module_intm[5]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1886),
.Q(add_subt_module_DmP[5]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_5_ ( .D(
add_subt_module_Oper_Start_in_module_intM[5]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1889),
.Q(add_subt_module_DMP[5]) );
DFFRXLTS d_ff4_Xn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Xn_net3522529), .RN(n1939), .Q(d_ff_Xn[9]) );
DFFRXLTS reg_val_muxX_2stage_Q_reg_9_ ( .D(first_mux_X[9]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1937), .Q(d_ff2_X[9]) );
DFFRXLTS reg_shift_x_Q_reg_9_ ( .D(d_ff2_X[9]), .CK(reg_shift_y_net3522529),
.RN(n1938), .Q(d_ff3_sh_x_out[9]) );
DFFRXLTS d_ff4_Yn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Yn_net3522529), .RN(n1939), .Q(d_ff_Yn[9]) );
DFFRXLTS reg_val_muxY_2stage_Q_reg_9_ ( .D(first_mux_Y[9]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1923), .Q(d_ff2_Y[9]) );
DFFRXLTS reg_shift_y_Q_reg_9_ ( .D(d_ff2_Y[9]), .CK(reg_shift_y_net3522529),
.RN(n1937), .Q(d_ff3_sh_y_out[9]) );
DFFRXLTS d_ff5_Q_reg_9_ ( .D(mux_sal[9]), .CK(d_ff5_net3522529), .RN(n1938),
.Q(sign_inv_out[9]) );
DFFRXLTS d_ff4_Zn_Q_reg_9_ ( .D(result_add_subt[9]), .CK(d_ff4_Zn_net3522529), .RN(n1939), .Q(d_ff_Zn[9]) );
DFFRXLTS reg_val_muxZ_2stage_Q_reg_9_ ( .D(first_mux_Z[9]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n704), .Q(d_ff2_Z[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_9_ ( .D(
add_subt_module_Oper_Start_in_module_intm[9]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1892),
.Q(add_subt_module_DmP[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_9_ ( .D(
add_subt_module_Oper_Start_in_module_intM[9]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1888),
.Q(add_subt_module_DMP[9]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_mRegister_Q_reg_12_ ( .D(
add_subt_module_Oper_Start_in_module_intm[12]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1890),
.Q(add_subt_module_DmP[12]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_12_ ( .D(
add_subt_module_Oper_Start_in_module_intM[12]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1014),
.Q(add_subt_module_DMP[12]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_10_ ( .D(
add_subt_module_Oper_Start_in_module_intM[10]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1889),
.Q(add_subt_module_DMP[10]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_14_ ( .D(
add_subt_module_Oper_Start_in_module_intM[14]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1892),
.Q(add_subt_module_DMP[14]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_11_ ( .D(
add_subt_module_Oper_Start_in_module_intM[11]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1902),
.Q(add_subt_module_DMP[11]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_17_ ( .D(
add_subt_module_Oper_Start_in_module_intM[17]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1886),
.Q(add_subt_module_DMP[17]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_16_ ( .D(
add_subt_module_Oper_Start_in_module_intM[16]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1887),
.Q(add_subt_module_DMP[16]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_20_ ( .D(
add_subt_module_Oper_Start_in_module_intM[20]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1893),
.Q(add_subt_module_DMP[20]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_13_ ( .D(
add_subt_module_Oper_Start_in_module_intM[13]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1891),
.Q(add_subt_module_DMP[13]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_6_ ( .D(
add_subt_module_Oper_Start_in_module_intM[6]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1902),
.Q(add_subt_module_DMP[6]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_21_ ( .D(
add_subt_module_Oper_Start_in_module_intM[21]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1893),
.Q(add_subt_module_DMP[21]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_19_ ( .D(
add_subt_module_Oper_Start_in_module_intM[19]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1893),
.Q(add_subt_module_DMP[19]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_18_ ( .D(
add_subt_module_Oper_Start_in_module_intM[18]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1015),
.Q(add_subt_module_DMP[18]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_15_ ( .D(
add_subt_module_Oper_Start_in_module_intM[15]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1890),
.Q(add_subt_module_DMP[15]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_MRegister_Q_reg_22_ ( .D(
add_subt_module_Oper_Start_in_module_intM[22]), .CK(
add_subt_module_Oper_Start_in_module_MRegister_net3522619), .RN(n1893),
.Q(add_subt_module_DMP[22]) );
DFFRX4TS add_subt_module_Sel_D_Q_reg_0_ ( .D(n595), .CK(
add_subt_module_FS_Module_net3522637), .RN(n580), .Q(
add_subt_module_FSM_selector_D) );
DFFRXLTS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_25_ ( .D(
n1988), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1893), .Q(add_subt_module_Sgf_normalized_result[25]) );
DFFRXLTS add_subt_module_Oper_Start_in_module_SignRegister_Q_reg_0_ ( .D(
n1985), .CK(add_subt_module_Oper_Start_in_module_MRegister_net3522619),
.RN(n1899), .Q(add_subt_module_sign_final_result), .QN(n1777) );
SNPS_CLOCK_GATE_HIGH_CORDIC_Arch2_W32_EW8_SW23_SWR26_EWR5_1 clk_gate_reg_ch_mux_2_Q_reg (
.CLK(clk), .EN(n1983), .ENCLK(n1981), .TE(1'b0) );
DFFSX2TS R_0 ( .D(n1875), .CK(add_subt_module_YRegister_net3522547), .SN(
n1899), .Q(n1951) );
DFFRXLTS reg_LUT_Q_reg_27_ ( .D(1'b1), .CK(reg_shift_y_net3522529), .RN(
n1936), .Q(d_ff3_LUT_out[27]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Underflow_Q_reg_0_ ( .D(n596),
.CK(add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(
n1885), .Q(underflow_flag), .QN(n1874) );
DFFRX2TS add_subt_module_YRegister_Q_reg_23_ ( .D(n660), .CK(
add_subt_module_YRegister_net3522547), .RN(n1883), .Q(
add_subt_module_intDY[23]), .QN(n1847) );
DFFRX2TS add_subt_module_YRegister_Q_reg_15_ ( .D(n652), .CK(
add_subt_module_YRegister_net3522547), .RN(n1883), .Q(
add_subt_module_intDY[15]), .QN(n1843) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_25_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]),
.CK(clk), .RN(n1894), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .QN(
n1824) );
DFFRX2TS add_subt_module_YRegister_Q_reg_9_ ( .D(n646), .CK(
add_subt_module_YRegister_net3522547), .RN(n1888), .Q(
add_subt_module_intDY[9]), .QN(n1823) );
DFFRX2TS add_subt_module_YRegister_Q_reg_7_ ( .D(n644), .CK(
add_subt_module_YRegister_net3522547), .RN(n1900), .Q(
add_subt_module_intDY[7]), .QN(n1822) );
DFFRX2TS add_subt_module_YRegister_Q_reg_2_ ( .D(n639), .CK(
add_subt_module_YRegister_net3522547), .RN(n1901), .Q(
add_subt_module_intDY[2]), .QN(n1821) );
DFFRX2TS add_subt_module_YRegister_Q_reg_4_ ( .D(n641), .CK(
add_subt_module_YRegister_net3522547), .RN(n1901), .Q(
add_subt_module_intDY[4]), .QN(n1820) );
DFFRX2TS add_subt_module_YRegister_Q_reg_5_ ( .D(n642), .CK(
add_subt_module_YRegister_net3522547), .RN(n1901), .Q(
add_subt_module_intDY[5]), .QN(n1819) );
DFFRX2TS add_subt_module_XRegister_Q_reg_7_ ( .D(n612), .CK(
add_subt_module_YRegister_net3522547), .RN(n1900), .Q(
add_subt_module_intDX[7]), .QN(n1813) );
DFFRX2TS add_subt_module_XRegister_Q_reg_16_ ( .D(n621), .CK(
add_subt_module_YRegister_net3522547), .RN(n1878), .Q(
add_subt_module_intDX[16]), .QN(n1807) );
DFFRX2TS add_subt_module_XRegister_Q_reg_5_ ( .D(n610), .CK(
add_subt_module_YRegister_net3522547), .RN(n1901), .Q(
add_subt_module_intDX[5]), .QN(n1806) );
DFFRX2TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_4_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[4]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1897), .Q(add_subt_module_exp_oper_result[4]), .QN(n1796) );
DFFRX2TS add_subt_module_YRegister_Q_reg_12_ ( .D(n649), .CK(
add_subt_module_YRegister_net3522547), .RN(n1884), .Q(
add_subt_module_intDY[12]), .QN(n1787) );
DFFRX2TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_4_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[4]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565),
.RN(n1886), .Q(add_subt_module_LZA_output[4]), .QN(n1783) );
DFFRX2TS add_subt_module_Sel_C_Q_reg_0_ ( .D(n593), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n580), .Q(add_subt_module_FSM_selector_C), .QN(n1779) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_14_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1895), .Q(add_subt_module_Add_Subt_result[14]), .QN(n1773) );
DFFRX2TS add_subt_module_YRegister_Q_reg_30_ ( .D(n667), .CK(
add_subt_module_YRegister_net3522547), .RN(n1882), .Q(
add_subt_module_intDY[30]), .QN(n1770) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_23_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]),
.CK(clk), .RN(n1892), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .QN(
n1768) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_21_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]),
.CK(clk), .RN(n1885), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .QN(
n1767) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_20_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]),
.CK(clk), .RN(n1891), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .QN(
n1766) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_18_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]),
.CK(clk), .RN(n1890), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .QN(
n1765) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_19_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]),
.CK(clk), .RN(n1015), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .QN(
n1764) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_22_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]),
.CK(clk), .RN(n1887), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .QN(
n1763) );
DFFRX2TS cordic_FSM_state_reg_reg_1_ ( .D(cordic_FSM_state_next_1_), .CK(clk), .RN(n1882), .Q(cordic_FSM_state_reg[1]), .QN(n1762) );
DFFRX2TS add_subt_module_Sel_B_Q_reg_1_ ( .D(n597), .CK(
add_subt_module_FS_Module_net3522637), .RN(n580), .Q(
add_subt_module_FSM_selector_B[1]), .QN(n1749) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_5_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1899), .Q(add_subt_module_Add_Subt_result[5]), .QN(n1747) );
DFFRX1TS add_subt_module_Leading_Zero_Detector_Module_Output_Reg_Q_reg_3_ (
.D(add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[3]), .CK(
add_subt_module_Leading_Zero_Detector_Module_Output_Reg_net3522565),
.RN(n1885), .Q(add_subt_module_LZA_output[3]), .QN(n1744) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_7_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]),
.CK(clk), .RN(n1887), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .QN(
n1831) );
DFFRXLTS d_ff5_data_out_Q_reg_6_ ( .D(sign_inv_out[6]), .CK(
d_ff5_data_out_net3522529), .RN(n1931), .Q(data_output[6]) );
DFFRXLTS d_ff5_data_out_Q_reg_10_ ( .D(sign_inv_out[10]), .CK(
d_ff5_data_out_net3522529), .RN(n1930), .Q(data_output[10]) );
DFFRXLTS d_ff5_data_out_Q_reg_11_ ( .D(sign_inv_out[11]), .CK(
d_ff5_data_out_net3522529), .RN(n1929), .Q(data_output[11]) );
DFFRXLTS d_ff5_data_out_Q_reg_12_ ( .D(sign_inv_out[12]), .CK(
d_ff5_data_out_net3522529), .RN(n1927), .Q(data_output[12]) );
DFFRXLTS d_ff5_data_out_Q_reg_13_ ( .D(sign_inv_out[13]), .CK(
d_ff5_data_out_net3522529), .RN(n1929), .Q(data_output[13]) );
DFFRXLTS d_ff5_data_out_Q_reg_14_ ( .D(sign_inv_out[14]), .CK(
d_ff5_data_out_net3522529), .RN(n1927), .Q(data_output[14]) );
DFFRXLTS d_ff5_data_out_Q_reg_15_ ( .D(sign_inv_out[15]), .CK(
d_ff5_data_out_net3522529), .RN(n1925), .Q(data_output[15]) );
DFFRXLTS d_ff5_data_out_Q_reg_16_ ( .D(sign_inv_out[16]), .CK(
d_ff5_data_out_net3522529), .RN(n1933), .Q(data_output[16]) );
DFFRXLTS d_ff5_data_out_Q_reg_17_ ( .D(sign_inv_out[17]), .CK(
d_ff5_data_out_net3522529), .RN(n1928), .Q(data_output[17]) );
DFFRXLTS d_ff5_data_out_Q_reg_18_ ( .D(sign_inv_out[18]), .CK(
d_ff5_data_out_net3522529), .RN(n1933), .Q(data_output[18]) );
DFFRXLTS d_ff5_data_out_Q_reg_19_ ( .D(sign_inv_out[19]), .CK(
d_ff5_data_out_net3522529), .RN(n1928), .Q(data_output[19]) );
DFFRXLTS d_ff5_data_out_Q_reg_20_ ( .D(sign_inv_out[20]), .CK(
d_ff5_data_out_net3522529), .RN(n1931), .Q(data_output[20]) );
DFFRXLTS d_ff5_data_out_Q_reg_21_ ( .D(sign_inv_out[21]), .CK(
d_ff5_data_out_net3522529), .RN(n1930), .Q(data_output[21]) );
DFFRXLTS d_ff5_data_out_Q_reg_22_ ( .D(sign_inv_out[22]), .CK(
d_ff5_data_out_net3522529), .RN(n1929), .Q(data_output[22]) );
DFFRXLTS d_ff5_data_out_Q_reg_23_ ( .D(sign_inv_out[23]), .CK(
d_ff5_data_out_net3522529), .RN(n1930), .Q(data_output[23]) );
DFFRXLTS d_ff5_data_out_Q_reg_24_ ( .D(sign_inv_out[24]), .CK(
d_ff5_data_out_net3522529), .RN(n1929), .Q(data_output[24]) );
DFFRXLTS d_ff5_data_out_Q_reg_25_ ( .D(sign_inv_out[25]), .CK(
d_ff5_data_out_net3522529), .RN(n1927), .Q(data_output[25]) );
DFFRXLTS d_ff5_data_out_Q_reg_26_ ( .D(sign_inv_out[26]), .CK(
d_ff5_data_out_net3522529), .RN(n1925), .Q(data_output[26]) );
DFFRXLTS d_ff5_data_out_Q_reg_27_ ( .D(sign_inv_out[27]), .CK(
d_ff5_data_out_net3522529), .RN(n1933), .Q(data_output[27]) );
DFFRXLTS d_ff5_data_out_Q_reg_28_ ( .D(sign_inv_out[28]), .CK(
d_ff5_data_out_net3522529), .RN(n1931), .Q(data_output[28]) );
DFFRXLTS d_ff5_data_out_Q_reg_29_ ( .D(sign_inv_out[29]), .CK(
d_ff5_data_out_net3522529), .RN(n1930), .Q(data_output[29]) );
DFFRXLTS d_ff5_data_out_Q_reg_30_ ( .D(sign_inv_out[30]), .CK(
d_ff5_data_out_net3522529), .RN(n1929), .Q(data_output[30]) );
DFFRXLTS d_ff5_data_out_Q_reg_31_ ( .D(sign_inv_out[31]), .CK(
d_ff5_data_out_net3522529), .RN(n1912), .Q(data_output[31]) );
DFFRXLTS d_ff5_data_out_Q_reg_2_ ( .D(sign_inv_out[2]), .CK(
d_ff5_data_out_net3522529), .RN(n1933), .Q(data_output[2]) );
DFFRXLTS d_ff5_data_out_Q_reg_7_ ( .D(sign_inv_out[7]), .CK(
d_ff5_data_out_net3522529), .RN(n1934), .Q(data_output[7]) );
DFFRXLTS d_ff5_data_out_Q_reg_3_ ( .D(sign_inv_out[3]), .CK(
d_ff5_data_out_net3522529), .RN(n1935), .Q(data_output[3]) );
DFFRXLTS d_ff5_data_out_Q_reg_8_ ( .D(sign_inv_out[8]), .CK(
d_ff5_data_out_net3522529), .RN(n704), .Q(data_output[8]) );
DFFRXLTS d_ff5_data_out_Q_reg_0_ ( .D(sign_inv_out[0]), .CK(
d_ff5_data_out_net3522529), .RN(n1938), .Q(data_output[0]) );
DFFRXLTS d_ff5_data_out_Q_reg_4_ ( .D(sign_inv_out[4]), .CK(
d_ff5_data_out_net3522529), .RN(n1918), .Q(data_output[4]) );
DFFRXLTS d_ff5_data_out_Q_reg_1_ ( .D(sign_inv_out[1]), .CK(
d_ff5_data_out_net3522529), .RN(n704), .Q(data_output[1]) );
DFFRXLTS d_ff5_data_out_Q_reg_5_ ( .D(sign_inv_out[5]), .CK(
d_ff5_data_out_net3522529), .RN(n1936), .Q(data_output[5]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_16_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]),
.CK(clk), .RN(n1877), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .QN(
n1816) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_15_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]),
.CK(clk), .RN(n1878), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .QN(
n1818) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_13_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]),
.CK(clk), .RN(n1880), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .QN(
n1817) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_12_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]),
.CK(clk), .RN(n1879), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .QN(
n1829) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_14_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]),
.CK(clk), .RN(n1889), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .QN(
n1809) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_11_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]),
.CK(clk), .RN(n1880), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .QN(
n1827) );
DFFSX2TS add_subt_module_XRegister_Q_reg_28_ ( .D(n1961), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1802) );
DFFRXLTS d_ff5_data_out_Q_reg_9_ ( .D(sign_inv_out[9]), .CK(
d_ff5_data_out_net3522529), .RN(n1919), .Q(data_output[9]) );
DFFSX4TS cont_iter_count_reg_1_ ( .D(n1743), .CK(cont_iter_net3522673), .SN(
n1905), .Q(intadd_391_B_0_), .QN(cont_iter_out[1]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_26_ ( .D(n1954), .CK(
add_subt_module_YRegister_net3522547), .SN(n1882), .Q(n1846), .QN(
add_subt_module_intDY[26]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_25_ ( .D(n1955), .CK(
add_subt_module_YRegister_net3522547), .SN(n1882), .Q(n1845), .QN(
add_subt_module_intDY[25]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_24_ ( .D(n1956), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1838), .QN(
add_subt_module_intDY[24]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_0_ ( .D(
n724), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1898), .Q(n1853), .QN(add_subt_module_Add_Subt_result[0]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_6_ ( .D(n1947), .CK(
add_subt_module_YRegister_net3522547), .SN(n1900), .Q(n1746), .QN(
add_subt_module_intDX[6]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_1_ ( .D(n1941), .CK(
add_subt_module_YRegister_net3522547), .SN(n1901), .Q(n1800), .QN(
add_subt_module_intDX[1]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_21_ ( .D(n1957), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1835), .QN(
add_subt_module_intDY[21]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_10_ ( .D(n1958), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1849), .QN(
add_subt_module_intDY[10]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_8_ ( .D(n1950), .CK(
add_subt_module_YRegister_net3522547), .SN(n1900), .Q(n1850), .QN(
add_subt_module_intDY[8]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_6_ ( .D(n1948), .CK(
add_subt_module_YRegister_net3522547), .SN(n1900), .Q(n1848), .QN(
add_subt_module_intDY[6]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_0_ ( .D(n1943), .CK(
add_subt_module_YRegister_net3522547), .SN(n1888), .Q(n1852), .QN(
add_subt_module_intDY[0]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_30_ ( .D(n1959), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1801), .QN(
add_subt_module_intDX[30]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_26_ ( .D(n1963), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1755), .QN(
add_subt_module_intDX[26]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_25_ ( .D(n1964), .CK(
add_subt_module_YRegister_net3522547), .SN(n1885), .Q(n1794), .QN(
add_subt_module_intDX[25]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_24_ ( .D(n1965), .CK(
add_subt_module_YRegister_net3522547), .SN(n1885), .Q(n1754), .QN(
add_subt_module_intDX[24]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_23_ ( .D(n1966), .CK(
add_subt_module_YRegister_net3522547), .SN(n1885), .Q(n1795), .QN(
add_subt_module_intDX[23]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_22_ ( .D(n1967), .CK(
add_subt_module_YRegister_net3522547), .SN(n1876), .Q(n1753), .QN(
add_subt_module_intDX[22]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_21_ ( .D(n1968), .CK(
add_subt_module_YRegister_net3522547), .SN(n1877), .Q(n1792), .QN(
add_subt_module_intDX[21]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_20_ ( .D(n1969), .CK(
add_subt_module_YRegister_net3522547), .SN(n1878), .Q(n1752), .QN(
add_subt_module_intDX[20]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_19_ ( .D(n1970), .CK(
add_subt_module_YRegister_net3522547), .SN(n1877), .Q(n1789), .QN(
add_subt_module_intDX[19]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_18_ ( .D(n1971), .CK(
add_subt_module_YRegister_net3522547), .SN(n1876), .Q(n1751), .QN(
add_subt_module_intDX[18]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_17_ ( .D(n1972), .CK(
add_subt_module_YRegister_net3522547), .SN(n1879), .Q(n1788), .QN(
add_subt_module_intDX[17]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_15_ ( .D(n1973), .CK(
add_subt_module_YRegister_net3522547), .SN(n1876), .Q(n1791), .QN(
add_subt_module_intDX[15]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_14_ ( .D(n1974), .CK(
add_subt_module_YRegister_net3522547), .SN(n1880), .Q(n1750), .QN(
add_subt_module_intDX[14]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_13_ ( .D(n1975), .CK(
add_subt_module_YRegister_net3522547), .SN(n1878), .Q(n1790), .QN(
add_subt_module_intDX[13]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_12_ ( .D(n1976), .CK(
add_subt_module_YRegister_net3522547), .SN(n1880), .Q(n1833), .QN(
add_subt_module_intDX[12]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_11_ ( .D(n1977), .CK(
add_subt_module_YRegister_net3522547), .SN(n1879), .Q(n1782), .QN(
add_subt_module_intDX[11]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_10_ ( .D(n1978), .CK(
add_subt_module_YRegister_net3522547), .SN(n1880), .Q(n1760), .QN(
add_subt_module_intDX[10]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_9_ ( .D(n1979), .CK(
add_subt_module_YRegister_net3522547), .SN(n1891), .Q(n1758), .QN(
add_subt_module_intDX[9]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_8_ ( .D(n1949), .CK(
add_subt_module_YRegister_net3522547), .SN(n1900), .Q(n1799), .QN(
add_subt_module_intDX[8]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_4_ ( .D(n1946), .CK(
add_subt_module_YRegister_net3522547), .SN(n1901), .Q(n1761), .QN(
add_subt_module_intDX[4]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_3_ ( .D(n1944), .CK(
add_subt_module_YRegister_net3522547), .SN(n1889), .Q(n1798), .QN(
add_subt_module_intDX[3]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_2_ ( .D(n1945), .CK(
add_subt_module_YRegister_net3522547), .SN(n1901), .Q(n1759), .QN(
add_subt_module_intDX[2]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_0_ ( .D(n1942), .CK(
add_subt_module_YRegister_net3522547), .SN(n1901), .Q(n1769), .QN(
add_subt_module_intDX[0]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_29_ ( .D(n1960), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1793), .QN(
add_subt_module_intDX[29]) );
DFFSX2TS add_subt_module_XRegister_Q_reg_27_ ( .D(n1962), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1756), .QN(
add_subt_module_intDX[27]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_22_ ( .D(n1742), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1776), .QN(
add_subt_module_intDY[22]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_19_ ( .D(n1741), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1774), .QN(
add_subt_module_intDY[19]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_18_ ( .D(n1740), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1841), .QN(
add_subt_module_intDY[18]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_16_ ( .D(n1739), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1832), .QN(
add_subt_module_intDY[16]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_29_ ( .D(n916), .CK(
add_subt_module_YRegister_net3522547), .SN(n1882), .Q(n1844), .QN(
add_subt_module_intDY[29]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_28_ ( .D(n913), .CK(
add_subt_module_YRegister_net3522547), .SN(n1882), .Q(n1837), .QN(
add_subt_module_intDY[28]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_27_ ( .D(n911), .CK(
add_subt_module_YRegister_net3522547), .SN(n1882), .Q(n1839), .QN(
add_subt_module_intDY[27]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_20_ ( .D(n909), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1836), .QN(
add_subt_module_intDY[20]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_17_ ( .D(n907), .CK(
add_subt_module_YRegister_net3522547), .SN(n1883), .Q(n1842), .QN(
add_subt_module_intDY[17]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_14_ ( .D(n1738), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1775), .QN(
add_subt_module_intDY[14]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_13_ ( .D(n1737), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1834), .QN(
add_subt_module_intDY[13]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_11_ ( .D(n1736), .CK(
add_subt_module_YRegister_net3522547), .SN(n1884), .Q(n1840), .QN(
add_subt_module_intDY[11]) );
DFFSX2TS add_subt_module_YRegister_Q_reg_3_ ( .D(n1735), .CK(
add_subt_module_YRegister_net3522547), .SN(n1014), .Q(n1851), .QN(
add_subt_module_intDY[3]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_1_ ( .D(
n717), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1898), .Q(n1815), .QN(add_subt_module_Add_Subt_result[1]) );
DFFSX2TS cont_iter_count_reg_3_ ( .D(n1734), .CK(cont_iter_net3522673), .SN(
n1922), .Q(n1781), .QN(cont_iter_out[3]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_2_ ( .D(
n718), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1898), .Q(n1825), .QN(add_subt_module_Add_Subt_result[2]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_15_ ( .D(
n719), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1895), .Q(n1854), .QN(add_subt_module_Add_Subt_result[15]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_7_ ( .D(
n709), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1899), .Q(n1855), .QN(add_subt_module_Add_Subt_result[7]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_17_ ( .D(
n720), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1895), .Q(n1785), .QN(add_subt_module_Add_Subt_result[17]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_8_ ( .D(
n710), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1894), .Q(n1826), .QN(add_subt_module_Add_Subt_result[8]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_9_ ( .D(
n711), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1894), .Q(n1772), .QN(add_subt_module_Add_Subt_result[9]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_19_ ( .D(
n723), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1891), .Q(n1830), .QN(add_subt_module_Add_Subt_result[19]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_11_ ( .D(
n707), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1898), .Q(n1797), .QN(add_subt_module_Add_Subt_result[11]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_10_ ( .D(
n708), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1899), .Q(n1805), .QN(add_subt_module_Add_Subt_result[10]) );
DFFSX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_12_ ( .D(
n712), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .SN(
n1897), .Q(n1811), .QN(add_subt_module_Add_Subt_result[12]) );
DFFSX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_10_ (
.D(n742), .CK(clk), .SN(n1893), .Q(n1828), .QN(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_24_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]),
.CK(clk), .RN(n1894), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]) );
DFFRX2TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_17_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]),
.CK(clk), .RN(n1894), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]) );
DFFRX2TS cont_var_count_reg_0_ ( .D(n591), .CK(n1981), .RN(n1906), .Q(
cont_var_out[0]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_18_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1899), .Q(add_subt_module_Add_Subt_result[18]) );
DFFRX1TS reg_ch_mux_2_Q_reg_0_ ( .D(n584), .CK(n1981), .RN(n687), .Q(
sel_mux_2_reg[0]), .QN(n1771) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_16_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1895), .Q(add_subt_module_Add_Subt_result[16]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_3_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1898), .Q(add_subt_module_Add_Subt_result[3]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_20_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1895), .Q(add_subt_module_Add_Subt_result[20]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_13_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1898), .Q(add_subt_module_Add_Subt_result[13]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_4_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1899), .Q(add_subt_module_Add_Subt_result[4]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_23_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1898), .Q(add_subt_module_Add_Subt_result[23]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_25_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1898), .Q(add_subt_module_Add_Subt_result[25]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_6_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1899), .Q(add_subt_module_Add_Subt_result[6]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_27_ ( .D(first_mux_X[27]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1926), .Q(d_ff2_X[27]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_27_ ( .D(first_mux_Y[27]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1906), .Q(d_ff2_Y[27]) );
DFFRX4TS reg_ch_mux_1_Q_reg_0_ ( .D(n585), .CK(n1981), .RN(n1921), .Q(
sel_mux_1_reg), .QN(n1778) );
DFFRX1TS add_subt_module_YRegister_Q_reg_1_ ( .D(n638), .CK(
add_subt_module_YRegister_net3522547), .RN(n1901), .Q(
add_subt_module_intDY[1]), .QN(n713) );
DFFRX1TS add_subt_module_Exp_Operation_Module_Overflow_Q_reg_0_ ( .D(n1984),
.CK(add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(
n1886), .Q(overflow_flag) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_29_ ( .D(first_mux_X[29]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1920), .Q(d_ff2_X[29]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_29_ ( .D(first_mux_Y[29]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1922), .Q(d_ff2_Y[29]) );
DFFRX1TS reg_operation_Q_reg_0_ ( .D(operation), .CK(reg_Z0_net3522529),
.RN(n1905), .Q(d_ff1_operation_out) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_9_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]),
.CK(clk), .RN(n1879), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_1_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[1]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1896), .Q(add_subt_module_exp_oper_result[1]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_2_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[2]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1894), .Q(add_subt_module_exp_oper_result[2]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(
n1995), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1889), .Q(add_subt_module_Sgf_normalized_result[2]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_24_ ( .D(
n1989), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1893), .Q(add_subt_module_Sgf_normalized_result[24]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(
n1991), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1902), .Q(add_subt_module_Sgf_normalized_result[11]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(
n1992), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1014), .Q(add_subt_module_Sgf_normalized_result[7]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(
n1993), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1902), .Q(add_subt_module_Sgf_normalized_result[3]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(
n1994), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1014), .Q(add_subt_module_Sgf_normalized_result[6]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(
n1996), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1891), .Q(add_subt_module_Sgf_normalized_result[10]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(
n1997), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1889), .Q(add_subt_module_Sgf_normalized_result[5]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(
n1998), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1892), .Q(add_subt_module_Sgf_normalized_result[9]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(
n1999), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1902), .Q(add_subt_module_Sgf_normalized_result[4]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(
n2001), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1902), .Q(add_subt_module_Sgf_normalized_result[12]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(
n2002), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1014), .Q(add_subt_module_Sgf_normalized_result[16]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(
n2003), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1891), .Q(add_subt_module_Sgf_normalized_result[13]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(
n2004), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1887), .Q(add_subt_module_Sgf_normalized_result[19]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(
n2006), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1893), .Q(add_subt_module_Sgf_normalized_result[22]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(
n2007), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1892), .Q(add_subt_module_Sgf_normalized_result[15]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(
n2008), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1890), .Q(add_subt_module_Sgf_normalized_result[8]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(
n2009), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1893), .Q(add_subt_module_Sgf_normalized_result[23]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(
n2010), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1886), .Q(add_subt_module_Sgf_normalized_result[21]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(
n2011), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1015), .Q(add_subt_module_Sgf_normalized_result[20]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(
n2012), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1888), .Q(add_subt_module_Sgf_normalized_result[17]) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_0_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1896), .Q(add_subt_module_exp_oper_result[0]) );
DFFRX1TS reg_ch_mux_3_Q_reg_0_ ( .D(n582), .CK(n1981), .RN(n1928), .Q(
sel_mux_3_reg), .QN(n1862) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(
n2013), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1893), .Q(add_subt_module_Sgf_normalized_result[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ (
.D(add_subt_module_final_result_ieee_Module_Sign_S_mux), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1885), .Q(result_add_subt[31]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[7]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[30]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[12]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1880), .Q(result_add_subt[12]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_26_ ( .D(first_mux_X[26]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1915), .Q(d_ff2_X[26]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_25_ ( .D(first_mux_X[25]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1919), .Q(d_ff2_X[25]) );
DFFRX1TS reg_val_muxX_2stage_Q_reg_24_ ( .D(first_mux_X[24]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1921), .Q(d_ff2_X[24]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_26_ ( .D(first_mux_Y[26]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1923), .Q(d_ff2_Y[26]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_25_ ( .D(first_mux_Y[25]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n687), .Q(d_ff2_Y[25]) );
DFFRX1TS reg_val_muxY_2stage_Q_reg_24_ ( .D(first_mux_Y[24]), .CK(
reg_val_muxZ_2stage_net3522529), .RN(n1918), .Q(d_ff2_Y[24]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_0_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]),
.CK(clk), .RN(n1015), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_1_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]),
.CK(clk), .RN(n1888), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]) );
DFFRX4TS add_subt_module_FS_Module_state_reg_reg_0_ ( .D(
add_subt_module_FS_Module_state_next[0]), .CK(
add_subt_module_FS_Module_net3522637), .RN(n1881), .Q(
add_subt_module_FS_Module_state_reg[0]), .QN(n1953) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_8_ (
.D(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]),
.CK(clk), .RN(n1014), .Q(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_24_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1898), .Q(add_subt_module_Add_Subt_result[24]), .QN(n1814) );
DFFRX1TS reg_region_flag_Q_reg_1_ ( .D(shift_region_flag[1]), .CK(
reg_Z0_net3522529), .RN(n1905), .Q(d_ff1_shift_region_flag_out[1]) );
DFFRX1TS cont_var_count_reg_1_ ( .D(n590), .CK(n1981), .RN(n1905), .Q(
cont_var_out[1]), .QN(n682) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(
n1990), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1894), .Q(add_subt_module_Sgf_normalized_result[1]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(
n2005), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1889), .Q(add_subt_module_Sgf_normalized_result[18]) );
DFFRX1TS add_subt_module_Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(
n2000), .CK(
add_subt_module_Barrel_Shifter_module_Output_Reg_net3522583), .RN(
n1890), .Q(add_subt_module_Sgf_normalized_result[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[22]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1876), .Q(result_add_subt[22]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[15]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1876), .Q(result_add_subt[15]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[18]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1876), .Q(result_add_subt[18]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[19]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1877), .Q(result_add_subt[19]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[21]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1877), .Q(result_add_subt[21]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ (
.D(n1873), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1882), .Q(result_add_subt[6]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[13]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1878), .Q(result_add_subt[13]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[20]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1878), .Q(result_add_subt[20]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[16]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1878), .Q(result_add_subt[16]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[17]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1879), .Q(result_add_subt[17]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[11]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1879), .Q(result_add_subt[11]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[14]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1880), .Q(result_add_subt[14]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[10]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1880), .Q(result_add_subt[10]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[6]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[29]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[5]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[28]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[4]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[27]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[3]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[26]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[2]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[25]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[1]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[24]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ (
.D(add_subt_module_final_result_ieee_Module_Exp_S_mux[0]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1881), .Q(result_add_subt[23]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ (
.D(n1872), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1885), .Q(result_add_subt[2]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ (
.D(n1871), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1885), .Q(result_add_subt[7]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ (
.D(n1870), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1892), .Q(result_add_subt[3]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ (
.D(n1869), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1887), .Q(result_add_subt[8]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ (
.D(n1865), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1888), .Q(result_add_subt[0]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ (
.D(n1868), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1014), .Q(result_add_subt[4]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ (
.D(n1867), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1892), .Q(result_add_subt[1]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ (
.D(n1866), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1887), .Q(result_add_subt[5]) );
DFFRX1TS add_subt_module_final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ (
.D(add_subt_module_final_result_ieee_Module_Sgf_S_mux[9]), .CK(
add_subt_module_final_result_ieee_Module_Final_Result_IEEE_net3522547),
.RN(n1015), .Q(result_add_subt[9]) );
DFFSX1TS reg_ch_mux_2_Q_reg_1_ ( .D(n1733), .CK(n1981), .SN(n1918), .Q(n1812), .QN(sel_mux_2_reg[1]) );
DFFRX2TS cordic_FSM_state_reg_reg_2_ ( .D(n601), .CK(clk), .RN(n1882), .Q(
cordic_FSM_state_reg[2]), .QN(n1980) );
DFFRX2TS cordic_FSM_state_reg_reg_0_ ( .D(n602), .CK(clk), .RN(n1881), .Q(
cordic_FSM_state_reg[0]), .QN(n680) );
DFFRX1TS add_subt_module_Sel_B_Q_reg_0_ ( .D(n594), .CK(
add_subt_module_FS_Module_net3522637), .RN(n580), .Q(
add_subt_module_FSM_selector_B[0]), .QN(n679) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_21_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1895), .Q(add_subt_module_Add_Subt_result[21]), .QN(n1810) );
DFFRX1TS add_subt_module_Exp_Operation_Module_exp_result_Q_reg_3_ ( .D(
add_subt_module_Exp_Operation_Module_Data_S[3]), .CK(
add_subt_module_Exp_Operation_Module_exp_result_net3522601), .RN(n1896), .Q(add_subt_module_exp_oper_result[3]), .QN(n1757) );
DFFSX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_5_ (
.D(n722), .CK(clk), .SN(n1876), .Q(n1857), .QN(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]) );
DFFSX1TS add_subt_module_Barrel_Shifter_module_Mux_Array_Mid_Reg_Q_reg_6_ (
.D(n753), .CK(clk), .SN(n1879), .Q(n1858), .QN(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]) );
DFFRX1TS add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_Q_reg_22_ ( .D(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1898), .Q(add_subt_module_Add_Subt_result[22]) );
DFFRX2TS add_subt_module_Add_Subt_Sgf_module_Add_overflow_Result_Q_reg_0_ (
.D(add_subt_module_Add_Subt_Sgf_module_S_to_D[26]), .CK(
add_subt_module_Add_Subt_Sgf_module_Add_Subt_Result_net3522583), .RN(
n1899), .Q(add_subt_module_add_overflow_flag), .QN(n1786) );
CMPR32X2TS intadd_391_U4 ( .A(d_ff2_X[24]), .B(n686), .C(intadd_391_CI),
.CO(intadd_391_n3), .S(sh_exp_x[1]) );
CMPR32X2TS intadd_392_U4 ( .A(d_ff2_Y[24]), .B(n686), .C(intadd_392_CI),
.CO(intadd_392_n3), .S(sh_exp_y[1]) );
CMPR32X2TS intadd_392_U3 ( .A(d_ff2_Y[25]), .B(data_out_LUT[8]), .C(
intadd_392_n3), .CO(intadd_392_n2), .S(sh_exp_y[2]) );
CMPR32X2TS intadd_391_U3 ( .A(d_ff2_X[25]), .B(data_out_LUT[8]), .C(
intadd_391_n3), .CO(intadd_391_n2), .S(sh_exp_x[2]) );
CMPR32X2TS intadd_391_U2 ( .A(d_ff2_X[26]), .B(n1781), .C(intadd_391_n2),
.CO(intadd_391_n1), .S(sh_exp_x[3]) );
CMPR32X2TS intadd_392_U2 ( .A(d_ff2_Y[26]), .B(n1781), .C(intadd_392_n2),
.CO(intadd_392_n1), .S(sh_exp_y[3]) );
AOI222X1TS U1078 ( .A0(n1046), .A1(d_ff2_Z[30]), .B0(n1045), .B1(d_ff2_Y[30]), .C0(n1044), .C1(d_ff2_X[30]), .Y(n1959) );
BUFX3TS U1079 ( .A(n1532), .Y(n1583) );
INVX2TS U1080 ( .A(n1532), .Y(n1585) );
CMPR32X2TS U1081 ( .A(n967), .B(n966), .C(n965), .CO(n969), .S(
add_subt_module_Exp_Operation_Module_Data_S[7]) );
INVX4TS U1082 ( .A(n1159), .Y(n678) );
CMPR32X2TS U1083 ( .A(n958), .B(n957), .C(n956), .CO(n953), .S(
add_subt_module_Exp_Operation_Module_Data_S[2]) );
INVX2TS U1084 ( .A(n689), .Y(n690) );
CMPR32X2TS U1085 ( .A(n963), .B(n968), .C(n962), .CO(n959), .S(
add_subt_module_Exp_Operation_Module_Data_S[0]) );
NAND2X1TS U1086 ( .A(n1673), .B(n1207), .Y(n1481) );
NOR3X1TS U1087 ( .A(add_subt_module_Add_Subt_result[21]), .B(
add_subt_module_Add_Subt_result[19]), .C(
add_subt_module_Add_Subt_result[20]), .Y(n1480) );
INVX2TS U1088 ( .A(n1054), .Y(n1471) );
NOR2X1TS U1089 ( .A(n683), .B(add_subt_module_FS_Module_state_reg[1]), .Y(
n928) );
CLKBUFX2TS U1090 ( .A(n1953), .Y(n683) );
NOR2XLTS U1091 ( .A(n1840), .B(add_subt_module_intDX[11]), .Y(n1323) );
OAI21XLTS U1092 ( .A0(add_subt_module_intDX[15]), .A1(n1843), .B0(
add_subt_module_intDX[14]), .Y(n1331) );
OAI21XLTS U1093 ( .A0(add_subt_module_intDX[23]), .A1(n1847), .B0(
add_subt_module_intDX[22]), .Y(n1351) );
NOR2XLTS U1094 ( .A(n1796), .B(add_subt_module_exp_oper_result[3]), .Y(n988)
);
OAI21XLTS U1095 ( .A0(n1181), .A1(n1431), .B0(n1182), .Y(n835) );
NOR2XLTS U1096 ( .A(n1135), .B(n1814), .Y(n1064) );
NOR2XLTS U1097 ( .A(n1748), .B(add_subt_module_FS_Module_state_reg[0]), .Y(
n1016) );
NOR2XLTS U1098 ( .A(n1062), .B(add_subt_module_Add_Subt_result[0]), .Y(n1056) );
NOR2XLTS U1099 ( .A(n1784), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n1055) );
INVX2TS U1100 ( .A(n1455), .Y(n1449) );
NAND2X1TS U1101 ( .A(n791), .B(n790), .Y(n880) );
AOI211XLTS U1102 ( .A0(n1543), .A1(n1264), .B0(n1263), .C0(n1262), .Y(n1265)
);
OAI21XLTS U1103 ( .A0(n1065), .A1(n1142), .B0(n1071), .Y(n1066) );
INVX2TS U1104 ( .A(n1255), .Y(n1257) );
NOR2XLTS U1105 ( .A(d_ff2_X[29]), .B(n1731), .Y(n1730) );
OAI21XLTS U1106 ( .A0(n1540), .A1(n1809), .B0(n1265), .Y(n2000) );
OAI21XLTS U1107 ( .A0(n1148), .A1(n1525), .B0(n1147), .Y(n2006) );
OAI211XLTS U1108 ( .A0(n1173), .A1(n701), .B0(n1168), .C0(n1167), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[14]) );
OAI211XLTS U1109 ( .A0(n1173), .A1(n1159), .B0(n1144), .C0(n1143), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[13]) );
OAI21XLTS U1110 ( .A0(n1663), .A1(n1593), .B0(n1126), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[18]) );
OAI211XLTS U1111 ( .A0(n1483), .A1(n1257), .B0(n1217), .C0(n1216), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[0]) );
NOR2XLTS U1112 ( .A(cont_iter_out[3]), .B(n1290), .Y(data_out_LUT[26]) );
XOR2X1TS U1113 ( .A(n1409), .B(n1408), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[23]) );
XOR2X1TS U1114 ( .A(n1418), .B(n1417), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[21]) );
XOR2X1TS U1115 ( .A(n1185), .B(n1184), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[14]) );
OAI211X1TS U1116 ( .A0(n1173), .A1(n1590), .B0(n1172), .C0(n1171), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[15]) );
CLKAND2X2TS U1117 ( .A(n741), .B(n740), .Y(n742) );
CLKAND2X2TS U1118 ( .A(n752), .B(n751), .Y(n753) );
OAI21X1TS U1119 ( .A0(n1765), .A1(n1508), .B0(n1229), .Y(n1992) );
OAI211X1TS U1120 ( .A0(n1083), .A1(n1525), .B0(n1082), .C0(n1081), .Y(n1998)
);
OAI211X1TS U1121 ( .A0(n1190), .A1(n1201), .B0(n1189), .C0(n1539), .Y(n2002)
);
OAI211X1TS U1122 ( .A0(n1588), .A1(n1173), .B0(n1162), .C0(n1161), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[16]) );
AO21X1TS U1123 ( .A0(n1009), .A1(n1546), .B0(n1008), .Y(n1996) );
OAI211X1TS U1124 ( .A0(n1223), .A1(n1243), .B0(n1222), .C0(n1221), .Y(n2012)
);
OAI211X1TS U1125 ( .A0(n1518), .A1(n1243), .B0(n1242), .C0(n1241), .Y(n1997)
);
OAI211X1TS U1126 ( .A0(n1073), .A1(n1159), .B0(n1072), .C0(n1593), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[20]) );
OAI211X1TS U1127 ( .A0(n1522), .A1(n1243), .B0(n1234), .C0(n1233), .Y(n1994)
);
OAI21X1TS U1128 ( .A0(n1677), .A1(n1805), .B0(n1676), .Y(n1678) );
OAI21X1TS U1129 ( .A0(n1067), .A1(n1645), .B0(n1066), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[21]) );
OAI211X1TS U1130 ( .A0(n1257), .A1(n1853), .B0(n1256), .C0(n1676), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[4]) );
OAI211X1TS U1131 ( .A0(n1133), .A1(n1593), .B0(n1132), .C0(n1131), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[17]) );
XOR2X1TS U1132 ( .A(n866), .B(n865), .Y(n711) );
OAI211X1TS U1133 ( .A0(n1569), .A1(n1829), .B0(n1568), .C0(n1553), .Y(n1554)
);
OAI211X1TS U1134 ( .A0(n1533), .A1(n1201), .B0(n1200), .C0(n1539), .Y(n2003)
);
OAI211X1TS U1135 ( .A0(n1569), .A1(n1827), .B0(n1568), .C0(n1559), .Y(n1560)
);
OAI211X1TS U1136 ( .A0(n1195), .A1(n1201), .B0(n1194), .C0(n1539), .Y(n2007)
);
OAI211X1TS U1137 ( .A0(n1569), .A1(n1828), .B0(n1568), .C0(n1567), .Y(n1570)
);
XOR2X1TS U1138 ( .A(n871), .B(n870), .Y(n710) );
OAI211X1TS U1139 ( .A0(n1540), .A1(n1828), .B0(n1007), .C0(n1006), .Y(n1008)
);
NAND4BX1TS U1140 ( .AN(n1498), .B(n1497), .C(n1496), .D(n1495), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[1]) );
OAI211X1TS U1141 ( .A0(n1540), .A1(n1829), .B0(n1539), .C0(n1538), .Y(n1541)
);
OAI21X1TS U1142 ( .A0(n883), .A1(n879), .B0(n880), .Y(n871) );
NAND2BX1TS U1143 ( .AN(n1531), .B(n1530), .Y(n2005) );
XOR2X1TS U1144 ( .A(n1447), .B(n1446), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[5]) );
OAI21X1TS U1145 ( .A0(n1536), .A1(n1816), .B0(n1218), .Y(n1219) );
NAND2BX1TS U1146 ( .AN(n1520), .B(n1519), .Y(n2011) );
OAI211X1TS U1147 ( .A0(n1218), .A1(n1243), .B0(n1568), .C0(n997), .Y(n998)
);
NAND2BX1TS U1148 ( .AN(n1524), .B(n1523), .Y(n2004) );
OAI21X1TS U1149 ( .A0(n1588), .A1(n1142), .B0(n1071), .Y(n1061) );
OAI211X1TS U1150 ( .A0(n1521), .A1(n1550), .B0(n1568), .C0(n1231), .Y(n1232)
);
INVX3TS U1151 ( .A(n701), .Y(n702) );
OAI21X1TS U1152 ( .A0(n1447), .A1(n1443), .B0(n1444), .Y(n1442) );
NAND4X1TS U1153 ( .A(n1488), .B(n1497), .C(n1487), .D(n1486), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[2]) );
OAI211X1TS U1154 ( .A0(n1517), .A1(n1550), .B0(n1568), .C0(n1238), .Y(n1239)
);
AOI32X2TS U1155 ( .A0(n1634), .A1(n1648), .A2(n1633), .B0(n1632), .B1(n1645),
.Y(n1653) );
OAI21X1TS U1156 ( .A0(n1540), .A1(n1827), .B0(n1539), .Y(n1247) );
OAI21X1TS U1157 ( .A0(add_subt_module_Add_Subt_result[3]), .A1(
add_subt_module_Add_Subt_result[2]), .B0(n1484), .Y(n1251) );
AOI32X2TS U1158 ( .A0(n1641), .A1(n1648), .A2(n1640), .B0(n1639), .B1(n1645),
.Y(n1655) );
NOR2X1TS U1159 ( .A(n1527), .B(n1243), .Y(n1228) );
AOI31X1TS U1160 ( .A0(n1477), .A1(add_subt_module_Add_Subt_result[6]), .A2(
n1855), .B0(n1476), .Y(n1217) );
OAI21X1TS U1161 ( .A0(n1150), .A1(n1525), .B0(n1149), .Y(n2010) );
OAI21X1TS U1162 ( .A0(n1152), .A1(n1525), .B0(n1151), .Y(n2009) );
NAND2BX1TS U1163 ( .AN(n1505), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .Y(
n1283) );
AO22X1TS U1164 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[2]), .B0(
add_subt_module_DmP[21]), .B1(n1779), .Y(n1069) );
INVX3TS U1165 ( .A(n1068), .Y(n1142) );
CLKINVX2TS U1166 ( .A(n1252), .Y(n1477) );
NOR2X1TS U1167 ( .A(n1292), .B(n1279), .Y(enab_d_ff4_Yn) );
INVX3TS U1168 ( .A(n1532), .Y(n1581) );
INVX3TS U1169 ( .A(n1532), .Y(n1489) );
AO22X1TS U1170 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[3]), .B0(
add_subt_module_DmP[20]), .B1(n1779), .Y(n1122) );
AND2X2TS U1171 ( .A(n993), .B(n992), .Y(n1240) );
INVX3TS U1172 ( .A(n1068), .Y(n1658) );
NOR2X1TS U1173 ( .A(n896), .B(n897), .Y(n894) );
XOR2X1TS U1174 ( .A(d_ff2_Y[30]), .B(n1727), .Y(sh_exp_y[7]) );
XOR2X1TS U1175 ( .A(n968), .B(n943), .Y(n962) );
AND2X2TS U1176 ( .A(n940), .B(n726), .Y(n1133) );
XOR2X1TS U1177 ( .A(d_ff2_X[30]), .B(n1730), .Y(sh_exp_x[7]) );
OR2X2TS U1178 ( .A(n1004), .B(n1757), .Y(n992) );
OAI211X1TS U1179 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(n1121),
.B0(n1472), .C0(n1120), .Y(add_subt_module_FS_Module_state_next[0]) );
NAND2BX1TS U1180 ( .AN(load_cont_iter), .B(n1725), .Y(enab_cont_iter) );
OR2X2TS U1181 ( .A(n1677), .B(add_subt_module_Add_Subt_result[12]), .Y(n1209) );
OAI21X1TS U1182 ( .A0(n1732), .A1(n1864), .B0(n1731), .Y(sh_exp_x[5]) );
NAND3X1TS U1183 ( .A(n1473), .B(n1467), .C(n1577), .Y(
add_subt_module_FS_Module_state_next[2]) );
OAI21X1TS U1184 ( .A0(n1729), .A1(n1863), .B0(n1728), .Y(sh_exp_y[5]) );
NAND3X1TS U1185 ( .A(n1474), .B(n1473), .C(n1472), .Y(
add_subt_module_FS_Module_state_next[3]) );
OAI211X1TS U1186 ( .A0(n1270), .A1(n1808), .B0(n1724), .C0(n1715), .Y(n600)
);
NOR2X1TS U1187 ( .A(n1119), .B(n1471), .Y(n1120) );
NOR2X1TS U1188 ( .A(d_ff2_Y[29]), .B(n1728), .Y(n1727) );
OAI211X1TS U1189 ( .A0(cont_iter_out[1]), .A1(data_out_LUT[22]), .B0(n1704),
.C0(n1289), .Y(data_out_LUT[24]) );
NAND3X1TS U1190 ( .A(n1579), .B(n1578), .C(n1577), .Y(
add_subt_module_FS_Module_state_next[1]) );
OAI21X1TS U1191 ( .A0(n1438), .A1(n1444), .B0(n1439), .Y(n781) );
NAND2BX1TS U1192 ( .AN(data_out_LUT[12]), .B(n1698), .Y(data_out_LUT[14]) );
NAND2BX1TS U1193 ( .AN(n999), .B(n1075), .Y(n1002) );
NOR2X1TS U1194 ( .A(n1680), .B(n1482), .Y(n1487) );
AO22X1TS U1195 ( .A0(n1494), .A1(add_subt_module_Add_Subt_result[12]), .B0(
n1673), .B1(n1210), .Y(n1679) );
AOI31X2TS U1196 ( .A0(n1288), .A1(n1702), .A2(intadd_391_B_0_), .B0(n1287),
.Y(n1704) );
NAND2BX1TS U1197 ( .AN(n1163), .B(n1166), .Y(data_out_LUT[1]) );
AND2X2TS U1198 ( .A(n1060), .B(add_subt_module_add_overflow_flag), .Y(n1071)
);
AND2X2TS U1199 ( .A(n1145), .B(n694), .Y(n1075) );
INVX6TS U1200 ( .A(n1395), .Y(n787) );
NOR2X1TS U1201 ( .A(add_subt_module_FS_Module_state_reg[1]), .B(n1475), .Y(
add_subt_module_FSM_LZA_load) );
NAND3X1TS U1202 ( .A(n1059), .B(n1468), .C(n1058), .Y(n1060) );
CLKAND2X2TS U1203 ( .A(n915), .B(n914), .Y(n916) );
CLKAND2X2TS U1204 ( .A(n912), .B(n914), .Y(n913) );
OAI211X1TS U1205 ( .A0(n1303), .A1(n1359), .B0(n1302), .C0(n1301), .Y(n1308)
);
CLKAND2X2TS U1206 ( .A(n910), .B(n914), .Y(n911) );
CLKAND2X2TS U1207 ( .A(n908), .B(n1713), .Y(n909) );
CLKAND2X2TS U1208 ( .A(n906), .B(n1713), .Y(n907) );
NAND2BX1TS U1209 ( .AN(add_subt_module_exp_oper_result[7]), .B(n1672), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[7]) );
NAND2BX1TS U1210 ( .AN(add_subt_module_exp_oper_result[2]), .B(n1672), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[2]) );
NAND2BX1TS U1211 ( .AN(add_subt_module_exp_oper_result[1]), .B(n1672), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[1]) );
NAND2BX1TS U1212 ( .AN(add_subt_module_exp_oper_result[0]), .B(n1672), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[0]) );
NAND2BX1TS U1213 ( .AN(add_subt_module_exp_oper_result[5]), .B(n1672), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[5]) );
INVX1TS U1214 ( .A(n935), .Y(n991) );
NAND2BX1TS U1215 ( .AN(add_subt_module_exp_oper_result[6]), .B(n1672), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[6]) );
NOR2X2TS U1216 ( .A(add_subt_module_FSM_selector_B[1]), .B(n694), .Y(n725)
);
NOR2X4TS U1217 ( .A(n985), .B(n984), .Y(n986) );
NOR2X1TS U1218 ( .A(n1953), .B(n1638), .Y(n985) );
NAND2BX1TS U1219 ( .AN(add_subt_module_Sgf_normalized_result[25]), .B(n1390),
.Y(n1398) );
OAI221XLTS U1220 ( .A0(n1800), .A1(add_subt_module_intDY[1]), .B0(n1769),
.B1(add_subt_module_intDY[0]), .C0(n1085), .Y(n1090) );
OAI211X2TS U1221 ( .A0(add_subt_module_intDX[12]), .A1(n1787), .B0(n1335),
.C0(n1321), .Y(n1337) );
INVX3TS U1222 ( .A(n1684), .Y(n1708) );
NAND3X1TS U1223 ( .A(n1850), .B(n1325), .C(add_subt_module_intDX[8]), .Y(
n1326) );
CLKMX2X2TS U1224 ( .A(add_subt_module_DMP[22]), .B(
add_subt_module_Sgf_normalized_result[24]), .S0(n1386), .Y(n1387) );
NOR2X1TS U1225 ( .A(n1638), .B(add_subt_module_FS_Module_state_reg[3]), .Y(
n729) );
INVX3TS U1226 ( .A(n1703), .Y(data_out_LUT[8]) );
OAI211X1TS U1227 ( .A0(add_subt_module_intDX[8]), .A1(n1850), .B0(n1325),
.C0(n1328), .Y(n1339) );
NAND3X1TS U1228 ( .A(cordic_FSM_state_reg[2]), .B(n1269), .C(n1808), .Y(
n1715) );
CLKMX2X2TS U1229 ( .A(add_subt_module_DMP[20]), .B(
add_subt_module_Sgf_normalized_result[22]), .S0(n1386), .Y(n1379) );
INVX3TS U1230 ( .A(n1705), .Y(n1702) );
NOR2X1TS U1231 ( .A(n1323), .B(add_subt_module_intDY[10]), .Y(n1324) );
CLKMX2X2TS U1232 ( .A(add_subt_module_DMP[21]), .B(
add_subt_module_Sgf_normalized_result[23]), .S0(n1386), .Y(n1383) );
NAND3X1TS U1233 ( .A(n1846), .B(n1300), .C(add_subt_module_intDX[26]), .Y(
n1302) );
INVX2TS U1234 ( .A(n1683), .Y(n1706) );
INVX2TS U1235 ( .A(n1683), .Y(n1025) );
NOR2X1TS U1236 ( .A(n1358), .B(add_subt_module_intDY[24]), .Y(n1299) );
OAI211X2TS U1237 ( .A0(add_subt_module_intDX[20]), .A1(n1836), .B0(n1355),
.C0(n1340), .Y(n1349) );
INVX1TS U1238 ( .A(n1019), .Y(n1017) );
NAND2BX1TS U1239 ( .AN(add_subt_module_intDX[9]), .B(
add_subt_module_intDY[9]), .Y(n1325) );
NAND3X1TS U1240 ( .A(n684), .B(n680), .C(cordic_FSM_state_reg[1]), .Y(n1153)
);
NOR2X1TS U1241 ( .A(add_subt_module_Add_Subt_result[15]), .B(
add_subt_module_Add_Subt_result[16]), .Y(n1206) );
NAND2BX1TS U1242 ( .AN(add_subt_module_intDX[21]), .B(
add_subt_module_intDY[21]), .Y(n1340) );
OR2X2TS U1243 ( .A(add_subt_module_Add_Subt_result[7]), .B(
add_subt_module_Add_Subt_result[6]), .Y(n1250) );
NAND2BX1TS U1244 ( .AN(add_subt_module_intDX[13]), .B(
add_subt_module_intDY[13]), .Y(n1321) );
NAND2BX1TS U1245 ( .AN(add_subt_module_intDX[19]), .B(
add_subt_module_intDY[19]), .Y(n1346) );
NOR2X1TS U1246 ( .A(cordic_FSM_state_reg[3]), .B(n1983), .Y(enab_d_ff2_RB2)
);
NAND2BX1TS U1247 ( .AN(add_subt_module_intDX[27]), .B(
add_subt_module_intDY[27]), .Y(n1300) );
OAI21X1TS U1248 ( .A0(add_subt_module_intDX[21]), .A1(n1835), .B0(
add_subt_module_intDX[20]), .Y(n1343) );
NAND2BX1TS U1249 ( .AN(add_subt_module_intDY[27]), .B(
add_subt_module_intDX[27]), .Y(n1301) );
NAND2BX1TS U1250 ( .AN(add_subt_module_intDX[24]), .B(
add_subt_module_intDY[24]), .Y(n1356) );
NOR2X1TS U1251 ( .A(n1748), .B(n1953), .Y(n1018) );
NOR2X1TS U1252 ( .A(n1808), .B(n1983), .Y(enab_d_ff5_data_out) );
NOR2X1TS U1253 ( .A(n1784), .B(n1953), .Y(n964) );
NOR2X1TS U1254 ( .A(cont_iter_out[0]), .B(n680), .Y(n1987) );
INVX3TS U1255 ( .A(n715), .Y(n1705) );
INVX3TS U1256 ( .A(sel_mux_1_reg), .Y(n1707) );
NOR2X1TS U1257 ( .A(n1786), .B(add_subt_module_FS_Module_state_reg[0]), .Y(
n984) );
XOR2X1TS U1258 ( .A(n1400), .B(n1399), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[25]) );
OAI21X2TS U1259 ( .A0(n839), .A1(n838), .B0(n837), .Y(n840) );
NAND3X1TS U1260 ( .A(n1255), .B(add_subt_module_Add_Subt_result[1]), .C(
n1825), .Y(n1676) );
OAI21X2TS U1261 ( .A0(n1874), .A1(n974), .B0(n973), .Y(n596) );
OR4X4TS U1262 ( .A(n1267), .B(add_subt_module_Exp_Operation_Module_Data_S[7]), .C(add_subt_module_Exp_Operation_Module_Data_S[6]), .D(n972), .Y(n973) );
OAI21X4TS U1263 ( .A0(n1409), .A1(n1405), .B0(n1406), .Y(n1404) );
OAI211X4TS U1264 ( .A0(n1204), .A1(n1203), .B0(n1202), .C0(n1717), .Y(
cordic_FSM_state_next_1_) );
NAND2X1TS U1265 ( .A(n1019), .B(n1084), .Y(n975) );
AO21X1TS U1266 ( .A0(add_subt_module_Exp_Operation_Module_Data_S[7]), .A1(
n1268), .B0(n1267), .Y(n1984) );
CLKAND2X2TS U1267 ( .A(n986), .B(n693), .Y(n1543) );
CLKAND2X2TS U1268 ( .A(n1258), .B(n986), .Y(n1003) );
MX2X1TS U1269 ( .A(add_subt_module_DMP[25]), .B(
add_subt_module_exp_oper_result[2]), .S0(n1386), .Y(n957) );
MX2X1TS U1270 ( .A(add_subt_module_DMP[28]), .B(
add_subt_module_exp_oper_result[5]), .S0(
add_subt_module_FSM_selector_D), .Y(n948) );
CLKAND2X2TS U1271 ( .A(n690), .B(add_subt_module_DmP[28]), .Y(n934) );
OAI32X1TS U1272 ( .A0(n1320), .A1(n1319), .A2(n1318), .B0(n1317), .B1(n1319),
.Y(n1338) );
AOI222X1TS U1273 ( .A0(add_subt_module_intDY[4]), .A1(n1761), .B0(n1316),
.B1(n1315), .C0(add_subt_module_intDY[5]), .C1(n1806), .Y(n1318) );
MX2X1TS U1274 ( .A(add_subt_module_DMP[2]), .B(
add_subt_module_Sgf_normalized_result[4]), .S0(n933), .Y(n775) );
MX2X1TS U1275 ( .A(add_subt_module_DMP[11]), .B(
add_subt_module_Sgf_normalized_result[13]), .S0(n854), .Y(n831) );
MX2X1TS U1276 ( .A(add_subt_module_DMP[7]), .B(
add_subt_module_Sgf_normalized_result[9]), .S0(n854), .Y(n794) );
MX2X1TS U1277 ( .A(add_subt_module_DMP[6]), .B(
add_subt_module_Sgf_normalized_result[8]), .S0(n933), .Y(n792) );
MX2X1TS U1278 ( .A(add_subt_module_DMP[5]), .B(
add_subt_module_Sgf_normalized_result[7]), .S0(n933), .Y(n790) );
NOR2X1TS U1279 ( .A(n1179), .B(n1181), .Y(n836) );
NAND2X1TS U1280 ( .A(n1437), .B(n782), .Y(n784) );
NOR2X1TS U1281 ( .A(n1443), .B(n1438), .Y(n782) );
MX2X1TS U1282 ( .A(add_subt_module_DMP[0]), .B(
add_subt_module_Sgf_normalized_result[2]), .S0(n933), .Y(n765) );
AO22XLTS U1283 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[8]), .B0(
add_subt_module_DmP[15]), .B1(n1140), .Y(n739) );
AO22XLTS U1284 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[9]), .B0(
add_subt_module_DmP[14]), .B1(n1140), .Y(n736) );
AO22XLTS U1285 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[11]), .B0(
add_subt_module_DmP[12]), .B1(n1140), .Y(n734) );
AO22XLTS U1286 ( .A0(n1657), .A1(add_subt_module_Add_Subt_result[7]), .B0(
add_subt_module_DmP[16]), .B1(n1140), .Y(n1141) );
AO22XLTS U1287 ( .A0(n700), .A1(add_subt_module_Add_Subt_result[5]), .B0(
add_subt_module_DmP[18]), .B1(n1140), .Y(n1127) );
AO22XLTS U1288 ( .A0(n700), .A1(add_subt_module_Add_Subt_result[4]), .B0(
add_subt_module_DmP[19]), .B1(n1779), .Y(n1123) );
AO22XLTS U1289 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[14]), .B0(
add_subt_module_DmP[9]), .B1(n1140), .Y(n731) );
AO22XLTS U1290 ( .A0(n1657), .A1(add_subt_module_Add_Subt_result[18]), .B0(
add_subt_module_DmP[5]), .B1(n1779), .Y(n743) );
AO22XLTS U1291 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[16]), .B0(
add_subt_module_DmP[7]), .B1(n1140), .Y(n749) );
AO22XLTS U1292 ( .A0(n700), .A1(add_subt_module_Add_Subt_result[20]), .B0(
add_subt_module_DmP[3]), .B1(n1779), .Y(n754) );
AO22XLTS U1293 ( .A0(n700), .A1(add_subt_module_Add_Subt_result[17]), .B0(
add_subt_module_DmP[6]), .B1(n1140), .Y(n747) );
NAND2X1TS U1294 ( .A(n1465), .B(n928), .Y(n1054) );
NAND3XLTS U1295 ( .A(n1145), .B(n1534), .C(n1000), .Y(n1001) );
CLKAND2X2TS U1296 ( .A(n1391), .B(add_subt_module_Sgf_normalized_result[1]),
.Y(n759) );
INVX2TS U1297 ( .A(n889), .Y(n896) );
INVX2TS U1298 ( .A(cordic_FSM_state_reg[0]), .Y(n685) );
NOR2X2TS U1299 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.Y(n1721) );
NAND2X2TS U1300 ( .A(n1065), .B(n737), .Y(n1159) );
NAND3XLTS U1301 ( .A(n1673), .B(add_subt_module_Add_Subt_result[16]), .C(
n1785), .Y(n1212) );
NOR3BXLTS U1302 ( .AN(add_subt_module_Add_Subt_result[14]), .B(n1675), .C(
add_subt_module_Add_Subt_result[18]), .Y(n1210) );
MX2X1TS U1303 ( .A(add_subt_module_DMP[23]), .B(
add_subt_module_exp_oper_result[0]), .S0(n1386), .Y(n963) );
ADDFHX2TS U1304 ( .A(n955), .B(n954), .CI(n953), .CO(n950), .S(
add_subt_module_Exp_Operation_Module_Data_S[3]) );
MX2X1TS U1305 ( .A(add_subt_module_DMP[26]), .B(
add_subt_module_exp_oper_result[3]), .S0(n1386), .Y(n954) );
AO21XLTS U1306 ( .A0(n1700), .A1(n1699), .B0(data_out_LUT[10]), .Y(
data_out_LUT[0]) );
ADDFHX2TS U1307 ( .A(n946), .B(n945), .CI(n944), .CO(n965), .S(
add_subt_module_Exp_Operation_Module_Data_S[6]) );
MX2X1TS U1308 ( .A(add_subt_module_DMP[29]), .B(
add_subt_module_exp_oper_result[6]), .S0(n933), .Y(n945) );
CLKAND2X2TS U1309 ( .A(n690), .B(add_subt_module_DmP[29]), .Y(n932) );
NAND2BXLTS U1310 ( .AN(add_subt_module_intDY[9]), .B(
add_subt_module_intDX[9]), .Y(n1327) );
OAI21XLTS U1311 ( .A0(add_subt_module_intDX[13]), .A1(n1834), .B0(
add_subt_module_intDX[12]), .Y(n1322) );
OAI211XLTS U1312 ( .A0(n1851), .A1(add_subt_module_intDX[3]), .B0(n1313),
.C0(n1312), .Y(n1316) );
NAND2BXLTS U1313 ( .AN(add_subt_module_intDX[2]), .B(
add_subt_module_intDY[2]), .Y(n1312) );
OAI2BB2XLTS U1314 ( .B0(add_subt_module_intDY[0]), .B1(n1311), .A0N(
add_subt_module_intDX[1]), .A1N(n713), .Y(n1313) );
OAI21XLTS U1315 ( .A0(add_subt_module_intDX[1]), .A1(n713), .B0(
add_subt_module_intDX[0]), .Y(n1311) );
AOI2BB2XLTS U1316 ( .B0(add_subt_module_intDX[3]), .B1(n1851), .A0N(
add_subt_module_intDY[2]), .A1N(n1314), .Y(n1315) );
OAI21XLTS U1317 ( .A0(add_subt_module_intDX[3]), .A1(n1851), .B0(
add_subt_module_intDX[2]), .Y(n1314) );
NAND3BX1TS U1318 ( .AN(n1344), .B(n1342), .C(n1341), .Y(n1362) );
MX2X1TS U1319 ( .A(add_subt_module_DMP[4]), .B(
add_subt_module_Sgf_normalized_result[6]), .S0(n933), .Y(n779) );
MX2X1TS U1320 ( .A(add_subt_module_DMP[18]), .B(
add_subt_module_Sgf_normalized_result[20]), .S0(n1386), .Y(n1370) );
MX2X1TS U1321 ( .A(add_subt_module_DMP[1]), .B(
add_subt_module_Sgf_normalized_result[3]), .S0(n933), .Y(n773) );
MX2X1TS U1322 ( .A(add_subt_module_DMP[14]), .B(
add_subt_module_Sgf_normalized_result[16]), .S0(n854), .Y(n847) );
MX2X1TS U1323 ( .A(add_subt_module_DMP[16]), .B(
add_subt_module_Sgf_normalized_result[18]), .S0(n854), .Y(n855) );
MX2X1TS U1324 ( .A(add_subt_module_DMP[10]), .B(
add_subt_module_Sgf_normalized_result[12]), .S0(n854), .Y(n805) );
MX2X1TS U1325 ( .A(add_subt_module_DMP[8]), .B(
add_subt_module_Sgf_normalized_result[10]), .S0(n854), .Y(n796) );
MX2X1TS U1326 ( .A(add_subt_module_DMP[9]), .B(
add_subt_module_Sgf_normalized_result[11]), .S0(n854), .Y(n801) );
MX2X1TS U1327 ( .A(add_subt_module_DMP[17]), .B(
add_subt_module_Sgf_normalized_result[19]), .S0(n1386), .Y(n859) );
MX2X1TS U1328 ( .A(add_subt_module_DMP[15]), .B(
add_subt_module_Sgf_normalized_result[17]), .S0(n854), .Y(n851) );
NAND2X1TS U1329 ( .A(n810), .B(n799), .Y(n827) );
MX2X1TS U1330 ( .A(add_subt_module_DMP[13]), .B(
add_subt_module_Sgf_normalized_result[15]), .S0(n854), .Y(n844) );
MX2X1TS U1331 ( .A(add_subt_module_DMP[3]), .B(
add_subt_module_Sgf_normalized_result[5]), .S0(n933), .Y(n777) );
MX2X1TS U1332 ( .A(add_subt_module_DMP[12]), .B(
add_subt_module_Sgf_normalized_result[14]), .S0(n854), .Y(n833) );
OAI21X1TS U1333 ( .A0(n830), .A1(n829), .B0(n828), .Y(n1175) );
NOR2X1TS U1334 ( .A(n824), .B(n830), .Y(n1174) );
MX2X1TS U1335 ( .A(add_subt_module_DMP[19]), .B(
add_subt_module_Sgf_normalized_result[21]), .S0(n1386), .Y(n1376) );
NAND2X1TS U1336 ( .A(n1019), .B(n729), .Y(n1058) );
NAND2X1TS U1337 ( .A(n1084), .B(n1784), .Y(n1022) );
OR2X1TS U1338 ( .A(n1388), .B(n1387), .Y(n1402) );
OR2X1TS U1339 ( .A(n1380), .B(n1379), .Y(n1411) );
AO22XLTS U1340 ( .A0(n1657), .A1(add_subt_module_Add_Subt_result[21]), .B0(
add_subt_module_DmP[2]), .B1(n1779), .Y(n1627) );
AO22XLTS U1341 ( .A0(n721), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B0(
n1237), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]), .Y(
n1552) );
AO22XLTS U1342 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .A1(
n1564), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[27]), .B1(
n1563), .Y(n1551) );
AO22XLTS U1343 ( .A0(n721), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B0(
n1237), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]), .Y(
n1558) );
AO22XLTS U1344 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .A1(
n1564), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[26]), .B1(
n1563), .Y(n1557) );
AO22XLTS U1345 ( .A0(n721), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B0(
n1237), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]), .Y(
n1566) );
AO22XLTS U1346 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .A1(
n1564), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[25]), .B1(
n1563), .Y(n1565) );
OR2X1TS U1347 ( .A(n1371), .B(n1370), .Y(n1420) );
OR2X1TS U1348 ( .A(n848), .B(n847), .Y(n1428) );
OR2X1TS U1349 ( .A(n856), .B(n855), .Y(n1424) );
CLKAND2X2TS U1350 ( .A(n933), .B(add_subt_module_Sgf_normalized_result[0]),
.Y(n763) );
NAND2X1TS U1351 ( .A(n1785), .B(n1206), .Y(n1675) );
CLKINVX3TS U1352 ( .A(rst), .Y(n1013) );
AOI2BB1XLTS U1353 ( .A0N(n1211), .A1N(add_subt_module_Add_Subt_result[23]),
.B0(add_subt_module_Add_Subt_result[24]), .Y(n1213) );
INVX2TS U1354 ( .A(n1683), .Y(n1023) );
INVX2TS U1355 ( .A(n1683), .Y(n1682) );
INVX2TS U1356 ( .A(n1165), .Y(n1699) );
NOR2X2TS U1357 ( .A(n1702), .B(intadd_391_B_0_), .Y(n1701) );
NOR3XLTS U1358 ( .A(n1277), .B(n1272), .C(n1279), .Y(enab_d_ff4_Xn) );
AOI2BB1XLTS U1359 ( .A0N(cont_var_out[0]), .A1N(cont_var_out[1]), .B0(n1273),
.Y(n1272) );
NOR3BXLTS U1360 ( .AN(n1668), .B(n1273), .C(n1279), .Y(enab_d_ff4_Zn) );
CLKAND2X2TS U1361 ( .A(n1019), .B(n1018), .Y(n1856) );
OR2X1TS U1362 ( .A(n1464), .B(n1466), .Y(
add_subt_module_FSM_barrel_shifter_load) );
NAND4XLTS U1363 ( .A(n1726), .B(n1725), .C(n1724), .D(n1983), .Y(n602) );
INVX2TS U1364 ( .A(n878), .Y(n1733) );
CLKAND2X2TS U1365 ( .A(n1672), .B(add_subt_module_Sgf_normalized_result[11]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[9]) );
CLKAND2X2TS U1366 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[7]),
.Y(n1866) );
CLKAND2X2TS U1367 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[3]),
.Y(n1867) );
CLKAND2X2TS U1368 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[6]),
.Y(n1868) );
CLKAND2X2TS U1369 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[2]),
.Y(n1865) );
CLKAND2X2TS U1370 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[10]),
.Y(n1869) );
CLKAND2X2TS U1371 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[5]),
.Y(n1870) );
CLKAND2X2TS U1372 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[9]),
.Y(n1871) );
CLKAND2X2TS U1373 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[4]),
.Y(n1872) );
CLKAND2X2TS U1374 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[12]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[10]) );
CLKAND2X2TS U1375 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[16]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[14]) );
CLKAND2X2TS U1376 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[13]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[11]) );
CLKAND2X2TS U1377 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[19]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[17]) );
CLKAND2X2TS U1378 ( .A(n1670), .B(add_subt_module_Sgf_normalized_result[18]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[16]) );
CLKAND2X2TS U1379 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[22]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[20]) );
CLKAND2X2TS U1380 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[15]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[13]) );
CLKAND2X2TS U1381 ( .A(n1574), .B(add_subt_module_Sgf_normalized_result[8]),
.Y(n1873) );
CLKAND2X2TS U1382 ( .A(n1672), .B(add_subt_module_Sgf_normalized_result[23]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[21]) );
CLKAND2X2TS U1383 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[21]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[19]) );
CLKAND2X2TS U1384 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[20]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[18]) );
CLKAND2X2TS U1385 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[17]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[15]) );
CLKAND2X2TS U1386 ( .A(n1672), .B(add_subt_module_Sgf_normalized_result[24]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[22]) );
INVX2TS U1387 ( .A(n1084), .Y(n1121) );
OR2X1TS U1388 ( .A(d_ff_Xn[24]), .B(n1024), .Y(first_mux_X[24]) );
OR2X1TS U1389 ( .A(d_ff_Xn[25]), .B(n1023), .Y(first_mux_X[25]) );
OR2X1TS U1390 ( .A(d_ff_Xn[26]), .B(n1682), .Y(first_mux_X[26]) );
CLKAND2X2TS U1391 ( .A(n1671), .B(add_subt_module_Sgf_normalized_result[14]),
.Y(add_subt_module_final_result_ieee_Module_Sgf_S_mux[12]) );
OAI32X1TS U1392 ( .A0(n1156), .A1(n1293), .A2(n1695), .B0(n1271), .B1(n1155),
.Y(n582) );
AO21XLTS U1393 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .A1(
n1537), .B0(n998), .Y(n2008) );
AOI2BB2XLTS U1394 ( .B0(n996), .B1(n1145), .A0N(n1223), .A1N(n691), .Y(n997)
);
AOI2BB1XLTS U1395 ( .A0N(n1240), .A1N(n1817), .B0(n1239), .Y(n1241) );
AOI2BB1XLTS U1396 ( .A0N(n1240), .A1N(n1809), .B0(n1232), .Y(n1233) );
MX2X1TS U1397 ( .A(add_subt_module_DMP[24]), .B(
add_subt_module_exp_oper_result[1]), .S0(n1386), .Y(n960) );
OR2X1TS U1398 ( .A(d_ff_Xn[29]), .B(n1025), .Y(first_mux_X[29]) );
OAI32X1TS U1399 ( .A0(n1158), .A1(n1293), .A2(n1708), .B0(n1163), .B1(n1157),
.Y(n585) );
OR2X1TS U1400 ( .A(d_ff_Xn[27]), .B(n1024), .Y(first_mux_X[27]) );
XOR2XLTS U1401 ( .A(n1454), .B(n1453), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[4]) );
OAI32X1TS U1402 ( .A0(n1294), .A1(n1293), .A2(n1771), .B0(n1292), .B1(n1291),
.Y(n584) );
CLKAND2X2TS U1403 ( .A(n757), .B(n756), .Y(n722) );
XOR2XLTS U1404 ( .A(n894), .B(n893), .Y(n718) );
INVX2TS U1405 ( .A(n895), .Y(n1734) );
INVX2TS U1406 ( .A(n899), .Y(n1735) );
INVX2TS U1407 ( .A(n901), .Y(n1736) );
INVX2TS U1408 ( .A(n903), .Y(n1737) );
INVX2TS U1409 ( .A(n918), .Y(n1739) );
INVX2TS U1410 ( .A(n920), .Y(n1740) );
INVX2TS U1411 ( .A(n922), .Y(n1741) );
INVX2TS U1412 ( .A(n924), .Y(n1742) );
XOR2XLTS U1413 ( .A(n926), .B(n925), .Y(n724) );
INVX2TS U1414 ( .A(n927), .Y(n1743) );
NAND3XLTS U1415 ( .A(cordic_FSM_state_reg[0]), .B(n1762), .C(n1808), .Y(
n1203) );
AOI211XLTS U1416 ( .A0(n1721), .A1(cordic_FSM_state_reg[1]), .B0(n1722),
.C0(load_cont_var), .Y(n1202) );
AO22XLTS U1417 ( .A0(n1710), .A1(d_ff3_sh_x_out[30]), .B0(n1709), .B1(
d_ff3_sh_y_out[30]), .Y(n667) );
AO21XLTS U1418 ( .A0(n1953), .A1(add_subt_module_FSM_Add_Subt_Sgf_load),
.B0(add_subt_module_FSM_selector_C), .Y(n593) );
MX2X1TS U1419 ( .A(add_subt_module_DMP[27]), .B(
add_subt_module_exp_oper_result[4]), .S0(
add_subt_module_FSM_selector_D), .Y(n951) );
AO22XLTS U1420 ( .A0(n1296), .A1(d_ff3_sh_x_out[31]), .B0(n1295), .B1(
d_ff3_sh_y_out[31]), .Y(n1297) );
OR2X1TS U1421 ( .A(n1575), .B(n1391), .Y(n595) );
MX2X1TS U1422 ( .A(add_subt_module_intDY[6]), .B(add_subt_module_intDX[6]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[6]) );
MX2X1TS U1423 ( .A(add_subt_module_intDY[10]), .B(add_subt_module_intDX[10]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[10]) );
MX2X1TS U1424 ( .A(add_subt_module_intDY[9]), .B(add_subt_module_intDX[9]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[9]) );
AO22XLTS U1425 ( .A0(n1684), .A1(d_ff_Zn[9]), .B0(n1778), .B1(d_ff1_Z[9]),
.Y(first_mux_Z[9]) );
AO22XLTS U1426 ( .A0(n1689), .A1(d_ff_Yn[9]), .B0(n1690), .B1(d_ff_Xn[9]),
.Y(mux_sal[9]) );
MX2X1TS U1427 ( .A(add_subt_module_intDY[5]), .B(add_subt_module_intDX[5]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[5]) );
AO22XLTS U1428 ( .A0(n1684), .A1(d_ff_Zn[5]), .B0(n1778), .B1(d_ff1_Z[5]),
.Y(first_mux_Z[5]) );
AO22XLTS U1429 ( .A0(n1689), .A1(d_ff_Yn[5]), .B0(n1691), .B1(d_ff_Xn[5]),
.Y(mux_sal[5]) );
OR2X1TS U1430 ( .A(d_ff_Xn[5]), .B(n1025), .Y(first_mux_X[5]) );
MX2X1TS U1431 ( .A(add_subt_module_intDY[1]), .B(add_subt_module_intDX[1]),
.S0(n1580), .Y(add_subt_module_Oper_Start_in_module_intM[1]) );
AO22XLTS U1432 ( .A0(n1686), .A1(d_ff_Zn[1]), .B0(n1778), .B1(d_ff1_Z[1]),
.Y(first_mux_Z[1]) );
AO22XLTS U1433 ( .A0(n1689), .A1(d_ff_Yn[1]), .B0(n1862), .B1(d_ff_Xn[1]),
.Y(mux_sal[1]) );
OR2X1TS U1434 ( .A(d_ff_Xn[1]), .B(n1023), .Y(first_mux_X[1]) );
MX2X1TS U1435 ( .A(add_subt_module_intDY[4]), .B(add_subt_module_intDX[4]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[4]) );
AO22XLTS U1436 ( .A0(n1684), .A1(d_ff_Zn[4]), .B0(n1685), .B1(d_ff1_Z[4]),
.Y(first_mux_Z[4]) );
AO22XLTS U1437 ( .A0(n1689), .A1(d_ff_Yn[4]), .B0(n1691), .B1(d_ff_Xn[4]),
.Y(mux_sal[4]) );
MX2X1TS U1438 ( .A(add_subt_module_intDY[0]), .B(add_subt_module_intDX[0]),
.S0(n1580), .Y(add_subt_module_Oper_Start_in_module_intM[0]) );
AO22XLTS U1439 ( .A0(n1683), .A1(d_ff_Zn[0]), .B0(n1685), .B1(d_ff1_Z[0]),
.Y(first_mux_Z[0]) );
AO22XLTS U1440 ( .A0(n1689), .A1(d_ff_Yn[0]), .B0(n1695), .B1(d_ff_Xn[0]),
.Y(mux_sal[0]) );
MX2X1TS U1441 ( .A(add_subt_module_intDY[8]), .B(add_subt_module_intDX[8]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[8]) );
AO22XLTS U1442 ( .A0(n1684), .A1(d_ff_Zn[8]), .B0(n1685), .B1(d_ff1_Z[8]),
.Y(first_mux_Z[8]) );
AO22XLTS U1443 ( .A0(n1689), .A1(d_ff_Yn[8]), .B0(n1690), .B1(d_ff_Xn[8]),
.Y(mux_sal[8]) );
MX2X1TS U1444 ( .A(add_subt_module_intDY[3]), .B(add_subt_module_intDX[3]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[3]) );
AO22XLTS U1445 ( .A0(n1684), .A1(d_ff_Zn[3]), .B0(n1778), .B1(d_ff1_Z[3]),
.Y(first_mux_Z[3]) );
AO22XLTS U1446 ( .A0(n1689), .A1(d_ff_Yn[3]), .B0(n1691), .B1(d_ff_Xn[3]),
.Y(mux_sal[3]) );
MX2X1TS U1447 ( .A(add_subt_module_intDY[7]), .B(add_subt_module_intDX[7]),
.S0(n1547), .Y(add_subt_module_Oper_Start_in_module_intM[7]) );
AO22XLTS U1448 ( .A0(n1684), .A1(d_ff_Zn[7]), .B0(n1778), .B1(d_ff1_Z[7]),
.Y(first_mux_Z[7]) );
AO22XLTS U1449 ( .A0(n1689), .A1(d_ff_Yn[7]), .B0(n1690), .B1(d_ff_Xn[7]),
.Y(mux_sal[7]) );
OR2X1TS U1450 ( .A(d_ff_Xn[7]), .B(n1024), .Y(first_mux_X[7]) );
MX2X1TS U1451 ( .A(add_subt_module_intDY[2]), .B(add_subt_module_intDX[2]),
.S0(n1580), .Y(add_subt_module_Oper_Start_in_module_intM[2]) );
AO22XLTS U1452 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[2]), .B0(n1685), .B1(
d_ff1_Z[2]), .Y(first_mux_Z[2]) );
AO22XLTS U1453 ( .A0(n1689), .A1(d_ff_Yn[2]), .B0(n1862), .B1(d_ff_Xn[2]),
.Y(mux_sal[2]) );
OR2X1TS U1454 ( .A(d_ff_Xn[2]), .B(n1682), .Y(first_mux_X[2]) );
AO22XLTS U1455 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[31]), .B0(n1706), .B1(
d_ff1_Z[31]), .Y(first_mux_Z[31]) );
AO22XLTS U1456 ( .A0(sel_mux_3_reg), .A1(d_ff_Yn[31]), .B0(n1695), .B1(
d_ff_Xn[31]), .Y(mux_sal[31]) );
NAND3BXLTS U1457 ( .AN(add_subt_module_Add_Subt_result[12]), .B(n1494), .C(
add_subt_module_Add_Subt_result[11]), .Y(n1495) );
AOI31XLTS U1458 ( .A0(n1478), .A1(n1477), .A2(
add_subt_module_Add_Subt_result[5]), .B0(n1476), .Y(n1488) );
AO22XLTS U1459 ( .A0(sel_mux_3_reg), .A1(d_ff_Yn[30]), .B0(n1695), .B1(
d_ff_Xn[30]), .Y(mux_sal[30]) );
AO22XLTS U1460 ( .A0(n1694), .A1(d_ff_Yn[29]), .B0(n1695), .B1(d_ff_Xn[29]),
.Y(mux_sal[29]) );
AO22XLTS U1461 ( .A0(n1694), .A1(d_ff_Yn[28]), .B0(n1695), .B1(d_ff_Xn[28]),
.Y(mux_sal[28]) );
AO22XLTS U1462 ( .A0(n1694), .A1(d_ff_Yn[27]), .B0(n1695), .B1(d_ff_Xn[27]),
.Y(mux_sal[27]) );
AO22XLTS U1463 ( .A0(n1694), .A1(d_ff_Yn[26]), .B0(n1695), .B1(d_ff_Xn[26]),
.Y(mux_sal[26]) );
AO22XLTS U1464 ( .A0(n1694), .A1(d_ff_Yn[25]), .B0(n1693), .B1(d_ff_Xn[25]),
.Y(mux_sal[25]) );
AO22XLTS U1465 ( .A0(n1694), .A1(d_ff_Yn[24]), .B0(n1693), .B1(d_ff_Xn[24]),
.Y(mux_sal[24]) );
AO22XLTS U1466 ( .A0(n1694), .A1(d_ff_Yn[23]), .B0(n1693), .B1(d_ff_Xn[23]),
.Y(mux_sal[23]) );
AO22XLTS U1467 ( .A0(n1694), .A1(d_ff_Yn[22]), .B0(n1693), .B1(d_ff_Xn[22]),
.Y(mux_sal[22]) );
AO22XLTS U1468 ( .A0(n1694), .A1(d_ff_Yn[21]), .B0(n1693), .B1(d_ff_Xn[21]),
.Y(mux_sal[21]) );
AO22XLTS U1469 ( .A0(n1694), .A1(d_ff_Yn[20]), .B0(n1693), .B1(d_ff_Xn[20]),
.Y(mux_sal[20]) );
AO22XLTS U1470 ( .A0(n1692), .A1(d_ff_Yn[19]), .B0(n1693), .B1(d_ff_Xn[19]),
.Y(mux_sal[19]) );
AO22XLTS U1471 ( .A0(n1692), .A1(d_ff_Yn[18]), .B0(n1693), .B1(d_ff_Xn[18]),
.Y(mux_sal[18]) );
AO22XLTS U1472 ( .A0(n1692), .A1(d_ff_Yn[17]), .B0(n1693), .B1(d_ff_Xn[17]),
.Y(mux_sal[17]) );
AO22XLTS U1473 ( .A0(n1692), .A1(d_ff_Yn[16]), .B0(n1693), .B1(d_ff_Xn[16]),
.Y(mux_sal[16]) );
AO22XLTS U1474 ( .A0(n1692), .A1(d_ff_Yn[15]), .B0(n1690), .B1(d_ff_Xn[15]),
.Y(mux_sal[15]) );
AO22XLTS U1475 ( .A0(n1692), .A1(d_ff_Yn[14]), .B0(n1690), .B1(d_ff_Xn[14]),
.Y(mux_sal[14]) );
AO22XLTS U1476 ( .A0(n1692), .A1(d_ff_Yn[13]), .B0(n1690), .B1(d_ff_Xn[13]),
.Y(mux_sal[13]) );
AO22XLTS U1477 ( .A0(n1692), .A1(d_ff_Yn[12]), .B0(n1690), .B1(d_ff_Xn[12]),
.Y(mux_sal[12]) );
AO22XLTS U1478 ( .A0(n1692), .A1(d_ff_Yn[11]), .B0(n1690), .B1(d_ff_Xn[11]),
.Y(mux_sal[11]) );
AO22XLTS U1479 ( .A0(n1692), .A1(d_ff_Yn[10]), .B0(n1690), .B1(d_ff_Xn[10]),
.Y(mux_sal[10]) );
AO22XLTS U1480 ( .A0(n1689), .A1(d_ff_Yn[6]), .B0(n1690), .B1(d_ff_Xn[6]),
.Y(mux_sal[6]) );
OR2X1TS U1481 ( .A(d_ff_Xn[28]), .B(n1682), .Y(first_mux_X[28]) );
OR2X1TS U1482 ( .A(d_ff_Xn[19]), .B(n1024), .Y(first_mux_X[19]) );
OR2X1TS U1483 ( .A(d_ff_Xn[17]), .B(n1025), .Y(first_mux_X[17]) );
OR2X1TS U1484 ( .A(d_ff_Xn[16]), .B(n1682), .Y(first_mux_X[16]) );
OR2X1TS U1485 ( .A(d_ff_Xn[14]), .B(n1023), .Y(first_mux_X[14]) );
OR2X1TS U1486 ( .A(d_ff_Xn[13]), .B(n1025), .Y(first_mux_X[13]) );
OR2X1TS U1487 ( .A(d_ff_Xn[12]), .B(n1025), .Y(first_mux_X[12]) );
OR2X1TS U1488 ( .A(d_ff_Xn[6]), .B(n1023), .Y(first_mux_X[6]) );
AO22XLTS U1489 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[30]), .B0(n1706), .B1(
d_ff1_Z[30]), .Y(first_mux_Z[30]) );
AO22XLTS U1490 ( .A0(n1688), .A1(d_ff_Zn[29]), .B0(n1687), .B1(d_ff1_Z[29]),
.Y(first_mux_Z[29]) );
AO22XLTS U1491 ( .A0(n1688), .A1(d_ff_Zn[28]), .B0(n1706), .B1(d_ff1_Z[28]),
.Y(first_mux_Z[28]) );
AO22XLTS U1492 ( .A0(n1688), .A1(d_ff_Zn[27]), .B0(n1687), .B1(d_ff1_Z[27]),
.Y(first_mux_Z[27]) );
AO22XLTS U1493 ( .A0(n1688), .A1(d_ff_Zn[26]), .B0(n1706), .B1(d_ff1_Z[26]),
.Y(first_mux_Z[26]) );
AO22XLTS U1494 ( .A0(n1688), .A1(d_ff_Zn[25]), .B0(n1687), .B1(d_ff1_Z[25]),
.Y(first_mux_Z[25]) );
AO22XLTS U1495 ( .A0(n1688), .A1(d_ff_Zn[24]), .B0(n1706), .B1(d_ff1_Z[24]),
.Y(first_mux_Z[24]) );
AO22XLTS U1496 ( .A0(n1688), .A1(d_ff_Zn[23]), .B0(n1687), .B1(d_ff1_Z[23]),
.Y(first_mux_Z[23]) );
AO21XLTS U1497 ( .A0(intadd_392_n1), .A1(d_ff2_Y[27]), .B0(n1729), .Y(
sh_exp_y[4]) );
OAI21XLTS U1498 ( .A0(n1705), .A1(n1804), .B0(intadd_391_CI), .Y(sh_exp_x[0]) );
AO21XLTS U1499 ( .A0(intadd_391_n1), .A1(d_ff2_X[27]), .B0(n1732), .Y(
sh_exp_x[4]) );
AO22XLTS U1500 ( .A0(data_out_LUT[8]), .A1(n1701), .B0(intadd_391_B_0_),
.B1(n1700), .Y(data_out_LUT[2]) );
AOI222X1TS U1501 ( .A0(n705), .A1(cont_iter_out[1]), .B0(n705), .B1(n1705),
.C0(cont_iter_out[3]), .C1(intadd_391_B_0_), .Y(data_out_LUT[4]) );
NAND3XLTS U1502 ( .A(n1705), .B(n1781), .C(intadd_391_B_0_), .Y(n1698) );
OR2X1TS U1503 ( .A(data_out_LUT[20]), .B(n1163), .Y(data_out_LUT[11]) );
AO21XLTS U1504 ( .A0(n1699), .A1(data_out_LUT[8]), .B0(data_out_LUT[16]),
.Y(data_out_LUT[9]) );
OAI32X1TS U1505 ( .A0(intadd_391_B_0_), .A1(cont_iter_out[3]), .A2(n1702),
.B0(n978), .B1(n1703), .Y(data_out_LUT[10]) );
AO21XLTS U1506 ( .A0(n1699), .A1(data_out_LUT[8]), .B0(data_out_LUT[18]),
.Y(data_out_LUT[21]) );
AOI2BB2XLTS U1507 ( .B0(n1702), .B1(data_out_LUT[22]), .A0N(data_out_LUT[22]), .A1N(n1702), .Y(data_out_LUT[23]) );
AOI221XLTS U1508 ( .A0(cont_iter_out[2]), .A1(n1701), .B0(data_out_LUT[8]),
.B1(n1020), .C0(n680), .Y(n1986) );
AO22XLTS U1509 ( .A0(n1684), .A1(d_ff_Zn[12]), .B0(n1687), .B1(d_ff1_Z[12]),
.Y(first_mux_Z[12]) );
AO22XLTS U1510 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[10]), .B0(n1687), .B1(
d_ff1_Z[10]), .Y(first_mux_Z[10]) );
AO22XLTS U1511 ( .A0(n1686), .A1(d_ff_Zn[14]), .B0(n1687), .B1(d_ff1_Z[14]),
.Y(first_mux_Z[14]) );
AO22XLTS U1512 ( .A0(sel_mux_1_reg), .A1(d_ff_Zn[11]), .B0(n1685), .B1(
d_ff1_Z[11]), .Y(first_mux_Z[11]) );
AO22XLTS U1513 ( .A0(n1686), .A1(d_ff_Zn[17]), .B0(n1685), .B1(d_ff1_Z[17]),
.Y(first_mux_Z[17]) );
AO22XLTS U1514 ( .A0(n1686), .A1(d_ff_Zn[16]), .B0(n1706), .B1(d_ff1_Z[16]),
.Y(first_mux_Z[16]) );
AO22XLTS U1515 ( .A0(n1688), .A1(d_ff_Zn[20]), .B0(n1687), .B1(d_ff1_Z[20]),
.Y(first_mux_Z[20]) );
AO22XLTS U1516 ( .A0(n1684), .A1(d_ff_Zn[13]), .B0(n1685), .B1(d_ff1_Z[13]),
.Y(first_mux_Z[13]) );
AO22XLTS U1517 ( .A0(n1684), .A1(d_ff_Zn[6]), .B0(n1685), .B1(d_ff1_Z[6]),
.Y(first_mux_Z[6]) );
AO22XLTS U1518 ( .A0(n1688), .A1(d_ff_Zn[21]), .B0(n1687), .B1(d_ff1_Z[21]),
.Y(first_mux_Z[21]) );
AO22XLTS U1519 ( .A0(n1686), .A1(d_ff_Zn[19]), .B0(n1685), .B1(d_ff1_Z[19]),
.Y(first_mux_Z[19]) );
AO22XLTS U1520 ( .A0(n1686), .A1(d_ff_Zn[18]), .B0(n1687), .B1(d_ff1_Z[18]),
.Y(first_mux_Z[18]) );
AO22XLTS U1521 ( .A0(n1686), .A1(d_ff_Zn[15]), .B0(n1685), .B1(d_ff1_Z[15]),
.Y(first_mux_Z[15]) );
AO22XLTS U1522 ( .A0(n1688), .A1(d_ff_Zn[22]), .B0(n1706), .B1(d_ff1_Z[22]),
.Y(first_mux_Z[22]) );
MX2X1TS U1523 ( .A(add_subt_module_DMP[30]), .B(
add_subt_module_exp_oper_result[7]), .S0(n933), .Y(n966) );
CLKAND2X2TS U1524 ( .A(n690), .B(add_subt_module_DmP[30]), .Y(n931) );
INVX2TS U1525 ( .A(add_subt_module_FSM_selector_B[0]), .Y(n1534) );
NOR2X2TS U1526 ( .A(n1133), .B(n737), .Y(n1656) );
AND3X4TS U1527 ( .A(n1721), .B(n1762), .C(n1980), .Y(n716) );
BUFX3TS U1528 ( .A(n716), .Y(n1011) );
INVX2TS U1529 ( .A(n1062), .Y(n1657) );
INVX2TS U1530 ( .A(add_subt_module_FSM_selector_B[0]), .Y(n692) );
NOR3X2TS U1531 ( .A(n1953), .B(n1638), .C(add_subt_module_add_overflow_flag),
.Y(n1550) );
INVX2TS U1532 ( .A(n1546), .Y(n1525) );
CLKINVX3TS U1533 ( .A(n1012), .Y(n1918) );
INVX2TS U1534 ( .A(cordic_FSM_state_reg[2]), .Y(n684) );
INVX2TS U1535 ( .A(cont_iter_out[1]), .Y(n686) );
CLKINVX3TS U1536 ( .A(n1010), .Y(n1920) );
INVX2TS U1537 ( .A(n1011), .Y(n1915) );
INVX2TS U1538 ( .A(n1293), .Y(n1926) );
INVX2TS U1539 ( .A(n1010), .Y(n687) );
INVX2TS U1540 ( .A(n1010), .Y(n688) );
INVX2TS U1541 ( .A(n725), .Y(n689) );
INVX2TS U1542 ( .A(n1546), .Y(n691) );
INVX2TS U1543 ( .A(n692), .Y(n693) );
INVX2TS U1544 ( .A(n692), .Y(n694) );
INVX2TS U1545 ( .A(n1135), .Y(n695) );
INVX2TS U1546 ( .A(n1135), .Y(n696) );
INVX2TS U1547 ( .A(n1135), .Y(n697) );
INVX2TS U1548 ( .A(n1657), .Y(n698) );
INVX2TS U1549 ( .A(n698), .Y(n699) );
INVX2TS U1550 ( .A(n698), .Y(n700) );
INVX2TS U1551 ( .A(n1656), .Y(n701) );
INVX2TS U1552 ( .A(n701), .Y(n703) );
AOI22X2TS U1553 ( .A0(n1602), .A1(n1136), .B0(n1124), .B1(n1142), .Y(n1170)
);
AOI22X2TS U1554 ( .A0(n1602), .A1(n1138), .B0(n1128), .B1(n1142), .Y(n1169)
);
AOI22X2TS U1555 ( .A0(n1602), .A1(n1137), .B0(n1136), .B1(n1142), .Y(n1603)
);
NOR2X4TS U1556 ( .A(sel_mux_2_reg[1]), .B(sel_mux_2_reg[0]), .Y(n1709) );
OAI221X1TS U1557 ( .A0(n1802), .A1(add_subt_module_intDY[28]), .B0(n1756),
.B1(add_subt_module_intDY[27]), .C0(n1108), .Y(n1111) );
OAI221X1TS U1558 ( .A0(n1752), .A1(add_subt_module_intDY[20]), .B0(n1789),
.B1(add_subt_module_intDY[19]), .C0(n1100), .Y(n1103) );
BUFX3TS U1559 ( .A(n1011), .Y(n1293) );
BUFX3TS U1560 ( .A(n1011), .Y(n1010) );
CLKINVX3TS U1561 ( .A(n1011), .Y(n1907) );
CLKINVX3TS U1562 ( .A(n1011), .Y(n1906) );
AOI211X1TS U1563 ( .A0(n1465), .A1(n1784), .B0(n1464), .C0(
add_subt_module_FSM_exp_operation_load_diff), .Y(n1467) );
NOR4X2TS U1564 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(
add_subt_module_FS_Module_state_reg[2]), .C(
add_subt_module_FS_Module_state_reg[1]), .D(n1953), .Y(n669) );
AOI211X1TS U1565 ( .A0(n1762), .A1(n1723), .B0(n1722), .C0(n1721), .Y(n1726)
);
OAI22X1TS U1566 ( .A0(beg_fsm_cordic), .A1(n1720), .B0(
cordic_FSM_state_reg[0]), .B1(n1719), .Y(n1723) );
OAI2BB2XLTS U1567 ( .B0(n1330), .B1(n1337), .A0N(n1329), .A1N(n1328), .Y(
n1333) );
OAI221X1TS U1568 ( .A0(n1782), .A1(add_subt_module_intDY[11]), .B0(n1760),
.B1(add_subt_module_intDY[10]), .C0(n1328), .Y(n1095) );
AOI22X2TS U1569 ( .A0(n1782), .A1(add_subt_module_intDY[11]), .B0(n1760),
.B1(add_subt_module_intDY[10]), .Y(n1328) );
AOI22X2TS U1570 ( .A0(n1602), .A1(n1601), .B0(n1600), .B1(n1658), .Y(n1612)
);
AOI22X2TS U1571 ( .A0(n1602), .A1(n1596), .B0(n1595), .B1(n1658), .Y(n1609)
);
AOI22X2TS U1572 ( .A0(n1602), .A1(n1139), .B0(n1138), .B1(n1658), .Y(n1606)
);
AOI22X2TS U1573 ( .A0(n1661), .A1(n744), .B0(n1596), .B1(n1658), .Y(n1619)
);
AOI22X2TS U1574 ( .A0(n1661), .A1(n748), .B0(n1139), .B1(n1658), .Y(n1616)
);
AOI22X2TS U1575 ( .A0(n1661), .A1(n1628), .B0(n748), .B1(n1658), .Y(n1622)
);
AOI22X2TS U1576 ( .A0(n1661), .A1(n746), .B0(n1601), .B1(n1658), .Y(n1623)
);
AOI22X2TS U1577 ( .A0(n1602), .A1(n750), .B0(n1137), .B1(n1658), .Y(n1613)
);
AOI22X2TS U1578 ( .A0(n1661), .A1(n755), .B0(n750), .B1(n1658), .Y(n1624) );
NOR2X1TS U1579 ( .A(n1278), .B(n1271), .Y(n1277) );
NOR2X4TS U1580 ( .A(n1245), .B(n1225), .Y(n1563) );
AOI21X4TS U1581 ( .A0(n1744), .A1(n1783), .B0(
add_subt_module_FSM_selector_B[1]), .Y(n1245) );
AOI221XLTS U1582 ( .A0(cont_var_out[1]), .A1(n1276), .B0(n682), .B1(n1275),
.C0(load_cont_var), .Y(n590) );
CLKINVX3TS U1583 ( .A(n1010), .Y(n1931) );
CLKINVX3TS U1584 ( .A(n716), .Y(n1934) );
CLKINVX3TS U1585 ( .A(n1012), .Y(n1921) );
CLKINVX3TS U1586 ( .A(n716), .Y(n1912) );
CLKINVX3TS U1587 ( .A(n716), .Y(n1903) );
CLKINVX3TS U1588 ( .A(n716), .Y(n1932) );
CLKINVX3TS U1589 ( .A(n716), .Y(n1935) );
CLKINVX3TS U1590 ( .A(n716), .Y(n1904) );
CLKINVX3TS U1591 ( .A(n1293), .Y(n1908) );
CLKINVX3TS U1592 ( .A(n1293), .Y(n1916) );
CLKINVX3TS U1593 ( .A(n1293), .Y(n1913) );
CLKINVX3TS U1594 ( .A(n1011), .Y(n1905) );
CLKINVX3TS U1595 ( .A(n1011), .Y(n1922) );
INVX2TS U1596 ( .A(n1012), .Y(n704) );
CLKINVX3TS U1597 ( .A(n1012), .Y(n1937) );
CLKINVX3TS U1598 ( .A(n1012), .Y(n1938) );
CLKINVX3TS U1599 ( .A(n1012), .Y(n1939) );
BUFX3TS U1600 ( .A(n716), .Y(n1012) );
CLKINVX3TS U1601 ( .A(n1010), .Y(n1927) );
CLKINVX3TS U1602 ( .A(n1010), .Y(n1925) );
CLKINVX3TS U1603 ( .A(n1010), .Y(n1933) );
CLKINVX3TS U1604 ( .A(n1010), .Y(n1928) );
CLKINVX3TS U1605 ( .A(n1010), .Y(n1929) );
CLKINVX3TS U1606 ( .A(n1010), .Y(n1930) );
CLKINVX3TS U1607 ( .A(n1293), .Y(n1924) );
CLKINVX3TS U1608 ( .A(n1012), .Y(n1909) );
CLKINVX3TS U1609 ( .A(n1011), .Y(n1910) );
CLKINVX3TS U1610 ( .A(n1012), .Y(n1911) );
CLKINVX3TS U1611 ( .A(n716), .Y(n1917) );
CLKINVX3TS U1612 ( .A(n716), .Y(n1914) );
AOI22X2TS U1613 ( .A0(n1602), .A1(n1600), .B0(n1589), .B1(n1142), .Y(n1597)
);
OAI221X1TS U1614 ( .A0(n1798), .A1(add_subt_module_intDY[3]), .B0(n1759),
.B1(add_subt_module_intDY[2]), .C0(n1086), .Y(n1089) );
OAI21X2TS U1615 ( .A0(n1435), .A1(n784), .B0(n783), .Y(n842) );
OAI221X1TS U1616 ( .A0(n1813), .A1(add_subt_module_intDY[7]), .B0(n1746),
.B1(add_subt_module_intDY[6]), .C0(n1317), .Y(n1097) );
OAI221X1TS U1617 ( .A0(n1754), .A1(add_subt_module_intDY[24]), .B0(n1795),
.B1(add_subt_module_intDY[23]), .C0(n1106), .Y(n1113) );
OAI221X1TS U1618 ( .A0(n1807), .A1(add_subt_module_intDY[16]), .B0(n1791),
.B1(add_subt_module_intDY[15]), .C0(n1098), .Y(n1105) );
BUFX3TS U1619 ( .A(n678), .Y(n1654) );
OAI21X1TS U1620 ( .A0(n1400), .A1(n1394), .B0(n1397), .Y(n1396) );
AOI222X1TS U1621 ( .A0(n1046), .A1(d_ff2_Z[24]), .B0(n1042), .B1(d_ff2_Y[24]), .C0(n1041), .C1(d_ff2_X[24]), .Y(n1965) );
AOI222X1TS U1622 ( .A0(n1046), .A1(d_ff2_Z[25]), .B0(n1042), .B1(d_ff2_Y[25]), .C0(n1041), .C1(d_ff2_X[25]), .Y(n1964) );
AOI222X1TS U1623 ( .A0(n1046), .A1(d_ff2_Z[26]), .B0(n1042), .B1(d_ff2_Y[26]), .C0(n1041), .C1(d_ff2_X[26]), .Y(n1963) );
BUFX3TS U1624 ( .A(n1038), .Y(n1028) );
NOR2X4TS U1625 ( .A(n1812), .B(sel_mux_2_reg[0]), .Y(n1038) );
AOI222X1TS U1626 ( .A0(n684), .A1(cordic_FSM_state_reg[1]), .B0(n684), .B1(
n1273), .C0(n1762), .C1(n680), .Y(n1270) );
AOI22X2TS U1627 ( .A0(n1661), .A1(n1639), .B0(n746), .B1(n1645), .Y(n1635)
);
AOI22X2TS U1628 ( .A0(n1661), .A1(n1632), .B0(n744), .B1(n1645), .Y(n1629)
);
AOI22X2TS U1629 ( .A0(n1661), .A1(n1659), .B0(n1628), .B1(n1645), .Y(n1649)
);
AOI22X2TS U1630 ( .A0(n1661), .A1(n1646), .B0(n755), .B1(n1645), .Y(n1642)
);
INVX4TS U1631 ( .A(n1068), .Y(n1645) );
AOI21X2TS U1632 ( .A0(n986), .A1(n1549), .B0(n1548), .Y(n1569) );
NOR2X4TS U1633 ( .A(n982), .B(n1786), .Y(n1145) );
BUFX3TS U1634 ( .A(n1013), .Y(n1014) );
INVX2TS U1635 ( .A(sel_mux_3_reg), .Y(n1691) );
ADDFHX2TS U1636 ( .A(n961), .B(n960), .CI(n959), .CO(n956), .S(
add_subt_module_Exp_Operation_Module_Data_S[1]) );
AOI32X4TS U1637 ( .A0(d_ff1_operation_out), .A1(n681), .A2(
d_ff1_shift_region_flag_out[1]), .B0(n1696), .B1(
d_ff1_shift_region_flag_out[0]), .Y(n1697) );
AOI222X1TS U1638 ( .A0(n1046), .A1(d_ff2_Z[29]), .B0(n1042), .B1(d_ff2_Y[29]), .C0(n1041), .C1(d_ff2_X[29]), .Y(n1960) );
NOR4X2TS U1639 ( .A(n1745), .B(n1748), .C(n1784), .D(
add_subt_module_FS_Module_state_reg[0]), .Y(n1718) );
NOR2X2TS U1640 ( .A(overflow_flag), .B(underflow_flag), .Y(n1670) );
NOR2X4TS U1641 ( .A(n1220), .B(n1003), .Y(n1540) );
CLKBUFX2TS U1642 ( .A(n1703), .Y(n705) );
NAND2X2TS U1643 ( .A(n1703), .B(cont_iter_out[3]), .Y(data_out_LUT[22]) );
BUFX3TS U1644 ( .A(sel_mux_1_reg), .Y(n1686) );
BUFX3TS U1645 ( .A(n727), .Y(n706) );
CLKBUFX2TS U1646 ( .A(n727), .Y(n1665) );
AOI222X1TS U1647 ( .A0(n1046), .A1(d_ff2_Z[27]), .B0(n1045), .B1(d_ff2_Y[27]), .C0(n1044), .C1(d_ff2_X[27]), .Y(n1962) );
NOR2X4TS U1648 ( .A(n995), .B(n994), .Y(n1568) );
OR3X1TS U1649 ( .A(d_ff2_X[28]), .B(d_ff2_X[27]), .C(intadd_391_n1), .Y(
n1731) );
OAI21XLTS U1650 ( .A0(n1213), .A1(add_subt_module_Add_Subt_result[25]), .B0(
n1212), .Y(n1214) );
NOR2X4TS U1651 ( .A(n1005), .B(n1564), .Y(n1539) );
NOR3X4TS U1652 ( .A(n1783), .B(n1225), .C(add_subt_module_FSM_selector_B[1]),
.Y(n1564) );
NOR2X2TS U1653 ( .A(n1481), .B(add_subt_module_Add_Subt_result[13]), .Y(
n1494) );
NOR2X1TS U1654 ( .A(n1208), .B(add_subt_module_Add_Subt_result[3]), .Y(n1255) );
OAI21XLTS U1655 ( .A0(add_subt_module_Add_Subt_result[3]), .A1(n1485), .B0(
n1484), .Y(n1486) );
NOR2X4TS U1656 ( .A(sel_mux_2_reg[1]), .B(n1771), .Y(n1710) );
AOI22X2TS U1657 ( .A0(n1254), .A1(add_subt_module_Add_Subt_result[10]), .B0(
n1673), .B1(add_subt_module_Add_Subt_result[18]), .Y(n1497) );
NOR2X2TS U1658 ( .A(cont_var_out[0]), .B(n682), .Y(n1668) );
NAND3X2TS U1659 ( .A(cordic_FSM_state_reg[2]), .B(n1762), .C(n680), .Y(n1983) );
AOI32X1TS U1660 ( .A0(cordic_FSM_state_reg[0]), .A1(n684), .A2(n980), .B0(
cordic_FSM_state_reg[2]), .B1(n979), .Y(n981) );
XNOR2X1TS U1661 ( .A(n1178), .B(n823), .Y(n707) );
XNOR2X1TS U1662 ( .A(n820), .B(n819), .Y(n708) );
XNOR2X1TS U1663 ( .A(n883), .B(n882), .Y(n709) );
XNOR2X1TS U1664 ( .A(n809), .B(n808), .Y(n712) );
XNOR2X1TS U1665 ( .A(n897), .B(n896), .Y(n717) );
XNOR2X1TS U1666 ( .A(n888), .B(n887), .Y(n719) );
XNOR2X1TS U1667 ( .A(n876), .B(n875), .Y(n720) );
AND2X2TS U1668 ( .A(n690), .B(n988), .Y(n721) );
XNOR2X1TS U1669 ( .A(n1368), .B(n862), .Y(n723) );
BUFX3TS U1670 ( .A(n1583), .Y(n1547) );
NOR2XLTS U1671 ( .A(n1344), .B(add_subt_module_intDY[16]), .Y(n1345) );
OR2X1TS U1672 ( .A(add_subt_module_Sgf_normalized_result[2]), .B(n1390), .Y(
n761) );
INVX4TS U1673 ( .A(n1395), .Y(n1375) );
NOR2X1TS U1674 ( .A(n827), .B(n838), .Y(n841) );
OAI211XLTS U1675 ( .A0(n1526), .A1(n1550), .B0(n1568), .C0(n1226), .Y(n1227)
);
INVX2TS U1676 ( .A(n1532), .Y(n1516) );
OR3X1TS U1677 ( .A(d_ff2_Y[28]), .B(d_ff2_Y[27]), .C(intadd_392_n1), .Y(
n1728) );
INVX2TS U1678 ( .A(n905), .Y(n1738) );
OAI21XLTS U1679 ( .A0(n1027), .A1(n1749), .B0(n1026), .Y(n597) );
OR2X1TS U1680 ( .A(d_ff_Xn[3]), .B(n1706), .Y(first_mux_X[3]) );
OR2X1TS U1681 ( .A(d_ff_Xn[20]), .B(n1706), .Y(first_mux_X[20]) );
OR2X1TS U1682 ( .A(d_ff_Xn[10]), .B(n1706), .Y(first_mux_X[10]) );
OAI21XLTS U1683 ( .A0(n1705), .A1(n1803), .B0(intadd_392_CI), .Y(sh_exp_y[0]) );
NOR3XLTS U1684 ( .A(n1276), .B(load_cont_var), .C(n1274), .Y(n591) );
NOR3XLTS U1685 ( .A(n684), .B(n685), .C(n1021), .Y(ready_cordic) );
NOR2X2TS U1686 ( .A(n1534), .B(add_subt_module_FSM_selector_B[1]), .Y(n935)
);
NAND2X1TS U1687 ( .A(n935), .B(add_subt_module_LZA_output[1]), .Y(n940) );
NAND2X1TS U1688 ( .A(n690), .B(add_subt_module_exp_oper_result[1]), .Y(n726)
);
AOI22X1TS U1689 ( .A0(n935), .A1(add_subt_module_LZA_output[0]), .B0(
add_subt_module_FSM_selector_B[1]), .B1(n1534), .Y(n942) );
OAI2BB1X2TS U1690 ( .A0N(add_subt_module_exp_oper_result[0]), .A1N(n679),
.B0(n942), .Y(n737) );
NAND2X2TS U1691 ( .A(n1133), .B(n737), .Y(n1590) );
INVX2TS U1692 ( .A(n1590), .Y(n727) );
NAND2X1TS U1693 ( .A(n935), .B(add_subt_module_LZA_output[2]), .Y(n938) );
NAND2X1TS U1694 ( .A(n690), .B(add_subt_module_exp_oper_result[2]), .Y(n728)
);
AND2X2TS U1695 ( .A(n938), .B(n728), .Y(n1068) );
BUFX3TS U1696 ( .A(n1068), .Y(n1661) );
NOR2X2TS U1697 ( .A(n1745), .B(add_subt_module_FS_Module_state_reg[1]), .Y(
n1019) );
BUFX3TS U1698 ( .A(n1779), .Y(n1638) );
INVX2TS U1699 ( .A(n1058), .Y(n730) );
NAND2X2TS U1700 ( .A(n730), .B(n1786), .Y(n1062) );
NAND2X2TS U1701 ( .A(n1062), .B(add_subt_module_FSM_selector_C), .Y(n1135)
);
BUFX3TS U1702 ( .A(n1779), .Y(n1140) );
AOI21X1TS U1703 ( .A0(add_subt_module_Add_Subt_result[11]), .A1(n697), .B0(
n731), .Y(n744) );
OAI2BB2XLTS U1704 ( .B0(n1062), .B1(n1805), .A0N(add_subt_module_DmP[13]),
.A1N(n1140), .Y(n732) );
AOI21X1TS U1705 ( .A0(n696), .A1(add_subt_module_Add_Subt_result[15]), .B0(
n732), .Y(n1596) );
INVX2TS U1706 ( .A(n1133), .Y(n1065) );
OR2X2TS U1707 ( .A(n1065), .B(n737), .Y(n1588) );
INVX2TS U1708 ( .A(n1588), .Y(n1663) );
AOI22X1TS U1709 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[15]), .B0(
add_subt_module_DmP[8]), .B1(n1638), .Y(n733) );
OA21XLTS U1710 ( .A0(n1805), .A1(n1135), .B0(n733), .Y(n746) );
AOI21X1TS U1711 ( .A0(add_subt_module_Add_Subt_result[14]), .A1(n695), .B0(
n734), .Y(n1601) );
AOI22X1TS U1712 ( .A0(n1665), .A1(n1619), .B0(n1650), .B1(n1623), .Y(n741)
);
AOI22X1TS U1713 ( .A0(n699), .A1(add_subt_module_Add_Subt_result[13]), .B0(
add_subt_module_DmP[10]), .B1(n1638), .Y(n735) );
OA21XLTS U1714 ( .A0(n1811), .A1(n1135), .B0(n735), .Y(n748) );
AOI21X1TS U1715 ( .A0(add_subt_module_Add_Subt_result[16]), .A1(n696), .B0(
n736), .Y(n1139) );
BUFX3TS U1716 ( .A(n1068), .Y(n1602) );
OAI2BB2XLTS U1717 ( .B0(n1062), .B1(n1811), .A0N(add_subt_module_DmP[11]),
.A1N(n1638), .Y(n738) );
AOI21X1TS U1718 ( .A0(n696), .A1(add_subt_module_Add_Subt_result[13]), .B0(
n738), .Y(n750) );
AOI21X1TS U1719 ( .A0(n695), .A1(add_subt_module_Add_Subt_result[17]), .B0(
n739), .Y(n1137) );
AOI22X1TS U1720 ( .A0(n1656), .A1(n1616), .B0(n1654), .B1(n1613), .Y(n740)
);
AOI21X1TS U1721 ( .A0(n696), .A1(add_subt_module_Add_Subt_result[7]), .B0(
n743), .Y(n1632) );
INVX2TS U1722 ( .A(n1588), .Y(n1650) );
OAI2BB2XLTS U1723 ( .B0(n1062), .B1(n1830), .A0N(add_subt_module_DmP[4]),
.A1N(n1140), .Y(n745) );
AOI21X1TS U1724 ( .A0(n697), .A1(add_subt_module_Add_Subt_result[6]), .B0(
n745), .Y(n1639) );
AOI22X1TS U1725 ( .A0(n1665), .A1(n1629), .B0(n1129), .B1(n1635), .Y(n752)
);
AOI21X1TS U1726 ( .A0(add_subt_module_Add_Subt_result[8]), .A1(n697), .B0(
n747), .Y(n1628) );
AOI21X1TS U1727 ( .A0(n697), .A1(add_subt_module_Add_Subt_result[9]), .B0(
n749), .Y(n755) );
AOI22X1TS U1728 ( .A0(n1656), .A1(n1622), .B0(n1654), .B1(n1624), .Y(n751)
);
AOI21X1TS U1729 ( .A0(add_subt_module_Add_Subt_result[5]), .A1(n696), .B0(
n754), .Y(n1646) );
AOI22X1TS U1730 ( .A0(n727), .A1(n1635), .B0(n1129), .B1(n1642), .Y(n757) );
AOI22X1TS U1731 ( .A0(n703), .A1(n1629), .B0(n678), .B1(n1622), .Y(n756) );
CLKXOR2X2TS U1732 ( .A(n1951), .B(n1780), .Y(n1462) );
BUFX3TS U1733 ( .A(add_subt_module_FSM_selector_D), .Y(n1390) );
NOR2BX4TS U1734 ( .AN(n1462), .B(n1390), .Y(n758) );
INVX6TS U1735 ( .A(n758), .Y(n1395) );
XOR2X1TS U1736 ( .A(n787), .B(add_subt_module_Sgf_normalized_result[1]), .Y(
n760) );
BUFX3TS U1737 ( .A(add_subt_module_FSM_selector_D), .Y(n1391) );
NOR2X2TS U1738 ( .A(n760), .B(n759), .Y(n897) );
XOR2X1TS U1739 ( .A(n787), .B(n761), .Y(n766) );
BUFX3TS U1740 ( .A(add_subt_module_FSM_selector_D), .Y(n933) );
NOR2X1TS U1741 ( .A(n766), .B(n765), .Y(n890) );
NOR2X1TS U1742 ( .A(n897), .B(n890), .Y(n768) );
INVX4TS U1743 ( .A(n1395), .Y(n1393) );
NOR2BX1TS U1744 ( .AN(add_subt_module_Sgf_normalized_result[0]), .B(n1390),
.Y(n762) );
XOR2X1TS U1745 ( .A(n1393), .B(n762), .Y(n925) );
INVX2TS U1746 ( .A(n925), .Y(n764) );
NOR2X1TS U1747 ( .A(n1393), .B(n763), .Y(n926) );
NOR2X1TS U1748 ( .A(n764), .B(n926), .Y(n889) );
NAND2X1TS U1749 ( .A(n766), .B(n765), .Y(n891) );
INVX2TS U1750 ( .A(n891), .Y(n767) );
AOI21X1TS U1751 ( .A0(n768), .A1(n889), .B0(n767), .Y(n1435) );
NOR2BX1TS U1752 ( .AN(add_subt_module_Sgf_normalized_result[3]), .B(n1390),
.Y(n769) );
XOR2X1TS U1753 ( .A(n787), .B(n769), .Y(n774) );
NOR2X1TS U1754 ( .A(n774), .B(n773), .Y(n1448) );
NOR2BX1TS U1755 ( .AN(add_subt_module_Sgf_normalized_result[4]), .B(n1390),
.Y(n770) );
XOR2X1TS U1756 ( .A(n787), .B(n770), .Y(n776) );
NOR2X2TS U1757 ( .A(n776), .B(n775), .Y(n1450) );
NOR2X1TS U1758 ( .A(n1448), .B(n1450), .Y(n1437) );
NOR2BX1TS U1759 ( .AN(add_subt_module_Sgf_normalized_result[5]), .B(n1390),
.Y(n771) );
XOR2X1TS U1760 ( .A(n787), .B(n771), .Y(n778) );
NOR2X2TS U1761 ( .A(n778), .B(n777), .Y(n1443) );
NOR2BX1TS U1762 ( .AN(add_subt_module_Sgf_normalized_result[6]), .B(n1390),
.Y(n772) );
XOR2X1TS U1763 ( .A(n787), .B(n772), .Y(n780) );
NOR2X2TS U1764 ( .A(n780), .B(n779), .Y(n1438) );
NAND2X1TS U1765 ( .A(n774), .B(n773), .Y(n1455) );
NAND2X1TS U1766 ( .A(n776), .B(n775), .Y(n1451) );
OAI21X1TS U1767 ( .A0(n1450), .A1(n1455), .B0(n1451), .Y(n1436) );
NAND2X1TS U1768 ( .A(n778), .B(n777), .Y(n1444) );
NAND2X1TS U1769 ( .A(n780), .B(n779), .Y(n1439) );
AOI21X1TS U1770 ( .A0(n1436), .A1(n782), .B0(n781), .Y(n783) );
INVX2TS U1771 ( .A(n842), .Y(n883) );
BUFX3TS U1772 ( .A(add_subt_module_FSM_selector_D), .Y(n1373) );
NOR2BX1TS U1773 ( .AN(add_subt_module_Sgf_normalized_result[7]), .B(n1373),
.Y(n785) );
XOR2X1TS U1774 ( .A(n787), .B(n785), .Y(n791) );
NOR2X2TS U1775 ( .A(n791), .B(n790), .Y(n879) );
NOR2BX1TS U1776 ( .AN(add_subt_module_Sgf_normalized_result[8]), .B(n1373),
.Y(n786) );
XOR2X1TS U1777 ( .A(n787), .B(n786), .Y(n793) );
NOR2X2TS U1778 ( .A(n793), .B(n792), .Y(n867) );
NOR2X1TS U1779 ( .A(n879), .B(n867), .Y(n810) );
NOR2BX1TS U1780 ( .AN(add_subt_module_Sgf_normalized_result[9]), .B(n1390),
.Y(n788) );
XOR2X1TS U1781 ( .A(n1375), .B(n788), .Y(n795) );
BUFX3TS U1782 ( .A(add_subt_module_FSM_selector_D), .Y(n854) );
NOR2X1TS U1783 ( .A(n795), .B(n794), .Y(n814) );
NOR2BX1TS U1784 ( .AN(add_subt_module_Sgf_normalized_result[10]), .B(n1373),
.Y(n789) );
XOR2X1TS U1785 ( .A(n1375), .B(n789), .Y(n797) );
NOR2X2TS U1786 ( .A(n797), .B(n796), .Y(n816) );
NOR2X2TS U1787 ( .A(n814), .B(n816), .Y(n799) );
NAND2X1TS U1788 ( .A(n793), .B(n792), .Y(n868) );
OAI21X1TS U1789 ( .A0(n867), .A1(n880), .B0(n868), .Y(n811) );
NAND2X1TS U1790 ( .A(n795), .B(n794), .Y(n863) );
NAND2X1TS U1791 ( .A(n797), .B(n796), .Y(n817) );
OAI21X1TS U1792 ( .A0(n816), .A1(n863), .B0(n817), .Y(n798) );
AOI21X1TS U1793 ( .A0(n811), .A1(n799), .B0(n798), .Y(n839) );
OAI21X1TS U1794 ( .A0(n883), .A1(n827), .B0(n839), .Y(n821) );
NOR2BX1TS U1795 ( .AN(add_subt_module_Sgf_normalized_result[11]), .B(n1373),
.Y(n800) );
XOR2X1TS U1796 ( .A(n1375), .B(n800), .Y(n802) );
NOR2X1TS U1797 ( .A(n802), .B(n801), .Y(n824) );
INVX2TS U1798 ( .A(n824), .Y(n822) );
NAND2X1TS U1799 ( .A(n802), .B(n801), .Y(n829) );
INVX2TS U1800 ( .A(n829), .Y(n803) );
AOI21X1TS U1801 ( .A0(n821), .A1(n822), .B0(n803), .Y(n809) );
NOR2BX1TS U1802 ( .AN(add_subt_module_Sgf_normalized_result[12]), .B(n1373),
.Y(n804) );
XOR2X1TS U1803 ( .A(n1375), .B(n804), .Y(n806) );
NOR2X2TS U1804 ( .A(n806), .B(n805), .Y(n830) );
INVX2TS U1805 ( .A(n830), .Y(n807) );
NAND2X1TS U1806 ( .A(n806), .B(n805), .Y(n828) );
NAND2X1TS U1807 ( .A(n807), .B(n828), .Y(n808) );
INVX2TS U1808 ( .A(n810), .Y(n813) );
INVX2TS U1809 ( .A(n811), .Y(n812) );
OAI21X1TS U1810 ( .A0(n883), .A1(n813), .B0(n812), .Y(n866) );
INVX2TS U1811 ( .A(n814), .Y(n864) );
INVX2TS U1812 ( .A(n863), .Y(n815) );
AOI21X1TS U1813 ( .A0(n866), .A1(n864), .B0(n815), .Y(n820) );
INVX2TS U1814 ( .A(n816), .Y(n818) );
NAND2X1TS U1815 ( .A(n818), .B(n817), .Y(n819) );
INVX2TS U1816 ( .A(n821), .Y(n1178) );
NAND2X1TS U1817 ( .A(n822), .B(n829), .Y(n823) );
NOR2BX1TS U1818 ( .AN(add_subt_module_Sgf_normalized_result[13]), .B(n1373),
.Y(n825) );
XOR2X1TS U1819 ( .A(n1375), .B(n825), .Y(n832) );
NOR2X1TS U1820 ( .A(n832), .B(n831), .Y(n1179) );
NOR2BX1TS U1821 ( .AN(add_subt_module_Sgf_normalized_result[14]), .B(n1373),
.Y(n826) );
XOR2X1TS U1822 ( .A(n1375), .B(n826), .Y(n834) );
NOR2X2TS U1823 ( .A(n834), .B(n833), .Y(n1181) );
NAND2X2TS U1824 ( .A(n1174), .B(n836), .Y(n838) );
NAND2X1TS U1825 ( .A(n832), .B(n831), .Y(n1431) );
NAND2X1TS U1826 ( .A(n834), .B(n833), .Y(n1182) );
AOI21X1TS U1827 ( .A0(n1175), .A1(n836), .B0(n835), .Y(n837) );
AOI21X4TS U1828 ( .A0(n842), .A1(n841), .B0(n840), .Y(n888) );
NOR2BX1TS U1829 ( .AN(add_subt_module_Sgf_normalized_result[15]), .B(n1373),
.Y(n843) );
XOR2X1TS U1830 ( .A(n1375), .B(n843), .Y(n845) );
NOR2X1TS U1831 ( .A(n845), .B(n844), .Y(n884) );
NAND2X1TS U1832 ( .A(n845), .B(n844), .Y(n885) );
OAI21X4TS U1833 ( .A0(n888), .A1(n884), .B0(n885), .Y(n1430) );
NOR2BX1TS U1834 ( .AN(add_subt_module_Sgf_normalized_result[16]), .B(n1373),
.Y(n846) );
XOR2X1TS U1835 ( .A(n1375), .B(n846), .Y(n848) );
NAND2X1TS U1836 ( .A(n848), .B(n847), .Y(n1427) );
INVX2TS U1837 ( .A(n1427), .Y(n849) );
AOI21X4TS U1838 ( .A0(n1430), .A1(n1428), .B0(n849), .Y(n876) );
NOR2BX1TS U1839 ( .AN(add_subt_module_Sgf_normalized_result[17]), .B(n1391),
.Y(n850) );
XOR2X1TS U1840 ( .A(n1375), .B(n850), .Y(n852) );
NOR2X1TS U1841 ( .A(n852), .B(n851), .Y(n872) );
NAND2X1TS U1842 ( .A(n852), .B(n851), .Y(n873) );
OAI21X4TS U1843 ( .A0(n876), .A1(n872), .B0(n873), .Y(n1426) );
NOR2BX1TS U1844 ( .AN(add_subt_module_Sgf_normalized_result[18]), .B(n1391),
.Y(n853) );
XOR2X1TS U1845 ( .A(n1393), .B(n853), .Y(n856) );
NAND2X1TS U1846 ( .A(n856), .B(n855), .Y(n1423) );
INVX2TS U1847 ( .A(n1423), .Y(n857) );
AOI21X4TS U1848 ( .A0(n1426), .A1(n1424), .B0(n857), .Y(n1368) );
NOR2BX1TS U1849 ( .AN(add_subt_module_Sgf_normalized_result[19]), .B(n1391),
.Y(n858) );
XOR2X1TS U1850 ( .A(n1393), .B(n858), .Y(n860) );
BUFX3TS U1851 ( .A(add_subt_module_FSM_selector_D), .Y(n1386) );
NOR2X1TS U1852 ( .A(n860), .B(n859), .Y(n1367) );
INVX2TS U1853 ( .A(n1367), .Y(n861) );
NAND2X1TS U1854 ( .A(n860), .B(n859), .Y(n1366) );
NAND2X1TS U1855 ( .A(n861), .B(n1366), .Y(n862) );
NAND2X1TS U1856 ( .A(n864), .B(n863), .Y(n865) );
INVX2TS U1857 ( .A(n867), .Y(n869) );
NAND2X1TS U1858 ( .A(n869), .B(n868), .Y(n870) );
INVX2TS U1859 ( .A(n872), .Y(n874) );
NAND2X1TS U1860 ( .A(n874), .B(n873), .Y(n875) );
INVX2TS U1861 ( .A(n714), .Y(n1703) );
INVX2TS U1862 ( .A(n1012), .Y(n1940) );
NAND3X1TS U1863 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[2]),
.C(n1721), .Y(n1291) );
INVX2TS U1864 ( .A(n1701), .Y(n1020) );
NOR2X4TS U1865 ( .A(data_out_LUT[22]), .B(n1020), .Y(n1273) );
INVX2TS U1866 ( .A(n1291), .Y(n1294) );
NAND2X1TS U1867 ( .A(sel_mux_2_reg[1]), .B(n1940), .Y(n877) );
OAI32X1TS U1868 ( .A0(n1291), .A1(n1273), .A2(n682), .B0(n1294), .B1(n877),
.Y(n878) );
INVX2TS U1869 ( .A(n879), .Y(n881) );
NAND2X1TS U1870 ( .A(n881), .B(n880), .Y(n882) );
INVX2TS U1871 ( .A(n884), .Y(n886) );
NAND2X1TS U1872 ( .A(n886), .B(n885), .Y(n887) );
INVX2TS U1873 ( .A(n890), .Y(n892) );
NAND2X1TS U1874 ( .A(n892), .B(n891), .Y(n893) );
NOR2X1TS U1875 ( .A(data_out_LUT[8]), .B(n1020), .Y(n1290) );
NOR2X2TS U1876 ( .A(cont_iter_out[3]), .B(data_out_LUT[8]), .Y(n1700) );
NAND2X1TS U1877 ( .A(n1701), .B(n1700), .Y(n1286) );
OAI32X1TS U1878 ( .A0(n680), .A1(n1290), .A2(n1781), .B0(n1286), .B1(n680),
.Y(n895) );
BUFX3TS U1879 ( .A(n1038), .Y(n1461) );
BUFX3TS U1880 ( .A(n1710), .Y(n1712) );
BUFX3TS U1881 ( .A(n1709), .Y(n1711) );
AOI22X1TS U1882 ( .A0(n1712), .A1(d_ff3_sh_x_out[3]), .B0(n1711), .B1(
d_ff3_sh_y_out[3]), .Y(n898) );
OAI2BB1X1TS U1883 ( .A0N(n1461), .A1N(d_ff3_LUT_out[3]), .B0(n898), .Y(n899)
);
AOI22X1TS U1884 ( .A0(n1712), .A1(d_ff3_sh_x_out[11]), .B0(n1711), .B1(
d_ff3_sh_y_out[11]), .Y(n900) );
OAI2BB1X1TS U1885 ( .A0N(n1028), .A1N(d_ff3_LUT_out[7]), .B0(n900), .Y(n901)
);
AOI22X1TS U1886 ( .A0(n1712), .A1(d_ff3_sh_x_out[13]), .B0(n1711), .B1(
d_ff3_sh_y_out[13]), .Y(n902) );
OAI2BB1X1TS U1887 ( .A0N(n1028), .A1N(d_ff3_LUT_out[13]), .B0(n902), .Y(n903) );
AOI22X1TS U1888 ( .A0(n1712), .A1(d_ff3_sh_x_out[14]), .B0(n1711), .B1(
d_ff3_sh_y_out[14]), .Y(n904) );
OAI2BB1X1TS U1889 ( .A0N(n1028), .A1N(d_ff3_LUT_out[5]), .B0(n904), .Y(n905)
);
BUFX3TS U1890 ( .A(n1710), .Y(n1296) );
BUFX3TS U1891 ( .A(n1709), .Y(n1295) );
AOI22X1TS U1892 ( .A0(n1296), .A1(d_ff3_sh_x_out[17]), .B0(n1295), .B1(
d_ff3_sh_y_out[17]), .Y(n906) );
BUFX3TS U1893 ( .A(n1038), .Y(n1039) );
NAND2X1TS U1894 ( .A(n1039), .B(d_ff3_LUT_out[15]), .Y(n1713) );
AOI22X1TS U1895 ( .A0(n1296), .A1(d_ff3_sh_x_out[20]), .B0(n1295), .B1(
d_ff3_sh_y_out[20]), .Y(n908) );
AOI22X1TS U1896 ( .A0(n1296), .A1(d_ff3_sh_x_out[27]), .B0(n1295), .B1(
d_ff3_sh_y_out[27]), .Y(n910) );
NAND2X1TS U1897 ( .A(n1039), .B(d_ff3_LUT_out[27]), .Y(n914) );
AOI22X1TS U1898 ( .A0(n1296), .A1(d_ff3_sh_x_out[28]), .B0(n1295), .B1(
d_ff3_sh_y_out[28]), .Y(n912) );
AOI22X1TS U1899 ( .A0(n1296), .A1(d_ff3_sh_x_out[29]), .B0(n1295), .B1(
d_ff3_sh_y_out[29]), .Y(n915) );
AOI22X1TS U1900 ( .A0(n1296), .A1(d_ff3_sh_x_out[16]), .B0(n1295), .B1(
d_ff3_sh_y_out[16]), .Y(n917) );
OAI2BB1X1TS U1901 ( .A0N(n1028), .A1N(d_ff3_LUT_out[3]), .B0(n917), .Y(n918)
);
AOI22X1TS U1902 ( .A0(n1296), .A1(d_ff3_sh_x_out[18]), .B0(n1295), .B1(
d_ff3_sh_y_out[18]), .Y(n919) );
OAI2BB1X1TS U1903 ( .A0N(n1028), .A1N(d_ff3_LUT_out[13]), .B0(n919), .Y(n920) );
AOI22X1TS U1904 ( .A0(n1296), .A1(d_ff3_sh_x_out[19]), .B0(n1295), .B1(
d_ff3_sh_y_out[19]), .Y(n921) );
OAI2BB1X1TS U1905 ( .A0N(n1028), .A1N(d_ff3_LUT_out[19]), .B0(n921), .Y(n922) );
AOI22X1TS U1906 ( .A0(n1296), .A1(d_ff3_sh_x_out[22]), .B0(n1295), .B1(
d_ff3_sh_y_out[22]), .Y(n923) );
OAI2BB1X1TS U1907 ( .A0N(n1028), .A1N(d_ff3_LUT_out[19]), .B0(n923), .Y(n924) );
NAND2X1TS U1908 ( .A(n1702), .B(cont_iter_out[1]), .Y(n1165) );
OAI21X1TS U1909 ( .A0(cont_iter_out[1]), .A1(n1702), .B0(n1165), .Y(n976) );
NOR2BX1TS U1910 ( .AN(n976), .B(n685), .Y(n927) );
NOR2X2TS U1911 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(
add_subt_module_FS_Module_state_reg[0]), .Y(n1084) );
NOR2X2TS U1912 ( .A(n1748), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n1465) );
AOI211X1TS U1913 ( .A0(n1745), .A1(n1748), .B0(n1471), .C0(n1786), .Y(n930)
);
NAND2X2TS U1914 ( .A(n1465), .B(n683), .Y(n1475) );
INVX2TS U1915 ( .A(n1475), .Y(n1027) );
AOI21X1TS U1916 ( .A0(add_subt_module_FS_Module_state_reg[2]), .A1(n1022),
.B0(n1027), .Y(n929) );
OAI211X4TS U1917 ( .A0(add_subt_module_FSM_selector_C), .A1(n975), .B0(n930),
.C0(n929), .Y(n968) );
XOR2X1TS U1918 ( .A(n968), .B(n931), .Y(n967) );
XOR2X1TS U1919 ( .A(n968), .B(n932), .Y(n946) );
XOR2X1TS U1920 ( .A(n968), .B(n934), .Y(n949) );
OAI2BB2XLTS U1921 ( .B0(n991), .B1(n1783), .A0N(n725), .A1N(
add_subt_module_DmP[27]), .Y(n936) );
XOR2X1TS U1922 ( .A(n968), .B(n936), .Y(n952) );
NOR2X2TS U1923 ( .A(add_subt_module_FSM_selector_B[1]), .B(n1744), .Y(n999)
);
NAND2X1TS U1924 ( .A(n999), .B(n693), .Y(n1503) );
OAI2BB1X1TS U1925 ( .A0N(n725), .A1N(add_subt_module_DmP[26]), .B0(n1503),
.Y(n937) );
XOR2X1TS U1926 ( .A(n968), .B(n937), .Y(n955) );
OAI2BB1X1TS U1927 ( .A0N(add_subt_module_DmP[25]), .A1N(n725), .B0(n938),
.Y(n939) );
XOR2X1TS U1928 ( .A(n968), .B(n939), .Y(n958) );
OAI2BB1X1TS U1929 ( .A0N(add_subt_module_DmP[24]), .A1N(n725), .B0(n940),
.Y(n941) );
XOR2X1TS U1930 ( .A(n968), .B(n941), .Y(n961) );
OAI2BB1X1TS U1931 ( .A0N(add_subt_module_DmP[23]), .A1N(n692), .B0(n942),
.Y(n943) );
CMPR32X2TS U1932 ( .A(n949), .B(n948), .C(n947), .CO(n944), .S(
add_subt_module_Exp_Operation_Module_Data_S[5]) );
CMPR32X2TS U1933 ( .A(n952), .B(n951), .C(n950), .CO(n947), .S(
add_subt_module_Exp_Operation_Module_Data_S[4]) );
NAND2X1TS U1934 ( .A(n1465), .B(n964), .Y(n1468) );
OAI21X1TS U1935 ( .A0(n1779), .A1(n975), .B0(n1468), .Y(n974) );
XOR2X4TS U1936 ( .A(n969), .B(n968), .Y(n1267) );
INVX2TS U1937 ( .A(n974), .Y(n970) );
OR4X2TS U1938 ( .A(add_subt_module_Exp_Operation_Module_Data_S[2]), .B(
add_subt_module_Exp_Operation_Module_Data_S[1]), .C(
add_subt_module_Exp_Operation_Module_Data_S[0]), .D(n970), .Y(n971) );
OR4X2TS U1939 ( .A(add_subt_module_Exp_Operation_Module_Data_S[5]), .B(
add_subt_module_Exp_Operation_Module_Data_S[4]), .C(
add_subt_module_Exp_Operation_Module_Data_S[3]), .D(n971), .Y(n972) );
OAI31X1TS U1940 ( .A0(add_subt_module_FS_Module_state_reg[2]), .A1(n1953),
.A2(n1784), .B0(n975), .Y(add_subt_module_FSM_exp_operation_load_diff)
);
NOR2X2TS U1941 ( .A(n1703), .B(n1781), .Y(n1288) );
NOR2X2TS U1942 ( .A(n1288), .B(n1700), .Y(n1166) );
OAI21X1TS U1943 ( .A0(n1703), .A1(cont_iter_out[1]), .B0(n1166), .Y(
data_out_LUT[16]) );
AOI33X1TS U1944 ( .A0(n1705), .A1(cont_iter_out[1]), .A2(data_out_LUT[8]),
.B0(intadd_391_B_0_), .B1(n1781), .B2(n1702), .Y(n1289) );
NAND2X1TS U1945 ( .A(n1288), .B(n976), .Y(n977) );
NAND2X1TS U1946 ( .A(n1289), .B(n977), .Y(data_out_LUT[6]) );
AOI21X1TS U1947 ( .A0(n1702), .A1(intadd_391_B_0_), .B0(cont_iter_out[3]),
.Y(n978) );
OAI31X1TS U1948 ( .A0(n1273), .A1(n1668), .A2(n1808), .B0(n1762), .Y(n980)
);
NAND2X1TS U1949 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[0]),
.Y(n1280) );
INVX2TS U1950 ( .A(n1280), .Y(n1269) );
OAI22X1TS U1951 ( .A0(cordic_FSM_state_reg[1]), .A1(ack_cordic), .B0(
cordic_FSM_state_reg[3]), .B1(n1269), .Y(n979) );
NAND2X1TS U1952 ( .A(n981), .B(n1983), .Y(n601) );
NOR4X2TS U1953 ( .A(n1703), .B(cont_iter_out[3]), .C(n1705), .D(
cont_iter_out[1]), .Y(n1163) );
NOR2X1TS U1954 ( .A(n683), .B(add_subt_module_FSM_selector_C), .Y(n982) );
NAND2X1TS U1955 ( .A(n999), .B(n1075), .Y(n993) );
NAND2X1TS U1956 ( .A(n1145), .B(n690), .Y(n1004) );
NOR2X1TS U1957 ( .A(n1757), .B(add_subt_module_exp_oper_result[4]), .Y(n983)
);
NAND2X2TS U1958 ( .A(n690), .B(n983), .Y(n1536) );
INVX2TS U1959 ( .A(n1536), .Y(n1499) );
NAND2X1TS U1960 ( .A(n1499), .B(n986), .Y(n987) );
NAND2X2TS U1961 ( .A(n1240), .B(n987), .Y(n1537) );
NAND2X2TS U1962 ( .A(n999), .B(n1783), .Y(n1244) );
INVX2TS U1963 ( .A(n1244), .Y(n1197) );
AOI22X1TS U1964 ( .A0(add_subt_module_LZA_output[4]), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .B1(
n1783), .Y(n1502) );
OR3X1TS U1965 ( .A(n693), .B(add_subt_module_exp_oper_result[3]), .C(
add_subt_module_exp_oper_result[4]), .Y(n989) );
NAND2X2TS U1966 ( .A(n989), .B(n1749), .Y(n1237) );
AOI22X1TS U1967 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n721), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .B1(
n1237), .Y(n990) );
OAI31X1TS U1968 ( .A0(n991), .A1(n1502), .A2(add_subt_module_LZA_output[3]),
.B0(n990), .Y(n996) );
AOI31X1TS U1969 ( .A0(n694), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .A2(
n1197), .B0(n996), .Y(n1218) );
INVX2TS U1970 ( .A(n986), .Y(n1243) );
NOR2X1TS U1971 ( .A(n992), .B(n1796), .Y(n995) );
NOR2X1TS U1972 ( .A(n1783), .B(n993), .Y(n994) );
OAI21X4TS U1973 ( .A0(n1244), .A1(n692), .B0(n1536), .Y(n1549) );
AND2X2TS U1974 ( .A(n1237), .B(n1534), .Y(n1258) );
INVX2TS U1975 ( .A(n1258), .Y(n1535) );
INVX2TS U1976 ( .A(n1245), .Y(n1196) );
NAND2X2TS U1977 ( .A(n693), .B(n1196), .Y(n1235) );
NAND2X2TS U1978 ( .A(n1535), .B(n1235), .Y(n1506) );
AOI22X1TS U1979 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n1549), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B1(
n1506), .Y(n1223) );
BUFX3TS U1980 ( .A(n1550), .Y(n1546) );
AOI22X1TS U1981 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1197), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .B1(
n1196), .Y(n1195) );
OAI222X1TS U1982 ( .A0(n1535), .A1(n1818), .B0(n1536), .B1(n1768), .C0(n1534), .C1(n1195), .Y(n1009) );
NAND2X1TS U1983 ( .A(n1749), .B(add_subt_module_exp_oper_result[3]), .Y(
n1000) );
NAND2X1TS U1984 ( .A(n1002), .B(n1001), .Y(n1220) );
OAI22X1TS U1985 ( .A0(n1245), .A1(n1828), .B0(n1244), .B1(n1765), .Y(n1191)
);
NOR2X1TS U1986 ( .A(n1004), .B(n1796), .Y(n1005) );
INVX2TS U1987 ( .A(n1075), .Y(n1225) );
INVX2TS U1988 ( .A(n1539), .Y(n1263) );
AOI21X1TS U1989 ( .A0(n1191), .A1(n1543), .B0(n1263), .Y(n1007) );
NAND2X1TS U1990 ( .A(n1537), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .Y(
n1006) );
INVX2TS U1991 ( .A(n1011), .Y(n1919) );
INVX2TS U1992 ( .A(n1011), .Y(n1923) );
BUFX3TS U1993 ( .A(n1013), .Y(n1886) );
INVX2TS U1994 ( .A(n1012), .Y(n1936) );
BUFX3TS U1995 ( .A(n1891), .Y(n1877) );
BUFX3TS U1996 ( .A(n1014), .Y(n1878) );
BUFX3TS U1997 ( .A(n1889), .Y(n1879) );
BUFX3TS U1998 ( .A(n1888), .Y(n1876) );
CLKBUFX2TS U1999 ( .A(n1013), .Y(n1015) );
BUFX3TS U2000 ( .A(n1014), .Y(n1896) );
BUFX3TS U2001 ( .A(n1889), .Y(n1897) );
BUFX3TS U2002 ( .A(n1013), .Y(n1887) );
BUFX3TS U2003 ( .A(n1013), .Y(n1890) );
BUFX3TS U2004 ( .A(n1013), .Y(n1892) );
BUFX3TS U2005 ( .A(n1888), .Y(n1893) );
BUFX3TS U2006 ( .A(n1886), .Y(n1885) );
BUFX3TS U2007 ( .A(n1887), .Y(n1895) );
BUFX3TS U2008 ( .A(n1013), .Y(n1891) );
CLKBUFX2TS U2009 ( .A(n1013), .Y(n1902) );
BUFX3TS U2010 ( .A(n1892), .Y(n1899) );
CLKBUFX3TS U2011 ( .A(n1890), .Y(n1901) );
CLKBUFX3TS U2012 ( .A(n1892), .Y(n1900) );
BUFX3TS U2013 ( .A(n1013), .Y(n1888) );
CLKBUFX3TS U2014 ( .A(n1886), .Y(n1884) );
CLKBUFX3TS U2015 ( .A(n1887), .Y(n1883) );
BUFX3TS U2016 ( .A(n1886), .Y(n1880) );
BUFX3TS U2017 ( .A(n1887), .Y(n1882) );
BUFX3TS U2018 ( .A(n1013), .Y(n1889) );
BUFX3TS U2019 ( .A(n1890), .Y(n1898) );
BUFX3TS U2020 ( .A(n1890), .Y(n1881) );
BUFX3TS U2021 ( .A(n1892), .Y(n1894) );
BUFX3TS U2022 ( .A(sel_mux_1_reg), .Y(n1688) );
CLKBUFX2TS U2023 ( .A(sel_mux_1_reg), .Y(n1683) );
NAND2X1TS U2024 ( .A(n1019), .B(n1016), .Y(n1059) );
INVX2TS U2025 ( .A(n1059), .Y(n1464) );
NOR3X2TS U2026 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1953), .C(
n1017), .Y(n1466) );
NAND2X1TS U2027 ( .A(n1762), .B(cordic_FSM_state_reg[3]), .Y(n1021) );
NOR4X2TS U2028 ( .A(cordic_FSM_state_reg[1]), .B(cordic_FSM_state_reg[3]),
.C(n684), .D(n680), .Y(load_cont_var) );
NAND4BX1TS U2029 ( .AN(n1021), .B(n1718), .C(n684), .D(n685), .Y(n1279) );
NOR2X1TS U2030 ( .A(cordic_FSM_state_reg[3]), .B(n1153), .Y(load_cont_iter)
);
NOR2X1TS U2031 ( .A(n1022), .B(add_subt_module_FS_Module_state_reg[2]), .Y(
n1716) );
INVX2TS U2032 ( .A(n1716), .Y(n580) );
NAND2X1TS U2033 ( .A(n1804), .B(n1705), .Y(intadd_391_CI) );
NAND2X1TS U2034 ( .A(n1803), .B(n1705), .Y(intadd_392_CI) );
INVX2TS U2035 ( .A(n1683), .Y(n1024) );
OAI21XLTS U2036 ( .A0(add_subt_module_FS_Module_state_reg[1]), .A1(
add_subt_module_add_overflow_flag), .B0(n1027), .Y(n1026) );
BUFX3TS U2037 ( .A(n1038), .Y(n1033) );
BUFX3TS U2038 ( .A(n1710), .Y(n1049) );
BUFX3TS U2039 ( .A(n1709), .Y(n1048) );
AOI222X1TS U2040 ( .A0(n1033), .A1(d_ff2_Z[0]), .B0(n1049), .B1(d_ff2_Y[0]),
.C0(n1048), .C1(d_ff2_X[0]), .Y(n1942) );
AOI222X1TS U2041 ( .A0(n1033), .A1(d_ff3_LUT_out[0]), .B0(n1049), .B1(
d_ff3_sh_x_out[0]), .C0(n1048), .C1(d_ff3_sh_y_out[0]), .Y(n1943) );
AOI222X1TS U2042 ( .A0(n1028), .A1(d_ff3_LUT_out[1]), .B0(n1049), .B1(
d_ff3_sh_x_out[1]), .C0(n1048), .C1(d_ff3_sh_y_out[1]), .Y(n1029) );
INVX2TS U2043 ( .A(n1029), .Y(n638) );
BUFX3TS U2044 ( .A(n1710), .Y(n1036) );
BUFX3TS U2045 ( .A(n1709), .Y(n1035) );
AOI222X1TS U2046 ( .A0(n1033), .A1(d_ff2_Z[4]), .B0(n1036), .B1(d_ff2_Y[4]),
.C0(n1035), .C1(d_ff2_X[4]), .Y(n1946) );
AOI222X1TS U2047 ( .A0(n1033), .A1(d_ff2_Z[3]), .B0(n1036), .B1(d_ff2_Y[3]),
.C0(n1035), .C1(d_ff2_X[3]), .Y(n1944) );
AOI222X1TS U2048 ( .A0(n1039), .A1(d_ff3_LUT_out[6]), .B0(n1036), .B1(
d_ff3_sh_x_out[6]), .C0(n1035), .C1(d_ff3_sh_y_out[6]), .Y(n1948) );
AOI222X1TS U2049 ( .A0(n1039), .A1(d_ff2_Z[8]), .B0(n1036), .B1(d_ff2_Y[8]),
.C0(n1035), .C1(d_ff2_X[8]), .Y(n1949) );
AOI222X1TS U2050 ( .A0(n1033), .A1(d_ff2_Z[2]), .B0(n1036), .B1(d_ff2_Y[2]),
.C0(n1035), .C1(d_ff2_X[2]), .Y(n1945) );
AOI222X1TS U2051 ( .A0(n1039), .A1(d_ff3_LUT_out[8]), .B0(n1036), .B1(
d_ff3_sh_x_out[8]), .C0(n1035), .C1(d_ff3_sh_y_out[8]), .Y(n1950) );
AOI222X1TS U2052 ( .A0(n1039), .A1(d_ff2_Z[6]), .B0(n1712), .B1(d_ff2_Y[6]),
.C0(n1711), .C1(d_ff2_X[6]), .Y(n1947) );
AOI222X1TS U2053 ( .A0(n1033), .A1(d_ff2_Z[1]), .B0(n1712), .B1(d_ff2_Y[1]),
.C0(n1711), .C1(d_ff2_X[1]), .Y(n1941) );
AOI222X1TS U2054 ( .A0(n1033), .A1(d_ff3_LUT_out[2]), .B0(n1036), .B1(
d_ff3_sh_x_out[2]), .C0(n1035), .C1(d_ff3_sh_y_out[2]), .Y(n1030) );
INVX2TS U2055 ( .A(n1030), .Y(n639) );
AOI222X1TS U2056 ( .A0(n1033), .A1(d_ff2_Z[7]), .B0(n1036), .B1(d_ff2_Y[7]),
.C0(n1035), .C1(d_ff2_X[7]), .Y(n1031) );
INVX2TS U2057 ( .A(n1031), .Y(n612) );
AOI222X1TS U2058 ( .A0(n1033), .A1(d_ff3_LUT_out[4]), .B0(n1036), .B1(
d_ff3_sh_x_out[4]), .C0(n1035), .C1(d_ff3_sh_y_out[4]), .Y(n1032) );
INVX2TS U2059 ( .A(n1032), .Y(n641) );
AOI222X1TS U2060 ( .A0(n1033), .A1(d_ff2_Z[5]), .B0(n1712), .B1(d_ff2_Y[5]),
.C0(n1711), .C1(d_ff2_X[5]), .Y(n1034) );
INVX2TS U2061 ( .A(n1034), .Y(n610) );
AOI222X1TS U2062 ( .A0(n1039), .A1(d_ff2_Z[31]), .B0(n1036), .B1(d_ff2_Y[31]), .C0(n1035), .C1(d_ff2_X[31]), .Y(n1037) );
INVX2TS U2063 ( .A(n1037), .Y(n636) );
AOI222X1TS U2064 ( .A0(n1461), .A1(d_ff3_LUT_out[26]), .B0(n1710), .B1(
d_ff3_sh_x_out[26]), .C0(n1709), .C1(d_ff3_sh_y_out[26]), .Y(n1954) );
AOI222X1TS U2065 ( .A0(n1461), .A1(d_ff3_LUT_out[24]), .B0(n1710), .B1(
d_ff3_sh_x_out[24]), .C0(n1709), .C1(d_ff3_sh_y_out[24]), .Y(n1956) );
AOI222X1TS U2066 ( .A0(n1461), .A1(d_ff3_LUT_out[25]), .B0(n1710), .B1(
d_ff3_sh_x_out[25]), .C0(n1709), .C1(d_ff3_sh_y_out[25]), .Y(n1955) );
BUFX3TS U2067 ( .A(n1038), .Y(n1046) );
BUFX3TS U2068 ( .A(n1710), .Y(n1042) );
BUFX3TS U2069 ( .A(n1709), .Y(n1041) );
BUFX3TS U2070 ( .A(n1038), .Y(n1050) );
AOI222X1TS U2071 ( .A0(n1050), .A1(d_ff2_Z[11]), .B0(n1042), .B1(d_ff2_Y[11]), .C0(n1041), .C1(d_ff2_X[11]), .Y(n1977) );
BUFX3TS U2072 ( .A(n1710), .Y(n1045) );
BUFX3TS U2073 ( .A(n1709), .Y(n1044) );
AOI222X1TS U2074 ( .A0(n1050), .A1(d_ff2_Z[19]), .B0(n1045), .B1(d_ff2_Y[19]), .C0(n1044), .C1(d_ff2_X[19]), .Y(n1970) );
AOI222X1TS U2075 ( .A0(n1039), .A1(d_ff2_Z[22]), .B0(n1042), .B1(d_ff2_Y[22]), .C0(n1041), .C1(d_ff2_X[22]), .Y(n1967) );
AOI222X1TS U2076 ( .A0(n1039), .A1(d_ff2_Z[23]), .B0(n1045), .B1(d_ff2_Y[23]), .C0(n1044), .C1(d_ff2_X[23]), .Y(n1966) );
AOI222X1TS U2077 ( .A0(n1461), .A1(d_ff3_LUT_out[10]), .B0(n1045), .B1(
d_ff3_sh_x_out[10]), .C0(n1044), .C1(d_ff3_sh_y_out[10]), .Y(n1958) );
AOI222X1TS U2078 ( .A0(n1050), .A1(d_ff2_Z[20]), .B0(n1042), .B1(d_ff2_Y[20]), .C0(n1041), .C1(d_ff2_X[20]), .Y(n1969) );
AOI222X1TS U2079 ( .A0(n1046), .A1(d_ff2_Z[9]), .B0(n1045), .B1(d_ff2_Y[9]),
.C0(n1044), .C1(d_ff2_X[9]), .Y(n1979) );
AOI222X1TS U2080 ( .A0(n1461), .A1(d_ff3_LUT_out[21]), .B0(n1045), .B1(
d_ff3_sh_x_out[21]), .C0(n1044), .C1(d_ff3_sh_y_out[21]), .Y(n1957) );
AOI222X1TS U2081 ( .A0(n1039), .A1(d_ff2_Z[21]), .B0(n1042), .B1(d_ff2_Y[21]), .C0(n1041), .C1(d_ff2_X[21]), .Y(n1968) );
AOI222X1TS U2082 ( .A0(n1050), .A1(d_ff2_Z[15]), .B0(n1042), .B1(d_ff2_Y[15]), .C0(n1041), .C1(d_ff2_X[15]), .Y(n1973) );
AOI222X1TS U2083 ( .A0(n1050), .A1(d_ff2_Z[17]), .B0(n1049), .B1(d_ff2_Y[17]), .C0(n1048), .C1(d_ff2_X[17]), .Y(n1972) );
AOI222X1TS U2084 ( .A0(n1046), .A1(d_ff2_Z[10]), .B0(n1049), .B1(d_ff2_Y[10]), .C0(n1048), .C1(d_ff2_X[10]), .Y(n1978) );
AOI222X1TS U2085 ( .A0(n1050), .A1(d_ff2_Z[18]), .B0(n1049), .B1(d_ff2_Y[18]), .C0(n1048), .C1(d_ff2_X[18]), .Y(n1971) );
AOI222X1TS U2086 ( .A0(n1050), .A1(d_ff2_Z[13]), .B0(n1049), .B1(d_ff2_Y[13]), .C0(n1048), .C1(d_ff2_X[13]), .Y(n1975) );
AOI222X1TS U2087 ( .A0(n1050), .A1(d_ff2_Z[12]), .B0(n1049), .B1(d_ff2_Y[12]), .C0(n1048), .C1(d_ff2_X[12]), .Y(n1976) );
AOI222X1TS U2088 ( .A0(n1050), .A1(d_ff2_Z[14]), .B0(n1049), .B1(d_ff2_Y[14]), .C0(n1048), .C1(d_ff2_X[14]), .Y(n1974) );
AOI222X1TS U2089 ( .A0(n1461), .A1(d_ff3_LUT_out[12]), .B0(n1045), .B1(
d_ff3_sh_x_out[12]), .C0(n1044), .C1(d_ff3_sh_y_out[12]), .Y(n1040) );
INVX2TS U2090 ( .A(n1040), .Y(n649) );
AOI222X1TS U2091 ( .A0(n1046), .A1(d_ff2_Z[28]), .B0(n1042), .B1(d_ff2_Y[28]), .C0(n1041), .C1(d_ff2_X[28]), .Y(n1961) );
AOI222X1TS U2092 ( .A0(n1461), .A1(d_ff3_LUT_out[9]), .B0(n1045), .B1(
d_ff3_sh_x_out[9]), .C0(n1044), .C1(d_ff3_sh_y_out[9]), .Y(n1043) );
INVX2TS U2093 ( .A(n1043), .Y(n646) );
AOI222X1TS U2094 ( .A0(n1046), .A1(d_ff3_LUT_out[23]), .B0(n1045), .B1(
d_ff3_sh_x_out[23]), .C0(n1044), .C1(d_ff3_sh_y_out[23]), .Y(n1047) );
INVX2TS U2095 ( .A(n1047), .Y(n660) );
AOI222X1TS U2096 ( .A0(n1050), .A1(d_ff2_Z[16]), .B0(n1049), .B1(d_ff2_Y[16]), .C0(n1048), .C1(d_ff2_X[16]), .Y(n1051) );
INVX2TS U2097 ( .A(n1051), .Y(n621) );
OA22X1TS U2098 ( .A0(r_mode[0]), .A1(n1777), .B0(
add_subt_module_Sgf_normalized_result[0]), .B1(
add_subt_module_Sgf_normalized_result[1]), .Y(n1053) );
NAND2X1TS U2099 ( .A(r_mode[0]), .B(r_mode[1]), .Y(n1052) );
OAI211X1TS U2100 ( .A0(add_subt_module_sign_final_result), .A1(r_mode[1]),
.B0(n1053), .C0(n1052), .Y(n1470) );
NOR2X1TS U2101 ( .A(n1470), .B(n1054), .Y(n1575) );
NOR3X2TS U2102 ( .A(add_subt_module_FS_Module_state_reg[3]), .B(n1745), .C(
n1784), .Y(add_subt_module_FSM_Add_Subt_Sgf_load) );
NAND2X1TS U2103 ( .A(n1084), .B(n1055), .Y(n1118) );
INVX2TS U2104 ( .A(n1118), .Y(n1952) );
NOR2X1TS U2105 ( .A(n1135), .B(add_subt_module_Add_Subt_result[25]), .Y(
n1057) );
NOR2X2TS U2106 ( .A(n1057), .B(n1056), .Y(n1587) );
INVX2TS U2107 ( .A(n1587), .Y(n1124) );
OAI31X1TS U2108 ( .A0(n1124), .A1(n1142), .A2(n1588), .B0(n1061), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[22]) );
OAI2BB2XLTS U2109 ( .B0(n1062), .B1(n1815), .A0N(add_subt_module_DmP[22]),
.A1N(n1638), .Y(n1063) );
NOR2X2TS U2110 ( .A(n1064), .B(n1063), .Y(n1128) );
INVX2TS U2111 ( .A(n1128), .Y(n1586) );
AOI22X1TS U2112 ( .A0(n706), .A1(n1587), .B0(n1650), .B1(n1586), .Y(n1067)
);
INVX2TS U2113 ( .A(n1071), .Y(n1073) );
CLKBUFX2TS U2114 ( .A(n1068), .Y(n1648) );
AOI21X2TS U2115 ( .A0(n695), .A1(add_subt_module_Add_Subt_result[23]), .B0(
n1069), .Y(n1591) );
OAI22X1TS U2116 ( .A0(n1128), .A1(n1590), .B0(n1591), .B1(n1588), .Y(n1070)
);
AOI32X1TS U2117 ( .A0(n702), .A1(n1648), .A2(n1587), .B0(n1070), .B1(n1602),
.Y(n1072) );
NAND2X2TS U2118 ( .A(n1071), .B(n1142), .Y(n1593) );
AOI22X1TS U2119 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n1197), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .B1(
n1196), .Y(n1190) );
INVX2TS U2120 ( .A(n1190), .Y(n1074) );
AOI222X1TS U2121 ( .A0(n1074), .A1(n694), .B0(n1499), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .C0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[39]), .C1(
n1258), .Y(n1083) );
INVX2TS U2122 ( .A(n1568), .Y(n1077) );
AOI22X1TS U2123 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n721), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .B1(
n1237), .Y(n1079) );
INVX2TS U2124 ( .A(n1145), .Y(n1146) );
AOI22X1TS U2125 ( .A0(add_subt_module_LZA_output[4]), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .B1(
n1783), .Y(n1284) );
NOR3X1TS U2126 ( .A(add_subt_module_FSM_selector_B[1]), .B(
add_subt_module_LZA_output[3]), .C(n1284), .Y(n1078) );
OAI2BB2XLTS U2127 ( .B0(n1079), .B1(n1146), .A0N(n1078), .A1N(n1075), .Y(
n1076) );
AOI211X1TS U2128 ( .A0(n1537), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(
n1077), .C0(n1076), .Y(n1082) );
AOI21X1TS U2129 ( .A0(n1197), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .B0(
n1078), .Y(n1080) );
OAI21X1TS U2130 ( .A0(n1080), .A1(n679), .B0(n1079), .Y(n1186) );
NAND2X1TS U2131 ( .A(n986), .B(n1186), .Y(n1081) );
NOR2X1TS U2132 ( .A(n1784), .B(n1475), .Y(n1576) );
AOI211X1TS U2133 ( .A0(add_subt_module_FSM_selector_C), .A1(n1466), .B0(
n1464), .C0(n1576), .Y(n1472) );
AOI22X1TS U2134 ( .A0(add_subt_module_intDX[30]), .A1(
add_subt_module_intDY[30]), .B0(n1770), .B1(n1801), .Y(n1091) );
AOI22X1TS U2135 ( .A0(n1800), .A1(add_subt_module_intDY[1]), .B0(n1769),
.B1(add_subt_module_intDY[0]), .Y(n1085) );
AOI22X1TS U2136 ( .A0(n1798), .A1(add_subt_module_intDY[3]), .B0(n1759),
.B1(add_subt_module_intDY[2]), .Y(n1086) );
AOI22X1TS U2137 ( .A0(n1806), .A1(add_subt_module_intDY[5]), .B0(n1761),
.B1(add_subt_module_intDY[4]), .Y(n1087) );
OAI221XLTS U2138 ( .A0(n1806), .A1(add_subt_module_intDY[5]), .B0(n1761),
.B1(add_subt_module_intDY[4]), .C0(n1087), .Y(n1088) );
NOR4X1TS U2139 ( .A(n1091), .B(n1090), .C(n1089), .D(n1088), .Y(n1117) );
AOI22X1TS U2140 ( .A0(add_subt_module_intDY[7]), .A1(n1813), .B0(
add_subt_module_intDY[6]), .B1(n1746), .Y(n1317) );
AOI22X1TS U2141 ( .A0(n1758), .A1(add_subt_module_intDY[9]), .B0(n1799),
.B1(add_subt_module_intDY[8]), .Y(n1092) );
OAI221XLTS U2142 ( .A0(n1758), .A1(add_subt_module_intDY[9]), .B0(n1799),
.B1(add_subt_module_intDY[8]), .C0(n1092), .Y(n1096) );
AOI22X1TS U2143 ( .A0(n1750), .A1(add_subt_module_intDY[14]), .B0(n1790),
.B1(add_subt_module_intDY[13]), .Y(n1093) );
OAI221XLTS U2144 ( .A0(n1750), .A1(add_subt_module_intDY[14]), .B0(n1790),
.B1(add_subt_module_intDY[13]), .C0(n1093), .Y(n1094) );
NOR4X1TS U2145 ( .A(n1097), .B(n1096), .C(n1095), .D(n1094), .Y(n1116) );
AOI22X1TS U2146 ( .A0(n1807), .A1(add_subt_module_intDY[16]), .B0(n1791),
.B1(add_subt_module_intDY[15]), .Y(n1098) );
AOI22X1TS U2147 ( .A0(n1751), .A1(add_subt_module_intDY[18]), .B0(n1788),
.B1(add_subt_module_intDY[17]), .Y(n1099) );
OAI221XLTS U2148 ( .A0(n1751), .A1(add_subt_module_intDY[18]), .B0(n1788),
.B1(add_subt_module_intDY[17]), .C0(n1099), .Y(n1104) );
AOI22X1TS U2149 ( .A0(n1752), .A1(add_subt_module_intDY[20]), .B0(n1789),
.B1(add_subt_module_intDY[19]), .Y(n1100) );
AOI22X1TS U2150 ( .A0(n1753), .A1(add_subt_module_intDY[22]), .B0(n1792),
.B1(add_subt_module_intDY[21]), .Y(n1101) );
OAI221XLTS U2151 ( .A0(n1753), .A1(add_subt_module_intDY[22]), .B0(n1792),
.B1(add_subt_module_intDY[21]), .C0(n1101), .Y(n1102) );
NOR4X1TS U2152 ( .A(n1105), .B(n1104), .C(n1103), .D(n1102), .Y(n1115) );
AOI22X1TS U2153 ( .A0(n1754), .A1(add_subt_module_intDY[24]), .B0(n1795),
.B1(add_subt_module_intDY[23]), .Y(n1106) );
AOI22X1TS U2154 ( .A0(n1755), .A1(add_subt_module_intDY[26]), .B0(n1794),
.B1(add_subt_module_intDY[25]), .Y(n1107) );
OAI221XLTS U2155 ( .A0(n1755), .A1(add_subt_module_intDY[26]), .B0(n1794),
.B1(add_subt_module_intDY[25]), .C0(n1107), .Y(n1112) );
AOI22X1TS U2156 ( .A0(n1802), .A1(add_subt_module_intDY[28]), .B0(n1756),
.B1(add_subt_module_intDY[27]), .Y(n1108) );
AOI22X1TS U2157 ( .A0(n1793), .A1(add_subt_module_intDY[29]), .B0(n1787),
.B1(add_subt_module_intDX[12]), .Y(n1109) );
OAI221XLTS U2158 ( .A0(n1793), .A1(add_subt_module_intDY[29]), .B0(n1787),
.B1(add_subt_module_intDX[12]), .C0(n1109), .Y(n1110) );
NOR4X1TS U2159 ( .A(n1113), .B(n1112), .C(n1111), .D(n1110), .Y(n1114) );
NAND4X1TS U2160 ( .A(n1117), .B(n1116), .C(n1115), .D(n1114), .Y(n1364) );
INVX2TS U2161 ( .A(n1364), .Y(n1463) );
AOI21X1TS U2162 ( .A0(n1463), .A1(n1462), .B0(n1118), .Y(n1119) );
INVX2TS U2163 ( .A(n1588), .Y(n1129) );
AOI21X2TS U2164 ( .A0(n695), .A1(add_subt_module_Add_Subt_result[22]), .B0(
n1122), .Y(n1589) );
OAI222X1TS U2165 ( .A0(n1159), .A1(n1128), .B0(n701), .B1(n1591), .C0(n1590),
.C1(n1589), .Y(n1125) );
AOI21X1TS U2166 ( .A0(n695), .A1(add_subt_module_Add_Subt_result[21]), .B0(
n1123), .Y(n1136) );
AOI22X1TS U2167 ( .A0(n1602), .A1(n1125), .B0(n1650), .B1(n1170), .Y(n1126)
);
AOI21X1TS U2168 ( .A0(add_subt_module_Add_Subt_result[20]), .A1(n695), .B0(
n1127), .Y(n1138) );
AOI22X1TS U2169 ( .A0(n1665), .A1(n1170), .B0(n1663), .B1(n1169), .Y(n1132)
);
OAI22X1TS U2170 ( .A0(n1591), .A1(n1159), .B0(n1589), .B1(n701), .Y(n1130)
);
NAND2X1TS U2171 ( .A(n1648), .B(n1130), .Y(n1131) );
AOI22X1TS U2172 ( .A0(n700), .A1(add_subt_module_Add_Subt_result[6]), .B0(
add_subt_module_DmP[17]), .B1(n1638), .Y(n1134) );
OA21XLTS U2173 ( .A0(n1830), .A1(n1135), .B0(n1134), .Y(n1595) );
AO22X1TS U2174 ( .A0(n1068), .A1(n1595), .B0(n1142), .B1(n1591), .Y(n1173)
);
AOI22X1TS U2175 ( .A0(n1665), .A1(n1603), .B0(n1129), .B1(n1606), .Y(n1144)
);
AOI21X1TS U2176 ( .A0(add_subt_module_Add_Subt_result[18]), .A1(n695), .B0(
n1141), .Y(n1600) );
NAND2X1TS U2177 ( .A(n702), .B(n1597), .Y(n1143) );
NAND4X2TS U2178 ( .A(n694), .B(add_subt_module_LZA_output[4]), .C(n1744),
.D(n1749), .Y(n1281) );
OAI22X1TS U2179 ( .A0(n1235), .A1(n1861), .B0(n1281), .B1(n1764), .Y(n1561)
);
AOI211X1TS U2180 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .A1(
n1549), .B0(n1561), .C0(n1558), .Y(n1148) );
AO21X2TS U2181 ( .A0(n1506), .A1(n986), .B0(n1145), .Y(n1529) );
NOR2X4TS U2182 ( .A(n1506), .B(n1146), .Y(n1528) );
AOI21X1TS U2183 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1529), .B0(n1528), .Y(n1147) );
OAI22X1TS U2184 ( .A0(n1235), .A1(n1859), .B0(n1766), .B1(n1281), .Y(n1555)
);
AOI211X1TS U2185 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .A1(
n1549), .B0(n1555), .C0(n1552), .Y(n1150) );
AOI21X1TS U2186 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1529), .B0(n1528), .Y(n1149) );
OAI22X1TS U2187 ( .A0(n1235), .A1(n1860), .B0(n1281), .B1(n1765), .Y(n1571)
);
AOI211X1TS U2188 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]), .A1(
n1549), .B0(n1571), .C0(n1566), .Y(n1152) );
AOI21X1TS U2189 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1529), .B0(n1528), .Y(n1151) );
INVX2TS U2190 ( .A(n1153), .Y(n1722) );
NAND2X1TS U2191 ( .A(cordic_FSM_state_reg[3]), .B(n1722), .Y(n1155) );
INVX2TS U2192 ( .A(n1155), .Y(n1156) );
BUFX3TS U2193 ( .A(n1862), .Y(n1695) );
NOR2X1TS U2194 ( .A(d_ff1_operation_out), .B(d_ff1_shift_region_flag_out[1]),
.Y(n1696) );
AOI21X1TS U2195 ( .A0(d_ff1_shift_region_flag_out[1]), .A1(
d_ff1_operation_out), .B0(n1696), .Y(n1154) );
XOR2X1TS U2196 ( .A(n681), .B(n1154), .Y(n1271) );
NAND2X1TS U2197 ( .A(n1808), .B(n684), .Y(n1720) );
NOR2X1TS U2198 ( .A(n1720), .B(n1280), .Y(n1158) );
BUFX3TS U2199 ( .A(sel_mux_1_reg), .Y(n1684) );
INVX2TS U2200 ( .A(n1158), .Y(n1157) );
AOI22X1TS U2201 ( .A0(n1665), .A1(n1169), .B0(n703), .B1(n1170), .Y(n1162)
);
OAI32X1TS U2202 ( .A0(n1645), .A1(n1159), .A2(n1589), .B0(n1593), .B1(n1159),
.Y(n1160) );
INVX2TS U2203 ( .A(n1160), .Y(n1161) );
OAI21X1TS U2204 ( .A0(n705), .A1(intadd_391_B_0_), .B0(n1166), .Y(
data_out_LUT[20]) );
AOI21X1TS U2205 ( .A0(cont_iter_out[1]), .A1(n1700), .B0(n1288), .Y(n1164)
);
OAI21X1TS U2206 ( .A0(cont_iter_out[3]), .A1(n1165), .B0(n1164), .Y(
data_out_LUT[12]) );
OAI21X1TS U2207 ( .A0(n1703), .A1(n1702), .B0(n1166), .Y(data_out_LUT[18])
);
AOI22X1TS U2208 ( .A0(n1665), .A1(n1597), .B0(n1663), .B1(n1603), .Y(n1168)
);
NAND2X1TS U2209 ( .A(n678), .B(n1169), .Y(n1167) );
AOI22X1TS U2210 ( .A0(n702), .A1(n1169), .B0(n1663), .B1(n1597), .Y(n1172)
);
NAND2X1TS U2211 ( .A(n1654), .B(n1170), .Y(n1171) );
INVX2TS U2212 ( .A(n1174), .Y(n1177) );
INVX2TS U2213 ( .A(n1175), .Y(n1176) );
OAI21X1TS U2214 ( .A0(n1178), .A1(n1177), .B0(n1176), .Y(n1434) );
INVX2TS U2215 ( .A(n1179), .Y(n1432) );
INVX2TS U2216 ( .A(n1431), .Y(n1180) );
AOI21X1TS U2217 ( .A0(n1434), .A1(n1432), .B0(n1180), .Y(n1185) );
INVX2TS U2218 ( .A(n1181), .Y(n1183) );
NAND2X1TS U2219 ( .A(n1183), .B(n1182), .Y(n1184) );
INVX2TS U2220 ( .A(n1543), .Y(n1201) );
AOI21X1TS U2221 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n1499), .B0(n1186), .Y(n1187) );
OAI22X1TS U2222 ( .A0(n1187), .A1(n691), .B0(n1540), .B1(n1816), .Y(n1188)
);
AOI21X1TS U2223 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n1537), .B0(n1188), .Y(n1189) );
AOI222X1TS U2224 ( .A0(n1191), .A1(n693), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .B1(
n1499), .C0(n1258), .C1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[33]), .Y(
n1192) );
OAI22X1TS U2225 ( .A0(n1540), .A1(n1818), .B0(n1192), .B1(n691), .Y(n1193)
);
AOI21X1TS U2226 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1537), .B0(n1193), .Y(n1194) );
AOI22X1TS U2227 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1197), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .B1(
n1196), .Y(n1533) );
OAI22X1TS U2228 ( .A0(n1245), .A1(n1829), .B0(n1766), .B1(n1244), .Y(n1542)
);
AOI222X1TS U2229 ( .A0(n1542), .A1(n694), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .B1(
n1499), .C0(n1258), .C1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[35]), .Y(
n1198) );
OAI22X1TS U2230 ( .A0(n1540), .A1(n1817), .B0(n1198), .B1(n691), .Y(n1199)
);
AOI21X1TS U2231 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1537), .B0(n1199), .Y(n1200) );
INVX2TS U2232 ( .A(beg_fsm_cordic), .Y(n1204) );
NAND4X1TS U2233 ( .A(cordic_FSM_state_reg[3]), .B(cordic_FSM_state_reg[0]),
.C(n1762), .D(n1980), .Y(n1717) );
AOI2BB1X1TS U2234 ( .A0N(n1853), .A1N(add_subt_module_Add_Subt_result[1]),
.B0(add_subt_module_Add_Subt_result[2]), .Y(n1483) );
INVX2TS U2235 ( .A(n1480), .Y(n1205) );
NOR2X1TS U2236 ( .A(add_subt_module_Add_Subt_result[25]), .B(
add_subt_module_Add_Subt_result[24]), .Y(n1492) );
NOR2X1TS U2237 ( .A(add_subt_module_Add_Subt_result[23]), .B(
add_subt_module_Add_Subt_result[22]), .Y(n1490) );
NAND2X1TS U2238 ( .A(n1492), .B(n1490), .Y(n1479) );
NOR2X4TS U2239 ( .A(n1205), .B(n1479), .Y(n1673) );
NOR3X1TS U2240 ( .A(n1675), .B(add_subt_module_Add_Subt_result[14]), .C(
add_subt_module_Add_Subt_result[18]), .Y(n1207) );
NAND2X2TS U2241 ( .A(n1494), .B(n1797), .Y(n1677) );
OR4X2TS U2242 ( .A(n1209), .B(add_subt_module_Add_Subt_result[10]), .C(
add_subt_module_Add_Subt_result[9]), .D(
add_subt_module_Add_Subt_result[8]), .Y(n1252) );
NOR4X2TS U2243 ( .A(n1252), .B(add_subt_module_Add_Subt_result[5]), .C(
add_subt_module_Add_Subt_result[4]), .D(n1250), .Y(n1484) );
INVX2TS U2244 ( .A(n1484), .Y(n1208) );
NOR4BX2TS U2245 ( .AN(add_subt_module_Add_Subt_result[4]), .B(n1252), .C(
add_subt_module_Add_Subt_result[5]), .D(n1250), .Y(n1476) );
INVX2TS U2246 ( .A(n1209), .Y(n1254) );
NOR3BX1TS U2247 ( .AN(add_subt_module_Add_Subt_result[8]), .B(n1677), .C(
add_subt_module_Add_Subt_result[9]), .Y(n1215) );
AOI21X1TS U2248 ( .A0(n1810), .A1(add_subt_module_Add_Subt_result[20]), .B0(
add_subt_module_Add_Subt_result[22]), .Y(n1211) );
NOR4BX1TS U2249 ( .AN(n1497), .B(n1215), .C(n1679), .D(n1214), .Y(n1216) );
AOI22X1TS U2250 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[40]), .A1(
n1220), .B0(n1546), .B1(n1219), .Y(n1222) );
OA21XLTS U2251 ( .A0(n1824), .A1(n1240), .B0(n1539), .Y(n1221) );
AND2X2TS U2252 ( .A(n1506), .B(n1546), .Y(n1573) );
INVX2TS U2253 ( .A(n1573), .Y(n1508) );
INVX2TS U2254 ( .A(n1240), .Y(n1548) );
OAI22X1TS U2255 ( .A0(n1235), .A1(n1831), .B0(n1281), .B1(n1768), .Y(n1224)
);
AOI21X1TS U2256 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .A1(
n1549), .B0(n1224), .Y(n1527) );
AOI22X1TS U2257 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n721), .B0(n1237), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .Y(
n1526) );
AOI22X1TS U2258 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1(
n1564), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[30]), .B1(
n1563), .Y(n1226) );
AOI211X1TS U2259 ( .A0(n1548), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[38]), .B0(
n1228), .C0(n1227), .Y(n1229) );
OAI22X1TS U2260 ( .A0(n1235), .A1(n1858), .B0(n1281), .B1(n1763), .Y(n1230)
);
AOI21X1TS U2261 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .A1(
n1549), .B0(n1230), .Y(n1522) );
NAND2X1TS U2262 ( .A(n1573), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .Y(
n1234) );
AOI22X1TS U2263 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n721), .B0(n1237), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]), .Y(
n1521) );
AOI22X1TS U2264 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1(
n1564), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[29]), .B1(
n1563), .Y(n1231) );
OAI22X1TS U2265 ( .A0(n1235), .A1(n1857), .B0(n1281), .B1(n1767), .Y(n1236)
);
AOI21X1TS U2266 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[36]), .A1(
n1549), .B0(n1236), .Y(n1518) );
NAND2X1TS U2267 ( .A(n1573), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n1242) );
AOI22X1TS U2268 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n721), .B0(n1237), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]), .Y(
n1517) );
AOI22X1TS U2269 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1(
n1564), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[28]), .B1(
n1563), .Y(n1238) );
OAI22X1TS U2270 ( .A0(n1245), .A1(n1827), .B0(n1764), .B1(n1244), .Y(n1259)
);
INVX2TS U2271 ( .A(n1537), .Y(n1261) );
OAI22X1TS U2272 ( .A0(n1245), .A1(n1809), .B0(n1763), .B1(n1244), .Y(n1264)
);
AOI222X1TS U2273 ( .A0(n1264), .A1(n693), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .B1(
n1499), .C0(n1258), .C1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[37]), .Y(
n1246) );
OAI22X1TS U2274 ( .A0(n1261), .A1(n1764), .B0(n1246), .B1(n691), .Y(n1248)
);
AOI211X1TS U2275 ( .A0(n1543), .A1(n1259), .B0(n1248), .C0(n1247), .Y(n1249)
);
INVX2TS U2276 ( .A(n1249), .Y(n1991) );
AOI31XLTS U2277 ( .A0(n1772), .A1(n1747), .A2(n1826), .B0(
add_subt_module_Add_Subt_result[10]), .Y(n1253) );
INVX2TS U2278 ( .A(n1250), .Y(n1478) );
OAI21X1TS U2279 ( .A0(n1478), .A1(n1252), .B0(n1251), .Y(n1498) );
AOI211X1TS U2280 ( .A0(n1254), .A1(n1253), .B0(n1498), .C0(n1476), .Y(n1256)
);
AOI222X1TS U2281 ( .A0(n1259), .A1(n693), .B0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .B1(
n1499), .C0(n1258), .C1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[34]), .Y(
n1260) );
OAI22X1TS U2282 ( .A0(n1261), .A1(n1763), .B0(n1260), .B1(n691), .Y(n1262)
);
NOR2X1TS U2283 ( .A(d_ff2_X[27]), .B(intadd_391_n1), .Y(n1732) );
NOR2X1TS U2284 ( .A(d_ff2_Y[27]), .B(intadd_392_n1), .Y(n1729) );
AND4X1TS U2285 ( .A(add_subt_module_Exp_Operation_Module_Data_S[3]), .B(
add_subt_module_Exp_Operation_Module_Data_S[2]), .C(
add_subt_module_Exp_Operation_Module_Data_S[1]), .D(
add_subt_module_Exp_Operation_Module_Data_S[0]), .Y(n1266) );
AND4X1TS U2286 ( .A(add_subt_module_Exp_Operation_Module_Data_S[6]), .B(
add_subt_module_Exp_Operation_Module_Data_S[5]), .C(
add_subt_module_Exp_Operation_Module_Data_S[4]), .D(n1266), .Y(n1268)
);
OR4X2TS U2287 ( .A(ack_cordic), .B(n1808), .C(n684), .D(
cordic_FSM_state_reg[1]), .Y(n1724) );
INVX2TS U2288 ( .A(n1273), .Y(n1278) );
NOR2X2TS U2289 ( .A(n1273), .B(n1717), .Y(n1669) );
NAND2X1TS U2290 ( .A(n1669), .B(cont_var_out[0]), .Y(n1275) );
INVX2TS U2291 ( .A(n1275), .Y(n1276) );
AOI21X1TS U2292 ( .A0(n1669), .A1(n682), .B0(cont_var_out[0]), .Y(n1274) );
AOI21X1TS U2293 ( .A0(cont_var_out[0]), .A1(n1278), .B0(n1277), .Y(n1292) );
NOR3XLTS U2294 ( .A(cordic_FSM_state_reg[2]), .B(n1808), .C(n1280), .Y(
enab_dff_5) );
NOR2BX1TS U2295 ( .AN(n1281), .B(n721), .Y(n1505) );
NOR3X1TS U2296 ( .A(n689), .B(n1757), .C(n1796), .Y(n1500) );
AOI22X1TS U2297 ( .A0(n1500), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .B0(
n1499), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[32]), .Y(
n1282) );
OAI211X1TS U2298 ( .A0(n1284), .A1(n1503), .B0(n1283), .C0(n1282), .Y(n1513)
);
AOI21X1TS U2299 ( .A0(n1506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]), .B0(
n1513), .Y(n1285) );
OAI2BB2XLTS U2300 ( .B0(n1285), .B1(n1546), .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1N(
n1573), .Y(n1990) );
INVX2TS U2301 ( .A(n1286), .Y(n1287) );
BUFX3TS U2302 ( .A(n1670), .Y(n1574) );
XNOR2X1TS U2303 ( .A(cont_var_out[0]), .B(d_ff3_sign_out), .Y(n1298) );
XNOR2X1TS U2304 ( .A(n1298), .B(n1297), .Y(n1875) );
NOR2X1TS U2305 ( .A(n1845), .B(add_subt_module_intDX[25]), .Y(n1358) );
AOI22X1TS U2306 ( .A0(add_subt_module_intDX[25]), .A1(n1845), .B0(
add_subt_module_intDX[24]), .B1(n1299), .Y(n1303) );
OAI21X1TS U2307 ( .A0(add_subt_module_intDX[26]), .A1(n1846), .B0(n1300),
.Y(n1359) );
NOR2X1TS U2308 ( .A(n1770), .B(add_subt_module_intDX[30]), .Y(n1306) );
NOR2X1TS U2309 ( .A(n1844), .B(add_subt_module_intDX[29]), .Y(n1304) );
AOI211X1TS U2310 ( .A0(add_subt_module_intDY[28]), .A1(n1802), .B0(n1306),
.C0(n1304), .Y(n1357) );
NOR3X1TS U2311 ( .A(n1802), .B(n1304), .C(add_subt_module_intDY[28]), .Y(
n1305) );
AOI221X1TS U2312 ( .A0(add_subt_module_intDX[30]), .A1(n1770), .B0(
add_subt_module_intDX[29]), .B1(n1844), .C0(n1305), .Y(n1307) );
AOI2BB2X1TS U2313 ( .B0(n1308), .B1(n1357), .A0N(n1307), .A1N(n1306), .Y(
n1363) );
NOR2X1TS U2314 ( .A(n1842), .B(add_subt_module_intDX[17]), .Y(n1344) );
OAI2BB1X1TS U2315 ( .A0N(n1806), .A1N(add_subt_module_intDY[5]), .B0(
add_subt_module_intDX[4]), .Y(n1309) );
OAI22X1TS U2316 ( .A0(add_subt_module_intDY[4]), .A1(n1309), .B0(n1806),
.B1(add_subt_module_intDY[5]), .Y(n1320) );
OAI2BB1X1TS U2317 ( .A0N(n1813), .A1N(add_subt_module_intDY[7]), .B0(
add_subt_module_intDX[6]), .Y(n1310) );
OAI22X1TS U2318 ( .A0(add_subt_module_intDY[6]), .A1(n1310), .B0(n1813),
.B1(add_subt_module_intDY[7]), .Y(n1319) );
OA22X1TS U2319 ( .A0(n1775), .A1(add_subt_module_intDX[14]), .B0(n1843),
.B1(add_subt_module_intDX[15]), .Y(n1335) );
OAI2BB2XLTS U2320 ( .B0(add_subt_module_intDY[12]), .B1(n1322), .A0N(
add_subt_module_intDX[13]), .A1N(n1834), .Y(n1334) );
AOI22X1TS U2321 ( .A0(add_subt_module_intDX[11]), .A1(n1840), .B0(
add_subt_module_intDX[10]), .B1(n1324), .Y(n1330) );
AOI21X1TS U2322 ( .A0(n1327), .A1(n1326), .B0(n1337), .Y(n1329) );
OAI2BB2XLTS U2323 ( .B0(add_subt_module_intDY[14]), .B1(n1331), .A0N(
add_subt_module_intDX[15]), .A1N(n1843), .Y(n1332) );
AOI211X1TS U2324 ( .A0(n1335), .A1(n1334), .B0(n1333), .C0(n1332), .Y(n1336)
);
OAI31X1TS U2325 ( .A0(n1339), .A1(n1338), .A2(n1337), .B0(n1336), .Y(n1342)
);
OA22X1TS U2326 ( .A0(n1776), .A1(add_subt_module_intDX[22]), .B0(n1847),
.B1(add_subt_module_intDX[23]), .Y(n1355) );
OAI21X1TS U2327 ( .A0(add_subt_module_intDX[18]), .A1(n1841), .B0(n1346),
.Y(n1350) );
AOI211X1TS U2328 ( .A0(add_subt_module_intDY[16]), .A1(n1807), .B0(n1349),
.C0(n1350), .Y(n1341) );
OAI2BB2XLTS U2329 ( .B0(add_subt_module_intDY[20]), .B1(n1343), .A0N(
add_subt_module_intDX[21]), .A1N(n1835), .Y(n1354) );
AOI22X1TS U2330 ( .A0(add_subt_module_intDX[17]), .A1(n1842), .B0(
add_subt_module_intDX[16]), .B1(n1345), .Y(n1348) );
AOI32X1TS U2331 ( .A0(n1841), .A1(n1346), .A2(add_subt_module_intDX[18]),
.B0(add_subt_module_intDX[19]), .B1(n1774), .Y(n1347) );
OAI32X1TS U2332 ( .A0(n1350), .A1(n1349), .A2(n1348), .B0(n1347), .B1(n1349),
.Y(n1353) );
OAI2BB2XLTS U2333 ( .B0(add_subt_module_intDY[22]), .B1(n1351), .A0N(
add_subt_module_intDX[23]), .A1N(n1847), .Y(n1352) );
AOI211X1TS U2334 ( .A0(n1355), .A1(n1354), .B0(n1353), .C0(n1352), .Y(n1361)
);
NAND4BBX1TS U2335 ( .AN(n1359), .BN(n1358), .C(n1357), .D(n1356), .Y(n1360)
);
AOI32X4TS U2336 ( .A0(n1363), .A1(n1362), .A2(n1361), .B0(n1360), .B1(n1363),
.Y(n1532) );
AOI21X1TS U2337 ( .A0(n1585), .A1(n1364), .B0(add_subt_module_intDX[31]),
.Y(n1365) );
OAI22X1TS U2338 ( .A0(n1365), .A1(n1951), .B0(n1780), .B1(n1489), .Y(n1985)
);
OAI21X4TS U2339 ( .A0(n1368), .A1(n1367), .B0(n1366), .Y(n1422) );
NOR2BX1TS U2340 ( .AN(add_subt_module_Sgf_normalized_result[20]), .B(n1391),
.Y(n1369) );
XOR2X1TS U2341 ( .A(n1393), .B(n1369), .Y(n1371) );
NAND2X1TS U2342 ( .A(n1371), .B(n1370), .Y(n1419) );
INVX2TS U2343 ( .A(n1419), .Y(n1372) );
AOI21X4TS U2344 ( .A0(n1422), .A1(n1420), .B0(n1372), .Y(n1418) );
NOR2BX1TS U2345 ( .AN(add_subt_module_Sgf_normalized_result[21]), .B(n1373),
.Y(n1374) );
XOR2X1TS U2346 ( .A(n1375), .B(n1374), .Y(n1377) );
NOR2X1TS U2347 ( .A(n1377), .B(n1376), .Y(n1414) );
NAND2X1TS U2348 ( .A(n1377), .B(n1376), .Y(n1415) );
OAI21X4TS U2349 ( .A0(n1418), .A1(n1414), .B0(n1415), .Y(n1413) );
NOR2BX1TS U2350 ( .AN(add_subt_module_Sgf_normalized_result[22]), .B(n1391),
.Y(n1378) );
XOR2X1TS U2351 ( .A(n1393), .B(n1378), .Y(n1380) );
NAND2X1TS U2352 ( .A(n1380), .B(n1379), .Y(n1410) );
INVX2TS U2353 ( .A(n1410), .Y(n1381) );
AOI21X4TS U2354 ( .A0(n1413), .A1(n1411), .B0(n1381), .Y(n1409) );
NOR2BX1TS U2355 ( .AN(add_subt_module_Sgf_normalized_result[23]), .B(n1391),
.Y(n1382) );
XOR2X1TS U2356 ( .A(n1393), .B(n1382), .Y(n1384) );
NOR2X1TS U2357 ( .A(n1384), .B(n1383), .Y(n1405) );
NAND2X1TS U2358 ( .A(n1384), .B(n1383), .Y(n1406) );
NOR2BX1TS U2359 ( .AN(add_subt_module_Sgf_normalized_result[24]), .B(n1391),
.Y(n1385) );
XOR2X1TS U2360 ( .A(n1393), .B(n1385), .Y(n1388) );
NAND2X1TS U2361 ( .A(n1388), .B(n1387), .Y(n1401) );
INVX2TS U2362 ( .A(n1401), .Y(n1389) );
AOI21X2TS U2363 ( .A0(n1404), .A1(n1402), .B0(n1389), .Y(n1400) );
INVX2TS U2364 ( .A(n1398), .Y(n1394) );
NOR2BX1TS U2365 ( .AN(add_subt_module_Sgf_normalized_result[25]), .B(n1391),
.Y(n1392) );
XNOR2X1TS U2366 ( .A(n1393), .B(n1392), .Y(n1397) );
XNOR2X1TS U2367 ( .A(n1396), .B(n1395), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[26]) );
NAND2X1TS U2368 ( .A(n1398), .B(n1397), .Y(n1399) );
NAND2X1TS U2369 ( .A(n1402), .B(n1401), .Y(n1403) );
XNOR2X1TS U2370 ( .A(n1404), .B(n1403), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[24]) );
INVX2TS U2371 ( .A(n1405), .Y(n1407) );
NAND2X1TS U2372 ( .A(n1407), .B(n1406), .Y(n1408) );
NAND2X1TS U2373 ( .A(n1411), .B(n1410), .Y(n1412) );
XNOR2X1TS U2374 ( .A(n1413), .B(n1412), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[22]) );
INVX2TS U2375 ( .A(n1414), .Y(n1416) );
NAND2X1TS U2376 ( .A(n1416), .B(n1415), .Y(n1417) );
NAND2X1TS U2377 ( .A(n1420), .B(n1419), .Y(n1421) );
XNOR2X1TS U2378 ( .A(n1422), .B(n1421), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[20]) );
NAND2X1TS U2379 ( .A(n1424), .B(n1423), .Y(n1425) );
XNOR2X1TS U2380 ( .A(n1426), .B(n1425), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[18]) );
NAND2X1TS U2381 ( .A(n1428), .B(n1427), .Y(n1429) );
XNOR2X1TS U2382 ( .A(n1430), .B(n1429), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[16]) );
NAND2X1TS U2383 ( .A(n1432), .B(n1431), .Y(n1433) );
XNOR2X1TS U2384 ( .A(n1434), .B(n1433), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[13]) );
INVX2TS U2385 ( .A(n1435), .Y(n1458) );
AOI21X1TS U2386 ( .A0(n1458), .A1(n1437), .B0(n1436), .Y(n1447) );
INVX2TS U2387 ( .A(n1438), .Y(n1440) );
NAND2X1TS U2388 ( .A(n1440), .B(n1439), .Y(n1441) );
XNOR2X1TS U2389 ( .A(n1442), .B(n1441), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[6]) );
INVX2TS U2390 ( .A(n1443), .Y(n1445) );
NAND2X1TS U2391 ( .A(n1445), .B(n1444), .Y(n1446) );
INVX2TS U2392 ( .A(n1448), .Y(n1456) );
AOI21X1TS U2393 ( .A0(n1458), .A1(n1456), .B0(n1449), .Y(n1454) );
INVX2TS U2394 ( .A(n1450), .Y(n1452) );
NAND2X1TS U2395 ( .A(n1452), .B(n1451), .Y(n1453) );
NAND2X1TS U2396 ( .A(n1456), .B(n1455), .Y(n1457) );
XNOR2X1TS U2397 ( .A(n1458), .B(n1457), .Y(
add_subt_module_Add_Subt_Sgf_module_S_to_D[3]) );
AOI22X1TS U2398 ( .A0(n1712), .A1(d_ff3_sh_x_out[5]), .B0(n1711), .B1(
d_ff3_sh_y_out[5]), .Y(n1459) );
OAI2BB1X1TS U2399 ( .A0N(n1461), .A1N(d_ff3_LUT_out[5]), .B0(n1459), .Y(n642) );
AOI22X1TS U2400 ( .A0(n1712), .A1(d_ff3_sh_x_out[7]), .B0(n1711), .B1(
d_ff3_sh_y_out[7]), .Y(n1460) );
OAI2BB1X1TS U2401 ( .A0N(n1461), .A1N(d_ff3_LUT_out[7]), .B0(n1460), .Y(n644) );
AOI31X1TS U2402 ( .A0(n1463), .A1(n1462), .A2(n1952), .B0(n1856), .Y(n1473)
);
NAND2X1TS U2403 ( .A(n1466), .B(n1779), .Y(n1577) );
INVX2TS U2404 ( .A(n1468), .Y(n1469) );
AOI211X1TS U2405 ( .A0(n1471), .A1(n1470), .B0(n1469), .C0(
add_subt_module_FSM_Add_Subt_Sgf_load), .Y(n1474) );
MXI2X1TS U2406 ( .A(add_subt_module_add_overflow_flag), .B(n1534), .S0(n1475), .Y(n594) );
AOI2BB1X1TS U2407 ( .A0N(add_subt_module_Add_Subt_result[11]), .A1N(
add_subt_module_Add_Subt_result[13]), .B0(n1481), .Y(n1680) );
OAI22X1TS U2408 ( .A0(n1481), .A1(n1811), .B0(n1480), .B1(n1479), .Y(n1482)
);
INVX2TS U2409 ( .A(n1483), .Y(n1485) );
MXI2X1TS U2410 ( .A(n1801), .B(n1770), .S0(n1584), .Y(
add_subt_module_Oper_Start_in_module_intM[30]) );
MXI2X1TS U2411 ( .A(n1793), .B(n1844), .S0(n1516), .Y(
add_subt_module_Oper_Start_in_module_intM[29]) );
MXI2X1TS U2412 ( .A(n1802), .B(n1837), .S0(n1489), .Y(
add_subt_module_Oper_Start_in_module_intM[28]) );
MXI2X1TS U2413 ( .A(n1756), .B(n1839), .S0(n1489), .Y(
add_subt_module_Oper_Start_in_module_intM[27]) );
MXI2X1TS U2414 ( .A(n1755), .B(n1846), .S0(n1581), .Y(
add_subt_module_Oper_Start_in_module_intM[26]) );
MXI2X1TS U2415 ( .A(n1794), .B(n1845), .S0(n1584), .Y(
add_subt_module_Oper_Start_in_module_intM[25]) );
MXI2X1TS U2416 ( .A(n1754), .B(n1838), .S0(n1516), .Y(
add_subt_module_Oper_Start_in_module_intM[24]) );
MXI2X1TS U2417 ( .A(n1795), .B(n1847), .S0(n1489), .Y(
add_subt_module_Oper_Start_in_module_intM[23]) );
BUFX3TS U2418 ( .A(n1585), .Y(n1512) );
MXI2X1TS U2419 ( .A(n1770), .B(n1801), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[30]) );
MXI2X1TS U2420 ( .A(n1844), .B(n1793), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[29]) );
MXI2X1TS U2421 ( .A(n1837), .B(n1802), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[28]) );
MXI2X1TS U2422 ( .A(n1839), .B(n1756), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[27]) );
MXI2X1TS U2423 ( .A(n1846), .B(n1755), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[26]) );
MXI2X1TS U2424 ( .A(n1845), .B(n1794), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[25]) );
MXI2X1TS U2425 ( .A(n1838), .B(n1754), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[24]) );
AOI211X1TS U2426 ( .A0(n1854), .A1(n1773), .B0(
add_subt_module_Add_Subt_result[17]), .C0(
add_subt_module_Add_Subt_result[16]), .Y(n1493) );
OAI31X1TS U2427 ( .A0(n1830), .A1(add_subt_module_Add_Subt_result[21]), .A2(
add_subt_module_Add_Subt_result[20]), .B0(n1490), .Y(n1491) );
AOI22X1TS U2428 ( .A0(n1493), .A1(n1673), .B0(n1492), .B1(n1491), .Y(n1496)
);
MXI2X1TS U2429 ( .A(n1847), .B(n1795), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intm[23]) );
AOI22X1TS U2430 ( .A0(n1500), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .B0(
n1499), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[31]), .Y(
n1501) );
OA21XLTS U2431 ( .A0(n1503), .A1(n1502), .B0(n1501), .Y(n1504) );
OAI21X1TS U2432 ( .A0(n1505), .A1(n1816), .B0(n1504), .Y(n1509) );
AOI21X1TS U2433 ( .A0(n1506), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]), .B0(
n1509), .Y(n1507) );
OAI22X1TS U2434 ( .A0(n1508), .A1(n1824), .B0(n1546), .B1(n1507), .Y(n2013)
);
AOI22X1TS U2435 ( .A0(n1573), .A1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[23]), .B0(
n1546), .B1(n1509), .Y(n1511) );
AOI21X1TS U2436 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[48]), .A1(
n1529), .B0(n1528), .Y(n1510) );
NAND2X1TS U2437 ( .A(n1511), .B(n1510), .Y(n1988) );
MXI2X1TS U2438 ( .A(n1753), .B(n1776), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intM[22]) );
AOI22X1TS U2439 ( .A0(n1513), .A1(n1546), .B0(n1573), .B1(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[24]), .Y(
n1515) );
AOI21X1TS U2440 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[47]), .A1(
n1529), .B0(n1528), .Y(n1514) );
NAND2X1TS U2441 ( .A(n1515), .B(n1514), .Y(n1989) );
MXI2X1TS U2442 ( .A(n1792), .B(n1835), .S0(n1516), .Y(
add_subt_module_Oper_Start_in_module_intM[21]) );
MXI2X1TS U2443 ( .A(n1752), .B(n1836), .S0(n1585), .Y(
add_subt_module_Oper_Start_in_module_intM[20]) );
MXI2X1TS U2444 ( .A(n1789), .B(n1774), .S0(n1512), .Y(
add_subt_module_Oper_Start_in_module_intM[19]) );
MXI2X1TS U2445 ( .A(n1751), .B(n1841), .S0(n1585), .Y(
add_subt_module_Oper_Start_in_module_intM[18]) );
AOI21X1TS U2446 ( .A0(n1518), .A1(n1517), .B0(n691), .Y(n1520) );
AOI21X1TS U2447 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .A1(
n1529), .B0(n1528), .Y(n1519) );
MXI2X1TS U2448 ( .A(n1788), .B(n1842), .S0(n1584), .Y(
add_subt_module_Oper_Start_in_module_intM[17]) );
AOI21X1TS U2449 ( .A0(n1522), .A1(n1521), .B0(n691), .Y(n1524) );
AOI21X1TS U2450 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[42]), .A1(
n1529), .B0(n1528), .Y(n1523) );
MXI2X1TS U2451 ( .A(n1807), .B(n1832), .S0(n1585), .Y(
add_subt_module_Oper_Start_in_module_intM[16]) );
AOI21X1TS U2452 ( .A0(n1527), .A1(n1526), .B0(n1525), .Y(n1531) );
AOI21X1TS U2453 ( .A0(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[41]), .A1(
n1529), .B0(n1528), .Y(n1530) );
MXI2X1TS U2454 ( .A(n1791), .B(n1843), .S0(n1516), .Y(
add_subt_module_Oper_Start_in_module_intM[15]) );
MXI2X1TS U2455 ( .A(n1750), .B(n1775), .S0(n1585), .Y(
add_subt_module_Oper_Start_in_module_intM[14]) );
MXI2X1TS U2456 ( .A(n1790), .B(n1834), .S0(n1584), .Y(
add_subt_module_Oper_Start_in_module_intM[13]) );
MXI2X1TS U2457 ( .A(n1833), .B(n1787), .S0(n1585), .Y(
add_subt_module_Oper_Start_in_module_intM[12]) );
MXI2X1TS U2458 ( .A(n1782), .B(n1840), .S0(n1489), .Y(
add_subt_module_Oper_Start_in_module_intM[11]) );
OAI222X1TS U2459 ( .A0(n1536), .A1(n1767), .B0(n1817), .B1(n1535), .C0(n1534), .C1(n1533), .Y(n1545) );
NAND2X1TS U2460 ( .A(n1537), .B(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[43]), .Y(
n1538) );
AOI21X1TS U2461 ( .A0(n1543), .A1(n1542), .B0(n1541), .Y(n1544) );
OAI2BB1X1TS U2462 ( .A0N(n1546), .A1N(n1545), .B0(n1544), .Y(n2001) );
BUFX3TS U2463 ( .A(n1583), .Y(n1580) );
AOI21X1TS U2464 ( .A0(n1552), .A1(n1525), .B0(n1551), .Y(n1553) );
AOI21X1TS U2465 ( .A0(n986), .A1(n1555), .B0(n1554), .Y(n1556) );
OAI2BB1X1TS U2466 ( .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[44]), .A1N(
n1573), .B0(n1556), .Y(n1999) );
AOI21X1TS U2467 ( .A0(n1558), .A1(n1525), .B0(n1557), .Y(n1559) );
AOI21X1TS U2468 ( .A0(n986), .A1(n1561), .B0(n1560), .Y(n1562) );
OAI2BB1X1TS U2469 ( .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[45]), .A1N(
n1573), .B0(n1562), .Y(n1993) );
AOI21X1TS U2470 ( .A0(n1566), .A1(n1525), .B0(n1565), .Y(n1567) );
AOI21X1TS U2471 ( .A0(n986), .A1(n1571), .B0(n1570), .Y(n1572) );
OAI2BB1X1TS U2472 ( .A0N(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[46]), .A1N(
n1573), .B0(n1572), .Y(n1995) );
BUFX3TS U2473 ( .A(n1670), .Y(n1672) );
NAND2X1TS U2474 ( .A(n1672), .B(n1757), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[3]) );
NAND2X1TS U2475 ( .A(n1574), .B(n1796), .Y(
add_subt_module_final_result_ieee_Module_Exp_S_mux[4]) );
AOI21X1TS U2477 ( .A0(n1777), .A1(n1874), .B0(overflow_flag), .Y(
add_subt_module_final_result_ieee_Module_Sign_S_mux) );
AOI211X1TS U2478 ( .A0(add_subt_module_FS_Module_state_reg[0]), .A1(
add_subt_module_FSM_Add_Subt_Sgf_load), .B0(n1952), .C0(n669), .Y(
n1579) );
NOR3X1TS U2479 ( .A(n1856), .B(n1576), .C(n1575), .Y(n1578) );
AOI22X1TS U2480 ( .A0(n1580), .A1(n1852), .B0(n1769), .B1(n1584), .Y(
add_subt_module_Oper_Start_in_module_intm[0]) );
INVX2TS U2481 ( .A(n1532), .Y(n1584) );
AOI22X1TS U2482 ( .A0(n1580), .A1(n713), .B0(n1800), .B1(n1489), .Y(
add_subt_module_Oper_Start_in_module_intm[1]) );
AOI22X1TS U2483 ( .A0(n1580), .A1(n1821), .B0(n1759), .B1(n1489), .Y(
add_subt_module_Oper_Start_in_module_intm[2]) );
AOI22X1TS U2484 ( .A0(n1580), .A1(n1851), .B0(n1798), .B1(n1585), .Y(
add_subt_module_Oper_Start_in_module_intm[3]) );
AOI22X1TS U2485 ( .A0(n1580), .A1(n1820), .B0(n1761), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[4]) );
AOI22X1TS U2486 ( .A0(n1580), .A1(n1819), .B0(n1806), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[5]) );
BUFX3TS U2487 ( .A(n1583), .Y(n1582) );
AOI22X1TS U2488 ( .A0(n1582), .A1(n1848), .B0(n1746), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[6]) );
AOI22X1TS U2489 ( .A0(n1582), .A1(n1822), .B0(n1813), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[7]) );
AOI22X1TS U2490 ( .A0(n1582), .A1(n1850), .B0(n1799), .B1(n1584), .Y(
add_subt_module_Oper_Start_in_module_intm[8]) );
AOI22X1TS U2491 ( .A0(n1582), .A1(n1823), .B0(n1758), .B1(n1516), .Y(
add_subt_module_Oper_Start_in_module_intm[9]) );
AOI22X1TS U2492 ( .A0(n1582), .A1(n1849), .B0(n1760), .B1(n1584), .Y(
add_subt_module_Oper_Start_in_module_intm[10]) );
AOI22X1TS U2493 ( .A0(n1582), .A1(n1840), .B0(n1782), .B1(n1516), .Y(
add_subt_module_Oper_Start_in_module_intm[11]) );
AOI22X1TS U2494 ( .A0(n1582), .A1(n1787), .B0(n1833), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[12]) );
AOI22X1TS U2495 ( .A0(n1582), .A1(n1834), .B0(n1790), .B1(n1516), .Y(
add_subt_module_Oper_Start_in_module_intm[13]) );
AOI22X1TS U2496 ( .A0(n1582), .A1(n1775), .B0(n1750), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[14]) );
AOI22X1TS U2497 ( .A0(n1582), .A1(n1843), .B0(n1791), .B1(n1584), .Y(
add_subt_module_Oper_Start_in_module_intm[15]) );
AOI22X1TS U2498 ( .A0(n1583), .A1(n1832), .B0(n1807), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[16]) );
AOI22X1TS U2499 ( .A0(n1547), .A1(n1842), .B0(n1788), .B1(n1516), .Y(
add_subt_module_Oper_Start_in_module_intm[17]) );
AOI22X1TS U2500 ( .A0(n1547), .A1(n1841), .B0(n1751), .B1(n1489), .Y(
add_subt_module_Oper_Start_in_module_intm[18]) );
AOI22X1TS U2501 ( .A0(n1580), .A1(n1774), .B0(n1789), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[19]) );
AOI22X1TS U2502 ( .A0(n1583), .A1(n1836), .B0(n1752), .B1(n1489), .Y(
add_subt_module_Oper_Start_in_module_intm[20]) );
AOI22X1TS U2503 ( .A0(n1583), .A1(n1835), .B0(n1792), .B1(n1489), .Y(
add_subt_module_Oper_Start_in_module_intm[21]) );
AOI22X1TS U2504 ( .A0(n1583), .A1(n1776), .B0(n1753), .B1(n1581), .Y(
add_subt_module_Oper_Start_in_module_intm[22]) );
AOI22X1TS U2505 ( .A0(n1654), .A1(n1587), .B0(n703), .B1(n1586), .Y(n1594)
);
OA22X1TS U2506 ( .A0(n1591), .A1(n1590), .B0(n1589), .B1(n1588), .Y(n1592)
);
AOI32X1TS U2507 ( .A0(n1594), .A1(n1593), .A2(n1592), .B0(n1645), .B1(n1593),
.Y(add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[19]) );
AOI22X1TS U2508 ( .A0(n727), .A1(n1606), .B0(n1663), .B1(n1609), .Y(n1599)
);
AOI22X1TS U2509 ( .A0(n703), .A1(n1603), .B0(n1654), .B1(n1597), .Y(n1598)
);
NAND2X1TS U2510 ( .A(n1599), .B(n1598), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[12]) );
AOI22X1TS U2511 ( .A0(n706), .A1(n1609), .B0(n1129), .B1(n1612), .Y(n1605)
);
AOI22X1TS U2512 ( .A0(n702), .A1(n1606), .B0(n678), .B1(n1603), .Y(n1604) );
NAND2X1TS U2513 ( .A(n1605), .B(n1604), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[11]) );
AOI22X1TS U2514 ( .A0(n706), .A1(n1612), .B0(n1650), .B1(n1613), .Y(n1608)
);
AOI22X1TS U2515 ( .A0(n703), .A1(n1609), .B0(n678), .B1(n1606), .Y(n1607) );
NAND2X1TS U2516 ( .A(n1608), .B(n1607), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[10]) );
AOI22X1TS U2517 ( .A0(n706), .A1(n1613), .B0(n1663), .B1(n1616), .Y(n1611)
);
AOI22X1TS U2518 ( .A0(n702), .A1(n1612), .B0(n678), .B1(n1609), .Y(n1610) );
NAND2X1TS U2519 ( .A(n1611), .B(n1610), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[9]) );
AOI22X1TS U2520 ( .A0(n727), .A1(n1616), .B0(n1129), .B1(n1619), .Y(n1615)
);
AOI22X1TS U2521 ( .A0(n703), .A1(n1613), .B0(n678), .B1(n1612), .Y(n1614) );
NAND2X1TS U2522 ( .A(n1615), .B(n1614), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[8]) );
AOI22X1TS U2523 ( .A0(n706), .A1(n1623), .B0(n1129), .B1(n1624), .Y(n1618)
);
AOI22X1TS U2524 ( .A0(n702), .A1(n1619), .B0(n1654), .B1(n1616), .Y(n1617)
);
NAND2X1TS U2525 ( .A(n1618), .B(n1617), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[7]) );
AOI22X1TS U2526 ( .A0(n727), .A1(n1624), .B0(n1650), .B1(n1622), .Y(n1621)
);
AOI22X1TS U2527 ( .A0(n703), .A1(n1623), .B0(n1654), .B1(n1619), .Y(n1620)
);
NAND2X1TS U2528 ( .A(n1621), .B(n1620), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[6]) );
AOI22X1TS U2529 ( .A0(n706), .A1(n1622), .B0(n1663), .B1(n1629), .Y(n1626)
);
AOI22X1TS U2530 ( .A0(n702), .A1(n1624), .B0(n678), .B1(n1623), .Y(n1625) );
NAND2X1TS U2531 ( .A(n1626), .B(n1625), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[5]) );
AOI21X1TS U2532 ( .A0(add_subt_module_Add_Subt_result[4]), .A1(n697), .B0(
n1627), .Y(n1659) );
AOI22X1TS U2533 ( .A0(n706), .A1(n1642), .B0(n1650), .B1(n1649), .Y(n1631)
);
AOI22X1TS U2534 ( .A0(n703), .A1(n1635), .B0(n1654), .B1(n1629), .Y(n1630)
);
NAND2X1TS U2535 ( .A(n1631), .B(n1630), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[4]) );
AOI22X1TS U2536 ( .A0(n700), .A1(add_subt_module_Add_Subt_result[22]), .B0(
add_subt_module_DmP[1]), .B1(n1638), .Y(n1634) );
NAND2X1TS U2537 ( .A(n697), .B(add_subt_module_Add_Subt_result[3]), .Y(n1633) );
AOI22X1TS U2538 ( .A0(n727), .A1(n1649), .B0(n1663), .B1(n1653), .Y(n1637)
);
AOI22X1TS U2539 ( .A0(n703), .A1(n1642), .B0(n1654), .B1(n1635), .Y(n1636)
);
NAND2X1TS U2540 ( .A(n1637), .B(n1636), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[3]) );
AOI22X1TS U2541 ( .A0(n1657), .A1(add_subt_module_Add_Subt_result[23]), .B0(
add_subt_module_DmP[0]), .B1(n1638), .Y(n1641) );
NAND2X1TS U2542 ( .A(n696), .B(add_subt_module_Add_Subt_result[2]), .Y(n1640) );
AOI22X1TS U2543 ( .A0(n706), .A1(n1653), .B0(n1129), .B1(n1655), .Y(n1644)
);
AOI22X1TS U2544 ( .A0(n702), .A1(n1649), .B0(n1654), .B1(n1642), .Y(n1643)
);
NAND2X1TS U2545 ( .A(n1644), .B(n1643), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[2]) );
AOI22X1TS U2546 ( .A0(n727), .A1(n1655), .B0(n702), .B1(n1653), .Y(n1652) );
AOI22X1TS U2547 ( .A0(n696), .A1(add_subt_module_Add_Subt_result[1]), .B0(
n700), .B1(add_subt_module_Add_Subt_result[24]), .Y(n1647) );
AOI22X1TS U2548 ( .A0(n1648), .A1(n1647), .B0(n1646), .B1(n1645), .Y(n1664)
);
AOI22X1TS U2549 ( .A0(n1650), .A1(n1664), .B0(n678), .B1(n1649), .Y(n1651)
);
NAND2X1TS U2550 ( .A(n1652), .B(n1651), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[1]) );
AOI22X1TS U2551 ( .A0(n702), .A1(n1655), .B0(n678), .B1(n1653), .Y(n1667) );
AOI22X1TS U2552 ( .A0(n697), .A1(add_subt_module_Add_Subt_result[0]), .B0(
add_subt_module_Add_Subt_result[25]), .B1(n1657), .Y(n1660) );
AOI22X1TS U2553 ( .A0(n1661), .A1(n1660), .B0(n1659), .B1(n1142), .Y(n1662)
);
AOI22X1TS U2554 ( .A0(n706), .A1(n1664), .B0(n1650), .B1(n1662), .Y(n1666)
);
NAND2X1TS U2555 ( .A(n1667), .B(n1666), .Y(
add_subt_module_Barrel_Shifter_module_Mux_Array_Data_array[0]) );
NAND2X1TS U2556 ( .A(n1669), .B(n1668), .Y(n1725) );
BUFX3TS U2557 ( .A(n1670), .Y(n1671) );
INVX2TS U2558 ( .A(n1673), .Y(n1674) );
NOR3BX1TS U2559 ( .AN(n1675), .B(n1674), .C(
add_subt_module_Add_Subt_result[18]), .Y(n1681) );
OR4X2TS U2560 ( .A(n1681), .B(n1680), .C(n1679), .D(n1678), .Y(
add_subt_module_Leading_Zero_Detector_Module_Codec_to_Reg[3]) );
NOR2BX1TS U2561 ( .AN(d_ff_Yn[0]), .B(n1708), .Y(first_mux_Y[0]) );
NOR2BX1TS U2562 ( .AN(d_ff_Yn[1]), .B(n1682), .Y(first_mux_Y[1]) );
NOR2BX1TS U2563 ( .AN(d_ff_Yn[2]), .B(n1778), .Y(first_mux_Y[2]) );
NOR2BX1TS U2564 ( .AN(d_ff_Yn[3]), .B(n1024), .Y(first_mux_Y[3]) );
NOR2BX1TS U2565 ( .AN(d_ff_Yn[4]), .B(n1778), .Y(first_mux_Y[4]) );
NOR2BX1TS U2566 ( .AN(d_ff_Yn[5]), .B(n1025), .Y(first_mux_Y[5]) );
NOR2BX1TS U2567 ( .AN(d_ff_Yn[6]), .B(n1778), .Y(first_mux_Y[6]) );
NOR2BX1TS U2568 ( .AN(d_ff_Yn[7]), .B(n1023), .Y(first_mux_Y[7]) );
NOR2BX1TS U2569 ( .AN(d_ff_Yn[8]), .B(n1778), .Y(first_mux_Y[8]) );
NOR2BX1TS U2570 ( .AN(d_ff_Yn[9]), .B(n1778), .Y(first_mux_Y[9]) );
NOR2BX1TS U2571 ( .AN(d_ff_Yn[10]), .B(n1682), .Y(first_mux_Y[10]) );
NOR2BX1TS U2572 ( .AN(d_ff_Yn[11]), .B(n1024), .Y(first_mux_Y[11]) );
NOR2BX1TS U2573 ( .AN(d_ff_Yn[12]), .B(n1025), .Y(first_mux_Y[12]) );
NOR2BX1TS U2574 ( .AN(d_ff_Yn[13]), .B(n1023), .Y(first_mux_Y[13]) );
NOR2BX1TS U2575 ( .AN(d_ff_Yn[14]), .B(n1682), .Y(first_mux_Y[14]) );
NOR2BX1TS U2576 ( .AN(d_ff_Yn[15]), .B(n1024), .Y(first_mux_Y[15]) );
NOR2BX1TS U2577 ( .AN(d_ff_Yn[16]), .B(n1023), .Y(first_mux_Y[16]) );
NOR2BX1TS U2578 ( .AN(d_ff_Yn[17]), .B(n1024), .Y(first_mux_Y[17]) );
NOR2BX1TS U2579 ( .AN(d_ff_Yn[18]), .B(n1682), .Y(first_mux_Y[18]) );
NOR2BX1TS U2580 ( .AN(d_ff_Yn[19]), .B(n1025), .Y(first_mux_Y[19]) );
NOR2BX1TS U2581 ( .AN(d_ff_Yn[20]), .B(n1023), .Y(first_mux_Y[20]) );
NOR2BX1TS U2582 ( .AN(d_ff_Yn[21]), .B(n1682), .Y(first_mux_Y[21]) );
NOR2BX1TS U2583 ( .AN(d_ff_Yn[22]), .B(n1024), .Y(first_mux_Y[22]) );
NOR2BX1TS U2584 ( .AN(d_ff_Yn[23]), .B(n1025), .Y(first_mux_Y[23]) );
NOR2BX1TS U2585 ( .AN(d_ff_Yn[24]), .B(n1025), .Y(first_mux_Y[24]) );
NOR2BX1TS U2586 ( .AN(d_ff_Yn[25]), .B(n1707), .Y(first_mux_Y[25]) );
NOR2BX1TS U2587 ( .AN(d_ff_Yn[26]), .B(n1707), .Y(first_mux_Y[26]) );
NOR2BX1TS U2588 ( .AN(d_ff_Yn[27]), .B(n1707), .Y(first_mux_Y[27]) );
NOR2BX1TS U2589 ( .AN(d_ff_Yn[28]), .B(n1707), .Y(first_mux_Y[28]) );
NOR2BX1TS U2590 ( .AN(d_ff_Yn[29]), .B(n1707), .Y(first_mux_Y[29]) );
NOR2BX1TS U2591 ( .AN(d_ff_Yn[30]), .B(n1707), .Y(first_mux_Y[30]) );
NOR2BX1TS U2592 ( .AN(d_ff_Yn[31]), .B(n1707), .Y(first_mux_Y[31]) );
INVX2TS U2593 ( .A(n1686), .Y(n1685) );
INVX2TS U2594 ( .A(n1686), .Y(n1687) );
INVX2TS U2595 ( .A(n1695), .Y(n1689) );
BUFX3TS U2596 ( .A(n1691), .Y(n1690) );
INVX2TS U2597 ( .A(n1691), .Y(n1692) );
BUFX3TS U2598 ( .A(n1691), .Y(n1693) );
INVX2TS U2599 ( .A(n1691), .Y(n1694) );
XNOR2X1TS U2600 ( .A(data_output2_31_), .B(n1697), .Y(sign_inv_out[31]) );
AOI32X1TS U2601 ( .A0(n1705), .A1(n1704), .A2(cont_iter_out[1]), .B0(n705),
.B1(n1704), .Y(data_out_LUT[25]) );
NOR2BX1TS U2602 ( .AN(d_ff_Xn[0]), .B(n1707), .Y(first_mux_X[0]) );
NOR2BX1TS U2603 ( .AN(d_ff_Xn[4]), .B(n1707), .Y(first_mux_X[4]) );
NOR2BX1TS U2604 ( .AN(d_ff_Xn[8]), .B(n1023), .Y(first_mux_X[8]) );
NOR2BX1TS U2605 ( .AN(d_ff_Xn[9]), .B(n1707), .Y(first_mux_X[9]) );
NOR2BX1TS U2606 ( .AN(d_ff_Xn[11]), .B(n1708), .Y(first_mux_X[11]) );
NOR2BX1TS U2607 ( .AN(d_ff_Xn[15]), .B(n1708), .Y(first_mux_X[15]) );
NOR2BX1TS U2608 ( .AN(d_ff_Xn[18]), .B(n1708), .Y(first_mux_X[18]) );
NOR2BX1TS U2609 ( .AN(d_ff_Xn[21]), .B(n1708), .Y(first_mux_X[21]) );
NOR2BX1TS U2610 ( .AN(d_ff_Xn[22]), .B(n1708), .Y(first_mux_X[22]) );
NOR2BX1TS U2611 ( .AN(d_ff_Xn[23]), .B(n1708), .Y(first_mux_X[23]) );
NOR2BX1TS U2612 ( .AN(d_ff_Xn[30]), .B(n1708), .Y(first_mux_X[30]) );
NOR2BX1TS U2613 ( .AN(d_ff_Xn[31]), .B(n1708), .Y(first_mux_X[31]) );
AOI22X1TS U2614 ( .A0(n1712), .A1(d_ff3_sh_x_out[15]), .B0(n1711), .B1(
d_ff3_sh_y_out[15]), .Y(n1714) );
NAND2X1TS U2615 ( .A(n1714), .B(n1713), .Y(n652) );
AOI22X1TS U2616 ( .A0(n1718), .A1(n1717), .B0(n1716), .B1(n1715), .Y(n604)
);
INVX2TS U2617 ( .A(n1718), .Y(n1719) );
XNOR2X1TS U2619 ( .A(d_ff2_Y[29]), .B(n1728), .Y(sh_exp_y[6]) );
XNOR2X1TS U2620 ( .A(d_ff2_X[29]), .B(n1731), .Y(sh_exp_x[6]) );
initial $sdf_annotate("CORDIC_Arch2_ASIC_fpu_syn_constraints_clk10.tcl_GATED_syn.sdf");
endmodule
|
module BoothPPG_32R4(a ,b, sign,
i, pp0, pp1, pp2, pp3,
pp4, pp5, pp6, pp7,
pp8, pp9, pp10, pp11,
pp12, pp13, pp14, pp15,
pp16);
input wire[31:0] a;
input wire[31:0] b;
input wire sign;
output wire[15:0] i;
output wire[33:0] pp0;
output wire[33:0] pp1;
output wire[33:0] pp2;
output wire[33:0] pp3;
output wire[33:0] pp4;
output wire[33:0] pp5;
output wire[33:0] pp6;
output wire[33:0] pp7;
output wire[33:0] pp8;
output wire[33:0] pp9;
output wire[33:0] pp10;
output wire[33:0] pp11;
output wire[33:0] pp12;
output wire[33:0] pp13;
output wire[33:0] pp14;
output wire[33:0] pp15;
output wire[31:0] pp16;
assign i[15:0] = {b[31], b[29], b[27], b[25], b[23], b[21], b[19], b[17], b[15], b[13], b[11], b[9], b[7], b[5], b[3], b[1]};
BoothPPG_32R4_NORM ppg0( .mulcand(a), .r4input({b[1:0],1'b0}), .sign(sign), .pp(pp0));
BoothPPG_32R4_NORM ppg1( .mulcand(a), .r4input(b[3:1]), .sign(sign), .pp(pp1));
BoothPPG_32R4_NORM ppg2( .mulcand(a), .r4input(b[5:3]), .sign(sign), .pp(pp2));
BoothPPG_32R4_NORM ppg3( .mulcand(a), .r4input(b[7:5]), .sign(sign), .pp(pp3));
BoothPPG_32R4_NORM ppg4( .mulcand(a), .r4input(b[9:7]), .sign(sign), .pp(pp4));
BoothPPG_32R4_NORM ppg5( .mulcand(a), .r4input(b[11:9]), .sign(sign), .pp(pp5));
BoothPPG_32R4_NORM ppg6( .mulcand(a), .r4input(b[13:11]), .sign(sign), .pp(pp6));
BoothPPG_32R4_NORM ppg7( .mulcand(a), .r4input(b[15:13]), .sign(sign), .pp(pp7));
BoothPPG_32R4_NORM ppg8( .mulcand(a), .r4input(b[17:15]), .sign(sign), .pp(pp8));
BoothPPG_32R4_NORM ppg9( .mulcand(a), .r4input(b[19:17]), .sign(sign), .pp(pp9));
BoothPPG_32R4_NORM ppg10(.mulcand(a), .r4input(b[21:19]), .sign(sign), .pp(pp10));
BoothPPG_32R4_NORM ppg11(.mulcand(a), .r4input(b[23:21]), .sign(sign), .pp(pp11));
BoothPPG_32R4_NORM ppg12(.mulcand(a), .r4input(b[25:23]), .sign(sign), .pp(pp12));
BoothPPG_32R4_NORM ppg13(.mulcand(a), .r4input(b[27:25]), .sign(sign), .pp(pp13));
BoothPPG_32R4_NORM ppg14(.mulcand(a), .r4input(b[29:27]), .sign(sign), .pp(pp14));
BoothPPG_32R4_NORM ppg15(.mulcand(a), .r4input(b[31:29]), .sign(sign), .pp(pp15));
BoothPPG_32R4_MSB ppg16(.mulcand(a), .msb(b[31]), .sign(sign), .pp(pp16));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EBUFN_PP_BLACKBOX_V
`define SKY130_FD_SC_MS__EBUFN_PP_BLACKBOX_V
/**
* ebufn: Tri-state buffer, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__ebufn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__EBUFN_PP_BLACKBOX_V
|
(*
* Copyright © 2013 http://io7m.com
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*)
(** The virtual filesystem. *)
Require Coq.Lists.List.
Require Archive.
Require ArchiveHandler.
Require Error.
Require FilesystemOp.
Require FilesystemRef.
Require ListAux.
Require ListMapWeak.
Require ListSetWeak.
Require ListNonEmptyStack.
Require ListStack.
Require MapWeak.
Require MapWeakAux.
Require PathReal.
Require PathVirtual.
Import Error.Notations.
Import ListAux.Notations.
(** Abbreviations. *)
Module FOp := FilesystemOp.
Module FRef := FilesystemRef.
Open Scope error_monad_scope.
Open Scope list_scope.
(** This file is broken into a [Signature] and [Implementation] section. The
[Signature] type documents the interface exposed by filesystem implementations
and the [Implementation] type documents the expected semantics of the
implementations. The semantics are given in terms of pure functional programs
with additional proofs that these programs are correct. It is expected that this
will be enough information to derive an implementation in an imperative language
such as Java. *)
(** The interface exposed by filesystem implementations. *)
Module Type Signature.
(** The type of filesystems. *)
Parameter t : Type.
(** Initialize a filesystem using the directory [p] in which to search for archive files. *)
Parameter make_with_path : forall (p : PathReal.t), t.
(** Initialize a filesystem without specifying an archive directory. *)
Parameter make : unit -> t.
(** Obtain a reference to the file or directory at the given [p]. Returns:
- [Success (Some r)] where [r] is a reference to the file or directory, if it exists.
- [Success None] if the file or directory does not exist.
- [Failure e] for some [e], if the object does not exist or if an I/O or other error occurs. *)
Parameter lookup : forall (p : PathVirtual.t) (f : t), FOp.t (option FRef.t).
(** Create a directory [p], including all ancestors of [p] if necessary. *)
Parameter create_directory : forall (p : PathVirtual.t) (f : t), FOp.t t.
(** Mount the archive named [a] at [p]. *)
Parameter mount : forall (p : PathVirtual.t) (a : Names.t) (f : t), FOp.t t.
End Signature.
(** The expected semantics of filesystem implementations. *)
Module Implementation : Signature.
Module Stacks := ListNonEmptyStack.Make.
Module PVS := PathVirtual.Sets.
Module PVM := PathVirtual.Maps.
Module PVMA := MapWeakAux.Make (PVM).
Module E := Error.
(** Filesystems maintain the following state: *)
Inductive fs := Filesystem {
(** A set of explicitly-created virtual directories... *)
fs_directories : PVS.t;
(** ... of which [root] is always a member, and: *)
fs_directories_root : PVS.is_in PathVirtual.root fs_directories;
(** A set of mappings from virtual paths to non-empty stacks of archives... *)
fs_mounts : PVM.t (Stacks.t Archive.t);
(** ... such that each the mount path of each archive in the stack matches
that of the key with which the stack is associated in the map. *)
fs_mounts_paths :
PVM.for_all_mappings (fun k s =>
Stacks.for_all (fun a => Archive.mount_path a = k) s) fs_mounts;
(** Optionally, the name of a directory containing archive files. *)
fs_archive_path : option PathReal.t;
(** A list of archive type handlers. *)
fs_handlers : list ArchiveHandler.t
}.
Definition t := fs.
(** In order to provide the required semantics for [mount], filesystems need to
distinguish between directories provided by archives, and directories created
explicitly with [create_directory]. *)
Inductive fs_ref : Set :=
| FSRFile : PathVirtual.t -> fs_ref
| FSRDirectoryArchive : PathVirtual.t -> fs_ref
| FSRDirectoryCreated : PathVirtual.t -> fs_ref.
(** Each reference holds the path to the object. *)
Definition fs_ref_path (f : fs_ref) : PathVirtual.t :=
match f with
| FSRFile p => p
| FSRDirectoryArchive p => p
| FSRDirectoryCreated p => p
end.
(** There is a straightforward translation from internal filesystem references
to [FRef.t]. *)
Definition fs_ref_convert (r : fs_ref) : FRef.t :=
match r with
| FSRFile p => FRef.FSFile p
| FSRDirectoryArchive p => FRef.FSDirectory p
| FSRDirectoryCreated p => FRef.FSDirectory p
end.
(** The conversion maintains the correct paths. *)
Theorem fs_ref_convert_correct : forall
(f : fs_ref)
(p : PathVirtual.t),
fs_ref_path f = FRef.path (fs_ref_convert f).
Proof.
destruct f; reflexivity.
Qed.
(** Construct a new filesystem using [p] as the directory in which to look for archives. *)
Definition make_with_path (p : PathReal.t) : t.
Proof.
refine (Filesystem
(PVS.singleton PathVirtual.root)
_
(@PVM.empty (Stacks.t Archive.t))
_
(Some p)
ArchiveHandler.handlers).
destruct (PathVirtual.eq_decidable PathVirtual.root p) as [Heq|Hneq].
rewrite Heq.
rewrite PVS.singleton_eq; apply (PVS.insert_is_in p).
rewrite PVS.singleton_eq; apply (PVS.insert_is_in PathVirtual.root).
apply PVM.for_all_mappings_empty.
Qed.
(** Construct a new filesystem without a directory in which to look for archives. *)
Definition make (_ : unit) : t.
Proof.
refine (Filesystem
(PVS.singleton PathVirtual.root)
_
(@PVM.empty (Stacks.t Archive.t))
_
None
ArchiveHandler.handlers).
rewrite PVS.singleton_eq; apply (PVS.insert_is_in PathVirtual.root).
apply PVM.for_all_mappings_empty.
Qed.
Definition is_mounted_at
(p : PathVirtual.t)
(a : Archive.t)
(f : fs)
: Prop :=
match PVM.lookup p (fs_mounts f) with
| Some s => Stacks.is_in a s
| None => False
end.
(** File lookups. *)
Module Type LookupInterface.
Parameter lookup : forall (p : PathVirtual.t) (f : t), FOp.t (option FRef.t).
Parameter lookup_internal : forall (p : PathVirtual.t) (f : t), FOp.t (option fs_ref).
Parameter lookup_internal_path : forall
(p : PathVirtual.t)
(f : fs)
(r : fs_ref),
lookup_internal p f = E.Success (Some r) -> fs_ref_path r = p.
Parameter lookup_internal_created : forall
(p : PathVirtual.t)
(f : fs),
PVS.is_in p (fs_directories f) ->
lookup_internal p f = E.Success (Some (FSRDirectoryCreated p)).
Parameter lookup_internal_root : forall
(f : fs),
lookup_internal PathVirtual.root f =
E.Success (Some (FSRDirectoryCreated PathVirtual.root)).
Parameter lookup_path : forall
(p : PathVirtual.t)
(f : fs)
(r : FRef.t),
lookup p f = E.Success (Some r) -> FRef.path r = p.
Parameter lookup_root : forall
(f : fs),
lookup PathVirtual.root f =
E.Success (Some (FRef.FSDirectory PathVirtual.root)).
End LookupInterface.
Module Lookup : LookupInterface.
(** Attempt to lookup [p] in [a], classifying the result. *)
Definition lookup_internal_in_archive
(p : PathVirtual.t)
(a : { a : Archive.t | Archive.contains p a })
: FOp.t (option fs_ref) :=
match a with
| exist a _ =>
let arc_m := Archive.mount_path a in
let arc_p := PathVirtual.subtract p arc_m in
(Archive.lookup a) arc_p >>= (fun r =>
match r with
| None => E.Success None
| Some r =>
match r with
| FRef.FSFile rp => E.Success (Some (FSRFile (arc_m ++ rp)))
| FRef.FSDirectory rp => E.Success (Some (FSRDirectoryArchive (arc_m ++ rp)))
end
end)
end.
(** Looking up the root directory always succeeds. *)
Theorem lookup_internal_in_archive_root : forall
(a : { a : Archive.t | Archive.contains PathVirtual.root a }),
lookup_internal_in_archive PathVirtual.root a =
E.Success (Some (FSRDirectoryArchive PathVirtual.root)).
Proof.
intros.
unfold lookup_internal_in_archive.
destruct a as [a Ha].
unfold Archive.contains in Ha.
assert (Archive.mount_path a = PathVirtual.root) as H_root.
apply (PathVirtual.contains_is_root).
assumption.
rewrite H_root.
rewrite PathVirtual.subtract_root.
rewrite Archive.lookup_root.
reflexivity.
Qed.
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_in_archive_same : forall
(p : PathVirtual.t)
(a : { a : Archive.t | Archive.contains p a })
(r : fs_ref),
lookup_internal_in_archive p a = E.Success (Some r) ->
fs_ref_path r = p.
Proof.
intros p a r H_succ.
destruct a as [a Hc].
unfold Archive.contains in Hc.
unfold lookup_internal_in_archive in H_succ.
remember (PathVirtual.subtract p (Archive.mount_path a)) as H_psubm.
destruct (E.bind_inversion _ _ _ _ _ _ H_succ) as [opt_r Hinv].
clear H_succ.
destruct Hinv as [Hinv_L Hinv_R].
destruct opt_r as [some_r|].
destruct some_r as [rp|rp].
(*
For each of the possible [lookup] cases, it's necessary to
show that [(Archive.mount_path a) ++ rp = p], where [rp] is
the path in the returned reference.
*)
cut ((Archive.mount_path a) ++ rp = p).
intros Hrpe.
rewrite Hrpe in Hinv_R.
injection Hinv_R.
intros H_inj.
rewrite <- H_inj.
reflexivity.
pose proof (Archive.lookup_same a H_psubm _ Hinv_L) as H_lookup_same.
simpl in H_lookup_same.
pose proof (PathVirtual.contains_subtract_id _ _ Hc) as H_app.
rewrite H_lookup_same.
rewrite HeqH_psubm.
assumption.
cut ((Archive.mount_path a) ++ rp = p).
intros Hrpe.
rewrite Hrpe in Hinv_R.
injection Hinv_R.
intros H_inj.
rewrite <- H_inj.
reflexivity.
pose proof (Archive.lookup_same a H_psubm _ Hinv_L) as H_lookup_same.
simpl in H_lookup_same.
pose proof (PathVirtual.contains_subtract_id _ _ Hc) as H_app.
rewrite H_lookup_same.
rewrite HeqH_psubm.
assumption.
discriminate.
Qed.
Definition archive_contains_iter
(s : Stacks.t Archive.t)
(p : PathVirtual.t)
(f : forall x, List.In x (Stacks.peek_list s) -> Archive.contains p x)
(ap : { x : Archive.t | List.In x (Stacks.peek_list s) })
: { x : Archive.t | Archive.contains p x } :=
match ap with
| exist x p => exist _ x (f x p)
end.
Definition stacks_contains_forall_function : forall
(p : PathVirtual.t)
(s : Stacks.t Archive.t)
(Hc : Stacks.for_all (Archive.contains p) s),
(forall a : Archive.t, List.In a (Stacks.peek_list s) -> Archive.contains p a).
Proof.
intros.
destruct (Stacks.for_all_peek (Archive.contains p) s) as [HfaL HfaR].
pose proof (HfaL Hc) as Hlfa.
clear HfaL.
clear HfaR.
destruct (List.Forall_forall (Archive.contains p) (Stacks.peek_list s)) as [HfaL HfaR].
pose proof (HfaL Hlfa) as Hlistfa.
clear HfaL.
clear HfaR.
clear Hlfa.
apply Hlistfa.
assumption.
Qed.
(** Try to obtain a reference to the file or directory named by [p]
in the given archive stack [s]. *)
Definition lookup_internal_in_archives
(p : PathVirtual.t)
(s : Stacks.t Archive.t)
(Hc : Stacks.for_all (Archive.contains p) s)
: FOp.t (option fs_ref) :=
let stack := ListAux.in_list (Stacks.peek_list s) in
let archives := List.map (archive_contains_iter s p (stacks_contains_forall_function p s Hc)) stack in
E.find_m (lookup_internal_in_archive p) archives.
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_in_archives_same : forall
(p : PathVirtual.t)
(s : Stacks.t Archive.t)
(Hc : Stacks.for_all (Archive.contains p) s)
(r : fs_ref),
lookup_internal_in_archives p s Hc = E.Success (Some r) ->
fs_ref_path r = p.
Proof.
intros p s Hc r H_succ.
unfold lookup_internal_in_archives in H_succ.
remember (lookup_internal_in_archive p) as Hf.
remember (ListAux.in_list (Stacks.peek_list s)) as H_stack.
remember (List.map (archive_contains_iter s p (stacks_contains_forall_function p s Hc)) H_stack) as H_arcs.
assert (H_arcs <> nil) as H_arcs_not_nil.
rewrite HeqH_arcs.
apply ListAux.map_preserves_not_nil.
rewrite HeqH_stack.
apply ListAux.in_list_preserves_not_nil.
apply Stacks.peek_list_not_empty.
destruct (Error.find_success_some _ _ _ Hf H_arcs r H_succ) as [k Hk].
rewrite HeqHf in Hk.
apply (lookup_internal_in_archive_same p k r Hk).
Qed.
(** Looking up the root directory always succeeds. *)
Theorem lookup_internal_in_archives_root : forall
(s : Stacks.t Archive.t)
(Hc : Stacks.for_all (Archive.contains PathVirtual.root) s),
lookup_internal_in_archives PathVirtual.root s Hc =
E.Success (Some (FSRDirectoryArchive PathVirtual.root)).
Proof.
intros.
unfold lookup_internal_in_archives.
remember (lookup_internal_in_archive PathVirtual.root) as Hf.
remember (ListAux.in_list (Stacks.peek_list s)) as H_stack.
remember (List.map (archive_contains_iter s PathVirtual.root
(stacks_contains_forall_function PathVirtual.root s Hc)) H_stack) as H_arcs.
assert (H_arcs <> nil) as H_arcs_not_nil.
rewrite HeqH_arcs.
apply ListAux.map_preserves_not_nil.
rewrite HeqH_stack.
apply ListAux.in_list_preserves_not_nil.
apply Stacks.peek_list_not_empty.
destruct H_arcs.
contradict H_arcs_not_nil; reflexivity.
pose proof (lookup_internal_in_archive_root s0) as H_root.
rewrite HeqHf.
simpl.
rewrite H_root.
reflexivity.
Qed.
Theorem stacks_mount_path_implies_contains : forall
(m : PathVirtual.t)
(s : Stacks.t Archive.t)
(Hc : Stacks.for_all (fun a => Archive.mount_path a = m) s),
Stacks.for_all (Archive.contains m) s.
Proof.
intros.
apply (@Stacks.for_all_implication Archive.t
(fun a => Archive.mount_path a = m) _
(fun a => Archive.mount_path_implies_contains m a) s Hc).
Qed.
Theorem stacks_mount_path_implies_contains_all : forall
(m p : PathVirtual.t)
(s : Stacks.t Archive.t)
(Hpc : PathVirtual.contains m p)
(Hac : Stacks.for_all (Archive.contains m) s),
Stacks.for_all (Archive.contains p) s.
Proof.
intros.
apply (@Stacks.for_all_implication Archive.t
(fun a => Archive.contains m a)
(fun a => Archive.contains p a)).
intros a Hacm.
apply (Archive.contains_transitive p m a); assumption.
assumption.
Qed.
(** Look up [p] in the stack of archives mounted at [m], if any. *)
Definition lookup_internal_in_mount_contains
(p : PathVirtual.t)
(f : fs)
(m : PathVirtual.t)
(Hc : PathVirtual.contains m p)
: FOp.t (option fs_ref) :=
match PVMA.lookup_ex m (fs_mounts f) with
| Some (exist s H_maps) =>
(** Compute a proof that all archives at [m] contain [p]. *)
let H_contains_m := PVM.for_all_mappings_maps _ (fs_mounts f) m _ (fs_mounts_paths f) H_maps in
let H_contains_m_all := stacks_mount_path_implies_contains m s H_contains_m in
let H_contains_p_all := stacks_mount_path_implies_contains_all m p s Hc H_contains_m_all in
lookup_internal_in_archives p s H_contains_p_all
| None => E.Success None
end.
(** Looking up the root directory always succeeds. *)
Theorem lookup_internal_in_mount_contains_root : forall
(f : fs)
(m : PathVirtual.t)
(Hc : PathVirtual.contains m PathVirtual.root),
(lookup_internal_in_mount_contains PathVirtual.root f m Hc = E.Success None) \/
(lookup_internal_in_mount_contains PathVirtual.root f m Hc =
E.Success (Some (FSRDirectoryArchive PathVirtual.root))).
Proof.
intros f m Hc.
unfold lookup_internal_in_mount_contains.
destruct (PVMA.lookup_ex m (fs_mounts f)) as [[s Hs]|].
remember (PVM.for_all_mappings_maps _ (fs_mounts f) m _ (fs_mounts_paths f) Hs)
as H_contains_m.
remember (stacks_mount_path_implies_contains m s H_contains_m)
as H_contains_m_all.
remember (stacks_mount_path_implies_contains_all m PathVirtual.root s _ H_contains_m_all)
as H_contains_p_all.
rewrite (lookup_internal_in_archives_root).
right; reflexivity.
left; reflexivity.
Qed.
(** If [m] contains [p], check for [p - m] in the stack of archives at [m], if any. *)
Definition lookup_internal_in_mount
(p : PathVirtual.t)
(f : fs)
(m : PathVirtual.t)
: FOp.t (option fs_ref) :=
match PathVirtual.contains_decidable m p with
| right _ => E.Success None
| left hc => lookup_internal_in_mount_contains p f m hc
end.
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_in_mount_path : forall
(p : PathVirtual.t)
(f : fs)
(m : PathVirtual.t)
r,
lookup_internal_in_mount p f m = E.Success (Some r) ->
fs_ref_path r = p.
Proof.
intros p f m r H_look.
unfold lookup_internal_in_mount in H_look.
destruct (PathVirtual.contains_decidable m p).
unfold lookup_internal_in_mount_contains in H_look.
destruct (PVMA.lookup_ex m (fs_mounts f)) as [[s Hs]|].
remember (PVM.for_all_mappings_maps _ (fs_mounts f) m _ (fs_mounts_paths f) Hs)
as H_contains_m.
remember (stacks_mount_path_implies_contains m s H_contains_m)
as H_contains_m_all.
remember (stacks_mount_path_implies_contains_all m p s c H_contains_m_all)
as H_contains_p_all.
apply (lookup_internal_in_archives_same p s H_contains_p_all r H_look).
discriminate.
discriminate.
Qed.
(** Looking up the root directory always succeeds. *)
Theorem lookup_internal_in_mount_root : forall
(f : fs)
(m : PathVirtual.t),
(lookup_internal_in_mount PathVirtual.root f m = E.Success None) \/
(lookup_internal_in_mount PathVirtual.root f m =
E.Success (Some (FSRDirectoryArchive PathVirtual.root))).
Proof.
intros f m.
unfold lookup_internal_in_mount.
destruct (PathVirtual.contains_decidable m PathVirtual.root) as [HcL|HcR].
destruct (lookup_internal_in_mount_contains_root f m HcL).
rewrite H.
left; reflexivity.
right; rewrite H; reflexivity.
left; reflexivity.
Qed.
(** Check all archives for the given [p]. Only archives that are mounted
at paths that contain (according to [PathVirtual.contains]) the given [p]
are checked. *)
Definition lookup_internal_in_mounts
(p : PathVirtual.t)
(f : fs)
: FOp.t (option fs_ref) :=
E.find_m (lookup_internal_in_mount p f) (PVM.keys (fs_mounts f)).
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_in_mounts_path : forall
(p : PathVirtual.t)
(f : fs)
r,
lookup_internal_in_mounts p f = E.Success (Some r) ->
fs_ref_path r = p.
Proof.
intros until r.
unfold lookup_internal_in_mounts.
remember (PVM.keys (fs_mounts f)) as H_mounts.
remember (lookup_internal_in_mount p f) as H_look.
intros H_find.
destruct (E.find_success_some _ _ _ H_look H_mounts r H_find).
rewrite HeqH_look in H.
apply (lookup_internal_in_mount_path p f x r H).
Qed.
(** Looking up the root directory always succeeds. *)
Theorem lookup_internal_in_mounts_root : forall (f : fs),
(lookup_internal_in_mounts PathVirtual.root f = E.Success None) \/
(lookup_internal_in_mounts PathVirtual.root f =
E.Success (Some (FSRDirectoryArchive PathVirtual.root))).
Proof.
intros f.
unfold lookup_internal_in_mounts.
induction (PVM.keys (fs_mounts f)) as [|kh kr].
simpl. left; reflexivity.
simpl.
destruct (lookup_internal_in_mount_root f kh).
rewrite H; auto.
rewrite H; auto.
Qed.
(** Check the set of explicitly-created virtual directories for [p]. *)
Definition lookup_internal_in_directories
(p : PathVirtual.t)
(f : fs)
: option fs_ref :=
match PVS.is_in_decidable p (fs_directories f) with
| left _ => Some (FSRDirectoryCreated p)
| right _ => None
end.
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_in_directories_path : forall
(p : PathVirtual.t)
(f : fs)
r,
lookup_internal_in_directories p f = (Some r) ->
fs_ref_path r = p.
Proof.
intros p f r.
unfold lookup_internal_in_directories.
intros H_look.
destruct (PVS.is_in_decidable p).
injection H_look.
intros H_eq.
rewrite <- H_eq.
reflexivity.
discriminate.
Qed.
(** Looking up [root] always succeeds and returns a created directory. *)
Theorem lookup_internal_in_directories_root : forall (f : fs),
lookup_internal_in_directories PathVirtual.root f =
Some (FSRDirectoryCreated PathVirtual.root).
Proof.
intros f.
unfold lookup_internal_in_directories.
destruct (PVS.is_in_decidable PathVirtual.root (fs_directories f)).
reflexivity.
contradict n.
exact (fs_directories_root f).
Qed.
(** Check all relevant archives and virtual directories for [p].
Note that if a directory exists in an archive and also exists in the list
of explicitly created directories, the explicitly created one takes precedence. *)
Definition lookup_internal_direct
(p : PathVirtual.t)
(f : fs)
: FOp.t (option fs_ref) :=
lookup_internal_in_mounts p f >>= (fun opt =>
match opt with
| None => E.Success (lookup_internal_in_directories p f)
| Some r =>
match r with
| FSRDirectoryArchive p => E.Success (lookup_internal_in_directories p f)
| FSRDirectoryCreated p => E.Success (lookup_internal_in_directories p f)
| FSRFile p => E.Success opt
end
end).
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_direct_path : forall
(p : PathVirtual.t)
(f : fs)
r,
lookup_internal_direct p f = E.Success (Some r) ->
fs_ref_path r = p.
Proof.
intros p f r.
unfold lookup_internal_direct.
intros H_look.
destruct (E.bind_inversion _ _ _ _ _ _ H_look) as [rr H_invR].
destruct H_invR as [H_invRL H_invRR].
rewrite H_invRL in H_look.
simpl in *.
destruct rr.
destruct f0.
rewrite H_invRR in H_invRL.
apply (lookup_internal_in_mounts_path p f r H_invRL).
injection H_invRR.
intros H_eq.
pose proof (lookup_internal_in_directories_path t0 f r H_eq) as H_dp.
pose proof (lookup_internal_in_mounts_path p f (FSRDirectoryArchive t0) H_invRL) as H_eq2.
rewrite <- H_dp in H_eq2.
assumption.
injection H_invRR.
intros H_eq.
pose proof (lookup_internal_in_directories_path t0 f r H_eq) as H_dp.
pose proof (lookup_internal_in_mounts_path p f (FSRDirectoryCreated t0) H_invRL) as H_eq2.
rewrite <- H_dp in H_eq2.
assumption.
injection H_invRR.
intros H_eq.
apply (lookup_internal_in_directories_path p f r H_eq).
Qed.
(** Check that the given [p] is a directory and fail if it isn't. *)
Definition check_directory
(p : PathVirtual.t)
(f : fs)
: FOp.t unit :=
match lookup_internal_direct p f with
| E.Failure e => E.Failure e
| E.Success None => E.Failure FOp.Error_Nonexistent
| E.Success (Some r) =>
match r with
| FSRFile _ => E.Failure FOp.Error_Not_A_Directory
| FSRDirectoryArchive _ => E.Success tt
| FSRDirectoryCreated _ => E.Success tt
end
end.
(** Check that all of the ancestors of [p] are directories. *)
Definition check_ancestor_directories
(p : PathVirtual.t)
(f : fs)
: FOp.t unit :=
E.fold_m (fun _ ancestor => check_directory ancestor f)
tt (PathVirtual.Enumeration.enumeration p).
(** Look up [p] in the filesystem, first checking if all ancestors of [p]
exist and are directories. *)
Definition lookup_internal
(p : PathVirtual.t)
(f : fs)
: FOp.t (option fs_ref) :=
check_ancestor_directories p f >> lookup_internal_direct p f.
(** The paths returned inside references will always match the original path. *)
Theorem lookup_internal_path : forall
(p : PathVirtual.t)
(f : fs)
r,
lookup_internal p f = E.Success (Some r) ->
fs_ref_path r = p.
Proof.
intros p f r.
unfold lookup_internal.
intros H_look.
destruct (E.bind_inversion _ _ _ _ _ _ H_look) as [rr H_invR].
destruct H_invR as [H_invRL H_invRR].
apply (lookup_internal_direct_path p f r H_invRR).
Qed.
(** Looking up [root] always succeeds and returns a created directory. *)
Theorem lookup_internal_root : forall
(f : fs),
lookup_internal PathVirtual.root f =
E.Success (Some (FSRDirectoryCreated PathVirtual.root)).
Proof.
intros f.
unfold lookup_internal.
simpl.
unfold lookup_internal_direct.
destruct (lookup_internal_in_mounts_root f) as [Hn|Hs].
rewrite Hn.
simpl.
rewrite (lookup_internal_in_directories_root f).
reflexivity.
rewrite Hs.
simpl.
rewrite (lookup_internal_in_directories_root f).
reflexivity.
Qed.
(** If [p] is in the filesystem's set of directories, [p] will always be returned
as a created directory. *)
Theorem lookup_internal_created : forall
(p : PathVirtual.t)
(f : fs),
PVS.is_in p (fs_directories f) ->
lookup_internal p f = E.Success (Some (FSRDirectoryCreated p)).
Proof.
intros p f H_in.
Admitted.
Definition lookup
(p : PathVirtual.t)
(f : fs)
: FOp.t (option FRef.t) :=
lookup_internal p f >>= (fun opt =>
match opt with
| Some r => E.Success (Some (fs_ref_convert r))
| None => E.Success None
end).
(** The paths returned inside references will always match the original path. *)
Theorem lookup_path : forall
(p : PathVirtual.t)
(f : fs)
r,
lookup p f = E.Success (Some r) ->
FRef.path r = p.
Proof.
intros p f r.
unfold lookup.
intros H_look.
destruct (E.bind_inversion _ _ _ _ _ _ H_look) as [rr H_invR].
destruct H_invR as [H_invRL H_invRR].
destruct rr.
injection H_invRR.
intros H_eq.
rewrite <- H_eq.
rewrite <- fs_ref_convert_correct.
apply (lookup_internal_path p f f0 H_invRL).
auto.
discriminate.
Qed.
(** Looking up [root] always succeeds and returns a created directory. *)
Theorem lookup_root : forall (f : fs),
lookup PathVirtual.root f =
E.Success (Some (FRef.FSDirectory PathVirtual.root)).
Proof.
intros f.
unfold lookup.
rewrite (lookup_internal_root f).
reflexivity.
Qed.
End Lookup.
(** Directory creation. *)
Module Type CreateDirectoryInterface.
Parameter create_directory : forall (p : PathVirtual.t) (f : t), FOp.t t.
Parameter create_directory_created : forall p f g,
create_directory p f = E.Success g ->
Lookup.lookup_internal p g = E.Success (Some (FSRDirectoryCreated p)).
End CreateDirectoryInterface.
Module CreateDirectory : CreateDirectoryInterface.
(** Add the directory [p] to the set of virtual directories in [f]. *)
Definition create_directory_insert
(p : PathVirtual.t)
(f : fs)
: fs.
Proof.
refine (Filesystem
(PVS.insert p (fs_directories f))
_
(fs_mounts f)
(fs_mounts_paths f)
(fs_archive_path f)
(fs_handlers f)).
destruct (PathVirtual.eq_decidable PathVirtual.root p) as [Heq|Hneq].
rewrite Heq.
apply (PVS.insert_is_in p (fs_directories f)).
apply (PVS.insert_preserves_is_in PathVirtual.root p (fs_directories f) Hneq (fs_directories_root f)).
Defined.
(** An inserted directory is definitely inserted. *)
Theorem create_directory_inserted : forall
(p : PathVirtual.t)
(f : fs),
PVS.is_in p (fs_directories (create_directory_insert p f)).
Proof.
intros.
apply (PVS.insert_is_in).
Qed.
Definition create_directory_internal_actual
(f : fs)
(p : PathVirtual.t)
: FOp.t t :=
Lookup.lookup_internal p f >>= (fun opt =>
match opt with
| None => E.Success (create_directory_insert p f)
| Some r =>
match r with
| FSRFile _ => E.Failure FOp.Error_Not_A_Directory
| FSRDirectoryArchive _ => E.Success f
| FSRDirectoryCreated _ => E.Success f
end
end).
Theorem create_directory_internal_actual_create : forall f p g,
create_directory_internal_actual f p = E.Success g ->
Lookup.lookup_internal p g = E.Success (Some (FSRDirectoryCreated p)) \/
Lookup.lookup_internal p g = E.Success (Some (FSRDirectoryArchive p)).
Proof.
intros f p g H_create.
destruct (E.bind_inversion _ _ _ _ _ _ H_create) as [h [HL HR]].
destruct h.
destruct f0.
discriminate.
injection HR.
intros Hfg.
rewrite <- Hfg.
right.
pose proof (Lookup.lookup_internal_path p f (FSRDirectoryArchive t0) HL) as H_path.
simpl in H_path.
rewrite <- H_path.
rewrite <- H_path in HL.
assumption.
injection HR.
intros Hfg.
rewrite <- Hfg.
left.
pose proof (Lookup.lookup_internal_path p f (FSRDirectoryCreated t0) HL) as H_path.
simpl in H_path.
rewrite <- H_path.
rewrite <- H_path in HL.
assumption.
injection HR.
intros Hfg.
rewrite <- Hfg.
pose proof (create_directory_inserted p f).
left. apply (Lookup.lookup_internal_created p _ H).
Qed.
Definition create_directory
(p : PathVirtual.t)
(f : fs)
: FOp.t t :=
E.fold_m create_directory_internal_actual f (PathVirtual.Enumeration.enumeration p).
Theorem create_directory_created : forall p f g,
create_directory p f = E.Success g ->
Lookup.lookup_internal p g = E.Success (Some (FSRDirectoryCreated p)).
Proof.
intros p f g.
unfold create_directory.
intros H_fold.
destruct (E.fold_success _ _ _ _ _ _ _ H_fold) as [H_fsl|H_fsr].
rewrite (PathVirtual.Enumeration.enumeration_is_root p H_fsl).
rewrite (Lookup.lookup_internal_root g).
reflexivity.
simpl.
induction (PathVirtual.Enumeration.enumeration p) as [|eh er].
Admitted.
End CreateDirectory.
(** Archive mounting. *)
Module Type MountInterface.
Parameter mount : forall (p : PathVirtual.t) (a : Names.t) (f : t), FOp.t t.
End MountInterface.
Module Mount : MountInterface.
(** Determine whether or not the given mount point is a directory. If it is,
determine if it is provided by an archive or was explicitly created. If it
was provided by an archive, explicitly create it. *)
Definition mount_check_point
(p : PathVirtual.t)
(f : fs)
: FOp.t t :=
Lookup.lookup_internal p f >>= (fun opt =>
match opt with
| Some (FSRFile r) => E.Failure FOp.Error_Not_A_Directory
| Some (FSRDirectoryArchive p) => CreateDirectory.create_directory p f
| Some (FSRDirectoryCreated p) => E.Success f
| None => E.Failure FOp.Error_Nonexistent
end).
Theorem mount_check_point_directory : forall p f g,
mount_check_point p f = E.Success g ->
Lookup.lookup_internal p g = E.Success (Some (FSRDirectoryCreated p)).
Proof.
intros p f g H_check.
destruct (E.bind_inversion _ _ _ _ _ _ H_check) as [opt [HbL HbR]].
destruct opt.
destruct f0.
discriminate.
assert (t0 = p) as H_eq.
pose proof (Lookup.lookup_internal_path p f (FSRDirectoryArchive t0) HbL).
assumption.
rewrite <- H_eq.
apply (CreateDirectory.create_directory_created t0 f g HbR).
assert (t0 = p) as H_eq.
pose proof (Lookup.lookup_internal_path p f (FSRDirectoryCreated t0) HbL).
assumption.
injection HbR; intros H_eq2.
rewrite <- H_eq in *.
rewrite <- H_eq2.
assumption.
discriminate.
Qed.
(** Mount the archive named [a], setting [m] as the mount point for the archive,
failing immediately if the given filesystem does not have a defined archive
directory. *)
Definition mount_load_archive
(a : Names.t)
(m : PathVirtual.t)
(f : fs)
: FOp.t Archive.t :=
match fs_archive_path f with
| None => E.Failure FOp.Error_Nonexistent
| Some d => ArchiveHandler.handle (fs_handlers f) (d @@ a) m
end.
(** Loaded archives have the correct mount paths. *)
Theorem mount_load_archive_path : forall
(a : Names.t)
(m : PathVirtual.t)
(f : fs)
(r : Archive.t),
mount_load_archive a m f = E.Success r ->
Archive.mount_path r = m.
Proof.
intros until r.
unfold mount_load_archive.
destruct (fs_archive_path f).
induction (fs_handlers f) as [|fh fr].
intros; discriminate.
simpl. destruct (ArchiveHandler.can_handle fh (t0 @@ a)).
intros.
apply (ArchiveHandler.load_path_correct fh (t0 @@ a) m r H).
apply IHfr.
intros; discriminate.
Qed.
(** If the mount [p] exists, push [a] onto the stack of archives. Otherwise,
create a new archive stack at [p] consisting of [a]. *)
Definition mount_push_or_singleton
(a : Archive.t)
(p : PathVirtual.t)
(ms : PVM.t (Stacks.t Archive.t))
(Hm : Archive.mount_path a = p)
: PVM.t (Stacks.t Archive.t) :=
match PVMA.lookup_ex p ms with
| Some (exist stack _) => PVM.insert p (Stacks.push a stack) ms
| None => PVM.insert p (Stacks.singleton a) ms
end.
(** [mount_push_or_singleton] is correct. *)
Theorem mount_push_or_singleton_is_in : forall
(a : Archive.t)
(p : PathVirtual.t)
(ms : PVM.t (Stacks.t Archive.t))
(Hm : Archive.mount_path a = p),
exists (s : Stacks.t Archive.t),
PVM.key_maps_to p s (mount_push_or_singleton a p ms Hm) /\ Stacks.is_in a s.
Proof.
intros.
unfold mount_push_or_singleton.
remember (PVMA.lookup_ex p ms) as H_look.
destruct H_look.
destruct s as [x Hx].
exists (Stacks.push a x).
split.
apply (PVM.insert_maps_to p (Stacks.push a x) ms).
apply (Stacks.push_in a x).
exists (Stacks.singleton a).
split.
apply (PVM.insert_maps_to p (Stacks.singleton a) ms).
apply (Stacks.singleton_in a).
Qed.
(** Inserted the loaded archive [a] at [p]. This function simply calculates
proofs, the actual "insert" semantics are given in [mount_push_or_singleton]. *)
Definition mount_insert_archive
(p : PathVirtual.t)
(f : fs)
(a : Archive.t)
(Hm : Archive.mount_path a = p)
: fs.
Proof.
refine (
Filesystem
(fs_directories f)
(fs_directories_root f)
(mount_push_or_singleton a p (fs_mounts f) Hm)
_
(fs_archive_path f)
(fs_handlers f)
).
unfold mount_push_or_singleton.
destruct (PVMA.lookup_ex p (fs_mounts f)) as [some|none].
destruct some as [s_existing H_p_maps_existing].
(** First, show that the paths are correct in the existing stack. *)
pose proof (fs_mounts_paths f)
as H_existing_mappings_all.
pose proof (PVM.for_all_mappings_maps _ (fs_mounts f) _ _ H_existing_mappings_all H_p_maps_existing)
as H_existing_stack_prop.
(** Then, given that the path is correct in the pushed archive, [P]
holds for the new stack. *)
pose proof (Stacks.for_all_push _ s_existing a H_existing_stack_prop Hm)
as H_pushed_stack_prop.
(** [P] held for the original map, and it holds for the new stack,
so it holds for the new map. *)
apply PVM.for_all_mappings_insert.
assumption.
assumption.
(** In this case, the stack being inserted is a singleton. If [P]
holds for the archive, it holds for the singleton. *)
pose proof (Stacks.for_all_singleton (fun a => Archive.mount_path a = p) a Hm)
as H_singleton.
pose proof (fs_mounts_paths f)
as H_existing_mappings_all.
(** [P] held for the original map, and it holds for the new stack,
so it holds for the new map. *)
apply PVM.for_all_mappings_insert.
assumption.
assumption.
Defined.
Definition mount
(p : PathVirtual.t)
(n : Names.t)
(f : fs)
: FOp.t t :=
mount_check_point p f >>= (fun g =>
match mount_load_archive n p g as mla
return (mount_load_archive n p g = mla -> FOp.t t)
with
| E.Failure e => fun _ => E.Failure e
| E.Success a => fun H => E.Success (mount_insert_archive p g a (mount_load_archive_path n p g a H))
end eq_refl).
(** A mounted archive is mounted. *)
Theorem mount_insert_archive_is_mounted : forall
(p : PathVirtual.t)
(f : fs)
(a : Archive.t)
(H : Archive.mount_path a = p),
is_mounted_at p a (mount_insert_archive p f a H).
Proof.
intros p f a H.
unfold is_mounted_at.
simpl.
unfold mount_insert_archive.
simpl.
remember (mount_push_or_singleton a p (fs_mounts f) H) as H_mpush.
destruct (mount_push_or_singleton_is_in a p (fs_mounts f) H) as [s Hs].
destruct Hs as [HsL HsR].
destruct (PVM.lookup_maps_to_some p s H_mpush).
rewrite HeqH_mpush in H0.
pose proof (H0 HsL).
rewrite HeqH_mpush.
rewrite H2.
assumption.
Qed.
End Mount.
Definition lookup := Lookup.lookup.
Definition create_directory := CreateDirectory.create_directory.
Definition mount := Mount.mount.
End Implementation.
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A222O_PP_SYMBOL_V
`define SKY130_FD_SC_LS__A222O_PP_SYMBOL_V
/**
* a222o: 2-input AND into all inputs of 3-input OR.
*
* X = ((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a222o (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
input C1 ,
input C2 ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A222O_PP_SYMBOL_V
|
`timescale 1 ns / 1 ps
`include "example_core_lite_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S00_AXI_MAX_BURST_LENGTH 1
`define S00_AXI_DATA_BUS_WIDTH 32
`define S00_AXI_ADDRESS_BUS_WIDTH 32
`define S00_AXI_MAX_DATA_SIZE (`S00_AXI_DATA_BUS_WIDTH*`S00_AXI_MAX_BURST_LENGTH)/8
module example_core_lite_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S00_AXI AXI4 Lite Local Reg
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_rd_data_lite;
reg [`S00_AXI_DATA_BUS_WIDTH-1:0] S00_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S00_AXI_lite_response;
reg [`S00_AXI_ADDRESS_BUS_WIDTH-1:0] S00_AXI_mtestAddress;
reg [3-1:0] S00_AXI_mtestProtection_lite;
integer S00_AXI_mtestvectorlite; // Master side testvector
integer S00_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S00_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S00_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S00_AXI_mtestvectorlite = 0;
S00_AXI_mtestAddress = `S00_AXI_SLAVE_ADDRESS;
S00_AXI_mtestProtection_lite = 0;
S00_AXI_mtestdatasizelite = `S00_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S00_AXI_mtestvectorlite = 0; S00_AXI_mtestvectorlite <= 3; S00_AXI_mtestvectorlite = S00_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],
S00_AXI_mtestdatasizelite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S00_AXI_mtestAddress,
S00_AXI_mtestProtection_lite,
S00_AXI_rd_data_lite,
S00_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S00_AXI_mtestvectorlite,S00_AXI_rd_data_lite,S00_AXI_lite_response);
CHECK_RESPONSE_OKAY(S00_AXI_lite_response);
COMPARE_LITE_DATA(S00_AXI_test_data_lite[S00_AXI_mtestvectorlite],S00_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S00_AXI_mtestvectorlite,S00_AXI_mtestvectorlite);
S00_AXI_mtestAddress = S00_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S00_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S00_AXI_test_data_lite[0] = 32'h0101FFFF;
S00_AXI_test_data_lite[1] = 32'habcd0001;
S00_AXI_test_data_lite[2] = 32'hdead0011;
S00_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S00_AXI_TEST();
end
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.2 Build 153 07/15/2015 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module pll (
inclk0,
c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 5,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 3,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone IV E",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "6"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "30.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "30.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "5"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
module sim_camera (
input i_cam_in_clk,
input i_cam_rst,
input i_flash,
output o_pix_clk,
output reg o_flash_strobe = 0,
output reg o_vsync = 0,
output reg o_hsync = 0,
output reg [7:0] o_pix_data = 0
);
//Local Parameters
localparam START = 4'h0;
localparam INIT = 4'h1;
localparam VBLANK = 4'h2;
localparam HBLANK = 4'h3;
localparam WRITE_ROW = 4'h4;
localparam VBLANK_COUNT = 100;
localparam HBLANK_COUNT = 20;
localparam ROW_COUNT = 32'h10;
localparam BYTE_COUNT = 32'h20;
//Registers/Wires
reg [31:0] r_vblank_count = 0;
reg [31:0] r_hblank_count = 0;
reg [31:0] r_byte_count = 0;
reg [31:0] r_row_count = 0;
reg [31:0] r_byte_index = 0;
reg [3:0] state = START;
wire w_vblank;
wire w_hblank;
reg [7:0] r_data = 8'h00;
//Submodules
//Asynchronous Logic
assign o_pix_clk = i_cam_in_clk;
assign w_vblank = (r_vblank_count < VBLANK_COUNT);
assign w_hblank = (r_hblank_count < HBLANK_COUNT);
//Synchronous Logic
always @ (posedge i_cam_in_clk) begin
if (!i_cam_rst) begin
o_flash_strobe <= 0;
o_vsync <= 0;
o_hsync <= 0;
o_pix_data <= 0;
r_vblank_count <= VBLANK_COUNT;
r_hblank_count <= HBLANK_COUNT;
r_row_count <= ROW_COUNT;
r_byte_count <= BYTE_COUNT;
state <= INIT;
r_data <= 0;
end
else begin
if (r_vblank_count < VBLANK_COUNT) begin
r_vblank_count <= r_vblank_count + 1;
end
if (r_hblank_count < HBLANK_COUNT) begin
r_hblank_count <= r_hblank_count + 1;
end
case (state)
START: begin
end
INIT: begin
o_vsync <= 0;
o_hsync <= 0;
r_vblank_count <= 0;
state <= VBLANK;
end
VBLANK: begin
o_vsync <= 0;
o_hsync <= 0;
r_data <= 0;
r_byte_count <= 0;
r_row_count <= 0;
if (!w_vblank) begin
state <= WRITE_ROW;
end
end
HBLANK: begin
o_vsync <= 1;
o_hsync <= 0;
r_data <= 0;
r_byte_count <= 0;
if (!w_hblank) begin
state <= WRITE_ROW;
end
end
WRITE_ROW: begin
o_vsync <= 1;
o_hsync <= 1;
if (r_byte_count < BYTE_COUNT) begin
//Send a byte
o_pix_data <= r_data;
r_data <= r_data + 1;
r_byte_count <= r_byte_count + 1;
end
else begin
//Still more rows to write
if (r_row_count < ROW_COUNT - 1) begin
r_hblank_count <= 0;
o_hsync <= 0;
state <= HBLANK;
r_row_count <= r_row_count + 1;
end
else begin
r_vblank_count <= 0;
o_vsync <= 0;
o_hsync <= 0;
state <= VBLANK;
end
end
end
endcase
end
end
endmodule
|
/**
* ------------------------------------------------------------
* Copyright (c) All rights reserved
* SiLab, Institute of Physics, University of Bonn
* ------------------------------------------------------------
*/
`timescale 1ps/1ps
`default_nettype none
// WARNING! THIS MODULE IS WORK IN PROGRESS! NOT TESTED!
/*
* Possible extra options:
* - delay block that allow SEQ_EXT_START in past (enabled by parameter - for speed needed applications a simple memory circular buffer)
* - SEQ_EXT_START selections as pulse or as gate/enable
* - multi window recording (sorted with but multiple times)
*/
module seq_rec_core
#(
parameter MEM_BYTES = 8*1024,
parameter ABUSWIDTH = 16,
parameter IN_BITS = 8 //4,8,16,32
)(
BUS_CLK,
BUS_RST,
BUS_ADD,
BUS_DATA_IN,
BUS_RD,
BUS_WR,
BUS_DATA_OUT,
SEQ_CLK,
SEQ_IN,
SEQ_EXT_START
);
localparam VERSION = 0;
input wire BUS_CLK;
input wire BUS_RST;
input wire [ABUSWIDTH-1:0] BUS_ADD;
input wire [7:0] BUS_DATA_IN;
input wire BUS_RD;
input wire BUS_WR;
output reg [7:0] BUS_DATA_OUT;
input wire SEQ_CLK;
input wire [IN_BITS-1:0] SEQ_IN;
input wire SEQ_EXT_START;
`include "../includes/log2func.v"
localparam ADDR_SIZEA = `CLOG2(MEM_BYTES);
localparam ADDR_SIZEB = (IN_BITS > 8) ? `CLOG2(MEM_BYTES/(IN_BITS/8)) : `CLOG2(MEM_BYTES*(8/IN_BITS));
reg [7:0] status_regs [15:0];
wire RST;
wire SOFT_RST;
assign RST = BUS_RST || SOFT_RST;
localparam DEF_BIT_OUT = MEM_BYTES;
always @(posedge BUS_CLK) begin
if(RST) begin
status_regs[0] <= 0;
status_regs[1] <= 0;
status_regs[2] <= 0;
status_regs[3] <= DEF_BIT_OUT[7:0]; //bits
status_regs[4] <= DEF_BIT_OUT[15:8]; //bits
end
else if(BUS_WR && BUS_ADD < 16)
status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN;
end
reg [7:0] BUS_IN_MEM;
reg [7:0] BUS_OUT_MEM;
// 1 - finished
wire START;
assign SOFT_RST = (BUS_ADD==0 && BUS_WR);
assign START = (BUS_ADD==1 && BUS_WR);
wire [15:0] CONF_COUNT;
assign CONF_COUNT = {status_regs[4], status_regs[3]};
wire CONF_EN_SEQ_EXT_START;
assign CONF_EN_SEQ_EXT_START = status_regs[2][0];
reg CONF_DONE;
wire [7:0] BUS_STATUS_OUT;
assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]];
reg [7:0] BUS_DATA_OUT_REG;
always @ (posedge BUS_CLK) begin
if(BUS_RD)
begin
if(BUS_ADD == 0)
BUS_DATA_OUT_REG <= VERSION;
else if(BUS_ADD == 1)
BUS_DATA_OUT_REG <= {7'b0,CONF_DONE};
else if(BUS_ADD == 2)
BUS_DATA_OUT_REG <= {7'b0,CONF_EN_SEQ_EXT_START};
else if(BUS_ADD == 3)
BUS_DATA_OUT_REG <= CONF_COUNT[15:8];
else if(BUS_ADD == 4)
BUS_DATA_OUT_REG <= CONF_COUNT[7:0];
else if(BUS_ADD < 16)
BUS_DATA_OUT_REG <= BUS_STATUS_OUT;
end
end
reg [ABUSWIDTH-1:0] PREV_BUS_ADD;
always @ (posedge BUS_CLK) begin
if(BUS_RD) begin
PREV_BUS_ADD <= BUS_ADD;
end
end
always @(*) begin
if(PREV_BUS_ADD < 16)
BUS_DATA_OUT = BUS_DATA_OUT_REG;
else if(PREV_BUS_ADD < 16 + MEM_BYTES )
BUS_DATA_OUT = BUS_IN_MEM;
else
BUS_DATA_OUT = 8'hxx;
end
reg [ABUSWIDTH-1:0] out_bit_cnt;
wire [ADDR_SIZEB-1:0] memout_addrb;
assign memout_addrb = out_bit_cnt-1;
wire [ADDR_SIZEA-1:0] memout_addra;
wire [ABUSWIDTH-1:0] BUS_ADD_MEM;
assign BUS_ADD_MEM = BUS_ADD-16;
localparam IN_BYTES = IN_BITS/8;
localparam IN_BYTES_WIDTH = `CLOG2(IN_BYTES);
generate
if (IN_BITS<=8) begin
assign memout_addra = BUS_ADD_MEM;
end else begin
assign memout_addra = {BUS_ADD_MEM[ADDR_SIZEA:IN_BYTES_WIDTH], {(IN_BYTES_WIDTH){1'b0}}} + (IN_BYTES-1) - BUS_ADD_MEM[IN_BYTES_WIDTH-1:0]; //Byte order
end
endgenerate
reg [IN_BITS-1:0] SEQ_IN_MEM;
wire WEA, WEB;
assign WEA = BUS_WR && BUS_ADD >=16 && BUS_ADD < 16+MEM_BYTES && !WEB;
generate
if (IN_BITS==8) begin
(* RAM_STYLE="{BLOCK}" *)
reg [7:0] mem [(2**ADDR_SIZEA)-1:0];
// synthesis translate_off
//to make simulator happy (no X propagation)
integer i;
initial
for(i = 0; i < (2**ADDR_SIZEA); i = i + 1)
mem[i] = 0;
// synthesis translate_on
always @(posedge BUS_CLK) begin
if (WEA)
mem[memout_addra] <= BUS_DATA_IN;
BUS_IN_MEM <= mem[memout_addra];
end
always @(posedge SEQ_CLK)
if(WEB)
mem[memout_addrb] <= SEQ_IN;
end else begin
wire [7:0] douta;
seq_rec_blk_mem memout(
.clka(BUS_CLK), .clkb(SEQ_CLK), .douta(douta), .doutb(),
.wea(WEA), .web(WEB), .addra(memout_addra), .addrb(memout_addrb),
.dina(BUS_DATA_IN), .dinb(SEQ_IN)
);
always@(*) begin
BUS_IN_MEM = douta;
end
end
endgenerate
assign WEB = out_bit_cnt != 0;
wire RST_SYNC;
wire RST_SOFT_SYNC;
cdc_pulse_sync rst_pulse_sync (.clk_in(BUS_CLK), .pulse_in(RST), .clk_out(SEQ_CLK), .pulse_out(RST_SOFT_SYNC));
assign RST_SYNC = RST_SOFT_SYNC || BUS_RST;
wire START_SYNC;
cdc_pulse_sync start_pulse_sync (.clk_in(BUS_CLK), .pulse_in(START), .clk_out(SEQ_CLK), .pulse_out(START_SYNC));
wire [ADDR_SIZEB:0] STOP_BIT;
assign STOP_BIT = CONF_COUNT;
wire START_SYNC_OR_TRIG;
assign START_SYNC_OR_TRIG = START_SYNC | (CONF_EN_SEQ_EXT_START & SEQ_EXT_START);
always @ (posedge SEQ_CLK)
if (RST_SYNC)
out_bit_cnt <= 0;
else if(START_SYNC_OR_TRIG)
out_bit_cnt <= 1;
else if(out_bit_cnt == STOP_BIT)
out_bit_cnt <= out_bit_cnt;
else if(out_bit_cnt != 0)
out_bit_cnt <= out_bit_cnt + 1;
reg DONE;
always @(posedge SEQ_CLK)
if(RST_SYNC | START_SYNC_OR_TRIG)
DONE <= 0;
else if(out_bit_cnt == STOP_BIT)
DONE <= 1;
wire DONE_SYNC;
cdc_pulse_sync done_pulse_sync (.clk_in(SEQ_CLK), .pulse_in(DONE), .clk_out(BUS_CLK), .pulse_out(DONE_SYNC));
always @(posedge BUS_CLK)
if(RST)
CONF_DONE <= 1;
else if(START)
CONF_DONE <= 0;
else if(DONE_SYNC)
CONF_DONE <= 1;
endmodule |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__MUX2_LP2_V
`define SKY130_FD_SC_LP__MUX2_LP2_V
/**
* mux2: 2-input multiplexer.
*
* Verilog wrapper for mux2 with size for low power (alternative).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__mux2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_lp2 (
X ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__mux2_lp2 (
X ,
A0,
A1,
S
);
output X ;
input A0;
input A1;
input S ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__mux2 base (
.X(X),
.A0(A0),
.A1(A1),
.S(S)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__MUX2_LP2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A222OI_FUNCTIONAL_V
`define SKY130_FD_SC_MS__A222OI_FUNCTIONAL_V
/**
* a222oi: 2-input AND into all inputs of 3-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2) | (C1 & C2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__a222oi (
Y ,
A1,
A2,
B1,
B2,
C1,
C2
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input B2;
input C1;
input C2;
// Local signals
wire nand0_out ;
wire nand1_out ;
wire nand2_out ;
wire and0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1 );
nand nand1 (nand1_out , B2, B1 );
nand nand2 (nand2_out , C2, C1 );
and and0 (and0_out_Y, nand0_out, nand1_out, nand2_out);
buf buf0 (Y , and0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A222OI_FUNCTIONAL_V |
/*
* File: demo_top.v
* Project: pippo
* Designer: kiss@pwrsemi
* Mainteiner: kiss@pwrsemi
* Checker:
* Assigner:
* Description:
* top module for FPGA demo on XUP board
*
*/
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "def_pippo.v"
module demo_top(
FPGA_SYSTEMACE_CLOCK,
SW_0, SW_1, SW_2, SW_3,
PB_ENTER, PB_UP, PB_DOWN, PB_LEFT, PB_RIGHT,
LED_0, LED_1, LED_2, LED_3,
RS232_TX_DATA, RS232_RX_DATA
);
//
// I/O
//
// clock to DCM
input FPGA_SYSTEMACE_CLOCK; // 32MHz
// swith on board
input SW_0;
input SW_1;
input SW_2;
input SW_3;
// pushbotton on board
input PB_ENTER;
input PB_UP;
input PB_DOWN;
input PB_LEFT;
input PB_RIGHT;
// led on board
output LED_0;
output LED_1;
output LED_2;
output LED_3;
// uart on board
input RS232_RX_DATA;
output RS232_TX_DATA;
//
// interconnections
//
wire dsu_sram_we;
wire [31:0] iimx_adr_o;
wire iimx_rqt_o;
wire [31:0] iimx_dat_i;
wire iimx_ack_i;
wire iimx_rty_i;
wire iimx_err_i;
wire [31:0] iimx_adr_i;
wire [31:0] dimx_adr_o;
wire dimx_rqt_o;
wire dimx_we_o;
wire [3:0] dimx_sel_o;
wire [31:0] dimx_dat_o;
wire [31:0] dimx_dat_i;
wire dimx_ack_i;
wire dimx_err_i;
//
// clock and reset
//
demo_clk demo_clk (
.CLK_IN(FPGA_SYSTEMACE_CLOCK),
.RST(1'b0),
.CLK1X(clk32M),
.CLK2X(clk),
.LOCK(dcm_lock)
);
// [TBD] BUFG
wire rst_tmp;
assign rst_tmp = !PB_ENTER;
reg rst_tmp1, rst_tmp2, rst_tmp3;
always @(posedge clk) begin
rst_tmp1 <= rst_tmp;
rst_tmp2 <= rst_tmp1;
rst_tmp3 <= rst_tmp2;
end
assign rst = rst_tmp1 & rst_tmp2 & rst_tmp3;
//
// heartbreak logic: clock is running
//
// Note: frequency of clk is 64MHz. 1s = 15.5ns * 64 * 10e6 (0x3D0_9000, 0011_1101_0000_1001_0000_0000_0000)
reg [26:0] clk_counter;
always @(posedge clk or posedge rst) begin
if(rst)
clk_counter <= 27'd0;
else
clk_counter <= clk_counter + 27'd1;
end
//
// reserved logic: just to keep core un-optimized by synthesis tool
//
wire iimx_rqt_status;
wire iimx_rsp_status;
wire dimx_rqt_status;
wire dimx_rsp_status;
assign iimx_rqt_status = (|iimx_adr_o) & iimx_rqt_o;
assign dimx_rqt_status = (|dimx_adr_o) & dimx_rqt_o;
assign iimx_rsp_status = (|iimx_dat_i) & iimx_ack_i;
assign dimx_rsp_status = ((|dimx_dat_i) | dimx_we_o) & dimx_ack_i;
//
// xup-v2p board source
// Note: When the FPGA drives a logic 0, the corresponding LED turns on. A single four-position DIP
// switch and five push buttons are provided for user input. If the DIP switch is up, closed, or on,
// or the push button is pressed, a logic 0 is seen by the FPGA, otherwise a logic 1 is indicated.
// signal pushed assert when push push-buttons
wire pushed_tmp;
assign pushed_tmp = !(PB_UP & PB_DOWN & PB_LEFT & PB_RIGHT);
reg pushed_tmp1, pushed_tmp2, pushed_tmp3;
always @(posedge clk) begin
pushed_tmp1 <= pushed_tmp;
pushed_tmp2 <= pushed_tmp1;
pushed_tmp3 <= pushed_tmp2;
end
assign pushed = pushed_tmp1 & pushed_tmp2 & pushed_tmp3;
//
//
//
reg [9:0] num_burn_word;
always @(posedge clk or posedge rst) begin
if(rst)
num_burn_word <= 10'd0;
else if (dsu_sram_we)
num_burn_word <= num_burn_word + 10'd1;
end
//
// LED & SW
//
// SW_0: enable heartbreak flashing
// SW_1: enable imx rqt status flashing
// SW_2: enable imx rsp status flashing
// SW_3: enable for dsu burning mode
//
// LED0: status of clk
// LED1: status of imx request
// LED2: status of imx response
// LED3: status of on-chip ram burning process
assign dsu_rst = pushed;
assign dsu_burn_enable = SW_3;
assign LED0_light = clk_counter[26] & !rst & SW_0;
assign LED1_light = iimx_rqt_status | dimx_rqt_status & SW_1;
assign LED2_light = iimx_rsp_status | dimx_rsp_status & SW_2;
assign LED3_light = |num_burn_word;
assign LED_0 = ! LED0_light;
assign LED_1 = ! LED1_light;
assign LED_2 = ! LED2_light;
assign LED_3 = ! LED3_light;
//
// sys_top
//
top_pss sys_top_pss(
.clk(clk),
.rst(rst),
.dsu_rst(dsu_rst),
.dsu_burn_enable(dsu_burn_enable),
.dsu_sram_we(dsu_sram_we),
.txd(RS232_TX_DATA),
.rxd(RS232_RX_DATA),
.iimx_adr_o(iimx_adr_o),
.iimx_rqt_o(iimx_rqt_o),
.iimx_rty_i(iimx_rty_i),
.iimx_ack_i(iimx_ack_i),
.iimx_err_i(iimx_err_i),
.iimx_dat_i(iimx_dat_i),
.iimx_adr_i(iimx_adr_i),
.dimx_adr_o(dimx_adr_o),
.dimx_rqt_o(dimx_rqt_o),
.dimx_we_o(dimx_we_o),
.dimx_sel_o(dimx_sel_o),
.dimx_dat_o(dimx_dat_o),
.dimx_dat_i(dimx_dat_i),
.dimx_ack_i(dimx_ack_i),
.dimx_err_i(dimx_err_i)
);
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// vim:set shiftwidth=3 softtabstop=3 expandtab:
//
// Module: unused_reg.v
// Project: NetFPGA
// Description: Unused register block
//
///////////////////////////////////////////////////////////////////////////////
module unused_reg
#(
parameter REG_ADDR_WIDTH = 5
)
(
// Register interface signals
input reg_req,
output reg_ack,
input reg_rd_wr_L,
input [REG_ADDR_WIDTH - 1:0] reg_addr,
output [`CPCI_NF2_DATA_WIDTH - 1:0] reg_rd_data,
input [`CPCI_NF2_DATA_WIDTH - 1:0] reg_wr_data,
//
input clk,
input reset
);
reg reg_req_d1;
assign reg_rd_data = 'h dead_beef;
// Only generate an ack on a new request
assign reg_ack = reg_req && !reg_req_d1;
always @(posedge clk)
begin
reg_req_d1 <= reg_req;
end
endmodule // unused_reg
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_SYMBOL_V
`define SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_SYMBOL_V
/**
* clkdlyinv5sd2: Clock Delay Inverter 5-stage 0.25um length inner
* stage gate.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__clkdlyinv5sd2 (
//# {{data|Data Signals}}
input A ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__CLKDLYINV5SD2_PP_SYMBOL_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND4_BEHAVIORAL_V
`define SKY130_FD_SC_MS__NAND4_BEHAVIORAL_V
/**
* nand4: 4-input NAND.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__nand4 (
Y,
A,
B,
C,
D
);
// Module ports
output Y;
input A;
input B;
input C;
input D;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out_Y, D, C, B, A );
buf buf0 (Y , nand0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND4_BEHAVIORAL_V |
// final sub module for text
module game_text
(
input wire clk,
input wire [1:0] ball,
// ball's number (well, 9 is max)
input wire [3:0] dig0, dig1,
// score (well, I think a score more than 9 is highly possible)
input wire [9:0] pix_x, pix_y,
output wire [3:0] text_on,
output reg [2:0] text_rgb
// we output text_rgb only because we have to select it according to FSM
);
// signal declaration
wire [10:0] rom_addr;
reg [6:0] char_addr, char_addr_s, char_addr_l,
char_addr_r, char_addr_o;
// char_addr is the final address selected by MUX
// s stands for score (and ball, but I can not use sb...)
// l stands for logo (well, our special plalindrome logo WPPW)
// r stands for registration information (in this case, student ID and name)
// o stands for over (actually game over I assume, anyway)
reg [3:0] row_addr;
wire [3:0] row_addr_s, row_addr_l, row_addr_r, row_addr_o;
reg [2:0] bit_addr;
wire [2:0] bit_addr_s, bit_addr_l,bit_addr_r, bit_addr_o;
wire [7:0] font_word;
wire font_bit, score_on, logo_on, registration_on, over_on;
wire [5:0] registration_rom_addr;
// instantiate font ROM
font_rom font_unit
(.clk(clk), .addr(rom_addr), .data(font_word));
// this is a real font_rom
// implemented as a block rom
// not the same as the following simple roms
//-------------------------------------------
// score region
// - display two-digit score, ball on top left
// - scale to 16-by-32 font
// - line 1, 16 chars: "Score:DD Ball:D"
//-------------------------------------------
assign score_on = (pix_y[9:5]==0) && (pix_x[9:4]<16);
// all on signal comes out as text_on (array) signal
assign row_addr_s = pix_y[4:1];
assign bit_addr_s = pix_x[3:1];
// all addr will be selected using mux circuit
always @*
case (pix_x[7:4])
4'h0: char_addr_s = 7'h53; // S
4'h1: char_addr_s = 7'h63; // c
4'h2: char_addr_s = 7'h6f; // o
4'h3: char_addr_s = 7'h72; // r
4'h4: char_addr_s = 7'h65; // e
4'h5: char_addr_s = 7'h3a; // :
4'h6: char_addr_s = {3'b011, dig1}; // digit 10
4'h7: char_addr_s = {3'b011, dig0}; // digit 1
4'h8: char_addr_s = 7'h00; //
4'h9: char_addr_s = 7'h00; //
4'ha: char_addr_s = 7'h42; // B
4'hb: char_addr_s = 7'h61; // a
4'hc: char_addr_s = 7'h6c; // l
4'hd: char_addr_s = 7'h6c; // l
4'he: char_addr_s = 7'h3a; // :
4'hf: char_addr_s = {5'b01100, ball};
// this kind of concatenation is to perform num2str (matlab or python)
endcase
//-------------------------------------------
// logo region:
// - display logo "WPPW" at top center
// - stands for Wei Pang Peng Wei
// - used as background
// - scale to 64-by-128 font
//-------------------------------------------
assign logo_on = (pix_y[9:7]==2) &&
(3<=pix_x[9:6]) && (pix_x[9:6]<=6);
assign row_addr_l = pix_y[6:3];
assign bit_addr_l = pix_x[5:3];
always @*
case (pix_x[8:6])
3'o3: char_addr_l = 7'h57; // W
3'o4: char_addr_l = 7'h50; // P
3'o5: char_addr_l = 7'h50; // P
default: char_addr_l = 7'h57; // W
// using default to avoid warning
endcase
//-------------------------------------------
// registration region
// - display registration (4-by-16 tiles)on center
// - registration text:
// 3120103795
// Pengwei Wu
// 3120102358
// Wei Cheng
//-------------------------------------------
assign registration_on = (pix_x[9:7]==2) && (pix_y[9:6]==2);
assign row_addr_r = pix_y[3:0];
assign bit_addr_r = pix_x[2:0];
assign registration_rom_addr = {pix_y[5:4], pix_x[6:3]};
always @*
case (registration_rom_addr)
// row 1 generated by MATLAB
6'h00: char_addr_r = 7'h33;
6'h01: char_addr_r = 7'h31;
6'h02: char_addr_r = 7'h32;
6'h03: char_addr_r = 7'h30;
6'h04: char_addr_r = 7'h31;
6'h05: char_addr_r = 7'h30;
6'h06: char_addr_r = 7'h33;
6'h07: char_addr_r = 7'h37;
6'h08: char_addr_r = 7'h39;
6'h09: char_addr_r = 7'h35;
6'h0A: char_addr_r = 7'h20;
6'h0B: char_addr_r = 7'h20;
6'h0C: char_addr_r = 7'h20;
6'h0D: char_addr_r = 7'h20;
// visualization
// well
6'h0E: char_addr_r = 7'h20;
6'h0F: char_addr_r = 7'h20;
// row 2
6'h10: char_addr_r = 7'h50;
6'h11: char_addr_r = 7'h65;
6'h12: char_addr_r = 7'h6E;
6'h13: char_addr_r = 7'h67;
6'h14: char_addr_r = 7'h77;
6'h15: char_addr_r = 7'h65;
6'h16: char_addr_r = 7'h69;
6'h17: char_addr_r = 7'h20;
6'h18: char_addr_r = 7'h57;
6'h19: char_addr_r = 7'h75;
6'h1A: char_addr_r = 7'h20;
6'h1B: char_addr_r = 7'h20;
6'h1C: char_addr_r = 7'h20;
6'h1D: char_addr_r = 7'h20;
// visualization
// well
6'h1E: char_addr_r = 7'h20;
6'h1F: char_addr_r = 7'h20;
// row 3
6'h20: char_addr_r = 7'h33;
6'h21: char_addr_r = 7'h31;
6'h22: char_addr_r = 7'h32;
6'h23: char_addr_r = 7'h30;
6'h24: char_addr_r = 7'h31;
6'h25: char_addr_r = 7'h30;
6'h26: char_addr_r = 7'h32;
6'h27: char_addr_r = 7'h33;
6'h28: char_addr_r = 7'h35;
6'h29: char_addr_r = 7'h38;
6'h2A: char_addr_r = 7'h20;
6'h2B: char_addr_r = 7'h20;
6'h2C: char_addr_r = 7'h20;
6'h2D: char_addr_r = 7'h20;
// visualization
// well
6'h2E: char_addr_r = 7'h20;
6'h2F: char_addr_r = 7'h20;
// row 4
6'h30: char_addr_r = 7'h57;
6'h31: char_addr_r = 7'h65;
6'h32: char_addr_r = 7'h69;
6'h33: char_addr_r = 7'h20;
6'h34: char_addr_r = 7'h43;
6'h35: char_addr_r = 7'h68;
6'h36: char_addr_r = 7'h65;
6'h37: char_addr_r = 7'h6E;
6'h38: char_addr_r = 7'h67;
6'h39: char_addr_r = 7'h20;
6'h3A: char_addr_r = 7'h20;
6'h3B: char_addr_r = 7'h20;
6'h3C: char_addr_r = 7'h20;
6'h3D: char_addr_r = 7'h20;
// well, this is very annoying, try consola?
6'h3E: char_addr_r = 7'h20;
6'h3F: char_addr_r = 7'h20;
endcase
//-------------------------------------------
// game over region
// - display "Game Over" at center
// - scale to 32-by-64 fonts
//-----------------------------------------
// don't worry about game over text display sequence
// will be adjusted in the top module by FSM
assign over_on = (pix_y[9:6]==3) &&
(5<=pix_x[9:5]) && (pix_x[9:5]<=13);
assign row_addr_o = pix_y[5:2];
assign bit_addr_o = pix_x[4:2];
always @*
case(pix_x[8:5])
4'h5: char_addr_o = 7'h47; // G
4'h6: char_addr_o = 7'h61; // a
4'h7: char_addr_o = 7'h6d; // m
4'h8: char_addr_o = 7'h65; // e
4'h9: char_addr_o = 7'h00; //
4'ha: char_addr_o = 7'h4f; // O
4'hb: char_addr_o = 7'h76; // v
4'hc: char_addr_o = 7'h65; // e
default: char_addr_o = 7'h72; // r
endcase
//-------------------------------------------
// mux for font ROM addresses and rgb
//-------------------------------------------
// you can adjust color here
always @*
begin
text_rgb = 3'b110; // background, yellow
if (score_on)
begin
char_addr = char_addr_s;
row_addr = row_addr_s;
bit_addr = bit_addr_s;
if (font_bit)
text_rgb = 3'b001;
end
else if (registration_on)
begin
char_addr = char_addr_r;
row_addr = row_addr_r;
bit_addr = bit_addr_r;
if (font_bit)
text_rgb = 3'b001;
end
else if (logo_on)
begin
char_addr = char_addr_l;
row_addr = row_addr_l;
bit_addr = bit_addr_l;
if (font_bit)
text_rgb = 3'b011;
end
else // game over
begin
char_addr = char_addr_o;
row_addr = row_addr_o;
bit_addr = bit_addr_o;
if (font_bit)
text_rgb = 3'b001;
end
end
assign text_on = {score_on, logo_on, registration_on, over_on};
//-------------------------------------------
// font rom interface (well)
//-------------------------------------------
// just concatenation
assign rom_addr = {char_addr, row_addr};
assign font_bit = font_word[~bit_addr];
endmodule
|
module rgbmatrix (
input clk,
input rst,
output reg R0,
output reg G0,
output reg B0,
output reg R1,
output reg G1,
output reg B1,
output reg A,
output reg B,
output reg C,
output reg D,
output reg MATCLK,
output reg MATLAT,
output reg MATOE
);
localparam WAIT = 0,
BLANK = 1,
LATCH = 2,
UNBLANK = 3,
READ = 4,
SHIFT1 = 5,
SHIFT2 = 6;
reg [2:0] state;
reg [10:0] timer;
reg [3:0] delay;
reg [3:0] rd_row;
reg [1:0] rd_bit;
reg [4:0] rd_col;
always @ (posedge clk or posedge rst)
begin
if (rst)
begin
R0 <= 0;
G0 <= 0;
B0 <= 0;
R1 <= 0;
G1 <= 0;
B1 <= 0;
A <= 0;
B <= 0;
C <= 0;
D <= 0;
MATCLK <= 0;
MATLAT <= 0;
MATOE <= 1;
state <= READ;
timer <= 0;
delay <= 0;
rd_row <= 0;
rd_bit <= 0;
rd_col <= 0;
end
else
begin
// implemnt timer for binary coded modulation
// bit plane 0 is displayed for ~192 clock cycles
// each succesfive bit plane is displayed for 2x the clocks of the previous bit plane
if (timer == 0)
begin
case (rd_bit)
0: timer <= 191;
1: timer <= 383;
2: timer <= 767;
3: timer <= 1535;
endcase
end
else
begin
timer <= timer - 1;
end
// state machine
case (state)
// wait for timer to expire then blank the display
WAIT: begin
MATCLK <= 0;
if (timer == 0)
begin
MATOE <= 1;
delay <= 8;
state <= BLANK;
end
end
// wait a while then latch in data previosly shifted into display
BLANK: begin
if (delay == 0)
begin
MATLAT <= 1;
delay <= 8;
state <= LATCH;
A <= rd_row[0];
B <= rd_row[1];
C <= rd_row[2];
D <= rd_row[3];
end
else
begin
delay <= delay - 1;
end
end
// wait a while then unblank the display to display the latched data
LATCH: begin
if (delay == 0)
begin
MATOE <= 0;
MATLAT <= 0;
state <= UNBLANK;
end
else
begin
delay <= delay - 1;
end
end
// find the next bit, row, column, and buffer to display
// this is converted to a read address using combinatorial logic above
UNBLANK: begin
if (rd_bit == 3)
begin
rd_bit <= 0;
if (rd_row == 15)
begin
rd_row <= 0;
end
else
begin
rd_row <= rd_row + 1;
end
end
else
begin
rd_bit <= rd_bit + 1;
end
rd_col <= 0;
state <= READ;
end
// the read, shift1, and shift2 states could be reduced to two states
// if I knew which edge of sclk latched the data into the shift registers
// this is good enough for one panel but for more than about four panels
// it'd be worth reducing to two clocks instead of three clocks.
// wait for read data to be output from RAM
READ: begin
state <= SHIFT1;
MATCLK <= 0;
end
// drive the column data out the outputs
SHIFT1: begin
R0 <= rd_row[0];
G0 <= rd_row[1];
B0 <= 0;
R1 <= 0;
G1 <= rd_row[1];
B1 <= 0;
state <= SHIFT2;
end
// clock the data into the RAM, move to next column, repeat 32x
SHIFT2: begin
MATCLK <= 1;
if (rd_col == 31)
begin
rd_col <= 0;
state <= WAIT;
end
else
begin
rd_col <= rd_col + 1;
state <= READ;
end
end
endcase
end
end
endmodule |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2009-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Virtex-6 Integrated Block for PCI Express
// File : pci_exp_usrapp_com.v
// Version : 2.4
//--
//--------------------------------------------------------------------------------
`include "board_common.v"
module pci_exp_usrapp_com ();
/* Local variables */
reg [31:0] rx_file_ptr;
reg [7:0] frame_store_rx[5119:0];
integer frame_store_rx_idx;
reg [31:0] tx_file_ptr;
reg [7:0] frame_store_tx[5119:0];
integer frame_store_tx_idx;
reg [31:0] log_file_ptr;
integer _frame_store_idx;
event rcvd_cpld, rcvd_memrd, rcvd_memwr;
event rcvd_cpl, rcvd_memrd64, rcvd_memwr64;
event rcvd_msg, rcvd_msgd, rcvd_cfgrd0;
event rcvd_cfgwr0, rcvd_cfgrd1, rcvd_cfgwr1;
event rcvd_iord, rcvd_iowr;
initial begin
frame_store_rx_idx = 0;
frame_store_tx_idx = 0;
rx_file_ptr = $fopen("rx.dat");
if (!rx_file_ptr) begin
$write("ERROR: Could not open rx.dat.\n");
$finish;
end
tx_file_ptr = $fopen("tx.dat");
if (!tx_file_ptr) begin
$write("ERROR: Could not open tx.dat.\n");
$finish;
end
end
/************************************************************
Task : TSK_PARSE_FRAME
Inputs : None
Outputs : None
Description : Parse frame data
*************************************************************/
task TSK_PARSE_FRAME;
input log_file;
reg [1:0] fmt;
reg [4:0] f_type;
reg [2:0] traffic_class;
reg td;
reg ep;
reg [1:0] attr;
reg [9:0] length;
reg payload;
reg [15:0] requester_id;
reg [15:0] completer_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [7:0] message_code;
reg [31:0] address_low;
reg [31:0] address_high;
reg [9:0] register_address;
reg [2:0] completion_status;
reg [31:0] _log_file_ptr;
integer _frame_store_idx;
begin
if (log_file == `RX_LOG)
_log_file_ptr = rx_file_ptr;
else
_log_file_ptr = tx_file_ptr;
if (log_file == `RX_LOG) begin
_frame_store_idx = frame_store_rx_idx;
frame_store_rx_idx = 0;
end else begin
_frame_store_idx = frame_store_tx_idx;
frame_store_tx_idx = 0;
end
if (log_file == `RX_LOG) begin
$display("[%t] : TSK_PARSE_FRAME on Receive", $realtime);
end
else begin
$display("[%t] : TSK_PARSE_FRAME on Transmit", $realtime);
end
TSK_DECIPHER_FRAME (fmt, f_type, traffic_class, td, ep, attr, length, log_file);
// decode the packets received based on fmt and f_type
casex({fmt, f_type})
`PCI_EXP_MEM_READ32 : begin
$fdisplay(_log_file_ptr, "[%t] : Memory Read-32 Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_memrd;
end
`PCI_EXP_IO_READ : begin
$fdisplay(_log_file_ptr, "[%t] : IO Read Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_iord;
end
`PCI_EXP_CFG_READ0 : begin
$fdisplay(_log_file_ptr, "[%t] : Config Read Type 0 Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_cfgrd0;
end
`PCI_EXP_COMPLETION_WO_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Completion Without Data Frame \n", $time);
payload = 0;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_cpl;
end
`PCI_EXP_MEM_READ64: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Read-64 Frame \n", $time);
payload = 0;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_memrd64;
end
`PCI_EXP_MSG_NODATA: begin
$fdisplay(_log_file_ptr, "[%t] : Message With No Data Frame \n", $time);
payload = 0;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
if (log_file == `RX_LOG)
-> rcvd_msg;
end
`PCI_EXP_MEM_WRITE32: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Write-32 Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_memwr;
end
`PCI_EXP_IO_WRITE: begin
$fdisplay(_log_file_ptr, "[%t] : IO Write Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_iowr;
end
`PCI_EXP_CFG_WRITE0: begin
$fdisplay(_log_file_ptr, "[%t] : Config Write Type 0 Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_cfgwr0;
end
`PCI_EXP_COMPLETION_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Completion With Data Frame \n", $time);
payload = 1;
TSK_3DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_cpld;
end
`PCI_EXP_MEM_WRITE64: begin
$fdisplay(_log_file_ptr, "[%t] : Memory Write-64 Frame \n", $time);
payload = 1;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_memwr64;
end
`PCI_EXP_MSG_DATA: begin
$fdisplay(_log_file_ptr, "[%t] : Message With Data Frame \n", $time);
payload = 1;
TSK_4DW(fmt, f_type, traffic_class, td, ep, attr, length, payload, _frame_store_idx, _log_file_ptr, log_file);
$fdisplay(_log_file_ptr, "\n");
if (log_file == `RX_LOG)
-> rcvd_msgd;
end
default: begin
$fdisplay(_log_file_ptr, "[%t] : Not a valid frame \n", $time);
$display(_log_file_ptr, "[%t] : Received an invalid frame \n", $time);
$finish(2);
end
endcase
end
endtask // TSK_PARSE_FRAME
/************************************************************
Task : TSK_DECIPHER_FRAME
Inputs : None
Outputs : fmt, f_type, traffic_class, td, ep, attr, length
Description : Deciphers frame
*************************************************************/
task TSK_DECIPHER_FRAME;
output [1:0] fmt;
output [4:0] f_type;
output [2:0] traffic_class;
output td;
output ep;
output [1:0] attr;
output [9:0] length;
input txrx;
begin
fmt = (txrx ? frame_store_tx[0] : frame_store_rx[0]) >> 5;
f_type = txrx ? frame_store_tx[0] : frame_store_rx[0];
traffic_class = (txrx ? frame_store_tx[1] : frame_store_rx[1]) >> 4;
td = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 7;
ep = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 6;
attr = (txrx ? frame_store_tx[2] : frame_store_rx[2]) >> 4;
length = (txrx ? frame_store_tx[2] : frame_store_rx[2]);
length = (length << 8) | (txrx ? frame_store_tx[3] : frame_store_rx[3]);
end
endtask // TSK_DECIPHER_FRAME
/************************************************************
Task : TSK_3DW
Inputs : fmt, f_type, traffic_class, td, ep, attr, length,
payload, _frame_store_idx
Outputs : None
Description : Gets variables and prints frame
*************************************************************/
task TSK_3DW;
input [1:0] fmt;
input [4:0] f_type;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input payload;
input [31:0] _frame_store_idx;
input [31:0] _log_file_ptr;
input txrx;
reg [15:0] requester_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [31:0] address_low;
reg [15:0] completer_id;
reg [9:0] register_address;
reg [2:0] completion_status;
reg [31:0] dword_data; // this will be used to recontruct bytes of data and sent to tx_app
integer _i;
begin
$fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(_log_file_ptr, "\t TD: %h", td);
$fdisplay(_log_file_ptr, "\t EP: %h", ep);
$fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
casex({fmt, f_type})
`PCI_EXP_CFG_READ0,
`PCI_EXP_CFG_WRITE0: begin
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
completer_id = {txrx ? frame_store_tx[8] : frame_store_rx[8], txrx ? frame_store_tx[9] : frame_store_rx[9]};
register_address = txrx ? frame_store_tx[10] : frame_store_rx[10];
register_address = (register_address << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
$fdisplay(_log_file_ptr, "\t Register Address: 0x%h \n", register_address);
if (payload == 1) begin
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
`PCI_EXP_COMPLETION_WO_DATA,
`PCI_EXP_COMPLETION_DATA: begin
completer_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
completion_status = txrx ? (frame_store_tx[6] >> 5) : (frame_store_rx[6] >> 5);
requester_id = txrx ? {frame_store_tx[8], frame_store_tx[9]} : {frame_store_rx[8], frame_store_rx[9]};
tag = txrx ? frame_store_tx[10] : frame_store_rx[10];
$fdisplay(_log_file_ptr, "\t Completer Id: 0x%h", completer_id);
$fdisplay(_log_file_ptr, "\t Completion Status: 0x%h", completion_status);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h ", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h \n", tag);
if (payload == 1) begin
dword_data = 32'h0000_0000;
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
if (!txrx) begin // if we are called from rx
dword_data = dword_data >> 8; // build a dword to send to tx app
dword_data = dword_data | {frame_store_rx[_i], 24'h00_0000};
end
end
`TX_TASKS.TSK_SET_READ_DATA(4'hf,dword_data); // send the data to the tx_app
end
end
// memory reads, io reads, memory writes and io writes
default: begin
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
address_low = txrx ? frame_store_tx[8] : frame_store_rx[8];
address_low = (address_low << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 12; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", (txrx ? frame_store_tx[_i] : frame_store_rx[_i]));
end
end
end
endcase
end
endtask // TSK_3DW
/************************************************************
Task : TSK_4DW
Inputs : fmt, f_type, traffic_class, td, ep, attr, length
payload, _frame_store_idx
Outputs : None
Description : Gets variables and prints frame
*************************************************************/
task TSK_4DW;
input [1:0] fmt;
input [4:0] f_type;
input [2:0] traffic_class;
input td;
input ep;
input [1:0] attr;
input [9:0] length;
input payload;
input [31:0] _frame_store_idx;
input [31:0] _log_file_ptr;
input txrx;
reg [15:0] requester_id;
reg [7:0] tag;
reg [7:0] byte_enables;
reg [7:0] message_code;
reg [31:0] address_high;
reg [31:0] address_low;
reg [2:0] msg_type;
integer _i;
begin
$fdisplay(_log_file_ptr, "\t Traffic Class: 0x%h", traffic_class);
$fdisplay(_log_file_ptr, "\t TD: %h", td);
$fdisplay(_log_file_ptr, "\t EP: %h", ep);
$fdisplay(_log_file_ptr, "\t Attributes: 0x%h", attr);
$fdisplay(_log_file_ptr, "\t Length: 0x%h", length);
requester_id = txrx ? {frame_store_tx[4], frame_store_tx[5]} : {frame_store_rx[4], frame_store_rx[5]};
tag = txrx ? frame_store_tx[6] : frame_store_rx[6];
byte_enables = txrx ? frame_store_tx[7] : frame_store_rx[7];
message_code = txrx ? frame_store_tx[7] : frame_store_rx[7];
address_high = txrx ? frame_store_tx[8] : frame_store_rx[8];
address_high = (address_high << 8) | (txrx ? frame_store_tx[9] : frame_store_rx[9]);
address_high = (address_high << 8) | (txrx ? frame_store_tx[10] : frame_store_rx[10]);
address_high = (address_high << 8) | (txrx ? frame_store_tx[11] : frame_store_rx[11]);
address_low = txrx ? frame_store_tx[12] : frame_store_rx[12];
address_low = (address_low << 8) | (txrx ? frame_store_tx[13] : frame_store_rx[13]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[14] : frame_store_rx[14]);
address_low = (address_low << 8) | (txrx ? frame_store_tx[15] : frame_store_rx[15]);
$fdisplay(_log_file_ptr, "\t Requester Id: 0x%h", requester_id);
$fdisplay(_log_file_ptr, "\t Tag: 0x%h", tag);
casex({fmt, f_type})
`PCI_EXP_MEM_READ64,
`PCI_EXP_MEM_WRITE64: begin
$fdisplay(_log_file_ptr, "\t Last and First Byte Enables: 0x%h", byte_enables);
$fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
`PCI_EXP_MSG_NODATA,
`PCI_EXP_MSG_DATA: begin
msg_type = f_type;
$fdisplay(_log_file_ptr, "\t Message Type: 0x%h", msg_type);
$fdisplay(_log_file_ptr, "\t Message Code: 0x%h", message_code);
$fdisplay(_log_file_ptr, "\t Address High: 0x%h", address_high);
$fdisplay(_log_file_ptr, "\t Address Low: 0x%h \n", address_low);
if (payload == 1) begin
for (_i = 16; _i < _frame_store_idx; _i = _i + 1) begin
$fdisplay(_log_file_ptr, "\t 0x%h", txrx ? frame_store_tx[_i] : frame_store_rx[_i]);
end
end
end
endcase
end
endtask // TSK_4DW
/************************************************************
Task : TSK_READ_DATA
Inputs : None
Outputs : None
Description : Consume clocks.
*************************************************************/
task TSK_READ_DATA;
input last;
input txrx;
input [63:0] trn_d;
input [3:0] trn_rem;
integer _i;
reg [7:0] _byte;
reg [63:0] _msk;
reg [3:0] _rem;
begin
_msk = 64'hff00000000000000;
_rem = last ? ((trn_rem == 8'h0F) ? 4 : 8) : 8;
for (_i = 0; _i < _rem; _i = _i + 1) begin
_byte = (trn_d & (_msk >> (_i * 8))) >> (((7) - _i) * 8);
if (txrx) begin
board.RP.com_usrapp.frame_store_tx[board.RP.com_usrapp.frame_store_tx_idx] = _byte;
board.RP.com_usrapp.frame_store_tx_idx = board.RP.com_usrapp.frame_store_tx_idx + 1;
end else begin
board.RP.com_usrapp.frame_store_rx[board.RP.com_usrapp.frame_store_rx_idx] = _byte;
board.RP.com_usrapp.frame_store_rx_idx = board.RP.com_usrapp.frame_store_rx_idx + 1;
end
end
end
endtask // TSK_READ_DATA
`include "pci_exp_expect_tasks.v"
endmodule // pci_exp_usrapp_com
|
/* ********************************************************************************************* */
/* * SHA-256 Manager * */
/* * Authors: * */
/* * André Bannwart Perina * */
/* * Luciano Falqueto * */
/* * Wallison de Oliveira * */
/* ********************************************************************************************* */
/* * Copyright (c) 2016 André B. Perina, Luciano Falqueto and Wallison de Oliveira * */
/* * * */
/* * Permission is hereby granted, free of charge, to any person obtaining a copy of this * */
/* * software and associated documentation files (the "Software"), to deal in the Software * */
/* * without restriction, including without limitation the rights to use, copy, modify, * */
/* * merge, publish, distribute, sublicense, and/or sell copies of the Software, and to * */
/* * permit persons to whom the Software is furnished to do so, subject to the following * */
/* * conditions: * */
/* * * */
/* * The above copyright notice and this permission notice shall be included in all copies * */
/* * or substantial portions of the Software. * */
/* * * */
/* * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, * */
/* * INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR * */
/* * PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE * */
/* * FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR * */
/* * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * */
/* * DEALINGS IN THE SOFTWARE. * */
/* ********************************************************************************************* */
module Manager(
clk,
rst_n,
p_mosi,
p_miso,
p_valid,
sha_reset_n,
sha_init,
sha_next,
sha_mode,
sha_block,
sha_digest
);
/* Usual inputs */
input clk;
input rst_n;
/* Parallel bus */
input [255:0] p_mosi;
output [255:0] p_miso;
input p_valid;
/* IO to/from SHA-256 module */
output sha_reset_n;
output sha_init;
output sha_next;
output sha_mode;
output [511:0] sha_block;
input [255:0] sha_digest;
reg [1:0] pValidPrev;
assign p_miso = sha_digest;
/* First cycle after rising edge of p_valid: Reset SHA-256 module */
assign sha_reset_n = !(p_valid && !pValidPrev[0]);
/* Second cycle after rising edge of p_valid: Init SHA-256 module */
assign sha_init = (pValidPrev[0] && !pValidPrev[1]);
assign sha_next = 'b0;
assign sha_mode = 'b1;
/* Only 32 bytes are used. The rest is set to standard SHA padding */
assign sha_block = {p_mosi, 1'b1, 255'h100};
always @(posedge clk or negedge rst_n) begin
if(!rst_n) begin
pValidPrev <= 'b11;
end
else begin
/* pValidPrev[0] holds last p_valid value */
pValidPrev[0] <= p_valid;
/* pValidPrev[1] holds second last p_valid value */
pValidPrev[1] <= pValidPrev[0];
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_V
`define SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_V
/**
* nand4bb: 4-input NAND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__nand4bb (
Y ,
A_N,
B_N,
C ,
D
);
// Module ports
output Y ;
input A_N;
input B_N;
input C ;
input D ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out;
wire or0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out, D, C );
or or0 (or0_out_Y, B_N, A_N, nand0_out);
buf buf0 (Y , or0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND4BB_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_PP_V
/**
* a2111oi: 2-input AND into first input of 4-input NOR.
*
* Y = !((A1 & A2) | B1 | C1 | D1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__a2111oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y , B1, C1, D1, and0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111OI_BEHAVIORAL_PP_V |
module ARMAria
#(
parameter WORD_SIZE = 32,
parameter INSTRUCTION_WIDTH = 16,
parameter FLAG_COUNT = 5,
parameter IO_WIDTH = 16,
parameter SEGMENTS_COUNT = 7*8,
parameter OFFSET_WIDTH = 12
)(
input fast_clock, confirmation_button, reset_button,
input continue_button, request_os_button,
input [(IO_WIDTH - 1) : 0] sw,
output [(IO_WIDTH - 1) : 0] rled,
output [(FLAG_COUNT - 1) : 0] gled,
output [(SEGMENTS_COUNT - 1) : 0] sseg,
output slow_clock, reset,
output is_input, is_output, enable
);
/* Wire Declaration Section*/
wire alu_negative, alu_zero, alu_carry, alu_overflow;
wire bs_negative, bs_zero, bs_carry, confirmation;
wire continue_debounced, n_flag, z_flag, should_branch;
wire c_flag, v_flag, is_os, is_memory_write;
wire should_fill_b_offset, is_bios, user_request;
wire [1 : 0] interruption;
wire [2 : 0] controlMAH, b_sign_extend;
wire [2 : 0] load_sign_extend, controlRB;
wire [3 : 0] RegD, RegA, RegB, controlALU, controlBS;
wire [(OFFSET_WIDTH - 1) : 0] OffImmed;
wire [(INSTRUCTION_WIDTH -1) : 0] Instruction;
wire [(WORD_SIZE - 1) : 0] instruction_address, next_PC;
wire [(WORD_SIZE - 1) : 0] data_address, ALU_result, final_result;
wire [(WORD_SIZE - 1) : 0] PC, SP, memory_read_data, Bse;
wire [(WORD_SIZE - 1) : 0] PreMemIn, MemIn, Bbus, IData, PreB;
wire [(WORD_SIZE - 1) : 0] next_SP, Abus, MemOut, Bsh;
/* Buttons startup */
DeBounce dbc(fast_clock, confirmation_button, confirmation);
DeBounce dbr(fast_clock, reset_button, reset);
DeBounce dbco(fast_clock, continue_button, continue_debounced);
DeBounce dbur(fast_clock, request_os_button, user_request);
/*Drive slow clock */
FrequencyDivider fd(fast_clock, slow_clock);
/* Module interconnection*/
Control control_unit(
Instruction,
alu_negative, alu_carry, alu_overflow,
alu_zero, continue_debounced, bs_negative,
bs_zero, bs_carry, reset, slow_clock,
confirmation,
interruption,
OffImmed,
RegD, RegA, RegB,
controlBS, controlALU,
controlRB, controlMAH,
b_sign_extend, load_sign_extend,
is_memory_write, should_fill_b_offset,
n_flag, z_flag, c_flag, v_flag, is_os, enable,
should_branch, is_input, is_output, is_bios
);
MemoryUnit mu(
is_memory_write, slow_clock, fast_clock,
data_address, instruction_address, MemOut,
is_bios,
Instruction,
memory_read_data
);
IOmodule enterescape(
slow_clock, fast_clock,
is_output & (~is_input),
reset, enable,
MemOut, IData, sw,
n_flag, z_flag, c_flag, v_flag, is_os,
rled, gled, sseg, instruction_address
);
MemoryAddressHandler mah(
is_os, should_branch, reset,
controlMAH,
ALU_result, PC, SP,
next_SP, data_address,
final_result, next_PC,
instruction_address
);
MemoryDataHandler mdh(
(is_input && !is_output),
IData, memory_read_data,
PreMemIn
);
SignExtend load_sign_extend_unit(
PreMemIn,
load_sign_extend,
MemIn
);
RegBank ARMARIAbank(
enable, reset, slow_clock, fast_clock,
controlRB,
RegA, RegB, RegD,
final_result, MemIn,
next_SP, next_PC,
Abus, Bbus,
PC, SP, MemOut,
{n_flag, z_flag, c_flag, v_flag}
);
MUXBS muxbusb(
should_fill_b_offset,
Bbus, OffImmed,
PreB
);
SignExtend channel_B_sign_extend_unit(
PreB,
b_sign_extend,
Bse
);
BarrelShifter NiagaraFalls(
Abus, Bse,
controlBS,
Bsh,
bs_negative, bs_zero, bs_carry
);
ALU arithmeticlogicunit(
Abus, Bsh,
ALU_result,
controlALU,
c_flag,
alu_negative, alu_zero, alu_carry, alu_overflow
);
Watchdog pitbull(
slow_clock, fast_clock,
user_request,
interruption
);
endmodule
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: main
// Project Name:
// Target Devices:
// Tool versions:
// Description: Master Control FSM
//
// Dependencies: address
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module main(
/* input clock */
input CLKIN,
/* SNES signals */
input [23:0] SNES_ADDR_IN,
input SNES_READ_IN,
input SNES_WRITE_IN,
input SNES_ROMSEL_IN,
inout [7:0] SNES_DATA,
input SNES_CPU_CLK_IN,
input SNES_REFRESH,
output SNES_IRQ,
output SNES_DATABUS_OE,
output SNES_DATABUS_DIR,
input SNES_SYSCLK,
input [7:0] SNES_PA_IN,
input SNES_PARD_IN,
input SNES_PAWR_IN,
/* SRAM signals */
/* Bus 1: PSRAM, 128Mbit, 16bit, 70ns */
inout [15:0] ROM_DATA,
output [22:0] ROM_ADDR,
output ROM_CE,
output ROM_OE,
output ROM_WE,
output ROM_BHE,
output ROM_BLE,
/* Bus 2: SRAM, 4Mbit, 8bit, 45ns */
inout [7:0] RAM_DATA,
output [18:0] RAM_ADDR,
//output RAM_CE,
output RAM_OE,
output RAM_WE,
/* MCU signals */
input SPI_MOSI,
inout SPI_MISO,
input SPI_SS,
inout SPI_SCK,
input MCU_OVR,
output MCU_RDY,
output DAC_MCLK,
output DAC_LRCK,
output DAC_SDOUT,
/* SD signals */
input [3:0] SD_DAT,
inout SD_CMD,
inout SD_CLK,
/* debug */
output p113_out
);
wire CLK2;
wire [7:0] GSU_SNES_DATA_IN;
wire [7:0] GSU_SNES_DATA_OUT;
wire [7:0] spi_cmd_data;
wire [7:0] spi_param_data;
wire [7:0] spi_input_data;
wire [31:0] spi_byte_cnt;
wire [2:0] spi_bit_cnt;
wire [23:0] MCU_ADDR;
wire [2:0] MAPPER;
wire [23:0] SAVERAM_MASK;
wire [23:0] ROM_MASK;
wire [7:0] SD_DMA_SRAM_DATA;
wire [1:0] SD_DMA_TGT;
wire [10:0] SD_DMA_PARTIAL_START;
wire [10:0] SD_DMA_PARTIAL_END;
wire [10:0] dac_addr;
wire [2:0] dac_vol_select_out;
wire [8:0] dac_ptr_addr;
wire [7:0] msu_volumerq_out;
wire [7:0] msu_status_out;
wire [31:0] msu_addressrq_out;
wire [15:0] msu_trackrq_out;
wire [13:0] msu_write_addr;
wire [13:0] msu_ptr_addr;
wire [7:0] MSU_SNES_DATA_IN;
wire [7:0] MSU_SNES_DATA_OUT;
wire [5:0] msu_status_reset_bits;
wire [5:0] msu_status_set_bits;
wire [23:0] MAPPED_SNES_ADDR;
wire ROM_ADDR0;
wire [8:0] snescmd_addr_mcu;
wire [7:0] snescmd_data_out_mcu;
wire [7:0] snescmd_data_in_mcu;
reg [7:0] SNES_PARDr;
reg [7:0] SNES_READr;
reg [7:0] SNES_WRITEr;
reg [7:0] SNES_CPU_CLKr;
reg [7:0] SNES_ROMSELr;
reg [23:0] SNES_ADDRr [6:0];
reg [7:0] SNES_PAr [6:0];
reg [7:0] SNES_DATAr [4:0];
reg SNES_DEADr = 1;
reg SNES_reset_strobe = 0;
reg free_strobe = 0;
wire SNES_PARD_start = ((SNES_PARDr[6:1] | SNES_PARDr[7:2]) == 6'b111110);
wire SNES_RD_start = ((SNES_READr[6:1] | SNES_READr[7:2]) == 6'b111100);
wire SNES_RD_end = ((SNES_READr[6:1] & SNES_READr[7:2]) == 6'b000001);
wire SNES_WR_end = ((SNES_WRITEr[6:1] & SNES_WRITEr[7:2]) == 6'b000001);
wire SNES_cycle_start = ((SNES_CPU_CLKr[7:2] & SNES_CPU_CLKr[6:1]) == 6'b000011);
wire SNES_cycle_end = ((SNES_CPU_CLKr[7:2] | SNES_CPU_CLKr[6:1]) == 6'b111000);
wire SNES_WRITE = SNES_WRITEr[2] & SNES_WRITEr[1];
wire SNES_READ = SNES_READr[2] & SNES_READr[1];
wire SNES_CPU_CLK = SNES_CPU_CLKr[2] & SNES_CPU_CLKr[1];
wire SNES_PARD = SNES_PARDr[2] & SNES_PARDr[1];
wire SNES_ROMSEL = (SNES_ROMSELr[5] & SNES_ROMSELr[4]);
wire [23:0] SNES_ADDR = (SNES_ADDRr[6] & SNES_ADDRr[5]);
wire [7:0] SNES_PA = (SNES_PAr[6] & SNES_PAr[5]);
wire [7:0] SNES_DATA_IN = (SNES_DATAr[3] & SNES_DATAr[2]);
reg [7:0] BUS_DATA;
always @(posedge CLK2) begin
if(~SNES_READ) BUS_DATA <= SNES_DATA;
else if(~SNES_WRITE) BUS_DATA <= SNES_DATA_IN;
end
wire free_slot = SNES_cycle_end | free_strobe;
wire ROM_HIT;
assign DCM_RST=0;
always @(posedge CLK2) begin
free_strobe <= 1'b0;
if(SNES_cycle_start) free_strobe <= ~ROM_HIT;
end
always @(posedge CLK2) begin
SNES_PARDr <= {SNES_PARDr[6:0], SNES_PARD_IN};
SNES_READr <= {SNES_READr[6:0], SNES_READ_IN};
SNES_WRITEr <= {SNES_WRITEr[6:0], SNES_WRITE_IN};
SNES_CPU_CLKr <= {SNES_CPU_CLKr[6:0], SNES_CPU_CLK_IN};
SNES_ROMSELr <= {SNES_ROMSELr[6:0], SNES_ROMSEL_IN};
SNES_ADDRr[6] <= SNES_ADDRr[5];
SNES_ADDRr[5] <= SNES_ADDRr[4];
SNES_ADDRr[4] <= SNES_ADDRr[3];
SNES_ADDRr[3] <= SNES_ADDRr[2];
SNES_ADDRr[2] <= SNES_ADDRr[1];
SNES_ADDRr[1] <= SNES_ADDRr[0];
SNES_ADDRr[0] <= SNES_ADDR_IN;
SNES_PAr[6] <= SNES_PAr[5];
SNES_PAr[5] <= SNES_PAr[4];
SNES_PAr[4] <= SNES_PAr[3];
SNES_PAr[3] <= SNES_PAr[2];
SNES_PAr[2] <= SNES_PAr[1];
SNES_PAr[1] <= SNES_PAr[0];
SNES_PAr[0] <= SNES_PA_IN;
SNES_DATAr[4] <= SNES_DATAr[3];
SNES_DATAr[3] <= SNES_DATAr[2];
SNES_DATAr[2] <= SNES_DATAr[1];
SNES_DATAr[1] <= SNES_DATAr[0];
SNES_DATAr[0] <= SNES_DATA;
end
parameter ST_IDLE = 7'b0000001;
parameter ST_MCU_RD_ADDR = 7'b0000010;
parameter ST_MCU_RD_END = 7'b0000100;
parameter ST_MCU_WR_ADDR = 7'b0001000;
parameter ST_MCU_WR_END = 7'b0010000;
parameter ST_GSU_ROM_RD_ADDR = 7'b0100000;
parameter ST_GSU_ROM_RD_END = 7'b1000000;
parameter ST_RAM_IDLE = 7'b0000001;
parameter ST_RAM_GSU_RD_ADDR = 7'b0000010;
parameter ST_RAM_GSU_RD_END = 7'b0000100;
parameter ST_RAM_GSU_WR_ADDR = 7'b0001000;
parameter ST_RAM_GSU_WR_END = 7'b0010000;
parameter SNES_DEAD_TIMEOUT = 17'd86400; // 1ms
parameter ROM_CYCLE_LEN = 4'd7;
parameter RAM_CYCLE_LEN = 4'd4;
reg [6:0] STATE;
reg [6:0] RAM_STATE;
initial STATE = ST_IDLE;
assign MSU_SNES_DATA_IN = BUS_DATA;
assign GSU_SNES_DATA_IN = BUS_DATA;
sd_dma snes_sd_dma(
.CLK(CLK2),
.SD_DAT(SD_DAT),
.SD_CLK(SD_CLK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.DBG_cyclecnt(SD_DMA_DBG_cyclecnt),
.DBG_clkcnt(SD_DMA_DBG_clkcnt)
);
wire SD_DMA_TO_ROM = (SD_DMA_STATUS && (SD_DMA_TGT == 2'b00));
dac snes_dac(
.clkin(CLK2),
.sysclk(SNES_SYSCLK),
.mclk_out(DAC_MCLK),
.lrck_out(DAC_LRCK),
.sdout(DAC_SDOUT),
.we(SD_DMA_TGT==2'b01 ? SD_DMA_SRAM_WE : 1'b1),
.pgm_address(dac_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.DAC_STATUS(DAC_STATUS),
.volume(msu_volumerq_out),
.vol_latch(msu_volume_latch_out),
.vol_select(dac_vol_select_out),
.palmode(dac_palmode_out),
.play(dac_play),
.reset(dac_reset),
.dac_address_ext(dac_ptr_addr)
);
msu snes_msu (
.clkin(CLK2),
.enable(msu_enable),
.pgm_address(msu_write_addr),
.pgm_data(SD_DMA_SRAM_DATA),
.pgm_we(SD_DMA_TGT==2'b10 ? SD_DMA_SRAM_WE : 1'b1),
.reg_addr(SNES_ADDR[2:0]),
.reg_data_in(MSU_SNES_DATA_IN),
.reg_data_out(MSU_SNES_DATA_OUT),
.reg_oe_falling(SNES_RD_start),
.reg_oe_rising(SNES_RD_end),
.reg_we_rising(SNES_WR_end),
.status_out(msu_status_out),
.volume_out(msu_volumerq_out),
.volume_latch_out(msu_volume_latch_out),
.addr_out(msu_addressrq_out),
.track_out(msu_trackrq_out),
.status_reset_bits(msu_status_reset_bits),
.status_set_bits(msu_status_set_bits),
.status_reset_we(msu_status_reset_we),
.msu_address_ext(msu_ptr_addr),
.msu_address_ext_write(msu_addr_reset),
.DBG_msu_reg_oe_rising(DBG_msu_reg_oe_rising),
.DBG_msu_reg_oe_falling(DBG_msu_reg_oe_falling),
.DBG_msu_reg_we_rising(DBG_msu_reg_we_rising),
.DBG_msu_address(DBG_msu_address),
.DBG_msu_address_ext_write_rising(DBG_msu_address_ext_write_rising)
);
reg [7:0] GSU_ROM_DINr;
wire [23:0] GSU_ROM_ADDR;
reg [7:0] GSU_RAM_DINr;
reg [7:0] GSU_RAM_DOr;
wire [18:0] GSU_RAM_ADDR;
//wire [2:0] gsu_busy;
gsu snes_gsu (
.clkin(CLK2),
.DI(GSU_SNES_DATA_IN),
.DO(GSU_SNES_DATA_OUT),
.ADDR(SNES_ADDR),
.CS(gsu_enable),
.reg_we_rising(SNES_WR_end),
.ROM_BUS_DI(GSU_ROM_DINr),
.ROM_BUS_ADDR(GSU_ROM_ADDR),
.ROM_BUS_RRQ(GSU_ROM_RRQ),
.ROM_BUS_RDY(GSU_ROM_RDY),
.RAM_BUS_DI(GSU_RAM_DINr),
.RAM_BUS_DO(GSU_RAM_DOr),
.RAM_BUS_ADDR(GSU_RAM_ADDR),
.RAM_BUS_RRQ(GSU_RAM_RRQ),
.RAM_BUS_WRQ(GSU_RAM_WRQ),
.RAM_BUS_RDY(GSU_RAM_RDY),
.gsu_active(gsu_active),
.ron(gsu_rom_exclusive),
.ran(gsu_ram_exclusive)
);
spi snes_spi(
.clk(CLK2),
.MOSI(SPI_MOSI),
.MISO(SPI_MISO),
.SSEL(SPI_SS),
.SCK(SPI_SCK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.endmessage(spi_endmessage),
.startmessage(spi_startmessage),
.input_data(spi_input_data),
.byte_cnt(spi_byte_cnt),
.bit_cnt(spi_bit_cnt)
);
reg [7:0] MCU_DINr;
wire [7:0] MCU_DOUT;
wire [7:0] featurebits;
wire [31:0] cheat_pgm_data;
wire [7:0] cheat_data_out;
wire [2:0] cheat_pgm_idx;
wire [15:0] dsp_feat;
wire feat_cmd_unlock = featurebits[5];
mcu_cmd snes_mcu_cmd(
.clk(CLK2),
.snes_sysclk(SNES_SYSCLK),
.cmd_ready(spi_cmd_ready),
.param_ready(spi_param_ready),
.cmd_data(spi_cmd_data),
.param_data(spi_param_data),
.mcu_mapper(MAPPER),
.mcu_write(MCU_WRITE),
.mcu_data_in(MCU_DINr),
.mcu_data_out(MCU_DOUT),
.spi_byte_cnt(spi_byte_cnt),
.spi_bit_cnt(spi_bit_cnt),
.spi_data_out(spi_input_data),
.addr_out(MCU_ADDR),
.saveram_mask_out(SAVERAM_MASK),
.rom_mask_out(ROM_MASK),
.SD_DMA_EN(SD_DMA_EN),
.SD_DMA_STATUS(SD_DMA_STATUS),
.SD_DMA_NEXTADDR(SD_DMA_NEXTADDR),
.SD_DMA_SRAM_DATA(SD_DMA_SRAM_DATA),
.SD_DMA_SRAM_WE(SD_DMA_SRAM_WE),
.SD_DMA_TGT(SD_DMA_TGT),
.SD_DMA_PARTIAL(SD_DMA_PARTIAL),
.SD_DMA_PARTIAL_START(SD_DMA_PARTIAL_START),
.SD_DMA_PARTIAL_END(SD_DMA_PARTIAL_END),
.SD_DMA_START_MID_BLOCK(SD_DMA_START_MID_BLOCK),
.SD_DMA_END_MID_BLOCK(SD_DMA_END_MID_BLOCK),
.dac_addr_out(dac_addr),
.DAC_STATUS(DAC_STATUS),
.dac_play_out(dac_play),
.dac_reset_out(dac_reset),
.dac_vol_select_out(dac_vol_select_out),
.dac_palmode_out(dac_palmode_out),
.dac_ptr_out(dac_ptr_addr),
.msu_addr_out(msu_write_addr),
.MSU_STATUS(msu_status_out),
.msu_status_reset_out(msu_status_reset_bits),
.msu_status_set_out(msu_status_set_bits),
.msu_status_reset_we(msu_status_reset_we),
.msu_volumerq(msu_volumerq_out),
.msu_addressrq(msu_addressrq_out),
.msu_trackrq(msu_trackrq_out),
.msu_ptr_out(msu_ptr_addr),
.msu_reset_out(msu_addr_reset),
.featurebits_out(featurebits),
.gsu_reset_out(gsu_reset),
.mcu_rrq(MCU_RRQ),
.mcu_wrq(MCU_WRQ),
.mcu_rq_rdy(MCU_RDY),
.region_out(mcu_region),
.snescmd_addr_out(snescmd_addr_mcu),
.snescmd_we_out(snescmd_we_mcu),
.snescmd_data_out(snescmd_data_out_mcu),
.snescmd_data_in(snescmd_data_in_mcu),
.cheat_pgm_idx_out(cheat_pgm_idx),
.cheat_pgm_data_out(cheat_pgm_data),
.cheat_pgm_we_out(cheat_pgm_we),
.dsp_feat_out(dsp_feat)
);
wire [7:0] DCM_STATUS;
// dcm1: dfs 3.6x
my_dcm snes_dcm(
.CLKIN(CLKIN),
.CLKFX(CLK2),
.LOCKED(DCM_LOCKED),
.RST(DCM_RST),
.STATUS(DCM_STATUS)
);
address snes_addr(
.CLK(CLK2),
.MAPPER(MAPPER),
.featurebits(featurebits),
.SNES_ADDR(SNES_ADDR), // requested address from SNES
.SNES_PA(SNES_PA),
.SNES_ROMSEL(SNES_ROMSEL),
.MAPPED_ADDR(MAPPED_SNES_ADDR), // Address to request from SRAM (active low)
.SRAM0_HIT(ROM_HIT), // want to access RAM0
.SRAM1_HIT(RAM_HIT), // want to access RAM1
.IS_SAVERAM(IS_SAVERAM),
.IS_GAMEPAKRAM(IS_GAMEPAKRAM),
.IS_ROM(IS_ROM),
.IS_WRITABLE(IS_WRITABLE),
.SAVERAM_MASK(SAVERAM_MASK),
.ROM_MASK(ROM_MASK),
//MSU-1
.msu_enable(msu_enable),
//GSU
.gsu_enable(gsu_enable),
//region
.r213f_enable(r213f_enable),
//CMD Interface
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable)
);
reg pad_latch = 0;
reg [4:0] pad_cnt = 0;
reg snes_ajr = 0;
cheat snes_cheat(
.clk(CLK2),
.SNES_ADDR(SNES_ADDR),
.SNES_PA(SNES_PA),
.SNES_DATA(SNES_DATA),
.SNES_reset_strobe(SNES_reset_strobe),
.SNES_wr_strobe(SNES_WR_end),
.SNES_rd_strobe(SNES_RD_start),
.snescmd_enable(snescmd_enable),
.nmicmd_enable(nmicmd_enable),
.return_vector_enable(return_vector_enable),
.branch1_enable(branch1_enable),
.branch2_enable(branch2_enable),
.pad_latch(pad_latch),
.snes_ajr(snes_ajr),
.SNES_cycle_start(SNES_cycle_start),
.pgm_idx(cheat_pgm_idx),
.pgm_we(cheat_pgm_we),
.pgm_in(cheat_pgm_data),
.data_out(cheat_data_out),
.cheat_hit(cheat_hit),
.snescmd_unlock(snescmd_unlock)
);
wire [7:0] snescmd_dout;
reg [7:0] r213fr;
reg r213f_forceread;
reg [2:0] r213f_delay;
reg [1:0] r213f_state;
initial r213fr = 8'h55;
initial r213f_forceread = 0;
initial r213f_state = 2'b01;
initial r213f_delay = 3'b000;
wire snoop_4200_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04200;
wire r4016_enable = {SNES_ADDR[22], SNES_ADDR[15:0]} == 17'h04016;
always @(posedge CLK2) begin
if(SNES_WR_end & snoop_4200_enable) begin
snes_ajr <= SNES_DATA[0];
end
end
always @(posedge CLK2) begin
if(SNES_WR_end & r4016_enable) begin
pad_latch <= 1'b1;
pad_cnt <= 5'h0;
end
if(SNES_RD_start & r4016_enable) begin
pad_cnt <= pad_cnt + 1;
if(&pad_cnt[3:0]) begin
pad_latch <= 1'b0;
end
end
end
assign SNES_DATA = (r213f_enable & ~SNES_PARD & ~r213f_forceread) ? r213fr
:(~SNES_READ ^ (r213f_forceread & r213f_enable & ~SNES_PARD))
? (msu_enable ? MSU_SNES_DATA_OUT
:gsu_enable ? GSU_SNES_DATA_OUT
:(cheat_hit & ~feat_cmd_unlock) ? cheat_data_out
:((snescmd_unlock | feat_cmd_unlock) & snescmd_enable) ? snescmd_dout
:(RAM_HIT & ~gsu_ram_exclusive) ? RAM_DATA
:(ROM_HIT & ~gsu_rom_exclusive) ? (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8])
: 8'bZ // XXX: will this cause problems? Should we have some kind of a driven value here?
) : 8'bZ;
reg [3:0] ST_MEM_DELAYr;
reg [3:0] ST_RAM_DELAYr;
reg MCU_RD_PENDr = 0;
reg MCU_WR_PENDr = 0;
reg GSU_ROM_RD_PENDr = 0;
reg GSU_RAM_RD_PENDr = 0;
reg GSU_RAM_WR_PENDr = 0;
reg [23:0] ROM_ADDRr;
reg [23:0] GSU_ROM_ADDRr;
reg [23:0] RAM_ADDRr;
reg [23:0] GSU_RAM_ADDRr;
reg RQ_MCU_RDYr;
initial RQ_MCU_RDYr = 1'b1;
assign MCU_RDY = RQ_MCU_RDYr;
reg RQ_GSU_ROM_RDYr;
initial RQ_GSU_ROM_RDYr = 1'b1;
assign GSU_ROM_RDY = RQ_GSU_ROM_RDYr;
reg RQ_GSU_RAM_RDYr;
initial RQ_GSU_RAM_RDYr = 1'b1;
assign GSU_RAM_RDY = RQ_GSU_RAM_RDYr;
wire MCU_WR_HIT = |(STATE & ST_MCU_WR_ADDR);
wire MCU_RD_HIT = |(STATE & ST_MCU_RD_ADDR);
wire MCU_HIT = MCU_WR_HIT | MCU_RD_HIT;
wire GSU_ROM_HIT = |(STATE & ST_GSU_ROM_RD_ADDR);
wire GSU_RAM_WR_HIT = |(RAM_STATE & ST_RAM_GSU_WR_ADDR);
wire GSU_RAM_RD_HIT = |(RAM_STATE & ST_RAM_GSU_RD_ADDR);
wire GSU_RAM_HIT = GSU_RAM_WR_HIT | GSU_RAM_RD_HIT;
assign ROM_ADDR = (SD_DMA_TO_ROM) ? MCU_ADDR[23:1] : MCU_HIT ? ROM_ADDRr[23:1] : GSU_ROM_HIT ? GSU_ROM_ADDRr[23:1] : MAPPED_SNES_ADDR[23:1];
assign ROM_ADDR0 = (SD_DMA_TO_ROM) ? MCU_ADDR[0] : MCU_HIT ? ROM_ADDRr[0] : GSU_ROM_HIT ? GSU_ROM_ADDRr[0] : MAPPED_SNES_ADDR[0];
assign RAM_ADDR = GSU_RAM_HIT ? GSU_RAM_ADDRr : MAPPED_SNES_ADDR;
reg[17:0] SNES_DEAD_CNTr;
initial SNES_DEAD_CNTr = 0;
always @(posedge CLK2) begin
if(gsu_active) begin
if(GSU_ROM_RRQ) begin
GSU_ROM_RD_PENDr <= 1'b1;
RQ_GSU_ROM_RDYr <= 1'b0;
GSU_ROM_ADDRr <= GSU_ROM_ADDR;
end else if(STATE == ST_GSU_ROM_RD_END) begin
GSU_ROM_RD_PENDr <= 1'b0;
RQ_GSU_ROM_RDYr <= 1'b1;
end
end
end
always @(posedge CLK2) begin
if(gsu_active) begin
if(GSU_RAM_RRQ) begin
GSU_RAM_RD_PENDr <= 1'b1;
RQ_GSU_RAM_RDYr <= 1'b0;
GSU_RAM_ADDRr <= GSU_RAM_ADDR;
end else if (GSU_RAM_WRQ) begin
GSU_RAM_WR_PENDr <= 1'b1;
RQ_GSU_RAM_RDYr <= 1'b0;
GSU_RAM_ADDRr <= GSU_RAM_ADDR;
end else if (RAM_STATE & (ST_RAM_GSU_RD_END | ST_RAM_GSU_WR_END)) begin
GSU_RAM_RD_PENDr <= 1'b0;
GSU_RAM_WR_PENDr <= 1'b0;
RQ_GSU_RAM_RDYr <= 1'b1;
end
end
end
always @(posedge CLK2) begin
if(MCU_RRQ) begin
MCU_RD_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(MCU_WRQ) begin
MCU_WR_PENDr <= 1'b1;
RQ_MCU_RDYr <= 1'b0;
ROM_ADDRr <= MCU_ADDR;
end else if(STATE & (ST_MCU_RD_END | ST_MCU_WR_END)) begin
MCU_RD_PENDr <= 1'b0;
MCU_WR_PENDr <= 1'b0;
RQ_MCU_RDYr <= 1'b1;
end
end
always @(posedge CLK2) begin
if(~SNES_CPU_CLKr[1]) SNES_DEAD_CNTr <= SNES_DEAD_CNTr + 1;
else SNES_DEAD_CNTr <= 17'h0;
end
always @(posedge CLK2) begin
SNES_reset_strobe <= 1'b0;
if(SNES_CPU_CLKr[1]) begin
SNES_DEADr <= 1'b0;
if(SNES_DEADr) SNES_reset_strobe <= 1'b1;
end
else if(SNES_DEAD_CNTr > SNES_DEAD_TIMEOUT) SNES_DEADr <= 1'b1;
end
always @(posedge CLK2) begin
if(SNES_DEADr & SNES_CPU_CLKr[1]) STATE <= ST_IDLE; // interrupt+restart an ongoing MCU access when the SNES comes alive
else
case(STATE)
ST_IDLE: begin
STATE <= ST_IDLE;
if(gsu_active) begin
if (GSU_ROM_RD_PENDr) begin
STATE <= ST_GSU_ROM_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN; // XXX: what is the right value here?
end
end else if(free_slot | SNES_DEADr) begin
if(MCU_RD_PENDr) begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
else if(MCU_WR_PENDr) begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ROM_CYCLE_LEN;
end
end
end
ST_MCU_RD_ADDR: begin
STATE <= ST_MCU_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_RD_END;
MCU_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_MCU_WR_ADDR: begin
STATE <= ST_MCU_WR_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_MCU_WR_END;
end
ST_MCU_RD_END, ST_MCU_WR_END: begin
STATE <= ST_IDLE;
end
ST_GSU_ROM_RD_ADDR: begin
STATE <= ST_GSU_ROM_RD_ADDR;
ST_MEM_DELAYr <= ST_MEM_DELAYr - 1;
if(ST_MEM_DELAYr == 0) STATE <= ST_GSU_ROM_RD_END;
GSU_ROM_DINr <= (ROM_ADDR0 ? ROM_DATA[7:0] : ROM_DATA[15:8]);
end
ST_GSU_ROM_RD_END: begin
STATE <= ST_IDLE;
end
endcase
end
always @(posedge CLK2) begin
case (RAM_STATE)
ST_RAM_IDLE: begin
RAM_STATE <= ST_RAM_IDLE;
if (gsu_active) begin
if (GSU_RAM_RD_PENDr) begin
RAM_STATE <= ST_RAM_GSU_RD_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
else if (GSU_RAM_WR_PENDr) begin
RAM_STATE <= ST_RAM_GSU_WR_ADDR;
ST_RAM_DELAYr <= RAM_CYCLE_LEN;
end
end
end
ST_RAM_GSU_RD_ADDR: begin
RAM_STATE <= ST_RAM_GSU_RD_ADDR;
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_GSU_RD_END;
GSU_RAM_DINr <= RAM_DATA; // XXX: make sure RAM_DATA is 8 bits wide
end
ST_RAM_GSU_WR_ADDR: begin
RAM_STATE <= ST_RAM_GSU_WR_ADDR;
ST_RAM_DELAYr <= ST_RAM_DELAYr - 1;
if(ST_RAM_DELAYr == 0) RAM_STATE <= ST_RAM_GSU_WR_END;
end
ST_RAM_GSU_RD_END, ST_RAM_GSU_WR_END: begin
RAM_STATE <= ST_RAM_IDLE;
end
endcase
end
always @(posedge CLK2) begin
if(SNES_cycle_end) r213f_forceread <= 1'b1;
else if(SNES_PARD_start & r213f_enable) begin
// r213f_delay <= 3'b000;
// r213f_state <= 2'b10;
// end else if(r213f_state == 2'b10) begin
// r213f_delay <= r213f_delay - 1;
// if(r213f_delay == 3'b000) begin
r213f_forceread <= 1'b0;
r213f_state <= 2'b01;
r213fr <= {SNES_DATA[7:5], mcu_region, SNES_DATA[3:0]};
// end
end
end
reg MCU_WRITE_1;
always @(posedge CLK2) MCU_WRITE_1<= MCU_WRITE;
assign ROM_DATA[7:0] = ROM_ADDR0
?(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT : 8'bZ
)
:8'bZ;
assign ROM_DATA[15:8] = ROM_ADDR0 ? 8'bZ
:(SD_DMA_TO_ROM ? (!MCU_WRITE_1 ? MCU_DOUT : 8'bZ)
: (ROM_HIT & ~SNES_WRITE) ? SNES_DATA
: MCU_WR_HIT ? MCU_DOUT
: 8'bZ
);
assign ROM_WE = SD_DMA_TO_ROM
?MCU_WRITE
: (ROM_HIT & IS_WRITABLE & SNES_CPU_CLK) ? SNES_WRITE
: MCU_WR_HIT ? 1'b0
: 1'b1;
// OE always active. Overridden by WE when needed.
assign ROM_OE = 1'b0;
assign ROM_CE = 1'b0;
assign ROM_BHE = ROM_ADDR0;
assign ROM_BLE = !ROM_ADDR0;
assign RAM_DATA = (RAM_HIT & ~SNES_WRITE) ? SNES_DATA
: (GSU_RAM_WR_HIT ? GSU_SNES_DATA_OUT : 8'bZ);
// XXX: the GSU should actually be in a waiting state when ran = 0 and RAM access is needed.
assign RAM_WE = (~gsu_ram_exclusive & RAM_HIT & SNES_CPU_CLK) ? SNES_WRITE
: (gsu_ram_exclusive & GSU_RAM_WR_HIT) ? 1'b0
: 1'b1;
assign RAM_OE = 1'b0;
//assign RAM_CE = 1'b0;
assign SNES_DATABUS_OE = msu_enable ? 1'b0 :
gsu_enable ? 1'b0 :
r213f_enable & !SNES_PARD ? 1'b0 :
snoop_4200_enable ? SNES_WRITE :
snescmd_enable ? (~(snescmd_unlock | feat_cmd_unlock) | (SNES_READ & SNES_WRITE)) :
((IS_ROM & SNES_ROMSEL)
|(!IS_ROM & !IS_SAVERAM & !IS_WRITABLE)
|(SNES_READ & SNES_WRITE)
);
assign SNES_DATABUS_DIR = (~SNES_READ | (~SNES_PARD & (r213f_enable)))
? 1'b1 ^ (r213f_forceread & r213f_enable & ~SNES_PARD)
: 1'b0;
assign SNES_IRQ = 1'b0; // TODO: the GSU can send an IRQ
assign p113_out = 1'b0;
snescmd_buf snescmd (
.clka(CLK2), // input clka
.wea(SNES_WR_end & ((snescmd_unlock | feat_cmd_unlock) & snescmd_enable)), // input [0 : 0] wea
.addra(SNES_ADDR[8:0]), // input [8 : 0] addra
.dina(SNES_DATA), // input [7 : 0] dina
.douta(snescmd_dout), // output [7 : 0] douta
.clkb(CLK2), // input clkb
.web(snescmd_we_mcu), // input [0 : 0] web
.addrb(snescmd_addr_mcu), // input [8 : 0] addrb
.dinb(snescmd_data_out_mcu), // input [7 : 0] dinb
.doutb(snescmd_data_in_mcu) // output [7 : 0] doutb
);
/*
wire [35:0] CONTROL0;
chipscope_icon icon (
.CONTROL0(CONTROL0) // INOUT BUS [35:0]
);
chipscope_ila ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SNES_ADDR), // IN BUS [23:0]
.TRIG1(SNES_DATA), // IN BUS [7:0]
.TRIG2({SNES_READ, SNES_WRITE, SNES_CPU_CLK, SNES_cycle_start, SNES_cycle_end, SNES_DEADr, MCU_RRQ, MCU_WRQ, MCU_RDY, ROM_WEr, ROM_WE, ROM_DOUT_ENr, ROM_SA, DBG_mcu_nextaddr, SNES_DATABUS_DIR, SNES_DATABUS_OE}), // IN BUS [15:0]
.TRIG3({bsx_data_ovr, r213f_forceread, r213f_enable, SNES_PARD, spi_cmd_ready, spi_param_ready, spi_input_data, SD_DAT}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(spi_byte_cnt[3:0])
);
/*
ila_srtc ila (
.CONTROL(CONTROL0), // INOUT BUS [35:0]
.CLK(CLK2), // IN
.TRIG0(SD_DMA_DBG_cyclecnt), // IN BUS [23:0]
.TRIG1(SD_DMA_SRAM_DATA), // IN BUS [7:0]
.TRIG2({SPI_SCK, SPI_MOSI, SPI_MISO, spi_cmd_ready, SD_DMA_SRAM_WE, SD_DMA_EN, SD_CLK, SD_DAT, SD_DMA_NEXTADDR, SD_DMA_STATUS, 3'b000}), // IN BUS [15:0]
.TRIG3({spi_cmd_data, spi_param_data}), // IN BUS [17:0]
.TRIG4(ROM_ADDRr), // IN BUS [23:0]
.TRIG5(ROM_DATA), // IN BUS [15:0]
.TRIG6(MCU_DINr), // IN BUS [7:0]
.TRIG7(ST_MEM_DELAYr)
);
*/
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for axis_arb_mux
*/
module test_axis_arb_mux_4_64;
// Parameters
parameter S_COUNT = 4;
parameter DATA_WIDTH = 64;
parameter KEEP_ENABLE = (DATA_WIDTH>8);
parameter KEEP_WIDTH = (DATA_WIDTH/8);
parameter ID_ENABLE = 1;
parameter ID_WIDTH = 8;
parameter DEST_ENABLE = 1;
parameter DEST_WIDTH = 8;
parameter USER_ENABLE = 1;
parameter USER_WIDTH = 1;
parameter ARB_TYPE_ROUND_ROBIN = 0;
parameter ARB_LSB_HIGH_PRIORITY = 1;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg [S_COUNT*DATA_WIDTH-1:0] s_axis_tdata = 0;
reg [S_COUNT*KEEP_WIDTH-1:0] s_axis_tkeep = 0;
reg [S_COUNT-1:0] s_axis_tvalid = 0;
reg [S_COUNT-1:0] s_axis_tlast = 0;
reg [S_COUNT*ID_WIDTH-1:0] s_axis_tid = 0;
reg [S_COUNT*DEST_WIDTH-1:0] s_axis_tdest = 0;
reg [S_COUNT*USER_WIDTH-1:0] s_axis_tuser = 0;
reg m_axis_tready = 0;
// Outputs
wire [S_COUNT-1:0] s_axis_tready;
wire [DATA_WIDTH-1:0] m_axis_tdata;
wire [KEEP_WIDTH-1:0] m_axis_tkeep;
wire m_axis_tvalid;
wire m_axis_tlast;
wire [ID_WIDTH-1:0] m_axis_tid;
wire [DEST_WIDTH-1:0] m_axis_tdest;
wire [USER_WIDTH-1:0] m_axis_tuser;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_axis_tdata,
s_axis_tkeep,
s_axis_tvalid,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tready
);
$to_myhdl(
s_axis_tready,
m_axis_tdata,
m_axis_tkeep,
m_axis_tvalid,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser
);
// dump file
$dumpfile("test_axis_arb_mux_4_64.lxt");
$dumpvars(0, test_axis_arb_mux_4_64);
end
axis_arb_mux #(
.S_COUNT(S_COUNT),
.DATA_WIDTH(DATA_WIDTH),
.KEEP_ENABLE(KEEP_ENABLE),
.KEEP_WIDTH(KEEP_WIDTH),
.ID_ENABLE(ID_ENABLE),
.ID_WIDTH(ID_WIDTH),
.DEST_ENABLE(DEST_ENABLE),
.DEST_WIDTH(DEST_WIDTH),
.USER_ENABLE(USER_ENABLE),
.USER_WIDTH(USER_WIDTH),
.ARB_TYPE_ROUND_ROBIN(ARB_TYPE_ROUND_ROBIN),
.ARB_LSB_HIGH_PRIORITY(ARB_LSB_HIGH_PRIORITY)
)
UUT (
.clk(clk),
.rst(rst),
// AXI inputs
.s_axis_tdata(s_axis_tdata),
.s_axis_tkeep(s_axis_tkeep),
.s_axis_tvalid(s_axis_tvalid),
.s_axis_tready(s_axis_tready),
.s_axis_tlast(s_axis_tlast),
.s_axis_tid(s_axis_tid),
.s_axis_tdest(s_axis_tdest),
.s_axis_tuser(s_axis_tuser),
// AXI output
.m_axis_tdata(m_axis_tdata),
.m_axis_tkeep(m_axis_tkeep),
.m_axis_tvalid(m_axis_tvalid),
.m_axis_tready(m_axis_tready),
.m_axis_tlast(m_axis_tlast),
.m_axis_tid(m_axis_tid),
.m_axis_tdest(m_axis_tdest),
.m_axis_tuser(m_axis_tuser)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2BB2O_TB_V
`define SKY130_FD_SC_LP__A2BB2O_TB_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2bb2o.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_lp__a2bb2o dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2BB2O_TB_V
|
/****************************************
Load Store
for MIST32 Processor
Takahiro Ito @cpu_labs
****************************************/
`default_nettype none
`include "core.h"
module execute_load_store(
//Prev
input wire [4:0] iCMD,
input wire iLOADSTORE_MODE, //0:SYS_LDST | 1:LDST
input wire [31:0] iSOURCE0,
input wire [31:0] iSOURCE1,
input wire iADV_ACTIVE,
input wire [31:0] iADV_DATA,
input wire [31:0] iSPR,
input wire [31:0] iPC,
//Output - Writeback
output wire oOUT_SPR_VALID,
output wire [31:0] oOUT_SPR,
output wire [31:0] oOUT_DATA,
//Output - LDST Pipe
output wire oLDST_RW,
output wire [31:0] oLDST_ADDR,
output wire [31:0] oLDST_DATA,
output wire [1:0] oLDST_ORDER,
output wire [1:0] oLOAD_SHIFT,
output wire [3:0] oLOAD_MASK //2bit -> 4bit
);
function [3:0] func_bytemask;
input [1:0] func_order;
input [1:0] func_address;
begin
case(func_order)
2'h0 :
begin
if(func_address[1:0] == 2'h0)begin
func_bytemask = 4'b0001;
end
else if(func_address[1:0] == 2'h1)begin
func_bytemask = 4'b0010;
end
else if(func_address[1:0] == 2'h2)begin
func_bytemask = 4'b0100;
end
else begin
func_bytemask = 4'b1000;
end
end
2'h1 :
begin
if(func_address[1:0] == 2'h0)begin
func_bytemask = 4'b0011;
end
else if(func_address[1:0] == 2'h2)begin
func_bytemask = 4'b1100;
end
else begin
func_bytemask = 4'b0000;
end
end
2'h2 :
begin
func_bytemask = 4'b1111;
end
default:
begin
func_bytemask = 4'b0000;
end
endcase
end
endfunction
function [31:0] func_store_data8;
input [1:0] func_shift;
input [31:0] func_data;
begin
case(func_shift)
2'h0 : func_store_data8 = {24'h0, func_data[7:0]};
2'h1 : func_store_data8 = {16'h0, func_data[7:0], 8'h0};
2'h2 : func_store_data8 = {8'h0, func_data[7:0], 16'h0};
2'h3 : func_store_data8 = {func_data[7:0], 24'h0};
endcase
end
endfunction
function [31:0] func_store_data16;
input [1:0] func_shift;
input [31:0] func_data;
begin
case(func_shift)
2'h0 : func_store_data16 = {16'h0, func_data[15:0]};
2'h2 : func_store_data16 = {func_data[15:0], 16'h0};
default : func_store_data16 = 32'hxxxxxxxx;
endcase
end
endfunction
reg spr_valid;
reg [31:0] spr;
reg [31:0] data;
reg [31:0] ldst_addr;
reg [31:0] ldst_data;
reg ldst_rw;
reg [1:0] ldst_order;
reg [3:0] ldst_load_mask;
reg [1:0] ldst_load_shift;
always @* begin
if(iLOADSTORE_MODE)begin
case(iCMD)
`EXE_LDSW_LD8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, iSOURCE1[1:0]);
ldst_load_shift = iSOURCE1[1:0];
end
`EXE_LDSW_LD16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, iSOURCE1[1:0]);
ldst_load_shift = (iSOURCE1[1:0] == 2'h0)? 2'h0 : 2'h2;//2'h3 - iSOURCE1[1:0];
end
`EXE_LDSW_LD32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
`EXE_LDSW_ST8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = func_store_data8(iSOURCE1[1:0], iSOURCE0);//iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, iSOURCE1[1:0]);
ldst_load_shift = iSOURCE1[1:0];
end
`EXE_LDSW_ST16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = func_store_data16((iSOURCE1[1:0] == 2'h0)? 2'h0 : 2'h2, iSOURCE0);//iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, iSOURCE1[1:0]);
ldst_load_shift = (iSOURCE1[1:0] == 2'h0)? 2'h0 : 2'h2;
end
`EXE_LDSW_ST32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
`EXE_LDSW_PUSH:
begin
spr_valid = 1'b1;
spr = iSPR - 32'h4;
data = 32'h0;
ldst_addr = iSPR - 32'h4;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'hf;
ldst_load_shift = 2'h0;
end
`EXE_LDSW_PPUSH:
begin
spr_valid = 1'b1;
spr = iSPR - 32'h4;
data = 32'h0;
ldst_addr = iSPR - 32'h4;
ldst_data = iPC;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'hf;
ldst_load_shift = 2'h0;
end
`EXE_LDSW_POP:
begin
spr_valid = 1'b1;
spr = iSPR + 32'h4;
data = 32'h0;
ldst_addr = iSPR;
ldst_data = 32'h0;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = 4'hf;
ldst_load_shift = 2'h0;
end
`EXE_LDSW_LDD8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + iADV_DATA;
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, (iSOURCE1[1:0] + iADV_DATA[1:0]));
ldst_load_shift = iSOURCE1[1:0] + iADV_DATA[1:0];
end
`EXE_LDSW_LDD16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 1'b0};
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0}));
ldst_load_shift = (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0} == 2'h0)? 2'h0 : 2'h2;//2'h3 - iSOURCE1[1:0];
end
`EXE_LDSW_LDD32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 2'b00};
ldst_data = iSOURCE0;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
`EXE_LDSW_STD8:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + iADV_DATA;
ldst_data = func_store_data8(iSOURCE1[1:0] + iADV_DATA[1:0], iSOURCE0);//iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h0;
ldst_load_mask = func_bytemask(2'h0, (iSOURCE1[1:0] + iADV_DATA[1:0]));
ldst_load_shift = iSOURCE1[1:0] + iADV_DATA[1:0];
end
`EXE_LDSW_STD16:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 1'b0};
ldst_data = func_store_data16((iSOURCE1[1:0] + {iADV_DATA[0], 1'b0} == 2'h0)? 2'h0 : 2'h2, iSOURCE0);//iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h1;
ldst_load_mask = func_bytemask(2'h1, (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0}));
ldst_load_shift = (iSOURCE1[1:0] + {iADV_DATA[0], 1'b0} == 2'h0)? 2'h0 : 2'h2;
end
`EXE_LDSW_STD32:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1 + {iADV_DATA, 2'b00};
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = func_bytemask(2'h2, iSOURCE1[1:0]);
ldst_load_shift = 2'h0;
end
default:
begin
spr_valid = 1'b0;
spr = iSPR;
data = 32'h0;
ldst_addr = iSOURCE1;
ldst_data = 32'h0;
ldst_rw = 1'b0;
ldst_order = 2'h0;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
endcase
end
//Sys Load / Store
else begin
case(iCMD)
`EXE_SYS_LDST_READ_SPR:
begin
spr_valid = 1'b1;
spr = iSPR;
data = iSPR;
ldst_addr = iSOURCE1;
ldst_data = iSPR;
ldst_rw = 1'b0;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
`EXE_SYS_LDST_WRITE_SPR:
begin
spr_valid = 1'b1;
spr = iSOURCE0;
data = 32'h0;
ldst_addr = iSOURCE0;
ldst_data = iSOURCE0;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
//EXE_SYS_LDST_ADD_SPR
default:
begin
spr_valid = 1'b1;
spr = iSOURCE0 + iSOURCE1;
data = 32'h0;
ldst_addr = iSOURCE0;
ldst_data = iSOURCE0 + iSOURCE1;
ldst_rw = 1'b1;
ldst_order = 2'h2;
ldst_load_mask = 4'h0;
ldst_load_shift = 2'h0;
end
endcase
end
end
assign oOUT_SPR_VALID = spr_valid;
assign oOUT_SPR = spr;
assign oOUT_DATA = data;
//Output - LDST Pipe
assign oLDST_RW = ldst_rw;
assign oLDST_ADDR = ldst_addr;
assign oLDST_DATA = ldst_data;
assign oLDST_ORDER = ldst_order;
assign oLOAD_SHIFT = ldst_load_shift;
assign oLOAD_MASK = ldst_load_mask;
endmodule
`default_nettype wire
|
`timescale 1ns / 100ps
/*
* The GPIA_BYTE module describes an 8-bit collection of GPIA_BITs. This
* octet of bits allows the following operations:
*
* - Set all eight bits to an arbitrary state in a single cycle,
* - Ensure an arbitrary set of bits are set true in a single cycle,
* - Ensure an arbitrary set of bits are cleared false in a single cycle,
* and finally,
* - Toggle an arbitrary set of bits truth value in a single cycle.
*/
module GPIA_BYTE(
input clk_i,
input res_i,
input [1:0] mode_i,
input [7:0] d_i,
input stb_i,
output [7:0] q_o
);
GPIA_BIT bit0(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[0]),
.stb_i(stb_i),
.q_o(q_o[0])
);
GPIA_BIT bit1(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[1]),
.stb_i(stb_i),
.q_o(q_o[1])
);
GPIA_BIT bit2(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[2]),
.stb_i(stb_i),
.q_o(q_o[2])
);
GPIA_BIT bit3(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[3]),
.stb_i(stb_i),
.q_o(q_o[3])
);
GPIA_BIT bit4(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[4]),
.stb_i(stb_i),
.q_o(q_o[4])
);
GPIA_BIT bit5(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[5]),
.stb_i(stb_i),
.q_o(q_o[5])
);
GPIA_BIT bit6(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[6]),
.stb_i(stb_i),
.q_o(q_o[6])
);
GPIA_BIT bit7(
.clk_i(clk_i),
.res_i(res_i),
.mode_i(mode_i),
.d_i(d_i[7]),
.stb_i(stb_i),
.q_o(q_o[7])
);
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230 10036
`timescale 1 ps / 1 ps
module alt_mem_ddrx_wdata_path
# (
// module parameter port list
parameter
CFG_LOCAL_DATA_WIDTH = 16,
CFG_MEM_IF_DQ_WIDTH = 8,
CFG_MEM_IF_DQS_WIDTH = 1,
CFG_INT_SIZE_WIDTH = 5,
CFG_DATA_ID_WIDTH = 4,
CFG_DRAM_WLAT_GROUP = 1,
CFG_LOCAL_WLAT_GROUP = 1,
CFG_TBP_NUM = 8,
CFG_BUFFER_ADDR_WIDTH = 10,
CFG_DWIDTH_RATIO = 2,
CFG_ECC_MULTIPLES = 1,
CFG_WDATA_REG = 0,
CFG_PARTIAL_BE_PER_WORD_ENABLE = 1,
CFG_ECC_CODE_WIDTH = 8,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ENABLE_ECC = 1,
CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1,
CFG_PORT_WIDTH_ENABLE_NO_DM = 1,
CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES = 1,
CFG_PORT_WIDTH_INTERFACE_WIDTH = 8,
CFG_ECC_BE_ALLLOW_RMW = 0
)
(
// port list
ctl_clk,
ctl_reset_n,
// configuration signals
cfg_burst_length,
cfg_enable_ecc,
cfg_enable_auto_corr,
cfg_enable_no_dm,
cfg_enable_ecc_code_overwrites,
cfg_interface_width,
// command generator & TBP command load interface / cmd update interface
wdatap_free_id_valid,
wdatap_free_id_dataid,
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
tbp_load_index,
proc_size,
// input interface data channel / buffer write interface
wr_data_mem_full,
write_data_en,
write_data,
byte_en,
// notify TBP interface
data_complete,
data_rmw_complete,
data_rmw_fetch,
data_partial_be,
// AFI interface / buffer read interface
doing_write,
dataid,
dataid_vector,
rdwr_data_valid,
rmw_correct,
rmw_partial,
doing_write_first,
dataid_first,
dataid_vector_first,
rdwr_data_valid_first,
rmw_correct_first,
rmw_partial_first,
doing_write_first_vector,
rdwr_data_valid_first_vector,
doing_write_last,
dataid_last,
dataid_vector_last,
rdwr_data_valid_last,
rmw_correct_last,
rmw_partial_last,
wdatap_data,
wdatap_rmw_partial_data,
wdatap_rmw_correct_data,
wdatap_rmw_partial,
wdatap_rmw_correct,
wdatap_dm,
wdatap_ecc_code,
wdatap_ecc_code_overwrite,
// RMW fifo interface, from rdatap
rmwfifo_data_valid,
rmwfifo_data,
rmwfifo_ecc_dbe,
rmwfifo_ecc_code
);
// -----------------------------
// local parameter declarations
// -----------------------------
localparam CFG_MEM_IF_DQ_PER_DQS = CFG_MEM_IF_DQ_WIDTH / CFG_MEM_IF_DQS_WIDTH;
localparam CFG_BURSTCOUNT_TRACKING_WIDTH = CFG_BUFFER_ADDR_WIDTH+1;
localparam CFG_RMWFIFO_ECC_DBE_WIDTH = CFG_ECC_MULTIPLES;
localparam CFG_RMWFIFO_ECC_CODE_WIDTH = CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_DATA_WIDTH = CFG_LOCAL_DATA_WIDTH + CFG_RMWFIFO_ECC_DBE_WIDTH + CFG_RMWFIFO_ECC_CODE_WIDTH;
localparam CFG_RMWDATA_FIFO_ADDR_WIDTH = (CFG_INT_SIZE_WIDTH == 1) ? CFG_INT_SIZE_WIDTH : CFG_INT_SIZE_WIDTH-1;
localparam CFG_LOCAL_BE_WIDTH = CFG_LOCAL_DATA_WIDTH / 8;
localparam CFG_LOCAL_DM_WIDTH = CFG_LOCAL_DATA_WIDTH / CFG_MEM_IF_DQ_PER_DQS; // to get the correct DM width based on x4 or x8 mode
localparam CFG_MMR_DRAM_DATA_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH;
localparam CFG_MMR_DRAM_DM_WIDTH = CFG_PORT_WIDTH_INTERFACE_WIDTH - 2; // Minus 3 because byte enable will be divided by 4/8
localparam integer CFG_DATAID_ARRAY_DEPTH = (2**CFG_DATA_ID_WIDTH);
localparam CFG_WR_DATA_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DATA_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
localparam CFG_WR_DM_WIDTH_PER_DQS_GROUP = CFG_LOCAL_DM_WIDTH / CFG_LOCAL_WLAT_GROUP / CFG_DWIDTH_RATIO;
// -----------------------------
// port declaration
// -----------------------------
// clock and reset
input ctl_clk;
input ctl_reset_n;
// configuration signals
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
input [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
input [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
input [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
input [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
output wdatap_free_id_valid;
output [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
// command generator & TBP command load interface / cmd update interface
input proc_busy;
input proc_load;
input proc_load_dataid;
input proc_write;
input [CFG_TBP_NUM-1:0] tbp_load_index;
input [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
output wr_data_mem_full;
input write_data_en;
input [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
input [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
output [CFG_TBP_NUM-1:0] data_complete;
output data_rmw_complete; // broadcast to TBP's
input data_rmw_fetch;
output data_partial_be;
// AFI interface / buffer read interface
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
input [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
input [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
input [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
input doing_write_first;
input [CFG_DATA_ID_WIDTH-1:0] dataid_first;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_first;
input rdwr_data_valid_first;
input rmw_correct_first;
input rmw_partial_first;
input [CFG_DRAM_WLAT_GROUP-1:0] doing_write_first_vector;
input [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid_first_vector;
input doing_write_last;
input [CFG_DATA_ID_WIDTH-1:0] dataid_last;
input [CFG_DATAID_ARRAY_DEPTH-1:0] dataid_vector_last;
input rdwr_data_valid_last;
input rmw_correct_last;
input rmw_partial_last;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
output [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
output wdatap_rmw_partial;
output wdatap_rmw_correct;
output [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
output [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
output [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
input rmwfifo_data_valid;
input [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
input [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
input [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// port type declaration
// -----------------------------
// clock and reset
wire ctl_clk;
wire ctl_reset_n;
// configuration signals
wire [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
wire [CFG_PORT_WIDTH_ENABLE_ECC - 1 : 0] cfg_enable_ecc;
wire [CFG_PORT_WIDTH_ENABLE_AUTO_CORR - 1 : 0] cfg_enable_auto_corr;
wire [CFG_PORT_WIDTH_ENABLE_NO_DM - 1 : 0] cfg_enable_no_dm;
wire [CFG_PORT_WIDTH_ENABLE_ECC_CODE_OVERWRITES - 1 : 0] cfg_enable_ecc_code_overwrites; // overwrite (and don't re-calculate) ecc code on DBE
wire [CFG_PORT_WIDTH_INTERFACE_WIDTH - 1 : 0] cfg_interface_width;
// command generator free dataid interface
wire wdatap_free_id_valid;
wire wdatap_int_free_id_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_free_id_dataid_vector;
// command generator & TBP command load interface / cmd update interface
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire [CFG_TBP_NUM-1:0] tbp_load_index;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
// input interface data channel / buffer write interface
wire wr_data_mem_full;
wire write_data_en;
wire [CFG_LOCAL_DATA_WIDTH-1:0] write_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] byte_en;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] data_complete;
wire data_rmw_complete;
wire data_partial_be;
// AFI interface / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] doing_write;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] dataid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rdwr_data_valid;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_correct;
wire [CFG_DRAM_WLAT_GROUP-1:0] rmw_partial;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_partial_data;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_rmw_correct_data;
wire wdatap_rmw_partial;
wire wdatap_rmw_correct;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dm;
reg [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] wdatap_ecc_code;
reg [CFG_ECC_MULTIPLES - 1 : 0] wdatap_ecc_code_overwrite;
// RMW fifo interface
wire rmwfifo_data_valid;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_data;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_ecc_code;
// -----------------------------
// signal declaration
// -----------------------------
// configuration
reg [CFG_MMR_DRAM_DATA_WIDTH - 1 : 0] cfg_dram_data_width;
reg [CFG_MMR_DRAM_DM_WIDTH - 1 : 0] cfg_dram_dm_width;
// command generator & TBP command load interface / cmd update interface
wire wdatap_cmdload_ready;
wire wdatap_cmdload_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_cmdload_dataid;
wire [CFG_TBP_NUM-1:0] wdatap_cmdload_tbp_index;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_cmdload_burstcount;
// input interface data channel / buffer write interface
wire wdatap_datawrite_ready;
wire wdatap_datawrite_valid;
wire wdatap_datawrite_accepted;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_datawrite_data;
wire [CFG_LOCAL_BE_WIDTH-1:0] wdatap_datawrite_be;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_datawrite_dm;
reg [CFG_LOCAL_DM_WIDTH-1:0] int_datawrite_dm;
wire wdatap_datawrite_partial_be;
wire wdatap_datawrite_allzeros_be;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_datawrite_address;
reg [CFG_ECC_MULTIPLES-1:0] int_datawrite_partial_be;
// notify TBP interface
wire [CFG_TBP_NUM-1:0] wdatap_tbp_data_ready;
wire wdatap_tbp_data_partial_be;
// AFI interface data channel / buffer read interface
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid;
wire [CFG_DRAM_WLAT_GROUP*CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector;
reg [CFG_DRAM_WLAT_GROUP*CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_r;
wire wdatap_dataread_valid_first;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_first;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_first;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_valid_first_vector;
wire wdatap_dataread_valid_last;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_dataread_dataid_last;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_dataread_dataid_vector_last;
wire [CFG_DRAM_WLAT_GROUP-1:0] wdatap_dataread_datavalid;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_partial_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_rmw_correct_data;
reg wdatap_dataread_rmw_partial;
reg wdatap_dataread_rmw_correct;
reg [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_dm;
wire [CFG_DRAM_WLAT_GROUP*CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_dataread_address;
wire wdatap_dataread_done;
wire wdatap_dataread_ready;
wire [CFG_LOCAL_DATA_WIDTH-1:0] wdatap_dataread_buffer_data;
wire [CFG_LOCAL_DM_WIDTH-1:0] wdatap_dataread_buffer_dm;
wire wdatap_free_id_get_ready;
wire wdatap_allocated_put_ready;
wire wdatap_allocated_put_valid;
wire wdatap_update_data_dataid_valid;
wire [CFG_DATA_ID_WIDTH-1:0] wdatap_update_data_dataid;
wire [CFG_DATAID_ARRAY_DEPTH-1:0] wdatap_update_data_dataid_vector;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_burstcount;
wire [CFG_BURSTCOUNT_TRACKING_WIDTH-1:0] wdatap_update_data_next_burstcount;
wire wdatap_notify_data_valid;
wire [CFG_INT_SIZE_WIDTH-1:0] wdatap_notify_data_burstcount_consumed;
// buffer read/write signals
wire wdatap_buffwrite_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffwrite_address;
wire wdatap_buffread_valid;
wire [CFG_BUFFER_ADDR_WIDTH-1:0] wdatap_buffread_address;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_input;
wire [CFG_RMWDATA_FIFO_DATA_WIDTH-1:0] rmwfifo_output;
wire rmwfifo_output_read;
wire rmwfifo_output_valid;
reg rmwfifo_output_valid_r;
wire rmwfifo_output_valid_pulse;
reg rmwfifo_output_valid_handshake;
wire [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmwfifo_output_data_r;
wire [CFG_ECC_MULTIPLES- 1 : 0] rmwfifo_output_ecc_dbe;
wire [CFG_ECC_MULTIPLES * CFG_ECC_CODE_WIDTH - 1 : 0] rmwfifo_output_ecc_code;
reg [CFG_LOCAL_DATA_WIDTH-1:0] rmw_merged_data;
reg rmw_correct_r1;
reg rmw_partial_r1;
reg rmw_correct_r2;
reg rmw_partial_r2;
wire rmwfifo_ready;
// debug signals, for assertions
wire err_rmwfifo_overflow;
// -----------------------------
// module definition
// -----------------------------
// renaming port names to more meaningfull internal names
assign wdatap_cmdload_valid = ~proc_busy & proc_load & proc_write & proc_load_dataid;
assign wdatap_cmdload_tbp_index = tbp_load_index;
assign wdatap_cmdload_burstcount = proc_size;
assign wdatap_cmdload_dataid = wdatap_free_id_dataid;
assign wr_data_mem_full = ~wdatap_datawrite_ready;
assign wdatap_datawrite_valid = write_data_en;
assign wdatap_datawrite_data = write_data;
assign wdatap_datawrite_be = byte_en; // we need to replicate
assign data_complete = wdatap_tbp_data_ready;
assign data_rmw_complete = rmwfifo_output_valid_pulse | rmwfifo_output_valid_handshake; // broadcast to all TBP's
assign data_partial_be = wdatap_tbp_data_partial_be;
assign wdatap_dataread_valid = doing_write & rdwr_data_valid & ~rmw_correct;
assign wdatap_dataread_dataid = dataid;
assign wdatap_dataread_dataid_vector = dataid_vector;
assign wdatap_dataread_valid_first = doing_write_first & rdwr_data_valid_first & ~rmw_correct_first;
assign wdatap_dataread_dataid_first = dataid_first;
assign wdatap_dataread_dataid_vector_first = dataid_vector_first;
assign wdatap_dataread_valid_first_vector = rdwr_data_valid_first_vector;
assign wdatap_dataread_valid_last = doing_write_last & rdwr_data_valid_last & ~rmw_correct_last ;
assign wdatap_dataread_dataid_last = dataid_last;
assign wdatap_dataread_dataid_vector_last = dataid_vector_last;
assign wdatap_data = wdatap_dataread_data;
assign wdatap_rmw_partial_data = wdatap_dataread_rmw_partial_data;
assign wdatap_rmw_correct_data = wdatap_dataread_rmw_correct_data;
assign wdatap_rmw_partial = wdatap_dataread_rmw_partial;
assign wdatap_rmw_correct = wdatap_dataread_rmw_correct;
assign wdatap_dm = wdatap_dataread_dm;
// internal signals
// flow control between free list & allocated list
assign wdatap_free_id_get_ready = wdatap_cmdload_valid;
assign wdatap_allocated_put_valid= wdatap_free_id_get_ready & wdatap_free_id_valid;
assign wdatap_free_id_valid = wdatap_int_free_id_valid & wdatap_cmdload_ready;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_data_width <= 0;
end
else
begin
if (cfg_enable_ecc)
begin
cfg_dram_data_width <= cfg_interface_width - CFG_ECC_CODE_WIDTH; // SPR:362973
end
else
begin
cfg_dram_data_width <= cfg_interface_width;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
cfg_dram_dm_width <= 0;
end
else
begin
cfg_dram_dm_width <= cfg_dram_data_width / CFG_MEM_IF_DQ_PER_DQS;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
//reset state ...
wdatap_dataread_dataid_r <= 0;
end
else
begin
//active state ...
wdatap_dataread_dataid_r <= wdatap_dataread_dataid;
end
end
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("INCR"),
.CTL_LIST_INIT_VALID ("VALID")
)
wdatap_list_freeid_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_free_id_get_ready),
.list_get_entry_valid (wdatap_int_free_id_valid),
.list_get_entry_id (wdatap_free_id_dataid),
.list_get_entry_id_vector (wdatap_free_id_dataid_vector),
// wdatap_dataread_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_dataread_ready),
.list_put_entry_valid (wdatap_dataread_done),
.list_put_entry_id (wdatap_dataread_dataid_r)
);
alt_mem_ddrx_list
#(
.CTL_LIST_WIDTH (CFG_DATA_ID_WIDTH),
.CTL_LIST_DEPTH (CFG_DATAID_ARRAY_DEPTH),
.CTL_LIST_INIT_VALUE_TYPE ("ZERO"),
.CTL_LIST_INIT_VALID ("INVALID")
)
wdatap_list_allocated_id_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.list_get_entry_ready (wdatap_notify_data_valid),
.list_get_entry_valid (wdatap_update_data_dataid_valid),
.list_get_entry_id (wdatap_update_data_dataid),
.list_get_entry_id_vector (wdatap_update_data_dataid_vector),
// wdatap_allocated_put_ready can be ignored, list entry availability is guaranteed
.list_put_entry_ready (wdatap_allocated_put_ready),
.list_put_entry_valid (wdatap_allocated_put_valid),
.list_put_entry_id (wdatap_free_id_dataid)
);
alt_mem_ddrx_burst_tracking
# (
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH)
)
wdatap_burst_tracking_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// data burst interface
.burst_ready (wdatap_datawrite_ready),
.burst_valid (wdatap_datawrite_valid),
// burstcount counter sent to data_id_manager
.burst_pending_burstcount (wdatap_update_data_burstcount),
.burst_next_pending_burstcount (wdatap_update_data_next_burstcount),
// burstcount consumed by data_id_manager
.burst_consumed_valid (wdatap_notify_data_valid),
.burst_counsumed_burstcount (wdatap_notify_data_burstcount_consumed)
);
alt_mem_ddrx_dataid_manager
# (
.CFG_DATA_ID_WIDTH (CFG_DATA_ID_WIDTH),
.CFG_LOCAL_WLAT_GROUP (CFG_LOCAL_WLAT_GROUP),
.CFG_DRAM_WLAT_GROUP (CFG_DRAM_WLAT_GROUP),
.CFG_BUFFER_ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.CFG_INT_SIZE_WIDTH (CFG_INT_SIZE_WIDTH),
.CFG_TBP_NUM (CFG_TBP_NUM),
.CFG_BURSTCOUNT_TRACKING_WIDTH (CFG_BURSTCOUNT_TRACKING_WIDTH),
.CFG_PORT_WIDTH_BURST_LENGTH (CFG_PORT_WIDTH_BURST_LENGTH),
.CFG_DWIDTH_RATIO (CFG_DWIDTH_RATIO),
.CFG_ECC_BE_ALLLOW_RMW (CFG_ECC_BE_ALLLOW_RMW)
)
wdatap_dataid_manager_inst
(
// clock & reset
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// configuration signals
.cfg_burst_length (cfg_burst_length),
.cfg_enable_ecc (cfg_enable_ecc),
.cfg_enable_auto_corr (cfg_enable_auto_corr),
.cfg_enable_no_dm (cfg_enable_no_dm),
// update cmd interface
.update_cmd_if_ready (wdatap_cmdload_ready),
.update_cmd_if_valid (wdatap_cmdload_valid),
.update_cmd_if_data_id (wdatap_cmdload_dataid),
.update_cmd_if_burstcount (wdatap_cmdload_burstcount),
.update_cmd_if_tbp_id (wdatap_cmdload_tbp_index),
// update data interface
.update_data_if_valid (wdatap_update_data_dataid_valid),
.update_data_if_data_id (wdatap_update_data_dataid),
.update_data_if_data_id_vector (wdatap_update_data_dataid_vector),
.update_data_if_burstcount (wdatap_update_data_burstcount),
.update_data_if_next_burstcount (wdatap_update_data_next_burstcount),
// notify data interface
.notify_data_if_valid (wdatap_notify_data_valid),
.notify_data_if_burstcount (wdatap_notify_data_burstcount_consumed),
// notify tbp interface
.notify_tbp_data_ready (wdatap_tbp_data_ready),
.notify_tbp_data_partial_be (wdatap_tbp_data_partial_be),
// buffer write address generate interface
.write_data_if_ready (wdatap_datawrite_ready),
.write_data_if_valid (wdatap_datawrite_valid),
.write_data_if_accepted (wdatap_datawrite_accepted),
.write_data_if_address (wdatap_datawrite_address),
.write_data_if_partial_be (wdatap_datawrite_partial_be),
.write_data_if_allzeros_be (wdatap_datawrite_allzeros_be),
// read data interface
.read_data_if_valid (wdatap_dataread_valid),
.read_data_if_data_id (wdatap_dataread_dataid),
.read_data_if_data_id_vector (wdatap_dataread_dataid_vector),
.read_data_if_valid_first (wdatap_dataread_valid_first),
.read_data_if_data_id_first (wdatap_dataread_dataid_first),
.read_data_if_data_id_vector_first (wdatap_dataread_dataid_vector_first),
.read_data_if_valid_first_vector (wdatap_dataread_valid_first_vector),
.read_data_if_valid_last (wdatap_dataread_valid_last),
.read_data_if_data_id_last (wdatap_dataread_dataid_last),
.read_data_if_data_id_vector_last (wdatap_dataread_dataid_vector_last),
.read_data_if_address (wdatap_dataread_address),
.read_data_if_datavalid (wdatap_dataread_datavalid),
.read_data_if_done (wdatap_dataread_done) // use with wdatap_dataread_dataid_r
);
genvar wdatap_m;
genvar wdatap_n;
generate
for (wdatap_m = 0;wdatap_m < CFG_DWIDTH_RATIO;wdatap_m = wdatap_m + 1)
begin : wdata_buffer_per_dwidth_ratio
for (wdatap_n = 0;wdatap_n < CFG_LOCAL_WLAT_GROUP;wdatap_n = wdatap_n + 1)
begin : wdata_buffer_per_dqs_group
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DATA_WIDTH_PER_DQS_GROUP),
.REGISTER_OUTPUT (CFG_WDATA_REG)
)
wdatap_buffer_data_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (wdatap_datawrite_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_data [(wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DATA_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DATA_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DATA_WIDTH_PER_DQS_GROUP)])
);
alt_mem_ddrx_buffer
# (
.ADDR_WIDTH (CFG_BUFFER_ADDR_WIDTH),
.DATA_WIDTH (CFG_WR_DM_WIDTH_PER_DQS_GROUP),
.REGISTER_OUTPUT (CFG_WDATA_REG)
)
wdatap_buffer_be_inst
(
// port list
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
// write interface
.write_valid (wdatap_datawrite_accepted),
.write_address (wdatap_datawrite_address),
.write_data (int_datawrite_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)]),
// read interface
.read_valid (wdatap_dataread_valid [wdatap_n]),
.read_address (wdatap_dataread_address [(wdatap_n + 1) * CFG_BUFFER_ADDR_WIDTH - 1 : wdatap_n * CFG_BUFFER_ADDR_WIDTH]),
.read_data (wdatap_dataread_buffer_dm [(wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + ((wdatap_n + 1) * CFG_WR_DM_WIDTH_PER_DQS_GROUP) - 1 : (wdatap_m * CFG_WR_DM_WIDTH_PER_DQS_GROUP * CFG_LOCAL_WLAT_GROUP) + (wdatap_n * CFG_WR_DM_WIDTH_PER_DQS_GROUP)])
);
end
end
endgenerate
//
// byteenables analysis & generation
//
// - generate partial byteenable signal, per DQ word or per local word
// - set unused interface width byteenables to either 0 or 1
//
genvar wdatap_j, wdatap_k;
generate
if (CFG_ECC_BE_ALLLOW_RMW) begin
reg [CFG_ECC_MULTIPLES-1:0] be_all_ones;
reg [CFG_ECC_MULTIPLES-1:0] be_all_zeros;
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_be = |int_datawrite_partial_be;
assign wdatap_datawrite_allzeros_be = (!cfg_enable_no_dm & &be_all_zeros) ? 1'b1 : 1'b0;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
always @ (*)
begin
be_all_ones[wdatap_j] = &int_datawrite_dm_unused1[wdatap_j];
be_all_zeros[wdatap_j] = ~(|int_datawrite_dm_unused0[wdatap_j]);
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_be[wdatap_j] = ~be_all_ones[wdatap_j];
end
else
begin
int_datawrite_partial_be[wdatap_j] = ~(be_all_ones[wdatap_j] | be_all_zeros[wdatap_j]);
end
if (cfg_enable_ecc)
begin
if (be_all_zeros[wdatap_j])
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
end
else begin
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] wdatap_datawrite_dm_widthratio [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused1 [CFG_ECC_MULTIPLES-1:0];
reg [(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1:0] int_datawrite_dm_unused0 [CFG_ECC_MULTIPLES-1:0];
assign wdatap_datawrite_partial_be = |int_datawrite_partial_be;
assign wdatap_datawrite_allzeros_be = 0;
for (wdatap_k = 0;wdatap_k < CFG_LOCAL_DM_WIDTH;wdatap_k = wdatap_k + 1)
begin : local_dm
always @ (*)
begin
if (CFG_MEM_IF_DQ_PER_DQS == 4)
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k / 2];
end
else
begin
wdatap_datawrite_dm [wdatap_k] = wdatap_datawrite_be [wdatap_k];
end
end
end
for (wdatap_j = 0; wdatap_j < CFG_ECC_MULTIPLES; wdatap_j = wdatap_j + 1)
begin : gen_partial_be
wire be_all_ones = &int_datawrite_dm_unused1[wdatap_j];
wire be_all_zeros = ~(|int_datawrite_dm_unused0[wdatap_j]);
always @ (*)
begin
wdatap_datawrite_dm_widthratio [wdatap_j] = wdatap_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))];
end
for (wdatap_k = 0; wdatap_k < (CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES); wdatap_k = wdatap_k + 1'b1)
begin : gen_dm_unused_bits
always @ (*)
begin
if (wdatap_k < cfg_dram_dm_width)
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = wdatap_datawrite_dm_widthratio [wdatap_j][wdatap_k];
end
else
begin
int_datawrite_dm_unused1 [wdatap_j] [wdatap_k] = {1'b1};
int_datawrite_dm_unused0 [wdatap_j] [wdatap_k] = {1'b0};
end
end
end
always @ (*)
begin
// partial be calculated for every dq width if byteenables, not partial be if either all ones, or all zeros
if (cfg_enable_no_dm)
begin
int_datawrite_partial_be[wdatap_j] = ~be_all_ones;
end
else
begin
int_datawrite_partial_be[wdatap_j] = ~( be_all_ones | be_all_zeros );
end
if (cfg_enable_ecc)
begin
if (be_all_zeros)
begin
// no ECC code will be written
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
else
begin
// higher unused be bit will be used for ECC word
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused1 [wdatap_j];
end
end
else
begin
int_datawrite_dm [(wdatap_j+1)*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES)-1 : (wdatap_j*(CFG_LOCAL_DM_WIDTH/CFG_ECC_MULTIPLES))] = int_datawrite_dm_unused0 [wdatap_j];
end
end
end
end
endgenerate
//
// rmw data fifo
//
// assume rmw data for 2 commands doesn't came back to back, causing rmwfifo_output_valid_pulse not to be generated for 2nd commands data
assign rmwfifo_output_valid_pulse = rmwfifo_output_valid & ~rmwfifo_output_valid_r;
// New data_rmw_complete logic, TBP/cmd_gen will have to assert data_rmw_fetch before data_rmw_complete de-asserts
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmwfifo_output_valid_handshake <= 1'b0;
end
else
begin
if (data_rmw_fetch)
begin
rmwfifo_output_valid_handshake <= 1'b0;
end
else if (rmwfifo_output_valid_pulse)
begin
rmwfifo_output_valid_handshake <= 1'b1;
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (~ctl_reset_n)
begin
rmwfifo_output_valid_r <= 1'b0;
rmw_correct_r1 <= 1'b0;
rmw_partial_r1 <= 1'b0;
rmw_correct_r2 <= 1'b0;
rmw_partial_r2 <= 1'b0;
end
else
begin
rmwfifo_output_valid_r <= rmwfifo_output_valid;
rmw_correct_r1 <= rmw_correct;
rmw_partial_r1 <= rmw_partial;
rmw_correct_r2 <= rmw_correct_r1;
rmw_partial_r2 <= rmw_partial_r1;
end
end
// RMW FIFO output register
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
rmwfifo_output_data_r <= 0;
end
else
begin
rmwfifo_output_data_r <= rmwfifo_output_data;
end
end
assign rmwfifo_input = {rmwfifo_ecc_code, rmwfifo_ecc_dbe, rmwfifo_data};
assign {rmwfifo_output_ecc_code, rmwfifo_output_ecc_dbe, rmwfifo_output_data} = rmwfifo_output;
assign rmwfifo_output_read = rmw_correct_r1 | (&wdatap_dataread_datavalid & rmw_partial_r1); // wdatap_dataread_datavalid must be all high together in ECC case (afi_wlat same for all DQS group), limitation in 11.0sp1
assign err_rmwfifo_overflow = rmwfifo_data_valid & ~rmwfifo_ready;
alt_mem_ddrx_fifo
#(
.CTL_FIFO_DATA_WIDTH (CFG_RMWDATA_FIFO_DATA_WIDTH),
.CTL_FIFO_ADDR_WIDTH (CFG_RMWDATA_FIFO_ADDR_WIDTH)
)
rmw_data_fifo_inst
(
.ctl_clk (ctl_clk),
.ctl_reset_n (ctl_reset_n),
.get_ready (rmwfifo_output_read),
.get_valid (rmwfifo_output_valid),
.get_data (rmwfifo_output),
.put_ready (rmwfifo_ready),
.put_valid (rmwfifo_data_valid),
.put_data (rmwfifo_input)
);
//
// rmw data merge block
//
genvar wdatap_i;
generate
for (wdatap_i = 0; wdatap_i < ((CFG_LOCAL_DM_WIDTH)); wdatap_i = wdatap_i + 1)
begin : gen_rmw_data_merge
always @ (*)
begin
if (wdatap_dataread_buffer_dm[wdatap_i])
begin
// data from wdatap buffer
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = wdatap_dataread_buffer_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
// data from rmwfifo
if (CFG_WDATA_REG)
begin
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data_r [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
else
begin
rmw_merged_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ] = rmwfifo_output_data [ ((wdatap_i + 1) * CFG_MEM_IF_DQ_PER_DQS) - 1 : (wdatap_i * CFG_MEM_IF_DQ_PER_DQS) ];
end
end
end
end
endgenerate
//
// wdata output mux
//
// drives wdatap_data & wdatap_be from either of
// if cfg_enabled etc ?
// - wdatap buffer (~rmw_correct & ~rmw_partial)
// - rmwfifo (rmw_correct)
// - merged wdatap buffer & rmwfifo (rmw_partial)
//
generate
if (CFG_WDATA_REG)
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data_r;
wdatap_dataread_rmw_partial = rmw_partial_r2;
wdatap_dataread_rmw_correct = rmw_correct_r2;
if (rmw_correct_r2 | rmw_partial_r2)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
wdatap_ecc_code <= 0;
wdatap_ecc_code_overwrite <= 0;
end
else
begin
wdatap_ecc_code <= rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r1)
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r1)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite <= rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite <= {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
end
else
begin
always @ (*)
begin
if (cfg_enable_ecc | cfg_enable_no_dm)
begin
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = rmw_merged_data;
wdatap_dataread_rmw_correct_data = rmwfifo_output_data;
wdatap_dataread_rmw_partial = rmw_partial_r1;
wdatap_dataread_rmw_correct = rmw_correct_r1;
if (rmw_correct_r1 | rmw_partial_r1)
begin
wdatap_dataread_dm = {(CFG_LOCAL_DM_WIDTH){1'b1}};
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
end
end
else
begin
wdatap_dataread_dm = wdatap_dataread_buffer_dm;
wdatap_dataread_data = wdatap_dataread_buffer_data;
wdatap_dataread_rmw_partial_data = 0;
wdatap_dataread_rmw_correct_data = 0;
wdatap_dataread_rmw_partial = 1'b0;
wdatap_dataread_rmw_correct = 1'b0;
end
end
// ecc code overwrite
// - is asserted when we don't want controller to re-calculate the ecc code
// - only allowed when we're not doing any writes in this clock
// - only allowed when rmwfifo output is valid
always @ (*)
begin
wdatap_ecc_code = rmwfifo_output_ecc_code;
if (cfg_enable_ecc_code_overwrites)
begin
if (rmw_correct_r1)
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
else if (rmw_partial_r1)
begin
if ( (|wdatap_dataread_buffer_dm) | (~rmwfifo_output_valid) )
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
else
begin
wdatap_ecc_code_overwrite = rmwfifo_output_ecc_dbe;
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
else
begin
wdatap_ecc_code_overwrite = {CFG_ECC_MULTIPLES{1'b0}};
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_TB_V
`define SKY130_FD_SC_LP__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_lp__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_TB_V
|
`timescale 1ns / 1ps
/* verilator lint_off STMTDLY */
module jt12_test;
reg rst;
reg clk;
wire s1_enters, s2_enters, s3_enters, s4_enters;
`include "../common/dump.vh"
initial begin
clk = 0;
forever #10 clk=~clk;
end
reg test_eg;
// envelope configuration
wire [4:0] keycode_III = 5'd10;
reg [4:0] arate; // attack rate
reg [4:0] rate1; // decay rate
reg [4:0] rate2; // sustain rate
wire [3:0] rrate = 4'hf; // release rate
wire [3:0] d1l = 4'd8; // sustain level
wire [1:0] ks_III = 2'd0; // key scale
// SSG operation
reg [3:0] ssg_eg_II;
// envelope operation
reg keyon;
reg keyoff;
// envelope number
wire [6:0] am = 7'd0;
reg [6:0] tl_VII=7'd0;
wire [1:0] ams_VII = 2'd0;
wire amsen_VII = 1'b0;
initial begin
rst = 0;
rate1 = 5'd29;
rate2 = 5'd27;
#5 rst = 1;
#20 rst = 0;
#(1*1000*1000) $finish;
end
integer cycles;
reg [4:0] cnt24;
wire zero = cnt24==5'd0;
reg keyon_done;
always @(posedge clk)
if( rst ) begin
keyon <= 1'b1;
keyoff <= 1'b0;
cycles <= 0;
keyon_done <= 1'b0;
ssg_eg_II <= 4'b0;
end else begin
cycles <= cycles + 1;
if( cycles==100 ) keyon<=1'b0;
if( cycles==110 ) keyoff<=1'b1;
if( cycles==134 ) keyoff<=1'b0;
if( cycles > 10000 ) begin
keyon <= cycles==10559;
ssg_eg_II <= 4'b1110;
end
end
always @(posedge clk)
if( rst ) begin
cnt24 <= 0;
end else begin
if( cnt24 == 5'd23 )
cnt24 <= 5'd0;
else
cnt24 <= cnt24 + 1;
end
always @(*)
if( cycles < 104 )
arate = 5'h1f;
else
arate = cnt24==5'd0 ? 5'd31 : 5'd0;
wire [9:0] eg_IX;
wire pg_rst_III;
jt12_eg uut(
// .test_eg(test_eg),
.rst (rst),
.clk (clk),
.clk_en (1'b1),
.zero (zero),
.eg_stop(1'b0),
// envelope configuration
.keycode_III(keycode_III),
.arate_II (arate), // attack rate
.rate1_II (rate1), // decay rate
.rate2_II (rate2), // sustain rate
.rrate_II (rrate), // release rate
.d1l_I (d1l), // sustain level
.ks_III (ks_III), // key scale
// SSG operation
.ssg_en_II ( cnt24==5'd0 ? ssg_eg_II[3] : 1'h0 ),
.ssg_eg_II ( cnt24==5'd1 ? ssg_eg_II[2:0] : 3'h0 ),
// envelope operation
.keyon_II (keyon),
// envelope number
.am (am),
.tl_VII (tl_VII),
.ams_VII (ams_VII),
.amsen_VII (amsen_VII),
.eg_IX (eg_IX),
.pg_rst_III (pg_rst_III)
);
wire [9:0] eg0;
wire [9:0] rest_and, rest_or;
/* verilator lint_off PINMISSING */
sep24 #(.width(10),.pos0(8)) sep(
.clk ( clk ),
.clk_en ( 1'b1 ),
.mixed ( eg_IX ),
.cnt ( cnt24 ),
.ch0s1 ( eg0 ),
.alland ( rest_and ),
.allor ( rest_or ),
.mask ( ~24'b1 )
);
/* verilator lint_on PINMISSING */
`ifdef NCVERILOG
initial $shm_probe(jt12_test,"AS");
`endif
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 2016/06/06 20:44:21
// Design Name:
// Module Name: Mealy_FSM_ROM_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mealy_FSM_ROM_tb(
);
reg clk, reset, x;
wire [2:0] count;
integer i;
Mealy_FSM_ROM DUT (clk, reset, x, count);
initial begin
#330 $finish;
end
initial begin
clk = 0;
for (i = 0; i < 66;i = i + 1) begin
#5 clk = ~clk;
end
end
initial begin
reset = 1;
#20 reset = 0;
#170 reset = 1;
#10 reset = 0;
end
initial begin
x = 0;
#40 x = 1;
#20 x = 0;
#60 x = 1;
#40 x = 0;
#20 x = 1;
#30 x = 0;
#30 x = 1;
end
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core
calculus embodying the key concept of _functional abstraction_,
which shows up in pretty much every real-world programming
language in some form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous chapter
when formalizing this calculus (syntax, small-step semantics,
typing rules) and its main properties (progress and preservation).
The new technical challenges arise from the mechanisms of
_variable binding_ and _substitution_. It will take some work to
deal with these. *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import Strings.String.
From PLF Require Import Maps.
From PLF Require Import Smallstep.
(* ################################################################# *)
(** * Overview *)
(** The STLC is built on some collection of _base types_:
booleans, numbers, strings, etc. The exact choice of base types
doesn't matter much -- the construction of the language and its
theoretical properties work out the same no matter what we
choose -- so for the sake of brevity let's take just [Bool] for
the moment. At the end of the chapter we'll see how to add more
base types, and in later chapters we'll enrich the pure STLC with
other useful constructs like pairs, records, subtyping, and
mutable state.
Starting from boolean constants and conditionals, we add three
things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out first in informal BNF notation -- we'll
formalize it below).
t ::= x (variable)
| \x:T,t (abstraction)
| t t (application)
| true (constant true)
| false (constant false)
| if t then t else t (conditional)
*)
(** The [\] symbol in a function abstraction [\x:T,t] is generally
written as a Greek letter "lambda" (hence the name of the
calculus). The variable [x] is called the _parameter_ to the
function; the term [t] is its _body_. The annotation [:T]
specifies the type of arguments that the function can be applied
to. *)
(** If you've seen lambda-calculus notation before, you might be
wondering why abstraction is written here as [\x:T,t] instead of
the usual "[\x:T.t]". The reason is that some front ends for
interacting with Coq use period to separate a file into
"sentences" to be passed separately to the Coq top level. *)
(** Some examples:
- [\x:Bool, x]
The identity function for booleans.
- [(\x:Bool, x) true]
The identity function for booleans, applied to the boolean [true].
- [\x:Bool, if x then false else true]
The boolean "not" function.
- [\x:Bool, true]
The constant function that takes every (boolean) argument to
[true].
- [\x:Bool, \y:Bool, x]
A two-argument function that takes two booleans and returns
the first one. (As in Coq, a two-argument function is really
a one-argument function whose body is also a one-argument
function.)
- [(\x:Bool, \y:Bool, x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
As in Coq, application associates to the left -- i.e., this
expression is parsed as [((\x:Bool, \y:Bool, x) false) true].
- [\f:Bool->Bool, f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(\f:Bool->Bool, f (f true)) (\x:Bool, false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
The STLC doesn't provide any primitive syntax for defining _named_
functions -- all functions are "anonymous." We'll see in chapter
[MoreStlc] that it is easy to add named functions to what we've
got -- indeed, the fundamental naming and binding mechanisms are
exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions.
T ::= Bool
| T -> T
For example:
- [\x:Bool, false] has type [Bool->Bool]
- [\x:Bool, x] has type [Bool->Bool]
- [(\x:Bool, x) true] has type [Bool]
- [\x:Bool, \y:Bool, x] has type [Bool->Bool->Bool]
(i.e., [Bool -> (Bool->Bool)])
- [(\x:Bool, \y:Bool, x) false] has type [Bool->Bool]
- [(\x:Bool, \y:Bool, x) false true] has type [Bool] *)
(* ################################################################# *)
(** * Syntax *)
(** We next formalize the syntax of the STLC. *)
Module STLC.
(* ================================================================= *)
(** ** Types *)
Inductive ty : Type :=
| Ty_Bool : ty
| Ty_Arrow : ty -> ty -> ty.
(* ================================================================= *)
(** ** Terms *)
Inductive tm : Type :=
| tm_var : string -> tm
| tm_app : tm -> tm -> tm
| tm_abs : string -> ty -> tm -> tm
| tm_true : tm
| tm_false : tm
| tm_if : tm -> tm -> tm -> tm.
Declare Custom Entry stlc.
Notation "<{ e }>" := e (e custom stlc at level 99).
Notation "( x )" := x (in custom stlc, x at level 99).
Notation "x" := x (in custom stlc at level 0, x constr at level 0).
Notation "S -> T" := (Ty_Arrow S T) (in custom stlc at level 50, right associativity).
Notation "x y" := (tm_app x y) (in custom stlc at level 1, left associativity).
Notation "\ x : t , y" :=
(tm_abs x t y) (in custom stlc at level 90, x at level 99,
t custom stlc at level 99,
y custom stlc at level 99,
left associativity).
Coercion tm_var : string >-> tm.
Notation "'Bool'" := Ty_Bool (in custom stlc at level 0).
Notation "'if' x 'then' y 'else' z" :=
(tm_if x y z) (in custom stlc at level 89,
x custom stlc at level 99,
y custom stlc at level 99,
z custom stlc at level 99,
left associativity).
Notation "'true'" := true (at level 1).
Notation "'true'" := tm_true (in custom stlc at level 0).
Notation "'false'" := false (at level 1).
Notation "'false'" := tm_false (in custom stlc at level 0).
(** Some more notation magic to set up the concrete syntax, as we did
in the [Imp] chapter... *)
Definition x : string := "x".
Definition y : string := "y".
Definition z : string := "z".
Hint Unfold x : core.
Hint Unfold y : core.
Hint Unfold z : core.
(** Note that an abstraction [\x:T,t] (formally, [tm_abs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use type inference to fill in missing annotations. We're
not considering type inference here. *)
(** Some examples... *)
Notation idB :=
<{\x:Bool, x}>.
Notation idBB :=
<{\x:Bool->Bool, x}>.
Notation idBBBB :=
<{\x:((Bool->Bool)->(Bool->Bool)), x}>.
Notation k := <{\x:Bool, \y:Bool, x}>.
Notation notB := <{\x:Bool, if x then false else true}>.
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ################################################################# *)
(** * Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin,
as always, by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ================================================================= *)
(** ** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if] expression
is never a value. *)
(** Second, an application is not a value: it represents a function
being invoked on some argument, which clearly still has work left
to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [\x:T, t] is a value only when [t] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [\x:T, t] is always a value, no matter
whether [t] is one or not -- in other words, we can say that
reduction stops at abstractions.
Our usual way of evaluating expressions in Gallina makes the first
choice -- for example,
Compute (fun x:bool => 3 + 4)
yields:
fun x:bool => 7
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T2 t1,
value <{\x:T2, t1}>
| v_true :
value <{true}>
| v_false :
value <{false}>.
Hint Constructors value : core.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete program" must not refer to any undefined
variables. We'll see shortly how to define the _free_ variables
in a STLC term. A complete program is _closed_ -- that is, it
contains no free variables.
(Conversely, a term with free variables is often called an _open
term_.) *)
(** Having made the choice not to reduce under abstractions, we don't
need to worry about whether variables are values, since we'll
always be reducing programs "from the outside in," and that means
the [step] relation will always be working with closed terms. *)
(* ================================================================= *)
(** ** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term. This
operation is used below to define the operational semantics of
function application, where we will need to substitute the
argument term for the function parameter in the function's body.
For example, we reduce
(\x:Bool, if x then true else x) false
to
if false then true else false
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given term [s]
for occurrences of some variable [x] in another term [t]. In
informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [s] for [x] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)]
yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (\y:Bool, if y then x else false)]
yields [\y:Bool, if y then true else false]
- [[x:=true] (\y:Bool, x)] yields [\y:Bool, true]
- [[x:=true] (\y:Bool, y)] yields [\y:Bool, y]
- [[x:=true] (\x:Bool, x)] yields [\x:Bool, x]
The last example is very important: substituting [x] with [true] in
[\x:Bool, x] does _not_ yield [\x:Bool, true]! The reason for
this is that the [x] in the body of [\x:Bool, x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](\x:T, t) = \x:T, t
[x:=s](\y:T, t) = \y:T, [x:=s]t if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (in custom stlc at level 20, x constr).
Fixpoint subst (x : string) (s : tm) (t : tm) : tm :=
match t with
| tm_var y =>
if eqb_string x y then s else t
| <{\y:T, t1}> =>
if eqb_string x y then t else <{\y:T, [x:=s] t1}>
| <{t1 t2}> =>
<{([x:=s] t1) ([x:=s] t2)}>
| <{true}> =>
<{true}>
| <{false}> =>
<{false}>
| <{if t1 then t2 else t3}> =>
<{if ([x:=s] t1) then ([x:=s] t2) else ([x:=s] t3)}>
end
where "'[' x ':=' s ']' t" := (subst x s t) (in custom stlc).
(** Note on notations: You might be wondering why we need curly braces
around the substitution notation in the above definition, and why
do we need to redefine the substition notation in the [stlc]
custom grammar. The reason is that reserved notations in
definitions have to be defined in the general Coq grammar (and not
a custom one like [stlc]). This restriction only applies to the
[subst] definition, that is before the [where ...] part. From now
on, using the substitution notation in the [stlc] custom grammar
doesn't need any curly braces. *)
(** For example... *)
Check <{[x:=true] x}>.
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on _closed_ terms (i.e., terms like [\x:Bool, x] that include
binders for all of the variables they mention), we can sidestep this
extra complexity, but it must be dealt with when formalizing
richer languages. *)
(** For example, using the definition of substitution above to
substitute the _open_ term [s = \x:Bool, r], where [r] is a _free_
reference to some global resource, for the variable [z] in the
term [t = \r:Bool, z], where [r] is a bound variable, we would get
[\r:Bool, \x:Bool, r], where the free reference to [r] in [s] has
been "captured" by the binder at the beginning of [t].
Why would this be bad? Because it violates the principle that the
names of bound variables do not matter. For example, if we rename
the bound variable in [t], e.g., let [t' = \w:Bool, z], then
[[x:=s]t'] is [\w:Bool, \x:Bool, r], which does not behave the
same as [[x:=s]t = \r:Bool, \x:Bool, r]. That is, renaming a
bound variable changes how [t] behaves under substitution. *)
(** See, for example, [Aydemir 2008] (in Bib.v) for further discussion
of this issue. *)
(** **** Exercise: 3 stars, standard (substi_correct)
The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the construectors; your job is to fill in the rest of the
constructors and prove that the relation you've defined coincides
with the function given above. *)
(* | tm_var y => *)
(* if eqb_string x y then s else t *)
(* | <{\y:T, t1}> => *)
(* if eqb_string x y then t else <{\y:T, [x:=s] t1}> *)
(* | <{t1 t2}> => *)
(* <{([x:=s] t1) ([x:=s] t2)}> *)
(* | <{true}> => *)
(* <{true}> *)
(* | <{false}> => *)
(* <{false}> *)
(* | <{if t1 then t2 else t3}> => *)
(* <{if ([x:=s] t1) then ([x:=s] t2) else ([x:=s] t3)}> *)
(* end *)
Inductive substi (s : tm) (x : string) : tm -> tm -> Prop :=
| s_var_same : substi s x (tm_var x) s
| s_var_diff y (Hneq: x <> y) : substi s x (tm_var y) (tm_var y)
| s_app t1 t2 t1' t2'
(Hrtor: substi s x t1 t1')
(Hrand: substi s x t2 t2') :
substi s x <{t1 t2}> <{t1' t2'}>
| s_abs_bound T t : substi s x <{\x:T, t}> <{\x:T, t}>
| s_abs_free y T t t'
(Hfree : x <> y)
(H: substi s x t t') :
substi s x <{\y:T, t}> <{\y:T, t'}>
| s_true : substi s x <{true}> <{true}>
| s_false : substi s x <{false}> <{false}>
| s_if t1 t2 t3 t1' t2' t3'
(Hcond: substi s x t1 t1')
(Hthen: substi s x t2 t2')
(Helse: substi s x t3 t3') :
substi s x <{if t1 then t2 else t3}> <{if t1' then t2' else t3'}>
.
Hint Constructors substi : core.
(* just to make future proofs more handy *)
Hint Resolve <- eqb_string_false_iff.
Hint Resolve eqb_string_false_iff.
Hint Resolve <- eqb_string_true_iff.
Hint Resolve eqb_string_true_iff.
Theorem substi_correct : forall s x t t',
<{ [x:=s]t }> = t' <-> substi s x t t'.
Proof.
intros s x t t'.
split; intro.
- (* -> *)
generalize dependent t'.
induction t; intros; inversion H; subst; try clear H; auto; try (constructor; auto).
+ (* variable *)
rename s0 into x'.
destruct (eqb_stringP x x'); subst; simpl;
[rewrite <- eqb_string_refl; auto |
try rewrite (proj2 (eqb_string_false_iff _ _) n); auto].
+ (* abstraction *)
rename s0 into x'.
destruct (eqb_stringP x x'); subst; simpl;
[try rewrite <- eqb_string_refl; auto |
try rewrite (proj2 (eqb_string_false_iff _ _) n); auto].
- (* <- *)
induction H; simpl;
try rewrite <- eqb_string_refl;
try rewrite (proj2 (eqb_string_false_iff _ _) Hneq);
try rewrite (proj2 (eqb_string_false_iff _ _) Hfree);
subst;
auto.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Reduction *)
(** The small-step reduction relation for STLC now follows the
same pattern as the ones we have seen before. Intuitively, to
reduce a function application, we first reduce its left-hand
side (the function) until it becomes an abstraction; then we
reduce its right-hand side (the argument) until it is also a
value; and finally we substitute the argument for the bound
variable in the body of the abstraction. This last rule, written
informally as
(\x:T,t12) v2 --> [x:=v2]t12
is traditionally called _beta-reduction_. *)
(**
value v2
--------------------------- (ST_AppAbs)
(\x:T2,t1) v2 --> [x:=v2]t1
t1 --> t1'
---------------- (ST_App1)
t1 t2 --> t1' t2
value v1
t2 --> t2'
---------------- (ST_App2)
v1 t2 --> v1 t2'
*)
(** ... plus the usual rules for conditionals:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) --> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) --> t2
t1 --> t1'
-------------------------------------------------------- (ST_If)
(if t1 then t2 else t3) --> (if t1' then t2 else t3)
*)
(** Formally: *)
Reserved Notation "t '-->' t'" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T2 t1 v2,
value v2 ->
<{(\x:T2, t1) v2}> --> <{ [x:=v2]t1 }>
| ST_App1 : forall t1 t1' t2,
t1 --> t1' ->
<{t1 t2}> --> <{t1' t2}>
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 --> t2' ->
<{v1 t2}> --> <{v1 t2'}>
| ST_IfTrue : forall t1 t2,
<{if true then t1 else t2}> --> t1
| ST_IfFalse : forall t1 t2,
<{if false then t1 else t2}> --> t2
| ST_If : forall t1 t1' t2 t3,
t1 --> t1' ->
<{if t1 then t2 else t3}> --> <{if t1' then t2 else t3}>
where "t '-->' t'" := (step t t').
Hint Constructors step : core.
Notation multistep := (multi step).
Notation "t1 '-->*' t2" := (multistep t1 t2) (at level 40).
(* ================================================================= *)
(** ** Examples *)
(** Example:
(\x:Bool->Bool, x) (\x:Bool, x) -->* \x:Bool, x
i.e.,
idBB idB -->* idB
*)
Lemma step_example1 :
<{idBB idB}> -->* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl.
apply multi_refl. Qed.
(** Example:
(\x:Bool->Bool, x) ((\x:Bool->Bool, x) (\x:Bool, x))
-->* \x:Bool, x
i.e.,
(idBB (idBB idB)) -->* idB.
*)
Lemma step_example2 :
<{idBB (idBB idB)}> -->* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
(\x:Bool->Bool, x)
(\x:Bool, if x then false else true)
true
-->* false
i.e.,
(idBB notB) true -->* false.
*)
Lemma step_example3 :
<{idBB notB true}> -->* <{false}>.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
(\x:Bool -> Bool, x)
((\x:Bool, if x then false else true) true)
-->* false
i.e.,
idBB (notB true) -->* false.
(Note that this term doesn't actually typecheck; even so, we can
ask how it reduces.)
*)
Lemma step_example4 :
<{idBB (notB true)}> -->* <{false}>.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** We can use the [normalize] tactic defined in the [Smallstep] chapter
to simplify these proofs. *)
Lemma step_example1' :
<{idBB idB}> -->* idB.
Proof. normalize. Qed.
Lemma step_example2' :
<{idBB (idBB idB)}> -->* idB.
Proof. normalize. Qed.
Lemma step_example3' :
<{idBB notB true}> -->* <{false}>.
Proof. normalize. Qed.
Lemma step_example4' :
<{idBB (notB true)}> -->* <{false}>.
Proof. normalize. Qed.
(** **** Exercise: 2 stars, standard (step_example5)
Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
<{idBBBB idBB idB}>
-->* idB.
Proof.
eapply multi_step.
constructor. constructor.
constructor. simpl.
eapply multi_step.
constructor. constructor. simpl.
eapply multi_refl.
Qed.
Lemma step_example5_with_normalize :
<{idBBBB idBB idB}>
-->* idB.
Proof. normalize. Qed.
(** [] *)
(* ################################################################# *)
(** * Typing *)
(** Next we consider the typing relation of the STLC. *)
(* ================================================================= *)
(** ** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place _typing judgment_, informally
written [Gamma |- t \in T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** Following the usual notation for partial maps, we write [(X |->
T, Gamma)] for "update the partial function [Gamma] so that it
maps [x] to [T]." *)
Definition context := partial_map ty.
(* ================================================================= *)
(** ** Typing Relation *)
(**
Gamma x = T1
----------------- (T_Var)
Gamma |- x \in T1
x |-> T2 ; Gamma |- t1 \in T1
----------------------------- (T_Abs)
Gamma |- \x:T2,t1 \in T2->T1
Gamma |- t1 \in T2->T1
Gamma |- t2 \in T2
---------------------- (T_App)
Gamma |- t1 t2 \in T1
--------------------- (T_True)
Gamma |- true \in Bool
--------------------- (T_False)
Gamma |- false \in Bool
Gamma |- t1 \in Bool Gamma |- t2 \in T1 Gamma |- t3 \in T1
---------------------------------------------------------------- (T_If)
Gamma |- if t1 then t2 else t3 \in T1
We can read the three-place relation [Gamma |- t \in T] as:
"under the assumptions in Gamma, the term [t] has the type [T]." *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 101,
t custom stlc, T custom stlc at level 0).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T1,
Gamma x = Some T1 ->
Gamma |- x \in T1
| T_Abs : forall Gamma x T1 T2 t1,
x |-> T2 ; Gamma |- t1 \in T1 ->
Gamma |- \x:T2, t1 \in (T2 -> T1)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (T2 -> T1) ->
Gamma |- t2 \in T2 ->
Gamma |- t1 t2 \in T1
| T_True : forall Gamma,
Gamma |- true \in Bool
| T_False : forall Gamma,
Gamma |- false \in Bool
| T_If : forall t1 t2 t3 T1 Gamma,
Gamma |- t1 \in Bool ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- if t1 then t2 else t3 \in T1
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type : core.
(* ================================================================= *)
(** ** Examples *)
Example typing_example_1 :
empty |- \x:Bool, x \in (Bool -> Bool).
Proof.
apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that, since we added the [has_type] constructors to the hints
database, [auto] can actually solve this one immediately. *)
Example typing_example_1' :
empty |- \x:Bool, x \in (Bool -> Bool).
Proof. auto. Qed.
(** More examples:
empty |- \x:A, \y:A->A, y (y x)
\in A -> (A->A) -> A.
*)
Example typing_example_2 :
empty |-
\x:Bool,
\y:Bool->Bool,
(y (y x)) \in
(Bool -> (Bool -> Bool) -> Bool).
Proof.
apply T_Abs.
apply T_Abs.
eapply T_App. apply T_Var. apply update_eq.
eapply T_App. apply T_Var. apply update_eq.
apply T_Var. apply update_neq. intros Contra. discriminate.
Qed.
(** **** Exercise: 2 stars, standard, optional (typing_example_2_full)
Prove the same result without using [auto], [eauto], or
[eapply] (or [...]). *)
Example typing_example_2_full :
empty |-
\x:Bool,
\y:Bool->Bool,
(y (y x)) \in
(Bool -> (Bool -> Bool) -> Bool).
Proof.
apply T_Abs. apply T_Abs.
apply T_App with (T2 := <{Bool}>).
apply T_Var. apply update_eq.
apply T_App with (T2 := <{Bool}>).
apply T_Var. apply update_eq.
apply T_Var. rewrite update_permute. apply update_eq.
intro. inversion H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (typing_example_3)
Formally prove the following typing derivation holds:
empty |- \x:Bool->B, \y:Bool->Bool, \z:Bool,
y (x z)
\in T.
*)
Example typing_example_3 :
exists T,
empty |-
\x:Bool->Bool,
\y:Bool->Bool,
\z:Bool,
(y (x z)) \in
T.
Proof.
exists <{(Bool -> Bool) -> (Bool -> Bool) -> Bool -> Bool}>.
apply T_Abs. apply T_Abs. apply T_Abs.
apply T_App with (T2 := <{Bool}>).
apply T_Var. unfold update. unfold t_update. simpl. reflexivity.
apply T_App with (T2 := <{Bool}>).
apply T_Var. unfold update. unfold t_update. simpl. reflexivity.
apply T_Var. unfold update. unfold t_update. simpl. reflexivity.
Qed.
(** [] *)
(** We can also show that some terms are _not_ typable. For example,
let's check that there is no typing derivation assigning a type
to the term [\x:Bool, \y:Bool, x y] -- i.e.,
~ exists T,
empty |- \x:Bool, \y:Bool, x y \in T.
*)
Example typing_nonexample_1 :
~ exists T,
empty |-
\x:Bool,
\y:Bool,
(x y) \in
T.
Proof.
intros Hc. destruct Hc as [T Hc].
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion Hc; subst; clear Hc.
inversion H4; subst; clear H4.
inversion H5; subst; clear H5 H4.
inversion H2; subst; clear H2.
discriminate H1.
Qed.
(** **** Exercise: 3 stars, standard, optional (typing_nonexample_3)
Another nonexample:
~ (exists S T,
empty |- \x:S, x x \in T).
*)
Example typing_nonexample_3 :
~ (exists S T,
empty |-
\x:S, x x \in T).
Proof.
intro.
destruct H as [S [T]].
inversion H; subst; clear H.
inversion H5; subst; clear H5.
inversion H2; subst; clear H2.
inversion H4; subst; clear H4.
rewrite H1 in H2.
inversion H2; clear H1 H2.
(* <{ T2 -> T1 }> = T2 *)
induction T2.
- inversion H0.
- inversion H0; subst; clear H0.
apply IHT2_1. apply H1.
Qed.
(** [] *)
End STLC.
(* 2020-09-09 21:08 *)
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module sirv_ResetCatchAndSync(
input clock,
input reset,
input test_mode,
output io_sync_reset
);
wire reset_n_catch_reg_clock;
wire reset_n_catch_reg_reset;
wire [2:0] reset_n_catch_reg_io_d;
wire [2:0] reset_n_catch_reg_io_q;
wire reset_n_catch_reg_io_en;
wire [1:0] T_6;
wire [2:0] T_7;
wire T_8;
wire T_9;
sirv_AsyncResetRegVec_36 reset_n_catch_reg (
.clock(reset_n_catch_reg_clock),
.reset(reset_n_catch_reg_reset),
.io_d(reset_n_catch_reg_io_d),
.io_q(reset_n_catch_reg_io_q),
.io_en(reset_n_catch_reg_io_en)
);
assign io_sync_reset = test_mode ? reset : T_9;
assign reset_n_catch_reg_clock = clock;
assign reset_n_catch_reg_reset = reset;
assign reset_n_catch_reg_io_d = T_7;
assign reset_n_catch_reg_io_en = 1'h1;
assign T_6 = reset_n_catch_reg_io_q[2:1];
assign T_7 = {1'h1,T_6};
assign T_8 = reset_n_catch_reg_io_q[0];
assign T_9 = ~ T_8;
endmodule
|
//-----------------------------------------------------
// Design Name : datapath
// File Name : datapath.v
// Function : This program designs an One-Pulse Generator.
// Coder : hydai
//-----------------------------------------------------
module datapath (
output reg V,
output reg C,
output reg N,
output reg Z,
output [15:0] R0,
output [15:0] R1,
output [15:0] R2,
output [15:0] R3,
output [15:0] R4,
output [15:0] R5,
output [15:0] R6,
output [15:0] R7,
output [15:0] R8,
output [15:0] R9,
output [15:0] R10,
output [15:0] R11,
output [15:0] R12,
output [15:0] R13,
output [15:0] R14,
output [15:0] R15,
output reg [15:0] BUSA,
output reg [15:0] BUSB,
input [25:0] control,
input [15:0] constant,
input [15:0] data,
input clk,
input rst_n
);
reg [15:0] R [0:15];
reg [15:0] BUSD;
wire [3:0] DA, AA, BA, FS, SA;
wire [2:0] SS;
wire MB, MD, RW;
reg [15:0] MUXB, FUResult;
reg [15:0] tmp16bit, tmp16bit1, tmp16bit2;
// get all signal
assign {DA, AA, BA, MB, FS, SS, SA, MD, RW} = control;
assign R0 = R[0];
assign R1 = R[1];
assign R2 = R[2];
assign R3 = R[3];
assign R4 = R[4];
assign R5 = R[5];
assign R6 = R[6];
assign R7 = R[7];
assign R8 = R[8];
assign R9 = R[9];
assign R10 = R[10];
assign R11 = R[11];
assign R12 = R[12];
assign R13 = R[13];
assign R14 = R[14];
assign R15 = R[15];
// Register files
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
R[0] <= 0;
R[1] <= 0;
R[2] <= 0;
R[3] <= 0;
R[4] <= 0;
R[5] <= 0;
R[6] <= 0;
R[7] <= 0;
R[8] <= 0;
R[9] <= 0;
R[10] <= 0;
R[11] <= 0;
R[12] <= 0;
R[13] <= 0;
R[14] <= 0;
R[15] <= 0;
end else begin
if (RW) begin
R[DA] <= BUSD;
end else begin
R[DA] <= R[DA];
end
end // end of if-else block
end // end of always
// MUX B
always @(*) begin
if (MB) begin
MUXB <= constant;
end else begin
MUXB <= R[BA];
end
end
// BUS A
always @(*) begin
BUSA <= R[AA];
end
// MUX D
always @(*) begin
if (MD) begin
BUSD <= data;
end else begin
BUSD <= FUResult;
end
end
// Barrel shifter
always @(*) begin
tmp16bit <= 0;
tmp16bit1 <= 0;
case(SS)
// B >> (SA) bits
3'b000: begin
BUSB <= MUXB >> SA;
end
// B << (SA) bits
3'b001: begin
BUSB <= MUXB << SA;
end
// B right rotating by (SA) bits
3'b010: begin
if (SA == 0) begin
BUSB <= MUXB;
end else begin
tmp16bit <= MUXB >> SA;
tmp16bit1 <= MUXB << (16 - SA);
BUSB <= tmp16bit | tmp16bit1;
end
end
// B left rotating by (SA) bits
3'b011: begin
if (SA == 0) begin
BUSB <= MUXB;
end else begin
tmp16bit <= MUXB << SA;
tmp16bit1 <= MUXB >> (16 - SA);
BUSB <= tmp16bit | tmp16bit1;
end
end
// B arithmetic-right-shift by (SA) bits
3'b100: begin
BUSB <= $signed(MUXB) >>> SA;
end
// Other cases
default: begin
BUSB <= MUXB;
end
endcase
end
// Function Unit
always @(*) begin
C <= 0;
V <= 0;
tmp16bit2 <= 0;
case (FS)
// F <- A
4'b0000: begin
FUResult <= BUSA;
end
// F <- A+1
4'b0001: begin
{C, FUResult} <= BUSA + 1'b1;
if (BUSA[15] == FUResult[15]) begin
V <= 0;
end else begin
V <= 1;
end
end
// F <- A+B
4'b0010: begin
{C, FUResult} <= BUSA + BUSB;
if (BUSA[15] == BUSB[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <- A+B+1
4'b0011: begin
{C, FUResult} <= BUSA + BUSB + 2'b01;
if (BUSA[15] == BUSB[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <= A + ~B
4'b0100: begin
tmp16bit2 <= ~BUSB;
{C, FUResult} <= BUSA + tmp16bit2;
if (BUSA[15] == tmp16bit2[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <= A + !B + 1
4'b0101: begin
tmp16bit2 <= ~BUSB;
{C, FUResult} <= BUSA + tmp16bit2 + 2'b01;
if (BUSA[15] == tmp16bit2[15]) begin
if (FUResult[15] == BUSA[15]) begin
V <= 0;
end else begin
V <= 1;
end
end else begin
V <= 0;
end
end
// F <= A - 1
4'b0110: begin
{C, FUResult} <= BUSA + 16'hffff;
if (BUSA[15] == FUResult[15]) begin
V <= 0;
end else begin
V <= 1;
end
end
// F <= A
4'b0111: begin
FUResult <= BUSA;
end
// F <= A AND B
4'b1000: begin
FUResult <= BUSA & BUSB;
end
// F <= A OR B
4'b1001: begin
FUResult <= BUSA | BUSB;
end
// F <= A XOR B
4'b1010: begin
FUResult <= BUSA ^ BUSB;
end
// F <= !A
4'b1011: begin
FUResult <= ~BUSA;
end
4'b1100: begin
FUResult <= BUSB;
end
default: begin
FUResult <= 0;
end
endcase
end
// Detect Negtive
always @(*) begin
if (FUResult[15] == 1) begin
N <= 1;
end else begin
N <= 0;
end
end
// Detect Zero
always @(*) begin
if (FUResult == 0) begin
Z <= 1;
end else begin
Z <= 0;
end
end
endmodule // endmodule of datapath
|
/**
* The computer player - AI :)
*/
module ai (
CLOCK,
RESET,
POSITION,
BALL_H,
BALL_V
);
input CLOCK, RESET;
input [10:0] BALL_H;
input [10:0] BALL_V;
output [7:0] POSITION;
reg [10:0] paddle;
// Just follow the ball.
always @ (posedge CLOCK or posedge RESET) begin
if (RESET) begin
paddle <= 0;
end else begin
if (BALL_V < 11'd32) begin
// top of the screen
paddle <= 0;
end else if (BALL_V > 11'd432) begin
// bottom of the screen
paddle <= 11'd400;
end else begin
// Center on the ball
paddle <= BALL_V - 11'd32;
end
end
end
/*
reg [27:0] timer;
always @ (posedge CLOCK or posedge RESET) begin
if (RESET) begin
timer <= 0;
end else begin
if (timer == 28'd500000) begin
timer <= 0;
end else begin
timer <= timer + 1;
end
end
end
*/
wire [10:0] final_paddle_pos = paddle >> 1; // divide by two to fit in the byte of the POSITION (2px resolution)
assign POSITION = final_paddle_pos[7:0];
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_data_path.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This is top level of read path and also consist of comparison logic
// for read data.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module read_data_path #(
parameter TCQ = 100,
parameter START_ADDR = 32'h00000000,
parameter nCK_PER_CLK = 4, // DRAM clock : MC clock
parameter MEM_TYPE = "DDR3",
parameter FAMILY = "VIRTEX6",
parameter BL_WIDTH = 6,
parameter MEM_BURST_LEN = 8,
parameter ADDR_WIDTH = 32,
parameter CMP_DATA_PIPE_STAGES = 3,
parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
parameter NUM_DQ_PINS = 8,
parameter DWIDTH = nCK_PER_CLK * 2 * NUM_DQ_PINS,
parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
parameter MEM_COL_WIDTH = 10
)
(
input clk_i,
input [9:0] rst_i,
input manual_clear_error,
output cmd_rdy_o,
input cmd_valid_i,
input memc_cmd_full_i,
input [31:0] prbs_fseed_i,
input mode_load_i,
input [3:0] data_mode_i,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
// input [31:0] m_addr_i,
input [31:0] simple_data0 ,
input [31:0] simple_data1 ,
input [31:0] simple_data2 ,
input [31:0] simple_data3 ,
input [31:0] simple_data4 ,
input [31:0] simple_data5 ,
input [31:0] simple_data6 ,
input [31:0] simple_data7 ,
input [31:0] fixed_data_i,
input [31:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
output data_rdy_o,
input data_valid_i,
input [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] data_i,
output data_error_o, //data_error on user data bus side
output [DWIDTH-1:0] cmp_data_o,
output [DWIDTH-1:0] rd_mdata_o ,
output cmp_data_valid,
output [31:0] cmp_addr_o,
output [5 :0] cmp_bl_o,
output [NUM_DQ_PINS/8 - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane
output [NUM_DQ_PINS/8 - 1:0] cumlative_dq_lane_error_r, // V6: latched error byte lane that occure on
// first error
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f0_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_r1_bit_error_r ,
output reg [NUM_DQ_PINS - 1:0] cumlative_dq_f1_bit_error_r ,
output reg [NUM_DQ_PINS-1:0] dq_r0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f0_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_r1_bit_error_r,
output reg [NUM_DQ_PINS-1:0] dq_f1_bit_error_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_r,
output reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_r,
output [31:0] error_addr_o
);
wire gen_rdy;
wire gen_valid;
wire [31:0] gen_addr;
wire [BL_WIDTH-1:0] gen_bl;
wire cmp_rdy;
wire cmp_valid;
wire [31:0] cmp_addr;
wire [5:0] cmp_bl;
reg data_error;
wire [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] cmp_data_r;
reg last_word_rd;
reg [5:0] bl_counter;
wire cmd_rdy;
wire user_bl_cnt_is_1;
wire data_rdy;
reg [DWIDTH:0] delayed_data;
wire rd_mdata_en;
reg [NUM_DQ_PINS*nCK_PER_CLK*2-1:0] rd_data_r;
reg force_wrcmd_gen;
reg wait_bl_end;
reg wait_bl_end_r1;
reg l_data_error ;
reg u_data_error;
reg v6_data_cmp_valid;
wire [DWIDTH -1 :0] rd_v6_mdata;
reg [DWIDTH -1 :0] cmpdata_r;
wire [DWIDTH -1 :0] rd_mdata;
reg cmp_data_en;
localparam ER_WIDTH = (nCK_PER_CLK == 2) ? NUM_DQ_PINS/2 : NUM_DQ_PINS;
wire [ER_WIDTH - 1:0] error_byte;
reg [ER_WIDTH - 1:0] error_byte_r1;
wire [NUM_DQ_PINS*nCK_PER_CLK*2 - 1:0] error_bit;
reg [NUM_DQ_PINS*nCK_PER_CLK*2 -1:0] error_bit_r1;
wire [NUM_DQ_PINS-1:0] dq_bit_error;
wire [NUM_DQ_PINS-1:0] cumlative_dq_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] dq_lane_error;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r1;
reg [ NUM_DQ_PINS/8-1:0] dq_lane_error_r2;
reg [NUM_DQ_PINS-1:0] dq_bit_error_r1;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f0_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_r1_bit_error_c;
wire [NUM_DQ_PINS-1:0] cumlative_dq_f1_bit_error_c;
wire [ NUM_DQ_PINS/8-1:0] cum_dq_lane_error_mask;
wire [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_c;
reg [ NUM_DQ_PINS/8-1:0] cumlative_dq_lane_error_reg;
reg [NUM_DQ_PINS - 1:0] dq_r0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_read_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f0_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_r1_expect_bit_rdlay1;
reg [NUM_DQ_PINS - 1:0] dq_f1_expect_bit_rdlay1;
wire [NUM_DQ_PINS-1:0] dq_r0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f0_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_r1_bit_error ;
wire [NUM_DQ_PINS-1:0] dq_f1_bit_error ;
reg [31:0] error_addr_r1;
reg [31:0] error_addr_r2;
reg [31:0] error_addr_r3;
wire cmd_start_i;
reg data_valid_r;
always @ (posedge clk_i) begin
wait_bl_end_r1 <= #TCQ wait_bl_end;
rd_data_r <= #TCQ data_i;
end
reg [7:0] force_wrcmd_timeout_cnts ;
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_gen <= #TCQ 1'b0;
else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111)
force_wrcmd_gen <= #TCQ 1'b0;
else if ((cmd_valid_i && bl_i > 16) || wait_bl_end )
force_wrcmd_gen <= #TCQ 1'b1;
end
always @ (posedge clk_i) begin
if (rst_i[0])
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1)
force_wrcmd_timeout_cnts <= #TCQ 'b0;
else if (force_wrcmd_gen)
force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1'b1;
end
always @ (posedge clk_i)
if (rst_i[0])
wait_bl_end <= #TCQ 1'b0;
else if (force_wrcmd_timeout_cnts == 8'b11111111)
wait_bl_end <= #TCQ 1'b0;
else if (gen_rdy && gen_valid && gen_bl > 16)
wait_bl_end <= #TCQ 1'b1;
else if (wait_bl_end && user_bl_cnt_is_1)
wait_bl_end <= #TCQ 1'b0;
assign cmd_rdy_o = cmd_rdy;
read_posted_fifo #(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_BURST_LEN (MEM_BURST_LEN),
.ADDR_WIDTH (32),
.BL_WIDTH (BL_WIDTH)
)
read_postedfifo(
.clk_i (clk_i),
.rst_i (rst_i[0]),
.cmd_rdy_o (cmd_rdy ),
.cmd_valid_i (cmd_valid_i ),
.data_valid_i (data_rdy ), // input to
.addr_i (addr_i ),
.bl_i (bl_i ),
.cmd_start_i (cmd_start),
.cmd_sent (cmd_sent),
.bl_sent (bl_sent ),
.cmd_en_i (cmd_en_i),
.memc_cmd_full_i (memc_cmd_full_i),
.gen_valid_o (gen_valid ),
.gen_addr_o (gen_addr ),
.gen_bl_o (gen_bl ),
.rd_mdata_en (rd_mdata_en)
);
rd_data_gen #(
.TCQ (TCQ),
.FAMILY (FAMILY),
.MEM_TYPE (MEM_TYPE),
.BL_WIDTH (BL_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.MEM_BURST_LEN (MEM_BURST_LEN),
.NUM_DQ_PINS (NUM_DQ_PINS),
.SEL_VICTIM_LINE (SEL_VICTIM_LINE),
.START_ADDR (START_ADDR),
.DATA_PATTERN (DATA_PATTERN),
.DWIDTH(DWIDTH),
.COLUMN_WIDTH (MEM_COL_WIDTH)
)
rd_datagen(
.clk_i (clk_i ),
.rst_i (rst_i[4:0]),
.prbs_fseed_i (prbs_fseed_i),
.data_mode_i (data_mode_i ),
.cmd_rdy_o (gen_rdy ),
.cmd_valid_i (gen_valid ),
.mode_load_i (mode_load_i),
.cmd_start_o (cmd_start),
// .m_addr_i (m_addr_i ),
.simple_data0 (simple_data0),
.simple_data1 (simple_data1),
.simple_data2 (simple_data2),
.simple_data3 (simple_data3),
.simple_data4 (simple_data4),
.simple_data5 (simple_data5),
.simple_data6 (simple_data6),
.simple_data7 (simple_data7),
.fixed_data_i (fixed_data_i),
.addr_i (gen_addr ),
.bl_i (gen_bl ),
.user_bl_cnt_is_1_o (user_bl_cnt_is_1),
.data_rdy_i (data_valid_i ), // input to
.data_valid_o (cmp_valid ),
.data_o (cmp_data )
);
afifo #
(
.TCQ (TCQ),
.DSIZE (DWIDTH),
.FIFO_DEPTH (32),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_mdata_fifo
(
.wr_clk (clk_i),
.rst (rst_i[0]),
.wr_en (data_valid_i),
.wr_data (data_i),
.rd_en (rd_mdata_en),
.rd_clk (clk_i),
.rd_data (rd_v6_mdata),
.full (),
.empty (),
.almost_full ()
);
always @ (posedge clk_i)
// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data};
cmp_data_r <= #TCQ cmp_data;
assign rd_mdata_o = rd_mdata;
assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r:
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata:
data_i;
assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en :
(FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i;
assign cmp_data_o = cmp_data_r;
assign cmp_addr_o = gen_addr;
assign cmp_bl_o = gen_bl[5:0];
assign data_rdy_o = data_rdy;
assign data_rdy = cmp_valid & data_valid_i;
always @ (posedge clk_i)
v6_data_cmp_valid <= #TCQ rd_mdata_en;
always @ (posedge clk_i)
cmp_data_en <= #TCQ data_rdy;
genvar i;
generate
if (FAMILY == "SPARTAN6")
begin: gen_error_1
always @ (posedge clk_i)
begin
if (cmp_data_en)
l_data_error <= #TCQ (rd_data_r[DWIDTH/2-1:0] != cmp_data_r[DWIDTH/2-1:0]);
else
l_data_error <= #TCQ 1'b0;
if (cmp_data_en)
u_data_error <= #TCQ (rd_data_r[DWIDTH-1:DWIDTH/2] != cmp_data_r[DWIDTH-1:DWIDTH/2]);
else
u_data_error <= #TCQ 1'b0;
data_error <= #TCQ l_data_error | u_data_error;
//synthesis translate_off
if (data_error)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
end
else
// if (FAMILY == "VIRTEX6" )
begin: gen_error_3
if (nCK_PER_CLK == 2)
begin
for (i = 0; i < NUM_DQ_PINS/2; i = i + 1)
begin: gen_cmp_2
assign error_byte[i]
= (data_valid_i && (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) );
end
//nCK_PER_CLK
for (i = 0; i < NUM_DQ_PINS*4; i = i + 1)
begin: gen_cmp_bit_2
assign error_bit[i]
= (data_valid_i && (data_i[i] != cmp_data[i]) ) ? 1'b1: 1'b0 ;
end
end
else
begin
for (i = 0; i < NUM_DQ_PINS; i = i + 1)
begin: gen_cmp_4
assign error_byte[i]
= (data_valid_i && (data_i[8*(i+1)-1:8*i] != cmp_data[8*(i+1)-1:8*i]) );
end
for (i = 0; i < NUM_DQ_PINS*8; i = i + 1)
begin: gen_cmp_bit_4
assign error_bit[i]
= (data_valid_i && (data_i[i] != cmp_data[i]) ) ? 1'b1: 1'b0 ;
end
end
always @ (posedge clk_i)
begin
dq_r0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*1 - 1:0];
dq_f0_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_read_bit_rdlay1 <= #TCQ data_i[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*1 - 1:0];
dq_f0_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*2 - 1:NUM_DQ_PINS*1];
dq_r1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*3 - 1:NUM_DQ_PINS*2];
dq_f1_expect_bit_rdlay1 <= #TCQ cmp_data[NUM_DQ_PINS*4 - 1:NUM_DQ_PINS*3];
dq_r0_read_bit_r <= #TCQ dq_r0_read_bit_rdlay1 ;
dq_f0_read_bit_r <= #TCQ dq_f0_read_bit_rdlay1 ;
dq_r1_read_bit_r <= #TCQ dq_r1_read_bit_rdlay1 ;
dq_f1_read_bit_r <= #TCQ dq_f1_read_bit_rdlay1 ;
dq_r0_expect_bit_r <= #TCQ dq_r0_expect_bit_rdlay1;
dq_f0_expect_bit_r <= #TCQ dq_f0_expect_bit_rdlay1;
dq_r1_expect_bit_r <= #TCQ dq_r1_expect_bit_rdlay1;
dq_f1_expect_bit_r <= #TCQ dq_f1_expect_bit_rdlay1;
end
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
error_byte_r1 <= #TCQ 'b0;
error_bit_r1 <= #TCQ 'b0;
data_error <= #TCQ 1'b0;
end
else begin
error_byte_r1 <= #TCQ error_byte;
error_bit_r1 <= #TCQ error_bit;
data_error <= #TCQ | error_byte_r1;
//synthesis translate_off
if (data_error)
$display ("ERROR at time %t" , $time);
//synthesis translate_on
end
end
for ( i = 0; i < NUM_DQ_PINS/8; i = i+1)
begin: gen_dq_error_map
assign dq_lane_error[i] = (error_byte_r1[i] | error_byte_r1[i+NUM_DQ_PINS/8] |
error_byte_r1[i+ (NUM_DQ_PINS*2/8)] |
error_byte_r1[i+ (NUM_DQ_PINS*3/8)]) ? 1'b1:1'b0;
assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
end
// mapped the user bits error to dq bits error
// mapper the error to rising 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r0_error_mapbit
assign dq_r0_bit_error[i] = (error_bit_r1[i]);
assign cumlative_dq_r0_bit_error_c[i] = cumlative_dq_r0_bit_error_r[i] | dq_r0_bit_error[i];
end
// mapper the error to falling 0
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f0_error_mapbit
assign dq_f0_bit_error[i] = (error_bit_r1[i+NUM_DQ_PINS*1] );
assign cumlative_dq_f0_bit_error_c[i] = cumlative_dq_f0_bit_error_r[i] | dq_f0_bit_error[i];
end
// mapper the error to rising 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_r1_error_mapbit
assign dq_r1_bit_error[i] = (error_bit_r1[i+ (NUM_DQ_PINS*2)]);
assign cumlative_dq_r1_bit_error_c[i] = cumlative_dq_r1_bit_error_r[i] | dq_r1_bit_error[i];
end
// mapper the error to falling 1
for ( i = 0; i < NUM_DQ_PINS; i = i+1)
begin: gen_dq_f1_error_mapbit
assign dq_f1_bit_error[i] = ( error_bit_r1[i+ (NUM_DQ_PINS*3)]);
assign cumlative_dq_f1_bit_error_c[i] = cumlative_dq_f1_bit_error_r[i] | dq_f1_bit_error[i];
end
reg COuta;
always @ (posedge clk_i)
begin
if (rst_i[1] || manual_clear_error) begin
dq_bit_error_r1 <= #TCQ 'b0;
dq_lane_error_r1 <= #TCQ 'b0;
dq_lane_error_r2 <= #TCQ 'b0;
data_valid_r <= #TCQ 1'b0;
dq_r0_bit_error_r <= #TCQ 'b0;
dq_f0_bit_error_r <= #TCQ 'b0;
dq_r1_bit_error_r <= #TCQ 'b0;
dq_f1_bit_error_r <= #TCQ 'b0;
cumlative_dq_lane_error_reg <= #TCQ 'b0;
cumlative_dq_r0_bit_error_r <= #TCQ 'b0;
cumlative_dq_f0_bit_error_r <= #TCQ 'b0;
cumlative_dq_r1_bit_error_r <= #TCQ 'b0;
cumlative_dq_f1_bit_error_r <= #TCQ 'b0;
error_addr_r1 <= #TCQ 'b0;
error_addr_r2 <= #TCQ 'b0;
error_addr_r3 <= #TCQ 'b0;
end
else begin
data_valid_r <= #TCQ data_valid_i;
dq_lane_error_r1 <= #TCQ dq_lane_error;
dq_bit_error_r1 <= #TCQ dq_bit_error;
cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c;
cumlative_dq_r0_bit_error_r <= #TCQ cumlative_dq_r0_bit_error_c;
cumlative_dq_f0_bit_error_r <= #TCQ cumlative_dq_f0_bit_error_c;
cumlative_dq_r1_bit_error_r <= #TCQ cumlative_dq_r1_bit_error_c;
cumlative_dq_f1_bit_error_r <= #TCQ cumlative_dq_f1_bit_error_c;
dq_r0_bit_error_r <= #TCQ dq_r0_bit_error;
dq_f0_bit_error_r <= #TCQ dq_f0_bit_error;
dq_r1_bit_error_r <= #TCQ dq_r1_bit_error;
dq_f1_bit_error_r <= #TCQ dq_f1_bit_error;
error_addr_r2 <= #TCQ error_addr_r1;
error_addr_r3 <= #TCQ error_addr_r2;
if (rd_mdata_en)
error_addr_r1 <= #TCQ gen_addr;
else if (data_valid_i)
{COuta,error_addr_r1} <= #TCQ error_addr_r1 + 4;
end
end
end
endgenerate
assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg;
assign dq_error_bytelane_cmp = dq_lane_error_r1;
assign data_error_o = data_error;
assign error_addr_o = error_addr_r3;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_V
`define SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_V
/**
* dlclkp: Clock gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_p_pp_pg_n/sky130_fd_sc_ls__udp_dlatch_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ls__dlclkp (
GCLK,
GATE,
CLK
);
// Module ports
output GCLK;
input GATE;
input CLK ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire m0 ;
wire clkn ;
wire CLK_delayed ;
wire GATE_delayed;
reg notifier ;
wire awake ;
// Name Output Other arguments
not not0 (clkn , CLK_delayed );
sky130_fd_sc_ls__udp_dlatch$P_pp$PG$N dlatch0 (m0 , GATE_delayed, clkn, notifier, VPWR, VGND);
and and0 (GCLK , m0, CLK_delayed );
assign awake = ( VPWR === 1'b1 );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLCLKP_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V
/**
* edfxtp: Delay flop with loopback enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_ls__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_ls__udp_dff_p.v"
`celldefine
module sky130_fd_sc_ls__edfxtp (
Q ,
CLK,
D ,
DE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_ls__udp_mux_2to1 mux_2to10 (mux_out, buf_Q, D, DE );
sky130_fd_sc_ls__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__EDFXTP_FUNCTIONAL_V |
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: California State University San Bernardino
// Engineer: Bogdan Kravtsov
// Tyler Clayton
//
// Create Date: 15:58:00 10/31/2016
// Module Name: I_EXECUTE_tb
// Project Name: MIPS
// Description: Testing the MIPS EX_MEM register implementation.
//
// Dependencies: I_EXECUTE.v
//
////////////////////////////////////////////////////////////////////////////////
module EX_MEM_tb;
// Inputs.
reg clk;
reg [1:0] ctlwb_out;
reg [2:0] ctlm_out;
reg [31:0] adder_out;
reg aluzero;
reg [31:0] aluout;
reg [31:0] readdat2;
reg [4:0] muxout;
// Outputs.
wire [1:0] wb_ctlout;
wire [2:0] m_ctlout;
wire [31:0] add_result;
wire zero;
wire [31:0] alu_result;
wire [31:0] rdata2out;
wire [4:0] five_bit_muxout;
// Instantiate the module.
EX_MEM ex_mem(.clk(clk), .ctlwb_out(ctlwb_out), .ctlm_out(ctlm_out),
.adder_out(adder_out), .aluzero(aluzero), .aluout(aluout),
.readdat2(readdat2), .muxout(muxout), .wb_ctlout(wb_ctlout),
.m_ctlout(m_ctlout), .add_result(add_result), .zero(zero),
.alu_result(alu_result), .rdata2out(rdata2out),
.five_bit_muxout(five_bit_muxout));
initial begin
// Initialize inputs.
clk = 0;
ctlwb_out = 0;
ctlm_out = 0;
adder_out = 0;
aluzero = 0;
aluout = 0;
readdat2 = 0;
muxout = 0;
// Wait 100 ns for global reset to finish.
#100;
$monitor("ctlwb_out = %b, ctlm_out = %b, adder_out = %b, ",
ctlwb_out, ctlm_out, adder_out,
"aluzero = %b, aluout = %b, readdat2 = %b, muxout = %b",
aluzero, aluout, readdat2, muxout);
ctlwb_out = 2'b01;
ctlm_out = 3'b101;
adder_out = 32'h00FF1133;
aluzero = 0;
aluout = 32'h00FFFFFF;
readdat2 = 32'h005100C3;
muxout = 4'b0101;
#20;
ctlwb_out = 2'b10;
ctlm_out = 3'b001;
adder_out = 32'h00FF1100;
aluzero = 0;
aluout = 32'h00FFFF23;
readdat2 = 32'h00F3DD10;
muxout = 4'b0011;
#20;
$finish;
end
always @ *
begin
#10 clk = ~clk;
end
endmodule
|
// (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 4
(* X_CORE_INFO = "axi_protocol_converter_v2_1_axi_protocol_converter,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "tutorial_auto_pc_1,axi_protocol_converter_v2_1_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "tutorial_auto_pc_1,axi_protocol_converter_v2_1_axi_protocol_converter,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=2,C_S_AXI_PROTOCOL=1,C_IGNORE_ID=0,C_AXI_ID_WIDTH=12,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=32,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=0,C_AXI_AWUSER_WIDTH=1,C_AXI_ARUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module tutorial_auto_pc_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [11 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [3 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WID" *)
input wire [11 : 0] s_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [31 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [3 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [11 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [11 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [3 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [11 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [31 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [31 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [3 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [31 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(2),
.C_S_AXI_PROTOCOL(1),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(12),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(4'H0),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(1'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(s_axi_wid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(4'H0),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(1'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(12'H000),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(12'H000),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(1'H1),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
(* Copyright (c) 2008-2012, Adam Chlipala
*
* This work is licensed under a
* Creative Commons Attribution-Noncommercial-No Derivative Works 3.0
* Unported License.
* The license text is available at:
* http://creativecommons.org/licenses/by-nc-nd/3.0/
*)
(* begin hide *)
Require Import Arith List.
Require Import CpdtTactics.
Set Implicit Arguments.
(* end hide *)
(** %\chapter{Dependent Data Structures}% *)
(** Our red-black tree example from the last chapter illustrated how dependent types enable static enforcement of data structure invariants. To find interesting uses of dependent data structures, however, we need not look to the favorite examples of data structures and algorithms textbooks. More basic examples like length-indexed and heterogeneous lists come up again and again as the building blocks of dependent programs. There is a surprisingly large design space for this class of data structure, and we will spend this chapter exploring it. *)
(** * More Length-Indexed Lists *)
(** We begin with a deeper look at the length-indexed lists that began the last chapter.%\index{Gallina terms!ilist}% *)
Section ilist.
Variable A : Set.
Inductive ilist : nat -> Set :=
| Nil : ilist O
| Cons : forall n, A -> ilist n -> ilist (S n).
(** We might like to have a certified function for selecting an element of an [ilist] by position. We could do this using subset types and explicit manipulation of proofs, but dependent types let us do it more directly. It is helpful to define a type family %\index{Gallina terms!fin}%[fin], where [fin n] is isomorphic to [{m : nat | m < n}]. The type family name stands for "finite." *)
(* EX: Define a function [get] for extracting an [ilist] element by position. *)
(* begin thide *)
Inductive fin : nat -> Set :=
| First : forall n, fin (S n)
| Next : forall n, fin n -> fin (S n).
(** An instance of [fin] is essentially a more richly typed copy of a prefix of the natural numbers. Every element is a [First] iterated through applying [Next] a number of times that indicates which number is being selected. For instance, the three values of type [fin 3] are [First 2], [Next (First 1)], and [Next (Next (First 0))].
Now it is easy to pick a [Prop]-free type for a selection function. As usual, our first implementation attempt will not convince the type checker, and we will attack the deficiencies one at a time.
[[
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx => ?
| Cons _ x ls' => fun idx =>
match idx with
| First _ => x
| Next _ idx' => get ls' idx'
end
end.
]]
%\vspace{-.15in}%We apply the usual wisdom of delaying arguments in [Fixpoint]s so that they may be included in [return] clauses. This still leaves us with a quandary in each of the [match] cases. First, we need to figure out how to take advantage of the contradiction in the [Nil] case. Every [fin] has a type of the form [S n], which cannot unify with the [O] value that we learn for [n] in the [Nil] case. The solution we adopt is another case of [match]-within-[return], with the [return] clause chosen carefully so that it returns the proper type [A] in case the [fin] index is [O], which we know is true here; and so that it returns an easy-to-inhabit type [unit] in the remaining, impossible cases, which nonetheless appear explicitly in the body of the [match].
[[
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx =>
match idx in fin n' return (match n' with
| O => A
| S _ => unit
end) with
| First _ => tt
| Next _ _ => tt
end
| Cons _ x ls' => fun idx =>
match idx with
| First _ => x
| Next _ idx' => get ls' idx'
end
end.
]]
%\vspace{-.15in}%Now the first [match] case type-checks, and we see that the problem with the [Cons] case is that the pattern-bound variable [idx'] does not have an apparent type compatible with [ls']. In fact, the error message Coq gives for this exact code can be confusing, thanks to an overenthusiastic type inference heuristic. We are told that the [Nil] case body has type [match X with | O => A | S _ => unit end] for a unification variable [X], while it is expected to have type [A]. We can see that setting [X] to [O] resolves the conflict, but Coq is not yet smart enough to do this unification automatically. Repeating the function's type in a [return] annotation, used with an [in] annotation, leads us to a more informative error message, saying that [idx'] has type [fin n1] while it is expected to have type [fin n0], where [n0] is bound by the [Cons] pattern and [n1] by the [Next] pattern. As the code is written above, nothing forces these two natural numbers to be equal, though we know intuitively that they must be.
We need to use [match] annotations to make the relationship explicit. Unfortunately, the usual trick of postponing argument binding will not help us here. We need to match on both [ls] and [idx]; one or the other must be matched first. To get around this, we apply the convoy pattern that we met last chapter. This application is a little more clever than those we saw before; we use the natural number predecessor function [pred] to express the relationship between the types of these variables.
[[
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx =>
match idx in fin n' return (match n' with
| O => A
| S _ => unit
end) with
| First _ => tt
| Next _ _ => tt
end
| Cons _ x ls' => fun idx =>
match idx in fin n' return ilist (pred n') -> A with
| First _ => fun _ => x
| Next _ idx' => fun ls' => get ls' idx'
end ls'
end.
]]
%\vspace{-.15in}%There is just one problem left with this implementation. Though we know that the local [ls'] in the [Next] case is equal to the original [ls'], the type-checker is not satisfied that the recursive call to [get] does not introduce non-termination. We solve the problem by convoy-binding the partial application of [get] to [ls'], rather than [ls'] by itself. *)
Fixpoint get n (ls : ilist n) : fin n -> A :=
match ls with
| Nil => fun idx =>
match idx in fin n' return (match n' with
| O => A
| S _ => unit
end) with
| First _ => tt
| Next _ _ => tt
end
| Cons _ x ls' => fun idx =>
match idx in fin n' return (fin (pred n') -> A) -> A with
| First _ => fun _ => x
| Next _ idx' => fun get_ls' => get_ls' idx'
end (get ls')
end.
(* end thide *)
End ilist.
Implicit Arguments Nil [A].
Implicit Arguments First [n].
(** A few examples show how to make use of these definitions. *)
Check Cons 0 (Cons 1 (Cons 2 Nil)).
(** %\vspace{-.15in}% [[
Cons 0 (Cons 1 (Cons 2 Nil))
: ilist nat 3
]]
*)
(* begin thide *)
Eval simpl in get (Cons 0 (Cons 1 (Cons 2 Nil))) First.
(** %\vspace{-.15in}% [[
= 0
: nat
]]
*)
Eval simpl in get (Cons 0 (Cons 1 (Cons 2 Nil))) (Next First).
(** %\vspace{-.15in}% [[
= 1
: nat
]]
*)
Eval simpl in get (Cons 0 (Cons 1 (Cons 2 Nil))) (Next (Next First)).
(** %\vspace{-.15in}% [[
= 2
: nat
]]
*)
(* end thide *)
(* begin hide *)
(* begin thide *)
Definition map' := map.
(* end thide *)
(* end hide *)
(** Our [get] function is also quite easy to reason about. We show how with a short example about an analogue to the list [map] function. *)
Section ilist_map.
Variables A B : Set.
Variable f : A -> B.
Fixpoint imap n (ls : ilist A n) : ilist B n :=
match ls with
| Nil => Nil
| Cons _ x ls' => Cons (f x) (imap ls')
end.
(** It is easy to prove that [get] "distributes over" [imap] calls. *)
(* EX: Prove that [get] distributes over [imap]. *)
(* begin thide *)
Theorem get_imap : forall n (idx : fin n) (ls : ilist A n),
get (imap ls) idx = f (get ls idx).
induction ls; dep_destruct idx; crush.
Qed.
(* end thide *)
End ilist_map.
(** The only tricky bit is remembering to use our [dep_destruct] tactic in place of plain [destruct] when faced with a baffling tactic error message. *)
(** * Heterogeneous Lists *)
(** Programmers who move to statically typed functional languages from scripting languages often complain about the requirement that every element of a list have the same type. With fancy type systems, we can partially lift this requirement. We can index a list type with a "type-level" list that explains what type each element of the list should have. This has been done in a variety of ways in Haskell using type classes, and we can do it much more cleanly and directly in Coq. *)
Section hlist.
Variable A : Type.
Variable B : A -> Type.
(* EX: Define a type [hlist] indexed by a [list A], where the type of each element is determined by running [B] on the corresponding element of the index list. *)
(** We parameterize our heterogeneous lists by a type [A] and an [A]-indexed type [B].%\index{Gallina terms!hlist}% *)
(* begin thide *)
Inductive hlist : list A -> Type :=
| HNil : hlist nil
| HCons : forall (x : A) (ls : list A), B x -> hlist ls -> hlist (x :: ls).
(** We can implement a variant of the last section's [get] function for [hlist]s. To get the dependent typing to work out, we will need to index our element selectors (in type family [member]) by the types of data that they point to.%\index{Gallina terms!member}% *)
(* end thide *)
(* EX: Define an analogue to [get] for [hlist]s. *)
(* begin thide *)
Variable elm : A.
Inductive member : list A -> Type :=
| HFirst : forall ls, member (elm :: ls)
| HNext : forall x ls, member ls -> member (x :: ls).
(** Because the element [elm] that we are "searching for" in a list does not change across the constructors of [member], we simplify our definitions by making [elm] a local variable. In the definition of [member], we say that [elm] is found in any list that begins with [elm], and, if removing the first element of a list leaves [elm] present, then [elm] is present in the original list, too. The form looks much like a predicate for list membership, but we purposely define [member] in [Type] so that we may decompose its values to guide computations.
We can use [member] to adapt our definition of [get] to [hlist]s. The same basic [match] tricks apply. In the [HCons] case, we form a two-element convoy, passing both the data element [x] and the recursor for the sublist [mls'] to the result of the inner [match]. We did not need to do that in [get]'s definition because the types of list elements were not dependent there. *)
Fixpoint hget ls (mls : hlist ls) : member ls -> B elm :=
match mls with
| HNil => fun mem =>
match mem in member ls' return (match ls' with
| nil => B elm
| _ :: _ => unit
end) with
| HFirst _ => tt
| HNext _ _ _ => tt
end
| HCons _ _ x mls' => fun mem =>
match mem in member ls' return (match ls' with
| nil => Empty_set
| x' :: ls'' =>
B x' -> (member ls'' -> B elm)
-> B elm
end) with
| HFirst _ => fun x _ => x
| HNext _ _ mem' => fun _ get_mls' => get_mls' mem'
end x (hget mls')
end.
(* end thide *)
End hlist.
(* begin thide *)
Implicit Arguments HNil [A B].
Implicit Arguments HCons [A B x ls].
Implicit Arguments HFirst [A elm ls].
Implicit Arguments HNext [A elm x ls].
(* end thide *)
(** By putting the parameters [A] and [B] in [Type], we enable fancier kinds of polymorphism than in mainstream functional languages. For instance, one use of [hlist] is for the simple heterogeneous lists that we referred to earlier. *)
Definition someTypes : list Set := nat :: bool :: nil.
(* begin thide *)
Example someValues : hlist (fun T : Set => T) someTypes :=
HCons 5 (HCons true HNil).
Eval simpl in hget someValues HFirst.
(** %\vspace{-.15in}% [[
= 5
: (fun T : Set => T) nat
]]
*)
Eval simpl in hget someValues (HNext HFirst).
(** %\vspace{-.15in}% [[
= true
: (fun T : Set => T) bool
]]
*)
(** We can also build indexed lists of pairs in this way. *)
Example somePairs : hlist (fun T : Set => T * T)%type someTypes :=
HCons (1, 2) (HCons (true, false) HNil).
(** There are many other useful applications of heterogeneous lists, based on different choices of the first argument to [hlist]. *)
(* end thide *)
(** ** A Lambda Calculus Interpreter *)
(** Heterogeneous lists are very useful in implementing %\index{interpreters}%interpreters for functional programming languages. Using the types and operations we have already defined, it is trivial to write an interpreter for simply typed lambda calculus%\index{lambda calculus}%. Our interpreter can alternatively be thought of as a denotational semantics (but worry not if you are not familiar with such terminology from semantics).
We start with an algebraic datatype for types. *)
Inductive type : Set :=
| Unit : type
| Arrow : type -> type -> type.
(** Now we can define a type family for expressions. An [exp ts t] will stand for an expression that has type [t] and whose free variables have types in the list [ts]. We effectively use the de Bruijn index variable representation%~\cite{DeBruijn}%. Variables are represented as [member] values; that is, a variable is more or less a constructive proof that a particular type is found in the type environment. *)
Inductive exp : list type -> type -> Set :=
| Const : forall ts, exp ts Unit
(* begin thide *)
| Var : forall ts t, member t ts -> exp ts t
| App : forall ts dom ran, exp ts (Arrow dom ran) -> exp ts dom -> exp ts ran
| Abs : forall ts dom ran, exp (dom :: ts) ran -> exp ts (Arrow dom ran).
(* end thide *)
Implicit Arguments Const [ts].
(** We write a simple recursive function to translate [type]s into [Set]s. *)
Fixpoint typeDenote (t : type) : Set :=
match t with
| Unit => unit
| Arrow t1 t2 => typeDenote t1 -> typeDenote t2
end.
(** Now it is straightforward to write an expression interpreter. The type of the function, [expDenote], tells us that we translate expressions into functions from properly typed environments to final values. An environment for a free variable list [ts] is simply an [hlist typeDenote ts]. That is, for each free variable, the heterogeneous list that is the environment must have a value of the variable's associated type. We use [hget] to implement the [Var] case, and we use [HCons] to extend the environment in the [Abs] case. *)
(* EX: Define an interpreter for [exp]s. *)
(* begin thide *)
Fixpoint expDenote ts t (e : exp ts t) : hlist typeDenote ts -> typeDenote t :=
match e with
| Const _ => fun _ => tt
| Var _ _ mem => fun s => hget s mem
| App _ _ _ e1 e2 => fun s => (expDenote e1 s) (expDenote e2 s)
| Abs _ _ _ e' => fun s => fun x => expDenote e' (HCons x s)
end.
(** Like for previous examples, our interpreter is easy to run with [simpl]. *)
Eval simpl in expDenote Const HNil.
(** %\vspace{-.15in}% [[
= tt
: typeDenote Unit
]]
*)
Eval simpl in expDenote (Abs (dom := Unit) (Var HFirst)) HNil.
(** %\vspace{-.15in}% [[
= fun x : unit => x
: typeDenote (Arrow Unit Unit)
]]
*)
Eval simpl in expDenote (Abs (dom := Unit)
(Abs (dom := Unit) (Var (HNext HFirst)))) HNil.
(** %\vspace{-.15in}% [[
= fun x _ : unit => x
: typeDenote (Arrow Unit (Arrow Unit Unit))
]]
*)
Eval simpl in expDenote (Abs (dom := Unit) (Abs (dom := Unit) (Var HFirst))) HNil.
(** %\vspace{-.15in}% [[
= fun _ x0 : unit => x0
: typeDenote (Arrow Unit (Arrow Unit Unit))
]]
*)
Eval simpl in expDenote (App (Abs (Var HFirst)) Const) HNil.
(** %\vspace{-.15in}% [[
= tt
: typeDenote Unit
]]
*)
(* end thide *)
(** We are starting to develop the tools behind dependent typing's amazing advantage over alternative approaches in several important areas. Here, we have implemented complete syntax, typing rules, and evaluation semantics for simply typed lambda calculus without even needing to define a syntactic substitution operation. We did it all without a single line of proof, and our implementation is manifestly executable. Other, more common approaches to language formalization often state and prove explicit theorems about type safety of languages. In the above example, we got type safety, termination, and other meta-theorems for free, by reduction to CIC, which we know has those properties. *)
(** * Recursive Type Definitions *)
(** %\index{recursive type definition}%There is another style of datatype definition that leads to much simpler definitions of the [get] and [hget] definitions above. Because Coq supports "type-level computation," we can redo our inductive definitions as _recursive_ definitions. Here we will preface type names with the letter [f] to indicate that they are based on explicit recursive _function_ definitions. *)
(* EX: Come up with an alternate [ilist] definition that makes it easier to write [get]. *)
Section filist.
Variable A : Set.
(* begin thide *)
Fixpoint filist (n : nat) : Set :=
match n with
| O => unit
| S n' => A * filist n'
end%type.
(** We say that a list of length 0 has no contents, and a list of length [S n'] is a pair of a data value and a list of length [n']. *)
Fixpoint ffin (n : nat) : Set :=
match n with
| O => Empty_set
| S n' => option (ffin n')
end.
(** We express that there are no index values when [n = O], by defining such indices as type [Empty_set]; and we express that, at [n = S n'], there is a choice between picking the first element of the list (represented as [None]) or choosing a later element (represented by [Some idx], where [idx] is an index into the list tail). For instance, the three values of type [ffin 3] are [None], [Some None], and [Some (Some None)]. *)
Fixpoint fget (n : nat) : filist n -> ffin n -> A :=
match n with
| O => fun _ idx => match idx with end
| S n' => fun ls idx =>
match idx with
| None => fst ls
| Some idx' => fget n' (snd ls) idx'
end
end.
(** Our new [get] implementation needs only one dependent [match], and its annotation is inferred for us. Our choices of data structure implementations lead to just the right typing behavior for this new definition to work out. *)
(* end thide *)
End filist.
(** Heterogeneous lists are a little trickier to define with recursion, but we then reap similar benefits in simplicity of use. *)
(* EX: Come up with an alternate [hlist] definition that makes it easier to write [hget]. *)
Section fhlist.
Variable A : Type.
Variable B : A -> Type.
(* begin thide *)
Fixpoint fhlist (ls : list A) : Type :=
match ls with
| nil => unit
| x :: ls' => B x * fhlist ls'
end%type.
(** The definition of [fhlist] follows the definition of [filist], with the added wrinkle of dependently typed data elements. *)
Variable elm : A.
Fixpoint fmember (ls : list A) : Type :=
match ls with
| nil => Empty_set
| x :: ls' => (x = elm) + fmember ls'
end%type.
(** The definition of [fmember] follows the definition of [ffin]. Empty lists have no members, and member types for nonempty lists are built by adding one new option to the type of members of the list tail. While for [ffin] we needed no new information associated with the option that we add, here we need to know that the head of the list equals the element we are searching for. We express that idea with a sum type whose left branch is the appropriate equality proposition. Since we define [fmember] to live in [Type], we can insert [Prop] types as needed, because [Prop] is a subtype of [Type].
We know all of the tricks needed to write a first attempt at a [get] function for [fhlist]s.
[[
Fixpoint fhget (ls : list A) : fhlist ls -> fmember ls -> B elm :=
match ls with
| nil => fun _ idx => match idx with end
| _ :: ls' => fun mls idx =>
match idx with
| inl _ => fst mls
| inr idx' => fhget ls' (snd mls) idx'
end
end.
]]
%\vspace{-.15in}%Only one problem remains. The expression [fst mls] is not known to have the proper type. To demonstrate that it does, we need to use the proof available in the [inl] case of the inner [match]. *)
Fixpoint fhget (ls : list A) : fhlist ls -> fmember ls -> B elm :=
match ls with
| nil => fun _ idx => match idx with end
| _ :: ls' => fun mls idx =>
match idx with
| inl pf => match pf with
| eq_refl => fst mls
end
| inr idx' => fhget ls' (snd mls) idx'
end
end.
(** By pattern-matching on the equality proof [pf], we make that equality known to the type-checker. Exactly why this works can be seen by studying the definition of equality. *)
(* begin hide *)
(* begin thide *)
Definition foo := @eq_refl.
(* end thide *)
(* end hide *)
Print eq.
(** %\vspace{-.15in}% [[
Inductive eq (A : Type) (x : A) : A -> Prop := eq_refl : x = x
]]
In a proposition [x = y], we see that [x] is a parameter and [y] is a regular argument. The type of the constructor [eq_refl] shows that [y] can only ever be instantiated to [x]. Thus, within a pattern-match with [eq_refl], occurrences of [y] can be replaced with occurrences of [x] for typing purposes. *)
(* end thide *)
End fhlist.
Implicit Arguments fhget [A B elm ls].
(** How does one choose between the two data structure encoding strategies we have presented so far? Before answering that question in this chapter's final section, we introduce one further approach. *)
(** * Data Structures as Index Functions *)
(** %\index{index function}%Indexed lists can be useful in defining other inductive types with constructors that take variable numbers of arguments. In this section, we consider parameterized trees with arbitrary branching factor. *)
Section tree.
Variable A : Set.
Inductive tree : Set :=
| Leaf : A -> tree
| Node : forall n, ilist tree n -> tree.
End tree.
(** Every [Node] of a [tree] has a natural number argument, which gives the number of child trees in the second argument, typed with [ilist]. We can define two operations on trees of naturals: summing their elements and incrementing their elements. It is useful to define a generic fold function on [ilist]s first. *)
Section ifoldr.
Variables A B : Set.
Variable f : A -> B -> B.
Variable i : B.
Fixpoint ifoldr n (ls : ilist A n) : B :=
match ls with
| Nil => i
| Cons _ x ls' => f x (ifoldr ls')
end.
End ifoldr.
Fixpoint sum (t : tree nat) : nat :=
match t with
| Leaf n => n
| Node _ ls => ifoldr (fun t' n => sum t' + n) O ls
end.
Fixpoint inc (t : tree nat) : tree nat :=
match t with
| Leaf n => Leaf (S n)
| Node _ ls => Node (imap inc ls)
end.
(** Now we might like to prove that [inc] does not decrease a tree's [sum]. *)
Theorem sum_inc : forall t, sum (inc t) >= sum t.
(* begin thide *)
induction t; crush.
(** [[
n : nat
i : ilist (tree nat) n
============================
ifoldr (fun (t' : tree nat) (n0 : nat) => sum t' + n0) 0 (imap inc i) >=
ifoldr (fun (t' : tree nat) (n0 : nat) => sum t' + n0) 0 i
]]
We are left with a single subgoal which does not seem provable directly. This is the same problem that we met in Chapter 3 with other %\index{nested inductive type}%nested inductive types. *)
Check tree_ind.
(** %\vspace{-.15in}% [[
tree_ind
: forall (A : Set) (P : tree A -> Prop),
(forall a : A, P (Leaf a)) ->
(forall (n : nat) (i : ilist (tree A) n), P (Node i)) ->
forall t : tree A, P t
]]
The automatically generated induction principle is too weak. For the [Node] case, it gives us no inductive hypothesis. We could write our own induction principle, as we did in Chapter 3, but there is an easier way, if we are willing to alter the definition of [tree]. *)
Abort.
Reset tree.
(** First, let us try using our recursive definition of [ilist]s instead of the inductive version. *)
Section tree.
Variable A : Set.
(** %\vspace{-.15in}% [[
Inductive tree : Set :=
| Leaf : A -> tree
| Node : forall n, filist tree n -> tree.
]]
<<
Error: Non strictly positive occurrence of "tree" in
"forall n : nat, filist tree n -> tree"
>>
The special-case rule for nested datatypes only works with nested uses of other inductive types, which could be replaced with uses of new mutually inductive types. We defined [filist] recursively, so it may not be used in nested inductive definitions.
Our final solution uses yet another of the inductive definition techniques introduced in Chapter 3, %\index{reflexive inductive type}%reflexive types. Instead of merely using [fin] to get elements out of [ilist], we can _define_ [ilist] in terms of [fin]. For the reasons outlined above, it turns out to be easier to work with [ffin] in place of [fin]. *)
Inductive tree : Set :=
| Leaf : A -> tree
| Node : forall n, (ffin n -> tree) -> tree.
(** A [Node] is indexed by a natural number [n], and the node's [n] children are represented as a function from [ffin n] to trees, which is isomorphic to the [ilist]-based representation that we used above. *)
End tree.
Implicit Arguments Node [A n].
(** We can redefine [sum] and [inc] for our new [tree] type. Again, it is useful to define a generic fold function first. This time, it takes in a function whose domain is some [ffin] type, and it folds another function over the results of calling the first function at every possible [ffin] value. *)
Section rifoldr.
Variables A B : Set.
Variable f : A -> B -> B.
Variable i : B.
Fixpoint rifoldr (n : nat) : (ffin n -> A) -> B :=
match n with
| O => fun _ => i
| S n' => fun get => f (get None) (rifoldr n' (fun idx => get (Some idx)))
end.
End rifoldr.
Implicit Arguments rifoldr [A B n].
Fixpoint sum (t : tree nat) : nat :=
match t with
| Leaf n => n
| Node _ f => rifoldr plus O (fun idx => sum (f idx))
end.
Fixpoint inc (t : tree nat) : tree nat :=
match t with
| Leaf n => Leaf (S n)
| Node _ f => Node (fun idx => inc (f idx))
end.
(** Now we are ready to prove the theorem where we got stuck before. We will not need to define any new induction principle, but it _will_ be helpful to prove some lemmas. *)
Lemma plus_ge : forall x1 y1 x2 y2,
x1 >= x2
-> y1 >= y2
-> x1 + y1 >= x2 + y2.
crush.
Qed.
Lemma sum_inc' : forall n (f1 f2 : ffin n -> nat),
(forall idx, f1 idx >= f2 idx)
-> rifoldr plus O f1 >= rifoldr plus O f2.
Hint Resolve plus_ge.
induction n; crush.
Qed.
Theorem sum_inc : forall t, sum (inc t) >= sum t.
Hint Resolve sum_inc'.
induction t; crush.
Qed.
(* end thide *)
(** Even if Coq would generate complete induction principles automatically for nested inductive definitions like the one we started with, there would still be advantages to using this style of reflexive encoding. We see one of those advantages in the definition of [inc], where we did not need to use any kind of auxiliary function. In general, reflexive encodings often admit direct implementations of operations that would require recursion if performed with more traditional inductive data structures. *)
(** ** Another Interpreter Example *)
(** We develop another example of variable-arity constructors, in the form of optimization of a small expression language with a construct like Scheme's <<cond>>. Each of our conditional expressions takes a list of pairs of boolean tests and bodies. The value of the conditional comes from the body of the first test in the list to evaluate to [true]. To simplify the %\index{interpreters}%interpreter we will write, we force each conditional to include a final, default case. *)
Inductive type' : Type := Nat | Bool.
Inductive exp' : type' -> Type :=
| NConst : nat -> exp' Nat
| Plus : exp' Nat -> exp' Nat -> exp' Nat
| Eq : exp' Nat -> exp' Nat -> exp' Bool
| BConst : bool -> exp' Bool
(* begin thide *)
| Cond : forall n t, (ffin n -> exp' Bool)
-> (ffin n -> exp' t) -> exp' t -> exp' t.
(* end thide *)
(** A [Cond] is parameterized by a natural [n], which tells us how many cases this conditional has. The test expressions are represented with a function of type [ffin n -> exp' Bool], and the bodies are represented with a function of type [ffin n -> exp' t], where [t] is the overall type. The final [exp' t] argument is the default case. For example, here is an expression that successively checks whether [2 + 2 = 5] (returning 0 if so) or if [1 + 1 = 2] (returning 1 if so), returning 2 otherwise. *)
Example ex1 := Cond 2
(fun f => match f with
| None => Eq (Plus (NConst 2) (NConst 2)) (NConst 5)
| Some None => Eq (Plus (NConst 1) (NConst 1)) (NConst 2)
| Some (Some v) => match v with end
end)
(fun f => match f with
| None => NConst 0
| Some None => NConst 1
| Some (Some v) => match v with end
end)
(NConst 2).
(** We start implementing our interpreter with a standard type denotation function. *)
Definition type'Denote (t : type') : Set :=
match t with
| Nat => nat
| Bool => bool
end.
(** To implement the expression interpreter, it is useful to have the following function that implements the functionality of [Cond] without involving any syntax. *)
(* begin thide *)
Section cond.
Variable A : Set.
Variable default : A.
Fixpoint cond (n : nat) : (ffin n -> bool) -> (ffin n -> A) -> A :=
match n with
| O => fun _ _ => default
| S n' => fun tests bodies =>
if tests None
then bodies None
else cond n'
(fun idx => tests (Some idx))
(fun idx => bodies (Some idx))
end.
End cond.
Implicit Arguments cond [A n].
(* end thide *)
(** Now the expression interpreter is straightforward to write. *)
(* begin thide *)
Fixpoint exp'Denote t (e : exp' t) : type'Denote t :=
match e with
| NConst n => n
| Plus e1 e2 => exp'Denote e1 + exp'Denote e2
| Eq e1 e2 =>
if eq_nat_dec (exp'Denote e1) (exp'Denote e2) then true else false
| BConst b => b
| Cond _ _ tests bodies default =>
cond
(exp'Denote default)
(fun idx => exp'Denote (tests idx))
(fun idx => exp'Denote (bodies idx))
end.
(* begin hide *)
Reset exp'Denote.
(* end hide *)
(* end thide *)
(* begin hide *)
Fixpoint exp'Denote t (e : exp' t) : type'Denote t :=
match e with
| NConst n => n
| Plus e1 e2 => exp'Denote e1 + exp'Denote e2
| Eq e1 e2 =>
if eq_nat_dec (exp'Denote e1) (exp'Denote e2) then true else false
| BConst b => b
| Cond _ _ tests bodies default =>
(* begin thide *)
cond
(exp'Denote default)
(fun idx => exp'Denote (tests idx))
(fun idx => exp'Denote (bodies idx))
(* end thide *)
end.
(* end hide *)
(** We will implement a constant-folding function that optimizes conditionals, removing cases with known-[false] tests and cases that come after known-[true] tests. A function [cfoldCond] implements the heart of this logic. The convoy pattern is used again near the end of the implementation. *)
(* begin thide *)
Section cfoldCond.
Variable t : type'.
Variable default : exp' t.
Fixpoint cfoldCond (n : nat)
: (ffin n -> exp' Bool) -> (ffin n -> exp' t) -> exp' t :=
match n with
| O => fun _ _ => default
| S n' => fun tests bodies =>
match tests None return _ with
| BConst true => bodies None
| BConst false => cfoldCond n'
(fun idx => tests (Some idx))
(fun idx => bodies (Some idx))
| _ =>
let e := cfoldCond n'
(fun idx => tests (Some idx))
(fun idx => bodies (Some idx)) in
match e in exp' t return exp' t -> exp' t with
| Cond n _ tests' bodies' default' => fun body =>
Cond
(S n)
(fun idx => match idx with
| None => tests None
| Some idx => tests' idx
end)
(fun idx => match idx with
| None => body
| Some idx => bodies' idx
end)
default'
| e => fun body =>
Cond
1
(fun _ => tests None)
(fun _ => body)
e
end (bodies None)
end
end.
End cfoldCond.
Implicit Arguments cfoldCond [t n].
(* end thide *)
(** Like for the interpreters, most of the action was in this helper function, and [cfold] itself is easy to write. *)
(* begin thide *)
Fixpoint cfold t (e : exp' t) : exp' t :=
match e with
| NConst n => NConst n
| Plus e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp' Nat with
| NConst n1, NConst n2 => NConst (n1 + n2)
| _, _ => Plus e1' e2'
end
| Eq e1 e2 =>
let e1' := cfold e1 in
let e2' := cfold e2 in
match e1', e2' return exp' Bool with
| NConst n1, NConst n2 => BConst (if eq_nat_dec n1 n2 then true else false)
| _, _ => Eq e1' e2'
end
| BConst b => BConst b
| Cond _ _ tests bodies default =>
cfoldCond
(cfold default)
(fun idx => cfold (tests idx))
(fun idx => cfold (bodies idx))
end.
(* end thide *)
(* begin thide *)
(** To prove our final correctness theorem, it is useful to know that [cfoldCond] preserves expression meanings. The following lemma formalizes that property. The proof is a standard mostly automated one, with the only wrinkle being a guided instantiation of the quantifiers in the induction hypothesis. *)
Lemma cfoldCond_correct : forall t (default : exp' t)
n (tests : ffin n -> exp' Bool) (bodies : ffin n -> exp' t),
exp'Denote (cfoldCond default tests bodies)
= exp'Denote (Cond n tests bodies default).
induction n; crush;
match goal with
| [ IHn : forall tests bodies, _, tests : _ -> _, bodies : _ -> _ |- _ ] =>
specialize (IHn (fun idx => tests (Some idx)) (fun idx => bodies (Some idx)))
end;
repeat (match goal with
| [ |- context[match ?E with NConst _ => _ | _ => _ end] ] =>
dep_destruct E
| [ |- context[if ?B then _ else _] ] => destruct B
end; crush).
Qed.
(** It is also useful to know that the result of a call to [cond] is not changed by substituting new tests and bodies functions, so long as the new functions have the same input-output behavior as the old. It turns out that, in Coq, it is not possible to prove in general that functions related in this way are equal. We treat this issue with our discussion of axioms in a later chapter. For now, it suffices to prove that the particular function [cond] is _extensional_; that is, it is unaffected by substitution of functions with input-output equivalents. *)
Lemma cond_ext : forall (A : Set) (default : A) n (tests tests' : ffin n -> bool)
(bodies bodies' : ffin n -> A),
(forall idx, tests idx = tests' idx)
-> (forall idx, bodies idx = bodies' idx)
-> cond default tests bodies
= cond default tests' bodies'.
induction n; crush;
match goal with
| [ |- context[if ?E then _ else _] ] => destruct E
end; crush.
Qed.
(** Now the final theorem is easy to prove. *)
(* end thide *)
Theorem cfold_correct : forall t (e : exp' t),
exp'Denote (cfold e) = exp'Denote e.
(* begin thide *)
Hint Rewrite cfoldCond_correct.
Hint Resolve cond_ext.
induction e; crush;
repeat (match goal with
| [ |- context[cfold ?E] ] => dep_destruct (cfold E)
end; crush).
Qed.
(* end thide *)
(** We add our two lemmas as hints and perform standard automation with pattern-matching of subterms to destruct. *)
(** * Choosing Between Representations *)
(** It is not always clear which of these representation techniques to apply in a particular situation, but I will try to summarize the pros and cons of each.
Inductive types are often the most pleasant to work with, after someone has spent the time implementing some basic library functions for them, using fancy [match] annotations. Many aspects of Coq's logic and tactic support are specialized to deal with inductive types, and you may miss out if you use alternate encodings.
Recursive types usually involve much less initial effort, but they can be less convenient to use with proof automation. For instance, the [simpl] tactic (which is among the ingredients in [crush]) will sometimes be overzealous in simplifying uses of functions over recursive types. Consider a call [get l f], where variable [l] has type [filist A (S n)]. The type of [l] would be simplified to an explicit pair type. In a proof involving many recursive types, this kind of unhelpful "simplification" can lead to rapid bloat in the sizes of subgoals. Even worse, it can prevent syntactic pattern-matching, like in cases where [filist] is expected but a pair type is found in the "simplified" version. The same problem applies to applications of recursive functions to values in recursive types: the recursive function call may "simplify" when the top-level structure of the type index but not the recursive value is known, because such functions are generally defined by recursion on the index, not the value.
Another disadvantage of recursive types is that they only apply to type families whose indices determine their "skeletons." This is not true for all data structures; a good counterexample comes from the richly typed programming language syntax types we have used several times so far. The fact that a piece of syntax has type [Nat] tells us nothing about the tree structure of that syntax.
Finally, Coq type inference can be more helpful in constructing values in inductive types. Application of a particular constructor of that type tells Coq what to expect from the arguments, while, for instance, forming a generic pair does not make clear an intention to interpret the value as belonging to a particular recursive type. This downside can be mitigated to an extent by writing "constructor" functions for a recursive type, mirroring the definition of the corresponding inductive type.
Reflexive encodings of data types are seen relatively rarely. As our examples demonstrated, manipulating index values manually can lead to hard-to-read code. A normal inductive type is generally easier to work with, once someone has gone through the trouble of implementing an induction principle manually with the techniques we studied in Chapter 3. For small developments, avoiding that kind of coding can justify the use of reflexive data structures. There are also some useful instances of %\index{co-inductive types}%co-inductive definitions with nested data structures (e.g., lists of values in the co-inductive type) that can only be deconstructed effectively with reflexive encoding of the nested structures. *)
|
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// IP VLNV: xilinx.com:ip:sem:4.1
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(* X_CORE_INFO = "sem_v4_1_7_x7_sem_controller,Vivado 2016.3" *)
(* CHECK_LICENSE_TYPE = "sem_0,sem_v4_1_7_x7_sem_controller,{sem=unknown}" *)
(* CORE_GENERATION_INFO = "sem_0,sem_v4_1_7_x7_sem_controller,{x_ipProduct=Vivado 2016.3,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=sem,x_ipVersion=4.1,x_ipCoreRevision=7,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,[email protected](unknown),c_xdevice=kintex7,c_xpackage=ffg676,c_xspeedgrade=-2,c_xdevicefamily=kintex7,c_family=kintex7,c_device_array=33554435,c_icapwidth=32,c_eipwidth=40,c_farwidth=26,c_component_name=sem_0,c_clock_per=10000,c_feature_set=16,c_hardware_cfg=6,c_software_cfg=9,b_debug=0,b_cosim=0,b_df\
set=0,b_gen_user_app=0}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module sem_0 (
status_heartbeat,
status_initialization,
status_observation,
status_correction,
status_classification,
status_injection,
status_essential,
status_uncorrectable,
monitor_txdata,
monitor_txwrite,
monitor_txfull,
monitor_rxdata,
monitor_rxread,
monitor_rxempty,
icap_o,
icap_csib,
icap_rdwrb,
icap_i,
icap_clk,
icap_request,
icap_grant,
fecc_crcerr,
fecc_eccerr,
fecc_eccerrsingle,
fecc_syndromevalid,
fecc_syndrome,
fecc_far,
fecc_synbit,
fecc_synword
);
output wire status_heartbeat;
output wire status_initialization;
output wire status_observation;
output wire status_correction;
output wire status_classification;
output wire status_injection;
output wire status_essential;
output wire status_uncorrectable;
output wire [7 : 0] monitor_txdata;
output wire monitor_txwrite;
input wire monitor_txfull;
input wire [7 : 0] monitor_rxdata;
output wire monitor_rxread;
input wire monitor_rxempty;
input wire [31 : 0] icap_o;
output wire icap_csib;
output wire icap_rdwrb;
output wire [31 : 0] icap_i;
input wire icap_clk;
output wire icap_request;
input wire icap_grant;
input wire fecc_crcerr;
input wire fecc_eccerr;
input wire fecc_eccerrsingle;
input wire fecc_syndromevalid;
input wire [12 : 0] fecc_syndrome;
input wire [25 : 0] fecc_far;
input wire [4 : 0] fecc_synbit;
input wire [6 : 0] fecc_synword;
sem_v4_1_7_x7_sem_controller #(
.c_xdevice("kintex7"),
.c_xpackage("ffg676"),
.c_xspeedgrade("-2"),
.c_xdevicefamily("kintex7"),
.c_family("kintex7"),
.c_device_array(33554435),
.c_icapwidth(32),
.c_eipwidth(40),
.c_farwidth(26),
.c_component_name("sem_0"),
.c_clock_per(10000),
.c_feature_set(16),
.c_hardware_cfg(6),
.c_software_cfg(9),
.b_debug(0),
.b_cosim(0),
.b_dfset(0),
.b_gen_user_app(0)
) inst (
.status_heartbeat(status_heartbeat),
.status_initialization(status_initialization),
.status_observation(status_observation),
.status_correction(status_correction),
.status_classification(status_classification),
.status_injection(status_injection),
.status_essential(status_essential),
.status_uncorrectable(status_uncorrectable),
.fetch_txdata(),
.fetch_txwrite(),
.fetch_txfull(1'B0),
.fetch_rxdata(8'B0),
.fetch_rxread(),
.fetch_rxempty(1'B1),
.fetch_tbladdr(32'B0),
.monitor_txdata(monitor_txdata),
.monitor_txwrite(monitor_txwrite),
.monitor_txfull(monitor_txfull),
.monitor_rxdata(monitor_rxdata),
.monitor_rxread(monitor_rxread),
.monitor_rxempty(monitor_rxempty),
.inject_strobe(1'B0),
.inject_address(40'B0),
.icap_o(icap_o),
.icap_csib(icap_csib),
.icap_rdwrb(icap_rdwrb),
.icap_i(icap_i),
.icap_clk(icap_clk),
.icap_request(icap_request),
.icap_grant(icap_grant),
.fecc_crcerr(fecc_crcerr),
.fecc_eccerr(fecc_eccerr),
.fecc_eccerrsingle(fecc_eccerrsingle),
.fecc_syndromevalid(fecc_syndromevalid),
.fecc_syndrome(fecc_syndrome),
.fecc_far(fecc_far),
.fecc_synbit(fecc_synbit),
.fecc_synword(fecc_synword)
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__CLKDLYBUF4S50_SYMBOL_V
`define SKY130_FD_SC_HD__CLKDLYBUF4S50_SYMBOL_V
/**
* clkdlybuf4s50: Clock Delay Buffer 4-stage 0.59um length inner stage
* gates.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__clkdlybuf4s50 (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__CLKDLYBUF4S50_SYMBOL_V
|
`timescale 1 ns / 1 ns
//////////////////////////////////////////////////////////////////////////////////
// Company: Rehkopf
// Engineer: Rehkopf
//
// Create Date: 01:13:46 05/09/2009
// Design Name:
// Module Name: address
// Project Name:
// Target Devices:
// Tool versions:
// Description: Address logic w/ SaveRAM masking
//
// Dependencies:
//
// Revision:
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module address(
input CLK,
input [15:0] featurebits, // peripheral enable/disable
input [2:0] MAPPER, // MCU detected mapper
input [23:0] SNES_ADDR, // requested address from SNES
input [7:0] SNES_PA, // peripheral address from SNES
input SNES_ROMSEL, // ROMSEL from SNES
output [23:0] ROM_ADDR, // Address to request from SRAM0
output ROM_HIT, // enable SRAM0
output IS_SAVERAM, // address/CS mapped as SRAM?
output IS_ROM, // address mapped as ROM?
output IS_WRITABLE, // address somehow mapped as writable area?
input [23:0] SAVERAM_MASK,
input [23:0] ROM_MASK,
output msu_enable,
output srtc_enable,
output use_bsx,
output bsx_tristate,
input [14:0] bsx_regs,
output dspx_enable,
output dspx_dp_enable,
output dspx_a0,
output r213f_enable,
output r2100_hit,
output snescmd_enable,
output nmicmd_enable,
output return_vector_enable,
output branch1_enable,
output branch2_enable,
input [8:0] bs_page_offset,
input [9:0] bs_page,
input bs_page_enable
);
/* feature bits. see src/fpga_spi.c for mapping */
parameter [2:0]
FEAT_DSPX = 0,
FEAT_ST0010 = 1,
FEAT_SRTC = 2,
FEAT_MSU1 = 3,
FEAT_213F = 4,
FEAT_2100 = 6
;
wire [23:0] SRAM_SNES_ADDR;
/* currently supported mappers:
Index Mapper
000 HiROM
001 LoROM
010 ExHiROM (48-64Mbit)
011 BS-X
100 ExLoROM (StarOCean and SFA2)
110 brainfuck interleaved 96MBit Star Ocean =)
111 menu (ROM in upper SRAM)
*/
// active high to select ROM when
// bank is in range ($00-$3F) or ($80-$BF) and accessing upper half of bank ($8000-$FFFF) (LoROM)
assign IS_ROM = ((!SNES_ADDR[22] & SNES_ADDR[15])
// bank is in range ($C0-$FF) or ($40-$7D). Avoid WRAM $7E-$7F with /ROMSEL signal
|(SNES_ADDR[22] & ~SNES_ROMSEL));
// select backup RAM when
// ST0010 chip is present, SRAM is mapped to
assign IS_SAVERAM = SAVERAM_MASK[0]&(featurebits[FEAT_ST0010]?((SNES_ADDR[22:19] == 4'b1101) & &(~SNES_ADDR[15:12]) & SNES_ADDR[11])
// for HiROM, ExtHIROM or interleaved StarOcean -> $3X:[$6000-$7FFF] or $BX:[$6000-$7FFF]
:((MAPPER == 3'b000 || MAPPER == 3'b010 || MAPPER == 3'b110) ? (!SNES_ADDR[22] & SNES_ADDR[21] & &SNES_ADDR[14:13] & !SNES_ADDR[15])
// for ExtLoROM -> $7X:[$6000-$7FFF]
:(MAPPER == 3'b100) ? ((SNES_ADDR[23:19] == 5'b01110) && (SNES_ADDR[15:13] == 3'b011))
// LoROM: SRAM @ Bank 0x70-0x7d, 0xf0-0xff
// Offset 0000-7fff for ROM >= 32 MBit, otherwise 0000-ffff
:(MAPPER == 3'b001)? (&SNES_ADDR[22:20] & (~SNES_ROMSEL) & (~SNES_ADDR[15] | ~ROM_MASK[21]))
// BS-X: SRAM @ Bank 0x10-0x17 Offset 5000-5fff
:(MAPPER == 3'b011) ? ((SNES_ADDR[23:19] == 5'b00010) & (SNES_ADDR[15:12] == 4'b0101) )
// Menu mapper: 8Mbit "SRAM" @ Bank 0xf0-0xff (entire banks!)
:(MAPPER == 3'b111) ? (&SNES_ADDR[23:20])
: 1'b0));
/* BS-X has 4 MBits of extra RAM that can be mapped to various places */
// LoROM: A23 = r03/r04 A22 = r06 A21 = r05 A20 = 0 A19 = d/c
// HiROM: A23 = r03/r04 A22 = d/c A21 = r06 A20 = r05 A19 = 0
wire [2:0] BSX_PSRAM_BANK = {bsx_regs[6], bsx_regs[5], 1'b0};
wire [2:0] SNES_PSRAM_BANK = bsx_regs[2] ? SNES_ADDR[21:19] : SNES_ADDR[22:20];
wire BSX_PSRAM_LOHI = (bsx_regs[3] & ~SNES_ADDR[23]) | (bsx_regs[4] & SNES_ADDR[23]);
wire BSX_IS_PSRAM = BSX_PSRAM_LOHI
& (( IS_ROM & (SNES_PSRAM_BANK == BSX_PSRAM_BANK)
&(SNES_ADDR[15] | bsx_regs[2])
&(~(SNES_ADDR[19] & bsx_regs[2])))
| (bsx_regs[2]
? (SNES_ADDR[22:21] == 2'b01 & SNES_ADDR[15:13] == 3'b011)
: (~SNES_ROMSEL & &SNES_ADDR[22:20] & ~SNES_ADDR[15]))
);
wire BSX_IS_CARTROM = ((bsx_regs[7] & (SNES_ADDR[23:22] == 2'b00))
|(bsx_regs[8] & (SNES_ADDR[23:22] == 2'b10)))
& SNES_ADDR[15];
wire BSX_HOLE_LOHI = (bsx_regs[9] & ~SNES_ADDR[23]) | (bsx_regs[10] & SNES_ADDR[23]);
wire BSX_IS_HOLE = BSX_HOLE_LOHI
& (bsx_regs[2] ? (SNES_ADDR[21:20] == {bsx_regs[11], 1'b0})
: (SNES_ADDR[22:21] == {bsx_regs[11], 1'b0}));
assign bsx_tristate = (MAPPER == 3'b011) & ~BSX_IS_CARTROM & ~BSX_IS_PSRAM & BSX_IS_HOLE;
wire [23:0] BSX_ADDR = bsx_regs[2] ? {1'b0, SNES_ADDR[22:0]}
: {2'b00, SNES_ADDR[22:16], SNES_ADDR[14:0]};
// '1' to signal access to cartrigde writable range (Backup RAM or BS-X RAM)
assign IS_WRITABLE = IS_SAVERAM | ((MAPPER == 3'b011) & BSX_IS_PSRAM);
/* BSX regs:
Index Function
1 0=map flash to ROM area; 1=map PRAM to ROM area
2 1=HiROM; 0=LoROM
3 1=Mirror PRAM @60-6f:0000-ffff
5 1=DO NOT mirror PRAM @40-4f:0000-ffff
6 1=DO NOT mirror PRAM @50-5f:0000-ffff
7 1=map BSX cartridge ROM @00-1f:8000-ffff
8 1=map BSX cartridge ROM @80-9f:8000-ffff
*/
// HiROM
assign SRAM_SNES_ADDR = ((MAPPER == 3'b000) ? (IS_SAVERAM ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, SNES_ADDR[22:0]} & ROM_MASK))
// LoROM
:(MAPPER == 3'b001) ? (IS_SAVERAM ? 24'hE00000 + ({SNES_ADDR[20:16], SNES_ADDR[14:0]} & SAVERAM_MASK)
: ({1'b0, ~SNES_ADDR[23], SNES_ADDR[22:16], SNES_ADDR[14:0]} & ROM_MASK))
// ExtHiROM
:(MAPPER == 3'b010) ? (IS_SAVERAM ? 24'hE00000 + ({7'b0000000, SNES_ADDR[19:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
// ExtLoROM
:(MAPPER == 3'b100) ? (IS_SAVERAM ? 24'hE00000 + ({7'b0000000, SNES_ADDR[19:16], SNES_ADDR[12:0]} & SAVERAM_MASK)
: ({1'b0, !SNES_ADDR[23], SNES_ADDR[21:0]} & ROM_MASK))
// BS-X
:(MAPPER == 3'b011) ? (IS_SAVERAM ? 24'hE00000 + {SNES_ADDR[18:16], SNES_ADDR[11:0]}
: BSX_IS_CARTROM ? (24'h800000 + ({SNES_ADDR[22:16], SNES_ADDR[14:0]} & 24'h0fffff))
: BSX_IS_PSRAM ? (24'h400000 + (BSX_ADDR & 24'h07FFFF))
: bs_page_enable ? (24'h900000 + {bs_page,bs_page_offset})
: (BSX_ADDR & 24'h0fffff))
// interleaved StarOcean
:(MAPPER == 3'b110) ? (IS_SAVERAM ? 24'hE00000 + ((SNES_ADDR[14:0] - 15'h6000) & SAVERAM_MASK)
:(SNES_ADDR[15] ? ({1'b0, SNES_ADDR[23:16], SNES_ADDR[14:0]})
:({2'b10, SNES_ADDR[23], SNES_ADDR[21:16], SNES_ADDR[14:0]}) ) )
// menu
:(MAPPER == 3'b111) ? (IS_SAVERAM ? SNES_ADDR
: (({1'b0, SNES_ADDR[22:0]} & ROM_MASK) + 24'hC00000) )
: 24'b0);
assign ROM_ADDR = SRAM_SNES_ADDR;
// '1' when accesing PSRAM for ROM, Backup RAM, BS-X RAM
assign ROM_HIT = IS_ROM | IS_WRITABLE | bs_page_enable;
// '1' when accessing to MSU register map $2000:$2007
assign msu_enable = featurebits[FEAT_MSU1] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfff8) == 16'h2000));
// MAGNO -> disabled for S-DD1 core
//assign use_bsx = (MAPPER == 3'b011);
assign use_bsx = 1'b0;
// MAGNO -> disabled for S-DD1 core
//assign srtc_enable = featurebits[FEAT_SRTC] & (!SNES_ADDR[22] && ((SNES_ADDR[15:0] & 16'hfffe) == 16'h2800));
assign srtc_enable = 1'b0;
assign dspx_enable = 1'b0;
assign dspx_dp_enable = 1'b0;
assign dspx_a0 = featurebits[FEAT_DSPX]
?((MAPPER == 3'b001) ? SNES_ADDR[14]
:(MAPPER == 3'b000) ? SNES_ADDR[12]
:1'b1)
: featurebits[FEAT_ST0010]
? SNES_ADDR[0]
: 1'b1;
assign r213f_enable = featurebits[FEAT_213F] & (SNES_PA == 8'h3f);
assign r2100_hit = (SNES_PA == 8'h00);
assign snescmd_enable = ({SNES_ADDR[22], SNES_ADDR[15:9]} == 8'b0_0010101);
assign nmicmd_enable = (SNES_ADDR == 24'h002BF2);
assign return_vector_enable = (SNES_ADDR == 24'h002A5A);
assign branch1_enable = (SNES_ADDR == 24'h002A13);
assign branch2_enable = (SNES_ADDR == 24'h002A4D);
endmodule
|
//////////////////////////////////////////////////////////////////////////////////
//
// This file is part of the N64 RGB/YPbPr DAC project.
//
// Copyright (C) 2015-2021 by Peter Bartmann <[email protected]>
//
// N64 RGB/YPbPr DAC is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
//////////////////////////////////////////////////////////////////////////////////
//
// Company: Circuit-Board.de
// Engineer: borti4938
//
// Module Name: testpattern
// Project Name: N64 Advanced RGB/YPbPr DAC Mod
// Target Devices: Cyclone IV: EP4CE6E22 , EP4CE10E22
// Cyclone 10 LP: 10CL006YE144, 10CL010YE144
// Tool versions: Altera Quartus Prime
// Description:
//
//////////////////////////////////////////////////////////////////////////////////
module testpattern(
VCLK,
nRST,
palmode,
vdata_sync_valid_i,
vdata_sync_i,
vdata_valid_o,
vdata_o
);
`include "vh/n64adv_vparams.vh"
input VCLK;
input nRST;
input palmode;
input vdata_sync_valid_i;
input [3:0] vdata_sync_i;
output reg vdata_valid_o = 1'b0;
output reg [`VDATA_I_FU_SLICE] vdata_o = {vdata_width_i{1'b0}};
wire negedge_nVSYNC = vdata_o[3*color_width_i+3] & !vdata_sync_i[3];
wire negedge_nHSYNC = vdata_o[3*color_width_i+1] & !vdata_sync_i[1];
reg [8:0] vcnt = 9'b0;
reg [9:0] hcnt = 10'b0;
wire [8:0] pattern_vstart = palmode ? `VSTART_PAL_LX1 : `VSTART_NTSC_LX1;
wire [8:0] pattern_vstop = palmode ? `VSTOP_PAL_LX1 : `VSTOP_NTSC_LX1;
wire [9:0] pattern_hstart = palmode ? `HSTART_PAL : `HSTART_NTSC;
wire [9:0] pattern_hstop = palmode ? `HSTOP_PAL : `HSTOP_NTSC;
always @(posedge VCLK or negedge nRST)
if (!nRST) begin
vdata_valid_o <= 1'b0;
vdata_o <= {vdata_width_i{1'b0}};
vcnt <= 9'b0;
hcnt <= 10'b0;
end else begin
vdata_valid_o <= vdata_sync_valid_i;
if (vdata_sync_valid_i) begin
if (negedge_nHSYNC) begin
hcnt <= 10'b0;
vcnt <= &vcnt ? vcnt : vcnt + 1'b1;
end else begin
hcnt <= &hcnt ? hcnt : hcnt + 1'b1;
end
if (negedge_nVSYNC)
vcnt <= 9'b0;
if ((vcnt >= pattern_vstart) && (vcnt < pattern_vstop)) begin
if ((hcnt > pattern_hstart) && (hcnt < pattern_hstop))
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{~vdata_o[0]}};
else
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{1'b0}};
if (hcnt == pattern_hstart)
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{vcnt[0]}};
end else begin
vdata_o[`VDATA_I_CO_SLICE] <= {3*color_width_i{1'b0}};
end
vdata_o[`VDATA_I_SY_SLICE] <= vdata_sync_i;
end
end
endmodule
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_protocol_converter:2.1
// IP Revision: 9
(* X_CORE_INFO = "axi_protocol_converter_v2_1_9_axi_protocol_converter,Vivado 2016.2" *)
(* CHECK_LICENSE_TYPE = "dma_loopback_auto_pc_2,axi_protocol_converter_v2_1_9_axi_protocol_converter,{}" *)
(* CORE_GENERATION_INFO = "dma_loopback_auto_pc_2,axi_protocol_converter_v2_1_9_axi_protocol_converter,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=axi_protocol_converter,x_ipVersion=2.1,x_ipCoreRevision=9,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_M_AXI_PROTOCOL=1,C_S_AXI_PROTOCOL=0,C_IGNORE_ID=0,C_AXI_ID_WIDTH=3,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_SUPPORTS_WRITE=1,C_AXI_SUPPORTS_READ=1,C_AXI_SUPPORTS_USER_SIGNALS=1,C_AXI_AWUSER_WIDTH=4,C_AXI_ARUSER_WIDTH=4,C_AXI_WUSE\
R_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_TRANSLATION_MODE=2}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module dma_loopback_auto_pc_2 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *)
input wire [2 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *)
input wire [31 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *)
input wire [7 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *)
input wire [2 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *)
input wire [1 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *)
input wire [0 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *)
input wire [3 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *)
input wire [2 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *)
input wire [3 : 0] s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *)
input wire [3 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWUSER" *)
input wire [3 : 0] s_axi_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *)
input wire s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *)
output wire s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *)
input wire [63 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *)
input wire [7 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *)
input wire s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *)
input wire s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *)
output wire s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *)
output wire [2 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *)
output wire [1 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *)
output wire s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *)
input wire s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *)
input wire [2 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *)
input wire [31 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *)
input wire [7 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *)
input wire [2 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *)
input wire [1 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *)
input wire [0 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *)
input wire [3 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *)
input wire [2 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *)
input wire [3 : 0] s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *)
input wire [3 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARUSER" *)
input wire [3 : 0] s_axi_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *)
input wire s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *)
output wire s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *)
output wire [2 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *)
output wire [63 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *)
output wire [1 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *)
output wire s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *)
output wire s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *)
input wire s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *)
output wire [2 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *)
output wire [3 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *)
output wire [1 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWUSER" *)
output wire [3 : 0] m_axi_awuser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *)
output wire m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *)
input wire m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WID" *)
output wire [2 : 0] m_axi_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *)
output wire m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *)
output wire m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *)
input wire m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *)
input wire [2 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *)
input wire m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *)
output wire m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *)
output wire [2 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *)
output wire [3 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *)
output wire [1 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARUSER" *)
output wire [3 : 0] m_axi_aruser;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *)
output wire m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *)
input wire m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *)
input wire [2 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *)
input wire m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *)
input wire m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *)
output wire m_axi_rready;
axi_protocol_converter_v2_1_9_axi_protocol_converter #(
.C_FAMILY("zynq"),
.C_M_AXI_PROTOCOL(1),
.C_S_AXI_PROTOCOL(0),
.C_IGNORE_ID(0),
.C_AXI_ID_WIDTH(3),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_SUPPORTS_WRITE(1),
.C_AXI_SUPPORTS_READ(1),
.C_AXI_SUPPORTS_USER_SIGNALS(1),
.C_AXI_AWUSER_WIDTH(4),
.C_AXI_ARUSER_WIDTH(4),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_TRANSLATION_MODE(2)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awregion(s_axi_awregion),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(s_axi_awuser),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(3'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(1'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arregion(s_axi_arregion),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(s_axi_aruser),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(m_axi_awuser),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(m_axi_wid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(m_axi_aruser),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ns / 1ps
module alu_min( RST, CLK, ENA, RGA, RGB, RGZ, KEY, OPT);
input RST, CLK, ENA;
input [7:0]OPT,RGA,RGB;
output [7:0]RGZ;
input [1:0]KEY;
reg [7:0]RGZ;
/**********************************************************************
* PROTECTION CELLS *
*********************************************************************/
always@(posedge CLK)begin
if(RST) RGZ = 0;
else begin
case(OPT)
8'b00000001: RGZ = 0;
8'b00000010: RGZ = RGA + RGB;
8'b00000011: RGZ = RGA - RGB;
8'b00000011: RGZ = RGA^RGB;
8'b00000100: RGZ = RGA&RGB;
8'b00000101: RGZ = RGA|RGB;
8'b00000110: RGZ = RGA&&RGB;
8'b00000111: RGZ = RGA||RGB;
8'b00001000: RGZ = RGA+1;
8'b00001001: RGZ = RGA-1;
8'b00001010: RGZ = RGA<<1;
8'b00001011: RGZ = RGA>>1;
8'b00001100: RGZ = !RGA;
8'b00001101: RGZ = ~RGA;
8'b00001110: RGZ = RGA+RGA;
8'b00001111: RGZ = RGA-RGA;
8'b00010000: RGZ = RGB+RGZ;
8'b00010001: RGZ = RGB-RGZ;
8'b00010011: RGZ = RGB^RGZ;
8'b00010100: RGZ = RGB&RGZ;
8'b00010101: RGZ = RGB|RGZ;
8'b00010110: RGZ = RGB&&RGZ;
8'b00010111: RGZ = RGB||RGZ;
8'b00111000: RGZ = RGZ+1;
8'b00111001: RGZ = RGZ-1;
8'b00111010: RGZ = RGZ<<1;
8'b00111011: RGZ = RGZ>>1;
8'b00111100: RGZ = !RGZ;
8'b00111101: RGZ = ~RGZ;
8'b00111110: RGZ = RGB+RGZ;
8'b00111111: RGZ = RGB-RGZ;
8'b00100000: RGZ = RGA+RGB;
8'b00100001: RGZ = RGA-RGB;
8'b00100011: RGZ = RGA^RGB;
8'b00100100: RGZ = RGA&RGB;
8'b00100101: RGZ = RGA|RGB;
8'b00100110: RGZ = RGA&&RGB;
8'b00100111: RGZ = RGA||RGB;
8'b00101000: RGZ = RGA+1;
8'b00101001: RGZ = RGA-1;
8'b00101010: RGZ = RGA<<1;
8'b00101011: RGZ = RGA>>1;
8'b00101100: RGZ = !RGA;
8'b00101101: RGZ = ~RGA;
8'b00101110: RGZ = RGA+RGA;
8'b00101111: RGZ = RGA-RGA;
8'b00110000: RGZ = RGZ+RGA;
8'b00110001: RGZ = RGZ-RGA;
8'b00111000: RGZ = RGZ+1;
8'b00111001: RGZ = RGZ-1;
8'b00111010: RGZ = RGZ<<1;
8'b00111011: RGZ = RGZ>>1;
8'b00111100: RGZ = !RGZ;
8'b00111101: RGZ = ~RGZ;
8'b00111110: RGZ = RGZ+RGB;
8'b00111111: RGZ = RGZ-RGB;
/////////////////////////////////////////////////////
8'b01000000: RGZ=RGA+RGB;
8'b01000001: RGZ=RGA-RGB;
8'b01000010: RGZ=RGB-1;
8'b01000100: RGZ=RGA&&RGB;
8'b01000101: RGZ=RGA||RGB;
8'b01000110: RGZ=!RGA;
8'b01000111: RGZ=~RGA;
8'b01001000: RGZ=RGA&RGB;
8'b01001001: RGZ=RGA|RGB;
8'b01001010: RGZ=RGA^RGB;
8'b01001011: RGZ=RGA<<1;
8'b01001100: RGZ=RGA>>1;
8'b01001101: RGZ=RGA+1;
8'b01001110: RGZ=RGA-1;
8'b01001111: RGZ=RGA-1;
8'b01010000: RGZ=RGA+RGB;
8'b01010001: RGZ=RGA-RGB;
8'b01010010: RGZ=RGB-1;
8'b01010011: RGZ=RGA*RGB;
8'b01010100: RGZ=RGA&&RGB;
8'b01010101: RGZ=RGA||RGB;
8'b01010110: RGZ=!RGA;
8'b01010111: RGZ=~RGA;
8'b01011000: RGZ=RGA&RGB;
8'b01011001: RGZ=RGA|RGB;
8'b01011010: RGZ=RGA^RGB;
8'b01011011: RGZ=RGA<<1;
8'b01011100: RGZ=RGA>>1;
8'b01011101: RGZ=RGA+1;
8'b01011110: RGZ=RGA-1;
8'b01011111: RGZ=RGA-1;
8'b01100000: RGZ=RGA+RGB;
8'b01100001: RGZ=RGA-RGB;
8'b01100010: RGZ=RGB-1;
8'b01100100: RGZ=RGA&&RGB;
8'b01100101: RGZ=RGA||RGB;
8'b01100110: RGZ=!RGA;
8'b01100111: RGZ=~RGA;
8'b01101000: RGZ=RGA&RGB;
8'b01101001: RGZ=RGA|RGB;
8'b01101010: RGZ=RGA^RGB;
8'b01101011: RGZ=RGA<<1;
8'b01101100: RGZ=RGA>>1;
8'b01101101: RGZ=RGA+1;
8'b01101110: RGZ=RGA-1;
8'b01101111: RGZ=RGA-1;
8'b01110000: RGZ=RGA+RGB;
8'b01110001: RGZ=RGA-RGB;
8'b01110010: RGZ=RGB-1;
8'b01110011: RGZ=RGA*RGB;
8'b01110100: RGZ=RGA&&RGB;
8'b01110101: RGZ=RGA||RGB;
8'b01110110: RGZ=!RGA;
8'b01110111: RGZ=~RGA;
8'b01111000: RGZ=RGA&RGB;
8'b01111001: RGZ=RGA|RGB;
8'b01111010: RGZ=RGA^RGB;
8'b01111011: RGZ=RGA<<1;
8'b01111100: RGZ=RGA>>1;
8'b01111101: RGZ=RGA+1;
8'b01111110: RGZ=RGA-1;
8'b01111111: RGZ=RGA-1;
8'b10000000: RGZ=RGA+RGB;
8'b10000001: RGZ=RGA-RGB;
8'b10000010: RGZ=RGB-1;
8'b10000100: RGZ=RGA&&RGB;
8'b10000101: RGZ=RGA||RGB;
8'b10000110: RGZ=!RGA;
8'b10000111: RGZ=~RGA;
8'b10001000: RGZ=RGA&RGB;
8'b10001001: RGZ=RGA|RGB;
8'b10001010: RGZ=RGA^RGB;
8'b10001011: RGZ=RGA<<1;
8'b10001100: RGZ=RGA>>1;
8'b10001101: RGZ=RGA+1;
8'b10001110: RGZ=RGA-1;
8'b10001111: RGZ=RGA-1;
8'b10010000: RGZ=RGA+RGB;
8'b10010001: RGZ=RGA-RGB;
8'b10010010: RGZ=RGB-1;
8'b10010100: RGZ=RGA&&RGB;
8'b10010101: RGZ=RGA||RGB;
8'b10010110: RGZ=!RGA;
8'b10010111: RGZ=~RGA;
8'b10011000: RGZ=RGA&RGB;
8'b10011001: RGZ=RGA|RGB;
8'b10011010: RGZ=RGA^RGB;
8'b10011011: RGZ=RGA<<1;
8'b10011100: RGZ=RGA>>1;
8'b10011101: RGZ=RGA+1;
8'b10011110: RGZ=RGA-1;
8'b10011111: RGZ=RGA-1;
8'b10100000: RGZ=RGA+RGB;
8'b10100001: RGZ=RGA-RGB;
8'b10100010: RGZ=RGB-1;
8'b10100011: RGZ=RGA*RGB;
8'b10100100: RGZ=RGA&&RGB;
8'b10100101: RGZ=RGA||RGB;
8'b10100110: RGZ=!RGA;
8'b10100111: RGZ=~RGA;
8'b10101000: RGZ=RGA&RGB;
8'b10101001: RGZ=RGA|RGB;
8'b10101010: RGZ=RGA^RGB;
8'b10101011: RGZ=RGA<<1;
8'b10101100: RGZ=RGA>>1;
8'b10101101: RGZ=RGA+1;
8'b10101110: RGZ=RGA-1;
8'b10101111: RGZ=RGA-1;
8'b10110000: RGZ=RGA+RGB;
8'b10110001: RGZ=RGA-RGB;
8'b10110010: RGZ=RGB-1;
8'b10110011: RGZ=RGA*RGB;
8'b10110100: RGZ=RGA&&RGB;
8'b10110101: RGZ=RGA||RGB;
8'b10110110: RGZ=!RGA;
8'b10110111: RGZ=~RGA;
8'b10111000: RGZ=RGA&RGB;
8'b10111001: RGZ=RGA|RGB;
8'b10111010: RGZ=RGA^RGB;
8'b10111011: RGZ=RGA<<1;
8'b10111100: RGZ=RGA>>1;
8'b10111101: RGZ=RGA+1;
8'b10111110: RGZ=RGA-1;
8'b10111111: RGZ=RGA-1;
8'b11000000: RGZ=RGA+RGB;
8'b11000001: RGZ=RGA-RGB;
8'b11000010: RGZ=RGB-1;
8'b11000011: RGZ=RGA*RGB;
8'b11000100: RGZ=RGA&&RGB;
8'b11000101: RGZ=RGA||RGB;
8'b11000110: RGZ=!RGA;
8'b11000111: RGZ=~RGA;
8'b11001000: RGZ=RGA&RGB;
8'b11001001: RGZ=RGA|RGB;
8'b11001010: RGZ=RGA^RGB;
8'b11001011: RGZ=RGA<<1;
8'b11001100: RGZ=RGA>>1;
8'b11001101: RGZ=RGA+1;
8'b11001110: RGZ=RGA-1;
8'b11001111: RGZ=RGA-1;
8'b11010000: RGZ=RGA+RGB;
8'b11010001: RGZ=RGA-RGB;
8'b11010010: RGZ=RGB-1;
8'b11010011: RGZ=RGA*RGB;
8'b11010100: RGZ=RGA&&RGB;
8'b11010101: RGZ=RGA||RGB;
8'b11010110: RGZ=!RGA;
8'b11010111: RGZ=~RGA;
8'b11011000: RGZ=RGA&RGB;
8'b11011001: RGZ=RGA|RGB;
8'b11011010: RGZ=RGA^RGB;
8'b11011011: RGZ=RGA<<1;
8'b11011100: RGZ=RGA>>1;
8'b11011101: RGZ=RGA+1;
8'b11011110: RGZ=RGA-1;
8'b11011111: RGZ=RGA-1;
8'b11100000: RGZ=RGA+RGB;
8'b11100001: RGZ=RGA-RGB;
8'b11100010: RGZ=RGB-1;
8'b11100011: RGZ=RGA*RGB;
8'b11100100: RGZ=RGA&&RGB;
8'b11100101: RGZ=RGA||RGB;
8'b11100110: RGZ=!RGA;
8'b11100111: RGZ=~RGA;
8'b11101000: RGZ=RGA&RGB;
8'b11101001: RGZ=RGA|RGB;
8'b11101010: RGZ=RGA^RGB;
8'b11101011: RGZ=RGA<<1;
8'b11101100: RGZ=RGA>>1;
8'b11101101: RGZ=RGA+1;
8'b11101110: RGZ=RGA-1;
8'b11101111: RGZ=RGA-1;
8'b11110000: RGZ=RGA+RGB;
8'b11110001: RGZ=RGA-RGB;
8'b11110010: RGZ=RGB-1;
8'b11110011: RGZ=RGA*RGB;
8'b11110100: RGZ=RGA&&RGB;
8'b11110101: RGZ=RGA||RGB;
8'b11110110: RGZ=!RGA;
8'b11110111: RGZ=~RGA;
8'b11111000: RGZ=RGA&RGB;
8'b11111001: RGZ=RGA|RGB;
8'b11111010: RGZ=RGA^RGB;
8'b11111011: RGZ=RGA<<1;
8'b11111100: RGZ=RGA>>1;
8'b11111101: RGZ=RGA+1;
8'b11111110: RGZ=RGA-1;
8'b11111111: RGZ=RGA-1;
endcase
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* Physical cgannel (PC) allocator
* Allocates new physical-channels in the destination trunk
* for newly arrived packets.
*
* "unrestricted" allocation (Peh/Dally style)
*
* Takes place in two stages:
*
* stage 1. ** Physical channel selection **
* Each waiting packet determines which PC it will request.
* (v:1 arbitration).
*
*
* stage 2. ** PC Allocation **
* Access to each output PC is arbitrated (PV x PV:1 arbiters)
*
*/
`include "types.v"
module LAG_pl_unrestricted_allocator (req, // PC request
output_port, // for which trunk?
pl_status, // which PCs are free
pl_new, // newly allocated PC id.
pl_new_valid, // has new PC been allocated?
pl_allocated, // change PC status from free to allocated?
clk, rst_n);
// `include "LAG_functions.v";
parameter buf_len = 4;
parameter xs=4;
parameter ys=4;
parameter np=5;
parameter nv=4;
parameter alloc_stages = 1;
//-----
input [np-1:0][nv-1:0] req;
input output_port_t output_port [np-1:0][nv-1:0];
input [np-1:0][nv-1:0] pl_status;
output [np-1:0][nv-1:0][nv-1:0] pl_new;
output [np-1:0][nv-1:0] pl_new_valid;
output [np-1:0][nv-1:0] pl_allocated;
input clk, rst_n;
genvar i,j,k,l;
logic [np-1:0][nv-1:0][nv-1:0] stage1_request, stage1_grant, stage1_grant_reg;
logic [np-1:0][nv-1:0][nv-1:0] selected_status;
logic [np-1:0][nv-1:0][np-1:0][nv-1:0] stage2_requests, stage2_requests_, stage2_grants;
logic [np-1:0][nv-1:0][nv-1:0][np-1:0] pl_new_;
output_port_t output_port_reg [np-1:0][nv-1:0];
generate
for (i=0; i<np; i++) begin:foriports
for (j=0; j<nv; j++) begin:forpls
if (alloc_stages == 2) begin
//
// Select PL status bits at output port of interest (determine which PLs are free to be allocated)
//
assign selected_status[i][j] = pl_status[oh2bin(output_port[i][j])];
//
// Requests for PL selection arbiter
//
// Narrows requests from all possible PLs that could be requested to 1
//
for (k=0; k<nv; k++) begin:forpls2
// Request is made if
// (1) Packet requires PL
// (2) PL Mask bit is set
// (3) PL is currently free, so it can be allocated
//
assign stage1_request[i][j][k] = req[i][j] && selected_status[i][j][k] && ~(|stage1_grant_reg[i][j]);
end
always @(posedge clk) begin
if (!rst_n) begin
stage1_grant_reg[i][j] <= '0;
output_port_reg[i][j] <= '0;
end else begin
stage1_grant_reg[i][j] <= stage1_grant[i][j];
output_port_reg[i][j] <= output_port[i][j];
end
end
//
// second-stage of arbitration, determines who gets PL
//
for (k=0; k<np; k++) begin:fo
for (l=0; l<nv; l++) begin:fv
assign stage2_requests[k][l][i][j] = stage1_grant_reg[i][j][l] && output_port_reg[i][j][k];
assign stage2_requests_[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
end
end
assign pl_allocated[i][j] = |(stage2_requests_[i][j]);
end else if (alloc_stages == 1) begin
assign selected_status[i][j] = pl_status[oh2bin(output_port[i][j])];
for (k=0; k<nv; k++) begin:forpls2
assign stage1_request[i][j][k] = req[i][j] && selected_status[i][j][k];
end
for (k=0; k<np; k++) begin:fo
for (l=0; l<nv; l++) begin:fv
assign stage2_requests[k][l][i][j] = stage1_grant[i][j][l] && output_port[i][j][k];
end
end
assign pl_allocated[i][j] = |(stage2_requests[i][j]);
end else begin
//$display("Error: parameter <alloc_stages> can obtain only (1) or (2) values!");
//$finish;
end
//
// first-stage of arbitration
//
// Arbiter state doesn't mean much here as requests on different clock cycles may be associated
// with different output ports. plselect_arbstateupdate determines if state is always or never
// updated.
//
//This stage determines one of free physical channel in te destination trunk
//for each input physical channel that form request
matrix_arb #(.size(nv), .multistage(1))
stage1arb
(.request(stage1_request[i][j]),
.grant(stage1_grant[i][j]),
.success((plselect_arbstateupdate==1)),
.clk, .rst_n);
//Second stage of arbitration. Eaxh output PC has one np*nv:1 arbiter
//
// np*nv np*nv:1 tree arbiters
//
LAG_tree_arbiter #(.multistage(0),
.size(np*nv),
.groupsize(nv)) plarb
(.request(stage2_requests[i][j]),
.grant(stage2_grants[i][j]),
.clk, .rst_n);
for (k=0; k<np; k++) begin:fo2
for (l=0; l<nv; l++) begin:fv2
// could get pl x from any one of the output ports
assign pl_new_[i][j][l][k]=stage2_grants[k][l][i][j];
end
end
for (l=0; l<nv; l++) begin:fv3
assign pl_new[i][j][l]=|pl_new_[i][j][l];
end
assign pl_new_valid[i][j]=|pl_new[i][j];
end
end
endgenerate
endmodule // LAG_pl_unrestricted_allocator
|
// megafunction wizard: %ROM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: exam.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module exam (
address,
clock,
q);
input [11:0] address;
input clock;
output [11:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [11:0] sub_wire0;
wire [11:0] q = sub_wire0[11:0];
altsyncram altsyncram_component (
.address_a (address),
.clock0 (clock),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_a ({12{1'b1}}),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_a (1'b0),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_a = "NONE",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
altsyncram_component.init_file = "./sprites/exam.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 4096,
altsyncram_component.operation_mode = "ROM",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.widthad_a = 12,
altsyncram_component.width_a = 12,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "./sprites/exam.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
// Retrieval info: PRIVATE: WidthData NUMERIC "12"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "./sprites/exam.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "12"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 12 0 OUTPUT NODEFVAL "q[11..0]"
// Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 12 0 @q_a 0 0 12 0
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL exam_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
Require Export PredMonad.Reflection.OrderedType.
Require Export PredMonad.Reflection.OrderedContext.
Require Import Coq.Logic.ProofIrrelevance.
Import EqNotations.
Import ListNotations.
Import ProofIrrelevanceTheory.
(***
*** Ordered Expressions
***)
Inductive OVar A {RA:OTRelation A} : Ctx -> Type :=
| OVar_0 {ctx:Ctx} : OVar A (CtxCons A ctx)
| OVar_S {ctx:Ctx} {B} {RB:OTRelation B} :
OVar A ctx -> OVar A (CtxCons B ctx)
.
Arguments OVar_0 {A RA ctx}.
Arguments OVar_S {A RA ctx B RB} v.
(* Expressions to represent proper functions *)
Inductive OExpr (ctx:Ctx) : forall A {RA:OTRelation A}, Type :=
| Var {A} {RA:OTRelation A} {valid:ValidCtx ctx} (v:OVar A ctx) : OExpr ctx A
| Embed {A} {RA:OTRelation A} {OA:OType A} {valid:ValidCtx ctx} (a:A) : OExpr ctx A
| App {A B:Type} {RA:OTRelation A} {OA:OType A} {RB:OTRelation B} {OB:OType B}
(e1 : OExpr ctx (A -o> B)) (e2 : OExpr ctx A) : OExpr ctx B
| Lam {A B:Type} {RA:OTRelation A} {OA:OType A} {RB:OTRelation B} {OB:OType B}
{valid:ValidCtx ctx}
(e: OExpr (CtxCons A ctx) B) : OExpr ctx (A -o> B)
.
Arguments Var {ctx} {A RA valid} v.
Arguments Embed {ctx} {A RA OA valid} a.
Arguments App {ctx} {A B RA OA RB OB} e1 e2.
Arguments Lam {ctx} {A B RA OA RB OB valid} e.
(* The type of any OVar in a ValidCtx is always an OType *)
Instance OType_OVar_type A {RA} ctx (v:@OVar A RA ctx) `{ValidCtx ctx}
: OType A | 5.
Proof.
revert H; induction v; intro valid; destruct valid; [ | apply IHv ]; assumption.
Qed.
(* The type of any OExpr is always an OType *)
Instance OType_OExpr_type ctx A {RA} (e:@OExpr ctx A RA) : OType A | 5.
Proof.
induction e; eauto with typeclass_instances.
Qed.
(* The context of any OExpr is always valid *)
Instance ValidCtx_OExpr_ctx ctx A {RA} (e:@OExpr ctx A RA) : ValidCtx ctx | 5.
Proof.
induction e; assumption.
Qed.
(***
*** Semantics of Ordered Expressions
***)
(* The semantics of a variable *)
Fixpoint varSemantics {A} {RA:OTRelation A} {ctx} (v:OVar A ctx) :
CtxElem ctx -o> A :=
match v in OVar _ ctx return CtxElem ctx -o> A with
| OVar_0 => snd_pfun (A:=CtxElem _)
| OVar_S v' => compose_pfun fst_pfun (varSemantics v')
end.
Arguments varSemantics {A RA ctx} !v.
(* The semantics of an ordered expression *)
Fixpoint exprSemantics {ctx A} {RA:OTRelation A} (e:OExpr ctx A) :
CtxElem ctx -o> A :=
match e in OExpr _ A return CtxElem ctx -o> A with
| Var v => varSemantics v
| Embed a => const_pfun a
| App e1 e2 =>
pfun_apply (exprSemantics e1) (exprSemantics e2)
| Lam e => pfun_curry (exprSemantics e)
end.
Arguments exprSemantics {ctx A RA} !e.
(***
*** Relating Ordered Expressions
***)
(* Two expressions are related iff their semantics are *)
Definition oexpr_R {ctx A} {RA:OTRelation A} : relation (OExpr ctx A) :=
fun e1 e2 => exprSemantics e1 <o= exprSemantics e2.
Arguments oexpr_R {ctx A RA} e1 e2 /.
(* oexpr_R is a PreOrder *)
Instance PreOrder_oexpr_R ctx A {RA} : PreOrder (@oexpr_R ctx A RA).
Proof.
split; intro; intros;
assert (ValidCtx ctx) as valid; try eauto with typeclass_instances;
assert (OType A) as OA; try eauto with typeclass_instances;
unfold oexpr_R.
- reflexivity.
- transitivity (exprSemantics y); assumption.
Qed.
(* Two expressions are equivalent iff their semantics are *)
Definition oexpr_eq {ctx A} {RA:OTRelation A} : relation (OExpr ctx A) :=
fun e1 e2 => exprSemantics e1 =o= exprSemantics e2.
Arguments oexpr_eq {ctx A RA} e1 e2 /.
(* oexpr_eq is an Equivalence *)
Instance Equivalence_oexpr_eq ctx A {RA} : Equivalence (@oexpr_eq ctx A RA).
Proof.
constructor; intro; intros;
assert (ValidCtx ctx) as valid; try eauto with typeclass_instances;
assert (OType A) as OA; try eauto with typeclass_instances;
unfold oexpr_eq.
{ split; reflexivity. }
{ symmetry; assumption. }
{ transitivity (exprSemantics y); assumption. }
Qed.
Notation "x <e= y" :=
(oexpr_R x y) (no associativity, at level 70).
Notation "x =e= y" :=
(oexpr_eq x y) (no associativity, at level 70).
(* The Embed constructor is Proper w.r.t. ot_R and oexpr_R *)
Instance Proper_Embed ctx A {RA OA valid} :
Proper (ot_R ==> oexpr_R) (@Embed ctx A RA OA valid).
Proof.
intros a1 a2 Ra. simpl. rewrite Ra. reflexivity.
Qed.
(* The Embed constructor is Proper w.r.t. ot_equiv and oexpr_eq *)
Instance Proper_Embed_eq ctx A {RA OA valid} :
Proper (ot_equiv ==> oexpr_eq) (@Embed ctx A RA OA valid).
Proof.
intros a1 a2 Ra. simpl. rewrite Ra. reflexivity.
Qed.
(* The App constructor is Proper *)
Instance Proper_App ctx {A B RA OA RB OB} :
Proper (oexpr_R ==> oexpr_R ==> oexpr_R) (@App ctx A B RA OA RB OB).
Proof.
intros f1 f2 Rf a1 a2 Ra. simpl in * |- *.
apply Proper_pfun_apply; assumption.
Qed.
(* The App constructor is Proper for equivalence *)
Instance Proper_App_eq ctx {A B RA OA RB OB} :
Proper (oexpr_eq ==> oexpr_eq ==> oexpr_eq) (@App ctx A B RA OA RB OB).
Proof.
intros f1 f2 Rf a1 a2 Ra. simpl in * |- *.
apply Proper_pfun_apply_equiv; assumption.
Qed.
(* The Lam constructor is Proper *)
Instance Proper_Lam ctx {A B RA OA RB OB valid} :
Proper (oexpr_R ==> oexpr_R) (@Lam ctx A B RA OA RB OB valid).
Proof.
intros e1 e2 Re. simpl in * |- *.
apply Proper_pfun_curry; assumption.
Qed.
(* The Lam constructor is Proper for equivalence *)
Instance Proper_Lam_eq ctx {A B RA OA RB OB valid} :
Proper (oexpr_eq ==> oexpr_eq) (@Lam ctx A B RA OA RB OB valid).
Proof.
intros e1 e2 Re. simpl in * |- *.
apply Proper_pfun_curry_equiv; assumption.
Qed.
(***
*** Weakening for Ordered Expressions
***)
(* Weakening / lifting of ordered expression variables *)
Fixpoint weakenOVar w W {RW:OTRelation W} :
forall {ctx A} {RA:OTRelation A}, OVar A ctx -> OVar A (ctxInsert w W ctx) :=
match w return
forall ctx A {RA:OTRelation A}, OVar A ctx -> OVar A (ctxInsert w W ctx)
with
| 0 =>
fun _ _ {_} v => OVar_S v
| S w' =>
fun ctx A {RA} v =>
match v in OVar _ ctx return OVar A (ctxInsert (S w') W ctx) with
| OVar_0 => OVar_0
| OVar_S v' => OVar_S (weakenOVar w' W v')
end
end.
(* Correctness of weakenOVar: it is equivalent to weaken_pfun *)
Lemma weakenOVar_correct w W {RW} {OW:OType W} {ctx A RA}
{OA:OType A} {valid:ValidCtx ctx} v :
varSemantics (@weakenOVar w W RW ctx A RA v) =o=
compose_pfun (weaken_pfun w W ctx) (varSemantics v).
Proof.
revert ctx valid v; induction w; intros; [ | destruct v; destruct valid ]; simpl.
- reflexivity.
- rewrite compose_pair_snd. reflexivity.
- rewrite compose_compose_pfun. rewrite compose_pair_fst.
rewrite <- compose_compose_pfun. f_equiv. apply IHw. assumption.
Qed.
(* Weakening / lifting of ordered expressions *)
Fixpoint weakenOExpr w W {RW:OTRelation W} {OW:OType W} {ctx} {A} {RA:OTRelation A}
(e:OExpr ctx A) : OExpr (ctxInsert w W ctx) A :=
match e in OExpr _ A return OExpr (ctxInsert w W ctx) A with
| Var v => Var (weakenOVar w W v)
| Embed a => Embed a
| App e1 e2 => App (weakenOExpr w W e1) (weakenOExpr w W e2)
| Lam e => Lam (weakenOExpr (S w) W e)
end.
(* Correctness of weakenOExpr: it is equivalent to weaken_pfun *)
Lemma weakenOExpr_correct w W {RW} {OW:OType W} {ctx A RA} e :
exprSemantics (@weakenOExpr w W RW OW ctx A RA e) =o=
compose_pfun (weaken_pfun w W ctx) (exprSemantics e).
Proof.
revert w; induction e; intros; simpl.
- apply weakenOVar_correct; try assumption.
apply (OType_OExpr_type _ _ (Var v)).
- rewrite compose_f_const_pfun; [ reflexivity | typeclasses eauto ].
- assert (ValidCtx ctx) as valid; [ apply (ValidCtx_OExpr_ctx _ _ e1) | ].
rewrite compose_pfun_apply; try typeclasses eauto.
f_equiv; [ apply IHe1 | apply IHe2 ].
- rewrite compose_pfun_curry; try assumption. Unshelve.
f_equiv. apply (IHe (S w)).
typeclasses eauto.
Qed.
(* Proper-ness of weakenOExpr *)
Instance Proper_weakenOExpr w W {RW} {OW:OType W} {ctx A RA} :
Proper (oexpr_R ==> oexpr_R) (@weakenOExpr w W RW OW ctx A RA).
Proof.
intros e1 e2 Re. unfold oexpr_R.
assert (ValidCtx ctx) as valid; [ apply (ValidCtx_OExpr_ctx _ _ e1) | ].
assert (OType A) as OA; [ eauto with typeclass_instances | ].
repeat rewrite weakenOExpr_correct. f_equiv. assumption.
Qed.
(* Proper-ness of weakenOExpr *)
Instance Proper_weakenOExpr_equiv w W {RW} {OW:OType W} {ctx A RA} :
Proper (oexpr_eq ==> oexpr_eq) (@weakenOExpr w W RW OW ctx A RA).
Proof.
intros e1 e2 Re. destruct Re; split; apply Proper_weakenOExpr; assumption.
Qed.
(***
*** Substitution for Ordered Expressions
***)
(* Substitution for ordered expression variables *)
Fixpoint substOVar n {ctx} {A} {RA:OTRelation A} :
OVar A ctx ->
forall {valid:ValidCtx ctx}, OExpr (ctxSuffix n ctx) (ctxNth n ctx) ->
OExpr (ctxDelete n ctx) A :=
match n return
OVar A ctx ->
ValidCtx ctx -> OExpr (ctxSuffix n ctx) (ctxNth n ctx) ->
OExpr (ctxDelete n ctx) A
with
| 0 =>
fun v =>
match v in OVar _ ctx return
ValidCtx ctx ->
OExpr (ctxSuffix 0 ctx) (ctxNth 0 ctx) -> OExpr (ctxDelete 0 ctx) A
with
| OVar_0 => fun _ s => s
| OVar_S v' => fun valid _ => Var (valid:=proj2 valid) v'
end
| S n' =>
fun v =>
match v in OVar _ ctx return
ValidCtx ctx ->
OExpr (ctxSuffix (S n') ctx) (ctxNth (S n') ctx) ->
OExpr (ctxDelete (S n') ctx) A
with
| OVar_0 =>
fun valid _ =>
Var (valid:=ValidCtx_ctxDelete (S n') (CtxCons _ _)) OVar_0
| @OVar_S _ _ ctx' B RB v' =>
fun valid s =>
weakenOExpr 0 B (OW:=proj1 valid) (A:=A)
(substOVar n' v' (valid:=proj2 valid) s)
end
end.
Arguments substOVar !n {ctx A RA} !v {valid} s.
(* Correctness of substOVar: it is equivalent to subst_pfun *)
Lemma substOVar_correct n {ctx A RA} v {valid} s :
exprSemantics (@substOVar n ctx A RA v valid s) =o=
compose_pfun (subst_pfun ctx n (exprSemantics s)) (varSemantics v).
Proof.
revert n valid s; induction v; intros; destruct n; destruct valid; simpl.
- rewrite compose_pair_snd. reflexivity.
- rewrite compose_pair_snd. reflexivity.
- assert (OType A) as OA; [ eauto with typeclass_instances | ].
rewrite compose_compose_pfun. rewrite compose_pair_fst.
rewrite id_compose_pfun. reflexivity.
- assert (OType A) as OA; [ eauto with typeclass_instances | ].
rewrite (weakenOExpr_correct 0). unfold weaken_pfun.
rewrite compose_compose_pfun. rewrite compose_pair_fst.
rewrite <- compose_compose_pfun. f_equiv. apply IHv.
Qed.
(* substOVar is Proper in its s argument *)
Instance Proper_substOVar n {ctx A RA} v {valid} :
Proper (oexpr_R ==> oexpr_R) (@substOVar n ctx A RA v valid).
Proof.
intros s1 s2; simpl; intro Rs.
assert (OType A) as OA; [ eauto with typeclass_instances | ].
repeat rewrite substOVar_correct. rewrite Rs. reflexivity.
Qed.
(* substOVar is Proper w.r.t. equivalence in its s argument *)
Instance Proper_substOVar_equiv n {ctx A RA} v {valid} :
Proper (oexpr_eq ==> oexpr_eq) (@substOVar n ctx A RA v valid).
Proof.
intros s1 s2 Rs; destruct Rs; split; apply Proper_substOVar; assumption.
Qed.
(* Substitution for ordered expressions *)
Fixpoint substOExpr n {ctx} {A} {RA:OTRelation A} (e:OExpr ctx A) :
OExpr (ctxSuffix n ctx) (ctxNth n ctx) -> OExpr (ctxDelete n ctx) A :=
match e with
| Var v => fun s => substOVar n v s
| Embed a => fun _ => Embed a
| App e1 e2 => fun s => App (substOExpr n e1 s) (substOExpr n e2 s)
| Lam e => fun s => Lam (substOExpr (S n) e s)
end.
Arguments substOExpr n {ctx A RA} !e.
(* Correctness of substOExpr: it is equivalent to subst_pfun *)
Lemma substOExpr_correct n {ctx A RA} e s :
exprSemantics (@substOExpr n ctx A RA e s) =o=
compose_pfun (subst_pfun ctx n (exprSemantics s)) (exprSemantics e).
Proof.
revert n s; induction e; intros; simpl.
- apply substOVar_correct.
- symmetry. apply compose_f_const_pfun. eauto with typeclass_instances.
- assert (ValidCtx ctx) as valid; [ apply (ValidCtx_OExpr_ctx _ _ e1) | ].
rewrite compose_pfun_apply; eauto with typeclass_instances.
rewrite IHe1. rewrite IHe2. reflexivity.
- rewrite compose_pfun_curry; eauto with typeclass_instances.
rewrite (IHe (S n)). reflexivity.
Qed.
(* The Beta rule for ordered expressions *)
Lemma OExpr_Beta ctx `{ValidCtx ctx} A `{OType A} B `{OType B}
(e1: OExpr (CtxCons A ctx) B) (e2: OExpr ctx A) :
App (Lam e1) e2 =e= substOExpr 0 e1 e2.
Proof.
simpl. rewrite pfun_apply_pfun_curry; eauto with typeclass_instances.
rewrite (substOExpr_correct 0 (ctx:=CtxCons A ctx)). reflexivity.
Qed.
(***
*** Other OExpr Rewrite Rules
***)
Lemma OExpr_fst_pair ctx `{ValidCtx ctx} A `{OType A} B `{OType B}
(e1: OExpr ctx A) (e2: OExpr ctx B) :
App (Embed (ofst (A:=A) (B:=B))) (App (App (Embed opair) e1) e2) =e= e1.
Proof.
split; intros c1 c2 Rc; simpl; apply pfun_Proper; assumption.
Qed.
Lemma OExpr_snd_pair ctx `{ValidCtx ctx} A `{OType A} B `{OType B}
(e1: OExpr ctx A) (e2: OExpr ctx B) :
App (Embed (osnd (A:=A) (B:=B))) (App (App (Embed opair) e1) e2) =e= e2.
Proof.
split; intros c1 c2 Rc; simpl; apply pfun_Proper; assumption.
Qed.
Lemma OExpr_pair_eta ctx `{ValidCtx ctx} A `{OType A} B `{OType B}
(e: OExpr ctx (A*B)) :
(App (App (Embed opair) (App (Embed ofst) e)) (App (Embed osnd) e))
=e= e.
Proof.
split; intros c1 c2 Rc; split; simpl; rewrite Rc; reflexivity.
Qed.
Hint Rewrite OExpr_fst_pair OExpr_snd_pair OExpr_pair_eta : osimpl.
Opaque ofst osnd opair.
(***
*** Quoting Tactic for Ordered Expressions
***)
(* Specially-marked versions of fst and snd just used for quoting OExprs *)
Definition celem_head ctx A {RA} (celem: CtxElem (@CtxCons A RA ctx)) : A :=
let (_,head) := celem in head.
Definition celem_rest ctx A {RA} (celem: CtxElem (@CtxCons A RA ctx)) :
CtxElem ctx :=
let (rest,_) := celem in rest.
(* Typeclass for incrementally quoting functions into OExpr variables, by
peeling off the celem_rest projections one at a time and adding them as OVar_S
constructors to the input variable to build the output variable *)
Class QuotesToVar {ctx1 ctx2 A} {RA:OTRelation A}
(f: CtxElem ctx1 -> CtxElem ctx2) (vin: OVar A ctx2)
(vout: OVar A ctx1) : Prop :=
quotesToVar :
forall c, varSemantics vin @o@ (f c) = varSemantics vout @o@ c.
Instance QuotesToVar_Base {ctx A} {RA:OTRelation A} v :
QuotesToVar (ctx1:=ctx) (fun c => c) v v.
Proof.
intro; reflexivity.
Qed.
Instance QuotesToVar_Step {ctx1 ctx2 A B} {RA:OTRelation A} {RB:OTRelation B}
(f: CtxElem ctx1 -> CtxElem (CtxCons B ctx2)) vin vout
(q: QuotesToVar f (OVar_S vin) vout) :
QuotesToVar (fun c => celem_rest _ _ (f c)) vin vout.
Proof.
intro. apply q.
Qed.
(* Class for quoting functions to OExprs *)
Class QuotesTo {ctx A} {RA:OTRelation A}
(f: CtxElem ctx -> A) (e: OExpr ctx A) : Prop :=
quotesTo : forall c, f c =o= exprSemantics e @o@ c.
(* Logically the same as QuotesTo, but we never build lambdas in this one, i.e.,
this only builds "atomic" OExprs *)
Class QuotesToAtomic {ctx A} {RA:OTRelation A}
(f: CtxElem ctx -> A) (e: OExpr ctx A) : Prop :=
quotesToAtomic : forall c, f c =o= exprSemantics e @o@ c.
(* Quote any term of functional type to a lambda *)
Instance QuotesTo_Lam {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A -o> B) e
(q: QuotesTo (fun c => f (celem_rest _ _ c) @o@ (celem_head _ _ c)) e) :
QuotesTo f (Lam e) | 2.
Proof.
intros c; split; intros a1 a2 Ra; simpl.
- rewrite <- (q (c, a2)). rewrite Ra. reflexivity.
- rewrite <- (q (c, a1)). rewrite <- Ra. reflexivity.
Qed.
(* Special case: quote ofuns as lambdas, destructuring the ofun *)
Instance QuotesTo_Lam_ofun {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A -> B) prp e
(q: QuotesTo (fun c => f (celem_rest _ _ c) (celem_head _ _ c)) e) :
QuotesTo (fun c => ofun (f c) (prp:=prp c)) (Lam e) | 1.
Proof.
apply QuotesTo_Lam. assumption.
Qed.
(* Quote any non-function term as an atomic OExpr *)
Instance QuotesTo_Atomic {ctx A} {RA:OTRelation A} (f: CtxElem ctx -> A) e
(q: QuotesToAtomic f e) :
QuotesTo f e | 3 := q.
(*
Ltac solve_QuotesTo :=
first [ apply QuotesTo_Lam_ofun | apply QuotesTo_Lam | apply QuotesTo_Atomic ].
Hint Extern 1 (QuotesTo _ _) => solve_QuotesTo : typeclass_instances.
*)
(* Quote any use of celem_head as a var *)
Instance QuotesTo_Var {ctx1 ctx2 A} {RA:OTRelation A} {valid:ValidCtx ctx1}
(f: CtxElem ctx1 -> CtxElem (CtxCons A ctx2)) v
(q: QuotesToVar f OVar_0 v) :
QuotesToAtomic (fun c => celem_head ctx2 A (f c)) (Var v) | 1.
Proof.
assert (OType A) as OA; [ apply (OType_OVar_type _ _ v) | ].
intro. simpl. rewrite <- (q c). reflexivity.
Qed.
(* Special case for an eta-reduced celem_head application *)
Instance QuotesTo_Var0 {ctx A} `{OType A} {valid:ValidCtx ctx} :
QuotesToAtomic (celem_head ctx A) (Var OVar_0) | 1.
Proof.
intro. reflexivity.
Qed.
(* Quote applications as OExpr applications, where the function must still be
atomic but the argument need not be *)
Instance QuotesTo_App {ctx A B} `{OType A} `{OType B}
(f1: CtxElem ctx -> A -o> B) (f2: CtxElem ctx -> A) e1 e2
(q1: QuotesToAtomic f1 e1) (q2: QuotesTo f2 e2) :
QuotesToAtomic (fun c => (f1 c) @o@ (f2 c)) (App e1 e2) | 1.
Proof.
intro c. simpl. rewrite <- (q1 c). rewrite <- (q2 c). reflexivity.
Qed.
(* Quote ofuns in atomic position as lambdas *)
Instance QuotesTo_ofun {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A -> B) prp e
(q: QuotesTo (fun c => f (celem_rest _ _ c) (celem_head _ _ c)) e) :
QuotesToAtomic (fun c => ofun (f c) (prp:=prp c)) (Lam e) | 1.
Proof.
apply QuotesTo_Lam. assumption.
Qed.
(* Quote objects that are independent of the context as embedded objects, but at
low priority *)
Instance QuotesTo_Embed {ctx A} `{OType A} {valid:ValidCtx ctx} (a:A) :
QuotesToAtomic (fun _ => a) (Embed a) | 2.
Proof.
intro. reflexivity.
Qed.
(* Quote pairs as applications of opair *)
Instance QuotesTo_pair {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(a: CtxElem ctx -> A) (b: CtxElem ctx -> B) e1 e2
(q1: QuotesTo a e1) (q2: QuotesTo b e2) :
QuotesToAtomic (fun c => (a c, b c)) (App (App (Embed opair) e1) e2) | 1.
Proof.
intro c. simpl. rewrite <- (q1 c). rewrite <- (q2 c). reflexivity.
Qed.
(* Quote applications of fst as applications of ofst *)
Instance QuotesTo_fst {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A * B) e (q: QuotesTo f e) :
QuotesToAtomic (fun c => fst (f c)) (App (Embed ofst) e) | 1.
Proof.
intro c. simpl. rewrite <- (q c). reflexivity.
Qed.
(* Quote applications of fst as applications of ofst *)
Instance QuotesTo_snd {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A * B) e (q: QuotesTo f e) :
QuotesToAtomic (fun c => snd (f c)) (App (Embed osnd) e) | 1.
Proof.
intro c. simpl. rewrite <- (q c). reflexivity.
Qed.
(*
Instance QuotesTo_Lam1 {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A -> B) prp e
(q: QuotesTo (fun c => f (celem_rest _ _ c) (celem_head _ _ c)) e) :
QuotesTo (fun c => {| pfun_app := f c; pfun_Proper := prp c |}) (Lam e) | 1.
Proof.
intros c; split; intros a1 a2 Ra; simpl.
- rewrite <- (q (c, a2)). rewrite Ra. reflexivity.
- rewrite <- (q (c, a1)). rewrite <- Ra. reflexivity.
Qed.
Instance QuotesTo_Lam2 {ctx A B} `{OType A} `{OType B} `{ValidCtx ctx}
(f: CtxElem ctx -> A -> B) prp e
(q: QuotesTo (fun c => f (celem_rest _ _ c) (celem_head _ _ c)) e) :
QuotesTo (fun c => ofun (f c) (prp:=prp c)) (Lam e)| 1.
Proof.
unfold ofun. apply QuotesTo_Lam1. assumption.
Qed.
*)
Lemma oquote_R {A} {RA:OTRelation A} {f1 f2 : A} {e1 e2: OExpr CtxNil A}
{q1: QuotesTo (fun _ => f1) e1} {q2: QuotesTo (fun _ => f2) e2} :
e1 <e= e2 -> f1 <o= f2.
Proof.
intro R12. assert (OType A) as OT; [ eauto with typeclass_instances | ].
rewrite (q1 tt). rewrite (q2 tt). apply R12. reflexivity.
Defined.
Lemma oquote_eq {A} {RA:OTRelation A} {f1 f2 : A} {e1 e2: OExpr CtxNil A}
{q1: QuotesTo (fun _ => f1) e1} {q2: QuotesTo (fun _ => f2) e2} :
e1 =e= e2 -> f1 =o= f2.
Proof.
intros eq12; destruct eq12; split; apply oquote_R; assumption.
Defined.
(* Translate a problem about proper functions into one about OExprs, by
"quoting" both sides *)
Ltac oquote :=
lazymatch goal with
| |- ?e1 =o= ?e2 =>
apply oquote_eq
| |- ?e1 <o= ?e2 =>
apply oquote_R
end.
Ltac oexpr_simpl :=
rewrite_strat (bottomup (choice (OExpr_Beta ; eval simpl) (hints osimpl))).
(* Translate a problem about proper functions into one about OExprs by calling
oquote, simplify both sides using the osimpl rewrite database, and then try to
use reflexivity, going back to proper functions if that does not work *)
Ltac osimpl := simpl; oquote; try oexpr_simpl; try reflexivity; simpl.
Lemma product_proj1_test A `{OType A} B `{OType B} (a:A) (b:B) :
ofst @o@ (a ,o, b) =o= a.
osimpl.
Qed.
(***
*** Old Version of Quoting Tactic, using Ltac Directly
***)
(*
Tactic Notation "unify'" open_constr(t) open_constr(u) :=
assert(t = u); [refine eq_refl|].
*)
Lemma ltac_oquote_R {A RA} (e1 e2 : @OExpr CtxNil A RA) :
e1 <e= e2 -> (exprSemantics e1) @o@ tt <o= (exprSemantics e2) @o@ tt.
Proof.
intro R12. apply R12. reflexivity.
Qed.
Lemma ltac_oquote_eq {A RA} (e1 e2 : @OExpr CtxNil A RA) :
e1 =e= e2 -> (exprSemantics e1) @o@ tt =o= (exprSemantics e2) @o@ tt.
Proof.
intro equiv.
destruct equiv; split; apply ltac_oquote_R; assumption.
Qed.
(* Quote an expression that we think corresponds to a variable *)
Ltac ltac_quote_ovar f :=
lazymatch f with
| (fun (celem:_) => @celem_head ?ctx ?A ?RA _) =>
uconstr:(@OVar_0 A RA ctx)
| (fun (celem:?ctype) => @celem_rest ?ctx ?B ?RB ?f') =>
let qv := ltac_quote_ovar (fun (celem:ctype) => f') in
uconstr:(@OVar_S _ _ B RB ctx qv)
end.
(* Quote an expression-in-context, returning an OExpr that corresponds to it *)
Ltac ltac_quote_oexpr f :=
lazymatch f with
| (fun (celem:?ctype) => ?e1 @o@ ?e2) =>
let q1 := ltac_quote_oexpr (fun (celem:ctype) => e1) in
let q2 := ltac_quote_oexpr (fun (celem:ctype) => e2) in
uconstr:(App q1 q2)
| (fun (celem:CtxElem ?ctx) => ofun (fun (x:?A) =>?g)) =>
let e_rec :=
(eval simpl in
(fun (celem':CtxElem (CtxCons A ctx)) =>
(fun (celem:CtxElem ctx) (x:A) => g)
(celem_rest ctx A celem') (celem_head ctx A celem')))
in
let q := ltac_quote_oexpr e_rec in
uconstr:(Lam q)
| (fun (celem:?ctype) => celem_head _ _ _) =>
let qv := ltac_quote_ovar f in
uconstr:(Var qv)
| (fun (celem:?ctype) => celem_rest _ _ _) =>
let qv := ltac_quote_ovar f in
uconstr:(Var qv)
| (fun (celem:?ctype) => ?body) =>
(* For constants, just make a fresh evar, and let the unification of the
change tactic used later fill it in *)
uconstr:(Embed _)
(*
lazymatch type of (fun (celem:ctype) => body) with
| _ -> ?A =>
let ename := fresh "e" in
let res1 := evar (ename:_) in
let e := constr:(?ename) in
let res := unify' (fun celem => body) (fun _ => e) in
uconstr:(Embed (ctx:=CtxNil) e)
end
*)
end.
(* Quote an expression at the top level by quoting it in the empty context *)
Ltac ltac_quote_oexpr_top e :=
ltac_quote_oexpr (fun (celem:CtxElem CtxNil) => e).
(* Translate a problem about proper functions into one about OExprs, by
"quoting" both sides *)
Ltac ltac_oquote :=
lazymatch goal with
| |- ?e1 =o= ?e2 =>
let q1 := ltac_quote_oexpr_top e1 in
let q2 := ltac_quote_oexpr_top e2 in
(* idtac q1 "=e=" q2; *)
apply (ltac_oquote_eq q1 q2)
| |- ?e1 <o= ?e2 =>
let q1 := ltac_quote_oexpr_top e1 in
let q2 := ltac_quote_oexpr_top e2 in
apply (ltac_oquote_R q1 q2)
end.
(* Translate a problem about proper functions into one about OExprs by calling
oquote, simplify both sides using the osimpl rewrite database, and then try to
use reflexivity, going back to proper functions if that does not work *)
Ltac ltac_osimpl := ltac_oquote; try oexpr_simpl; try reflexivity; simpl.
(***
*** Testing the Quote Mechanism
***)
Module OQuoteTest.
(* A simple test case for constant terms *)
Lemma simple_quote_test A `{OType A} a : a =o= a.
osimpl.
Qed.
(* A simple test case with all 4 OExpr constructs, that does beta-reduction *)
Lemma beta_test A `{OType A} a : (ofun (A:=A) (fun x => x)) @o@ a =o= a.
simpl. osimpl.
Qed.
(* A test case with the first projection of a product *)
Lemma product_proj1_test A `{OType A} B `{OType B} (a:A) (b:B) :
ofst @o@ (a ,o, b) =o= a.
osimpl.
Qed.
(* A test case with with beta-reduction and projections + eta for products *)
Lemma beta_product_test A `{OType A} B `{OType B} (p:A*B) :
ofun (fun p => (osnd @o@ p ,o, ofst @o@ p)) @o@ (osnd @o@ p ,o, ofst @o@ p)
=o= p.
(* osimpl *)
(* NOTE: we write this out to see how long each step takes... *)
simpl. oquote. oexpr_simpl. reflexivity.
Qed.
Lemma double_lambda_test A `{OType A} :
(ofun (fun (f : A -o> A) => ofun (fun x => f @o@ x))) @o@ (ofun (fun y => y))
=o= ofun (fun x => x).
osimpl.
Qed.
(* A test case with with beta-reduction and projections for products *)
Lemma beta_product_test2 A `{OType A} B `{OType B} :
ofun (fun a =>
ofun (fun b =>
ofun (fun p => (osnd @o@ p ,o, ofst @o@ p)) @o@ (b ,o, a)))
=o= opair.
(* osimpl *)
(* NOTE: we write this out to see how long each step takes... *)
simpl. oquote. oexpr_simpl. reflexivity.
Qed.
End OQuoteTest.
|
(** * References: Typing Mutable References *)
(** Up to this point, we have considered a variety of _pure_
language features, including functional abstraction, basic types
such as numbers and booleans, and structured types such as records
and variants. These features form the backbone of most
programming languages -- including purely functional languages
such as Haskell and "mostly functional" languages such as ML, as
well as imperative languages such as C and object-oriented
languages such as Java, C[#], and Scala.
However, most practical languages also include various _impure_
features that cannot be described in the simple semantic framework
we have used so far. In particular, besides just yielding
results, computation in these languages may assign to mutable
variables (reference cells, arrays, mutable record fields, etc.);
perform input and output to files, displays, or network
connections; make non-local transfers of control via exceptions,
jumps, or continuations; engage in inter-process synchronization
and communication; and so on. In the literature on programming
languages, such "side effects" of computation are collectively
referred to as _computational effects_.
In this chapter, we'll see how one sort of computational effect --
mutable references -- can be added to the calculi we have studied.
The main extension will be dealing explicitly with a _store_ (or
_heap_) and _pointers_ that name store locations. This extension
is fairly straightforward to define; the most interesting part is
the refinement we need to make to the statement of the type
preservation theorem. *)
Require Import Coq.Arith.Arith.
Require Import Coq.omega.Omega.
Require Import Coq.Lists.List.
Import ListNotations.
Require Import SfLib.
Require Import Maps.
Require Import Smallstep.
(* ################################################################# *)
(** * Definitions *)
(** Pretty much every programming language provides some form of
assignment operation that changes the contents of a previously
allocated piece of storage. (Coq's internal language Gallina is a
rare exception!)
In some languages -- notably ML and its relatives -- the
mechanisms for name-binding and those for assignment are kept
separate. We can have a variable [x] whose _value_ is the number
[5], or we can have a variable [y] whose value is a
_reference_ (or _pointer_) to a mutable cell whose current
contents is [5]. These are different things, and the difference
is visible to the programmer. We can add [x] to another number,
but not assign to it. We can use [y] to assign a new value to the
cell that it points to (by writing [y:=84]), but we cannot use [y]
directly as an argument to an operation like [+]. Instead, we
must explicitly _dereference_ it, writing [!y] to obtain its
current contents.
In most other languages -- in particular, in all members of the C
family, including Java -- _every_ variable name refers to a
mutable cell, and the operation of dereferencing a variable to
obtain its current contents is implicit.
For purposes of formal study, it is useful to keep these
mechanisms separate. The development in this chapter will closely
follow ML's model. Applying the lessons learned here to C-like
languages is a straightforward matter of collapsing some
distinctions and rendering some operations such as dereferencing
implicit instead of explicit. *)
(* ################################################################# *)
(** * Syntax *)
(** In this chapter, we study adding mutable references to the
simply-typed lambda calculus with natural numbers. *)
Module STLCRef.
(** The basic operations on references are _allocation_,
_dereferencing_, and _assignment_.
- To allocate a reference, we use the [ref] operator, providing
an initial value for the new cell. For example, [ref 5]
creates a new cell containing the value [5], and reduces to
a reference to that cell.
- To read the current value of this cell, we use the
dereferencing operator [!]; for example, [!(ref 5)] reduces
to [5].
- To change the value stored in a cell, we use the assignment
operator. If [r] is a reference, [r := 7] will store the
value [7] in the cell referenced by [r]. *)
(* ----------------------------------------------------------------- *)
(** *** Types *)
(** We start with the simply typed lambda calculus over the
natural numbers. Besides the base natural number type and arrow
types, we need to add two more types to deal with
references. First, we need the _unit type_, which we will use as
the result type of an assignment operation. We then add
_reference types_. *)
(** If [T] is a type, then [Ref T] is the type of references to
cells holding values of type [T].
T ::= Nat
| Unit
| T -> T
| Ref T
*)
Inductive ty : Type :=
| TNat : ty
| TUnit : ty
| TArrow : ty -> ty -> ty
| TRef : ty -> ty.
(* ----------------------------------------------------------------- *)
(** *** Terms *)
(** Besides variables, abstractions, applications,
natural-number-related terms, and [unit], we need four more sorts
of terms in order to handle mutable references:
t ::= ... Terms
| ref t allocation
| !t dereference
| t := t assignment
| l location
*)
Inductive tm : Type :=
(* STLC with numbers: *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* New terms: *)
| tunit : tm
| tref : tm -> tm
| tderef : tm -> tm
| tassign : tm -> tm -> tm
| tloc : nat -> tm.
(** Intuitively:
- [ref t] (formally, [tref t]) allocates a new reference cell
with the value [t] and reduces to the location of the newly
allocated cell;
- [!t] (formally, [tderef t]) reduces to the contents of the
cell referenced by [t];
- [t1 := t2] (formally, [tassign t1 t2]) assigns [t2] to the
cell referenced by [t1]; and
- [l] (formally, [tloc l]) is a reference to the cell at
location [l]. We'll discuss locations later. *)
(** In informal examples, we'll also freely use the extensions
of the STLC developed in the [MoreStlc] chapter; however, to keep
the proofs small, we won't bother formalizing them again here. (It
would be easy to do so, since there are no very interesting
interactions between those features and references.) *)
(* ----------------------------------------------------------------- *)
(** *** Typing (Preview) *)
(** Informally, the typing rules for allocation, dereferencing, and
assignment will look like this:
Gamma |- t1 : T1
------------------------ (T_Ref)
Gamma |- ref t1 : Ref T1
Gamma |- t1 : Ref T11
--------------------- (T_Deref)
Gamma |- !t1 : T11
Gamma |- t1 : Ref T11
Gamma |- t2 : T11
------------------------ (T_Assign)
Gamma |- t1 := t2 : Unit
The rule for locations will require a bit more machinery, and this
will motivate some changes to the other rules; we'll come back to
this later. *)
(* ----------------------------------------------------------------- *)
(** *** Values and Substitution *)
(** Besides abstractions and numbers, we have two new types of values:
the unit value, and locations. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_nat : forall n,
value (tnat n)
| v_unit :
value tunit
| v_loc : forall l,
value (tloc l).
Hint Constructors value.
(** Extending substitution to handle the new syntax of terms is
straightforward. *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if beq_id x x' then s else t
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tabs x' T t1 =>
if beq_id x x' then t else tabs x' T (subst x s t1)
| tnat n =>
t
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tunit =>
t
| tref t1 =>
tref (subst x s t1)
| tderef t1 =>
tderef (subst x s t1)
| tassign t1 t2 =>
tassign (subst x s t1) (subst x s t2)
| tloc _ =>
t
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ################################################################# *)
(** * Pragmatics *)
(* ================================================================= *)
(** ** Side Effects and Sequencing *)
(** The fact that we've chosen the result of an assignment
expression to be the trivial value [unit] allows a nice
abbreviation for _sequencing_. For example, we can write
r:=succ(!r); !r
as an abbreviation for
(\x:Unit. !r) (r:=succ(!r)).
This has the effect of reducing two expressions in order and
returning the value of the second. Restricting the type of the
first expression to [Unit] helps the typechecker to catch some
silly errors by permitting us to throw away the first value only
if it is really guaranteed to be trivial.
Notice that, if the second expression is also an assignment, then
the type of the whole sequence will be [Unit], so we can validly
place it to the left of another [;] to build longer sequences of
assignments:
r:=succ(!r); r:=succ(!r); r:=succ(!r); r:=succ(!r); !r
*)
(** Formally, we introduce sequencing as a _derived form_
[tseq] that expands into an abstraction and an application. *)
Definition tseq t1 t2 :=
tapp (tabs (Id 0) TUnit t2) t1.
(* ================================================================= *)
(** ** References and Aliasing *)
(** It is important to bear in mind the difference between the
_reference_ that is bound to some variable [r] and the _cell_
in the store that is pointed to by this reference.
If we make a copy of [r], for example by binding its value to
another variable [s], what gets copied is only the _reference_,
not the contents of the cell itself.
For example, after reducing
let r = ref 5 in
let s = r in
s := 82;
(!r)+1
the cell referenced by [r] will contain the value [82], while the
result of the whole expression will be [83]. The references [r]
and [s] are said to be _aliases_ for the same cell.
The possibility of aliasing can make programs with references
quite tricky to reason about. For example, the expression
r := 5; r := !s
assigns [5] to [r] and then immediately overwrites it with [s]'s
current value; this has exactly the same effect as the single
assignment
r := !s
_unless_ we happen to do it in a context where [r] and [s] are
aliases for the same cell! *)
(* ================================================================= *)
(** ** Shared State *)
(** Of course, aliasing is also a large part of what makes references
useful. In particular, it allows us to set up "implicit
communication channels" -- shared state -- between different parts
of a program. For example, suppose we define a reference cell and
two functions that manipulate its contents:
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
...
*)
(** Note that, since their argument types are [Unit], the
arguments to the abstractions in the definitions of [incc] and
[decc] are not providing any useful information to the bodies of
these functions (using the wildcard [_] as the name of the bound
variable is a reminder of this). Instead, their purpose of these
abstractions is to "slow down" the execution of the function
bodies. Since function abstractions are values, the two [let]s are
executed simply by binding these functions to the names [incc] and
[decc], rather than by actually incrementing or decrementing [c].
Later, each caddll to one of these functions results in its body
being executed once and performing the appropriate mutation on
[c]. Such functions are often called _thunks_.
In the context of these declarations, calling [incc] results in
changes to [c] that can be observed by calling [decc]. For
example, if we replace the [...] with [(incc unit; incc unit; decc
unit)], the result of the whole program will be [1]. *)
(* ================================================================= *)
(** ** Objects *)
(** We can go a step further and write a _function_ that creates [c],
[incc], and [decc], packages [incc] and [decc] together into a
record, and returns this record:
newcounter =
\_:Unit.
let c = ref 0 in
let incc = \_:Unit. (c := succ (!c); !c) in
let decc = \_:Unit. (c := pred (!c); !c) in
{i=incc, d=decc}
*)
(** Now, each time we call [newcounter], we get a new record of
functions that share access to the same storage cell [c]. The
caller of [newcounter] can't get at this storage cell directly,
but can affect it indirectly by calling the two functions. In
other words, we've created a simple form of _object_.
let c1 = newcounter unit in
let c2 = newcounter unit in
// Note that we've allocated two separate storage cells now!
let r1 = c1.i unit in
let r2 = c2.i unit in
r2 // yields 1, not 2!
*)
(** **** Exercise: 1 star (store_draw) *)
(** Draw (on paper) the contents of the store at the point in
execution where the first two [let]s have finished and the third
one is about to begin. *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** References to Compound Types *)
(** A reference cell need not contain just a number: the primitives
we've defined above allow us to create references to values of any
type, including functions. For example, we can use references to
functions to give an (inefficient) implementation of arrays
of numbers, as follows. Write [NatArray] for the type
[Ref (Nat->Nat)].
Recall the [equal] function from the [MoreStlc] chapter:
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
To build a new array, we allocate a reference cell and fill
it with a function that, when given an index, always returns [0].
newarray = \_:Unit. ref (\n:Nat.0)
To look up an element of an array, we simply apply
the function to the desired index.
lookup = \a:NatArray. \n:Nat. (!a) n
The interesting part of the encoding is the [update] function. It
takes an array, an index, and a new value to be stored at that index, and
does its job by creating (and storing in the reference) a new function
that, when it is asked for the value at this very index, returns the new
value that was given to [update], while on all other indices it passes the
lookup to the function that was previously stored in the reference.
update = \a:NatArray. \m:Nat. \v:Nat.
let oldf = !a in
a := (\n:Nat. if equal m n then v else oldf n);
References to values containing other references can also be very
useful, allowing us to define data structures such as mutable
lists and trees. *)
(** **** Exercise: 2 stars, recommended (compact_update) *)
(** If we defined [update] more compactly like this
update = \a:NatArray. \m:Nat. \v:Nat.
a := (\n:Nat. if equal m n then v else (!a) n)
would it behave the same? *)
(* FILL IN HERE *)
(** [] *)
(* ================================================================= *)
(** ** Null References *)
(** There is one final significant difference between our
references and C-style mutable variables: in C-like languages,
variables holding pointers into the heap may sometimes have the
value [NULL]. Dereferencing such a "null pointer" is an error,
and results either in a clean exception (Java and C[#]) or in
arbitrary and possibly insecure behavior (C and relatives like
C++). Null pointers cause significant trouble in C-like
languages: the fact that any pointer might be null means that any
dereference operation in the program can potentially fail.
Even in ML-like languages, there are occasionally situations where
we may or may not have a valid pointer in our hands. Fortunately,
there is no need to extend the basic mechanisms of references to
represent such situations: the sum types introduced in the
[MoreStlc] chapter already give us what we need.
First, we can use sums to build an analog of the [option] types
introduced in the [Lists] chapter. Define [Option T] to be an
abbreviation for [Unit + T].
Then a "nullable reference to a [T]" is simply an element of the
type [Option (Ref T)]. *)
(* ================================================================= *)
(** ** Garbage Collection *)
(** A last issue that we should mention before we move on with
formalizing references is storage _de_-allocation. We have not
provided any primitives for freeing reference cells when they are
no longer needed. Instead, like many modern languages (including
ML and Java) we rely on the run-time system to perform _garbage
collection_, automatically identifying and reusing cells that can
no longer be reached by the program.
This is _not_ just a question of taste in language design: it is
extremely difficult to achieve type safety in the presence of an
explicit deallocation operation. One reason for this is the
familiar _dangling reference_ problem: we allocate a cell holding
a number, save a reference to it in some data structure, use it
for a while, then deallocate it and allocate a new cell holding a
boolean, possibly reusing the same storage. Now we can have two
names for the same storage cell -- one with type [Ref Nat] and the
other with type [Ref Bool]. *)
(** **** Exercise: 1 star (type_safety_violation) *)
(** Show how this can lead to a violation of type safety. *)
(* FILL IN HERE *)
(** [] *)
(* ################################################################# *)
(** * Operational Semantics *)
(* ================================================================= *)
(** ** Locations *)
(** The most subtle aspect of the treatment of references
appears when we consider how to formalize their operational
behavior. One way to see why is to ask, "What should be the
_values_ of type [Ref T]?" The crucial observation that we need
to take into account is that reduci a [ref] operator should
_do_ something -- namely, allocate some storage -- and the result
of the operation should be a reference to this storage.
What, then, is a reference?
The run-time store in most programming-language implementations is
essentially just a big array of bytes. The run-time system keeps
track of which parts of this array are currently in use; when we
need to allocate a new reference cell, we allocate a large enough
segment from the free region of the store (4 bytes for integer
cells, 8 bytes for cells storing [Float]s, etc.), record somewhere
that it is being used, and return the index (typically, a 32- or
64-bit integer) of the start of the newly allocated region. These
indices are references.
For present purposes, there is no need to be quite so concrete.
We can think of the store as an array of _values_, rather than an
array of bytes, abstracting away from the different sizes of the
run-time representations of different values. A reference, then,
is simply an index into the store. (If we like, we can even
abstract away from the fact that these indices are numbers, but
for purposes of formalization in Coq it is convenient to use
numbers.) We use the word _location_ instead of _reference_ or
_pointer_ to emphasize this abstract quality.
Treating locations abstractly in this way will prevent us from
modeling the _pointer arithmetic_ found in low-level languages
such as C. This limitation is intentional. While pointer
arithmetic is occasionally very useful, especially for
implementing low-level services such as garbage collectors, it
cannot be tracked by most type systems: knowing that location [n]
in the store contains a [float] doesn't tell us anything useful
about the type of location [n+4]. In C, pointer arithmetic is a
notorious source of type-safety violations. *)
(* ================================================================= *)
(** ** Stores *)
(** Recall that, in the small-step operational semantics for
IMP, the step relation needed to carry along an auxiliary state in
addition to the program being executed. In the same way, once we
have added reference cells to the STLC, our step relation must
carry along a store to keep track of the contents of reference
cells.
We could re-use the same functional representation we used for
states in IMP, but for carrying out the proofs in this chapter it
is actually more convenient to represent a store simply as a
_list_ of values. (The reason we didn't use this representation
before is that, in IMP, a program could modify any location at any
time, so states had to be ready to map _any_ variable to a value.
However, in the STLC with references, the only way to create a
reference cell is with [tref t1], which puts the value of [t1]
in a new reference cell and reduces to the location of the newly
created reference cell. When reducing such an expression, we can
just add a new reference cell to the end of the list representing
the store.) *)
Definition store := list tm.
(** We use [store_lookup n st] to retrieve the value of the reference
cell at location [n] in the store [st]. Note that we must give a
default value to [nth] in case we try looking up an index which is
too large. (In fact, we will never actually do this, but proving
that we don't will require a bit of work.) *)
Definition store_lookup (n:nat) (st:store) :=
nth n st tunit.
(** To update the store, we use the [replace] function, which replaces
the contents of a cell at a particular index. *)
Fixpoint replace {A:Type} (n:nat) (x:A) (l:list A) : list A :=
match l with
| nil => nil
| h :: t =>
match n with
| O => x :: t
| S n' => h :: replace n' x t
end
end.
(** As might be expected, we will also need some technical
lemmas about [replace]; they are straightforward to prove. *)
Lemma replace_nil : forall A n (x:A),
replace n x nil = nil.
Proof.
destruct n; auto.
Qed.
Lemma length_replace : forall A n x (l:list A),
length (replace n x l) = length l.
Proof with auto.
intros A n x l. generalize dependent n.
induction l; intros n.
destruct n...
destruct n...
simpl. rewrite IHl...
Qed.
Lemma lookup_replace_eq : forall l t st,
l < length st ->
store_lookup l (replace l t st) = t.
Proof with auto.
intros l t st.
unfold store_lookup.
generalize dependent l.
induction st as [|t' st']; intros l Hlen.
- (* st = [] *)
inversion Hlen.
- (* st = t' :: st' *)
destruct l; simpl...
apply IHst'. simpl in Hlen. omega.
Qed.
Lemma lookup_replace_neq : forall l1 l2 t st,
l1 <> l2 ->
store_lookup l1 (replace l2 t st) = store_lookup l1 st.
Proof with auto.
unfold store_lookup.
induction l1 as [|l1']; intros l2 t st Hneq.
- (* l1 = 0 *)
destruct st.
+ (* st = [] *) rewrite replace_nil...
+ (* st = _ :: _ *) destruct l2... contradict Hneq...
- (* l1 = S l1' *)
destruct st as [|t2 st2].
+ (* st = [] *) destruct l2...
+ (* st = t2 :: st2 *)
destruct l2...
simpl; apply IHl1'...
Qed.
(* ================================================================= *)
(** ** Reduction *)
(** Next, we need to extend the operational semantics to take
stores into account. Since the result of reducing an expression
will in general depend on the contents of the store in which it is
reduced, the evaluation rules should take not just a term but
also a store as argument. Furthermore, since the reduction of a
term can cause side effects on the store, and these may affect the
reduction of other terms in the future, the reduction rules need
to return a new store. Thus, the shape of the single-step
reduction relation needs to change from [t ==> t'] to [t / st ==> t' /
st'], where [st] and [st'] are the starting and ending states of
the store.
To carry through this change, we first need to augment all of our
existing reduction rules with stores:
value v2
-------------------------------------- (ST_AppAbs)
(\x:T.t12) v2 / st ==> [x:=v2]t12 / st
t1 / st ==> t1' / st'
--------------------------- (ST_App1)
t1 t2 / st ==> t1' t2 / st'
value v1 t2 / st ==> t2' / st'
---------------------------------- (ST_App2)
v1 t2 / st ==> v1 t2' / st'
Note that the first rule here returns the store unchanged, since
function application, in itself, has no side effects. The other
two rules simply propagate side effects from premise to
conclusion.
Now, the result of reducing a [ref] expression will be a fresh
location; this is why we included locations in the syntax of terms
and in the set of values. It is crucial to note that making this
extension to the syntax of terms does not mean that we intend
_programmers_ to write terms involving explicit, concrete locations:
such terms will arise only as intermediate results during reduction.
This may seem odd, but it follows naturally from our design decision
to represent the result of every reduction step by a modified _term_.
If we had chosen a more "machine-like" model, e.g., with an explicit
stack to contain values of bound identifiers, then the idea of adding
locations to the set of allowed values might seem more obvious.
In terms of this expanded syntax, we can state reduction rules
for the new constructs that manipulate locations and the store.
First, to reduce a dereferencing expression [!t1], we must first
reduce [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------- (ST_Deref)
!t1 / st ==> !t1' / st'
Once [t1] has finished reducing, we should have an expression of
the form [!l], where [l] is some location. (A term that attempts
to dereference any other sort of value, such as a function or
[unit], is erroneous, as is a term that tries to dereference a
location that is larger than the size [|st|] of the currently
allocated store; the reduction rules simply get stuck in this
case. The type-safety properties established below assure us
that well-typed terms will never misbehave in this way.)
l < |st|
---------------------------------- (ST_DerefLoc)
!(loc l) / st ==> lookup l st / st
Next, to reduce an assignment expression [t1:=t2], we must first
reduce [t1] until it becomes a value (a location), and then
reduce [t2] until it becomes a value (of any sort):
t1 / st ==> t1' / st'
----------------------------------- (ST_Assign1)
t1 := t2 / st ==> t1' := t2 / st'
t2 / st ==> t2' / st'
--------------------------------- (ST_Assign2)
v1 := t2 / st ==> v1 := t2' / st'
Once we have finished with [t1] and [t2], we have an expression of
the form [l:=v2], which we execute by updating the store to make
location [l] contain [v2]:
l < |st|
------------------------------------- (ST_Assign)
loc l := v2 / st ==> unit / [l:=v2]st
The notation [[l:=v2]st] means "the store that maps [l] to [v2]
and maps all other locations to the same thing as [st.]" Note
that the term resulting from this reduction step is just [unit];
the interesting result is the updated store.
Finally, to reduct an expression of the form [ref t1], we first
reduce [t1] until it becomes a value:
t1 / st ==> t1' / st'
----------------------------- (ST_Ref)
ref t1 / st ==> ref t1' / st'
Then, to reduce the [ref] itself, we choose a fresh location at
the end of the current store -- i.e., location [|st|] -- and yield
a new store that extends [st] with the new value [v1].
-------------------------------- (ST_RefValue)
ref v1 / st ==> loc |st| / st,v1
The value resulting from this step is the newly allocated location
itself. (Formally, [st,v1] means [st ++ v1::nil] -- i.e., to add
a new reference cell to the store, we append it to the end.)
Note that these reduction rules do not perform any kind of
garbage collection: we simply allow the store to keep growing
without bound as reduction proceeds. This does not affect the
correctness of the results of reduction (after all, the
definition of "garbage" is precisely parts of the store that are
no longer reachable and so cannot play any further role in
reduction), but it means that a naive implementation of our
evaluator might run out of memory where a more sophisticated
evaluator would be able to continue by reusing locations whose
contents have become garbage.
Here are the rules again, formally: *)
Reserved Notation "t1 '/' st1 '==>' t2 '/' st2"
(at level 40, st1 at level 39, t2 at level 39).
Import ListNotations.
Inductive step : tm * store -> tm * store -> Prop :=
| ST_AppAbs : forall x T t12 v2 st,
value v2 ->
tapp (tabs x T t12) v2 / st ==> [x:=v2]t12 / st
| ST_App1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tapp t1 t2 / st ==> tapp t1' t2 / st'
| ST_App2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tapp v1 t2 / st ==> tapp v1 t2'/ st'
| ST_SuccNat : forall n st,
tsucc (tnat n) / st ==> tnat (S n) / st
| ST_Succ : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tsucc t1 / st ==> tsucc t1' / st'
| ST_PredNat : forall n st,
tpred (tnat n) / st ==> tnat (pred n) / st
| ST_Pred : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tpred t1 / st ==> tpred t1' / st'
| ST_MultNats : forall n1 n2 st,
tmult (tnat n1) (tnat n2) / st ==> tnat (mult n1 n2) / st
| ST_Mult1 : forall t1 t2 t1' st st',
t1 / st ==> t1' / st' ->
tmult t1 t2 / st ==> tmult t1' t2 / st'
| ST_Mult2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tmult v1 t2 / st ==> tmult v1 t2' / st'
| ST_If0 : forall t1 t1' t2 t3 st st',
t1 / st ==> t1' / st' ->
tif0 t1 t2 t3 / st ==> tif0 t1' t2 t3 / st'
| ST_If0_Zero : forall t2 t3 st,
tif0 (tnat 0) t2 t3 / st ==> t2 / st
| ST_If0_Nonzero : forall n t2 t3 st,
tif0 (tnat (S n)) t2 t3 / st ==> t3 / st
| ST_RefValue : forall v1 st,
value v1 ->
tref v1 / st ==> tloc (length st) / (st ++ v1::nil)
| ST_Ref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tref t1 / st ==> tref t1' / st'
| ST_DerefLoc : forall st l,
l < length st ->
tderef (tloc l) / st ==> store_lookup l st / st
| ST_Deref : forall t1 t1' st st',
t1 / st ==> t1' / st' ->
tderef t1 / st ==> tderef t1' / st'
| ST_Assign : forall v2 l st,
value v2 ->
l < length st ->
tassign (tloc l) v2 / st ==> tunit / replace l v2 st
| ST_Assign1 : forall t1 t1' t2 st st',
t1 / st ==> t1' / st' ->
tassign t1 t2 / st ==> tassign t1' t2 / st'
| ST_Assign2 : forall v1 t2 t2' st st',
value v1 ->
t2 / st ==> t2' / st' ->
tassign v1 t2 / st ==> tassign v1 t2' / st'
where "t1 '/' st1 '==>' t2 '/' st2" := (step (t1,st1) (t2,st2)).
(** One slightly ugly point should be noted here: In the [ST_RefValue]
rule, we extend the state by writing [st ++ v1::nil] rather than
the more natural [st ++ [v1]]. The reason for this is that the
notation we've defined for substitution uses square brackets,
which clash with the standard library's notation for lists. *)
Hint Constructors step.
Definition multistep := (multi step).
Notation "t1 '/' st '==>*' t2 '/' st'" :=
(multistep (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(* ################################################################# *)
(** * Typing *)
(** The contexts assigning types to free variables are exactly the
same as for the STLC: partial maps from identifiers to types. *)
Definition context := partial_map ty.
(* ================================================================= *)
(** ** Store typings *)
(** Having extended our syntax and reduction rules to accommodate
references, our last job is to write down typing rules for the new
constructs (and, of course, to check that these rules are sound!).
Naturally, the key question is, "What is the type of a location?"
First of all, notice that this question doesn't arise when
typechecking terms that programmers actually
write. Concrete location constants arise only in terms that are
the intermediate results of reduction; they are not in the
language that programmers write. So we only need to determine the
type of a location when we're in the middle of a reduction
sequence, e.g., trying to apply the progress or preservation
lemmas. Thus, even though we normally think of typing as a
_static_ program property, it makes sense for the typing of
locations to depend on the _dynamic_ progress of the program too.
As a first try, note that when we reduce a term containing
concrete locations, the type of the result depends on the contents
of the store that we start with. For example, if we reduce the
term [!(loc 1)] in the store [[unit, unit]], the result is [unit];
if we reduce the same term in the store [[unit, \x:Unit.x]], the
result is [\x:Unit.x]. With respect to the former store, the
location [1] has type [Unit], and with respect to the latter it
has type [Unit->Unit]. This observation leads us immediately to a
first attempt at a typing rule for locations:
Gamma |- lookup l st : T1
----------------------------
Gamma |- loc l : Ref T1
That is, to find the type of a location [l], we look up the
current contents of [l] in the store and calculate the type [T1]
of the contents. The type of the location is then [Ref T1].
Having begun in this way, we need to go a little further to reach a
consistent state. In effect, by making the type of a term depend on
the store, we have changed the typing relation from a three-place
relation (between contexts, terms, and types) to a four-place relation
(between contexts, _stores_, terms, and types). Since the store is,
intuitively, part of the context in which we calculate the type of a
term, let's write this four-place relation with the store to the left
of the turnstile: [Gamma; st |- t : T]. Our rule for typing
references now has the form
Gamma; st |- lookup l st : T1
--------------------------------
Gamma; st |- loc l : Ref T1
and all the rest of the typing rules in the system are extended
similarly with stores. (The other rules do not need to do anything
interesting with their stores -- just pass them from premise to
conclusion.)
However, this rule will not quite do. For one thing, typechecking
is rather inefficient, since calculating the type of a location [l]
involves calculating the type of the current contents [v] of [l]. If
[l] appears many times in a term [t], we will re-calculate the type of
[v] many times in the course of constructing a typing derivation for
[t]. Worse, if [v] itself contains locations, then we will have to
recalculate _their_ types each time they appear. Worse yet, the
proposed typing rule for locations may not allow us to derive
anything at all, if the store contains a _cycle_. For example,
there is no finite typing derivation for the location [0] with respect
to this store:
[\x:Nat. (!(loc 1)) x, \x:Nat. (!(loc 0)) x]
*)
(** **** Exercise: 2 stars (cyclic_store) *)
(** Can you find a term whose reduction will create this particular
cyclic store? *)
(** [] *)
(** These problems arise from the fact that our proposed
typing rule for locations requires us to recalculate the type of a
location every time we mention it in a term. But this,
intuitively, should not be necessary. After all, when a location
is first created, we know the type of the initial value that we
are storing into it. Suppose we are willing to enforce the
invariant that the type of the value contained in a given location
_never changes_; that is, although we may later store other values
into this location, those other values will always have the same
type as the initial one. In other words, we always have in mind a
single, definite type for every location in the store, which is
fixed when the location is allocated. Then these intended types
can be collected together as a _store typing_ -- a finite function
mapping locations to types.
As with the other type systems we've seen, this conservative typing
restriction on allowed updates means that we will rule out as
ill-typed some programs that could reduce perfectly well without
getting stuck.
Just as we did for stores, we will represent a store type simply
as a list of types: the type at index [i] records the type of the
values that we expect to be stored in cell [i]. *)
Definition store_ty := list ty.
(** The [store_Tlookup] function retrieves the type at a particular
index. *)
Definition store_Tlookup (n:nat) (ST:store_ty) :=
nth n ST TUnit.
(** Suppose we are given a store typing [ST] describing the store
[st] in which some term [t] will be reduced. Then we can use
[ST] to calculate the type of the result of [t] without ever
looking directly at [st]. For example, if [ST] is [[Unit,
Unit->Unit]], then we can immediately infer that [!(loc 1)] has
type [Unit->Unit]. More generally, the typing rule for locations
can be reformulated in terms of store typings like this:
l < |ST|
-------------------------------------
Gamma; ST |- loc l : Ref (lookup l ST)
That is, as long as [l] is a valid location, we can compute the
type of [l] just by looking it up in [ST]. Typing is again a
four-place relation, but it is parameterized on a store _typing_
rather than a concrete store. The rest of the typing rules are
analogously augmented with store typings. *)
(* ================================================================= *)
(** ** The Typing Relation *)
(** We can now formalize the typing relation for the STLC with
references. Here, again, are the rules we're adding to the base
STLC (with numbers and [Unit]): *)
(**
l < |ST|
-------------------------------------- (T_Loc)
Gamma; ST |- loc l : Ref (lookup l ST)
Gamma; ST |- t1 : T1
---------------------------- (T_Ref)
Gamma; ST |- ref t1 : Ref T1
Gamma; ST |- t1 : Ref T11
------------------------- (T_Deref)
Gamma; ST |- !t1 : T11
Gamma; ST |- t1 : Ref T11
Gamma; ST |- t2 : T11
----------------------------- (T_Assign)
Gamma; ST |- t1 := t2 : Unit
*)
Reserved Notation "Gamma ';' ST '|-' t '\in' T" (at level 40).
Inductive has_type : context -> store_ty -> tm -> ty -> Prop :=
| T_Var : forall Gamma ST x T,
Gamma x = Some T ->
Gamma; ST |- (tvar x) \in T
| T_Abs : forall Gamma ST x T11 T12 t12,
(update Gamma x T11); ST |- t12 \in T12 ->
Gamma; ST |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma ST t1 t2,
Gamma; ST |- t1 \in (TArrow T1 T2) ->
Gamma; ST |- t2 \in T1 ->
Gamma; ST |- (tapp t1 t2) \in T2
| T_Nat : forall Gamma ST n,
Gamma; ST |- (tnat n) \in TNat
| T_Succ : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tsucc t1) \in TNat
| T_Pred : forall Gamma ST t1,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- (tpred t1) \in TNat
| T_Mult : forall Gamma ST t1 t2,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in TNat ->
Gamma; ST |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma ST t1 t2 t3 T,
Gamma; ST |- t1 \in TNat ->
Gamma; ST |- t2 \in T ->
Gamma; ST |- t3 \in T ->
Gamma; ST |- (tif0 t1 t2 t3) \in T
| T_Unit : forall Gamma ST,
Gamma; ST |- tunit \in TUnit
| T_Loc : forall Gamma ST l,
l < length ST ->
Gamma; ST |- (tloc l) \in (TRef (store_Tlookup l ST))
| T_Ref : forall Gamma ST t1 T1,
Gamma; ST |- t1 \in T1 ->
Gamma; ST |- (tref t1) \in (TRef T1)
| T_Deref : forall Gamma ST t1 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- (tderef t1) \in T11
| T_Assign : forall Gamma ST t1 t2 T11,
Gamma; ST |- t1 \in (TRef T11) ->
Gamma; ST |- t2 \in T11 ->
Gamma; ST |- (tassign t1 t2) \in TUnit
where "Gamma ';' ST '|-' t '\in' T" := (has_type Gamma ST t T).
Hint Constructors has_type.
(** Of course, these typing rules will accurately predict the results
of reduction only if the concrete store used during reduction
actually conforms to the store typing that we assume for purposes
of typechecking. This proviso exactly parallels the situation
with free variables in the basic STLC: the substitution lemma
promises that, if [Gamma |- t : T], then we can replace the free
variables in [t] with values of the types listed in [Gamma] to
obtain a closed term of type [T], which, by the type preservation
theorem will reduce to a final result of type [T] if it yields
any result at all. We will see below how to formalize an
analogous intuition for stores and store typings.
However, for purposes of typechecking the terms that programmers
actually write, we do not need to do anything tricky to guess what
store typing we should use. Concrete locations arise only in
terms that are the intermediate results of reduction; they are
not in the language that programmers write. Thus, we can simply
typecheck the programmer's terms with respect to the _empty_ store
typing. As reduction proceeds and new locations are created, we
will always be able to see how to extend the store typing by
looking at the type of the initial values being placed in newly
allocated cells; this intuition is formalized in the statement of
the type preservation theorem below. *)
(* ################################################################# *)
(** * Properties *)
(** Our final task is to check that standard type safety
properties continue to hold for the STLC with references. The
progress theorem ("well-typed terms are not stuck") can be stated
and proved almost as for the STLC; we just need to add a few
straightforward cases to the proof to deal with the new
constructs. The preservation theorem is a bit more interesting,
so let's look at it first. *)
(* ================================================================= *)
(** ** Well-Typed Stores *)
(** Since we have extended both the reduction relation (with
initial and final stores) and the typing relation (with a store
typing), we need to change the statement of preservation to
include these parameters. But clearly we cannot just add stores
and store typings without saying anything about how they are
related -- i.e., this is wrong: *)
Theorem preservation_wrong1 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
empty; ST |- t' \in T.
Abort.
(** If we typecheck with respect to some set of assumptions about the
types of the values in the store and then reduce with respect to
a store that violates these assumptions, the result will be
disaster. We say that a store [st] is _well typed_ with respect a
store typing [ST] if the term at each location [l] in [st] has the
type at location [l] in [ST]. Since only closed terms ever get
stored in locations (why?), it suffices to type them in the empty
context. The following definition of [store_well_typed] formalizes
this. *)
Definition store_well_typed (ST:store_ty) (st:store) :=
length ST = length st /\
(forall l, l < length st ->
empty; ST |- (store_lookup l st) \in (store_Tlookup l ST)).
(** Informally, we will write [ST |- st] for [store_well_typed ST st]. *)
(** Intuitively, a store [st] is consistent with a store typing
[ST] if every value in the store has the type predicted by the
store typing. The only subtle point is the fact that, when
typing the values in the store, we supply the very same store
typing to the typing relation. This allows us to type circular
stores like the one we saw above. *)
(** **** Exercise: 2 stars (store_not_unique) *)
(** Can you find a store [st], and two
different store typings [ST1] and [ST2] such that both
[ST1 |- st] and [ST2 |- st]? *)
(* FILL IN HERE *)
(** [] *)
(** We can now state something closer to the desired preservation
property: *)
Theorem preservation_wrong2 : forall ST T t st t' st',
empty; ST |- t \in T ->
t / st ==> t' / st' ->
store_well_typed ST st ->
empty; ST |- t' \in T.
Abort.
(** This statement is fine for all of the reduction rules except
the allocation rule [ST_RefValue]. The problem is that this rule
yields a store with a larger domain than the initial store, which
falsifies the conclusion of the above statement: if [st'] includes
a binding for a fresh location [l], then [l] cannot be in the
domain of [ST], and it will not be the case that [t'] (which
definitely mentions [l]) is typable under [ST]. *)
(* ================================================================= *)
(** ** Extending Store Typings *)
(** Evidently, since the store can increase in size during reduction,
we need to allow the store typing to grow as well. This motivates
the following definition. We say that the store type [ST']
_extends_ [ST] if [ST'] is just [ST] with some new types added to
the end. *)
Inductive extends : store_ty -> store_ty -> Prop :=
| extends_nil : forall ST',
extends ST' nil
| extends_cons : forall x ST' ST,
extends ST' ST ->
extends (x::ST') (x::ST).
Hint Constructors extends.
(** We'll need a few technical lemmas about extended contexts.
First, looking up a type in an extended store typing yields the
same result as in the original: *)
Lemma extends_lookup : forall l ST ST',
l < length ST ->
extends ST' ST ->
store_Tlookup l ST' = store_Tlookup l ST.
Proof with auto.
intros l ST ST' Hlen H.
generalize dependent ST'. generalize dependent l.
induction ST as [|a ST2]; intros l Hlen ST' HST'.
- (* nil *) inversion Hlen.
- (* cons *) unfold store_Tlookup in *.
destruct ST'.
+ (* ST' = nil *) inversion HST'.
+ (* ST' = a' :: ST'2 *)
inversion HST'; subst.
destruct l as [|l'].
* (* l = 0 *) auto.
* (* l = S l' *) simpl. apply IHST2...
simpl in Hlen; omega.
Qed.
(** Next, if [ST'] extends [ST], the length of [ST'] is at least that
of [ST]. *)
Lemma length_extends : forall l ST ST',
l < length ST ->
extends ST' ST ->
l < length ST'.
Proof with eauto.
intros. generalize dependent l. induction H0; intros l Hlen.
inversion Hlen.
simpl in *.
destruct l; try omega.
apply lt_n_S. apply IHextends. omega.
Qed.
(** Finally, [ST ++ T] extends [ST], and [extends] is reflexive. *)
Lemma extends_app : forall ST T,
extends (ST ++ T) ST.
Proof with auto.
induction ST; intros T...
simpl...
Qed.
Lemma extends_refl : forall ST,
extends ST ST.
Proof.
induction ST; auto.
Qed.
(* ================================================================= *)
(** ** Preservation, Finally *)
(** We can now give the final, correct statement of the type
preservation property: *)
Definition preservation_theorem := forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
(** Note that the preservation theorem merely asserts that there is
_some_ store typing [ST'] extending [ST] (i.e., agreeing with [ST]
on the values of all the old locations) such that the new term
[t'] is well typed with respect to [ST']; it does not tell us
exactly what [ST'] is. It is intuitively clear, of course, that
[ST'] is either [ST] or else exactly [ST ++ T1::nil], where
[T1] is the type of the value [v1] in the extended store [st ++
v1::nil], but stating this explicitly would complicate the statement of
the theorem without actually making it any more useful: the weaker
version above is already in the right form (because its conclusion
implies its hypothesis) to "turn the crank" repeatedly and
conclude that every _sequence_ of reduction steps preserves
well-typedness. Combining this with the progress property, we
obtain the usual guarantee that "well-typed programs never go
wrong."
In order to prove this, we'll need a few lemmas, as usual. *)
(* ================================================================= *)
(** ** Substitution Lemma *)
(** First, we need an easy extension of the standard substitution
lemma, along with the same machinery about context invariance that
we used in the proof of the substitution lemma for the STLC. *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
| afi_succ : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tsucc t1)
| afi_pred : forall x t1,
appears_free_in x t1 ->
appears_free_in x (tpred t1)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if0_1 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_2 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if0_3 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_ref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tref t1)
| afi_deref : forall x t1,
appears_free_in x t1 -> appears_free_in x (tderef t1)
| afi_assign1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tassign t1 t2)
| afi_assign2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tassign t1 t2).
Hint Constructors appears_free_in.
Lemma free_in_context : forall x t T Gamma ST,
appears_free_in x t ->
Gamma; ST |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros. generalize dependent Gamma. generalize dependent T.
induction H;
intros; (try solve [ inversion H0; subst; eauto ]).
- (* afi_abs *)
inversion H1; subst.
apply IHappears_free_in in H8.
rewrite update_neq in H8; assumption.
Qed.
Lemma context_invariance : forall Gamma Gamma' ST t T,
Gamma; ST |- t \in T ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma'; ST |- t \in T.
Proof with eauto.
intros.
generalize dependent Gamma'.
induction H; intros...
- (* T_Var *)
apply T_Var. symmetry. rewrite <- H...
- (* T_Abs *)
apply T_Abs. apply IHhas_type; intros.
unfold update, t_update.
destruct (beq_idP x x0)...
- (* T_App *)
eapply T_App.
apply IHhas_type1...
apply IHhas_type2...
- (* T_Mult *)
eapply T_Mult.
apply IHhas_type1...
apply IHhas_type2...
- (* T_If0 *)
eapply T_If0.
apply IHhas_type1...
apply IHhas_type2...
apply IHhas_type3...
- (* T_Assign *)
eapply T_Assign.
apply IHhas_type1...
apply IHhas_type2...
Qed.
Lemma substitution_preserves_typing : forall Gamma ST x s S t T,
empty; ST |- s \in S ->
(update Gamma x S); ST |- t \in T ->
Gamma; ST |- ([x:=s]t) \in T.
Proof with eauto.
intros Gamma ST x s S t T Hs Ht.
generalize dependent Gamma. generalize dependent T.
induction t; intros T Gamma H;
inversion H; subst; simpl...
- (* tvar *)
rename i into y.
destruct (beq_idP x y).
+ (* x = y *)
subst.
rewrite update_eq in H3.
inversion H3; subst.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ _ _ _ Hcontra Hs)
as [T' HT'].
inversion HT'.
+ (* x <> y *)
apply T_Var.
rewrite update_neq in H3...
- (* tabs *) subst.
rename i into y.
destruct (beq_idP x y).
+ (* x = y *)
subst.
apply T_Abs. eapply context_invariance...
intros. rewrite update_shadow. reflexivity.
+ (* x <> x0 *)
apply T_Abs. apply IHt.
eapply context_invariance...
intros. unfold update, t_update.
destruct (beq_idP y x0)...
subst.
rewrite false_beq_id...
Qed.
(* ================================================================= *)
(** ** Assignment Preserves Store Typing *)
(** Next, we must show that replacing the contents of a cell in the
store with a new value of appropriate type does not change the
overall type of the store. (This is needed for the [ST_Assign]
rule.) *)
Lemma assign_pres_store_typing : forall ST st l t,
l < length st ->
store_well_typed ST st ->
empty; ST |- t \in (store_Tlookup l ST) ->
store_well_typed ST (replace l t st).
Proof with auto.
intros ST st l t Hlen HST Ht.
inversion HST; subst.
split. rewrite length_replace...
intros l' Hl'.
destruct (beq_nat l' l) eqn: Heqll'.
- (* l' = l *)
apply beq_nat_true in Heqll'; subst.
rewrite lookup_replace_eq...
- (* l' <> l *)
apply beq_nat_false in Heqll'.
rewrite lookup_replace_neq...
rewrite length_replace in Hl'.
apply H0...
Qed.
(* ================================================================= *)
(** ** Weakening for Stores *)
(** Finally, we need a lemma on store typings, stating that, if a
store typing is extended with a new location, the extended one
still allows us to assign the same types to the same terms as the
original.
(The lemma is called [store_weakening] because it resembles the
"weakening" lemmas found in proof theory, which show that adding a
new assumption to some logical theory does not decrease the set of
provable theorems.) *)
Lemma store_weakening : forall Gamma ST ST' t T,
extends ST' ST ->
Gamma; ST |- t \in T ->
Gamma; ST' |- t \in T.
Proof with eauto.
intros. induction H0; eauto.
- (* T_Loc *)
erewrite <- extends_lookup...
apply T_Loc.
eapply length_extends...
Qed.
(** We can use the [store_weakening] lemma to prove that if a store is
well typed with respect to a store typing, then the store extended
with a new term [t] will still be well typed with respect to the
store typing extended with [t]'s type. *)
Lemma store_well_typed_app : forall ST st t1 T1,
store_well_typed ST st ->
empty; ST |- t1 \in T1 ->
store_well_typed (ST ++ T1::nil) (st ++ t1::nil).
Proof with auto.
intros.
unfold store_well_typed in *.
inversion H as [Hlen Hmatch]; clear H.
rewrite app_length, plus_comm. simpl.
rewrite app_length, plus_comm. simpl.
split...
- (* types match. *)
intros l Hl.
unfold store_lookup, store_Tlookup.
apply le_lt_eq_dec in Hl; inversion Hl as [Hlt | Heq].
+ (* l < length st *)
apply lt_S_n in Hlt.
rewrite !app_nth1...
* apply store_weakening with ST. apply extends_app.
apply Hmatch...
* rewrite Hlen...
+ (* l = length st *)
inversion Heq.
rewrite app_nth2; try omega.
rewrite <- Hlen.
rewrite minus_diag. simpl.
apply store_weakening with ST...
{ apply extends_app. }
rewrite app_nth2; try omega.
rewrite minus_diag. simpl. trivial.
Qed.
(* ================================================================= *)
(** ** Preservation! *)
(** Now that we've got everything set up right, the proof of
preservation is actually quite straightforward. *)
(** Begin with one technical lemma: *)
Lemma nth_eq_last : forall A (l:list A) x d,
nth (length l) (l ++ x::nil) d = x.
Proof.
induction l; intros; [ auto | simpl; rewrite IHl; auto ].
Qed.
(** And here, at last, is the preservation theorem and proof: *)
Theorem preservation : forall ST t t' T st st',
empty; ST |- t \in T ->
store_well_typed ST st ->
t / st ==> t' / st' ->
exists ST',
(extends ST' ST /\
empty; ST' |- t' \in T /\
store_well_typed ST' st').
Proof with eauto using store_weakening, extends_refl.
remember (@empty ty) as Gamma.
intros ST t t' T st st' Ht.
generalize dependent t'.
induction Ht; intros t' HST Hstep;
subst; try (solve by inversion); inversion Hstep; subst;
try (eauto using store_weakening, extends_refl).
(* T_App *)
- (* ST_AppAbs *) exists ST.
inversion Ht1; subst.
split; try split... eapply substitution_preserves_typing...
- (* ST_App1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_App2 *)
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_Succ *)
+ (* ST_Succ *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_Pred *)
+ (* ST_Pred *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Mult *)
- (* ST_Mult1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_Mult2 *)
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* T_If0 *)
+ (* ST_If0_1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'... split...
(* T_Ref *)
- (* ST_RefValue *)
exists (ST ++ T1::nil).
inversion HST; subst.
split.
apply extends_app.
split.
replace (TRef T1)
with (TRef (store_Tlookup (length st) (ST ++ T1::nil))).
apply T_Loc.
rewrite <- H. rewrite app_length, plus_comm. simpl. omega.
unfold store_Tlookup. rewrite <- H. rewrite nth_eq_last.
reflexivity.
apply store_well_typed_app; assumption.
- (* ST_Ref *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Deref *)
- (* ST_DerefLoc *)
exists ST. split; try split...
inversion HST as [_ Hsty].
replace T11 with (store_Tlookup l ST).
apply Hsty...
inversion Ht; subst...
- (* ST_Deref *)
eapply IHHt in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
(* T_Assign *)
- (* ST_Assign *)
exists ST. split; try split...
eapply assign_pres_store_typing...
inversion Ht1; subst...
- (* ST_Assign1 *)
eapply IHHt1 in H0...
inversion H0 as [ST' [Hext [Hty Hsty]]].
exists ST'...
- (* ST_Assign2 *)
eapply IHHt2 in H5...
inversion H5 as [ST' [Hext [Hty Hsty]]].
exists ST'...
Qed.
(** **** Exercise: 3 stars (preservation_informal) *)
(** Write a careful informal proof of the preservation theorem,
concentrating on the [T_App], [T_Deref], [T_Assign], and [T_Ref]
cases.
(* FILL IN HERE *)
[] *)
(* ================================================================= *)
(** ** Progress *)
(** As we've said, progress for this system is pretty easy to prove;
the proof is very similar to the proof of progress for the STLC,
with a few new cases for the new syntactic constructs. *)
Theorem progress : forall ST t T st,
empty; ST |- t \in T ->
store_well_typed ST st ->
(value t \/ exists t', exists st', t / st ==> t' / st').
Proof with eauto.
intros ST t T st Ht HST. remember (@empty ty) as Gamma.
induction Ht; subst; try solve by inversion...
- (* T_App *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve by inversion.
destruct IHHt2 as [Ht2p | Ht2p]...
* (* t2 steps *)
inversion Ht2p as [t2' [st' Hstep]].
exists (tapp (tabs x T t) t2'). exists st'...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tapp t1' t2). exists st'...
- (* T_Succ *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [ inversion Ht ].
* (* t1 is a tnat *)
exists (tnat (S n)). exists st...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tsucc t1'). exists st'...
- (* T_Pred *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht ].
* (* t1 is a tnat *)
exists (tnat (pred n)). exists st...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tpred t1'). exists st'...
- (* T_Mult *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht1].
destruct IHHt2 as [Ht2p | Ht2p]...
* (* t2 is a value *)
inversion Ht2p; subst; try solve [inversion Ht2].
exists (tnat (mult n n0)). exists st...
* (* t2 steps *)
inversion Ht2p as [t2' [st' Hstep]].
exists (tmult (tnat n) t2'). exists st'...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tmult t1' t2). exists st'...
- (* T_If0 *)
right. destruct IHHt1 as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve [inversion Ht1].
destruct n.
* (* n = 0 *) exists t2. exists st...
* (* n = S n' *) exists t3. exists st...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tif0 t1' t2 t3). exists st'...
- (* T_Ref *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tref t1'). exists st'...
- (* T_Deref *)
right. destruct IHHt as [Ht1p | Ht1p]...
+ (* t1 is a value *)
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_DerefLoc...
inversion Ht; subst. inversion HST; subst.
rewrite <- H...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tderef t1'). exists st'...
- (* T_Assign *)
right. destruct IHHt1 as [Ht1p|Ht1p]...
+ (* t1 is a value *)
destruct IHHt2 as [Ht2p|Ht2p]...
* (* t2 is a value *)
inversion Ht1p; subst; try solve by inversion.
eexists. eexists. apply ST_Assign...
inversion HST; subst. inversion Ht1; subst.
rewrite H in H5...
* (* t2 steps *)
inversion Ht2p as [t2' [st' Hstep]].
exists (tassign t1 t2'). exists st'...
+ (* t1 steps *)
inversion Ht1p as [t1' [st' Hstep]].
exists (tassign t1' t2). exists st'...
Qed.
(* ################################################################# *)
(** * References and Nontermination *)
(** An important fact about the STLC (proved in chapter [Norm]) is
that it is is _normalizing_ -- that is, every well-typed term can
be reduced to a value in a finite number of steps.
What about STLC + references? Surprisingly, adding references
causes us to lose the normalization property: there exist
well-typed terms in the STLC + references which can continue to
reduce forever, without ever reaching a normal form!
How can we construct such a term? The main idea is to make a
function which calls itself. We first make a function which calls
another function stored in a reference cell; the trick is that we
then smuggle in a reference to itself!
(\r:Ref (Unit -> Unit).
r := (\x:Unit.(!r) unit); (!r) unit)
(ref (\x:Unit.unit))
First, [ref (\x:Unit.unit)] creates a reference to a cell of type
[Unit -> Unit]. We then pass this reference as the argument to a
function which binds it to the name [r], and assigns to it the
function [\x:Unit.(!r) unit] -- that is, the function which ignores
its argument and calls the function stored in [r] on the argument
[unit]; but of course, that function is itself! To start the
divergent loop, we execute the function stored in the cell by
evaluating [(!r) unit].
Here is the divergent term in Coq: *)
Module ExampleVariables.
Definition x := Id 0.
Definition y := Id 1.
Definition r := Id 2.
Definition s := Id 3.
End ExampleVariables.
Module RefsAndNontermination.
Import ExampleVariables.
Definition loop_fun :=
tabs x TUnit (tapp (tderef (tvar r)) tunit).
Definition loop :=
tapp
(tabs r (TRef (TArrow TUnit TUnit))
(tseq (tassign (tvar r) loop_fun)
(tapp (tderef (tvar r)) tunit)))
(tref (tabs x TUnit tunit)).
(** This term is well typed: *)
Lemma loop_typeable : exists T, empty; nil |- loop \in T.
Proof with eauto.
eexists. unfold loop. unfold loop_fun.
eapply T_App...
eapply T_Abs...
eapply T_App...
eapply T_Abs. eapply T_App. eapply T_Deref. eapply T_Var.
unfold update, t_update. simpl. reflexivity. auto.
eapply T_Assign.
eapply T_Var. unfold update, t_update. simpl. reflexivity.
eapply T_Abs.
eapply T_App...
eapply T_Deref. eapply T_Var. reflexivity.
Qed.
(** To show formally that the term diverges, we first define the
[step_closure] of the single-step reduction relation, written
[==>+]. This is just like the reflexive step closure of
single-step reduction (which we're been writing [==>*]), except
that it is not reflexive: [t ==>+ t'] means that [t] can reach
[t'] by _one or more_ steps of reduction. *)
Inductive step_closure {X:Type} (R: relation X) : X -> X -> Prop :=
| sc_one : forall (x y : X),
R x y -> step_closure R x y
| sc_step : forall (x y z : X),
R x y ->
step_closure R y z ->
step_closure R x z.
Definition multistep1 := (step_closure step).
Notation "t1 '/' st '==>+' t2 '/' st'" :=
(multistep1 (t1,st) (t2,st'))
(at level 40, st at level 39, t2 at level 39).
(** Now, we can show that the expression [loop] reduces to the
expression [!(loc 0) unit] and the size-one store
[[r:=(loc 0)]loop_fun]. *)
(** As a convenience, we introduce a slight variant of the [normalize]
tactic, called [reduce], which tries solving the goal with
[multi_refl] at each step, instead of waiting until the goal can't
be reduced any more. Of course, the whole point is that [loop]
doesn't normalize, so the old [normalize] tactic would just go
into an infinite loop reducing it forever! *)
Ltac print_goal := match goal with |- ?x => idtac x end.
Ltac reduce :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; compute)];
try solve [apply multi_refl]).
(** Next, we use [reduce] to show that [loop] steps to
[!(loc 0) unit], starting from the empty store. *)
Lemma loop_steps_to_loop_fun :
loop / nil ==>*
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof.
unfold loop.
reduce.
Qed.
(** Finally, we show that the latter expression reduces in
two steps to itself! *)
Lemma loop_fun_step_self :
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil ==>+
tapp (tderef (tloc 0)) tunit / cons ([r:=tloc 0]loop_fun) nil.
Proof with eauto.
unfold loop_fun; simpl.
eapply sc_step. apply ST_App1...
eapply sc_one. compute. apply ST_AppAbs...
Qed.
(** **** Exercise: 4 stars (factorial_ref) *)
(** Use the above ideas to implement a factorial function in STLC with
references. (There is no need to prove formally that it really
behaves like the factorial. Just uncomment the example below to make
sure it gives the correct result when applied to the argument
[4].) *)
Definition factorial : tm :=
(* FILL IN HERE *) admit.
Lemma factorial_type : empty; nil |- factorial \in (TArrow TNat TNat).
Proof with eauto.
(* FILL IN HERE *) Admitted.
(** If your definition is correct, you should be able to just
uncomment the example below; the proof should be fully
automatic using the [reduce] tactic. *)
(*
Lemma factorial_4 : exists st,
tapp factorial (tnat 4) / nil ==>* tnat 24 / st.
Proof.
eexists. unfold factorial. reduce.
Qed.
*)
(** [] *)
(* ################################################################# *)
(** * Additional Exercises *)
(** **** Exercise: 5 stars, optional (garabage_collector) *)
(** Challenge problem: modify our formalization to include an account
of garbage collection, and prove that it satisfies whatever nice
properties you can think to prove about it. *)
(** [] *)
End RefsAndNontermination.
End STLCRef.
(** $Date: 2016-05-26 16:17:19 -0400 (Thu, 26 May 2016) $ *)
|
// Copyright (c) 2013 Gueho Choi, Andrew Downing
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
/////////////////////////////////////////////////////////////
// module: instruction memory ( 8 x 256 )
// inputs: ReadEnable(rdEn), WriteEnable(wrEn), Address(addr), WriteData(wrData)
// outputs: Data(Data)
//
////////////////////////////////////////////////////////////
module InstrucMemoryHardcoded (Clk, rdEn, wrEn, addr, wrData, Data);
parameter WIDTH = 8;
parameter DEPTH = 256;
input Clk;
input rdEn, wrEn;
input [WIDTH-1:0] wrData;
input [7:0] addr;
output [WIDTH-1:0] Data;
reg [WIDTH-1:0] data_out;
always @ (posedge Clk)
begin : INST_MEMORY
case (addr)
// DIVIDER
// initialization
8'h0: data_out <= 32'h0c_00_09_xx; // dividend (addr 0) = 9
8'h1: data_out <= 32'h0c_01_04_xx; // divisor (addr 1) = 4
8'h2: data_out <= 32'h0c_02_00_xx; // quotient (addr 2) = 0
8'h3: data_out <= 32'h0c_c0_00_xx; // constant 0 (addr c0) = 0
8'h4: data_out <= 32'h0c_c1_01_xx; // constant 1 (addr c1) = 1
8'h5: data_out <= 32'h0c_c4_04_xx; // constant 4 (addr c4) = 4
8'h6: data_out <= 32'h08_10_xx_xx; // jump to instruction 10 (hardcoded inputs) or 20 (user input)
// division by repeated subtraction
8'h10: data_out <= 32'h01_00_00_01; // dividend = dividend - divisor
8'h11: data_out <= 32'h0b_14_00_xx; // if dividend < 0 then jump to instruction 14
8'h12: data_out <= 32'h00_02_02_c1; // quotient = quotient + 1
8'h13: data_out <= 32'h08_10_xx_xx; // jump to instruction 10
// calculate remainder, display output, and exit
8'h14: data_out <= 32'h00_03_00_01; // remainder (addr 3) = dividend + divisor
8'h15: data_out <= 32'h0d_fa_03_xx; // ssd0 = remainder
8'h16: data_out <= 32'h02_fb_03_c4; // ssd1 = remainder >> 4
8'h17: data_out <= 32'h0d_fc_02_xx; // ssd2 = quotient
8'h18: data_out <= 32'h02_fd_02_c4; // ssd3 = quotient >> 4
8'h19: data_out <= 32'h0f_xx_xx_xx; // end program
// get inputs from user
8'h20: data_out <= 32'h09_22_e4_xx; // if BtnL = 0 then jump to instruction 22
8'h21: data_out <= 32'h0d_00_e0_xx; // dividend = FPGA switches
8'h22: data_out <= 32'h09_24_e1_xx; // if BtnR = 0 then jump to instruction 24
8'h23: data_out <= 32'h0d_01_e0_xx; // divisor = FPGA switches
8'h24: data_out <= 32'h0d_fa_01_xx; // ssd0 = divisor
8'h25: data_out <= 32'h02_fb_01_c4; // ssd1 = divisor >> 4
8'h26: data_out <= 32'h0d_fc_00_xx; // ssd2 = dividend
8'h27: data_out <= 32'h02_fd_00_c4; // ssd3 = dividend >> 4
8'h28: data_out <= 32'h0a_10_e3_xx; // if BtnU > 0 then jump to instruction 10
8'h29: data_out <= 32'h08_20_xx_xx; // jump to instruction 20
/*
// ADDER
8'h0: data_out <= 32'h0c_00_01_xx; // addend0 (addr 0) = 1
8'h1: data_out <= 32'h0c_01_01_xx; // addend1 (addr 1) = 1
8'h2: data_out <= 32'h0c_c4_04_xx; // constant 4 (addr c4) = 4
8'h3: data_out <= 32'h09_05_e4_xx; // if BtnL = 0 then jump to instruction 5
8'h4: data_out <= 32'h0d_00_e0_xx; // addend0 = FPGA switches
8'h5: data_out <= 32'h09_07_e1_xx; // if BtnR = 0 then jump to instruction 7
8'h6: data_out <= 32'h0d_01_e0_xx; // addend1 = FPGA switches
8'h7: data_out <= 32'h00_02_00_01; // sum (addr 2) = addend0 + addend1
8'h8: data_out <= 32'h0d_fa_02_xx; // ssd0 = sum
8'h9: data_out <= 32'h02_fb_02_c4; // ssd1 = sum >> 4
8'ha: data_out <= 32'h0d_fc_01_xx; // ssd2 = addend2
8'hb: data_out <= 32'h0d_fd_00_xx; // ssd3 = addend1
8'hc: data_out <= 32'h08_03_xx_xx; // jump to instruction 3
*/
/*
// TEST EVERY INSTRUCTION
8'h0: data_out <= 32'h0c_a2_05_xx;
8'h1: data_out <= 32'h0c_a3_03_xx;
8'h2: data_out <= 32'h00_a1_a2_a3; // add
8'h3: data_out <= 32'h01_a1_a2_a3; // sub
8'h4: data_out <= 32'h0c_a2_04_xx;
8'h5: data_out <= 32'h0c_a3_02_xx;
8'h6: data_out <= 32'h02_a1_a2_a3; // rshift
8'h7: data_out <= 32'h03_a1_a2_a3; // lshift
8'h8: data_out <= 32'h0c_a2_03_xx;
8'h9: data_out <= 32'h0c_a3_11_xx;
8'ha: data_out <= 32'h04_a1_a2_a3; // and
8'hb: data_out <= 32'h05_a1_a2_a3; // or
8'hc: data_out <= 32'h06_a1_a2_a3; // xor
8'hd: data_out <= 32'h07_a1_a2_xx; // inv
8'he: data_out <= 32'h0c_c0_00_xx;
8'hf: data_out <= 32'h0c_c1_01_xx;
8'h10: data_out <= 32'h0c_cf_ff_xx;
8'h11: data_out <= 32'h08_13_xx_xx; // jmp
8'h13: data_out <= 32'h09_ff_cf_xx; // jeq0 -1
8'h14: data_out <= 32'h09_ff_c1_xx; // jeq0 1
8'h15: data_out <= 32'h09_17_c0_xx; // jeq0 0
8'h17: data_out <= 32'h0a_ff_cf_xx; // jgt0 -1
8'h18: data_out <= 32'h0a_ff_c0_xx; // jgt0 0
8'h19: data_out <= 32'h0a_1b_c1_xx; // jgt0 1
8'h1b: data_out <= 32'h0b_ff_c0_xx; // jlt0 0
8'h1c: data_out <= 32'h0b_ff_c1_xx; // jlt0 1
8'h1d: data_out <= 32'h0b_1f_cf_xx; // jlt0 -1
8'h1f: data_out <= 32'h0c_a1_05_xx;
8'h20: data_out <= 32'h0d_a2_a1_xx; // copy
9'h21: data_out <= 32'h0d_a3_a2_xx; // copy
9'h22: data_out <= 32'h0f_xx_xx_xx; // halt
*/
default: data_out <= 32'hxx_xx_xx_xx;
endcase
end
assign Data = data_out;
endmodule
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: alt_pll.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.0.0 Build 614 04/24/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module alt_pll (
areset,
inclk0,
c0,
c1,
locked);
input areset;
input inclk0;
output c0;
output c1;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [0:0] sub_wire2 = 1'h0;
wire [4:0] sub_wire3;
wire sub_wire6;
wire sub_wire0 = inclk0;
wire [1:0] sub_wire1 = {sub_wire2, sub_wire0};
wire [1:1] sub_wire5 = sub_wire3[1:1];
wire [0:0] sub_wire4 = sub_wire3[0:0];
wire c0 = sub_wire4;
wire c1 = sub_wire5;
wire locked = sub_wire6;
altpll altpll_component (
.areset (areset),
.inclk (sub_wire1),
.clk (sub_wire3),
.locked (sub_wire6),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.fref (),
.icdrclk (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 6,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 25,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 6,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 25,
altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 83333,
altpll_component.intended_device_family = "MAX 10",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=alt_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
altpll_component.width_clock = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "50.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "12.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "50.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "alt_pll.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK3 STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK4 STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "6"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "83333"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL alt_pll_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
|
module cordic_improving(Fcw,clk,rst_n,sin,cos);
input clk;
input rst_n;
input [35:0] Fcw;
wire [35:0] phi;
wire [21:0] phi1;
reg [21:0] phi1_1,phi1_2,phi1_3,phi1_4;
wire [18:0] phi2;
wire [15:0] b;
wire [21:0] X5,Y5,X9,Y9,X17,Y17;
output [15:0] sin,cos;
//step1 adder output phi [35:0];
adder U1 (.Fcw(Fcw),.clk(clk),.rst_n(rst_n),.out(phi));
assign phi1 =phi[35:14] ;//hight 22
//step2 quadrant mirror phi2 [18:0]
quarant_mirror U2(.in(phi1[18:0]),.MSB3(phi1[19]),.out(phi2),.clk(clk));
//step3 multiplier b [15:0]
multiplier U3(.in(phi2),.out(b),.clk(clk));
//step4 rom X5 Y5 [21:0]
cordic_rom U4(
.address(b[15:12]),
.X5(X5),
.Y5(Y5),.clk(clk));
//step6 butter_fly
butterfly_step U6(.X5(X5),.Y5(Y5),.clk(clk),.b(b[11:8]),.rst_n(rst_n),.X9(X9),.Y9(Y9));
//step7 merge
merge_step U7(.X9(X9),.Y9(Y9),.b(b[7:0]),.X17(X17),.Y17(Y17),.clk(clk));
//step8 output
out_put U8(.X17(X17),.Y17(Y17),.MSB(phi1_4[21:19]),.cos(cos),.sin(sin),.clk(clk));
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// phi1<=0;
phi1_1<=0;
phi1_2<=0;
phi1_3<=0;
phi1_4<=0;
end
else begin
phi1_1<=phi1;
phi1_2<=phi1_1;
phi1_3<=phi1_2;
phi1_4<=phi1_3;
end
end
endmodule
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* Pipelining Register (Interlocked pipeline register or single-element FIFO)
*
*
* ----------------
* ----> push pop <-----
* <---- ready valid ----->
*
* ----> data_in data_out ----->
*
* ----> clk
* ----> rst_n
* ----------------
*
*
* if (ready) register can accept data on next clock edge
* i.e. (1) register is empty (!valid)
* or (2) register is (valid) and (pop) is asserted
*
* if (valid) register contents are valid
*/
`include "types.v"
typedef flit_t reg_t;
module NW_pipereg (push, pop, data_in, data_out, ready, valid, clk, rst_n);
//parameter type reg_t = flit_t;
input push, pop, clk, rst_n;
input reg_t data_in;
output reg_t data_out;
output valid, ready;
logic valid;
reg_t r;
always@(posedge clk) begin
if (!rst_n) begin
valid<=1'b0;
end else begin
// attempt to push when register isn't ready
assert (!(push & !ready)) else $fatal;
if (pop) begin
// $display ("%d: %m: pop", $time);
end
if (push) begin
r <= data_in;
valid<=1'b1;
// $display ("%d: %m: push, new data=%1d, output_port=%b", $time, data_in.data, data_in.control.output_port);
end else begin
if (pop) begin
valid<=1'b0;
end
end
end
end // always@ (posedge clk)
assign ready = !valid || pop ;
assign data_out = r;
endmodule // NW_pipereg
|
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: sa1_mult.v
// Megafunction Name(s):
// lpm_mult
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 18.1.0 Build 625 09/12/2018 SJ Lite Edition
// ************************************************************
//Copyright (C) 2018 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module sa1_mult (
clock,
dataa,
datab,
result);
input clock;
input [15:0] dataa;
input [15:0] datab;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.sclr (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 1,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 16,
lpm_mult_component.lpm_widthb = 16,
lpm_mult_component.lpm_widthp = 32;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "16"
// Retrieval info: PRIVATE: WidthB NUMERIC "16"
// Retrieval info: PRIVATE: WidthP NUMERIC "32"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "1"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "32"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 16 0 INPUT NODEFVAL "dataa[15..0]"
// Retrieval info: USED_PORT: datab 0 0 16 0 INPUT NODEFVAL "datab[15..0]"
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 16 0 dataa 0 0 16 0
// Retrieval info: CONNECT: @datab 0 0 16 0 datab 0 0 16 0
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sa1_mult_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
|
`timescale 1ns/1ps
module tb_cocotb (
//Virtual Host Interface Signals
input clk,
input rst,
output master_ready,
input in_ready,
input [31:0] in_command,
input [31:0] in_address,
input [31:0] in_data,
input [27:0] in_data_count,
input out_ready,
output out_en,
output [31:0] out_status,
output [31:0] out_address,
output [31:0] out_data,
output [27:0] out_data_count,
input [31:0] test_id,
input ih_reset,
output device_interrupt
);
//Parameters
//Registers/Wires
reg r_rst;
reg r_in_ready;
reg [31:0] r_in_command;
reg [31:0] r_in_address;
reg [31:0] r_in_data;
reg [27:0] r_in_data_count;
reg r_out_ready;
reg r_ih_reset;
//There is a bug in COCOTB when stiumlating a signal, sometimes it can be corrupted if not registered
always @ (*) r_rst = rst;
always @ (*) r_in_ready = in_ready;
always @ (*) r_in_command = in_command;
always @ (*) r_in_address = in_address;
always @ (*) r_in_data = in_data;
always @ (*) r_in_data_count = in_data_count;
always @ (*) r_out_ready = out_ready;
always @ (*) r_ih_reset = ih_reset;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone Slave 0 (SDB) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//Memory Interface
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire mem_o_we;
wire mem_o_stb;
wire mem_o_cyc;
wire [3:0] mem_o_sel;
wire [31:0] mem_o_adr;
wire [31:0] mem_o_dat;
wire [31:0] mem_i_dat;
wire mem_i_ack;
wire mem_i_int;
//Ingress Ping Pong FIFO
wire w_in_rdy;
wire w_in_act;
wire w_in_rd_stb;
wire [23:0] w_in_size;
wire [31:0] w_in_data;
//Egress Ping Pong FIFO
wire [1:0] w_out_rdy;
wire [1:0] w_out_act;
wire w_out_wr_stb;
wire [23:0] w_out_size;
wire [31:0] w_out_data;
wire w_hi_master_ready;
wire w_hi_ih_reset;
wire w_hi_ih_ready;
wire [31:0] w_hi_in_command;
wire [31:0] w_hi_in_address;
wire [31:0] w_hi_in_data;
wire [27:0] w_hi_in_data_count;
wire w_hi_oh_ready;
wire w_hi_oh_en;
wire [31:0] w_hi_out_status;
wire [31:0] w_hi_out_address;
wire [31:0] w_hi_out_data;
wire [27:0] w_hi_out_data_count;
//Cocotb to PPFIFO Bridge
adapter_cocotb_2_ppfifo#(
.IN_FIFO_DEPTH (8 ),
.OUT_FIFO_DEPTH (3 )
) ctb_2_ppfifo (
.clk (clk ),
.rst (rst ),
.o_ctb_master_ready (master_ready ),
.i_ctb_in_ready (r_in_ready ),
.i_ctb_in_command (r_in_command ),
.i_ctb_in_address (r_in_address ),
.i_ctb_in_data (r_in_data ),
.i_ctb_in_data_count (r_in_data_count ),
.i_ctb_out_ready (r_out_ready ),
.o_ctb_out_en (out_en ),
.o_ctb_out_status (out_status ),
.o_ctb_out_address (out_address ),
.o_ctb_out_data (out_data ),
.o_ctb_out_data_count (out_data_count ),
.o_in_rdy (w_in_rdy ),
.i_in_act (w_in_act ),
.o_in_size (w_in_size ),
.i_in_stb (w_in_stb ),
.o_in_data (w_in_data ),
.o_out_rdy (w_out_rdy ),
.i_out_act (w_out_act ),
.o_out_size (w_out_size ),
.i_out_stb (w_out_stb ),
.i_out_data (w_out_data )
);
ppfifo_host_interface ppfifo_host_interface (
//boilerplate
.clk (clk ),
.rst (rst ),
//master interface
.i_master_ready (w_hi_master_ready ),
.o_ih_reset (w_hi_ih_reset ),
.o_ih_ready (w_hi_ih_ready ),
.o_in_command (w_hi_in_command ),
.o_in_address (w_hi_in_address ),
.o_in_data (w_hi_in_data ),
.o_in_data_count (w_hi_in_data_count ),
.o_oh_ready (w_hi_oh_ready ),
.i_oh_en (w_hi_oh_en ),
.i_out_status (w_hi_out_status ),
.i_out_address (w_hi_out_address ),
.i_out_data (w_hi_out_data ),
.i_out_data_count (w_hi_out_data_count ),
//Ingress Ping Pong FIFO
.i_ingress_rdy (w_in_rdy ),
.o_ingress_act (w_in_act ),
.i_ingress_size (w_in_size ),
.o_ingress_stb (w_in_stb ),
.i_ingress_data (w_in_data ),
//Egress Ping Pong FIFO
.i_egress_rdy (w_out_rdy ),
.o_egress_act (w_out_act ),
.i_egress_size (w_out_size ),
.o_egress_stb (w_out_stb ),
.o_egress_data (w_out_data )
);
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (r_rst ),
.o_master_ready (w_hi_master_ready ),
.i_ih_rst (w_hi_ih_reset ),
.i_ready (w_hi_ih_ready ),
.i_command (w_hi_in_command ),
.i_address (w_hi_in_address ),
.i_data (w_hi_in_data ),
.i_data_count (w_hi_in_data_count ),
.i_out_ready (w_hi_oh_ready ),
.o_en (w_hi_oh_en ),
.o_status (w_hi_out_status ),
.o_address (w_hi_out_address ),
.o_data (w_hi_out_data ),
.o_data_count (w_hi_out_data_count ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_msk (w_wbp_msk ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
pf_hi_tester s1 (
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_sel (4'b1111 ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (r_rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (r_rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (r_rst ),
//masters
.i_m1_we (mem_o_we ),
.i_m1_stb (mem_o_stb ),
.i_m1_cyc (mem_o_cyc ),
.i_m1_sel (mem_o_sel ),
.i_m1_dat (mem_o_dat ),
.i_m1_adr (mem_o_adr ),
.o_m1_dat (mem_i_dat ),
.o_m1_ack (mem_i_ack ),
.o_m1_int (mem_i_int ),
.i_m0_we (w_sm0_i_wbs_we ),
.i_m0_stb (w_sm0_i_wbs_stb ),
.i_m0_cyc (w_sm0_i_wbs_cyc ),
.i_m0_sel (w_sm0_i_wbs_sel ),
.i_m0_dat (w_sm0_i_wbs_dat ),
.i_m0_adr (w_sm0_i_wbs_adr ),
.o_m0_dat (w_sm0_o_wbs_dat ),
.o_m0_ack (w_sm0_o_wbs_ack ),
.o_m0_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
wb_bram #(
.DATA_WIDTH (32 ),
.ADDR_WIDTH (10 )
)bram(
.clk (clk ),
.rst (r_rst ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
//Disable Slave 0
assign w_wbs0_int = 0;
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign device_interrupt = w_wbp_int;
/*
READ ME IF YOUR MODULE WILL INTERFACE WITH MEMORY
If you want to talk to memory over the wishbone bus directly, your module must control the following signals:
(Your module will be a wishbone master)
mem_o_we
mem_o_stb
mem_o_cyc
mem_o_sel
mem_o_adr
mem_o_dat
mem_i_dat
mem_i_ack
mem_i_int
Currently this bus is disabled so if will not interface with memory these signals can be left
For a reference check out wb_sd_host
*/
assign mem_o_we = 0;
assign mem_o_stb = 0;
assign mem_o_cyc = 0;
assign mem_o_sel = 0;
assign mem_o_adr = 0;
assign mem_o_dat = 0;
//Submodules
//Asynchronous Logic
//Synchronous Logic
//Simulation Control
initial begin
$dumpfile ("design.vcd");
$dumpvars(0, tb_cocotb);
end
endmodule
|
`define K 32'h26dd3b6a // = 0.6072529350088814
`define BETA_0 32'h3243f6a9 // = atan 2^0 = 0.7853981633974483
`define BETA_1 32'h1dac6705 // = atan 2^(-1) = 0.4636476090008061
`define BETA_2 32'h0fadbafd // = atan 2^(-2) = 0.24497866312686414
`define BETA_3 32'h07f56ea7 // = atan 2^(-3) = 0.12435499454676144
`define BETA_4 32'h03feab77 // = atan 2^(-4) = 0.06241880999595735
`define BETA_5 32'h01ffd55c // = atan 2^(-5) = 0.031239833430268277
`define BETA_6 32'h00fffaab // = atan 2^(-6) = 0.015623728620476831
`define BETA_7 32'h007fff55 // = atan 2^(-7) = 0.007812341060101111
`define BETA_8 32'h003fffeb // = atan 2^(-8) = 0.0039062301319669718
`define BETA_9 32'h001ffffd // = atan 2^(-9) = 0.0019531225164788188
`define BETA_10 32'h00100000 // = atan 2^(-10) = 0.0009765621895593195
`define BETA_11 32'h00080000 // = atan 2^(-11) = 0.0004882812111948983
`define BETA_12 32'h00040000 // = atan 2^(-12) = 0.00024414062014936177
`define BETA_13 32'h00020000 // = atan 2^(-13) = 0.00012207031189367021
`define BETA_14 32'h00010000 // = atan 2^(-14) = 6.103515617420877e-05
`define BETA_15 32'h00008000 // = atan 2^(-15) = 3.0517578115526096e-05
`define BETA_16 32'h00004000 // = atan 2^(-16) = 1.5258789061315762e-05
`define BETA_17 32'h00002000 // = atan 2^(-17) = 7.62939453110197e-06
`define BETA_18 32'h00001000 // = atan 2^(-18) = 3.814697265606496e-06
`define BETA_19 32'h00000800 // = atan 2^(-19) = 1.907348632810187e-06
`define BETA_20 32'h00000400 // = atan 2^(-20) = 9.536743164059608e-07
`define BETA_21 32'h00000200 // = atan 2^(-21) = 4.7683715820308884e-07
`define BETA_22 32'h00000100 // = atan 2^(-22) = 2.3841857910155797e-07
`define BETA_23 32'h00000080 // = atan 2^(-23) = 1.1920928955078068e-07
`define BETA_24 32'h00000040 // = atan 2^(-24) = 5.960464477539055e-08
`define BETA_25 32'h00000020 // = atan 2^(-25) = 2.9802322387695303e-08
`define BETA_26 32'h00000010 // = atan 2^(-26) = 1.4901161193847655e-08
`define BETA_27 32'h00000008 // = atan 2^(-27) = 7.450580596923828e-09
`define BETA_28 32'h00000004 // = atan 2^(-28) = 3.725290298461914e-09
`define BETA_29 32'h00000002 // = atan 2^(-29) = 1.862645149230957e-09
`define BETA_30 32'h00000001 // = atan 2^(-30) = 9.313225746154785e-10
`define BETA_31 32'h00000000 // = atan 2^(-31) = 4.656612873077393e-10
module cordic(
angle,
clock, // Master clock
reset, // Master asynchronous reset (active-high)
start, // An input signal that the user of this module should set to high when computation should begin
angle_in, // Input angle
cos_out, // Output value for cosine of angle
sin_out // Output value for sine of angle
);
input clock;
input reset;
input start;
input [31:0] angle_in;
output [31:0] cos_out;
output [31:0] sin_out;
wire [31:0] cos_out = cos;
wire [31:0] sin_out = sin;
reg [31:0] cos;
reg [31:0] sin;
reg [31:0] angle;
reg [4:0] count;
reg state;
reg [31:0] cos_next;
reg [31:0] sin_next;
reg [31:0] angle_next;
reg [4:0] count_next;
reg state_next;
always @(posedge clock or posedge reset) begin
if (reset) begin
cos <= 0;
sin <= 0;
angle <= 0;
count <= 0;
state <= 0;
end else begin
cos <= cos_next;
sin <= sin_next;
angle <= angle_next;
count <= count_next;
state <= state_next;
end
end
always @* begin
// Set all logic regs to a value to prevent any of them holding the value
// from last tick and hence being misinterpreted as hardware registers.
cos_next = cos;
sin_next = sin;
angle_next = angle;
count_next = count;
state_next = state;
if (state) begin
// Compute mode.
cos_next = cos + (direction_negative ? sin_shr : -sin_shr);
sin_next = sin + (direction_negative ? -cos_shr : cos_shr);
angle_next = angle + (direction_negative ? beta : -beta);
count_next = count + 1;
if (count == 31) begin
// If this is the last iteration, go back to the idle state.
state_next = 0;
end
end
else begin
// Idle mode.
if (start) begin
cos_next = `K; // Set up initial value for cos.
sin_next = 0; // Set up initial value for sin.
angle_next = angle_in; // Latch input angle into the angle register.
count_next = 0; // Set up counter.
state_next = 1; // Go to compute mode.
end
end
end
wire [31:0] cos_signbits = {32{cos[31]}};
wire [31:0] sin_signbits = {32{sin[31]}};
wire [31:0] cos_shr = {cos_signbits, cos} >> count;
wire [31:0] sin_shr = {sin_signbits, sin} >> count;
wire direction_negative = angle[31];
wire [31:0] beta_lut [0:31];
assign beta_lut[0] = `BETA_0;
assign beta_lut[1] = `BETA_1;
assign beta_lut[2] = `BETA_2;
assign beta_lut[3] = `BETA_3;
assign beta_lut[4] = `BETA_4;
assign beta_lut[5] = `BETA_5;
assign beta_lut[6] = `BETA_6;
assign beta_lut[7] = `BETA_7;
assign beta_lut[8] = `BETA_8;
assign beta_lut[9] = `BETA_9;
assign beta_lut[10] = `BETA_10;
assign beta_lut[11] = `BETA_11;
assign beta_lut[12] = `BETA_12;
assign beta_lut[13] = `BETA_13;
assign beta_lut[14] = `BETA_14;
assign beta_lut[15] = `BETA_15;
assign beta_lut[16] = `BETA_16;
assign beta_lut[17] = `BETA_17;
assign beta_lut[18] = `BETA_18;
assign beta_lut[19] = `BETA_19;
assign beta_lut[20] = `BETA_20;
assign beta_lut[21] = `BETA_21;
assign beta_lut[22] = `BETA_22;
assign beta_lut[23] = `BETA_23;
assign beta_lut[24] = `BETA_24;
assign beta_lut[25] = `BETA_25;
assign beta_lut[26] = `BETA_26;
assign beta_lut[27] = `BETA_27;
assign beta_lut[28] = `BETA_28;
assign beta_lut[29] = `BETA_29;
assign beta_lut[30] = `BETA_30;
assign beta_lut[31] = `BETA_31;
wire [31:0] beta = beta_lut[count];
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A22OI_2_V
`define SKY130_FD_SC_HDLL__A22OI_2_V
/**
* a22oi: 2-input AND into both inputs of 2-input NOR.
*
* Y = !((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22oi with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a22oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_2 (
Y ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a22oi_2 (
Y ,
A1,
A2,
B1,
B2
);
output Y ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a22oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A22OI_2_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_PP_V
/**
* fill_diode: Fill diode.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__fill_diode (
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
input VPWR;
input VGND;
input VPB ;
input VNB ;
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__FILL_DIODE_BEHAVIORAL_PP_V |
(** * MoreInd: More on Induction *)
Require Export "ProofObjects".
(* ##################################################### *)
(** * Induction Principles *)
(** This is a good point to pause and take a deeper look at induction
principles.
Every time we declare a new [Inductive] datatype, Coq
automatically generates and proves an _induction principle_
for this type.
The induction principle for a type [t] is called [t_ind]. Here is
the one for natural numbers: *)
Check nat_ind.
(* ===> nat_ind :
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** *** *)
(** The [induction] tactic is a straightforward wrapper that, at
its core, simply performs [apply t_ind]. To see this more
clearly, let's experiment a little with using [apply nat_ind]
directly, instead of the [induction] tactic, to carry out some
proofs. Here, for example, is an alternate proof of a theorem
that we saw in the [Basics] chapter. *)
Theorem mult_0_r' : forall n:nat,
n * 0 = 0.
Proof.
apply nat_ind.
Case "O". reflexivity.
Case "S". simpl. intros n IHn. rewrite -> IHn.
reflexivity. Qed.
(** This proof is basically the same as the earlier one, but a
few minor differences are worth noting. First, in the induction
step of the proof (the ["S"] case), we have to do a little
bookkeeping manually (the [intros]) that [induction] does
automatically.
Second, we do not introduce [n] into the context before applying
[nat_ind] -- the conclusion of [nat_ind] is a quantified formula,
and [apply] needs this conclusion to exactly match the shape of
the goal state, including the quantifier. The [induction] tactic
works either with a variable in the context or a quantified
variable in the goal.
Third, the [apply] tactic automatically chooses variable names for
us (in the second subgoal, here), whereas [induction] lets us
specify (with the [as...] clause) what names should be used. The
automatic choice is actually a little unfortunate, since it
re-uses the name [n] for a variable that is different from the [n]
in the original theorem. This is why the [Case] annotation is
just [S] -- if we tried to write it out in the more explicit form
that we've been using for most proofs, we'd have to write [n = S
n], which doesn't make a lot of sense! All of these conveniences
make [induction] nicer to use in practice than applying induction
principles like [nat_ind] directly. But it is important to
realize that, modulo this little bit of bookkeeping, applying
[nat_ind] is what we are really doing. *)
(** **** Exercise: 2 stars, optional (plus_one_r') *)
(** Complete this proof as we did [mult_0_r'] above, without using
the [induction] tactic. *)
Theorem plus_one_r' : forall n:nat,
n + 1 = S n.
Proof.
apply nat_ind.
Case "O".
reflexivity.
Case "S".
intros n H.
simpl.
rewrite -> H.
reflexivity.
Qed.
(** [] *)
(** Coq generates induction principles for every datatype defined with
[Inductive], including those that aren't recursive. (Although
we don't need induction to prove properties of non-recursive
datatypes, the idea of an induction principle still makes sense
for them: it gives a way to prove that a property holds for all
values of the type.)
These generated principles follow a similar pattern. If we define a
type [t] with constructors [c1] ... [cn], Coq generates a theorem
with this shape:
t_ind :
forall P : t -> Prop,
... case for c1 ... ->
... case for c2 ... ->
...
... case for cn ... ->
forall n : t, P n
The specific shape of each case depends on the arguments to the
corresponding constructor. Before trying to write down a general
rule, let's look at some more examples. First, an example where
the constructors take no arguments: *)
Inductive yesno : Type :=
| yes : yesno
| no : yesno.
Check yesno_ind.
(* ===> yesno_ind : forall P : yesno -> Prop,
P yes ->
P no ->
forall y : yesno, P y *)
(** **** Exercise: 1 star, optional (rgb) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive rgb : Type :=
| red : rgb
| green : rgb
| blue : rgb.
(*
rgb_ind : forall P : rgb -> Prop, P red -> P green -> P blue -> forall x : rgb, P x
*)
Check rgb_ind.
(** [] *)
(** Here's another example, this time with one of the constructors
taking some arguments. *)
Inductive natlist : Type :=
| nnil : natlist
| ncons : nat -> natlist -> natlist.
Check natlist_ind.
(* ===> (modulo a little variable renaming for clarity)
natlist_ind :
forall P : natlist -> Prop,
P nnil ->
(forall (n : nat) (l : natlist), P l -> P (ncons n l)) ->
forall n : natlist, P n *)
(** **** Exercise: 1 star, optional (natlist1) *)
(** Suppose we had written the above definition a little
differently: *)
Inductive natlist1 : Type :=
| nnil1 : natlist1
| nsnoc1 : natlist1 -> nat -> natlist1.
(*
natlist1_ind :
forall P : natlist1 -> Prop,
P nnil1 ->
(forall l : natlist1, P l -> forall n : nat, P (nsnoc1 l n)) ->
forall n : natlist1, P n
*)
(** Now what will the induction principle look like? *)
(** [] *)
(** From these examples, we can extract this general rule:
- The type declaration gives several constructors; each
corresponds to one clause of the induction principle.
- Each constructor [c] takes argument types [a1]...[an].
- Each [ai] can be either [t] (the datatype we are defining) or
some other type [s].
- The corresponding case of the induction principle
says (in English):
- "for all values [x1]...[xn] of types [a1]...[an], if [P]
holds for each of the inductive arguments (each [xi] of
type [t]), then [P] holds for [c x1 ... xn]".
*)
(** **** Exercise: 1 star, optional (byntree_ind) *)
(** Write out the induction principle that Coq will generate for the
following datatype. Write down your answer on paper or type it
into a comment, and then compare it with what Coq prints. *)
Inductive byntree : Type :=
| bempty : byntree
| bleaf : yesno -> byntree
| nbranch : yesno -> byntree -> byntree -> byntree.
(*
byntree_ind : forall P : byntree -> Prop,
P bempty -> (forall y : yesno, P (bleaf y)) -> (forall (y : yesno) (b1 : byntree),
P b1 -> forall b2 : byntree, P b2 -> P (nbranch y b1 b2)) -> forall b : byntree, P b
*)
(** [] *)
(** **** Exercise: 1 star, optional (ex_set) *)
(** Here is an induction principle for an inductively defined
set.
ExSet_ind :
forall P : ExSet -> Prop,
(forall b : bool, P (con1 b)) ->
(forall (n : nat) (e : ExSet), P e -> P (con2 n e)) ->
forall e : ExSet, P e
Give an [Inductive] definition of [ExSet]: *)
Inductive ExSet : Type :=
| con1 : bool -> ExSet
| con2 : nat -> ExSet -> ExSet
.
(** [] *)
(** What about polymorphic datatypes?
The inductive definition of polymorphic lists
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
is very similar to that of [natlist]. The main difference is
that, here, the whole definition is _parameterized_ on a set [X]:
that is, we are defining a _family_ of inductive types [list X],
one for each [X]. (Note that, wherever [list] appears in the body
of the declaration, it is always applied to the parameter [X].)
The induction principle is likewise parameterized on [X]:
list_ind :
forall (X : Type) (P : list X -> Prop),
P [] ->
(forall (x : X) (l : list X), P l -> P (x :: l)) ->
forall l : list X, P l
Note the wording here (and, accordingly, the form of [list_ind]):
The _whole_ induction principle is parameterized on [X]. That is,
[list_ind] can be thought of as a polymorphic function that, when
applied to a type [X], gives us back an induction principle
specialized to the type [list X]. *)
(** **** Exercise: 1 star, optional (tree) *)
(** Write out the induction principle that Coq will generate for
the following datatype. Compare your answer with what Coq
prints. *)
Inductive tree (X:Type) : Type :=
| leaf : X -> tree X
| node : tree X -> tree X -> tree X.
Check tree_ind.
(*
tree_ind : forall (X : Type) (P : tree X -> Prop),
(forall x : X, P (leaf X x)) -> (forall t1 : tree X, P t1 -> forall t2 : tree X, P t2 ->
P (node X t1 t2)) -> forall t : tree X ,P t
*)
(** [] *)
(** **** Exercise: 1 star, optional (mytype) *)
(** Find an inductive definition that gives rise to the
following induction principle:
mytype_ind :
forall (X : Type) (P : mytype X -> Prop),
(forall x : X, P (constr1 X x)) ->
(forall n : nat, P (constr2 X n)) ->
(forall m : mytype X, P m ->
forall n : nat, P (constr3 X m n)) ->
forall m : mytype X, P m
*)
Inductive mytype (X : Type) : Type :=
| constr1 : X -> mytype X
| constr2 : nat -> mytype X
| constr3 : mytype X -> nat -> mytype X.
(** [] *)
(** **** Exercise: 1 star, optional (foo) *)
(** Find an inductive definition that gives rise to the
following induction principle:
foo_ind :
forall (X Y : Type) (P : foo X Y -> Prop),
(forall x : X, P (bar X Y x)) ->
(forall y : Y, P (baz X Y y)) ->
(forall f1 : nat -> foo X Y,
(forall n : nat, P (f1 n)) -> P (quux X Y f1)) ->
forall f2 : foo X Y, P f2
*)
Inductive foo (X Y : Type) : Type :=
| bar : X -> foo X Y
| baz : Y -> foo X Y
| qunn : (nat -> foo X Y) -> foo X Y.
(** [] *)
(** **** Exercise: 1 star, optional (foo') *)
(** Consider the following inductive definition: *)
Inductive foo' (X:Type) : Type :=
| C1 : list X -> foo' X -> foo' X
| C2 : foo' X.
(** What induction principle will Coq generate for [foo']? Fill
in the blanks, then check your answer with Coq.)
foo'_ind :
forall (X : Type) (P : foo' X -> Prop),
(forall (l : list X) (f : foo' X),
P f ->
P (C1 X l f) ) ->
P (C2 X) ->
forall f : foo' X, P f
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Hypotheses *)
(** Where does the phrase "induction hypothesis" fit into this story?
The induction principle for numbers
forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n
is a generic statement that holds for all propositions
[P] (strictly speaking, for all families of propositions [P]
indexed by a number [n]). Each time we use this principle, we
are choosing [P] to be a particular expression of type
[nat->Prop].
We can make the proof more explicit by giving this expression a
name. For example, instead of stating the theorem [mult_0_r] as
"[forall n, n * 0 = 0]," we can write it as "[forall n, P_m0r
n]", where [P_m0r] is defined as... *)
Definition P_m0r (n:nat) : Prop :=
n * 0 = 0.
(** ... or equivalently... *)
Definition P_m0r' : nat->Prop :=
fun n => n * 0 = 0.
(** Now when we do the proof it is easier to see where [P_m0r]
appears. *)
Theorem mult_0_r'' : forall n:nat,
P_m0r n.
Proof.
apply nat_ind.
Case "n = O". reflexivity.
Case "n = S n'".
(* Note the proof state at this point! *)
intros n IHn.
unfold P_m0r in IHn. unfold P_m0r. simpl. apply IHn. Qed.
(** This extra naming step isn't something that we'll do in
normal proofs, but it is useful to do it explicitly for an example
or two, because it allows us to see exactly what the induction
hypothesis is. If we prove [forall n, P_m0r n] by induction on
[n] (using either [induction] or [apply nat_ind]), we see that the
first subgoal requires us to prove [P_m0r 0] ("[P] holds for
zero"), while the second subgoal requires us to prove [forall n',
P_m0r n' -> P_m0r n' (S n')] (that is "[P] holds of [S n'] if it
holds of [n']" or, more elegantly, "[P] is preserved by [S]").
The _induction hypothesis_ is the premise of this latter
implication -- the assumption that [P] holds of [n'], which we are
allowed to use in proving that [P] holds for [S n']. *)
(* ##################################################### *)
(** ** More on the [induction] Tactic *)
(** The [induction] tactic actually does even more low-level
bookkeeping for us than we discussed above.
Recall the informal statement of the induction principle for
natural numbers:
- If [P n] is some proposition involving a natural number n, and
we want to show that P holds for _all_ numbers n, we can
reason like this:
- show that [P O] holds
- show that, if [P n'] holds, then so does [P (S n')]
- conclude that [P n] holds for all n.
So, when we begin a proof with [intros n] and then [induction n],
we are first telling Coq to consider a _particular_ [n] (by
introducing it into the context) and then telling it to prove
something about _all_ numbers (by using induction).
What Coq actually does in this situation, internally, is to
"re-generalize" the variable we perform induction on. For
example, in our original proof that [plus] is associative...
*)
Theorem plus_assoc' : forall n m p : nat,
n + (m + p) = (n + m) + p.
Proof.
(* ...we first introduce all 3 variables into the context,
which amounts to saying "Consider an arbitrary [n], [m], and
[p]..." *)
intros n m p.
(* ...We now use the [induction] tactic to prove [P n] (that
is, [n + (m + p) = (n + m) + p]) for _all_ [n],
and hence also for the particular [n] that is in the context
at the moment. *)
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
(* In the second subgoal generated by [induction] -- the
"inductive step" -- we must prove that [P n'] implies
[P (S n')] for all [n']. The [induction] tactic
automatically introduces [n'] and [P n'] into the context
for us, leaving just [P (S n')] as the goal. *)
simpl. rewrite -> IHn'. reflexivity. Qed.
(** It also works to apply [induction] to a variable that is
quantified in the goal. *)
Theorem plus_comm' : forall n m : nat,
n + m = m + n.
Proof.
induction n as [| n'].
Case "n = O". intros m. rewrite -> plus_0_r. reflexivity.
Case "n = S n'". intros m. simpl. rewrite -> IHn'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** Note that [induction n] leaves [m] still bound in the goal --
i.e., what we are proving inductively is a statement beginning
with [forall m].
If we do [induction] on a variable that is quantified in the goal
_after_ some other quantifiers, the [induction] tactic will
automatically introduce the variables bound by these quantifiers
into the context. *)
Theorem plus_comm'' : forall n m : nat,
n + m = m + n.
Proof.
(* Let's do induction on [m] this time, instead of [n]... *)
induction m as [| m'].
Case "m = O". simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** **** Exercise: 1 star, optional (plus_explicit_prop) *)
(** Rewrite both [plus_assoc'] and [plus_comm'] and their proofs in
the same style as [mult_0_r''] above -- that is, for each theorem,
give an explicit [Definition] of the proposition being proved by
induction, and state the theorem and proof in terms of this
defined proposition. *)
Definition P_plus_assoc (n m p : nat) : Prop := n + (m + p) = (n + m) + p.
Theorem plus_assoc'' : forall n m p : nat, P_plus_assoc n m p.
Proof.
intros n m p.
induction n as [| n'].
Case "n = O". reflexivity.
Case "n = S n'".
unfold P_plus_assoc. unfold P_plus_assoc in IHn'. simpl.
rewrite -> IHn'. reflexivity. Qed.
Definition P_plus_comm (n m : nat) : Prop := n + m = m + n.
Theorem plus_comm''' : forall n m : nat, P_plus_comm n m.
Proof.
induction m as [| m'].
Case "m = O". unfold P_plus_comm. simpl. rewrite -> plus_0_r. reflexivity.
Case "m = S m'". unfold P_plus_comm. unfold P_plus_comm in IHm'. simpl. rewrite <- IHm'.
rewrite <- plus_n_Sm. reflexivity. Qed.
(** [] *)
(** ** Generalizing Inductions. *)
(** One potentially confusing feature of the [induction] tactic is
that it happily lets you try to set up an induction over a term
that isn't sufficiently general. The net effect of this will be
to lose information (much as [destruct] can do), and leave
you unable to complete the proof. Here's an example: *)
Lemma one_not_beautiful_FAILED: ~ beautiful 1.
Proof.
intro H.
(* Just doing an [inversion] on [H] won't get us very far in the [b_sum]
case. (Try it!). So we'll need induction. A naive first attempt: *)
induction H.
(* But now, although we get four cases, as we would expect from
the definition of [beautiful], we lose all information about [H] ! *)
Abort.
(** The problem is that [induction] over a Prop only works properly over
completely general instances of the Prop, i.e. one in which all
the arguments are free (unconstrained) variables.
In this respect it behaves more
like [destruct] than like [inversion].
When you're tempted to do use [induction] like this, it is generally
an indication that you need to be proving something more general.
But in some cases, it suffices to pull out any concrete arguments
into separate equations, like this: *)
Lemma one_not_beautiful: forall n, n = 1 -> ~ beautiful n.
Proof.
intros n E H.
induction H as [| | | p q Hp IHp Hq IHq].
Case "b_0".
inversion E.
Case "b_3".
inversion E.
Case "b_5".
inversion E.
Case "b_sum".
(* the rest is a tedious case analysis *)
destruct p as [|p'].
SCase "p = 0".
destruct q as [|q'].
SSCase "q = 0".
inversion E.
SSCase "q = S q'".
apply IHq. apply E.
SCase "p = S p'".
destruct q as [|q'].
SSCase "q = 0".
apply IHp. rewrite plus_0_r in E. apply E.
SSCase "q = S q'".
simpl in E. inversion E. destruct p'. inversion H0. inversion H0.
Qed.
(** There's a handy [remember] tactic that can generate the second
proof state out of the original one. *)
Lemma one_not_beautiful': ~ beautiful 1.
Proof.
intros H.
remember 1 as n eqn:E.
(* now carry on as above *)
induction H.
Admitted.
(* ####################################################### *)
(** * Informal Proofs (Advanced) *)
(** Q: What is the relation between a formal proof of a proposition
[P] and an informal proof of the same proposition [P]?
A: The latter should _teach_ the reader how to produce the
former.
Q: How much detail is needed??
Unfortunately, There is no single right answer; rather, there is a
range of choices.
At one end of the spectrum, we can essentially give the reader the
whole formal proof (i.e., the informal proof amounts to just
transcribing the formal one into words). This gives the reader
the _ability_ to reproduce the formal one for themselves, but it
doesn't _teach_ them anything.
At the other end of the spectrum, we can say "The theorem is true
and you can figure out why for yourself if you think about it hard
enough." This is also not a good teaching strategy, because
usually writing the proof requires some deep insights into the
thing we're proving, and most readers will give up before they
rediscover all the same insights as we did.
In the middle is the golden mean -- a proof that includes all of
the essential insights (saving the reader the hard part of work
that we went through to find the proof in the first place) and
clear high-level suggestions for the more routine parts to save the
reader from spending too much time reconstructing these
parts (e.g., what the IH says and what must be shown in each case
of an inductive proof), but not so much detail that the main ideas
are obscured.
Another key point: if we're comparing a formal proof of a
proposition [P] and an informal proof of [P], the proposition [P]
doesn't change. That is, formal and informal proofs are _talking
about the same world_ and they _must play by the same rules_. *)
(** ** Informal Proofs by Induction *)
(** Since we've spent much of this chapter looking "under the hood" at
formal proofs by induction, now is a good moment to talk a little
about _informal_ proofs by induction.
In the real world of mathematical communication, written proofs
range from extremely longwinded and pedantic to extremely brief
and telegraphic. The ideal is somewhere in between, of course,
but while you are getting used to the style it is better to start
out at the pedantic end. Also, during the learning phase, it is
probably helpful to have a clear standard to compare against.
With this in mind, we offer two templates below -- one for proofs
by induction over _data_ (i.e., where the thing we're doing
induction on lives in [Type]) and one for proofs by induction over
_evidence_ (i.e., where the inductively defined thing lives in
[Prop]). In the rest of this course, please follow one of the two
for _all_ of your inductive proofs. *)
(** *** Induction Over an Inductively Defined Set *)
(** _Template_:
- _Theorem_: <Universally quantified proposition of the form
"For all [n:S], [P(n)]," where [S] is some inductively defined
set.>
_Proof_: By induction on [n].
<one case for each constructor [c] of [S]...>
- Suppose [n = c a1 ... ak], where <...and here we state
the IH for each of the [a]'s that has type [S], if any>.
We must show <...and here we restate [P(c a1 ... ak)]>.
<go on and prove [P(n)] to finish the case...>
- <other cases similarly...> []
_Example_:
- _Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index (S n) l = None].
_Proof_: By induction on [l].
- Suppose [l = []]. We must show, for all numbers [n],
that, if length [[] = n], then [index (S n) [] =
None].
This follows immediately from the definition of index.
- Suppose [l = x :: l'] for some [x] and [l'], where
[length l' = n'] implies [index (S n') l' = None], for
any number [n']. We must show, for all [n], that, if
[length (x::l') = n] then [index (S n) (x::l') =
None].
Let [n] be a number with [length l = n]. Since
length l = length (x::l') = S (length l'),
it suffices to show that
index (S (length l')) l' = None.
]]
But this follows directly from the induction hypothesis,
picking [n'] to be length [l']. [] *)
(** *** Induction Over an Inductively Defined Proposition *)
(** Since inductively defined proof objects are often called
"derivation trees," this form of proof is also known as _induction
on derivations_.
_Template_:
- _Theorem_: <Proposition of the form "[Q -> P]," where [Q] is
some inductively defined proposition (more generally,
"For all [x] [y] [z], [Q x y z -> P x y z]")>
_Proof_: By induction on a derivation of [Q]. <Or, more
generally, "Suppose we are given [x], [y], and [z]. We
show that [Q x y z] implies [P x y z], by induction on a
derivation of [Q x y z]"...>
<one case for each constructor [c] of [Q]...>
- Suppose the final rule used to show [Q] is [c]. Then
<...and here we state the types of all of the [a]'s
together with any equalities that follow from the
definition of the constructor and the IH for each of
the [a]'s that has type [Q], if there are any>. We must
show <...and here we restate [P]>.
<go on and prove [P] to finish the case...>
- <other cases similarly...> []
_Example_
- _Theorem_: The [<=] relation is transitive -- i.e., for all
numbers [n], [m], and [o], if [n <= m] and [m <= o], then
[n <= o].
_Proof_: By induction on a derivation of [m <= o].
- Suppose the final rule used to show [m <= o] is
[le_n]. Then [m = o] and we must show that [n <= m],
which is immediate by hypothesis.
- Suppose the final rule used to show [m <= o] is
[le_S]. Then [o = S o'] for some [o'] with [m <= o'].
We must show that [n <= S o'].
By induction hypothesis, [n <= o'].
But then, by [le_S], [n <= S o']. [] *)
(* ##################################################### *)
(** * Induction Principles in [Prop] (Advanced) *)
(** The remainder of this chapter offers some additional details on
how induction works in Coq, the process of building proof trees,
and the "trusted computing base" that underlies Coq proofs. It
can safely be skimmed on a first reading. (As with the other
advanced sections, we recommend skimming rather than skipping over
it outright: it answers some questions that occur to many Coq
users at some point, so it is useful to have a rough idea of
what's here.) *)
(** Earlier, we looked in detail at the induction principles that Coq
generates for inductively defined _sets_. The induction
principles for inductively defined _propositions_ like [gorgeous]
are a tiny bit more complicated. As with all induction
principles, we want to use the induction principle on [gorgeous]
to prove things by inductively considering the possible shapes
that something in [gorgeous] can have -- either it is evidence
that [0] is gorgeous, or it is evidence that, for some [n], [3+n]
is gorgeous, or it is evidence that, for some [n], [5+n] is
gorgeous and it includes evidence that [n] itself is. Intuitively
speaking, however, what we want to prove are not statements about
_evidence_ but statements about _numbers_. So we want an
induction principle that lets us prove properties of numbers by
induction on evidence.
For example, from what we've said so far, you might expect the
inductive definition of [gorgeous]...
Inductive gorgeous : nat -> Prop :=
g_0 : gorgeous 0
| g_plus3 : forall n, gorgeous n -> gorgeous (3+m)
| g_plus5 : forall n, gorgeous n -> gorgeous (5+m).
...to give rise to an induction principle that looks like this...
gorgeous_ind_max :
forall P : (forall n : nat, gorgeous n -> Prop),
P O g_0 ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (3+m) (g_plus3 m e) ->
(forall (m : nat) (e : gorgeous m),
P m e -> P (5+m) (g_plus5 m e) ->
forall (n : nat) (e : gorgeous n), P n e
... because:
- Since [gorgeous] is indexed by a number [n] (every [gorgeous]
object [e] is a piece of evidence that some particular number
[n] is gorgeous), the proposition [P] is parameterized by both
[n] and [e] -- that is, the induction principle can be used to
prove assertions involving both a gorgeous number and the
evidence that it is gorgeous.
- Since there are three ways of giving evidence of gorgeousness
([gorgeous] has three constructors), applying the induction
principle generates three subgoals:
- We must prove that [P] holds for [O] and [b_0].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [3+m] and [g_plus3 n e].
- We must prove that, whenever [n] is a gorgeous
number and [e] is an evidence of its gorgeousness,
if [P] holds of [n] and [e],
then it also holds of [5+m] and [g_plus5 n e].
- If these subgoals can be proved, then the induction principle
tells us that [P] is true for _all_ gorgeous numbers [n] and
evidence [e] of their gorgeousness.
But this is a little more flexibility than we actually need or
want: it is giving us a way to prove logical assertions where the
assertion involves properties of some piece of _evidence_ of
gorgeousness, while all we really care about is proving
properties of _numbers_ that are gorgeous -- we are interested in
assertions about numbers, not about evidence. It would therefore
be more convenient to have an induction principle for proving
propositions [P] that are parameterized just by [n] and whose
conclusion establishes [P] for all gorgeous numbers [n]:
forall P : nat -> Prop,
... ->
forall n : nat, gorgeous n -> P n
For this reason, Coq actually generates the following simplified
induction principle for [gorgeous]: *)
Check gorgeous_ind.
(* ===> gorgeous_ind
: forall P : nat -> Prop,
P 0 ->
(forall n : nat, gorgeous n -> P n -> P (3 + n)) ->
(forall n : nat, gorgeous n -> P n -> P (5 + n)) ->
forall n : nat, gorgeous n -> P n *)
(** In particular, Coq has dropped the evidence term [e] as a
parameter of the the proposition [P], and consequently has
rewritten the assumption [forall (n : nat) (e: gorgeous n), ...]
to be [forall (n : nat), gorgeous n -> ...]; i.e., we no longer
require explicit evidence of the provability of [gorgeous n]. *)
(** In English, [gorgeous_ind] says:
- Suppose, [P] is a property of natural numbers (that is, [P n] is
a [Prop] for every [n]). To show that [P n] holds whenever [n]
is gorgeous, it suffices to show:
- [P] holds for [0],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [3+n],
- for any [n], if [n] is gorgeous and [P] holds for
[n], then [P] holds for [5+n]. *)
(** As expected, we can apply [gorgeous_ind] directly instead of using [induction]. *)
Theorem gorgeous__beautiful' : forall n, gorgeous n -> beautiful n.
Proof.
intros.
apply gorgeous_ind.
Case "g_0".
apply b_0.
Case "g_plus3".
intros.
apply b_sum. apply b_3.
apply H1.
Case "g_plus5".
intros.
apply b_sum. apply b_5.
apply H1.
apply H.
Qed.
(** The precise form of an Inductive definition can affect the
induction principle Coq generates.
For example, in [Logic], we have defined [<=] as: *)
(* Inductive le : nat -> nat -> Prop :=
| le_n : forall n, le n n
| le_S : forall n m, (le n m) -> (le n (S m)). *)
(** This definition can be streamlined a little by observing that the
left-hand argument [n] is the same everywhere in the definition,
so we can actually make it a "general parameter" to the whole
definition, rather than an argument to each constructor. *)
Inductive le (n:nat) : nat -> Prop :=
| le_n : le n n
| le_S : forall m, (le n m) -> (le n (S m)).
Notation "m <= n" := (le m n).
(** The second one is better, even though it looks less symmetric.
Why? Because it gives us a simpler induction principle. *)
Check le_ind.
(* ===> forall (n : nat) (P : nat -> Prop),
P n ->
(forall m : nat, n <= m -> P m -> P (S m)) ->
forall n0 : nat, n <= n0 -> P n0 *)
(** By contrast, the induction principle that Coq calculates for the
first definition has a lot of extra quantifiers, which makes it
messier to work with when proving things by induction. Here is
the induction principle for the first [le]: *)
(* le_ind :
forall P : nat -> nat -> Prop,
(forall n : nat, P n n) ->
(forall n m : nat, le n m -> P n m -> P n (S m)) ->
forall n n0 : nat, le n n0 -> P n n0 *)
(* ##################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (foo_ind_principle) *)
(** Suppose we make the following inductive definition:
Inductive foo (X : Set) (Y : Set) : Set :=
| foo1 : X -> foo X Y
| foo2 : Y -> foo X Y
| foo3 : foo X Y -> foo X Y.
Fill in the blanks to complete the induction principle that will be
generated by Coq.
foo_ind
: forall (X Y : Set) (P : foo X Y -> Prop),
(forall x : X, P (foo1 X Y x)) ->
(forall y : Y, P (foo2 X Y y)) ->
(forall f : foo X Y, P f -> P (foo3 X Y f)) ->
forall f : foo X Y, P f
*)
(** [] *)
(** **** Exercise: 2 stars, optional (bar_ind_principle) *)
(** Consider the following induction principle:
bar_ind
: forall P : bar -> Prop,
(forall n : nat, P (bar1 n)) ->
(forall b : bar, P b -> P (bar2 b)) ->
(forall (b : bool) (b0 : bar), P b0 -> P (bar3 b b0)) ->
forall b : bar, P b
Write out the corresponding inductive set definition.
Inductive bar : Set :=
| bar1 : nat -> bar
| bar2 : bar -> bar
| bar3 : bool -> bar -> bar.
*)
(** [] *)
(** **** Exercise: 2 stars, optional (no_longer_than_ind) *)
(** Given the following inductively defined proposition:
Inductive no_longer_than (X : Set) : (list X) -> nat -> Prop :=
| nlt_nil : forall n, no_longer_than X [] n
| nlt_cons : forall x l n, no_longer_than X l n ->
no_longer_than X (x::l) (S n)
| nlt_succ : forall l n, no_longer_than X l n ->
no_longer_than X l (S n).
write the induction principle generated by Coq.
no_longer_than_ind
: forall (X : Set) (P : list X -> nat -> Prop),
(forall n : nat, P [] n) ->
(forall (x : X) (l : list X) (n : nat),
no_longer_than X l n -> P l n ->
P (x :: l) (S n) ->
(forall (l : list X) (n : nat),
no_longer_than X l n -> P l n ->
P l (S n) ->
forall (l : list X) (n : nat), no_longer_than X l n ->
P l n
*)
(** [] *)
(* ##################################################### *)
(** ** Induction Principles for other Logical Propositions *)
(** Similarly, in [Logic] we have defined [eq] as: *)
(* Inductive eq (X:Type) : X -> X -> Prop :=
refl_equal : forall x, eq X x x. *)
(** In the Coq standard library, the definition of equality is
slightly different: *)
Inductive eq' (X:Type) (x:X) : X -> Prop :=
refl_equal' : eq' X x x.
(** The advantage of this definition is that the induction
principle that Coq derives for it is precisely the familiar
principle of _Leibniz equality_: what we mean when we say "[x] and
[y] are equal" is that every property on [P] that is true of [x]
is also true of [y]. (One philosophical quibble should be noted,
though: Here, the "Leibniz equality principle" is a _consequence_
of the way we've defined equality as an inductive type. Leibniz
viewed things exactly the other way around: for him, this
principle itself _is the definition_ of equality.) *)
Check eq'_ind.
(* ===>
forall (X : Type) (x : X) (P : X -> Prop),
P x -> forall y : X, x =' y -> P y
===> (i.e., after a little reorganization)
forall (X : Type) (x : X) forall y : X,
x =' y ->
forall P : X -> Prop, P x -> P y *)
(** The induction principles for conjunction and disjunction are a
good illustration of Coq's way of generating simplified induction
principles for [Inductive]ly defined propositions, which we
discussed above. You try first: *)
(** **** Exercise: 1 star, optional (and_ind_principle) *)
(** See if you can predict the induction principle for conjunction. *)
(* forall (P Q R : Prop) (P -> Q -> R) -> P /\ Q -> R *)
(* Check and_ind. *)
(** [] *)
(** **** Exercise: 1 star, optional (or_ind_principle) *)
(** See if you can predict the induction principle for disjunction. *)
(* forall (P Q R : Prop) (P -> R) -> (Q -> R) -> P \/ Q -> R *)
(* Check or_ind. *)
(** [] *)
Check and_ind.
(** From the inductive definition of the proposition [and P Q]
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
we might expect Coq to generate this induction principle
and_ind_max :
forall (P Q : Prop) (P0 : P /\ Q -> Prop),
(forall (a : P) (b : Q), P0 (conj P Q a b)) ->
forall a : P /\ Q, P0 a
but actually it generates this simpler and more useful one:
and_ind :
forall P Q P0 : Prop,
(P -> Q -> P0) ->
P /\ Q -> P0
In the same way, when given the inductive definition of [or P Q]
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
instead of the "maximal induction principle"
or_ind_max :
forall (P Q : Prop) (P0 : P \/ Q -> Prop),
(forall a : P, P0 (or_introl P Q a)) ->
(forall b : Q, P0 (or_intror P Q b)) ->
forall o : P \/ Q, P0 o
what Coq actually generates is this:
or_ind :
forall P Q P0 : Prop,
(P -> P0) ->
(Q -> P0) ->
P \/ Q -> P0
]]
*)
(** **** Exercise: 1 star, optional (False_ind_principle) *)
(** Can you predict the induction principle for falsehood? *)
(* forall P : Prop, False -> P *)
(* Check False_ind. *)
(** [] *)
(** Here's the induction principle that Coq generates for existentials: *)
Check ex_ind.
(* ===> forall (X:Type) (P: X->Prop) (Q: Prop),
(forall witness:X, P witness -> Q) ->
ex X P ->
Q *)
(** This induction principle can be understood as follows: If we have
a function [f] that can construct evidence for [Q] given _any_
witness of type [X] together with evidence that this witness has
property [P], then from a proof of [ex X P] we can extract the
witness and evidence that must have been supplied to the
constructor, give these to [f], and thus obtain a proof of [Q]. *)
(* ######################################################### *)
(** ** Explicit Proof Objects for Induction *)
(** Although tactic-based proofs are normally much easier to
work with, the ability to write a proof term directly is sometimes
very handy, particularly when we want Coq to do something slightly
non-standard. *)
(** Recall the induction principle on naturals that Coq generates for
us automatically from the Inductive declation for [nat]. *)
Check nat_ind.
(* ===>
nat_ind : forall P : nat -> Prop,
P 0 ->
(forall n : nat, P n -> P (S n)) ->
forall n : nat, P n *)
(** There's nothing magic about this induction lemma: it's just
another Coq lemma that requires a proof. Coq generates the proof
automatically too... *)
Print nat_ind.
Print nat_rect.
(* ===> (after some manual inlining and tidying)
nat_ind =
fun (P : nat -> Prop)
(f : P 0)
(f0 : forall n : nat, P n -> P (S n)) =>
fix F (n : nat) : P n :=
match n with
| 0 => f
| S n0 => f0 n0 (F n0)
end.
*)
(** We can read this as follows:
Suppose we have evidence [f] that [P] holds on 0, and
evidence [f0] that [forall n:nat, P n -> P (S n)].
Then we can prove that [P] holds of an arbitrary nat [n] via
a recursive function [F] (here defined using the expression
form [Fix] rather than by a top-level [Fixpoint]
declaration). [F] pattern matches on [n]:
- If it finds 0, [F] uses [f] to show that [P n] holds.
- If it finds [S n0], [F] applies itself recursively on [n0]
to obtain evidence that [P n0] holds; then it applies [f0]
on that evidence to show that [P (S n)] holds.
[F] is just an ordinary recursive function that happens to
operate on evidence in [Prop] rather than on terms in [Set].
*)
(** We can adapt this approach to proving [nat_ind] to help prove
_non-standard_ induction principles too. Recall our desire to
prove that
[forall n : nat, even n -> ev n].
Attempts to do this by standard induction on [n] fail, because the
induction principle only lets us proceed when we can prove that
[even n -> even (S n)] -- which is of course never provable. What
we did in [Logic] was a bit of a hack:
[Theorem even__ev : forall n : nat,
(even n -> ev n) /\ (even (S n) -> ev (S n))].
We can make a much better proof by defining and proving a
non-standard induction principle that goes "by twos":
*)
Definition nat_ind2 :
forall (P : nat -> Prop),
P 0 ->
P 1 ->
(forall n : nat, P n -> P (S(S n))) ->
forall n : nat , P n :=
fun P => fun P0 => fun P1 => fun PSS =>
fix f (n:nat) := match n with
0 => P0
| 1 => P1
| S (S n') => PSS n' (f n')
end.
(** Once you get the hang of it, it is entirely straightforward to
give an explicit proof term for induction principles like this.
Proving this as a lemma using tactics is much less intuitive (try
it!).
The [induction ... using] tactic variant gives a convenient way to
specify a non-standard induction principle like this. *)
Lemma even__ev' : forall n, even n -> ev n.
Proof.
intros.
induction n as [ | |n'] using nat_ind2.
Case "even 0".
apply ev_0.
Case "even 1".
inversion H.
Case "even (S(S n'))".
apply ev_SS.
apply IHn'. unfold even. unfold even in H. simpl in H. apply H.
Qed.
(* ######################################################### *)
(** ** The Coq Trusted Computing Base *)
(** One issue that arises with any automated proof assistant is "why
trust it?": what if there is a bug in the implementation that
renders all its reasoning suspect?
While it is impossible to allay such concerns completely, the fact
that Coq is based on the Curry-Howard correspondence gives it a
strong foundation. Because propositions are just types and proofs
are just terms, checking that an alleged proof of a proposition is
valid just amounts to _type-checking_ the term. Type checkers are
relatively small and straightforward programs, so the "trusted
computing base" for Coq -- the part of the code that we have to
believe is operating correctly -- is small too.
What must a typechecker do? Its primary job is to make sure that
in each function application the expected and actual argument
types match, that the arms of a [match] expression are constructor
patterns belonging to the inductive type being matched over and
all arms of the [match] return the same type, and so on.
There are a few additional wrinkles:
- Since Coq types can themselves be expressions, the checker must
normalize these (by using the computation rules) before
comparing them.
- The checker must make sure that [match] expressions are
_exhaustive_. That is, there must be an arm for every possible
constructor. To see why, consider the following alleged proof
object:
Definition or_bogus : forall P Q, P \/ Q -> P :=
fun (P Q : Prop) (A : P \/ Q) =>
match A with
| or_introl H => H
end.
All the types here match correctly, but the [match] only
considers one of the possible constructors for [or]. Coq's
exhaustiveness check will reject this definition.
- The checker must make sure that each [fix] expression
terminates. It does this using a syntactic check to make sure
that each recursive call is on a subexpression of the original
argument. To see why this is essential, consider this alleged
proof:
Definition nat_false : forall (n:nat), False :=
fix f (n:nat) : False := f n.
Again, this is perfectly well-typed, but (fortunately) Coq will
reject it. *)
(** Note that the soundness of Coq depends only on the correctness of
this typechecking engine, not on the tactic machinery. If there
is a bug in a tactic implementation (and this certainly does
happen!), that tactic might construct an invalid proof term. But
when you type [Qed], Coq checks the term for validity from
scratch. Only lemmas whose proofs pass the type-checker can be
used in further proof developments. *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: P.20131013
// \ \ Application: netgen
// / / Filename: mul_int20_int20_int40.v
// /___/ /\ Timestamp: Thu Oct 1 16:05:24 2015
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int20_int20_int40.ngc /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int20_int20_int40.v
// Device : 7z020clg484-1
// Input file : /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int20_int20_int40.ngc
// Output file : /home/jhegarty/mult/ipcore_dir/tmp/_cg/mul_int20_int20_int40.v
// # of Modules : 1
// Design Name : mul_int20_int20_int40
// Xilinx : /opt/Xilinx/14.7/ISE_DS/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
module mul_int20_int20_int40 (
CLK, ce, inp, out
);
parameter INSTANCE_NAME="INST";
input wire CLK;
input wire ce;
input [39:0] inp;
output [39:0] out;
wire [19:0] a;
wire [19:0] b;
wire [39:0] p;
assign a = inp[19:0];
assign b = inp[39:20];
assign out = p;
wire clk;
assign clk = CLK;
// input [19 : 0] a;
// input [19 : 0] b;
// output [39 : 0] p;
wire \blk00000001/sig000007fc ;
wire \blk00000001/sig000007fb ;
wire \blk00000001/sig000007fa ;
wire \blk00000001/sig000007f9 ;
wire \blk00000001/sig000007f8 ;
wire \blk00000001/sig000007f7 ;
wire \blk00000001/sig000007f6 ;
wire \blk00000001/sig000007f5 ;
wire \blk00000001/sig000007f4 ;
wire \blk00000001/sig000007f3 ;
wire \blk00000001/sig000007f2 ;
wire \blk00000001/sig000007f1 ;
wire \blk00000001/sig000007f0 ;
wire \blk00000001/sig000007ef ;
wire \blk00000001/sig000007ee ;
wire \blk00000001/sig000007ed ;
wire \blk00000001/sig000007ec ;
wire \blk00000001/sig000007eb ;
wire \blk00000001/sig000007ea ;
wire \blk00000001/sig000007e9 ;
wire \blk00000001/sig000007e8 ;
wire \blk00000001/sig000007e7 ;
wire \blk00000001/sig000007e6 ;
wire \blk00000001/sig000007e5 ;
wire \blk00000001/sig000007e4 ;
wire \blk00000001/sig000007e3 ;
wire \blk00000001/sig000007e2 ;
wire \blk00000001/sig000007e1 ;
wire \blk00000001/sig000007e0 ;
wire \blk00000001/sig000007df ;
wire \blk00000001/sig000007de ;
wire \blk00000001/sig000007dd ;
wire \blk00000001/sig000007dc ;
wire \blk00000001/sig000007db ;
wire \blk00000001/sig000007da ;
wire \blk00000001/sig000007d9 ;
wire \blk00000001/sig000007d8 ;
wire \blk00000001/sig000007d7 ;
wire \blk00000001/sig000007d6 ;
wire \blk00000001/sig000007d5 ;
wire \blk00000001/sig000007d4 ;
wire \blk00000001/sig000007d3 ;
wire \blk00000001/sig000007d2 ;
wire \blk00000001/sig000007d1 ;
wire \blk00000001/sig000007d0 ;
wire \blk00000001/sig000007cf ;
wire \blk00000001/sig000007ce ;
wire \blk00000001/sig000007cd ;
wire \blk00000001/sig000007cc ;
wire \blk00000001/sig000007cb ;
wire \blk00000001/sig000007ca ;
wire \blk00000001/sig000007c9 ;
wire \blk00000001/sig000007c8 ;
wire \blk00000001/sig000007c7 ;
wire \blk00000001/sig000007c6 ;
wire \blk00000001/sig000007c5 ;
wire \blk00000001/sig000007c4 ;
wire \blk00000001/sig000007c3 ;
wire \blk00000001/sig000007c2 ;
wire \blk00000001/sig000007c1 ;
wire \blk00000001/sig000007c0 ;
wire \blk00000001/sig000007bf ;
wire \blk00000001/sig000007be ;
wire \blk00000001/sig000007bd ;
wire \blk00000001/sig000007bc ;
wire \blk00000001/sig000007bb ;
wire \blk00000001/sig000007ba ;
wire \blk00000001/sig000007b9 ;
wire \blk00000001/sig000007b8 ;
wire \blk00000001/sig000007b7 ;
wire \blk00000001/sig000007b6 ;
wire \blk00000001/sig000007b5 ;
wire \blk00000001/sig000007b4 ;
wire \blk00000001/sig000007b3 ;
wire \blk00000001/sig000007b2 ;
wire \blk00000001/sig000007b1 ;
wire \blk00000001/sig000007b0 ;
wire \blk00000001/sig000007af ;
wire \blk00000001/sig000007ae ;
wire \blk00000001/sig000007ad ;
wire \blk00000001/sig000007ac ;
wire \blk00000001/sig000007ab ;
wire \blk00000001/sig000007aa ;
wire \blk00000001/sig000007a9 ;
wire \blk00000001/sig000007a8 ;
wire \blk00000001/sig000007a7 ;
wire \blk00000001/sig000007a6 ;
wire \blk00000001/sig000007a5 ;
wire \blk00000001/sig000007a4 ;
wire \blk00000001/sig000007a3 ;
wire \blk00000001/sig000007a2 ;
wire \blk00000001/sig000007a1 ;
wire \blk00000001/sig000007a0 ;
wire \blk00000001/sig0000079f ;
wire \blk00000001/sig0000079e ;
wire \blk00000001/sig0000079d ;
wire \blk00000001/sig0000079c ;
wire \blk00000001/sig0000079b ;
wire \blk00000001/sig0000079a ;
wire \blk00000001/sig00000799 ;
wire \blk00000001/sig00000798 ;
wire \blk00000001/sig00000797 ;
wire \blk00000001/sig00000796 ;
wire \blk00000001/sig00000795 ;
wire \blk00000001/sig00000794 ;
wire \blk00000001/sig00000793 ;
wire \blk00000001/sig00000792 ;
wire \blk00000001/sig00000791 ;
wire \blk00000001/sig00000790 ;
wire \blk00000001/sig0000078f ;
wire \blk00000001/sig0000078e ;
wire \blk00000001/sig0000078d ;
wire \blk00000001/sig0000078c ;
wire \blk00000001/sig0000078b ;
wire \blk00000001/sig0000078a ;
wire \blk00000001/sig00000789 ;
wire \blk00000001/sig00000788 ;
wire \blk00000001/sig00000787 ;
wire \blk00000001/sig00000786 ;
wire \blk00000001/sig00000785 ;
wire \blk00000001/sig00000784 ;
wire \blk00000001/sig00000783 ;
wire \blk00000001/sig00000782 ;
wire \blk00000001/sig00000781 ;
wire \blk00000001/sig00000780 ;
wire \blk00000001/sig0000077f ;
wire \blk00000001/sig0000077e ;
wire \blk00000001/sig0000077d ;
wire \blk00000001/sig0000077c ;
wire \blk00000001/sig0000077b ;
wire \blk00000001/sig0000077a ;
wire \blk00000001/sig00000779 ;
wire \blk00000001/sig00000778 ;
wire \blk00000001/sig00000777 ;
wire \blk00000001/sig00000776 ;
wire \blk00000001/sig00000775 ;
wire \blk00000001/sig00000774 ;
wire \blk00000001/sig00000773 ;
wire \blk00000001/sig00000772 ;
wire \blk00000001/sig00000771 ;
wire \blk00000001/sig00000770 ;
wire \blk00000001/sig0000076f ;
wire \blk00000001/sig0000076e ;
wire \blk00000001/sig0000076d ;
wire \blk00000001/sig0000076c ;
wire \blk00000001/sig0000076b ;
wire \blk00000001/sig0000076a ;
wire \blk00000001/sig00000769 ;
wire \blk00000001/sig00000768 ;
wire \blk00000001/sig00000767 ;
wire \blk00000001/sig00000766 ;
wire \blk00000001/sig00000765 ;
wire \blk00000001/sig00000764 ;
wire \blk00000001/sig00000763 ;
wire \blk00000001/sig00000762 ;
wire \blk00000001/sig00000761 ;
wire \blk00000001/sig00000760 ;
wire \blk00000001/sig0000075f ;
wire \blk00000001/sig0000075e ;
wire \blk00000001/sig0000075d ;
wire \blk00000001/sig0000075c ;
wire \blk00000001/sig0000075b ;
wire \blk00000001/sig0000075a ;
wire \blk00000001/sig00000759 ;
wire \blk00000001/sig00000758 ;
wire \blk00000001/sig00000757 ;
wire \blk00000001/sig00000756 ;
wire \blk00000001/sig00000755 ;
wire \blk00000001/sig00000754 ;
wire \blk00000001/sig00000753 ;
wire \blk00000001/sig00000752 ;
wire \blk00000001/sig00000751 ;
wire \blk00000001/sig00000750 ;
wire \blk00000001/sig0000074f ;
wire \blk00000001/sig0000074e ;
wire \blk00000001/sig0000074d ;
wire \blk00000001/sig0000074c ;
wire \blk00000001/sig0000074b ;
wire \blk00000001/sig0000074a ;
wire \blk00000001/sig00000749 ;
wire \blk00000001/sig00000748 ;
wire \blk00000001/sig00000747 ;
wire \blk00000001/sig00000746 ;
wire \blk00000001/sig00000745 ;
wire \blk00000001/sig00000744 ;
wire \blk00000001/sig00000743 ;
wire \blk00000001/sig00000742 ;
wire \blk00000001/sig00000741 ;
wire \blk00000001/sig00000740 ;
wire \blk00000001/sig0000073f ;
wire \blk00000001/sig0000073e ;
wire \blk00000001/sig0000073d ;
wire \blk00000001/sig0000073c ;
wire \blk00000001/sig0000073b ;
wire \blk00000001/sig0000073a ;
wire \blk00000001/sig00000739 ;
wire \blk00000001/sig00000738 ;
wire \blk00000001/sig00000737 ;
wire \blk00000001/sig00000736 ;
wire \blk00000001/sig00000735 ;
wire \blk00000001/sig00000734 ;
wire \blk00000001/sig00000733 ;
wire \blk00000001/sig00000732 ;
wire \blk00000001/sig00000731 ;
wire \blk00000001/sig00000730 ;
wire \blk00000001/sig0000072f ;
wire \blk00000001/sig0000072e ;
wire \blk00000001/sig0000072d ;
wire \blk00000001/sig0000072c ;
wire \blk00000001/sig0000072b ;
wire \blk00000001/sig0000072a ;
wire \blk00000001/sig00000729 ;
wire \blk00000001/sig00000728 ;
wire \blk00000001/sig00000727 ;
wire \blk00000001/sig00000726 ;
wire \blk00000001/sig00000725 ;
wire \blk00000001/sig00000724 ;
wire \blk00000001/sig00000723 ;
wire \blk00000001/sig00000722 ;
wire \blk00000001/sig00000721 ;
wire \blk00000001/sig00000720 ;
wire \blk00000001/sig0000071f ;
wire \blk00000001/sig0000071e ;
wire \blk00000001/sig0000071d ;
wire \blk00000001/sig0000071c ;
wire \blk00000001/sig0000071b ;
wire \blk00000001/sig0000071a ;
wire \blk00000001/sig00000719 ;
wire \blk00000001/sig00000718 ;
wire \blk00000001/sig00000717 ;
wire \blk00000001/sig00000716 ;
wire \blk00000001/sig00000715 ;
wire \blk00000001/sig00000714 ;
wire \blk00000001/sig00000713 ;
wire \blk00000001/sig00000712 ;
wire \blk00000001/sig00000711 ;
wire \blk00000001/sig00000710 ;
wire \blk00000001/sig0000070f ;
wire \blk00000001/sig0000070e ;
wire \blk00000001/sig0000070d ;
wire \blk00000001/sig0000070c ;
wire \blk00000001/sig0000070b ;
wire \blk00000001/sig0000070a ;
wire \blk00000001/sig00000709 ;
wire \blk00000001/sig00000708 ;
wire \blk00000001/sig00000707 ;
wire \blk00000001/sig00000706 ;
wire \blk00000001/sig00000705 ;
wire \blk00000001/sig00000704 ;
wire \blk00000001/sig00000703 ;
wire \blk00000001/sig00000702 ;
wire \blk00000001/sig00000701 ;
wire \blk00000001/sig00000700 ;
wire \blk00000001/sig000006ff ;
wire \blk00000001/sig000006fe ;
wire \blk00000001/sig000006fd ;
wire \blk00000001/sig000006fc ;
wire \blk00000001/sig000006fb ;
wire \blk00000001/sig000006fa ;
wire \blk00000001/sig000006f9 ;
wire \blk00000001/sig000006f8 ;
wire \blk00000001/sig000006f7 ;
wire \blk00000001/sig000006f6 ;
wire \blk00000001/sig000006f5 ;
wire \blk00000001/sig000006f4 ;
wire \blk00000001/sig000006f3 ;
wire \blk00000001/sig000006f2 ;
wire \blk00000001/sig000006f1 ;
wire \blk00000001/sig000006f0 ;
wire \blk00000001/sig000006ef ;
wire \blk00000001/sig000006ee ;
wire \blk00000001/sig000006ed ;
wire \blk00000001/sig000006ec ;
wire \blk00000001/sig000006eb ;
wire \blk00000001/sig000006ea ;
wire \blk00000001/sig000006e9 ;
wire \blk00000001/sig000006e8 ;
wire \blk00000001/sig000006e7 ;
wire \blk00000001/sig000006e6 ;
wire \blk00000001/sig000006e5 ;
wire \blk00000001/sig000006e4 ;
wire \blk00000001/sig000006e3 ;
wire \blk00000001/sig000006e2 ;
wire \blk00000001/sig000006e1 ;
wire \blk00000001/sig000006e0 ;
wire \blk00000001/sig000006df ;
wire \blk00000001/sig000006de ;
wire \blk00000001/sig000006dd ;
wire \blk00000001/sig000006dc ;
wire \blk00000001/sig000006db ;
wire \blk00000001/sig000006da ;
wire \blk00000001/sig000006d9 ;
wire \blk00000001/sig000006d8 ;
wire \blk00000001/sig000006d7 ;
wire \blk00000001/sig000006d6 ;
wire \blk00000001/sig000006d5 ;
wire \blk00000001/sig000006d4 ;
wire \blk00000001/sig000006d3 ;
wire \blk00000001/sig000006d2 ;
wire \blk00000001/sig000006d1 ;
wire \blk00000001/sig000006d0 ;
wire \blk00000001/sig000006cf ;
wire \blk00000001/sig000006ce ;
wire \blk00000001/sig000006cd ;
wire \blk00000001/sig000006cc ;
wire \blk00000001/sig000006cb ;
wire \blk00000001/sig000006ca ;
wire \blk00000001/sig000006c9 ;
wire \blk00000001/sig000006c8 ;
wire \blk00000001/sig000006c7 ;
wire \blk00000001/sig000006c6 ;
wire \blk00000001/sig000006c5 ;
wire \blk00000001/sig000006c4 ;
wire \blk00000001/sig000006c3 ;
wire \blk00000001/sig000006c2 ;
wire \blk00000001/sig000006c1 ;
wire \blk00000001/sig000006c0 ;
wire \blk00000001/sig000006bf ;
wire \blk00000001/sig000006be ;
wire \blk00000001/sig000006bd ;
wire \blk00000001/sig000006bc ;
wire \blk00000001/sig000006bb ;
wire \blk00000001/sig000006ba ;
wire \blk00000001/sig000006b9 ;
wire \blk00000001/sig000006b8 ;
wire \blk00000001/sig000006b7 ;
wire \blk00000001/sig000006b6 ;
wire \blk00000001/sig000006b5 ;
wire \blk00000001/sig000006b4 ;
wire \blk00000001/sig000006b3 ;
wire \blk00000001/sig000006b2 ;
wire \blk00000001/sig000006b1 ;
wire \blk00000001/sig000006b0 ;
wire \blk00000001/sig000006af ;
wire \blk00000001/sig000006ae ;
wire \blk00000001/sig000006ad ;
wire \blk00000001/sig000006ac ;
wire \blk00000001/sig000006ab ;
wire \blk00000001/sig000006aa ;
wire \blk00000001/sig000006a9 ;
wire \blk00000001/sig000006a8 ;
wire \blk00000001/sig000006a7 ;
wire \blk00000001/sig000006a6 ;
wire \blk00000001/sig000006a5 ;
wire \blk00000001/sig000006a4 ;
wire \blk00000001/sig000006a3 ;
wire \blk00000001/sig000006a2 ;
wire \blk00000001/sig000006a1 ;
wire \blk00000001/sig000006a0 ;
wire \blk00000001/sig0000069f ;
wire \blk00000001/sig0000069e ;
wire \blk00000001/sig0000069d ;
wire \blk00000001/sig0000069c ;
wire \blk00000001/sig0000069b ;
wire \blk00000001/sig0000069a ;
wire \blk00000001/sig00000699 ;
wire \blk00000001/sig00000698 ;
wire \blk00000001/sig00000697 ;
wire \blk00000001/sig00000696 ;
wire \blk00000001/sig00000695 ;
wire \blk00000001/sig00000694 ;
wire \blk00000001/sig00000693 ;
wire \blk00000001/sig00000692 ;
wire \blk00000001/sig00000691 ;
wire \blk00000001/sig00000690 ;
wire \blk00000001/sig0000068f ;
wire \blk00000001/sig0000068e ;
wire \blk00000001/sig0000068d ;
wire \blk00000001/sig0000068c ;
wire \blk00000001/sig0000068b ;
wire \blk00000001/sig0000068a ;
wire \blk00000001/sig00000689 ;
wire \blk00000001/sig00000688 ;
wire \blk00000001/sig00000687 ;
wire \blk00000001/sig00000686 ;
wire \blk00000001/sig00000685 ;
wire \blk00000001/sig00000684 ;
wire \blk00000001/sig00000683 ;
wire \blk00000001/sig00000682 ;
wire \blk00000001/sig00000681 ;
wire \blk00000001/sig00000680 ;
wire \blk00000001/sig0000067f ;
wire \blk00000001/sig0000067e ;
wire \blk00000001/sig0000067d ;
wire \blk00000001/sig0000067c ;
wire \blk00000001/sig0000067b ;
wire \blk00000001/sig0000067a ;
wire \blk00000001/sig00000679 ;
wire \blk00000001/sig00000678 ;
wire \blk00000001/sig00000677 ;
wire \blk00000001/sig00000676 ;
wire \blk00000001/sig00000675 ;
wire \blk00000001/sig00000674 ;
wire \blk00000001/sig00000673 ;
wire \blk00000001/sig00000672 ;
wire \blk00000001/sig00000671 ;
wire \blk00000001/sig00000670 ;
wire \blk00000001/sig0000066f ;
wire \blk00000001/sig0000066e ;
wire \blk00000001/sig0000066d ;
wire \blk00000001/sig0000066c ;
wire \blk00000001/sig0000066b ;
wire \blk00000001/sig0000066a ;
wire \blk00000001/sig00000669 ;
wire \blk00000001/sig00000668 ;
wire \blk00000001/sig00000667 ;
wire \blk00000001/sig00000666 ;
wire \blk00000001/sig00000665 ;
wire \blk00000001/sig00000664 ;
wire \blk00000001/sig00000663 ;
wire \blk00000001/sig00000662 ;
wire \blk00000001/sig00000661 ;
wire \blk00000001/sig00000660 ;
wire \blk00000001/sig0000065f ;
wire \blk00000001/sig0000065e ;
wire \blk00000001/sig0000065d ;
wire \blk00000001/sig0000065c ;
wire \blk00000001/sig0000065b ;
wire \blk00000001/sig0000065a ;
wire \blk00000001/sig00000659 ;
wire \blk00000001/sig00000658 ;
wire \blk00000001/sig00000657 ;
wire \blk00000001/sig00000656 ;
wire \blk00000001/sig00000655 ;
wire \blk00000001/sig00000654 ;
wire \blk00000001/sig00000653 ;
wire \blk00000001/sig00000652 ;
wire \blk00000001/sig00000651 ;
wire \blk00000001/sig00000650 ;
wire \blk00000001/sig0000064f ;
wire \blk00000001/sig0000064e ;
wire \blk00000001/sig0000064d ;
wire \blk00000001/sig0000064c ;
wire \blk00000001/sig0000064b ;
wire \blk00000001/sig0000064a ;
wire \blk00000001/sig00000649 ;
wire \blk00000001/sig00000648 ;
wire \blk00000001/sig00000647 ;
wire \blk00000001/sig00000646 ;
wire \blk00000001/sig00000645 ;
wire \blk00000001/sig00000644 ;
wire \blk00000001/sig00000643 ;
wire \blk00000001/sig00000642 ;
wire \blk00000001/sig00000641 ;
wire \blk00000001/sig00000640 ;
wire \blk00000001/sig0000063f ;
wire \blk00000001/sig0000063e ;
wire \blk00000001/sig0000063d ;
wire \blk00000001/sig0000063c ;
wire \blk00000001/sig0000063b ;
wire \blk00000001/sig0000063a ;
wire \blk00000001/sig00000639 ;
wire \blk00000001/sig00000638 ;
wire \blk00000001/sig00000637 ;
wire \blk00000001/sig00000636 ;
wire \blk00000001/sig00000635 ;
wire \blk00000001/sig00000634 ;
wire \blk00000001/sig00000633 ;
wire \blk00000001/sig00000632 ;
wire \blk00000001/sig00000631 ;
wire \blk00000001/sig00000630 ;
wire \blk00000001/sig0000062f ;
wire \blk00000001/sig0000062e ;
wire \blk00000001/sig0000062d ;
wire \blk00000001/sig0000062c ;
wire \blk00000001/sig0000062b ;
wire \blk00000001/sig0000062a ;
wire \blk00000001/sig00000629 ;
wire \blk00000001/sig00000628 ;
wire \blk00000001/sig00000627 ;
wire \blk00000001/sig00000626 ;
wire \blk00000001/sig00000625 ;
wire \blk00000001/sig00000624 ;
wire \blk00000001/sig00000623 ;
wire \blk00000001/sig00000622 ;
wire \blk00000001/sig00000621 ;
wire \blk00000001/sig00000620 ;
wire \blk00000001/sig0000061f ;
wire \blk00000001/sig0000061e ;
wire \blk00000001/sig0000061d ;
wire \blk00000001/sig0000061c ;
wire \blk00000001/sig0000061b ;
wire \blk00000001/sig0000061a ;
wire \blk00000001/sig00000619 ;
wire \blk00000001/sig00000618 ;
wire \blk00000001/sig00000617 ;
wire \blk00000001/sig00000616 ;
wire \blk00000001/sig00000615 ;
wire \blk00000001/sig00000614 ;
wire \blk00000001/sig00000613 ;
wire \blk00000001/sig00000612 ;
wire \blk00000001/sig00000611 ;
wire \blk00000001/sig00000610 ;
wire \blk00000001/sig0000060f ;
wire \blk00000001/sig0000060e ;
wire \blk00000001/sig0000060d ;
wire \blk00000001/sig0000060c ;
wire \blk00000001/sig0000060b ;
wire \blk00000001/sig0000060a ;
wire \blk00000001/sig00000609 ;
wire \blk00000001/sig00000608 ;
wire \blk00000001/sig00000607 ;
wire \blk00000001/sig00000606 ;
wire \blk00000001/sig00000605 ;
wire \blk00000001/sig00000604 ;
wire \blk00000001/sig00000603 ;
wire \blk00000001/sig00000602 ;
wire \blk00000001/sig00000601 ;
wire \blk00000001/sig00000600 ;
wire \blk00000001/sig000005ff ;
wire \blk00000001/sig000005fe ;
wire \blk00000001/sig000005fd ;
wire \blk00000001/sig000005fc ;
wire \blk00000001/sig000005fb ;
wire \blk00000001/sig000005fa ;
wire \blk00000001/sig000005f9 ;
wire \blk00000001/sig000005f8 ;
wire \blk00000001/sig000005f7 ;
wire \blk00000001/sig000005f6 ;
wire \blk00000001/sig000005f5 ;
wire \blk00000001/sig000005f4 ;
wire \blk00000001/sig000005f3 ;
wire \blk00000001/sig000005f2 ;
wire \blk00000001/sig000005f1 ;
wire \blk00000001/sig000005f0 ;
wire \blk00000001/sig000005ef ;
wire \blk00000001/sig000005ee ;
wire \blk00000001/sig000005ed ;
wire \blk00000001/sig000005ec ;
wire \blk00000001/sig000005eb ;
wire \blk00000001/sig000005ea ;
wire \blk00000001/sig000005e9 ;
wire \blk00000001/sig000005e8 ;
wire \blk00000001/sig000005e7 ;
wire \blk00000001/sig000005e6 ;
wire \blk00000001/sig000005e5 ;
wire \blk00000001/sig000005e4 ;
wire \blk00000001/sig000005e3 ;
wire \blk00000001/sig000005e2 ;
wire \blk00000001/sig000005e1 ;
wire \blk00000001/sig000005e0 ;
wire \blk00000001/sig000005df ;
wire \blk00000001/sig000005de ;
wire \blk00000001/sig000005dd ;
wire \blk00000001/sig000005dc ;
wire \blk00000001/sig000005db ;
wire \blk00000001/sig000005da ;
wire \blk00000001/sig000005d9 ;
wire \blk00000001/sig000005d8 ;
wire \blk00000001/sig000005d7 ;
wire \blk00000001/sig000005d6 ;
wire \blk00000001/sig000005d5 ;
wire \blk00000001/sig000005d4 ;
wire \blk00000001/sig000005d3 ;
wire \blk00000001/sig000005d2 ;
wire \blk00000001/sig000005d1 ;
wire \blk00000001/sig000005d0 ;
wire \blk00000001/sig000005cf ;
wire \blk00000001/sig000005ce ;
wire \blk00000001/sig000005cd ;
wire \blk00000001/sig000005cc ;
wire \blk00000001/sig000005cb ;
wire \blk00000001/sig000005ca ;
wire \blk00000001/sig000005c9 ;
wire \blk00000001/sig000005c8 ;
wire \blk00000001/sig000005c7 ;
wire \blk00000001/sig000005c6 ;
wire \blk00000001/sig000005c5 ;
wire \blk00000001/sig000005c4 ;
wire \blk00000001/sig000005c3 ;
wire \blk00000001/sig000005c2 ;
wire \blk00000001/sig000005c1 ;
wire \blk00000001/sig000005c0 ;
wire \blk00000001/sig000005bf ;
wire \blk00000001/sig000005be ;
wire \blk00000001/sig000005bd ;
wire \blk00000001/sig000005bc ;
wire \blk00000001/sig000005bb ;
wire \blk00000001/sig000005ba ;
wire \blk00000001/sig000005b9 ;
wire \blk00000001/sig000005b8 ;
wire \blk00000001/sig000005b7 ;
wire \blk00000001/sig000005b6 ;
wire \blk00000001/sig000005b5 ;
wire \blk00000001/sig000005b4 ;
wire \blk00000001/sig000005b3 ;
wire \blk00000001/sig000005b2 ;
wire \blk00000001/sig000005b1 ;
wire \blk00000001/sig000005b0 ;
wire \blk00000001/sig000005af ;
wire \blk00000001/sig000005ae ;
wire \blk00000001/sig000005ad ;
wire \blk00000001/sig000005ac ;
wire \blk00000001/sig000005ab ;
wire \blk00000001/sig000005aa ;
wire \blk00000001/sig000005a9 ;
wire \blk00000001/sig000005a8 ;
wire \blk00000001/sig000005a7 ;
wire \blk00000001/sig000005a6 ;
wire \blk00000001/sig000005a5 ;
wire \blk00000001/sig000005a4 ;
wire \blk00000001/sig000005a3 ;
wire \blk00000001/sig000005a2 ;
wire \blk00000001/sig000005a1 ;
wire \blk00000001/sig000005a0 ;
wire \blk00000001/sig0000059f ;
wire \blk00000001/sig0000059e ;
wire \blk00000001/sig0000059d ;
wire \blk00000001/sig0000059c ;
wire \blk00000001/sig0000059b ;
wire \blk00000001/sig0000059a ;
wire \blk00000001/sig00000599 ;
wire \blk00000001/sig00000598 ;
wire \blk00000001/sig00000597 ;
wire \blk00000001/sig00000596 ;
wire \blk00000001/sig00000595 ;
wire \blk00000001/sig00000594 ;
wire \blk00000001/sig00000593 ;
wire \blk00000001/sig00000592 ;
wire \blk00000001/sig00000591 ;
wire \blk00000001/sig00000590 ;
wire \blk00000001/sig0000058f ;
wire \blk00000001/sig0000058e ;
wire \blk00000001/sig0000058d ;
wire \blk00000001/sig0000058c ;
wire \blk00000001/sig0000058b ;
wire \blk00000001/sig0000058a ;
wire \blk00000001/sig00000589 ;
wire \blk00000001/sig00000588 ;
wire \blk00000001/sig00000587 ;
wire \blk00000001/sig00000586 ;
wire \blk00000001/sig00000585 ;
wire \blk00000001/sig00000584 ;
wire \blk00000001/sig00000583 ;
wire \blk00000001/sig00000582 ;
wire \blk00000001/sig00000581 ;
wire \blk00000001/sig00000580 ;
wire \blk00000001/sig0000057f ;
wire \blk00000001/sig0000057e ;
wire \blk00000001/sig0000057d ;
wire \blk00000001/sig0000057c ;
wire \blk00000001/sig0000057b ;
wire \blk00000001/sig0000057a ;
wire \blk00000001/sig00000579 ;
wire \blk00000001/sig00000578 ;
wire \blk00000001/sig00000577 ;
wire \blk00000001/sig00000576 ;
wire \blk00000001/sig00000575 ;
wire \blk00000001/sig00000574 ;
wire \blk00000001/sig00000573 ;
wire \blk00000001/sig00000572 ;
wire \blk00000001/sig00000571 ;
wire \blk00000001/sig00000570 ;
wire \blk00000001/sig0000056f ;
wire \blk00000001/sig0000056e ;
wire \blk00000001/sig0000056d ;
wire \blk00000001/sig0000056c ;
wire \blk00000001/sig0000056b ;
wire \blk00000001/sig0000056a ;
wire \blk00000001/sig00000569 ;
wire \blk00000001/sig00000568 ;
wire \blk00000001/sig00000567 ;
wire \blk00000001/sig00000566 ;
wire \blk00000001/sig00000565 ;
wire \blk00000001/sig00000564 ;
wire \blk00000001/sig00000563 ;
wire \blk00000001/sig00000562 ;
wire \blk00000001/sig00000561 ;
wire \blk00000001/sig00000560 ;
wire \blk00000001/sig0000055f ;
wire \blk00000001/sig0000055e ;
wire \blk00000001/sig0000055d ;
wire \blk00000001/sig0000055c ;
wire \blk00000001/sig0000055b ;
wire \blk00000001/sig0000055a ;
wire \blk00000001/sig00000559 ;
wire \blk00000001/sig00000558 ;
wire \blk00000001/sig00000557 ;
wire \blk00000001/sig00000556 ;
wire \blk00000001/sig00000555 ;
wire \blk00000001/sig00000554 ;
wire \blk00000001/sig00000553 ;
wire \blk00000001/sig00000552 ;
wire \blk00000001/sig00000551 ;
wire \blk00000001/sig00000550 ;
wire \blk00000001/sig0000054f ;
wire \blk00000001/sig0000054e ;
wire \blk00000001/sig0000054d ;
wire \blk00000001/sig0000054c ;
wire \blk00000001/sig0000054b ;
wire \blk00000001/sig0000054a ;
wire \blk00000001/sig00000549 ;
wire \blk00000001/sig00000548 ;
wire \blk00000001/sig00000547 ;
wire \blk00000001/sig00000546 ;
wire \blk00000001/sig00000545 ;
wire \blk00000001/sig00000544 ;
wire \blk00000001/sig00000543 ;
wire \blk00000001/sig00000542 ;
wire \blk00000001/sig00000541 ;
wire \blk00000001/sig00000540 ;
wire \blk00000001/sig0000053f ;
wire \blk00000001/sig0000053e ;
wire \blk00000001/sig0000053d ;
wire \blk00000001/sig0000053c ;
wire \blk00000001/sig0000053b ;
wire \blk00000001/sig0000053a ;
wire \blk00000001/sig00000539 ;
wire \blk00000001/sig00000538 ;
wire \blk00000001/sig00000537 ;
wire \blk00000001/sig00000536 ;
wire \blk00000001/sig00000535 ;
wire \blk00000001/sig00000534 ;
wire \blk00000001/sig00000533 ;
wire \blk00000001/sig00000532 ;
wire \blk00000001/sig00000531 ;
wire \blk00000001/sig00000530 ;
wire \blk00000001/sig0000052f ;
wire \blk00000001/sig0000052e ;
wire \blk00000001/sig0000052d ;
wire \blk00000001/sig0000052c ;
wire \blk00000001/sig0000052b ;
wire \blk00000001/sig0000052a ;
wire \blk00000001/sig00000529 ;
wire \blk00000001/sig00000528 ;
wire \blk00000001/sig00000527 ;
wire \blk00000001/sig00000526 ;
wire \blk00000001/sig00000525 ;
wire \blk00000001/sig00000524 ;
wire \blk00000001/sig00000523 ;
wire \blk00000001/sig00000522 ;
wire \blk00000001/sig00000521 ;
wire \blk00000001/sig00000520 ;
wire \blk00000001/sig0000051f ;
wire \blk00000001/sig0000051e ;
wire \blk00000001/sig0000051d ;
wire \blk00000001/sig0000051c ;
wire \blk00000001/sig0000051b ;
wire \blk00000001/sig0000051a ;
wire \blk00000001/sig00000519 ;
wire \blk00000001/sig00000518 ;
wire \blk00000001/sig00000517 ;
wire \blk00000001/sig00000516 ;
wire \blk00000001/sig00000515 ;
wire \blk00000001/sig00000514 ;
wire \blk00000001/sig00000513 ;
wire \blk00000001/sig00000512 ;
wire \blk00000001/sig00000511 ;
wire \blk00000001/sig00000510 ;
wire \blk00000001/sig0000050f ;
wire \blk00000001/sig0000050e ;
wire \blk00000001/sig0000050d ;
wire \blk00000001/sig0000050c ;
wire \blk00000001/sig0000050b ;
wire \blk00000001/sig0000050a ;
wire \blk00000001/sig00000509 ;
wire \blk00000001/sig00000508 ;
wire \blk00000001/sig00000507 ;
wire \blk00000001/sig00000506 ;
wire \blk00000001/sig00000505 ;
wire \blk00000001/sig00000504 ;
wire \blk00000001/sig00000503 ;
wire \blk00000001/sig00000502 ;
wire \blk00000001/sig00000501 ;
wire \blk00000001/sig00000500 ;
wire \blk00000001/sig000004ff ;
wire \blk00000001/sig000004fe ;
wire \blk00000001/sig000004fd ;
wire \blk00000001/sig000004fc ;
wire \blk00000001/sig000004fb ;
wire \blk00000001/sig000004fa ;
wire \blk00000001/sig000004f9 ;
wire \blk00000001/sig000004f8 ;
wire \blk00000001/sig000004f7 ;
wire \blk00000001/sig000004f6 ;
wire \blk00000001/sig000004f5 ;
wire \blk00000001/sig000004f4 ;
wire \blk00000001/sig000004f3 ;
wire \blk00000001/sig000004f2 ;
wire \blk00000001/sig000004f1 ;
wire \blk00000001/sig000004f0 ;
wire \blk00000001/sig000004ef ;
wire \blk00000001/sig000004ee ;
wire \blk00000001/sig000004ed ;
wire \blk00000001/sig000004ec ;
wire \blk00000001/sig000004eb ;
wire \blk00000001/sig000004ea ;
wire \blk00000001/sig000004e9 ;
wire \blk00000001/sig000004e8 ;
wire \blk00000001/sig000004e7 ;
wire \blk00000001/sig000004e6 ;
wire \blk00000001/sig000004e5 ;
wire \blk00000001/sig000004e4 ;
wire \blk00000001/sig000004e3 ;
wire \blk00000001/sig000004e2 ;
wire \blk00000001/sig000004e1 ;
wire \blk00000001/sig000004e0 ;
wire \blk00000001/sig000004df ;
wire \blk00000001/sig000004de ;
wire \blk00000001/sig000004dd ;
wire \blk00000001/sig000004dc ;
wire \blk00000001/sig000004db ;
wire \blk00000001/sig000004da ;
wire \blk00000001/sig000004d9 ;
wire \blk00000001/sig000004d8 ;
wire \blk00000001/sig000004d7 ;
wire \blk00000001/sig000004d6 ;
wire \blk00000001/sig000004d5 ;
wire \blk00000001/sig000004d4 ;
wire \blk00000001/sig000004d3 ;
wire \blk00000001/sig000004d2 ;
wire \blk00000001/sig000004d1 ;
wire \blk00000001/sig000004d0 ;
wire \blk00000001/sig000004cf ;
wire \blk00000001/sig000004ce ;
wire \blk00000001/sig000004cd ;
wire \blk00000001/sig000004cc ;
wire \blk00000001/sig000004cb ;
wire \blk00000001/sig000004ca ;
wire \blk00000001/sig000004c9 ;
wire \blk00000001/sig000004c8 ;
wire \blk00000001/sig000004c7 ;
wire \blk00000001/sig000004c6 ;
wire \blk00000001/sig000004c5 ;
wire \blk00000001/sig000004c4 ;
wire \blk00000001/sig000004c3 ;
wire \blk00000001/sig000004c2 ;
wire \blk00000001/sig000004c1 ;
wire \blk00000001/sig000004c0 ;
wire \blk00000001/sig000004bf ;
wire \blk00000001/sig000004be ;
wire \blk00000001/sig000004bd ;
wire \blk00000001/sig000004bc ;
wire \blk00000001/sig000004bb ;
wire \blk00000001/sig000004ba ;
wire \blk00000001/sig000004b9 ;
wire \blk00000001/sig000004b8 ;
wire \blk00000001/sig000004b7 ;
wire \blk00000001/sig000004b6 ;
wire \blk00000001/sig000004b5 ;
wire \blk00000001/sig000004b4 ;
wire \blk00000001/sig000004b3 ;
wire \blk00000001/sig000004b2 ;
wire \blk00000001/sig000004b1 ;
wire \blk00000001/sig000004b0 ;
wire \blk00000001/sig000004af ;
wire \blk00000001/sig000004ae ;
wire \blk00000001/sig000004ad ;
wire \blk00000001/sig000004ac ;
wire \blk00000001/sig000004ab ;
wire \blk00000001/sig000004aa ;
wire \blk00000001/sig000004a9 ;
wire \blk00000001/sig000004a8 ;
wire \blk00000001/sig000004a7 ;
wire \blk00000001/sig000004a6 ;
wire \blk00000001/sig000004a5 ;
wire \blk00000001/sig000004a4 ;
wire \blk00000001/sig000004a3 ;
wire \blk00000001/sig000004a2 ;
wire \blk00000001/sig000004a1 ;
wire \blk00000001/sig000004a0 ;
wire \blk00000001/sig0000049f ;
wire \blk00000001/sig0000049e ;
wire \blk00000001/sig0000049d ;
wire \blk00000001/sig0000049c ;
wire \blk00000001/sig0000049b ;
wire \blk00000001/sig0000049a ;
wire \blk00000001/sig00000499 ;
wire \blk00000001/sig00000498 ;
wire \blk00000001/sig00000497 ;
wire \blk00000001/sig00000496 ;
wire \blk00000001/sig00000495 ;
wire \blk00000001/sig00000494 ;
wire \blk00000001/sig00000493 ;
wire \blk00000001/sig00000492 ;
wire \blk00000001/sig00000491 ;
wire \blk00000001/sig00000490 ;
wire \blk00000001/sig0000048f ;
wire \blk00000001/sig0000048e ;
wire \blk00000001/sig0000048d ;
wire \blk00000001/sig0000048c ;
wire \blk00000001/sig0000048b ;
wire \blk00000001/sig0000048a ;
wire \blk00000001/sig00000489 ;
wire \blk00000001/sig00000488 ;
wire \blk00000001/sig00000487 ;
wire \blk00000001/sig00000486 ;
wire \blk00000001/sig00000485 ;
wire \blk00000001/sig00000484 ;
wire \blk00000001/sig00000483 ;
wire \blk00000001/sig00000482 ;
wire \blk00000001/sig00000481 ;
wire \blk00000001/sig00000480 ;
wire \blk00000001/sig0000047f ;
wire \blk00000001/sig0000047e ;
wire \blk00000001/sig0000047d ;
wire \blk00000001/sig0000047c ;
wire \blk00000001/sig0000047b ;
wire \blk00000001/sig0000047a ;
wire \blk00000001/sig00000479 ;
wire \blk00000001/sig00000478 ;
wire \blk00000001/sig00000477 ;
wire \blk00000001/sig00000476 ;
wire \blk00000001/sig00000475 ;
wire \blk00000001/sig00000474 ;
wire \blk00000001/sig00000473 ;
wire \blk00000001/sig00000472 ;
wire \blk00000001/sig00000471 ;
wire \blk00000001/sig00000470 ;
wire \blk00000001/sig0000046f ;
wire \blk00000001/sig0000046e ;
wire \blk00000001/sig0000046d ;
wire \blk00000001/sig0000046c ;
wire \blk00000001/sig0000046b ;
wire \blk00000001/sig0000046a ;
wire \blk00000001/sig00000469 ;
wire \blk00000001/sig00000468 ;
wire \blk00000001/sig00000467 ;
wire \blk00000001/sig00000466 ;
wire \blk00000001/sig00000465 ;
wire \blk00000001/sig00000464 ;
wire \blk00000001/sig00000463 ;
wire \blk00000001/sig00000462 ;
wire \blk00000001/sig00000461 ;
wire \blk00000001/sig00000460 ;
wire \blk00000001/sig0000045f ;
wire \blk00000001/sig0000045e ;
wire \blk00000001/sig0000045d ;
wire \blk00000001/sig0000045c ;
wire \blk00000001/sig0000045b ;
wire \blk00000001/sig0000045a ;
wire \blk00000001/sig00000459 ;
wire \blk00000001/sig00000458 ;
wire \blk00000001/sig00000457 ;
wire \blk00000001/sig00000456 ;
wire \blk00000001/sig00000455 ;
wire \blk00000001/sig00000454 ;
wire \blk00000001/sig00000453 ;
wire \blk00000001/sig00000452 ;
wire \blk00000001/sig00000451 ;
wire \blk00000001/sig00000450 ;
wire \blk00000001/sig0000044f ;
wire \blk00000001/sig0000044e ;
wire \blk00000001/sig0000044d ;
wire \blk00000001/sig0000044c ;
wire \blk00000001/sig0000044b ;
wire \blk00000001/sig0000044a ;
wire \blk00000001/sig00000449 ;
wire \blk00000001/sig00000448 ;
wire \blk00000001/sig00000447 ;
wire \blk00000001/sig00000446 ;
wire \blk00000001/sig00000445 ;
wire \blk00000001/sig00000444 ;
wire \blk00000001/sig00000443 ;
wire \blk00000001/sig00000442 ;
wire \blk00000001/sig00000441 ;
wire \blk00000001/sig00000440 ;
wire \blk00000001/sig0000043f ;
wire \blk00000001/sig0000043e ;
wire \blk00000001/sig0000043d ;
wire \blk00000001/sig0000043c ;
wire \blk00000001/sig0000043b ;
wire \blk00000001/sig0000043a ;
wire \blk00000001/sig00000439 ;
wire \blk00000001/sig00000438 ;
wire \blk00000001/sig00000437 ;
wire \blk00000001/sig00000436 ;
wire \blk00000001/sig00000435 ;
wire \blk00000001/sig00000434 ;
wire \blk00000001/sig00000433 ;
wire \blk00000001/sig00000432 ;
wire \blk00000001/sig00000431 ;
wire \blk00000001/sig00000430 ;
wire \blk00000001/sig0000042f ;
wire \blk00000001/sig0000042e ;
wire \blk00000001/sig0000042d ;
wire \blk00000001/sig0000042c ;
wire \blk00000001/sig0000042b ;
wire \blk00000001/sig0000042a ;
wire \blk00000001/sig00000429 ;
wire \blk00000001/sig00000428 ;
wire \blk00000001/sig00000427 ;
wire \blk00000001/sig00000426 ;
wire \blk00000001/sig00000425 ;
wire \blk00000001/sig00000424 ;
wire \blk00000001/sig00000423 ;
wire \blk00000001/sig00000422 ;
wire \blk00000001/sig00000421 ;
wire \blk00000001/sig00000420 ;
wire \blk00000001/sig0000041f ;
wire \blk00000001/sig0000041e ;
wire \blk00000001/sig0000041d ;
wire \blk00000001/sig0000041c ;
wire \blk00000001/sig0000041b ;
wire \blk00000001/sig0000041a ;
wire \blk00000001/sig00000419 ;
wire \blk00000001/sig00000418 ;
wire \blk00000001/sig00000417 ;
wire \blk00000001/sig00000416 ;
wire \blk00000001/sig00000415 ;
wire \blk00000001/sig00000414 ;
wire \blk00000001/sig00000413 ;
wire \blk00000001/sig00000412 ;
wire \blk00000001/sig00000411 ;
wire \blk00000001/sig00000410 ;
wire \blk00000001/sig0000040f ;
wire \blk00000001/sig0000040e ;
wire \blk00000001/sig0000040d ;
wire \blk00000001/sig0000040c ;
wire \blk00000001/sig0000040b ;
wire \blk00000001/sig0000040a ;
wire \blk00000001/sig00000409 ;
wire \blk00000001/sig00000408 ;
wire \blk00000001/sig00000407 ;
wire \blk00000001/sig00000406 ;
wire \blk00000001/sig00000405 ;
wire \blk00000001/sig00000404 ;
wire \blk00000001/sig00000403 ;
wire \blk00000001/sig00000402 ;
wire \blk00000001/sig00000401 ;
wire \blk00000001/sig00000400 ;
wire \blk00000001/sig000003ff ;
wire \blk00000001/sig000003fe ;
wire \blk00000001/sig000003fd ;
wire \blk00000001/sig000003fc ;
wire \blk00000001/sig000003fb ;
wire \blk00000001/sig000003fa ;
wire \blk00000001/sig000003f9 ;
wire \blk00000001/sig000003f8 ;
wire \blk00000001/sig000003f7 ;
wire \blk00000001/sig000003f6 ;
wire \blk00000001/sig000003f5 ;
wire \blk00000001/sig000003f4 ;
wire \blk00000001/sig000003f3 ;
wire \blk00000001/sig000003f2 ;
wire \blk00000001/sig000003f1 ;
wire \blk00000001/sig000003f0 ;
wire \blk00000001/sig000003ef ;
wire \blk00000001/sig000003ee ;
wire \blk00000001/sig000003ed ;
wire \blk00000001/sig000003ec ;
wire \blk00000001/sig000003eb ;
wire \blk00000001/sig000003ea ;
wire \blk00000001/sig000003e9 ;
wire \blk00000001/sig000003e8 ;
wire \blk00000001/sig000003e7 ;
wire \blk00000001/sig000003e6 ;
wire \blk00000001/sig000003e5 ;
wire \blk00000001/sig000003e4 ;
wire \blk00000001/sig000003e3 ;
wire \blk00000001/sig000003e2 ;
wire \blk00000001/sig000003e1 ;
wire \blk00000001/sig000003e0 ;
wire \blk00000001/sig000003df ;
wire \blk00000001/sig000003de ;
wire \blk00000001/sig000003dd ;
wire \blk00000001/sig000003dc ;
wire \blk00000001/sig000003db ;
wire \blk00000001/sig000003da ;
wire \blk00000001/sig000003d9 ;
wire \blk00000001/sig000003d8 ;
wire \blk00000001/sig000003d7 ;
wire \blk00000001/sig000003d6 ;
wire \blk00000001/sig000003d5 ;
wire \blk00000001/sig000003d4 ;
wire \blk00000001/sig000003d3 ;
wire \blk00000001/sig000003d2 ;
wire \blk00000001/sig000003d1 ;
wire \blk00000001/sig000003d0 ;
wire \blk00000001/sig000003cf ;
wire \blk00000001/sig000003ce ;
wire \blk00000001/sig000003cd ;
wire \blk00000001/sig000003cc ;
wire \blk00000001/sig000003cb ;
wire \blk00000001/sig000003ca ;
wire \blk00000001/sig000003c9 ;
wire \blk00000001/sig000003c8 ;
wire \blk00000001/sig000003c7 ;
wire \blk00000001/sig000003c6 ;
wire \blk00000001/sig000003c5 ;
wire \blk00000001/sig000003c4 ;
wire \blk00000001/sig000003c3 ;
wire \blk00000001/sig000003c2 ;
wire \blk00000001/sig000003c1 ;
wire \blk00000001/sig000003c0 ;
wire \blk00000001/sig000003bf ;
wire \blk00000001/sig000003be ;
wire \blk00000001/sig000003bd ;
wire \blk00000001/sig000003bc ;
wire \blk00000001/sig000003bb ;
wire \blk00000001/sig000003ba ;
wire \blk00000001/sig000003b9 ;
wire \blk00000001/sig000003b8 ;
wire \blk00000001/sig000003b7 ;
wire \blk00000001/sig000003b6 ;
wire \blk00000001/sig000003b5 ;
wire \blk00000001/sig000003b4 ;
wire \blk00000001/sig000003b3 ;
wire \blk00000001/sig000003b2 ;
wire \blk00000001/sig000003b1 ;
wire \blk00000001/sig000003b0 ;
wire \blk00000001/sig000003af ;
wire \blk00000001/sig000003ae ;
wire \blk00000001/sig000003ad ;
wire \blk00000001/sig000003ac ;
wire \blk00000001/sig000003ab ;
wire \blk00000001/sig000003aa ;
wire \blk00000001/sig000003a9 ;
wire \blk00000001/sig000003a8 ;
wire \blk00000001/sig000003a7 ;
wire \blk00000001/sig000003a6 ;
wire \blk00000001/sig000003a5 ;
wire \blk00000001/sig000003a4 ;
wire \blk00000001/sig000003a3 ;
wire \blk00000001/sig000003a2 ;
wire \blk00000001/sig000003a1 ;
wire \blk00000001/sig000003a0 ;
wire \blk00000001/sig0000039f ;
wire \blk00000001/sig0000039e ;
wire \blk00000001/sig0000039d ;
wire \blk00000001/sig0000039c ;
wire \blk00000001/sig0000039b ;
wire \blk00000001/sig0000039a ;
wire \blk00000001/sig00000399 ;
wire \blk00000001/sig00000398 ;
wire \blk00000001/sig00000397 ;
wire \blk00000001/sig00000396 ;
wire \blk00000001/sig00000395 ;
wire \blk00000001/sig00000394 ;
wire \blk00000001/sig00000393 ;
wire \blk00000001/sig00000392 ;
wire \blk00000001/sig00000391 ;
wire \blk00000001/sig00000390 ;
wire \blk00000001/sig0000038f ;
wire \blk00000001/sig0000038e ;
wire \blk00000001/sig0000038d ;
wire \blk00000001/sig0000038c ;
wire \blk00000001/sig0000038b ;
wire \blk00000001/sig0000038a ;
wire \blk00000001/sig00000389 ;
wire \blk00000001/sig00000388 ;
wire \blk00000001/sig00000387 ;
wire \blk00000001/sig00000386 ;
wire \blk00000001/sig00000385 ;
wire \blk00000001/sig00000384 ;
wire \blk00000001/sig00000383 ;
wire \blk00000001/sig00000382 ;
wire \blk00000001/sig00000381 ;
wire \blk00000001/sig00000380 ;
wire \blk00000001/sig0000037f ;
wire \blk00000001/sig0000037e ;
wire \blk00000001/sig0000037d ;
wire \blk00000001/sig0000037c ;
wire \blk00000001/sig0000037b ;
wire \blk00000001/sig0000037a ;
wire \blk00000001/sig00000379 ;
wire \blk00000001/sig00000378 ;
wire \blk00000001/sig00000377 ;
wire \blk00000001/sig00000376 ;
wire \blk00000001/sig00000375 ;
wire \blk00000001/sig00000374 ;
wire \blk00000001/sig00000373 ;
wire \blk00000001/sig00000372 ;
wire \blk00000001/sig00000371 ;
wire \blk00000001/sig00000370 ;
wire \blk00000001/sig0000036f ;
wire \blk00000001/sig0000036e ;
wire \blk00000001/sig0000036d ;
wire \blk00000001/sig0000036c ;
wire \blk00000001/sig0000036b ;
wire \blk00000001/sig0000036a ;
wire \blk00000001/sig00000369 ;
wire \blk00000001/sig00000368 ;
wire \blk00000001/sig00000367 ;
wire \blk00000001/sig00000366 ;
wire \blk00000001/sig00000365 ;
wire \blk00000001/sig00000364 ;
wire \blk00000001/sig00000363 ;
wire \blk00000001/sig00000362 ;
wire \blk00000001/sig00000361 ;
wire \blk00000001/sig00000360 ;
wire \blk00000001/sig0000035f ;
wire \blk00000001/sig0000035e ;
wire \blk00000001/sig0000035d ;
wire \blk00000001/sig0000035c ;
wire \blk00000001/sig0000035b ;
wire \blk00000001/sig0000035a ;
wire \blk00000001/sig00000359 ;
wire \blk00000001/sig00000358 ;
wire \blk00000001/sig00000357 ;
wire \blk00000001/sig00000356 ;
wire \blk00000001/sig00000355 ;
wire \blk00000001/sig00000354 ;
wire \blk00000001/sig00000353 ;
wire \blk00000001/sig00000352 ;
wire \blk00000001/sig00000351 ;
wire \blk00000001/sig00000350 ;
wire \blk00000001/sig0000034f ;
wire \blk00000001/sig0000034e ;
wire \blk00000001/sig0000034d ;
wire \blk00000001/sig0000034c ;
wire \blk00000001/sig0000034b ;
wire \blk00000001/sig0000034a ;
wire \blk00000001/sig00000349 ;
wire \blk00000001/sig00000348 ;
wire \blk00000001/sig00000347 ;
wire \blk00000001/sig00000346 ;
wire \blk00000001/sig00000345 ;
wire \blk00000001/sig00000344 ;
wire \blk00000001/sig00000343 ;
wire \blk00000001/sig00000342 ;
wire \blk00000001/sig00000341 ;
wire \blk00000001/sig00000340 ;
wire \blk00000001/sig0000033f ;
wire \blk00000001/sig0000033e ;
wire \blk00000001/sig0000033d ;
wire \blk00000001/sig0000033c ;
wire \blk00000001/sig0000033b ;
wire \blk00000001/sig0000033a ;
wire \blk00000001/sig00000339 ;
wire \blk00000001/sig00000338 ;
wire \blk00000001/sig00000337 ;
wire \blk00000001/sig00000336 ;
wire \blk00000001/sig00000335 ;
wire \blk00000001/sig00000334 ;
wire \blk00000001/sig00000333 ;
wire \blk00000001/sig00000332 ;
wire \blk00000001/sig00000331 ;
wire \blk00000001/sig00000330 ;
wire \blk00000001/sig0000032f ;
wire \blk00000001/sig0000032e ;
wire \blk00000001/sig0000032d ;
wire \blk00000001/sig0000032c ;
wire \blk00000001/sig0000032b ;
wire \blk00000001/sig0000032a ;
wire \blk00000001/sig00000329 ;
wire \blk00000001/sig00000328 ;
wire \blk00000001/sig00000327 ;
wire \blk00000001/sig00000326 ;
wire \blk00000001/sig00000325 ;
wire \blk00000001/sig00000324 ;
wire \blk00000001/sig00000323 ;
wire \blk00000001/sig00000322 ;
wire \blk00000001/sig00000321 ;
wire \blk00000001/sig00000320 ;
wire \blk00000001/sig0000031f ;
wire \blk00000001/sig0000031e ;
wire \blk00000001/sig0000031d ;
wire \blk00000001/sig0000031c ;
wire \blk00000001/sig0000031b ;
wire \blk00000001/sig0000031a ;
wire \blk00000001/sig00000319 ;
wire \blk00000001/sig00000318 ;
wire \blk00000001/sig00000317 ;
wire \blk00000001/sig00000316 ;
wire \blk00000001/sig00000315 ;
wire \blk00000001/sig00000314 ;
wire \blk00000001/sig00000313 ;
wire \blk00000001/sig00000312 ;
wire \blk00000001/sig00000311 ;
wire \blk00000001/sig00000310 ;
wire \blk00000001/sig0000030f ;
wire \blk00000001/sig0000030e ;
wire \blk00000001/sig0000030d ;
wire \blk00000001/sig0000030c ;
wire \blk00000001/sig0000030b ;
wire \blk00000001/sig0000030a ;
wire \blk00000001/sig00000309 ;
wire \blk00000001/sig00000308 ;
wire \blk00000001/sig00000307 ;
wire \blk00000001/sig00000306 ;
wire \blk00000001/sig00000305 ;
wire \blk00000001/sig00000304 ;
wire \blk00000001/sig00000303 ;
wire \blk00000001/sig00000302 ;
wire \blk00000001/sig00000301 ;
wire \blk00000001/sig00000300 ;
wire \blk00000001/sig000002ff ;
wire \blk00000001/sig000002fe ;
wire \blk00000001/sig000002fd ;
wire \blk00000001/sig000002fc ;
wire \blk00000001/sig000002fb ;
wire \blk00000001/sig000002fa ;
wire \blk00000001/sig000002f9 ;
wire \blk00000001/sig000002f8 ;
wire \blk00000001/sig000002f7 ;
wire \blk00000001/sig000002f6 ;
wire \blk00000001/sig000002f5 ;
wire \blk00000001/sig000002f4 ;
wire \blk00000001/sig000002f3 ;
wire \blk00000001/sig000002f2 ;
wire \blk00000001/sig000002f1 ;
wire \blk00000001/sig000002f0 ;
wire \blk00000001/sig000002ef ;
wire \blk00000001/sig000002ee ;
wire \blk00000001/sig000002ed ;
wire \blk00000001/sig000002ec ;
wire \blk00000001/sig000002eb ;
wire \blk00000001/sig000002ea ;
wire \blk00000001/sig000002e9 ;
wire \blk00000001/sig000002e8 ;
wire \blk00000001/sig000002e7 ;
wire \blk00000001/sig000002e6 ;
wire \blk00000001/sig000002e5 ;
wire \blk00000001/sig000002e4 ;
wire \blk00000001/sig000002e3 ;
wire \blk00000001/sig000002e2 ;
wire \blk00000001/sig000002e1 ;
wire \blk00000001/sig000002e0 ;
wire \blk00000001/sig000002df ;
wire \blk00000001/sig000002de ;
wire \blk00000001/sig000002dd ;
wire \blk00000001/sig000002dc ;
wire \blk00000001/sig000002db ;
wire \blk00000001/sig000002da ;
wire \blk00000001/sig000002d9 ;
wire \blk00000001/sig000002d8 ;
wire \blk00000001/sig000002d7 ;
wire \blk00000001/sig000002d6 ;
wire \blk00000001/sig000002d5 ;
wire \blk00000001/sig000002d4 ;
wire \blk00000001/sig000002d3 ;
wire \blk00000001/sig000002d2 ;
wire \blk00000001/sig000002d1 ;
wire \blk00000001/sig000002d0 ;
wire \blk00000001/sig000002cf ;
wire \blk00000001/sig000002ce ;
wire \blk00000001/sig000002cd ;
wire \blk00000001/sig000002cc ;
wire \blk00000001/sig000002cb ;
wire \blk00000001/sig000002ca ;
wire \blk00000001/sig000002c9 ;
wire \blk00000001/sig000002c8 ;
wire \blk00000001/sig000002c7 ;
wire \blk00000001/sig000002c6 ;
wire \blk00000001/sig000002c5 ;
wire \blk00000001/sig000002c4 ;
wire \blk00000001/sig000002c3 ;
wire \blk00000001/sig000002c2 ;
wire \blk00000001/sig000002c1 ;
wire \blk00000001/sig000002c0 ;
wire \blk00000001/sig000002bf ;
wire \blk00000001/sig000002be ;
wire \blk00000001/sig000002bd ;
wire \blk00000001/sig000002bc ;
wire \blk00000001/sig000002bb ;
wire \blk00000001/sig000002ba ;
wire \blk00000001/sig000002b9 ;
wire \blk00000001/sig000002b8 ;
wire \blk00000001/sig000002b7 ;
wire \blk00000001/sig000002b6 ;
wire \blk00000001/sig000002b5 ;
wire \blk00000001/sig000002b4 ;
wire \blk00000001/sig000002b3 ;
wire \blk00000001/sig000002b2 ;
wire \blk00000001/sig000002b1 ;
wire \blk00000001/sig000002b0 ;
wire \blk00000001/sig000002af ;
wire \blk00000001/sig000002ae ;
wire \blk00000001/sig000002ad ;
wire \blk00000001/sig000002ac ;
wire \blk00000001/sig000002ab ;
wire \blk00000001/sig000002aa ;
wire \blk00000001/sig000002a9 ;
wire \blk00000001/sig000002a8 ;
wire \blk00000001/sig000002a7 ;
wire \blk00000001/sig000002a6 ;
wire \blk00000001/sig000002a5 ;
wire \blk00000001/sig000002a4 ;
wire \blk00000001/sig000002a3 ;
wire \blk00000001/sig000002a2 ;
wire \blk00000001/sig000002a1 ;
wire \blk00000001/sig000002a0 ;
wire \blk00000001/sig0000029f ;
wire \blk00000001/sig0000029e ;
wire \blk00000001/sig0000029d ;
wire \blk00000001/sig0000029c ;
wire \blk00000001/sig0000029b ;
wire \blk00000001/sig0000029a ;
wire \blk00000001/sig00000299 ;
wire \blk00000001/sig00000298 ;
wire \blk00000001/sig00000297 ;
wire \blk00000001/sig00000296 ;
wire \blk00000001/sig00000295 ;
wire \blk00000001/sig00000294 ;
wire \blk00000001/sig00000293 ;
wire \blk00000001/sig00000292 ;
wire \blk00000001/sig00000291 ;
wire \blk00000001/sig00000290 ;
wire \blk00000001/sig0000028f ;
wire \blk00000001/sig0000028e ;
wire \blk00000001/sig0000028d ;
wire \blk00000001/sig0000028c ;
wire \blk00000001/sig0000028b ;
wire \blk00000001/sig0000028a ;
wire \blk00000001/sig00000289 ;
wire \blk00000001/sig00000288 ;
wire \blk00000001/sig00000287 ;
wire \blk00000001/sig00000286 ;
wire \blk00000001/sig00000285 ;
wire \blk00000001/sig00000284 ;
wire \blk00000001/sig00000283 ;
wire \blk00000001/sig00000282 ;
wire \blk00000001/sig00000281 ;
wire \blk00000001/sig00000280 ;
wire \blk00000001/sig0000027f ;
wire \blk00000001/sig0000027e ;
wire \blk00000001/sig0000027d ;
wire \blk00000001/sig0000027c ;
wire \blk00000001/sig0000027b ;
wire \blk00000001/sig0000027a ;
wire \blk00000001/sig00000279 ;
wire \blk00000001/sig00000278 ;
wire \blk00000001/sig00000277 ;
wire \blk00000001/sig00000276 ;
wire \blk00000001/sig00000275 ;
wire \blk00000001/sig00000274 ;
wire \blk00000001/sig00000273 ;
wire \blk00000001/sig00000272 ;
wire \blk00000001/sig00000271 ;
wire \blk00000001/sig00000270 ;
wire \blk00000001/sig0000026f ;
wire \blk00000001/sig0000026e ;
wire \blk00000001/sig0000026d ;
wire \blk00000001/sig0000026c ;
wire \blk00000001/sig0000026b ;
wire \blk00000001/sig0000026a ;
wire \blk00000001/sig00000269 ;
wire \blk00000001/sig00000268 ;
wire \blk00000001/sig00000267 ;
wire \blk00000001/sig00000266 ;
wire \blk00000001/sig00000265 ;
wire \blk00000001/sig00000264 ;
wire \blk00000001/sig00000263 ;
wire \blk00000001/sig00000262 ;
wire \blk00000001/sig00000261 ;
wire \blk00000001/sig00000260 ;
wire \blk00000001/sig0000025f ;
wire \blk00000001/sig0000025e ;
wire \blk00000001/sig0000025d ;
wire \blk00000001/sig0000025c ;
wire \blk00000001/sig0000025b ;
wire \blk00000001/sig0000025a ;
wire \blk00000001/sig00000259 ;
wire \blk00000001/sig00000258 ;
wire \blk00000001/sig00000257 ;
wire \blk00000001/sig00000256 ;
wire \blk00000001/sig00000255 ;
wire \blk00000001/sig00000254 ;
wire \blk00000001/sig00000253 ;
wire \blk00000001/sig00000252 ;
wire \blk00000001/sig00000251 ;
wire \blk00000001/sig00000250 ;
wire \blk00000001/sig0000024f ;
wire \blk00000001/sig0000024e ;
wire \blk00000001/sig0000024d ;
wire \blk00000001/sig0000024c ;
wire \blk00000001/sig0000024b ;
wire \blk00000001/sig0000024a ;
wire \blk00000001/sig00000249 ;
wire \blk00000001/sig00000248 ;
wire \blk00000001/sig00000247 ;
wire \blk00000001/sig00000246 ;
wire \blk00000001/sig00000245 ;
wire \blk00000001/sig00000244 ;
wire \blk00000001/sig00000243 ;
wire \blk00000001/sig00000242 ;
wire \blk00000001/sig00000241 ;
wire \blk00000001/sig00000240 ;
wire \blk00000001/sig0000023f ;
wire \blk00000001/sig0000023e ;
wire \blk00000001/sig0000023d ;
wire \blk00000001/sig0000023c ;
wire \blk00000001/sig0000023b ;
wire \blk00000001/sig0000023a ;
wire \blk00000001/sig00000239 ;
wire \blk00000001/sig00000238 ;
wire \blk00000001/sig00000237 ;
wire \blk00000001/sig00000236 ;
wire \blk00000001/sig00000235 ;
wire \blk00000001/sig00000234 ;
wire \blk00000001/sig00000233 ;
wire \blk00000001/sig00000232 ;
wire \blk00000001/sig00000231 ;
wire \blk00000001/sig00000230 ;
wire \blk00000001/sig0000022f ;
wire \blk00000001/sig0000022e ;
wire \blk00000001/sig0000022d ;
wire \blk00000001/sig0000022c ;
wire \blk00000001/sig0000022b ;
wire \blk00000001/sig0000022a ;
wire \blk00000001/sig00000229 ;
wire \blk00000001/sig00000228 ;
wire \blk00000001/sig00000227 ;
wire \blk00000001/sig00000226 ;
wire \blk00000001/sig00000225 ;
wire \blk00000001/sig00000224 ;
wire \blk00000001/sig00000223 ;
wire \blk00000001/sig00000222 ;
wire \blk00000001/sig00000221 ;
wire \blk00000001/sig00000220 ;
wire \blk00000001/sig0000021f ;
wire \blk00000001/sig0000021e ;
wire \blk00000001/sig0000021d ;
wire \blk00000001/sig0000021c ;
wire \blk00000001/sig0000021b ;
wire \blk00000001/sig0000021a ;
wire \blk00000001/sig00000219 ;
wire \blk00000001/sig00000218 ;
wire \blk00000001/sig00000217 ;
wire \blk00000001/sig00000216 ;
wire \blk00000001/sig00000215 ;
wire \blk00000001/sig00000214 ;
wire \blk00000001/sig00000213 ;
wire \blk00000001/sig00000212 ;
wire \blk00000001/sig00000211 ;
wire \blk00000001/sig00000210 ;
wire \blk00000001/sig0000020f ;
wire \blk00000001/sig0000020e ;
wire \blk00000001/sig0000020d ;
wire \blk00000001/sig0000020c ;
wire \blk00000001/sig0000020b ;
wire \blk00000001/sig0000020a ;
wire \blk00000001/sig00000209 ;
wire \blk00000001/sig00000208 ;
wire \blk00000001/sig00000207 ;
wire \blk00000001/sig00000206 ;
wire \blk00000001/sig00000205 ;
wire \blk00000001/sig00000204 ;
wire \blk00000001/sig00000203 ;
wire \blk00000001/sig00000202 ;
wire \blk00000001/sig00000201 ;
wire \blk00000001/sig00000200 ;
wire \blk00000001/sig000001ff ;
wire \blk00000001/sig000001fe ;
wire \blk00000001/sig000001fd ;
wire \blk00000001/sig000001fc ;
wire \blk00000001/sig000001fb ;
wire \blk00000001/sig000001fa ;
wire \blk00000001/sig000001f9 ;
wire \blk00000001/sig000001f8 ;
wire \blk00000001/sig000001f7 ;
wire \blk00000001/sig000001f6 ;
wire \blk00000001/sig000001f5 ;
wire \blk00000001/sig000001f4 ;
wire \blk00000001/sig000001f3 ;
wire \blk00000001/sig000001f2 ;
wire \blk00000001/sig000001f1 ;
wire \blk00000001/sig000001f0 ;
wire \blk00000001/sig000001ef ;
wire \blk00000001/sig000001ee ;
wire \blk00000001/sig000001ed ;
wire \blk00000001/sig000001ec ;
wire \blk00000001/sig000001eb ;
wire \blk00000001/sig000001ea ;
wire \blk00000001/sig000001e9 ;
wire \blk00000001/sig000001e8 ;
wire \blk00000001/sig000001e7 ;
wire \blk00000001/sig000001e6 ;
wire \blk00000001/sig000001e5 ;
wire \blk00000001/sig000001e4 ;
wire \blk00000001/sig000001e3 ;
wire \blk00000001/sig000001e2 ;
wire \blk00000001/sig000001e1 ;
wire \blk00000001/sig000001e0 ;
wire \blk00000001/sig000001df ;
wire \blk00000001/sig000001de ;
wire \blk00000001/sig000001dd ;
wire \blk00000001/sig000001dc ;
wire \blk00000001/sig000001db ;
wire \blk00000001/sig000001da ;
wire \blk00000001/sig000001d9 ;
wire \blk00000001/sig000001d8 ;
wire \blk00000001/sig000001d7 ;
wire \blk00000001/sig000001d6 ;
wire \blk00000001/sig000001d5 ;
wire \blk00000001/sig000001d4 ;
wire \blk00000001/sig000001d3 ;
wire \blk00000001/sig000001d2 ;
wire \blk00000001/sig000001d1 ;
wire \blk00000001/sig000001d0 ;
wire \blk00000001/sig000001cf ;
wire \blk00000001/sig000001ce ;
wire \blk00000001/sig000001cd ;
wire \blk00000001/sig000001cc ;
wire \blk00000001/sig000001cb ;
wire \blk00000001/sig000001ca ;
wire \blk00000001/sig000001c9 ;
wire \blk00000001/sig000001c8 ;
wire \blk00000001/sig000001c7 ;
wire \blk00000001/sig000001c6 ;
wire \blk00000001/sig000001c5 ;
wire \blk00000001/sig000001c4 ;
wire \blk00000001/sig000001c3 ;
wire \blk00000001/sig000001c2 ;
wire \blk00000001/sig000001c1 ;
wire \blk00000001/sig000001c0 ;
wire \blk00000001/sig000001bf ;
wire \blk00000001/sig000001be ;
wire \blk00000001/sig000001bd ;
wire \blk00000001/sig000001bc ;
wire \blk00000001/sig000001bb ;
wire \blk00000001/sig000001ba ;
wire \blk00000001/sig000001b9 ;
wire \blk00000001/sig000001b8 ;
wire \blk00000001/sig000001b7 ;
wire \blk00000001/sig000001b6 ;
wire \blk00000001/sig000001b5 ;
wire \blk00000001/sig000001b4 ;
wire \blk00000001/sig000001b3 ;
wire \blk00000001/sig000001b2 ;
wire \blk00000001/sig000001b1 ;
wire \blk00000001/sig000001b0 ;
wire \blk00000001/sig000001af ;
wire \blk00000001/sig000001ae ;
wire \blk00000001/sig000001ad ;
wire \blk00000001/sig000001ac ;
wire \blk00000001/sig000001ab ;
wire \blk00000001/sig000001aa ;
wire \blk00000001/sig000001a9 ;
wire \blk00000001/sig000001a8 ;
wire \blk00000001/sig000001a7 ;
wire \blk00000001/sig000001a6 ;
wire \blk00000001/sig000001a5 ;
wire \blk00000001/sig000001a4 ;
wire \blk00000001/sig000001a3 ;
wire \blk00000001/sig000001a2 ;
wire \blk00000001/sig000001a1 ;
wire \blk00000001/sig000001a0 ;
wire \blk00000001/sig0000019f ;
wire \blk00000001/sig0000019e ;
wire \blk00000001/sig0000019d ;
wire \blk00000001/sig0000019c ;
wire \blk00000001/sig0000019b ;
wire \blk00000001/sig0000019a ;
wire \blk00000001/sig00000199 ;
wire \blk00000001/sig00000198 ;
wire \blk00000001/sig00000197 ;
wire \blk00000001/sig00000196 ;
wire \blk00000001/sig00000195 ;
wire \blk00000001/sig00000194 ;
wire \blk00000001/sig00000193 ;
wire \blk00000001/sig00000192 ;
wire \blk00000001/sig00000191 ;
wire \blk00000001/sig00000190 ;
wire \blk00000001/sig0000018f ;
wire \blk00000001/sig0000018e ;
wire \blk00000001/sig0000018d ;
wire \blk00000001/sig0000018c ;
wire \blk00000001/sig0000018b ;
wire \blk00000001/sig0000018a ;
wire \blk00000001/sig00000189 ;
wire \blk00000001/sig00000188 ;
wire \blk00000001/sig00000187 ;
wire \blk00000001/sig00000186 ;
wire \blk00000001/sig00000185 ;
wire \blk00000001/sig00000184 ;
wire \blk00000001/sig00000183 ;
wire \blk00000001/sig00000182 ;
wire \blk00000001/sig00000181 ;
wire \blk00000001/sig00000180 ;
wire \blk00000001/sig0000017f ;
wire \blk00000001/sig0000017e ;
wire \blk00000001/sig0000017d ;
wire \blk00000001/sig0000017c ;
wire \blk00000001/sig0000017b ;
wire \blk00000001/sig0000017a ;
wire \blk00000001/sig00000179 ;
wire \blk00000001/sig00000178 ;
wire \blk00000001/sig00000177 ;
wire \blk00000001/sig00000176 ;
wire \blk00000001/sig00000175 ;
wire \blk00000001/sig00000174 ;
wire \blk00000001/sig00000173 ;
wire \blk00000001/sig00000172 ;
wire \blk00000001/sig00000171 ;
wire \blk00000001/sig00000170 ;
wire \blk00000001/sig0000016f ;
wire \blk00000001/sig0000016e ;
wire \blk00000001/sig0000016d ;
wire \blk00000001/sig0000016c ;
wire \blk00000001/sig0000016b ;
wire \blk00000001/sig0000016a ;
wire \blk00000001/sig00000169 ;
wire \blk00000001/sig00000168 ;
wire \blk00000001/sig00000167 ;
wire \blk00000001/sig00000166 ;
wire \blk00000001/sig00000165 ;
wire \blk00000001/sig00000164 ;
wire \blk00000001/sig00000163 ;
wire \blk00000001/sig00000162 ;
wire \blk00000001/sig00000161 ;
wire \blk00000001/sig00000160 ;
wire \blk00000001/sig0000015f ;
wire \blk00000001/sig0000015e ;
wire \blk00000001/sig0000015d ;
wire \blk00000001/sig0000015c ;
wire \blk00000001/sig0000015b ;
wire \blk00000001/sig0000015a ;
wire \blk00000001/sig00000159 ;
wire \blk00000001/sig00000158 ;
wire \blk00000001/sig00000157 ;
wire \blk00000001/sig00000156 ;
wire \blk00000001/sig00000155 ;
wire \blk00000001/sig00000154 ;
wire \blk00000001/sig00000153 ;
wire \blk00000001/sig00000152 ;
wire \blk00000001/sig00000151 ;
wire \blk00000001/sig00000150 ;
wire \blk00000001/sig0000014f ;
wire \blk00000001/sig0000014e ;
wire \blk00000001/sig0000014d ;
wire \blk00000001/sig0000014c ;
wire \blk00000001/sig0000014b ;
wire \blk00000001/sig0000014a ;
wire \blk00000001/sig00000149 ;
wire \blk00000001/sig00000148 ;
wire \blk00000001/sig00000147 ;
wire \blk00000001/sig00000146 ;
wire \blk00000001/sig00000145 ;
wire \blk00000001/sig00000144 ;
wire \blk00000001/sig00000143 ;
wire \blk00000001/sig00000142 ;
wire \blk00000001/sig00000141 ;
wire \blk00000001/sig00000140 ;
wire \blk00000001/sig0000013f ;
wire \blk00000001/sig0000013e ;
wire \blk00000001/sig0000013d ;
wire \blk00000001/sig0000013c ;
wire \blk00000001/sig0000013b ;
wire \blk00000001/sig0000013a ;
wire \blk00000001/sig00000139 ;
wire \blk00000001/sig00000138 ;
wire \blk00000001/sig00000137 ;
wire \blk00000001/sig00000136 ;
wire \blk00000001/sig00000135 ;
wire \blk00000001/sig00000134 ;
wire \blk00000001/sig00000133 ;
wire \blk00000001/sig00000132 ;
wire \blk00000001/sig00000131 ;
wire \blk00000001/sig00000130 ;
wire \blk00000001/sig0000012f ;
wire \blk00000001/sig0000012e ;
wire \blk00000001/sig0000012d ;
wire \blk00000001/sig0000012c ;
wire \blk00000001/sig0000012b ;
wire \blk00000001/sig0000012a ;
wire \blk00000001/sig00000129 ;
wire \blk00000001/sig00000128 ;
wire \blk00000001/sig00000127 ;
wire \blk00000001/sig00000126 ;
wire \blk00000001/sig00000125 ;
wire \blk00000001/sig00000124 ;
wire \blk00000001/sig00000123 ;
wire \blk00000001/sig00000122 ;
wire \blk00000001/sig00000121 ;
wire \blk00000001/sig00000120 ;
wire \blk00000001/sig0000011f ;
wire \blk00000001/sig0000011e ;
wire \blk00000001/sig0000011d ;
wire \blk00000001/sig0000011c ;
wire \blk00000001/sig0000011b ;
wire \blk00000001/sig0000011a ;
wire \blk00000001/sig00000119 ;
wire \blk00000001/sig00000118 ;
wire \blk00000001/sig00000117 ;
wire \blk00000001/sig00000116 ;
wire \blk00000001/sig00000115 ;
wire \blk00000001/sig00000114 ;
wire \blk00000001/sig00000113 ;
wire \blk00000001/sig00000112 ;
wire \blk00000001/sig00000111 ;
wire \blk00000001/sig00000110 ;
wire \blk00000001/sig0000010f ;
wire \blk00000001/sig0000010e ;
wire \blk00000001/sig0000010d ;
wire \blk00000001/sig0000010c ;
wire \blk00000001/sig0000010b ;
wire \blk00000001/sig0000010a ;
wire \blk00000001/sig00000109 ;
wire \blk00000001/sig00000108 ;
wire \blk00000001/sig00000107 ;
wire \blk00000001/sig00000106 ;
wire \blk00000001/sig00000105 ;
wire \blk00000001/sig00000104 ;
wire \blk00000001/sig00000103 ;
wire \blk00000001/sig00000102 ;
wire \blk00000001/sig00000101 ;
wire \blk00000001/sig00000100 ;
wire \blk00000001/sig000000ff ;
wire \blk00000001/sig000000fe ;
wire \blk00000001/sig000000fd ;
wire \blk00000001/sig000000fc ;
wire \blk00000001/sig000000fb ;
wire \blk00000001/sig000000fa ;
wire \blk00000001/sig000000f9 ;
wire \blk00000001/sig000000f8 ;
wire \blk00000001/sig000000f7 ;
wire \blk00000001/sig000000f6 ;
wire \blk00000001/sig000000f5 ;
wire \blk00000001/sig000000f4 ;
wire \blk00000001/sig000000f3 ;
wire \blk00000001/sig000000f2 ;
wire \blk00000001/sig000000f1 ;
wire \blk00000001/sig000000f0 ;
wire \blk00000001/sig000000ef ;
wire \blk00000001/sig000000ee ;
wire \blk00000001/sig000000ed ;
wire \blk00000001/sig000000ec ;
wire \blk00000001/sig000000eb ;
wire \blk00000001/sig000000ea ;
wire \blk00000001/sig000000e9 ;
wire \blk00000001/sig000000e8 ;
wire \blk00000001/sig000000e7 ;
wire \blk00000001/sig000000e6 ;
wire \blk00000001/sig000000e5 ;
wire \blk00000001/sig000000e4 ;
wire \blk00000001/sig000000e3 ;
wire \blk00000001/sig000000e2 ;
wire \blk00000001/sig000000e1 ;
wire \blk00000001/sig000000e0 ;
wire \blk00000001/sig000000df ;
wire \blk00000001/sig000000de ;
wire \blk00000001/sig000000dd ;
wire \blk00000001/sig000000dc ;
wire \blk00000001/sig000000db ;
wire \blk00000001/sig000000da ;
wire \blk00000001/sig000000d9 ;
wire \blk00000001/sig000000d8 ;
wire \blk00000001/sig000000d7 ;
wire \blk00000001/sig000000d6 ;
wire \blk00000001/sig000000d5 ;
wire \blk00000001/sig000000d4 ;
wire \blk00000001/sig000000d3 ;
wire \blk00000001/sig000000d2 ;
wire \blk00000001/sig000000d1 ;
wire \blk00000001/sig000000d0 ;
wire \blk00000001/sig000000cf ;
wire \blk00000001/sig000000ce ;
wire \blk00000001/sig000000cd ;
wire \blk00000001/sig000000cc ;
wire \blk00000001/sig000000cb ;
wire \blk00000001/sig000000ca ;
wire \blk00000001/sig000000c9 ;
wire \blk00000001/sig000000c8 ;
wire \blk00000001/sig000000c7 ;
wire \blk00000001/sig000000c6 ;
wire \blk00000001/sig000000c5 ;
wire \blk00000001/sig000000c4 ;
wire \blk00000001/sig000000c3 ;
wire \blk00000001/sig000000c2 ;
wire \blk00000001/sig000000c1 ;
wire \blk00000001/sig000000c0 ;
wire \blk00000001/sig000000bf ;
wire \blk00000001/sig000000be ;
wire \blk00000001/sig000000bd ;
wire \blk00000001/sig000000bc ;
wire \blk00000001/sig000000bb ;
wire \blk00000001/sig000000ba ;
wire \blk00000001/sig000000b9 ;
wire \blk00000001/sig000000b8 ;
wire \blk00000001/sig000000b7 ;
wire \blk00000001/sig000000b6 ;
wire \blk00000001/sig000000b5 ;
wire \blk00000001/sig000000b4 ;
wire \blk00000001/sig000000b3 ;
wire \blk00000001/sig000000b2 ;
wire \blk00000001/sig000000b1 ;
wire \blk00000001/sig000000b0 ;
wire \blk00000001/sig000000af ;
wire \blk00000001/sig000000ae ;
wire \blk00000001/sig000000ad ;
wire \blk00000001/sig000000ac ;
wire \blk00000001/sig000000ab ;
wire \blk00000001/sig000000aa ;
wire \blk00000001/sig000000a9 ;
wire \blk00000001/sig000000a8 ;
wire \blk00000001/sig000000a7 ;
wire \blk00000001/sig000000a6 ;
wire \blk00000001/sig000000a5 ;
wire \blk00000001/sig000000a4 ;
wire \blk00000001/sig000000a3 ;
wire \blk00000001/sig000000a2 ;
wire \blk00000001/sig000000a1 ;
wire \blk00000001/sig000000a0 ;
wire \blk00000001/sig0000009f ;
wire \blk00000001/sig0000009e ;
wire \blk00000001/sig0000009d ;
wire \blk00000001/sig0000009c ;
wire \blk00000001/sig0000009b ;
wire \blk00000001/sig0000009a ;
wire \blk00000001/sig00000099 ;
wire \blk00000001/sig00000098 ;
wire \blk00000001/sig00000097 ;
wire \blk00000001/sig00000096 ;
wire \blk00000001/sig00000095 ;
wire \blk00000001/sig00000094 ;
wire \blk00000001/sig00000093 ;
wire \blk00000001/sig00000092 ;
wire \blk00000001/sig00000091 ;
wire \blk00000001/sig00000090 ;
wire \blk00000001/sig0000008f ;
wire \blk00000001/sig0000008e ;
wire \blk00000001/sig0000008d ;
wire \blk00000001/sig0000008c ;
wire \blk00000001/sig0000008b ;
wire \blk00000001/sig0000008a ;
wire \blk00000001/sig00000089 ;
wire \blk00000001/sig00000088 ;
wire \blk00000001/sig00000087 ;
wire \blk00000001/sig00000086 ;
wire \blk00000001/sig00000085 ;
wire \blk00000001/sig00000084 ;
wire \blk00000001/sig00000083 ;
wire \blk00000001/sig00000082 ;
wire \blk00000001/sig00000081 ;
wire \blk00000001/sig00000080 ;
wire \blk00000001/sig0000007f ;
wire \blk00000001/sig0000007e ;
wire \blk00000001/sig0000007d ;
wire \blk00000001/sig0000007c ;
wire \blk00000001/sig0000007b ;
wire \blk00000001/sig0000007a ;
wire \blk00000001/sig00000079 ;
wire \blk00000001/sig00000078 ;
wire \blk00000001/sig00000077 ;
wire \blk00000001/sig00000076 ;
wire \blk00000001/sig00000075 ;
wire \blk00000001/sig00000074 ;
wire \blk00000001/sig00000073 ;
wire \blk00000001/sig00000072 ;
wire \blk00000001/sig00000071 ;
wire \blk00000001/sig00000070 ;
wire \blk00000001/sig0000006f ;
wire \blk00000001/sig0000006e ;
wire \blk00000001/sig0000006d ;
wire \blk00000001/sig0000006c ;
wire \blk00000001/sig0000006b ;
wire \blk00000001/sig0000006a ;
wire \blk00000001/sig00000069 ;
wire \blk00000001/sig00000068 ;
wire \blk00000001/sig00000067 ;
wire \blk00000001/sig00000066 ;
wire \blk00000001/sig00000065 ;
wire \blk00000001/sig00000064 ;
wire \blk00000001/sig00000063 ;
wire \blk00000001/sig00000062 ;
wire \blk00000001/sig00000061 ;
wire \blk00000001/sig00000060 ;
wire \blk00000001/sig0000005f ;
wire \blk00000001/sig0000005e ;
wire \blk00000001/sig0000005d ;
wire \blk00000001/sig0000005c ;
wire \blk00000001/sig0000005b ;
wire \blk00000001/sig0000005a ;
wire \blk00000001/sig00000059 ;
wire \blk00000001/sig00000058 ;
wire \blk00000001/sig00000057 ;
wire \blk00000001/sig00000056 ;
wire \blk00000001/sig00000055 ;
wire \blk00000001/sig00000054 ;
wire \blk00000001/sig00000053 ;
wire \NLW_blk00000001/blk000007d2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007d0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007ce_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007cc_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007ca_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007c8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007c6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007c4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007c2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007c0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007be_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007bc_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007ba_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007b8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007b6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007b4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007b2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007b0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007ae_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007ac_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007aa_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007a8_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007a6_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007a4_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007a2_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk000007a0_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000079e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000079c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000079a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000798_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000796_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000794_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000792_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000790_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000078e_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000078c_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk0000078a_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000788_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000786_Q15_UNCONNECTED ;
wire \NLW_blk00000001/blk00000784_Q15_UNCONNECTED ;
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007d3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007fc ),
.Q(\blk00000001/sig000006bc )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007d2 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000464 ),
.Q(\blk00000001/sig000007fc ),
.Q15(\NLW_blk00000001/blk000007d2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007d1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007fb ),
.Q(\blk00000001/sig000006bd )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007d0 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000389 ),
.Q(\blk00000001/sig000007fb ),
.Q15(\NLW_blk00000001/blk000007d0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007cf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007fa ),
.Q(\blk00000001/sig000006ea )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007ce (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000395 ),
.Q(\blk00000001/sig000007fa ),
.Q15(\NLW_blk00000001/blk000007ce_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007cd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f9 ),
.Q(\blk00000001/sig00000672 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007cc (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000046a ),
.Q(\blk00000001/sig000007f9 ),
.Q15(\NLW_blk00000001/blk000007cc_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007cb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f8 ),
.Q(\blk00000001/sig000006e9 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007ca (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000470 ),
.Q(\blk00000001/sig000007f8 ),
.Q15(\NLW_blk00000001/blk000007ca_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007c9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f7 ),
.Q(\blk00000001/sig00000673 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007c8 (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000038f ),
.Q(\blk00000001/sig000007f7 ),
.Q15(\NLW_blk00000001/blk000007c8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007c7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f6 ),
.Q(\blk00000001/sig00000674 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007c6 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000005e7 ),
.Q(\blk00000001/sig000007f6 ),
.Q15(\NLW_blk00000001/blk000007c6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007c5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f5 ),
.Q(\blk00000001/sig0000063e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007c4 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000053 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000383 ),
.Q(\blk00000001/sig000007f5 ),
.Q15(\NLW_blk00000001/blk000007c4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007c3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f4 ),
.Q(\blk00000001/sig0000063f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007c2 (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000005bb ),
.Q(\blk00000001/sig000007f4 ),
.Q15(\NLW_blk00000001/blk000007c2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007c1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f3 ),
.Q(\blk00000001/sig0000063d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007c0 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000053 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000045e ),
.Q(\blk00000001/sig000007f3 ),
.Q15(\NLW_blk00000001/blk000007c0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007bf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f2 ),
.Q(\blk00000001/sig00000640 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007be (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006a7 ),
.Q(\blk00000001/sig000007f2 ),
.Q15(\NLW_blk00000001/blk000007be_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007bd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f1 ),
.Q(\blk00000001/sig00000641 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007bc (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006a8 ),
.Q(\blk00000001/sig000007f1 ),
.Q15(\NLW_blk00000001/blk000007bc_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007bb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007f0 ),
.Q(\blk00000001/sig00000643 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007ba (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006aa ),
.Q(\blk00000001/sig000007f0 ),
.Q15(\NLW_blk00000001/blk000007ba_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007b9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007ef ),
.Q(\blk00000001/sig00000644 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007b8 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006ab ),
.Q(\blk00000001/sig000007ef ),
.Q15(\NLW_blk00000001/blk000007b8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007b7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007ee ),
.Q(\blk00000001/sig00000642 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007b6 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006a9 ),
.Q(\blk00000001/sig000007ee ),
.Q15(\NLW_blk00000001/blk000007b6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007b5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007ed ),
.Q(\blk00000001/sig00000645 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007b4 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006ac ),
.Q(\blk00000001/sig000007ed ),
.Q15(\NLW_blk00000001/blk000007b4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007b3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007ec ),
.Q(\blk00000001/sig00000646 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007b2 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006ad ),
.Q(\blk00000001/sig000007ec ),
.Q15(\NLW_blk00000001/blk000007b2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007b1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007eb ),
.Q(\blk00000001/sig00000648 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007b0 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006af ),
.Q(\blk00000001/sig000007eb ),
.Q15(\NLW_blk00000001/blk000007b0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007af (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007ea ),
.Q(\blk00000001/sig00000649 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007ae (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b0 ),
.Q(\blk00000001/sig000007ea ),
.Q15(\NLW_blk00000001/blk000007ae_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007ad (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e9 ),
.Q(\blk00000001/sig00000647 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007ac (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006ae ),
.Q(\blk00000001/sig000007e9 ),
.Q15(\NLW_blk00000001/blk000007ac_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007ab (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e8 ),
.Q(\blk00000001/sig0000064a )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007aa (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b1 ),
.Q(\blk00000001/sig000007e8 ),
.Q15(\NLW_blk00000001/blk000007aa_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007a9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e7 ),
.Q(\blk00000001/sig0000064b )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007a8 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b2 ),
.Q(\blk00000001/sig000007e7 ),
.Q15(\NLW_blk00000001/blk000007a8_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007a7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e6 ),
.Q(\blk00000001/sig0000064d )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007a6 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b4 ),
.Q(\blk00000001/sig000007e6 ),
.Q15(\NLW_blk00000001/blk000007a6_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007a5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e5 ),
.Q(\blk00000001/sig0000064e )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007a4 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b5 ),
.Q(\blk00000001/sig000007e5 ),
.Q15(\NLW_blk00000001/blk000007a4_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007a3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e4 ),
.Q(\blk00000001/sig0000064c )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007a2 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b3 ),
.Q(\blk00000001/sig000007e4 ),
.Q15(\NLW_blk00000001/blk000007a2_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000007a1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e3 ),
.Q(\blk00000001/sig0000064f )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk000007a0 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b6 ),
.Q(\blk00000001/sig000007e3 ),
.Q15(\NLW_blk00000001/blk000007a0_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000079f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e2 ),
.Q(\blk00000001/sig00000650 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000079e (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b7 ),
.Q(\blk00000001/sig000007e2 ),
.Q15(\NLW_blk00000001/blk0000079e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000079d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e1 ),
.Q(\blk00000001/sig00000652 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000079c (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b9 ),
.Q(\blk00000001/sig000007e1 ),
.Q15(\NLW_blk00000001/blk0000079c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000079b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007e0 ),
.Q(\blk00000001/sig00000653 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000079a (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006ba ),
.Q(\blk00000001/sig000007e0 ),
.Q15(\NLW_blk00000001/blk0000079a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000799 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007df ),
.Q(\blk00000001/sig00000651 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000798 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006b8 ),
.Q(\blk00000001/sig000007df ),
.Q15(\NLW_blk00000001/blk00000798_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000797 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007de ),
.Q(\blk00000001/sig00000654 )
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000796 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000006bb ),
.Q(\blk00000001/sig000007de ),
.Q15(\NLW_blk00000001/blk00000796_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000795 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007dd ),
.Q(p[0])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000794 (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000053 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000476 ),
.Q(\blk00000001/sig000007dd ),
.Q15(\NLW_blk00000001/blk00000794_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000793 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007dc ),
.Q(p[2])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000792 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000053 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000613 ),
.Q(\blk00000001/sig000007dc ),
.Q15(\NLW_blk00000001/blk00000792_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000791 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007db ),
.Q(p[3])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000790 (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000701 ),
.Q(\blk00000001/sig000007db ),
.Q15(\NLW_blk00000001/blk00000790_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000078f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007da ),
.Q(p[1])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000078e (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000053 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000039b ),
.Q(\blk00000001/sig000007da ),
.Q15(\NLW_blk00000001/blk0000078e_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000078d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007d9 ),
.Q(p[4])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000078c (
.A0(\blk00000001/sig00000053 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig000005a2 ),
.Q(\blk00000001/sig000007d9 ),
.Q15(\NLW_blk00000001/blk0000078c_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000078b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007d8 ),
.Q(p[5])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk0000078a (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000068f ),
.Q(\blk00000001/sig000007d8 ),
.Q15(\NLW_blk00000001/blk0000078a_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000789 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007d7 ),
.Q(p[7])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000788 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000691 ),
.Q(\blk00000001/sig000007d7 ),
.Q15(\NLW_blk00000001/blk00000788_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000787 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007d6 ),
.Q(p[8])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000786 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig0000056b ),
.Q(\blk00000001/sig000007d6 ),
.Q15(\NLW_blk00000001/blk00000786_Q15_UNCONNECTED )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000785 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000007d5 ),
.Q(p[6])
);
SRLC16E #(
.INIT ( 16'h0000 ))
\blk00000001/blk00000784 (
.A0(\blk00000001/sig00000054 ),
.A1(\blk00000001/sig00000054 ),
.A2(\blk00000001/sig00000054 ),
.A3(\blk00000001/sig00000054 ),
.CE(ce),
.CLK(clk),
.D(\blk00000001/sig00000690 ),
.Q(\blk00000001/sig000007d5 ),
.Q15(\NLW_blk00000001/blk00000784_Q15_UNCONNECTED )
);
LUT3 #(
.INIT ( 8'hD7 ))
\blk00000001/blk00000783 (
.I0(a[19]),
.I1(b[18]),
.I2(b[19]),
.O(\blk00000001/sig000007d4 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000782 (
.I0(a[0]),
.I1(b[0]),
.O(\blk00000001/sig00000552 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000781 (
.I0(a[0]),
.I1(b[2]),
.O(\blk00000001/sig0000054f )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk00000780 (
.I0(a[0]),
.I1(b[4]),
.O(\blk00000001/sig0000054c )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000077f (
.I0(a[0]),
.I1(b[6]),
.O(\blk00000001/sig00000549 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000077e (
.I0(a[0]),
.I1(b[8]),
.O(\blk00000001/sig00000546 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000077d (
.I0(a[0]),
.I1(b[10]),
.O(\blk00000001/sig00000543 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000077c (
.I0(a[0]),
.I1(b[12]),
.O(\blk00000001/sig00000540 )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000077b (
.I0(a[0]),
.I1(b[14]),
.O(\blk00000001/sig0000053d )
);
LUT2 #(
.INIT ( 4'h8 ))
\blk00000001/blk0000077a (
.I0(a[0]),
.I1(b[16]),
.O(\blk00000001/sig0000053a )
);
LUT2 #(
.INIT ( 4'h7 ))
\blk00000001/blk00000779 (
.I0(a[0]),
.I1(b[18]),
.O(\blk00000001/sig0000045c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000778 (
.I0(a[10]),
.I1(b[0]),
.I2(a[9]),
.I3(b[1]),
.O(\blk00000001/sig000002e6 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000777 (
.I0(a[10]),
.I1(b[1]),
.I2(a[11]),
.I3(b[0]),
.O(\blk00000001/sig000002d3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000776 (
.I0(a[11]),
.I1(b[1]),
.I2(a[12]),
.I3(b[0]),
.O(\blk00000001/sig000002c0 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000775 (
.I0(a[12]),
.I1(b[1]),
.I2(a[13]),
.I3(b[0]),
.O(\blk00000001/sig000002ad )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000774 (
.I0(a[13]),
.I1(b[1]),
.I2(a[14]),
.I3(b[0]),
.O(\blk00000001/sig0000029a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000773 (
.I0(a[14]),
.I1(b[1]),
.I2(a[15]),
.I3(b[0]),
.O(\blk00000001/sig00000287 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000772 (
.I0(a[15]),
.I1(b[1]),
.I2(a[16]),
.I3(b[0]),
.O(\blk00000001/sig00000274 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000771 (
.I0(a[16]),
.I1(b[1]),
.I2(a[17]),
.I3(b[0]),
.O(\blk00000001/sig00000261 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000770 (
.I0(a[17]),
.I1(b[1]),
.I2(a[18]),
.I3(b[0]),
.O(\blk00000001/sig0000024e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000076f (
.I0(a[18]),
.I1(b[1]),
.I2(a[19]),
.I3(b[0]),
.O(\blk00000001/sig0000023b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000076e (
.I0(a[0]),
.I1(b[1]),
.I2(a[1]),
.I3(b[0]),
.O(\blk00000001/sig0000039a )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk0000076d (
.I0(a[19]),
.I1(b[1]),
.I2(b[0]),
.O(\blk00000001/sig00000228 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk0000076c (
.I0(a[19]),
.I1(b[1]),
.I2(b[0]),
.O(\blk00000001/sig00000215 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000076b (
.I0(a[1]),
.I1(b[1]),
.I2(a[2]),
.I3(b[0]),
.O(\blk00000001/sig0000037e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000076a (
.I0(a[2]),
.I1(b[1]),
.I2(a[3]),
.I3(b[0]),
.O(\blk00000001/sig0000036b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000769 (
.I0(a[3]),
.I1(b[1]),
.I2(a[4]),
.I3(b[0]),
.O(\blk00000001/sig00000358 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000768 (
.I0(a[4]),
.I1(b[1]),
.I2(a[5]),
.I3(b[0]),
.O(\blk00000001/sig00000345 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000767 (
.I0(a[5]),
.I1(b[1]),
.I2(a[6]),
.I3(b[0]),
.O(\blk00000001/sig00000332 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000766 (
.I0(a[6]),
.I1(b[1]),
.I2(a[7]),
.I3(b[0]),
.O(\blk00000001/sig0000031f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000765 (
.I0(a[7]),
.I1(b[1]),
.I2(a[8]),
.I3(b[0]),
.O(\blk00000001/sig0000030c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000764 (
.I0(a[8]),
.I1(b[1]),
.I2(a[9]),
.I3(b[0]),
.O(\blk00000001/sig000002f9 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000763 (
.I0(a[10]),
.I1(b[2]),
.I2(a[9]),
.I3(b[3]),
.O(\blk00000001/sig000002e4 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000762 (
.I0(a[10]),
.I1(b[3]),
.I2(a[11]),
.I3(b[2]),
.O(\blk00000001/sig000002d1 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000761 (
.I0(a[11]),
.I1(b[3]),
.I2(a[12]),
.I3(b[2]),
.O(\blk00000001/sig000002be )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000760 (
.I0(a[12]),
.I1(b[3]),
.I2(a[13]),
.I3(b[2]),
.O(\blk00000001/sig000002ab )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000075f (
.I0(a[13]),
.I1(b[3]),
.I2(a[14]),
.I3(b[2]),
.O(\blk00000001/sig00000298 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000075e (
.I0(a[14]),
.I1(b[3]),
.I2(a[15]),
.I3(b[2]),
.O(\blk00000001/sig00000285 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000075d (
.I0(a[15]),
.I1(b[3]),
.I2(a[16]),
.I3(b[2]),
.O(\blk00000001/sig00000272 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000075c (
.I0(a[16]),
.I1(b[3]),
.I2(a[17]),
.I3(b[2]),
.O(\blk00000001/sig0000025f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000075b (
.I0(a[17]),
.I1(b[3]),
.I2(a[18]),
.I3(b[2]),
.O(\blk00000001/sig0000024c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000075a (
.I0(a[18]),
.I1(b[3]),
.I2(a[19]),
.I3(b[2]),
.O(\blk00000001/sig00000239 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000759 (
.I0(a[0]),
.I1(b[3]),
.I2(a[1]),
.I3(b[2]),
.O(\blk00000001/sig00000397 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000758 (
.I0(a[19]),
.I1(b[3]),
.I2(b[2]),
.O(\blk00000001/sig00000226 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000757 (
.I0(a[19]),
.I1(b[3]),
.I2(b[2]),
.O(\blk00000001/sig00000214 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000756 (
.I0(a[1]),
.I1(b[3]),
.I2(a[2]),
.I3(b[2]),
.O(\blk00000001/sig0000037c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000755 (
.I0(a[2]),
.I1(b[3]),
.I2(a[3]),
.I3(b[2]),
.O(\blk00000001/sig00000369 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000754 (
.I0(a[3]),
.I1(b[3]),
.I2(a[4]),
.I3(b[2]),
.O(\blk00000001/sig00000356 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000753 (
.I0(a[4]),
.I1(b[3]),
.I2(a[5]),
.I3(b[2]),
.O(\blk00000001/sig00000343 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000752 (
.I0(a[5]),
.I1(b[3]),
.I2(a[6]),
.I3(b[2]),
.O(\blk00000001/sig00000330 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000751 (
.I0(a[6]),
.I1(b[3]),
.I2(a[7]),
.I3(b[2]),
.O(\blk00000001/sig0000031d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000750 (
.I0(a[7]),
.I1(b[3]),
.I2(a[8]),
.I3(b[2]),
.O(\blk00000001/sig0000030a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000074f (
.I0(a[8]),
.I1(b[3]),
.I2(a[9]),
.I3(b[2]),
.O(\blk00000001/sig000002f7 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000074e (
.I0(a[10]),
.I1(b[4]),
.I2(a[9]),
.I3(b[5]),
.O(\blk00000001/sig000002e2 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000074d (
.I0(a[10]),
.I1(b[5]),
.I2(a[11]),
.I3(b[4]),
.O(\blk00000001/sig000002cf )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000074c (
.I0(a[11]),
.I1(b[5]),
.I2(a[12]),
.I3(b[4]),
.O(\blk00000001/sig000002bc )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000074b (
.I0(a[12]),
.I1(b[5]),
.I2(a[13]),
.I3(b[4]),
.O(\blk00000001/sig000002a9 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000074a (
.I0(a[13]),
.I1(b[5]),
.I2(a[14]),
.I3(b[4]),
.O(\blk00000001/sig00000296 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000749 (
.I0(a[14]),
.I1(b[5]),
.I2(a[15]),
.I3(b[4]),
.O(\blk00000001/sig00000283 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000748 (
.I0(a[15]),
.I1(b[5]),
.I2(a[16]),
.I3(b[4]),
.O(\blk00000001/sig00000270 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000747 (
.I0(a[16]),
.I1(b[5]),
.I2(a[17]),
.I3(b[4]),
.O(\blk00000001/sig0000025d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000746 (
.I0(a[17]),
.I1(b[5]),
.I2(a[18]),
.I3(b[4]),
.O(\blk00000001/sig0000024a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000745 (
.I0(a[18]),
.I1(b[5]),
.I2(a[19]),
.I3(b[4]),
.O(\blk00000001/sig00000237 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000744 (
.I0(a[0]),
.I1(b[5]),
.I2(a[1]),
.I3(b[4]),
.O(\blk00000001/sig00000394 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000743 (
.I0(a[19]),
.I1(b[5]),
.I2(b[4]),
.O(\blk00000001/sig00000224 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000742 (
.I0(a[19]),
.I1(b[5]),
.I2(b[4]),
.O(\blk00000001/sig00000213 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000741 (
.I0(a[1]),
.I1(b[5]),
.I2(a[2]),
.I3(b[4]),
.O(\blk00000001/sig0000037a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000740 (
.I0(a[2]),
.I1(b[5]),
.I2(a[3]),
.I3(b[4]),
.O(\blk00000001/sig00000367 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000073f (
.I0(a[3]),
.I1(b[5]),
.I2(a[4]),
.I3(b[4]),
.O(\blk00000001/sig00000354 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000073e (
.I0(a[4]),
.I1(b[5]),
.I2(a[5]),
.I3(b[4]),
.O(\blk00000001/sig00000341 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000073d (
.I0(a[5]),
.I1(b[5]),
.I2(a[6]),
.I3(b[4]),
.O(\blk00000001/sig0000032e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000073c (
.I0(a[6]),
.I1(b[5]),
.I2(a[7]),
.I3(b[4]),
.O(\blk00000001/sig0000031b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000073b (
.I0(a[7]),
.I1(b[5]),
.I2(a[8]),
.I3(b[4]),
.O(\blk00000001/sig00000308 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000073a (
.I0(a[8]),
.I1(b[5]),
.I2(a[9]),
.I3(b[4]),
.O(\blk00000001/sig000002f5 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000739 (
.I0(a[10]),
.I1(b[6]),
.I2(a[9]),
.I3(b[7]),
.O(\blk00000001/sig000002e0 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000738 (
.I0(a[10]),
.I1(b[7]),
.I2(a[11]),
.I3(b[6]),
.O(\blk00000001/sig000002cd )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000737 (
.I0(a[11]),
.I1(b[7]),
.I2(a[12]),
.I3(b[6]),
.O(\blk00000001/sig000002ba )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000736 (
.I0(a[12]),
.I1(b[7]),
.I2(a[13]),
.I3(b[6]),
.O(\blk00000001/sig000002a7 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000735 (
.I0(a[13]),
.I1(b[7]),
.I2(a[14]),
.I3(b[6]),
.O(\blk00000001/sig00000294 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000734 (
.I0(a[14]),
.I1(b[7]),
.I2(a[15]),
.I3(b[6]),
.O(\blk00000001/sig00000281 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000733 (
.I0(a[15]),
.I1(b[7]),
.I2(a[16]),
.I3(b[6]),
.O(\blk00000001/sig0000026e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000732 (
.I0(a[16]),
.I1(b[7]),
.I2(a[17]),
.I3(b[6]),
.O(\blk00000001/sig0000025b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000731 (
.I0(a[17]),
.I1(b[7]),
.I2(a[18]),
.I3(b[6]),
.O(\blk00000001/sig00000248 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000730 (
.I0(a[18]),
.I1(b[7]),
.I2(a[19]),
.I3(b[6]),
.O(\blk00000001/sig00000235 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000072f (
.I0(a[0]),
.I1(b[7]),
.I2(a[1]),
.I3(b[6]),
.O(\blk00000001/sig00000391 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk0000072e (
.I0(a[19]),
.I1(b[7]),
.I2(b[6]),
.O(\blk00000001/sig00000222 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk0000072d (
.I0(a[19]),
.I1(b[7]),
.I2(b[6]),
.O(\blk00000001/sig00000212 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000072c (
.I0(a[1]),
.I1(b[7]),
.I2(a[2]),
.I3(b[6]),
.O(\blk00000001/sig00000378 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000072b (
.I0(a[2]),
.I1(b[7]),
.I2(a[3]),
.I3(b[6]),
.O(\blk00000001/sig00000365 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000072a (
.I0(a[3]),
.I1(b[7]),
.I2(a[4]),
.I3(b[6]),
.O(\blk00000001/sig00000352 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000729 (
.I0(a[4]),
.I1(b[7]),
.I2(a[5]),
.I3(b[6]),
.O(\blk00000001/sig0000033f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000728 (
.I0(a[5]),
.I1(b[7]),
.I2(a[6]),
.I3(b[6]),
.O(\blk00000001/sig0000032c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000727 (
.I0(a[6]),
.I1(b[7]),
.I2(a[7]),
.I3(b[6]),
.O(\blk00000001/sig00000319 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000726 (
.I0(a[7]),
.I1(b[7]),
.I2(a[8]),
.I3(b[6]),
.O(\blk00000001/sig00000306 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000725 (
.I0(a[8]),
.I1(b[7]),
.I2(a[9]),
.I3(b[6]),
.O(\blk00000001/sig000002f3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000724 (
.I0(a[10]),
.I1(b[8]),
.I2(a[9]),
.I3(b[9]),
.O(\blk00000001/sig000002de )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000723 (
.I0(a[10]),
.I1(b[9]),
.I2(a[11]),
.I3(b[8]),
.O(\blk00000001/sig000002cb )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000722 (
.I0(a[11]),
.I1(b[9]),
.I2(a[12]),
.I3(b[8]),
.O(\blk00000001/sig000002b8 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000721 (
.I0(a[12]),
.I1(b[9]),
.I2(a[13]),
.I3(b[8]),
.O(\blk00000001/sig000002a5 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000720 (
.I0(a[13]),
.I1(b[9]),
.I2(a[14]),
.I3(b[8]),
.O(\blk00000001/sig00000292 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000071f (
.I0(a[14]),
.I1(b[9]),
.I2(a[15]),
.I3(b[8]),
.O(\blk00000001/sig0000027f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000071e (
.I0(a[15]),
.I1(b[9]),
.I2(a[16]),
.I3(b[8]),
.O(\blk00000001/sig0000026c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000071d (
.I0(a[16]),
.I1(b[9]),
.I2(a[17]),
.I3(b[8]),
.O(\blk00000001/sig00000259 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000071c (
.I0(a[17]),
.I1(b[9]),
.I2(a[18]),
.I3(b[8]),
.O(\blk00000001/sig00000246 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000071b (
.I0(a[18]),
.I1(b[9]),
.I2(a[19]),
.I3(b[8]),
.O(\blk00000001/sig00000233 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000071a (
.I0(a[0]),
.I1(b[9]),
.I2(a[1]),
.I3(b[8]),
.O(\blk00000001/sig0000038e )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000719 (
.I0(a[19]),
.I1(b[9]),
.I2(b[8]),
.O(\blk00000001/sig00000220 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000718 (
.I0(a[19]),
.I1(b[9]),
.I2(b[8]),
.O(\blk00000001/sig00000211 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000717 (
.I0(a[1]),
.I1(b[9]),
.I2(a[2]),
.I3(b[8]),
.O(\blk00000001/sig00000376 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000716 (
.I0(a[2]),
.I1(b[9]),
.I2(a[3]),
.I3(b[8]),
.O(\blk00000001/sig00000363 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000715 (
.I0(a[3]),
.I1(b[9]),
.I2(a[4]),
.I3(b[8]),
.O(\blk00000001/sig00000350 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000714 (
.I0(a[4]),
.I1(b[9]),
.I2(a[5]),
.I3(b[8]),
.O(\blk00000001/sig0000033d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000713 (
.I0(a[5]),
.I1(b[9]),
.I2(a[6]),
.I3(b[8]),
.O(\blk00000001/sig0000032a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000712 (
.I0(a[6]),
.I1(b[9]),
.I2(a[7]),
.I3(b[8]),
.O(\blk00000001/sig00000317 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000711 (
.I0(a[7]),
.I1(b[9]),
.I2(a[8]),
.I3(b[8]),
.O(\blk00000001/sig00000304 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000710 (
.I0(a[8]),
.I1(b[9]),
.I2(a[9]),
.I3(b[8]),
.O(\blk00000001/sig000002f1 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070f (
.I0(a[10]),
.I1(b[10]),
.I2(a[9]),
.I3(b[11]),
.O(\blk00000001/sig000002dc )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070e (
.I0(a[10]),
.I1(b[11]),
.I2(a[11]),
.I3(b[10]),
.O(\blk00000001/sig000002c9 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070d (
.I0(a[11]),
.I1(b[11]),
.I2(a[12]),
.I3(b[10]),
.O(\blk00000001/sig000002b6 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070c (
.I0(a[12]),
.I1(b[11]),
.I2(a[13]),
.I3(b[10]),
.O(\blk00000001/sig000002a3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070b (
.I0(a[13]),
.I1(b[11]),
.I2(a[14]),
.I3(b[10]),
.O(\blk00000001/sig00000290 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk0000070a (
.I0(a[14]),
.I1(b[11]),
.I2(a[15]),
.I3(b[10]),
.O(\blk00000001/sig0000027d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000709 (
.I0(a[15]),
.I1(b[11]),
.I2(a[16]),
.I3(b[10]),
.O(\blk00000001/sig0000026a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000708 (
.I0(a[16]),
.I1(b[11]),
.I2(a[17]),
.I3(b[10]),
.O(\blk00000001/sig00000257 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000707 (
.I0(a[17]),
.I1(b[11]),
.I2(a[18]),
.I3(b[10]),
.O(\blk00000001/sig00000244 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000706 (
.I0(a[18]),
.I1(b[11]),
.I2(a[19]),
.I3(b[10]),
.O(\blk00000001/sig00000231 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000705 (
.I0(a[0]),
.I1(b[11]),
.I2(a[1]),
.I3(b[10]),
.O(\blk00000001/sig0000038b )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000704 (
.I0(a[19]),
.I1(b[11]),
.I2(b[10]),
.O(\blk00000001/sig0000021e )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk00000703 (
.I0(a[19]),
.I1(b[11]),
.I2(b[10]),
.O(\blk00000001/sig00000210 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000702 (
.I0(a[1]),
.I1(b[11]),
.I2(a[2]),
.I3(b[10]),
.O(\blk00000001/sig00000374 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000701 (
.I0(a[2]),
.I1(b[11]),
.I2(a[3]),
.I3(b[10]),
.O(\blk00000001/sig00000361 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk00000700 (
.I0(a[3]),
.I1(b[11]),
.I2(a[4]),
.I3(b[10]),
.O(\blk00000001/sig0000034e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ff (
.I0(a[4]),
.I1(b[11]),
.I2(a[5]),
.I3(b[10]),
.O(\blk00000001/sig0000033b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fe (
.I0(a[5]),
.I1(b[11]),
.I2(a[6]),
.I3(b[10]),
.O(\blk00000001/sig00000328 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fd (
.I0(a[6]),
.I1(b[11]),
.I2(a[7]),
.I3(b[10]),
.O(\blk00000001/sig00000315 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fc (
.I0(a[7]),
.I1(b[11]),
.I2(a[8]),
.I3(b[10]),
.O(\blk00000001/sig00000302 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fb (
.I0(a[8]),
.I1(b[11]),
.I2(a[9]),
.I3(b[10]),
.O(\blk00000001/sig000002ef )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006fa (
.I0(a[10]),
.I1(b[12]),
.I2(a[9]),
.I3(b[13]),
.O(\blk00000001/sig000002da )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f9 (
.I0(a[10]),
.I1(b[13]),
.I2(a[11]),
.I3(b[12]),
.O(\blk00000001/sig000002c7 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f8 (
.I0(a[11]),
.I1(b[13]),
.I2(a[12]),
.I3(b[12]),
.O(\blk00000001/sig000002b4 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f7 (
.I0(a[12]),
.I1(b[13]),
.I2(a[13]),
.I3(b[12]),
.O(\blk00000001/sig000002a1 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f6 (
.I0(a[13]),
.I1(b[13]),
.I2(a[14]),
.I3(b[12]),
.O(\blk00000001/sig0000028e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f5 (
.I0(a[14]),
.I1(b[13]),
.I2(a[15]),
.I3(b[12]),
.O(\blk00000001/sig0000027b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f4 (
.I0(a[15]),
.I1(b[13]),
.I2(a[16]),
.I3(b[12]),
.O(\blk00000001/sig00000268 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f3 (
.I0(a[16]),
.I1(b[13]),
.I2(a[17]),
.I3(b[12]),
.O(\blk00000001/sig00000255 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f2 (
.I0(a[17]),
.I1(b[13]),
.I2(a[18]),
.I3(b[12]),
.O(\blk00000001/sig00000242 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f1 (
.I0(a[18]),
.I1(b[13]),
.I2(a[19]),
.I3(b[12]),
.O(\blk00000001/sig0000022f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006f0 (
.I0(a[0]),
.I1(b[13]),
.I2(a[1]),
.I3(b[12]),
.O(\blk00000001/sig00000388 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006ef (
.I0(a[19]),
.I1(b[13]),
.I2(b[12]),
.O(\blk00000001/sig0000021c )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006ee (
.I0(a[19]),
.I1(b[13]),
.I2(b[12]),
.O(\blk00000001/sig0000020f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ed (
.I0(a[1]),
.I1(b[13]),
.I2(a[2]),
.I3(b[12]),
.O(\blk00000001/sig00000372 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ec (
.I0(a[2]),
.I1(b[13]),
.I2(a[3]),
.I3(b[12]),
.O(\blk00000001/sig0000035f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006eb (
.I0(a[3]),
.I1(b[13]),
.I2(a[4]),
.I3(b[12]),
.O(\blk00000001/sig0000034c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ea (
.I0(a[4]),
.I1(b[13]),
.I2(a[5]),
.I3(b[12]),
.O(\blk00000001/sig00000339 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e9 (
.I0(a[5]),
.I1(b[13]),
.I2(a[6]),
.I3(b[12]),
.O(\blk00000001/sig00000326 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e8 (
.I0(a[6]),
.I1(b[13]),
.I2(a[7]),
.I3(b[12]),
.O(\blk00000001/sig00000313 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e7 (
.I0(a[7]),
.I1(b[13]),
.I2(a[8]),
.I3(b[12]),
.O(\blk00000001/sig00000300 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e6 (
.I0(a[8]),
.I1(b[13]),
.I2(a[9]),
.I3(b[12]),
.O(\blk00000001/sig000002ed )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e5 (
.I0(a[10]),
.I1(b[14]),
.I2(a[9]),
.I3(b[15]),
.O(\blk00000001/sig000002d8 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e4 (
.I0(a[10]),
.I1(b[15]),
.I2(a[11]),
.I3(b[14]),
.O(\blk00000001/sig000002c5 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e3 (
.I0(a[11]),
.I1(b[15]),
.I2(a[12]),
.I3(b[14]),
.O(\blk00000001/sig000002b2 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e2 (
.I0(a[12]),
.I1(b[15]),
.I2(a[13]),
.I3(b[14]),
.O(\blk00000001/sig0000029f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e1 (
.I0(a[13]),
.I1(b[15]),
.I2(a[14]),
.I3(b[14]),
.O(\blk00000001/sig0000028c )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006e0 (
.I0(a[14]),
.I1(b[15]),
.I2(a[15]),
.I3(b[14]),
.O(\blk00000001/sig00000279 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006df (
.I0(a[15]),
.I1(b[15]),
.I2(a[16]),
.I3(b[14]),
.O(\blk00000001/sig00000266 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006de (
.I0(a[16]),
.I1(b[15]),
.I2(a[17]),
.I3(b[14]),
.O(\blk00000001/sig00000253 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006dd (
.I0(a[17]),
.I1(b[15]),
.I2(a[18]),
.I3(b[14]),
.O(\blk00000001/sig00000240 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006dc (
.I0(a[18]),
.I1(b[15]),
.I2(a[19]),
.I3(b[14]),
.O(\blk00000001/sig0000022d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006db (
.I0(a[0]),
.I1(b[15]),
.I2(a[1]),
.I3(b[14]),
.O(\blk00000001/sig00000385 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006da (
.I0(a[19]),
.I1(b[15]),
.I2(b[14]),
.O(\blk00000001/sig0000021a )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006d9 (
.I0(a[19]),
.I1(b[15]),
.I2(b[14]),
.O(\blk00000001/sig0000020e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d8 (
.I0(a[1]),
.I1(b[15]),
.I2(a[2]),
.I3(b[14]),
.O(\blk00000001/sig00000370 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d7 (
.I0(a[2]),
.I1(b[15]),
.I2(a[3]),
.I3(b[14]),
.O(\blk00000001/sig0000035d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d6 (
.I0(a[3]),
.I1(b[15]),
.I2(a[4]),
.I3(b[14]),
.O(\blk00000001/sig0000034a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d5 (
.I0(a[4]),
.I1(b[15]),
.I2(a[5]),
.I3(b[14]),
.O(\blk00000001/sig00000337 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d4 (
.I0(a[5]),
.I1(b[15]),
.I2(a[6]),
.I3(b[14]),
.O(\blk00000001/sig00000324 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d3 (
.I0(a[6]),
.I1(b[15]),
.I2(a[7]),
.I3(b[14]),
.O(\blk00000001/sig00000311 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d2 (
.I0(a[7]),
.I1(b[15]),
.I2(a[8]),
.I3(b[14]),
.O(\blk00000001/sig000002fe )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d1 (
.I0(a[8]),
.I1(b[15]),
.I2(a[9]),
.I3(b[14]),
.O(\blk00000001/sig000002eb )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006d0 (
.I0(a[10]),
.I1(b[16]),
.I2(a[9]),
.I3(b[17]),
.O(\blk00000001/sig000002d6 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cf (
.I0(a[10]),
.I1(b[17]),
.I2(a[11]),
.I3(b[16]),
.O(\blk00000001/sig000002c3 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ce (
.I0(a[11]),
.I1(b[17]),
.I2(a[12]),
.I3(b[16]),
.O(\blk00000001/sig000002b0 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cd (
.I0(a[12]),
.I1(b[17]),
.I2(a[13]),
.I3(b[16]),
.O(\blk00000001/sig0000029d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cc (
.I0(a[13]),
.I1(b[17]),
.I2(a[14]),
.I3(b[16]),
.O(\blk00000001/sig0000028a )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006cb (
.I0(a[14]),
.I1(b[17]),
.I2(a[15]),
.I3(b[16]),
.O(\blk00000001/sig00000277 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006ca (
.I0(a[15]),
.I1(b[17]),
.I2(a[16]),
.I3(b[16]),
.O(\blk00000001/sig00000264 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c9 (
.I0(a[16]),
.I1(b[17]),
.I2(a[17]),
.I3(b[16]),
.O(\blk00000001/sig00000251 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c8 (
.I0(a[17]),
.I1(b[17]),
.I2(a[18]),
.I3(b[16]),
.O(\blk00000001/sig0000023e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c7 (
.I0(a[18]),
.I1(b[17]),
.I2(a[19]),
.I3(b[16]),
.O(\blk00000001/sig0000022b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c6 (
.I0(a[0]),
.I1(b[17]),
.I2(a[1]),
.I3(b[16]),
.O(\blk00000001/sig00000382 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006c5 (
.I0(a[19]),
.I1(b[17]),
.I2(b[16]),
.O(\blk00000001/sig00000218 )
);
LUT3 #(
.INIT ( 8'h28 ))
\blk00000001/blk000006c4 (
.I0(a[19]),
.I1(b[17]),
.I2(b[16]),
.O(\blk00000001/sig0000020d )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c3 (
.I0(a[1]),
.I1(b[17]),
.I2(a[2]),
.I3(b[16]),
.O(\blk00000001/sig0000036e )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c2 (
.I0(a[2]),
.I1(b[17]),
.I2(a[3]),
.I3(b[16]),
.O(\blk00000001/sig0000035b )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c1 (
.I0(a[3]),
.I1(b[17]),
.I2(a[4]),
.I3(b[16]),
.O(\blk00000001/sig00000348 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006c0 (
.I0(a[4]),
.I1(b[17]),
.I2(a[5]),
.I3(b[16]),
.O(\blk00000001/sig00000335 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bf (
.I0(a[5]),
.I1(b[17]),
.I2(a[6]),
.I3(b[16]),
.O(\blk00000001/sig00000322 )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006be (
.I0(a[6]),
.I1(b[17]),
.I2(a[7]),
.I3(b[16]),
.O(\blk00000001/sig0000030f )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bd (
.I0(a[7]),
.I1(b[17]),
.I2(a[8]),
.I3(b[16]),
.O(\blk00000001/sig000002fc )
);
LUT4 #(
.INIT ( 16'h7888 ))
\blk00000001/blk000006bc (
.I0(a[8]),
.I1(b[17]),
.I2(a[9]),
.I3(b[16]),
.O(\blk00000001/sig000002e9 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006bb (
.I0(a[1]),
.I1(b[18]),
.I2(b[19]),
.I3(a[0]),
.O(\blk00000001/sig0000020b )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006ba (
.I0(a[2]),
.I1(b[18]),
.I2(b[19]),
.I3(a[1]),
.O(\blk00000001/sig0000020a )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b9 (
.I0(a[3]),
.I1(b[18]),
.I2(b[19]),
.I3(a[2]),
.O(\blk00000001/sig00000209 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b8 (
.I0(a[4]),
.I1(b[18]),
.I2(b[19]),
.I3(a[3]),
.O(\blk00000001/sig00000208 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b7 (
.I0(a[5]),
.I1(b[18]),
.I2(b[19]),
.I3(a[4]),
.O(\blk00000001/sig00000207 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b6 (
.I0(a[6]),
.I1(b[18]),
.I2(b[19]),
.I3(a[5]),
.O(\blk00000001/sig00000206 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b5 (
.I0(a[7]),
.I1(b[18]),
.I2(b[19]),
.I3(a[6]),
.O(\blk00000001/sig00000205 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b4 (
.I0(a[8]),
.I1(b[18]),
.I2(b[19]),
.I3(a[7]),
.O(\blk00000001/sig00000204 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b3 (
.I0(a[8]),
.I1(b[19]),
.I2(a[9]),
.I3(b[18]),
.O(\blk00000001/sig00000203 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b2 (
.I0(a[9]),
.I1(b[19]),
.I2(a[10]),
.I3(b[18]),
.O(\blk00000001/sig00000202 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b1 (
.I0(a[11]),
.I1(b[18]),
.I2(b[19]),
.I3(a[10]),
.O(\blk00000001/sig00000201 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006b0 (
.I0(a[12]),
.I1(b[18]),
.I2(b[19]),
.I3(a[11]),
.O(\blk00000001/sig00000200 )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006af (
.I0(a[13]),
.I1(b[18]),
.I2(b[19]),
.I3(a[12]),
.O(\blk00000001/sig000001ff )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006ae (
.I0(a[14]),
.I1(b[18]),
.I2(b[19]),
.I3(a[13]),
.O(\blk00000001/sig000001fe )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006ad (
.I0(a[15]),
.I1(b[18]),
.I2(b[19]),
.I3(a[14]),
.O(\blk00000001/sig000001fd )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006ac (
.I0(a[16]),
.I1(b[18]),
.I2(b[19]),
.I3(a[15]),
.O(\blk00000001/sig000001fc )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006ab (
.I0(a[17]),
.I1(b[18]),
.I2(b[19]),
.I3(a[16]),
.O(\blk00000001/sig000001fb )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006aa (
.I0(a[18]),
.I1(b[18]),
.I2(b[19]),
.I3(a[17]),
.O(\blk00000001/sig000001fa )
);
LUT4 #(
.INIT ( 16'h8777 ))
\blk00000001/blk000006a9 (
.I0(b[18]),
.I1(a[19]),
.I2(b[19]),
.I3(a[18]),
.O(\blk00000001/sig000001f9 )
);
LUT3 #(
.INIT ( 8'hD7 ))
\blk00000001/blk000006a8 (
.I0(a[19]),
.I1(b[18]),
.I2(b[19]),
.O(\blk00000001/sig000001f8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000473 ),
.Q(\blk00000001/sig000007be )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000398 ),
.Q(\blk00000001/sig000007bf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000396 ),
.Q(\blk00000001/sig000007c0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037b ),
.Q(\blk00000001/sig000007c1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000368 ),
.Q(\blk00000001/sig000007c2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000355 ),
.Q(\blk00000001/sig000007c3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000342 ),
.Q(\blk00000001/sig000007c4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000006a0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000032f ),
.Q(\blk00000001/sig000007c5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000069f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000031c ),
.Q(\blk00000001/sig000007c6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000069e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000309 ),
.Q(\blk00000001/sig000007c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000069d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f6 ),
.Q(\blk00000001/sig000007c8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000069c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e3 ),
.Q(\blk00000001/sig000007c9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000069b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d0 ),
.Q(\blk00000001/sig000007ca )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000069a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002bd ),
.Q(\blk00000001/sig000007cb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000699 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002aa ),
.Q(\blk00000001/sig000007cc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000698 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000297 ),
.Q(\blk00000001/sig000007cd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000697 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000284 ),
.Q(\blk00000001/sig000007ce )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000696 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000271 ),
.Q(\blk00000001/sig000007cf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000695 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000025e ),
.Q(\blk00000001/sig000007d0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000694 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000024b ),
.Q(\blk00000001/sig000007d1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000693 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000238 ),
.Q(\blk00000001/sig000007d2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000692 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000225 ),
.Q(\blk00000001/sig000007d3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000691 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000393 ),
.Q(\blk00000001/sig000007aa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000690 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000379 ),
.Q(\blk00000001/sig000007ab )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000068f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000366 ),
.Q(\blk00000001/sig000007ac )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000068e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000353 ),
.Q(\blk00000001/sig000007ad )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000068d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000340 ),
.Q(\blk00000001/sig000007ae )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000068c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000032d ),
.Q(\blk00000001/sig000007af )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000068b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000031a ),
.Q(\blk00000001/sig000007b0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000068a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000307 ),
.Q(\blk00000001/sig000007b1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000689 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f4 ),
.Q(\blk00000001/sig000007b2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000688 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e1 ),
.Q(\blk00000001/sig000007b3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000687 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ce ),
.Q(\blk00000001/sig000007b4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000686 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002bb ),
.Q(\blk00000001/sig000007b5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000685 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a8 ),
.Q(\blk00000001/sig000007b6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000684 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000295 ),
.Q(\blk00000001/sig000007b7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000683 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000282 ),
.Q(\blk00000001/sig000007b8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000682 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026f ),
.Q(\blk00000001/sig000007b9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000681 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000025c ),
.Q(\blk00000001/sig000007ba )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000680 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000249 ),
.Q(\blk00000001/sig000007bb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000067f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000236 ),
.Q(\blk00000001/sig000007bc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000067e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000223 ),
.Q(\blk00000001/sig000007bd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000067d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000046d ),
.Q(\blk00000001/sig00000794 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000067c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000392 ),
.Q(\blk00000001/sig00000795 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000067b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000390 ),
.Q(\blk00000001/sig00000796 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000067a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000377 ),
.Q(\blk00000001/sig00000797 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000679 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000364 ),
.Q(\blk00000001/sig00000798 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000678 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000351 ),
.Q(\blk00000001/sig00000799 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000677 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000033e ),
.Q(\blk00000001/sig0000079a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000676 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000032b ),
.Q(\blk00000001/sig0000079b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000675 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000318 ),
.Q(\blk00000001/sig0000079c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000674 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000305 ),
.Q(\blk00000001/sig0000079d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000673 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f2 ),
.Q(\blk00000001/sig0000079e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000672 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002df ),
.Q(\blk00000001/sig0000079f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000671 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002cc ),
.Q(\blk00000001/sig000007a0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000670 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b9 ),
.Q(\blk00000001/sig000007a1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000066f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a6 ),
.Q(\blk00000001/sig000007a2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000066e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000293 ),
.Q(\blk00000001/sig000007a3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000066d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000280 ),
.Q(\blk00000001/sig000007a4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000066c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026d ),
.Q(\blk00000001/sig000007a5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000066b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000025a ),
.Q(\blk00000001/sig000007a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000066a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000247 ),
.Q(\blk00000001/sig000007a7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000669 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000234 ),
.Q(\blk00000001/sig000007a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000668 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000221 ),
.Q(\blk00000001/sig000007a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000667 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000387 ),
.Q(\blk00000001/sig00000756 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000666 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000371 ),
.Q(\blk00000001/sig00000757 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000665 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000035e ),
.Q(\blk00000001/sig00000758 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000664 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000034b ),
.Q(\blk00000001/sig00000759 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000663 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000338 ),
.Q(\blk00000001/sig0000075a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000662 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000325 ),
.Q(\blk00000001/sig0000075b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000661 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000312 ),
.Q(\blk00000001/sig0000075c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000660 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ff ),
.Q(\blk00000001/sig0000075d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000065f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ec ),
.Q(\blk00000001/sig0000075e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000065e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d9 ),
.Q(\blk00000001/sig0000075f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000065d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c6 ),
.Q(\blk00000001/sig00000760 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000065c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b3 ),
.Q(\blk00000001/sig00000761 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000065b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a0 ),
.Q(\blk00000001/sig00000762 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000065a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028d ),
.Q(\blk00000001/sig00000763 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000659 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000027a ),
.Q(\blk00000001/sig00000764 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000658 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000267 ),
.Q(\blk00000001/sig00000765 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000657 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000254 ),
.Q(\blk00000001/sig00000766 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000656 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000241 ),
.Q(\blk00000001/sig00000767 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000655 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000022e ),
.Q(\blk00000001/sig00000768 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000654 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000021b ),
.Q(\blk00000001/sig00000769 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000653 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038d ),
.Q(\blk00000001/sig00000780 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000652 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000375 ),
.Q(\blk00000001/sig00000781 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000651 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000362 ),
.Q(\blk00000001/sig00000782 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000650 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000034f ),
.Q(\blk00000001/sig00000783 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000033c ),
.Q(\blk00000001/sig00000784 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000329 ),
.Q(\blk00000001/sig00000785 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000316 ),
.Q(\blk00000001/sig00000786 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000303 ),
.Q(\blk00000001/sig00000787 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f0 ),
.Q(\blk00000001/sig00000788 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000064a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002dd ),
.Q(\blk00000001/sig00000789 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000649 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ca ),
.Q(\blk00000001/sig0000078a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000648 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b7 ),
.Q(\blk00000001/sig0000078b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000647 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a4 ),
.Q(\blk00000001/sig0000078c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000646 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000291 ),
.Q(\blk00000001/sig0000078d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000645 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000027e ),
.Q(\blk00000001/sig0000078e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000644 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000026b ),
.Q(\blk00000001/sig0000078f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000643 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000258 ),
.Q(\blk00000001/sig00000790 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000642 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000245 ),
.Q(\blk00000001/sig00000791 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000641 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000232 ),
.Q(\blk00000001/sig00000792 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000640 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000021f ),
.Q(\blk00000001/sig00000793 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000467 ),
.Q(\blk00000001/sig0000076a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038c ),
.Q(\blk00000001/sig0000076b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000038a ),
.Q(\blk00000001/sig0000076c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000373 ),
.Q(\blk00000001/sig0000076d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000360 ),
.Q(\blk00000001/sig0000076e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000063a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000034d ),
.Q(\blk00000001/sig0000076f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000639 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000033a ),
.Q(\blk00000001/sig00000770 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000638 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000327 ),
.Q(\blk00000001/sig00000771 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000637 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000314 ),
.Q(\blk00000001/sig00000772 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000636 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000301 ),
.Q(\blk00000001/sig00000773 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000635 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ee ),
.Q(\blk00000001/sig00000774 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000634 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002db ),
.Q(\blk00000001/sig00000775 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000633 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c8 ),
.Q(\blk00000001/sig00000776 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000632 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b5 ),
.Q(\blk00000001/sig00000777 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000631 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002a2 ),
.Q(\blk00000001/sig00000778 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000630 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028f ),
.Q(\blk00000001/sig00000779 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000027c ),
.Q(\blk00000001/sig0000077a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000269 ),
.Q(\blk00000001/sig0000077b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000256 ),
.Q(\blk00000001/sig0000077c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000243 ),
.Q(\blk00000001/sig0000077d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000230 ),
.Q(\blk00000001/sig0000077e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000062a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000021d ),
.Q(\blk00000001/sig0000077f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000629 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000461 ),
.Q(\blk00000001/sig00000740 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000628 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000386 ),
.Q(\blk00000001/sig00000741 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000627 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000384 ),
.Q(\blk00000001/sig00000742 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000626 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036f ),
.Q(\blk00000001/sig00000743 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000625 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000035c ),
.Q(\blk00000001/sig00000744 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000624 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000349 ),
.Q(\blk00000001/sig00000745 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000623 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000336 ),
.Q(\blk00000001/sig00000746 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000622 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000323 ),
.Q(\blk00000001/sig00000747 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000621 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000310 ),
.Q(\blk00000001/sig00000748 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000620 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002fd ),
.Q(\blk00000001/sig00000749 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ea ),
.Q(\blk00000001/sig0000074a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d7 ),
.Q(\blk00000001/sig0000074b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c4 ),
.Q(\blk00000001/sig0000074c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002b1 ),
.Q(\blk00000001/sig0000074d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000029e ),
.Q(\blk00000001/sig0000074e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000061a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000028b ),
.Q(\blk00000001/sig0000074f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000619 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000278 ),
.Q(\blk00000001/sig00000750 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000618 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000265 ),
.Q(\blk00000001/sig00000751 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000617 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000252 ),
.Q(\blk00000001/sig00000752 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000616 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023f ),
.Q(\blk00000001/sig00000753 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000615 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000022c ),
.Q(\blk00000001/sig00000754 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000614 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000219 ),
.Q(\blk00000001/sig00000755 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000613 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000381 ),
.Q(\blk00000001/sig0000072c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000612 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036d ),
.Q(\blk00000001/sig0000072d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000611 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000035a ),
.Q(\blk00000001/sig0000072e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000610 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000347 ),
.Q(\blk00000001/sig0000072f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000334 ),
.Q(\blk00000001/sig00000730 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000321 ),
.Q(\blk00000001/sig00000731 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000030e ),
.Q(\blk00000001/sig00000732 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002fb ),
.Q(\blk00000001/sig00000733 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e8 ),
.Q(\blk00000001/sig00000734 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000060a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d5 ),
.Q(\blk00000001/sig00000735 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000609 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c2 ),
.Q(\blk00000001/sig00000736 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000608 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002af ),
.Q(\blk00000001/sig00000737 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000607 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000029c ),
.Q(\blk00000001/sig00000738 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000606 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000289 ),
.Q(\blk00000001/sig00000739 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000605 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000276 ),
.Q(\blk00000001/sig0000073a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000604 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000263 ),
.Q(\blk00000001/sig0000073b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000603 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000250 ),
.Q(\blk00000001/sig0000073c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000602 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023d ),
.Q(\blk00000001/sig0000073d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000601 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000022a ),
.Q(\blk00000001/sig0000073e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000600 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000217 ),
.Q(\blk00000001/sig0000073f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ff (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000380 ),
.Q(\blk00000001/sig00000716 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fe (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037f ),
.Q(\blk00000001/sig00000717 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036c ),
.Q(\blk00000001/sig00000718 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000359 ),
.Q(\blk00000001/sig00000719 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000346 ),
.Q(\blk00000001/sig0000071a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005fa (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000333 ),
.Q(\blk00000001/sig0000071b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000320 ),
.Q(\blk00000001/sig0000071c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000030d ),
.Q(\blk00000001/sig0000071d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002fa ),
.Q(\blk00000001/sig0000071e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e7 ),
.Q(\blk00000001/sig0000071f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d4 ),
.Q(\blk00000001/sig00000720 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002c1 ),
.Q(\blk00000001/sig00000721 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ae ),
.Q(\blk00000001/sig00000722 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000029b ),
.Q(\blk00000001/sig00000723 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000288 ),
.Q(\blk00000001/sig00000724 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005f0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000275 ),
.Q(\blk00000001/sig00000725 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ef (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000262 ),
.Q(\blk00000001/sig00000726 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ee (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000024f ),
.Q(\blk00000001/sig00000727 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ed (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023c ),
.Q(\blk00000001/sig00000728 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ec (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000229 ),
.Q(\blk00000001/sig00000729 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005eb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000216 ),
.Q(\blk00000001/sig0000072a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ea (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000020c ),
.Q(\blk00000001/sig0000072b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000399 ),
.Q(\blk00000001/sig00000629 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000037d ),
.Q(\blk00000001/sig0000062a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000036a ),
.Q(\blk00000001/sig0000062b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000357 ),
.Q(\blk00000001/sig0000062c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000344 ),
.Q(\blk00000001/sig0000062d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000331 ),
.Q(\blk00000001/sig0000062e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000031e ),
.Q(\blk00000001/sig0000062f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000030b ),
.Q(\blk00000001/sig00000630 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002f8 ),
.Q(\blk00000001/sig00000631 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005e0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002e5 ),
.Q(\blk00000001/sig00000632 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005df (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002d2 ),
.Q(\blk00000001/sig00000633 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005de (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002bf ),
.Q(\blk00000001/sig00000634 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005dd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000002ac ),
.Q(\blk00000001/sig00000635 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005dc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000299 ),
.Q(\blk00000001/sig00000636 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005db (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000286 ),
.Q(\blk00000001/sig00000637 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005da (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000273 ),
.Q(\blk00000001/sig00000638 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000260 ),
.Q(\blk00000001/sig00000639 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000024d ),
.Q(\blk00000001/sig0000063a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000023a ),
.Q(\blk00000001/sig0000063b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000227 ),
.Q(\blk00000001/sig0000063c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000614 ),
.Q(\blk00000001/sig00000701 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000615 ),
.Q(\blk00000001/sig00000702 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000616 ),
.Q(\blk00000001/sig00000703 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000617 ),
.Q(\blk00000001/sig00000704 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000618 ),
.Q(\blk00000001/sig00000705 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005d0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000619 ),
.Q(\blk00000001/sig00000706 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000061a ),
.Q(\blk00000001/sig00000707 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ce (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000061b ),
.Q(\blk00000001/sig00000708 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000061c ),
.Q(\blk00000001/sig00000709 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000061d ),
.Q(\blk00000001/sig0000070a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005cb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000061e ),
.Q(\blk00000001/sig0000070b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ca (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000061f ),
.Q(\blk00000001/sig0000070c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000620 ),
.Q(\blk00000001/sig0000070d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000621 ),
.Q(\blk00000001/sig0000070e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000622 ),
.Q(\blk00000001/sig0000070f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000623 ),
.Q(\blk00000001/sig00000710 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000624 ),
.Q(\blk00000001/sig00000711 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000625 ),
.Q(\blk00000001/sig00000712 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000626 ),
.Q(\blk00000001/sig00000713 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000627 ),
.Q(\blk00000001/sig00000714 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000628 ),
.Q(\blk00000001/sig00000715 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005c0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d1 ),
.Q(\blk00000001/sig000006be )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bf (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d2 ),
.Q(\blk00000001/sig000006bf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005be (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d3 ),
.Q(\blk00000001/sig000006c0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d4 ),
.Q(\blk00000001/sig000006c1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bc (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d5 ),
.Q(\blk00000001/sig000006c2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005bb (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d6 ),
.Q(\blk00000001/sig000006c3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ba (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d7 ),
.Q(\blk00000001/sig000006c4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d8 ),
.Q(\blk00000001/sig000006c5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d9 ),
.Q(\blk00000001/sig000006c6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005da ),
.Q(\blk00000001/sig000006c7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005db ),
.Q(\blk00000001/sig000006c8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005dc ),
.Q(\blk00000001/sig000006c9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005dd ),
.Q(\blk00000001/sig000006ca )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005de ),
.Q(\blk00000001/sig000006cb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005df ),
.Q(\blk00000001/sig000006cc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e0 ),
.Q(\blk00000001/sig000006cd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005b0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e1 ),
.Q(\blk00000001/sig000006ce )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005af (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e2 ),
.Q(\blk00000001/sig000006cf )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ae (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e3 ),
.Q(\blk00000001/sig000006d0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ad (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e4 ),
.Q(\blk00000001/sig000006d1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ac (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e5 ),
.Q(\blk00000001/sig000006d2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005ab (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e6 ),
.Q(\blk00000001/sig000006d3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005aa (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005fd ),
.Q(\blk00000001/sig000006eb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a9 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005fe ),
.Q(\blk00000001/sig000006ec )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a8 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ff ),
.Q(\blk00000001/sig000006ed )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a7 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000600 ),
.Q(\blk00000001/sig000006ee )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a6 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000601 ),
.Q(\blk00000001/sig000006ef )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a5 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000602 ),
.Q(\blk00000001/sig000006f0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a4 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000603 ),
.Q(\blk00000001/sig000006f1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a3 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000604 ),
.Q(\blk00000001/sig000006f2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a2 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000605 ),
.Q(\blk00000001/sig000006f3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a1 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000606 ),
.Q(\blk00000001/sig000006f4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000005a0 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000607 ),
.Q(\blk00000001/sig000006f5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000608 ),
.Q(\blk00000001/sig000006f6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000609 ),
.Q(\blk00000001/sig000006f7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000060a ),
.Q(\blk00000001/sig000006f8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000060b ),
.Q(\blk00000001/sig000006f9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000060c ),
.Q(\blk00000001/sig000006fa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000059a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000060d ),
.Q(\blk00000001/sig000006fb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000599 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000060e ),
.Q(\blk00000001/sig000006fc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000598 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000060f ),
.Q(\blk00000001/sig000006fd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000597 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000610 ),
.Q(\blk00000001/sig000006fe )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000596 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000611 ),
.Q(\blk00000001/sig000006ff )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000595 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000612 ),
.Q(\blk00000001/sig00000700 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000594 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e8 ),
.Q(\blk00000001/sig000006d4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000593 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005e9 ),
.Q(\blk00000001/sig000006d5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000592 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ea ),
.Q(\blk00000001/sig000006d6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000591 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005eb ),
.Q(\blk00000001/sig000006d7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000590 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ec ),
.Q(\blk00000001/sig000006d8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ed ),
.Q(\blk00000001/sig000006d9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ee ),
.Q(\blk00000001/sig000006da )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ef ),
.Q(\blk00000001/sig000006db )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f0 ),
.Q(\blk00000001/sig000006dc )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f1 ),
.Q(\blk00000001/sig000006dd )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000058a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f2 ),
.Q(\blk00000001/sig000006de )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000589 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f3 ),
.Q(\blk00000001/sig000006df )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000588 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f4 ),
.Q(\blk00000001/sig000006e0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000587 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f5 ),
.Q(\blk00000001/sig000006e1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000586 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f6 ),
.Q(\blk00000001/sig000006e2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000585 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f7 ),
.Q(\blk00000001/sig000006e3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000584 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f8 ),
.Q(\blk00000001/sig000006e4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000583 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005f9 ),
.Q(\blk00000001/sig000006e5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000582 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005fa ),
.Q(\blk00000001/sig000006e6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000581 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005fb ),
.Q(\blk00000001/sig000006e7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000580 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005fc ),
.Q(\blk00000001/sig000006e8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bc ),
.Q(\blk00000001/sig000006a7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bd ),
.Q(\blk00000001/sig000006a8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005be ),
.Q(\blk00000001/sig000006a9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005bf ),
.Q(\blk00000001/sig000006aa )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c0 ),
.Q(\blk00000001/sig000006ab )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000057a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c1 ),
.Q(\blk00000001/sig000006ac )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000579 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c2 ),
.Q(\blk00000001/sig000006ad )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000578 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c3 ),
.Q(\blk00000001/sig000006ae )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000577 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c4 ),
.Q(\blk00000001/sig000006af )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000576 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c5 ),
.Q(\blk00000001/sig000006b0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000575 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c6 ),
.Q(\blk00000001/sig000006b1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000574 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c7 ),
.Q(\blk00000001/sig000006b2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000573 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c8 ),
.Q(\blk00000001/sig000006b3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000572 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005c9 ),
.Q(\blk00000001/sig000006b4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000571 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ca ),
.Q(\blk00000001/sig000006b5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000570 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cb ),
.Q(\blk00000001/sig000006b6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cc ),
.Q(\blk00000001/sig000006b7 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cd ),
.Q(\blk00000001/sig000006b8 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ce ),
.Q(\blk00000001/sig000006b9 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005cf ),
.Q(\blk00000001/sig000006ba )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005d0 ),
.Q(\blk00000001/sig000006bb )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000056a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a3 ),
.Q(\blk00000001/sig0000068f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000569 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a4 ),
.Q(\blk00000001/sig00000690 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000568 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a5 ),
.Q(\blk00000001/sig00000691 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000567 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a6 ),
.Q(\blk00000001/sig00000692 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000566 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a7 ),
.Q(\blk00000001/sig00000693 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000565 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a8 ),
.Q(\blk00000001/sig00000694 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000564 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a9 ),
.Q(\blk00000001/sig00000695 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000563 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005aa ),
.Q(\blk00000001/sig00000696 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000562 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ab ),
.Q(\blk00000001/sig00000697 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000561 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ac ),
.Q(\blk00000001/sig00000698 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000560 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ad ),
.Q(\blk00000001/sig00000699 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ae ),
.Q(\blk00000001/sig0000069a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005af ),
.Q(\blk00000001/sig0000069b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b0 ),
.Q(\blk00000001/sig0000069c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b1 ),
.Q(\blk00000001/sig0000069d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b2 ),
.Q(\blk00000001/sig0000069e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000055a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b3 ),
.Q(\blk00000001/sig0000069f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000559 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b4 ),
.Q(\blk00000001/sig000006a0 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000558 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b5 ),
.Q(\blk00000001/sig000006a1 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000557 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b6 ),
.Q(\blk00000001/sig000006a2 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000556 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b7 ),
.Q(\blk00000001/sig000006a3 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000555 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b8 ),
.Q(\blk00000001/sig000006a4 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000554 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005b9 ),
.Q(\blk00000001/sig000006a5 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000553 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005ba ),
.Q(\blk00000001/sig000006a6 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000552 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000006d4 ),
.Q(\blk00000001/sig00000675 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000551 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000589 ),
.Q(\blk00000001/sig00000676 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000550 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058a ),
.Q(\blk00000001/sig00000677 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058b ),
.Q(\blk00000001/sig00000678 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058c ),
.Q(\blk00000001/sig00000679 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058d ),
.Q(\blk00000001/sig0000067a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058e ),
.Q(\blk00000001/sig0000067b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000058f ),
.Q(\blk00000001/sig0000067c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000054a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000590 ),
.Q(\blk00000001/sig0000067d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000549 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000591 ),
.Q(\blk00000001/sig0000067e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000548 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000592 ),
.Q(\blk00000001/sig0000067f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000547 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000593 ),
.Q(\blk00000001/sig00000680 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000546 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000594 ),
.Q(\blk00000001/sig00000681 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000545 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000595 ),
.Q(\blk00000001/sig00000682 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000544 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000596 ),
.Q(\blk00000001/sig00000683 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000543 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000597 ),
.Q(\blk00000001/sig00000684 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000542 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000598 ),
.Q(\blk00000001/sig00000685 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000541 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000599 ),
.Q(\blk00000001/sig00000686 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000540 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059a ),
.Q(\blk00000001/sig00000687 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059b ),
.Q(\blk00000001/sig00000688 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059c ),
.Q(\blk00000001/sig00000689 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059d ),
.Q(\blk00000001/sig0000068a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059e ),
.Q(\blk00000001/sig0000068b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000059f ),
.Q(\blk00000001/sig0000068c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000053a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a0 ),
.Q(\blk00000001/sig0000068d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000539 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig000005a1 ),
.Q(\blk00000001/sig0000068e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000538 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056c ),
.Q(\blk00000001/sig00000655 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000537 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056d ),
.Q(\blk00000001/sig00000656 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000536 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056e ),
.Q(\blk00000001/sig00000657 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000535 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056f ),
.Q(\blk00000001/sig00000658 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000534 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000570 ),
.Q(\blk00000001/sig00000659 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000533 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000571 ),
.Q(\blk00000001/sig0000065a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000532 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000572 ),
.Q(\blk00000001/sig0000065b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000531 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000573 ),
.Q(\blk00000001/sig0000065c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000530 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000574 ),
.Q(\blk00000001/sig0000065d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000575 ),
.Q(\blk00000001/sig0000065e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000576 ),
.Q(\blk00000001/sig0000065f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000577 ),
.Q(\blk00000001/sig00000660 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000578 ),
.Q(\blk00000001/sig00000661 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000579 ),
.Q(\blk00000001/sig00000662 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000052a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057a ),
.Q(\blk00000001/sig00000663 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000529 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057b ),
.Q(\blk00000001/sig00000664 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000528 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057c ),
.Q(\blk00000001/sig00000665 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000527 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057d ),
.Q(\blk00000001/sig00000666 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000526 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057e ),
.Q(\blk00000001/sig00000667 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000525 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000057f ),
.Q(\blk00000001/sig00000668 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000524 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000580 ),
.Q(\blk00000001/sig00000669 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000523 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000581 ),
.Q(\blk00000001/sig0000066a )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000522 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000582 ),
.Q(\blk00000001/sig0000066b )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000521 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000583 ),
.Q(\blk00000001/sig0000066c )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000520 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000584 ),
.Q(\blk00000001/sig0000066d )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000585 ),
.Q(\blk00000001/sig0000066e )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000586 ),
.Q(\blk00000001/sig0000066f )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000587 ),
.Q(\blk00000001/sig00000670 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000588 ),
.Q(\blk00000001/sig00000671 )
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000655 ),
.Q(p[9])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000051a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000656 ),
.Q(p[10])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000519 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000657 ),
.Q(p[11])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000518 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000658 ),
.Q(p[12])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000517 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000659 ),
.Q(p[13])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000516 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000065a ),
.Q(p[14])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000515 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000065b ),
.Q(p[15])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000514 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000553 ),
.Q(p[16])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000513 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000554 ),
.Q(p[17])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000512 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000555 ),
.Q(p[18])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000511 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000556 ),
.Q(p[19])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000510 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000557 ),
.Q(p[20])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050f (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000558 ),
.Q(p[21])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050e (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000559 ),
.Q(p[22])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050d (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000055a ),
.Q(p[23])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050c (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000055b ),
.Q(p[24])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050b (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000055c ),
.Q(p[25])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk0000050a (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000055d ),
.Q(p[26])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000509 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000055e ),
.Q(p[27])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000508 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000055f ),
.Q(p[28])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000507 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000560 ),
.Q(p[29])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000506 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000561 ),
.Q(p[30])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000505 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000562 ),
.Q(p[31])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000504 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000563 ),
.Q(p[32])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000503 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000564 ),
.Q(p[33])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000502 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000565 ),
.Q(p[34])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000501 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000566 ),
.Q(p[35])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk00000500 (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000567 ),
.Q(p[36])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004ff (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000568 ),
.Q(p[37])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fe (
.C(clk),
.CE(ce),
.D(\blk00000001/sig00000569 ),
.Q(p[38])
);
FDE #(
.INIT ( 1'b0 ))
\blk00000001/blk000004fd (
.C(clk),
.CE(ce),
.D(\blk00000001/sig0000056a ),
.Q(p[39])
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004fc (
.I0(\blk00000001/sig00000629 ),
.I1(\blk00000001/sig000007be ),
.O(\blk00000001/sig000001f7 )
);
MUXCY \blk00000001/blk000004fb (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig00000629 ),
.S(\blk00000001/sig000001f7 ),
.O(\blk00000001/sig000001f6 )
);
XORCY \blk00000001/blk000004fa (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig000001f7 ),
.O(\blk00000001/sig00000613 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004f9 (
.I0(\blk00000001/sig0000062a ),
.I1(\blk00000001/sig000007bf ),
.O(\blk00000001/sig000001f5 )
);
MUXCY \blk00000001/blk000004f8 (
.CI(\blk00000001/sig000001f6 ),
.DI(\blk00000001/sig0000062a ),
.S(\blk00000001/sig000001f5 ),
.O(\blk00000001/sig000001f4 )
);
XORCY \blk00000001/blk000004f7 (
.CI(\blk00000001/sig000001f6 ),
.LI(\blk00000001/sig000001f5 ),
.O(\blk00000001/sig00000614 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004f6 (
.I0(\blk00000001/sig0000062b ),
.I1(\blk00000001/sig000007c0 ),
.O(\blk00000001/sig000001f3 )
);
MUXCY \blk00000001/blk000004f5 (
.CI(\blk00000001/sig000001f4 ),
.DI(\blk00000001/sig0000062b ),
.S(\blk00000001/sig000001f3 ),
.O(\blk00000001/sig000001f2 )
);
XORCY \blk00000001/blk000004f4 (
.CI(\blk00000001/sig000001f4 ),
.LI(\blk00000001/sig000001f3 ),
.O(\blk00000001/sig00000615 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004f3 (
.I0(\blk00000001/sig0000062c ),
.I1(\blk00000001/sig000007c1 ),
.O(\blk00000001/sig000001f1 )
);
MUXCY \blk00000001/blk000004f2 (
.CI(\blk00000001/sig000001f2 ),
.DI(\blk00000001/sig0000062c ),
.S(\blk00000001/sig000001f1 ),
.O(\blk00000001/sig000001f0 )
);
XORCY \blk00000001/blk000004f1 (
.CI(\blk00000001/sig000001f2 ),
.LI(\blk00000001/sig000001f1 ),
.O(\blk00000001/sig00000616 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004f0 (
.I0(\blk00000001/sig0000062d ),
.I1(\blk00000001/sig000007c2 ),
.O(\blk00000001/sig000001ef )
);
MUXCY \blk00000001/blk000004ef (
.CI(\blk00000001/sig000001f0 ),
.DI(\blk00000001/sig0000062d ),
.S(\blk00000001/sig000001ef ),
.O(\blk00000001/sig000001ee )
);
XORCY \blk00000001/blk000004ee (
.CI(\blk00000001/sig000001f0 ),
.LI(\blk00000001/sig000001ef ),
.O(\blk00000001/sig00000617 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004ed (
.I0(\blk00000001/sig0000062e ),
.I1(\blk00000001/sig000007c3 ),
.O(\blk00000001/sig000001ed )
);
MUXCY \blk00000001/blk000004ec (
.CI(\blk00000001/sig000001ee ),
.DI(\blk00000001/sig0000062e ),
.S(\blk00000001/sig000001ed ),
.O(\blk00000001/sig000001ec )
);
XORCY \blk00000001/blk000004eb (
.CI(\blk00000001/sig000001ee ),
.LI(\blk00000001/sig000001ed ),
.O(\blk00000001/sig00000618 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004ea (
.I0(\blk00000001/sig0000062f ),
.I1(\blk00000001/sig000007c4 ),
.O(\blk00000001/sig000001eb )
);
MUXCY \blk00000001/blk000004e9 (
.CI(\blk00000001/sig000001ec ),
.DI(\blk00000001/sig0000062f ),
.S(\blk00000001/sig000001eb ),
.O(\blk00000001/sig000001ea )
);
XORCY \blk00000001/blk000004e8 (
.CI(\blk00000001/sig000001ec ),
.LI(\blk00000001/sig000001eb ),
.O(\blk00000001/sig00000619 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004e7 (
.I0(\blk00000001/sig00000630 ),
.I1(\blk00000001/sig000007c5 ),
.O(\blk00000001/sig000001e9 )
);
MUXCY \blk00000001/blk000004e6 (
.CI(\blk00000001/sig000001ea ),
.DI(\blk00000001/sig00000630 ),
.S(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig000001e8 )
);
XORCY \blk00000001/blk000004e5 (
.CI(\blk00000001/sig000001ea ),
.LI(\blk00000001/sig000001e9 ),
.O(\blk00000001/sig0000061a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004e4 (
.I0(\blk00000001/sig00000631 ),
.I1(\blk00000001/sig000007c6 ),
.O(\blk00000001/sig000001e7 )
);
MUXCY \blk00000001/blk000004e3 (
.CI(\blk00000001/sig000001e8 ),
.DI(\blk00000001/sig00000631 ),
.S(\blk00000001/sig000001e7 ),
.O(\blk00000001/sig000001e6 )
);
XORCY \blk00000001/blk000004e2 (
.CI(\blk00000001/sig000001e8 ),
.LI(\blk00000001/sig000001e7 ),
.O(\blk00000001/sig0000061b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004e1 (
.I0(\blk00000001/sig00000632 ),
.I1(\blk00000001/sig000007c7 ),
.O(\blk00000001/sig000001e5 )
);
MUXCY \blk00000001/blk000004e0 (
.CI(\blk00000001/sig000001e6 ),
.DI(\blk00000001/sig00000632 ),
.S(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig000001e4 )
);
XORCY \blk00000001/blk000004df (
.CI(\blk00000001/sig000001e6 ),
.LI(\blk00000001/sig000001e5 ),
.O(\blk00000001/sig0000061c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004de (
.I0(\blk00000001/sig00000633 ),
.I1(\blk00000001/sig000007c8 ),
.O(\blk00000001/sig000001e3 )
);
MUXCY \blk00000001/blk000004dd (
.CI(\blk00000001/sig000001e4 ),
.DI(\blk00000001/sig00000633 ),
.S(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig000001e2 )
);
XORCY \blk00000001/blk000004dc (
.CI(\blk00000001/sig000001e4 ),
.LI(\blk00000001/sig000001e3 ),
.O(\blk00000001/sig0000061d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004db (
.I0(\blk00000001/sig00000634 ),
.I1(\blk00000001/sig000007c9 ),
.O(\blk00000001/sig000001e1 )
);
MUXCY \blk00000001/blk000004da (
.CI(\blk00000001/sig000001e2 ),
.DI(\blk00000001/sig00000634 ),
.S(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig000001e0 )
);
XORCY \blk00000001/blk000004d9 (
.CI(\blk00000001/sig000001e2 ),
.LI(\blk00000001/sig000001e1 ),
.O(\blk00000001/sig0000061e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004d8 (
.I0(\blk00000001/sig00000635 ),
.I1(\blk00000001/sig000007ca ),
.O(\blk00000001/sig000001df )
);
MUXCY \blk00000001/blk000004d7 (
.CI(\blk00000001/sig000001e0 ),
.DI(\blk00000001/sig00000635 ),
.S(\blk00000001/sig000001df ),
.O(\blk00000001/sig000001de )
);
XORCY \blk00000001/blk000004d6 (
.CI(\blk00000001/sig000001e0 ),
.LI(\blk00000001/sig000001df ),
.O(\blk00000001/sig0000061f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004d5 (
.I0(\blk00000001/sig00000636 ),
.I1(\blk00000001/sig000007cb ),
.O(\blk00000001/sig000001dd )
);
MUXCY \blk00000001/blk000004d4 (
.CI(\blk00000001/sig000001de ),
.DI(\blk00000001/sig00000636 ),
.S(\blk00000001/sig000001dd ),
.O(\blk00000001/sig000001dc )
);
XORCY \blk00000001/blk000004d3 (
.CI(\blk00000001/sig000001de ),
.LI(\blk00000001/sig000001dd ),
.O(\blk00000001/sig00000620 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004d2 (
.I0(\blk00000001/sig00000637 ),
.I1(\blk00000001/sig000007cc ),
.O(\blk00000001/sig000001db )
);
MUXCY \blk00000001/blk000004d1 (
.CI(\blk00000001/sig000001dc ),
.DI(\blk00000001/sig00000637 ),
.S(\blk00000001/sig000001db ),
.O(\blk00000001/sig000001da )
);
XORCY \blk00000001/blk000004d0 (
.CI(\blk00000001/sig000001dc ),
.LI(\blk00000001/sig000001db ),
.O(\blk00000001/sig00000621 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004cf (
.I0(\blk00000001/sig00000638 ),
.I1(\blk00000001/sig000007cd ),
.O(\blk00000001/sig000001d9 )
);
MUXCY \blk00000001/blk000004ce (
.CI(\blk00000001/sig000001da ),
.DI(\blk00000001/sig00000638 ),
.S(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig000001d8 )
);
XORCY \blk00000001/blk000004cd (
.CI(\blk00000001/sig000001da ),
.LI(\blk00000001/sig000001d9 ),
.O(\blk00000001/sig00000622 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004cc (
.I0(\blk00000001/sig00000639 ),
.I1(\blk00000001/sig000007ce ),
.O(\blk00000001/sig000001d7 )
);
MUXCY \blk00000001/blk000004cb (
.CI(\blk00000001/sig000001d8 ),
.DI(\blk00000001/sig00000639 ),
.S(\blk00000001/sig000001d7 ),
.O(\blk00000001/sig000001d6 )
);
XORCY \blk00000001/blk000004ca (
.CI(\blk00000001/sig000001d8 ),
.LI(\blk00000001/sig000001d7 ),
.O(\blk00000001/sig00000623 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004c9 (
.I0(\blk00000001/sig0000063a ),
.I1(\blk00000001/sig000007cf ),
.O(\blk00000001/sig000001d5 )
);
MUXCY \blk00000001/blk000004c8 (
.CI(\blk00000001/sig000001d6 ),
.DI(\blk00000001/sig0000063a ),
.S(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig000001d4 )
);
XORCY \blk00000001/blk000004c7 (
.CI(\blk00000001/sig000001d6 ),
.LI(\blk00000001/sig000001d5 ),
.O(\blk00000001/sig00000624 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004c6 (
.I0(\blk00000001/sig0000063b ),
.I1(\blk00000001/sig000007d0 ),
.O(\blk00000001/sig000001d3 )
);
MUXCY \blk00000001/blk000004c5 (
.CI(\blk00000001/sig000001d4 ),
.DI(\blk00000001/sig0000063b ),
.S(\blk00000001/sig000001d3 ),
.O(\blk00000001/sig000001d2 )
);
XORCY \blk00000001/blk000004c4 (
.CI(\blk00000001/sig000001d4 ),
.LI(\blk00000001/sig000001d3 ),
.O(\blk00000001/sig00000625 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004c3 (
.I0(\blk00000001/sig0000063c ),
.I1(\blk00000001/sig000007d1 ),
.O(\blk00000001/sig000001d1 )
);
MUXCY \blk00000001/blk000004c2 (
.CI(\blk00000001/sig000001d2 ),
.DI(\blk00000001/sig0000063c ),
.S(\blk00000001/sig000001d1 ),
.O(\blk00000001/sig000001d0 )
);
XORCY \blk00000001/blk000004c1 (
.CI(\blk00000001/sig000001d2 ),
.LI(\blk00000001/sig000001d1 ),
.O(\blk00000001/sig00000626 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004c0 (
.I0(\blk00000001/sig0000063c ),
.I1(\blk00000001/sig000007d2 ),
.O(\blk00000001/sig000001cf )
);
MUXCY \blk00000001/blk000004bf (
.CI(\blk00000001/sig000001d0 ),
.DI(\blk00000001/sig0000063c ),
.S(\blk00000001/sig000001cf ),
.O(\blk00000001/sig000001ce )
);
XORCY \blk00000001/blk000004be (
.CI(\blk00000001/sig000001d0 ),
.LI(\blk00000001/sig000001cf ),
.O(\blk00000001/sig00000627 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004bd (
.I0(\blk00000001/sig0000063c ),
.I1(\blk00000001/sig000007d3 ),
.O(\blk00000001/sig000001cd )
);
XORCY \blk00000001/blk000004bc (
.CI(\blk00000001/sig000001ce ),
.LI(\blk00000001/sig000001cd ),
.O(\blk00000001/sig00000628 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004bb (
.I0(\blk00000001/sig000007aa ),
.I1(\blk00000001/sig00000794 ),
.O(\blk00000001/sig000001cc )
);
MUXCY \blk00000001/blk000004ba (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig000007aa ),
.S(\blk00000001/sig000001cc ),
.O(\blk00000001/sig000001cb )
);
XORCY \blk00000001/blk000004b9 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig000001cc ),
.O(\blk00000001/sig000005fd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004b8 (
.I0(\blk00000001/sig000007ab ),
.I1(\blk00000001/sig00000795 ),
.O(\blk00000001/sig000001ca )
);
MUXCY \blk00000001/blk000004b7 (
.CI(\blk00000001/sig000001cb ),
.DI(\blk00000001/sig000007ab ),
.S(\blk00000001/sig000001ca ),
.O(\blk00000001/sig000001c9 )
);
XORCY \blk00000001/blk000004b6 (
.CI(\blk00000001/sig000001cb ),
.LI(\blk00000001/sig000001ca ),
.O(\blk00000001/sig000005fe )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004b5 (
.I0(\blk00000001/sig000007ac ),
.I1(\blk00000001/sig00000796 ),
.O(\blk00000001/sig000001c8 )
);
MUXCY \blk00000001/blk000004b4 (
.CI(\blk00000001/sig000001c9 ),
.DI(\blk00000001/sig000007ac ),
.S(\blk00000001/sig000001c8 ),
.O(\blk00000001/sig000001c7 )
);
XORCY \blk00000001/blk000004b3 (
.CI(\blk00000001/sig000001c9 ),
.LI(\blk00000001/sig000001c8 ),
.O(\blk00000001/sig000005ff )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004b2 (
.I0(\blk00000001/sig000007ad ),
.I1(\blk00000001/sig00000797 ),
.O(\blk00000001/sig000001c6 )
);
MUXCY \blk00000001/blk000004b1 (
.CI(\blk00000001/sig000001c7 ),
.DI(\blk00000001/sig000007ad ),
.S(\blk00000001/sig000001c6 ),
.O(\blk00000001/sig000001c5 )
);
XORCY \blk00000001/blk000004b0 (
.CI(\blk00000001/sig000001c7 ),
.LI(\blk00000001/sig000001c6 ),
.O(\blk00000001/sig00000600 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004af (
.I0(\blk00000001/sig000007ae ),
.I1(\blk00000001/sig00000798 ),
.O(\blk00000001/sig000001c4 )
);
MUXCY \blk00000001/blk000004ae (
.CI(\blk00000001/sig000001c5 ),
.DI(\blk00000001/sig000007ae ),
.S(\blk00000001/sig000001c4 ),
.O(\blk00000001/sig000001c3 )
);
XORCY \blk00000001/blk000004ad (
.CI(\blk00000001/sig000001c5 ),
.LI(\blk00000001/sig000001c4 ),
.O(\blk00000001/sig00000601 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004ac (
.I0(\blk00000001/sig000007af ),
.I1(\blk00000001/sig00000799 ),
.O(\blk00000001/sig000001c2 )
);
MUXCY \blk00000001/blk000004ab (
.CI(\blk00000001/sig000001c3 ),
.DI(\blk00000001/sig000007af ),
.S(\blk00000001/sig000001c2 ),
.O(\blk00000001/sig000001c1 )
);
XORCY \blk00000001/blk000004aa (
.CI(\blk00000001/sig000001c3 ),
.LI(\blk00000001/sig000001c2 ),
.O(\blk00000001/sig00000602 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a9 (
.I0(\blk00000001/sig000007b0 ),
.I1(\blk00000001/sig0000079a ),
.O(\blk00000001/sig000001c0 )
);
MUXCY \blk00000001/blk000004a8 (
.CI(\blk00000001/sig000001c1 ),
.DI(\blk00000001/sig000007b0 ),
.S(\blk00000001/sig000001c0 ),
.O(\blk00000001/sig000001bf )
);
XORCY \blk00000001/blk000004a7 (
.CI(\blk00000001/sig000001c1 ),
.LI(\blk00000001/sig000001c0 ),
.O(\blk00000001/sig00000603 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a6 (
.I0(\blk00000001/sig000007b1 ),
.I1(\blk00000001/sig0000079b ),
.O(\blk00000001/sig000001be )
);
MUXCY \blk00000001/blk000004a5 (
.CI(\blk00000001/sig000001bf ),
.DI(\blk00000001/sig000007b1 ),
.S(\blk00000001/sig000001be ),
.O(\blk00000001/sig000001bd )
);
XORCY \blk00000001/blk000004a4 (
.CI(\blk00000001/sig000001bf ),
.LI(\blk00000001/sig000001be ),
.O(\blk00000001/sig00000604 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a3 (
.I0(\blk00000001/sig000007b2 ),
.I1(\blk00000001/sig0000079c ),
.O(\blk00000001/sig000001bc )
);
MUXCY \blk00000001/blk000004a2 (
.CI(\blk00000001/sig000001bd ),
.DI(\blk00000001/sig000007b2 ),
.S(\blk00000001/sig000001bc ),
.O(\blk00000001/sig000001bb )
);
XORCY \blk00000001/blk000004a1 (
.CI(\blk00000001/sig000001bd ),
.LI(\blk00000001/sig000001bc ),
.O(\blk00000001/sig00000605 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000004a0 (
.I0(\blk00000001/sig000007b3 ),
.I1(\blk00000001/sig0000079d ),
.O(\blk00000001/sig000001ba )
);
MUXCY \blk00000001/blk0000049f (
.CI(\blk00000001/sig000001bb ),
.DI(\blk00000001/sig000007b3 ),
.S(\blk00000001/sig000001ba ),
.O(\blk00000001/sig000001b9 )
);
XORCY \blk00000001/blk0000049e (
.CI(\blk00000001/sig000001bb ),
.LI(\blk00000001/sig000001ba ),
.O(\blk00000001/sig00000606 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000049d (
.I0(\blk00000001/sig000007b4 ),
.I1(\blk00000001/sig0000079e ),
.O(\blk00000001/sig000001b8 )
);
MUXCY \blk00000001/blk0000049c (
.CI(\blk00000001/sig000001b9 ),
.DI(\blk00000001/sig000007b4 ),
.S(\blk00000001/sig000001b8 ),
.O(\blk00000001/sig000001b7 )
);
XORCY \blk00000001/blk0000049b (
.CI(\blk00000001/sig000001b9 ),
.LI(\blk00000001/sig000001b8 ),
.O(\blk00000001/sig00000607 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000049a (
.I0(\blk00000001/sig000007b5 ),
.I1(\blk00000001/sig0000079f ),
.O(\blk00000001/sig000001b6 )
);
MUXCY \blk00000001/blk00000499 (
.CI(\blk00000001/sig000001b7 ),
.DI(\blk00000001/sig000007b5 ),
.S(\blk00000001/sig000001b6 ),
.O(\blk00000001/sig000001b5 )
);
XORCY \blk00000001/blk00000498 (
.CI(\blk00000001/sig000001b7 ),
.LI(\blk00000001/sig000001b6 ),
.O(\blk00000001/sig00000608 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000497 (
.I0(\blk00000001/sig000007b6 ),
.I1(\blk00000001/sig000007a0 ),
.O(\blk00000001/sig000001b4 )
);
MUXCY \blk00000001/blk00000496 (
.CI(\blk00000001/sig000001b5 ),
.DI(\blk00000001/sig000007b6 ),
.S(\blk00000001/sig000001b4 ),
.O(\blk00000001/sig000001b3 )
);
XORCY \blk00000001/blk00000495 (
.CI(\blk00000001/sig000001b5 ),
.LI(\blk00000001/sig000001b4 ),
.O(\blk00000001/sig00000609 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000494 (
.I0(\blk00000001/sig000007b7 ),
.I1(\blk00000001/sig000007a1 ),
.O(\blk00000001/sig000001b2 )
);
MUXCY \blk00000001/blk00000493 (
.CI(\blk00000001/sig000001b3 ),
.DI(\blk00000001/sig000007b7 ),
.S(\blk00000001/sig000001b2 ),
.O(\blk00000001/sig000001b1 )
);
XORCY \blk00000001/blk00000492 (
.CI(\blk00000001/sig000001b3 ),
.LI(\blk00000001/sig000001b2 ),
.O(\blk00000001/sig0000060a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000491 (
.I0(\blk00000001/sig000007b8 ),
.I1(\blk00000001/sig000007a2 ),
.O(\blk00000001/sig000001b0 )
);
MUXCY \blk00000001/blk00000490 (
.CI(\blk00000001/sig000001b1 ),
.DI(\blk00000001/sig000007b8 ),
.S(\blk00000001/sig000001b0 ),
.O(\blk00000001/sig000001af )
);
XORCY \blk00000001/blk0000048f (
.CI(\blk00000001/sig000001b1 ),
.LI(\blk00000001/sig000001b0 ),
.O(\blk00000001/sig0000060b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000048e (
.I0(\blk00000001/sig000007b9 ),
.I1(\blk00000001/sig000007a3 ),
.O(\blk00000001/sig000001ae )
);
MUXCY \blk00000001/blk0000048d (
.CI(\blk00000001/sig000001af ),
.DI(\blk00000001/sig000007b9 ),
.S(\blk00000001/sig000001ae ),
.O(\blk00000001/sig000001ad )
);
XORCY \blk00000001/blk0000048c (
.CI(\blk00000001/sig000001af ),
.LI(\blk00000001/sig000001ae ),
.O(\blk00000001/sig0000060c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000048b (
.I0(\blk00000001/sig000007ba ),
.I1(\blk00000001/sig000007a4 ),
.O(\blk00000001/sig000001ac )
);
MUXCY \blk00000001/blk0000048a (
.CI(\blk00000001/sig000001ad ),
.DI(\blk00000001/sig000007ba ),
.S(\blk00000001/sig000001ac ),
.O(\blk00000001/sig000001ab )
);
XORCY \blk00000001/blk00000489 (
.CI(\blk00000001/sig000001ad ),
.LI(\blk00000001/sig000001ac ),
.O(\blk00000001/sig0000060d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000488 (
.I0(\blk00000001/sig000007bb ),
.I1(\blk00000001/sig000007a5 ),
.O(\blk00000001/sig000001aa )
);
MUXCY \blk00000001/blk00000487 (
.CI(\blk00000001/sig000001ab ),
.DI(\blk00000001/sig000007bb ),
.S(\blk00000001/sig000001aa ),
.O(\blk00000001/sig000001a9 )
);
XORCY \blk00000001/blk00000486 (
.CI(\blk00000001/sig000001ab ),
.LI(\blk00000001/sig000001aa ),
.O(\blk00000001/sig0000060e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000485 (
.I0(\blk00000001/sig000007bc ),
.I1(\blk00000001/sig000007a6 ),
.O(\blk00000001/sig000001a8 )
);
MUXCY \blk00000001/blk00000484 (
.CI(\blk00000001/sig000001a9 ),
.DI(\blk00000001/sig000007bc ),
.S(\blk00000001/sig000001a8 ),
.O(\blk00000001/sig000001a7 )
);
XORCY \blk00000001/blk00000483 (
.CI(\blk00000001/sig000001a9 ),
.LI(\blk00000001/sig000001a8 ),
.O(\blk00000001/sig0000060f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000482 (
.I0(\blk00000001/sig000007bd ),
.I1(\blk00000001/sig000007a7 ),
.O(\blk00000001/sig000001a6 )
);
MUXCY \blk00000001/blk00000481 (
.CI(\blk00000001/sig000001a7 ),
.DI(\blk00000001/sig000007bd ),
.S(\blk00000001/sig000001a6 ),
.O(\blk00000001/sig000001a5 )
);
XORCY \blk00000001/blk00000480 (
.CI(\blk00000001/sig000001a7 ),
.LI(\blk00000001/sig000001a6 ),
.O(\blk00000001/sig00000610 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000047f (
.I0(\blk00000001/sig000007bd ),
.I1(\blk00000001/sig000007a8 ),
.O(\blk00000001/sig000001a4 )
);
MUXCY \blk00000001/blk0000047e (
.CI(\blk00000001/sig000001a5 ),
.DI(\blk00000001/sig000007bd ),
.S(\blk00000001/sig000001a4 ),
.O(\blk00000001/sig000001a3 )
);
XORCY \blk00000001/blk0000047d (
.CI(\blk00000001/sig000001a5 ),
.LI(\blk00000001/sig000001a4 ),
.O(\blk00000001/sig00000611 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000047c (
.I0(\blk00000001/sig000007bd ),
.I1(\blk00000001/sig000007a9 ),
.O(\blk00000001/sig000001a2 )
);
XORCY \blk00000001/blk0000047b (
.CI(\blk00000001/sig000001a3 ),
.LI(\blk00000001/sig000001a2 ),
.O(\blk00000001/sig00000612 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000047a (
.I0(\blk00000001/sig00000780 ),
.I1(\blk00000001/sig0000076a ),
.O(\blk00000001/sig000001a1 )
);
MUXCY \blk00000001/blk00000479 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig00000780 ),
.S(\blk00000001/sig000001a1 ),
.O(\blk00000001/sig000001a0 )
);
XORCY \blk00000001/blk00000478 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig000001a1 ),
.O(\blk00000001/sig000005e7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000477 (
.I0(\blk00000001/sig00000781 ),
.I1(\blk00000001/sig0000076b ),
.O(\blk00000001/sig0000019f )
);
MUXCY \blk00000001/blk00000476 (
.CI(\blk00000001/sig000001a0 ),
.DI(\blk00000001/sig00000781 ),
.S(\blk00000001/sig0000019f ),
.O(\blk00000001/sig0000019e )
);
XORCY \blk00000001/blk00000475 (
.CI(\blk00000001/sig000001a0 ),
.LI(\blk00000001/sig0000019f ),
.O(\blk00000001/sig000005e8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000474 (
.I0(\blk00000001/sig00000782 ),
.I1(\blk00000001/sig0000076c ),
.O(\blk00000001/sig0000019d )
);
MUXCY \blk00000001/blk00000473 (
.CI(\blk00000001/sig0000019e ),
.DI(\blk00000001/sig00000782 ),
.S(\blk00000001/sig0000019d ),
.O(\blk00000001/sig0000019c )
);
XORCY \blk00000001/blk00000472 (
.CI(\blk00000001/sig0000019e ),
.LI(\blk00000001/sig0000019d ),
.O(\blk00000001/sig000005e9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000471 (
.I0(\blk00000001/sig00000783 ),
.I1(\blk00000001/sig0000076d ),
.O(\blk00000001/sig0000019b )
);
MUXCY \blk00000001/blk00000470 (
.CI(\blk00000001/sig0000019c ),
.DI(\blk00000001/sig00000783 ),
.S(\blk00000001/sig0000019b ),
.O(\blk00000001/sig0000019a )
);
XORCY \blk00000001/blk0000046f (
.CI(\blk00000001/sig0000019c ),
.LI(\blk00000001/sig0000019b ),
.O(\blk00000001/sig000005ea )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000046e (
.I0(\blk00000001/sig00000784 ),
.I1(\blk00000001/sig0000076e ),
.O(\blk00000001/sig00000199 )
);
MUXCY \blk00000001/blk0000046d (
.CI(\blk00000001/sig0000019a ),
.DI(\blk00000001/sig00000784 ),
.S(\blk00000001/sig00000199 ),
.O(\blk00000001/sig00000198 )
);
XORCY \blk00000001/blk0000046c (
.CI(\blk00000001/sig0000019a ),
.LI(\blk00000001/sig00000199 ),
.O(\blk00000001/sig000005eb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000046b (
.I0(\blk00000001/sig00000785 ),
.I1(\blk00000001/sig0000076f ),
.O(\blk00000001/sig00000197 )
);
MUXCY \blk00000001/blk0000046a (
.CI(\blk00000001/sig00000198 ),
.DI(\blk00000001/sig00000785 ),
.S(\blk00000001/sig00000197 ),
.O(\blk00000001/sig00000196 )
);
XORCY \blk00000001/blk00000469 (
.CI(\blk00000001/sig00000198 ),
.LI(\blk00000001/sig00000197 ),
.O(\blk00000001/sig000005ec )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000468 (
.I0(\blk00000001/sig00000786 ),
.I1(\blk00000001/sig00000770 ),
.O(\blk00000001/sig00000195 )
);
MUXCY \blk00000001/blk00000467 (
.CI(\blk00000001/sig00000196 ),
.DI(\blk00000001/sig00000786 ),
.S(\blk00000001/sig00000195 ),
.O(\blk00000001/sig00000194 )
);
XORCY \blk00000001/blk00000466 (
.CI(\blk00000001/sig00000196 ),
.LI(\blk00000001/sig00000195 ),
.O(\blk00000001/sig000005ed )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000465 (
.I0(\blk00000001/sig00000787 ),
.I1(\blk00000001/sig00000771 ),
.O(\blk00000001/sig00000193 )
);
MUXCY \blk00000001/blk00000464 (
.CI(\blk00000001/sig00000194 ),
.DI(\blk00000001/sig00000787 ),
.S(\blk00000001/sig00000193 ),
.O(\blk00000001/sig00000192 )
);
XORCY \blk00000001/blk00000463 (
.CI(\blk00000001/sig00000194 ),
.LI(\blk00000001/sig00000193 ),
.O(\blk00000001/sig000005ee )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000462 (
.I0(\blk00000001/sig00000788 ),
.I1(\blk00000001/sig00000772 ),
.O(\blk00000001/sig00000191 )
);
MUXCY \blk00000001/blk00000461 (
.CI(\blk00000001/sig00000192 ),
.DI(\blk00000001/sig00000788 ),
.S(\blk00000001/sig00000191 ),
.O(\blk00000001/sig00000190 )
);
XORCY \blk00000001/blk00000460 (
.CI(\blk00000001/sig00000192 ),
.LI(\blk00000001/sig00000191 ),
.O(\blk00000001/sig000005ef )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000045f (
.I0(\blk00000001/sig00000789 ),
.I1(\blk00000001/sig00000773 ),
.O(\blk00000001/sig0000018f )
);
MUXCY \blk00000001/blk0000045e (
.CI(\blk00000001/sig00000190 ),
.DI(\blk00000001/sig00000789 ),
.S(\blk00000001/sig0000018f ),
.O(\blk00000001/sig0000018e )
);
XORCY \blk00000001/blk0000045d (
.CI(\blk00000001/sig00000190 ),
.LI(\blk00000001/sig0000018f ),
.O(\blk00000001/sig000005f0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000045c (
.I0(\blk00000001/sig0000078a ),
.I1(\blk00000001/sig00000774 ),
.O(\blk00000001/sig0000018d )
);
MUXCY \blk00000001/blk0000045b (
.CI(\blk00000001/sig0000018e ),
.DI(\blk00000001/sig0000078a ),
.S(\blk00000001/sig0000018d ),
.O(\blk00000001/sig0000018c )
);
XORCY \blk00000001/blk0000045a (
.CI(\blk00000001/sig0000018e ),
.LI(\blk00000001/sig0000018d ),
.O(\blk00000001/sig000005f1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000459 (
.I0(\blk00000001/sig0000078b ),
.I1(\blk00000001/sig00000775 ),
.O(\blk00000001/sig0000018b )
);
MUXCY \blk00000001/blk00000458 (
.CI(\blk00000001/sig0000018c ),
.DI(\blk00000001/sig0000078b ),
.S(\blk00000001/sig0000018b ),
.O(\blk00000001/sig0000018a )
);
XORCY \blk00000001/blk00000457 (
.CI(\blk00000001/sig0000018c ),
.LI(\blk00000001/sig0000018b ),
.O(\blk00000001/sig000005f2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000456 (
.I0(\blk00000001/sig0000078c ),
.I1(\blk00000001/sig00000776 ),
.O(\blk00000001/sig00000189 )
);
MUXCY \blk00000001/blk00000455 (
.CI(\blk00000001/sig0000018a ),
.DI(\blk00000001/sig0000078c ),
.S(\blk00000001/sig00000189 ),
.O(\blk00000001/sig00000188 )
);
XORCY \blk00000001/blk00000454 (
.CI(\blk00000001/sig0000018a ),
.LI(\blk00000001/sig00000189 ),
.O(\blk00000001/sig000005f3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000453 (
.I0(\blk00000001/sig0000078d ),
.I1(\blk00000001/sig00000777 ),
.O(\blk00000001/sig00000187 )
);
MUXCY \blk00000001/blk00000452 (
.CI(\blk00000001/sig00000188 ),
.DI(\blk00000001/sig0000078d ),
.S(\blk00000001/sig00000187 ),
.O(\blk00000001/sig00000186 )
);
XORCY \blk00000001/blk00000451 (
.CI(\blk00000001/sig00000188 ),
.LI(\blk00000001/sig00000187 ),
.O(\blk00000001/sig000005f4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000450 (
.I0(\blk00000001/sig0000078e ),
.I1(\blk00000001/sig00000778 ),
.O(\blk00000001/sig00000185 )
);
MUXCY \blk00000001/blk0000044f (
.CI(\blk00000001/sig00000186 ),
.DI(\blk00000001/sig0000078e ),
.S(\blk00000001/sig00000185 ),
.O(\blk00000001/sig00000184 )
);
XORCY \blk00000001/blk0000044e (
.CI(\blk00000001/sig00000186 ),
.LI(\blk00000001/sig00000185 ),
.O(\blk00000001/sig000005f5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000044d (
.I0(\blk00000001/sig0000078f ),
.I1(\blk00000001/sig00000779 ),
.O(\blk00000001/sig00000183 )
);
MUXCY \blk00000001/blk0000044c (
.CI(\blk00000001/sig00000184 ),
.DI(\blk00000001/sig0000078f ),
.S(\blk00000001/sig00000183 ),
.O(\blk00000001/sig00000182 )
);
XORCY \blk00000001/blk0000044b (
.CI(\blk00000001/sig00000184 ),
.LI(\blk00000001/sig00000183 ),
.O(\blk00000001/sig000005f6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000044a (
.I0(\blk00000001/sig00000790 ),
.I1(\blk00000001/sig0000077a ),
.O(\blk00000001/sig00000181 )
);
MUXCY \blk00000001/blk00000449 (
.CI(\blk00000001/sig00000182 ),
.DI(\blk00000001/sig00000790 ),
.S(\blk00000001/sig00000181 ),
.O(\blk00000001/sig00000180 )
);
XORCY \blk00000001/blk00000448 (
.CI(\blk00000001/sig00000182 ),
.LI(\blk00000001/sig00000181 ),
.O(\blk00000001/sig000005f7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000447 (
.I0(\blk00000001/sig00000791 ),
.I1(\blk00000001/sig0000077b ),
.O(\blk00000001/sig0000017f )
);
MUXCY \blk00000001/blk00000446 (
.CI(\blk00000001/sig00000180 ),
.DI(\blk00000001/sig00000791 ),
.S(\blk00000001/sig0000017f ),
.O(\blk00000001/sig0000017e )
);
XORCY \blk00000001/blk00000445 (
.CI(\blk00000001/sig00000180 ),
.LI(\blk00000001/sig0000017f ),
.O(\blk00000001/sig000005f8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000444 (
.I0(\blk00000001/sig00000792 ),
.I1(\blk00000001/sig0000077c ),
.O(\blk00000001/sig0000017d )
);
MUXCY \blk00000001/blk00000443 (
.CI(\blk00000001/sig0000017e ),
.DI(\blk00000001/sig00000792 ),
.S(\blk00000001/sig0000017d ),
.O(\blk00000001/sig0000017c )
);
XORCY \blk00000001/blk00000442 (
.CI(\blk00000001/sig0000017e ),
.LI(\blk00000001/sig0000017d ),
.O(\blk00000001/sig000005f9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000441 (
.I0(\blk00000001/sig00000793 ),
.I1(\blk00000001/sig0000077d ),
.O(\blk00000001/sig0000017b )
);
MUXCY \blk00000001/blk00000440 (
.CI(\blk00000001/sig0000017c ),
.DI(\blk00000001/sig00000793 ),
.S(\blk00000001/sig0000017b ),
.O(\blk00000001/sig0000017a )
);
XORCY \blk00000001/blk0000043f (
.CI(\blk00000001/sig0000017c ),
.LI(\blk00000001/sig0000017b ),
.O(\blk00000001/sig000005fa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000043e (
.I0(\blk00000001/sig00000793 ),
.I1(\blk00000001/sig0000077e ),
.O(\blk00000001/sig00000179 )
);
MUXCY \blk00000001/blk0000043d (
.CI(\blk00000001/sig0000017a ),
.DI(\blk00000001/sig00000793 ),
.S(\blk00000001/sig00000179 ),
.O(\blk00000001/sig00000178 )
);
XORCY \blk00000001/blk0000043c (
.CI(\blk00000001/sig0000017a ),
.LI(\blk00000001/sig00000179 ),
.O(\blk00000001/sig000005fb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000043b (
.I0(\blk00000001/sig00000793 ),
.I1(\blk00000001/sig0000077f ),
.O(\blk00000001/sig00000177 )
);
XORCY \blk00000001/blk0000043a (
.CI(\blk00000001/sig00000178 ),
.LI(\blk00000001/sig00000177 ),
.O(\blk00000001/sig000005fc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000439 (
.I0(\blk00000001/sig00000702 ),
.I1(\blk00000001/sig000006e9 ),
.O(\blk00000001/sig00000176 )
);
MUXCY \blk00000001/blk00000438 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig00000702 ),
.S(\blk00000001/sig00000176 ),
.O(\blk00000001/sig00000175 )
);
XORCY \blk00000001/blk00000437 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig00000176 ),
.O(\blk00000001/sig000005a2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000436 (
.I0(\blk00000001/sig00000703 ),
.I1(\blk00000001/sig000006ea ),
.O(\blk00000001/sig00000174 )
);
MUXCY \blk00000001/blk00000435 (
.CI(\blk00000001/sig00000175 ),
.DI(\blk00000001/sig00000703 ),
.S(\blk00000001/sig00000174 ),
.O(\blk00000001/sig00000173 )
);
XORCY \blk00000001/blk00000434 (
.CI(\blk00000001/sig00000175 ),
.LI(\blk00000001/sig00000174 ),
.O(\blk00000001/sig000005a3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000433 (
.I0(\blk00000001/sig00000704 ),
.I1(\blk00000001/sig000006eb ),
.O(\blk00000001/sig00000172 )
);
MUXCY \blk00000001/blk00000432 (
.CI(\blk00000001/sig00000173 ),
.DI(\blk00000001/sig00000704 ),
.S(\blk00000001/sig00000172 ),
.O(\blk00000001/sig00000171 )
);
XORCY \blk00000001/blk00000431 (
.CI(\blk00000001/sig00000173 ),
.LI(\blk00000001/sig00000172 ),
.O(\blk00000001/sig000005a4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000430 (
.I0(\blk00000001/sig00000705 ),
.I1(\blk00000001/sig000006ec ),
.O(\blk00000001/sig00000170 )
);
MUXCY \blk00000001/blk0000042f (
.CI(\blk00000001/sig00000171 ),
.DI(\blk00000001/sig00000705 ),
.S(\blk00000001/sig00000170 ),
.O(\blk00000001/sig0000016f )
);
XORCY \blk00000001/blk0000042e (
.CI(\blk00000001/sig00000171 ),
.LI(\blk00000001/sig00000170 ),
.O(\blk00000001/sig000005a5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000042d (
.I0(\blk00000001/sig00000706 ),
.I1(\blk00000001/sig000006ed ),
.O(\blk00000001/sig0000016e )
);
MUXCY \blk00000001/blk0000042c (
.CI(\blk00000001/sig0000016f ),
.DI(\blk00000001/sig00000706 ),
.S(\blk00000001/sig0000016e ),
.O(\blk00000001/sig0000016d )
);
XORCY \blk00000001/blk0000042b (
.CI(\blk00000001/sig0000016f ),
.LI(\blk00000001/sig0000016e ),
.O(\blk00000001/sig000005a6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000042a (
.I0(\blk00000001/sig00000707 ),
.I1(\blk00000001/sig000006ee ),
.O(\blk00000001/sig0000016c )
);
MUXCY \blk00000001/blk00000429 (
.CI(\blk00000001/sig0000016d ),
.DI(\blk00000001/sig00000707 ),
.S(\blk00000001/sig0000016c ),
.O(\blk00000001/sig0000016b )
);
XORCY \blk00000001/blk00000428 (
.CI(\blk00000001/sig0000016d ),
.LI(\blk00000001/sig0000016c ),
.O(\blk00000001/sig000005a7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000427 (
.I0(\blk00000001/sig00000708 ),
.I1(\blk00000001/sig000006ef ),
.O(\blk00000001/sig0000016a )
);
MUXCY \blk00000001/blk00000426 (
.CI(\blk00000001/sig0000016b ),
.DI(\blk00000001/sig00000708 ),
.S(\blk00000001/sig0000016a ),
.O(\blk00000001/sig00000169 )
);
XORCY \blk00000001/blk00000425 (
.CI(\blk00000001/sig0000016b ),
.LI(\blk00000001/sig0000016a ),
.O(\blk00000001/sig000005a8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000424 (
.I0(\blk00000001/sig00000709 ),
.I1(\blk00000001/sig000006f0 ),
.O(\blk00000001/sig00000168 )
);
MUXCY \blk00000001/blk00000423 (
.CI(\blk00000001/sig00000169 ),
.DI(\blk00000001/sig00000709 ),
.S(\blk00000001/sig00000168 ),
.O(\blk00000001/sig00000167 )
);
XORCY \blk00000001/blk00000422 (
.CI(\blk00000001/sig00000169 ),
.LI(\blk00000001/sig00000168 ),
.O(\blk00000001/sig000005a9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000421 (
.I0(\blk00000001/sig0000070a ),
.I1(\blk00000001/sig000006f1 ),
.O(\blk00000001/sig00000166 )
);
MUXCY \blk00000001/blk00000420 (
.CI(\blk00000001/sig00000167 ),
.DI(\blk00000001/sig0000070a ),
.S(\blk00000001/sig00000166 ),
.O(\blk00000001/sig00000165 )
);
XORCY \blk00000001/blk0000041f (
.CI(\blk00000001/sig00000167 ),
.LI(\blk00000001/sig00000166 ),
.O(\blk00000001/sig000005aa )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000041e (
.I0(\blk00000001/sig0000070b ),
.I1(\blk00000001/sig000006f2 ),
.O(\blk00000001/sig00000164 )
);
MUXCY \blk00000001/blk0000041d (
.CI(\blk00000001/sig00000165 ),
.DI(\blk00000001/sig0000070b ),
.S(\blk00000001/sig00000164 ),
.O(\blk00000001/sig00000163 )
);
XORCY \blk00000001/blk0000041c (
.CI(\blk00000001/sig00000165 ),
.LI(\blk00000001/sig00000164 ),
.O(\blk00000001/sig000005ab )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000041b (
.I0(\blk00000001/sig0000070c ),
.I1(\blk00000001/sig000006f3 ),
.O(\blk00000001/sig00000162 )
);
MUXCY \blk00000001/blk0000041a (
.CI(\blk00000001/sig00000163 ),
.DI(\blk00000001/sig0000070c ),
.S(\blk00000001/sig00000162 ),
.O(\blk00000001/sig00000161 )
);
XORCY \blk00000001/blk00000419 (
.CI(\blk00000001/sig00000163 ),
.LI(\blk00000001/sig00000162 ),
.O(\blk00000001/sig000005ac )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000418 (
.I0(\blk00000001/sig0000070d ),
.I1(\blk00000001/sig000006f4 ),
.O(\blk00000001/sig00000160 )
);
MUXCY \blk00000001/blk00000417 (
.CI(\blk00000001/sig00000161 ),
.DI(\blk00000001/sig0000070d ),
.S(\blk00000001/sig00000160 ),
.O(\blk00000001/sig0000015f )
);
XORCY \blk00000001/blk00000416 (
.CI(\blk00000001/sig00000161 ),
.LI(\blk00000001/sig00000160 ),
.O(\blk00000001/sig000005ad )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000415 (
.I0(\blk00000001/sig0000070e ),
.I1(\blk00000001/sig000006f5 ),
.O(\blk00000001/sig0000015e )
);
MUXCY \blk00000001/blk00000414 (
.CI(\blk00000001/sig0000015f ),
.DI(\blk00000001/sig0000070e ),
.S(\blk00000001/sig0000015e ),
.O(\blk00000001/sig0000015d )
);
XORCY \blk00000001/blk00000413 (
.CI(\blk00000001/sig0000015f ),
.LI(\blk00000001/sig0000015e ),
.O(\blk00000001/sig000005ae )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000412 (
.I0(\blk00000001/sig0000070f ),
.I1(\blk00000001/sig000006f6 ),
.O(\blk00000001/sig0000015c )
);
MUXCY \blk00000001/blk00000411 (
.CI(\blk00000001/sig0000015d ),
.DI(\blk00000001/sig0000070f ),
.S(\blk00000001/sig0000015c ),
.O(\blk00000001/sig0000015b )
);
XORCY \blk00000001/blk00000410 (
.CI(\blk00000001/sig0000015d ),
.LI(\blk00000001/sig0000015c ),
.O(\blk00000001/sig000005af )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000040f (
.I0(\blk00000001/sig00000710 ),
.I1(\blk00000001/sig000006f7 ),
.O(\blk00000001/sig0000015a )
);
MUXCY \blk00000001/blk0000040e (
.CI(\blk00000001/sig0000015b ),
.DI(\blk00000001/sig00000710 ),
.S(\blk00000001/sig0000015a ),
.O(\blk00000001/sig00000159 )
);
XORCY \blk00000001/blk0000040d (
.CI(\blk00000001/sig0000015b ),
.LI(\blk00000001/sig0000015a ),
.O(\blk00000001/sig000005b0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000040c (
.I0(\blk00000001/sig00000711 ),
.I1(\blk00000001/sig000006f8 ),
.O(\blk00000001/sig00000158 )
);
MUXCY \blk00000001/blk0000040b (
.CI(\blk00000001/sig00000159 ),
.DI(\blk00000001/sig00000711 ),
.S(\blk00000001/sig00000158 ),
.O(\blk00000001/sig00000157 )
);
XORCY \blk00000001/blk0000040a (
.CI(\blk00000001/sig00000159 ),
.LI(\blk00000001/sig00000158 ),
.O(\blk00000001/sig000005b1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000409 (
.I0(\blk00000001/sig00000712 ),
.I1(\blk00000001/sig000006f9 ),
.O(\blk00000001/sig00000156 )
);
MUXCY \blk00000001/blk00000408 (
.CI(\blk00000001/sig00000157 ),
.DI(\blk00000001/sig00000712 ),
.S(\blk00000001/sig00000156 ),
.O(\blk00000001/sig00000155 )
);
XORCY \blk00000001/blk00000407 (
.CI(\blk00000001/sig00000157 ),
.LI(\blk00000001/sig00000156 ),
.O(\blk00000001/sig000005b2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000406 (
.I0(\blk00000001/sig00000713 ),
.I1(\blk00000001/sig000006fa ),
.O(\blk00000001/sig00000154 )
);
MUXCY \blk00000001/blk00000405 (
.CI(\blk00000001/sig00000155 ),
.DI(\blk00000001/sig00000713 ),
.S(\blk00000001/sig00000154 ),
.O(\blk00000001/sig00000153 )
);
XORCY \blk00000001/blk00000404 (
.CI(\blk00000001/sig00000155 ),
.LI(\blk00000001/sig00000154 ),
.O(\blk00000001/sig000005b3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000403 (
.I0(\blk00000001/sig00000714 ),
.I1(\blk00000001/sig000006fb ),
.O(\blk00000001/sig00000152 )
);
MUXCY \blk00000001/blk00000402 (
.CI(\blk00000001/sig00000153 ),
.DI(\blk00000001/sig00000714 ),
.S(\blk00000001/sig00000152 ),
.O(\blk00000001/sig00000151 )
);
XORCY \blk00000001/blk00000401 (
.CI(\blk00000001/sig00000153 ),
.LI(\blk00000001/sig00000152 ),
.O(\blk00000001/sig000005b4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000400 (
.I0(\blk00000001/sig000006fc ),
.I1(\blk00000001/sig00000715 ),
.O(\blk00000001/sig00000150 )
);
MUXCY \blk00000001/blk000003ff (
.CI(\blk00000001/sig00000151 ),
.DI(\blk00000001/sig00000715 ),
.S(\blk00000001/sig00000150 ),
.O(\blk00000001/sig0000014f )
);
XORCY \blk00000001/blk000003fe (
.CI(\blk00000001/sig00000151 ),
.LI(\blk00000001/sig00000150 ),
.O(\blk00000001/sig000005b5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003fd (
.I0(\blk00000001/sig000006fd ),
.I1(\blk00000001/sig00000715 ),
.O(\blk00000001/sig0000014e )
);
MUXCY \blk00000001/blk000003fc (
.CI(\blk00000001/sig0000014f ),
.DI(\blk00000001/sig00000715 ),
.S(\blk00000001/sig0000014e ),
.O(\blk00000001/sig0000014d )
);
XORCY \blk00000001/blk000003fb (
.CI(\blk00000001/sig0000014f ),
.LI(\blk00000001/sig0000014e ),
.O(\blk00000001/sig000005b6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003fa (
.I0(\blk00000001/sig000006fe ),
.I1(\blk00000001/sig00000715 ),
.O(\blk00000001/sig0000014c )
);
MUXCY \blk00000001/blk000003f9 (
.CI(\blk00000001/sig0000014d ),
.DI(\blk00000001/sig00000715 ),
.S(\blk00000001/sig0000014c ),
.O(\blk00000001/sig0000014b )
);
XORCY \blk00000001/blk000003f8 (
.CI(\blk00000001/sig0000014d ),
.LI(\blk00000001/sig0000014c ),
.O(\blk00000001/sig000005b7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f7 (
.I0(\blk00000001/sig00000715 ),
.I1(\blk00000001/sig000006ff ),
.O(\blk00000001/sig0000014a )
);
MUXCY \blk00000001/blk000003f6 (
.CI(\blk00000001/sig0000014b ),
.DI(\blk00000001/sig00000715 ),
.S(\blk00000001/sig0000014a ),
.O(\blk00000001/sig00000149 )
);
XORCY \blk00000001/blk000003f5 (
.CI(\blk00000001/sig0000014b ),
.LI(\blk00000001/sig0000014a ),
.O(\blk00000001/sig000005b8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f4 (
.I0(\blk00000001/sig00000715 ),
.I1(\blk00000001/sig00000700 ),
.O(\blk00000001/sig00000148 )
);
MUXCY \blk00000001/blk000003f3 (
.CI(\blk00000001/sig00000149 ),
.DI(\blk00000001/sig00000715 ),
.S(\blk00000001/sig00000148 ),
.O(\blk00000001/sig00000147 )
);
XORCY \blk00000001/blk000003f2 (
.CI(\blk00000001/sig00000149 ),
.LI(\blk00000001/sig00000148 ),
.O(\blk00000001/sig000005b9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003f1 (
.I0(\blk00000001/sig00000715 ),
.I1(\blk00000001/sig00000700 ),
.O(\blk00000001/sig00000146 )
);
XORCY \blk00000001/blk000003f0 (
.CI(\blk00000001/sig00000147 ),
.LI(\blk00000001/sig00000146 ),
.O(\blk00000001/sig000005ba )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ef (
.I0(\blk00000001/sig00000756 ),
.I1(\blk00000001/sig00000740 ),
.O(\blk00000001/sig00000145 )
);
MUXCY \blk00000001/blk000003ee (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig00000756 ),
.S(\blk00000001/sig00000145 ),
.O(\blk00000001/sig00000144 )
);
XORCY \blk00000001/blk000003ed (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig00000145 ),
.O(\blk00000001/sig000005d1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ec (
.I0(\blk00000001/sig00000757 ),
.I1(\blk00000001/sig00000741 ),
.O(\blk00000001/sig00000143 )
);
MUXCY \blk00000001/blk000003eb (
.CI(\blk00000001/sig00000144 ),
.DI(\blk00000001/sig00000757 ),
.S(\blk00000001/sig00000143 ),
.O(\blk00000001/sig00000142 )
);
XORCY \blk00000001/blk000003ea (
.CI(\blk00000001/sig00000144 ),
.LI(\blk00000001/sig00000143 ),
.O(\blk00000001/sig000005d2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e9 (
.I0(\blk00000001/sig00000758 ),
.I1(\blk00000001/sig00000742 ),
.O(\blk00000001/sig00000141 )
);
MUXCY \blk00000001/blk000003e8 (
.CI(\blk00000001/sig00000142 ),
.DI(\blk00000001/sig00000758 ),
.S(\blk00000001/sig00000141 ),
.O(\blk00000001/sig00000140 )
);
XORCY \blk00000001/blk000003e7 (
.CI(\blk00000001/sig00000142 ),
.LI(\blk00000001/sig00000141 ),
.O(\blk00000001/sig000005d3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e6 (
.I0(\blk00000001/sig00000759 ),
.I1(\blk00000001/sig00000743 ),
.O(\blk00000001/sig0000013f )
);
MUXCY \blk00000001/blk000003e5 (
.CI(\blk00000001/sig00000140 ),
.DI(\blk00000001/sig00000759 ),
.S(\blk00000001/sig0000013f ),
.O(\blk00000001/sig0000013e )
);
XORCY \blk00000001/blk000003e4 (
.CI(\blk00000001/sig00000140 ),
.LI(\blk00000001/sig0000013f ),
.O(\blk00000001/sig000005d4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e3 (
.I0(\blk00000001/sig0000075a ),
.I1(\blk00000001/sig00000744 ),
.O(\blk00000001/sig0000013d )
);
MUXCY \blk00000001/blk000003e2 (
.CI(\blk00000001/sig0000013e ),
.DI(\blk00000001/sig0000075a ),
.S(\blk00000001/sig0000013d ),
.O(\blk00000001/sig0000013c )
);
XORCY \blk00000001/blk000003e1 (
.CI(\blk00000001/sig0000013e ),
.LI(\blk00000001/sig0000013d ),
.O(\blk00000001/sig000005d5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003e0 (
.I0(\blk00000001/sig0000075b ),
.I1(\blk00000001/sig00000745 ),
.O(\blk00000001/sig0000013b )
);
MUXCY \blk00000001/blk000003df (
.CI(\blk00000001/sig0000013c ),
.DI(\blk00000001/sig0000075b ),
.S(\blk00000001/sig0000013b ),
.O(\blk00000001/sig0000013a )
);
XORCY \blk00000001/blk000003de (
.CI(\blk00000001/sig0000013c ),
.LI(\blk00000001/sig0000013b ),
.O(\blk00000001/sig000005d6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003dd (
.I0(\blk00000001/sig0000075c ),
.I1(\blk00000001/sig00000746 ),
.O(\blk00000001/sig00000139 )
);
MUXCY \blk00000001/blk000003dc (
.CI(\blk00000001/sig0000013a ),
.DI(\blk00000001/sig0000075c ),
.S(\blk00000001/sig00000139 ),
.O(\blk00000001/sig00000138 )
);
XORCY \blk00000001/blk000003db (
.CI(\blk00000001/sig0000013a ),
.LI(\blk00000001/sig00000139 ),
.O(\blk00000001/sig000005d7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003da (
.I0(\blk00000001/sig0000075d ),
.I1(\blk00000001/sig00000747 ),
.O(\blk00000001/sig00000137 )
);
MUXCY \blk00000001/blk000003d9 (
.CI(\blk00000001/sig00000138 ),
.DI(\blk00000001/sig0000075d ),
.S(\blk00000001/sig00000137 ),
.O(\blk00000001/sig00000136 )
);
XORCY \blk00000001/blk000003d8 (
.CI(\blk00000001/sig00000138 ),
.LI(\blk00000001/sig00000137 ),
.O(\blk00000001/sig000005d8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d7 (
.I0(\blk00000001/sig0000075e ),
.I1(\blk00000001/sig00000748 ),
.O(\blk00000001/sig00000135 )
);
MUXCY \blk00000001/blk000003d6 (
.CI(\blk00000001/sig00000136 ),
.DI(\blk00000001/sig0000075e ),
.S(\blk00000001/sig00000135 ),
.O(\blk00000001/sig00000134 )
);
XORCY \blk00000001/blk000003d5 (
.CI(\blk00000001/sig00000136 ),
.LI(\blk00000001/sig00000135 ),
.O(\blk00000001/sig000005d9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d4 (
.I0(\blk00000001/sig0000075f ),
.I1(\blk00000001/sig00000749 ),
.O(\blk00000001/sig00000133 )
);
MUXCY \blk00000001/blk000003d3 (
.CI(\blk00000001/sig00000134 ),
.DI(\blk00000001/sig0000075f ),
.S(\blk00000001/sig00000133 ),
.O(\blk00000001/sig00000132 )
);
XORCY \blk00000001/blk000003d2 (
.CI(\blk00000001/sig00000134 ),
.LI(\blk00000001/sig00000133 ),
.O(\blk00000001/sig000005da )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003d1 (
.I0(\blk00000001/sig00000760 ),
.I1(\blk00000001/sig0000074a ),
.O(\blk00000001/sig00000131 )
);
MUXCY \blk00000001/blk000003d0 (
.CI(\blk00000001/sig00000132 ),
.DI(\blk00000001/sig00000760 ),
.S(\blk00000001/sig00000131 ),
.O(\blk00000001/sig00000130 )
);
XORCY \blk00000001/blk000003cf (
.CI(\blk00000001/sig00000132 ),
.LI(\blk00000001/sig00000131 ),
.O(\blk00000001/sig000005db )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ce (
.I0(\blk00000001/sig00000761 ),
.I1(\blk00000001/sig0000074b ),
.O(\blk00000001/sig0000012f )
);
MUXCY \blk00000001/blk000003cd (
.CI(\blk00000001/sig00000130 ),
.DI(\blk00000001/sig00000761 ),
.S(\blk00000001/sig0000012f ),
.O(\blk00000001/sig0000012e )
);
XORCY \blk00000001/blk000003cc (
.CI(\blk00000001/sig00000130 ),
.LI(\blk00000001/sig0000012f ),
.O(\blk00000001/sig000005dc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003cb (
.I0(\blk00000001/sig00000762 ),
.I1(\blk00000001/sig0000074c ),
.O(\blk00000001/sig0000012d )
);
MUXCY \blk00000001/blk000003ca (
.CI(\blk00000001/sig0000012e ),
.DI(\blk00000001/sig00000762 ),
.S(\blk00000001/sig0000012d ),
.O(\blk00000001/sig0000012c )
);
XORCY \blk00000001/blk000003c9 (
.CI(\blk00000001/sig0000012e ),
.LI(\blk00000001/sig0000012d ),
.O(\blk00000001/sig000005dd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003c8 (
.I0(\blk00000001/sig00000763 ),
.I1(\blk00000001/sig0000074d ),
.O(\blk00000001/sig0000012b )
);
MUXCY \blk00000001/blk000003c7 (
.CI(\blk00000001/sig0000012c ),
.DI(\blk00000001/sig00000763 ),
.S(\blk00000001/sig0000012b ),
.O(\blk00000001/sig0000012a )
);
XORCY \blk00000001/blk000003c6 (
.CI(\blk00000001/sig0000012c ),
.LI(\blk00000001/sig0000012b ),
.O(\blk00000001/sig000005de )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003c5 (
.I0(\blk00000001/sig00000764 ),
.I1(\blk00000001/sig0000074e ),
.O(\blk00000001/sig00000129 )
);
MUXCY \blk00000001/blk000003c4 (
.CI(\blk00000001/sig0000012a ),
.DI(\blk00000001/sig00000764 ),
.S(\blk00000001/sig00000129 ),
.O(\blk00000001/sig00000128 )
);
XORCY \blk00000001/blk000003c3 (
.CI(\blk00000001/sig0000012a ),
.LI(\blk00000001/sig00000129 ),
.O(\blk00000001/sig000005df )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003c2 (
.I0(\blk00000001/sig00000765 ),
.I1(\blk00000001/sig0000074f ),
.O(\blk00000001/sig00000127 )
);
MUXCY \blk00000001/blk000003c1 (
.CI(\blk00000001/sig00000128 ),
.DI(\blk00000001/sig00000765 ),
.S(\blk00000001/sig00000127 ),
.O(\blk00000001/sig00000126 )
);
XORCY \blk00000001/blk000003c0 (
.CI(\blk00000001/sig00000128 ),
.LI(\blk00000001/sig00000127 ),
.O(\blk00000001/sig000005e0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003bf (
.I0(\blk00000001/sig00000766 ),
.I1(\blk00000001/sig00000750 ),
.O(\blk00000001/sig00000125 )
);
MUXCY \blk00000001/blk000003be (
.CI(\blk00000001/sig00000126 ),
.DI(\blk00000001/sig00000766 ),
.S(\blk00000001/sig00000125 ),
.O(\blk00000001/sig00000124 )
);
XORCY \blk00000001/blk000003bd (
.CI(\blk00000001/sig00000126 ),
.LI(\blk00000001/sig00000125 ),
.O(\blk00000001/sig000005e1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003bc (
.I0(\blk00000001/sig00000767 ),
.I1(\blk00000001/sig00000751 ),
.O(\blk00000001/sig00000123 )
);
MUXCY \blk00000001/blk000003bb (
.CI(\blk00000001/sig00000124 ),
.DI(\blk00000001/sig00000767 ),
.S(\blk00000001/sig00000123 ),
.O(\blk00000001/sig00000122 )
);
XORCY \blk00000001/blk000003ba (
.CI(\blk00000001/sig00000124 ),
.LI(\blk00000001/sig00000123 ),
.O(\blk00000001/sig000005e2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b9 (
.I0(\blk00000001/sig00000768 ),
.I1(\blk00000001/sig00000752 ),
.O(\blk00000001/sig00000121 )
);
MUXCY \blk00000001/blk000003b8 (
.CI(\blk00000001/sig00000122 ),
.DI(\blk00000001/sig00000768 ),
.S(\blk00000001/sig00000121 ),
.O(\blk00000001/sig00000120 )
);
XORCY \blk00000001/blk000003b7 (
.CI(\blk00000001/sig00000122 ),
.LI(\blk00000001/sig00000121 ),
.O(\blk00000001/sig000005e3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b6 (
.I0(\blk00000001/sig00000769 ),
.I1(\blk00000001/sig00000753 ),
.O(\blk00000001/sig0000011f )
);
MUXCY \blk00000001/blk000003b5 (
.CI(\blk00000001/sig00000120 ),
.DI(\blk00000001/sig00000769 ),
.S(\blk00000001/sig0000011f ),
.O(\blk00000001/sig0000011e )
);
XORCY \blk00000001/blk000003b4 (
.CI(\blk00000001/sig00000120 ),
.LI(\blk00000001/sig0000011f ),
.O(\blk00000001/sig000005e4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b3 (
.I0(\blk00000001/sig00000769 ),
.I1(\blk00000001/sig00000754 ),
.O(\blk00000001/sig0000011d )
);
MUXCY \blk00000001/blk000003b2 (
.CI(\blk00000001/sig0000011e ),
.DI(\blk00000001/sig00000769 ),
.S(\blk00000001/sig0000011d ),
.O(\blk00000001/sig0000011c )
);
XORCY \blk00000001/blk000003b1 (
.CI(\blk00000001/sig0000011e ),
.LI(\blk00000001/sig0000011d ),
.O(\blk00000001/sig000005e5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003b0 (
.I0(\blk00000001/sig00000769 ),
.I1(\blk00000001/sig00000755 ),
.O(\blk00000001/sig0000011b )
);
XORCY \blk00000001/blk000003af (
.CI(\blk00000001/sig0000011c ),
.LI(\blk00000001/sig0000011b ),
.O(\blk00000001/sig000005e6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ae (
.I0(\blk00000001/sig0000072c ),
.I1(\blk00000001/sig00000716 ),
.O(\blk00000001/sig0000011a )
);
MUXCY \blk00000001/blk000003ad (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig0000072c ),
.S(\blk00000001/sig0000011a ),
.O(\blk00000001/sig00000119 )
);
XORCY \blk00000001/blk000003ac (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig0000011a ),
.O(\blk00000001/sig000005bb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003ab (
.I0(\blk00000001/sig0000072d ),
.I1(\blk00000001/sig00000717 ),
.O(\blk00000001/sig00000118 )
);
MUXCY \blk00000001/blk000003aa (
.CI(\blk00000001/sig00000119 ),
.DI(\blk00000001/sig0000072d ),
.S(\blk00000001/sig00000118 ),
.O(\blk00000001/sig00000117 )
);
XORCY \blk00000001/blk000003a9 (
.CI(\blk00000001/sig00000119 ),
.LI(\blk00000001/sig00000118 ),
.O(\blk00000001/sig000005bc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a8 (
.I0(\blk00000001/sig0000072e ),
.I1(\blk00000001/sig00000718 ),
.O(\blk00000001/sig00000116 )
);
MUXCY \blk00000001/blk000003a7 (
.CI(\blk00000001/sig00000117 ),
.DI(\blk00000001/sig0000072e ),
.S(\blk00000001/sig00000116 ),
.O(\blk00000001/sig00000115 )
);
XORCY \blk00000001/blk000003a6 (
.CI(\blk00000001/sig00000117 ),
.LI(\blk00000001/sig00000116 ),
.O(\blk00000001/sig000005bd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a5 (
.I0(\blk00000001/sig0000072f ),
.I1(\blk00000001/sig00000719 ),
.O(\blk00000001/sig00000114 )
);
MUXCY \blk00000001/blk000003a4 (
.CI(\blk00000001/sig00000115 ),
.DI(\blk00000001/sig0000072f ),
.S(\blk00000001/sig00000114 ),
.O(\blk00000001/sig00000113 )
);
XORCY \blk00000001/blk000003a3 (
.CI(\blk00000001/sig00000115 ),
.LI(\blk00000001/sig00000114 ),
.O(\blk00000001/sig000005be )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000003a2 (
.I0(\blk00000001/sig00000730 ),
.I1(\blk00000001/sig0000071a ),
.O(\blk00000001/sig00000112 )
);
MUXCY \blk00000001/blk000003a1 (
.CI(\blk00000001/sig00000113 ),
.DI(\blk00000001/sig00000730 ),
.S(\blk00000001/sig00000112 ),
.O(\blk00000001/sig00000111 )
);
XORCY \blk00000001/blk000003a0 (
.CI(\blk00000001/sig00000113 ),
.LI(\blk00000001/sig00000112 ),
.O(\blk00000001/sig000005bf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000039f (
.I0(\blk00000001/sig00000731 ),
.I1(\blk00000001/sig0000071b ),
.O(\blk00000001/sig00000110 )
);
MUXCY \blk00000001/blk0000039e (
.CI(\blk00000001/sig00000111 ),
.DI(\blk00000001/sig00000731 ),
.S(\blk00000001/sig00000110 ),
.O(\blk00000001/sig0000010f )
);
XORCY \blk00000001/blk0000039d (
.CI(\blk00000001/sig00000111 ),
.LI(\blk00000001/sig00000110 ),
.O(\blk00000001/sig000005c0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000039c (
.I0(\blk00000001/sig00000732 ),
.I1(\blk00000001/sig0000071c ),
.O(\blk00000001/sig0000010e )
);
MUXCY \blk00000001/blk0000039b (
.CI(\blk00000001/sig0000010f ),
.DI(\blk00000001/sig00000732 ),
.S(\blk00000001/sig0000010e ),
.O(\blk00000001/sig0000010d )
);
XORCY \blk00000001/blk0000039a (
.CI(\blk00000001/sig0000010f ),
.LI(\blk00000001/sig0000010e ),
.O(\blk00000001/sig000005c1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000399 (
.I0(\blk00000001/sig00000733 ),
.I1(\blk00000001/sig0000071d ),
.O(\blk00000001/sig0000010c )
);
MUXCY \blk00000001/blk00000398 (
.CI(\blk00000001/sig0000010d ),
.DI(\blk00000001/sig00000733 ),
.S(\blk00000001/sig0000010c ),
.O(\blk00000001/sig0000010b )
);
XORCY \blk00000001/blk00000397 (
.CI(\blk00000001/sig0000010d ),
.LI(\blk00000001/sig0000010c ),
.O(\blk00000001/sig000005c2 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000396 (
.I0(\blk00000001/sig00000734 ),
.I1(\blk00000001/sig0000071e ),
.O(\blk00000001/sig0000010a )
);
MUXCY \blk00000001/blk00000395 (
.CI(\blk00000001/sig0000010b ),
.DI(\blk00000001/sig00000734 ),
.S(\blk00000001/sig0000010a ),
.O(\blk00000001/sig00000109 )
);
XORCY \blk00000001/blk00000394 (
.CI(\blk00000001/sig0000010b ),
.LI(\blk00000001/sig0000010a ),
.O(\blk00000001/sig000005c3 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000393 (
.I0(\blk00000001/sig00000735 ),
.I1(\blk00000001/sig0000071f ),
.O(\blk00000001/sig00000108 )
);
MUXCY \blk00000001/blk00000392 (
.CI(\blk00000001/sig00000109 ),
.DI(\blk00000001/sig00000735 ),
.S(\blk00000001/sig00000108 ),
.O(\blk00000001/sig00000107 )
);
XORCY \blk00000001/blk00000391 (
.CI(\blk00000001/sig00000109 ),
.LI(\blk00000001/sig00000108 ),
.O(\blk00000001/sig000005c4 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000390 (
.I0(\blk00000001/sig00000736 ),
.I1(\blk00000001/sig00000720 ),
.O(\blk00000001/sig00000106 )
);
MUXCY \blk00000001/blk0000038f (
.CI(\blk00000001/sig00000107 ),
.DI(\blk00000001/sig00000736 ),
.S(\blk00000001/sig00000106 ),
.O(\blk00000001/sig00000105 )
);
XORCY \blk00000001/blk0000038e (
.CI(\blk00000001/sig00000107 ),
.LI(\blk00000001/sig00000106 ),
.O(\blk00000001/sig000005c5 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000038d (
.I0(\blk00000001/sig00000737 ),
.I1(\blk00000001/sig00000721 ),
.O(\blk00000001/sig00000104 )
);
MUXCY \blk00000001/blk0000038c (
.CI(\blk00000001/sig00000105 ),
.DI(\blk00000001/sig00000737 ),
.S(\blk00000001/sig00000104 ),
.O(\blk00000001/sig00000103 )
);
XORCY \blk00000001/blk0000038b (
.CI(\blk00000001/sig00000105 ),
.LI(\blk00000001/sig00000104 ),
.O(\blk00000001/sig000005c6 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000038a (
.I0(\blk00000001/sig00000738 ),
.I1(\blk00000001/sig00000722 ),
.O(\blk00000001/sig00000102 )
);
MUXCY \blk00000001/blk00000389 (
.CI(\blk00000001/sig00000103 ),
.DI(\blk00000001/sig00000738 ),
.S(\blk00000001/sig00000102 ),
.O(\blk00000001/sig00000101 )
);
XORCY \blk00000001/blk00000388 (
.CI(\blk00000001/sig00000103 ),
.LI(\blk00000001/sig00000102 ),
.O(\blk00000001/sig000005c7 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000387 (
.I0(\blk00000001/sig00000739 ),
.I1(\blk00000001/sig00000723 ),
.O(\blk00000001/sig00000100 )
);
MUXCY \blk00000001/blk00000386 (
.CI(\blk00000001/sig00000101 ),
.DI(\blk00000001/sig00000739 ),
.S(\blk00000001/sig00000100 ),
.O(\blk00000001/sig000000ff )
);
XORCY \blk00000001/blk00000385 (
.CI(\blk00000001/sig00000101 ),
.LI(\blk00000001/sig00000100 ),
.O(\blk00000001/sig000005c8 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000384 (
.I0(\blk00000001/sig0000073a ),
.I1(\blk00000001/sig00000724 ),
.O(\blk00000001/sig000000fe )
);
MUXCY \blk00000001/blk00000383 (
.CI(\blk00000001/sig000000ff ),
.DI(\blk00000001/sig0000073a ),
.S(\blk00000001/sig000000fe ),
.O(\blk00000001/sig000000fd )
);
XORCY \blk00000001/blk00000382 (
.CI(\blk00000001/sig000000ff ),
.LI(\blk00000001/sig000000fe ),
.O(\blk00000001/sig000005c9 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000381 (
.I0(\blk00000001/sig0000073b ),
.I1(\blk00000001/sig00000725 ),
.O(\blk00000001/sig000000fc )
);
MUXCY \blk00000001/blk00000380 (
.CI(\blk00000001/sig000000fd ),
.DI(\blk00000001/sig0000073b ),
.S(\blk00000001/sig000000fc ),
.O(\blk00000001/sig000000fb )
);
XORCY \blk00000001/blk0000037f (
.CI(\blk00000001/sig000000fd ),
.LI(\blk00000001/sig000000fc ),
.O(\blk00000001/sig000005ca )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000037e (
.I0(\blk00000001/sig0000073c ),
.I1(\blk00000001/sig00000726 ),
.O(\blk00000001/sig000000fa )
);
MUXCY \blk00000001/blk0000037d (
.CI(\blk00000001/sig000000fb ),
.DI(\blk00000001/sig0000073c ),
.S(\blk00000001/sig000000fa ),
.O(\blk00000001/sig000000f9 )
);
XORCY \blk00000001/blk0000037c (
.CI(\blk00000001/sig000000fb ),
.LI(\blk00000001/sig000000fa ),
.O(\blk00000001/sig000005cb )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000037b (
.I0(\blk00000001/sig0000073d ),
.I1(\blk00000001/sig00000727 ),
.O(\blk00000001/sig000000f8 )
);
MUXCY \blk00000001/blk0000037a (
.CI(\blk00000001/sig000000f9 ),
.DI(\blk00000001/sig0000073d ),
.S(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000000f7 )
);
XORCY \blk00000001/blk00000379 (
.CI(\blk00000001/sig000000f9 ),
.LI(\blk00000001/sig000000f8 ),
.O(\blk00000001/sig000005cc )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000378 (
.I0(\blk00000001/sig0000073e ),
.I1(\blk00000001/sig00000728 ),
.O(\blk00000001/sig000000f6 )
);
MUXCY \blk00000001/blk00000377 (
.CI(\blk00000001/sig000000f7 ),
.DI(\blk00000001/sig0000073e ),
.S(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000000f5 )
);
XORCY \blk00000001/blk00000376 (
.CI(\blk00000001/sig000000f7 ),
.LI(\blk00000001/sig000000f6 ),
.O(\blk00000001/sig000005cd )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000375 (
.I0(\blk00000001/sig0000073f ),
.I1(\blk00000001/sig00000729 ),
.O(\blk00000001/sig000000f4 )
);
MUXCY \blk00000001/blk00000374 (
.CI(\blk00000001/sig000000f5 ),
.DI(\blk00000001/sig0000073f ),
.S(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig000000f3 )
);
XORCY \blk00000001/blk00000373 (
.CI(\blk00000001/sig000000f5 ),
.LI(\blk00000001/sig000000f4 ),
.O(\blk00000001/sig000005ce )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000372 (
.I0(\blk00000001/sig0000073f ),
.I1(\blk00000001/sig0000072a ),
.O(\blk00000001/sig000000f2 )
);
MUXCY \blk00000001/blk00000371 (
.CI(\blk00000001/sig000000f3 ),
.DI(\blk00000001/sig0000073f ),
.S(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig000000f1 )
);
XORCY \blk00000001/blk00000370 (
.CI(\blk00000001/sig000000f3 ),
.LI(\blk00000001/sig000000f2 ),
.O(\blk00000001/sig000005cf )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000036f (
.I0(\blk00000001/sig0000073f ),
.I1(\blk00000001/sig0000072b ),
.O(\blk00000001/sig000000f0 )
);
XORCY \blk00000001/blk0000036e (
.CI(\blk00000001/sig000000f1 ),
.LI(\blk00000001/sig000000f0 ),
.O(\blk00000001/sig000005d0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000036d (
.I0(\blk00000001/sig000006d5 ),
.I1(\blk00000001/sig000006bc ),
.O(\blk00000001/sig000000ef )
);
MUXCY \blk00000001/blk0000036c (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig000006d5 ),
.S(\blk00000001/sig000000ef ),
.O(\blk00000001/sig000000ee )
);
XORCY \blk00000001/blk0000036b (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig000000ef ),
.O(\blk00000001/sig00000589 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000036a (
.I0(\blk00000001/sig000006d6 ),
.I1(\blk00000001/sig000006bd ),
.O(\blk00000001/sig000000ed )
);
MUXCY \blk00000001/blk00000369 (
.CI(\blk00000001/sig000000ee ),
.DI(\blk00000001/sig000006d6 ),
.S(\blk00000001/sig000000ed ),
.O(\blk00000001/sig000000ec )
);
XORCY \blk00000001/blk00000368 (
.CI(\blk00000001/sig000000ee ),
.LI(\blk00000001/sig000000ed ),
.O(\blk00000001/sig0000058a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000367 (
.I0(\blk00000001/sig000006d7 ),
.I1(\blk00000001/sig000006be ),
.O(\blk00000001/sig000000eb )
);
MUXCY \blk00000001/blk00000366 (
.CI(\blk00000001/sig000000ec ),
.DI(\blk00000001/sig000006d7 ),
.S(\blk00000001/sig000000eb ),
.O(\blk00000001/sig000000ea )
);
XORCY \blk00000001/blk00000365 (
.CI(\blk00000001/sig000000ec ),
.LI(\blk00000001/sig000000eb ),
.O(\blk00000001/sig0000058b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000364 (
.I0(\blk00000001/sig000006d8 ),
.I1(\blk00000001/sig000006bf ),
.O(\blk00000001/sig000000e9 )
);
MUXCY \blk00000001/blk00000363 (
.CI(\blk00000001/sig000000ea ),
.DI(\blk00000001/sig000006d8 ),
.S(\blk00000001/sig000000e9 ),
.O(\blk00000001/sig000000e8 )
);
XORCY \blk00000001/blk00000362 (
.CI(\blk00000001/sig000000ea ),
.LI(\blk00000001/sig000000e9 ),
.O(\blk00000001/sig0000058c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000361 (
.I0(\blk00000001/sig000006d9 ),
.I1(\blk00000001/sig000006c0 ),
.O(\blk00000001/sig000000e7 )
);
MUXCY \blk00000001/blk00000360 (
.CI(\blk00000001/sig000000e8 ),
.DI(\blk00000001/sig000006d9 ),
.S(\blk00000001/sig000000e7 ),
.O(\blk00000001/sig000000e6 )
);
XORCY \blk00000001/blk0000035f (
.CI(\blk00000001/sig000000e8 ),
.LI(\blk00000001/sig000000e7 ),
.O(\blk00000001/sig0000058d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000035e (
.I0(\blk00000001/sig000006da ),
.I1(\blk00000001/sig000006c1 ),
.O(\blk00000001/sig000000e5 )
);
MUXCY \blk00000001/blk0000035d (
.CI(\blk00000001/sig000000e6 ),
.DI(\blk00000001/sig000006da ),
.S(\blk00000001/sig000000e5 ),
.O(\blk00000001/sig000000e4 )
);
XORCY \blk00000001/blk0000035c (
.CI(\blk00000001/sig000000e6 ),
.LI(\blk00000001/sig000000e5 ),
.O(\blk00000001/sig0000058e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000035b (
.I0(\blk00000001/sig000006db ),
.I1(\blk00000001/sig000006c2 ),
.O(\blk00000001/sig000000e3 )
);
MUXCY \blk00000001/blk0000035a (
.CI(\blk00000001/sig000000e4 ),
.DI(\blk00000001/sig000006db ),
.S(\blk00000001/sig000000e3 ),
.O(\blk00000001/sig000000e2 )
);
XORCY \blk00000001/blk00000359 (
.CI(\blk00000001/sig000000e4 ),
.LI(\blk00000001/sig000000e3 ),
.O(\blk00000001/sig0000058f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000358 (
.I0(\blk00000001/sig000006dc ),
.I1(\blk00000001/sig000006c3 ),
.O(\blk00000001/sig000000e1 )
);
MUXCY \blk00000001/blk00000357 (
.CI(\blk00000001/sig000000e2 ),
.DI(\blk00000001/sig000006dc ),
.S(\blk00000001/sig000000e1 ),
.O(\blk00000001/sig000000e0 )
);
XORCY \blk00000001/blk00000356 (
.CI(\blk00000001/sig000000e2 ),
.LI(\blk00000001/sig000000e1 ),
.O(\blk00000001/sig00000590 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000355 (
.I0(\blk00000001/sig000006dd ),
.I1(\blk00000001/sig000006c4 ),
.O(\blk00000001/sig000000df )
);
MUXCY \blk00000001/blk00000354 (
.CI(\blk00000001/sig000000e0 ),
.DI(\blk00000001/sig000006dd ),
.S(\blk00000001/sig000000df ),
.O(\blk00000001/sig000000de )
);
XORCY \blk00000001/blk00000353 (
.CI(\blk00000001/sig000000e0 ),
.LI(\blk00000001/sig000000df ),
.O(\blk00000001/sig00000591 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000352 (
.I0(\blk00000001/sig000006de ),
.I1(\blk00000001/sig000006c5 ),
.O(\blk00000001/sig000000dd )
);
MUXCY \blk00000001/blk00000351 (
.CI(\blk00000001/sig000000de ),
.DI(\blk00000001/sig000006de ),
.S(\blk00000001/sig000000dd ),
.O(\blk00000001/sig000000dc )
);
XORCY \blk00000001/blk00000350 (
.CI(\blk00000001/sig000000de ),
.LI(\blk00000001/sig000000dd ),
.O(\blk00000001/sig00000592 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000034f (
.I0(\blk00000001/sig000006df ),
.I1(\blk00000001/sig000006c6 ),
.O(\blk00000001/sig000000db )
);
MUXCY \blk00000001/blk0000034e (
.CI(\blk00000001/sig000000dc ),
.DI(\blk00000001/sig000006df ),
.S(\blk00000001/sig000000db ),
.O(\blk00000001/sig000000da )
);
XORCY \blk00000001/blk0000034d (
.CI(\blk00000001/sig000000dc ),
.LI(\blk00000001/sig000000db ),
.O(\blk00000001/sig00000593 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000034c (
.I0(\blk00000001/sig000006e0 ),
.I1(\blk00000001/sig000006c7 ),
.O(\blk00000001/sig000000d9 )
);
MUXCY \blk00000001/blk0000034b (
.CI(\blk00000001/sig000000da ),
.DI(\blk00000001/sig000006e0 ),
.S(\blk00000001/sig000000d9 ),
.O(\blk00000001/sig000000d8 )
);
XORCY \blk00000001/blk0000034a (
.CI(\blk00000001/sig000000da ),
.LI(\blk00000001/sig000000d9 ),
.O(\blk00000001/sig00000594 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000349 (
.I0(\blk00000001/sig000006e1 ),
.I1(\blk00000001/sig000006c8 ),
.O(\blk00000001/sig000000d7 )
);
MUXCY \blk00000001/blk00000348 (
.CI(\blk00000001/sig000000d8 ),
.DI(\blk00000001/sig000006e1 ),
.S(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig000000d6 )
);
XORCY \blk00000001/blk00000347 (
.CI(\blk00000001/sig000000d8 ),
.LI(\blk00000001/sig000000d7 ),
.O(\blk00000001/sig00000595 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000346 (
.I0(\blk00000001/sig000006e2 ),
.I1(\blk00000001/sig000006c9 ),
.O(\blk00000001/sig000000d5 )
);
MUXCY \blk00000001/blk00000345 (
.CI(\blk00000001/sig000000d6 ),
.DI(\blk00000001/sig000006e2 ),
.S(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig000000d4 )
);
XORCY \blk00000001/blk00000344 (
.CI(\blk00000001/sig000000d6 ),
.LI(\blk00000001/sig000000d5 ),
.O(\blk00000001/sig00000596 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000343 (
.I0(\blk00000001/sig000006e3 ),
.I1(\blk00000001/sig000006ca ),
.O(\blk00000001/sig000000d3 )
);
MUXCY \blk00000001/blk00000342 (
.CI(\blk00000001/sig000000d4 ),
.DI(\blk00000001/sig000006e3 ),
.S(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig000000d2 )
);
XORCY \blk00000001/blk00000341 (
.CI(\blk00000001/sig000000d4 ),
.LI(\blk00000001/sig000000d3 ),
.O(\blk00000001/sig00000597 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000340 (
.I0(\blk00000001/sig000006e4 ),
.I1(\blk00000001/sig000006cb ),
.O(\blk00000001/sig000000d1 )
);
MUXCY \blk00000001/blk0000033f (
.CI(\blk00000001/sig000000d2 ),
.DI(\blk00000001/sig000006e4 ),
.S(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig000000d0 )
);
XORCY \blk00000001/blk0000033e (
.CI(\blk00000001/sig000000d2 ),
.LI(\blk00000001/sig000000d1 ),
.O(\blk00000001/sig00000598 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000033d (
.I0(\blk00000001/sig000006e5 ),
.I1(\blk00000001/sig000006cc ),
.O(\blk00000001/sig000000cf )
);
MUXCY \blk00000001/blk0000033c (
.CI(\blk00000001/sig000000d0 ),
.DI(\blk00000001/sig000006e5 ),
.S(\blk00000001/sig000000cf ),
.O(\blk00000001/sig000000ce )
);
XORCY \blk00000001/blk0000033b (
.CI(\blk00000001/sig000000d0 ),
.LI(\blk00000001/sig000000cf ),
.O(\blk00000001/sig00000599 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000033a (
.I0(\blk00000001/sig000006e6 ),
.I1(\blk00000001/sig000006cd ),
.O(\blk00000001/sig000000cd )
);
MUXCY \blk00000001/blk00000339 (
.CI(\blk00000001/sig000000ce ),
.DI(\blk00000001/sig000006e6 ),
.S(\blk00000001/sig000000cd ),
.O(\blk00000001/sig000000cc )
);
XORCY \blk00000001/blk00000338 (
.CI(\blk00000001/sig000000ce ),
.LI(\blk00000001/sig000000cd ),
.O(\blk00000001/sig0000059a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000337 (
.I0(\blk00000001/sig000006e7 ),
.I1(\blk00000001/sig000006ce ),
.O(\blk00000001/sig000000cb )
);
MUXCY \blk00000001/blk00000336 (
.CI(\blk00000001/sig000000cc ),
.DI(\blk00000001/sig000006e7 ),
.S(\blk00000001/sig000000cb ),
.O(\blk00000001/sig000000ca )
);
XORCY \blk00000001/blk00000335 (
.CI(\blk00000001/sig000000cc ),
.LI(\blk00000001/sig000000cb ),
.O(\blk00000001/sig0000059b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000334 (
.I0(\blk00000001/sig000006cf ),
.I1(\blk00000001/sig000006e8 ),
.O(\blk00000001/sig000000c9 )
);
MUXCY \blk00000001/blk00000333 (
.CI(\blk00000001/sig000000ca ),
.DI(\blk00000001/sig000006e8 ),
.S(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig000000c8 )
);
XORCY \blk00000001/blk00000332 (
.CI(\blk00000001/sig000000ca ),
.LI(\blk00000001/sig000000c9 ),
.O(\blk00000001/sig0000059c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000331 (
.I0(\blk00000001/sig000006d0 ),
.I1(\blk00000001/sig000006e8 ),
.O(\blk00000001/sig000000c7 )
);
MUXCY \blk00000001/blk00000330 (
.CI(\blk00000001/sig000000c8 ),
.DI(\blk00000001/sig000006e8 ),
.S(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig000000c6 )
);
XORCY \blk00000001/blk0000032f (
.CI(\blk00000001/sig000000c8 ),
.LI(\blk00000001/sig000000c7 ),
.O(\blk00000001/sig0000059d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000032e (
.I0(\blk00000001/sig000006d1 ),
.I1(\blk00000001/sig000006e8 ),
.O(\blk00000001/sig000000c5 )
);
MUXCY \blk00000001/blk0000032d (
.CI(\blk00000001/sig000000c6 ),
.DI(\blk00000001/sig000006e8 ),
.S(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig000000c4 )
);
XORCY \blk00000001/blk0000032c (
.CI(\blk00000001/sig000000c6 ),
.LI(\blk00000001/sig000000c5 ),
.O(\blk00000001/sig0000059e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000032b (
.I0(\blk00000001/sig000006e8 ),
.I1(\blk00000001/sig000006d2 ),
.O(\blk00000001/sig000000c3 )
);
MUXCY \blk00000001/blk0000032a (
.CI(\blk00000001/sig000000c4 ),
.DI(\blk00000001/sig000006e8 ),
.S(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig000000c2 )
);
XORCY \blk00000001/blk00000329 (
.CI(\blk00000001/sig000000c4 ),
.LI(\blk00000001/sig000000c3 ),
.O(\blk00000001/sig0000059f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000328 (
.I0(\blk00000001/sig000006e8 ),
.I1(\blk00000001/sig000006d3 ),
.O(\blk00000001/sig000000c1 )
);
MUXCY \blk00000001/blk00000327 (
.CI(\blk00000001/sig000000c2 ),
.DI(\blk00000001/sig000006e8 ),
.S(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000000c0 )
);
XORCY \blk00000001/blk00000326 (
.CI(\blk00000001/sig000000c2 ),
.LI(\blk00000001/sig000000c1 ),
.O(\blk00000001/sig000005a0 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000325 (
.I0(\blk00000001/sig000006e8 ),
.I1(\blk00000001/sig000006d3 ),
.O(\blk00000001/sig000000bf )
);
XORCY \blk00000001/blk00000324 (
.CI(\blk00000001/sig000000c0 ),
.LI(\blk00000001/sig000000bf ),
.O(\blk00000001/sig000005a1 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000323 (
.I0(\blk00000001/sig00000692 ),
.I1(\blk00000001/sig00000672 ),
.O(\blk00000001/sig000000be )
);
MUXCY \blk00000001/blk00000322 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig00000692 ),
.S(\blk00000001/sig000000be ),
.O(\blk00000001/sig000000bd )
);
XORCY \blk00000001/blk00000321 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig000000be ),
.O(\blk00000001/sig0000056b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000320 (
.I0(\blk00000001/sig00000693 ),
.I1(\blk00000001/sig00000673 ),
.O(\blk00000001/sig000000bc )
);
MUXCY \blk00000001/blk0000031f (
.CI(\blk00000001/sig000000bd ),
.DI(\blk00000001/sig00000693 ),
.S(\blk00000001/sig000000bc ),
.O(\blk00000001/sig000000bb )
);
XORCY \blk00000001/blk0000031e (
.CI(\blk00000001/sig000000bd ),
.LI(\blk00000001/sig000000bc ),
.O(\blk00000001/sig0000056c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000031d (
.I0(\blk00000001/sig00000694 ),
.I1(\blk00000001/sig00000674 ),
.O(\blk00000001/sig000000ba )
);
MUXCY \blk00000001/blk0000031c (
.CI(\blk00000001/sig000000bb ),
.DI(\blk00000001/sig00000694 ),
.S(\blk00000001/sig000000ba ),
.O(\blk00000001/sig000000b9 )
);
XORCY \blk00000001/blk0000031b (
.CI(\blk00000001/sig000000bb ),
.LI(\blk00000001/sig000000ba ),
.O(\blk00000001/sig0000056d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000031a (
.I0(\blk00000001/sig00000695 ),
.I1(\blk00000001/sig00000675 ),
.O(\blk00000001/sig000000b8 )
);
MUXCY \blk00000001/blk00000319 (
.CI(\blk00000001/sig000000b9 ),
.DI(\blk00000001/sig00000695 ),
.S(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig000000b7 )
);
XORCY \blk00000001/blk00000318 (
.CI(\blk00000001/sig000000b9 ),
.LI(\blk00000001/sig000000b8 ),
.O(\blk00000001/sig0000056e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000317 (
.I0(\blk00000001/sig00000696 ),
.I1(\blk00000001/sig00000676 ),
.O(\blk00000001/sig000000b6 )
);
MUXCY \blk00000001/blk00000316 (
.CI(\blk00000001/sig000000b7 ),
.DI(\blk00000001/sig00000696 ),
.S(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig000000b5 )
);
XORCY \blk00000001/blk00000315 (
.CI(\blk00000001/sig000000b7 ),
.LI(\blk00000001/sig000000b6 ),
.O(\blk00000001/sig0000056f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000314 (
.I0(\blk00000001/sig00000697 ),
.I1(\blk00000001/sig00000677 ),
.O(\blk00000001/sig000000b4 )
);
MUXCY \blk00000001/blk00000313 (
.CI(\blk00000001/sig000000b5 ),
.DI(\blk00000001/sig00000697 ),
.S(\blk00000001/sig000000b4 ),
.O(\blk00000001/sig000000b3 )
);
XORCY \blk00000001/blk00000312 (
.CI(\blk00000001/sig000000b5 ),
.LI(\blk00000001/sig000000b4 ),
.O(\blk00000001/sig00000570 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000311 (
.I0(\blk00000001/sig00000698 ),
.I1(\blk00000001/sig00000678 ),
.O(\blk00000001/sig000000b2 )
);
MUXCY \blk00000001/blk00000310 (
.CI(\blk00000001/sig000000b3 ),
.DI(\blk00000001/sig00000698 ),
.S(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig000000b1 )
);
XORCY \blk00000001/blk0000030f (
.CI(\blk00000001/sig000000b3 ),
.LI(\blk00000001/sig000000b2 ),
.O(\blk00000001/sig00000571 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000030e (
.I0(\blk00000001/sig00000699 ),
.I1(\blk00000001/sig00000679 ),
.O(\blk00000001/sig000000b0 )
);
MUXCY \blk00000001/blk0000030d (
.CI(\blk00000001/sig000000b1 ),
.DI(\blk00000001/sig00000699 ),
.S(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig000000af )
);
XORCY \blk00000001/blk0000030c (
.CI(\blk00000001/sig000000b1 ),
.LI(\blk00000001/sig000000b0 ),
.O(\blk00000001/sig00000572 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000030b (
.I0(\blk00000001/sig0000069a ),
.I1(\blk00000001/sig0000067a ),
.O(\blk00000001/sig000000ae )
);
MUXCY \blk00000001/blk0000030a (
.CI(\blk00000001/sig000000af ),
.DI(\blk00000001/sig0000069a ),
.S(\blk00000001/sig000000ae ),
.O(\blk00000001/sig000000ad )
);
XORCY \blk00000001/blk00000309 (
.CI(\blk00000001/sig000000af ),
.LI(\blk00000001/sig000000ae ),
.O(\blk00000001/sig00000573 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000308 (
.I0(\blk00000001/sig0000069b ),
.I1(\blk00000001/sig0000067b ),
.O(\blk00000001/sig000000ac )
);
MUXCY \blk00000001/blk00000307 (
.CI(\blk00000001/sig000000ad ),
.DI(\blk00000001/sig0000069b ),
.S(\blk00000001/sig000000ac ),
.O(\blk00000001/sig000000ab )
);
XORCY \blk00000001/blk00000306 (
.CI(\blk00000001/sig000000ad ),
.LI(\blk00000001/sig000000ac ),
.O(\blk00000001/sig00000574 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000305 (
.I0(\blk00000001/sig0000069c ),
.I1(\blk00000001/sig0000067c ),
.O(\blk00000001/sig000000aa )
);
MUXCY \blk00000001/blk00000304 (
.CI(\blk00000001/sig000000ab ),
.DI(\blk00000001/sig0000069c ),
.S(\blk00000001/sig000000aa ),
.O(\blk00000001/sig000000a9 )
);
XORCY \blk00000001/blk00000303 (
.CI(\blk00000001/sig000000ab ),
.LI(\blk00000001/sig000000aa ),
.O(\blk00000001/sig00000575 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000302 (
.I0(\blk00000001/sig0000069d ),
.I1(\blk00000001/sig0000067d ),
.O(\blk00000001/sig000000a8 )
);
MUXCY \blk00000001/blk00000301 (
.CI(\blk00000001/sig000000a9 ),
.DI(\blk00000001/sig0000069d ),
.S(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig000000a7 )
);
XORCY \blk00000001/blk00000300 (
.CI(\blk00000001/sig000000a9 ),
.LI(\blk00000001/sig000000a8 ),
.O(\blk00000001/sig00000576 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ff (
.I0(\blk00000001/sig0000069e ),
.I1(\blk00000001/sig0000067e ),
.O(\blk00000001/sig000000a6 )
);
MUXCY \blk00000001/blk000002fe (
.CI(\blk00000001/sig000000a7 ),
.DI(\blk00000001/sig0000069e ),
.S(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig000000a5 )
);
XORCY \blk00000001/blk000002fd (
.CI(\blk00000001/sig000000a7 ),
.LI(\blk00000001/sig000000a6 ),
.O(\blk00000001/sig00000577 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002fc (
.I0(\blk00000001/sig0000069f ),
.I1(\blk00000001/sig0000067f ),
.O(\blk00000001/sig000000a4 )
);
MUXCY \blk00000001/blk000002fb (
.CI(\blk00000001/sig000000a5 ),
.DI(\blk00000001/sig0000069f ),
.S(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig000000a3 )
);
XORCY \blk00000001/blk000002fa (
.CI(\blk00000001/sig000000a5 ),
.LI(\blk00000001/sig000000a4 ),
.O(\blk00000001/sig00000578 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002f9 (
.I0(\blk00000001/sig000006a0 ),
.I1(\blk00000001/sig00000680 ),
.O(\blk00000001/sig000000a2 )
);
MUXCY \blk00000001/blk000002f8 (
.CI(\blk00000001/sig000000a3 ),
.DI(\blk00000001/sig000006a0 ),
.S(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig000000a1 )
);
XORCY \blk00000001/blk000002f7 (
.CI(\blk00000001/sig000000a3 ),
.LI(\blk00000001/sig000000a2 ),
.O(\blk00000001/sig00000579 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002f6 (
.I0(\blk00000001/sig000006a1 ),
.I1(\blk00000001/sig00000681 ),
.O(\blk00000001/sig000000a0 )
);
MUXCY \blk00000001/blk000002f5 (
.CI(\blk00000001/sig000000a1 ),
.DI(\blk00000001/sig000006a1 ),
.S(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig0000009f )
);
XORCY \blk00000001/blk000002f4 (
.CI(\blk00000001/sig000000a1 ),
.LI(\blk00000001/sig000000a0 ),
.O(\blk00000001/sig0000057a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002f3 (
.I0(\blk00000001/sig000006a2 ),
.I1(\blk00000001/sig00000682 ),
.O(\blk00000001/sig0000009e )
);
MUXCY \blk00000001/blk000002f2 (
.CI(\blk00000001/sig0000009f ),
.DI(\blk00000001/sig000006a2 ),
.S(\blk00000001/sig0000009e ),
.O(\blk00000001/sig0000009d )
);
XORCY \blk00000001/blk000002f1 (
.CI(\blk00000001/sig0000009f ),
.LI(\blk00000001/sig0000009e ),
.O(\blk00000001/sig0000057b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002f0 (
.I0(\blk00000001/sig000006a3 ),
.I1(\blk00000001/sig00000683 ),
.O(\blk00000001/sig0000009c )
);
MUXCY \blk00000001/blk000002ef (
.CI(\blk00000001/sig0000009d ),
.DI(\blk00000001/sig000006a3 ),
.S(\blk00000001/sig0000009c ),
.O(\blk00000001/sig0000009b )
);
XORCY \blk00000001/blk000002ee (
.CI(\blk00000001/sig0000009d ),
.LI(\blk00000001/sig0000009c ),
.O(\blk00000001/sig0000057c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ed (
.I0(\blk00000001/sig000006a4 ),
.I1(\blk00000001/sig00000684 ),
.O(\blk00000001/sig0000009a )
);
MUXCY \blk00000001/blk000002ec (
.CI(\blk00000001/sig0000009b ),
.DI(\blk00000001/sig000006a4 ),
.S(\blk00000001/sig0000009a ),
.O(\blk00000001/sig00000099 )
);
XORCY \blk00000001/blk000002eb (
.CI(\blk00000001/sig0000009b ),
.LI(\blk00000001/sig0000009a ),
.O(\blk00000001/sig0000057d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ea (
.I0(\blk00000001/sig000006a5 ),
.I1(\blk00000001/sig00000685 ),
.O(\blk00000001/sig00000098 )
);
MUXCY \blk00000001/blk000002e9 (
.CI(\blk00000001/sig00000099 ),
.DI(\blk00000001/sig000006a5 ),
.S(\blk00000001/sig00000098 ),
.O(\blk00000001/sig00000097 )
);
XORCY \blk00000001/blk000002e8 (
.CI(\blk00000001/sig00000099 ),
.LI(\blk00000001/sig00000098 ),
.O(\blk00000001/sig0000057e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002e7 (
.I0(\blk00000001/sig00000686 ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig00000096 )
);
MUXCY \blk00000001/blk000002e6 (
.CI(\blk00000001/sig00000097 ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig00000096 ),
.O(\blk00000001/sig00000095 )
);
XORCY \blk00000001/blk000002e5 (
.CI(\blk00000001/sig00000097 ),
.LI(\blk00000001/sig00000096 ),
.O(\blk00000001/sig0000057f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002e4 (
.I0(\blk00000001/sig00000687 ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig00000094 )
);
MUXCY \blk00000001/blk000002e3 (
.CI(\blk00000001/sig00000095 ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000093 )
);
XORCY \blk00000001/blk000002e2 (
.CI(\blk00000001/sig00000095 ),
.LI(\blk00000001/sig00000094 ),
.O(\blk00000001/sig00000580 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002e1 (
.I0(\blk00000001/sig00000688 ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig00000092 )
);
MUXCY \blk00000001/blk000002e0 (
.CI(\blk00000001/sig00000093 ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000091 )
);
XORCY \blk00000001/blk000002df (
.CI(\blk00000001/sig00000093 ),
.LI(\blk00000001/sig00000092 ),
.O(\blk00000001/sig00000581 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002de (
.I0(\blk00000001/sig00000689 ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig00000090 )
);
MUXCY \blk00000001/blk000002dd (
.CI(\blk00000001/sig00000091 ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig00000090 ),
.O(\blk00000001/sig0000008f )
);
XORCY \blk00000001/blk000002dc (
.CI(\blk00000001/sig00000091 ),
.LI(\blk00000001/sig00000090 ),
.O(\blk00000001/sig00000582 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002db (
.I0(\blk00000001/sig0000068a ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig0000008e )
);
MUXCY \blk00000001/blk000002da (
.CI(\blk00000001/sig0000008f ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig0000008e ),
.O(\blk00000001/sig0000008d )
);
XORCY \blk00000001/blk000002d9 (
.CI(\blk00000001/sig0000008f ),
.LI(\blk00000001/sig0000008e ),
.O(\blk00000001/sig00000583 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002d8 (
.I0(\blk00000001/sig0000068b ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig0000008c )
);
MUXCY \blk00000001/blk000002d7 (
.CI(\blk00000001/sig0000008d ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig0000008c ),
.O(\blk00000001/sig0000008b )
);
XORCY \blk00000001/blk000002d6 (
.CI(\blk00000001/sig0000008d ),
.LI(\blk00000001/sig0000008c ),
.O(\blk00000001/sig00000584 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002d5 (
.I0(\blk00000001/sig0000068c ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig0000008a )
);
MUXCY \blk00000001/blk000002d4 (
.CI(\blk00000001/sig0000008b ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000089 )
);
XORCY \blk00000001/blk000002d3 (
.CI(\blk00000001/sig0000008b ),
.LI(\blk00000001/sig0000008a ),
.O(\blk00000001/sig00000585 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002d2 (
.I0(\blk00000001/sig0000068d ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig00000088 )
);
MUXCY \blk00000001/blk000002d1 (
.CI(\blk00000001/sig00000089 ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig00000088 ),
.O(\blk00000001/sig00000087 )
);
XORCY \blk00000001/blk000002d0 (
.CI(\blk00000001/sig00000089 ),
.LI(\blk00000001/sig00000088 ),
.O(\blk00000001/sig00000586 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002cf (
.I0(\blk00000001/sig0000068e ),
.I1(\blk00000001/sig000006a6 ),
.O(\blk00000001/sig00000086 )
);
MUXCY \blk00000001/blk000002ce (
.CI(\blk00000001/sig00000087 ),
.DI(\blk00000001/sig000006a6 ),
.S(\blk00000001/sig00000086 ),
.O(\blk00000001/sig00000085 )
);
XORCY \blk00000001/blk000002cd (
.CI(\blk00000001/sig00000087 ),
.LI(\blk00000001/sig00000086 ),
.O(\blk00000001/sig00000587 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002cc (
.I0(\blk00000001/sig000006a6 ),
.I1(\blk00000001/sig0000068e ),
.O(\blk00000001/sig00000084 )
);
XORCY \blk00000001/blk000002cb (
.CI(\blk00000001/sig00000085 ),
.LI(\blk00000001/sig00000084 ),
.O(\blk00000001/sig00000588 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ca (
.I0(\blk00000001/sig0000065c ),
.I1(\blk00000001/sig0000063d ),
.O(\blk00000001/sig00000083 )
);
MUXCY \blk00000001/blk000002c9 (
.CI(\blk00000001/sig00000054 ),
.DI(\blk00000001/sig0000065c ),
.S(\blk00000001/sig00000083 ),
.O(\blk00000001/sig00000082 )
);
XORCY \blk00000001/blk000002c8 (
.CI(\blk00000001/sig00000054 ),
.LI(\blk00000001/sig00000083 ),
.O(\blk00000001/sig00000553 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002c7 (
.I0(\blk00000001/sig0000065d ),
.I1(\blk00000001/sig0000063e ),
.O(\blk00000001/sig00000081 )
);
MUXCY \blk00000001/blk000002c6 (
.CI(\blk00000001/sig00000082 ),
.DI(\blk00000001/sig0000065d ),
.S(\blk00000001/sig00000081 ),
.O(\blk00000001/sig00000080 )
);
XORCY \blk00000001/blk000002c5 (
.CI(\blk00000001/sig00000082 ),
.LI(\blk00000001/sig00000081 ),
.O(\blk00000001/sig00000554 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002c4 (
.I0(\blk00000001/sig0000065e ),
.I1(\blk00000001/sig0000063f ),
.O(\blk00000001/sig0000007f )
);
MUXCY \blk00000001/blk000002c3 (
.CI(\blk00000001/sig00000080 ),
.DI(\blk00000001/sig0000065e ),
.S(\blk00000001/sig0000007f ),
.O(\blk00000001/sig0000007e )
);
XORCY \blk00000001/blk000002c2 (
.CI(\blk00000001/sig00000080 ),
.LI(\blk00000001/sig0000007f ),
.O(\blk00000001/sig00000555 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002c1 (
.I0(\blk00000001/sig0000065f ),
.I1(\blk00000001/sig00000640 ),
.O(\blk00000001/sig0000007d )
);
MUXCY \blk00000001/blk000002c0 (
.CI(\blk00000001/sig0000007e ),
.DI(\blk00000001/sig0000065f ),
.S(\blk00000001/sig0000007d ),
.O(\blk00000001/sig0000007c )
);
XORCY \blk00000001/blk000002bf (
.CI(\blk00000001/sig0000007e ),
.LI(\blk00000001/sig0000007d ),
.O(\blk00000001/sig00000556 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002be (
.I0(\blk00000001/sig00000660 ),
.I1(\blk00000001/sig00000641 ),
.O(\blk00000001/sig0000007b )
);
MUXCY \blk00000001/blk000002bd (
.CI(\blk00000001/sig0000007c ),
.DI(\blk00000001/sig00000660 ),
.S(\blk00000001/sig0000007b ),
.O(\blk00000001/sig0000007a )
);
XORCY \blk00000001/blk000002bc (
.CI(\blk00000001/sig0000007c ),
.LI(\blk00000001/sig0000007b ),
.O(\blk00000001/sig00000557 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002bb (
.I0(\blk00000001/sig00000661 ),
.I1(\blk00000001/sig00000642 ),
.O(\blk00000001/sig00000079 )
);
MUXCY \blk00000001/blk000002ba (
.CI(\blk00000001/sig0000007a ),
.DI(\blk00000001/sig00000661 ),
.S(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000078 )
);
XORCY \blk00000001/blk000002b9 (
.CI(\blk00000001/sig0000007a ),
.LI(\blk00000001/sig00000079 ),
.O(\blk00000001/sig00000558 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b8 (
.I0(\blk00000001/sig00000662 ),
.I1(\blk00000001/sig00000643 ),
.O(\blk00000001/sig00000077 )
);
MUXCY \blk00000001/blk000002b7 (
.CI(\blk00000001/sig00000078 ),
.DI(\blk00000001/sig00000662 ),
.S(\blk00000001/sig00000077 ),
.O(\blk00000001/sig00000076 )
);
XORCY \blk00000001/blk000002b6 (
.CI(\blk00000001/sig00000078 ),
.LI(\blk00000001/sig00000077 ),
.O(\blk00000001/sig00000559 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b5 (
.I0(\blk00000001/sig00000663 ),
.I1(\blk00000001/sig00000644 ),
.O(\blk00000001/sig00000075 )
);
MUXCY \blk00000001/blk000002b4 (
.CI(\blk00000001/sig00000076 ),
.DI(\blk00000001/sig00000663 ),
.S(\blk00000001/sig00000075 ),
.O(\blk00000001/sig00000074 )
);
XORCY \blk00000001/blk000002b3 (
.CI(\blk00000001/sig00000076 ),
.LI(\blk00000001/sig00000075 ),
.O(\blk00000001/sig0000055a )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002b2 (
.I0(\blk00000001/sig00000664 ),
.I1(\blk00000001/sig00000645 ),
.O(\blk00000001/sig00000073 )
);
MUXCY \blk00000001/blk000002b1 (
.CI(\blk00000001/sig00000074 ),
.DI(\blk00000001/sig00000664 ),
.S(\blk00000001/sig00000073 ),
.O(\blk00000001/sig00000072 )
);
XORCY \blk00000001/blk000002b0 (
.CI(\blk00000001/sig00000074 ),
.LI(\blk00000001/sig00000073 ),
.O(\blk00000001/sig0000055b )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002af (
.I0(\blk00000001/sig00000665 ),
.I1(\blk00000001/sig00000646 ),
.O(\blk00000001/sig00000071 )
);
MUXCY \blk00000001/blk000002ae (
.CI(\blk00000001/sig00000072 ),
.DI(\blk00000001/sig00000665 ),
.S(\blk00000001/sig00000071 ),
.O(\blk00000001/sig00000070 )
);
XORCY \blk00000001/blk000002ad (
.CI(\blk00000001/sig00000072 ),
.LI(\blk00000001/sig00000071 ),
.O(\blk00000001/sig0000055c )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002ac (
.I0(\blk00000001/sig00000666 ),
.I1(\blk00000001/sig00000647 ),
.O(\blk00000001/sig0000006f )
);
MUXCY \blk00000001/blk000002ab (
.CI(\blk00000001/sig00000070 ),
.DI(\blk00000001/sig00000666 ),
.S(\blk00000001/sig0000006f ),
.O(\blk00000001/sig0000006e )
);
XORCY \blk00000001/blk000002aa (
.CI(\blk00000001/sig00000070 ),
.LI(\blk00000001/sig0000006f ),
.O(\blk00000001/sig0000055d )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a9 (
.I0(\blk00000001/sig00000667 ),
.I1(\blk00000001/sig00000648 ),
.O(\blk00000001/sig0000006d )
);
MUXCY \blk00000001/blk000002a8 (
.CI(\blk00000001/sig0000006e ),
.DI(\blk00000001/sig00000667 ),
.S(\blk00000001/sig0000006d ),
.O(\blk00000001/sig0000006c )
);
XORCY \blk00000001/blk000002a7 (
.CI(\blk00000001/sig0000006e ),
.LI(\blk00000001/sig0000006d ),
.O(\blk00000001/sig0000055e )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a6 (
.I0(\blk00000001/sig00000668 ),
.I1(\blk00000001/sig00000649 ),
.O(\blk00000001/sig0000006b )
);
MUXCY \blk00000001/blk000002a5 (
.CI(\blk00000001/sig0000006c ),
.DI(\blk00000001/sig00000668 ),
.S(\blk00000001/sig0000006b ),
.O(\blk00000001/sig0000006a )
);
XORCY \blk00000001/blk000002a4 (
.CI(\blk00000001/sig0000006c ),
.LI(\blk00000001/sig0000006b ),
.O(\blk00000001/sig0000055f )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a3 (
.I0(\blk00000001/sig00000669 ),
.I1(\blk00000001/sig0000064a ),
.O(\blk00000001/sig00000069 )
);
MUXCY \blk00000001/blk000002a2 (
.CI(\blk00000001/sig0000006a ),
.DI(\blk00000001/sig00000669 ),
.S(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000068 )
);
XORCY \blk00000001/blk000002a1 (
.CI(\blk00000001/sig0000006a ),
.LI(\blk00000001/sig00000069 ),
.O(\blk00000001/sig00000560 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk000002a0 (
.I0(\blk00000001/sig0000066a ),
.I1(\blk00000001/sig0000064b ),
.O(\blk00000001/sig00000067 )
);
MUXCY \blk00000001/blk0000029f (
.CI(\blk00000001/sig00000068 ),
.DI(\blk00000001/sig0000066a ),
.S(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000066 )
);
XORCY \blk00000001/blk0000029e (
.CI(\blk00000001/sig00000068 ),
.LI(\blk00000001/sig00000067 ),
.O(\blk00000001/sig00000561 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000029d (
.I0(\blk00000001/sig0000066b ),
.I1(\blk00000001/sig0000064c ),
.O(\blk00000001/sig00000065 )
);
MUXCY \blk00000001/blk0000029c (
.CI(\blk00000001/sig00000066 ),
.DI(\blk00000001/sig0000066b ),
.S(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000064 )
);
XORCY \blk00000001/blk0000029b (
.CI(\blk00000001/sig00000066 ),
.LI(\blk00000001/sig00000065 ),
.O(\blk00000001/sig00000562 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000029a (
.I0(\blk00000001/sig0000066c ),
.I1(\blk00000001/sig0000064d ),
.O(\blk00000001/sig00000063 )
);
MUXCY \blk00000001/blk00000299 (
.CI(\blk00000001/sig00000064 ),
.DI(\blk00000001/sig0000066c ),
.S(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000062 )
);
XORCY \blk00000001/blk00000298 (
.CI(\blk00000001/sig00000064 ),
.LI(\blk00000001/sig00000063 ),
.O(\blk00000001/sig00000563 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000297 (
.I0(\blk00000001/sig0000066d ),
.I1(\blk00000001/sig0000064e ),
.O(\blk00000001/sig00000061 )
);
MUXCY \blk00000001/blk00000296 (
.CI(\blk00000001/sig00000062 ),
.DI(\blk00000001/sig0000066d ),
.S(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000060 )
);
XORCY \blk00000001/blk00000295 (
.CI(\blk00000001/sig00000062 ),
.LI(\blk00000001/sig00000061 ),
.O(\blk00000001/sig00000564 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000294 (
.I0(\blk00000001/sig0000066e ),
.I1(\blk00000001/sig0000064f ),
.O(\blk00000001/sig0000005f )
);
MUXCY \blk00000001/blk00000293 (
.CI(\blk00000001/sig00000060 ),
.DI(\blk00000001/sig0000066e ),
.S(\blk00000001/sig0000005f ),
.O(\blk00000001/sig0000005e )
);
XORCY \blk00000001/blk00000292 (
.CI(\blk00000001/sig00000060 ),
.LI(\blk00000001/sig0000005f ),
.O(\blk00000001/sig00000565 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000291 (
.I0(\blk00000001/sig0000066f ),
.I1(\blk00000001/sig00000650 ),
.O(\blk00000001/sig0000005d )
);
MUXCY \blk00000001/blk00000290 (
.CI(\blk00000001/sig0000005e ),
.DI(\blk00000001/sig0000066f ),
.S(\blk00000001/sig0000005d ),
.O(\blk00000001/sig0000005c )
);
XORCY \blk00000001/blk0000028f (
.CI(\blk00000001/sig0000005e ),
.LI(\blk00000001/sig0000005d ),
.O(\blk00000001/sig00000566 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000028e (
.I0(\blk00000001/sig00000670 ),
.I1(\blk00000001/sig00000651 ),
.O(\blk00000001/sig0000005b )
);
MUXCY \blk00000001/blk0000028d (
.CI(\blk00000001/sig0000005c ),
.DI(\blk00000001/sig00000670 ),
.S(\blk00000001/sig0000005b ),
.O(\blk00000001/sig0000005a )
);
XORCY \blk00000001/blk0000028c (
.CI(\blk00000001/sig0000005c ),
.LI(\blk00000001/sig0000005b ),
.O(\blk00000001/sig00000567 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk0000028b (
.I0(\blk00000001/sig00000671 ),
.I1(\blk00000001/sig00000652 ),
.O(\blk00000001/sig00000059 )
);
MUXCY \blk00000001/blk0000028a (
.CI(\blk00000001/sig0000005a ),
.DI(\blk00000001/sig00000671 ),
.S(\blk00000001/sig00000059 ),
.O(\blk00000001/sig00000058 )
);
XORCY \blk00000001/blk00000289 (
.CI(\blk00000001/sig0000005a ),
.LI(\blk00000001/sig00000059 ),
.O(\blk00000001/sig00000568 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000288 (
.I0(\blk00000001/sig00000671 ),
.I1(\blk00000001/sig00000653 ),
.O(\blk00000001/sig00000057 )
);
MUXCY \blk00000001/blk00000287 (
.CI(\blk00000001/sig00000058 ),
.DI(\blk00000001/sig00000671 ),
.S(\blk00000001/sig00000057 ),
.O(\blk00000001/sig00000056 )
);
XORCY \blk00000001/blk00000286 (
.CI(\blk00000001/sig00000058 ),
.LI(\blk00000001/sig00000057 ),
.O(\blk00000001/sig00000569 )
);
LUT2 #(
.INIT ( 4'h6 ))
\blk00000001/blk00000285 (
.I0(\blk00000001/sig00000671 ),
.I1(\blk00000001/sig00000654 ),
.O(\blk00000001/sig00000055 )
);
XORCY \blk00000001/blk00000284 (
.CI(\blk00000001/sig00000056 ),
.LI(\blk00000001/sig00000055 ),
.O(\blk00000001/sig0000056a )
);
MULT_AND \blk00000001/blk00000283 (
.I0(b[0]),
.I1(a[0]),
.LO(\blk00000001/sig00000551 )
);
MULT_AND \blk00000001/blk00000282 (
.I0(b[1]),
.I1(a[0]),
.LO(\blk00000001/sig00000550 )
);
MULT_AND \blk00000001/blk00000281 (
.I0(b[2]),
.I1(a[0]),
.LO(\blk00000001/sig0000054e )
);
MULT_AND \blk00000001/blk00000280 (
.I0(b[3]),
.I1(a[0]),
.LO(\blk00000001/sig0000054d )
);
MULT_AND \blk00000001/blk0000027f (
.I0(b[4]),
.I1(a[0]),
.LO(\blk00000001/sig0000054b )
);
MULT_AND \blk00000001/blk0000027e (
.I0(b[5]),
.I1(a[0]),
.LO(\blk00000001/sig0000054a )
);
MULT_AND \blk00000001/blk0000027d (
.I0(b[6]),
.I1(a[0]),
.LO(\blk00000001/sig00000548 )
);
MULT_AND \blk00000001/blk0000027c (
.I0(b[7]),
.I1(a[0]),
.LO(\blk00000001/sig00000547 )
);
MULT_AND \blk00000001/blk0000027b (
.I0(b[8]),
.I1(a[0]),
.LO(\blk00000001/sig00000545 )
);
MULT_AND \blk00000001/blk0000027a (
.I0(b[9]),
.I1(a[0]),
.LO(\blk00000001/sig00000544 )
);
MULT_AND \blk00000001/blk00000279 (
.I0(b[10]),
.I1(a[0]),
.LO(\blk00000001/sig00000542 )
);
MULT_AND \blk00000001/blk00000278 (
.I0(b[11]),
.I1(a[0]),
.LO(\blk00000001/sig00000541 )
);
MULT_AND \blk00000001/blk00000277 (
.I0(b[12]),
.I1(a[0]),
.LO(\blk00000001/sig0000053f )
);
MULT_AND \blk00000001/blk00000276 (
.I0(b[13]),
.I1(a[0]),
.LO(\blk00000001/sig0000053e )
);
MULT_AND \blk00000001/blk00000275 (
.I0(b[14]),
.I1(a[0]),
.LO(\blk00000001/sig0000053c )
);
MULT_AND \blk00000001/blk00000274 (
.I0(b[15]),
.I1(a[0]),
.LO(\blk00000001/sig0000053b )
);
MULT_AND \blk00000001/blk00000273 (
.I0(b[16]),
.I1(a[0]),
.LO(\blk00000001/sig00000539 )
);
MULT_AND \blk00000001/blk00000272 (
.I0(b[17]),
.I1(a[0]),
.LO(\blk00000001/sig00000538 )
);
MULT_AND \blk00000001/blk00000271 (
.I0(b[18]),
.I1(a[0]),
.LO(\blk00000001/sig00000537 )
);
MULT_AND \blk00000001/blk00000270 (
.I0(b[1]),
.I1(a[1]),
.LO(\blk00000001/sig00000536 )
);
MULT_AND \blk00000001/blk0000026f (
.I0(b[3]),
.I1(a[1]),
.LO(\blk00000001/sig00000535 )
);
MULT_AND \blk00000001/blk0000026e (
.I0(b[5]),
.I1(a[1]),
.LO(\blk00000001/sig00000534 )
);
MULT_AND \blk00000001/blk0000026d (
.I0(b[7]),
.I1(a[1]),
.LO(\blk00000001/sig00000533 )
);
MULT_AND \blk00000001/blk0000026c (
.I0(b[9]),
.I1(a[1]),
.LO(\blk00000001/sig00000532 )
);
MULT_AND \blk00000001/blk0000026b (
.I0(b[11]),
.I1(a[1]),
.LO(\blk00000001/sig00000531 )
);
MULT_AND \blk00000001/blk0000026a (
.I0(b[13]),
.I1(a[1]),
.LO(\blk00000001/sig00000530 )
);
MULT_AND \blk00000001/blk00000269 (
.I0(b[15]),
.I1(a[1]),
.LO(\blk00000001/sig0000052f )
);
MULT_AND \blk00000001/blk00000268 (
.I0(b[17]),
.I1(a[1]),
.LO(\blk00000001/sig0000052e )
);
MULT_AND \blk00000001/blk00000267 (
.I0(b[18]),
.I1(a[1]),
.LO(\blk00000001/sig0000052d )
);
MULT_AND \blk00000001/blk00000266 (
.I0(b[1]),
.I1(a[2]),
.LO(\blk00000001/sig0000052c )
);
MULT_AND \blk00000001/blk00000265 (
.I0(b[3]),
.I1(a[2]),
.LO(\blk00000001/sig0000052b )
);
MULT_AND \blk00000001/blk00000264 (
.I0(b[5]),
.I1(a[2]),
.LO(\blk00000001/sig0000052a )
);
MULT_AND \blk00000001/blk00000263 (
.I0(b[7]),
.I1(a[2]),
.LO(\blk00000001/sig00000529 )
);
MULT_AND \blk00000001/blk00000262 (
.I0(b[9]),
.I1(a[2]),
.LO(\blk00000001/sig00000528 )
);
MULT_AND \blk00000001/blk00000261 (
.I0(b[11]),
.I1(a[2]),
.LO(\blk00000001/sig00000527 )
);
MULT_AND \blk00000001/blk00000260 (
.I0(b[13]),
.I1(a[2]),
.LO(\blk00000001/sig00000526 )
);
MULT_AND \blk00000001/blk0000025f (
.I0(b[15]),
.I1(a[2]),
.LO(\blk00000001/sig00000525 )
);
MULT_AND \blk00000001/blk0000025e (
.I0(b[17]),
.I1(a[2]),
.LO(\blk00000001/sig00000524 )
);
MULT_AND \blk00000001/blk0000025d (
.I0(b[18]),
.I1(a[2]),
.LO(\blk00000001/sig00000523 )
);
MULT_AND \blk00000001/blk0000025c (
.I0(b[1]),
.I1(a[3]),
.LO(\blk00000001/sig00000522 )
);
MULT_AND \blk00000001/blk0000025b (
.I0(b[3]),
.I1(a[3]),
.LO(\blk00000001/sig00000521 )
);
MULT_AND \blk00000001/blk0000025a (
.I0(b[5]),
.I1(a[3]),
.LO(\blk00000001/sig00000520 )
);
MULT_AND \blk00000001/blk00000259 (
.I0(b[7]),
.I1(a[3]),
.LO(\blk00000001/sig0000051f )
);
MULT_AND \blk00000001/blk00000258 (
.I0(b[9]),
.I1(a[3]),
.LO(\blk00000001/sig0000051e )
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MULT_AND \blk00000001/blk00000257 (
.I0(b[11]),
.I1(a[3]),
.LO(\blk00000001/sig0000051d )
);
MULT_AND \blk00000001/blk00000256 (
.I0(b[13]),
.I1(a[3]),
.LO(\blk00000001/sig0000051c )
);
MULT_AND \blk00000001/blk00000255 (
.I0(b[15]),
.I1(a[3]),
.LO(\blk00000001/sig0000051b )
);
MULT_AND \blk00000001/blk00000254 (
.I0(b[17]),
.I1(a[3]),
.LO(\blk00000001/sig0000051a )
);
MULT_AND \blk00000001/blk00000253 (
.I0(b[18]),
.I1(a[3]),
.LO(\blk00000001/sig00000519 )
);
MULT_AND \blk00000001/blk00000252 (
.I0(b[1]),
.I1(a[4]),
.LO(\blk00000001/sig00000518 )
);
MULT_AND \blk00000001/blk00000251 (
.I0(b[3]),
.I1(a[4]),
.LO(\blk00000001/sig00000517 )
);
MULT_AND \blk00000001/blk00000250 (
.I0(b[5]),
.I1(a[4]),
.LO(\blk00000001/sig00000516 )
);
MULT_AND \blk00000001/blk0000024f (
.I0(b[7]),
.I1(a[4]),
.LO(\blk00000001/sig00000515 )
);
MULT_AND \blk00000001/blk0000024e (
.I0(b[9]),
.I1(a[4]),
.LO(\blk00000001/sig00000514 )
);
MULT_AND \blk00000001/blk0000024d (
.I0(b[11]),
.I1(a[4]),
.LO(\blk00000001/sig00000513 )
);
MULT_AND \blk00000001/blk0000024c (
.I0(b[13]),
.I1(a[4]),
.LO(\blk00000001/sig00000512 )
);
MULT_AND \blk00000001/blk0000024b (
.I0(b[15]),
.I1(a[4]),
.LO(\blk00000001/sig00000511 )
);
MULT_AND \blk00000001/blk0000024a (
.I0(b[17]),
.I1(a[4]),
.LO(\blk00000001/sig00000510 )
);
MULT_AND \blk00000001/blk00000249 (
.I0(b[18]),
.I1(a[4]),
.LO(\blk00000001/sig0000050f )
);
MULT_AND \blk00000001/blk00000248 (
.I0(b[1]),
.I1(a[5]),
.LO(\blk00000001/sig0000050e )
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MULT_AND \blk00000001/blk00000247 (
.I0(b[3]),
.I1(a[5]),
.LO(\blk00000001/sig0000050d )
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MULT_AND \blk00000001/blk00000246 (
.I0(b[5]),
.I1(a[5]),
.LO(\blk00000001/sig0000050c )
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MULT_AND \blk00000001/blk00000245 (
.I0(b[7]),
.I1(a[5]),
.LO(\blk00000001/sig0000050b )
);
MULT_AND \blk00000001/blk00000244 (
.I0(b[9]),
.I1(a[5]),
.LO(\blk00000001/sig0000050a )
);
MULT_AND \blk00000001/blk00000243 (
.I0(b[11]),
.I1(a[5]),
.LO(\blk00000001/sig00000509 )
);
MULT_AND \blk00000001/blk00000242 (
.I0(b[13]),
.I1(a[5]),
.LO(\blk00000001/sig00000508 )
);
MULT_AND \blk00000001/blk00000241 (
.I0(b[15]),
.I1(a[5]),
.LO(\blk00000001/sig00000507 )
);
MULT_AND \blk00000001/blk00000240 (
.I0(b[17]),
.I1(a[5]),
.LO(\blk00000001/sig00000506 )
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MULT_AND \blk00000001/blk0000023f (
.I0(b[18]),
.I1(a[5]),
.LO(\blk00000001/sig00000505 )
);
MULT_AND \blk00000001/blk0000023e (
.I0(b[1]),
.I1(a[6]),
.LO(\blk00000001/sig00000504 )
);
MULT_AND \blk00000001/blk0000023d (
.I0(b[3]),
.I1(a[6]),
.LO(\blk00000001/sig00000503 )
);
MULT_AND \blk00000001/blk0000023c (
.I0(b[5]),
.I1(a[6]),
.LO(\blk00000001/sig00000502 )
);
MULT_AND \blk00000001/blk0000023b (
.I0(b[7]),
.I1(a[6]),
.LO(\blk00000001/sig00000501 )
);
MULT_AND \blk00000001/blk0000023a (
.I0(b[9]),
.I1(a[6]),
.LO(\blk00000001/sig00000500 )
);
MULT_AND \blk00000001/blk00000239 (
.I0(b[11]),
.I1(a[6]),
.LO(\blk00000001/sig000004ff )
);
MULT_AND \blk00000001/blk00000238 (
.I0(b[13]),
.I1(a[6]),
.LO(\blk00000001/sig000004fe )
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MULT_AND \blk00000001/blk00000237 (
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.I1(a[6]),
.LO(\blk00000001/sig000004fd )
);
MULT_AND \blk00000001/blk00000236 (
.I0(b[17]),
.I1(a[6]),
.LO(\blk00000001/sig000004fc )
);
MULT_AND \blk00000001/blk00000235 (
.I0(b[18]),
.I1(a[6]),
.LO(\blk00000001/sig000004fb )
);
MULT_AND \blk00000001/blk00000234 (
.I0(b[1]),
.I1(a[7]),
.LO(\blk00000001/sig000004fa )
);
MULT_AND \blk00000001/blk00000233 (
.I0(b[3]),
.I1(a[7]),
.LO(\blk00000001/sig000004f9 )
);
MULT_AND \blk00000001/blk00000232 (
.I0(b[5]),
.I1(a[7]),
.LO(\blk00000001/sig000004f8 )
);
MULT_AND \blk00000001/blk00000231 (
.I0(b[7]),
.I1(a[7]),
.LO(\blk00000001/sig000004f7 )
);
MULT_AND \blk00000001/blk00000230 (
.I0(b[9]),
.I1(a[7]),
.LO(\blk00000001/sig000004f6 )
);
MULT_AND \blk00000001/blk0000022f (
.I0(b[11]),
.I1(a[7]),
.LO(\blk00000001/sig000004f5 )
);
MULT_AND \blk00000001/blk0000022e (
.I0(b[13]),
.I1(a[7]),
.LO(\blk00000001/sig000004f4 )
);
MULT_AND \blk00000001/blk0000022d (
.I0(b[15]),
.I1(a[7]),
.LO(\blk00000001/sig000004f3 )
);
MULT_AND \blk00000001/blk0000022c (
.I0(b[17]),
.I1(a[7]),
.LO(\blk00000001/sig000004f2 )
);
MULT_AND \blk00000001/blk0000022b (
.I0(b[18]),
.I1(a[7]),
.LO(\blk00000001/sig000004f1 )
);
MULT_AND \blk00000001/blk0000022a (
.I0(b[1]),
.I1(a[8]),
.LO(\blk00000001/sig000004f0 )
);
MULT_AND \blk00000001/blk00000229 (
.I0(b[3]),
.I1(a[8]),
.LO(\blk00000001/sig000004ef )
);
MULT_AND \blk00000001/blk00000228 (
.I0(b[5]),
.I1(a[8]),
.LO(\blk00000001/sig000004ee )
);
MULT_AND \blk00000001/blk00000227 (
.I0(b[7]),
.I1(a[8]),
.LO(\blk00000001/sig000004ed )
);
MULT_AND \blk00000001/blk00000226 (
.I0(b[9]),
.I1(a[8]),
.LO(\blk00000001/sig000004ec )
);
MULT_AND \blk00000001/blk00000225 (
.I0(b[11]),
.I1(a[8]),
.LO(\blk00000001/sig000004eb )
);
MULT_AND \blk00000001/blk00000224 (
.I0(b[13]),
.I1(a[8]),
.LO(\blk00000001/sig000004ea )
);
MULT_AND \blk00000001/blk00000223 (
.I0(b[15]),
.I1(a[8]),
.LO(\blk00000001/sig000004e9 )
);
MULT_AND \blk00000001/blk00000222 (
.I0(b[17]),
.I1(a[8]),
.LO(\blk00000001/sig000004e8 )
);
MULT_AND \blk00000001/blk00000221 (
.I0(b[18]),
.I1(a[8]),
.LO(\blk00000001/sig000004e7 )
);
MULT_AND \blk00000001/blk00000220 (
.I0(b[1]),
.I1(a[9]),
.LO(\blk00000001/sig000004e6 )
);
MULT_AND \blk00000001/blk0000021f (
.I0(b[3]),
.I1(a[9]),
.LO(\blk00000001/sig000004e5 )
);
MULT_AND \blk00000001/blk0000021e (
.I0(b[5]),
.I1(a[9]),
.LO(\blk00000001/sig000004e4 )
);
MULT_AND \blk00000001/blk0000021d (
.I0(b[7]),
.I1(a[9]),
.LO(\blk00000001/sig000004e3 )
);
MULT_AND \blk00000001/blk0000021c (
.I0(b[9]),
.I1(a[9]),
.LO(\blk00000001/sig000004e2 )
);
MULT_AND \blk00000001/blk0000021b (
.I0(b[11]),
.I1(a[9]),
.LO(\blk00000001/sig000004e1 )
);
MULT_AND \blk00000001/blk0000021a (
.I0(b[13]),
.I1(a[9]),
.LO(\blk00000001/sig000004e0 )
);
MULT_AND \blk00000001/blk00000219 (
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.I1(a[9]),
.LO(\blk00000001/sig000004df )
);
MULT_AND \blk00000001/blk00000218 (
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.I1(a[9]),
.LO(\blk00000001/sig000004de )
);
MULT_AND \blk00000001/blk00000217 (
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.I1(a[9]),
.LO(\blk00000001/sig000004dd )
);
MULT_AND \blk00000001/blk00000216 (
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.I1(a[10]),
.LO(\blk00000001/sig000004dc )
);
MULT_AND \blk00000001/blk00000215 (
.I0(b[3]),
.I1(a[10]),
.LO(\blk00000001/sig000004db )
);
MULT_AND \blk00000001/blk00000214 (
.I0(b[5]),
.I1(a[10]),
.LO(\blk00000001/sig000004da )
);
MULT_AND \blk00000001/blk00000213 (
.I0(b[7]),
.I1(a[10]),
.LO(\blk00000001/sig000004d9 )
);
MULT_AND \blk00000001/blk00000212 (
.I0(b[9]),
.I1(a[10]),
.LO(\blk00000001/sig000004d8 )
);
MULT_AND \blk00000001/blk00000211 (
.I0(b[11]),
.I1(a[10]),
.LO(\blk00000001/sig000004d7 )
);
MULT_AND \blk00000001/blk00000210 (
.I0(b[13]),
.I1(a[10]),
.LO(\blk00000001/sig000004d6 )
);
MULT_AND \blk00000001/blk0000020f (
.I0(b[15]),
.I1(a[10]),
.LO(\blk00000001/sig000004d5 )
);
MULT_AND \blk00000001/blk0000020e (
.I0(b[17]),
.I1(a[10]),
.LO(\blk00000001/sig000004d4 )
);
MULT_AND \blk00000001/blk0000020d (
.I0(b[18]),
.I1(a[10]),
.LO(\blk00000001/sig000004d3 )
);
MULT_AND \blk00000001/blk0000020c (
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.I1(a[11]),
.LO(\blk00000001/sig000004d2 )
);
MULT_AND \blk00000001/blk0000020b (
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.LO(\blk00000001/sig000004d1 )
);
MULT_AND \blk00000001/blk0000020a (
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.LO(\blk00000001/sig000004d0 )
);
MULT_AND \blk00000001/blk00000209 (
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);
MULT_AND \blk00000001/blk00000208 (
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);
MULT_AND \blk00000001/blk00000207 (
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);
MULT_AND \blk00000001/blk00000206 (
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.LO(\blk00000001/sig000004cc )
);
MULT_AND \blk00000001/blk00000205 (
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);
MULT_AND \blk00000001/blk00000204 (
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);
MULT_AND \blk00000001/blk00000203 (
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);
MULT_AND \blk00000001/blk00000202 (
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.LO(\blk00000001/sig000004c8 )
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MULT_AND \blk00000001/blk00000201 (
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MULT_AND \blk00000001/blk00000200 (
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);
MULT_AND \blk00000001/blk000001ff (
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.LO(\blk00000001/sig000004c5 )
);
MULT_AND \blk00000001/blk000001fe (
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.LO(\blk00000001/sig000004c4 )
);
MULT_AND \blk00000001/blk000001fd (
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.LO(\blk00000001/sig000004c3 )
);
MULT_AND \blk00000001/blk000001fc (
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.LO(\blk00000001/sig000004c2 )
);
MULT_AND \blk00000001/blk000001fb (
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.LO(\blk00000001/sig000004c1 )
);
MULT_AND \blk00000001/blk000001fa (
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.LO(\blk00000001/sig000004c0 )
);
MULT_AND \blk00000001/blk000001f9 (
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);
MULT_AND \blk00000001/blk000001f8 (
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.LO(\blk00000001/sig000004be )
);
MULT_AND \blk00000001/blk000001f7 (
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);
MULT_AND \blk00000001/blk000001f6 (
.I0(b[5]),
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.LO(\blk00000001/sig000004bc )
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MULT_AND \blk00000001/blk000001f5 (
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MULT_AND \blk00000001/blk000001f4 (
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.LO(\blk00000001/sig000004ba )
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MULT_AND \blk00000001/blk000001f3 (
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.LO(\blk00000001/sig000004b9 )
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MULT_AND \blk00000001/blk000001f2 (
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MULT_AND \blk00000001/blk000001f1 (
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.LO(\blk00000001/sig000004b7 )
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MULT_AND \blk00000001/blk000001f0 (
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);
MULT_AND \blk00000001/blk000001ef (
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.LO(\blk00000001/sig000004b5 )
);
MULT_AND \blk00000001/blk000001ee (
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.LO(\blk00000001/sig000004b4 )
);
MULT_AND \blk00000001/blk000001ed (
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);
MULT_AND \blk00000001/blk000001ec (
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);
MULT_AND \blk00000001/blk000001eb (
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MULT_AND \blk00000001/blk000001ea (
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MULT_AND \blk00000001/blk000001e9 (
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MULT_AND \blk00000001/blk000001e8 (
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);
MULT_AND \blk00000001/blk000001e7 (
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MULT_AND \blk00000001/blk000001e6 (
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MULT_AND \blk00000001/blk000001e5 (
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MULT_AND \blk00000001/blk000001e4 (
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MULT_AND \blk00000001/blk000001e3 (
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MULT_AND \blk00000001/blk000001e2 (
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MULT_AND \blk00000001/blk000001e1 (
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MULT_AND \blk00000001/blk000001e0 (
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MULT_AND \blk00000001/blk000001df (
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);
MULT_AND \blk00000001/blk000001de (
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MULT_AND \blk00000001/blk000001dd (
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MULT_AND \blk00000001/blk000001dc (
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MULT_AND \blk00000001/blk000001db (
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MULT_AND \blk00000001/blk000001da (
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MULT_AND \blk00000001/blk000001d9 (
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MULT_AND \blk00000001/blk000001d8 (
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MULT_AND \blk00000001/blk000001d7 (
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MULT_AND \blk00000001/blk000001d6 (
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MULT_AND \blk00000001/blk000001d5 (
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MULT_AND \blk00000001/blk000001d4 (
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MULT_AND \blk00000001/blk000001d3 (
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MULT_AND \blk00000001/blk000001d2 (
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MULT_AND \blk00000001/blk000001d1 (
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MULT_AND \blk00000001/blk000001d0 (
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MULT_AND \blk00000001/blk000001cf (
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MULT_AND \blk00000001/blk000001ce (
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MULT_AND \blk00000001/blk000001cd (
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MULT_AND \blk00000001/blk000001cc (
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MULT_AND \blk00000001/blk000001cb (
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MULT_AND \blk00000001/blk000001ca (
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MULT_AND \blk00000001/blk000001c9 (
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.LO(\blk00000001/sig0000048f )
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MULT_AND \blk00000001/blk000001c8 (
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.LO(\blk00000001/sig0000048e )
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MULT_AND \blk00000001/blk000001c7 (
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.LO(\blk00000001/sig0000048d )
);
MULT_AND \blk00000001/blk000001c6 (
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);
MULT_AND \blk00000001/blk000001c5 (
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MULT_AND \blk00000001/blk000001c4 (
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.LO(\blk00000001/sig0000048a )
);
MULT_AND \blk00000001/blk000001c3 (
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.I1(a[18]),
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);
MULT_AND \blk00000001/blk000001c2 (
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.I1(a[18]),
.LO(\blk00000001/sig00000488 )
);
MULT_AND \blk00000001/blk000001c1 (
.I0(b[11]),
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MULT_AND \blk00000001/blk000001c0 (
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MULT_AND \blk00000001/blk000001bf (
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MULT_AND \blk00000001/blk000001be (
.I0(b[17]),
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MULT_AND \blk00000001/blk000001bd (
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MULT_AND \blk00000001/blk000001bc (
.I0(b[1]),
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MULT_AND \blk00000001/blk000001bb (
.I0(b[3]),
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MULT_AND \blk00000001/blk000001ba (
.I0(b[5]),
.I1(a[19]),
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MULT_AND \blk00000001/blk000001b9 (
.I0(b[7]),
.I1(a[19]),
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MULT_AND \blk00000001/blk000001b8 (
.I0(b[9]),
.I1(a[19]),
.LO(\blk00000001/sig0000047e )
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MULT_AND \blk00000001/blk000001b7 (
.I0(b[11]),
.I1(a[19]),
.LO(\blk00000001/sig0000047d )
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MULT_AND \blk00000001/blk000001b6 (
.I0(b[13]),
.I1(a[19]),
.LO(\blk00000001/sig0000047c )
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MULT_AND \blk00000001/blk000001b5 (
.I0(b[15]),
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MULT_AND \blk00000001/blk000001b4 (
.I0(b[17]),
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MULT_AND \blk00000001/blk000001b3 (
.I0(b[18]),
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MULT_AND \blk00000001/blk000001b2 (
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MUXCY \blk00000001/blk000001b1 (
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XORCY \blk00000001/blk000001b0 (
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MUXCY \blk00000001/blk000001af (
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MUXCY \blk00000001/blk000001ae (
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XORCY \blk00000001/blk000001ad (
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MUXCY \blk00000001/blk000001ac (
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MUXCY \blk00000001/blk000001ab (
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XORCY \blk00000001/blk000001aa (
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MUXCY \blk00000001/blk000001a9 (
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MUXCY \blk00000001/blk000001a8 (
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XORCY \blk00000001/blk000001a7 (
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MUXCY \blk00000001/blk000001a6 (
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MUXCY \blk00000001/blk000001a5 (
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XORCY \blk00000001/blk000001a4 (
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MUXCY \blk00000001/blk000001a3 (
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MUXCY \blk00000001/blk000001a2 (
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XORCY \blk00000001/blk000001a1 (
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MUXCY \blk00000001/blk000001a0 (
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MUXCY \blk00000001/blk0000019f (
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XORCY \blk00000001/blk0000019e (
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MUXCY \blk00000001/blk0000019d (
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MUXCY \blk00000001/blk0000019c (
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XORCY \blk00000001/blk0000019b (
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MUXCY \blk00000001/blk0000019a (
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MUXCY \blk00000001/blk00000199 (
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XORCY \blk00000001/blk00000198 (
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MUXCY \blk00000001/blk00000197 (
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MUXCY \blk00000001/blk00000196 (
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MUXCY \blk00000001/blk00000195 (
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MUXCY \blk00000001/blk00000194 (
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MUXCY \blk00000001/blk00000193 (
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MUXCY \blk00000001/blk00000192 (
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MUXCY \blk00000001/blk00000191 (
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MUXCY \blk00000001/blk00000190 (
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MUXCY \blk00000001/blk0000018f (
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MUXCY \blk00000001/blk0000018e (
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MUXCY \blk00000001/blk0000018d (
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MUXCY \blk00000001/blk0000018c (
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MUXCY \blk00000001/blk0000018b (
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MUXCY \blk00000001/blk0000018a (
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MUXCY \blk00000001/blk00000189 (
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MUXCY \blk00000001/blk00000188 (
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MUXCY \blk00000001/blk00000187 (
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MUXCY \blk00000001/blk00000186 (
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MUXCY \blk00000001/blk00000185 (
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MUXCY \blk00000001/blk00000184 (
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MUXCY \blk00000001/blk00000183 (
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MUXCY \blk00000001/blk00000182 (
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MUXCY \blk00000001/blk00000181 (
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MUXCY \blk00000001/blk00000180 (
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MUXCY \blk00000001/blk0000017f (
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MUXCY \blk00000001/blk0000017e (
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MUXCY \blk00000001/blk0000017d (
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MUXCY \blk00000001/blk0000017c (
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MUXCY \blk00000001/blk0000017b (
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MUXCY \blk00000001/blk0000017a (
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MUXCY \blk00000001/blk00000179 (
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MUXCY \blk00000001/blk00000178 (
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MUXCY \blk00000001/blk00000177 (
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MUXCY \blk00000001/blk00000176 (
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MUXCY \blk00000001/blk00000175 (
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MUXCY \blk00000001/blk00000174 (
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MUXCY \blk00000001/blk00000173 (
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MUXCY \blk00000001/blk00000172 (
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MUXCY \blk00000001/blk00000171 (
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MUXCY \blk00000001/blk00000170 (
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MUXCY \blk00000001/blk0000016f (
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MUXCY \blk00000001/blk0000016e (
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MUXCY \blk00000001/blk0000016d (
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MUXCY \blk00000001/blk0000016c (
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MUXCY \blk00000001/blk0000016b (
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MUXCY \blk00000001/blk0000016a (
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MUXCY \blk00000001/blk00000169 (
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MUXCY \blk00000001/blk00000168 (
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MUXCY \blk00000001/blk00000167 (
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MUXCY \blk00000001/blk00000166 (
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MUXCY \blk00000001/blk00000165 (
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MUXCY \blk00000001/blk00000164 (
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MUXCY \blk00000001/blk00000163 (
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MUXCY \blk00000001/blk00000162 (
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MUXCY \blk00000001/blk00000161 (
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MUXCY \blk00000001/blk00000160 (
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MUXCY \blk00000001/blk0000015f (
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MUXCY \blk00000001/blk0000015e (
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MUXCY \blk00000001/blk0000015d (
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MUXCY \blk00000001/blk0000015c (
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MUXCY \blk00000001/blk0000015b (
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MUXCY \blk00000001/blk0000015a (
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MUXCY \blk00000001/blk00000159 (
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MUXCY \blk00000001/blk00000158 (
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MUXCY \blk00000001/blk00000157 (
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MUXCY \blk00000001/blk00000156 (
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MUXCY \blk00000001/blk00000155 (
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MUXCY \blk00000001/blk00000154 (
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MUXCY \blk00000001/blk00000153 (
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MUXCY \blk00000001/blk00000152 (
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MUXCY \blk00000001/blk00000151 (
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MUXCY \blk00000001/blk00000150 (
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MUXCY \blk00000001/blk0000014f (
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MUXCY \blk00000001/blk0000014e (
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MUXCY \blk00000001/blk0000014d (
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MUXCY \blk00000001/blk0000014c (
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MUXCY \blk00000001/blk0000014b (
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MUXCY \blk00000001/blk0000014a (
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MUXCY \blk00000001/blk00000149 (
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MUXCY \blk00000001/blk00000148 (
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MUXCY \blk00000001/blk00000147 (
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MUXCY \blk00000001/blk00000146 (
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MUXCY \blk00000001/blk00000145 (
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MUXCY \blk00000001/blk00000144 (
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MUXCY \blk00000001/blk00000143 (
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MUXCY \blk00000001/blk00000142 (
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MUXCY \blk00000001/blk00000141 (
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MUXCY \blk00000001/blk00000140 (
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MUXCY \blk00000001/blk0000013f (
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MUXCY \blk00000001/blk0000013e (
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MUXCY \blk00000001/blk0000013d (
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MUXCY \blk00000001/blk0000013c (
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MUXCY \blk00000001/blk0000013b (
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MUXCY \blk00000001/blk0000013a (
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MUXCY \blk00000001/blk00000139 (
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MUXCY \blk00000001/blk00000138 (
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MUXCY \blk00000001/blk00000137 (
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MUXCY \blk00000001/blk00000136 (
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MUXCY \blk00000001/blk00000135 (
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MUXCY \blk00000001/blk00000134 (
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MUXCY \blk00000001/blk00000133 (
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MUXCY \blk00000001/blk00000132 (
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MUXCY \blk00000001/blk00000131 (
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MUXCY \blk00000001/blk00000130 (
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MUXCY \blk00000001/blk0000012f (
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MUXCY \blk00000001/blk0000012e (
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MUXCY \blk00000001/blk0000012d (
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MUXCY \blk00000001/blk0000012c (
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MUXCY \blk00000001/blk0000012b (
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MUXCY \blk00000001/blk0000012a (
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MUXCY \blk00000001/blk00000129 (
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MUXCY \blk00000001/blk00000128 (
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MUXCY \blk00000001/blk00000127 (
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MUXCY \blk00000001/blk00000126 (
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MUXCY \blk00000001/blk00000125 (
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MUXCY \blk00000001/blk00000124 (
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MUXCY \blk00000001/blk00000123 (
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MUXCY \blk00000001/blk00000122 (
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MUXCY \blk00000001/blk00000121 (
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MUXCY \blk00000001/blk00000120 (
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MUXCY \blk00000001/blk0000011f (
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MUXCY \blk00000001/blk0000011e (
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MUXCY \blk00000001/blk0000011d (
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MUXCY \blk00000001/blk0000011c (
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MUXCY \blk00000001/blk0000011b (
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MUXCY \blk00000001/blk0000011a (
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MUXCY \blk00000001/blk00000119 (
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MUXCY \blk00000001/blk00000118 (
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MUXCY \blk00000001/blk00000117 (
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MUXCY \blk00000001/blk00000116 (
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MUXCY \blk00000001/blk00000115 (
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MUXCY \blk00000001/blk00000114 (
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MUXCY \blk00000001/blk00000113 (
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MUXCY \blk00000001/blk00000112 (
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MUXCY \blk00000001/blk00000111 (
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MUXCY \blk00000001/blk00000110 (
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MUXCY \blk00000001/blk0000010f (
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MUXCY \blk00000001/blk0000010e (
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MUXCY \blk00000001/blk0000010d (
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MUXCY \blk00000001/blk0000010c (
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MUXCY \blk00000001/blk0000010b (
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MUXCY \blk00000001/blk0000010a (
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MUXCY \blk00000001/blk00000109 (
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MUXCY \blk00000001/blk00000108 (
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MUXCY \blk00000001/blk00000107 (
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MUXCY \blk00000001/blk00000106 (
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MUXCY \blk00000001/blk00000105 (
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MUXCY \blk00000001/blk00000104 (
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MUXCY \blk00000001/blk00000103 (
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MUXCY \blk00000001/blk00000102 (
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MUXCY \blk00000001/blk00000101 (
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MUXCY \blk00000001/blk00000100 (
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MUXCY \blk00000001/blk000000ff (
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MUXCY \blk00000001/blk000000fe (
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MUXCY \blk00000001/blk000000fd (
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MUXCY \blk00000001/blk000000fc (
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MUXCY \blk00000001/blk000000fb (
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MUXCY \blk00000001/blk000000fa (
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MUXCY \blk00000001/blk000000f9 (
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MUXCY \blk00000001/blk000000f8 (
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MUXCY \blk00000001/blk000000f7 (
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MUXCY \blk00000001/blk000000f6 (
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MUXCY \blk00000001/blk000000f5 (
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MUXCY \blk00000001/blk000000f4 (
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MUXCY \blk00000001/blk000000f3 (
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MUXCY \blk00000001/blk000000f2 (
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MUXCY \blk00000001/blk000000f1 (
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MUXCY \blk00000001/blk000000f0 (
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MUXCY \blk00000001/blk000000ef (
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MUXCY \blk00000001/blk000000ee (
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MUXCY \blk00000001/blk000000ed (
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MUXCY \blk00000001/blk000000ec (
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MUXCY \blk00000001/blk000000eb (
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MUXCY \blk00000001/blk000000ea (
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MUXCY \blk00000001/blk000000e9 (
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MUXCY \blk00000001/blk000000e8 (
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MUXCY \blk00000001/blk000000e7 (
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MUXCY \blk00000001/blk000000e6 (
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MUXCY \blk00000001/blk000000e5 (
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MUXCY \blk00000001/blk000000e4 (
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MUXCY \blk00000001/blk000000e3 (
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MUXCY \blk00000001/blk000000e2 (
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MUXCY \blk00000001/blk000000e1 (
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MUXCY \blk00000001/blk000000e0 (
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MUXCY \blk00000001/blk000000df (
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MUXCY \blk00000001/blk000000de (
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MUXCY \blk00000001/blk000000dd (
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MUXCY \blk00000001/blk000000dc (
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MUXCY \blk00000001/blk000000db (
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MUXCY \blk00000001/blk000000da (
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MUXCY \blk00000001/blk000000d9 (
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MUXCY \blk00000001/blk000000d8 (
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MUXCY \blk00000001/blk000000d7 (
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XORCY \blk00000001/blk000000d6 (
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XORCY \blk00000001/blk000000d5 (
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XORCY \blk00000001/blk000000d4 (
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XORCY \blk00000001/blk000000d3 (
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XORCY \blk00000001/blk000000d2 (
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XORCY \blk00000001/blk000000d1 (
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XORCY \blk00000001/blk000000d0 (
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XORCY \blk00000001/blk000000cf (
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XORCY \blk00000001/blk000000ce (
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XORCY \blk00000001/blk000000cd (
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XORCY \blk00000001/blk000000cc (
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XORCY \blk00000001/blk000000cb (
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XORCY \blk00000001/blk000000ca (
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XORCY \blk00000001/blk000000c9 (
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XORCY \blk00000001/blk00000033 (
.CI(\blk00000001/sig000003cb ),
.LI(\blk00000001/sig0000025b ),
.O(\blk00000001/sig0000026d )
);
XORCY \blk00000001/blk00000032 (
.CI(\blk00000001/sig000003ca ),
.LI(\blk00000001/sig00000259 ),
.O(\blk00000001/sig0000026b )
);
XORCY \blk00000001/blk00000031 (
.CI(\blk00000001/sig000003c9 ),
.LI(\blk00000001/sig00000257 ),
.O(\blk00000001/sig00000269 )
);
XORCY \blk00000001/blk00000030 (
.CI(\blk00000001/sig000003c8 ),
.LI(\blk00000001/sig00000255 ),
.O(\blk00000001/sig00000267 )
);
XORCY \blk00000001/blk0000002f (
.CI(\blk00000001/sig000003c7 ),
.LI(\blk00000001/sig00000253 ),
.O(\blk00000001/sig00000265 )
);
XORCY \blk00000001/blk0000002e (
.CI(\blk00000001/sig000003c6 ),
.LI(\blk00000001/sig00000251 ),
.O(\blk00000001/sig00000263 )
);
XORCY \blk00000001/blk0000002d (
.CI(\blk00000001/sig000003c5 ),
.LI(\blk00000001/sig000001fc ),
.O(\blk00000001/sig00000262 )
);
XORCY \blk00000001/blk0000002c (
.CI(\blk00000001/sig000003c4 ),
.LI(\blk00000001/sig0000024e ),
.O(\blk00000001/sig00000260 )
);
XORCY \blk00000001/blk0000002b (
.CI(\blk00000001/sig000003c3 ),
.LI(\blk00000001/sig0000024c ),
.O(\blk00000001/sig0000025e )
);
XORCY \blk00000001/blk0000002a (
.CI(\blk00000001/sig000003c2 ),
.LI(\blk00000001/sig0000024a ),
.O(\blk00000001/sig0000025c )
);
XORCY \blk00000001/blk00000029 (
.CI(\blk00000001/sig000003c1 ),
.LI(\blk00000001/sig00000248 ),
.O(\blk00000001/sig0000025a )
);
XORCY \blk00000001/blk00000028 (
.CI(\blk00000001/sig000003c0 ),
.LI(\blk00000001/sig00000246 ),
.O(\blk00000001/sig00000258 )
);
XORCY \blk00000001/blk00000027 (
.CI(\blk00000001/sig000003bf ),
.LI(\blk00000001/sig00000244 ),
.O(\blk00000001/sig00000256 )
);
XORCY \blk00000001/blk00000026 (
.CI(\blk00000001/sig000003be ),
.LI(\blk00000001/sig00000242 ),
.O(\blk00000001/sig00000254 )
);
XORCY \blk00000001/blk00000025 (
.CI(\blk00000001/sig000003bd ),
.LI(\blk00000001/sig00000240 ),
.O(\blk00000001/sig00000252 )
);
XORCY \blk00000001/blk00000024 (
.CI(\blk00000001/sig000003bc ),
.LI(\blk00000001/sig0000023e ),
.O(\blk00000001/sig00000250 )
);
XORCY \blk00000001/blk00000023 (
.CI(\blk00000001/sig000003bb ),
.LI(\blk00000001/sig000001fb ),
.O(\blk00000001/sig0000024f )
);
XORCY \blk00000001/blk00000022 (
.CI(\blk00000001/sig000003ba ),
.LI(\blk00000001/sig0000023b ),
.O(\blk00000001/sig0000024d )
);
XORCY \blk00000001/blk00000021 (
.CI(\blk00000001/sig000003b9 ),
.LI(\blk00000001/sig00000239 ),
.O(\blk00000001/sig0000024b )
);
XORCY \blk00000001/blk00000020 (
.CI(\blk00000001/sig000003b8 ),
.LI(\blk00000001/sig00000237 ),
.O(\blk00000001/sig00000249 )
);
XORCY \blk00000001/blk0000001f (
.CI(\blk00000001/sig000003b7 ),
.LI(\blk00000001/sig00000235 ),
.O(\blk00000001/sig00000247 )
);
XORCY \blk00000001/blk0000001e (
.CI(\blk00000001/sig000003b6 ),
.LI(\blk00000001/sig00000233 ),
.O(\blk00000001/sig00000245 )
);
XORCY \blk00000001/blk0000001d (
.CI(\blk00000001/sig000003b5 ),
.LI(\blk00000001/sig00000231 ),
.O(\blk00000001/sig00000243 )
);
XORCY \blk00000001/blk0000001c (
.CI(\blk00000001/sig000003b4 ),
.LI(\blk00000001/sig0000022f ),
.O(\blk00000001/sig00000241 )
);
XORCY \blk00000001/blk0000001b (
.CI(\blk00000001/sig000003b3 ),
.LI(\blk00000001/sig0000022d ),
.O(\blk00000001/sig0000023f )
);
XORCY \blk00000001/blk0000001a (
.CI(\blk00000001/sig000003b2 ),
.LI(\blk00000001/sig0000022b ),
.O(\blk00000001/sig0000023d )
);
XORCY \blk00000001/blk00000019 (
.CI(\blk00000001/sig000003b1 ),
.LI(\blk00000001/sig000001fa ),
.O(\blk00000001/sig0000023c )
);
XORCY \blk00000001/blk00000018 (
.CI(\blk00000001/sig000003b0 ),
.LI(\blk00000001/sig00000228 ),
.O(\blk00000001/sig0000023a )
);
XORCY \blk00000001/blk00000017 (
.CI(\blk00000001/sig000003af ),
.LI(\blk00000001/sig00000226 ),
.O(\blk00000001/sig00000238 )
);
XORCY \blk00000001/blk00000016 (
.CI(\blk00000001/sig000003ae ),
.LI(\blk00000001/sig00000224 ),
.O(\blk00000001/sig00000236 )
);
XORCY \blk00000001/blk00000015 (
.CI(\blk00000001/sig000003ad ),
.LI(\blk00000001/sig00000222 ),
.O(\blk00000001/sig00000234 )
);
XORCY \blk00000001/blk00000014 (
.CI(\blk00000001/sig000003ac ),
.LI(\blk00000001/sig00000220 ),
.O(\blk00000001/sig00000232 )
);
XORCY \blk00000001/blk00000013 (
.CI(\blk00000001/sig000003ab ),
.LI(\blk00000001/sig0000021e ),
.O(\blk00000001/sig00000230 )
);
XORCY \blk00000001/blk00000012 (
.CI(\blk00000001/sig000003aa ),
.LI(\blk00000001/sig0000021c ),
.O(\blk00000001/sig0000022e )
);
XORCY \blk00000001/blk00000011 (
.CI(\blk00000001/sig000003a9 ),
.LI(\blk00000001/sig0000021a ),
.O(\blk00000001/sig0000022c )
);
XORCY \blk00000001/blk00000010 (
.CI(\blk00000001/sig000003a8 ),
.LI(\blk00000001/sig00000218 ),
.O(\blk00000001/sig0000022a )
);
XORCY \blk00000001/blk0000000f (
.CI(\blk00000001/sig000003a7 ),
.LI(\blk00000001/sig000001f9 ),
.O(\blk00000001/sig00000229 )
);
XORCY \blk00000001/blk0000000e (
.CI(\blk00000001/sig000003a6 ),
.LI(\blk00000001/sig00000215 ),
.O(\blk00000001/sig00000227 )
);
XORCY \blk00000001/blk0000000d (
.CI(\blk00000001/sig000003a5 ),
.LI(\blk00000001/sig00000214 ),
.O(\blk00000001/sig00000225 )
);
XORCY \blk00000001/blk0000000c (
.CI(\blk00000001/sig000003a4 ),
.LI(\blk00000001/sig00000213 ),
.O(\blk00000001/sig00000223 )
);
XORCY \blk00000001/blk0000000b (
.CI(\blk00000001/sig000003a3 ),
.LI(\blk00000001/sig00000212 ),
.O(\blk00000001/sig00000221 )
);
XORCY \blk00000001/blk0000000a (
.CI(\blk00000001/sig000003a2 ),
.LI(\blk00000001/sig00000211 ),
.O(\blk00000001/sig0000021f )
);
XORCY \blk00000001/blk00000009 (
.CI(\blk00000001/sig000003a1 ),
.LI(\blk00000001/sig00000210 ),
.O(\blk00000001/sig0000021d )
);
XORCY \blk00000001/blk00000008 (
.CI(\blk00000001/sig000003a0 ),
.LI(\blk00000001/sig0000020f ),
.O(\blk00000001/sig0000021b )
);
XORCY \blk00000001/blk00000007 (
.CI(\blk00000001/sig0000039f ),
.LI(\blk00000001/sig0000020e ),
.O(\blk00000001/sig00000219 )
);
XORCY \blk00000001/blk00000006 (
.CI(\blk00000001/sig0000039e ),
.LI(\blk00000001/sig0000020d ),
.O(\blk00000001/sig00000217 )
);
XORCY \blk00000001/blk00000005 (
.CI(\blk00000001/sig0000039d ),
.LI(\blk00000001/sig000007d4 ),
.O(\blk00000001/sig00000216 )
);
XORCY \blk00000001/blk00000004 (
.CI(\blk00000001/sig0000039c ),
.LI(\blk00000001/sig000001f8 ),
.O(\blk00000001/sig0000020c )
);
GND \blk00000001/blk00000003 (
.G(\blk00000001/sig00000054 )
);
VCC \blk00000001/blk00000002 (
.P(\blk00000001/sig00000053 )
);
endmodule
|
//-------------------------------------------------------------------
//
// Filename : mode_write.v
// Created On : 2015-01-05
// Author : Yanheng Lu
// Description : mode write back to mode ram
//
//-------------------------------------------------------------------
module mode_write(
clk ,
rstn ,
cnt ,
blockcnt ,
bestmode ,
bestmode16 ,
bestmode32 ,
finish ,
md_we ,
md_waddr ,
md_wdata
);
input rstn;
input clk;
input [5:0] cnt;
input [6:0] blockcnt;
input [5:0] bestmode;
input [5:0] bestmode16;
input [5:0] bestmode32;
input finish;
output md_we;
output [5:0] md_wdata;
output [6:0] md_waddr;
reg md_we;
reg [5:0] md_wdata;
reg [6:0] md_waddr;
always@(posedge clk or negedge rstn)
if(!rstn)
md_waddr <= 7'd0;
else if(md_we)
md_waddr <= md_waddr + 1'b1;
else if(finish)
md_waddr <= 7'd0;
always@(posedge clk or negedge rstn)
if(!rstn)
md_we <= 1'b0;
else if(((blockcnt>7'd1)&&(cnt==6'd11))
||((blockcnt[1:0]==2'b01)&&(cnt==6'd12)&&(blockcnt!=7'd1))
||((blockcnt[3:0]==4'b0001)&&(cnt==6'd13)&&(blockcnt!=7'd1)))// 8x8 & 16x16 & 32x32
md_we <= 1'b1;
else
md_we <= 1'b0;
always@(posedge clk or negedge rstn)
if(!rstn)
md_wdata <= 'd0;
else if(cnt=='d11)
md_wdata <= bestmode;
else if(cnt=='d12)
md_wdata <= bestmode16;
else if(cnt=='d13)
md_wdata <= bestmode32;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__CLKBUF_BEHAVIORAL_V
`define SKY130_FD_SC_LP__CLKBUF_BEHAVIORAL_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__clkbuf (
X,
A
);
// Module ports
output X;
input A;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf0_out_X;
// Name Output Other arguments
buf buf0 (buf0_out_X, A );
buf buf1 (X , buf0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__CLKBUF_BEHAVIORAL_V |
`timescale 1 ns / 1 ps
`default_nettype none
`ifndef VCDFILE
`define VCDFILE "testbench_lcu_tb.vcd"
`endif
module tb;
`include "../../../../library/tbassert.v"
// ============================================================================
reg clk;
reg thresh_sw;
reg [31:0] threshold, threshold_down, counter, counter_down;
initial clk <= 1'd0;
initial thresh_sw <= 1'd0;
initial threshold <= 32'd0;
initial threshold_down <= 32'd0;
initial counter <= 32'd0;
initial counter_down <= 32'd0;
always #5 clk <= !clk;
always #500 thresh_sw <= !thresh_sw;
initial begin
$dumpfile(`VCDFILE);
$dumpvars;
#500000 $finish();
end
// ============================================================================
// DUT
wire gtu, gts, ltu, lts, geu, ges, leu, les, zero, max;
wire gtu_n, gts_n, ltu_n, lts_n, geu_n, ges_n, leu_n, les_n, zero_n, max_n;
top dut
(
.count (clk),
.count_sw (thresh_sw),
.thresh_sw (thresh_sw),
.gtu (gtu),
.gts (gts),
.ltu (ltu),
.lts (lts),
.geu (geu),
.ges (ges),
.leu (leu),
.les (les),
.zero (zero),
.max (max),
.gtu_n (gtu_n),
.gts_n (gts_n),
.ltu_n (ltu_n),
.lts_n (lts_n),
.geu_n (geu_n),
.ges_n (ges_n),
.leu_n (leu_n),
.les_n (les_n),
.zero_n (zero_n),
.max_n (max_n)
);
always @(posedge clk) begin
if (thresh_sw) begin
counter <= counter + 1;
counter_down <= counter_down - 1;
threshold <= counter - 32'd31;
threshold_down <= counter_down + 32'd31;
end else begin
threshold <= threshold + 1;
threshold_down <= threshold_down - 1;
end
tbassert((counter == 32'b0) == zero, counter);
tbassert((counter == 32'hFFFFFFFF) == max, counter);
tbassert((counter > threshold) == gtu, gtu);
tbassert(($signed(counter) > $signed(threshold)) == gts, gts);
tbassert((counter < threshold) == ltu, ltu);
tbassert(($signed(counter) < $signed(threshold)) == lts, lts);
tbassert((counter >= threshold) == geu, geu);
tbassert(($signed(counter) >= $signed(threshold)) == ges, ges);
tbassert((counter <= threshold) == leu, leu);
tbassert(($signed(counter) <= $signed(threshold)) == les, les);
tbassert((counter_down == 32'b0) == zero_n, counter);
tbassert((counter_down == 32'hFFFFFFFF) == max_n, counter);
tbassert((counter_down > threshold_down) == gtu_n, gtu_n);
tbassert(($signed(counter_down) > $signed(threshold_down)) == gts_n, gts_n);
tbassert((counter_down < threshold_down) == ltu_n, ltu_n);
tbassert(($signed(counter_down) < $signed(threshold_down)) == lts_n, lts_n);
tbassert((counter_down >= threshold_down) == geu_n, geu_n);
tbassert(($signed(counter_down) >= $signed(threshold_down)) == ges_n, ges_n);
tbassert((counter_down <= threshold_down) == leu_n, leu_n);
tbassert(($signed(counter_down) <= $signed(threshold_down)) == les_n, les_n);
end
// ============================================================================
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Mon Feb 13 12:45:31 2017
// Host : WK117 running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_auto_cc_0/system_auto_cc_0_sim_netlist.v
// Design : system_auto_cc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a35ticsg324-1L
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_auto_cc_0
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 SI_CLK CLK" *) input s_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 SI_RST RST" *) input s_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [0:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [27:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [127:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [15:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [0:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [0:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [27:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [0:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [127:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 MI_CLK CLK" *) input m_axi_aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 MI_RST RST" *) input m_axi_aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWID" *) output [0:0]m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [27:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLEN" *) output [7:0]m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWSIZE" *) output [2:0]m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWBURST" *) output [1:0]m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWLOCK" *) output [0:0]m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWCACHE" *) output [3:0]m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREGION" *) output [3:0]m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWQOS" *) output [3:0]m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [127:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [15:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WLAST" *) output m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BID" *) input [0:0]m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARID" *) output [0:0]m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [27:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLEN" *) output [7:0]m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARSIZE" *) output [2:0]m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARBURST" *) output [1:0]m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARLOCK" *) output [0:0]m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARCACHE" *) output [3:0]m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREGION" *) output [3:0]m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARQOS" *) output [3:0]m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RID" *) input [0:0]m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [127:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RLAST" *) input m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) output m_axi_rready;
wire m_axi_aclk;
wire [27:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire m_axi_aresetn;
wire [0:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [27:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [0:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [15:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_axi_aclk;
wire [27:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [27:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [127:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [127:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [15:0]s_axi_wstrb;
wire s_axi_wvalid;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_ARADDR_RIGHT = "29" *)
(* C_ARADDR_WIDTH = "28" *)
(* C_ARBURST_RIGHT = "16" *)
(* C_ARBURST_WIDTH = "2" *)
(* C_ARCACHE_RIGHT = "11" *)
(* C_ARCACHE_WIDTH = "4" *)
(* C_ARID_RIGHT = "57" *)
(* C_ARID_WIDTH = "1" *)
(* C_ARLEN_RIGHT = "21" *)
(* C_ARLEN_WIDTH = "8" *)
(* C_ARLOCK_RIGHT = "15" *)
(* C_ARLOCK_WIDTH = "1" *)
(* C_ARPROT_RIGHT = "8" *)
(* C_ARPROT_WIDTH = "3" *)
(* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "4" *)
(* C_ARREGION_RIGHT = "4" *)
(* C_ARREGION_WIDTH = "4" *)
(* C_ARSIZE_RIGHT = "18" *)
(* C_ARSIZE_WIDTH = "3" *)
(* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *)
(* C_AR_WIDTH = "58" *)
(* C_AWADDR_RIGHT = "29" *)
(* C_AWADDR_WIDTH = "28" *)
(* C_AWBURST_RIGHT = "16" *)
(* C_AWBURST_WIDTH = "2" *)
(* C_AWCACHE_RIGHT = "11" *)
(* C_AWCACHE_WIDTH = "4" *)
(* C_AWID_RIGHT = "57" *)
(* C_AWID_WIDTH = "1" *)
(* C_AWLEN_RIGHT = "21" *)
(* C_AWLEN_WIDTH = "8" *)
(* C_AWLOCK_RIGHT = "15" *)
(* C_AWLOCK_WIDTH = "1" *)
(* C_AWPROT_RIGHT = "8" *)
(* C_AWPROT_WIDTH = "3" *)
(* C_AWQOS_RIGHT = "0" *)
(* C_AWQOS_WIDTH = "4" *)
(* C_AWREGION_RIGHT = "4" *)
(* C_AWREGION_WIDTH = "4" *)
(* C_AWSIZE_RIGHT = "18" *)
(* C_AWSIZE_WIDTH = "3" *)
(* C_AWUSER_RIGHT = "0" *)
(* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "58" *)
(* C_AXI_ADDR_WIDTH = "28" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "128" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_IS_ACLK_ASYNC = "1" *)
(* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "1" *)
(* C_BRESP_RIGHT = "0" *)
(* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *)
(* C_BUSER_WIDTH = "0" *)
(* C_B_WIDTH = "3" *)
(* C_FAMILY = "artix7" *)
(* C_FIFO_AR_WIDTH = "58" *)
(* C_FIFO_AW_WIDTH = "58" *)
(* C_FIFO_B_WIDTH = "3" *)
(* C_FIFO_R_WIDTH = "132" *)
(* C_FIFO_W_WIDTH = "145" *)
(* C_M_AXI_ACLK_RATIO = "2" *)
(* C_RDATA_RIGHT = "3" *)
(* C_RDATA_WIDTH = "128" *)
(* C_RID_RIGHT = "131" *)
(* C_RID_WIDTH = "1" *)
(* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "1" *)
(* C_RRESP_RIGHT = "1" *)
(* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *)
(* C_RUSER_WIDTH = "0" *)
(* C_R_WIDTH = "132" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_S_AXI_ACLK_RATIO = "1" *)
(* C_WDATA_RIGHT = "17" *)
(* C_WDATA_WIDTH = "128" *)
(* C_WID_RIGHT = "145" *)
(* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *)
(* C_WLAST_WIDTH = "1" *)
(* C_WSTRB_RIGHT = "1" *)
(* C_WSTRB_WIDTH = "16" *)
(* C_WUSER_RIGHT = "0" *)
(* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "145" *)
(* P_ACLK_RATIO = "2" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_FULLY_REG = "1" *)
(* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *)
(* P_ROUNDING_OFFSET = "0" *)
(* P_SI_LT_MI = "1'b1" *)
(* downgradeipidentifiedwarnings = "yes" *)
system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter inst
(.m_axi_aclk(m_axi_aclk),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_aresetn(m_axi_aresetn),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_ARADDR_RIGHT = "29" *) (* C_ARADDR_WIDTH = "28" *) (* C_ARBURST_RIGHT = "16" *)
(* C_ARBURST_WIDTH = "2" *) (* C_ARCACHE_RIGHT = "11" *) (* C_ARCACHE_WIDTH = "4" *)
(* C_ARID_RIGHT = "57" *) (* C_ARID_WIDTH = "1" *) (* C_ARLEN_RIGHT = "21" *)
(* C_ARLEN_WIDTH = "8" *) (* C_ARLOCK_RIGHT = "15" *) (* C_ARLOCK_WIDTH = "1" *)
(* C_ARPROT_RIGHT = "8" *) (* C_ARPROT_WIDTH = "3" *) (* C_ARQOS_RIGHT = "0" *)
(* C_ARQOS_WIDTH = "4" *) (* C_ARREGION_RIGHT = "4" *) (* C_ARREGION_WIDTH = "4" *)
(* C_ARSIZE_RIGHT = "18" *) (* C_ARSIZE_WIDTH = "3" *) (* C_ARUSER_RIGHT = "0" *)
(* C_ARUSER_WIDTH = "0" *) (* C_AR_WIDTH = "58" *) (* C_AWADDR_RIGHT = "29" *)
(* C_AWADDR_WIDTH = "28" *) (* C_AWBURST_RIGHT = "16" *) (* C_AWBURST_WIDTH = "2" *)
(* C_AWCACHE_RIGHT = "11" *) (* C_AWCACHE_WIDTH = "4" *) (* C_AWID_RIGHT = "57" *)
(* C_AWID_WIDTH = "1" *) (* C_AWLEN_RIGHT = "21" *) (* C_AWLEN_WIDTH = "8" *)
(* C_AWLOCK_RIGHT = "15" *) (* C_AWLOCK_WIDTH = "1" *) (* C_AWPROT_RIGHT = "8" *)
(* C_AWPROT_WIDTH = "3" *) (* C_AWQOS_RIGHT = "0" *) (* C_AWQOS_WIDTH = "4" *)
(* C_AWREGION_RIGHT = "4" *) (* C_AWREGION_WIDTH = "4" *) (* C_AWSIZE_RIGHT = "18" *)
(* C_AWSIZE_WIDTH = "3" *) (* C_AWUSER_RIGHT = "0" *) (* C_AWUSER_WIDTH = "0" *)
(* C_AW_WIDTH = "58" *) (* C_AXI_ADDR_WIDTH = "28" *) (* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "128" *)
(* C_AXI_ID_WIDTH = "1" *) (* C_AXI_IS_ACLK_ASYNC = "1" *) (* C_AXI_PROTOCOL = "0" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_BID_RIGHT = "2" *)
(* C_BID_WIDTH = "1" *) (* C_BRESP_RIGHT = "0" *) (* C_BRESP_WIDTH = "2" *)
(* C_BUSER_RIGHT = "0" *) (* C_BUSER_WIDTH = "0" *) (* C_B_WIDTH = "3" *)
(* C_FAMILY = "artix7" *) (* C_FIFO_AR_WIDTH = "58" *) (* C_FIFO_AW_WIDTH = "58" *)
(* C_FIFO_B_WIDTH = "3" *) (* C_FIFO_R_WIDTH = "132" *) (* C_FIFO_W_WIDTH = "145" *)
(* C_M_AXI_ACLK_RATIO = "2" *) (* C_RDATA_RIGHT = "3" *) (* C_RDATA_WIDTH = "128" *)
(* C_RID_RIGHT = "131" *) (* C_RID_WIDTH = "1" *) (* C_RLAST_RIGHT = "0" *)
(* C_RLAST_WIDTH = "1" *) (* C_RRESP_RIGHT = "1" *) (* C_RRESP_WIDTH = "2" *)
(* C_RUSER_RIGHT = "0" *) (* C_RUSER_WIDTH = "0" *) (* C_R_WIDTH = "132" *)
(* C_SYNCHRONIZER_STAGE = "3" *) (* C_S_AXI_ACLK_RATIO = "1" *) (* C_WDATA_RIGHT = "17" *)
(* C_WDATA_WIDTH = "128" *) (* C_WID_RIGHT = "145" *) (* C_WID_WIDTH = "0" *)
(* C_WLAST_RIGHT = "0" *) (* C_WLAST_WIDTH = "1" *) (* C_WSTRB_RIGHT = "1" *)
(* C_WSTRB_WIDTH = "16" *) (* C_WUSER_RIGHT = "0" *) (* C_WUSER_WIDTH = "0" *)
(* C_W_WIDTH = "145" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* ORIG_REF_NAME = "axi_clock_converter_v2_1_10_axi_clock_converter" *)
(* P_ACLK_RATIO = "2" *) (* P_AXI3 = "1" *) (* P_AXI4 = "0" *)
(* P_AXILITE = "2" *) (* P_FULLY_REG = "1" *) (* P_LIGHT_WT = "0" *)
(* P_LUTRAM_ASYNC = "12" *) (* P_ROUNDING_OFFSET = "0" *) (* P_SI_LT_MI = "1'b1" *)
module system_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
(s_axi_aclk,
s_axi_aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_aclk,
m_axi_aresetn,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
(* keep = "true" *) input s_axi_aclk;
(* keep = "true" *) input s_axi_aresetn;
input [0:0]s_axi_awid;
input [27:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [127:0]s_axi_wdata;
input [15:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [27:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [127:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
(* keep = "true" *) input m_axi_aclk;
(* keep = "true" *) input m_axi_aresetn;
output [0:0]m_axi_awid;
output [27:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [27:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire async_conv_reset_n;
(* RTL_KEEP = "true" *) wire m_axi_aclk;
wire [27:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
(* RTL_KEEP = "true" *) wire m_axi_aresetn;
wire [0:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [27:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [0:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [15:0]m_axi_wstrb;
wire m_axi_wvalid;
(* RTL_KEEP = "true" *) wire s_axi_aclk;
wire [27:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
(* RTL_KEEP = "true" *) wire s_axi_aresetn;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [27:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [127:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [127:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [15:0]s_axi_wstrb;
wire s_axi_wvalid;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED ;
wire \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED ;
wire [4:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED ;
wire [10:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED ;
wire [17:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED ;
wire [7:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED ;
wire [3:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED ;
wire [0:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED ;
wire [9:0]\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
GND GND
(.G(\<const0> ));
(* C_ADD_NGC_CONSTRAINT = "0" *)
(* C_APPLICATION_TYPE_AXIS = "0" *)
(* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *)
(* C_APPLICATION_TYPE_WACH = "0" *)
(* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *)
(* C_AXIS_TDATA_WIDTH = "8" *)
(* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *)
(* C_AXIS_TKEEP_WIDTH = "1" *)
(* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *)
(* C_AXIS_TYPE = "0" *)
(* C_AXI_ADDR_WIDTH = "28" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "128" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_COMMON_CLOCK = "0" *)
(* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *)
(* C_DEFAULT_VALUE = "BlankString" *)
(* C_DIN_WIDTH = "18" *)
(* C_DIN_WIDTH_AXIS = "1" *)
(* C_DIN_WIDTH_RACH = "58" *)
(* C_DIN_WIDTH_RDCH = "132" *)
(* C_DIN_WIDTH_WACH = "58" *)
(* C_DIN_WIDTH_WDCH = "145" *)
(* C_DIN_WIDTH_WRCH = "3" *)
(* C_DOUT_RST_VAL = "0" *)
(* C_DOUT_WIDTH = "18" *)
(* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *)
(* C_EN_SAFETY_CKT = "0" *)
(* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *)
(* C_ERROR_INJECTION_TYPE_RACH = "0" *)
(* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *)
(* C_ERROR_INJECTION_TYPE_WDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *)
(* C_FULL_FLAGS_RST_VAL = "1" *)
(* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *)
(* C_HAS_AXIS_TDATA = "1" *)
(* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *)
(* C_HAS_AXIS_TKEEP = "0" *)
(* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *)
(* C_HAS_AXIS_TSTRB = "0" *)
(* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *)
(* C_HAS_AXI_AWUSER = "0" *)
(* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "1" *)
(* C_HAS_AXI_RD_CHANNEL = "1" *)
(* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *)
(* C_HAS_AXI_WUSER = "0" *)
(* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *)
(* C_HAS_DATA_COUNTS_AXIS = "0" *)
(* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *)
(* C_HAS_DATA_COUNTS_WACH = "0" *)
(* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *)
(* C_HAS_INT_CLK = "0" *)
(* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *)
(* C_HAS_OVERFLOW = "0" *)
(* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *)
(* C_HAS_PROG_FLAGS_RDCH = "0" *)
(* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *)
(* C_HAS_PROG_FLAGS_WRCH = "0" *)
(* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *)
(* C_HAS_RST = "1" *)
(* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *)
(* C_HAS_UNDERFLOW = "0" *)
(* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *)
(* C_HAS_WR_DATA_COUNT = "0" *)
(* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *)
(* C_IMPLEMENTATION_TYPE_AXIS = "11" *)
(* C_IMPLEMENTATION_TYPE_RACH = "12" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WACH = "12" *)
(* C_IMPLEMENTATION_TYPE_WDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "12" *)
(* C_INIT_WR_PNTR_VAL = "0" *)
(* C_INTERFACE_TYPE = "2" *)
(* C_MEMORY_TYPE = "1" *)
(* C_MIF_FILE_NAME = "BlankString" *)
(* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *)
(* C_OVERFLOW_LOW = "0" *)
(* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *)
(* C_PRELOAD_REGS = "0" *)
(* C_PRIM_FIFO_TYPE = "4kx4" *)
(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *)
(* C_PRIM_FIFO_TYPE_RACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_RDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1021" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "13" *)
(* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *)
(* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *)
(* C_PROG_EMPTY_TYPE_RACH = "0" *)
(* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *)
(* C_PROG_EMPTY_TYPE_WDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *)
(* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *)
(* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *)
(* C_PROG_FULL_TYPE_RACH = "0" *)
(* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *)
(* C_PROG_FULL_TYPE_WDCH = "0" *)
(* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *)
(* C_RDCH_TYPE = "0" *)
(* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *)
(* C_RD_FREQ = "1" *)
(* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *)
(* C_REG_SLICE_MODE_RACH = "0" *)
(* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *)
(* C_REG_SLICE_MODE_WDCH = "0" *)
(* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *)
(* C_SYNCHRONIZER_STAGE = "3" *)
(* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *)
(* C_USE_COMMON_UNDERFLOW = "0" *)
(* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *)
(* C_USE_ECC = "0" *)
(* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *)
(* C_USE_ECC_RDCH = "0" *)
(* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *)
(* C_USE_ECC_WRCH = "0" *)
(* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *)
(* C_USE_FWFT_DATA_COUNT = "0" *)
(* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *)
(* C_WACH_TYPE = "0" *)
(* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *)
(* C_WR_ACK_LOW = "0" *)
(* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *)
(* C_WR_DEPTH_AXIS = "1024" *)
(* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "16" *)
(* C_WR_DEPTH_WACH = "16" *)
(* C_WR_DEPTH_WDCH = "16" *)
(* C_WR_DEPTH_WRCH = "16" *)
(* C_WR_FREQ = "1" *)
(* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *)
(* C_WR_PNTR_WIDTH_RACH = "4" *)
(* C_WR_PNTR_WIDTH_RDCH = "4" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *)
(* C_WR_PNTR_WIDTH_WDCH = "4" *)
(* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *)
system_auto_cc_0_fifo_generator_v13_1_3 \gen_clock_conv.gen_async_conv.asyncfifo_axi
(.almost_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED ),
.almost_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED ),
.axi_ar_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED [4:0]),
.axi_ar_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED ),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_injectsbiterr(1'b0),
.axi_ar_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED ),
.axi_ar_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED ),
.axi_ar_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED ),
.axi_ar_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_ar_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED [4:0]),
.axi_ar_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED ),
.axi_ar_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED ),
.axi_ar_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED [4:0]),
.axi_aw_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED [4:0]),
.axi_aw_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED ),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED ),
.axi_aw_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED ),
.axi_aw_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED ),
.axi_aw_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_aw_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED [4:0]),
.axi_aw_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED ),
.axi_aw_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED ),
.axi_aw_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED [4:0]),
.axi_b_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED [4:0]),
.axi_b_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED ),
.axi_b_injectdbiterr(1'b0),
.axi_b_injectsbiterr(1'b0),
.axi_b_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED ),
.axi_b_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED ),
.axi_b_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED ),
.axi_b_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_b_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED [4:0]),
.axi_b_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED ),
.axi_b_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED ),
.axi_b_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED [4:0]),
.axi_r_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED [4:0]),
.axi_r_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED ),
.axi_r_injectdbiterr(1'b0),
.axi_r_injectsbiterr(1'b0),
.axi_r_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED ),
.axi_r_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED ),
.axi_r_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_r_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED ),
.axi_r_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_r_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED [4:0]),
.axi_r_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED ),
.axi_r_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED ),
.axi_r_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED [4:0]),
.axi_w_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED [4:0]),
.axi_w_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED ),
.axi_w_injectdbiterr(1'b0),
.axi_w_injectsbiterr(1'b0),
.axi_w_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED ),
.axi_w_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED ),
.axi_w_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_w_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED ),
.axi_w_prog_full_thresh({1'b0,1'b0,1'b0,1'b0}),
.axi_w_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED [4:0]),
.axi_w_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED ),
.axi_w_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED ),
.axi_w_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED [4:0]),
.axis_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED [10:0]),
.axis_dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED ),
.axis_injectdbiterr(1'b0),
.axis_injectsbiterr(1'b0),
.axis_overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED ),
.axis_prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED ),
.axis_prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED ),
.axis_prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.axis_rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED [10:0]),
.axis_sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED ),
.axis_underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED ),
.axis_wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED [10:0]),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED [9:0]),
.dbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED ),
.din({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.dout(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED [17:0]),
.empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED ),
.full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED ),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.int_clk(1'b0),
.m_aclk(m_axi_aclk),
.m_aclk_en(1'b1),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(m_axi_arburst),
.m_axi_arcache(m_axi_arcache),
.m_axi_arid(m_axi_arid),
.m_axi_arlen(m_axi_arlen),
.m_axi_arlock(m_axi_arlock),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(m_axi_arqos),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(m_axi_arregion),
.m_axi_arsize(m_axi_arsize),
.m_axi_aruser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED [0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(m_axi_awburst),
.m_axi_awcache(m_axi_awcache),
.m_axi_awid(m_axi_awid),
.m_axi_awlen(m_axi_awlen),
.m_axi_awlock(m_axi_awlock),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(m_axi_awqos),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(m_axi_awregion),
.m_axi_awsize(m_axi_awsize),
.m_axi_awuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED [0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(m_axi_rid),
.m_axi_rlast(m_axi_rlast),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED [0]),
.m_axi_wlast(m_axi_wlast),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED [0]),
.m_axi_wvalid(m_axi_wvalid),
.m_axis_tdata(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED [7:0]),
.m_axis_tdest(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED [0]),
.m_axis_tid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED [0]),
.m_axis_tkeep(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED [0]),
.m_axis_tlast(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED ),
.m_axis_tready(1'b0),
.m_axis_tstrb(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED [0]),
.m_axis_tuser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED [3:0]),
.m_axis_tvalid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED ),
.overflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED ),
.prog_empty(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED ),
.prog_empty_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_empty_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED ),
.prog_full_thresh({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_assert({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.prog_full_thresh_negate({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.rd_clk(1'b0),
.rd_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED [9:0]),
.rd_en(1'b0),
.rd_rst(1'b0),
.rd_rst_busy(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED ),
.rst(1'b0),
.s_aclk(s_axi_aclk),
.s_aclk_en(1'b1),
.s_aresetn(async_conv_reset_n),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED [0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED [0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid),
.s_axis_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axis_tdest(1'b0),
.s_axis_tid(1'b0),
.s_axis_tkeep(1'b0),
.s_axis_tlast(1'b0),
.s_axis_tready(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED ),
.s_axis_tstrb(1'b0),
.s_axis_tuser({1'b0,1'b0,1'b0,1'b0}),
.s_axis_tvalid(1'b0),
.sbiterr(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED ),
.sleep(1'b0),
.srst(1'b0),
.underflow(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED ),
.valid(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED ),
.wr_ack(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED ),
.wr_clk(1'b0),
.wr_data_count(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED [9:0]),
.wr_en(1'b0),
.wr_rst(1'b0),
.wr_rst_busy(\NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED ));
LUT2 #(
.INIT(4'h8))
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1
(.I0(s_axi_aresetn),
.I1(m_axi_aresetn),
.O(async_conv_reset_n));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs
(out,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_full_fb_i_reg_1,
Q,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
m_aclk,
AR,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
output ram_empty_i_reg;
output [3:0]ram_empty_i_reg_0;
input ram_full_fb_i_reg_1;
input [3:0]Q;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [2:0]\gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input m_aclk;
input [0:0]AR;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire [3:0]ram_empty_i_reg_0;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2_n_0;
wire ram_full_i_i_4_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized1 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized3 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized5 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.m_aclk(m_aclk),
.out(p_8_out));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(ram_empty_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(ram_empty_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(ram_empty_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(ram_empty_i_reg_0[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__2
(.I0(ram_empty_i_reg_0[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(ram_empty_i_reg_0[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(ram_empty_i_reg_0[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1
(.I0(ram_full_i_i_2_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(Q[3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4
(.I0(p_23_out[2]),
.I1(Q[2]),
.I2(p_23_out[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_27
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
D,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
\gc0.count_d1_reg[2] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [0:0]D;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]\gc0.count_d1_reg[2] ;
wire [0:0]AR;
wire [0:0]D;
wire [3:0]Q;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [2:0]\gc0.count_d1_reg[2] ;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire [1:1]gray2bin;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire p_0_out;
wire [2:0]p_23_out_1;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__1_n_0;
wire ram_full_i_i_4__1_n_0;
wire [3:0]rd_pntr_gc;
wire s_aclk;
wire [3:0]wr_pntr_gc;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(gray2bin));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_42 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q(wr_pntr_gc),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized1_43 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q(rd_pntr_gc),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_44 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized3_45 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_46 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(p_0_out),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
system_auto_cc_0_synchronizer_ff__parameterized5_47 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out_1[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out_1[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out_1[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [0]),
.Q(rd_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [1]),
.Q(rd_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[2] [2]),
.Q(rd_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(rd_pntr_gc[3]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(gray2bin),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(p_0_out),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(wr_pntr_gc[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(wr_pntr_gc[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(wr_pntr_gc[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(wr_pntr_gc[3]));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__1
(.I0(ram_full_i_i_2__1_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__1_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__1
(.I0(p_23_out_1[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out_1[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out_1[0]),
.O(ram_full_i_i_2__1_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__1
(.I0(p_23_out_1[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out_1[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out_1[0]),
.O(ram_full_i_i_4__1_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_48
(out,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
ram_empty_i_reg,
ram_empty_i_reg_0,
ram_full_fb_i_reg_1,
Q,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
m_aclk,
AR,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
output ram_empty_i_reg;
output [3:0]ram_empty_i_reg_0;
input ram_full_fb_i_reg_1;
input [3:0]Q;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [2:0]\gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input m_aclk;
input [0:0]AR;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire [3:0]ram_empty_i_reg_0;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__0_n_0;
wire ram_full_i_i_4__0_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_63 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized1_64 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_65 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized3_66 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_67 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized5_68 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.m_aclk(m_aclk),
.out(p_8_out));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(ram_empty_i_reg_0[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(ram_empty_i_reg_0[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(ram_empty_i_reg_0[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(ram_empty_i_reg_0[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__3
(.I0(ram_empty_i_reg_0[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(ram_empty_i_reg_0[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(ram_empty_i_reg_0[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__0
(.I0(ram_full_i_i_2__0_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(Q[3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__0_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__0
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__0_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__0
(.I0(p_23_out[2]),
.I1(Q[2]),
.I2(p_23_out[1]),
.I3(Q[1]),
.I4(Q[0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__0_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_6
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__2_n_0;
wire ram_full_i_i_4__2_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_21 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized1_22 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_23 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized3_24 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_25 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
system_auto_cc_0_synchronizer_ff__parameterized5_26 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__0
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__2
(.I0(ram_full_i_i_2__2_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__2_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__2_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__2
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__2_n_0));
endmodule
(* ORIG_REF_NAME = "clk_x_pntrs" *)
module system_auto_cc_0_clk_x_pntrs_70
(out,
ram_empty_i_reg,
Q,
ram_full_fb_i_reg,
ram_full_fb_i_reg_0,
\gc0.count_reg[2] ,
ram_full_fb_i_reg_1,
\gic0.gc0.count_d1_reg[3] ,
\grstd1.grst_full.grst_f.rst_d3_reg ,
\gic0.gc0.count_reg[2] ,
\gic0.gc0.count_d2_reg[3] ,
s_aclk,
AR,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ,
\gc0.count_d1_reg[3] ,
D,
\Q_reg_reg[1] );
output [3:0]out;
output ram_empty_i_reg;
output [3:0]Q;
output ram_full_fb_i_reg;
output [0:0]ram_full_fb_i_reg_0;
input [2:0]\gc0.count_reg[2] ;
input ram_full_fb_i_reg_1;
input [3:0]\gic0.gc0.count_d1_reg[3] ;
input \grstd1.grst_full.grst_f.rst_d3_reg ;
input [2:0]\gic0.gc0.count_reg[2] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input s_aclk;
input [0:0]AR;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
input [0:0]\gc0.count_d1_reg[3] ;
input [2:0]D;
input [0:0]\Q_reg_reg[1] ;
wire [0:0]AR;
wire [2:0]D;
wire [3:0]Q;
wire [0:0]\Q_reg_reg[1] ;
wire __0_n_0;
wire __1_n_0;
wire __2_n_0;
wire [2:0]bin2gray;
wire [0:0]\gc0.count_d1_reg[3] ;
wire [2:0]\gc0.count_reg[2] ;
wire [3:0]\gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [2:0]\gic0.gc0.count_reg[2] ;
wire \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ;
wire \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ;
wire \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ;
wire \grstd1.grst_full.grst_f.rst_d3_reg ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]out;
wire [2:0]p_23_out;
wire [3:0]p_3_out;
wire [3:0]p_4_out;
wire [3:0]p_5_out;
wire [3:0]p_6_out;
wire [3:0]p_8_out;
wire ram_empty_i_reg;
wire ram_full_fb_i_reg;
wire [0:0]ram_full_fb_i_reg_0;
wire ram_full_fb_i_reg_1;
wire ram_full_i_i_2__3_n_0;
wire ram_full_i_i_4__3_n_0;
wire s_aclk;
LUT3 #(
.INIT(8'h96))
__0
(.I0(out[2]),
.I1(out[1]),
.I2(out[3]),
.O(__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
__1
(.I0(p_8_out[1]),
.I1(p_8_out[0]),
.I2(p_8_out[3]),
.I3(p_8_out[2]),
.O(__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h96))
__2
(.I0(p_8_out[2]),
.I1(p_8_out[1]),
.I2(p_8_out[3]),
.O(__2_n_0));
system_auto_cc_0_synchronizer_ff__parameterized0_87 \gnxpm_cdc.gsync_stage[1].rd_stg_inst
(.D(p_3_out),
.Q({\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] }),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized1_88 \gnxpm_cdc.gsync_stage[1].wr_stg_inst
(.AR(AR),
.D(p_4_out),
.Q({\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ,\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] }),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized2_89 \gnxpm_cdc.gsync_stage[2].rd_stg_inst
(.D(p_5_out),
.\Q_reg_reg[3]_0 (p_3_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ));
system_auto_cc_0_synchronizer_ff__parameterized3_90 \gnxpm_cdc.gsync_stage[2].wr_stg_inst
(.AR(AR),
.D(p_6_out),
.\Q_reg_reg[3]_0 (p_4_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff__parameterized4_91 \gnxpm_cdc.gsync_stage[3].rd_stg_inst
(.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_5_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.out(out));
system_auto_cc_0_synchronizer_ff__parameterized5_92 \gnxpm_cdc.gsync_stage[3].wr_stg_inst
(.AR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.\Q_reg_reg[3]_0 (p_6_out),
.out(p_8_out),
.s_aclk(s_aclk));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__1_n_0),
.Q(p_23_out[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(__2_n_0),
.Q(p_23_out[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4 ),
.Q(p_23_out[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_bin_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(p_8_out[3]),
.Q(ram_full_fb_i_reg_0));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(D[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.rd_pntr_gc_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gc0.count_d1_reg[3] ),
.Q(\gnxpm_cdc.rd_pntr_gc_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[1] ),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(__0_n_0),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4 ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_bin_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(out[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[0]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [0]),
.I1(\gic0.gc0.count_d2_reg[3] [1]),
.O(bin2gray[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[1]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [1]),
.I1(\gic0.gc0.count_d2_reg[3] [2]),
.O(bin2gray[1]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_gc[2]_i_1
(.I0(\gic0.gc0.count_d2_reg[3] [2]),
.I1(\gic0.gc0.count_d2_reg[3] [3]),
.O(bin2gray[2]));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(bin2gray[2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\gnxpm_cdc.wr_pntr_gc_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3] [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg_n_0_[3] ));
LUT6 #(
.INIT(64'h9009000000009009))
ram_empty_i_i_4__1
(.I0(Q[2]),
.I1(\gc0.count_reg[2] [2]),
.I2(Q[1]),
.I3(\gc0.count_reg[2] [1]),
.I4(\gc0.count_reg[2] [0]),
.I5(Q[0]),
.O(ram_empty_i_reg));
LUT6 #(
.INIT(64'h0000F88F00008888))
ram_full_i_i_1__3
(.I0(ram_full_i_i_2__3_n_0),
.I1(ram_full_fb_i_reg_1),
.I2(\gic0.gc0.count_d1_reg[3] [3]),
.I3(ram_full_fb_i_reg_0),
.I4(\grstd1.grst_full.grst_f.rst_d3_reg ),
.I5(ram_full_i_i_4__3_n_0),
.O(ram_full_fb_i_reg));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_2__3
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_reg[2] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_reg[2] [1]),
.I4(\gic0.gc0.count_reg[2] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_2__3_n_0));
LUT6 #(
.INIT(64'h9009000000009009))
ram_full_i_i_4__3
(.I0(p_23_out[2]),
.I1(\gic0.gc0.count_d1_reg[3] [2]),
.I2(p_23_out[1]),
.I3(\gic0.gc0.count_d1_reg[3] [1]),
.I4(\gic0.gc0.count_d1_reg[3] [0]),
.I5(p_23_out[0]),
.O(ram_full_i_i_4__3_n_0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem
(dout_i,
s_aclk,
ram_full_fb_i_reg,
DI,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [57:0]dout_i;
input s_aclk;
input [0:0]ram_full_fb_i_reg;
input [57:0]DI;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [57:0]DI;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_57_n_0;
wire RAM_reg_0_15_54_57_n_1;
wire RAM_reg_0_15_54_57_n_2;
wire RAM_reg_0_15_54_57_n_3;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [57:0]dout_i;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]ram_full_fb_i_reg;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[1:0]),
.DIB(DI[3:2]),
.DIC(DI[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[13:12]),
.DIB(DI[15:14]),
.DIC(DI[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[19:18]),
.DIB(DI[21:20]),
.DIC(DI[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[25:24]),
.DIB(DI[27:26]),
.DIC(DI[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[31:30]),
.DIB(DI[33:32]),
.DIC(DI[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[37:36]),
.DIB(DI[39:38]),
.DIC(DI[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[43:42]),
.DIB(DI[45:44]),
.DIC(DI[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[49:48]),
.DIB(DI[51:50]),
.DIC(DI[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_57
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[55:54]),
.DIB(DI[57:56]),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_57_n_0,RAM_reg_0_15_54_57_n_1}),
.DOB({RAM_reg_0_15_54_57_n_2,RAM_reg_0_15_54_57_n_3}),
.DOC(NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(DI[7:6]),
.DIB(DI[9:8]),
.DIC(DI[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(ram_full_fb_i_reg));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(dout_i[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(dout_i[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(dout_i[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(dout_i[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(dout_i[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(dout_i[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(dout_i[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(dout_i[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(dout_i[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(dout_i[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(dout_i[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(dout_i[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(dout_i[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(dout_i[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(dout_i[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(dout_i[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(dout_i[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(dout_i[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(dout_i[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(dout_i[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(dout_i[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(dout_i[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(dout_i[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(dout_i[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(dout_i[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(dout_i[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(dout_i[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(dout_i[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(dout_i[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(dout_i[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(dout_i[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(dout_i[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(dout_i[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(dout_i[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(dout_i[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(dout_i[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(dout_i[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(dout_i[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(dout_i[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(dout_i[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(dout_i[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(dout_i[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(dout_i[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(dout_i[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(dout_i[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(dout_i[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(dout_i[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(dout_i[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(dout_i[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_1),
.Q(dout_i[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_0),
.Q(dout_i[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_3),
.Q(dout_i[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_2),
.Q(dout_i[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(dout_i[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(dout_i[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(dout_i[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(dout_i[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(dout_i[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem_81
(Q,
s_aclk,
E,
I123,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [57:0]Q;
input s_aclk;
input [0:0]E;
input [57:0]I123;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [0:0]E;
wire [57:0]I123;
wire [57:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_57_n_0;
wire RAM_reg_0_15_54_57_n_1;
wire RAM_reg_0_15_54_57_n_2;
wire RAM_reg_0_15_54_57_n_3;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[1:0]),
.DIB(I123[3:2]),
.DIC(I123[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[13:12]),
.DIB(I123[15:14]),
.DIC(I123[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[19:18]),
.DIB(I123[21:20]),
.DIC(I123[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[25:24]),
.DIB(I123[27:26]),
.DIC(I123[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[31:30]),
.DIB(I123[33:32]),
.DIC(I123[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[37:36]),
.DIB(I123[39:38]),
.DIC(I123[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[43:42]),
.DIB(I123[45:44]),
.DIC(I123[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[49:48]),
.DIB(I123[51:50]),
.DIC(I123[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_57
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[55:54]),
.DIB(I123[57:56]),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_57_n_0,RAM_reg_0_15_54_57_n_1}),
.DOB({RAM_reg_0_15_54_57_n_2,RAM_reg_0_15_54_57_n_3}),
.DOC(NLW_RAM_reg_0_15_54_57_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_54_57_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I123[7:6]),
.DIB(I123[9:8]),
.DIC(I123[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_57_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem__parameterized0
(Q,
s_aclk,
E,
I115,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk);
output [144:0]Q;
input s_aclk;
input [0:0]E;
input [144:0]I115;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
wire [0:0]E;
wire [144:0]I115;
wire [144:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_102_107_n_0;
wire RAM_reg_0_15_102_107_n_1;
wire RAM_reg_0_15_102_107_n_2;
wire RAM_reg_0_15_102_107_n_3;
wire RAM_reg_0_15_102_107_n_4;
wire RAM_reg_0_15_102_107_n_5;
wire RAM_reg_0_15_108_113_n_0;
wire RAM_reg_0_15_108_113_n_1;
wire RAM_reg_0_15_108_113_n_2;
wire RAM_reg_0_15_108_113_n_3;
wire RAM_reg_0_15_108_113_n_4;
wire RAM_reg_0_15_108_113_n_5;
wire RAM_reg_0_15_114_119_n_0;
wire RAM_reg_0_15_114_119_n_1;
wire RAM_reg_0_15_114_119_n_2;
wire RAM_reg_0_15_114_119_n_3;
wire RAM_reg_0_15_114_119_n_4;
wire RAM_reg_0_15_114_119_n_5;
wire RAM_reg_0_15_120_125_n_0;
wire RAM_reg_0_15_120_125_n_1;
wire RAM_reg_0_15_120_125_n_2;
wire RAM_reg_0_15_120_125_n_3;
wire RAM_reg_0_15_120_125_n_4;
wire RAM_reg_0_15_120_125_n_5;
wire RAM_reg_0_15_126_131_n_0;
wire RAM_reg_0_15_126_131_n_1;
wire RAM_reg_0_15_126_131_n_2;
wire RAM_reg_0_15_126_131_n_3;
wire RAM_reg_0_15_126_131_n_4;
wire RAM_reg_0_15_126_131_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_132_137_n_0;
wire RAM_reg_0_15_132_137_n_1;
wire RAM_reg_0_15_132_137_n_2;
wire RAM_reg_0_15_132_137_n_3;
wire RAM_reg_0_15_132_137_n_4;
wire RAM_reg_0_15_132_137_n_5;
wire RAM_reg_0_15_138_143_n_0;
wire RAM_reg_0_15_138_143_n_1;
wire RAM_reg_0_15_138_143_n_2;
wire RAM_reg_0_15_138_143_n_3;
wire RAM_reg_0_15_138_143_n_4;
wire RAM_reg_0_15_138_143_n_5;
wire RAM_reg_0_15_144_144_n_1;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_59_n_0;
wire RAM_reg_0_15_54_59_n_1;
wire RAM_reg_0_15_54_59_n_2;
wire RAM_reg_0_15_54_59_n_3;
wire RAM_reg_0_15_54_59_n_4;
wire RAM_reg_0_15_54_59_n_5;
wire RAM_reg_0_15_60_65_n_0;
wire RAM_reg_0_15_60_65_n_1;
wire RAM_reg_0_15_60_65_n_2;
wire RAM_reg_0_15_60_65_n_3;
wire RAM_reg_0_15_60_65_n_4;
wire RAM_reg_0_15_60_65_n_5;
wire RAM_reg_0_15_66_71_n_0;
wire RAM_reg_0_15_66_71_n_1;
wire RAM_reg_0_15_66_71_n_2;
wire RAM_reg_0_15_66_71_n_3;
wire RAM_reg_0_15_66_71_n_4;
wire RAM_reg_0_15_66_71_n_5;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire RAM_reg_0_15_72_77_n_0;
wire RAM_reg_0_15_72_77_n_1;
wire RAM_reg_0_15_72_77_n_2;
wire RAM_reg_0_15_72_77_n_3;
wire RAM_reg_0_15_72_77_n_4;
wire RAM_reg_0_15_72_77_n_5;
wire RAM_reg_0_15_78_83_n_0;
wire RAM_reg_0_15_78_83_n_1;
wire RAM_reg_0_15_78_83_n_2;
wire RAM_reg_0_15_78_83_n_3;
wire RAM_reg_0_15_78_83_n_4;
wire RAM_reg_0_15_78_83_n_5;
wire RAM_reg_0_15_84_89_n_0;
wire RAM_reg_0_15_84_89_n_1;
wire RAM_reg_0_15_84_89_n_2;
wire RAM_reg_0_15_84_89_n_3;
wire RAM_reg_0_15_84_89_n_4;
wire RAM_reg_0_15_84_89_n_5;
wire RAM_reg_0_15_90_95_n_0;
wire RAM_reg_0_15_90_95_n_1;
wire RAM_reg_0_15_90_95_n_2;
wire RAM_reg_0_15_90_95_n_3;
wire RAM_reg_0_15_90_95_n_4;
wire RAM_reg_0_15_90_95_n_5;
wire RAM_reg_0_15_96_101_n_0;
wire RAM_reg_0_15_96_101_n_1;
wire RAM_reg_0_15_96_101_n_2;
wire RAM_reg_0_15_96_101_n_3;
wire RAM_reg_0_15_96_101_n_4;
wire RAM_reg_0_15_96_101_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED;
wire [1:1]NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[1:0]),
.DIB(I115[3:2]),
.DIC(I115[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_102_107
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[103:102]),
.DIB(I115[105:104]),
.DIC(I115[107:106]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_102_107_n_0,RAM_reg_0_15_102_107_n_1}),
.DOB({RAM_reg_0_15_102_107_n_2,RAM_reg_0_15_102_107_n_3}),
.DOC({RAM_reg_0_15_102_107_n_4,RAM_reg_0_15_102_107_n_5}),
.DOD(NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_108_113
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[109:108]),
.DIB(I115[111:110]),
.DIC(I115[113:112]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_108_113_n_0,RAM_reg_0_15_108_113_n_1}),
.DOB({RAM_reg_0_15_108_113_n_2,RAM_reg_0_15_108_113_n_3}),
.DOC({RAM_reg_0_15_108_113_n_4,RAM_reg_0_15_108_113_n_5}),
.DOD(NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_114_119
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[115:114]),
.DIB(I115[117:116]),
.DIC(I115[119:118]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_114_119_n_0,RAM_reg_0_15_114_119_n_1}),
.DOB({RAM_reg_0_15_114_119_n_2,RAM_reg_0_15_114_119_n_3}),
.DOC({RAM_reg_0_15_114_119_n_4,RAM_reg_0_15_114_119_n_5}),
.DOD(NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_120_125
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[121:120]),
.DIB(I115[123:122]),
.DIC(I115[125:124]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_120_125_n_0,RAM_reg_0_15_120_125_n_1}),
.DOB({RAM_reg_0_15_120_125_n_2,RAM_reg_0_15_120_125_n_3}),
.DOC({RAM_reg_0_15_120_125_n_4,RAM_reg_0_15_120_125_n_5}),
.DOD(NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_126_131
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[127:126]),
.DIB(I115[129:128]),
.DIC(I115[131:130]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_126_131_n_0,RAM_reg_0_15_126_131_n_1}),
.DOB({RAM_reg_0_15_126_131_n_2,RAM_reg_0_15_126_131_n_3}),
.DOC({RAM_reg_0_15_126_131_n_4,RAM_reg_0_15_126_131_n_5}),
.DOD(NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[13:12]),
.DIB(I115[15:14]),
.DIC(I115[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_132_137
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[133:132]),
.DIB(I115[135:134]),
.DIC(I115[137:136]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_132_137_n_0,RAM_reg_0_15_132_137_n_1}),
.DOB({RAM_reg_0_15_132_137_n_2,RAM_reg_0_15_132_137_n_3}),
.DOC({RAM_reg_0_15_132_137_n_4,RAM_reg_0_15_132_137_n_5}),
.DOD(NLW_RAM_reg_0_15_132_137_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_138_143
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[139:138]),
.DIB(I115[141:140]),
.DIC(I115[143:142]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_138_143_n_0,RAM_reg_0_15_138_143_n_1}),
.DOB({RAM_reg_0_15_138_143_n_2,RAM_reg_0_15_138_143_n_3}),
.DOC({RAM_reg_0_15_138_143_n_4,RAM_reg_0_15_138_143_n_5}),
.DOD(NLW_RAM_reg_0_15_138_143_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_144_144
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA({1'b0,I115[144]}),
.DIB({1'b0,1'b0}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({NLW_RAM_reg_0_15_144_144_DOA_UNCONNECTED[1],RAM_reg_0_15_144_144_n_1}),
.DOB(NLW_RAM_reg_0_15_144_144_DOB_UNCONNECTED[1:0]),
.DOC(NLW_RAM_reg_0_15_144_144_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_144_144_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[19:18]),
.DIB(I115[21:20]),
.DIC(I115[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[25:24]),
.DIB(I115[27:26]),
.DIC(I115[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[31:30]),
.DIB(I115[33:32]),
.DIC(I115[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[37:36]),
.DIB(I115[39:38]),
.DIC(I115[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[43:42]),
.DIB(I115[45:44]),
.DIC(I115[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[49:48]),
.DIB(I115[51:50]),
.DIC(I115[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[55:54]),
.DIB(I115[57:56]),
.DIC(I115[59:58]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_59_n_0,RAM_reg_0_15_54_59_n_1}),
.DOB({RAM_reg_0_15_54_59_n_2,RAM_reg_0_15_54_59_n_3}),
.DOC({RAM_reg_0_15_54_59_n_4,RAM_reg_0_15_54_59_n_5}),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_65
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[61:60]),
.DIB(I115[63:62]),
.DIC(I115[65:64]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_60_65_n_0,RAM_reg_0_15_60_65_n_1}),
.DOB({RAM_reg_0_15_60_65_n_2,RAM_reg_0_15_60_65_n_3}),
.DOC({RAM_reg_0_15_60_65_n_4,RAM_reg_0_15_60_65_n_5}),
.DOD(NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_66_71
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[67:66]),
.DIB(I115[69:68]),
.DIC(I115[71:70]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_66_71_n_0,RAM_reg_0_15_66_71_n_1}),
.DOB({RAM_reg_0_15_66_71_n_2,RAM_reg_0_15_66_71_n_3}),
.DOC({RAM_reg_0_15_66_71_n_4,RAM_reg_0_15_66_71_n_5}),
.DOD(NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[7:6]),
.DIB(I115[9:8]),
.DIC(I115[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_72_77
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[73:72]),
.DIB(I115[75:74]),
.DIC(I115[77:76]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_72_77_n_0,RAM_reg_0_15_72_77_n_1}),
.DOB({RAM_reg_0_15_72_77_n_2,RAM_reg_0_15_72_77_n_3}),
.DOC({RAM_reg_0_15_72_77_n_4,RAM_reg_0_15_72_77_n_5}),
.DOD(NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_78_83
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[79:78]),
.DIB(I115[81:80]),
.DIC(I115[83:82]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_78_83_n_0,RAM_reg_0_15_78_83_n_1}),
.DOB({RAM_reg_0_15_78_83_n_2,RAM_reg_0_15_78_83_n_3}),
.DOC({RAM_reg_0_15_78_83_n_4,RAM_reg_0_15_78_83_n_5}),
.DOD(NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_84_89
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[85:84]),
.DIB(I115[87:86]),
.DIC(I115[89:88]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_84_89_n_0,RAM_reg_0_15_84_89_n_1}),
.DOB({RAM_reg_0_15_84_89_n_2,RAM_reg_0_15_84_89_n_3}),
.DOC({RAM_reg_0_15_84_89_n_4,RAM_reg_0_15_84_89_n_5}),
.DOD(NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_90_95
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[91:90]),
.DIB(I115[93:92]),
.DIC(I115[95:94]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_90_95_n_0,RAM_reg_0_15_90_95_n_1}),
.DOB({RAM_reg_0_15_90_95_n_2,RAM_reg_0_15_90_95_n_3}),
.DOC({RAM_reg_0_15_90_95_n_4,RAM_reg_0_15_90_95_n_5}),
.DOD(NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_96_101
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I115[97:96]),
.DIB(I115[99:98]),
.DIC(I115[101:100]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_96_101_n_0,RAM_reg_0_15_96_101_n_1}),
.DOB({RAM_reg_0_15_96_101_n_2,RAM_reg_0_15_96_101_n_3}),
.DOC({RAM_reg_0_15_96_101_n_4,RAM_reg_0_15_96_101_n_5}),
.DOD(NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED[1:0]),
.WCLK(s_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[100]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_5),
.Q(Q[100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[101]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_4),
.Q(Q[101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[102]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_1),
.Q(Q[102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[103]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_0),
.Q(Q[103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[104]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_3),
.Q(Q[104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[105]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_2),
.Q(Q[105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[106]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_5),
.Q(Q[106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[107]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_4),
.Q(Q[107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[108]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_1),
.Q(Q[108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[109]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_0),
.Q(Q[109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[110]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_3),
.Q(Q[110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[111]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_2),
.Q(Q[111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[112]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_5),
.Q(Q[112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[113]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_4),
.Q(Q[113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[114]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_1),
.Q(Q[114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[115]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_0),
.Q(Q[115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[116]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_3),
.Q(Q[116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[117]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_2),
.Q(Q[117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[118]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_5),
.Q(Q[118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[119]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_4),
.Q(Q[119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[120]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_1),
.Q(Q[120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[121]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_0),
.Q(Q[121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[122]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_3),
.Q(Q[122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[123]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_2),
.Q(Q[123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[124]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_5),
.Q(Q[124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[125]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_4),
.Q(Q[125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[126]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_1),
.Q(Q[126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[127]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_0),
.Q(Q[127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[128]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_3),
.Q(Q[128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[129]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_2),
.Q(Q[129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[130]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_5),
.Q(Q[130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[131]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_4),
.Q(Q[131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[132]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_1),
.Q(Q[132]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[133]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_0),
.Q(Q[133]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[134]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_3),
.Q(Q[134]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[135]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_2),
.Q(Q[135]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[136]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_5),
.Q(Q[136]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[137]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_132_137_n_4),
.Q(Q[137]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[138]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_1),
.Q(Q[138]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[139]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_0),
.Q(Q[139]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[140]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_3),
.Q(Q[140]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[141]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_2),
.Q(Q[141]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[142]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_5),
.Q(Q[142]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[143]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_138_143_n_4),
.Q(Q[143]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[144]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_144_144_n_1),
.Q(Q[144]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_5),
.Q(Q[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_4),
.Q(Q[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_1),
.Q(Q[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_0),
.Q(Q[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_3),
.Q(Q[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_2),
.Q(Q[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_5),
.Q(Q[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[65]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_4),
.Q(Q[65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[66]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_1),
.Q(Q[66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[67]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_0),
.Q(Q[67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[68]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_3),
.Q(Q[68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[69]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_2),
.Q(Q[69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[70]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_5),
.Q(Q[70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[71]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_4),
.Q(Q[71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[72]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_1),
.Q(Q[72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[73]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_0),
.Q(Q[73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[74]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_3),
.Q(Q[74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[75]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_2),
.Q(Q[75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[76]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_5),
.Q(Q[76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[77]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_4),
.Q(Q[77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[78]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_1),
.Q(Q[78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[79]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_0),
.Q(Q[79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[80]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_3),
.Q(Q[80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[81]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_2),
.Q(Q[81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[82]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_5),
.Q(Q[82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[83]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_4),
.Q(Q[83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[84]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_1),
.Q(Q[84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[85]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_0),
.Q(Q[85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[86]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_3),
.Q(Q[86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[87]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_2),
.Q(Q[87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[88]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_5),
.Q(Q[88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[89]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_4),
.Q(Q[89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[90]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_1),
.Q(Q[90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[91]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_0),
.Q(Q[91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[92]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_3),
.Q(Q[92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[93]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_2),
.Q(Q[93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[94]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_5),
.Q(Q[94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[95]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_4),
.Q(Q[95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[96]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_1),
.Q(Q[96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[97]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_0),
.Q(Q[97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[98]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_3),
.Q(Q[98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[99]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_2),
.Q(Q[99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(m_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem__parameterized1
(Q,
m_aclk,
E,
m_axi_bresp,
m_axi_bid,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk);
output [2:0]Q;
input m_aclk;
input [0:0]E;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
wire [0:0]E;
wire [2:0]Q;
wire RAM_reg_0_15_0_2_n_0;
wire RAM_reg_0_15_0_2_n_1;
wire RAM_reg_0_15_0_2_n_3;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire s_aclk;
wire [1:1]NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_2
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(m_axi_bresp),
.DIB({1'b0,m_axi_bid}),
.DIC({1'b0,1'b0}),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_2_n_0,RAM_reg_0_15_0_2_n_1}),
.DOB({NLW_RAM_reg_0_15_0_2_DOB_UNCONNECTED[1],RAM_reg_0_15_0_2_n_3}),
.DOC(NLW_RAM_reg_0_15_0_2_DOC_UNCONNECTED[1:0]),
.DOD(NLW_RAM_reg_0_15_0_2_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_2_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_2_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_2_n_3),
.Q(Q[2]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "dmem" *)
module system_auto_cc_0_dmem__parameterized2
(Q,
m_aclk,
E,
I127,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk);
output [131:0]Q;
input m_aclk;
input [0:0]E;
input [131:0]I127;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
wire [0:0]E;
wire [131:0]I127;
wire [131:0]Q;
wire RAM_reg_0_15_0_5_n_0;
wire RAM_reg_0_15_0_5_n_1;
wire RAM_reg_0_15_0_5_n_2;
wire RAM_reg_0_15_0_5_n_3;
wire RAM_reg_0_15_0_5_n_4;
wire RAM_reg_0_15_0_5_n_5;
wire RAM_reg_0_15_102_107_n_0;
wire RAM_reg_0_15_102_107_n_1;
wire RAM_reg_0_15_102_107_n_2;
wire RAM_reg_0_15_102_107_n_3;
wire RAM_reg_0_15_102_107_n_4;
wire RAM_reg_0_15_102_107_n_5;
wire RAM_reg_0_15_108_113_n_0;
wire RAM_reg_0_15_108_113_n_1;
wire RAM_reg_0_15_108_113_n_2;
wire RAM_reg_0_15_108_113_n_3;
wire RAM_reg_0_15_108_113_n_4;
wire RAM_reg_0_15_108_113_n_5;
wire RAM_reg_0_15_114_119_n_0;
wire RAM_reg_0_15_114_119_n_1;
wire RAM_reg_0_15_114_119_n_2;
wire RAM_reg_0_15_114_119_n_3;
wire RAM_reg_0_15_114_119_n_4;
wire RAM_reg_0_15_114_119_n_5;
wire RAM_reg_0_15_120_125_n_0;
wire RAM_reg_0_15_120_125_n_1;
wire RAM_reg_0_15_120_125_n_2;
wire RAM_reg_0_15_120_125_n_3;
wire RAM_reg_0_15_120_125_n_4;
wire RAM_reg_0_15_120_125_n_5;
wire RAM_reg_0_15_126_131_n_0;
wire RAM_reg_0_15_126_131_n_1;
wire RAM_reg_0_15_126_131_n_2;
wire RAM_reg_0_15_126_131_n_3;
wire RAM_reg_0_15_126_131_n_4;
wire RAM_reg_0_15_126_131_n_5;
wire RAM_reg_0_15_12_17_n_0;
wire RAM_reg_0_15_12_17_n_1;
wire RAM_reg_0_15_12_17_n_2;
wire RAM_reg_0_15_12_17_n_3;
wire RAM_reg_0_15_12_17_n_4;
wire RAM_reg_0_15_12_17_n_5;
wire RAM_reg_0_15_18_23_n_0;
wire RAM_reg_0_15_18_23_n_1;
wire RAM_reg_0_15_18_23_n_2;
wire RAM_reg_0_15_18_23_n_3;
wire RAM_reg_0_15_18_23_n_4;
wire RAM_reg_0_15_18_23_n_5;
wire RAM_reg_0_15_24_29_n_0;
wire RAM_reg_0_15_24_29_n_1;
wire RAM_reg_0_15_24_29_n_2;
wire RAM_reg_0_15_24_29_n_3;
wire RAM_reg_0_15_24_29_n_4;
wire RAM_reg_0_15_24_29_n_5;
wire RAM_reg_0_15_30_35_n_0;
wire RAM_reg_0_15_30_35_n_1;
wire RAM_reg_0_15_30_35_n_2;
wire RAM_reg_0_15_30_35_n_3;
wire RAM_reg_0_15_30_35_n_4;
wire RAM_reg_0_15_30_35_n_5;
wire RAM_reg_0_15_36_41_n_0;
wire RAM_reg_0_15_36_41_n_1;
wire RAM_reg_0_15_36_41_n_2;
wire RAM_reg_0_15_36_41_n_3;
wire RAM_reg_0_15_36_41_n_4;
wire RAM_reg_0_15_36_41_n_5;
wire RAM_reg_0_15_42_47_n_0;
wire RAM_reg_0_15_42_47_n_1;
wire RAM_reg_0_15_42_47_n_2;
wire RAM_reg_0_15_42_47_n_3;
wire RAM_reg_0_15_42_47_n_4;
wire RAM_reg_0_15_42_47_n_5;
wire RAM_reg_0_15_48_53_n_0;
wire RAM_reg_0_15_48_53_n_1;
wire RAM_reg_0_15_48_53_n_2;
wire RAM_reg_0_15_48_53_n_3;
wire RAM_reg_0_15_48_53_n_4;
wire RAM_reg_0_15_48_53_n_5;
wire RAM_reg_0_15_54_59_n_0;
wire RAM_reg_0_15_54_59_n_1;
wire RAM_reg_0_15_54_59_n_2;
wire RAM_reg_0_15_54_59_n_3;
wire RAM_reg_0_15_54_59_n_4;
wire RAM_reg_0_15_54_59_n_5;
wire RAM_reg_0_15_60_65_n_0;
wire RAM_reg_0_15_60_65_n_1;
wire RAM_reg_0_15_60_65_n_2;
wire RAM_reg_0_15_60_65_n_3;
wire RAM_reg_0_15_60_65_n_4;
wire RAM_reg_0_15_60_65_n_5;
wire RAM_reg_0_15_66_71_n_0;
wire RAM_reg_0_15_66_71_n_1;
wire RAM_reg_0_15_66_71_n_2;
wire RAM_reg_0_15_66_71_n_3;
wire RAM_reg_0_15_66_71_n_4;
wire RAM_reg_0_15_66_71_n_5;
wire RAM_reg_0_15_6_11_n_0;
wire RAM_reg_0_15_6_11_n_1;
wire RAM_reg_0_15_6_11_n_2;
wire RAM_reg_0_15_6_11_n_3;
wire RAM_reg_0_15_6_11_n_4;
wire RAM_reg_0_15_6_11_n_5;
wire RAM_reg_0_15_72_77_n_0;
wire RAM_reg_0_15_72_77_n_1;
wire RAM_reg_0_15_72_77_n_2;
wire RAM_reg_0_15_72_77_n_3;
wire RAM_reg_0_15_72_77_n_4;
wire RAM_reg_0_15_72_77_n_5;
wire RAM_reg_0_15_78_83_n_0;
wire RAM_reg_0_15_78_83_n_1;
wire RAM_reg_0_15_78_83_n_2;
wire RAM_reg_0_15_78_83_n_3;
wire RAM_reg_0_15_78_83_n_4;
wire RAM_reg_0_15_78_83_n_5;
wire RAM_reg_0_15_84_89_n_0;
wire RAM_reg_0_15_84_89_n_1;
wire RAM_reg_0_15_84_89_n_2;
wire RAM_reg_0_15_84_89_n_3;
wire RAM_reg_0_15_84_89_n_4;
wire RAM_reg_0_15_84_89_n_5;
wire RAM_reg_0_15_90_95_n_0;
wire RAM_reg_0_15_90_95_n_1;
wire RAM_reg_0_15_90_95_n_2;
wire RAM_reg_0_15_90_95_n_3;
wire RAM_reg_0_15_90_95_n_4;
wire RAM_reg_0_15_90_95_n_5;
wire RAM_reg_0_15_96_101_n_0;
wire RAM_reg_0_15_96_101_n_1;
wire RAM_reg_0_15_96_101_n_2;
wire RAM_reg_0_15_96_101_n_3;
wire RAM_reg_0_15_96_101_n_4;
wire RAM_reg_0_15_96_101_n_5;
wire [3:0]\gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire s_aclk;
wire [1:0]NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED;
wire [1:0]NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED;
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_0_5
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[1:0]),
.DIB(I127[3:2]),
.DIC(I127[5:4]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_0_5_n_0,RAM_reg_0_15_0_5_n_1}),
.DOB({RAM_reg_0_15_0_5_n_2,RAM_reg_0_15_0_5_n_3}),
.DOC({RAM_reg_0_15_0_5_n_4,RAM_reg_0_15_0_5_n_5}),
.DOD(NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_102_107
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[103:102]),
.DIB(I127[105:104]),
.DIC(I127[107:106]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_102_107_n_0,RAM_reg_0_15_102_107_n_1}),
.DOB({RAM_reg_0_15_102_107_n_2,RAM_reg_0_15_102_107_n_3}),
.DOC({RAM_reg_0_15_102_107_n_4,RAM_reg_0_15_102_107_n_5}),
.DOD(NLW_RAM_reg_0_15_102_107_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_108_113
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[109:108]),
.DIB(I127[111:110]),
.DIC(I127[113:112]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_108_113_n_0,RAM_reg_0_15_108_113_n_1}),
.DOB({RAM_reg_0_15_108_113_n_2,RAM_reg_0_15_108_113_n_3}),
.DOC({RAM_reg_0_15_108_113_n_4,RAM_reg_0_15_108_113_n_5}),
.DOD(NLW_RAM_reg_0_15_108_113_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_114_119
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[115:114]),
.DIB(I127[117:116]),
.DIC(I127[119:118]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_114_119_n_0,RAM_reg_0_15_114_119_n_1}),
.DOB({RAM_reg_0_15_114_119_n_2,RAM_reg_0_15_114_119_n_3}),
.DOC({RAM_reg_0_15_114_119_n_4,RAM_reg_0_15_114_119_n_5}),
.DOD(NLW_RAM_reg_0_15_114_119_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_120_125
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[121:120]),
.DIB(I127[123:122]),
.DIC(I127[125:124]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_120_125_n_0,RAM_reg_0_15_120_125_n_1}),
.DOB({RAM_reg_0_15_120_125_n_2,RAM_reg_0_15_120_125_n_3}),
.DOC({RAM_reg_0_15_120_125_n_4,RAM_reg_0_15_120_125_n_5}),
.DOD(NLW_RAM_reg_0_15_120_125_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_126_131
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[127:126]),
.DIB(I127[129:128]),
.DIC(I127[131:130]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_126_131_n_0,RAM_reg_0_15_126_131_n_1}),
.DOB({RAM_reg_0_15_126_131_n_2,RAM_reg_0_15_126_131_n_3}),
.DOC({RAM_reg_0_15_126_131_n_4,RAM_reg_0_15_126_131_n_5}),
.DOD(NLW_RAM_reg_0_15_126_131_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_12_17
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[13:12]),
.DIB(I127[15:14]),
.DIC(I127[17:16]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_12_17_n_0,RAM_reg_0_15_12_17_n_1}),
.DOB({RAM_reg_0_15_12_17_n_2,RAM_reg_0_15_12_17_n_3}),
.DOC({RAM_reg_0_15_12_17_n_4,RAM_reg_0_15_12_17_n_5}),
.DOD(NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_18_23
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[19:18]),
.DIB(I127[21:20]),
.DIC(I127[23:22]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_18_23_n_0,RAM_reg_0_15_18_23_n_1}),
.DOB({RAM_reg_0_15_18_23_n_2,RAM_reg_0_15_18_23_n_3}),
.DOC({RAM_reg_0_15_18_23_n_4,RAM_reg_0_15_18_23_n_5}),
.DOD(NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_24_29
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[25:24]),
.DIB(I127[27:26]),
.DIC(I127[29:28]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_24_29_n_0,RAM_reg_0_15_24_29_n_1}),
.DOB({RAM_reg_0_15_24_29_n_2,RAM_reg_0_15_24_29_n_3}),
.DOC({RAM_reg_0_15_24_29_n_4,RAM_reg_0_15_24_29_n_5}),
.DOD(NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_30_35
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[31:30]),
.DIB(I127[33:32]),
.DIC(I127[35:34]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_30_35_n_0,RAM_reg_0_15_30_35_n_1}),
.DOB({RAM_reg_0_15_30_35_n_2,RAM_reg_0_15_30_35_n_3}),
.DOC({RAM_reg_0_15_30_35_n_4,RAM_reg_0_15_30_35_n_5}),
.DOD(NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_36_41
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[37:36]),
.DIB(I127[39:38]),
.DIC(I127[41:40]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_36_41_n_0,RAM_reg_0_15_36_41_n_1}),
.DOB({RAM_reg_0_15_36_41_n_2,RAM_reg_0_15_36_41_n_3}),
.DOC({RAM_reg_0_15_36_41_n_4,RAM_reg_0_15_36_41_n_5}),
.DOD(NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_42_47
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[43:42]),
.DIB(I127[45:44]),
.DIC(I127[47:46]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_42_47_n_0,RAM_reg_0_15_42_47_n_1}),
.DOB({RAM_reg_0_15_42_47_n_2,RAM_reg_0_15_42_47_n_3}),
.DOC({RAM_reg_0_15_42_47_n_4,RAM_reg_0_15_42_47_n_5}),
.DOD(NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_48_53
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[49:48]),
.DIB(I127[51:50]),
.DIC(I127[53:52]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_48_53_n_0,RAM_reg_0_15_48_53_n_1}),
.DOB({RAM_reg_0_15_48_53_n_2,RAM_reg_0_15_48_53_n_3}),
.DOC({RAM_reg_0_15_48_53_n_4,RAM_reg_0_15_48_53_n_5}),
.DOD(NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_54_59
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[55:54]),
.DIB(I127[57:56]),
.DIC(I127[59:58]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_54_59_n_0,RAM_reg_0_15_54_59_n_1}),
.DOB({RAM_reg_0_15_54_59_n_2,RAM_reg_0_15_54_59_n_3}),
.DOC({RAM_reg_0_15_54_59_n_4,RAM_reg_0_15_54_59_n_5}),
.DOD(NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_60_65
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[61:60]),
.DIB(I127[63:62]),
.DIC(I127[65:64]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_60_65_n_0,RAM_reg_0_15_60_65_n_1}),
.DOB({RAM_reg_0_15_60_65_n_2,RAM_reg_0_15_60_65_n_3}),
.DOC({RAM_reg_0_15_60_65_n_4,RAM_reg_0_15_60_65_n_5}),
.DOD(NLW_RAM_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_66_71
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[67:66]),
.DIB(I127[69:68]),
.DIC(I127[71:70]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_66_71_n_0,RAM_reg_0_15_66_71_n_1}),
.DOB({RAM_reg_0_15_66_71_n_2,RAM_reg_0_15_66_71_n_3}),
.DOC({RAM_reg_0_15_66_71_n_4,RAM_reg_0_15_66_71_n_5}),
.DOD(NLW_RAM_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_6_11
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[7:6]),
.DIB(I127[9:8]),
.DIC(I127[11:10]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_6_11_n_0,RAM_reg_0_15_6_11_n_1}),
.DOB({RAM_reg_0_15_6_11_n_2,RAM_reg_0_15_6_11_n_3}),
.DOC({RAM_reg_0_15_6_11_n_4,RAM_reg_0_15_6_11_n_5}),
.DOD(NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_72_77
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[73:72]),
.DIB(I127[75:74]),
.DIC(I127[77:76]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_72_77_n_0,RAM_reg_0_15_72_77_n_1}),
.DOB({RAM_reg_0_15_72_77_n_2,RAM_reg_0_15_72_77_n_3}),
.DOC({RAM_reg_0_15_72_77_n_4,RAM_reg_0_15_72_77_n_5}),
.DOD(NLW_RAM_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_78_83
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[79:78]),
.DIB(I127[81:80]),
.DIC(I127[83:82]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_78_83_n_0,RAM_reg_0_15_78_83_n_1}),
.DOB({RAM_reg_0_15_78_83_n_2,RAM_reg_0_15_78_83_n_3}),
.DOC({RAM_reg_0_15_78_83_n_4,RAM_reg_0_15_78_83_n_5}),
.DOD(NLW_RAM_reg_0_15_78_83_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_84_89
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[85:84]),
.DIB(I127[87:86]),
.DIC(I127[89:88]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_84_89_n_0,RAM_reg_0_15_84_89_n_1}),
.DOB({RAM_reg_0_15_84_89_n_2,RAM_reg_0_15_84_89_n_3}),
.DOC({RAM_reg_0_15_84_89_n_4,RAM_reg_0_15_84_89_n_5}),
.DOD(NLW_RAM_reg_0_15_84_89_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_90_95
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[91:90]),
.DIB(I127[93:92]),
.DIC(I127[95:94]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_90_95_n_0,RAM_reg_0_15_90_95_n_1}),
.DOB({RAM_reg_0_15_90_95_n_2,RAM_reg_0_15_90_95_n_3}),
.DOC({RAM_reg_0_15_90_95_n_4,RAM_reg_0_15_90_95_n_5}),
.DOD(NLW_RAM_reg_0_15_90_95_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
(* METHODOLOGY_DRC_VIOS = "" *)
RAM32M RAM_reg_0_15_96_101
(.ADDRA({1'b0,\gc0.count_d1_reg[3] }),
.ADDRB({1'b0,\gc0.count_d1_reg[3] }),
.ADDRC({1'b0,\gc0.count_d1_reg[3] }),
.ADDRD({1'b0,\gic0.gc0.count_d2_reg[3] }),
.DIA(I127[97:96]),
.DIB(I127[99:98]),
.DIC(I127[101:100]),
.DID({1'b0,1'b0}),
.DOA({RAM_reg_0_15_96_101_n_0,RAM_reg_0_15_96_101_n_1}),
.DOB({RAM_reg_0_15_96_101_n_2,RAM_reg_0_15_96_101_n_3}),
.DOC({RAM_reg_0_15_96_101_n_4,RAM_reg_0_15_96_101_n_5}),
.DOD(NLW_RAM_reg_0_15_96_101_DOD_UNCONNECTED[1:0]),
.WCLK(m_aclk),
.WE(E));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[0]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_1),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[100]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_5),
.Q(Q[100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[101]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_4),
.Q(Q[101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[102]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_1),
.Q(Q[102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[103]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_0),
.Q(Q[103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[104]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_3),
.Q(Q[104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[105]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_2),
.Q(Q[105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[106]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_5),
.Q(Q[106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[107]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_102_107_n_4),
.Q(Q[107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[108]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_1),
.Q(Q[108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[109]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_0),
.Q(Q[109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[10]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_5),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[110]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_3),
.Q(Q[110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[111]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_2),
.Q(Q[111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[112]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_5),
.Q(Q[112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[113]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_108_113_n_4),
.Q(Q[113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[114]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_1),
.Q(Q[114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[115]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_0),
.Q(Q[115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[116]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_3),
.Q(Q[116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[117]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_2),
.Q(Q[117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[118]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_5),
.Q(Q[118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[119]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_114_119_n_4),
.Q(Q[119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[11]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_4),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[120]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_1),
.Q(Q[120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[121]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_0),
.Q(Q[121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[122]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_3),
.Q(Q[122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[123]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_2),
.Q(Q[123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[124]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_5),
.Q(Q[124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[125]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_120_125_n_4),
.Q(Q[125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[126]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_1),
.Q(Q[126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[127]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_0),
.Q(Q[127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[128]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_3),
.Q(Q[128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[129]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_2),
.Q(Q[129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[12]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_1),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[130]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_5),
.Q(Q[130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[131]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_126_131_n_4),
.Q(Q[131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[13]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_0),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[14]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_3),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[15]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_2),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[16]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_5),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[17]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_12_17_n_4),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[18]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_1),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[19]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_0),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[1]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_0),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[20]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_3),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[21]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_2),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[22]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_5),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[23]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_18_23_n_4),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[24]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_1),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[25]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_0),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[26]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_3),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[27]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_2),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[28]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_5),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[29]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_24_29_n_4),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[2]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_3),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[30]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_1),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[31]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_0),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[32]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_3),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[33]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_2),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[34]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_5),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[35]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_30_35_n_4),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[36]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_1),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[37]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_0),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[38]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_3),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[39]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_2),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[3]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_2),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[40]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_5),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[41]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_36_41_n_4),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[42]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_1),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[43]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_0),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[44]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_3),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[45]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_2),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[46]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_5),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[47]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_42_47_n_4),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[48]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_1),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[49]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_0),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[4]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_5),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[50]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_3),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[51]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_2),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[52]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_5),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[53]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_48_53_n_4),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[54]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_1),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[55]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_0),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[56]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_3),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[57]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_2),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[58]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_5),
.Q(Q[58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[59]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_54_59_n_4),
.Q(Q[59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[5]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_0_5_n_4),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[60]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_1),
.Q(Q[60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[61]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_0),
.Q(Q[61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[62]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_3),
.Q(Q[62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[63]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_2),
.Q(Q[63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[64]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_5),
.Q(Q[64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[65]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_60_65_n_4),
.Q(Q[65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[66]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_1),
.Q(Q[66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[67]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_0),
.Q(Q[67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[68]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_3),
.Q(Q[68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[69]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_2),
.Q(Q[69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[6]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_1),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[70]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_5),
.Q(Q[70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[71]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_66_71_n_4),
.Q(Q[71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[72]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_1),
.Q(Q[72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[73]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_0),
.Q(Q[73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[74]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_3),
.Q(Q[74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[75]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_2),
.Q(Q[75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[76]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_5),
.Q(Q[76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[77]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_72_77_n_4),
.Q(Q[77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[78]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_1),
.Q(Q[78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[79]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_0),
.Q(Q[79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[7]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_0),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[80]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_3),
.Q(Q[80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[81]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_2),
.Q(Q[81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[82]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_5),
.Q(Q[82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[83]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_78_83_n_4),
.Q(Q[83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[84]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_1),
.Q(Q[84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[85]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_0),
.Q(Q[85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[86]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_3),
.Q(Q[86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[87]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_2),
.Q(Q[87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[88]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_5),
.Q(Q[88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[89]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_84_89_n_4),
.Q(Q[89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[8]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_3),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[90]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_1),
.Q(Q[90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[91]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_0),
.Q(Q[91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[92]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_3),
.Q(Q[92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[93]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_2),
.Q(Q[93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[94]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_5),
.Q(Q[94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[95]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_90_95_n_4),
.Q(Q[95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[96]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_1),
.Q(Q[96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[97]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_0),
.Q(Q[97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[98]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_3),
.Q(Q[98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[99]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_96_101_n_2),
.Q(Q[99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\gpr1.dout_i_reg[9]
(.C(s_aclk),
.CE(\gpregsm1.curr_fwft_state_reg[1] ),
.D(RAM_reg_0_15_6_11_n_2),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo
(s_axi_awready,
m_axi_awvalid,
Q,
m_aclk,
s_aclk,
inverted_reset,
m_axi_awready,
s_axi_awvalid,
DI);
output s_axi_awready;
output m_axi_awvalid;
output [57:0]Q;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_awready;
input s_axi_awvalid;
input [57:0]DI;
wire [57:0]DI;
wire [57:0]Q;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [0:0]gray2bin;
wire inverted_reset;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [3:0]p_0_out_0;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire p_23_out;
wire [3:3]p_23_out_1;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
wire [2:0]wr_pntr_plus2;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_27 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D(gray2bin),
.Q(p_22_out),
.\gc0.count_d1_reg[2] ({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.\gc0.count_d1_reg[3] (p_0_out_0[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (p_23_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out_1),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(gray2bin));
system_auto_cc_0_rd_logic_28 \gntv_or_sync_fifo.gl0.rd
(.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[2] ({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out_0),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[57] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
system_auto_cc_0_wr_logic_29 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out_1),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
system_auto_cc_0_memory \gntv_or_sync_fifo.mem
(.DI(DI),
.E(\gntv_or_sync_fifo.gl0.rd_n_4 ),
.Q(Q),
.\gc0.count_d1_reg[3] (p_0_out_0),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.ram_full_fb_i_reg(p_18_out),
.s_aclk(s_aclk));
system_auto_cc_0_reset_blk_ramfifo_30 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(p_23_out),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo_69
(s_axi_arready,
m_axi_arvalid,
\m_axi_arid[0] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_arready,
s_axi_arvalid,
I123);
output s_axi_arready;
output m_axi_arvalid;
output [57:0]\m_axi_arid[0] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_arready;
input s_axi_arvalid;
input [57:0]I123;
wire [57:0]I123;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_rach;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_70 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_22_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rach),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic_71 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[57] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
system_auto_cc_0_wr_logic_72 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
system_auto_cc_0_memory_73 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I123(I123),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\m_axi_arid[0] (\m_axi_arid[0] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk));
system_auto_cc_0_reset_blk_ramfifo_74 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_rach),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo__parameterized0
(s_axi_wready,
m_axi_wvalid,
\m_axi_wdata[127] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_wready,
s_axi_wvalid,
I115);
output s_axi_wready;
output m_axi_wvalid;
output [144:0]\m_axi_wdata[127] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_wready;
input s_axi_wvalid;
input [144:0]I115;
wire [144:0]I115;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_9 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire inverted_reset;
wire m_aclk;
wire [144:0]\m_axi_wdata[127] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_15_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
wire [2:0]wr_pntr_plus2;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_6 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_22_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d1_reg[3] (p_13_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (p_15_out),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic_7 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[144] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.m_aclk(m_aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out({rd_rst_i[2],rd_rst_i[0]}));
system_auto_cc_0_wr_logic_8 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_9 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
system_auto_cc_0_memory__parameterized0 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I115(I115),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\m_axi_wdata[127] (\m_axi_wdata[127] ),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk));
system_auto_cc_0_reset_blk_ramfifo_9 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(p_15_out),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo__parameterized1
(s_axi_bvalid,
m_axi_bready,
s_axi_bid,
s_axi_bresp,
s_aclk,
m_aclk,
inverted_reset,
m_axi_bresp,
m_axi_bid,
m_axi_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_axi_bready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input s_aclk;
input m_aclk;
input inverted_reset;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input m_axi_bvalid;
input s_axi_bready;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_0 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.rd_n_8 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire [0:0]\gr1.gr1_int.rfwft/p_0_in ;
wire inverted_reset;
wire m_aclk;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_wrch;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 ,\gntv_or_sync_fifo.gl0.rd_n_8 }),
.Q(p_13_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_wrch),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_i_reg_0(p_22_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic \gntv_or_sync_fifo.gl0.rd
(.AR(rd_rst_i[2]),
.D({\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 ,\gntv_or_sync_fifo.gl0.rd_n_8 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.out({\gntv_or_sync_fifo.gl0.rd_n_0 ,\gr1.gr1_int.rfwft/p_0_in }),
.s_aclk(s_aclk),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
system_auto_cc_0_wr_logic \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.m_aclk(m_aclk),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ));
system_auto_cc_0_memory__parameterized1 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.\gpregsm1.curr_fwft_state_reg[1]_0 ({\gntv_or_sync_fifo.gl0.rd_n_0 ,\gr1.gr1_int.rfwft/p_0_in }),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.out(rd_rst_i[0]),
.s_aclk(s_aclk),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp));
system_auto_cc_0_reset_blk_ramfifo rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_wrch),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "fifo_generator_ramfifo" *)
module system_auto_cc_0_fifo_generator_ramfifo__parameterized2
(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ,
s_axi_rvalid,
m_axi_rready,
\s_axi_rid[0] ,
s_aclk,
m_aclk,
m_axi_rvalid,
s_axi_rready,
s_aresetn,
I127);
output \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ;
output s_axi_rvalid;
output m_axi_rready;
output [131:0]\s_axi_rid[0] ;
input s_aclk;
input m_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_aresetn;
input [131:0]I127;
wire [131:0]I127;
wire \gntv_or_sync_fifo.gcx.clkx/_n_0 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_4 ;
wire \gntv_or_sync_fifo.gcx.clkx_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_4 ;
wire \gntv_or_sync_fifo.gl0.rd_n_5 ;
wire \gntv_or_sync_fifo.gl0.rd_n_6 ;
wire \gntv_or_sync_fifo.gl0.rd_n_7 ;
wire \gntv_or_sync_fifo.gl0.wr_n_3 ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ;
wire [3:0]p_0_out;
wire [3:0]p_12_out;
wire [3:0]p_13_out;
wire p_18_out;
wire [3:0]p_22_out;
wire [3:3]p_23_out;
wire [3:0]p_7_out;
wire ram_rd_en_i;
wire [2:0]rd_pntr_plus1;
wire [2:0]rd_rst_i;
wire rst_full_ff_i;
wire s_aclk;
wire s_aresetn;
wire [131:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [2:0]wr_pntr_plus2;
wire wr_rst_busy_rdch;
wire [1:0]wr_rst_i;
system_auto_cc_0_clk_x_pntrs_48 \gntv_or_sync_fifo.gcx.clkx
(.AR(wr_rst_i[0]),
.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.Q(p_13_out),
.\Q_reg_reg[1] (\gntv_or_sync_fifo.gcx.clkx/_n_0 ),
.\gc0.count_d1_reg[3] (p_0_out[3]),
.\gc0.count_reg[2] (rd_pntr_plus1),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gic0.gc0.count_reg[2] (wr_pntr_plus2),
.\grstd1.grst_full.grst_f.rst_d3_reg (wr_rst_busy_rdch),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] (rd_rst_i[1]),
.out(p_7_out),
.ram_empty_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.ram_empty_i_reg_0(p_22_out),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.ram_full_fb_i_reg_0(p_23_out),
.ram_full_fb_i_reg_1(\gntv_or_sync_fifo.gl0.wr_n_3 ),
.s_aclk(s_aclk));
LUT4 #(
.INIT(16'h6996))
\gntv_or_sync_fifo.gcx.clkx/
(.I0(p_7_out[1]),
.I1(p_7_out[0]),
.I2(p_7_out[3]),
.I3(p_7_out[2]),
.O(\gntv_or_sync_fifo.gcx.clkx/_n_0 ));
system_auto_cc_0_rd_logic_49 \gntv_or_sync_fifo.gl0.rd
(.D({\gntv_or_sync_fifo.gl0.rd_n_5 ,\gntv_or_sync_fifo.gl0.rd_n_6 ,\gntv_or_sync_fifo.gl0.rd_n_7 }),
.E(ram_rd_en_i),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (p_0_out),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gntv_or_sync_fifo.gcx.clkx_n_6 ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (p_22_out),
.\goreg_dm.dout_i_reg[131] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.out({rd_rst_i[2],rd_rst_i[0]}),
.s_aclk(s_aclk),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
system_auto_cc_0_wr_logic_50 \gntv_or_sync_fifo.gl0.wr
(.AR(wr_rst_i[1]),
.E(p_18_out),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gntv_or_sync_fifo.gcx.clkx_n_4 ),
.\gic0.gc0.count_d2_reg[3] (p_13_out),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (p_23_out),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (p_12_out),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(rst_full_ff_i),
.ram_full_fb_i_reg(\gntv_or_sync_fifo.gl0.wr_n_3 ));
system_auto_cc_0_memory__parameterized2 \gntv_or_sync_fifo.mem
(.E(p_18_out),
.I127(I127),
.\gc0.count_d1_reg[3] (p_0_out),
.\gic0.gc0.count_d2_reg[3] (p_12_out),
.\gpregsm1.curr_fwft_state_reg[1] (ram_rd_en_i),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] (\gntv_or_sync_fifo.gl0.rd_n_4 ),
.s_aclk(s_aclk),
.\s_axi_rid[0] (\s_axi_rid[0] ));
system_auto_cc_0_reset_blk_ramfifo_51 rstblk
(.\gc0.count_reg[1] (rd_rst_i),
.\grstd1.grst_full.grst_f.rst_d3_reg_0 (rst_full_ff_i),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 (\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg ),
.out(wr_rst_i),
.ram_full_fb_i_reg(wr_rst_busy_rdch),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top
(s_axi_arready,
m_axi_arvalid,
\m_axi_arid[0] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_arready,
s_axi_arvalid,
I123);
output s_axi_arready;
output m_axi_arvalid;
output [57:0]\m_axi_arid[0] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_arready;
input s_axi_arvalid;
input [57:0]I123;
wire [57:0]I123;
wire inverted_reset;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
system_auto_cc_0_fifo_generator_ramfifo_69 \grf.rf
(.I123(I123),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_arid[0] (\m_axi_arid[0] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top_0
(s_axi_awready,
m_axi_awvalid,
Q,
m_aclk,
s_aclk,
inverted_reset,
m_axi_awready,
s_axi_awvalid,
DI);
output s_axi_awready;
output m_axi_awvalid;
output [57:0]Q;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_awready;
input s_axi_awvalid;
input [57:0]DI;
wire [57:0]DI;
wire [57:0]Q;
wire inverted_reset;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
system_auto_cc_0_fifo_generator_ramfifo \grf.rf
(.DI(DI),
.Q(Q),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top__parameterized0
(s_axi_wready,
m_axi_wvalid,
\m_axi_wdata[127] ,
m_aclk,
s_aclk,
inverted_reset,
m_axi_wready,
s_axi_wvalid,
I115);
output s_axi_wready;
output m_axi_wvalid;
output [144:0]\m_axi_wdata[127] ;
input m_aclk;
input s_aclk;
input inverted_reset;
input m_axi_wready;
input s_axi_wvalid;
input [144:0]I115;
wire [144:0]I115;
wire inverted_reset;
wire m_aclk;
wire [144:0]\m_axi_wdata[127] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
system_auto_cc_0_fifo_generator_ramfifo__parameterized0 \grf.rf
(.I115(I115),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_wdata[127] (\m_axi_wdata[127] ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top__parameterized1
(s_axi_bvalid,
m_axi_bready,
s_axi_bid,
s_axi_bresp,
s_aclk,
m_aclk,
inverted_reset,
m_axi_bresp,
m_axi_bid,
m_axi_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_axi_bready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input s_aclk;
input m_aclk;
input inverted_reset;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input m_axi_bvalid;
input s_axi_bready;
wire inverted_reset;
wire m_aclk;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire s_aclk;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
system_auto_cc_0_fifo_generator_ramfifo__parameterized1 \grf.rf
(.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.s_aclk(s_aclk),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_top" *)
module system_auto_cc_0_fifo_generator_top__parameterized2
(inverted_reset,
s_axi_rvalid,
m_axi_rready,
\s_axi_rid[0] ,
s_aclk,
m_aclk,
m_axi_rvalid,
s_axi_rready,
s_aresetn,
I127);
output inverted_reset;
output s_axi_rvalid;
output m_axi_rready;
output [131:0]\s_axi_rid[0] ;
input s_aclk;
input m_aclk;
input m_axi_rvalid;
input s_axi_rready;
input s_aresetn;
input [131:0]I127;
wire [131:0]I127;
wire inverted_reset;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire s_aclk;
wire s_aresetn;
wire [131:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
system_auto_cc_0_fifo_generator_ramfifo__parameterized2 \grf.rf
(.I127(I127),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg (inverted_reset),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
(* C_ADD_NGC_CONSTRAINT = "0" *) (* C_APPLICATION_TYPE_AXIS = "0" *) (* C_APPLICATION_TYPE_RACH = "0" *)
(* C_APPLICATION_TYPE_RDCH = "0" *) (* C_APPLICATION_TYPE_WACH = "0" *) (* C_APPLICATION_TYPE_WDCH = "0" *)
(* C_APPLICATION_TYPE_WRCH = "0" *) (* C_AXIS_TDATA_WIDTH = "8" *) (* C_AXIS_TDEST_WIDTH = "1" *)
(* C_AXIS_TID_WIDTH = "1" *) (* C_AXIS_TKEEP_WIDTH = "1" *) (* C_AXIS_TSTRB_WIDTH = "1" *)
(* C_AXIS_TUSER_WIDTH = "4" *) (* C_AXIS_TYPE = "0" *) (* C_AXI_ADDR_WIDTH = "28" *)
(* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *) (* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "128" *) (* C_AXI_ID_WIDTH = "1" *) (* C_AXI_LEN_WIDTH = "8" *)
(* C_AXI_LOCK_WIDTH = "1" *) (* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_TYPE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *) (* C_COMMON_CLOCK = "0" *) (* C_COUNT_TYPE = "0" *)
(* C_DATA_COUNT_WIDTH = "10" *) (* C_DEFAULT_VALUE = "BlankString" *) (* C_DIN_WIDTH = "18" *)
(* C_DIN_WIDTH_AXIS = "1" *) (* C_DIN_WIDTH_RACH = "58" *) (* C_DIN_WIDTH_RDCH = "132" *)
(* C_DIN_WIDTH_WACH = "58" *) (* C_DIN_WIDTH_WDCH = "145" *) (* C_DIN_WIDTH_WRCH = "3" *)
(* C_DOUT_RST_VAL = "0" *) (* C_DOUT_WIDTH = "18" *) (* C_ENABLE_RLOCS = "0" *)
(* C_ENABLE_RST_SYNC = "1" *) (* C_EN_SAFETY_CKT = "0" *) (* C_ERROR_INJECTION_TYPE = "0" *)
(* C_ERROR_INJECTION_TYPE_AXIS = "0" *) (* C_ERROR_INJECTION_TYPE_RACH = "0" *) (* C_ERROR_INJECTION_TYPE_RDCH = "0" *)
(* C_ERROR_INJECTION_TYPE_WACH = "0" *) (* C_ERROR_INJECTION_TYPE_WDCH = "0" *) (* C_ERROR_INJECTION_TYPE_WRCH = "0" *)
(* C_FAMILY = "artix7" *) (* C_FULL_FLAGS_RST_VAL = "1" *) (* C_HAS_ALMOST_EMPTY = "0" *)
(* C_HAS_ALMOST_FULL = "0" *) (* C_HAS_AXIS_TDATA = "1" *) (* C_HAS_AXIS_TDEST = "0" *)
(* C_HAS_AXIS_TID = "0" *) (* C_HAS_AXIS_TKEEP = "0" *) (* C_HAS_AXIS_TLAST = "0" *)
(* C_HAS_AXIS_TREADY = "1" *) (* C_HAS_AXIS_TSTRB = "0" *) (* C_HAS_AXIS_TUSER = "1" *)
(* C_HAS_AXI_ARUSER = "0" *) (* C_HAS_AXI_AWUSER = "0" *) (* C_HAS_AXI_BUSER = "0" *)
(* C_HAS_AXI_ID = "1" *) (* C_HAS_AXI_RD_CHANNEL = "1" *) (* C_HAS_AXI_RUSER = "0" *)
(* C_HAS_AXI_WR_CHANNEL = "1" *) (* C_HAS_AXI_WUSER = "0" *) (* C_HAS_BACKUP = "0" *)
(* C_HAS_DATA_COUNT = "0" *) (* C_HAS_DATA_COUNTS_AXIS = "0" *) (* C_HAS_DATA_COUNTS_RACH = "0" *)
(* C_HAS_DATA_COUNTS_RDCH = "0" *) (* C_HAS_DATA_COUNTS_WACH = "0" *) (* C_HAS_DATA_COUNTS_WDCH = "0" *)
(* C_HAS_DATA_COUNTS_WRCH = "0" *) (* C_HAS_INT_CLK = "0" *) (* C_HAS_MASTER_CE = "0" *)
(* C_HAS_MEMINIT_FILE = "0" *) (* C_HAS_OVERFLOW = "0" *) (* C_HAS_PROG_FLAGS_AXIS = "0" *)
(* C_HAS_PROG_FLAGS_RACH = "0" *) (* C_HAS_PROG_FLAGS_RDCH = "0" *) (* C_HAS_PROG_FLAGS_WACH = "0" *)
(* C_HAS_PROG_FLAGS_WDCH = "0" *) (* C_HAS_PROG_FLAGS_WRCH = "0" *) (* C_HAS_RD_DATA_COUNT = "0" *)
(* C_HAS_RD_RST = "0" *) (* C_HAS_RST = "1" *) (* C_HAS_SLAVE_CE = "0" *)
(* C_HAS_SRST = "0" *) (* C_HAS_UNDERFLOW = "0" *) (* C_HAS_VALID = "0" *)
(* C_HAS_WR_ACK = "0" *) (* C_HAS_WR_DATA_COUNT = "0" *) (* C_HAS_WR_RST = "0" *)
(* C_IMPLEMENTATION_TYPE = "0" *) (* C_IMPLEMENTATION_TYPE_AXIS = "11" *) (* C_IMPLEMENTATION_TYPE_RACH = "12" *)
(* C_IMPLEMENTATION_TYPE_RDCH = "12" *) (* C_IMPLEMENTATION_TYPE_WACH = "12" *) (* C_IMPLEMENTATION_TYPE_WDCH = "12" *)
(* C_IMPLEMENTATION_TYPE_WRCH = "12" *) (* C_INIT_WR_PNTR_VAL = "0" *) (* C_INTERFACE_TYPE = "2" *)
(* C_MEMORY_TYPE = "1" *) (* C_MIF_FILE_NAME = "BlankString" *) (* C_MSGON_VAL = "1" *)
(* C_OPTIMIZATION_MODE = "0" *) (* C_OVERFLOW_LOW = "0" *) (* C_POWER_SAVING_MODE = "0" *)
(* C_PRELOAD_LATENCY = "1" *) (* C_PRELOAD_REGS = "0" *) (* C_PRIM_FIFO_TYPE = "4kx4" *)
(* C_PRIM_FIFO_TYPE_AXIS = "512x36" *) (* C_PRIM_FIFO_TYPE_RACH = "512x36" *) (* C_PRIM_FIFO_TYPE_RDCH = "512x36" *)
(* C_PRIM_FIFO_TYPE_WACH = "512x36" *) (* C_PRIM_FIFO_TYPE_WDCH = "512x36" *) (* C_PRIM_FIFO_TYPE_WRCH = "512x36" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL = "2" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS = "1021" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH = "13" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH = "13" *) (* C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH = "13" *)
(* C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH = "13" *) (* C_PROG_EMPTY_THRESH_NEGATE_VAL = "3" *) (* C_PROG_EMPTY_TYPE = "0" *)
(* C_PROG_EMPTY_TYPE_AXIS = "0" *) (* C_PROG_EMPTY_TYPE_RACH = "0" *) (* C_PROG_EMPTY_TYPE_RDCH = "0" *)
(* C_PROG_EMPTY_TYPE_WACH = "0" *) (* C_PROG_EMPTY_TYPE_WDCH = "0" *) (* C_PROG_EMPTY_TYPE_WRCH = "0" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL = "1022" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_AXIS = "1023" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_RACH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_RDCH = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WACH = "15" *) (* C_PROG_FULL_THRESH_ASSERT_VAL_WDCH = "15" *)
(* C_PROG_FULL_THRESH_ASSERT_VAL_WRCH = "15" *) (* C_PROG_FULL_THRESH_NEGATE_VAL = "1021" *) (* C_PROG_FULL_TYPE = "0" *)
(* C_PROG_FULL_TYPE_AXIS = "0" *) (* C_PROG_FULL_TYPE_RACH = "0" *) (* C_PROG_FULL_TYPE_RDCH = "0" *)
(* C_PROG_FULL_TYPE_WACH = "0" *) (* C_PROG_FULL_TYPE_WDCH = "0" *) (* C_PROG_FULL_TYPE_WRCH = "0" *)
(* C_RACH_TYPE = "0" *) (* C_RDCH_TYPE = "0" *) (* C_RD_DATA_COUNT_WIDTH = "10" *)
(* C_RD_DEPTH = "1024" *) (* C_RD_FREQ = "1" *) (* C_RD_PNTR_WIDTH = "10" *)
(* C_REG_SLICE_MODE_AXIS = "0" *) (* C_REG_SLICE_MODE_RACH = "0" *) (* C_REG_SLICE_MODE_RDCH = "0" *)
(* C_REG_SLICE_MODE_WACH = "0" *) (* C_REG_SLICE_MODE_WDCH = "0" *) (* C_REG_SLICE_MODE_WRCH = "0" *)
(* C_SELECT_XPM = "0" *) (* C_SYNCHRONIZER_STAGE = "3" *) (* C_UNDERFLOW_LOW = "0" *)
(* C_USE_COMMON_OVERFLOW = "0" *) (* C_USE_COMMON_UNDERFLOW = "0" *) (* C_USE_DEFAULT_SETTINGS = "0" *)
(* C_USE_DOUT_RST = "1" *) (* C_USE_ECC = "0" *) (* C_USE_ECC_AXIS = "0" *)
(* C_USE_ECC_RACH = "0" *) (* C_USE_ECC_RDCH = "0" *) (* C_USE_ECC_WACH = "0" *)
(* C_USE_ECC_WDCH = "0" *) (* C_USE_ECC_WRCH = "0" *) (* C_USE_EMBEDDED_REG = "0" *)
(* C_USE_FIFO16_FLAGS = "0" *) (* C_USE_FWFT_DATA_COUNT = "0" *) (* C_USE_PIPELINE_REG = "0" *)
(* C_VALID_LOW = "0" *) (* C_WACH_TYPE = "0" *) (* C_WDCH_TYPE = "0" *)
(* C_WRCH_TYPE = "0" *) (* C_WR_ACK_LOW = "0" *) (* C_WR_DATA_COUNT_WIDTH = "10" *)
(* C_WR_DEPTH = "1024" *) (* C_WR_DEPTH_AXIS = "1024" *) (* C_WR_DEPTH_RACH = "16" *)
(* C_WR_DEPTH_RDCH = "16" *) (* C_WR_DEPTH_WACH = "16" *) (* C_WR_DEPTH_WDCH = "16" *)
(* C_WR_DEPTH_WRCH = "16" *) (* C_WR_FREQ = "1" *) (* C_WR_PNTR_WIDTH = "10" *)
(* C_WR_PNTR_WIDTH_AXIS = "10" *) (* C_WR_PNTR_WIDTH_RACH = "4" *) (* C_WR_PNTR_WIDTH_RDCH = "4" *)
(* C_WR_PNTR_WIDTH_WACH = "4" *) (* C_WR_PNTR_WIDTH_WDCH = "4" *) (* C_WR_PNTR_WIDTH_WRCH = "4" *)
(* C_WR_RESPONSE_LATENCY = "1" *) (* ORIG_REF_NAME = "fifo_generator_v13_1_3" *)
module system_auto_cc_0_fifo_generator_v13_1_3
(backup,
backup_marker,
clk,
rst,
srst,
wr_clk,
wr_rst,
rd_clk,
rd_rst,
din,
wr_en,
rd_en,
prog_empty_thresh,
prog_empty_thresh_assert,
prog_empty_thresh_negate,
prog_full_thresh,
prog_full_thresh_assert,
prog_full_thresh_negate,
int_clk,
injectdbiterr,
injectsbiterr,
sleep,
dout,
full,
almost_full,
wr_ack,
overflow,
empty,
almost_empty,
valid,
underflow,
data_count,
rd_data_count,
wr_data_count,
prog_full,
prog_empty,
sbiterr,
dbiterr,
wr_rst_busy,
rd_rst_busy,
m_aclk,
s_aclk,
s_aresetn,
m_aclk_en,
s_aclk_en,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awregion,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awqos,
m_axi_awregion,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arregion,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arqos,
m_axi_arregion,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready,
s_axis_tvalid,
s_axis_tready,
s_axis_tdata,
s_axis_tstrb,
s_axis_tkeep,
s_axis_tlast,
s_axis_tid,
s_axis_tdest,
s_axis_tuser,
m_axis_tvalid,
m_axis_tready,
m_axis_tdata,
m_axis_tstrb,
m_axis_tkeep,
m_axis_tlast,
m_axis_tid,
m_axis_tdest,
m_axis_tuser,
axi_aw_injectsbiterr,
axi_aw_injectdbiterr,
axi_aw_prog_full_thresh,
axi_aw_prog_empty_thresh,
axi_aw_data_count,
axi_aw_wr_data_count,
axi_aw_rd_data_count,
axi_aw_sbiterr,
axi_aw_dbiterr,
axi_aw_overflow,
axi_aw_underflow,
axi_aw_prog_full,
axi_aw_prog_empty,
axi_w_injectsbiterr,
axi_w_injectdbiterr,
axi_w_prog_full_thresh,
axi_w_prog_empty_thresh,
axi_w_data_count,
axi_w_wr_data_count,
axi_w_rd_data_count,
axi_w_sbiterr,
axi_w_dbiterr,
axi_w_overflow,
axi_w_underflow,
axi_w_prog_full,
axi_w_prog_empty,
axi_b_injectsbiterr,
axi_b_injectdbiterr,
axi_b_prog_full_thresh,
axi_b_prog_empty_thresh,
axi_b_data_count,
axi_b_wr_data_count,
axi_b_rd_data_count,
axi_b_sbiterr,
axi_b_dbiterr,
axi_b_overflow,
axi_b_underflow,
axi_b_prog_full,
axi_b_prog_empty,
axi_ar_injectsbiterr,
axi_ar_injectdbiterr,
axi_ar_prog_full_thresh,
axi_ar_prog_empty_thresh,
axi_ar_data_count,
axi_ar_wr_data_count,
axi_ar_rd_data_count,
axi_ar_sbiterr,
axi_ar_dbiterr,
axi_ar_overflow,
axi_ar_underflow,
axi_ar_prog_full,
axi_ar_prog_empty,
axi_r_injectsbiterr,
axi_r_injectdbiterr,
axi_r_prog_full_thresh,
axi_r_prog_empty_thresh,
axi_r_data_count,
axi_r_wr_data_count,
axi_r_rd_data_count,
axi_r_sbiterr,
axi_r_dbiterr,
axi_r_overflow,
axi_r_underflow,
axi_r_prog_full,
axi_r_prog_empty,
axis_injectsbiterr,
axis_injectdbiterr,
axis_prog_full_thresh,
axis_prog_empty_thresh,
axis_data_count,
axis_wr_data_count,
axis_rd_data_count,
axis_sbiterr,
axis_dbiterr,
axis_overflow,
axis_underflow,
axis_prog_full,
axis_prog_empty);
input backup;
input backup_marker;
input clk;
input rst;
input srst;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [17:0]din;
input wr_en;
input rd_en;
input [9:0]prog_empty_thresh;
input [9:0]prog_empty_thresh_assert;
input [9:0]prog_empty_thresh_negate;
input [9:0]prog_full_thresh;
input [9:0]prog_full_thresh_assert;
input [9:0]prog_full_thresh_negate;
input int_clk;
input injectdbiterr;
input injectsbiterr;
input sleep;
output [17:0]dout;
output full;
output almost_full;
output wr_ack;
output overflow;
output empty;
output almost_empty;
output valid;
output underflow;
output [9:0]data_count;
output [9:0]rd_data_count;
output [9:0]wr_data_count;
output prog_full;
output prog_empty;
output sbiterr;
output dbiterr;
output wr_rst_busy;
output rd_rst_busy;
input m_aclk;
input s_aclk;
input s_aresetn;
input m_aclk_en;
input s_aclk_en;
input [0:0]s_axi_awid;
input [27:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awqos;
input [3:0]s_axi_awregion;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [127:0]s_axi_wdata;
input [15:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
output [0:0]m_axi_awid;
output [27:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awqos;
output [3:0]m_axi_awregion;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [127:0]m_axi_wdata;
output [15:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
input [0:0]s_axi_arid;
input [27:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arqos;
input [3:0]s_axi_arregion;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [127:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_arid;
output [27:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arqos;
output [3:0]m_axi_arregion;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [127:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
input s_axis_tvalid;
output s_axis_tready;
input [7:0]s_axis_tdata;
input [0:0]s_axis_tstrb;
input [0:0]s_axis_tkeep;
input s_axis_tlast;
input [0:0]s_axis_tid;
input [0:0]s_axis_tdest;
input [3:0]s_axis_tuser;
output m_axis_tvalid;
input m_axis_tready;
output [7:0]m_axis_tdata;
output [0:0]m_axis_tstrb;
output [0:0]m_axis_tkeep;
output m_axis_tlast;
output [0:0]m_axis_tid;
output [0:0]m_axis_tdest;
output [3:0]m_axis_tuser;
input axi_aw_injectsbiterr;
input axi_aw_injectdbiterr;
input [3:0]axi_aw_prog_full_thresh;
input [3:0]axi_aw_prog_empty_thresh;
output [4:0]axi_aw_data_count;
output [4:0]axi_aw_wr_data_count;
output [4:0]axi_aw_rd_data_count;
output axi_aw_sbiterr;
output axi_aw_dbiterr;
output axi_aw_overflow;
output axi_aw_underflow;
output axi_aw_prog_full;
output axi_aw_prog_empty;
input axi_w_injectsbiterr;
input axi_w_injectdbiterr;
input [3:0]axi_w_prog_full_thresh;
input [3:0]axi_w_prog_empty_thresh;
output [4:0]axi_w_data_count;
output [4:0]axi_w_wr_data_count;
output [4:0]axi_w_rd_data_count;
output axi_w_sbiterr;
output axi_w_dbiterr;
output axi_w_overflow;
output axi_w_underflow;
output axi_w_prog_full;
output axi_w_prog_empty;
input axi_b_injectsbiterr;
input axi_b_injectdbiterr;
input [3:0]axi_b_prog_full_thresh;
input [3:0]axi_b_prog_empty_thresh;
output [4:0]axi_b_data_count;
output [4:0]axi_b_wr_data_count;
output [4:0]axi_b_rd_data_count;
output axi_b_sbiterr;
output axi_b_dbiterr;
output axi_b_overflow;
output axi_b_underflow;
output axi_b_prog_full;
output axi_b_prog_empty;
input axi_ar_injectsbiterr;
input axi_ar_injectdbiterr;
input [3:0]axi_ar_prog_full_thresh;
input [3:0]axi_ar_prog_empty_thresh;
output [4:0]axi_ar_data_count;
output [4:0]axi_ar_wr_data_count;
output [4:0]axi_ar_rd_data_count;
output axi_ar_sbiterr;
output axi_ar_dbiterr;
output axi_ar_overflow;
output axi_ar_underflow;
output axi_ar_prog_full;
output axi_ar_prog_empty;
input axi_r_injectsbiterr;
input axi_r_injectdbiterr;
input [3:0]axi_r_prog_full_thresh;
input [3:0]axi_r_prog_empty_thresh;
output [4:0]axi_r_data_count;
output [4:0]axi_r_wr_data_count;
output [4:0]axi_r_rd_data_count;
output axi_r_sbiterr;
output axi_r_dbiterr;
output axi_r_overflow;
output axi_r_underflow;
output axi_r_prog_full;
output axi_r_prog_empty;
input axis_injectsbiterr;
input axis_injectdbiterr;
input [9:0]axis_prog_full_thresh;
input [9:0]axis_prog_empty_thresh;
output [10:0]axis_data_count;
output [10:0]axis_wr_data_count;
output [10:0]axis_rd_data_count;
output axis_sbiterr;
output axis_dbiterr;
output axis_overflow;
output axis_underflow;
output axis_prog_full;
output axis_prog_empty;
wire \<const0> ;
wire m_aclk;
wire [27:0]m_axi_araddr;
wire [1:0]m_axi_arburst;
wire [3:0]m_axi_arcache;
wire [0:0]m_axi_arid;
wire [7:0]m_axi_arlen;
wire [0:0]m_axi_arlock;
wire [2:0]m_axi_arprot;
wire [3:0]m_axi_arqos;
wire m_axi_arready;
wire [3:0]m_axi_arregion;
wire [2:0]m_axi_arsize;
wire m_axi_arvalid;
wire [27:0]m_axi_awaddr;
wire [1:0]m_axi_awburst;
wire [3:0]m_axi_awcache;
wire [0:0]m_axi_awid;
wire [7:0]m_axi_awlen;
wire [0:0]m_axi_awlock;
wire [2:0]m_axi_awprot;
wire [3:0]m_axi_awqos;
wire m_axi_awready;
wire [3:0]m_axi_awregion;
wire [2:0]m_axi_awsize;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [127:0]m_axi_rdata;
wire [0:0]m_axi_rid;
wire m_axi_rlast;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [127:0]m_axi_wdata;
wire m_axi_wlast;
wire m_axi_wready;
wire [15:0]m_axi_wstrb;
wire m_axi_wvalid;
wire s_aclk;
wire s_aresetn;
wire [27:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [27:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [127:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [127:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [15:0]s_axi_wstrb;
wire s_axi_wvalid;
assign almost_empty = \<const0> ;
assign almost_full = \<const0> ;
assign axi_ar_data_count[4] = \<const0> ;
assign axi_ar_data_count[3] = \<const0> ;
assign axi_ar_data_count[2] = \<const0> ;
assign axi_ar_data_count[1] = \<const0> ;
assign axi_ar_data_count[0] = \<const0> ;
assign axi_ar_dbiterr = \<const0> ;
assign axi_ar_overflow = \<const0> ;
assign axi_ar_prog_empty = \<const0> ;
assign axi_ar_prog_full = \<const0> ;
assign axi_ar_rd_data_count[4] = \<const0> ;
assign axi_ar_rd_data_count[3] = \<const0> ;
assign axi_ar_rd_data_count[2] = \<const0> ;
assign axi_ar_rd_data_count[1] = \<const0> ;
assign axi_ar_rd_data_count[0] = \<const0> ;
assign axi_ar_sbiterr = \<const0> ;
assign axi_ar_underflow = \<const0> ;
assign axi_ar_wr_data_count[4] = \<const0> ;
assign axi_ar_wr_data_count[3] = \<const0> ;
assign axi_ar_wr_data_count[2] = \<const0> ;
assign axi_ar_wr_data_count[1] = \<const0> ;
assign axi_ar_wr_data_count[0] = \<const0> ;
assign axi_aw_data_count[4] = \<const0> ;
assign axi_aw_data_count[3] = \<const0> ;
assign axi_aw_data_count[2] = \<const0> ;
assign axi_aw_data_count[1] = \<const0> ;
assign axi_aw_data_count[0] = \<const0> ;
assign axi_aw_dbiterr = \<const0> ;
assign axi_aw_overflow = \<const0> ;
assign axi_aw_prog_empty = \<const0> ;
assign axi_aw_prog_full = \<const0> ;
assign axi_aw_rd_data_count[4] = \<const0> ;
assign axi_aw_rd_data_count[3] = \<const0> ;
assign axi_aw_rd_data_count[2] = \<const0> ;
assign axi_aw_rd_data_count[1] = \<const0> ;
assign axi_aw_rd_data_count[0] = \<const0> ;
assign axi_aw_sbiterr = \<const0> ;
assign axi_aw_underflow = \<const0> ;
assign axi_aw_wr_data_count[4] = \<const0> ;
assign axi_aw_wr_data_count[3] = \<const0> ;
assign axi_aw_wr_data_count[2] = \<const0> ;
assign axi_aw_wr_data_count[1] = \<const0> ;
assign axi_aw_wr_data_count[0] = \<const0> ;
assign axi_b_data_count[4] = \<const0> ;
assign axi_b_data_count[3] = \<const0> ;
assign axi_b_data_count[2] = \<const0> ;
assign axi_b_data_count[1] = \<const0> ;
assign axi_b_data_count[0] = \<const0> ;
assign axi_b_dbiterr = \<const0> ;
assign axi_b_overflow = \<const0> ;
assign axi_b_prog_empty = \<const0> ;
assign axi_b_prog_full = \<const0> ;
assign axi_b_rd_data_count[4] = \<const0> ;
assign axi_b_rd_data_count[3] = \<const0> ;
assign axi_b_rd_data_count[2] = \<const0> ;
assign axi_b_rd_data_count[1] = \<const0> ;
assign axi_b_rd_data_count[0] = \<const0> ;
assign axi_b_sbiterr = \<const0> ;
assign axi_b_underflow = \<const0> ;
assign axi_b_wr_data_count[4] = \<const0> ;
assign axi_b_wr_data_count[3] = \<const0> ;
assign axi_b_wr_data_count[2] = \<const0> ;
assign axi_b_wr_data_count[1] = \<const0> ;
assign axi_b_wr_data_count[0] = \<const0> ;
assign axi_r_data_count[4] = \<const0> ;
assign axi_r_data_count[3] = \<const0> ;
assign axi_r_data_count[2] = \<const0> ;
assign axi_r_data_count[1] = \<const0> ;
assign axi_r_data_count[0] = \<const0> ;
assign axi_r_dbiterr = \<const0> ;
assign axi_r_overflow = \<const0> ;
assign axi_r_prog_empty = \<const0> ;
assign axi_r_prog_full = \<const0> ;
assign axi_r_rd_data_count[4] = \<const0> ;
assign axi_r_rd_data_count[3] = \<const0> ;
assign axi_r_rd_data_count[2] = \<const0> ;
assign axi_r_rd_data_count[1] = \<const0> ;
assign axi_r_rd_data_count[0] = \<const0> ;
assign axi_r_sbiterr = \<const0> ;
assign axi_r_underflow = \<const0> ;
assign axi_r_wr_data_count[4] = \<const0> ;
assign axi_r_wr_data_count[3] = \<const0> ;
assign axi_r_wr_data_count[2] = \<const0> ;
assign axi_r_wr_data_count[1] = \<const0> ;
assign axi_r_wr_data_count[0] = \<const0> ;
assign axi_w_data_count[4] = \<const0> ;
assign axi_w_data_count[3] = \<const0> ;
assign axi_w_data_count[2] = \<const0> ;
assign axi_w_data_count[1] = \<const0> ;
assign axi_w_data_count[0] = \<const0> ;
assign axi_w_dbiterr = \<const0> ;
assign axi_w_overflow = \<const0> ;
assign axi_w_prog_empty = \<const0> ;
assign axi_w_prog_full = \<const0> ;
assign axi_w_rd_data_count[4] = \<const0> ;
assign axi_w_rd_data_count[3] = \<const0> ;
assign axi_w_rd_data_count[2] = \<const0> ;
assign axi_w_rd_data_count[1] = \<const0> ;
assign axi_w_rd_data_count[0] = \<const0> ;
assign axi_w_sbiterr = \<const0> ;
assign axi_w_underflow = \<const0> ;
assign axi_w_wr_data_count[4] = \<const0> ;
assign axi_w_wr_data_count[3] = \<const0> ;
assign axi_w_wr_data_count[2] = \<const0> ;
assign axi_w_wr_data_count[1] = \<const0> ;
assign axi_w_wr_data_count[0] = \<const0> ;
assign axis_data_count[10] = \<const0> ;
assign axis_data_count[9] = \<const0> ;
assign axis_data_count[8] = \<const0> ;
assign axis_data_count[7] = \<const0> ;
assign axis_data_count[6] = \<const0> ;
assign axis_data_count[5] = \<const0> ;
assign axis_data_count[4] = \<const0> ;
assign axis_data_count[3] = \<const0> ;
assign axis_data_count[2] = \<const0> ;
assign axis_data_count[1] = \<const0> ;
assign axis_data_count[0] = \<const0> ;
assign axis_dbiterr = \<const0> ;
assign axis_overflow = \<const0> ;
assign axis_prog_empty = \<const0> ;
assign axis_prog_full = \<const0> ;
assign axis_rd_data_count[10] = \<const0> ;
assign axis_rd_data_count[9] = \<const0> ;
assign axis_rd_data_count[8] = \<const0> ;
assign axis_rd_data_count[7] = \<const0> ;
assign axis_rd_data_count[6] = \<const0> ;
assign axis_rd_data_count[5] = \<const0> ;
assign axis_rd_data_count[4] = \<const0> ;
assign axis_rd_data_count[3] = \<const0> ;
assign axis_rd_data_count[2] = \<const0> ;
assign axis_rd_data_count[1] = \<const0> ;
assign axis_rd_data_count[0] = \<const0> ;
assign axis_sbiterr = \<const0> ;
assign axis_underflow = \<const0> ;
assign axis_wr_data_count[10] = \<const0> ;
assign axis_wr_data_count[9] = \<const0> ;
assign axis_wr_data_count[8] = \<const0> ;
assign axis_wr_data_count[7] = \<const0> ;
assign axis_wr_data_count[6] = \<const0> ;
assign axis_wr_data_count[5] = \<const0> ;
assign axis_wr_data_count[4] = \<const0> ;
assign axis_wr_data_count[3] = \<const0> ;
assign axis_wr_data_count[2] = \<const0> ;
assign axis_wr_data_count[1] = \<const0> ;
assign axis_wr_data_count[0] = \<const0> ;
assign data_count[9] = \<const0> ;
assign data_count[8] = \<const0> ;
assign data_count[7] = \<const0> ;
assign data_count[6] = \<const0> ;
assign data_count[5] = \<const0> ;
assign data_count[4] = \<const0> ;
assign data_count[3] = \<const0> ;
assign data_count[2] = \<const0> ;
assign data_count[1] = \<const0> ;
assign data_count[0] = \<const0> ;
assign dbiterr = \<const0> ;
assign dout[17] = \<const0> ;
assign dout[16] = \<const0> ;
assign dout[15] = \<const0> ;
assign dout[14] = \<const0> ;
assign dout[13] = \<const0> ;
assign dout[12] = \<const0> ;
assign dout[11] = \<const0> ;
assign dout[10] = \<const0> ;
assign dout[9] = \<const0> ;
assign dout[8] = \<const0> ;
assign dout[7] = \<const0> ;
assign dout[6] = \<const0> ;
assign dout[5] = \<const0> ;
assign dout[4] = \<const0> ;
assign dout[3] = \<const0> ;
assign dout[2] = \<const0> ;
assign dout[1] = \<const0> ;
assign dout[0] = \<const0> ;
assign empty = \<const0> ;
assign full = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wuser[0] = \<const0> ;
assign m_axis_tdata[7] = \<const0> ;
assign m_axis_tdata[6] = \<const0> ;
assign m_axis_tdata[5] = \<const0> ;
assign m_axis_tdata[4] = \<const0> ;
assign m_axis_tdata[3] = \<const0> ;
assign m_axis_tdata[2] = \<const0> ;
assign m_axis_tdata[1] = \<const0> ;
assign m_axis_tdata[0] = \<const0> ;
assign m_axis_tdest[0] = \<const0> ;
assign m_axis_tid[0] = \<const0> ;
assign m_axis_tkeep[0] = \<const0> ;
assign m_axis_tlast = \<const0> ;
assign m_axis_tstrb[0] = \<const0> ;
assign m_axis_tuser[3] = \<const0> ;
assign m_axis_tuser[2] = \<const0> ;
assign m_axis_tuser[1] = \<const0> ;
assign m_axis_tuser[0] = \<const0> ;
assign m_axis_tvalid = \<const0> ;
assign overflow = \<const0> ;
assign prog_empty = \<const0> ;
assign prog_full = \<const0> ;
assign rd_data_count[9] = \<const0> ;
assign rd_data_count[8] = \<const0> ;
assign rd_data_count[7] = \<const0> ;
assign rd_data_count[6] = \<const0> ;
assign rd_data_count[5] = \<const0> ;
assign rd_data_count[4] = \<const0> ;
assign rd_data_count[3] = \<const0> ;
assign rd_data_count[2] = \<const0> ;
assign rd_data_count[1] = \<const0> ;
assign rd_data_count[0] = \<const0> ;
assign rd_rst_busy = \<const0> ;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axis_tready = \<const0> ;
assign sbiterr = \<const0> ;
assign underflow = \<const0> ;
assign valid = \<const0> ;
assign wr_ack = \<const0> ;
assign wr_data_count[9] = \<const0> ;
assign wr_data_count[8] = \<const0> ;
assign wr_data_count[7] = \<const0> ;
assign wr_data_count[6] = \<const0> ;
assign wr_data_count[5] = \<const0> ;
assign wr_data_count[4] = \<const0> ;
assign wr_data_count[3] = \<const0> ;
assign wr_data_count[2] = \<const0> ;
assign wr_data_count[1] = \<const0> ;
assign wr_data_count[0] = \<const0> ;
assign wr_rst_busy = \<const0> ;
GND GND
(.G(\<const0> ));
system_auto_cc_0_fifo_generator_v13_1_3_synth inst_fifo_gen
(.DI({s_axi_awid,s_axi_awaddr,s_axi_awlen,s_axi_awsize,s_axi_awburst,s_axi_awlock,s_axi_awcache,s_axi_awprot,s_axi_awqos,s_axi_awregion}),
.I115({s_axi_wdata,s_axi_wstrb,s_axi_wlast}),
.I123({s_axi_arid,s_axi_araddr,s_axi_arlen,s_axi_arsize,s_axi_arburst,s_axi_arlock,s_axi_arcache,s_axi_arprot,s_axi_arqos,s_axi_arregion}),
.I127({m_axi_rid,m_axi_rdata,m_axi_rresp,m_axi_rlast}),
.Q({m_axi_awid,m_axi_awaddr,m_axi_awlen,m_axi_awsize,m_axi_awburst,m_axi_awlock,m_axi_awcache,m_axi_awprot,m_axi_awqos,m_axi_awregion}),
.m_aclk(m_aclk),
.\m_axi_arid[0] ({m_axi_arid,m_axi_araddr,m_axi_arlen,m_axi_arsize,m_axi_arburst,m_axi_arlock,m_axi_arcache,m_axi_arprot,m_axi_arqos,m_axi_arregion}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.\m_axi_wdata[127] ({m_axi_wdata,m_axi_wstrb,m_axi_wlast}),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[0] ({s_axi_rid,s_axi_rdata,s_axi_rresp,s_axi_rlast}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "fifo_generator_v13_1_3_synth" *)
module system_auto_cc_0_fifo_generator_v13_1_3_synth
(Q,
\m_axi_wdata[127] ,
s_axi_bid,
s_axi_bresp,
\m_axi_arid[0] ,
\s_axi_rid[0] ,
s_axi_awready,
s_axi_wready,
s_axi_bvalid,
m_axi_awvalid,
m_axi_wvalid,
m_axi_bready,
s_axi_arready,
s_axi_rvalid,
m_axi_arvalid,
m_axi_rready,
m_aclk,
s_aclk,
I115,
m_axi_bresp,
m_axi_bid,
s_axi_bready,
I123,
I127,
DI,
m_axi_awready,
m_axi_wready,
m_axi_bvalid,
m_axi_arready,
m_axi_rvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_arvalid,
s_axi_rready,
s_aresetn);
output [57:0]Q;
output [144:0]\m_axi_wdata[127] ;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [57:0]\m_axi_arid[0] ;
output [131:0]\s_axi_rid[0] ;
output s_axi_awready;
output s_axi_wready;
output s_axi_bvalid;
output m_axi_awvalid;
output m_axi_wvalid;
output m_axi_bready;
output s_axi_arready;
output s_axi_rvalid;
output m_axi_arvalid;
output m_axi_rready;
input m_aclk;
input s_aclk;
input [144:0]I115;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input s_axi_bready;
input [57:0]I123;
input [131:0]I127;
input [57:0]DI;
input m_axi_awready;
input m_axi_wready;
input m_axi_bvalid;
input m_axi_arready;
input m_axi_rvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input s_axi_arvalid;
input s_axi_rready;
input s_aresetn;
wire [57:0]DI;
wire [144:0]I115;
wire [57:0]I123;
wire [131:0]I127;
wire [57:0]Q;
wire inverted_reset;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]m_axi_bid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire [144:0]\m_axi_wdata[127] ;
wire m_axi_wready;
wire m_axi_wvalid;
wire s_aclk;
wire s_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire s_axi_awready;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [131:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_wready;
wire s_axi_wvalid;
system_auto_cc_0_fifo_generator_top \gaxi_full_lite.gread_ch.grach2.axi_rach
(.I123(I123),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_arid[0] (\m_axi_arid[0] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
system_auto_cc_0_fifo_generator_top__parameterized2 \gaxi_full_lite.gread_ch.grdch2.axi_rdch
(.I127(I127),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_aclk(s_aclk),
.s_aresetn(s_aresetn),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
system_auto_cc_0_fifo_generator_top_0 \gaxi_full_lite.gwrite_ch.gwach2.axi_wach
(.DI(DI),
.Q(Q),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
system_auto_cc_0_fifo_generator_top__parameterized0 \gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch
(.I115(I115),
.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.\m_axi_wdata[127] (\m_axi_wdata[127] ),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
system_auto_cc_0_fifo_generator_top__parameterized1 \gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch
(.inverted_reset(inverted_reset),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.s_aclk(s_aclk),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory
(Q,
E,
m_aclk,
s_aclk,
ram_full_fb_i_reg,
DI,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] );
output [57:0]Q;
input [0:0]E;
input m_aclk;
input s_aclk;
input [0:0]ram_full_fb_i_reg;
input [57:0]DI;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [57:0]DI;
wire [0:0]E;
wire [57:0]Q;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]ram_full_fb_i_reg;
wire s_aclk;
system_auto_cc_0_dmem \gdm.dm_gen.dm
(.DI(DI),
.dout_i({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.ram_full_fb_i_reg(ram_full_fb_i_reg),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(Q[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(Q[10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(Q[11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(Q[12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(Q[13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(Q[14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(Q[15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(Q[16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(Q[17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(Q[18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(Q[19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(Q[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(Q[20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(Q[21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(Q[22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(Q[23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(Q[24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(Q[25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(Q[26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(Q[27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(Q[28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(Q[29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(Q[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(Q[30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(Q[31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(Q[32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(Q[33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(Q[34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(Q[35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(Q[36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(Q[37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(Q[38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(Q[39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(Q[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(Q[40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(Q[41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(Q[42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(Q[43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(Q[44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(Q[45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(Q[46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(Q[47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(Q[48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(Q[49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(Q[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(Q[50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(Q[51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(Q[52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(Q[53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(Q[54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(Q[55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(Q[56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(Q[57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(Q[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(Q[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(Q[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(Q[8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(E),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(Q[9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory_73
(\m_axi_arid[0] ,
s_aclk,
E,
I123,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [57:0]\m_axi_arid[0] ;
input s_aclk;
input [0:0]E;
input [57:0]I123;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [57:0]I123;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_9 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [57:0]\m_axi_arid[0] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
system_auto_cc_0_dmem_81 \gdm.dm_gen.dm
(.E(E),
.I123(I123),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\m_axi_arid[0] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\m_axi_arid[0] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\m_axi_arid[0] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\m_axi_arid[0] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\m_axi_arid[0] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\m_axi_arid[0] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\m_axi_arid[0] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\m_axi_arid[0] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\m_axi_arid[0] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\m_axi_arid[0] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\m_axi_arid[0] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\m_axi_arid[0] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\m_axi_arid[0] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\m_axi_arid[0] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\m_axi_arid[0] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\m_axi_arid[0] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\m_axi_arid[0] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\m_axi_arid[0] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\m_axi_arid[0] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\m_axi_arid[0] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\m_axi_arid[0] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\m_axi_arid[0] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\m_axi_arid[0] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\m_axi_arid[0] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\m_axi_arid[0] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\m_axi_arid[0] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\m_axi_arid[0] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\m_axi_arid[0] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\m_axi_arid[0] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\m_axi_arid[0] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\m_axi_arid[0] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\m_axi_arid[0] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\m_axi_arid[0] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\m_axi_arid[0] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\m_axi_arid[0] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\m_axi_arid[0] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\m_axi_arid[0] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\m_axi_arid[0] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\m_axi_arid[0] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\m_axi_arid[0] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\m_axi_arid[0] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\m_axi_arid[0] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\m_axi_arid[0] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\m_axi_arid[0] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\m_axi_arid[0] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\m_axi_arid[0] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\m_axi_arid[0] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\m_axi_arid[0] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\m_axi_arid[0] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\m_axi_arid[0] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\m_axi_arid[0] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\m_axi_arid[0] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\m_axi_arid[0] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\m_axi_arid[0] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\m_axi_arid[0] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\m_axi_arid[0] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\m_axi_arid[0] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\m_axi_arid[0] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory__parameterized0
(\m_axi_wdata[127] ,
s_aclk,
E,
I115,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [144:0]\m_axi_wdata[127] ;
input s_aclk;
input [0:0]E;
input [144:0]I115;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [144:0]I115;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_100 ;
wire \gdm.dm_gen.dm_n_101 ;
wire \gdm.dm_gen.dm_n_102 ;
wire \gdm.dm_gen.dm_n_103 ;
wire \gdm.dm_gen.dm_n_104 ;
wire \gdm.dm_gen.dm_n_105 ;
wire \gdm.dm_gen.dm_n_106 ;
wire \gdm.dm_gen.dm_n_107 ;
wire \gdm.dm_gen.dm_n_108 ;
wire \gdm.dm_gen.dm_n_109 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_110 ;
wire \gdm.dm_gen.dm_n_111 ;
wire \gdm.dm_gen.dm_n_112 ;
wire \gdm.dm_gen.dm_n_113 ;
wire \gdm.dm_gen.dm_n_114 ;
wire \gdm.dm_gen.dm_n_115 ;
wire \gdm.dm_gen.dm_n_116 ;
wire \gdm.dm_gen.dm_n_117 ;
wire \gdm.dm_gen.dm_n_118 ;
wire \gdm.dm_gen.dm_n_119 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_120 ;
wire \gdm.dm_gen.dm_n_121 ;
wire \gdm.dm_gen.dm_n_122 ;
wire \gdm.dm_gen.dm_n_123 ;
wire \gdm.dm_gen.dm_n_124 ;
wire \gdm.dm_gen.dm_n_125 ;
wire \gdm.dm_gen.dm_n_126 ;
wire \gdm.dm_gen.dm_n_127 ;
wire \gdm.dm_gen.dm_n_128 ;
wire \gdm.dm_gen.dm_n_129 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_130 ;
wire \gdm.dm_gen.dm_n_131 ;
wire \gdm.dm_gen.dm_n_132 ;
wire \gdm.dm_gen.dm_n_133 ;
wire \gdm.dm_gen.dm_n_134 ;
wire \gdm.dm_gen.dm_n_135 ;
wire \gdm.dm_gen.dm_n_136 ;
wire \gdm.dm_gen.dm_n_137 ;
wire \gdm.dm_gen.dm_n_138 ;
wire \gdm.dm_gen.dm_n_139 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_140 ;
wire \gdm.dm_gen.dm_n_141 ;
wire \gdm.dm_gen.dm_n_142 ;
wire \gdm.dm_gen.dm_n_143 ;
wire \gdm.dm_gen.dm_n_144 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_58 ;
wire \gdm.dm_gen.dm_n_59 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_60 ;
wire \gdm.dm_gen.dm_n_61 ;
wire \gdm.dm_gen.dm_n_62 ;
wire \gdm.dm_gen.dm_n_63 ;
wire \gdm.dm_gen.dm_n_64 ;
wire \gdm.dm_gen.dm_n_65 ;
wire \gdm.dm_gen.dm_n_66 ;
wire \gdm.dm_gen.dm_n_67 ;
wire \gdm.dm_gen.dm_n_68 ;
wire \gdm.dm_gen.dm_n_69 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_70 ;
wire \gdm.dm_gen.dm_n_71 ;
wire \gdm.dm_gen.dm_n_72 ;
wire \gdm.dm_gen.dm_n_73 ;
wire \gdm.dm_gen.dm_n_74 ;
wire \gdm.dm_gen.dm_n_75 ;
wire \gdm.dm_gen.dm_n_76 ;
wire \gdm.dm_gen.dm_n_77 ;
wire \gdm.dm_gen.dm_n_78 ;
wire \gdm.dm_gen.dm_n_79 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_80 ;
wire \gdm.dm_gen.dm_n_81 ;
wire \gdm.dm_gen.dm_n_82 ;
wire \gdm.dm_gen.dm_n_83 ;
wire \gdm.dm_gen.dm_n_84 ;
wire \gdm.dm_gen.dm_n_85 ;
wire \gdm.dm_gen.dm_n_86 ;
wire \gdm.dm_gen.dm_n_87 ;
wire \gdm.dm_gen.dm_n_88 ;
wire \gdm.dm_gen.dm_n_89 ;
wire \gdm.dm_gen.dm_n_9 ;
wire \gdm.dm_gen.dm_n_90 ;
wire \gdm.dm_gen.dm_n_91 ;
wire \gdm.dm_gen.dm_n_92 ;
wire \gdm.dm_gen.dm_n_93 ;
wire \gdm.dm_gen.dm_n_94 ;
wire \gdm.dm_gen.dm_n_95 ;
wire \gdm.dm_gen.dm_n_96 ;
wire \gdm.dm_gen.dm_n_97 ;
wire \gdm.dm_gen.dm_n_98 ;
wire \gdm.dm_gen.dm_n_99 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [144:0]\m_axi_wdata[127] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
system_auto_cc_0_dmem__parameterized0 \gdm.dm_gen.dm
(.E(E),
.I115(I115),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 ,\gdm.dm_gen.dm_n_58 ,\gdm.dm_gen.dm_n_59 ,\gdm.dm_gen.dm_n_60 ,\gdm.dm_gen.dm_n_61 ,\gdm.dm_gen.dm_n_62 ,\gdm.dm_gen.dm_n_63 ,\gdm.dm_gen.dm_n_64 ,\gdm.dm_gen.dm_n_65 ,\gdm.dm_gen.dm_n_66 ,\gdm.dm_gen.dm_n_67 ,\gdm.dm_gen.dm_n_68 ,\gdm.dm_gen.dm_n_69 ,\gdm.dm_gen.dm_n_70 ,\gdm.dm_gen.dm_n_71 ,\gdm.dm_gen.dm_n_72 ,\gdm.dm_gen.dm_n_73 ,\gdm.dm_gen.dm_n_74 ,\gdm.dm_gen.dm_n_75 ,\gdm.dm_gen.dm_n_76 ,\gdm.dm_gen.dm_n_77 ,\gdm.dm_gen.dm_n_78 ,\gdm.dm_gen.dm_n_79 ,\gdm.dm_gen.dm_n_80 ,\gdm.dm_gen.dm_n_81 ,\gdm.dm_gen.dm_n_82 ,\gdm.dm_gen.dm_n_83 ,\gdm.dm_gen.dm_n_84 ,\gdm.dm_gen.dm_n_85 ,\gdm.dm_gen.dm_n_86 ,\gdm.dm_gen.dm_n_87 ,\gdm.dm_gen.dm_n_88 ,\gdm.dm_gen.dm_n_89 ,\gdm.dm_gen.dm_n_90 ,\gdm.dm_gen.dm_n_91 ,\gdm.dm_gen.dm_n_92 ,\gdm.dm_gen.dm_n_93 ,\gdm.dm_gen.dm_n_94 ,\gdm.dm_gen.dm_n_95 ,\gdm.dm_gen.dm_n_96 ,\gdm.dm_gen.dm_n_97 ,\gdm.dm_gen.dm_n_98 ,\gdm.dm_gen.dm_n_99 ,\gdm.dm_gen.dm_n_100 ,\gdm.dm_gen.dm_n_101 ,\gdm.dm_gen.dm_n_102 ,\gdm.dm_gen.dm_n_103 ,\gdm.dm_gen.dm_n_104 ,\gdm.dm_gen.dm_n_105 ,\gdm.dm_gen.dm_n_106 ,\gdm.dm_gen.dm_n_107 ,\gdm.dm_gen.dm_n_108 ,\gdm.dm_gen.dm_n_109 ,\gdm.dm_gen.dm_n_110 ,\gdm.dm_gen.dm_n_111 ,\gdm.dm_gen.dm_n_112 ,\gdm.dm_gen.dm_n_113 ,\gdm.dm_gen.dm_n_114 ,\gdm.dm_gen.dm_n_115 ,\gdm.dm_gen.dm_n_116 ,\gdm.dm_gen.dm_n_117 ,\gdm.dm_gen.dm_n_118 ,\gdm.dm_gen.dm_n_119 ,\gdm.dm_gen.dm_n_120 ,\gdm.dm_gen.dm_n_121 ,\gdm.dm_gen.dm_n_122 ,\gdm.dm_gen.dm_n_123 ,\gdm.dm_gen.dm_n_124 ,\gdm.dm_gen.dm_n_125 ,\gdm.dm_gen.dm_n_126 ,\gdm.dm_gen.dm_n_127 ,\gdm.dm_gen.dm_n_128 ,\gdm.dm_gen.dm_n_129 ,\gdm.dm_gen.dm_n_130 ,\gdm.dm_gen.dm_n_131 ,\gdm.dm_gen.dm_n_132 ,\gdm.dm_gen.dm_n_133 ,\gdm.dm_gen.dm_n_134 ,\gdm.dm_gen.dm_n_135 ,\gdm.dm_gen.dm_n_136 ,\gdm.dm_gen.dm_n_137 ,\gdm.dm_gen.dm_n_138 ,\gdm.dm_gen.dm_n_139 ,\gdm.dm_gen.dm_n_140 ,\gdm.dm_gen.dm_n_141 ,\gdm.dm_gen.dm_n_142 ,\gdm.dm_gen.dm_n_143 ,\gdm.dm_gen.dm_n_144 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_144 ),
.Q(\m_axi_wdata[127] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[100]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\m_axi_wdata[127] [100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[101]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\m_axi_wdata[127] [101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[102]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\m_axi_wdata[127] [102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[103]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\m_axi_wdata[127] [103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[104]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\m_axi_wdata[127] [104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[105]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\m_axi_wdata[127] [105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[106]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\m_axi_wdata[127] [106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[107]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\m_axi_wdata[127] [107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[108]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\m_axi_wdata[127] [108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[109]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\m_axi_wdata[127] [109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_134 ),
.Q(\m_axi_wdata[127] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[110]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\m_axi_wdata[127] [110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[111]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\m_axi_wdata[127] [111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[112]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\m_axi_wdata[127] [112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[113]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\m_axi_wdata[127] [113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[114]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\m_axi_wdata[127] [114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[115]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\m_axi_wdata[127] [115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[116]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\m_axi_wdata[127] [116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[117]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\m_axi_wdata[127] [117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[118]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\m_axi_wdata[127] [118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[119]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\m_axi_wdata[127] [119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_133 ),
.Q(\m_axi_wdata[127] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[120]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\m_axi_wdata[127] [120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[121]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\m_axi_wdata[127] [121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[122]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\m_axi_wdata[127] [122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[123]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\m_axi_wdata[127] [123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[124]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\m_axi_wdata[127] [124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[125]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\m_axi_wdata[127] [125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[126]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\m_axi_wdata[127] [126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[127]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\m_axi_wdata[127] [127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[128]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\m_axi_wdata[127] [128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[129]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\m_axi_wdata[127] [129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_132 ),
.Q(\m_axi_wdata[127] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[130]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\m_axi_wdata[127] [130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[131]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\m_axi_wdata[127] [131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[132]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\m_axi_wdata[127] [132]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[133]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\m_axi_wdata[127] [133]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[134]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\m_axi_wdata[127] [134]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[135]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\m_axi_wdata[127] [135]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[136]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\m_axi_wdata[127] [136]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[137]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\m_axi_wdata[127] [137]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[138]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\m_axi_wdata[127] [138]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[139]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\m_axi_wdata[127] [139]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_131 ),
.Q(\m_axi_wdata[127] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[140]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\m_axi_wdata[127] [140]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[141]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\m_axi_wdata[127] [141]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[142]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\m_axi_wdata[127] [142]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[143]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\m_axi_wdata[127] [143]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[144]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\m_axi_wdata[127] [144]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_130 ),
.Q(\m_axi_wdata[127] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_129 ),
.Q(\m_axi_wdata[127] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_128 ),
.Q(\m_axi_wdata[127] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_127 ),
.Q(\m_axi_wdata[127] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_126 ),
.Q(\m_axi_wdata[127] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_125 ),
.Q(\m_axi_wdata[127] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_143 ),
.Q(\m_axi_wdata[127] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_124 ),
.Q(\m_axi_wdata[127] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_123 ),
.Q(\m_axi_wdata[127] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_122 ),
.Q(\m_axi_wdata[127] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_121 ),
.Q(\m_axi_wdata[127] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_120 ),
.Q(\m_axi_wdata[127] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_119 ),
.Q(\m_axi_wdata[127] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_118 ),
.Q(\m_axi_wdata[127] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_117 ),
.Q(\m_axi_wdata[127] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_116 ),
.Q(\m_axi_wdata[127] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_115 ),
.Q(\m_axi_wdata[127] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_142 ),
.Q(\m_axi_wdata[127] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_114 ),
.Q(\m_axi_wdata[127] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_113 ),
.Q(\m_axi_wdata[127] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_112 ),
.Q(\m_axi_wdata[127] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_111 ),
.Q(\m_axi_wdata[127] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_110 ),
.Q(\m_axi_wdata[127] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_109 ),
.Q(\m_axi_wdata[127] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_108 ),
.Q(\m_axi_wdata[127] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_107 ),
.Q(\m_axi_wdata[127] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_106 ),
.Q(\m_axi_wdata[127] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_105 ),
.Q(\m_axi_wdata[127] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_141 ),
.Q(\m_axi_wdata[127] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_104 ),
.Q(\m_axi_wdata[127] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_103 ),
.Q(\m_axi_wdata[127] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_102 ),
.Q(\m_axi_wdata[127] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_101 ),
.Q(\m_axi_wdata[127] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_100 ),
.Q(\m_axi_wdata[127] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_99 ),
.Q(\m_axi_wdata[127] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_98 ),
.Q(\m_axi_wdata[127] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_97 ),
.Q(\m_axi_wdata[127] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_96 ),
.Q(\m_axi_wdata[127] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_95 ),
.Q(\m_axi_wdata[127] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_140 ),
.Q(\m_axi_wdata[127] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_94 ),
.Q(\m_axi_wdata[127] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_93 ),
.Q(\m_axi_wdata[127] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_92 ),
.Q(\m_axi_wdata[127] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_91 ),
.Q(\m_axi_wdata[127] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_90 ),
.Q(\m_axi_wdata[127] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_89 ),
.Q(\m_axi_wdata[127] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_88 ),
.Q(\m_axi_wdata[127] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_87 ),
.Q(\m_axi_wdata[127] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_86 ),
.Q(\m_axi_wdata[127] [58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_85 ),
.Q(\m_axi_wdata[127] [59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_139 ),
.Q(\m_axi_wdata[127] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_84 ),
.Q(\m_axi_wdata[127] [60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_83 ),
.Q(\m_axi_wdata[127] [61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_82 ),
.Q(\m_axi_wdata[127] [62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_81 ),
.Q(\m_axi_wdata[127] [63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_80 ),
.Q(\m_axi_wdata[127] [64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[65]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_79 ),
.Q(\m_axi_wdata[127] [65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[66]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_78 ),
.Q(\m_axi_wdata[127] [66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[67]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_77 ),
.Q(\m_axi_wdata[127] [67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[68]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_76 ),
.Q(\m_axi_wdata[127] [68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[69]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_75 ),
.Q(\m_axi_wdata[127] [69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_138 ),
.Q(\m_axi_wdata[127] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[70]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_74 ),
.Q(\m_axi_wdata[127] [70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[71]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_73 ),
.Q(\m_axi_wdata[127] [71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[72]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_72 ),
.Q(\m_axi_wdata[127] [72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[73]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_71 ),
.Q(\m_axi_wdata[127] [73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[74]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_70 ),
.Q(\m_axi_wdata[127] [74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[75]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_69 ),
.Q(\m_axi_wdata[127] [75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[76]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_68 ),
.Q(\m_axi_wdata[127] [76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[77]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_67 ),
.Q(\m_axi_wdata[127] [77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[78]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_66 ),
.Q(\m_axi_wdata[127] [78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[79]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_65 ),
.Q(\m_axi_wdata[127] [79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_137 ),
.Q(\m_axi_wdata[127] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[80]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_64 ),
.Q(\m_axi_wdata[127] [80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[81]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_63 ),
.Q(\m_axi_wdata[127] [81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[82]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_62 ),
.Q(\m_axi_wdata[127] [82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[83]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_61 ),
.Q(\m_axi_wdata[127] [83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[84]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_60 ),
.Q(\m_axi_wdata[127] [84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[85]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_59 ),
.Q(\m_axi_wdata[127] [85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[86]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_58 ),
.Q(\m_axi_wdata[127] [86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[87]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\m_axi_wdata[127] [87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[88]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\m_axi_wdata[127] [88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[89]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\m_axi_wdata[127] [89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_136 ),
.Q(\m_axi_wdata[127] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[90]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\m_axi_wdata[127] [90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[91]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\m_axi_wdata[127] [91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[92]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\m_axi_wdata[127] [92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[93]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\m_axi_wdata[127] [93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[94]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\m_axi_wdata[127] [94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[95]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\m_axi_wdata[127] [95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[96]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\m_axi_wdata[127] [96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[97]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\m_axi_wdata[127] [97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[98]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\m_axi_wdata[127] [98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[99]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\m_axi_wdata[127] [99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(m_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_135 ),
.Q(\m_axi_wdata[127] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory__parameterized1
(s_axi_bid,
s_axi_bresp,
m_aclk,
E,
m_axi_bresp,
m_axi_bid,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk,
out,
\gpregsm1.curr_fwft_state_reg[1]_0 ,
s_axi_bready);
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input m_aclk;
input [0:0]E;
input [1:0]m_axi_bresp;
input [0:0]m_axi_bid;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
input [0:0]out;
input [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ;
input s_axi_bready;
wire [0:0]E;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_2 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire \goreg_dm.dout_i[0]_i_1_n_0 ;
wire \goreg_dm.dout_i[1]_i_1_n_0 ;
wire \goreg_dm.dout_i[2]_i_1_n_0 ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire [1:0]\gpregsm1.curr_fwft_state_reg[1]_0 ;
wire m_aclk;
wire [0:0]m_axi_bid;
wire [1:0]m_axi_bresp;
wire [0:0]out;
wire s_aclk;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
system_auto_cc_0_dmem__parameterized1 \gdm.dm_gen.dm
(.E(E),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.s_aclk(s_aclk));
LUT6 #(
.INIT(64'hEFEFFFEF20200020))
\goreg_dm.dout_i[0]_i_1
(.I0(\gdm.dm_gen.dm_n_2 ),
.I1(out),
.I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]),
.I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]),
.I4(s_axi_bready),
.I5(s_axi_bresp[0]),
.O(\goreg_dm.dout_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFEFFFEF20200020))
\goreg_dm.dout_i[1]_i_1
(.I0(\gdm.dm_gen.dm_n_1 ),
.I1(out),
.I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]),
.I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]),
.I4(s_axi_bready),
.I5(s_axi_bresp[1]),
.O(\goreg_dm.dout_i[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEFEFFFEF20200020))
\goreg_dm.dout_i[2]_i_1
(.I0(\gdm.dm_gen.dm_n_0 ),
.I1(out),
.I2(\gpregsm1.curr_fwft_state_reg[1]_0 [1]),
.I3(\gpregsm1.curr_fwft_state_reg[1]_0 [0]),
.I4(s_axi_bready),
.I5(s_axi_bid),
.O(\goreg_dm.dout_i[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\goreg_dm.dout_i[0]_i_1_n_0 ),
.Q(s_axi_bresp[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(\goreg_dm.dout_i[1]_i_1_n_0 ),
.Q(s_axi_bresp[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(\goreg_dm.dout_i[2]_i_1_n_0 ),
.Q(s_axi_bid),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "memory" *)
module system_auto_cc_0_memory__parameterized2
(\s_axi_rid[0] ,
m_aclk,
E,
I127,
\gc0.count_d1_reg[3] ,
\gic0.gc0.count_d2_reg[3] ,
\gpregsm1.curr_fwft_state_reg[1] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] );
output [131:0]\s_axi_rid[0] ;
input m_aclk;
input [0:0]E;
input [131:0]I127;
input [3:0]\gc0.count_d1_reg[3] ;
input [3:0]\gic0.gc0.count_d2_reg[3] ;
input [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire [0:0]E;
wire [131:0]I127;
wire [3:0]\gc0.count_d1_reg[3] ;
wire \gdm.dm_gen.dm_n_0 ;
wire \gdm.dm_gen.dm_n_1 ;
wire \gdm.dm_gen.dm_n_10 ;
wire \gdm.dm_gen.dm_n_100 ;
wire \gdm.dm_gen.dm_n_101 ;
wire \gdm.dm_gen.dm_n_102 ;
wire \gdm.dm_gen.dm_n_103 ;
wire \gdm.dm_gen.dm_n_104 ;
wire \gdm.dm_gen.dm_n_105 ;
wire \gdm.dm_gen.dm_n_106 ;
wire \gdm.dm_gen.dm_n_107 ;
wire \gdm.dm_gen.dm_n_108 ;
wire \gdm.dm_gen.dm_n_109 ;
wire \gdm.dm_gen.dm_n_11 ;
wire \gdm.dm_gen.dm_n_110 ;
wire \gdm.dm_gen.dm_n_111 ;
wire \gdm.dm_gen.dm_n_112 ;
wire \gdm.dm_gen.dm_n_113 ;
wire \gdm.dm_gen.dm_n_114 ;
wire \gdm.dm_gen.dm_n_115 ;
wire \gdm.dm_gen.dm_n_116 ;
wire \gdm.dm_gen.dm_n_117 ;
wire \gdm.dm_gen.dm_n_118 ;
wire \gdm.dm_gen.dm_n_119 ;
wire \gdm.dm_gen.dm_n_12 ;
wire \gdm.dm_gen.dm_n_120 ;
wire \gdm.dm_gen.dm_n_121 ;
wire \gdm.dm_gen.dm_n_122 ;
wire \gdm.dm_gen.dm_n_123 ;
wire \gdm.dm_gen.dm_n_124 ;
wire \gdm.dm_gen.dm_n_125 ;
wire \gdm.dm_gen.dm_n_126 ;
wire \gdm.dm_gen.dm_n_127 ;
wire \gdm.dm_gen.dm_n_128 ;
wire \gdm.dm_gen.dm_n_129 ;
wire \gdm.dm_gen.dm_n_13 ;
wire \gdm.dm_gen.dm_n_130 ;
wire \gdm.dm_gen.dm_n_131 ;
wire \gdm.dm_gen.dm_n_14 ;
wire \gdm.dm_gen.dm_n_15 ;
wire \gdm.dm_gen.dm_n_16 ;
wire \gdm.dm_gen.dm_n_17 ;
wire \gdm.dm_gen.dm_n_18 ;
wire \gdm.dm_gen.dm_n_19 ;
wire \gdm.dm_gen.dm_n_2 ;
wire \gdm.dm_gen.dm_n_20 ;
wire \gdm.dm_gen.dm_n_21 ;
wire \gdm.dm_gen.dm_n_22 ;
wire \gdm.dm_gen.dm_n_23 ;
wire \gdm.dm_gen.dm_n_24 ;
wire \gdm.dm_gen.dm_n_25 ;
wire \gdm.dm_gen.dm_n_26 ;
wire \gdm.dm_gen.dm_n_27 ;
wire \gdm.dm_gen.dm_n_28 ;
wire \gdm.dm_gen.dm_n_29 ;
wire \gdm.dm_gen.dm_n_3 ;
wire \gdm.dm_gen.dm_n_30 ;
wire \gdm.dm_gen.dm_n_31 ;
wire \gdm.dm_gen.dm_n_32 ;
wire \gdm.dm_gen.dm_n_33 ;
wire \gdm.dm_gen.dm_n_34 ;
wire \gdm.dm_gen.dm_n_35 ;
wire \gdm.dm_gen.dm_n_36 ;
wire \gdm.dm_gen.dm_n_37 ;
wire \gdm.dm_gen.dm_n_38 ;
wire \gdm.dm_gen.dm_n_39 ;
wire \gdm.dm_gen.dm_n_4 ;
wire \gdm.dm_gen.dm_n_40 ;
wire \gdm.dm_gen.dm_n_41 ;
wire \gdm.dm_gen.dm_n_42 ;
wire \gdm.dm_gen.dm_n_43 ;
wire \gdm.dm_gen.dm_n_44 ;
wire \gdm.dm_gen.dm_n_45 ;
wire \gdm.dm_gen.dm_n_46 ;
wire \gdm.dm_gen.dm_n_47 ;
wire \gdm.dm_gen.dm_n_48 ;
wire \gdm.dm_gen.dm_n_49 ;
wire \gdm.dm_gen.dm_n_5 ;
wire \gdm.dm_gen.dm_n_50 ;
wire \gdm.dm_gen.dm_n_51 ;
wire \gdm.dm_gen.dm_n_52 ;
wire \gdm.dm_gen.dm_n_53 ;
wire \gdm.dm_gen.dm_n_54 ;
wire \gdm.dm_gen.dm_n_55 ;
wire \gdm.dm_gen.dm_n_56 ;
wire \gdm.dm_gen.dm_n_57 ;
wire \gdm.dm_gen.dm_n_58 ;
wire \gdm.dm_gen.dm_n_59 ;
wire \gdm.dm_gen.dm_n_6 ;
wire \gdm.dm_gen.dm_n_60 ;
wire \gdm.dm_gen.dm_n_61 ;
wire \gdm.dm_gen.dm_n_62 ;
wire \gdm.dm_gen.dm_n_63 ;
wire \gdm.dm_gen.dm_n_64 ;
wire \gdm.dm_gen.dm_n_65 ;
wire \gdm.dm_gen.dm_n_66 ;
wire \gdm.dm_gen.dm_n_67 ;
wire \gdm.dm_gen.dm_n_68 ;
wire \gdm.dm_gen.dm_n_69 ;
wire \gdm.dm_gen.dm_n_7 ;
wire \gdm.dm_gen.dm_n_70 ;
wire \gdm.dm_gen.dm_n_71 ;
wire \gdm.dm_gen.dm_n_72 ;
wire \gdm.dm_gen.dm_n_73 ;
wire \gdm.dm_gen.dm_n_74 ;
wire \gdm.dm_gen.dm_n_75 ;
wire \gdm.dm_gen.dm_n_76 ;
wire \gdm.dm_gen.dm_n_77 ;
wire \gdm.dm_gen.dm_n_78 ;
wire \gdm.dm_gen.dm_n_79 ;
wire \gdm.dm_gen.dm_n_8 ;
wire \gdm.dm_gen.dm_n_80 ;
wire \gdm.dm_gen.dm_n_81 ;
wire \gdm.dm_gen.dm_n_82 ;
wire \gdm.dm_gen.dm_n_83 ;
wire \gdm.dm_gen.dm_n_84 ;
wire \gdm.dm_gen.dm_n_85 ;
wire \gdm.dm_gen.dm_n_86 ;
wire \gdm.dm_gen.dm_n_87 ;
wire \gdm.dm_gen.dm_n_88 ;
wire \gdm.dm_gen.dm_n_89 ;
wire \gdm.dm_gen.dm_n_9 ;
wire \gdm.dm_gen.dm_n_90 ;
wire \gdm.dm_gen.dm_n_91 ;
wire \gdm.dm_gen.dm_n_92 ;
wire \gdm.dm_gen.dm_n_93 ;
wire \gdm.dm_gen.dm_n_94 ;
wire \gdm.dm_gen.dm_n_95 ;
wire \gdm.dm_gen.dm_n_96 ;
wire \gdm.dm_gen.dm_n_97 ;
wire \gdm.dm_gen.dm_n_98 ;
wire \gdm.dm_gen.dm_n_99 ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ;
wire s_aclk;
wire [131:0]\s_axi_rid[0] ;
system_auto_cc_0_dmem__parameterized2 \gdm.dm_gen.dm
(.E(E),
.I127(I127),
.Q({\gdm.dm_gen.dm_n_0 ,\gdm.dm_gen.dm_n_1 ,\gdm.dm_gen.dm_n_2 ,\gdm.dm_gen.dm_n_3 ,\gdm.dm_gen.dm_n_4 ,\gdm.dm_gen.dm_n_5 ,\gdm.dm_gen.dm_n_6 ,\gdm.dm_gen.dm_n_7 ,\gdm.dm_gen.dm_n_8 ,\gdm.dm_gen.dm_n_9 ,\gdm.dm_gen.dm_n_10 ,\gdm.dm_gen.dm_n_11 ,\gdm.dm_gen.dm_n_12 ,\gdm.dm_gen.dm_n_13 ,\gdm.dm_gen.dm_n_14 ,\gdm.dm_gen.dm_n_15 ,\gdm.dm_gen.dm_n_16 ,\gdm.dm_gen.dm_n_17 ,\gdm.dm_gen.dm_n_18 ,\gdm.dm_gen.dm_n_19 ,\gdm.dm_gen.dm_n_20 ,\gdm.dm_gen.dm_n_21 ,\gdm.dm_gen.dm_n_22 ,\gdm.dm_gen.dm_n_23 ,\gdm.dm_gen.dm_n_24 ,\gdm.dm_gen.dm_n_25 ,\gdm.dm_gen.dm_n_26 ,\gdm.dm_gen.dm_n_27 ,\gdm.dm_gen.dm_n_28 ,\gdm.dm_gen.dm_n_29 ,\gdm.dm_gen.dm_n_30 ,\gdm.dm_gen.dm_n_31 ,\gdm.dm_gen.dm_n_32 ,\gdm.dm_gen.dm_n_33 ,\gdm.dm_gen.dm_n_34 ,\gdm.dm_gen.dm_n_35 ,\gdm.dm_gen.dm_n_36 ,\gdm.dm_gen.dm_n_37 ,\gdm.dm_gen.dm_n_38 ,\gdm.dm_gen.dm_n_39 ,\gdm.dm_gen.dm_n_40 ,\gdm.dm_gen.dm_n_41 ,\gdm.dm_gen.dm_n_42 ,\gdm.dm_gen.dm_n_43 ,\gdm.dm_gen.dm_n_44 ,\gdm.dm_gen.dm_n_45 ,\gdm.dm_gen.dm_n_46 ,\gdm.dm_gen.dm_n_47 ,\gdm.dm_gen.dm_n_48 ,\gdm.dm_gen.dm_n_49 ,\gdm.dm_gen.dm_n_50 ,\gdm.dm_gen.dm_n_51 ,\gdm.dm_gen.dm_n_52 ,\gdm.dm_gen.dm_n_53 ,\gdm.dm_gen.dm_n_54 ,\gdm.dm_gen.dm_n_55 ,\gdm.dm_gen.dm_n_56 ,\gdm.dm_gen.dm_n_57 ,\gdm.dm_gen.dm_n_58 ,\gdm.dm_gen.dm_n_59 ,\gdm.dm_gen.dm_n_60 ,\gdm.dm_gen.dm_n_61 ,\gdm.dm_gen.dm_n_62 ,\gdm.dm_gen.dm_n_63 ,\gdm.dm_gen.dm_n_64 ,\gdm.dm_gen.dm_n_65 ,\gdm.dm_gen.dm_n_66 ,\gdm.dm_gen.dm_n_67 ,\gdm.dm_gen.dm_n_68 ,\gdm.dm_gen.dm_n_69 ,\gdm.dm_gen.dm_n_70 ,\gdm.dm_gen.dm_n_71 ,\gdm.dm_gen.dm_n_72 ,\gdm.dm_gen.dm_n_73 ,\gdm.dm_gen.dm_n_74 ,\gdm.dm_gen.dm_n_75 ,\gdm.dm_gen.dm_n_76 ,\gdm.dm_gen.dm_n_77 ,\gdm.dm_gen.dm_n_78 ,\gdm.dm_gen.dm_n_79 ,\gdm.dm_gen.dm_n_80 ,\gdm.dm_gen.dm_n_81 ,\gdm.dm_gen.dm_n_82 ,\gdm.dm_gen.dm_n_83 ,\gdm.dm_gen.dm_n_84 ,\gdm.dm_gen.dm_n_85 ,\gdm.dm_gen.dm_n_86 ,\gdm.dm_gen.dm_n_87 ,\gdm.dm_gen.dm_n_88 ,\gdm.dm_gen.dm_n_89 ,\gdm.dm_gen.dm_n_90 ,\gdm.dm_gen.dm_n_91 ,\gdm.dm_gen.dm_n_92 ,\gdm.dm_gen.dm_n_93 ,\gdm.dm_gen.dm_n_94 ,\gdm.dm_gen.dm_n_95 ,\gdm.dm_gen.dm_n_96 ,\gdm.dm_gen.dm_n_97 ,\gdm.dm_gen.dm_n_98 ,\gdm.dm_gen.dm_n_99 ,\gdm.dm_gen.dm_n_100 ,\gdm.dm_gen.dm_n_101 ,\gdm.dm_gen.dm_n_102 ,\gdm.dm_gen.dm_n_103 ,\gdm.dm_gen.dm_n_104 ,\gdm.dm_gen.dm_n_105 ,\gdm.dm_gen.dm_n_106 ,\gdm.dm_gen.dm_n_107 ,\gdm.dm_gen.dm_n_108 ,\gdm.dm_gen.dm_n_109 ,\gdm.dm_gen.dm_n_110 ,\gdm.dm_gen.dm_n_111 ,\gdm.dm_gen.dm_n_112 ,\gdm.dm_gen.dm_n_113 ,\gdm.dm_gen.dm_n_114 ,\gdm.dm_gen.dm_n_115 ,\gdm.dm_gen.dm_n_116 ,\gdm.dm_gen.dm_n_117 ,\gdm.dm_gen.dm_n_118 ,\gdm.dm_gen.dm_n_119 ,\gdm.dm_gen.dm_n_120 ,\gdm.dm_gen.dm_n_121 ,\gdm.dm_gen.dm_n_122 ,\gdm.dm_gen.dm_n_123 ,\gdm.dm_gen.dm_n_124 ,\gdm.dm_gen.dm_n_125 ,\gdm.dm_gen.dm_n_126 ,\gdm.dm_gen.dm_n_127 ,\gdm.dm_gen.dm_n_128 ,\gdm.dm_gen.dm_n_129 ,\gdm.dm_gen.dm_n_130 ,\gdm.dm_gen.dm_n_131 }),
.\gc0.count_d1_reg[3] (\gc0.count_d1_reg[3] ),
.\gic0.gc0.count_d2_reg[3] (\gic0.gc0.count_d2_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gpregsm1.curr_fwft_state_reg[1] ),
.m_aclk(m_aclk),
.s_aclk(s_aclk));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[0]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_131 ),
.Q(\s_axi_rid[0] [0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[100]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_31 ),
.Q(\s_axi_rid[0] [100]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[101]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_30 ),
.Q(\s_axi_rid[0] [101]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[102]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_29 ),
.Q(\s_axi_rid[0] [102]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[103]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_28 ),
.Q(\s_axi_rid[0] [103]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[104]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_27 ),
.Q(\s_axi_rid[0] [104]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[105]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_26 ),
.Q(\s_axi_rid[0] [105]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[106]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_25 ),
.Q(\s_axi_rid[0] [106]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[107]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_24 ),
.Q(\s_axi_rid[0] [107]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[108]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_23 ),
.Q(\s_axi_rid[0] [108]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[109]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_22 ),
.Q(\s_axi_rid[0] [109]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[10]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_121 ),
.Q(\s_axi_rid[0] [10]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[110]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_21 ),
.Q(\s_axi_rid[0] [110]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[111]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_20 ),
.Q(\s_axi_rid[0] [111]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[112]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_19 ),
.Q(\s_axi_rid[0] [112]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[113]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_18 ),
.Q(\s_axi_rid[0] [113]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[114]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_17 ),
.Q(\s_axi_rid[0] [114]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[115]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_16 ),
.Q(\s_axi_rid[0] [115]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[116]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_15 ),
.Q(\s_axi_rid[0] [116]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[117]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_14 ),
.Q(\s_axi_rid[0] [117]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[118]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_13 ),
.Q(\s_axi_rid[0] [118]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[119]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_12 ),
.Q(\s_axi_rid[0] [119]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[11]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_120 ),
.Q(\s_axi_rid[0] [11]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[120]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_11 ),
.Q(\s_axi_rid[0] [120]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[121]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_10 ),
.Q(\s_axi_rid[0] [121]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[122]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_9 ),
.Q(\s_axi_rid[0] [122]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[123]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_8 ),
.Q(\s_axi_rid[0] [123]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[124]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_7 ),
.Q(\s_axi_rid[0] [124]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[125]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_6 ),
.Q(\s_axi_rid[0] [125]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[126]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_5 ),
.Q(\s_axi_rid[0] [126]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[127]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_4 ),
.Q(\s_axi_rid[0] [127]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[128]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_3 ),
.Q(\s_axi_rid[0] [128]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[129]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_2 ),
.Q(\s_axi_rid[0] [129]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[12]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_119 ),
.Q(\s_axi_rid[0] [12]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[130]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_1 ),
.Q(\s_axi_rid[0] [130]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[131]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_0 ),
.Q(\s_axi_rid[0] [131]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[13]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_118 ),
.Q(\s_axi_rid[0] [13]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[14]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_117 ),
.Q(\s_axi_rid[0] [14]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[15]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_116 ),
.Q(\s_axi_rid[0] [15]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[16]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_115 ),
.Q(\s_axi_rid[0] [16]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[17]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_114 ),
.Q(\s_axi_rid[0] [17]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[18]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_113 ),
.Q(\s_axi_rid[0] [18]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[19]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_112 ),
.Q(\s_axi_rid[0] [19]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[1]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_130 ),
.Q(\s_axi_rid[0] [1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[20]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_111 ),
.Q(\s_axi_rid[0] [20]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[21]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_110 ),
.Q(\s_axi_rid[0] [21]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[22]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_109 ),
.Q(\s_axi_rid[0] [22]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[23]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_108 ),
.Q(\s_axi_rid[0] [23]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[24]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_107 ),
.Q(\s_axi_rid[0] [24]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[25]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_106 ),
.Q(\s_axi_rid[0] [25]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[26]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_105 ),
.Q(\s_axi_rid[0] [26]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[27]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_104 ),
.Q(\s_axi_rid[0] [27]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[28]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_103 ),
.Q(\s_axi_rid[0] [28]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[29]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_102 ),
.Q(\s_axi_rid[0] [29]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[2]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_129 ),
.Q(\s_axi_rid[0] [2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[30]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_101 ),
.Q(\s_axi_rid[0] [30]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[31]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_100 ),
.Q(\s_axi_rid[0] [31]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[32]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_99 ),
.Q(\s_axi_rid[0] [32]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[33]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_98 ),
.Q(\s_axi_rid[0] [33]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[34]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_97 ),
.Q(\s_axi_rid[0] [34]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[35]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_96 ),
.Q(\s_axi_rid[0] [35]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[36]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_95 ),
.Q(\s_axi_rid[0] [36]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[37]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_94 ),
.Q(\s_axi_rid[0] [37]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[38]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_93 ),
.Q(\s_axi_rid[0] [38]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[39]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_92 ),
.Q(\s_axi_rid[0] [39]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[3]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_128 ),
.Q(\s_axi_rid[0] [3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[40]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_91 ),
.Q(\s_axi_rid[0] [40]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[41]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_90 ),
.Q(\s_axi_rid[0] [41]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[42]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_89 ),
.Q(\s_axi_rid[0] [42]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[43]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_88 ),
.Q(\s_axi_rid[0] [43]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[44]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_87 ),
.Q(\s_axi_rid[0] [44]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[45]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_86 ),
.Q(\s_axi_rid[0] [45]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[46]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_85 ),
.Q(\s_axi_rid[0] [46]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[47]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_84 ),
.Q(\s_axi_rid[0] [47]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[48]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_83 ),
.Q(\s_axi_rid[0] [48]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[49]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_82 ),
.Q(\s_axi_rid[0] [49]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[4]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_127 ),
.Q(\s_axi_rid[0] [4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[50]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_81 ),
.Q(\s_axi_rid[0] [50]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[51]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_80 ),
.Q(\s_axi_rid[0] [51]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[52]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_79 ),
.Q(\s_axi_rid[0] [52]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[53]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_78 ),
.Q(\s_axi_rid[0] [53]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[54]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_77 ),
.Q(\s_axi_rid[0] [54]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[55]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_76 ),
.Q(\s_axi_rid[0] [55]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[56]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_75 ),
.Q(\s_axi_rid[0] [56]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[57]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_74 ),
.Q(\s_axi_rid[0] [57]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[58]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_73 ),
.Q(\s_axi_rid[0] [58]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[59]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_72 ),
.Q(\s_axi_rid[0] [59]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[5]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_126 ),
.Q(\s_axi_rid[0] [5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[60]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_71 ),
.Q(\s_axi_rid[0] [60]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[61]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_70 ),
.Q(\s_axi_rid[0] [61]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[62]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_69 ),
.Q(\s_axi_rid[0] [62]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[63]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_68 ),
.Q(\s_axi_rid[0] [63]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[64]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_67 ),
.Q(\s_axi_rid[0] [64]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[65]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_66 ),
.Q(\s_axi_rid[0] [65]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[66]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_65 ),
.Q(\s_axi_rid[0] [66]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[67]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_64 ),
.Q(\s_axi_rid[0] [67]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[68]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_63 ),
.Q(\s_axi_rid[0] [68]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[69]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_62 ),
.Q(\s_axi_rid[0] [69]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[6]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_125 ),
.Q(\s_axi_rid[0] [6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[70]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_61 ),
.Q(\s_axi_rid[0] [70]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[71]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_60 ),
.Q(\s_axi_rid[0] [71]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[72]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_59 ),
.Q(\s_axi_rid[0] [72]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[73]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_58 ),
.Q(\s_axi_rid[0] [73]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[74]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_57 ),
.Q(\s_axi_rid[0] [74]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[75]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_56 ),
.Q(\s_axi_rid[0] [75]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[76]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_55 ),
.Q(\s_axi_rid[0] [76]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[77]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_54 ),
.Q(\s_axi_rid[0] [77]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[78]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_53 ),
.Q(\s_axi_rid[0] [78]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[79]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_52 ),
.Q(\s_axi_rid[0] [79]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[7]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_124 ),
.Q(\s_axi_rid[0] [7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[80]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_51 ),
.Q(\s_axi_rid[0] [80]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[81]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_50 ),
.Q(\s_axi_rid[0] [81]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[82]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_49 ),
.Q(\s_axi_rid[0] [82]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[83]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_48 ),
.Q(\s_axi_rid[0] [83]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[84]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_47 ),
.Q(\s_axi_rid[0] [84]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[85]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_46 ),
.Q(\s_axi_rid[0] [85]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[86]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_45 ),
.Q(\s_axi_rid[0] [86]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[87]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_44 ),
.Q(\s_axi_rid[0] [87]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[88]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_43 ),
.Q(\s_axi_rid[0] [88]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[89]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_42 ),
.Q(\s_axi_rid[0] [89]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[8]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_123 ),
.Q(\s_axi_rid[0] [8]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[90]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_41 ),
.Q(\s_axi_rid[0] [90]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[91]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_40 ),
.Q(\s_axi_rid[0] [91]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[92]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_39 ),
.Q(\s_axi_rid[0] [92]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[93]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_38 ),
.Q(\s_axi_rid[0] [93]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[94]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_37 ),
.Q(\s_axi_rid[0] [94]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[95]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_36 ),
.Q(\s_axi_rid[0] [95]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[96]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_35 ),
.Q(\s_axi_rid[0] [96]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[97]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_34 ),
.Q(\s_axi_rid[0] [97]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[98]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_33 ),
.Q(\s_axi_rid[0] [98]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[99]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_32 ),
.Q(\s_axi_rid[0] [99]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\goreg_dm.dout_i_reg[9]
(.C(s_aclk),
.CE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0] ),
.D(\gdm.dm_gen.dm_n_122 ),
.Q(\s_axi_rid[0] [9]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire [3:0]plusOp__6;
wire ram_empty_i_i_2__2_n_0;
wire ram_empty_i_i_3__2_n_0;
wire ram_empty_i_reg;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__2
(.I0(Q[0]),
.O(plusOp__6[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__6[1]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__6[2]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__6[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.D(plusOp__6[0]),
.PRE(AR),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__6[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__6[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__6[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__2
(.I0(ram_empty_i_i_2__2_n_0),
.I1(ram_empty_i_i_3__2_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__2_n_0));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__2_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_20
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp__0;
wire ram_empty_i_i_2__0_n_0;
wire ram_empty_i_i_3__0_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__0
(.I0(Q[0]),
.O(plusOp__0[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__0[1]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__0[2]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__0[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp__0[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__0[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__0
(.I0(ram_empty_i_i_2__0_n_0),
.I1(ram_empty_i_i_3__0_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__0_n_0));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__0
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__0_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_41
(Q,
ram_empty_i_reg,
\gnxpm_cdc.rd_pntr_gc_reg[2] ,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [0:0]E;
wire [3:0]Q;
wire [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp;
wire ram_empty_i_i_2_n_0;
wire ram_empty_i_i_3_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [1]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(\gnxpm_cdc.rd_pntr_gc_reg[2] [2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1
(.I0(ram_empty_i_i_2_n_0),
.I1(ram_empty_i_i_3_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2_n_0));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_62
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
s_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire [0:0]out;
wire [3:0]plusOp__8;
wire ram_empty_i_i_2__3_n_0;
wire ram_empty_i_i_3__3_n_0;
wire ram_empty_i_reg;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__3
(.I0(Q[0]),
.O(plusOp__8[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__8[1]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__8[2]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__8[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.D(plusOp__8[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(out),
.D(plusOp__8[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__3
(.I0(ram_empty_i_i_2__3_n_0),
.I1(ram_empty_i_i_3__3_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__3_n_0));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__3
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__3_n_0));
endmodule
(* ORIG_REF_NAME = "rd_bin_cntr" *)
module system_auto_cc_0_rd_bin_cntr_86
(Q,
ram_empty_i_reg,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gpregsm1.curr_fwft_state_reg[1] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
E,
m_aclk,
out);
output [3:0]Q;
output ram_empty_i_reg;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input \gpregsm1.curr_fwft_state_reg[1] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]out;
wire [2:0]D;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gpregsm1.curr_fwft_state_reg[1] ;
wire m_aclk;
wire [0:0]out;
wire [3:0]plusOp__2;
wire ram_empty_i_i_2__1_n_0;
wire ram_empty_i_i_3__1_n_0;
wire ram_empty_i_reg;
LUT1 #(
.INIT(2'h1))
\gc0.count[0]_i_1__1
(.I0(Q[0]),
.O(plusOp__2[0]));
LUT2 #(
.INIT(4'h6))
\gc0.count[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__2[1]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h78))
\gc0.count[2]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__2[2]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h7F80))
\gc0.count[3]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__2[3]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[0]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[1]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[2]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(Q[3]),
.Q(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]));
FDPE #(
.INIT(1'b1))
\gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.D(plusOp__2[0]),
.PRE(out),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(out),
.D(plusOp__2[3]),
.Q(Q[3]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.O(D[0]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.O(D[2]));
LUT4 #(
.INIT(16'hF888))
ram_empty_i_i_1__1
(.I0(ram_empty_i_i_2__1_n_0),
.I1(ram_empty_i_i_3__1_n_0),
.I2(\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.I3(\gpregsm1.curr_fwft_state_reg[1] ),
.O(ram_empty_i_reg));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_2__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [2]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [2]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [3]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.O(ram_empty_i_i_2__1_n_0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h9009))
ram_empty_i_i_3__1
(.I0(\gnxpm_cdc.rd_pntr_gc_reg[3] [0]),
.I1(\gnxpm_cdc.wr_pntr_bin_reg[3] [0]),
.I2(\gnxpm_cdc.rd_pntr_gc_reg[3] [1]),
.I3(\gnxpm_cdc.wr_pntr_bin_reg[3] [1]),
.O(ram_empty_i_i_3__1_n_0));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft
(out,
ram_empty_i_reg,
E,
s_axi_bvalid,
s_aclk,
AR,
s_axi_bready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output [1:0]out;
output ram_empty_i_reg;
output [0:0]E;
output s_axi_bvalid;
input s_aclk;
input [0:0]AR;
input s_axi_bready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]AR;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [1:0]next_fwft_state;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire s_aclk;
wire s_axi_bready;
wire s_axi_bvalid;
(* DONT_TOUCH *) wire user_valid;
assign out[1:0] = curr_fwft_state;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__2
(.I0(ram_empty_fb_i_reg),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(AR),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(AR),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__2
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(AR),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__2
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_bready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(AR),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(AR),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(s_axi_bready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__2
(.I0(curr_fwft_state[1]),
.I1(s_axi_bready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
LUT1 #(
.INIT(2'h1))
s_axi_bvalid_INST_0
(.I0(empty_fwft_i),
.O(s_axi_bvalid));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_18
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[144] ,
m_axi_wvalid,
m_aclk,
out,
m_axi_wready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[144] ;
output m_axi_wvalid;
input m_aclk;
input [1:0]out;
input m_axi_wready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[144] ;
wire m_aclk;
wire m_axi_wready;
wire m_axi_wvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__0
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__0
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__0
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[144]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_wready),
.O(\goreg_dm.dout_i_reg[144] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_wready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_wvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_wvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__0
(.I0(curr_fwft_state[1]),
.I1(m_axi_wready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_39
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[57] ,
m_axi_awvalid,
m_aclk,
out,
m_axi_awready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output m_axi_awvalid;
input m_aclk;
input [1:0]out;
input m_axi_awready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[57]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_awready),
.O(\goreg_dm.dout_i_reg[57] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_awready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_awvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_awvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5
(.I0(curr_fwft_state[1]),
.I1(m_axi_awready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_60
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[131] ,
s_axi_rvalid,
s_aclk,
out,
s_axi_rready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[131] ;
output s_axi_rvalid;
input s_aclk;
input [1:0]out;
input s_axi_rready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[131] ;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
wire s_aclk;
wire s_axi_rready;
wire s_axi_rvalid;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__3
(.I0(ram_empty_fb_i_reg),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__3
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__3
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[131]_i_1
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(s_axi_rready),
.O(\goreg_dm.dout_i_reg[131] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(s_axi_rready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(s_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__3
(.I0(curr_fwft_state[1]),
.I1(s_axi_rready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
LUT1 #(
.INIT(2'h1))
s_axi_rvalid_INST_0
(.I0(empty_fwft_i),
.O(s_axi_rvalid));
endmodule
(* ORIG_REF_NAME = "rd_fwft" *)
module system_auto_cc_0_rd_fwft_84
(ram_empty_i_reg,
E,
\goreg_dm.dout_i_reg[57] ,
m_axi_arvalid,
m_aclk,
out,
m_axi_arready,
ram_empty_fb_i_reg,
\gnxpm_cdc.wr_pntr_bin_reg[3] ,
Q);
output ram_empty_i_reg;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output m_axi_arvalid;
input m_aclk;
input [1:0]out;
input m_axi_arready;
input ram_empty_fb_i_reg;
input [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
input [0:0]Q;
wire [0:0]E;
wire [0:0]Q;
(* DONT_TOUCH *) wire aempty_fwft_fb_i;
(* DONT_TOUCH *) wire aempty_fwft_i;
wire aempty_fwft_i0;
(* DONT_TOUCH *) wire [1:0]curr_fwft_state;
(* DONT_TOUCH *) wire empty_fwft_fb_i;
(* DONT_TOUCH *) wire empty_fwft_fb_o_i;
wire empty_fwft_fb_o_i0;
(* DONT_TOUCH *) wire empty_fwft_i;
wire empty_fwft_i0;
wire [0:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire m_aclk;
wire m_axi_arready;
wire m_axi_arvalid;
wire [1:0]next_fwft_state;
wire [1:0]out;
wire ram_empty_fb_i_reg;
wire ram_empty_i_reg;
(* DONT_TOUCH *) wire user_valid;
LUT5 #(
.INIT(32'hFAEF8000))
aempty_fwft_fb_i_i_1__1
(.I0(ram_empty_fb_i_reg),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(curr_fwft_state[1]),
.I4(aempty_fwft_fb_i),
.O(aempty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
aempty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(aempty_fwft_i0),
.PRE(out[1]),
.Q(aempty_fwft_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_i_i_1__1
(.I0(empty_fwft_fb_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(empty_fwft_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_i));
LUT4 #(
.INIT(16'hB2A2))
empty_fwft_fb_o_i_i_1__1
(.I0(empty_fwft_fb_o_i),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(empty_fwft_fb_o_i0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_fb_o_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_fb_o_i0),
.PRE(out[1]),
.Q(empty_fwft_fb_o_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
empty_fwft_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(empty_fwft_i0),
.PRE(out[1]),
.Q(empty_fwft_i));
LUT4 #(
.INIT(16'h00DF))
\gc0.count_d1[3]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(E));
LUT4 #(
.INIT(16'h4404))
\goreg_dm.dout_i[57]_i_1__0
(.I0(out[0]),
.I1(curr_fwft_state[1]),
.I2(curr_fwft_state[0]),
.I3(m_axi_arready),
.O(\goreg_dm.dout_i_reg[57] ));
LUT3 #(
.INIT(8'hAE))
\gpregsm1.curr_fwft_state[0]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(curr_fwft_state[0]),
.I2(m_axi_arready),
.O(next_fwft_state[0]));
LUT4 #(
.INIT(16'h20FF))
\gpregsm1.curr_fwft_state[1]_i_1__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.O(next_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(curr_fwft_state[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.curr_fwft_state_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[1]),
.Q(curr_fwft_state[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDCE #(
.INIT(1'b0))
\gpregsm1.user_valid_reg
(.C(m_aclk),
.CE(1'b1),
.CLR(out[1]),
.D(next_fwft_state[0]),
.Q(user_valid));
LUT1 #(
.INIT(2'h1))
m_axi_arvalid_INST_0
(.I0(empty_fwft_i),
.O(m_axi_arvalid));
LUT6 #(
.INIT(64'h00DF0000000000DF))
ram_empty_i_i_5__1
(.I0(curr_fwft_state[1]),
.I1(m_axi_arready),
.I2(curr_fwft_state[0]),
.I3(ram_empty_fb_i_reg),
.I4(\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.I5(Q),
.O(ram_empty_i_reg));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic
(out,
Q,
E,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
s_axi_bvalid,
s_aclk,
AR,
s_axi_bready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [1:0]out;
output [2:0]Q;
output [0:0]E;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output s_axi_bvalid;
input s_aclk;
input [0:0]AR;
input s_axi_bready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]AR;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire \gr1.gr1_int.rfwft_n_2 ;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
wire s_aclk;
wire s_axi_bready;
wire s_axi_bvalid;
system_auto_cc_0_rd_fwft \gr1.gr1_int.rfwft
(.AR(AR),
.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_2 ),
.s_aclk(s_aclk),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid));
system_auto_cc_0_rd_status_flags_as \gras.rsts
(.AR(AR),
.\gc0.count_d1_reg[2] (rpntr_n_4),
.out(p_2_out),
.s_aclk(s_aclk));
system_auto_cc_0_rd_bin_cntr rpntr
(.AR(AR),
.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_2 ),
.ram_empty_i_reg(rpntr_n_4),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_28
(Q,
E,
\goreg_dm.dout_i_reg[57] ,
\gnxpm_cdc.rd_pntr_gc_reg[2] ,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_awvalid,
m_aclk,
out,
m_axi_awready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_awvalid;
input m_aclk;
input [1:0]out;
input m_axi_awready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]E;
wire [2:0]Q;
wire [2:0]\gnxpm_cdc.rd_pntr_gc_reg[2] ;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_awready;
wire m_axi_awvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
system_auto_cc_0_rd_fwft_39 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[57] (\goreg_dm.dout_i_reg[57] ),
.m_aclk(m_aclk),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
system_auto_cc_0_rd_status_flags_as_40 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
system_auto_cc_0_rd_bin_cntr_41 rpntr
(.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[2] (\gnxpm_cdc.rd_pntr_gc_reg[2] ),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_49
(Q,
E,
\goreg_dm.dout_i_reg[131] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
s_axi_rvalid,
s_aclk,
out,
s_axi_rready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[131] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output s_axi_rvalid;
input s_aclk;
input [1:0]out;
input s_axi_rready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[131] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
wire s_aclk;
wire s_axi_rready;
wire s_axi_rvalid;
system_auto_cc_0_rd_fwft_60 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[131] (\goreg_dm.dout_i_reg[131] ),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ),
.s_aclk(s_aclk),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
system_auto_cc_0_rd_status_flags_as_61 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out),
.s_aclk(s_aclk));
system_auto_cc_0_rd_bin_cntr_62 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_7
(Q,
E,
\goreg_dm.dout_i_reg[144] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_wvalid,
m_aclk,
out,
m_axi_wready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[144] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_wvalid;
input m_aclk;
input [1:0]out;
input m_axi_wready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[144] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_wready;
wire m_axi_wvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
system_auto_cc_0_rd_fwft_18 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[144] (\goreg_dm.dout_i_reg[144] ),
.m_aclk(m_aclk),
.m_axi_wready(m_axi_wready),
.m_axi_wvalid(m_axi_wvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
system_auto_cc_0_rd_status_flags_as_19 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
system_auto_cc_0_rd_bin_cntr_20 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_logic" *)
module system_auto_cc_0_rd_logic_71
(Q,
E,
\goreg_dm.dout_i_reg[57] ,
D,
\gnxpm_cdc.rd_pntr_gc_reg[3] ,
m_axi_arvalid,
m_aclk,
out,
m_axi_arready,
\gnxpm_cdc.wr_pntr_bin_reg[2] ,
\gnxpm_cdc.wr_pntr_bin_reg[3] );
output [2:0]Q;
output [0:0]E;
output [0:0]\goreg_dm.dout_i_reg[57] ;
output [2:0]D;
output [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
output m_axi_arvalid;
input m_aclk;
input [1:0]out;
input m_axi_arready;
input \gnxpm_cdc.wr_pntr_bin_reg[2] ;
input [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [2:0]D;
wire [0:0]E;
wire [2:0]Q;
wire [3:0]\gnxpm_cdc.rd_pntr_gc_reg[3] ;
wire \gnxpm_cdc.wr_pntr_bin_reg[2] ;
wire [3:0]\gnxpm_cdc.wr_pntr_bin_reg[3] ;
wire [0:0]\goreg_dm.dout_i_reg[57] ;
wire \gr1.gr1_int.rfwft_n_0 ;
wire m_aclk;
wire m_axi_arready;
wire m_axi_arvalid;
wire [1:0]out;
wire p_2_out;
wire [3:3]rd_pntr_plus1;
wire rpntr_n_4;
system_auto_cc_0_rd_fwft_84 \gr1.gr1_int.rfwft
(.E(E),
.Q(rd_pntr_plus1),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] [3]),
.\goreg_dm.dout_i_reg[57] (\goreg_dm.dout_i_reg[57] ),
.m_aclk(m_aclk),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.out(out),
.ram_empty_fb_i_reg(p_2_out),
.ram_empty_i_reg(\gr1.gr1_int.rfwft_n_0 ));
system_auto_cc_0_rd_status_flags_as_85 \gras.rsts
(.\gc0.count_d1_reg[2] (rpntr_n_4),
.m_aclk(m_aclk),
.\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] (out[1]),
.out(p_2_out));
system_auto_cc_0_rd_bin_cntr_86 rpntr
(.D(D),
.E(E),
.Q({rd_pntr_plus1,Q}),
.\gnxpm_cdc.rd_pntr_gc_reg[3] (\gnxpm_cdc.rd_pntr_gc_reg[3] ),
.\gnxpm_cdc.wr_pntr_bin_reg[2] (\gnxpm_cdc.wr_pntr_bin_reg[2] ),
.\gnxpm_cdc.wr_pntr_bin_reg[3] (\gnxpm_cdc.wr_pntr_bin_reg[3] ),
.\gpregsm1.curr_fwft_state_reg[1] (\gr1.gr1_int.rfwft_n_0 ),
.m_aclk(m_aclk),
.out(out[1]),
.ram_empty_i_reg(rpntr_n_4));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as
(out,
\gc0.count_d1_reg[2] ,
s_aclk,
AR);
output out;
input \gc0.count_d1_reg[2] ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire \gc0.count_d1_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire s_aclk;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(AR),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(AR),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_19
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_40
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_61
(out,
\gc0.count_d1_reg[2] ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
wire s_aclk;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "rd_status_flags_as" *)
module system_auto_cc_0_rd_status_flags_as_85
(out,
\gc0.count_d1_reg[2] ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] );
output out;
input \gc0.count_d1_reg[2] ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
wire \gc0.count_d1_reg[2] ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ;
(* DONT_TOUCH *) wire ram_empty_fb_i;
(* DONT_TOUCH *) wire ram_empty_i;
assign out = ram_empty_fb_i;
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_fb_i));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_empty_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gc0.count_d1_reg[2] ),
.PRE(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2] ),
.Q(ram_empty_i));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
s_aclk,
m_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input s_aclk;
input m_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_1 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_2 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_3 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_4 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_5 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.m_aclk(m_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_30
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_31 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_32 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_33 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_34 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_35 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff_36 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_51
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ,
s_aclk,
m_aclk,
s_aresetn);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
output \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ;
input s_aclk;
input m_aclk;
input s_aresetn;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire s_aresetn;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_52 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_53 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_54 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.out(p_5_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_55 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.m_aclk(m_aclk),
.out(p_6_out));
system_auto_cc_0_synchronizer_ff_56 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_57 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.m_aclk(m_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_rd_reg2));
LUT1 #(
.INIT(2'h1))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1
(.I0(s_aresetn),
.O(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0 ),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_74
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_75 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_76 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_77 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_78 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_79 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff_80 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "reset_blk_ramfifo" *)
module system_auto_cc_0_reset_blk_ramfifo_9
(out,
\gc0.count_reg[1] ,
\grstd1.grst_full.grst_f.rst_d3_reg_0 ,
ram_full_fb_i_reg,
m_aclk,
s_aclk,
inverted_reset);
output [1:0]out;
output [2:0]\gc0.count_reg[1] ;
output \grstd1.grst_full.grst_f.rst_d3_reg_0 ;
output ram_full_fb_i_reg;
input m_aclk;
input s_aclk;
input inverted_reset;
wire inverted_reset;
wire m_aclk;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ;
wire \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ;
wire p_5_out;
wire p_6_out;
wire p_7_out;
wire p_8_out;
wire rd_rst_asreg;
(* DONT_TOUCH *) wire [2:0]rd_rst_reg;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_d3;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_rd_reg2;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg1;
(* async_reg = "true" *) (* msgon = "true" *) wire rst_wr_reg2;
wire s_aclk;
wire wr_rst_asreg;
(* DONT_TOUCH *) wire [2:0]wr_rst_reg;
assign \gc0.count_reg[1] [2:0] = rd_rst_reg;
assign \grstd1.grst_full.grst_f.rst_d3_reg_0 = rst_d2;
assign out[1:0] = wr_rst_reg[1:0];
assign ram_full_fb_i_reg = rst_d3;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(rst_wr_reg2),
.Q(rst_d1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d1),
.PRE(rst_wr_reg2),
.Q(rst_d2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b1))
\grstd1.grst_full.grst_f.rst_d3_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_d2),
.PRE(rst_wr_reg2),
.Q(rst_d3));
system_auto_cc_0_synchronizer_ff_10 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst
(.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_11 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst
(.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_12 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_7_out),
.in0(rd_rst_asreg),
.m_aclk(m_aclk),
.out(p_5_out));
system_auto_cc_0_synchronizer_ff_13 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst
(.AS(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.\Q_reg_reg[0]_0 (p_8_out),
.in0(wr_rst_asreg),
.out(p_6_out),
.s_aclk(s_aclk));
system_auto_cc_0_synchronizer_ff_14 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst
(.\Q_reg_reg[0]_0 (p_7_out),
.m_aclk(m_aclk));
system_auto_cc_0_synchronizer_ff_15 \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst
(.\Q_reg_reg[0]_0 (p_8_out),
.s_aclk(s_aclk));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg
(.C(m_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.PRE(rst_rd_reg2),
.Q(rd_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1 ),
.Q(rd_rst_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg
(.C(m_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_rd_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg
(.C(m_aclk),
.CE(1'b1),
.D(rst_rd_reg1),
.PRE(inverted_reset),
.Q(rst_rd_reg2));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(inverted_reset),
.Q(rst_wr_reg1));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDPE #(
.INIT(1'b0))
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg
(.C(s_aclk),
.CE(1'b1),
.D(rst_wr_reg1),
.PRE(inverted_reset),
.Q(rst_wr_reg2));
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg
(.C(s_aclk),
.CE(1'b1),
.D(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.PRE(rst_wr_reg2),
.Q(wr_rst_asreg));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[0]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[1]));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.D(1'b0),
.PRE(\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1 ),
.Q(wr_rst_reg[2]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_1
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_10
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_11
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_12
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_13
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_14
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_15
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_2
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_3
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_31
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_32
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_33
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_34
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_35
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_36
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_4
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_5
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_52
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_53
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_54
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_55
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_56
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_57
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_75
(out,
in0,
m_aclk);
output out;
input [0:0]in0;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_76
(out,
in0,
s_aclk);
output out;
input [0:0]in0;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire s_aclk;
assign out = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(in0),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_77
(\Q_reg_reg[0]_0 ,
AS,
out,
m_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input m_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire m_aclk;
wire out;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_78
(\Q_reg_reg[0]_0 ,
AS,
out,
s_aclk,
in0);
output \Q_reg_reg[0]_0 ;
output [0:0]AS;
input out;
input s_aclk;
input [0:0]in0;
wire [0:0]AS;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire [0:0]in0;
wire out;
wire s_aclk;
assign \Q_reg_reg[0]_0 = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(out),
.Q(Q_reg),
.R(1'b0));
LUT2 #(
.INIT(4'h2))
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2
(.I0(in0),
.I1(Q_reg),
.O(AS));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_79
(\Q_reg_reg[0]_0 ,
m_aclk);
input \Q_reg_reg[0]_0 ;
input m_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire m_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff_80
(\Q_reg_reg[0]_0 ,
s_aclk);
input \Q_reg_reg[0]_0 ;
input s_aclk;
(* async_reg = "true" *) (* msgon = "true" *) wire Q_reg;
wire \Q_reg_reg[0]_0 ;
wire s_aclk;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDRE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.D(\Q_reg_reg[0]_0 ),
.Q(Q_reg),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0
(D,
Q,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_21
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_42
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_63
(D,
Q,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized0_87
(D,
Q,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1
(D,
Q,
m_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_22
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_43
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_64
(D,
Q,
m_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized1_88
(D,
Q,
s_aclk,
AR);
output [3:0]D;
input [3:0]Q;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [3:0]Q;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(Q[3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_23
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_44
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_65
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized2_89
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_24
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_45
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_66
(D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized3_90
(D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign D[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_25
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_46
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_67
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized4_91
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] );
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
wire [0:0]\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1] ),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_26
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_47
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_68
(out,
D,
\Q_reg_reg[3]_0 ,
m_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire m_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(m_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "synchronizer_ff" *)
module system_auto_cc_0_synchronizer_ff__parameterized5_92
(out,
D,
\Q_reg_reg[3]_0 ,
s_aclk,
AR);
output [3:0]out;
output [0:0]D;
input [3:0]\Q_reg_reg[3]_0 ;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]D;
(* async_reg = "true" *) (* msgon = "true" *) wire [3:0]Q_reg;
wire [3:0]\Q_reg_reg[3]_0 ;
wire s_aclk;
assign out[3:0] = Q_reg;
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[0]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [0]),
.Q(Q_reg[0]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[1]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [1]),
.Q(Q_reg[1]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[2]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [2]),
.Q(Q_reg[2]));
(* ASYNC_REG *)
(* KEEP = "yes" *)
(* msgon = "true" *)
FDCE #(
.INIT(1'b0))
\Q_reg_reg[3]
(.C(s_aclk),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg_reg[3]_0 [3]),
.Q(Q_reg[3]));
LUT2 #(
.INIT(4'h6))
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2
(.I0(Q_reg[2]),
.I1(Q_reg[3]),
.O(D));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
m_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire [3:0]plusOp__1;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1
(.I0(Q[0]),
.O(plusOp__1[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__1[1]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__1[2]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__1[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.D(plusOp__1[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__1[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_17
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__5;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__2
(.I0(Q[0]),
.O(plusOp__5[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__2
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__5[1]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__2
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__5[2]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__2
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__5[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__5[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__5[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_38
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__4;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__1
(.I0(Q[0]),
.O(plusOp__4[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__1
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__4[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__4[2]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__4[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__4[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__4[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_59
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
m_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input m_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire [3:0]plusOp__3;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__0
(.I0(Q[0]),
.O(plusOp__3[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__0
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__3[1]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__3[2]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__0
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__3[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(m_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(m_aclk),
.CE(E),
.D(plusOp__3[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(m_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__3[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_bin_cntr" *)
module system_auto_cc_0_wr_bin_cntr_83
(Q,
\gic0.gc0.count_d2_reg[3]_0 ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
E,
s_aclk,
AR);
output [3:0]Q;
output [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input [0:0]E;
input s_aclk;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [3:0]Q;
wire [3:0]\gic0.gc0.count_d2_reg[3]_0 ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire [3:0]plusOp__7;
wire s_aclk;
LUT1 #(
.INIT(2'h1))
\gic0.gc0.count[0]_i_1__3
(.I0(Q[0]),
.O(plusOp__7[0]));
LUT2 #(
.INIT(4'h6))
\gic0.gc0.count[1]_i_1__3
(.I0(Q[0]),
.I1(Q[1]),
.O(plusOp__7[1]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'h78))
\gic0.gc0.count[2]_i_1__3
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.O(plusOp__7[2]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h7F80))
\gic0.gc0.count[3]_i_1__3
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.O(plusOp__7[3]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_d1_reg[0]
(.C(s_aclk),
.CE(E),
.D(Q[0]),
.PRE(AR),
.Q(\gic0.gc0.count_d2_reg[3]_0 [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[1]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[2]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d1_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(Q[3]),
.Q(\gic0.gc0.count_d2_reg[3]_0 [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [0]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [0]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[1]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [1]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [2]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_d2_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(\gic0.gc0.count_d2_reg[3]_0 [3]),
.Q(\gnxpm_cdc.wr_pntr_gc_reg[3] [3]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[0]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[0]),
.Q(Q[0]));
FDPE #(
.INIT(1'b1))
\gic0.gc0.count_reg[1]
(.C(s_aclk),
.CE(E),
.D(plusOp__7[1]),
.PRE(AR),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[2]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\gic0.gc0.count_reg[3]
(.C(s_aclk),
.CE(E),
.CLR(AR),
.D(plusOp__7[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic
(Q,
ram_full_fb_i_reg,
E,
m_axi_bready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_bvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output m_axi_bready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_bvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire m_axi_bready;
wire m_axi_bvalid;
wire out;
wire ram_full_fb_i_reg;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.m_aclk(m_aclk),
.m_axi_bready(m_axi_bready),
.m_axi_bvalid(m_axi_bvalid),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg));
system_auto_cc_0_wr_bin_cntr wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.m_aclk(m_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_29
(Q,
ram_full_fb_i_reg,
E,
s_axi_awready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_awvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_awready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_awvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_37 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid));
system_auto_cc_0_wr_bin_cntr_38 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_50
(Q,
ram_full_fb_i_reg,
E,
m_axi_rready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_rvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output m_axi_rready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_rvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire out;
wire ram_full_fb_i_reg;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_58 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.m_aclk(m_aclk),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg));
system_auto_cc_0_wr_bin_cntr_59 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.m_aclk(m_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_72
(Q,
ram_full_fb_i_reg,
E,
s_axi_arready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_arvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_arready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_arvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_82 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid));
system_auto_cc_0_wr_bin_cntr_83 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_logic" *)
module system_auto_cc_0_wr_logic_8
(Q,
ram_full_fb_i_reg,
E,
s_axi_wready,
\gic0.gc0.count_d2_reg[3] ,
\gnxpm_cdc.wr_pntr_gc_reg[3] ,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_wvalid,
\gnxpm_cdc.rd_pntr_bin_reg[3] ,
AR);
output [2:0]Q;
output ram_full_fb_i_reg;
output [0:0]E;
output s_axi_wready;
output [3:0]\gic0.gc0.count_d2_reg[3] ;
output [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_wvalid;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
input [0:0]AR;
wire [0:0]AR;
wire [0:0]E;
wire [2:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [3:0]\gic0.gc0.count_d2_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [3:0]\gnxpm_cdc.wr_pntr_gc_reg[3] ;
wire out;
wire ram_full_fb_i_reg;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
wire [3:3]wr_pntr_plus2;
system_auto_cc_0_wr_status_flags_as_16 \gwas.wsts
(.E(E),
.Q(wr_pntr_plus2),
.\gic0.gc0.count_d1_reg[3] (\gic0.gc0.count_d1_reg[3] ),
.\gnxpm_cdc.rd_pntr_bin_reg[3] (\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.out(out),
.ram_full_fb_i_reg_0(ram_full_fb_i_reg),
.s_aclk(s_aclk),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
system_auto_cc_0_wr_bin_cntr_17 wpntr
(.AR(AR),
.E(E),
.Q({wr_pntr_plus2,Q}),
.\gic0.gc0.count_d2_reg[3]_0 (\gic0.gc0.count_d2_reg[3] ),
.\gnxpm_cdc.wr_pntr_gc_reg[3] (\gnxpm_cdc.wr_pntr_gc_reg[3] ),
.s_aclk(s_aclk));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as
(ram_full_fb_i_reg_0,
E,
m_axi_bready,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_bvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output m_axi_bready;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_bvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire m_aclk;
wire m_axi_bready;
wire m_axi_bvalid;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1
(.I0(m_axi_bvalid),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h1))
m_axi_bready_INST_0
(.I0(ram_full_i),
.O(m_axi_bready));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3
(.I0(ram_full_fb_i),
.I1(m_axi_bvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_16
(ram_full_fb_i_reg_0,
E,
s_axi_wready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_wvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_wready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_wvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_wready;
wire s_axi_wvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__2
(.I0(s_axi_wvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__2
(.I0(ram_full_fb_i),
.I1(s_axi_wvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_wready_INST_0
(.I0(ram_full_i),
.O(s_axi_wready));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_37
(ram_full_fb_i_reg_0,
E,
s_axi_awready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_awvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_awready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_awvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_awready;
wire s_axi_awvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__1
(.I0(s_axi_awvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__1
(.I0(ram_full_fb_i),
.I1(s_axi_awvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_awready_INST_0
(.I0(ram_full_i),
.O(s_axi_awready));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_58
(ram_full_fb_i_reg_0,
E,
m_axi_rready,
\gic0.gc0.count_d1_reg[3] ,
m_aclk,
out,
m_axi_rvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output m_axi_rready;
input \gic0.gc0.count_d1_reg[3] ;
input m_aclk;
input out;
input m_axi_rvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire m_aclk;
wire m_axi_rready;
wire m_axi_rvalid;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__0
(.I0(m_axi_rvalid),
.I1(ram_full_fb_i),
.O(E));
LUT1 #(
.INIT(2'h1))
m_axi_rready_INST_0
(.I0(ram_full_i),
.O(m_axi_rready));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__0
(.I0(ram_full_fb_i),
.I1(m_axi_rvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(m_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
endmodule
(* ORIG_REF_NAME = "wr_status_flags_as" *)
module system_auto_cc_0_wr_status_flags_as_82
(ram_full_fb_i_reg_0,
E,
s_axi_arready,
\gic0.gc0.count_d1_reg[3] ,
s_aclk,
out,
s_axi_arvalid,
Q,
\gnxpm_cdc.rd_pntr_bin_reg[3] );
output ram_full_fb_i_reg_0;
output [0:0]E;
output s_axi_arready;
input \gic0.gc0.count_d1_reg[3] ;
input s_aclk;
input out;
input s_axi_arvalid;
input [0:0]Q;
input [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire [0:0]E;
wire [0:0]Q;
wire \gic0.gc0.count_d1_reg[3] ;
wire [0:0]\gnxpm_cdc.rd_pntr_bin_reg[3] ;
wire out;
(* DONT_TOUCH *) wire ram_full_fb_i;
wire ram_full_fb_i_reg_0;
(* DONT_TOUCH *) wire ram_full_i;
wire s_aclk;
wire s_axi_arready;
wire s_axi_arvalid;
LUT2 #(
.INIT(4'h2))
\gic0.gc0.count_d1[3]_i_1__3
(.I0(s_axi_arvalid),
.I1(ram_full_fb_i),
.O(E));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_fb_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_fb_i));
LUT4 #(
.INIT(16'h4004))
ram_full_i_i_3__3
(.I0(ram_full_fb_i),
.I1(s_axi_arvalid),
.I2(Q),
.I3(\gnxpm_cdc.rd_pntr_bin_reg[3] ),
.O(ram_full_fb_i_reg_0));
(* DONT_TOUCH *)
(* KEEP = "yes" *)
(* equivalent_register_removal = "no" *)
FDPE #(
.INIT(1'b1))
ram_full_i_reg
(.C(s_aclk),
.CE(1'b1),
.D(\gic0.gc0.count_d1_reg[3] ),
.PRE(out),
.Q(ram_full_i));
LUT1 #(
.INIT(2'h1))
s_axi_arready_INST_0
(.I0(ram_full_i),
.O(s_axi_arready));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__O21BA_TB_V
`define SKY130_FD_SC_LS__O21BA_TB_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__o21ba.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg B1_N;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
B1_N = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 B1_N = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A1 = 1'b1;
#180 A2 = 1'b1;
#200 B1_N = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A1 = 1'b0;
#320 A2 = 1'b0;
#340 B1_N = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 B1_N = 1'b1;
#540 A2 = 1'b1;
#560 A1 = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 B1_N = 1'bx;
#680 A2 = 1'bx;
#700 A1 = 1'bx;
end
sky130_fd_sc_ls__o21ba dut (.A1(A1), .A2(A2), .B1_N(B1_N), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__O21BA_TB_V
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__OR2_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__OR2_BEHAVIORAL_PP_V
/**
* or2: 2-input OR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__or2 (
VPWR,
VGND,
X ,
A ,
B
);
// Module ports
input VPWR;
input VGND;
output X ;
input A ;
input B ;
// Local signals
wire or0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
or or0 (or0_out_X , B, A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__OR2_BEHAVIORAL_PP_V |
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:30:33 2016
/////////////////////////////////////////////////////////////
module FSM_Add_Subtract ( clk, rst, rst_FSM, beg_FSM, zero_flag_i,
norm_iteration_i, add_overflow_i, round_i, load_1_o, load_2_o,
load_3_o, load_8_o, A_S_op_o, load_4_o, left_right_o, bit_shift_o,
load_5_o, load_6_o, load_7_o, ctrl_a_o, ctrl_b_o, ctrl_b_load_o,
ctrl_c_o, ctrl_d_o, rst_int, ready );
output [1:0] ctrl_b_o;
input clk, rst, rst_FSM, beg_FSM, zero_flag_i, norm_iteration_i,
add_overflow_i, round_i;
output load_1_o, load_2_o, load_3_o, load_8_o, A_S_op_o, load_4_o,
left_right_o, bit_shift_o, load_5_o, load_6_o, load_7_o, ctrl_a_o,
ctrl_b_load_o, ctrl_c_o, ctrl_d_o, rst_int, ready;
wire n1, n2, n4, ctrl_d_o, n7, n8, n9, n10, n11, n15, n16, n17, n18, n19,
n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33,
n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47,
n48, n49, n50, n51, n52, n53, n54, n55, n56;
wire [3:0] state_reg;
assign ctrl_a_o = ctrl_d_o;
INVX2TS U3 ( .A(rst), .Y(n1) );
DFFRX2TS \state_reg_reg[2] ( .D(n53), .CK(clk), .RN(n1), .Q(state_reg[2]),
.QN(n15) );
DFFRX2TS \state_reg_reg[3] ( .D(n55), .CK(clk), .RN(n1), .Q(state_reg[3]),
.QN(n9) );
DFFRX2TS \state_reg_reg[1] ( .D(n54), .CK(clk), .RN(n1), .Q(state_reg[1]),
.QN(n16) );
DFFRX2TS \state_reg_reg[0] ( .D(n56), .CK(clk), .RN(n1), .Q(state_reg[0]),
.QN(n17) );
NOR3BX1TS U67 ( .AN(n45), .B(n17), .C(state_reg[1]), .Y(n25) );
NOR2X1TS U68 ( .A(n16), .B(state_reg[3]), .Y(n51) );
NAND3X1TS U69 ( .A(n16), .B(n9), .C(n49), .Y(n41) );
NAND3X1TS U70 ( .A(n16), .B(n9), .C(n50), .Y(n32) );
NAND3X1TS U71 ( .A(state_reg[1]), .B(n17), .C(n45), .Y(n29) );
NAND3X1TS U72 ( .A(state_reg[1]), .B(n49), .C(state_reg[3]), .Y(n20) );
NAND2X1TS U73 ( .A(n43), .B(n27), .Y(load_5_o) );
INVX2TS U74 ( .A(n43), .Y(ctrl_c_o) );
OAI21X1TS U75 ( .A0(n32), .A1(n18), .B0(n24), .Y(n36) );
OAI21X1TS U76 ( .A0(n18), .A1(n41), .B0(n33), .Y(load_8_o) );
INVX2TS U77 ( .A(n28), .Y(ctrl_d_o) );
INVX2TS U78 ( .A(n22), .Y(n10) );
NOR3X1TS U79 ( .A(load_2_o), .B(load_1_o), .C(load_7_o), .Y(n31) );
NAND2X1TS U80 ( .A(n51), .B(n49), .Y(n43) );
NAND2X1TS U81 ( .A(n50), .B(n51), .Y(n27) );
NAND2X1TS U82 ( .A(n44), .B(n29), .Y(ctrl_b_load_o) );
NAND2X1TS U83 ( .A(n32), .B(n24), .Y(load_4_o) );
NAND3X1TS U84 ( .A(n41), .B(n42), .C(n33), .Y(load_3_o) );
INVX2TS U85 ( .A(n40), .Y(load_2_o) );
INVX2TS U86 ( .A(n41), .Y(n4) );
INVX2TS U87 ( .A(n39), .Y(rst_int) );
INVX2TS U88 ( .A(n44), .Y(load_6_o) );
INVX2TS U89 ( .A(n20), .Y(ready) );
INVX2TS U90 ( .A(n32), .Y(n8) );
INVX2TS U91 ( .A(n29), .Y(n7) );
NAND2X1TS U92 ( .A(round_i), .B(n25), .Y(n28) );
NAND4X1TS U93 ( .A(add_overflow_i), .B(n31), .C(n46), .D(n47), .Y(A_S_op_o)
);
NOR4XLTS U94 ( .A(n48), .B(ctrl_b_load_o), .C(load_5_o), .D(load_4_o), .Y(
n47) );
AOI211X1TS U95 ( .A0(n4), .A1(n18), .B0(n50), .C0(n25), .Y(n46) );
NAND3X1TS U96 ( .A(n20), .B(n39), .C(n42), .Y(n48) );
INVX2TS U97 ( .A(norm_iteration_i), .Y(n18) );
NOR2BX1TS U98 ( .AN(ctrl_b_load_o), .B(add_overflow_i), .Y(ctrl_b_o[0]) );
OA21XLTS U99 ( .A0(n36), .A1(load_8_o), .B0(add_overflow_i), .Y(bit_shift_o)
);
OAI2BB1X1TS U100 ( .A0N(load_6_o), .A1N(add_overflow_i), .B0(n29), .Y(
ctrl_b_o[1]) );
AOI211X1TS U101 ( .A0(n41), .A1(n32), .B0(n18), .C0(add_overflow_i), .Y(
left_right_o) );
AOI21X1TS U102 ( .A0(load_2_o), .A1(zero_flag_i), .B0(load_7_o), .Y(n22) );
OAI22X1TS U103 ( .A0(beg_FSM), .A1(n39), .B0(rst_FSM), .B1(n20), .Y(n26) );
NAND4BX1TS U104 ( .AN(load_5_o), .B(n33), .C(n34), .D(n35), .Y(n55) );
AOI21X1TS U105 ( .A0(n25), .A1(n19), .B0(n7), .Y(n34) );
AOI211X1TS U106 ( .A0(state_reg[3]), .A1(n26), .B0(n36), .C0(n10), .Y(n35)
);
INVX2TS U107 ( .A(round_i), .Y(n19) );
NAND4X1TS U108 ( .A(n27), .B(n28), .C(n29), .D(n30), .Y(n54) );
AOI221X1TS U109 ( .A0(n8), .A1(n18), .B0(state_reg[1]), .B1(n26), .C0(n11),
.Y(n30) );
INVX2TS U110 ( .A(n31), .Y(n11) );
AOI31X1TS U111 ( .A0(n37), .A1(n2), .A2(n38), .B0(n26), .Y(n56) );
NOR3X1TS U112 ( .A(n25), .B(rst_int), .C(n4), .Y(n38) );
AOI2BB1X1TS U113 ( .A0N(n40), .A1N(zero_flag_i), .B0(n7), .Y(n37) );
INVX2TS U114 ( .A(n36), .Y(n2) );
NOR2X1TS U115 ( .A(n15), .B(state_reg[0]), .Y(n49) );
NOR2X1TS U116 ( .A(n9), .B(state_reg[2]), .Y(n45) );
NOR2X1TS U117 ( .A(n17), .B(n15), .Y(n50) );
NOR3X1TS U118 ( .A(state_reg[2]), .B(state_reg[3]), .C(state_reg[1]), .Y(n52) );
NAND3X1TS U119 ( .A(n17), .B(n16), .C(n45), .Y(n44) );
NAND3X1TS U120 ( .A(state_reg[0]), .B(state_reg[1]), .C(n45), .Y(n33) );
NAND3X1TS U121 ( .A(n51), .B(n15), .C(state_reg[0]), .Y(n42) );
NAND2X1TS U122 ( .A(n52), .B(n17), .Y(n39) );
NAND3X1TS U123 ( .A(n17), .B(n15), .C(n51), .Y(n40) );
NAND3X1TS U124 ( .A(n49), .B(n16), .C(state_reg[3]), .Y(n24) );
AND3X2TS U125 ( .A(n50), .B(state_reg[3]), .C(n16), .Y(load_7_o) );
NAND3X1TS U126 ( .A(n21), .B(n22), .C(n23), .Y(n53) );
NOR4BX1TS U127 ( .AN(n24), .B(load_3_o), .C(load_6_o), .D(n25), .Y(n23) );
AOI22X1TS U128 ( .A0(n8), .A1(n18), .B0(state_reg[2]), .B1(n26), .Y(n21) );
AND2X2TS U129 ( .A(n52), .B(state_reg[0]), .Y(load_1_o) );
endmodule
|
module top
(
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
parameter PRESCALER = 4; //100000;
// UART loopback + switches to avoid unused inputs
assign tx = rx || (|sw);
// ============================================================================
// Reset
reg [3:0] rst_sr;
wire rst;
initial rst_sr <= 4'hF;
always @(posedge clk)
if (sw[0]) rst_sr <= 4'hF;
else rst_sr <= rst_sr >> 1;
assign rst = rst_sr[0];
// ============================================================================
// Clock prescaler
reg [32:0] ps_cnt = 0;
wire ps_tick = ps_cnt[32];
always @(posedge clk)
if (rst || ps_tick)
ps_cnt <= PRESCALER - 2;
else
ps_cnt <= ps_cnt - 1;
// ============================================================================
// SRL chain testers
wire sim_error = sw[2];
wire [7:0] srl_q;
wire [7:0] error;
genvar i;
generate for(i=0; i<8; i=i+1) begin
localparam j = (i % 4);
wire srl_d;
wire srl_sh;
localparam SITE = (i==0) ? "SLICE_X2Y100" :
(i==1) ? "SLICE_X2Y101" :
(i==2) ? "SLICE_X2Y102" :
(i==3) ? "SLICE_X2Y103" :
(i==4) ? "SLICE_X2Y104" :
(i==5) ? "SLICE_X2Y105" :
(i==6) ? "SLICE_X2Y106" :
/*(i==7) ?*/ "SLICE_X2Y107";
srl_shift_tester #
(
.SRL_LENGTH ((j==0) ? 32 : (16 + j*32)),
.FIXED_DELAY ((j==0) ? 32 : (16 + j*32))
)
tester
(
.clk (clk),
.rst (rst),
.ce (ps_tick),
.srl_sh (srl_sh),
.srl_d (srl_d),
.srl_q (srl_q[i] ^ sim_error),
.error (error[i])
);
srl_chain_mixed #
(
.BEGIN_WITH_SRL16 ((j==0) || (i>=8)),
.END_WITH_SRL16 ((j==0) || (i< 8)),
.NUM_SRL32 (j),
.SITE (SITE)
)
chain_seg
(
.CLK (clk),
.CE (srl_sh),
.D (srl_d),
.Q (srl_q[i])
);
end endgenerate
// ============================================================================
// Error latch
reg [7:0] error_lat = 0;
always @(posedge clk)
if (rst)
error_lat <= 0;
else
error_lat <= error_lat | error;
// ============================================================================
// LEDs
genvar j;
generate for(j=0; j<8; j=j+1) begin
assign led[j ] = (sw[1]) ? error_lat[j] : error[j];
assign led[j+8] = srl_q[j];
end endgenerate
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: Adam LLC
// Engineer: Adam Michael
//
// Create Date: 11:50:15 09/27/2015
// Design Name: Lab2Part2AJM
// Module Name: C:/Users/adam/Documents/GitHub/Digital Systems/Lab2-Part2-Controller7SegmentDisplayKeypadScanner/Lab2Part2AJMTest.v
// Project Name: Lab2-Part2-Controller7SegmentDisplayKeypadScanner
////////////////////////////////////////////////////////////////////////////////
module Lab2Part2AJMTest;
reg [3:0] Rows;
reg ClockIn, Start, Reset;
wire [3:0] Columns;
wire Locked, Found;
wire [7:0] Display;
wire [3:0] Transistors;
defparam uut.StartSwitch.Timer.Divider = 3;
defparam uut.ControlUnit.Timer.Divider = 3;
Lab2Part2AJM uut(Rows, ClockIn, Start, Reset, Columns, Locked, Found, Display, Transistors);
defparam uut.ControlUnit.Timer.Divider = 3;
wire [7:0] Segment0 = uut.Segment0;
wire [7:0] Segment1 = uut.Segment1;
wire [7:0] Segment2 = uut.Segment2;
wire [7:0] Segment3 = uut.Segment3;
wire [3:0] OnesDigit = uut.OnesDigit;
wire [3:0] TensDigit = uut.TensDigit;
wire [2:0] ControllerCurrentState = uut.ControlUnit.CurrentState;
wire [2:0] ControllerNextState = uut.ControlUnit.NextState;
wire ControllerStart = uut.ControlUnit.Start;
wire DebouncedStart = uut.DebouncedStart;
wire NormalStart = uut.Start;
wire [1:0] DebouncerState = uut.StartSwitch.State;
wire [1:0] DebouncerNextState = uut.StartSwitch.NextState;
always #5 ClockIn = ~ClockIn;
initial begin
Rows = 4'b0000; ClockIn = 0; Start = 0; Reset = 1; #100;
Reset = 0; #100;
Rows = 4'b1111; #100;
Start = 1; #500;
Rows = 4'b1111; #100;
Rows = 4'b1011; #100;
Rows = 4'b0111; #200;
$stop;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR2B_PP_BLACKBOX_V
`define SKY130_FD_SC_LP__OR2B_PP_BLACKBOX_V
/**
* or2b: 2-input OR, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__or2b (
X ,
A ,
B_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR2B_PP_BLACKBOX_V
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:39:57 03/02/2016
// Design Name: Ctr
// Module Name: G:/ceshi/lab3c/test_for_Ctr.v
// Project Name: lab3c
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Ctr
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test_for_Ctr;
// Inputs
reg [5:0] opCode;
// Outputs
wire regDst;
wire aluSrc;
wire memToReg;
wire regWrite;
wire memRead;
wire memWrite;
wire branch;
wire [1:0] aluOp;
wire jump;
// Instantiate the Unit Under Test (UUT)
Ctr uut (
.opCode(opCode),
.regDst(regDst),
.aluSrc(aluSrc),
.memToReg(memToReg),
.regWrite(regWrite),
.memRead(memRead),
.memWrite(memWrite),
.branch(branch),
.aluOp(aluOp),
.jump(jump)
);
initial begin
// Initialize Inputs
opCode = 0;
// Wait 100 ns for global reset to finish
#100;
#100 opCode = 6'b000010;
#100 opCode=6'b000000;
#100 opCode=6'b100011;
#100 opCode=6'b101011;
#100 opCode=6'b000100;
// Add stimulus here
end
endmodule
|
//-----------------------------------------------------------------------------
// The way that we connect things in low-frequency simulation mode. In this
// case just pass everything through to the ARM, which can bit-bang this
// (because it is so slow).
//
// Jonathan Westhues, April 2006
//-----------------------------------------------------------------------------
module lo_simulate(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
divisor
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [7:0] divisor;
// No logic, straight through.
assign pwr_oe3 = 1'b0;
assign pwr_oe1 = ssp_dout;
assign pwr_oe2 = ssp_dout;
assign pwr_oe4 = ssp_dout;
assign ssp_clk = cross_lo;
assign pwr_lo = 1'b0;
assign pwr_hi = 1'b0;
assign dbg = ssp_frame;
// Divide the clock to be used for the ADC
reg [7:0] pck_divider;
reg clk_state;
always @(posedge pck0)
begin
if(pck_divider == divisor[7:0])
begin
pck_divider <= 8'd0;
clk_state = !clk_state;
end
else
begin
pck_divider <= pck_divider + 1;
end
end
assign adc_clk = ~clk_state;
// Toggle the output with hysteresis
// Set to high if the ADC value is above 200
// Set to low if the ADC value is below 64
reg is_high;
reg is_low;
reg output_state;
always @(posedge pck0)
begin
if((pck_divider == 8'd7) && !clk_state) begin
is_high = (adc_d >= 8'd191);
is_low = (adc_d <= 8'd64);
end
end
always @(posedge is_high or posedge is_low)
begin
if(is_high)
output_state <= 1'd1;
else if(is_low)
output_state <= 1'd0;
end
assign ssp_frame = output_state;
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 13:09:11 03/06/2017
// Design Name: Dlatch_NAND
// Module Name: D:/Projects/XilinxISE/HW1/Homework1/testDlatch_NAND.v
// Project Name: Homework1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: Dlatch_NAND
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module testDlatch_NAND;
// Inputs
reg En;
reg D;
// Outputs
wire Q;
wire not_Q;
// Instantiate the DESIGN Under Test (DUT)
Dlatch_NAND dut (
.En(En),
.D(D),
.Q(Q),
.not_Q(not_Q)
);
initial begin
// Initialize Inputs
En = 0;
D = 0;
// Wait 100 ns for global reset to finish
#50;
En = 1;
D = 0;
#50;
En = 1;
D = 1;
#50;
En = 1;
D = 0;
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
#50;
En = 1;
D = 1;
#50;
En = 0;
D = 0;
#50;
En = 0;
D = 1;
// Add stimulus here
end
endmodule
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
module hi_iso14443a(
ck_1356meg,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
dbg,
mod_type
);
input ck_1356meg;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
output dbg;
input [3:0] mod_type;
wire adc_clk = ck_1356meg;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3:
// detecting and shaping the reader's signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a
// hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
reg after_hysteresis;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(adc_d >= 16) after_hysteresis <= 1'b1; // U >= 1,14V -> after_hysteresis = 1
else if(adc_d < 8) after_hysteresis <= 1'b0; // U < 1,04V -> after_hysteresis = 0
// Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit
// (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
// In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the ”End of Pause” after the field exceeds
// 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
// detecting a loss of reader's field (adc_d < 192 for 4096 clock cycles). If this is the case,
// set the detected reader signal (after_hysteresis) to '1' (unmodulated)
if(adc_d >= 192)
begin
has_been_low_for <= 12'd0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
begin
has_been_low_for <= has_been_low_for + 1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3
// detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8
// carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles.
reg deep_modulation;
reg [2:0] deep_counter;
reg [8:0] saw_deep_modulation;
always @(negedge adc_clk)
begin
if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
begin
if(deep_counter == 3'd7) // adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
begin
deep_modulation <= 1'b1;
saw_deep_modulation <= 8'd0;
end
else
deep_counter <= deep_counter + 1;
end
else
begin
deep_counter <= 3'd0;
if(saw_deep_modulation == 8'd255) // adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag's response
deep_modulation <= 1'b0;
else
saw_deep_modulation <= saw_deep_modulation + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3
// filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
// for noise reduction and edge detection.
// store 4 previous samples:
reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
always @(negedge adc_clk)
begin
input_prev_4 <= input_prev_3;
input_prev_3 <= input_prev_2;
input_prev_2 <= input_prev_1;
input_prev_1 <= adc_d;
end
// adc_d_filtered = 2*input_prev4 + 1*input_prev3 + 0*input_prev2 - 1*input_prev1 - 2*input
// = (2*input_prev4 + input_prev3) - (2*input + input_prev1)
wire [8:0] input_prev_4_times_2 = input_prev_4 << 1;
wire [8:0] adc_d_times_2 = adc_d << 1;
wire [9:0] tmp1 = input_prev_4_times_2 + input_prev_3;
wire [9:0] tmp2 = adc_d_times_2 + input_prev_1;
// convert intermediate signals to signed and calculate the filter output
wire signed [10:0] adc_d_filtered = {1'b0, tmp1} - {1'b0, tmp2};
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
// 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
reg pre_after_hysteresis;
reg [3:0] reader_falling_edge_time;
reg [6:0] negedge_cnt;
always @(negedge adc_clk)
begin
// detect a reader signal's falling edge and remember its timing:
pre_after_hysteresis <= after_hysteresis;
if (pre_after_hysteresis && ~after_hysteresis)
begin
reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
end
// adjust internal timer counter if necessary:
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `FPGA_HF_ISO14443A_SNIFFER || mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) && deep_modulation)
begin
if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
begin
negedge_cnt <= negedge_cnt + 2; // time warp
end
else if (reader_falling_edge_time == 4'd0) // reader signal changes right before sampling. Better sample later next time.
begin
negedge_cnt <= negedge_cnt; // freeze time
end
else
begin
negedge_cnt <= negedge_cnt + 1; // Continue as usual
end
reader_falling_edge_time[3:0] <= 4'd8; // adjust only once per detected edge
end
else if (negedge_cnt == 7'd127) // normal operation: count from 0 to 127
begin
negedge_cnt <= 0;
end
else
begin
negedge_cnt <= negedge_cnt + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// determine best possible time for starting/resetting the modulation detector.
reg [3:0] mod_detect_reset_time;
always @(negedge adc_clk)
begin
if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
// (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
// 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
// To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
// at mod_detect_reset_time+4 and mod_detect_reset_time+12 (-4 ticks).
// 9 + 4 + 3 + 7 - 4 = 19. 19 mod 16 = 3
begin
mod_detect_reset_time <= 4'd4;
end
else
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
begin
// detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
// reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed
// 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
// Then the same as above.
// - 9 - 3 - 1 + 4 + 3 + 7 - 4 = -3
begin
mod_detect_reset_time <= negedge_cnt[3:0] - 4'd3;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
// falling and rising edge (in any order), a modulation is detected.
reg signed [10:0] rx_mod_falling_edge_max;
reg signed [10:0] rx_mod_rising_edge_max;
reg curbit;
`define EDGE_DETECT_THRESHOLD 5
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == mod_detect_reset_time)
begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge
if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD))
curbit <= 1'b1; // modulation
else
curbit <= 1'b0; // no modulation
// reset modulation detector
rx_mod_rising_edge_max <= 0;
rx_mod_falling_edge_max <= 0;
end
else // look for steepest edges (slopes)
begin
if (adc_d_filtered > 0)
begin
if (adc_d_filtered > rx_mod_falling_edge_max)
rx_mod_falling_edge_max <= adc_d_filtered;
end
else
begin
if (adc_d_filtered < rx_mod_rising_edge_max)
rx_mod_rising_edge_max <= adc_d_filtered;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag+Reader -> PM3
// sample 4 bits reader data and 4 bits tag data for sniffing
reg [3:0] reader_data;
reg [3:0] tag_data;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0)
begin
reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
tag_data[3:0] <= {tag_data[2:0], curbit};
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader:
// a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
reg [31:0] mod_sig_buf;
reg [4:0] mod_sig_ptr;
reg mod_sig;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0) // sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
begin
mod_sig_buf[31:2] <= mod_sig_buf[30:1]; // shift
if (~ssp_dout && ~mod_sig_buf[1])
mod_sig_buf[1] <= 1'b0; // delete the correction bit (a single 1 preceded and succeeded by 0)
else
mod_sig_buf[1] <= mod_sig_buf[0];
mod_sig_buf[0] <= ssp_dout; // add new data to the delay line
mod_sig = mod_sig_buf[mod_sig_ptr]; // the delayed signal.
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader, internal timing:
// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
// transmission stream, causing the required additional delay.
reg [10:0] fdt_counter;
reg fdt_indicator, fdt_elapsed;
reg [3:0] mod_sig_flip;
reg [3:0] sub_carrier_cnt;
// we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
// count to 1172 - 9 - 3 - 32 = 1128
`define FDT_COUNT 11'd1128
// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
// fdt_indicator is assigned to sendbit after at least 1 tick, the transfer to ARM needs minimum 8 ticks. Response from
// ARM could appear at ssp_dout 8 ticks later.
// 1128 - 464 - 1 - 8 - 8 = 647
`define FDT_INDICATOR_COUNT 11'd647
// Note: worst case, assignment to sendbit takes 15 ticks more, and transfer to ARM needs 7*16 = 112 ticks more.
// When the ARM's response then appears, the fdt_count is already 647 + 15 + 112 = 774, which still allows the ARM a possible
// response window of 1128 - 774 = 354 ticks.
// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
assign fdt_reset = ~after_hysteresis && mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN;
always @(negedge adc_clk)
begin
if (fdt_reset)
begin
fdt_counter <= 11'd0;
fdt_elapsed <= 1'b0;
fdt_indicator <= 1'b0;
end
else
begin
if(fdt_counter == `FDT_COUNT)
begin
if(~fdt_elapsed) // just reached fdt.
begin
mod_sig_flip <= negedge_cnt[3:0]; // start modulation at this time
sub_carrier_cnt <= 4'd0; // subcarrier phase in sync with start of modulation
fdt_elapsed <= 1'b1;
end
else
begin
sub_carrier_cnt <= sub_carrier_cnt + 1;
end
end
else
begin
fdt_counter <= fdt_counter + 1;
end
end
if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader or Tag
// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
// or undelayed when sending to a tag
reg mod_sig_coil;
always @(negedge adc_clk)
begin
if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD) // need to take care of proper fdt timing
begin
if(fdt_counter == `FDT_COUNT)
begin
if(fdt_elapsed)
begin
if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
end
else
begin
mod_sig_coil <= mod_sig; // just reached fdt. Immediately assign signal to coil
end
end
end
else // other modes: don't delay
begin
mod_sig_coil <= ssp_dout;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader
// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
reg temp_buffer_reset;
always @(negedge adc_clk)
begin
if(fdt_reset)
begin
mod_sig_ptr <= 5'd0;
temp_buffer_reset = 1'b0;
end
else
begin
if(fdt_counter == `FDT_COUNT && ~fdt_elapsed) // if we just reached fdt
if(~(| mod_sig_ptr[4:0]))
mod_sig_ptr <= 5'd8; // ... but didn't buffer a 1 yet, delay next 1 by n*128 ticks.
else
temp_buffer_reset = 1'b1; // else no need for further delays.
if(negedge_cnt[3:0] == 4'd0) // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
begin
if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt is reached.
if (mod_sig_ptr == 5'd31)
mod_sig_ptr <= 5'd0; // buffer overflow - data loss.
else
mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
else if(fdt_elapsed && ~temp_buffer_reset)
begin
// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
// at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
if(ssp_dout)
temp_buffer_reset = 1'b1;
if(mod_sig_ptr == 5'd1)
mod_sig_ptr <= 5'd8; // still nothing received, need to go for the next interval
else
mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
end
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
reg [7:0] to_arm;
always @(negedge adc_clk)
begin
if (negedge_cnt[5:0] == 6'd63) // fill the buffer
begin
if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
begin
if(deep_modulation) // a reader is sending (or there's no field at all)
begin
to_arm <= {reader_data[3:0], 4'b0000}; // don't send tag data
end
else
begin
to_arm <= {reader_data[3:0], tag_data[3:0]};
end
end
else
begin
to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
end
end
if(negedge_cnt[2:0] == 3'b000 && mod_type == `FPGA_HF_ISO14443A_SNIFFER) // shift at double speed
begin
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt[5:0] != 6'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `FPGA_HF_ISO14443A_SNIFFER)
begin
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt[6:0] != 7'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA <-> ARM communication:
// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
reg ssp_clk;
reg ssp_frame;
always @(negedge adc_clk)
begin
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
// FPGA_HF_ISO14443A_SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
begin
if(negedge_cnt[2:0] == 3'd0)
ssp_clk <= 1'b1;
if(negedge_cnt[2:0] == 3'd4)
ssp_clk <= 1'b0;
if(negedge_cnt[5:0] == 6'd0) // ssp_frame rising edge indicates start of frame
ssp_frame <= 1'b1;
if(negedge_cnt[5:0] == 6'd8)
ssp_frame <= 1'b0;
end
else
// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
begin
if(negedge_cnt[3:0] == 4'd0)
ssp_clk <= 1'b1;
if(negedge_cnt[3:0] == 4'd8)
ssp_clk <= 1'b0;
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame, sampled on falling edge of ssp_clk
ssp_frame <= 1'b1;
if(negedge_cnt[6:0] == 7'd23)
ssp_frame <= 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// select the data to be sent to ARM
reg bit_to_arm;
reg sendbit;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0)
begin
// What do we communicate to the ARM
if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN)
sendbit = after_hysteresis;
else if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD)
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
else */
sendbit = fdt_indicator;
else if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
sendbit = curbit;
else
sendbit = 1'b0;
end
if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
// send sampled reader and tag data:
bit_to_arm = to_arm[7];
else if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
// send timing information:
bit_to_arm = to_arm[7];
else
// send data or fdt_indicator
bit_to_arm = sendbit;
end
assign ssp_din = bit_to_arm;
// Subcarrier (adc_clk/16, for FPGA_HF_ISO14443A_TAGSIM_MOD only).
wire sub_carrier;
assign sub_carrier = ~sub_carrier_cnt[3];
// in FPGA_HF_ISO14443A_READER_MOD: drop carrier for mod_sig_coil == 1 (pause);
// in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off
assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)));
// Enable HF antenna drivers:
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
// FPGA_HF_ISO14443A_TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD);
// This is all LF, so doesn't matter.
assign pwr_oe2 = 1'b0;
assign pwr_lo = 1'b0;
assign dbg = negedge_cnt[3];
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 17:33:00 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top system_buffer_register_1_0 -prefix
// system_buffer_register_1_0_ system_buffer_register_0_0_sim_netlist.v
// Design : system_buffer_register_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module system_buffer_register_1_0_buffer_register
(val_out,
val_in,
clk);
output [31:0]val_out;
input [31:0]val_in;
input clk;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
FDRE \val_out_reg[0]
(.C(clk),
.CE(1'b1),
.D(val_in[0]),
.Q(val_out[0]),
.R(1'b0));
FDRE \val_out_reg[10]
(.C(clk),
.CE(1'b1),
.D(val_in[10]),
.Q(val_out[10]),
.R(1'b0));
FDRE \val_out_reg[11]
(.C(clk),
.CE(1'b1),
.D(val_in[11]),
.Q(val_out[11]),
.R(1'b0));
FDRE \val_out_reg[12]
(.C(clk),
.CE(1'b1),
.D(val_in[12]),
.Q(val_out[12]),
.R(1'b0));
FDRE \val_out_reg[13]
(.C(clk),
.CE(1'b1),
.D(val_in[13]),
.Q(val_out[13]),
.R(1'b0));
FDRE \val_out_reg[14]
(.C(clk),
.CE(1'b1),
.D(val_in[14]),
.Q(val_out[14]),
.R(1'b0));
FDRE \val_out_reg[15]
(.C(clk),
.CE(1'b1),
.D(val_in[15]),
.Q(val_out[15]),
.R(1'b0));
FDRE \val_out_reg[16]
(.C(clk),
.CE(1'b1),
.D(val_in[16]),
.Q(val_out[16]),
.R(1'b0));
FDRE \val_out_reg[17]
(.C(clk),
.CE(1'b1),
.D(val_in[17]),
.Q(val_out[17]),
.R(1'b0));
FDRE \val_out_reg[18]
(.C(clk),
.CE(1'b1),
.D(val_in[18]),
.Q(val_out[18]),
.R(1'b0));
FDRE \val_out_reg[19]
(.C(clk),
.CE(1'b1),
.D(val_in[19]),
.Q(val_out[19]),
.R(1'b0));
FDRE \val_out_reg[1]
(.C(clk),
.CE(1'b1),
.D(val_in[1]),
.Q(val_out[1]),
.R(1'b0));
FDRE \val_out_reg[20]
(.C(clk),
.CE(1'b1),
.D(val_in[20]),
.Q(val_out[20]),
.R(1'b0));
FDRE \val_out_reg[21]
(.C(clk),
.CE(1'b1),
.D(val_in[21]),
.Q(val_out[21]),
.R(1'b0));
FDRE \val_out_reg[22]
(.C(clk),
.CE(1'b1),
.D(val_in[22]),
.Q(val_out[22]),
.R(1'b0));
FDRE \val_out_reg[23]
(.C(clk),
.CE(1'b1),
.D(val_in[23]),
.Q(val_out[23]),
.R(1'b0));
FDRE \val_out_reg[24]
(.C(clk),
.CE(1'b1),
.D(val_in[24]),
.Q(val_out[24]),
.R(1'b0));
FDRE \val_out_reg[25]
(.C(clk),
.CE(1'b1),
.D(val_in[25]),
.Q(val_out[25]),
.R(1'b0));
FDRE \val_out_reg[26]
(.C(clk),
.CE(1'b1),
.D(val_in[26]),
.Q(val_out[26]),
.R(1'b0));
FDRE \val_out_reg[27]
(.C(clk),
.CE(1'b1),
.D(val_in[27]),
.Q(val_out[27]),
.R(1'b0));
FDRE \val_out_reg[28]
(.C(clk),
.CE(1'b1),
.D(val_in[28]),
.Q(val_out[28]),
.R(1'b0));
FDRE \val_out_reg[29]
(.C(clk),
.CE(1'b1),
.D(val_in[29]),
.Q(val_out[29]),
.R(1'b0));
FDRE \val_out_reg[2]
(.C(clk),
.CE(1'b1),
.D(val_in[2]),
.Q(val_out[2]),
.R(1'b0));
FDRE \val_out_reg[30]
(.C(clk),
.CE(1'b1),
.D(val_in[30]),
.Q(val_out[30]),
.R(1'b0));
FDRE \val_out_reg[31]
(.C(clk),
.CE(1'b1),
.D(val_in[31]),
.Q(val_out[31]),
.R(1'b0));
FDRE \val_out_reg[3]
(.C(clk),
.CE(1'b1),
.D(val_in[3]),
.Q(val_out[3]),
.R(1'b0));
FDRE \val_out_reg[4]
(.C(clk),
.CE(1'b1),
.D(val_in[4]),
.Q(val_out[4]),
.R(1'b0));
FDRE \val_out_reg[5]
(.C(clk),
.CE(1'b1),
.D(val_in[5]),
.Q(val_out[5]),
.R(1'b0));
FDRE \val_out_reg[6]
(.C(clk),
.CE(1'b1),
.D(val_in[6]),
.Q(val_out[6]),
.R(1'b0));
FDRE \val_out_reg[7]
(.C(clk),
.CE(1'b1),
.D(val_in[7]),
.Q(val_out[7]),
.R(1'b0));
FDRE \val_out_reg[8]
(.C(clk),
.CE(1'b1),
.D(val_in[8]),
.Q(val_out[8]),
.R(1'b0));
FDRE \val_out_reg[9]
(.C(clk),
.CE(1'b1),
.D(val_in[9]),
.Q(val_out[9]),
.R(1'b0));
endmodule
(* CHECK_LICENSE_TYPE = "system_buffer_register_0_0,buffer_register,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "buffer_register,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_buffer_register_1_0
(clk,
val_in,
val_out);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clk CLK" *) input clk;
input [31:0]val_in;
output [31:0]val_out;
wire clk;
wire [31:0]val_in;
wire [31:0]val_out;
system_buffer_register_1_0_buffer_register U0
(.clk(clk),
.val_in(val_in),
.val_out(val_out));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1 ns / 1 ps
`include "Video_PR_v1_0_tb_include.vh"
// lite_response Type Defines
`define RESPONSE_OKAY 2'b00
`define RESPONSE_EXOKAY 2'b01
`define RESP_BUS_WIDTH 2
`define BURST_TYPE_INCR 2'b01
`define BURST_TYPE_WRAP 2'b10
// AMBA AXI4 Lite Range Constants
`define S_AXI_MAX_BURST_LENGTH 1
`define S_AXI_DATA_BUS_WIDTH 32
`define S_AXI_ADDRESS_BUS_WIDTH 32
`define S_AXI_MAX_DATA_SIZE (`S_AXI_DATA_BUS_WIDTH*`S_AXI_MAX_BURST_LENGTH)/8
module Video_PR_v1_0_tb;
reg tb_ACLK;
reg tb_ARESETn;
// Create an instance of the example tb
`BD_WRAPPER dut (.ACLK(tb_ACLK),
.ARESETN(tb_ARESETn));
// Local Variables
// AMBA S_AXI AXI4 Lite Local Reg
reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_rd_data_lite;
reg [`S_AXI_DATA_BUS_WIDTH-1:0] S_AXI_test_data_lite [3:0];
reg [`RESP_BUS_WIDTH-1:0] S_AXI_lite_response;
reg [`S_AXI_ADDRESS_BUS_WIDTH-1:0] S_AXI_mtestAddress;
reg [3-1:0] S_AXI_mtestProtection_lite;
integer S_AXI_mtestvectorlite; // Master side testvector
integer S_AXI_mtestdatasizelite;
integer result_slave_lite;
// Simple Reset Generator and test
initial begin
tb_ARESETn = 1'b0;
#500;
// Release the reset on the posedge of the clk.
@(posedge tb_ACLK);
tb_ARESETn = 1'b1;
@(posedge tb_ACLK);
end
// Simple Clock Generator
initial tb_ACLK = 1'b0;
always #10 tb_ACLK = !tb_ACLK;
//------------------------------------------------------------------------
// TEST LEVEL API: CHECK_RESPONSE_OKAY
//------------------------------------------------------------------------
// Description:
// CHECK_RESPONSE_OKAY(lite_response)
// This task checks if the return lite_response is equal to OKAY
//------------------------------------------------------------------------
task automatic CHECK_RESPONSE_OKAY;
input [`RESP_BUS_WIDTH-1:0] response;
begin
if (response !== `RESPONSE_OKAY) begin
$display("TESTBENCH ERROR! lite_response is not OKAY",
"\n expected = 0x%h",`RESPONSE_OKAY,
"\n actual = 0x%h",response);
$stop;
end
end
endtask
//------------------------------------------------------------------------
// TEST LEVEL API: COMPARE_LITE_DATA
//------------------------------------------------------------------------
// Description:
// COMPARE_LITE_DATA(expected,actual)
// This task checks if the actual data is equal to the expected data.
// X is used as don't care but it is not permitted for the full vector
// to be don't care.
//------------------------------------------------------------------------
`define S_AXI_DATA_BUS_WIDTH 32
task automatic COMPARE_LITE_DATA;
input [`S_AXI_DATA_BUS_WIDTH-1:0]expected;
input [`S_AXI_DATA_BUS_WIDTH-1:0]actual;
begin
if (expected === 'hx || actual === 'hx) begin
$display("TESTBENCH ERROR! COMPARE_LITE_DATA cannot be performed with an expected or actual vector that is all 'x'!");
result_slave_lite = 0;
$stop;
end
if (actual != expected) begin
$display("TESTBENCH ERROR! Data expected is not equal to actual.",
"\nexpected = 0x%h",expected,
"\nactual = 0x%h",actual);
result_slave_lite = 0;
$stop;
end
else
begin
$display("TESTBENCH Passed! Data expected is equal to actual.",
"\n expected = 0x%h",expected,
"\n actual = 0x%h",actual);
end
end
endtask
task automatic S_AXI_TEST;
begin
$display("---------------------------------------------------------");
$display("EXAMPLE TEST : S_AXI");
$display("Simple register write and read example");
$display("---------------------------------------------------------");
S_AXI_mtestvectorlite = 0;
S_AXI_mtestAddress = `S_AXI_SLAVE_ADDRESS;
S_AXI_mtestProtection_lite = 0;
S_AXI_mtestdatasizelite = `S_AXI_MAX_DATA_SIZE;
result_slave_lite = 1;
for (S_AXI_mtestvectorlite = 0; S_AXI_mtestvectorlite <= 3; S_AXI_mtestvectorlite = S_AXI_mtestvectorlite + 1)
begin
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.WRITE_BURST_CONCURRENT( S_AXI_mtestAddress,
S_AXI_mtestProtection_lite,
S_AXI_test_data_lite[S_AXI_mtestvectorlite],
S_AXI_mtestdatasizelite,
S_AXI_lite_response);
$display("EXAMPLE TEST %d write : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_lite_response);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.READ_BURST(S_AXI_mtestAddress,
S_AXI_mtestProtection_lite,
S_AXI_rd_data_lite,
S_AXI_lite_response);
$display("EXAMPLE TEST %d read : DATA = 0x%h, lite_response = 0x%h",S_AXI_mtestvectorlite,S_AXI_rd_data_lite,S_AXI_lite_response);
CHECK_RESPONSE_OKAY(S_AXI_lite_response);
COMPARE_LITE_DATA(S_AXI_test_data_lite[S_AXI_mtestvectorlite],S_AXI_rd_data_lite);
$display("EXAMPLE TEST %d : Sequential write and read burst transfers complete from the master side. %d",S_AXI_mtestvectorlite,S_AXI_mtestvectorlite);
S_AXI_mtestAddress = S_AXI_mtestAddress + 32'h00000004;
end
$display("---------------------------------------------------------");
$display("EXAMPLE TEST S_AXI: PTGEN_TEST_FINISHED!");
if ( result_slave_lite ) begin
$display("PTGEN_TEST: PASSED!");
end else begin
$display("PTGEN_TEST: FAILED!");
end
$display("---------------------------------------------------------");
end
endtask
// Create the test vectors
initial begin
// When performing debug enable all levels of INFO messages.
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
dut.`BD_INST_NAME.master_0.cdn_axi4_lite_master_bfm_inst.set_channel_level_info(1);
// Create test data vectors
S_AXI_test_data_lite[0] = 32'h0101FFFF;
S_AXI_test_data_lite[1] = 32'habcd0001;
S_AXI_test_data_lite[2] = 32'hdead0011;
S_AXI_test_data_lite[3] = 32'hbeef0011;
end
// Drive the BFM
initial begin
// Wait for end of reset
wait(tb_ARESETn === 0) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
wait(tb_ARESETn === 1) @(posedge tb_ACLK);
S_AXI_TEST();
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__A211OI_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__A211OI_PP_BLACKBOX_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__a211oi (
Y ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__A211OI_PP_BLACKBOX_V
|
// ======================================================================
// Printf_test.v generated from TopDesign.cysch
// 02/11/2015 at 10:44
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=1600, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=1600, I2cClockFromTerm=false, I2cDataRate=100, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=1, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=true, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=true, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=false, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=false, ScbClkFreqDes=1382.4, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=4, ScbModeHw=2, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=0, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=UART_1, CY_INSTANCE_SHORT_NAME=UART_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=UART_1, )
module SCB_P4_v1_20_0 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("723379629.62963"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_379;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__tx_net;
wire [0:0] tmpFB_0__tx_net;
wire [0:0] tmpIO_0__tx_net;
wire [0:0] tmpINTERRUPT_0__tx_net;
electrical [0:0] tmpSIOVREF__tx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/23b8206d-1c77-4e61-be4a-b4037d5de5fc"),
.drive_mode(3'b110),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b1),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
tx
(.oe(tmpOE__tx_net),
.y({Net_656}),
.fb({tmpFB_0__tx_net[0:0]}),
.io({tmpIO_0__tx_net[0:0]}),
.siovref(tmpSIOVREF__tx_net),
.interrupt({tmpINTERRUPT_0__tx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__tx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
wire [0:0] tmpOE__rx_net;
wire [0:0] tmpIO_0__rx_net;
wire [0:0] tmpINTERRUPT_0__rx_net;
electrical [0:0] tmpSIOVREF__rx_net;
cy_psoc3_pins_v1_10
#(.id("43ec2fa1-bf22-4b71-9477-b6ca7b97f0b0/78e33e5d-45ea-4b75-88d5-73274e8a7ce4"),
.drive_mode(3'b001),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("I"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
rx
(.oe(tmpOE__rx_net),
.y({1'b0}),
.fb({Net_379}),
.io({tmpIO_0__rx_net[0:0]}),
.siovref(tmpSIOVREF__rx_net),
.interrupt({tmpINTERRUPT_0__rx_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__rx_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 2;
endmodule
// Component: cy_analog_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_analog_virtualmux_v1_0\cy_analog_virtualmux_v1_0.v"
`endif
// Component: Bus_Connect_v1_10
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v1_10"
`include "$CYPRESS_DIR\..\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v1_10\Bus_Connect_v1_10.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v1_10"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cycomponentlibrary\CyComponentLibrary.cylib\Bus_Connect_v1_10\Bus_Connect_v1_10.v"
`endif
// ADC_SAR_SEQ_P4_v1_10(AdcAClock=4, AdcAdjust=0, AdcAlternateResolution=0, AdcAvgMode=0, AdcAvgSamplesNum=7, AdcBClock=4, AdcCClock=4, AdcChannelsEnConf=1, AdcChannelsModeConf=0, AdcClock=1, AdcClockFrequency=2999988, AdcCompareMode=0, AdcDataFormatJustification=0, AdcDClock=4, AdcDifferentialResultFormat=0, AdcHighLimit=2047, AdcInjChannelEnabled=false, AdcInputBufGain=0, AdcLowLimit=0, AdcMaxResolution=12, AdcSampleMode=0, AdcSarMuxChannelConfig=0, AdcSequencedChannels=1, AdcSingleEndedNegativeInput=0, AdcSingleResultFormat=1, AdcSymbolHasSingleEndedInputChannel=false, AdcTotalChannels=1, AdcVrefSelect=7, AdcVrefVoltage_mV=3300, rm_int=false, SeqChannelsConfigTable=<?xml version="1.0" encoding="utf-16"?><CyChannelsConfigTable xmlns:Version="1_10"><m_channelsConfigTable><CyChannelsConfigTableRow><m_enabled>false</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Diff</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow><CyChannelsConfigTableRow><m_enabled>true</m_enabled><m_resolution>Twelve</m_resolution><m_mode>Single</m_mode><m_averaged>false</m_averaged><m_acqTime>AClocks</m_acqTime><m_limitsDetectIntrEnabled>false</m_limitsDetectIntrEnabled><m_saturationIntrEnabled>false</m_saturationIntrEnabled></CyChannelsConfigTableRow></m_channelsConfigTable></CyChannelsConfigTable>, CY_COMPONENT_NAME=ADC_SAR_SEQ_P4_v1_10, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=ADC, CY_INSTANCE_SHORT_NAME=ADC, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=10, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=ADC, )
module ADC_SAR_SEQ_P4_v1_10_1 (
soc,
aclk,
Vref,
sdone,
eoc,
vinPlus0);
input soc;
input aclk;
inout Vref;
electrical Vref;
output sdone;
output eoc;
inout vinPlus0;
electrical vinPlus0;
wire Net_3093;
wire Net_3090;
wire Net_2786;
electrical Net_2785;
electrical Net_2784;
electrical Net_2783;
wire Net_2782;
electrical Net_2781;
electrical Net_2780;
electrical Net_2779;
electrical Net_2575;
electrical Net_2574;
electrical Net_2573;
electrical Net_2572;
electrical Net_2571;
electrical Net_2570;
electrical Net_2569;
electrical Net_2568;
electrical Net_2567;
electrical Net_2566;
electrical Net_2565;
electrical Net_2564;
electrical muxout_plus;
electrical Net_2563;
electrical Net_2562;
electrical Net_2561;
electrical Net_2560;
electrical Net_2559;
electrical Net_2557;
electrical Net_2556;
electrical Net_2555;
electrical Net_2554;
electrical muxout_minus;
electrical Net_2553;
electrical Net_2552;
electrical Net_2551;
electrical Net_2550;
electrical Net_2549;
electrical Net_2548;
electrical Net_2547;
electrical [16:0] mux_bus_minus;
electrical [16:0] mux_bus_plus;
electrical Net_2546;
electrical Net_2545;
electrical Net_2544;
electrical Net_2542;
electrical Net_2541;
wire Net_2221;
electrical Net_1849;
electrical Net_1848;
electrical Net_1846;
wire Net_2273;
wire [11:0] Net_2272;
wire Net_2271;
wire [3:0] Net_2270;
wire Net_2269;
wire Net_15;
wire Net_13;
wire Net_14;
wire Net_11;
wire Net_26;
electrical Net_2793;
electrical Net_2794;
wire Net_1845;
electrical [0:0] Net_1450;
electrical [0:0] Net_2375;
electrical Net_1851;
electrical Net_2580;
electrical Net_3046;
electrical Net_3016;
electrical Net_2020;
electrical Net_124;
electrical Net_2102;
electrical Net_2099;
wire [1:0] Net_1963;
wire Net_17;
electrical Net_8;
electrical Net_43;
cy_psoc4_sar_v1_0 cy_psoc4_sar (
.vplus(Net_2020),
.vminus(Net_124),
.vref(Net_8),
.ext_vref(Net_43),
.clock(Net_17),
.sw_negvref(Net_26),
.cfg_st_sel(Net_1963[1:0]),
.cfg_average(Net_11),
.cfg_resolution(Net_14),
.cfg_differential(Net_13),
.trigger(soc),
.data_hilo_sel(Net_15),
.sample_done(sdone),
.chan_id_valid(Net_2269),
.chan_id(Net_2270[3:0]),
.data_valid(Net_2271),
.eos_intr(eoc),
.data(Net_2272[11:0]),
.irq(Net_2273));
// clk_src_sel (cy_virtualmux_v1_0)
assign Net_17 = Net_1845;
// int_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 int_vref_sel_connect(Net_8, Net_1846);
defparam int_vref_sel_connect.sig_width = 1;
// ext_vref_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vref_sel_connect(Net_43, Net_1849);
defparam ext_vref_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_1 (
.noconnect(Net_1846));
ZeroTerminal ZeroTerminal_3 (
.z(Net_14));
ZeroTerminal ZeroTerminal_4 (
.z(Net_13));
ZeroTerminal ZeroTerminal_5 (
.z(Net_15));
ZeroTerminal ZeroTerminal_6 (
.z(Net_1963[0]));
ZeroTerminal ZeroTerminal_7 (
.z(Net_1963[1]));
cy_clock_v1_0
#(.id("b0574397-86aa-4552-91b4-736ae77c7a57/a12a1691-924f-48e5-a017-176d592c3b32"),
.source_clock_id(""),
.divisor(0),
.period("333334666.672"),
.is_direct(0),
.is_digital(0))
intClock
(.clock_out(Net_1845));
ZeroTerminal ZeroTerminal_2 (
.z(Net_11));
ZeroTerminal ZeroTerminal_1 (
.z(Net_26));
wire [0:0] tmpOE__ExtVref_net;
wire [0:0] tmpFB_0__ExtVref_net;
wire [0:0] tmpIO_0__ExtVref_net;
wire [0:0] tmpINTERRUPT_0__ExtVref_net;
electrical [0:0] tmpSIOVREF__ExtVref_net;
cy_psoc3_pins_v1_10
#(.id("b0574397-86aa-4552-91b4-736ae77c7a57/05a9c8de-3ba2-4909-8250-95fdc61c0bf4"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
ExtVref
(.oe(tmpOE__ExtVref_net),
.y({1'b0}),
.fb({tmpFB_0__ExtVref_net[0:0]}),
.analog({Net_1849}),
.io({tmpIO_0__ExtVref_net[0:0]}),
.siovref(tmpSIOVREF__ExtVref_net),
.interrupt({tmpINTERRUPT_0__ExtVref_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__ExtVref_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
// ext_vneg_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 ext_vneg_sel_connect(Net_2580, Net_1851);
defparam ext_vneg_sel_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_3 (
.noconnect(Net_1851));
// cy_analog_virtualmux_vplus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus9_connect(mux_bus_plus[9], Net_2541);
defparam cy_analog_virtualmux_vplus9_connect.sig_width = 1;
// cy_analog_virtualmux_vplus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus8_connect(mux_bus_plus[8], Net_2542);
defparam cy_analog_virtualmux_vplus8_connect.sig_width = 1;
// cy_analog_virtualmux_vplus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus1_connect(mux_bus_plus[1], Net_2544);
defparam cy_analog_virtualmux_vplus1_connect.sig_width = 1;
// cy_analog_virtualmux_vplus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus2_connect(mux_bus_plus[2], Net_2545);
defparam cy_analog_virtualmux_vplus2_connect.sig_width = 1;
// cy_analog_virtualmux_vplus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus3_connect(mux_bus_plus[3], Net_2546);
defparam cy_analog_virtualmux_vplus3_connect.sig_width = 1;
// cy_analog_virtualmux_vplus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus4_connect(mux_bus_plus[4], Net_2547);
defparam cy_analog_virtualmux_vplus4_connect.sig_width = 1;
// cy_analog_virtualmux_vplus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus6_connect(mux_bus_plus[6], Net_2548);
defparam cy_analog_virtualmux_vplus6_connect.sig_width = 1;
// cy_analog_virtualmux_vplus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus7_connect(mux_bus_plus[7], Net_2549);
defparam cy_analog_virtualmux_vplus7_connect.sig_width = 1;
Bus_Connect_v1_10 Connect_1 (
.in_bus(mux_bus_plus[16:0]),
.out_bus(Net_1450[0:0]));
defparam Connect_1.in_width = 17;
defparam Connect_1.out_width = 1;
// cy_analog_virtualmux_vplus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus5_connect(mux_bus_plus[5], Net_2550);
defparam cy_analog_virtualmux_vplus5_connect.sig_width = 1;
// cy_analog_virtualmux_vplus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus10_connect(mux_bus_plus[10], Net_2551);
defparam cy_analog_virtualmux_vplus10_connect.sig_width = 1;
// cy_analog_virtualmux_vplus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus11_connect(mux_bus_plus[11], Net_2552);
defparam cy_analog_virtualmux_vplus11_connect.sig_width = 1;
// cy_analog_virtualmux_vplus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus12_connect(mux_bus_plus[12], Net_2553);
defparam cy_analog_virtualmux_vplus12_connect.sig_width = 1;
// cy_analog_virtualmux_vplus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus13_connect(mux_bus_plus[13], Net_2554);
defparam cy_analog_virtualmux_vplus13_connect.sig_width = 1;
// cy_analog_virtualmux_vplus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus14_connect(mux_bus_plus[14], Net_2555);
defparam cy_analog_virtualmux_vplus14_connect.sig_width = 1;
// cy_analog_virtualmux_vplus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus15_connect(mux_bus_plus[15], Net_2556);
defparam cy_analog_virtualmux_vplus15_connect.sig_width = 1;
// cy_analog_virtualmux_vplus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vplus_inj_connect(Net_3016, Net_2557);
defparam cy_analog_virtualmux_vplus_inj_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_6 (
.noconnect(Net_2544));
cy_analog_noconnect_v1_0 cy_analog_noconnect_7 (
.noconnect(Net_2545));
cy_analog_noconnect_v1_0 cy_analog_noconnect_8 (
.noconnect(Net_2546));
cy_analog_noconnect_v1_0 cy_analog_noconnect_9 (
.noconnect(Net_2547));
cy_analog_noconnect_v1_0 cy_analog_noconnect_10 (
.noconnect(Net_2550));
cy_analog_noconnect_v1_0 cy_analog_noconnect_11 (
.noconnect(Net_2548));
cy_analog_noconnect_v1_0 cy_analog_noconnect_12 (
.noconnect(Net_2549));
cy_analog_noconnect_v1_0 cy_analog_noconnect_13 (
.noconnect(Net_2542));
cy_analog_noconnect_v1_0 cy_analog_noconnect_14 (
.noconnect(Net_2541));
cy_analog_noconnect_v1_0 cy_analog_noconnect_15 (
.noconnect(Net_2551));
cy_analog_noconnect_v1_0 cy_analog_noconnect_16 (
.noconnect(Net_2552));
cy_analog_noconnect_v1_0 cy_analog_noconnect_17 (
.noconnect(Net_2553));
cy_analog_noconnect_v1_0 cy_analog_noconnect_18 (
.noconnect(Net_2554));
cy_analog_noconnect_v1_0 cy_analog_noconnect_19 (
.noconnect(Net_2555));
cy_analog_noconnect_v1_0 cy_analog_noconnect_20 (
.noconnect(Net_2556));
cy_analog_noconnect_v1_0 cy_analog_noconnect_21 (
.noconnect(Net_2557));
// cy_analog_virtualmux_37 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_37_connect(Net_3016, mux_bus_plus[1]);
defparam cy_analog_virtualmux_37_connect.sig_width = 1;
// cy_analog_virtualmux_vminus0 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus0_connect(mux_bus_minus[0], Net_2559);
defparam cy_analog_virtualmux_vminus0_connect.sig_width = 1;
// cy_analog_virtualmux_vminus1 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus1_connect(mux_bus_minus[1], Net_2560);
defparam cy_analog_virtualmux_vminus1_connect.sig_width = 1;
// cy_analog_virtualmux_vminus2 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus2_connect(mux_bus_minus[2], Net_2561);
defparam cy_analog_virtualmux_vminus2_connect.sig_width = 1;
// cy_analog_virtualmux_vminus3 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus3_connect(mux_bus_minus[3], Net_2562);
defparam cy_analog_virtualmux_vminus3_connect.sig_width = 1;
// cy_analog_virtualmux_vminus4 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus4_connect(mux_bus_minus[4], Net_2563);
defparam cy_analog_virtualmux_vminus4_connect.sig_width = 1;
// cy_analog_virtualmux_vminus5 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus5_connect(mux_bus_minus[5], Net_2564);
defparam cy_analog_virtualmux_vminus5_connect.sig_width = 1;
// cy_analog_virtualmux_vminus6 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus6_connect(mux_bus_minus[6], Net_2565);
defparam cy_analog_virtualmux_vminus6_connect.sig_width = 1;
// cy_analog_virtualmux_vminus7 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus7_connect(mux_bus_minus[7], Net_2566);
defparam cy_analog_virtualmux_vminus7_connect.sig_width = 1;
// cy_analog_virtualmux_vminus8 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus8_connect(mux_bus_minus[8], Net_2567);
defparam cy_analog_virtualmux_vminus8_connect.sig_width = 1;
// cy_analog_virtualmux_vminus9 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus9_connect(mux_bus_minus[9], Net_2568);
defparam cy_analog_virtualmux_vminus9_connect.sig_width = 1;
// cy_analog_virtualmux_vminus10 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus10_connect(mux_bus_minus[10], Net_2569);
defparam cy_analog_virtualmux_vminus10_connect.sig_width = 1;
// cy_analog_virtualmux_vminus11 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus11_connect(mux_bus_minus[11], Net_2570);
defparam cy_analog_virtualmux_vminus11_connect.sig_width = 1;
// cy_analog_virtualmux_vminus12 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus12_connect(mux_bus_minus[12], Net_2571);
defparam cy_analog_virtualmux_vminus12_connect.sig_width = 1;
// cy_analog_virtualmux_vminus13 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus13_connect(mux_bus_minus[13], Net_2572);
defparam cy_analog_virtualmux_vminus13_connect.sig_width = 1;
// cy_analog_virtualmux_vminus14 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus14_connect(mux_bus_minus[14], Net_2573);
defparam cy_analog_virtualmux_vminus14_connect.sig_width = 1;
// cy_analog_virtualmux_vminus15 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus15_connect(mux_bus_minus[15], Net_2574);
defparam cy_analog_virtualmux_vminus15_connect.sig_width = 1;
// cy_analog_virtualmux_vminus_inj (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_vminus_inj_connect(Net_3046, Net_2575);
defparam cy_analog_virtualmux_vminus_inj_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_37 (
.noconnect(Net_2575));
// cy_analog_virtualmux_36 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_36_connect(Net_3046, mux_bus_minus[1]);
defparam cy_analog_virtualmux_36_connect.sig_width = 1;
// cy_analog_virtualmux_42 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_42_connect(Net_2020, muxout_plus);
defparam cy_analog_virtualmux_42_connect.sig_width = 1;
// cy_analog_virtualmux_43 (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 cy_analog_virtualmux_43_connect(Net_124, muxout_minus);
defparam cy_analog_virtualmux_43_connect.sig_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_39 (
.noconnect(Net_2779));
cy_analog_noconnect_v1_0 cy_analog_noconnect_40 (
.noconnect(Net_2783));
cy_analog_noconnect_v1_0 cy_analog_noconnect_38 (
.noconnect(Net_2780));
cy_analog_noconnect_v1_0 cy_analog_noconnect_41 (
.noconnect(Net_2781));
cy_analog_noconnect_v1_0 cy_analog_noconnect_43 (
.noconnect(Net_2784));
cy_analog_noconnect_v1_0 cy_analog_noconnect_44 (
.noconnect(Net_2785));
Bus_Connect_v1_10 Connect_2 (
.in_bus(mux_bus_minus[16:0]),
.out_bus(Net_2375[0:0]));
defparam Connect_2.in_width = 17;
defparam Connect_2.out_width = 1;
cy_analog_noconnect_v1_0 cy_analog_noconnect_2 (
.noconnect(Net_2559));
cy_analog_noconnect_v1_0 cy_analog_noconnect_4 (
.noconnect(Net_2560));
cy_analog_noconnect_v1_0 cy_analog_noconnect_22 (
.noconnect(Net_2561));
cy_analog_noconnect_v1_0 cy_analog_noconnect_23 (
.noconnect(Net_2562));
cy_analog_noconnect_v1_0 cy_analog_noconnect_24 (
.noconnect(Net_2563));
cy_analog_noconnect_v1_0 cy_analog_noconnect_25 (
.noconnect(Net_2564));
cy_analog_noconnect_v1_0 cy_analog_noconnect_26 (
.noconnect(Net_2565));
cy_analog_noconnect_v1_0 cy_analog_noconnect_27 (
.noconnect(Net_2566));
cy_analog_noconnect_v1_0 cy_analog_noconnect_28 (
.noconnect(Net_2567));
cy_analog_noconnect_v1_0 cy_analog_noconnect_29 (
.noconnect(Net_2568));
cy_analog_noconnect_v1_0 cy_analog_noconnect_30 (
.noconnect(Net_2569));
cy_analog_noconnect_v1_0 cy_analog_noconnect_31 (
.noconnect(Net_2570));
cy_analog_noconnect_v1_0 cy_analog_noconnect_32 (
.noconnect(Net_2571));
cy_analog_noconnect_v1_0 cy_analog_noconnect_33 (
.noconnect(Net_2572));
cy_analog_noconnect_v1_0 cy_analog_noconnect_34 (
.noconnect(Net_2573));
cy_analog_noconnect_v1_0 cy_analog_noconnect_35 (
.noconnect(Net_2574));
cy_isr_v1_0
#(.int_type(2'b10))
IRQ
(.int_signal(Net_2273));
assign Net_3093 = Net_1845 | Net_3090;
ZeroTerminal ZeroTerminal_8 (
.z(Net_3090));
// adc_plus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_plus_in_sel_connect(muxout_plus, mux_bus_plus[0]);
defparam adc_plus_in_sel_connect.sig_width = 1;
// adc_minus_in_sel (cy_analog_virtualmux_v1_0)
cy_connect_v1_0 adc_minus_in_sel_connect(muxout_minus, mux_bus_minus[0]);
defparam adc_minus_in_sel_connect.sig_width = 1;
cy_connect_v1_0 vinPlus0__cy_connect_v1_0(vinPlus0, mux_bus_plus[0]);
defparam vinPlus0__cy_connect_v1_0.sig_width = 1;
endmodule
// top
module top ;
electrical Net_32;
wire Net_31;
wire Net_30;
wire Net_29;
wire Net_28;
electrical Net_27;
wire Net_6;
wire Net_5;
wire Net_4;
SCB_P4_v1_20_0 UART_1 (
.sclk(Net_4),
.interrupt(Net_5),
.clock(1'b0));
ADC_SAR_SEQ_P4_v1_10_1 ADC (
.Vref(Net_27),
.sdone(Net_28),
.eoc(Net_29),
.aclk(1'b0),
.soc(1'b0),
.vinPlus0(Net_32));
wire [0:0] tmpOE__ADC_Test_net;
wire [0:0] tmpFB_0__ADC_Test_net;
wire [0:0] tmpIO_0__ADC_Test_net;
wire [0:0] tmpINTERRUPT_0__ADC_Test_net;
electrical [0:0] tmpSIOVREF__ADC_Test_net;
cy_psoc3_pins_v1_10
#(.id("42d42caa-d405-4edf-a265-58c332cb1cd9"),
.drive_mode(3'b000),
.ibuf_enabled(1'b0),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("A"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
ADC_Test
(.oe(tmpOE__ADC_Test_net),
.y({1'b0}),
.fb({tmpFB_0__ADC_Test_net[0:0]}),
.analog({Net_32}),
.io({tmpIO_0__ADC_Test_net[0:0]}),
.siovref(tmpSIOVREF__ADC_Test_net),
.interrupt({tmpINTERRUPT_0__ADC_Test_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__ADC_Test_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__LED_net;
wire [0:0] tmpFB_0__LED_net;
wire [0:0] tmpIO_0__LED_net;
wire [0:0] tmpINTERRUPT_0__LED_net;
electrical [0:0] tmpSIOVREF__LED_net;
cy_psoc3_pins_v1_10
#(.id("3dba336a-f6a5-43fb-aed3-de1e0b7bf362"),
.drive_mode(3'b110),
.ibuf_enabled(1'b1),
.init_dr_st(1'b0),
.input_clk_en(0),
.input_sync(1'b1),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("O"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b10),
.width(1))
LED
(.oe(tmpOE__LED_net),
.y({1'b0}),
.fb({tmpFB_0__LED_net[0:0]}),
.io({tmpIO_0__LED_net[0:0]}),
.siovref(tmpSIOVREF__LED_net),
.interrupt({tmpINTERRUPT_0__LED_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__LED_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
endmodule
|
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
`default_nettype wire
`define SYSTEM_DE2_115
module Frix(
input wire CLOCK_50,
// KEY
input wire [3:0] KEY,
// SDRAM
output wire [12:0] DRAM_ADDR,
output wire [1:0] DRAM_BA,
output wire DRAM_CAS_N,
output wire DRAM_CKE,
output wire DRAM_CLK,
output wire DRAM_CS_N,
inout wire [31:0] DRAM_DQ,
output wire [3:0] DRAM_DQM,
output wire DRAM_RAS_N,
output wire DRAM_WE_N,
// PS2 KEYBOARD
inout wire PS2_CLK,
inout wire PS2_DAT,
// SD
output wire SD_CLK,
inout wire SD_CMD,
inout wire [3:0] SD_DAT,
input wire SD_WP_N,
// VGA
output wire VGA_CLK,
output wire VGA_SYNC_N,
output wire VGA_BLANK_N,
output wire VGA_HS,
output wire VGA_VS,
output wire [7:0] VGA_R,
output wire [7:0] VGA_G,
output wire [7:0] VGA_B,
// LED
output reg [17:0] LEDR,
output reg [ 8:0] LEDG
);
//------------------------------------------------------------------------------
wire clk_sys;
wire clk_vga;
wire clk_sound;
wire rst;
wire rst_n;
wire RST_X_IN;
assign RST_X_IN = KEY[3];
assign DRAM_CLK = clk_sys;
GEN gen(
.CLK_IN (CLOCK_50),
.RST_X_IN (RST_X_IN),
.CLK_OUT (clk_sys),
.VGA_CLK_OUT (clk_vga),
.RST_X_OUT (rst_n)
);
assign rst = ~rst_n;
//------------------------------------------------------------------------------
wire ao486_reset;
//------------------------------------------------------------------------------
wire cache_waitrequest;
reg [25:0] cnt;
always @(posedge clk_sys) cnt <= cnt + 1;
always @(posedge clk_sys) begin
LEDG[0] <= cnt[25];
LEDG[1] <= ~rst;
LEDG[2] <= ~ao486_reset;
LEDG[3] <= ~SD_WP_N;
LEDG[5:4] <= {~PS2_CLK, ~PS2_DAT};
LEDG[8:6] <= {~SD_DAT[1:0], ~SD_CMD};
LEDR[17:0] <= {DRAM_ADDR[11:0], DRAM_BA, DRAM_CAS_N, DRAM_CKE, DRAM_CS_N};
end
//------------------------------------------------------------------------------
system u0(
.clk_sys (clk_sys),
.reset_sys (rst),
.clk_vga (clk_vga),
.reset_vga (rst),
.vga_clock (VGA_CLK),
.vga_sync_n (VGA_SYNC_N),
.vga_blank_n (VGA_BLANK_N),
.vga_horiz_sync (VGA_HS),
.vga_vert_sync (VGA_VS),
.vga_r (VGA_R),
.vga_g (VGA_G),
.vga_b (VGA_B),
.sdram_addr (DRAM_ADDR),
.sdram_ba (DRAM_BA),
.sdram_cas_n (DRAM_CAS_N),
.sdram_cke (DRAM_CKE),
.sdram_cs_n (DRAM_CS_N),
.sdram_dq (DRAM_DQ),
.sdram_dqm (DRAM_DQM),
.sdram_ras_n (DRAM_RAS_N),
.sdram_we_n (DRAM_WE_N),
.sd_clk (SD_CLK),
.sd_dat (SD_DAT),
.sd_cmd (SD_CMD),
.ps2_kbclk (PS2_CLK),
.ps2_kbdat (PS2_DAT),
.reset_only_ao486 (ao486_reset)
);
endmodule
|
module daala_idct4_mmap_v1_0_S00_AXI #
(
// Users to add parameters here
// User parameters ends
// Do not modify the parameters beyond this line
// Width of S_AXI data bus
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of S_AXI address bus
parameter integer C_S_AXI_ADDR_WIDTH = 4
)
(
// Users to add ports here
// User ports ends
// Do not modify the ports beyond this line
// Global Clock Signal
input wire S_AXI_ACLK,
// Global Reset Signal. This Signal is Active LOW
input wire S_AXI_ARESETN,
// Write address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
// Write channel Protection type. This signal indicates the
// privilege and security level of the transaction, and whether
// the transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_AWPROT,
// Write address valid. This signal indicates that the master signaling
// valid write address and control information.
input wire S_AXI_AWVALID,
// Write address ready. This signal indicates that the slave is ready
// to accept an address and associated control signals.
output wire S_AXI_AWREADY,
// Write data (issued by master, acceped by Slave)
input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
// Write strobes. This signal indicates which byte lanes hold
// valid data. There is one write strobe bit for each eight
// bits of the write data bus.
input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
// Write valid. This signal indicates that valid write
// data and strobes are available.
input wire S_AXI_WVALID,
// Write ready. This signal indicates that the slave
// can accept the write data.
output wire S_AXI_WREADY,
// Write response. This signal indicates the status
// of the write transaction.
output wire [1 : 0] S_AXI_BRESP,
// Write response valid. This signal indicates that the channel
// is signaling a valid write response.
output wire S_AXI_BVALID,
// Response ready. This signal indicates that the master
// can accept a write response.
input wire S_AXI_BREADY,
// Read address (issued by master, acceped by Slave)
input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
// Protection type. This signal indicates the privilege
// and security level of the transaction, and whether the
// transaction is a data access or an instruction access.
input wire [2 : 0] S_AXI_ARPROT,
// Read address valid. This signal indicates that the channel
// is signaling valid read address and control information.
input wire S_AXI_ARVALID,
// Read address ready. This signal indicates that the slave is
// ready to accept an address and associated control signals.
output wire S_AXI_ARREADY,
// Read data (issued by slave)
output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
// Read response. This signal indicates the status of the
// read transfer.
output wire [1 : 0] S_AXI_RRESP,
// Read valid. This signal indicates that the channel is
// signaling the required read data.
output wire S_AXI_RVALID,
// Read ready. This signal indicates that the master can
// accept the read data and response information.
input wire S_AXI_RREADY
);
// AXI4LITE signals
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
reg axi_awready;
reg axi_wready;
reg [1 : 0] axi_bresp;
reg axi_bvalid;
reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
reg axi_arready;
reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
reg [1 : 0] axi_rresp;
reg axi_rvalid;
// Example-specific design signals
// local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
// ADDR_LSB is used for addressing 32/64 bit registers/memories
// ADDR_LSB = 2 for 32 bits (n downto 2)
// ADDR_LSB = 3 for 64 bits (n downto 3)
localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
localparam integer OPT_MEM_ADDR_BITS = 1;
//----------------------------------------------
//-- Signals for user logic register space example
//------------------------------------------------
//-- Number of Slave Registers 4
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg0;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg1;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg2;
reg [C_S_AXI_DATA_WIDTH-1:0] slv_reg3;
wire slv_reg_rden;
wire slv_reg_wren;
reg [C_S_AXI_DATA_WIDTH-1:0] reg_data_out;
integer byte_index;
// I/O Connections assignments
assign S_AXI_AWREADY = axi_awready;
assign S_AXI_WREADY = axi_wready;
assign S_AXI_BRESP = axi_bresp;
assign S_AXI_BVALID = axi_bvalid;
assign S_AXI_ARREADY = axi_arready;
assign S_AXI_RDATA = axi_rdata;
assign S_AXI_RRESP = axi_rresp;
assign S_AXI_RVALID = axi_rvalid;
// Implement axi_awready generation
// axi_awready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awready <= 1'b0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// slave is ready to accept write address when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_awready <= 1'b1;
end
else
begin
axi_awready <= 1'b0;
end
end
end
// Implement axi_awaddr latching
// This process is used to latch the address when both
// S_AXI_AWVALID and S_AXI_WVALID are valid.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_awaddr <= 0;
end
else
begin
if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID)
begin
// Write Address latching
axi_awaddr <= S_AXI_AWADDR;
end
end
end
// Implement axi_wready generation
// axi_wready is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
// de-asserted when reset is low.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_wready <= 1'b0;
end
else
begin
if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID)
begin
// slave is ready to accept write data when
// there is a valid write address and write data
// on the write address and data bus. This design
// expects no outstanding transactions.
axi_wready <= 1'b1;
end
else
begin
axi_wready <= 1'b0;
end
end
end
// Implement memory mapped register select and write logic generation
// The write data is accepted and written to memory mapped registers when
// axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
// select byte enables of slave registers while writing.
// These registers are cleared when reset (active low) is applied.
// Slave register write enable is asserted when valid address and data are available
// and the slave is ready to accept the write address and write data.
assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
end
else begin
if (slv_reg_wren)
begin
case ( axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 0
slv_reg0[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h1:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 1
slv_reg1[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
/*
2'h2:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 2
slv_reg2[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
2'h3:
for ( byte_index = 0; byte_index <= (C_S_AXI_DATA_WIDTH/8)-1; byte_index = byte_index+1 )
if ( S_AXI_WSTRB[byte_index] == 1 ) begin
// Respective byte enables are asserted as per write strobes
// Slave register 3
slv_reg3[(byte_index*8) +: 8] <= S_AXI_WDATA[(byte_index*8) +: 8];
end
*/
default : begin
//slv_reg0 <= slv_reg0;
//slv_reg1 <= slv_reg1;
//slv_reg2 <= slv_reg2;
//slv_reg3 <= slv_reg3;
end
endcase
end
end
end
// Implement write response logic generation
// The write response and response valid signals are asserted by the slave
// when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
// This marks the acceptance of address and indicates the status of
// write transaction.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_bvalid <= 0;
axi_bresp <= 2'b0;
end
else
begin
if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
begin
// indicates a valid write response is available
axi_bvalid <= 1'b1;
axi_bresp <= 2'b0; // 'OKAY' response
end // work error responses in future
else
begin
if (S_AXI_BREADY && axi_bvalid)
//check if bready is asserted while bvalid is high)
//(there is a possibility that bready is always asserted high)
begin
axi_bvalid <= 1'b0;
end
end
end
end
// Implement axi_arready generation
// axi_arready is asserted for one S_AXI_ACLK clock cycle when
// S_AXI_ARVALID is asserted. axi_awready is
// de-asserted when reset (active low) is asserted.
// The read address is also latched when S_AXI_ARVALID is
// asserted. axi_araddr is reset to zero on reset assertion.
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_arready <= 1'b0;
axi_araddr <= 32'b0;
end
else
begin
if (~axi_arready && S_AXI_ARVALID)
begin
// indicates that the slave has acceped the valid read address
axi_arready <= 1'b1;
// Read address latching
axi_araddr <= S_AXI_ARADDR;
end
else
begin
axi_arready <= 1'b0;
end
end
end
// Implement axi_arvalid generation
// axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
// S_AXI_ARVALID and axi_arready are asserted. The slave registers
// data are available on the axi_rdata bus at this instance. The
// assertion of axi_rvalid marks the validity of read data on the
// bus and axi_rresp indicates the status of read transaction.axi_rvalid
// is deasserted on reset (active low). axi_rresp and axi_rdata are
// cleared to zero on reset (active low).
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rvalid <= 0;
axi_rresp <= 0;
end
else
begin
if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
begin
// Valid read data is available at the read data bus
axi_rvalid <= 1'b1;
axi_rresp <= 2'b0; // 'OKAY' response
end
else if (axi_rvalid && S_AXI_RREADY)
begin
// Read data is accepted by the master
axi_rvalid <= 1'b0;
end
end
end
reg signed[15:0] x0, x1, x2, x3;
// Implement memory mapped register select and read logic generation
// Slave register read enable is asserted when valid address is available
// and the slave is ready to accept the read address.
assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
always @(*)
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
reg_data_out <= 0;
end
else
begin
// Address decoding for reading registers
case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
2'h0 : reg_data_out <= slv_reg0;
2'h1 : reg_data_out <= slv_reg1;
2'h2 : reg_data_out <= {x0,x1};
2'h3 : reg_data_out <= {x2,x3};
default : reg_data_out <= 0;
endcase
end
end
// Output register or memory read data
always @( posedge S_AXI_ACLK )
begin
if ( S_AXI_ARESETN == 1'b0 )
begin
axi_rdata <= 0;
end
else
begin
// When there is a valid read address (S_AXI_ARVALID) with
// acceptance of read address by the slave (axi_arready),
// output the read dada
if (slv_reg_rden)
begin
axi_rdata <= reg_data_out; // register read data
end
end
end
// Add user logic here
wire signed [15:0] y0, y1, y2, y3;
assign y0 = slv_reg0[31:16];
assign y1 = slv_reg0[15:0];
assign y2 = slv_reg1[31:16];
assign y3 = slv_reg1[15:0];
reg signed [31:0] t0;
reg signed [31:0] t1;
reg signed [31:0] t2;
reg signed [31:0] t2h;
reg signed [31:0] t3;
always @(posedge S_AXI_ACLK)
begin
// lines in the lapping diagram
t0 = y0;
t1 = y1;
t2 = y2;
t3 = y3;
t3 = t3 + ((t1*16'sd18293+16'sd8192)>>>14);
//$display("%d",t3);
t1 = t1 - ((t3*16'sd21407+16'sd16384)>>>15);
//$display("%d",t1);
t3 = t3 + ((t1*16'sd23013+16'sd16384)>>>15);
//$display("%d",t3);
t2 = t0 - t2;
t2h = t2 >>> 1;
t0 = t0 - (t2h - (t3 >>> 1));
t1 = t2h - t1;
x0 = t0;
x1 = t2-t1;
x2 = t1;
x3 = t0 - t3;
end
// User logic ends
endmodule
|
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_mult_cell (
// inputs:
M_mul_src1,
M_mul_src2,
clk,
reset_n,
// outputs:
M_mul_cell_result
)
;
output [ 31: 0] M_mul_cell_result;
input [ 31: 0] M_mul_src1;
input [ 31: 0] M_mul_src2;
input clk;
input reset_n;
wire [ 31: 0] M_mul_cell_result;
wire [ 31: 0] M_mul_cell_result_part_1;
wire [ 15: 0] M_mul_cell_result_part_2;
wire mul_clr;
assign mul_clr = ~reset_n;
altmult_add the_altmult_add_part_1
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[15 : 0]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_1)
);
defparam the_altmult_add_part_1.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_1.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_1.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_1.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_1.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_1.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_1.input_source_a0 = "DATAA",
the_altmult_add_part_1.input_source_b0 = "DATAB",
the_altmult_add_part_1.intended_device_family = "CYCLONEII",
the_altmult_add_part_1.lpm_type = "altmult_add",
the_altmult_add_part_1.multiplier1_direction = "ADD",
the_altmult_add_part_1.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_1.multiplier_register0 = "CLOCK0",
the_altmult_add_part_1.number_of_multipliers = 1,
the_altmult_add_part_1.output_register = "UNREGISTERED",
the_altmult_add_part_1.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_1.port_signa = "PORT_UNUSED",
the_altmult_add_part_1.port_signb = "PORT_UNUSED",
the_altmult_add_part_1.representation_a = "UNSIGNED",
the_altmult_add_part_1.representation_b = "UNSIGNED",
the_altmult_add_part_1.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_1.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_1.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_1.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_1.signed_register_a = "UNREGISTERED",
the_altmult_add_part_1.signed_register_b = "UNREGISTERED",
the_altmult_add_part_1.width_a = 16,
the_altmult_add_part_1.width_b = 16,
the_altmult_add_part_1.width_result = 32;
altmult_add the_altmult_add_part_2
(
.aclr0 (mul_clr),
.clock0 (clk),
.dataa (M_mul_src1[31 : 16]),
.datab (M_mul_src2[15 : 0]),
.ena0 (1'b1),
.result (M_mul_cell_result_part_2)
);
defparam the_altmult_add_part_2.addnsub_multiplier_pipeline_aclr1 = "ACLR0",
the_altmult_add_part_2.addnsub_multiplier_pipeline_register1 = "CLOCK0",
the_altmult_add_part_2.addnsub_multiplier_register1 = "UNREGISTERED",
the_altmult_add_part_2.dedicated_multiplier_circuitry = "YES",
the_altmult_add_part_2.input_register_a0 = "UNREGISTERED",
the_altmult_add_part_2.input_register_b0 = "UNREGISTERED",
the_altmult_add_part_2.input_source_a0 = "DATAA",
the_altmult_add_part_2.input_source_b0 = "DATAB",
the_altmult_add_part_2.intended_device_family = "CYCLONEII",
the_altmult_add_part_2.lpm_type = "altmult_add",
the_altmult_add_part_2.multiplier1_direction = "ADD",
the_altmult_add_part_2.multiplier_aclr0 = "ACLR0",
the_altmult_add_part_2.multiplier_register0 = "CLOCK0",
the_altmult_add_part_2.number_of_multipliers = 1,
the_altmult_add_part_2.output_register = "UNREGISTERED",
the_altmult_add_part_2.port_addnsub1 = "PORT_UNUSED",
the_altmult_add_part_2.port_signa = "PORT_UNUSED",
the_altmult_add_part_2.port_signb = "PORT_UNUSED",
the_altmult_add_part_2.representation_a = "UNSIGNED",
the_altmult_add_part_2.representation_b = "UNSIGNED",
the_altmult_add_part_2.signed_pipeline_aclr_a = "ACLR0",
the_altmult_add_part_2.signed_pipeline_aclr_b = "ACLR0",
the_altmult_add_part_2.signed_pipeline_register_a = "CLOCK0",
the_altmult_add_part_2.signed_pipeline_register_b = "CLOCK0",
the_altmult_add_part_2.signed_register_a = "UNREGISTERED",
the_altmult_add_part_2.signed_register_b = "UNREGISTERED",
the_altmult_add_part_2.width_a = 16,
the_altmult_add_part_2.width_b = 16,
the_altmult_add_part_2.width_result = 16;
assign M_mul_cell_result = {M_mul_cell_result_part_1[31 : 16] +
M_mul_cell_result_part_2,
M_mul_cell_result_part_1[15 : 0]};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__UDP_DLATCH_P_BLACKBOX_V
`define SKY130_FD_SC_MS__UDP_DLATCH_P_BLACKBOX_V
/**
* udp_dlatch$P: D-latch, gated standard drive / active high
* (Q output UDP)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__udp_dlatch$P (
Q ,
D ,
GATE
);
output Q ;
input D ;
input GATE;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__UDP_DLATCH_P_BLACKBOX_V
|
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