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/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__AND2B_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__AND2B_BEHAVIORAL_PP_V
/**
* and2b: 2-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__and2b (
X ,
A_N ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X , not0_out, B );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__AND2B_BEHAVIORAL_PP_V |
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerperipheralhdladi_pcore_dut.v
// Created: 2014-09-08 14:12:15
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerperipheralhdladi_pcore_dut
// Source Path: controllerperipheralhdladi_pcore/controllerperipheralhdladi_pcore_dut
// Hierarchy Level: 1
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerperipheralhdladi_pcore_dut
(
CLK_IN,
reset,
dut_enable,
adc_current1,
adc_current2,
encoder_a,
encoder_b,
encoder_index,
axi_controller_mode,
axi_command,
axi_velocity_p_gain,
axi_velocity_i_gain,
axi_current_p_gain,
axi_current_i_gain,
axi_open_loop_bias,
axi_open_loop_scalar,
axi_encoder_zero_offset,
ce_out_0,
ce_out_1,
pwm_a,
pwm_b,
pwm_c,
mon_phase_voltage_a,
mon_phase_voltage_b,
mon_phase_current_a,
mon_phase_current_b,
mon_rotor_position,
mon_electrical_position,
mon_rotor_velocity,
mon_d_current,
mon_q_current,
axi_electrical_pos_err
);
input CLK_IN;
input reset;
input dut_enable; // ufix1
input signed [17:0] adc_current1; // sfix18_En17
input signed [17:0] adc_current2; // sfix18_En17
input encoder_a; // ufix1
input encoder_b; // ufix1
input encoder_index; // ufix1
input [1:0] axi_controller_mode; // ufix2
input signed [17:0] axi_command; // sfix18_En8
input signed [17:0] axi_velocity_p_gain; // sfix18_En16
input signed [17:0] axi_velocity_i_gain; // sfix18_En15
input signed [17:0] axi_current_p_gain; // sfix18_En10
input signed [17:0] axi_current_i_gain; // sfix18_En2
input signed [17:0] axi_open_loop_bias; // sfix18_En14
input signed [17:0] axi_open_loop_scalar; // sfix18_En16
input signed [17:0] axi_encoder_zero_offset; // sfix18_En14
output ce_out_0; // ufix1
output ce_out_1; // ufix1
output pwm_a; // ufix1
output pwm_b; // ufix1
output pwm_c; // ufix1
output signed [31:0] mon_phase_voltage_a; // sfix32
output signed [31:0] mon_phase_voltage_b; // sfix32
output signed [31:0] mon_phase_current_a; // sfix32
output signed [31:0] mon_phase_current_b; // sfix32
output signed [31:0] mon_rotor_position; // sfix32
output signed [31:0] mon_electrical_position; // sfix32
output signed [31:0] mon_rotor_velocity; // sfix32
output signed [31:0] mon_d_current; // sfix32
output signed [31:0] mon_q_current; // sfix32
output signed [18:0] axi_electrical_pos_err; // sfix19_En14
wire enb;
wire ce_out_0_sig; // ufix1
wire ce_out_1_sig; // ufix1
wire pwm_a_sig; // ufix1
wire pwm_b_sig; // ufix1
wire pwm_c_sig; // ufix1
wire signed [31:0] mon_phase_voltage_a_sig; // sfix32
wire signed [31:0] mon_phase_voltage_b_sig; // sfix32
wire signed [31:0] mon_phase_current_a_sig; // sfix32
wire signed [31:0] mon_phase_current_b_sig; // sfix32
wire signed [31:0] mon_rotor_position_sig; // sfix32
wire signed [31:0] mon_electrical_position_sig; // sfix32
wire signed [31:0] mon_rotor_velocity_sig; // sfix32
wire signed [31:0] mon_d_current_sig; // sfix32
wire signed [31:0] mon_q_current_sig; // sfix32
wire signed [18:0] axi_electrical_pos_err_sig; // sfix19_En14
assign enb = dut_enable;
controllerPeripheralHdlAdi u_controllerPeripheralHdlAdi (.CLK_IN(CLK_IN),
.clk_enable(enb),
.reset(reset),
.adc_current1(adc_current1), // sfix18_En17
.adc_current2(adc_current2), // sfix18_En17
.encoder_a(encoder_a), // ufix1
.encoder_b(encoder_b), // ufix1
.encoder_index(encoder_index), // ufix1
.axi_controller_mode(axi_controller_mode), // ufix2
.axi_command(axi_command), // sfix18_En8
.axi_velocity_p_gain(axi_velocity_p_gain), // sfix18_En16
.axi_velocity_i_gain(axi_velocity_i_gain), // sfix18_En15
.axi_current_p_gain(axi_current_p_gain), // sfix18_En10
.axi_current_i_gain(axi_current_i_gain), // sfix18_En2
.axi_open_loop_bias(axi_open_loop_bias), // sfix18_En14
.axi_open_loop_scalar(axi_open_loop_scalar), // sfix18_En16
.axi_encoder_zero_offset(axi_encoder_zero_offset), // sfix18_En14
.ce_out_0(ce_out_0_sig), // ufix1
.ce_out_1(ce_out_1_sig), // ufix1
.pwm_a(pwm_a_sig), // ufix1
.pwm_b(pwm_b_sig), // ufix1
.pwm_c(pwm_c_sig), // ufix1
.mon_phase_voltage_a(mon_phase_voltage_a_sig), // sfix32
.mon_phase_voltage_b(mon_phase_voltage_b_sig), // sfix32
.mon_phase_current_a(mon_phase_current_a_sig), // sfix32
.mon_phase_current_b(mon_phase_current_b_sig), // sfix32
.mon_rotor_position(mon_rotor_position_sig), // sfix32
.mon_electrical_position(mon_electrical_position_sig), // sfix32
.mon_rotor_velocity(mon_rotor_velocity_sig), // sfix32
.mon_d_current(mon_d_current_sig), // sfix32
.mon_q_current(mon_q_current_sig), // sfix32
.axi_electrical_pos_err(axi_electrical_pos_err_sig) // sfix19_En14
);
assign ce_out_0 = ce_out_0_sig;
assign ce_out_1 = ce_out_1_sig;
assign pwm_a = pwm_a_sig;
assign pwm_b = pwm_b_sig;
assign pwm_c = pwm_c_sig;
assign mon_phase_voltage_a = mon_phase_voltage_a_sig;
assign mon_phase_voltage_b = mon_phase_voltage_b_sig;
assign mon_phase_current_a = mon_phase_current_a_sig;
assign mon_phase_current_b = mon_phase_current_b_sig;
assign mon_rotor_position = mon_rotor_position_sig;
assign mon_electrical_position = mon_electrical_position_sig;
assign mon_rotor_velocity = mon_rotor_velocity_sig;
assign mon_d_current = mon_d_current_sig;
assign mon_q_current = mon_q_current_sig;
assign axi_electrical_pos_err = axi_electrical_pos_err_sig;
endmodule // controllerperipheralhdladi_pcore_dut
|
// $Id: testbench.v 5188 2012-08-30 00:31:31Z dub $
/*
Copyright (c) 2007-2012, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
`default_nettype none
module testbench
();
`include "c_functions.v"
`include "c_constants.v"
`include "rtr_constants.v"
`include "vcr_constants.v"
`include "parameters.v"
parameter Tclk = 2;
parameter initial_seed = 0;
// maximum number of packets to generate (-1 = no limit)
parameter max_packet_count = -1;
// packet injection rate (percentage of cycles)
parameter packet_rate = 25;
// flit consumption rate (percentage of cycles)
parameter consume_rate = 50;
// width of packet count register
parameter packet_count_reg_width = 32;
// channel latency in cycles
parameter channel_latency = 1;
// only inject traffic at the node ports
parameter inject_node_ports_only = 1;
// warmup time in cycles
parameter warmup_time = 100;
// measurement interval in cycles
parameter measure_time = 3000;
// select packet length mode (0: uniform random, 1: bimodal)
parameter packet_length_mode = 0;
// width required to select individual resource class
localparam resource_class_idx_width = clogb(num_resource_classes);
// total number of packet classes
localparam num_packet_classes = num_message_classes * num_resource_classes;
// number of VCs
localparam num_vcs = num_packet_classes * num_vcs_per_class;
// width required to select individual VC
localparam vc_idx_width = clogb(num_vcs);
// total number of routers
localparam num_routers
= (num_nodes + num_nodes_per_router - 1) / num_nodes_per_router;
// number of routers in each dimension
localparam num_routers_per_dim = croot(num_routers, num_dimensions);
// width required to select individual router in a dimension
localparam dim_addr_width = clogb(num_routers_per_dim);
// width required to select individual router in entire network
localparam router_addr_width = num_dimensions * dim_addr_width;
// connectivity within each dimension
localparam connectivity
= (topology == `TOPOLOGY_MESH) ?
`CONNECTIVITY_LINE :
(topology == `TOPOLOGY_TORUS) ?
`CONNECTIVITY_RING :
(topology == `TOPOLOGY_FBFLY) ?
`CONNECTIVITY_FULL :
-1;
// number of adjacent routers in each dimension
localparam num_neighbors_per_dim
= ((connectivity == `CONNECTIVITY_LINE) ||
(connectivity == `CONNECTIVITY_RING)) ?
2 :
(connectivity == `CONNECTIVITY_FULL) ?
(num_routers_per_dim - 1) :
-1;
// number of input and output ports on router
localparam num_ports
= num_dimensions * num_neighbors_per_dim + num_nodes_per_router;
// width required to select individual port
localparam port_idx_width = clogb(num_ports);
// width required to select individual node at current router
localparam node_addr_width = clogb(num_nodes_per_router);
// width required for lookahead routing information
localparam lar_info_width = port_idx_width + resource_class_idx_width;
// total number of bits required for storing routing information
localparam dest_info_width
= (routing_type == `ROUTING_TYPE_PHASED_DOR) ?
(num_resource_classes * router_addr_width + node_addr_width) :
-1;
// total number of bits required for routing-related information
localparam route_info_width = lar_info_width + dest_info_width;
// width of flow control signals
localparam flow_ctrl_width
= (flow_ctrl_type == `FLOW_CTRL_TYPE_CREDIT) ? (1 + vc_idx_width) :
-1;
// width of link management signals
localparam link_ctrl_width = enable_link_pm ? 1 : 0;
// width of flit control signals
localparam flit_ctrl_width
= (packet_format == `PACKET_FORMAT_HEAD_TAIL) ?
(1 + vc_idx_width + 1 + 1) :
(packet_format == `PACKET_FORMAT_TAIL_ONLY) ?
(1 + vc_idx_width + 1) :
(packet_format == `PACKET_FORMAT_EXPLICIT_LENGTH) ?
(1 + vc_idx_width + 1) :
-1;
// channel width
localparam channel_width
= link_ctrl_width + flit_ctrl_width + flit_data_width;
// use atomic VC allocation
localparam atomic_vc_allocation = (elig_mask == `ELIG_MASK_USED);
// number of pipeline stages in the channels
localparam num_channel_stages = channel_latency - 1;
reg clk;
reg reset;
//wires that are directly conected to the channel/flow_ctrl ports of each router
wire [0:channel_width-1] channel_router_0_op_0;
wire [0:channel_width-1] channel_router_0_op_1;
wire [0:channel_width-1] channel_router_0_op_2;
wire [0:channel_width-1] channel_router_0_op_3;
wire [0:channel_width-1] channel_router_0_op_4;
wire [0:channel_width-1] channel_router_0_ip_0;
wire [0:channel_width-1] channel_router_0_ip_1;
wire [0:channel_width-1] channel_router_0_ip_2;
wire [0:channel_width-1] channel_router_0_ip_3;
wire [0:channel_width-1] channel_router_0_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_0_op_4;
wire [0:channel_width-1] channel_router_1_op_0;
wire [0:channel_width-1] channel_router_1_op_1;
wire [0:channel_width-1] channel_router_1_op_2;
wire [0:channel_width-1] channel_router_1_op_3;
wire [0:channel_width-1] channel_router_1_op_4;
wire [0:channel_width-1] channel_router_1_ip_0;
wire [0:channel_width-1] channel_router_1_ip_1;
wire [0:channel_width-1] channel_router_1_ip_2;
wire [0:channel_width-1] channel_router_1_ip_3;
wire [0:channel_width-1] channel_router_1_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_1_op_4;
wire [0:channel_width-1] channel_router_2_op_0;
wire [0:channel_width-1] channel_router_2_op_1;
wire [0:channel_width-1] channel_router_2_op_2;
wire [0:channel_width-1] channel_router_2_op_3;
wire [0:channel_width-1] channel_router_2_op_4;
wire [0:channel_width-1] channel_router_2_ip_0;
wire [0:channel_width-1] channel_router_2_ip_1;
wire [0:channel_width-1] channel_router_2_ip_2;
wire [0:channel_width-1] channel_router_2_ip_3;
wire [0:channel_width-1] channel_router_2_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_2_op_4;
wire [0:channel_width-1] channel_router_3_op_0;
wire [0:channel_width-1] channel_router_3_op_1;
wire [0:channel_width-1] channel_router_3_op_2;
wire [0:channel_width-1] channel_router_3_op_3;
wire [0:channel_width-1] channel_router_3_op_4;
wire [0:channel_width-1] channel_router_3_ip_0;
wire [0:channel_width-1] channel_router_3_ip_1;
wire [0:channel_width-1] channel_router_3_ip_2;
wire [0:channel_width-1] channel_router_3_ip_3;
wire [0:channel_width-1] channel_router_3_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_3_op_4;
wire [0:channel_width-1] channel_router_4_op_0;
wire [0:channel_width-1] channel_router_4_op_1;
wire [0:channel_width-1] channel_router_4_op_2;
wire [0:channel_width-1] channel_router_4_op_3;
wire [0:channel_width-1] channel_router_4_op_4;
wire [0:channel_width-1] channel_router_4_ip_0;
wire [0:channel_width-1] channel_router_4_ip_1;
wire [0:channel_width-1] channel_router_4_ip_2;
wire [0:channel_width-1] channel_router_4_ip_3;
wire [0:channel_width-1] channel_router_4_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_4_op_4;
wire [0:channel_width-1] channel_router_5_op_0;
wire [0:channel_width-1] channel_router_5_op_1;
wire [0:channel_width-1] channel_router_5_op_2;
wire [0:channel_width-1] channel_router_5_op_3;
wire [0:channel_width-1] channel_router_5_op_4;
wire [0:channel_width-1] channel_router_5_ip_0;
wire [0:channel_width-1] channel_router_5_ip_1;
wire [0:channel_width-1] channel_router_5_ip_2;
wire [0:channel_width-1] channel_router_5_ip_3;
wire [0:channel_width-1] channel_router_5_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_5_op_4;
wire [0:channel_width-1] channel_router_6_op_0;
wire [0:channel_width-1] channel_router_6_op_1;
wire [0:channel_width-1] channel_router_6_op_2;
wire [0:channel_width-1] channel_router_6_op_3;
wire [0:channel_width-1] channel_router_6_op_4;
wire [0:channel_width-1] channel_router_6_ip_0;
wire [0:channel_width-1] channel_router_6_ip_1;
wire [0:channel_width-1] channel_router_6_ip_2;
wire [0:channel_width-1] channel_router_6_ip_3;
wire [0:channel_width-1] channel_router_6_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_6_op_4;
wire [0:channel_width-1] channel_router_7_op_0;
wire [0:channel_width-1] channel_router_7_op_1;
wire [0:channel_width-1] channel_router_7_op_2;
wire [0:channel_width-1] channel_router_7_op_3;
wire [0:channel_width-1] channel_router_7_op_4;
wire [0:channel_width-1] channel_router_7_ip_0;
wire [0:channel_width-1] channel_router_7_ip_1;
wire [0:channel_width-1] channel_router_7_ip_2;
wire [0:channel_width-1] channel_router_7_ip_3;
wire [0:channel_width-1] channel_router_7_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_7_op_4;
wire [0:channel_width-1] channel_router_8_op_0;
wire [0:channel_width-1] channel_router_8_op_1;
wire [0:channel_width-1] channel_router_8_op_2;
wire [0:channel_width-1] channel_router_8_op_3;
wire [0:channel_width-1] channel_router_8_op_4;
wire [0:channel_width-1] channel_router_8_ip_0;
wire [0:channel_width-1] channel_router_8_ip_1;
wire [0:channel_width-1] channel_router_8_ip_2;
wire [0:channel_width-1] channel_router_8_ip_3;
wire [0:channel_width-1] channel_router_8_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_ip_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_ip_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_ip_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_ip_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_ip_4;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_op_0;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_op_1;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_op_2;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_op_3;
wire [0:flow_ctrl_width-1] flow_ctrl_router_8_op_4;
//wires that are connected to the flit_sink and packet_source modules
wire [0:(num_routers*channel_width)-1] injection_channels;
wire [0:(num_routers*flow_ctrl_width)-1] injection_flow_ctrl;
wire [0:(num_routers*channel_width)-1] ejection_channels;
wire [0:(num_routers*flow_ctrl_width)-1] ejection_flow_ctrl;
//connected together channels and flow_ctrl
assign channel_router_0_ip_0 = {channel_width{1'b0}};
assign channel_router_0_ip_1 = channel_router_1_op_0;
assign channel_router_0_ip_2 = {channel_width{1'b0}};
assign channel_router_0_ip_3 = channel_router_3_op_2;
assign channel_router_0_ip_4 = injection_channels[0*channel_width:(1*channel_width)-1];
assign flow_ctrl_router_0_op_0 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_0_op_1 = flow_ctrl_router_1_ip_0;
assign flow_ctrl_router_0_op_2 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_0_op_3 = flow_ctrl_router_3_ip_2;
assign flow_ctrl_router_0_op_4 = ejection_flow_ctrl[0*flow_ctrl_width:(1*flow_ctrl_width)-1];
assign channel_router_1_ip_0 = channel_router_0_op_1;
assign channel_router_1_ip_1 = channel_router_2_op_0;
assign channel_router_1_ip_2 = {channel_width{1'b0}};
assign channel_router_1_ip_3 = channel_router_4_op_2;
assign channel_router_1_ip_4 = injection_channels[1*channel_width:(2*channel_width)-1];
assign flow_ctrl_router_1_op_0 = flow_ctrl_router_0_ip_1;
assign flow_ctrl_router_1_op_1 = flow_ctrl_router_2_ip_0;
assign flow_ctrl_router_1_op_2 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_1_op_3 = flow_ctrl_router_4_ip_2;
assign flow_ctrl_router_1_op_4 = ejection_flow_ctrl[1*flow_ctrl_width:(2*flow_ctrl_width)-1];
assign channel_router_2_ip_0 = channel_router_1_op_1;
assign channel_router_2_ip_1 = {channel_width{1'b0}};
assign channel_router_2_ip_2 = {channel_width{1'b0}};
assign channel_router_2_ip_3 = channel_router_5_op_2;
assign channel_router_2_ip_4 = injection_channels[2*channel_width:(3*channel_width)-1];
assign flow_ctrl_router_2_op_0 = flow_ctrl_router_1_ip_1;
assign flow_ctrl_router_2_op_1 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_2_op_2 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_2_op_3 = flow_ctrl_router_5_ip_2;
assign flow_ctrl_router_2_op_4 = ejection_flow_ctrl[2*flow_ctrl_width:(3*flow_ctrl_width)-1];
assign channel_router_3_ip_0 = {channel_width{1'b0}};
assign channel_router_3_ip_1 = channel_router_4_op_0;
assign channel_router_3_ip_2 = channel_router_0_op_3;
assign channel_router_3_ip_3 = channel_router_6_op_2;
assign channel_router_3_ip_4 = injection_channels[3*channel_width:(4*channel_width)-1];
assign flow_ctrl_router_3_op_0 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_3_op_1 = flow_ctrl_router_4_ip_0;
assign flow_ctrl_router_3_op_2 = flow_ctrl_router_0_ip_3;
assign flow_ctrl_router_3_op_3 = flow_ctrl_router_6_ip_2;
assign flow_ctrl_router_3_op_4 = ejection_flow_ctrl[3*flow_ctrl_width:(4*flow_ctrl_width)-1];
assign channel_router_4_ip_0 = channel_router_3_op_1;
assign channel_router_4_ip_1 = channel_router_5_op_0;
assign channel_router_4_ip_2 = channel_router_1_op_3;
assign channel_router_4_ip_3 = channel_router_7_op_2;
assign channel_router_4_ip_4 = injection_channels[4*channel_width:(5*channel_width)-1];
assign flow_ctrl_router_4_op_0 = flow_ctrl_router_3_ip_1;
assign flow_ctrl_router_4_op_1 = flow_ctrl_router_5_ip_0;
assign flow_ctrl_router_4_op_2 = flow_ctrl_router_1_ip_3;
assign flow_ctrl_router_4_op_3 = flow_ctrl_router_7_ip_2;
assign flow_ctrl_router_4_op_4 = ejection_flow_ctrl[4*flow_ctrl_width:(5*flow_ctrl_width)-1];
assign channel_router_5_ip_0 = channel_router_4_op_1;
assign channel_router_5_ip_1 = {channel_width{1'b0}};
assign channel_router_5_ip_2 = channel_router_2_op_3;
assign channel_router_5_ip_3 = channel_router_8_op_2;
assign channel_router_5_ip_4 = injection_channels[5*channel_width:(6*channel_width)-1];
assign flow_ctrl_router_5_op_0 = flow_ctrl_router_4_ip_1;
assign flow_ctrl_router_5_op_1 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_5_op_2 = flow_ctrl_router_2_ip_3;
assign flow_ctrl_router_5_op_3 = flow_ctrl_router_8_ip_2;
assign flow_ctrl_router_5_op_4 = ejection_flow_ctrl[5*flow_ctrl_width:(6*flow_ctrl_width)-1];
assign channel_router_6_ip_0 = {channel_width{1'b0}};
assign channel_router_6_ip_1 = channel_router_7_op_0;
assign channel_router_6_ip_2 = channel_router_3_op_3;
assign channel_router_6_ip_3 = {channel_width{1'b0}};
assign channel_router_6_ip_4 = injection_channels[6*channel_width:(7*channel_width)-1];
assign flow_ctrl_router_6_op_0 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_6_op_1 = flow_ctrl_router_7_ip_0;
assign flow_ctrl_router_6_op_2 = flow_ctrl_router_3_ip_3;
assign flow_ctrl_router_6_op_3 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_6_op_4 = ejection_flow_ctrl[6*flow_ctrl_width:(7*flow_ctrl_width)-1];
assign channel_router_7_ip_0 = channel_router_6_op_1;
assign channel_router_7_ip_1 = channel_router_8_op_0;
assign channel_router_7_ip_2 = channel_router_4_op_3;
assign channel_router_7_ip_3 = {channel_width{1'b0}};
assign channel_router_7_ip_4 = injection_channels[7*channel_width:(8*channel_width)-1];
assign flow_ctrl_router_7_op_0 = flow_ctrl_router_6_ip_1;
assign flow_ctrl_router_7_op_1 = flow_ctrl_router_8_ip_0;
assign flow_ctrl_router_7_op_2 = flow_ctrl_router_4_ip_3;
assign flow_ctrl_router_7_op_3 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_7_op_4 = ejection_flow_ctrl[7*flow_ctrl_width:(8*flow_ctrl_width)-1];
assign channel_router_8_ip_0 = channel_router_7_op_1;
assign channel_router_8_ip_1 = {channel_width{1'b0}};
assign channel_router_8_ip_2 = channel_router_5_op_3;
assign channel_router_8_ip_3 = {channel_width{1'b0}};
assign channel_router_8_ip_4 = injection_channels[8*channel_width:(9*channel_width)-1];
assign flow_ctrl_router_8_op_0 = flow_ctrl_router_7_ip_1;
assign flow_ctrl_router_8_op_1 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_8_op_2 = flow_ctrl_router_5_ip_3;
assign flow_ctrl_router_8_op_3 = {flow_ctrl_width{1'b0}};
assign flow_ctrl_router_8_op_4 = ejection_flow_ctrl[8*flow_ctrl_width:(9*flow_ctrl_width)-1];
//connected routers to flit_sink and packet_source
assign injection_flow_ctrl[0*flow_ctrl_width:(1*flow_ctrl_width)-1] = flow_ctrl_router_0_ip_4;
assign ejection_channels[0*channel_width:(1*channel_width)-1] = channel_router_0_op_4;
assign injection_flow_ctrl[1*flow_ctrl_width:(2*flow_ctrl_width)-1] = flow_ctrl_router_1_ip_4;
assign ejection_channels[1*channel_width:(2*channel_width)-1] = channel_router_1_op_4;
assign injection_flow_ctrl[2*flow_ctrl_width:(3*flow_ctrl_width)-1] = flow_ctrl_router_2_ip_4;
assign ejection_channels[2*channel_width:(3*channel_width)-1] = channel_router_2_op_4;
assign injection_flow_ctrl[3*flow_ctrl_width:(4*flow_ctrl_width)-1] = flow_ctrl_router_3_ip_4;
assign ejection_channels[3*channel_width:(4*channel_width)-1] = channel_router_3_op_4;
assign injection_flow_ctrl[4*flow_ctrl_width:(5*flow_ctrl_width)-1] = flow_ctrl_router_4_ip_4;
assign ejection_channels[4*channel_width:(5*channel_width)-1] = channel_router_4_op_4;
assign injection_flow_ctrl[5*flow_ctrl_width:(6*flow_ctrl_width)-1] = flow_ctrl_router_5_ip_4;
assign ejection_channels[5*channel_width:(6*channel_width)-1] = channel_router_5_op_4;
assign injection_flow_ctrl[6*flow_ctrl_width:(7*flow_ctrl_width)-1] = flow_ctrl_router_6_ip_4;
assign ejection_channels[6*channel_width:(7*channel_width)-1] = channel_router_6_op_4;
assign injection_flow_ctrl[7*flow_ctrl_width:(8*flow_ctrl_width)-1] = flow_ctrl_router_7_ip_4;
assign ejection_channels[7*channel_width:(8*channel_width)-1] = channel_router_7_op_4;
assign injection_flow_ctrl[8*flow_ctrl_width:(9*flow_ctrl_width)-1] = flow_ctrl_router_8_ip_4;
assign ejection_channels[8*channel_width:(9*channel_width)-1] = channel_router_8_op_4;
wire [0:num_routers-1] flit_valid_in_ip;
wire [0:num_routers-1] cred_valid_out_ip;
wire [0:num_routers-1] flit_valid_out_op;
wire [0:num_routers-1] cred_valid_in_op;
wire [0:num_routers-1] ps_error_ip;
reg run;
genvar ip;
generate
//9 packet sources, one for each router in the 3x3 mesh
for(ip = 0; ip < num_routers; ip = ip + 1) //variable name is "ip" but it's really the router id
begin:ips
wire [0:flow_ctrl_width-1] flow_ctrl_out;
assign flow_ctrl_out = injection_flow_ctrl[ip*flow_ctrl_width:
(ip+1)*flow_ctrl_width-1];
assign cred_valid_out_ip[ip] = flow_ctrl_out[0];
wire [0:flow_ctrl_width-1] flow_ctrl_dly;
c_shift_reg
#(.width(flow_ctrl_width),
.depth(num_channel_stages),
.reset_type(reset_type))
flow_ctrl_dly_sr
(.clk(clk),
.reset(reset),
.active(1'b1),
.data_in(flow_ctrl_out),
.data_out(flow_ctrl_dly));
wire [0:channel_width-1] channel;
wire flit_valid;
wire [0:router_addr_width-1] router_address;
wire ps_error;
//determines router address based on router id
case(ip)
0: assign router_address = 4'b0000;
1: assign router_address = 4'b0100;
2: assign router_address = 4'b1000;
3: assign router_address = 4'b0001;
4: assign router_address = 4'b0101;
5: assign router_address = 4'b1001;
6: assign router_address = 4'b0010;
7: assign router_address = 4'b0110;
8: assign router_address = 4'b1010;
default: assign router_address = 4'b0000;
endcase
packet_source
#(.initial_seed(initial_seed+ip),
.max_packet_count(max_packet_count),
.packet_rate(packet_rate),
.packet_count_reg_width(packet_count_reg_width),
.packet_length_mode(packet_length_mode),
.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.routing_type(routing_type),
.dim_order(dim_order),
.fb_mgmt_type(fb_mgmt_type),
.disable_static_reservations(disable_static_reservations),
.elig_mask(elig_mask),
.port_id(4), //hardcoded to the injection port, port 4
.reset_type(reset_type))
ps
(.clk(clk),
.reset(reset),
.router_address(router_address),
.channel(channel),
.flit_valid(flit_valid),
.flow_ctrl(flow_ctrl_dly),
.run(run),
.error(ps_error));
assign ps_error_ip[ip] = ps_error;
wire [0:channel_width-1] channel_dly;
c_shift_reg
#(.width(channel_width),
.depth(num_channel_stages),
.reset_type(reset_type))
channel_dly_sr
(.clk(clk),
.reset(reset),
.active(1'b1),
.data_in(channel),
.data_out(channel_dly));
assign injection_channels[ip*channel_width:(ip+1)*channel_width-1]
= channel_dly;
wire flit_valid_dly;
c_shift_reg
#(.width(1),
.depth(num_channel_stages),
.reset_type(reset_type))
flit_valid_dly_sr
(.clk(clk),
.reset(reset),
.active(1'b1),
.data_in(flit_valid),
.data_out(flit_valid_dly));
assign flit_valid_in_ip[ip] = flit_valid_dly;
end
endgenerate
//routers currently connected as a 3X3 mesh
wire [0:num_routers-1] rtr_error;
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_0
(.clk(clk),
.reset(reset),
.router_address(4'b0000),
.channel_in_ip({channel_router_0_ip_0, channel_router_0_ip_1, channel_router_0_ip_2, channel_router_0_ip_3, channel_router_0_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_0_ip_0, flow_ctrl_router_0_ip_1, flow_ctrl_router_0_ip_2, flow_ctrl_router_0_ip_3, flow_ctrl_router_0_ip_4 }),
.channel_out_op({ channel_router_0_op_0, channel_router_0_op_1, channel_router_0_op_2, channel_router_0_op_3, channel_router_0_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_0_op_0, flow_ctrl_router_0_op_1, flow_ctrl_router_0_op_2, flow_ctrl_router_0_op_3, flow_ctrl_router_0_op_4 }),
.error(rtr_error[0]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_1
(.clk(clk),
.reset(reset),
.router_address(4'b0100),
.channel_in_ip({channel_router_1_ip_0, channel_router_1_ip_1, channel_router_1_ip_2, channel_router_1_ip_3, channel_router_1_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_1_ip_0, flow_ctrl_router_1_ip_1, flow_ctrl_router_1_ip_2, flow_ctrl_router_1_ip_3, flow_ctrl_router_1_ip_4 }),
.channel_out_op({ channel_router_1_op_0, channel_router_1_op_1, channel_router_1_op_2, channel_router_1_op_3, channel_router_1_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_1_op_0, flow_ctrl_router_1_op_1, flow_ctrl_router_1_op_2, flow_ctrl_router_1_op_3, flow_ctrl_router_1_op_4 }),
.error(rtr_error[1]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_2
(.clk(clk),
.reset(reset),
.router_address(4'b1000),
.channel_in_ip({channel_router_2_ip_0, channel_router_2_ip_1, channel_router_2_ip_2, channel_router_2_ip_3, channel_router_2_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_2_ip_0, flow_ctrl_router_2_ip_1, flow_ctrl_router_2_ip_2, flow_ctrl_router_2_ip_3, flow_ctrl_router_2_ip_4 }),
.channel_out_op({ channel_router_2_op_0, channel_router_2_op_1, channel_router_2_op_2, channel_router_2_op_3, channel_router_2_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_2_op_0, flow_ctrl_router_2_op_1, flow_ctrl_router_2_op_2, flow_ctrl_router_2_op_3, flow_ctrl_router_2_op_4 }),
.error(rtr_error[2]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_3
(.clk(clk),
.reset(reset),
.router_address(4'b0001),
.channel_in_ip({channel_router_3_ip_0, channel_router_3_ip_1, channel_router_3_ip_2, channel_router_3_ip_3, channel_router_3_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_3_ip_0, flow_ctrl_router_3_ip_1, flow_ctrl_router_3_ip_2, flow_ctrl_router_3_ip_3, flow_ctrl_router_3_ip_4 }),
.channel_out_op({ channel_router_3_op_0, channel_router_3_op_1, channel_router_3_op_2, channel_router_3_op_3, channel_router_3_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_3_op_0, flow_ctrl_router_3_op_1, flow_ctrl_router_3_op_2, flow_ctrl_router_3_op_3, flow_ctrl_router_3_op_4 }),
.error(rtr_error[3]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_4
(.clk(clk),
.reset(reset),
.router_address(4'b0101),
.channel_in_ip({channel_router_4_ip_0, channel_router_4_ip_1, channel_router_4_ip_2, channel_router_4_ip_3, channel_router_4_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_4_ip_0, flow_ctrl_router_4_ip_1, flow_ctrl_router_4_ip_2, flow_ctrl_router_4_ip_3, flow_ctrl_router_4_ip_4 }),
.channel_out_op({ channel_router_4_op_0, channel_router_4_op_1, channel_router_4_op_2, channel_router_4_op_3, channel_router_4_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_4_op_0, flow_ctrl_router_4_op_1, flow_ctrl_router_4_op_2, flow_ctrl_router_4_op_3, flow_ctrl_router_4_op_4 }),
.error(rtr_error[4]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_5
(.clk(clk),
.reset(reset),
.router_address(4'b1001),
.channel_in_ip({channel_router_5_ip_0, channel_router_5_ip_1, channel_router_5_ip_2, channel_router_5_ip_3, channel_router_5_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_5_ip_0, flow_ctrl_router_5_ip_1, flow_ctrl_router_5_ip_2, flow_ctrl_router_5_ip_3, flow_ctrl_router_5_ip_4 }),
.channel_out_op({ channel_router_5_op_0, channel_router_5_op_1, channel_router_5_op_2, channel_router_5_op_3, channel_router_5_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_5_op_0, flow_ctrl_router_5_op_1, flow_ctrl_router_5_op_2, flow_ctrl_router_5_op_3, flow_ctrl_router_5_op_4 }),
.error(rtr_error[5]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_6
(.clk(clk),
.reset(reset),
.router_address(4'b0010),
.channel_in_ip({channel_router_6_ip_0, channel_router_6_ip_1, channel_router_6_ip_2, channel_router_6_ip_3, channel_router_6_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_6_ip_0, flow_ctrl_router_6_ip_1, flow_ctrl_router_6_ip_2, flow_ctrl_router_6_ip_3, flow_ctrl_router_6_ip_4 }),
.channel_out_op({ channel_router_6_op_0, channel_router_6_op_1, channel_router_6_op_2, channel_router_6_op_3, channel_router_6_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_6_op_0, flow_ctrl_router_6_op_1, flow_ctrl_router_6_op_2, flow_ctrl_router_6_op_3, flow_ctrl_router_6_op_4 }),
.error(rtr_error[6]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_7
(.clk(clk),
.reset(reset),
.router_address(4'b0110),
.channel_in_ip({channel_router_7_ip_0, channel_router_7_ip_1, channel_router_7_ip_2, channel_router_7_ip_3, channel_router_7_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_7_ip_0, flow_ctrl_router_7_ip_1, flow_ctrl_router_7_ip_2, flow_ctrl_router_7_ip_3, flow_ctrl_router_7_ip_4 }),
.channel_out_op({ channel_router_7_op_0, channel_router_7_op_1, channel_router_7_op_2, channel_router_7_op_3, channel_router_7_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_7_op_0, flow_ctrl_router_7_op_1, flow_ctrl_router_7_op_2, flow_ctrl_router_7_op_3, flow_ctrl_router_7_op_4 }),
.error(rtr_error[7]));
router_wrap
#(.topology(topology),
.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_nodes(num_nodes),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.flow_ctrl_bypass(flow_ctrl_bypass),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.router_type(router_type),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.restrict_turns(restrict_turns),
.predecode_lar_info(predecode_lar_info),
.routing_type(routing_type),
.dim_order(dim_order),
.input_stage_can_hold(input_stage_can_hold),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.explicit_pipeline_register(explicit_pipeline_register),
.dual_path_alloc(dual_path_alloc),
.dual_path_allow_conflicts(dual_path_allow_conflicts),
.dual_path_mask_on_ready(dual_path_mask_on_ready),
.precomp_ivc_sel(precomp_ivc_sel),
.precomp_ip_sel(precomp_ip_sel),
.elig_mask(elig_mask),
.vc_alloc_type(vc_alloc_type),
.vc_alloc_arbiter_type(vc_alloc_arbiter_type),
.vc_alloc_prefer_empty(vc_alloc_prefer_empty),
.sw_alloc_type(sw_alloc_type),
.sw_alloc_arbiter_type(sw_alloc_arbiter_type),
.sw_alloc_spec_type(sw_alloc_spec_type),
.crossbar_type(crossbar_type),
.reset_type(reset_type))
rtr_8
(.clk(clk),
.reset(reset),
.router_address(4'b1010),
.channel_in_ip({channel_router_8_ip_0, channel_router_8_ip_1, channel_router_8_ip_2, channel_router_8_ip_3, channel_router_8_ip_4}),
.flow_ctrl_out_ip({ flow_ctrl_router_8_ip_0, flow_ctrl_router_8_ip_1, flow_ctrl_router_8_ip_2, flow_ctrl_router_8_ip_3, flow_ctrl_router_8_ip_4 }),
.channel_out_op({ channel_router_8_op_0, channel_router_8_op_1, channel_router_8_op_2, channel_router_8_op_3, channel_router_8_op_4 }),
.flow_ctrl_in_op({ flow_ctrl_router_8_op_0, flow_ctrl_router_8_op_1, flow_ctrl_router_8_op_2, flow_ctrl_router_8_op_3, flow_ctrl_router_8_op_4 }),
.error(rtr_error[8]));
//9 router checkers. One for each router in the 3X3 mesh
wire [0:num_routers-1] rchk_error;
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_0
(.clk(clk),
.reset(reset),
.router_address(4'b0000),
.channel_in_ip({channel_router_0_ip_0, channel_router_0_ip_1, channel_router_0_ip_2, channel_router_0_ip_3, channel_router_0_ip_4}),
.channel_out_op({ channel_router_0_op_0, channel_router_0_op_1, channel_router_0_op_2, channel_router_0_op_3, channel_router_0_op_4 }),
.error(rchk_error[0]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_1
(.clk(clk),
.reset(reset),
.router_address(4'b0100),
.channel_in_ip({channel_router_1_ip_0, channel_router_1_ip_1, channel_router_1_ip_2, channel_router_1_ip_3, channel_router_1_ip_4}),
.channel_out_op({ channel_router_1_op_0, channel_router_1_op_1, channel_router_1_op_2, channel_router_1_op_3, channel_router_1_op_4 }),
.error(rchk_error[1]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_2
(.clk(clk),
.reset(reset),
.router_address(4'b1000),
.channel_in_ip({channel_router_2_ip_0, channel_router_2_ip_1, channel_router_2_ip_2, channel_router_2_ip_3, channel_router_2_ip_4}),
.channel_out_op({ channel_router_2_op_0, channel_router_2_op_1, channel_router_2_op_2, channel_router_2_op_3, channel_router_2_op_4 }),
.error(rchk_error[2]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_3
(.clk(clk),
.reset(reset),
.router_address(4'b0001),
.channel_in_ip({channel_router_3_ip_0, channel_router_3_ip_1, channel_router_3_ip_2, channel_router_3_ip_3, channel_router_3_ip_4}),
.channel_out_op({ channel_router_3_op_0, channel_router_3_op_1, channel_router_3_op_2, channel_router_3_op_3, channel_router_3_op_4 }),
.error(rchk_error[3]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_4
(.clk(clk),
.reset(reset),
.router_address(4'b0101),
.channel_in_ip({channel_router_4_ip_0, channel_router_4_ip_1, channel_router_4_ip_2, channel_router_4_ip_3, channel_router_4_ip_4}),
.channel_out_op({ channel_router_4_op_0, channel_router_4_op_1, channel_router_4_op_2, channel_router_4_op_3, channel_router_4_op_4 }),
.error(rchk_error[4]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_5
(.clk(clk),
.reset(reset),
.router_address(4'b1001),
.channel_in_ip({channel_router_5_ip_0, channel_router_5_ip_1, channel_router_5_ip_2, channel_router_5_ip_3, channel_router_5_ip_4}),
.channel_out_op({ channel_router_5_op_0, channel_router_5_op_1, channel_router_5_op_2, channel_router_5_op_3, channel_router_5_op_4 }),
.error(rchk_error[5]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_6
(.clk(clk),
.reset(reset),
.router_address(4'b0010),
.channel_in_ip({channel_router_6_ip_0, channel_router_6_ip_1, channel_router_6_ip_2, channel_router_6_ip_3, channel_router_6_ip_4}),
.channel_out_op({ channel_router_6_op_0, channel_router_6_op_1, channel_router_6_op_2, channel_router_6_op_3, channel_router_6_op_4 }),
.error(rchk_error[6]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_7
(.clk(clk),
.reset(reset),
.router_address(4'b0110),
.channel_in_ip({channel_router_7_ip_0, channel_router_7_ip_1, channel_router_7_ip_2, channel_router_7_ip_3, channel_router_7_ip_4}),
.channel_out_op({ channel_router_7_op_0, channel_router_7_op_1, channel_router_7_op_2, channel_router_7_op_3, channel_router_7_op_4 }),
.error(rchk_error[7]));
router_checker
#(.buffer_size(buffer_size),
.num_message_classes(num_message_classes),
.num_resource_classes(num_resource_classes),
.num_vcs_per_class(num_vcs_per_class),
.num_routers_per_dim(num_routers_per_dim),
.num_dimensions(num_dimensions),
.num_nodes_per_router(num_nodes_per_router),
.connectivity(connectivity),
.packet_format(packet_format),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.error_capture_mode(error_capture_mode),
.routing_type(routing_type),
.dim_order(dim_order),
.reset_type(reset_type))
rchk_8
(.clk(clk),
.reset(reset),
.router_address(4'b1010),
.channel_in_ip({channel_router_8_ip_0, channel_router_8_ip_1, channel_router_8_ip_2, channel_router_8_ip_3, channel_router_8_ip_4}),
.channel_out_op({ channel_router_8_op_0, channel_router_8_op_1, channel_router_8_op_2, channel_router_8_op_3, channel_router_8_op_4 }),
.error(rchk_error[8]));
wire [0:num_routers-1] fs_error_op;
genvar op;
generate
for(op = 0; op < num_routers; op = op + 1) //variable name is "op" but it's really the router id
begin:ops
wire [0:channel_width-1] channel_out;
assign channel_out = ejection_channels[op*channel_width:
(op+1)*channel_width-1];
wire [0:flit_ctrl_width-1] flit_ctrl_out;
assign flit_ctrl_out
= channel_out[link_ctrl_width:link_ctrl_width+flit_ctrl_width-1];
assign flit_valid_out_op[op] = flit_ctrl_out[0];
wire [0:channel_width-1] channel_dly;
c_shift_reg
#(.width(channel_width),
.depth(num_channel_stages),
.reset_type(reset_type))
channel_dly_sr
(.clk(clk),
.reset(reset),
.active(1'b1),
.data_in(channel_out),
.data_out(channel_dly));
wire [0:flow_ctrl_width-1] flow_ctrl;
wire fs_error;
flit_sink
#(.initial_seed(initial_seed + num_routers + op),
.consume_rate(consume_rate),
.buffer_size(buffer_size),
.num_vcs(num_vcs),
.packet_format(packet_format),
.flow_ctrl_type(flow_ctrl_type),
.max_payload_length(max_payload_length),
.min_payload_length(min_payload_length),
.route_info_width(route_info_width),
.enable_link_pm(enable_link_pm),
.flit_data_width(flit_data_width),
.fb_regfile_type(fb_regfile_type),
.fb_mgmt_type(fb_mgmt_type),
.atomic_vc_allocation(atomic_vc_allocation),
.reset_type(reset_type))
fs
(.clk(clk),
.reset(reset),
.channel(channel_dly),
.flow_ctrl(flow_ctrl),
.error(fs_error));
assign fs_error_op[op] = fs_error;
wire [0:flow_ctrl_width-1] flow_ctrl_dly;
c_shift_reg
#(.width(flow_ctrl_width),
.depth(num_channel_stages),
.reset_type(reset_type))
flow_ctrl_in_sr
(.clk(clk),
.reset(reset),
.active(1'b1),
.data_in(flow_ctrl),
.data_out(flow_ctrl_dly));
assign ejection_flow_ctrl[op*flow_ctrl_width:(op+1)*flow_ctrl_width-1]
= flow_ctrl_dly;
assign cred_valid_in_op[op] = flow_ctrl_dly[0];
end
endgenerate
wire [0:2] tb_errors;
assign tb_errors = {|ps_error_ip, |fs_error_op, |rchk_error};
wire tb_error;
assign tb_error = |tb_errors;
wire [0:31] in_flits_s, in_flits_q;
assign in_flits_s = in_flits_q + pop_count(flit_valid_in_ip);
c_dff
#(.width(32),
.reset_type(reset_type))
in_flitsq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(in_flits_s),
.q(in_flits_q));
wire [0:31] in_flits;
assign in_flits = in_flits_s;
wire [0:31] in_creds_s, in_creds_q;
assign in_creds_s = in_creds_q + pop_count(cred_valid_out_ip);
c_dff
#(.width(32),
.reset_type(reset_type))
in_credsq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(in_creds_s),
.q(in_creds_q));
wire [0:31] in_creds;
assign in_creds = in_creds_q;
wire [0:31] out_flits_s, out_flits_q;
assign out_flits_s = out_flits_q + pop_count(flit_valid_out_op);
c_dff
#(.width(32),
.reset_type(reset_type))
out_flitsq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(out_flits_s),
.q(out_flits_q));
wire [0:31] out_flits;
assign out_flits = out_flits_s;
wire [0:31] out_creds_s, out_creds_q;
assign out_creds_s = out_creds_q + pop_count(cred_valid_in_op);
c_dff
#(.width(32),
.reset_type(reset_type))
out_credsq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(out_creds_s),
.q(out_creds_q));
wire [0:31] out_creds;
assign out_creds = out_creds_q;
reg count_en;
wire [0:31] count_in_flits_s, count_in_flits_q;
assign count_in_flits_s
= count_en ?
count_in_flits_q + pop_count(flit_valid_in_ip) :
count_in_flits_q;
c_dff
#(.width(32),
.reset_type(reset_type))
count_in_flitsq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(count_in_flits_s),
.q(count_in_flits_q));
wire [0:31] count_in_flits;
assign count_in_flits = count_in_flits_s;
wire [0:31] count_out_flits_s, count_out_flits_q;
assign count_out_flits_s
= count_en ?
count_out_flits_q + pop_count(flit_valid_out_op) :
count_out_flits_q;
c_dff
#(.width(32),
.reset_type(reset_type))
count_out_flitsq
(.clk(clk),
.reset(reset),
.active(1'b1),
.d(count_out_flits_s),
.q(count_out_flits_q));
wire [0:31] count_out_flits;
assign count_out_flits = count_out_flits_s;
reg clk_en;
always
begin
clk <= clk_en;
#(Tclk/2);
clk <= 1'b0;
#(Tclk/2);
end
always @(posedge clk)
begin
if(|rtr_error)
begin
$display("internal error detected, cyc=%d", $time);
$stop;
end
if(tb_error)
begin
$display("external error detected, cyc=%d", $time);
$stop;
end
end
integer cycles;
integer d;
initial
begin
reset = 1'b0;
clk_en = 1'b0;
run = 1'b0;
count_en = 1'b0;
cycles = 0;
#(Tclk);
#(Tclk/2);
reset = 1'b1;
#(Tclk);
reset = 1'b0;
#(Tclk);
clk_en = 1'b1;
#(Tclk/2);
$display("warming up...");
run = 1'b1;
while(cycles < warmup_time)
begin
cycles = cycles + 1;
#(Tclk);
end
$display("measuring...");
count_en = 1'b1;
while(cycles < warmup_time + measure_time)
begin
cycles = cycles + 1;
#(Tclk);
end
count_en = 1'b0;
$display("measured %d cycles", measure_time);
$display("%d flits in, %d flits out", count_in_flits, count_out_flits);
$display("cooling down...");
run = 1'b0;
while((in_flits > out_flits) || (in_flits > in_creds))
begin
cycles = cycles + 1;
#(Tclk);
end
#(Tclk*10);
$display("simulation ended after %d cycles", cycles);
$display("%d flits received, %d flits sent", in_flits, out_flits);
$finish;
end
endmodule
|
// -*- Mode: Verilog -*-
// Filename : wb_dsp_top.v
// Description : Top level module for wishbone DSP
// Author : Philip Tracton
// Created On : Wed Dec 2 12:53:51 2015
// Last Modified By: Philip Tracton
// Last Modified On: Wed Dec 2 12:53:51 2015
// Update Count : 0
// Status : Unknown, Use with caution!
module wb_dsp_top (/*AUTOARG*/
// Outputs
interrupt, wb_master_adr_o, wb_master_dat_o, wb_master_sel_o,
wb_master_we_o, wb_master_cyc_o, wb_master_stb_o, wb_master_cti_o,
wb_master_bte_o, wb_slave_dat_o, wb_slave_ack_o, wb_slave_err_o,
wb_slave_rty_o,
// Inputs
wb_clk, wb_rst, begin_equation, wb_master_dat_i, wb_master_ack_i,
wb_master_err_i, wb_master_rty_i, wb_slave_adr_i, wb_slave_dat_i,
wb_slave_sel_i, wb_slave_we_i, wb_slave_cyc_i, wb_slave_stb_i,
wb_slave_cti_i, wb_slave_bte_i
) ;
parameter master_dw = 32;
parameter master_aw = 32;
parameter slave_dw = 32;
parameter slave_aw = 8;
//
// Common Interface
//
input wb_clk;
input wb_rst;
output wire interrupt;
input [3:0] begin_equation;
//
// Master Interface
//
output wire [master_aw-1:0] wb_master_adr_o;
output wire [master_dw-1:0] wb_master_dat_o;
output wire [3:0] wb_master_sel_o;
output wire wb_master_we_o;
output wire wb_master_cyc_o;
output wire wb_master_stb_o;
output wire [2:0] wb_master_cti_o;
output wire [1:0] wb_master_bte_o;
input [master_dw-1:0] wb_master_dat_i;
input wb_master_ack_i;
input wb_master_err_i;
input wb_master_rty_i;
//
// Slave Interface
//
input [slave_aw-1:0] wb_slave_adr_i;
input [slave_dw-1:0] wb_slave_dat_i;
input [3:0] wb_slave_sel_i;
input wb_slave_we_i;
input wb_slave_cyc_i;
input wb_slave_stb_i;
input [2:0] wb_slave_cti_i;
input [1:0] wb_slave_bte_i;
output wire [slave_dw-1:0] wb_slave_dat_o;
output wire wb_slave_ack_o;
output wire wb_slave_err_o;
output wire wb_slave_rty_o;
wire [slave_dw-1:0] equation0_address_reg;
wire [slave_dw-1:0] equation1_address_reg;
wire [slave_dw-1:0] equation2_address_reg;
wire [slave_dw-1:0] equation3_address_reg;
wire [slave_dw-1:0] control_reg;
wire [slave_dw-1:0] status_reg;
wire [7:0] equation_enable;
wire equation_done = 0;
wire [master_dw-1:0] master_data_rd;
wire [master_dw-1:0] sm_dat_i;
wire [master_dw-1:0] base_address;
wire [master_aw-1:0] sm_address;
wire [3:0] sm_selection;
wire sm_write;
wire [master_dw-1:0] sm_data_wr;
wire sm_start;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [master_aw-1:0] eq_adr_o; // From equations of wb_dsp_equations_top.v
wire [1:0] eq_bte_o; // From equations of wb_dsp_equations_top.v
wire [2:0] eq_cti_o; // From equations of wb_dsp_equations_top.v
wire eq_cyc_o; // From equations of wb_dsp_equations_top.v
wire [master_dw-1:0] eq_dat_o; // From equations of wb_dsp_equations_top.v
wire [3:0] eq_sel_o; // From equations of wb_dsp_equations_top.v
wire eq_stb_o; // From equations of wb_dsp_equations_top.v
wire eq_we_o; // From equations of wb_dsp_equations_top.v
// End of automatics
/*AUTOREG*/
//
// Single bus master interface the Algorithm State Machine and all equations will use
// for access data in SRAM
//
wb_master_interface bus_master(
// Outputs
.wb_adr_o (wb_master_adr_o[master_aw-1:0]),
.wb_dat_o (wb_master_dat_o[master_dw-1:0]),
.wb_sel_o (wb_master_sel_o[3:0]),
.wb_we_o (wb_master_we_o),
.wb_cyc_o (wb_master_cyc_o),
.wb_stb_o (wb_master_stb_o),
.wb_cti_o (wb_master_cti_o[2:0]),
.wb_bte_o (wb_master_bte_o[1:0]),
.data_rd (master_data_rd[master_dw-1:0]),
.active (active),
// Inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_dat_i (sm_dat_i[master_dw-1:0]),
.wb_ack_i (wb_master_ack_i),
.wb_err_i (wb_master_err_i),
.wb_rty_i (wb_master_rty_i),
.start (sm_start),
.address (sm_address[master_aw-1:0]),
.selection (sm_selection[3:0]),
.write (sm_write),
.data_wr (sm_data_wr[master_dw-1:0]));
wb_dsp_slave_registers #(.aw(slave_aw), .dw(slave_dw))
slave_registers
(
// Outputs
.interrupt (interrupt),
.wb_dat_o (wb_slave_dat_o[slave_dw-1:0]),
.wb_ack_o (wb_slave_ack_o),
.wb_err_o (wb_slave_err_o),
.wb_rty_o (wb_slave_rty_o),
.equation0_address_reg (equation0_address_reg[slave_dw-1:0]),
.equation1_address_reg (equation1_address_reg[slave_dw-1:0]),
.equation2_address_reg (equation2_address_reg[slave_dw-1:0]),
.equation3_address_reg (equation3_address_reg[slave_dw-1:0]),
.control_reg (control_reg[slave_dw-1:0]),
// Inputs
.status_reg (status_reg),
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_adr_i (wb_slave_adr_i[slave_aw-1:0]),
.wb_dat_i (wb_slave_dat_i[slave_dw-1:0]),
.wb_sel_i (wb_slave_sel_i[3:0]),
.wb_we_i (wb_slave_we_i),
.wb_cyc_i (wb_slave_cyc_i),
.wb_stb_i (wb_slave_stb_i),
.wb_cti_i (wb_slave_cti_i[2:0]),
.wb_bte_i (wb_slave_bte_i[1:0])
);
wire alg_start;
wire [master_aw-1:0] alg_address;
wire [3:0] alg_selection;
wire alg_write;
wire [master_dw-1:0] alg_data_wr;
wb_dsp_algorithm_sm #(.aw(master_aw), .dw(master_dw))
algorithm(
// Outputs
.alg_start (alg_start),
.alg_address (alg_address[master_aw-1:0]),
.alg_selection (alg_selection[3:0]),
.alg_write (alg_write),
.alg_data_wr (alg_data_wr[master_dw-1:0]),
.status_reg (status_reg[master_dw-1:0]),
.equation_enable (equation_enable[7:0]),
.base_address (base_address[master_aw-1:0]),
// Inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.alg_data_rd (master_data_rd[master_dw-1:0]),
.begin_equation (begin_equation[3:0]),
.equation0_address_reg (equation0_address_reg[master_dw-1:0]),
.equation1_address_reg (equation1_address_reg[master_dw-1:0]),
.equation2_address_reg (equation2_address_reg[master_dw-1:0]),
.equation3_address_reg (equation3_address_reg[master_dw-1:0]),
.control_reg (control_reg[master_dw-1:0]),
.equation_done (equation_done),
.active (active));
wb_dsp_equations_top #(.aw(master_aw), .dw(master_dw))
equations(
// Outputs
.eq_adr_o (eq_adr_o[master_aw-1:0]),
.eq_dat_o (eq_dat_o[master_dw-1:0]),
.eq_sel_o (eq_sel_o[3:0]),
.eq_we_o (eq_we_o),
.eq_cyc_o (eq_cyc_o),
.eq_stb_o (eq_stb_o),
.eq_cti_o (eq_cti_o[2:0]),
.eq_bte_o (eq_bte_o[1:0]),
.equation_done (equation_done),
// Inputs
.wb_clk (wb_clk),
.wb_rst (wb_rst),
.wb_dat_i (master_data_rd[master_dw-1:0]),
.wb_ack_i (wb_ack_i),
.wb_err_i (wb_err_i),
.wb_rty_i (wb_rty_i),
.base_address (base_address[master_aw-1:0]),
.equation_enable (equation_enable[7:0]));
/****************************************************************************
Put all the equation output busses together. This is why they are required
to drive 0's on all signal when not active!
****************************************************************************/
assign sm_address = alg_address | eq_adr_o;
assign sm_dat_i = alg_data_wr | eq_dat_o;
assign sm_selection = alg_selection | eq_sel_o;
assign sm_write = alg_write | eq_we_o;
endmodule // wb_dsp_top
|
/*
Distributed under the MIT license.
Copyright (c) 2015 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/*
* Author: Dave McCoy ([email protected])
* Description:
* Tranlates data from a Ping Pong FIFO to an AXI Stream
*
* Changes: Who? What?
* 04/06/2017: DFM Initial check in.
* 04/06/2017: DFM Added count so that the 'last' will not be strobed until
* all is sent.
*/
`timescale 1ps / 1ps
module adapter_ppfifo_2_axi_stream #(
parameter DATA_WIDTH = 24,
parameter STROBE_WIDTH = DATA_WIDTH / 8,
parameter USE_KEEP = 0
)(
input rst,
//Ping Poing FIFO Read Interface
input i_ppfifo_rdy,
output reg o_ppfifo_act,
input [23:0] i_ppfifo_size,
input [(DATA_WIDTH + 1) - 1:0] i_ppfifo_data,
output o_ppfifo_stb,
//AXI Stream Output
input i_axi_clk,
output [3:0] o_axi_user,
input i_axi_ready,
output [DATA_WIDTH - 1:0] o_axi_data,
output o_axi_last,
output reg o_axi_valid,
output [31:0] o_debug
);
//local parameters
localparam IDLE = 0;
localparam READY = 1;
localparam RELEASE = 2;
//registes/wires
reg [3:0] state;
reg [23:0] r_count;
//submodules
//asynchronous logic
assign o_axi_data = i_ppfifo_data[DATA_WIDTH - 1: 0];
assign o_ppfifo_stb = (i_axi_ready & o_axi_valid);
assign o_axi_user[0] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH] : 1'b0;
assign o_axi_user[3:1] = 3'h0;
assign o_axi_last = ((r_count + 1) >= i_ppfifo_size) & o_ppfifo_act & o_axi_valid;
//synchronous logic
assign o_debug[3:0] = state;
assign o_debug[4] = (r_count < i_ppfifo_size) ? i_ppfifo_data[DATA_WIDTH]: 1'b0;
assign o_debug[5] = o_ppfifo_act;
assign o_debug[6] = i_ppfifo_rdy;
assign o_debug[7] = (r_count > 0);
assign o_debug[8] = (i_ppfifo_size > 0);
assign o_debug[9] = (r_count == i_ppfifo_size);
assign o_debug[15:10] = 0;
assign o_debug[23:16] = r_count[7:0];
assign o_debug[31:24] = 0;
always @ (posedge i_axi_clk) begin
o_axi_valid <= 0;
if (rst) begin
state <= IDLE;
o_ppfifo_act <= 0;
r_count <= 0;
end
else begin
case (state)
IDLE: begin
o_ppfifo_act <= 0;
if (i_ppfifo_rdy && !o_ppfifo_act) begin
r_count <= 0;
o_ppfifo_act <= 1;
state <= READY;
end
end
READY: begin
if (r_count < i_ppfifo_size) begin
o_axi_valid <= 1;
if (i_axi_ready && o_axi_valid) begin
r_count <= r_count + 1;
if ((r_count + 1) >= i_ppfifo_size) begin
o_axi_valid <= 0;
end
end
end
else begin
o_ppfifo_act <= 0;
state <= RELEASE;
end
end
RELEASE: begin
state <= IDLE;
end
default: begin
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O211A_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O211A_FUNCTIONAL_PP_V
/**
* o211a: 2-input OR into first input of 3-input AND.
*
* X = ((A1 | A2) & B1 & C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o211a (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire or0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
or or0 (or0_out , A2, A1 );
and and0 (and0_out_X , or0_out, B1, C1 );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O211A_FUNCTIONAL_PP_V |
module wasca (
altpll_0_areset_conduit_export,
altpll_0_locked_conduit_export,
altpll_0_phasedone_conduit_export,
clk_clk,
clock_116_mhz_clk,
external_sdram_controller_wire_addr,
external_sdram_controller_wire_ba,
external_sdram_controller_wire_cas_n,
external_sdram_controller_wire_cke,
external_sdram_controller_wire_cs_n,
external_sdram_controller_wire_dq,
external_sdram_controller_wire_dqm,
external_sdram_controller_wire_ras_n,
external_sdram_controller_wire_we_n,
pio_0_external_connection_export,
sd_mmc_controller_0_sd_card_io_sd_clk_o_pad,
sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i,
sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o,
sd_mmc_controller_0_sd_card_io_sd_cmd_out_o,
sd_mmc_controller_0_sd_card_io_sd_dat_dat_i,
sd_mmc_controller_0_sd_card_io_sd_dat_oe_o,
sd_mmc_controller_0_sd_card_io_sd_dat_out_o,
sega_saturn_abus_slave_0_abus_address,
sega_saturn_abus_slave_0_abus_chipselect,
sega_saturn_abus_slave_0_abus_read,
sega_saturn_abus_slave_0_abus_write,
sega_saturn_abus_slave_0_abus_functioncode,
sega_saturn_abus_slave_0_abus_timing,
sega_saturn_abus_slave_0_abus_waitrequest,
sega_saturn_abus_slave_0_abus_addressstrobe,
sega_saturn_abus_slave_0_abus_interrupt,
sega_saturn_abus_slave_0_abus_addressdata,
sega_saturn_abus_slave_0_abus_direction,
sega_saturn_abus_slave_0_abus_muxing,
sega_saturn_abus_slave_0_abus_disableout,
sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset,
uart_0_external_connection_rxd,
uart_0_external_connection_txd);
input altpll_0_areset_conduit_export;
output altpll_0_locked_conduit_export;
output altpll_0_phasedone_conduit_export;
input clk_clk;
output clock_116_mhz_clk;
output [12:0] external_sdram_controller_wire_addr;
output [1:0] external_sdram_controller_wire_ba;
output external_sdram_controller_wire_cas_n;
output external_sdram_controller_wire_cke;
output external_sdram_controller_wire_cs_n;
inout [15:0] external_sdram_controller_wire_dq;
output [1:0] external_sdram_controller_wire_dqm;
output external_sdram_controller_wire_ras_n;
output external_sdram_controller_wire_we_n;
inout [3:0] pio_0_external_connection_export;
output sd_mmc_controller_0_sd_card_io_sd_clk_o_pad;
input sd_mmc_controller_0_sd_card_io_sd_cmd_dat_i;
output sd_mmc_controller_0_sd_card_io_sd_cmd_oe_o;
output sd_mmc_controller_0_sd_card_io_sd_cmd_out_o;
input [3:0] sd_mmc_controller_0_sd_card_io_sd_dat_dat_i;
output sd_mmc_controller_0_sd_card_io_sd_dat_oe_o;
output [3:0] sd_mmc_controller_0_sd_card_io_sd_dat_out_o;
input [9:0] sega_saturn_abus_slave_0_abus_address;
input [2:0] sega_saturn_abus_slave_0_abus_chipselect;
input sega_saturn_abus_slave_0_abus_read;
input [1:0] sega_saturn_abus_slave_0_abus_write;
input [1:0] sega_saturn_abus_slave_0_abus_functioncode;
input [2:0] sega_saturn_abus_slave_0_abus_timing;
output sega_saturn_abus_slave_0_abus_waitrequest;
input sega_saturn_abus_slave_0_abus_addressstrobe;
output sega_saturn_abus_slave_0_abus_interrupt;
inout [15:0] sega_saturn_abus_slave_0_abus_addressdata;
output sega_saturn_abus_slave_0_abus_direction;
output [1:0] sega_saturn_abus_slave_0_abus_muxing;
output sega_saturn_abus_slave_0_abus_disableout;
input sega_saturn_abus_slave_0_conduit_saturn_reset_saturn_reset;
input uart_0_external_connection_rxd;
output uart_0_external_connection_txd;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Thu Sep 14 10:23:02 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ vio_0_stub.v
// Design : vio_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "vio,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe_in0, probe_in1, probe_in2, probe_in3,
probe_out0, probe_out1)
/* synthesis syn_black_box black_box_pad_pin="clk,probe_in0[0:0],probe_in1[0:0],probe_in2[0:0],probe_in3[0:0],probe_out0[0:0],probe_out1[0:0]" */;
input clk;
input [0:0]probe_in0;
input [0:0]probe_in1;
input [0:0]probe_in2;
input [0:0]probe_in3;
output [0:0]probe_out0;
output [0:0]probe_out1;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DLRTP_BLACKBOX_V
`define SKY130_FD_SC_LS__DLRTP_BLACKBOX_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DLRTP_BLACKBOX_V
|
(*
Copyright 2014 Cornell University
This file is part of VPrl (the Verified Nuprl project).
VPrl is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
VPrl is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with VPrl. Ifnot, see <http://www.gnu.org/licenses/>.
Website: http://nuprl.org/html/verification/
Authors: Abhishek Anand & Vincent Rahli
*)
Require Export computation_preserve3.
Lemma get_utokens_sub_sub_keep_first_subset {o} :
forall (sub : @Sub o) l1 l2,
subset l1 l2
-> subset (get_utokens_sub (sub_keep_first sub l1))
(get_utokens_sub (sub_keep_first sub l2)).
Proof.
introv s i.
allunfold @get_utokens_sub.
allrw lin_flat_map; exrepnd.
eexists; dands; eauto.
allrw @in_range_iff; exrepnd.
exists v.
allrw @in_sub_keep_first; repnd; dands; auto.
Qed.
Lemma sub_keep_first_eq_nil {o} :
forall (sub : @Sub o) vs,
disjoint vs (dom_sub sub)
-> sub_keep_first sub vs = [].
Proof.
induction sub; introv disj; allsimpl; auto.
destruct a as [v t]; allsimpl; allrw disjoint_cons_r; repnd.
boolvar; tcsp.
Qed.
Lemma implies_subset_get_utokens_sub_sub_keep_first_flat_map {o} :
forall {T} (l : list T) f atoms (sub : @Sub o),
(forall x, LIn x l -> subset (get_utokens_sub (sub_keep_first sub (f x))) atoms)
-> subset (get_utokens_sub (sub_keep_first sub (flat_map f l))) atoms.
Proof.
introv imp i.
allunfold @get_utokens_sub.
allrw lin_flat_map; exrepnd.
allrw @in_range_iff; exrepnd.
allrw @in_sub_keep_first; repnd.
allrw lin_flat_map; exrepnd.
pose proof (imp x1 i2) as h.
apply h.
apply lin_flat_map.
eexists; dands; eauto.
apply in_range_iff.
exists v.
apply in_sub_keep_first; dands; auto.
Qed.
Lemma get_utokens_sub_sub_keep_first_subset_get_utokens_step_seq_lsubst_aux {o} :
forall (t : @NTerm o) sub,
subset
(get_utokens_sub (sub_keep_first sub (free_vars t)))
(get_utokens_step_seq (lsubst_aux t sub)).
Proof.
nterm_ind1s t as [v|f ind|op bs ind] Case; introv; allsimpl.
- Case "vterm".
remember (sub_find sub v) as sf; symmetry in Heqsf; destruct sf; simpl.
+ introv i.
unfold get_utokens_sub in i; rw lin_flat_map in i; exrepnd.
allrw @in_range_iff; exrepnd.
allrw @in_sub_keep_first; repnd.
allsimpl; repndors; subst; tcsp.
rw i1 in Heqsf; ginv.
apply subset_get_utokens_get_utokens_step_seq in i0; auto.
+ rw @sub_keep_first_eq_nil; autorewrite with slow; auto.
introv i j; allsimpl; repndors; subst; tcsp.
apply sub_find_none2 in Heqsf; sp.
- Case "sterm".
rw @sub_keep_first_eq_nil; autorewrite with slow; eauto 3 with slow.
- Case "oterm".
allrw @fold_get_utokens_step_seq_bterms_seq.
allrw @fold_get_utokens_step_seq_op_seq.
apply implies_subset_get_utokens_sub_sub_keep_first_flat_map.
introv i.
destruct x as [l t]; allsimpl.
allrw flat_map_map; unfold compose.
apply subset_app_l.
apply subset_app_r.
eapply subset_trans;[|apply subsetSingleFlatMap;eauto].
simpl.
eapply subset_trans;[|eapply ind;eauto 3 with slow].
introv j.
allunfold @get_utokens_sub.
allrw lin_flat_map; exrepnd.
allrw @in_range_iff; exrepnd.
allrw @in_sub_keep_first; repnd.
allrw in_remove_nvars; repnd.
eexists; dands; eauto.
apply in_range_iff.
exists v.
apply in_sub_keep_first; dands; auto.
rw @sub_find_sub_filter_eq.
boolvar; tcsp.
Qed.
Lemma compute_step_lsubst_aux {o} :
forall lib (t u : @NTerm o) sub,
nt_wf t
-> cl_sub sub
-> subvars (free_vars t) (dom_sub sub)
-> compute_step lib t = csuccess u
-> {v : NTerm
& compute_step lib (lsubst_aux t sub) = csuccess v
# alpha_eq v (lsubst_aux u sub)}.
Proof.
nterm_ind1s t as [v|f ind|op bs ind] Case; introv wf cl sv comp; ginv.
- Case "sterm".
allsimpl.
csunf comp; allsimpl; ginv.
csunf; simpl; eexists; dands; eauto.
- Case "oterm".
dopid op as [can|ncan|exc|abs] SCase.
+ SCase "Can".
csunf comp; allsimpl; ginv.
csunf; simpl; eexists; dands; eauto.
+ SCase "NCan".
destruct bs; try (complete (allsimpl; ginv)).
destruct b as [l t]; try (complete (allsimpl; ginv)).
destruct l; try (complete (allsimpl; ginv)).
{ destruct t as [v|f|op bts]; try (complete (allsimpl; ginv)).
{ allsimpl.
dopid_noncan ncan SSCase; try (complete (csunf comp; allsimpl; ginv)).
- SSCase "NApply".
csunf comp; allsimpl.
apply compute_step_seq_apply_success in comp; exrepnd; subst; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw @sub_filter_nil_r.
csunf; simpl.
eexists; dands; eauto.
- SSCase "NEApply".
csunf comp; allsimpl.
apply compute_step_eapply_success in comp; exrepnd; subst; allsimpl.
allrw remove_nvars_nil_l.
repndors; exrepnd; subst; allsimpl.
+ apply compute_step_eapply2_success in comp1; exrepnd; subst; allsimpl.
allrw app_nil_r.
repndors; exrepnd; subst; ginv; allsimpl; GC.
csunf; simpl.
dcwf h; simpl.
boolvar; try omega.
rw Znat.Nat2Z.id.
eexists; dands; eauto.
allrw @nt_wf_eapply_iff; exrepnd; allunfold @nobnd; ginv.
allrw @nt_wf_sterm_iff.
pose proof (wf2 n) as q; repnd.
rw @lsubst_aux_trivial_cl_term2; auto.
+ allrw @sub_filter_nil_r.
apply isexc_implies2 in comp0; exrepnd; subst; allsimpl.
csunf; simpl.
dcwf h; simpl.
eexists; dands; eauto.
+ allrw @sub_filter_nil_r.
fold_terms.
pose proof (ind arg2 arg2 []) as h; repeat (autodimp h hyp); eauto 3 with slow; clear ind.
pose proof (h x sub) as ih; clear h.
allrw @nt_wf_eapply_iff; exrepnd; allunfold @nobnd; ginv.
allrw @nt_wf_sterm_iff.
allsimpl; allrw app_nil_r.
repeat (autodimp ih hyp); exrepnd.
fold_terms; unfold mk_eapply.
rw @compute_step_eapply_iscan_isnoncan_like; simpl; eauto 3 with slow.
rw ih1; eexists; dands; eauto.
apply implies_alpha_eq_mk_eapply; eauto 3 with slow.
- SSCase "NFix".
csunf comp; allsimpl.
apply compute_step_fix_success in comp; repnd; subst; allsimpl.
csunf; simpl.
eexists; dands; eauto.
- SSCase "NCbv".
csunf comp; allsimpl.
apply compute_step_cbv_success in comp; exrepnd; subst; allsimpl.
allrw app_nil_r.
csunf; simpl; eexists; dands; eauto.
unfold apply_bterm; simpl; allrw @fold_subst.
pose proof (simple_lsubst_lsubst_aux_sub_aeq x [(v,sterm f)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; eauto 3 with slow.
unfold covered; simpl; auto.
- SSCase "NTryCatch".
csunf comp; allsimpl.
apply compute_step_try_success in comp; exrepnd; subst; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r.
allrw @sub_filter_nil_r.
csunf; simpl; eexists; dands; eauto;[].
apply implies_alpha_eq_mk_atom_eq; eauto 3 with slow.
rw @sub_find_sub_filter; simpl; tcsp.
- SSCase "NCanTest".
csunf comp; allsimpl.
apply nt_wf_NCanTest in wf; exrepnd; allunfold @nobnd; ginv; allsimpl.
autorewrite with slow in *.
allrw subvars_app_l; repnd.
csunf; simpl.
eexists; dands; eauto.
}
dopid op as [can2|ncan2|exc2|abs2] SSCase.
* SSCase "Can".
dopid_noncan ncan SSSCase.
{ SSSCase "NApply".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_apply_success in comp; repndors; exrepnd; subst; fold_terms.
{ simpl; unfold apply_bterm; simpl.
allrw @sub_filter_nil_r.
allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
eexists;dands;[complete eauto|].
pose proof (simple_lsubst_lsubst_aux_sub_aeq b [(v,arg)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil. }
{ allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r.
allrw @sub_filter_nil_r.
eexists; dands; eauto. }
}
{ SSSCase "NEApply".
csunf comp; allsimpl.
apply compute_step_eapply_success in comp; exrepnd; subst; allsimpl.
allrw remove_nvars_nil_l.
repndors; exrepnd; allsimpl; subst; autorewrite with slow in *.
- apply compute_step_eapply2_success in comp1; repnd; subst; allsimpl.
allrw app_nil_r.
repndors; exrepnd; subst; allsimpl; ginv;[].
unfold mk_lam in comp3; ginv; allsimpl; autorewrite with slow in *.
fold_terms; unfold mk_eapply.
rw @compute_step_eapply_lam_iscan; eauto 3 with slow.
eexists; dands; eauto.
unfold apply_bterm; simpl; allrw @fold_subst.
allrw subvars_app_l; repnd.
pose proof (simple_lsubst_lsubst_aux_sub_aeq b [(v,arg2)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; eauto 3 with slow.
- fold_terms; unfold mk_eapply.
rw @compute_step_eapply_iscan_isexc; simpl; eauto 3 with slow.
eapply eapply_wf_def_len_implies;[|exact comp2].
allrw map_map; unfold compose.
apply eq_maps; introv i; destruct x; unfold num_bvars; simpl; auto.
- allrw @sub_filter_nil_r.
pose proof (ind arg2 arg2 []) as h; clear ind.
repeat (autodimp h hyp); eauto 3 with slow.
allrw @nt_wf_eapply_iff; exrepnd; subst; allsimpl; allunfold @nobnd; ginv.
allsimpl; allrw app_nil_r.
allrw subvars_app_l; repnd.
pose proof (h x sub) as ih; clear h.
repeat (autodimp ih hyp); eauto 3 with slow.
exrepnd.
fold_terms; unfold mk_eapply.
rw @compute_step_eapply_iscan_isnoncan_like; simpl; eauto 3 with slow.
{ rw ih1; eexists; dands; eauto.
allrw @sub_filter_nil_r.
fold_terms.
apply implies_alpha_eq_mk_eapply; auto. }
{ eapply eapply_wf_def_len_implies;[|exact comp2].
allrw map_map; unfold compose.
apply eq_maps; introv i; destruct x0; unfold num_bvars; simpl; auto. }
}
{ SSSCase "NApseq".
clear ind; csunf comp; csunf; allsimpl.
apply compute_step_apseq_success in comp; exrepnd; subst; allsimpl.
boolvar; try omega.
rw @Znat.Nat2Z.id.
eexists; dands; eauto.
}
{ SSSCase "NFix".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_fix_success in comp; repnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
eexists;dands;[complete eauto|];auto. }
{ SSSCase "NSpread".
clear ind; csunf comp; simpl in comp.
apply compute_step_spread_success in comp; exrepnd; subst; allsimpl; fold_terms.
csunf; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
eexists;dands;[complete eauto|].
pose proof (simple_lsubst_lsubst_aux_sub_aeq arg [(va,a),(vb,b)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil. }
{ SSSCase "NDsup".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_dsup_success in comp; exrepnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
eexists;dands;[complete eauto|].
pose proof (simple_lsubst_lsubst_aux_sub_aeq arg [(va,a),(vb,b)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil. }
{ SSSCase "NDecide".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_decide_success in comp; exrepnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
dorn comp0; repnd; subst; allsimpl.
- eexists;dands;[complete eauto|].
pose proof (simple_lsubst_lsubst_aux_sub_aeq t1 [(v1,d)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil.
- eexists;dands;[complete eauto|].
pose proof (simple_lsubst_lsubst_aux_sub_aeq t2 [(v2,d)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil. }
{ SSSCase "NCbv".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_cbv_success in comp; exrepnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
eexists;dands;[complete eauto|].
pose proof (simple_lsubst_lsubst_aux_sub_aeq x [(v,oterm (Can can2) bts)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil. }
{ SSSCase "NSleep".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_sleep_success in comp; exrepnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
unfold compute_step_sleep; simpl.
eexists;dands;[complete eauto|]; auto. }
{ SSSCase "NTUni".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_tuni_success in comp; exrepnd; subst; allsimpl; fold_terms.
unfold compute_step_tuni; simpl.
boolvar; try omega.
eexists;dands;[complete eauto|]; auto.
rw Znat.Nat2Z.id; auto. }
{ SSSCase "NMinus".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_minus_success in comp; exrepnd; subst; allsimpl; fold_terms.
eexists; dands; eauto.
unfold compute_step_minus; simpl; auto. }
{ SSSCase "NFresh".
csunf comp; allsimpl; ginv. }
{ SSSCase "NTryCatch".
clear ind; csunf comp; csunf; simpl in comp.
apply compute_step_try_success in comp; exrepnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
allrw subvars_app_l; allrw subvars_remove_nvars; repnd.
allrw @sub_find_sub_filter_eq; allrw memvar_singleton; boolvar.
eexists;dands; eauto. }
{ SSSCase "NParallel".
csunf comp; allsimpl.
apply compute_step_parallel_success in comp; subst; allsimpl; fold_terms.
exists (@mk_axiom o); dands; auto. }
{ SSSCase "NCompOp".
destruct bs; try (complete (csunf comp; allsimpl; dcwf h));[].
destruct b as [l t].
destruct l; destruct t as [v|f|op bs2]; try (complete (csunf comp; allsimpl; dcwf h));[].
dopid op as [can3|ncan3|exc3|abs3] SSSSCase.
- SSSSCase "Can".
csunf comp; csunf; simpl in comp; boolvar; tcsp; ginv.
dcwf h;[].
apply compute_step_compop_success_can_can in comp; exrepnd; subst; allsimpl.
dcwf h;[].
boolvar; tcsp.
repndors; exrepnd; subst;
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r;
allrw @get_param_from_cop_some; subst; allsimpl;
unfold compute_step_comp; simpl;
allrw @get_param_from_cop_pk2can;
eexists; dands; eauto;
boolvar; tcsp.
- SSSSCase "NCan".
rw @compute_step_ncompop_ncan2 in comp; boolvar; tcsp; ginv.
dcwf h;allsimpl;[].
remember (compute_step lib (oterm (NCan ncan3) bs2)) as comp1;
symmetry in Heqcomp1; destruct comp1; ginv.
simpl in sv; allrw remove_nvars_nil_l; allrw subvars_app_l; repnd.
allrw @nt_wf_NCompOp; exrepnd; allunfold @nobnd; ginv.
allsimpl; allrw @sub_filter_nil_r; allrw remove_nvars_nil_l; allrw app_nil_r.
eapply (ind (oterm (NCan ncan3) bs2) (oterm (NCan ncan3) bs2)) in Heqcomp1;eauto 3 with slow;exrepnd;[].
allsimpl; rw @compute_step_ncompop_ncan2; boolvar; tcsp.
allrw @sub_filter_nil_r.
rw Heqcomp1.
dcwf h; allsimpl;[].
eexists;dands;[complete eauto|].
apply alpha_eq_oterm_snd_subterm.
apply alphaeqbt_nilv2; auto.
- SSSSCase "Exc".
csunf comp; csunf; allsimpl.
repeat (dcwf h);[].
boolvar; tcsp; ginv.
allsimpl; ginv; allsimpl; allrw remove_nvars_nil_l;
allrw subvars_app_l; allrw @sub_filter_nil_r; repnd.
eexists;dands;[complete eauto|]; auto.
- SSSSCase "Abs".
allsimpl.
csunf comp; csunf; allsimpl; boolvar; tcsp; ginv.
repeat (dcwf h);[].
allunfold @on_success.
allrw remove_nvars_nil_l; allrw @sub_filter_nil_r.
allrw subvars_app_l; repnd.
csunf comp; csunf; allsimpl.
remember (compute_step_lib lib abs3 bs2) as csl;
symmetry in Heqcsl; destruct csl; ginv; simpl;
allrw @sub_filter_nil_r.
applydup @compute_step_lib_success in Heqcsl; exrepnd; subst.
applydup @found_entry_implies_matching_entry in Heqcsl1; auto.
unfold matching_entry in Heqcsl0; repnd.
pose proof (compute_step_lib_success_change_bs
lib abs3 oa2
bs2 (map (fun t : BTerm => lsubst_bterm_aux t sub) bs2)
vars rhs correct) as h.
repeat (autodimp h hyp);
[ rw map_map; unfold compose; apply eq_maps;
introv j; destruct x; unfold num_bvars; auto
| ].
rw h; clear h.
eexists;dands;[complete eauto|].
auto.
apply alpha_eq_oterm_snd_subterm.
apply alphaeqbt_nilv2; auto.
unfold correct_abs in correct; repnd.
fold (lsubst_bterms_aux bs2 sub).
apply alpha_eq_lsubst_aux_mk_instance; auto.
}
{ SSSCase "NArithOp".
destruct bs; try (complete (csunf comp; allsimpl; dcwf h));[].
destruct b as [l t].
destruct l; destruct t as [v|f|op bs2]; try (complete (csunf comp; allsimpl; dcwf h));[].
dopid op as [can3|ncan3|exc3|abs3] SSSSCase.
- SSSSCase "Can".
csunf comp; csunf; allsimpl.
repeat (dcwf h);[].
boolvar; tcsp; ginv.
apply compute_step_arithop_success_can_can in comp; exrepnd; subst; allsimpl.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r;
unfold compute_step_arith; rw comp3; rw comp5; simpl.
eexists; dands; eauto.
- SSSSCase "NCan".
allsimpl.
allrw @compute_step_narithop_ncan2; boolvar; tcsp; ginv.
repeat (dcwf h); [].
remember (compute_step lib (oterm (NCan ncan3) bs2)) as comp1;
symmetry in Heqcomp1; destruct comp1; ginv.
simpl in sv; allrw remove_nvars_nil_l; allrw subvars_app_l; repnd.
allrw @nt_wf_NArithOp; exrepnd; allunfold @nobnd; ginv.
allsimpl; allrw @sub_filter_nil_r; allrw remove_nvars_nil_l; allrw app_nil_r.
eapply ind in Heqcomp1; eauto 3 with slow; exrepnd;[].
allsimpl; allrw @sub_filter_nil_r; rw Heqcomp1.
eexists;dands;[complete eauto|].
simpl.
apply alpha_eq_oterm_snd_subterm.
apply alphaeqbt_nilv2; auto.
- SSSSCase "Exc".
csunf comp; csunf; allsimpl; boolvar; tcsp; ginv.
repeat (dcwf h);[].
allsimpl; ginv; allsimpl; allrw remove_nvars_nil_l;
allrw subvars_app_l; allrw @sub_filter_nil_r; repnd.
eexists;dands;[complete eauto|]; auto.
- SSSSCase "Abs".
allsimpl.
allrw @compute_step_narithop_abs2; boolvar; tcsp; ginv.
repeat (dcwf h);[].
allunfold @on_success.
allrw remove_nvars_nil_l; allrw @sub_filter_nil_r.
allrw subvars_app_l; repnd.
remember (compute_step_lib lib abs3 bs2) as csl;
symmetry in Heqcsl; destruct csl; ginv; simpl;
allrw @sub_filter_nil_r.
applydup @compute_step_lib_success in Heqcsl; exrepnd; subst.
applydup @found_entry_implies_matching_entry in Heqcsl1; auto.
unfold matching_entry in Heqcsl0; repnd.
pose proof (compute_step_lib_success_change_bs
lib abs3 oa2
bs2 (map (fun t : BTerm => lsubst_bterm_aux t sub) bs2)
vars rhs correct) as h.
repeat (autodimp h hyp);
[ rw map_map; unfold compose; apply eq_maps;
introv j; destruct x; unfold num_bvars; auto
| ].
rw h; clear h.
eexists;dands;[complete eauto|].
auto.
apply alpha_eq_oterm_snd_subterm.
apply alphaeqbt_nilv2; auto.
unfold correct_abs in correct; repnd.
fold (lsubst_bterms_aux bs2 sub).
apply alpha_eq_lsubst_aux_mk_instance; auto.
}
{ SSSCase "NCanTest".
clear ind; csunf comp; csunf; allsimpl.
apply compute_step_can_test_success in comp; exrepnd; subst; allsimpl; fold_terms.
allrw remove_nvars_nil_l; allrw app_nil_r; allrw @sub_filter_nil_r.
eexists;dands;[complete eauto|].
remember (canonical_form_test_for c can2) as cft; destruct cft; auto. }
* SSCase "NCan".
allsimpl.
allrw @compute_step_ncan_ncan.
remember (compute_step lib (oterm (NCan ncan2) bts)) as cs;
symmetry in Heqcs; destruct cs; ginv.
simpl in sv; allrw remove_nvars_nil_l; allrw subvars_app_l; repnd.
pose proof (ind (oterm (NCan ncan2) bts) (oterm (NCan ncan2) bts) []) as h;
repeat (autodimp h hyp); eauto 3 with slow.
applydup @nt_wf_oterm_fst in wf.
eapply h in Heqcs; eauto; exrepnd; clear h;[].
allrw @sub_filter_nil_r.
allsimpl; rw Heqcs1.
eexists;dands;[complete eauto|].
simpl; allrw @sub_filter_nil_r.
apply alpha_eq_oterm_fst_subterm.
apply alphaeqbt_nilv2; auto.
* SSCase "Exc".
csunf comp; csunf; allsimpl.
apply compute_step_catch_success in comp; dorn comp; exrepnd; subst;
allsimpl; allrw remove_nvars_nil_l; allrw app_nil_r;
allrw subvars_app_l; repnd; allrw @sub_filter_nil_r.
{ eexists;dands;[complete eauto|].
apply implies_alpha_eq_mk_atom_eq; auto.
pose proof (simple_lsubst_lsubst_aux_sub_aeq b [(v,e)] sub) as h.
repeat (autodimp h hyp).
rw @covered_sub_cons; dands; auto.
apply covered_sub_nil. }
{ rw @compute_step_catch_non_trycatch; auto.
eexists;dands;[complete eauto|]; auto. }
* SSCase "Abs".
allsimpl.
allrw @compute_step_ncan_abs.
allunfold @on_success.
allrw remove_nvars_nil_l; allrw @sub_filter_nil_r.
allrw subvars_app_l; repnd.
remember (compute_step_lib lib abs2 bts) as csl;
symmetry in Heqcsl; destruct csl; ginv; simpl;
allrw @sub_filter_nil_r.
applydup @compute_step_lib_success in Heqcsl; exrepnd; subst.
applydup @found_entry_implies_matching_entry in Heqcsl1; auto.
unfold matching_entry in Heqcsl0; repnd.
pose proof (compute_step_lib_success_change_bs
lib abs2 oa2
bts (map (fun t : BTerm => lsubst_bterm_aux t sub) bts)
vars rhs correct) as h.
repeat (autodimp h hyp);
[ rw map_map; unfold compose; apply eq_maps;
introv i; destruct x; unfold num_bvars; auto
| ].
rw h; clear h.
eexists;dands;[complete eauto|].
auto.
apply alpha_eq_oterm_fst_subterm.
apply alphaeqbt_nilv2; auto.
unfold correct_abs in correct; repnd.
fold (lsubst_bterms_aux bts sub).
apply alpha_eq_lsubst_aux_mk_instance; auto.
}
{ csunf comp; csunf; allsimpl.
apply compute_step_fresh_success in comp; exrepnd; subst.
repndors; exrepnd; subst.
- allsimpl.
rw @sub_find_sub_filter; tcsp.
boolvar.
eexists; dands; eauto.
- rw @compute_step_fresh_if_isvalue_like0; eauto with slow.
eexists; dands; eauto.
repeat (rw <- @cl_lsubst_lsubst_aux; eauto 3 with slow).
apply alpha_eq_sym.
apply cl_lsubst_pushdown_fresh; eauto with slow.
- rw @compute_step_fresh_if_isnoncan_like0; eauto with slow; allsimpl; allrw app_nil_r.
remember (get_fresh_atom t) as a'.
remember (get_fresh_atom (lsubst_aux t (sub_filter sub [n]))) as a''.
pose proof (get_fresh_atom_prop t) as fa'; rw <- Heqa' in fa'.
pose proof (get_fresh_atom_prop (lsubst_aux t (sub_filter sub [n]))) as fa''; rw <- Heqa'' in fa''.
pose proof (compute_step_subst_utoken lib t x [(n, mk_utoken a')]) as ch.
allrw @nt_wf_fresh.
repeat (autodimp ch hyp); eauto with slow.
{ unfold get_utokens_sub; simpl; apply disjoint_singleton_l; tcsp. }
exrepnd.
pose proof (ch0 [(n,mk_utoken a'')]) as comp'; clear ch0; allsimpl.
repeat (autodimp comp' hyp).
{ apply nr_ut_sub_cons; auto; introv i j.
destruct fa''.
apply get_utokens_lsubst_aux; rw in_app_iff; tcsp. }
{ unfold get_utokens_sub; simpl; rw disjoint_singleton_l; intro i.
destruct fa''.
apply get_utokens_lsubst_aux; rw in_app_iff; tcsp. }
exrepnd.
allrw @fold_subst.
pose proof (ind t (subst t n (mk_utoken a'')) [n]) as h; clear ind.
repeat (autodimp h hyp).
{ rw @simple_osize_subst; eauto 3 with slow. }
pose proof (h s (sub_filter sub [n])) as k; clear h.
repeat (autodimp k hyp); eauto 3 with slow.
{ apply nt_wf_subst; eauto 3 with slow. }
{ rw @cl_subst_subst_aux; eauto 3 with slow.
unfold subst_aux; allsimpl; allrw app_nil_r.
rw @free_vars_lsubst_aux_cl; simpl; eauto with slow.
rw <- @dom_sub_sub_filter.
allrw subvars_prop; introv i; applydup sv in i.
allrw in_remove_nvars; allsimpl; allrw not_over_or; repnd; sp. }
exrepnd.
rw <- @cl_lsubst_lsubst_aux in k1; eauto with slow.
unfold subst in k1.
rw @computation2.cl_lsubst_swap in k1; simpl; eauto with slow;
[|rw disjoint_singleton_l; rw <- @dom_sub_sub_filter; rw in_remove_nvars; simpl; complete sp].
rw <- @cl_lsubst_lsubst_aux; eauto with slow.
unfold subst.
rw k1; simpl.
eexists; dands; eauto.
assert (alpha_eq v (lsubst w (sub_filter sub [n] ++ [(n,mk_utoken a'')]))) as aeq.
{ eapply alpha_eq_trans;[exact k0|].
rw <- @cl_lsubst_lsubst_aux; eauto 3 with slow.
eapply (alpha_eq_trans _ (lsubst (subst w n (mk_utoken a'')) (sub_filter sub [n]))).
- apply alpha_eq_lsubst_if_ext_eq; eauto 3 with slow.
- unfold subst; rw <- @cl_lsubst_app; eauto 3 with slow.
apply alpha_eq_lsubst_if_ext_eq; auto; introv i.
allrw @sub_find_app; allrw @sub_find_sub_filter_eq; simpl;[].
rw memvar_singleton; boolvar; tcsp; eauto 3 with slow;[].
remember (sub_find sub v0) as sf; destruct sf; simpl; auto. }
pose proof (implies_alpha_eq_mk_fresh_subst_utokens
n a'' v
(lsubst w (sub_filter sub [n] ++ [(n, mk_utoken a'')]))
aeq) as h.
eapply alpha_eq_trans;[exact h|clear h].
rw @cl_lsubst_app; eauto 3 with slow.
rw <- @cl_lsubst_lsubst_aux in fa''; eauto 3 with slow.
eapply alpha_eq_trans;[apply implies_alpha_eq_mk_fresh; apply simple_alphaeq_subst_utokens_subst|].
{ intro h.
allrw @get_utokens_lsubst; allrw in_app_iff; allrw not_over_or; repnd.
repndors; tcsp.
- eapply get_utokens_sub_sub_keep_first_subset in h;
[|apply subvars_eq in ch3;eauto]; tcsp. }
apply implies_alpha_eq_mk_fresh.
apply (alpha_eq_subst_utokens _ _ [(a',mk_var n)] [(a',mk_var n)]) in ch1; eauto 3 with slow.
pose proof (simple_alphaeq_subst_utokens_subst w n a') as aeq1.
autodimp aeq1 hyp.
{ intro k; apply ch4 in k; tcsp. }
assert (alpha_eq (subst_utokens x [(a', mk_var n)]) w) as aeq2; eauto 3 with slow; clear aeq1.
apply (lsubst_alpha_congr2 _ _ (sub_filter sub [n])) in aeq2.
rw <- @cl_lsubst_lsubst_aux; eauto 3 with slow.
}
+ SCase "Exc".
csunf comp; csunf; allsimpl; ginv.
eexists; dands; eauto.
+ SCase "Abs".
csunf comp; allsimpl.
csunf; simpl.
applydup @compute_step_lib_success in comp; exrepnd; subst.
applydup @found_entry_implies_matching_entry in comp1; auto.
unfold matching_entry in comp0; repnd.
pose proof (compute_step_lib_success_change_bs
lib abs oa2
bs (map (fun t : BTerm => lsubst_bterm_aux t sub) bs)
vars rhs correct) as h.
repeat (autodimp h hyp);
[ rw map_map; unfold compose; apply eq_maps;
introv i; destruct x; unfold num_bvars; auto
| ].
rw h; clear h.
eexists;dands;[complete eauto|].
auto.
unfold correct_abs in correct; repnd.
fold (lsubst_bterms_aux bs sub).
apply alpha_eq_lsubst_aux_mk_instance; auto.
Qed.
(* !!MOVE *)
Hint Resolve subvars_trans : slow.
Lemma is_utok_implies_wf {o} :
forall (t : @NTerm o), is_utok t -> wf_term t.
Proof.
introv h.
apply is_utok_implies in h; exrepnd; subst; eauto 3 with slow.
Qed.
Hint Resolve is_utok_implies_wf : slow.
Lemma is_utok_sub_implies_wf_sub {o} :
forall (sub : @Sub o),
is_utok_sub sub -> wf_sub sub.
Proof.
induction sub; introv h; eauto 3 with slow.
destruct a.
allrw @is_utok_sub_cons; repnd.
apply wf_sub_cons; eauto 3 with slow.
Qed.
Hint Resolve is_utok_sub_implies_wf_sub : slow.
Lemma wf_term_utok {o} :
forall a (bs : list (@BTerm o)),
wf_term (oterm (Can (NUTok a)) bs)
<=> (bs = []).
Proof.
introv; split; intro k; subst; auto; allrw @wf_oterm_iff; allsimpl; repnd; tcsp.
destruct bs; allsimpl; cpx.
Qed.
Lemma alphaeq_preserves_wf_term {o} :
forall (t1 t2 : @NTerm o),
alpha_eq t1 t2
-> wf_term t1
-> wf_term t2.
Proof.
introv aeq w.
apply alphaeq_preserves_wf in aeq.
allrw @wf_term_eq; apply aeq; auto.
Qed.
Hint Resolve alphaeq_preserves_wf_term : slow.
Hint Rewrite diff_nil : slow.
Lemma get_utokens_subst_utokens_aux_subset2 {o} :
forall (t : @NTerm o) sub,
wf_term t
-> subset (diff (get_patom_deq o) (utok_sub_dom sub) (get_utokens t))
(get_utokens (subst_utokens_aux t sub)).
Proof.
nterm_ind t as [v|f ind|op bs ind] Case; introv wf; auto.
- Case "vterm".
allsimpl; auto.
rw diff_nil; auto.
- Case "sterm".
allsimpl; autorewrite with slow; auto.
- Case "oterm".
rw @subst_utokens_aux_oterm.
remember (get_utok op) as guo; symmetry in Heqguo; destruct guo; allsimpl.
+ apply get_utok_some in Heqguo; subst; allsimpl.
unfold subst_utok.
allrw @wf_term_utok; subst; allsimpl.
remember (utok_sub_find sub g) as sf; symmetry in Heqsf; destruct sf; allsimpl.
* apply utok_sub_find_some in Heqsf.
apply in_utok_sub_eta in Heqsf; repnd.
rw diff_cons_r; boolvar; tcsp; GC.
rw diff_nil; auto.
* apply utok_sub_find_none in Heqsf.
rw diff_cons_r; boolvar; tcsp.
rw diff_nil; auto.
+ rw diff_app_r.
allapply @get_utok_none; allrw; simpl.
allrw diff_nil; simpl.
allrw flat_map_map; unfold compose.
rw diff_flat_map_r.
apply subset_flat_map2; introv i.
destruct x as [l t]; allsimpl.
eapply ind; eauto.
allrw @wf_oterm_iff; repnd.
pose proof (wf (bterm l t)) as k; sp.
Qed.
Lemma get_utokens_subst_utokens_subset2 {o} :
forall (t : @NTerm o) sub,
wf_term t
-> subset
(diff (get_patom_deq o) (utok_sub_dom sub) (get_utokens t))
(get_utokens (subst_utokens t sub)).
Proof.
introv w i.
pose proof (unfold_subst_utokens sub t) as h; exrepnd; rw h0.
applydup @alphaeq_preserves_utokens in h1 as k; rw k in i.
apply get_utokens_subst_utokens_aux_subset2; eauto with slow.
Qed.
(*
Lemma get_utokens_ot_subst_utokens_aux_subset2 {o} :
forall (t : @NTerm o) sub,
wf_term t
-> subset
(get_utokens_ot t)
(get_utokens_ot (subst_utokens_aux t sub)).
Proof.
nterm_ind t as [v|op bs ind] Case; introv wf.
- Case "vterm".
allsimpl; auto.
- Case "oterm".
rw @subst_utokens_aux_oterm.
remember (get_utok op) as guo; symmetry in Heqguo; destruct guo; allsimpl.
+ apply get_utok_some in Heqguo; subst; allsimpl.
unfold subst_utok.
allrw @wf_term_utok; subst; allsimpl; auto.
+ allrw @wf_oterm_iff; repnd.
apply subset_app_lr; auto.
allrw flat_map_map; unfold compose.
apply subset_flat_map2; introv i.
destruct x as [l t]; allsimpl.
eapply ind; eauto.
pose proof (wf (bterm l t)) as k; sp.
Qed.
Lemma get_utokens_ot_subst_utokens_subset2 {o} :
forall (t : @NTerm o) sub,
wf_term t
-> subset (get_utokens_ot t) (get_utokens_ot (subst_utokens t sub)).
Proof.
introv wf i.
pose proof (unfold_subst_utokens sub t) as h; exrepnd; rw h0.
applydup @alphaeq_preserves_utokens_ot in h1 as k; rw k in i.
apply get_utokens_ot_subst_utokens_aux_subset2; eauto with slow.
Qed.
*)
Lemma wf_term_implies {o} :
forall (t : @NTerm o), wf_term t -> nt_wf t.
Proof.
introv w.
apply nt_wf_eq; auto.
Qed.
Hint Resolve wf_term_implies : slow.
Hint Resolve preserve_nt_wf_compute_step : slow.
Hint Resolve nt_wf_implies : slow.
Lemma compute_step_preserves_wf {o} :
forall lib (t1 t2 : @NTerm o),
compute_step lib t1 = csuccess t2
-> wf_term t1
-> wf_term t2.
Proof.
introv comp wf.
eauto with slow.
Qed.
Hint Resolve compute_step_preserves_wf : slow.
Lemma isprogram_implies_wf {o} :
forall (t : @NTerm o), isprogram t -> wf_term t.
Proof.
introv isp.
destruct isp; eauto with slow.
Qed.
Hint Resolve eqset_trans : slow.
Hint Resolve eqset_sym : slow.
Lemma sub_bound_vars_allvars_sub {o} :
forall (sub : @Sub o),
allvars_sub sub
-> sub_bound_vars sub = [].
Proof.
induction sub; introv h; allsimpl; auto.
destruct a.
allrw @allvars_sub_cons; repnd.
rw IHsub; auto.
apply isvariable_implies in h0; exrepnd; subst; simpl; auto.
Qed.
Lemma alpha_eq_subst_utoken_not_in_implies {o} :
forall (t1 t2 : @NTerm o) v a,
!LIn a (get_utokens t1)
-> !LIn a (get_utokens t2)
-> !LIn v (bound_vars t1)
-> !LIn v (bound_vars t2)
-> alpha_eq (subst t1 v (mk_utoken a)) (subst t2 v (mk_utoken a))
-> alpha_eq t1 t2.
Proof.
nterm_ind1s t1 as [v1|f1 ind1|op1 bs1 ind1] Case; introv ni1 ni2 nib1 nib2 aeq; allsimpl; GC.
- Case "vterm".
repeat (unfsubst in aeq); allsimpl; boolvar.
+ destruct t2 as [v2|f2|op2 bs2]; allsimpl; boolvar; tcsp;
try (complete (inversion aeq)).
inversion aeq; allsimpl; subst.
destruct bs2; allsimpl; cpx; GC.
destruct ni2; sp.
+ destruct t2 as [v2|f2|op2 bs2]; allsimpl; boolvar; tcsp;
try (complete (inversion aeq)).
- Case "sterm".
repeat (unfsubst in aeq); allsimpl.
destruct t2 as [v2|f2|op2 bs2]; allsimpl; GC; tcsp;
boolvar; tcsp; try (complete (inversion aeq)).
- Case "oterm".
repeat (unfsubst in aeq); allsimpl.
destruct t2 as [v2|f2|op2 bs2]; allsimpl;
try (complete (inversion aeq)).
+ boolvar; GC.
* inversion aeq; allsimpl; subst.
destruct bs1; allsimpl; cpx; GC.
destruct ni1; sp.
* inversion aeq.
+ allrw @alpha_eq_oterm_combine2; repnd; subst.
allrw map_length.
dands; auto.
introv i.
destruct b1 as [l1 t1].
destruct b2 as [l2 t2].
allrw in_app_iff; allrw not_over_or; repnd.
allrw lin_flat_map; exrepnd.
pose proof (aeq (lsubst_bterm_aux (bterm l1 t1) [(v,mk_utoken a)])
(lsubst_bterm_aux (bterm l2 t2) [(v,mk_utoken a)])) as h; clear aeq.
rw <- @map_combine in h.
rw in_map_iff in h.
autodimp h hyp.
{ eexists; dands; eauto. }
allsimpl.
applydup in_combine in i; repnd.
boolvar; tcsp; allrw @lsubst_aux_nil; auto.
{ destruct nib1.
exists (bterm l1 t1); dands; simpl; auto.
rw in_app_iff; sp. }
{ destruct nib2.
exists (bterm l2 t2); dands; simpl; auto.
rw in_app_iff; sp. }
apply alphaeq_bterm3_if
with (lva := v
:: all_vars t1
++ all_vars t2
)
in h.
inversion h as [? ? ? ? ? disj len1 len2 norep al]; subst; clear h.
allrw disjoint_app_r; allrw disjoint_cons_r; allrw disjoint_app_r; repnd.
apply (al_bterm _ _ lv); allrw disjoint_app_r; dands; try omega; eauto 3 with slow.
apply alpha_eq_if3 in al.
pose proof (lsubst_aux_nest_swap2 t1 [(v,mk_utoken a)] (var_ren l1 lv)) as h1.
simpl in h1; allrw disjoint_singleton_l.
allrw <- @sub_free_vars_is_flat_map_free_vars_range.
allrw <- @sub_bound_vars_is_flat_map_bound_vars_range.
repeat (rw @sub_free_vars_var_ren in h1; auto).
repeat (rw @dom_sub_var_ren in h1; auto).
repeat (autodimp h1 hyp); eauto with slow.
pose proof (lsubst_aux_nest_swap2 t2 [(v,mk_utoken a)] (var_ren l2 lv)) as h2.
simpl in h2; allrw disjoint_singleton_l.
allrw <- @sub_free_vars_is_flat_map_free_vars_range.
allrw <- @sub_bound_vars_is_flat_map_bound_vars_range.
repeat (rw @sub_free_vars_var_ren in h2; auto; try omega).
repeat (rw @dom_sub_var_ren in h2; auto; try omega).
repeat (autodimp h2 hyp); eauto with slow.
rw h1 in al; rw h2 in al; clear h1 h2.
allrw @fold_subst.
pose proof (ind1 t1 (lsubst_aux t1 (var_ren l1 lv)) l1) as h; clear ind1.
allrw @lsubst_aux_allvars_preserves_osize2.
repeat (autodimp h hyp); eauto 3 with slow.
pose proof (h (lsubst_aux t2 (var_ren l2 lv)) v a) as k; clear h.
repeat (autodimp k hyp).
{ intro j; apply get_utokens_lsubst_aux in j.
rw @get_utokens_sub_allvars_sub in j; eauto with slow.
rw app_nil_r in j; auto.
destruct ni1.
exists (bterm l1 t1); simpl; sp. }
{ intro j; apply get_utokens_lsubst_aux in j.
rw @get_utokens_sub_allvars_sub in j; eauto with slow.
rw app_nil_r in j; auto.
destruct ni2.
exists (bterm l2 t2); simpl; sp. }
{ intro j; pose proof (eqvars_bound_vars_lsubst_aux t1 (var_ren l1 lv)) as h.
rw eqvars_prop in h; apply h in j; clear h.
rw @sub_bound_vars_allvars_sub in j; eauto 3 with slow.
rw app_nil_r in j.
destruct nib1.
exists (bterm l1 t1); simpl; rw in_app_iff; sp. }
{ intro j; pose proof (eqvars_bound_vars_lsubst_aux t2 (var_ren l2 lv)) as h.
rw eqvars_prop in h; apply h in j; clear h.
rw @sub_bound_vars_allvars_sub in j; eauto 3 with slow.
rw app_nil_r in j.
destruct nib2.
exists (bterm l2 t2); simpl; rw in_app_iff; sp. }
{ repeat unfsubst. }
{ rw @lsubst_lsubst_aux2; eauto 3 with slow; try omega.
rw @lsubst_lsubst_aux2; eauto 3 with slow; try omega. }
Qed.
(* !!MOVE *)
Hint Resolve alpha_eq_preserves_isvalue_like : slow.
Lemma isvalue_like_pushdown_fresh {o} :
forall v (t : @NTerm o),
isvalue_like t
-> isvalue_like (pushdown_fresh v t).
Proof.
introv isv.
allunfold @isvalue_like; repndors.
- apply iscan_implies in isv; repndors; exrepnd; subst; simpl; sp.
- apply isexc_implies2 in isv; exrepnd; subst; simpl; sp.
Qed.
Hint Resolve isvalue_like_pushdown_fresh : slow.
Lemma reduces_in_atmost_k_step_fresh_id {o} :
forall (lib : @library o) v t,
isvalue_like t
-> !(reduces_to lib (mk_fresh v (mk_var v)) t).
Proof.
introv isv r.
unfold reduces_to in r; exrepnd.
induction k; introv.
- allrw @reduces_in_atmost_k_steps_0; subst.
unfold isvalue_like in isv; allsimpl; sp.
- allrw @reduces_in_atmost_k_steps_S; exrepnd.
csunf r0; allsimpl; boolvar; ginv; sp.
Qed.
Hint Resolve computek_preserves_program reduces_to_preserves_program : slow.
Ltac decomp_progc := unfold_all_mk;
match goal with
| [ |- isprogram (oterm _ ?lbt)] => try trivial;apply isprogram_ot_if_eauto2;
[spc;fail| ];
(let Hlt := fresh "XXHlt" in
let n := fresh "XXn" in
simpl; intros n Hlt;
repeat (destruct n; try omega); unfold selectbt; simpl; unfold nobnd
)
| [ |- isprogram_bt (bterm [] ?lbt)] => apply implies_isprogram_bt0
end .
(*it loops.. use decomp_progc instead
Ltac decomp_progc2 :=unfold mk_apply;
match goal with
| [ |- isprogram (oterm _ ?lbt)] => try trivial;apply isprogram_ot_if_eauto2;
[spc |
(let Hlt := fresh "XXHlt" in
let n := fresh "XXn" in
simpl; intros n Hlt;
repeat (destruct n; try omega); unfold selectbt; simpl; unfold nobnd
)]
| [ |- isprogram_bt (bterm [] ?lbt)] => apply implies_isprogram_bt0
end .
*)
Lemma computes_in_max_k_steps_refl {p} :
forall lib k v,
@isvalue p v -> computes_to_value_in_max_k_steps lib k v v.
Proof.
intros. unfolds_base. dands;sp.
apply compute_at_most_k_steps_if_value;sp.
Qed.
Ltac repeatn n tac:=
match n with
| 0 => idtac
| S ?n => tac; repeatn n tac
end.
Lemma computes_to_value_in_max_k_steps_0 {p} :
forall lib (a b : @NTerm p),
computes_to_value_in_max_k_steps lib 0 a b <=> (a = b # isvalue b).
Proof.
unfold computes_to_value_in_max_k_steps, reduces_in_atmost_k_steps.
simpl; introv; split; intro k; repnd.
inversion k0; auto.
subst; dands; auto.
Qed.
Lemma computes_to_value_in_max_k_steps_S {p} :
forall lib t v k,
computes_to_value_in_max_k_steps lib (S k) t v
<=> {u : @NTerm p
& compute_step lib t = csuccess u
# computes_to_value_in_max_k_steps lib k u v}.
Proof.
introv; split; intro comp.
- allunfold @computes_to_value_in_max_k_steps; repnd.
apply reduces_in_atmost_k_steps_S in comp0; exrepnd.
exists u; sp.
- exrepnd.
allunfold @computes_to_value_in_max_k_steps; repnd; dands; auto.
rw @reduces_in_atmost_k_steps_S.
exists u; sp.
Qed.
Lemma computes_to_value_in_max_k_steps_isvalue_like {o} :
forall lib k (t u : @NTerm o),
computes_to_value_in_max_k_steps lib k t u
-> isvalue_like t
-> t = u.
Proof.
induction k; introv comp isv.
- allrw @computes_to_value_in_max_k_steps_0; sp.
- allrw @computes_to_value_in_max_k_steps_S; exrepnd.
unfold isvalue_like in isv; repndors.
+ apply iscan_implies in isv; repndors; exrepnd; subst;
csunf comp1; allsimpl; ginv;
apply IHk in comp0; eauto with slow.
+ apply isexc_implies2 in isv; exrepnd; subst.
csunf comp1; allsimpl; ginv.
apply IHk in comp0; eauto with slow.
Qed.
Lemma compute_at_most_k_steps_S2 {o} :
forall (lib : library) (n : nat) (t : @NTerm o),
compute_at_most_k_steps lib (S n) t
= match compute_step lib t with
| csuccess u => compute_at_most_k_steps lib n u
| cfailure m u => cfailure m u
end.
Proof.
induction n; introv; allsimpl.
- remember (compute_step lib t) as c; destruct c; auto.
- rw IHn; remember (compute_step lib t) as c; destruct c; auto.
Qed.
Lemma co_wf_pk2can {o} :
forall (pk : @param_kind o), co_wf CompOpEq (pk2can pk) [] = true.
Proof.
introv.
unfold co_wf.
allrw @get_param_from_cop_pk2can; auto.
Qed.
Hint Rewrite @co_wf_pk2can : slow.
(* move to computation.v*)
Lemma compute_max_steps_eauto {p} :
forall lib k t tv,
@computes_to_value_in_max_k_steps p lib k t tv -> isvalue tv.
Proof.
introv Hc.
repnud Hc.
trivial.
Qed.
Lemma compute_max_steps_eauto2 {p} : forall t,
@isvalue p t -> isprogram t.
Proof.
introv Hc.
inverts Hc.
trivial.
Qed.
(* move to computation.v*)
Lemma no_change_after_value3 {p} :
forall lib t k1 v,
@computes_to_value_in_max_k_steps p lib k1 t v
-> (isvalue v)
-> forall k2, k1<=k2 -> computes_to_value_in_max_k_steps lib k2 t v.
Proof.
unfold computes_to_value_in_max_k_steps. intros.
repnd.
dands;sp.
eapply no_change_after_value2; eauto.
Qed.
Lemma compute_at_most_k_steps_isvalue_like {o} :
forall lib k (t : @NTerm o),
isvalue_like t
-> compute_at_most_k_steps lib k t = csuccess t.
Proof.
induction k; simpl; introv isv; auto.
rw IHk; auto.
apply compute_step_value_like; auto.
Qed.
Lemma computes_atmost_ksteps_prinarg {p} :
forall lib op ntp lbt k ntpc,
compute_at_most_k_steps lib k ntp = @csuccess p ntpc
-> {j : nat $ compute_at_most_k_steps lib j (oterm (NCan op) ((bterm [] ntp)::lbt))
= csuccess (oterm (NCan op) ((bterm [] ntpc)::lbt))
# j<=k}.
Proof.
induction k as [| k Hind]; introv Hck;[exists 0; allsimpl|];spc;[].
destruct ntp as [| | ntpo ntplbt];
[rw @compute_at_most_steps_var in Hck; spc; fail| |].
{ rw @compute_at_most_k_steps_isvalue_like in Hck; eauto 3 with slow; ginv.
exists 0; dands; auto; try omega. }
allsimpl.
remember (compute_at_most_k_steps lib k (oterm ntpo ntplbt)) as ck.
destruct ck as [csk | cf]; spc;[].
dimp (Hind csk); exrepnd; spc;[]. clear Hind.
destruct csk as [sckv| f | csko csklbt]; [inverts Hck; fail| |].
{ rw @compute_step_value_like in Hck; eauto 3 with slow; ginv.
eexists; dands; eauto. }
dopid csko as [cskoc| cskon | cskexc | cskabs] Case.
- Case "Can".
simpl in Hck. inverts Hck. exists j; sp.
- Case "NCan".
exists (S j). dands;[|omega]. simpl. rw hyp1. simpl in Hck. simpl.
rw @compute_step_ncan_ncan.
rw Hck;sp.
- Case "Exc".
rw @compute_step_exception in Hck; sp; inversion Hck; subst; GC.
exists j; sp.
- Case "Abs".
exists (S j).
dands;[|omega]. simpl. rw hyp1. simpl in Hck. simpl.
rw @compute_step_ncan_abs.
csunf Hck; allsimpl.
rw Hck;sp.
Qed.
Lemma reduces_to_prinarg {p} : forall lib op ntp ntpc lbt,
@reduces_to p lib ntp ntpc
-> reduces_to lib (oterm (NCan op) ((bterm [] ntp)::lbt))
(oterm (NCan op) ((bterm [] ntpc)::lbt)).
Proof.
introv Hc. repnud Hc. exrepnd.
eapply (computes_atmost_ksteps_prinarg) in Hc0.
exrepnd.
exists j.
eauto.
Qed.
Lemma compute_at_most_k_steps_step {p} :
forall lib t m a, compute_at_most_k_steps lib m t = csuccess a
-> m >0
-> {tc : @NTerm p $ compute_step lib t = csuccess tc}.
Proof.
induction m as [| m Hind];introv Hc Hlt;[omega|].
allsimpl. remember (compute_at_most_k_steps lib m t) as ck.
destruct ck; spc.
destruct m; allsimpl; [ inverts Heqck ; exists a; spc |].
dimp (Hind n); spc; omega.
Qed.
Lemma if_computes_to_value_steps_arith {p} :
forall lib a k lbt v,
computes_to_value_in_max_k_steps lib k (oterm (NCan (NArithOp a)) lbt) v
-> {n1,n2 : NTerm $ lbt = [bterm [] n1, bterm [] n2] #
{nv1,nv2 : Z $ v = mk_integer ((get_arith_op a) nv1 nv2) #
{ k1,k2 : nat $ k1+k2+1 <=k
# computes_to_value_in_max_k_steps lib k1 n1 (mk_integer nv1)
# computes_to_value_in_max_k_steps lib k2 n2 (mk_integer nv2)
# compute_at_most_k_steps lib (k1+k2) (oterm (NCan (NArithOp a)) lbt)
= csuccess (oterm (NCan (NArithOp a))
[bterm [] (mk_integer nv1),
bterm [] (@mk_integer p nv2)])
}}}.
Proof.
induction k as [| k Hind]; introv Hcv.
{ allrw @computes_to_value_in_max_k_steps_0; repnd; subst.
allapply @isvalue_ncan; tcsp. }
repnud Hcv.
unfold reduces_in_atmost_k_steps in Hcv0.
rw @compute_at_most_k_steps_eq_f in Hcv0.
simpl in Hcv0. rename Hcv0 into Hcomp.
dlist lbt SSCase as [| arg1]; invertsn Hcomp.
SSCase "conscase".
destruct arg1 as [arg1vs arg1nt];
dlist arg1vs SSSCase as [|arg1v1]; [|inverts Hcomp].
SSSCase "nilcase".
destruct arg1nt as [v89|f| arg1o arg1bts];[inverts Hcomp| |];[|].
{ csunf Hcomp; allsimpl; ginv. }
dopid arg1o as [arg1c | arg1nc | arg1exc | arg1abs] SSSSCase; try (complete ginv).
- SSSSCase "Can".
destruct lbt as [| bt2 lbt].
{ csunf Hcomp; allsimpl; boolvar; ginv; dcwf h. }
destruct bt2 as [lv2 nt2].
destruct lv2; destruct nt2 as [?|?| arg2o arg2bts];
try (complete (csunf Hcomp; allsimpl; boolvar; ginv; dcwf h));[].
dopid arg2o as [arg2c | arg2nc | arg2exc | arg2abs] SSSSSCase; try (complete ginv).
+ SSSSSCase "Can".
csunf Hcomp; allsimpl; boolvar; allsimpl; ginv; dcwf h;[].
match goal with
| [ H : context[compute_step_arith ?a1 ?a2 ?a3 ?a4 ?a5 ?a6 ?a7] |- _ ] =>
remember (compute_step_arith a1 a2 a3 a4 a5 a6 a7) as c
end; destruct c; ginv; symmetry in Heqc.
apply compute_step_arithop_success_can_can in Heqc; exrepnd; subst.
allapply @get_param_from_cop_pki; subst; fold_terms.
exists (@mk_integer p n1) (@mk_integer p n2); dands; auto.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
rw @compute_on_value in Hcomp; eauto 3 with slow; ginv.
exists n1 n2; dands; auto.
exists 0 0; dands; auto; try omega;
apply computes_in_max_k_steps_refl; eauto with slow.
+ SSSSSCase "NCan".
rw @compute_step_narithop_ncan2 in Hcomp; boolvar; tcsp; ginv; dcwf h;[].
remember (compute_step lib (oterm (NCan arg2nc) arg2bts)) as c.
symmetry in Heqc; destruct c; allsimpl; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; exrepnd; subst; ginv; clear Hind.
eexists; eexists; dands; eauto.
eexists; eexists; dands; eauto.
applydup @computes_to_value_in_max_k_steps_isvalue_like in HcompHcv4; eauto with slow.
inversion HcompHcv0; subst; fold_terms; GC.
exists k1 (S k2); dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw NPeano.Nat.add_succ_r.
rw @compute_at_most_k_steps_S2.
unfold mk_integer, nobnd.
rw @compute_step_narithop_ncan2; simpl; boolvar; tcsp.
rw Heqc; auto.
+ SSSSSCase "Exc".
csunf Hcomp; allsimpl; boolvar; ginv; dcwf h;[].
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
rw @compute_at_most_k_steps_exception in Hcomp; inversion Hcomp; subst; GC.
allapply @isvalue_exc; sp.
+ SSSSSCase "Abs".
rw @compute_step_narithop_abs2 in Hcomp; boolvar; tcsp; ginv; dcwf h;[].
remember (compute_step_lib lib arg2abs arg2bts) as c.
symmetry in Heqc; destruct c; allsimpl; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; exrepnd; subst; ginv; clear Hind.
eexists; eexists; dands; eauto.
eexists; eexists; dands; eauto.
applydup @computes_to_value_in_max_k_steps_isvalue_like in HcompHcv4; eauto with slow.
inversion HcompHcv0; subst; fold_terms; GC.
exists k1 (S k2); dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw NPeano.Nat.add_succ_r.
rw @compute_at_most_k_steps_S2.
unfold mk_integer, nobnd.
rw @compute_step_narithop_abs2; simpl; boolvar; tcsp.
rw Heqc; auto.
- SSSSCase "NCan".
rw @compute_step_narithop_ncan1 in Hcomp.
remember (compute_step lib (oterm (NCan arg1nc) arg1bts)) as c.
symmetry in Heqc; destruct c; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; exrepnd; subst; ginv; clear Hind.
eexists; eexists; dands; eauto.
eexists; eexists; dands; eauto.
exists (S k1) k2; dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw plus_Sn_m.
rw @compute_at_most_k_steps_S2.
unfold mk_integer, nobnd.
rw @compute_step_narithop_ncan1; simpl; boolvar; tcsp.
rw Heqc; auto.
- SSSSCase "Exc".
csunf Hcomp; allsimpl; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
rw @compute_at_most_k_steps_exception in Hcomp; inversion Hcomp; subst; GC.
allapply @isvalue_exc; sp.
- SSSSCase "Abs".
rw @compute_step_narithop_abs1 in Hcomp.
remember (compute_step_lib lib arg1abs arg1bts) as c.
symmetry in Heqc; destruct c; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; exrepnd; subst; ginv; clear Hind.
eexists; eexists; dands; eauto.
eexists; eexists; dands; eauto.
exists (S k1) k2; dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw plus_Sn_m.
rw @compute_at_most_k_steps_S2.
unfold mk_integer, nobnd.
rw @compute_step_narithop_abs1; simpl; boolvar; tcsp.
rw Heqc; auto.
Qed.
Lemma if_computes_to_value_steps_ncomp {p} :
forall lib a k lbt v,
computes_to_value_in_max_k_steps lib k (oterm (NCan (NCompOp a)) lbt) v
-> {n1,n2,n3,n4 : @NTerm p $ lbt = [bterm [] n1, bterm [] n2, bterm [] n3, bterm [] n4] #
{ c1,c2 : CanonicalOp $ let tc:= (oterm (NCan (NCompOp a))
[bterm [] (oterm (Can c1) []),
bterm [] (oterm (Can c2) []),
bterm [] n3,
bterm [] n4]) in
{ k1,k2 : nat $ k1+k2+1 <=k
# computes_to_value_in_max_k_steps lib k1 n1 (oterm (Can c1) [])
# computes_to_value_in_max_k_steps lib k2 n2 (oterm (Can c2) [])
# compute_at_most_k_steps lib (k1+k2) (oterm (NCan (NCompOp a)) lbt)
= csuccess tc
}}}.
Proof.
induction k as [| k Hind]; introv Hcv.
{ allrw @computes_to_value_in_max_k_steps_0; repnd; subst.
allapply @isvalue_ncan; tcsp. }
repnud Hcv.
unfold reduces_in_atmost_k_steps in Hcv0.
rw @compute_at_most_k_steps_eq_f in Hcv0.
simpl in Hcv0.
rename Hcv0 into Hcomp.
dlist lbt SSCase as [| arg1]; invertsn Hcomp.
SSCase "conscase".
destruct arg1 as [arg1vs arg1nt];
dlist arg1vs SSSCase as [|arg1v1]; [|inverts Hcomp].
SSSCase "nilcase".
destruct arg1nt as [v89|f| arg1o arg1bts];[inverts Hcomp| |];[|].
{ csunf Hcomp; allsimpl; ginv. }
dopid arg1o as [arg1c | arg1nc | arg1exc | arg1abs] SSSSCase.
- SSSSCase "Can".
destruct lbt as [| bt2 lbt].
{ csunf Hcomp; allsimpl; boolvar; ginv; dcwf h. }
destruct bt2 as [lv2 nt2];[].
destruct lv2; destruct nt2 as [?|?| arg2o arg2bts];
try (complete (csunf Hcomp; allsimpl; boolvar; ginv; dcwf h));[].
dopid arg2o as [arg2c | arg2nc | arg2exc | arg2abs] SSSSSCase; try (complete ginv).
+ SSSSSCase "Can".
csunf Hcomp; allsimpl; boolvar; tcsp; ginv; dcwf h;[].
match goal with
| [ H : context[compute_step_comp ?a1 ?a2 ?a3 ?a4 ?a5 ?a6 ?a7] |- _ ] =>
remember (compute_step_comp a1 a2 a3 a4 a5 a6 a7) as c
end; destruct c; ginv; symmetry in Heqc.
apply compute_step_compop_success_can_can in Heqc; exrepnd; subst;
repndors; exrepnd; subst;
allrw @get_param_from_cop_some; subst; allsimpl;
unfold nobnd; allsimpl; GC;
eexists; eexists; eexists; eexists; dands; eauto.
* exists (@Nint p n1) (@Nint p n2) 0 0; dands; try omega; auto; fold_terms.
{ rw @computes_to_value_in_max_k_steps_0; dands; eauto 3 with slow. }
{ rw @computes_to_value_in_max_k_steps_0; dands; eauto 3 with slow. }
* exists (pk2can pk1) (pk2can pk2) 0 0; dands; try omega; auto; fold_terms;
allrw <- @pk2term_eq.
{ rw @computes_to_value_in_max_k_steps_0; dands; eauto 3 with slow. }
{ rw @computes_to_value_in_max_k_steps_0; dands; eauto 3 with slow. }
+ SSSSSCase "NCan".
rw @compute_step_ncompop_ncan2 in Hcomp; boolvar; tcsp; ginv; dcwf h;[].
remember (compute_step lib (oterm (NCan arg2nc) arg2bts)) as c.
symmetry in Heqc; destruct c; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; clear Hind.
exrepnd; ginv.
eexists; eexists; eexists; eexists; dands; eauto.
applydup @computes_to_value_in_max_k_steps_isvalue_like in HcompHcv3; eauto with slow.
inversion HcompHcv0; subst; fold_terms; GC.
exists c1 c2 k1 (S k2); dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw NPeano.Nat.add_succ_r.
rw @compute_at_most_k_steps_S2.
unfold nobnd.
rw @compute_step_ncompop_ncan2; simpl; boolvar; tcsp; dcwf h.
rw Heqc; auto.
+ SSSSSCase "Exc".
csunf Hcomp; allsimpl; ginv; dcwf h;[].
boolvar; tcsp; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
rw @compute_at_most_k_steps_exception in Hcomp; inversion Hcomp; subst; GC.
allapply @isvalue_exc; sp.
+ SSSSSCase "Abs".
rw @compute_step_ncompop_abs2 in Hcomp; boolvar; tcsp; ginv; dcwf h;[].
remember (compute_step_lib lib arg2abs arg2bts) as c.
symmetry in Heqc; destruct c; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; clear Hind.
exrepnd; ginv.
eexists; eexists; eexists; eexists; dands; eauto.
applydup @computes_to_value_in_max_k_steps_isvalue_like in HcompHcv3; eauto with slow.
inversion HcompHcv0; subst; fold_terms; GC.
exists c1 c2 k1 (S k2); dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw NPeano.Nat.add_succ_r.
rw @compute_at_most_k_steps_S2.
unfold nobnd.
rw @compute_step_ncompop_abs2; simpl; boolvar; tcsp; dcwf h;[].
rw Heqc; auto.
- SSSSCase "NCan".
rw @compute_step_ncompop_ncan1 in Hcomp; boolvar; tcsp; ginv.
remember (compute_step lib (oterm (NCan arg1nc) arg1bts)) as c.
symmetry in Heqc; destruct c; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; clear Hind.
exrepnd; ginv.
eexists; eexists; eexists; eexists; dands; eauto.
exists c1 c2 (S k1) k2; dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw NPeano.Nat.add_succ_l.
rw @compute_at_most_k_steps_S2.
unfold nobnd.
rw @compute_step_ncompop_ncan1; simpl; boolvar; tcsp.
rw Heqc; auto.
- SSSSCase "Exc".
csunf Hcomp; allsimpl; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
rw @compute_at_most_k_steps_exception in Hcomp; inversion Hcomp; subst; GC.
allapply @isvalue_exc; sp.
- SSSSCase "Abs".
rw @compute_step_ncompop_abs1 in Hcomp; boolvar; tcsp; ginv.
remember (compute_step_lib lib arg1abs arg1bts) as c.
symmetry in Heqc; destruct c; ginv.
rw <- @compute_at_most_k_steps_eq_f in Hcomp.
make_and Hcomp Hcv.
apply Hind in HcompHcv; clear Hind.
exrepnd; ginv.
eexists; eexists; eexists; eexists; dands; eauto.
exists c1 c2 (S k1) k2; dands; try omega; auto.
* rw @computes_to_value_in_max_k_steps_S.
eexists; dands; eauto.
* rw NPeano.Nat.add_succ_l.
rw @compute_at_most_k_steps_S2.
unfold nobnd.
rw @compute_step_ncompop_abs1; simpl; boolvar; tcsp.
rw Heqc; auto.
Qed.
Lemma computes_steps_prinargs_arith {p} :
forall lib a ntp1 ntp2 lbt k1 k2 ntpc1 ntpc2,
compute_at_most_k_steps lib k1 ntp1 = csuccess ntpc1
-> isinteger ntpc1
-> compute_at_most_k_steps lib k2 ntp2 = @csuccess p ntpc2
-> {j : nat $ compute_at_most_k_steps lib j (oterm (NCan (NArithOp a))
((bterm [] ntp1)::((bterm [] ntp2)::lbt)))
= csuccess (oterm (NCan (NArithOp a))
((bterm [] ntpc1)::((bterm [] ntpc2)::lbt)))
# j<= (k1+k2)}.
Proof.
induction k2 as [| k2 Hind]; introv H1c H1v H2c.
- inverts H2c.
match goal with
| [ |- {_ : nat $ compute_at_most_k_steps _ _
(oterm (NCan ?no) (?h :: ?tl)) = _ # _ }] =>
apply @computes_atmost_ksteps_prinarg with (lbt:= tl)
(op:=no) in H1c
end.
exrepnd. exists j. dands; spc. omega.
- duplicate H1v. inverts H1v as Hisp1.
rename H2c into Hck. rename k2 into k.
destruct ntp2 as [|?| ntp2o ntp2lbt];
[rw @compute_at_most_steps_var in Hck; spc; fail| |].
{ rw @compute_at_most_k_steps_isvalue_like in Hck; eauto 3 with slow.
ginv.
pose proof (Hind (mk_integer x) (sterm n)) as h; clear Hind.
repeat (autodimp h hyp).
{ rw @compute_at_most_k_steps_isvalue_like; eauto 3 with slow. }
exrepnd.
eexists; dands; eauto; try omega. }
allsimpl.
remember (compute_at_most_k_steps lib k (oterm ntp2o ntp2lbt)) as ck.
destruct ck as [csk | cf]; spc;[].
pose proof (Hind _ csk H1c H1v0 eq_refl) as XX. clear H1v0. exrepnd.
destruct csk as [sckv|?| csko csklbt]; [inverts Hck; fail| |].
{ csunf Hck; allsimpl; ginv.
eexists; dands; eauto; try omega. }
dopid csko as [cskoc| cskon | cskexc | cskabs] Case.
+ Case "Can".
simpl in Hck. inverts Hck. exists j; sp. omega.
+ Case "NCan".
exists (S j). dands;[|omega]. simpl. rw XX1.
allunfold @mk_integer.
rw @compute_step_narithop_ncan2; rw Hck.
dcwf h.
+ Case "Exc".
rw @compute_step_exception in Hck; sp; inversion Hck; subst; GC.
exists j; sp; omega.
+ Case "Abs".
exists (S j). dands;[|omega]. simpl. rw XX1. simpl. simpl in Hck. simpl.
allunfold @mk_integer.
rw @compute_step_narithop_abs2; boolvar; allsimpl; tcsp.
csunf Hck; allsimpl.
rw Hck;sp.
Qed.
(* proof is exactly same as computes_steps_prinargs_arith *)
Lemma computes_steps_prinargs_comp {p} :
forall lib a ntp1 ntp2 lbt k1 k2 ntpc1 ntpc2,
compute_at_most_k_steps lib k1 ntp1 = csuccess ntpc1
-> iswfpk a ntpc1
-> compute_at_most_k_steps lib k2 ntp2 = @csuccess p ntpc2
-> {j : nat $ compute_at_most_k_steps lib j (oterm (NCan (NCompOp a))
((bterm [] ntp1)::((bterm [] ntp2)::lbt)))
= csuccess (oterm (NCan (NCompOp a))
((bterm [] ntpc1)::((bterm [] ntpc2)::lbt)))
# j<= (k1+k2)}.
Proof.
induction k2 as [| k2 Hind]; introv H1c H1v H2c.
- inverts H2c.
match goal with
| [ |- {_ : nat $ compute_at_most_k_steps _ _
(oterm (NCan ?no) (?h :: ?tl)) = _ # _ }] =>
apply @computes_atmost_ksteps_prinarg with (lbt:= tl)
(op:=no) in H1c
end.
exrepnd. exists j. dands; spc. omega.
- rename H2c into Hck. rename k2 into k.
destruct ntp2 as [|?| ntp2o ntp2lbt];
[rw @compute_at_most_steps_var in Hck; spc; fail| |].
{ rw @compute_at_most_k_steps_isvalue_like in Hck; eauto 3 with slow.
ginv.
pose proof (Hind ntpc1 (sterm n)) as h; clear Hind.
repeat (autodimp h hyp).
{ rw @compute_at_most_k_steps_isvalue_like; eauto 3 with slow. }
exrepnd.
eexists; dands; eauto; try omega. }
allsimpl.
remember (compute_at_most_k_steps lib k (oterm ntp2o ntp2lbt)) as ck.
destruct ck as [csk | cf]; spc;[].
pose proof (Hind _ csk H1c H1v eq_refl) as XX; exrepnd.
destruct csk as [sckv|?| csko csklbt]; [inverts Hck; fail| |].
{ csunf Hck; allsimpl; ginv.
eexists; dands; eauto; try omega. }
dopid csko as [cskoc| cskon | cskexc | cskabs] Case.
+ Case "Can".
simpl in Hck. inverts Hck. exists j; sp. omega.
+ Case "NCan".
exists (S j). dands;[|omega]. simpl. rw XX1.
destruct a; allsimpl.
* unfold isinteger in H1v; exrepnd; subst; allunfold @mk_integer.
rw @compute_step_ncompop_ncan2;rw Hck.
dcwf h;tcsp.
* unfold ispk in H1v; exrepnd; subst; allrw @pk2term_eq.
rw @compute_step_ncompop_ncan2;rw Hck.
autorewrite with slow; tcsp.
+ Case "Exc".
rw @compute_step_exception in Hck; sp; inversion Hck; subst; GC.
exists j; sp; omega.
+ Case "Abs".
exists (S j). dands;[|omega]. simpl. rw XX1.
csunf Hck; allsimpl.
destruct a; allsimpl.
* unfold isinteger in H1v; exrepnd; subst; allunfold @mk_integer.
rw @compute_step_ncompop_abs2; allsimpl; rw Hck; auto.
* unfold ispk in H1v; exrepnd; subst; allrw @pk2term_eq.
rw @compute_step_ncompop_abs2;rw Hck.
autorewrite with slow; tcsp.
Qed.
Lemma reduce_to_prinargs_arith {p} :
forall lib a ntp1 ntp2 lbt ntpv1 ntpc2,
computes_to_value lib ntp1 ntpv1
-> isinteger ntpv1
-> @reduces_to p lib ntp2 ntpc2
-> reduces_to lib (oterm (NCan (NArithOp a))
((bterm [] ntp1)::((bterm [] ntp2)::lbt)))
(oterm (NCan (NArithOp a))
((bterm [] ntpv1)::((bterm [] ntpc2)::lbt))).
Proof.
introv H1c isi H2c.
repnud H2c. repnud H1c. repnud H1c0. exrepnd.
eapply @computes_steps_prinargs_arith with (lbt:=lbt)
(a:=a) (ntpc1:= ntpv1) (ntpc2:= ntpc2) in H1c1; exrepnd; eauto.
unfolds_base; exists j; eauto.
Qed.
(* %\noindent% The following lemma is also a consequence of the fact
that the first argument is always principal
*)
Lemma reduce_to_prinargs_comp {p} :
forall lib a ntp1 ntp2 lbt ntpv1 ntpc2,
computes_to_value lib ntp1 ntpv1
-> iswfpk a ntpv1
-> @reduces_to p lib ntp2 ntpc2
-> reduces_to lib (oterm (NCan (NCompOp a))
((bterm [] ntp1)::((bterm [] ntp2)::lbt)))
(oterm (NCan (NCompOp a))
((bterm [] ntpv1)::((bterm [] ntpc2)::lbt))).
Proof.
introv H1c isw H2c.
repnud H2c. repnud H1c. repnud H1c0. exrepnd.
eapply @computes_steps_prinargs_comp with (lbt:=lbt)
(a:=a) (ntpc1:= ntpv1) (ntpc2:= ntpc2) in H1c1; exrepnd; eauto.
unfolds_base; exists j; eauto.
Qed.
Ltac decomp_progh :=allunfold mk_apply;
match goal with
| [ H1 : (computes_to_value ?lib ?tl _), H2 : (isprogram ?t1) |- _ ] =>
let Hf := fresh H1 H2 "pr" in
pose proof (preserve_program lib _ _ H1 H2) as Hf; hide_hyp H1
| [ H1 : (compute_at_most_k_steps ?lib _ ?tl = csuccess _), H2 : (isprogram ?t1) |- _ ] =>
let Hf := fresh H1 H2 "pr" in
pose proof (computek_preserves_program lib _ _ _ H1 H2) as Hf; hide_hyp H1
| [ H : isprogram (oterm _ _) |- _ ] => let Hf := fresh H "bts" in
pose proof (isprogram_ot_implies_eauto2 _ _ H) as Hf; simpl in Hf;
hide_hyp H
| [ H: (forall _:nat, (_< ?m) -> isprogram_bt _) |- _ ] =>
fail_if_not_number m;
(let XXX:= fresh H "0bt" in
assert (0<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps);
try (let XXX:= fresh H "1bt" in
assert (1<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps);
try (let XXX:= fresh H "2bt" in
assert (2<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps);
try (let XXX:= fresh H "3bt" in
assert (3<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps); clear H
| [ H : isprogram_bt (bterm [] ?lbt) |- _ ] => apply isprogram_bt_nobnd in H
end.
Ltac make_reduces_to Hyp :=
let Hf := fresh Hyp "rd" in
let T:= type of Hyp in
match T with
compute_at_most_k_steps ?lib ?m ?tl = csuccess ?tc =>
assert (reduces_to lib tl tc) as Hf by (exists m; trivial)
end.
Ltac reduces_to_step Hyp :=
let T:= type of Hyp in
match T with
reduces_to ?lib _ ?tr =>
let TRS := eval simpl in
(compute_step lib tr) in
match TRS with
| csuccess ?trs => apply reduces_to_if_split1 with (v:=trs) in Hyp;[|simpl;auto;fail]
| _ => idtac "RHS did not compute to csuccess _ in 1 step, It computed to: " TRS ;fail
end
end.
Ltac decomp_progc2 := unfold_all_mk; let Hlt := fresh "Hltpc" in
match goal with
| [ |- isprogram (oterm _ ?lbt)] => try trivial;apply isprogram_ot_if_eauto2;repeat( simpl_list);[spc|]
| [ |- forall _, _ < _ -> isprogram_bt _ _ ] => introv Hlt;repeat(simpl_list);repeat(dlt Hlt)
| [ |- context[map num_bvars (map (fun _:_ => lsubst_bterm_aux _ _) _ )]] => try rewrite map_num_bvars_bterms
| [ |- isprogram_bt (bterm [] ?lbt)] => apply implies_isprogram_bt0
end .
Ltac decomp_progh2 :=allunfold mk_apply;
match goal with
| [ H1 : (computes_to_value _ ?tl _), H2 : (isprogram ?t1) |- _ ] =>
let Hf := fresh H1 H2 "pr" in
pose proof (preserve_program _ _ _ H1 H2) as Hf; hide_hyp H1
| [ H1 : (compute_at_most_k_steps _ _ ?tl = csuccess _), H2 : (isprogram ?t1) |- _ ] =>
let Hf := fresh H1 H2 "pr" in
pose proof (computek_preserves_program _ _ _ _ H1 H2) as Hf; hide_hyp H1
| [ H : isprogram (oterm _ _) |- _ ] => let Hf := fresh H "bts" in
pose proof (isprogram_ot_implies_eauto2 _ _ H) as Hf; simpl in Hf;
allrw map_length;
hide_hyp H
| [ H: (forall _:nat, (_< ?m) -> isprogram_bt _) |- _ ] =>
(let XXX:= fresh H "0bt" in
assert (0<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps);
try (let XXX:= fresh H "1bt" in
assert (1<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps);
try (let XXX:= fresh H "2bt" in
assert (2<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps);
try (let XXX:= fresh H "3bt" in
assert (3<m) as XXX by omega; apply H in XXX;
unfold selectbt in XXX; simphyps); clear H
| [ H : isprogram_bt (bterm [] ?lbt) |- _ ] => apply isprogram_bt_nobnd in H
end.
(** exclude the trivial nop step when the input was
already canonical. This notion is what Crary's right arrow(|->) means
See Proposition 4.2. He says that for canonical terms
are not allowed at the LHS of this relation*)
Inductive computes_in_1step {p} : @library p -> @NTerm p -> @NTerm p -> [univ] :=
| c1step_nc :
forall lib (no: NonCanonicalOp) (lbt : list BTerm) (tc : NTerm),
compute_step lib (oterm (NCan no) lbt) = csuccess tc
-> computes_in_1step lib (oterm (NCan no) lbt) tc
| c1step_ab :
forall lib (x: opabs) (lbt : list BTerm) (tc : NTerm),
compute_step lib (oterm (Abs x) lbt) = csuccess tc
-> computes_in_1step lib (oterm (Abs x) lbt) tc.
Lemma computes_in_1step_prinarg {p} :
forall lib op ntp ntpc lbt,
@computes_in_1step p lib ntp ntpc
-> computes_in_1step lib (oterm (NCan op) ((bterm [] ntp)::lbt))
(oterm (NCan op) ((bterm [] ntpc)::lbt)).
Proof.
introv Hc.
invertsn Hc; constructor; simpl in Hc; csunf; simpl; rw Hc; sp.
Qed.
Theorem compute_1step_alpha {p} :
forall lib (t1 t2 t1' : @NTerm p),
nt_wf t1
-> alpha_eq t1 t2
-> computes_in_1step lib t1 t1'
-> { t2':@NTerm p & computes_in_1step lib t2 t2' # alpha_eq t1' t2'}.
Proof.
introv wf Hal Hc.
dup Hal as aeq.
invertsn Hc; apply alpha_eq_oterm_implies_combine in aeq; exrepnd; subst;
eapply compute_step_alpha in Hal; eauto; exrepnd;
eexists; dands; try constructor; eauto.
Qed.
Lemma computes_in_1step_program {p} : forall lib t1 t2,
@computes_in_1step p lib t1 t2
-> isprogram t1
-> isprogram t2.
Proof.
introv Hc.
invertsn Hc; introv Hp; eauto with slow.
Qed.
Definition computes_step_to_error {p} lib (t : @NTerm p) :=
match compute_step lib t with
| csuccess _ => False
| cfailure _ _ => True
end.
Definition computes_in_1step_alpha {p} lib (t1 t2 : @NTerm p):=
{t2a : NTerm $ computes_in_1step lib t1 t2a # alpha_eq t2 t2a}.
Hint Resolve computes_in_1step_program : slow.
Lemma computes_in_1step_alpha2 {o} :
forall lib (e1 e2 e1a e2a : @NTerm o),
nt_wf e1
-> computes_in_1step_alpha lib e1 e2
-> alpha_eq e1 e1a
-> alpha_eq e2 e2a
-> computes_in_1step_alpha lib e1a e2a.
Proof.
introv wf Hc H1a H2a.
invertsn Hc.
repnd.
apply (compute_1step_alpha _ _ _ _ wf H1a) in Hc0.
exrepnd.
unfolds_base.
eexists; eauto with slow.
Qed.
Ltac destruct_cstep Hyp cs :=
match type of Hyp with
context[ compute_step ?lib ?c] =>
remember (compute_step lib c) as cs;
let css := fresh cs "s" in
let csf := fresh cs "f" in
destruct cs as [css | csf]
end.
Ltac fold_compute_step t Hyp:=
let XX := fresh "XX" in
let tc := eval simpl in
(compute_step t) in
assert(tc=compute_step t) as XX by refl; rewrite XX in Hyp; clear XX.
Lemma compute_1step_eq {p} : forall lib t1 t2 t3,
@computes_in_1step p lib t1 t2
-> computes_in_1step lib t1 t3
-> t2=t3.
Proof.
introv H1c H2c.
invertsn H1c; invertsn H2c; congruence.
Qed.
Lemma compute_1step_alpha2 {o} :
forall lib (a1 a2 b1 b2 : @NTerm o),
nt_wf a1
-> alpha_eq a1 a2
-> computes_in_1step lib a1 b1
-> computes_in_1step lib a2 b2
-> alpha_eq b1 b2.
Proof.
introv wf Hal H1c H2c.
eapply compute_1step_alpha in Hal; eauto.
exrepnd.
assert (t2'=b2);[| congruence].
eapply compute_1step_eq; eauto.
Qed.
Inductive computes_in_kstep_alpha {p} : @library p -> nat -> @NTerm p -> @NTerm p -> [univ]:=
|ckainit : forall lib t1 t2, alpha_eq t1 t2 -> computes_in_kstep_alpha lib 0 t1 t2
|ckacons : forall lib k t1 t2 t3 ,
computes_in_1step_alpha lib t1 t2
-> computes_in_kstep_alpha lib k t2 t3
-> computes_in_kstep_alpha lib (S k) t1 t3.
Inductive computes_in_kstep {p} : @library p -> nat -> @NTerm p -> @NTerm p -> [univ]:=
|ckinit : forall lib t , computes_in_kstep lib 0 t t
|ckcons : forall lib k t1 t2 t3 ,
computes_in_1step lib t1 t2
-> computes_in_kstep lib k t2 t3
-> computes_in_kstep lib (S k) t1 t3.
Definition computes_to_alpha_value {p} lib (t1 t2 : @NTerm p) :=
{t2a : NTerm $ computes_to_value lib t1 t2a # alpha_eq t2a t2}.
Lemma noncan_tricot {p} : forall lib no lbt,
isprogram (oterm (NCan no) lbt)
-> { v : @NTerm p
$ compute_step lib (oterm (NCan no) lbt) = csuccess v
# isprogram v
# (isvalue v [+] isnoncan v [+] isexc v [+] isabs v [+] isseq v) }
[+] computes_step_to_error lib (oterm (NCan no) lbt).
Proof.
introv Hpr.
unfold computes_step_to_error.
remember (compute_step lib (oterm (NCan no) lbt)) as cs.
destruct cs as [csk | cnk]; auto.
left.
eexists; dands; eauto with slow.
apply isprogram_noncan; eauto with slow.
Qed.
Lemma noncan_tricot_abs {p} :
forall (lib : @library p) ab lbt,
isprogram (oterm (Abs ab) lbt)
-> { v : @NTerm p
$ compute_step lib (oterm (Abs ab) lbt) = csuccess v
# isprogram v
# (isvalue v [+] isnoncan v [+] isexc v [+] isabs v [+] isseq v) }
[+] computes_step_to_error lib (oterm (Abs ab) lbt).
Proof.
introv Hpr.
unfold computes_step_to_error.
remember (compute_step lib (oterm (Abs ab) lbt)) as cs.
destruct cs as [csk | cnk]; auto.
left.
eexists ; dands; eauto with slow.
apply isprogram_noncan; eauto with slow.
Qed.
Lemma isprogram_error {p} : forall lib td,
@isprogram p td
-> computes_step_to_error lib td
-> isnoncan td [+] isabs td.
Proof.
introv Hpr Hce. repnud Hpr.
destruct td as [?|?| o ?]; invertsn Hpr0.
- repnud Hce; csunf Hce; allsimpl; tcsp.
- repnud Hce.
destruct o; allsimpl; cpx.
Qed.
Lemma computes_in_1step_alpha_r {o} :
forall lib (tl1 tl2 tr1 tr2 : @NTerm o),
nt_wf tl1
-> computes_in_1step_alpha lib tl1 tr1
-> computes_in_1step_alpha lib tl2 tr2
-> alpha_eq tl1 tl2
-> alpha_eq tr1 tr2.
Proof.
introv wf H1ca H2ca Hal.
invertsn H1ca.
invertsn H2ca.
repnd.
eapply compute_1step_alpha2 in H2ca0;
[ | | |exact H1ca0]; eauto 4 with slow.
Qed.
Lemma computes_in_kstep_fun_l {o} :
forall lib k (tl1 tl2 tr : @NTerm o),
nt_wf tl1
-> alpha_eq tl1 tl2
-> computes_in_kstep_alpha lib k tl1 tr
-> computes_in_kstep_alpha lib k tl2 tr.
Proof.
induction k; introv wf Hal H1ck; inverts H1ck as Hstep H1ck; econstructor; eauto with slow;[].
eapply (computes_in_1step_alpha2 _ _ _ _ _ wf Hstep) in Hal; eauto.
Qed.
Hint Constructors computes_in_kstep : slow.
Lemma computes_in_1step_noncan_or_abs {p} : forall lib t1 t2,
@computes_in_1step p lib t1 t2
-> isnoncan t1 [+] isabs t1.
Proof.
introv Hcs.
inverts Hcs; simpl; auto.
Qed.
Lemma computes_in_1step_lsubst {p} : forall lib e t1 t2 vy,
computes_in_1step lib (@lsubst p e [(vy, t1)]) (lsubst e [(vy, t2)])
-> isnoncan t1
-> isnoncan t2
-> isnoncan (lsubst e [(vy, t2)]) [+] isabs (lsubst e [(vy, t2)]).
Proof.
introv H1c H1n H2n.
apply computes_in_1step_noncan_or_abs in H1c.
eapply noncan_or_abs_lsubst; eauto.
Qed.
Lemma computes_in_1step_to_alpha {p} : forall lib t1 t2,
@computes_in_1step p lib t1 t2
-> computes_in_1step_alpha lib t1 t2.
Proof.
intros.
econstructor; dands; eauto.
Qed.
Lemma compute_step_dicot {p} : forall lib e esk,
csuccess esk = @compute_step p lib e
-> (e = esk # isvalue_like esk)
[+]
computes_in_1step lib e esk.
Proof.
introv Hcs.
destruct e as [|?| oo lbt]; invertsn Hcs.
{ left; dands; eauto 3 with slow. }
dopid oo as [c|nc|exc|abs] Case;
csunf Hcs; allsimpl; ginv; tcsp;
try (complete (right; constructor; csunf; auto));
try (complete (left; sp; eauto with slow)).
Qed.
Lemma computes_to_value_step {p} :
forall lib (t1 t2 t3 : @NTerm p),
computes_to_value lib t2 t3
-> compute_step lib t1 = csuccess t2
-> computes_to_value lib t1 t3.
Proof.
introv Hcv Hcs.
invertsn Hcv.
apply reduces_to_if_step in Hcs.
eapply reduces_to_trans in Hcv; eauto.
split; auto.
Qed.
Hint Resolve computes_to_value_isvalue_refl: slow.
Lemma computes_in_1step_preserves_nt_wf {p} :
forall lib (t u : @NTerm p),
computes_in_1step lib t u
-> nt_wf t
-> nt_wf u.
Proof.
introv comp wf.
inversion comp as [? ? ? ? comp1|? ? ? ? comp1]; repnd; subst; clear comp;
apply preserve_nt_wf_compute_step in comp1; auto.
Qed.
Lemma computes_in_1step_alpha_preserves_nt_wf {p} :
forall lib (t u : @NTerm p),
computes_in_1step_alpha lib t u
-> nt_wf t
-> nt_wf u.
Proof.
introv comp wf.
inversion comp as [? xx]; repnd.
apply computes_in_1step_preserves_nt_wf in xx0; auto.
apply alphaeq_preserves_wf in xx; apply xx; auto.
Qed.
Lemma computes_in_kstep_alpha2 {p} :
forall lib k (t tv : @NTerm p),
nt_wf t
-> computes_in_kstep_alpha lib k t tv
-> isvalue tv
-> computes_to_alpha_value lib t tv.
Proof.
induction k as [ | k Hind]; introv wf Hcka Hisv; unfolds_base.
- invertsn Hcka. eexists; dands; eauto with slow.
- inverts Hcka as HH HHH.
applydup @computes_in_1step_alpha_preserves_nt_wf in HH as wf2; auto.
apply Hind in HHH; auto.
invertsn HHH. repnd.
invertsn HH.
repnd.
eapply compute_to_value_alpha in HH; eauto.
exrepnd.
rename HHH0 into Hcv.
invertsn HH0;
exists t2'; dands; eauto 3 with slow;
eapply computes_to_value_step; eauto.
Qed.
Lemma computes_to_value_in_max_k_steps_xx {p} :
forall lib m (t1 t2 : @NTerm p),
computes_to_value_in_max_k_steps lib m t1 t2
-> computes_to_value lib t1 t2.
Proof.
introv Hcm.
repnud Hcm.
constructor; auto.
eexists; eauto.
Qed.
Lemma computes_step_to_error_no_further {p} :
forall lib (t : @NTerm p),
computes_step_to_error lib t
-> forall tv k, computes_in_kstep_alpha lib (S k) t tv
-> False.
Proof.
unfold computes_step_to_error.
introv Hce Hcs.
invertsna Hcs Hcs.
invertsn Hcs.
exrepnd.
invertsn Hcs1; rw Hcs1 in Hce; cpx.
Qed.
Lemma computes_in_1step_alpha_program {p} :
forall lib (t1 t2 : @NTerm p),
computes_in_1step_alpha lib t1 t2
-> isprogram t1
-> isprogram t2.
Proof.
introv Hc1a H1p.
invertsn Hc1a. repnd.
apply computes_in_1step_program in Hc1a0; auto.
apply alpha_eq_sym in Hc1a.
eauto with slow.
Qed.
Lemma computes_to_value_wf4 {p} :
forall lib (x y : @NTerm p),
computes_to_value lib x y -> nt_wf y.
Proof.
introv Hc.
repnud Hc.
invertsn Hc.
repnud Hc.
auto.
Qed.
Lemma compute_xxx {p} :
forall lib (t v : @NTerm p),
computes_to_value lib t v
-> { k: nat $ computes_to_value_in_max_k_steps lib k t v}.
Proof.
introv Hcv.
unfold computes_to_value, reduces_to in Hcv.
exrepnd. exists k. unfolds_base.
sp.
Qed.
Definition hasvaluew {o} lib (t : @NTerm o) :=
nt_wf t -> hasvalue lib t.
Lemma r1alhasvalue {p} :
forall lib, respects1 alpha_eq (@hasvaluew p lib).
Proof.
introv H1 H2 wf.
allunfold @hasvaluew.
allunfold @hasvalue.
applydup @alphaeq_preserves_wf in H1 as q; applydup q in wf; clear q.
autodimp H2 hyp; exrepnd.
eapply compute_to_value_alpha in H1; eauto.
exrepnd.
eexists; eauto.
Qed.
Hint Resolve r1alhasvalue : respects.
Lemma hasvalue_implies_hasvaluew {o} :
forall lib (t : @NTerm o),
hasvalue lib t
-> hasvaluew lib t.
Proof.
introv hv w; auto.
Qed.
Lemma hasvaluew_implies_hasvalue {o} :
forall lib (t : @NTerm o),
nt_wf t
-> hasvaluew lib t
-> hasvalue lib t.
Proof. sp. Qed.
(*
Lemma if_hasvalue_applyx {p} :
forall lib f a,
isprog f
-> isprog a
-> hasvalue lib (mk_apply f a)
-> {b : @NTerm p
& computes_to_alpha_value lib f (mk_lam nvarx b)
# hasvalue lib (subst b nvarx a)}
[+] {s : nseq
& {n : nat
& computes_to_value lib f (mk_nseq s)
# computes_to_value lib a (mk_nat n) }}
[+] {s : ntseq
& {n : nat
& computes_to_value lib f (mk_ntseq s)
# computes_to_value lib a (mk_nat n)
# hasvalue lib (s n) }}.
Proof.
introv H1p H2p Hv.
apply if_hasvalue_apply in Hv; auto;[].
repndors; exrepnd; auto.
- left.
allrw @isprog_eq.
duplicate Hv0 as Hcv.
repnud Hv0.
invertsn Hv0.
apply isprogram_ot_iff in Hv0.
repnd.
allsimpl.
dLin_hyp.
allunfold @num_bvars; allsimpl; GC.
dimp (alpha_eq_bterm_single_change2 b v nvarx).
rename hyp into Hal.
match type of Hal with
alpha_eq_bterm _ (bterm _ ?nt) => exists nt
end.
duplicate Hal as Halb.
apply apply_bterm_alpha_congr2 with (lnt:=[a]) in Hal ; auto;[].
allunfold @subst.
allunfold @apply_bterm.
allsimpl.
apply hasvalue_implies_hasvaluew in Hv1.
rwhg Hal Hv1.
applydup @isprogram_bt_iff_isprog_vars in Hyp as isp.
apply isprog_vars_eq in isp; repnd.
apply hasvaluew_implies_hasvalue in Hv1;
[|apply lsubst_wf_if_eauto;
[apply wf_sub_cons;eauto 3 with slow|
apply lsubst_wf_if_eauto; eauto 3 with slow
]
].
dands; auto.
unfolds_base.
exists (mk_lam v b).
dands; auto.
repeat(prove_alpha_eq4); auto.
- right; left; eexists; eexists; dands; eauto.
SearchAbout hasvalue mk_apseq.
-
Qed.
*)
Lemma reduces_to_hasvalue {p} :
forall lib (t1 t2 : @NTerm p),
reduces_to lib t1 t2
-> hasvalue lib t2
-> hasvalue lib t1.
Proof.
introns X.
allunfold @hasvalue.
exrepnd.
exists t'.
allunfold @computes_to_value.
exrepnd. dands; auto;[].
eauto using reduces_to_trans.
Qed.
(*
apply compute_step_atmost_exact in Xc2. exrepnd.
eapply reduces_in_k_steps_alpha in Xc1; eauto. exrepnd.
repnud Xc1. apply compute_step_exact_implies_atmost in Xc1.
exists t2'. split; auto;[].
unfold computes_to_value, reduces_to. split; [eexists; eauto|];[].
apply alpha_preserves_value in Xc3; auto.
Qed.
*)
Lemma computes_to_value_exception {p} :
forall lib a (e v : @NTerm p),
computes_to_value lib (mk_exception a e) v
-> False.
Proof.
introv comp.
destruct comp.
apply reduces_to_exception in r; subst; tcsp.
apply isvalue_exc in i; sp.
Qed.
Lemma computes_to_exception_exception {p} :
forall lib a b (e v : @NTerm p),
computes_to_exception lib a (mk_exception b e) v
-> v = e # a = b.
Proof.
introv comp.
destruct comp.
unfold reduces_in_atmost_k_steps in r.
unfold mk_exception in r.
rw @compute_at_most_k_steps_exception in r.
inversion r; subst; sp.
Qed.
Lemma computes_to_exception_refl {p} :
forall lib a (e : @NTerm p),
computes_to_exception lib a (mk_exception a e) e.
Proof.
introv.
unfold computes_to_exception, reduces_to, reduces_in_atmost_k_steps.
exists 0; simpl; auto.
Qed.
Lemma norep_disjoint_implies_nr_ut_sub {o} :
forall sub (t : @NTerm o) u,
no_repeats (get_utokens_sub sub)
-> disjoint (get_utokens_sub sub) (get_utokens t)
-> nr_ut_sub u sub
-> nr_ut_sub t sub.
Proof.
induction sub; introv norep disj nrut; allsimpl; auto.
destruct a as [l w].
allrw @get_utokens_sub_cons.
allrw disjoint_app_l; repnd.
allrw no_repeats_app; repnd.
allrw @nr_ut_sub_cons_iff; exrepnd; subst; allsimpl.
allrw disjoint_singleton_l.
eexists; dands; eauto.
eapply IHsub; eauto.
eapply disjoint_eqset_r;[apply eqset_sym;apply get_utokens_subst|].
allrw disjoint_app_r; dands; auto.
boolvar; simpl; auto.
apply disjoint_singleton_r; auto.
Qed.
Lemma reduces_in_atmost_k_steps_change_utok_sub {o} :
forall lib k (t u : @NTerm o) sub sub',
nt_wf t
-> reduces_in_atmost_k_steps lib (lsubst t sub) u k
-> nr_ut_sub t sub
-> nr_ut_sub t sub'
-> dom_sub sub = dom_sub sub'
-> disjoint (get_utokens_sub sub) (get_utokens t)
-> disjoint (get_utokens_sub sub') (get_utokens t)
-> {w : NTerm
& {s : NTerm
& alpha_eq u (lsubst w sub)
# disjoint (get_utokens_sub sub) (get_utokens w)
# subvars (free_vars w) (free_vars t)
# subset (get_utokens w) (get_utokens t)
# reduces_in_atmost_k_steps lib (lsubst t sub') s k
# alpha_eq s (lsubst w sub')}}.
Proof.
induction k; introv wf comp nrut1 nrut2 eqdoms d1 d2.
- allrw @reduces_in_atmost_k_steps_0; subst.
exists t (lsubst t sub'); dands; eauto 3 with slow.
rw @reduces_in_atmost_k_steps_0; auto.
- allrw @reduces_in_atmost_k_steps_S; exrepnd.
pose proof (compute_step_subst_utoken lib t u0 sub) as h.
allsimpl; allrw disjoint_app_r; repnd.
repeat (autodimp h hyp); exrepnd.
pose proof (h0 sub') as p; repeat (autodimp p hyp); clear h0; exrepnd.
applydup @compute_step_preserves in comp1 as wfu; repnd;
[|apply lsubst_wf_if_eauto; eauto 3 with slow];[].
applydup @alphaeq_preserves_wf in h1 as q.
applydup q in wfu as wfw; clear q.
apply lsubst_wf_iff in wfw; eauto 3 with slow;[].
pose proof (reduces_in_atmost_k_steps_alpha
lib u0 (lsubst w sub) wfu h1 k u comp0) as comp'.
exrepnd.
pose proof (IHk w t2' sub sub' wfw comp'1) as q; clear IHk.
repeat (autodimp q hyp); eauto 4 with slow.
exrepnd.
pose proof (reduces_in_atmost_k_steps_alpha
lib (lsubst w sub') s) as c.
repeat (autodimp c hyp); eauto 4 with slow.
pose proof (c k s0 q5) as comp'; clear c; exrepnd.
exists w0 t2'0; dands; eauto with slow.
rw @reduces_in_atmost_k_steps_S.
exists s; dands; auto.
Qed.
Lemma iscan_sterm {o} :
forall (f : @ntseq o), iscan (sterm f).
Proof.
introv; simpl; auto.
Qed.
Hint Resolve iscan_sterm : slow.
Lemma is_can_or_exc_sterm {o} :
forall (f : @ntseq o), is_can_or_exc (sterm f).
Proof.
introv; left; eauto 3 with slow.
Qed.
Hint Resolve is_can_or_exc_sterm : slow.
(* end hide *)
(* begin hide *)
|
// (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:fifo_generator:13.1
// IP Revision: 2
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module ARM_FIFO_in (
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_rst_busy,
rd_rst_busy
);
input wire rst;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 write_clk CLK" *)
input wire wr_clk;
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 read_clk CLK" *)
input wire rd_clk;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
input wire [15 : 0] din;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
input wire wr_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
input wire rd_en;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
output wire [31 : 0] dout;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
output wire full;
(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
output wire empty;
output wire [9 : 0] rd_data_count;
output wire wr_rst_busy;
output wire rd_rst_busy;
fifo_generator_v13_1_2 #(
.C_COMMON_CLOCK(0),
.C_SELECT_XPM(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(16),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(32),
.C_ENABLE_RLOCS(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx18"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(1),
.C_USE_PIPELINE_REG(0),
.C_POWER_SAVING_MODE(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(11),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_EN_SAFETY_CKT(1),
.C_ERROR_INJECTION_TYPE(0),
.C_SYNCHRONIZER_STAGE(8),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(1),
.C_HAS_AXI_ID(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(1),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(1),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(8),
.C_AXIS_TID_WIDTH(1),
.C_AXIS_TDEST_WIDTH(1),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(1),
.C_AXIS_TKEEP_WIDTH(1),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_PRIM_FIFO_TYPE_WACH("512x36"),
.C_PRIM_FIFO_TYPE_WDCH("1kx36"),
.C_PRIM_FIFO_TYPE_WRCH("512x36"),
.C_PRIM_FIFO_TYPE_RACH("512x36"),
.C_PRIM_FIFO_TYPE_RDCH("1kx36"),
.C_PRIM_FIFO_TYPE_AXIS("1kx18"),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_WACH(1),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) inst (
.backup(1'D0),
.backup_marker(1'D0),
.clk(1'D0),
.rst(rst),
.srst(1'D0),
.wr_clk(wr_clk),
.wr_rst(1'D0),
.rd_clk(rd_clk),
.rd_rst(1'D0),
.din(din),
.wr_en(wr_en),
.rd_en(rd_en),
.prog_empty_thresh(9'B0),
.prog_empty_thresh_assert(9'B0),
.prog_empty_thresh_negate(9'B0),
.prog_full_thresh(10'B0),
.prog_full_thresh_assert(10'B0),
.prog_full_thresh_negate(10'B0),
.int_clk(1'D0),
.injectdbiterr(1'D0),
.injectsbiterr(1'D0),
.sleep(1'D0),
.dout(dout),
.full(full),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(empty),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(rd_data_count),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.wr_rst_busy(wr_rst_busy),
.rd_rst_busy(rd_rst_busy),
.m_aclk(1'D0),
.s_aclk(1'D0),
.s_aresetn(1'D0),
.m_aclk_en(1'D0),
.s_aclk_en(1'D0),
.s_axi_awid(1'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awlock(1'B0),
.s_axi_awcache(4'B0),
.s_axi_awprot(3'B0),
.s_axi_awqos(4'B0),
.s_axi_awregion(4'B0),
.s_axi_awuser(1'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wid(1'B0),
.s_axi_wdata(64'B0),
.s_axi_wstrb(8'B0),
.s_axi_wlast(1'D0),
.s_axi_wuser(1'B0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_buser(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'D0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'D0),
.m_axi_bid(1'B0),
.m_axi_bresp(2'B0),
.m_axi_buser(1'B0),
.m_axi_bvalid(1'D0),
.m_axi_bready(),
.s_axi_arid(1'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arlock(1'B0),
.s_axi_arcache(4'B0),
.s_axi_arprot(3'B0),
.s_axi_arqos(4'B0),
.s_axi_arregion(4'B0),
.s_axi_aruser(1'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'D0),
.m_axi_rid(1'B0),
.m_axi_rdata(64'B0),
.m_axi_rresp(2'B0),
.m_axi_rlast(1'D0),
.m_axi_ruser(1'B0),
.m_axi_rvalid(1'D0),
.m_axi_rready(),
.s_axis_tvalid(1'D0),
.s_axis_tready(),
.s_axis_tdata(8'B0),
.s_axis_tstrb(1'B0),
.s_axis_tkeep(1'B0),
.s_axis_tlast(1'D0),
.s_axis_tid(1'B0),
.s_axis_tdest(1'B0),
.s_axis_tuser(4'B0),
.m_axis_tvalid(),
.m_axis_tready(1'D0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'D0),
.axi_aw_injectdbiterr(1'D0),
.axi_aw_prog_full_thresh(4'B0),
.axi_aw_prog_empty_thresh(4'B0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'D0),
.axi_w_injectdbiterr(1'D0),
.axi_w_prog_full_thresh(10'B0),
.axi_w_prog_empty_thresh(10'B0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectsbiterr(1'D0),
.axi_b_injectdbiterr(1'D0),
.axi_b_prog_full_thresh(4'B0),
.axi_b_prog_empty_thresh(4'B0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectsbiterr(1'D0),
.axi_ar_injectdbiterr(1'D0),
.axi_ar_prog_full_thresh(4'B0),
.axi_ar_prog_empty_thresh(4'B0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'D0),
.axi_r_injectdbiterr(1'D0),
.axi_r_prog_full_thresh(10'B0),
.axi_r_prog_empty_thresh(10'B0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectsbiterr(1'D0),
.axis_injectdbiterr(1'D0),
.axis_prog_full_thresh(10'B0),
.axis_prog_empty_thresh(10'B0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty()
);
endmodule
|
`define MSBI 9 // Most significant Bit of DAC input
// this is a delta-sigma digital to analog converter
module dac (o, i, clock, reset);
output o; // this is the average output that feeds low pass filter
input [`MSBI:0] i; // dac input (excess 2**msbi)
input clock;
input reset;
reg o; // for optimum performance, ensure that this ff is in IOB
reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
reg [`MSBI+2:0] SigmaLatch = 1'b1 << (`MSBI+1); // Latches output of Sigma adder
reg [`MSBI+2:0] DeltaB; // B input of Delta adder
always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
always @(i or DeltaB) DeltaAdder = i + DeltaB;
always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
always @(posedge clock or posedge reset)
begin
if(reset)
begin
SigmaLatch <= #1 1'b1 << (`MSBI+1);
o <= #1 1'b0;
end
else
begin
SigmaLatch <= #1 SigmaAdder;
o <= #1 SigmaLatch[`MSBI+2];
end
end
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// This module is a wrapper for the soft IP NextGen controller and the MMR
// This file is only used for the ALTMEMPHY flow
//////////////////////////////////////////////////////////////////////////////
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
//
module nios_altmemddr_0_alt_mem_ddrx_controller_top(
clk,
half_clk,
reset_n,
local_ready,
local_write,
local_read,
local_address,
local_byteenable,
local_writedata,
local_burstcount,
local_beginbursttransfer,
local_readdata,
local_readdatavalid,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_autopch_req,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest
);
//////////////////////////////////////////////////////////////////////////////
// << START MEGAWIZARD INSERT GENERICS
// Inserted Generics
localparam MEM_TYPE = "DDR2";
localparam LOCAL_SIZE_WIDTH = 3;
localparam LOCAL_ADDR_WIDTH = 24;
localparam LOCAL_DATA_WIDTH = 32;
localparam LOCAL_BE_WIDTH = 4;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 14;
localparam MEM_IF_ROW_WIDTH = 14;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 2;
localparam MEM_IF_DQS_WIDTH = 1;
localparam MEM_IF_DQ_WIDTH = 8;
localparam MEM_IF_DM_WIDTH = 1;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 4;
localparam CTL_LOOK_AHEAD_DEPTH = 4;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 0;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CSR_BE_WIDTH = 4;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 5;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 4;
localparam MEM_TRRD = 2;
localparam MEM_TFAW = 5;
localparam MEM_TRFC = 14;
localparam MEM_TREFI = 911;
localparam MEM_TRCD = 2;
localparam MEM_TRP = 2;
localparam MEM_TWR = 2;
localparam MEM_TWTR = 2;
localparam MEM_TRTP = 2;
localparam MEM_TRAS = 6;
localparam MEM_TRC = 8;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 3;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_RD_TO_PCH_EXTRA_CLK = 0;
localparam CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK = 0;
localparam CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK = 0;
localparam CTL_ECC_MULTIPLES_16_24_40_72 = 1;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
localparam LOCAL_ID_WIDTH = 8;
localparam LOCAL_CS_WIDTH = 0;
localparam CTL_TBP_NUM = 4;
localparam WRBUFFER_ADDR_WIDTH = 6;
localparam RDBUFFER_ADDR_WIDTH = 7;
localparam MEM_IF_CHIP = 1;
localparam MEM_IF_BANKADDR_WIDTH = 2;
localparam MEM_IF_DWIDTH = 8;
localparam MAX_MEM_IF_CS_WIDTH = 30;
localparam MAX_MEM_IF_CHIP = 4;
localparam MAX_MEM_IF_BANKADDR_WIDTH = 3;
localparam MAX_MEM_IF_ROWADDR_WIDTH = 16;
localparam MAX_MEM_IF_COLADDR_WIDTH = 12;
localparam MAX_MEM_IF_ODT_WIDTH = 1;
localparam MAX_MEM_IF_DQS_WIDTH = 5;
localparam MAX_MEM_IF_DQ_WIDTH = 40;
localparam MAX_MEM_IF_MASK_WIDTH = 5;
localparam MAX_LOCAL_DATA_WIDTH = 80;
localparam CFG_TYPE = 'b001;
localparam CFG_INTERFACE_WIDTH = 8;
localparam CFG_BURST_LENGTH = 'b01000;
localparam CFG_DEVICE_WIDTH = 1;
localparam CFG_REORDER_DATA = 0;
localparam CFG_DATA_REORDERING_TYPE = "INTER_BANK";
localparam CFG_STARVE_LIMIT = 10;
localparam CFG_ADDR_ORDER = 'b00;
localparam CFG_TCCD = 2;
localparam CFG_SELF_RFSH_EXIT_CYCLES = 200;
localparam CFG_PDN_EXIT_CYCLES = 3;
localparam CFG_POWER_SAVING_EXIT_CYCLES = 5;
localparam CFG_MEM_CLK_ENTRY_CYCLES = 10;
localparam CTL_ENABLE_BURST_INTERRUPT = 0;
localparam CTL_ENABLE_BURST_TERMINATE = 0;
localparam MEM_TMRD_CK = 7;
localparam CFG_GEN_SBE = 0;
localparam CFG_GEN_DBE = 0;
localparam CFG_ENABLE_INTR = 0;
localparam CFG_MASK_SBE_INTR = 0;
localparam CFG_MASK_DBE_INTR = 0;
localparam CFG_MASK_CORRDROP_INTR = 0;
localparam CFG_CLR_INTR = 0;
localparam CFG_WRITE_ODT_CHIP = 'h1;
localparam CFG_READ_ODT_CHIP = 'h0;
localparam CFG_PORT_WIDTH_WRITE_ODT_CHIP = 1;
localparam CFG_PORT_WIDTH_READ_ODT_CHIP = 1;
localparam CFG_ENABLE_NO_DM = 0;
// << END MEGAWIZARD INSERT GENERICS
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_ENABLE_DQS_TRACKING = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 2;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 4;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 9; //case:234203
localparam CFG_PORT_WIDTH_TREFI = 14; //case:234203
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 5; //case:234203
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 6; //case:234203
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_WLAT_BUS_WIDTH = 5;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// KALEN HACK: We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RLAT_WIDTH = 5;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
localparam CFG_MM_ST_CONV_REG = 0;
localparam CFG_ECC_DECODER_REG = 0;
localparam CFG_ERRCMD_FIFO_REG = 0;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Avalon signals
output local_ready;
input local_write;
input local_read;
input [LOCAL_ADDR_WIDTH - 1 : 0] local_address;
input [LOCAL_BE_WIDTH - 1 : 0] local_byteenable;
input [LOCAL_DATA_WIDTH - 1 : 0] local_writedata;
input [LOCAL_SIZE_WIDTH - 1 : 0] local_burstcount;
input local_beginbursttransfer;
output [LOCAL_DATA_WIDTH - 1 : 0] local_readdata;
output local_readdatavalid;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
input local_autopch_req;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire itf_cmd_ready;
wire itf_cmd_valid;
wire itf_cmd;
wire [LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
wire [LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
wire itf_cmd_id;
wire itf_cmd_priority;
wire itf_cmd_autopercharge;
wire itf_cmd_multicast;
wire itf_wr_data_ready;
wire itf_wr_data_valid;
wire [LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
wire [LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
wire itf_rd_data_ready;
wire itf_rd_data_valid;
wire [LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire [2 - 1 : 0] itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// Converter
alt_mem_ddrx_mm_st_converter # (
.AVL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.AVL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.AVL_DATA_WIDTH ( LOCAL_DATA_WIDTH ),
.CFG_MM_ST_CONV_REG ( CFG_MM_ST_CONV_REG )
) mm_st_converter_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.ctl_half_clk ( half_clk ),
.ctl_half_clk_reset_n ( reset_n ),
.avl_ready ( local_ready ),
.avl_read_req ( local_read ),
.avl_write_req ( local_write ),
.avl_size ( local_burstcount ),
.avl_burstbegin ( local_beginbursttransfer ),
.avl_addr ( local_address ),
.avl_rdata_valid ( local_readdatavalid ),
.local_rdata_error ( ),
.avl_rdata ( local_readdata ),
.avl_wdata ( local_writedata ),
.avl_be ( local_byteenable ),
.local_multicast ( local_multicast ),
.local_autopch_req ( local_autopch_req ),
.local_priority ( local_priority ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id )
);
// Next Gen Controller
//////////////////////////////////////////////////////////////////////////////
alt_mem_ddrx_controller_st_top #(
.LOCAL_SIZE_WIDTH(LOCAL_SIZE_WIDTH),
.LOCAL_ADDR_WIDTH(LOCAL_ADDR_WIDTH),
.LOCAL_DATA_WIDTH(LOCAL_DATA_WIDTH),
.LOCAL_BE_WIDTH(LOCAL_BE_WIDTH),
.LOCAL_ID_WIDTH(LOCAL_ID_WIDTH),
.LOCAL_CS_WIDTH(LOCAL_CS_WIDTH),
.MEM_IF_ADDR_WIDTH(MEM_IF_ADDR_WIDTH),
.MEM_IF_CLK_PAIR_COUNT(MEM_IF_CLK_PAIR_COUNT),
.LOCAL_IF_TYPE(LOCAL_IF_TYPE),
.DWIDTH_RATIO(DWIDTH_RATIO),
.CTL_ODT_ENABLED(CTL_ODT_ENABLED),
.CTL_OUTPUT_REGD(CTL_OUTPUT_REGD),
.CTL_TBP_NUM(CTL_TBP_NUM),
.WRBUFFER_ADDR_WIDTH(WRBUFFER_ADDR_WIDTH),
.RDBUFFER_ADDR_WIDTH(RDBUFFER_ADDR_WIDTH),
.MEM_IF_CS_WIDTH(MEM_IF_CS_WIDTH),
.MEM_IF_CHIP(MEM_IF_CHIP),
.MEM_IF_BANKADDR_WIDTH(MEM_IF_BANKADDR_WIDTH),
.MEM_IF_ROW_WIDTH(MEM_IF_ROW_WIDTH),
.MEM_IF_COL_WIDTH(MEM_IF_COL_WIDTH),
.MEM_IF_ODT_WIDTH(MEM_IF_ODT_WIDTH),
.MEM_IF_DQS_WIDTH(MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH(MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH(MEM_IF_DM_WIDTH),
.MAX_MEM_IF_CS_WIDTH(MAX_MEM_IF_CS_WIDTH),
.MAX_MEM_IF_CHIP(MAX_MEM_IF_CHIP),
.MAX_MEM_IF_BANKADDR_WIDTH(MAX_MEM_IF_BANKADDR_WIDTH),
.MAX_MEM_IF_ROWADDR_WIDTH(MAX_MEM_IF_ROWADDR_WIDTH),
.MAX_MEM_IF_COLADDR_WIDTH(MAX_MEM_IF_COLADDR_WIDTH),
.MAX_MEM_IF_ODT_WIDTH(MAX_MEM_IF_ODT_WIDTH),
.MAX_MEM_IF_DQS_WIDTH(MAX_MEM_IF_DQS_WIDTH),
.MAX_MEM_IF_DQ_WIDTH(MAX_MEM_IF_DQ_WIDTH),
.MAX_MEM_IF_MASK_WIDTH(MAX_MEM_IF_MASK_WIDTH),
.MAX_LOCAL_DATA_WIDTH(MAX_LOCAL_DATA_WIDTH),
.CFG_TYPE(CFG_TYPE),
.CFG_INTERFACE_WIDTH(CFG_INTERFACE_WIDTH),
.CFG_BURST_LENGTH(CFG_BURST_LENGTH),
.CFG_DEVICE_WIDTH(CFG_DEVICE_WIDTH),
.CFG_REORDER_DATA(CFG_REORDER_DATA),
.CFG_DATA_REORDERING_TYPE(CFG_DATA_REORDERING_TYPE),
.CFG_STARVE_LIMIT(CFG_STARVE_LIMIT),
.CFG_ADDR_ORDER(CFG_ADDR_ORDER),
.MEM_CAS_WR_LAT(MEM_CAS_WR_LAT),
.MEM_ADD_LAT(MEM_ADD_LAT),
.MEM_TCL(MEM_TCL),
.MEM_TRRD(MEM_TRRD),
.MEM_TFAW(MEM_TFAW),
.MEM_TRFC(MEM_TRFC),
.MEM_TREFI(MEM_TREFI),
.MEM_TRCD(MEM_TRCD),
.MEM_TRP(MEM_TRP),
.MEM_TWR(MEM_TWR),
.MEM_TWTR(MEM_TWTR),
.MEM_TRTP(MEM_TRTP),
.MEM_TRAS(MEM_TRAS),
.MEM_TRC(MEM_TRC),
.CFG_TCCD(CFG_TCCD),
.MEM_AUTO_PD_CYCLES(MEM_AUTO_PD_CYCLES),
.CFG_SELF_RFSH_EXIT_CYCLES(CFG_SELF_RFSH_EXIT_CYCLES),
.CFG_PDN_EXIT_CYCLES(CFG_PDN_EXIT_CYCLES),
.CFG_POWER_SAVING_EXIT_CYCLES(CFG_POWER_SAVING_EXIT_CYCLES),
.CFG_MEM_CLK_ENTRY_CYCLES(CFG_MEM_CLK_ENTRY_CYCLES),
.MEM_TMRD_CK(MEM_TMRD_CK),
.CTL_ECC_ENABLED(CTL_ECC_ENABLED),
.CTL_ECC_RMW_ENABLED(CTL_ECC_RMW_ENABLED),
.CTL_ECC_MULTIPLES_16_24_40_72(CTL_ECC_MULTIPLES_16_24_40_72),
.CFG_GEN_SBE(CFG_GEN_SBE),
.CFG_GEN_DBE(CFG_GEN_DBE),
.CFG_ENABLE_INTR(CFG_ENABLE_INTR),
.CFG_MASK_SBE_INTR(CFG_MASK_SBE_INTR),
.CFG_MASK_DBE_INTR(CFG_MASK_DBE_INTR),
.CFG_MASK_CORRDROP_INTR(CFG_MASK_CORRDROP_INTR),
.CFG_CLR_INTR(CFG_CLR_INTR),
.CTL_USR_REFRESH(CTL_USR_REFRESH),
.CTL_REGDIMM_ENABLED(CTL_REGDIMM_ENABLED),
.CFG_WRITE_ODT_CHIP(CFG_WRITE_ODT_CHIP),
.CFG_READ_ODT_CHIP(CFG_READ_ODT_CHIP),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP(CFG_PORT_WIDTH_WRITE_ODT_CHIP),
.CFG_PORT_WIDTH_READ_ODT_CHIP(CFG_PORT_WIDTH_READ_ODT_CHIP),
.MEM_IF_CKE_WIDTH(MEM_IF_CKE_WIDTH),
.CTL_CSR_ENABLED(CTL_CSR_ENABLED),
.CFG_ENABLE_NO_DM(CFG_ENABLE_NO_DM),
.CSR_ADDR_WIDTH(CSR_ADDR_WIDTH),
.CSR_DATA_WIDTH(CSR_DATA_WIDTH),
.CSR_BE_WIDTH(CSR_BE_WIDTH),
.CFG_WLAT_BUS_WIDTH(AFI_WLAT_WIDTH),
.CFG_RLAT_BUS_WIDTH(AFI_RLAT_WIDTH),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT(MEM_IF_RD_TO_WR_TURNAROUND_OCT),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT(MEM_IF_WR_TO_RD_TURNAROUND_OCT),
.CTL_RD_TO_PCH_EXTRA_CLK(CTL_RD_TO_PCH_EXTRA_CLK),
.CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK(CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK),
.CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK(CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK),
.CFG_ECC_DECODER_REG(CFG_ECC_DECODER_REG),
.CFG_ERRCMD_FIFO_REG(CFG_ERRCMD_FIFO_REG)
) controller_inst (
.clk(clk),
.half_clk(half_clk),
.reset_n(reset_n),
.itf_cmd_ready(itf_cmd_ready),
.itf_cmd_valid(itf_cmd_valid),
.itf_cmd(itf_cmd),
.itf_cmd_address(itf_cmd_address),
.itf_cmd_burstlen(itf_cmd_burstlen),
.itf_cmd_id(itf_cmd_id),
.itf_cmd_priority(itf_cmd_priority),
.itf_cmd_autopercharge(itf_cmd_autopercharge),
.itf_cmd_multicast(itf_cmd_multicast),
.itf_wr_data_ready(itf_wr_data_ready),
.itf_wr_data_valid(itf_wr_data_valid),
.itf_wr_data(itf_wr_data),
.itf_wr_data_byte_en(itf_wr_data_byte_en),
.itf_wr_data_begin(itf_wr_data_begin),
.itf_wr_data_last(itf_wr_data_last),
.itf_wr_data_id(itf_wr_data_id),
.itf_rd_data_ready(itf_rd_data_ready),
.itf_rd_data_valid(itf_rd_data_valid),
.itf_rd_data(itf_rd_data),
.itf_rd_data_error(itf_rd_data_error),
.itf_rd_data_begin(itf_rd_data_begin),
.itf_rd_data_last(itf_rd_data_last),
.itf_rd_data_id(itf_rd_data_id),
.afi_rst_n(afi_rst_n),
.afi_cs_n(afi_cs_n),
.afi_cke(afi_cke),
.afi_odt(afi_odt),
.afi_addr(afi_addr),
.afi_ba(afi_ba),
.afi_ras_n(afi_ras_n),
.afi_cas_n(afi_cas_n),
.afi_we_n(afi_we_n),
.afi_dqs_burst(afi_dqs_burst),
.afi_wdata_valid(afi_wdata_valid),
.afi_wdata(afi_wdata),
.afi_dm(afi_dm),
.afi_wlat(afi_wlat),
.afi_rdata_en(afi_rdata_en),
.afi_rdata_en_full(afi_rdata_en_full),
.afi_rdata(afi_rdata),
.afi_rdata_valid(afi_rdata_valid),
.afi_rlat(afi_rlat),
.afi_cal_success(afi_cal_success),
.afi_cal_fail(afi_cal_fail),
.afi_cal_req(afi_cal_req),
.afi_mem_clk_disable(afi_mem_clk_disable),
.afi_cal_byte_lane_sel_n(afi_cal_byte_lane_sel_n),
.afi_ctl_refresh_done(afi_ctl_refresh_done),
.afi_seq_busy(afi_seq_busy),
.afi_ctl_long_idle(afi_ctl_long_idle),
.local_init_done(local_init_done),
.local_refresh_ack(local_refresh_ack),
.local_powerdn_ack(local_powerdn_ack),
.local_self_rfsh_ack(local_self_rfsh_ack),
.local_refresh_req(local_refresh_req),
.local_refresh_chip(local_refresh_chip),
.local_powerdn_req(local_powerdn_req),
.local_self_rfsh_req(local_self_rfsh_req),
.local_self_rfsh_chip(local_self_rfsh_chip),
.local_multicast(local_multicast),
.local_priority(local_priority),
.ecc_interrupt(ecc_interrupt),
.csr_read_req(csr_read_req),
.csr_write_req(csr_write_req),
.csr_burst_count(csr_burst_count),
.csr_beginbursttransfer(csr_beginbursttransfer),
.csr_addr(csr_addr),
.csr_wdata(csr_wdata),
.csr_rdata(csr_rdata),
.csr_be(csr_be),
.csr_rdata_valid(csr_rdata_valid),
.csr_waitrequest(csr_waitrequest)
);
endmodule
|
`timescale 1ns / 1ps
/*
-- Module Name: Key Generator
-- Description: Bloque generador de llaves de ronda. Este bloque toma la
la llave utilizada en la ronda anterior y la transforma
en una nueva llave para la ronda actual.
-- Dependencies: -- none
-- Parameters: -- none
-- Original Author: Héctor Cabrera
-- Current Author:
-- History:
-- Creacion 05 de Junio 2015
*/
module des_key_generator
(
input wire clk,
input wire reset,
// -- input -------------------------------------------------- >>>>>
input wire enable_din,
input wire source_sel_din,
input wire round_shift_din,
input wire [0:55] parity_drop_key_din,
// -- output ------------------------------------------------- >>>>>
output wire [0:47] round_key_dout
);
// -- Declaracion temparana de señales --------------------------- >>>>>
reg [0:27] upper_key_reg;
reg [0:27] lower_key_reg;
// -- Selector de origen de datos -------------------------------- >>>>>
wire [0:27] round_upper_key;
wire [0:27] round_lower_key;
assign round_upper_key = (source_sel_din) ? upper_key_shifted : parity_drop_key_din[28:55];
assign round_lower_key = (source_sel_din) ? lower_key_shifted : parity_drop_key_din[0:27];
// -- Registros de entrada --------------------------------------- >>>>>
always @(posedge clk)
if (reset)
begin
upper_key_reg <= {28{1'b0}};
lower_key_reg <= {28{1'b0}};
end
else
if (enable_din)
begin
upper_key_reg <= round_upper_key;
lower_key_reg <= round_lower_key;
end
// -- Circular Shifters ------------------------------------------ >>>>>
reg [0:27] upper_key_shifted;
reg [0:27] lower_key_shifted;
always @(*)
case (round_shift_din)
1'b0:
begin
upper_key_shifted = {upper_key_reg[1:27], upper_key_reg[0]};
lower_key_shifted = {lower_key_reg[1:27], lower_key_reg[0]};
end
1'b1:
begin
upper_key_shifted = {upper_key_reg[2:27], upper_key_reg[0:1]};
lower_key_shifted = {lower_key_reg[2:27], lower_key_reg[0:1]};
end
endcase
// -- Key Compression Box ---------------------------------------- >>>>>
wire [0:55] rejoin_key;
assign rejoin_key = {lower_key_shifted, upper_key_shifted};
assign round_key_dout [0 +: 8] = {
rejoin_key[13],
rejoin_key[16],
rejoin_key[10],
rejoin_key[23],
rejoin_key[0],
rejoin_key[4],
rejoin_key[2],
rejoin_key[27]
};
assign round_key_dout [8 +: 8] = {
rejoin_key[14],
rejoin_key[5],
rejoin_key[20],
rejoin_key[9],
rejoin_key[22],
rejoin_key[18],
rejoin_key[11],
rejoin_key[3]
};
assign round_key_dout [16 +: 8] = {
rejoin_key[25],
rejoin_key[7],
rejoin_key[15],
rejoin_key[6],
rejoin_key[26],
rejoin_key[19],
rejoin_key[12],
rejoin_key[1]
};
assign round_key_dout [24 +: 8] = {
rejoin_key[40],
rejoin_key[51],
rejoin_key[30],
rejoin_key[36],
rejoin_key[46],
rejoin_key[54],
rejoin_key[29],
rejoin_key[39]
};
assign round_key_dout [32 +: 8] = {
rejoin_key[50],
rejoin_key[44],
rejoin_key[32],
rejoin_key[47],
rejoin_key[43],
rejoin_key[48],
rejoin_key[38],
rejoin_key[55]
};
assign round_key_dout [40 +: 8] = {
rejoin_key[33],
rejoin_key[52],
rejoin_key[45],
rejoin_key[41],
rejoin_key[49],
rejoin_key[35],
rejoin_key[28],
rejoin_key[31]
};
endmodule
/* -- Plantilla de Instancia ------------------------------------ >>>>>>
des_key_generator key_generator
(
.clk (clk),
.reset (reset),
// -- input ---------------------------------------------- >>>>>
.enable_din (enable),
.source_sel_din (source_sel),
.round_shift_din (round_shift),
.parity_drop_key_din(parity_drop_key),
// -- output --------------------------------------------- >>>>>
.round_key_dout (round_key)
);
*/ |
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Tue Sep 19 11:17:53 2017
// Host : vldmr-PC running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k325tffg676-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[0:0],probe3[0:0],probe4[0:0],probe5[15:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [0:0]probe2;
input [0:0]probe3;
input [0:0]probe4;
input [15:0]probe5;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAPHETAP_PP_BLACKBOX_V
`define SKY130_FD_SC_LS__DECAPHETAP_PP_BLACKBOX_V
/**
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__decaphetap (
VPWR,
VGND,
VPB
);
input VPWR;
input VGND;
input VPB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAPHETAP_PP_BLACKBOX_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__UDP_DFF_PS_BLACKBOX_V
`define SKY130_FD_SC_HDLL__UDP_DFF_PS_BLACKBOX_V
/**
* udp_dff$PS: Positive edge triggered D flip-flop with active high
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__udp_dff$PS (
Q ,
D ,
CLK,
SET
);
output Q ;
input D ;
input CLK;
input SET;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__UDP_DFF_PS_BLACKBOX_V
|
module jt_sfg01(
input rst, // pin 25 (MSX 15) RESET
//inout reg [ 7:0] dio, // pins 43-50 IO(MSX 33-40) DATA BUS
output [ 7:0] sfg_dbi, // pins 43-50 IO(MSX 33-40) DATA BUS
input [ 7:0] sfg_dbo, // pins 43-50 IO(MSX 33-40) DATA BUS
input [15:0] addr, // pins 27-42 O (MSX 17-32) ADDRESS BUS
input clk, // pin 52 O (MSX 42) CLOCK 3.579545Mhz
// bus control
input wr_n, // pin 23 O (MSX 13) WRITE Request from CPU
input rd_n, // pin 24 O (MSX 14) READ Request from CPU
input slt3_n, // pin 14 O (MSX 04) SLOT Select signal
input iorq_n, // pin 21 O (MSX 11) I/O Request from CPU
input mi, // pin 19 O (MSX 09) M1 Signal from CPU
output int_n, // pin 18 I (MSX 08) Maskable INTERRUPT request, open collector signal
output wait_n, // pin 17 I (MSX 07) WAIT request, open collector signal
output oe_n, // ROM OE_n
output [15:0] left,
output [15:0] right
// midi
// input midi_rx,
// output midi_tx,
// keyboard control
);
// ADDRESS TABLE (A2-A0)
// #3FF0 (R) FM Status register
// #3FF0 (W) FM Address register
// #3FF1 (R/W) FM Data register
//
// #3FF2 (R/W) Yamaha external keyboard (YK-01 or YK-10) I/O address.
// #3FF3 (W) MIDI IRQ vector address
// #3FF4 (W) External IRQ vector address
// #3FF5 (R/W) MIDI UART Data read and write buffer
// #3FF6 (R) MIDI UART Status Register
// #3FF6 (W) MIDI UART Command Register
// glue logic
wire ce_n = &addr[13:7]; // IC105 and IC106
wire ic106_4 = ~(addr[6] & ce_n);
wire ic106_2 = ~(addr[5] & addr[4]);
wire ic107_3 = ~(~ic106_4 & ~ic106_2); // this is just an OR but I want to follow the schematic
wire ic107_4 = ~(~ic107_3 & ~addr[3]);
wire cs_n = ~(~ic107_4 & ~slt3_n); // ic107_1
assign busdir_n = ~(~iorq_n & ~mi); // ic107_2
assign wait_n = 1'b1; // No usamos el wait
// OPM_n == 0 --> CS_n --> YM2151
wire opm_n = !(!cs_n && addr[2:1]==2'b00); // OPM active when CS (0x3FF0-0x3FF8) and addr[2:1] =00
// wire [7:0] opm_dout;
// reg [7:0] rom_dout;
assign oe_n = !(!ce_n && !slt3_n);
// Data bus is IO so this manages hight impedance for Output Enable
/*
always @(woe_n) begin
oe_n <= woe_n;
if( !woe_n )
dio <= ( !opm_n ? opm_dout : 8'd0 ) | rom_dout;
else
dio <= 8'hzz;
end
*/
// assign midi_tx = 1'b0;
jt51(
.clk ( clk ), // main clock
.rst ( rst ), // reset
.cs_n ( opm_n ), // chip select
.wr_n ( wr_n ), // write
.a0 ( addr[0] ),
// .d_in ( dio ), // data in
// .d_out ( opm_dout ), // data out
.d_in ( sfg_dbo ), // data in
.d_out ( sfg_dbi ), // data out
.irq_n ( int_n ), // I do not synchronize this signal
// Low resolution output (same as real chip)
//output sample, // marks new output sample
//output signed [15:0] left,
//output signed [15:0] right,
// Full resolution output
//output signed [15:0] xleft,
//output signed [15:0] xright,
// unsigned outputs for sigma delta converters, full resolution
//output [15:0] dacleft,
//output [15:0] dacright
//.xleft ( left),
//.xright (right)
.left ( left),
.right (right)
);
/*
always @(*)
casex( {addr[7:0], ce_n, slt3_n} )
{ 8'hxx, 1'b1, 1'bx } : rom_dout = 8'd0;
{ 8'hxx, 1'bx, 1'b1 } : rom_dout = 8'd0;
{ 8'h80, 1'b0, 1'b0 } : rom_dout = 8'h4d;
{ 8'h81, 1'b0, 1'b0 } : rom_dout = 8'h43;
{ 8'h82, 1'b0, 1'b0 } : rom_dout = 8'h48;
{ 8'h83, 1'b0, 1'b0 } : rom_dout = 8'h46;
{ 8'h84, 1'b0, 1'b0 } : rom_dout = 8'h4d;
{ 8'h85, 1'b0, 1'b0 } : rom_dout = 8'h30;
default: rom_dout = 8'd0;
endcase
*/
endmodule // jt_sfg01
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module ad9467_spi (
spi_csn,
spi_clk,
spi_mosi,
spi_miso,
spi_sdio);
// 4 wire
input [ 1:0] spi_csn;
input spi_clk;
input spi_mosi;
output spi_miso;
// 3 wire
inout spi_sdio;
// internal registers
reg [ 5:0] spi_count = 'd0;
reg spi_rd_wr_n = 'd0;
reg spi_enable = 'd0;
// internal signals
wire spi_csn_s;
wire spi_enable_s;
// check on rising edge and change on falling edge
assign spi_csn_s = & spi_csn;
assign spi_enable_s = spi_enable & ~spi_csn_s;
always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0;
spi_rd_wr_n <= 1'd0;
end else begin
spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin
spi_rd_wr_n <= spi_mosi;
end
end
end
always @(negedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0;
end else begin
if (spi_count == 6'd16) begin
spi_enable <= spi_rd_wr_n;
end
end
end
// io butter
IOBUF i_iobuf_sdio (
.T (spi_enable_s),
.I (spi_mosi),
.O (spi_miso),
.IO (spi_sdio));
endmodule
|
// This module is a logic analyzer with sampling frequency of
// 2 times clk. It receives synchronized samples from
// bsg_ddr_sampler module and also chosses between the input lines
// to determine which line to store the sampled values.
//
// start_i signal triggers the sampling and it would stop sampling
// when its fifo becomes full. Next, the start signal would be
// de-asserted and dequing can be performed until the fifo is empty.
//
// It uses a 2 in 1 out FIFO, since during sampling each clock 2
// values are read but the signal would be send out 1 by 1.
`include "bsg_defines.v"
module bsg_logic_analyzer #( parameter `BSG_INV_PARAM(line_width_p )
, parameter `BSG_INV_PARAM(LA_els_p )
)
( input clk
, input reset
, input valid_en_i
, input [line_width_p-1:0] posedge_value_i
, input [line_width_p-1:0] negedge_value_i
, input [`BSG_SAFE_CLOG2(line_width_p)-1:0] input_bit_selector_i
, input start_i
, output ready_o
, output logic_analyzer_data_o
, output v_o
, input deque_i
);
// keeping state of enque
logic enque, enque_r;
always_ff @ (posedge clk)
if (reset)
enque_r <= 0;
else
enque_r <= enque;
// Enque starts by start_i signal and remains high until deque signal
// is asserted. It is assumed that start_i would not be asserted
// while dequing due to logic analyzer behavior. When first deque
// signal is asserted it will stop enquing. Since fifo uses a
// valid_and_read protocol, in case of fifo becoming full it would stop
// enqueing until deque is asserted, and as stated there would be no
// more enquing on that time.
assign enque = (start_i | enque_r) & ready_o;
// Select one bit of input signal for Logic Analyzer
// LSB is posedge and MSB is negedge
logic [1:0] LA_selected_line;
assign LA_selected_line[0] = posedge_value_i[input_bit_selector_i];
assign LA_selected_line[1] = negedge_value_i[input_bit_selector_i];
// Masking the valid bit
logic valid;
assign v_o = valid & valid_en_i;
// The protocol is ready_THEN_valid since we are checking the ready_o
// signal for generating the enque signal.
bsg_fifo_1r1w_narrowed
#( .width_p(2)
, .els_p(LA_els_p)
, .width_out_p(1)
, .lsb_to_msb_p(1)
, .ready_THEN_valid_p(1)
) narrowed_fifo
( .clk_i(clk)
, .reset_i(reset)
, .data_i(LA_selected_line)
, .v_i(enque)
, .ready_o(ready_o)
, .v_o(valid)
, .data_o(logic_analyzer_data_o)
, .yumi_i(deque_i)
);
endmodule
`BSG_ABSTRACT_MODULE(bsg_logic_analyzer)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__AND2_6_V
`define SKY130_FD_SC_HDLL__AND2_6_V
/**
* and2: 2-input AND.
*
* Verilog wrapper for and2 with size of 6 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__and2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_6 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__and2_6 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__and2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__AND2_6_V
|
// File: tb.v
// Generated by MyHDL 0.8dev
// Date: Sun Dec 16 22:45:16 2012
`timescale 1ns/10ps
module tb (
);
reg reset;
reg [3:0] live_count;
reg step;
reg clock;
wire age_out;
reg dut_age;
always @(posedge clock, posedge reset) begin: TB_DUT_SEQ
reg survival;
reg birth;
if (reset == 1) begin
dut_age <= 0;
end
else begin
birth = (live_count == 3);
survival = ((live_count == 2) || (live_count == 3));
if (step) begin
if (((dut_age == 0) && birth)) begin
dut_age <= 1;
end
else if (((dut_age == 1) && (!survival))) begin
dut_age <= 0;
end
end
end
end
assign age_out = dut_age;
initial begin: TB_CLOCKGEN
reset <= 0;
clock <= 0;
# 10;
reset <= 1;
# 10;
reset <= 0;
while (1'b1) begin
# 10;
clock <= (!clock);
end
end
initial begin: TB_CHECK
reg expected_age;
integer i;
integer v;
expected_age = 0;
for (i=0; i<1000; i=i+1) begin
@(negedge clock);
$write("%0d", age_out);
$write("\n");
case (i)
0: v = 2;
1: v = 7;
2: v = 0;
3: v = 6;
4: v = 0;
5: v = 2;
6: v = 0;
7: v = 7;
8: v = 0;
9: v = 3;
10: v = 7;
11: v = 6;
12: v = 0;
13: v = 8;
14: v = 6;
15: v = 5;
16: v = 8;
17: v = 3;
18: v = 1;
19: v = 0;
20: v = 2;
21: v = 7;
22: v = 7;
23: v = 0;
24: v = 4;
25: v = 4;
26: v = 3;
27: v = 6;
28: v = 5;
29: v = 0;
30: v = 1;
31: v = 5;
32: v = 8;
33: v = 6;
34: v = 5;
35: v = 5;
36: v = 8;
37: v = 6;
38: v = 3;
39: v = 1;
40: v = 4;
41: v = 5;
42: v = 1;
43: v = 6;
44: v = 7;
45: v = 4;
46: v = 8;
47: v = 0;
48: v = 2;
49: v = 1;
50: v = 1;
51: v = 4;
52: v = 2;
53: v = 7;
54: v = 1;
55: v = 6;
56: v = 4;
57: v = 7;
58: v = 6;
59: v = 2;
60: v = 1;
61: v = 2;
62: v = 2;
63: v = 6;
64: v = 8;
65: v = 4;
66: v = 4;
67: v = 7;
68: v = 4;
69: v = 3;
70: v = 0;
71: v = 3;
72: v = 2;
73: v = 4;
74: v = 1;
75: v = 2;
76: v = 4;
77: v = 5;
78: v = 4;
79: v = 4;
80: v = 0;
81: v = 1;
82: v = 1;
83: v = 1;
84: v = 7;
85: v = 8;
86: v = 5;
87: v = 6;
88: v = 1;
89: v = 2;
90: v = 5;
91: v = 7;
92: v = 8;
93: v = 4;
94: v = 5;
95: v = 0;
96: v = 1;
97: v = 7;
98: v = 5;
99: v = 6;
100: v = 8;
101: v = 5;
102: v = 2;
103: v = 7;
104: v = 2;
105: v = 4;
106: v = 5;
107: v = 4;
108: v = 1;
109: v = 8;
110: v = 4;
111: v = 7;
112: v = 6;
113: v = 8;
114: v = 4;
115: v = 8;
116: v = 0;
117: v = 3;
118: v = 0;
119: v = 5;
120: v = 8;
121: v = 8;
122: v = 4;
123: v = 3;
124: v = 3;
125: v = 3;
126: v = 1;
127: v = 2;
128: v = 5;
129: v = 3;
130: v = 2;
131: v = 2;
132: v = 6;
133: v = 6;
134: v = 1;
135: v = 1;
136: v = 5;
137: v = 5;
138: v = 6;
139: v = 6;
140: v = 1;
141: v = 3;
142: v = 3;
143: v = 4;
144: v = 8;
145: v = 8;
146: v = 4;
147: v = 3;
148: v = 2;
149: v = 4;
150: v = 6;
151: v = 7;
152: v = 2;
153: v = 5;
154: v = 5;
155: v = 0;
156: v = 1;
157: v = 2;
158: v = 1;
159: v = 4;
160: v = 0;
161: v = 0;
162: v = 2;
163: v = 6;
164: v = 7;
165: v = 6;
166: v = 7;
167: v = 0;
168: v = 8;
169: v = 2;
170: v = 4;
171: v = 5;
172: v = 4;
173: v = 7;
174: v = 3;
175: v = 3;
176: v = 2;
177: v = 6;
178: v = 7;
179: v = 7;
180: v = 8;
181: v = 0;
182: v = 7;
183: v = 8;
184: v = 4;
185: v = 1;
186: v = 6;
187: v = 5;
188: v = 4;
189: v = 4;
190: v = 6;
191: v = 4;
192: v = 8;
193: v = 0;
194: v = 6;
195: v = 2;
196: v = 1;
197: v = 3;
198: v = 5;
199: v = 5;
200: v = 6;
201: v = 2;
202: v = 8;
203: v = 4;
204: v = 6;
205: v = 0;
206: v = 0;
207: v = 6;
208: v = 4;
209: v = 0;
210: v = 8;
211: v = 7;
212: v = 2;
213: v = 3;
214: v = 3;
215: v = 8;
216: v = 8;
217: v = 5;
218: v = 8;
219: v = 4;
220: v = 5;
221: v = 8;
222: v = 6;
223: v = 6;
224: v = 8;
225: v = 7;
226: v = 5;
227: v = 2;
228: v = 2;
229: v = 2;
230: v = 3;
231: v = 6;
232: v = 5;
233: v = 5;
234: v = 5;
235: v = 6;
236: v = 3;
237: v = 6;
238: v = 4;
239: v = 8;
240: v = 6;
241: v = 5;
242: v = 2;
243: v = 8;
244: v = 1;
245: v = 8;
246: v = 2;
247: v = 4;
248: v = 1;
249: v = 8;
250: v = 2;
251: v = 5;
252: v = 8;
253: v = 2;
254: v = 6;
255: v = 6;
256: v = 2;
257: v = 4;
258: v = 7;
259: v = 6;
260: v = 8;
261: v = 0;
262: v = 6;
263: v = 7;
264: v = 2;
265: v = 5;
266: v = 6;
267: v = 1;
268: v = 3;
269: v = 4;
270: v = 1;
271: v = 2;
272: v = 7;
273: v = 1;
274: v = 4;
275: v = 2;
276: v = 6;
277: v = 6;
278: v = 1;
279: v = 3;
280: v = 3;
281: v = 5;
282: v = 0;
283: v = 8;
284: v = 5;
285: v = 7;
286: v = 8;
287: v = 1;
288: v = 6;
289: v = 3;
290: v = 1;
291: v = 4;
292: v = 0;
293: v = 7;
294: v = 4;
295: v = 7;
296: v = 2;
297: v = 5;
298: v = 3;
299: v = 6;
300: v = 1;
301: v = 6;
302: v = 0;
303: v = 0;
304: v = 1;
305: v = 8;
306: v = 3;
307: v = 2;
308: v = 5;
309: v = 1;
310: v = 8;
311: v = 1;
312: v = 1;
313: v = 4;
314: v = 2;
315: v = 6;
316: v = 2;
317: v = 2;
318: v = 7;
319: v = 0;
320: v = 5;
321: v = 5;
322: v = 2;
323: v = 0;
324: v = 8;
325: v = 2;
326: v = 3;
327: v = 5;
328: v = 8;
329: v = 2;
330: v = 8;
331: v = 0;
332: v = 6;
333: v = 5;
334: v = 0;
335: v = 8;
336: v = 6;
337: v = 6;
338: v = 4;
339: v = 8;
340: v = 7;
341: v = 5;
342: v = 6;
343: v = 1;
344: v = 1;
345: v = 7;
346: v = 8;
347: v = 6;
348: v = 1;
349: v = 4;
350: v = 4;
351: v = 8;
352: v = 4;
353: v = 6;
354: v = 7;
355: v = 4;
356: v = 3;
357: v = 5;
358: v = 3;
359: v = 4;
360: v = 3;
361: v = 5;
362: v = 6;
363: v = 1;
364: v = 3;
365: v = 1;
366: v = 7;
367: v = 1;
368: v = 2;
369: v = 8;
370: v = 6;
371: v = 1;
372: v = 4;
373: v = 6;
374: v = 6;
375: v = 7;
376: v = 8;
377: v = 8;
378: v = 8;
379: v = 0;
380: v = 4;
381: v = 6;
382: v = 2;
383: v = 0;
384: v = 5;
385: v = 4;
386: v = 7;
387: v = 2;
388: v = 7;
389: v = 2;
390: v = 3;
391: v = 5;
392: v = 4;
393: v = 1;
394: v = 2;
395: v = 8;
396: v = 8;
397: v = 3;
398: v = 8;
399: v = 4;
400: v = 5;
401: v = 3;
402: v = 0;
403: v = 8;
404: v = 0;
405: v = 0;
406: v = 6;
407: v = 5;
408: v = 4;
409: v = 6;
410: v = 0;
411: v = 0;
412: v = 5;
413: v = 3;
414: v = 2;
415: v = 1;
416: v = 2;
417: v = 7;
418: v = 0;
419: v = 6;
420: v = 1;
421: v = 0;
422: v = 2;
423: v = 0;
424: v = 0;
425: v = 4;
426: v = 4;
427: v = 0;
428: v = 0;
429: v = 3;
430: v = 7;
431: v = 5;
432: v = 7;
433: v = 2;
434: v = 1;
435: v = 4;
436: v = 1;
437: v = 4;
438: v = 3;
439: v = 7;
440: v = 6;
441: v = 1;
442: v = 8;
443: v = 7;
444: v = 6;
445: v = 1;
446: v = 2;
447: v = 2;
448: v = 6;
449: v = 3;
450: v = 6;
451: v = 8;
452: v = 3;
453: v = 6;
454: v = 8;
455: v = 6;
456: v = 4;
457: v = 4;
458: v = 3;
459: v = 5;
460: v = 2;
461: v = 0;
462: v = 4;
463: v = 4;
464: v = 7;
465: v = 3;
466: v = 2;
467: v = 4;
468: v = 6;
469: v = 8;
470: v = 1;
471: v = 5;
472: v = 5;
473: v = 7;
474: v = 8;
475: v = 0;
476: v = 5;
477: v = 1;
478: v = 4;
479: v = 1;
480: v = 3;
481: v = 2;
482: v = 5;
483: v = 0;
484: v = 2;
485: v = 2;
486: v = 6;
487: v = 2;
488: v = 5;
489: v = 6;
490: v = 1;
491: v = 0;
492: v = 8;
493: v = 1;
494: v = 2;
495: v = 6;
496: v = 4;
497: v = 3;
498: v = 0;
499: v = 7;
500: v = 8;
501: v = 0;
502: v = 5;
503: v = 7;
504: v = 7;
505: v = 7;
506: v = 2;
507: v = 6;
508: v = 8;
509: v = 3;
510: v = 4;
511: v = 0;
512: v = 2;
513: v = 8;
514: v = 0;
515: v = 6;
516: v = 1;
517: v = 0;
518: v = 0;
519: v = 5;
520: v = 1;
521: v = 2;
522: v = 7;
523: v = 7;
524: v = 5;
525: v = 3;
526: v = 1;
527: v = 8;
528: v = 0;
529: v = 3;
530: v = 7;
531: v = 3;
532: v = 8;
533: v = 2;
534: v = 0;
535: v = 8;
536: v = 0;
537: v = 6;
538: v = 7;
539: v = 4;
540: v = 3;
541: v = 4;
542: v = 8;
543: v = 6;
544: v = 4;
545: v = 8;
546: v = 4;
547: v = 0;
548: v = 7;
549: v = 5;
550: v = 4;
551: v = 2;
552: v = 4;
553: v = 2;
554: v = 5;
555: v = 4;
556: v = 3;
557: v = 7;
558: v = 4;
559: v = 2;
560: v = 3;
561: v = 3;
562: v = 1;
563: v = 2;
564: v = 0;
565: v = 5;
566: v = 6;
567: v = 7;
568: v = 4;
569: v = 0;
570: v = 8;
571: v = 3;
572: v = 4;
573: v = 2;
574: v = 4;
575: v = 7;
576: v = 4;
577: v = 2;
578: v = 5;
579: v = 7;
580: v = 6;
581: v = 7;
582: v = 3;
583: v = 8;
584: v = 4;
585: v = 6;
586: v = 8;
587: v = 1;
588: v = 5;
589: v = 4;
590: v = 6;
591: v = 7;
592: v = 5;
593: v = 6;
594: v = 7;
595: v = 4;
596: v = 1;
597: v = 4;
598: v = 2;
599: v = 0;
600: v = 4;
601: v = 6;
602: v = 6;
603: v = 7;
604: v = 2;
605: v = 2;
606: v = 0;
607: v = 6;
608: v = 4;
609: v = 7;
610: v = 7;
611: v = 1;
612: v = 7;
613: v = 8;
614: v = 2;
615: v = 0;
616: v = 5;
617: v = 8;
618: v = 6;
619: v = 0;
620: v = 2;
621: v = 6;
622: v = 2;
623: v = 1;
624: v = 2;
625: v = 3;
626: v = 8;
627: v = 7;
628: v = 8;
629: v = 1;
630: v = 0;
631: v = 7;
632: v = 8;
633: v = 4;
634: v = 8;
635: v = 6;
636: v = 8;
637: v = 2;
638: v = 7;
639: v = 2;
640: v = 2;
641: v = 7;
642: v = 2;
643: v = 6;
644: v = 8;
645: v = 8;
646: v = 1;
647: v = 4;
648: v = 8;
649: v = 0;
650: v = 5;
651: v = 6;
652: v = 5;
653: v = 5;
654: v = 8;
655: v = 6;
656: v = 3;
657: v = 4;
658: v = 6;
659: v = 8;
660: v = 6;
661: v = 6;
662: v = 0;
663: v = 3;
664: v = 4;
665: v = 5;
666: v = 2;
667: v = 2;
668: v = 4;
669: v = 5;
670: v = 0;
671: v = 3;
672: v = 6;
673: v = 4;
674: v = 3;
675: v = 0;
676: v = 3;
677: v = 2;
678: v = 3;
679: v = 1;
680: v = 7;
681: v = 6;
682: v = 1;
683: v = 6;
684: v = 2;
685: v = 1;
686: v = 7;
687: v = 8;
688: v = 4;
689: v = 5;
690: v = 7;
691: v = 3;
692: v = 1;
693: v = 8;
694: v = 1;
695: v = 6;
696: v = 3;
697: v = 3;
698: v = 4;
699: v = 0;
700: v = 1;
701: v = 6;
702: v = 4;
703: v = 6;
704: v = 7;
705: v = 3;
706: v = 8;
707: v = 7;
708: v = 3;
709: v = 3;
710: v = 5;
711: v = 2;
712: v = 7;
713: v = 1;
714: v = 5;
715: v = 1;
716: v = 8;
717: v = 4;
718: v = 4;
719: v = 8;
720: v = 8;
721: v = 4;
722: v = 4;
723: v = 0;
724: v = 8;
725: v = 7;
726: v = 0;
727: v = 7;
728: v = 1;
729: v = 6;
730: v = 7;
731: v = 4;
732: v = 7;
733: v = 7;
734: v = 8;
735: v = 6;
736: v = 3;
737: v = 6;
738: v = 5;
739: v = 0;
740: v = 8;
741: v = 5;
742: v = 2;
743: v = 6;
744: v = 1;
745: v = 4;
746: v = 1;
747: v = 8;
748: v = 8;
749: v = 6;
750: v = 5;
751: v = 6;
752: v = 3;
753: v = 4;
754: v = 0;
755: v = 4;
756: v = 2;
757: v = 2;
758: v = 2;
759: v = 3;
760: v = 6;
761: v = 4;
762: v = 5;
763: v = 6;
764: v = 6;
765: v = 1;
766: v = 6;
767: v = 0;
768: v = 2;
769: v = 3;
770: v = 3;
771: v = 3;
772: v = 3;
773: v = 7;
774: v = 8;
775: v = 4;
776: v = 0;
777: v = 8;
778: v = 8;
779: v = 1;
780: v = 4;
781: v = 4;
782: v = 4;
783: v = 2;
784: v = 2;
785: v = 6;
786: v = 0;
787: v = 7;
788: v = 7;
789: v = 0;
790: v = 4;
791: v = 4;
792: v = 5;
793: v = 4;
794: v = 2;
795: v = 8;
796: v = 0;
797: v = 1;
798: v = 1;
799: v = 7;
800: v = 3;
801: v = 0;
802: v = 8;
803: v = 6;
804: v = 0;
805: v = 3;
806: v = 2;
807: v = 8;
808: v = 1;
809: v = 7;
810: v = 7;
811: v = 5;
812: v = 1;
813: v = 0;
814: v = 6;
815: v = 5;
816: v = 3;
817: v = 3;
818: v = 0;
819: v = 4;
820: v = 4;
821: v = 0;
822: v = 6;
823: v = 0;
824: v = 2;
825: v = 7;
826: v = 0;
827: v = 2;
828: v = 3;
829: v = 8;
830: v = 5;
831: v = 7;
832: v = 5;
833: v = 7;
834: v = 1;
835: v = 4;
836: v = 8;
837: v = 8;
838: v = 8;
839: v = 3;
840: v = 2;
841: v = 1;
842: v = 3;
843: v = 3;
844: v = 5;
845: v = 5;
846: v = 1;
847: v = 5;
848: v = 5;
849: v = 4;
850: v = 1;
851: v = 0;
852: v = 2;
853: v = 8;
854: v = 3;
855: v = 0;
856: v = 4;
857: v = 4;
858: v = 4;
859: v = 5;
860: v = 1;
861: v = 5;
862: v = 5;
863: v = 0;
864: v = 1;
865: v = 1;
866: v = 7;
867: v = 7;
868: v = 5;
869: v = 4;
870: v = 5;
871: v = 8;
872: v = 7;
873: v = 7;
874: v = 7;
875: v = 3;
876: v = 1;
877: v = 4;
878: v = 1;
879: v = 7;
880: v = 6;
881: v = 1;
882: v = 0;
883: v = 3;
884: v = 2;
885: v = 1;
886: v = 4;
887: v = 8;
888: v = 6;
889: v = 3;
890: v = 7;
891: v = 4;
892: v = 5;
893: v = 7;
894: v = 2;
895: v = 8;
896: v = 5;
897: v = 7;
898: v = 4;
899: v = 1;
900: v = 1;
901: v = 7;
902: v = 5;
903: v = 3;
904: v = 6;
905: v = 5;
906: v = 1;
907: v = 8;
908: v = 6;
909: v = 8;
910: v = 3;
911: v = 0;
912: v = 0;
913: v = 7;
914: v = 3;
915: v = 3;
916: v = 7;
917: v = 1;
918: v = 3;
919: v = 3;
920: v = 7;
921: v = 4;
922: v = 5;
923: v = 2;
924: v = 8;
925: v = 7;
926: v = 0;
927: v = 4;
928: v = 8;
929: v = 1;
930: v = 2;
931: v = 7;
932: v = 3;
933: v = 6;
934: v = 8;
935: v = 7;
936: v = 7;
937: v = 7;
938: v = 6;
939: v = 2;
940: v = 6;
941: v = 6;
942: v = 6;
943: v = 4;
944: v = 5;
945: v = 8;
946: v = 4;
947: v = 4;
948: v = 2;
949: v = 8;
950: v = 0;
951: v = 1;
952: v = 8;
953: v = 2;
954: v = 1;
955: v = 4;
956: v = 8;
957: v = 8;
958: v = 1;
959: v = 3;
960: v = 8;
961: v = 1;
962: v = 7;
963: v = 3;
964: v = 4;
965: v = 6;
966: v = 2;
967: v = 3;
968: v = 5;
969: v = 8;
970: v = 1;
971: v = 6;
972: v = 5;
973: v = 4;
974: v = 5;
975: v = 2;
976: v = 7;
977: v = 8;
978: v = 0;
979: v = 2;
980: v = 4;
981: v = 0;
982: v = 3;
983: v = 0;
984: v = 0;
985: v = 5;
986: v = 1;
987: v = 8;
988: v = 0;
989: v = 2;
990: v = 0;
991: v = 6;
992: v = 8;
993: v = 1;
994: v = 6;
995: v = 1;
996: v = 0;
997: v = 5;
998: v = 2;
default: v = 4;
endcase
if (((age_out == 0) && (v == 3))) begin
expected_age = 1;
end
if (((age_out == 1) && (!((v == 2) || (v == 3))))) begin
expected_age = 0;
end
live_count <= v;
step <= 1;
@(posedge clock);
# 1;
if ((age_out == expected_age) !== 1) begin
$display("*** AssertionError ***");
end
end
$finish;
end
endmodule
|
module timer(
input CLK,
input switch_up,
input switch_dn,
input switch_cancel,
input switch_start_stop,
output [7:0] SEG,
output [3:0] DIGIT,
output BUZZER
);
wire s_up, s_dn, s_cancel, s_start_stop;
debouncer d1(.CLK (CLK), .switch_input (switch_up), .trans_dn (s_up));
debouncer d2(.CLK (CLK), .switch_input (switch_dn), .trans_dn (s_dn));
debouncer d3(.CLK (CLK), .switch_input (switch_cancel), .trans_dn (s_cancel));
debouncer d4(.CLK (CLK), .switch_input (switch_start_stop), .trans_dn (s_start_stop));
reg alarm_on = 0;
alarm a(.CLK (CLK), .BUZZER (BUZZER), .enable (alarm_on));
reg [3:0] secs = 0;
reg [3:0] ten_secs = 0;
reg [3:0] mins = 1;
reg [3:0] mins_stored;
reg [3:0] unused_digit = 4'd10; // digits above 9 not displayed
reg [25:0] prescaler = 0;
display_7_seg display(.CLK (CLK),
.units (secs), .tens (ten_secs), .hundreds (mins), .thousands (unused_digit),
.SEG (SEG), .DIGIT (DIGIT));
// States
localparam SETTING = 0, RUNNING = 1, BEEPING = 2;
reg [1:0] state = SETTING;
always @(posedge CLK)
begin
case (state)
SETTING : begin
handle_settings();
if (s_start_stop)
begin
mins_stored <= mins;
state <= RUNNING;
end
end
RUNNING : begin
decrement_time();
if (s_start_stop)
begin
state <= SETTING;
end
if (s_cancel)
begin
reset_time();
state <= SETTING;
end
if ((secs == 0) & (ten_secs == 0) & (mins == 0))
begin
alarm_on <= 1;
state <= BEEPING;
end
end
BEEPING : begin
if (s_cancel)
begin
alarm_on <= 0;
state <= SETTING;
reset_time();
end
end
endcase
end
task handle_settings;
begin
if (s_up)
begin
mins <= mins + 1;
if (mins == 9)
begin
mins <= 1;
end
end
if (s_dn)
begin
mins <= mins - 1;
if (mins == 1)
begin
mins <= 9;
end
end
end
endtask
task decrement_time;
begin
prescaler <= prescaler + 1;
if (prescaler == 26'd49999999) // 50 MHz to 1Hz
begin
prescaler <= 0;
secs <= secs - 1;
if (secs < 1)
begin
secs <= 9;
ten_secs <= ten_secs - 1;
if (ten_secs < 1)
begin
ten_secs <= 5;
mins <= mins - 1;
end
end
end
end
endtask
task reset_time;
begin
secs <= 0;
ten_secs <= 0;
mins <= mins_stored;
end
endtask
endmodule
|
// system_acl_iface_mm_interconnect_1.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.0 200 at 2015.04.18.10:44:23
`timescale 1 ps / 1 ps
module system_acl_iface_mm_interconnect_1 (
input wire pll_outclk0_clk, // pll_outclk0.clk
input wire clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset, // clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset.reset
input wire [29:0] clock_cross_kernel_mem1_m0_address, // clock_cross_kernel_mem1_m0.address
output wire clock_cross_kernel_mem1_m0_waitrequest, // .waitrequest
input wire [4:0] clock_cross_kernel_mem1_m0_burstcount, // .burstcount
input wire [31:0] clock_cross_kernel_mem1_m0_byteenable, // .byteenable
input wire clock_cross_kernel_mem1_m0_read, // .read
output wire [255:0] clock_cross_kernel_mem1_m0_readdata, // .readdata
output wire clock_cross_kernel_mem1_m0_readdatavalid, // .readdatavalid
input wire clock_cross_kernel_mem1_m0_write, // .write
input wire [255:0] clock_cross_kernel_mem1_m0_writedata, // .writedata
input wire clock_cross_kernel_mem1_m0_debugaccess, // .debugaccess
output wire [24:0] address_span_extender_kernel_windowed_slave_address, // address_span_extender_kernel_windowed_slave.address
output wire address_span_extender_kernel_windowed_slave_write, // .write
output wire address_span_extender_kernel_windowed_slave_read, // .read
input wire [255:0] address_span_extender_kernel_windowed_slave_readdata, // .readdata
output wire [255:0] address_span_extender_kernel_windowed_slave_writedata, // .writedata
output wire [4:0] address_span_extender_kernel_windowed_slave_burstcount, // .burstcount
output wire [31:0] address_span_extender_kernel_windowed_slave_byteenable, // .byteenable
input wire address_span_extender_kernel_windowed_slave_readdatavalid, // .readdatavalid
input wire address_span_extender_kernel_windowed_slave_waitrequest // .waitrequest
);
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest; // address_span_extender_kernel_windowed_slave_translator:uav_waitrequest -> clock_cross_kernel_mem1_m0_translator:uav_waitrequest
wire [9:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount; // clock_cross_kernel_mem1_m0_translator:uav_burstcount -> address_span_extender_kernel_windowed_slave_translator:uav_burstcount
wire [255:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata; // clock_cross_kernel_mem1_m0_translator:uav_writedata -> address_span_extender_kernel_windowed_slave_translator:uav_writedata
wire [29:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address; // clock_cross_kernel_mem1_m0_translator:uav_address -> address_span_extender_kernel_windowed_slave_translator:uav_address
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock; // clock_cross_kernel_mem1_m0_translator:uav_lock -> address_span_extender_kernel_windowed_slave_translator:uav_lock
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write; // clock_cross_kernel_mem1_m0_translator:uav_write -> address_span_extender_kernel_windowed_slave_translator:uav_write
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read; // clock_cross_kernel_mem1_m0_translator:uav_read -> address_span_extender_kernel_windowed_slave_translator:uav_read
wire [255:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata; // address_span_extender_kernel_windowed_slave_translator:uav_readdata -> clock_cross_kernel_mem1_m0_translator:uav_readdata
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess; // clock_cross_kernel_mem1_m0_translator:uav_debugaccess -> address_span_extender_kernel_windowed_slave_translator:uav_debugaccess
wire [31:0] clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable; // clock_cross_kernel_mem1_m0_translator:uav_byteenable -> address_span_extender_kernel_windowed_slave_translator:uav_byteenable
wire clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid; // address_span_extender_kernel_windowed_slave_translator:uav_readdatavalid -> clock_cross_kernel_mem1_m0_translator:uav_readdatavalid
altera_merlin_master_translator #(
.AV_ADDRESS_W (30),
.AV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (1),
.UAV_CONSTANT_BURST_BEHAVIOR (1),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) clock_cross_kernel_mem1_m0_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (clock_cross_kernel_mem1_m0_address), // avalon_anti_master_0.address
.av_waitrequest (clock_cross_kernel_mem1_m0_waitrequest), // .waitrequest
.av_burstcount (clock_cross_kernel_mem1_m0_burstcount), // .burstcount
.av_byteenable (clock_cross_kernel_mem1_m0_byteenable), // .byteenable
.av_read (clock_cross_kernel_mem1_m0_read), // .read
.av_readdata (clock_cross_kernel_mem1_m0_readdata), // .readdata
.av_readdatavalid (clock_cross_kernel_mem1_m0_readdatavalid), // .readdatavalid
.av_write (clock_cross_kernel_mem1_m0_write), // .write
.av_writedata (clock_cross_kernel_mem1_m0_writedata), // .writedata
.av_debugaccess (clock_cross_kernel_mem1_m0_debugaccess), // .debugaccess
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponserequest (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponserequest (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (256),
.UAV_DATA_W (256),
.AV_BURSTCOUNT_W (5),
.AV_BYTEENABLE_W (32),
.UAV_BYTEENABLE_W (32),
.UAV_ADDRESS_W (30),
.UAV_BURSTCOUNT_W (10),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (32),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) address_span_extender_kernel_windowed_slave_translator (
.clk (pll_outclk0_clk), // clk.clk
.reset (clock_cross_kernel_mem1_m0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_address), // avalon_universal_slave_0.address
.uav_burstcount (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_read), // .read
.uav_write (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (clock_cross_kernel_mem1_m0_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (address_span_extender_kernel_windowed_slave_address), // avalon_anti_slave_0.address
.av_write (address_span_extender_kernel_windowed_slave_write), // .write
.av_read (address_span_extender_kernel_windowed_slave_read), // .read
.av_readdata (address_span_extender_kernel_windowed_slave_readdata), // .readdata
.av_writedata (address_span_extender_kernel_windowed_slave_writedata), // .writedata
.av_burstcount (address_span_extender_kernel_windowed_slave_burstcount), // .burstcount
.av_byteenable (address_span_extender_kernel_windowed_slave_byteenable), // .byteenable
.av_readdatavalid (address_span_extender_kernel_windowed_slave_readdatavalid), // .readdatavalid
.av_waitrequest (address_span_extender_kernel_windowed_slave_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponserequest (1'b0), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponserequest (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: ctu_level_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////;
// ctu_mon.v
//
// Description: CTU Monitor
////////////////////////////////////////////////////////
module ctu_level_mon (
hi,
lo,
mon_en,
mon_num,
off_on
);
input hi; // hi signal
input lo; // lo signal
input mon_en; // monitor enable
input [31:0] mon_num; // monitor num for failure tracking
input off_on; // turn off if 1
always @(hi or lo)
begin
if ( !$test$plusargs("ctu_mon_off")) begin
if ((mon_en == 1'b1)&& (off_on != 1'b1)) begin
$display("ERROR : Signal hi or lo toggled when it shouldnt ; hi= %h ,lo=%d \n", hi,lo);
$display("****NOTE : IF YOUR TEST INTEND TO TOGGLE THESE SIGNALS ******\n");
$display("**** use -sim_run_args=+ctu_mon_off as run argument******\n");
finish_test(" Signal toggles when not supposed to", mon_num);
end
end
end
//=====================================================================
// This task allows some more clocks and kills the test
//=====================================================================
task finish_test;
input [512:0] message;
input [31:0] id;
begin
$display("%0d ERROR: CTU Monitor : %s MONITOR NUMBER : %d", $time, message,mon_num);
//@(posedge clk);
//@(posedge clk);
//@(posedge clk);
$error ("ctu_mon", "CTU monitor exited") ;
end
endtask
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo_mixed_widths
// ============================================================
// File Name: rxlengthfifo_128x13.v
// Megafunction Name(s):
// dcfifo_mixed_widths
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.1 Build 173 11/01/2011 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module rxlengthfifo_128x13 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
rdempty,
wrfull);
input aclr;
input [14:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [14:0] q;
output rdempty;
output wrfull;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire sub_wire0;
wire [14:0] sub_wire1;
wire sub_wire2;
wire wrfull = sub_wire0;
wire [14:0] q = sub_wire1[14:0];
wire rdempty = sub_wire2;
dcfifo_mixed_widths dcfifo_mixed_widths_component (
.rdclk (rdclk),
.wrclk (wrclk),
.wrreq (wrreq),
.aclr (aclr),
.data (data),
.rdreq (rdreq),
.wrfull (sub_wire0),
.q (sub_wire1),
.rdempty (sub_wire2),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ());
defparam
dcfifo_mixed_widths_component.intended_device_family = "Stratix IV",
dcfifo_mixed_widths_component.lpm_numwords = 512,
dcfifo_mixed_widths_component.lpm_showahead = "OFF",
dcfifo_mixed_widths_component.lpm_type = "dcfifo_mixed_widths",
dcfifo_mixed_widths_component.lpm_width = 15,
dcfifo_mixed_widths_component.lpm_widthu = 9,
dcfifo_mixed_widths_component.lpm_widthu_r = 9,
dcfifo_mixed_widths_component.lpm_width_r = 15,
dcfifo_mixed_widths_component.overflow_checking = "ON",
dcfifo_mixed_widths_component.rdsync_delaypipe = 4,
dcfifo_mixed_widths_component.underflow_checking = "ON",
dcfifo_mixed_widths_component.use_eab = "ON",
dcfifo_mixed_widths_component.write_aclr_synch = "OFF",
dcfifo_mixed_widths_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "15"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "1"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "15"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo_mixed_widths"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "15"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "9"
// Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "15"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 15 0 INPUT NODEFVAL "data[14..0]"
// Retrieval info: USED_PORT: q 0 0 15 0 OUTPUT NODEFVAL "q[14..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 15 0 data 0 0 15 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 15 0 @q 0 0 15 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL rxlengthfifo_128x13_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
// ======================================================================
// MPU_9150.v generated from TopDesign.cysch
// 02/28/2015 at 17:50
// This file is auto generated. ANY EDITS YOU MAKE MAY BE LOST WHEN THIS FILE IS REGENERATED!!!
// ======================================================================
/* -- WARNING: The following section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_DIE_LEOPARD 1
`define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3
`define CYDEV_CHIP_REV_LEOPARD_ES3 3
`define CYDEV_CHIP_REV_LEOPARD_ES2 1
`define CYDEV_CHIP_REV_LEOPARD_ES1 0
`define CYDEV_CHIP_DIE_PSOC4A 2
`define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17
`define CYDEV_CHIP_REV_PSOC4A_ES0 17
`define CYDEV_CHIP_DIE_PANTHER 3
`define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1
`define CYDEV_CHIP_REV_PANTHER_ES1 1
`define CYDEV_CHIP_REV_PANTHER_ES0 0
`define CYDEV_CHIP_DIE_PSOC5LP 4
`define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0
`define CYDEV_CHIP_REV_PSOC5LP_ES0 0
`define CYDEV_CHIP_DIE_EXPECT 2
`define CYDEV_CHIP_REV_EXPECT 17
`define CYDEV_CHIP_DIE_ACTUAL 2
/* -- WARNING: The previous section of defines are deprecated and will be removed in a future release -- */
`define CYDEV_CHIP_FAMILY_UNKNOWN 0
`define CYDEV_CHIP_MEMBER_UNKNOWN 0
`define CYDEV_CHIP_FAMILY_PSOC3 1
`define CYDEV_CHIP_MEMBER_3A 1
`define CYDEV_CHIP_REVISION_3A_PRODUCTION 3
`define CYDEV_CHIP_REVISION_3A_ES3 3
`define CYDEV_CHIP_REVISION_3A_ES2 1
`define CYDEV_CHIP_REVISION_3A_ES1 0
`define CYDEV_CHIP_FAMILY_PSOC4 2
`define CYDEV_CHIP_MEMBER_4A 2
`define CYDEV_CHIP_REVISION_4A_PRODUCTION 17
`define CYDEV_CHIP_REVISION_4A_ES0 17
`define CYDEV_CHIP_MEMBER_4D 3
`define CYDEV_CHIP_REVISION_4D_PRODUCTION 0
`define CYDEV_CHIP_REVISION_4D_ES0 0
`define CYDEV_CHIP_FAMILY_PSOC5 3
`define CYDEV_CHIP_MEMBER_5A 4
`define CYDEV_CHIP_REVISION_5A_PRODUCTION 1
`define CYDEV_CHIP_REVISION_5A_ES1 1
`define CYDEV_CHIP_REVISION_5A_ES0 0
`define CYDEV_CHIP_MEMBER_5B 5
`define CYDEV_CHIP_REVISION_5B_PRODUCTION 0
`define CYDEV_CHIP_REVISION_5B_ES0 0
`define CYDEV_CHIP_FAMILY_USED 2
`define CYDEV_CHIP_MEMBER_USED 2
`define CYDEV_CHIP_REVISION_USED 17
// Component: ZeroTerminal
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\ZeroTerminal\ZeroTerminal.v"
`endif
// Component: cy_virtualmux_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v"
`endif
// Component: or_v1_0
`ifdef CY_BLK_DIR
`undef CY_BLK_DIR
`endif
`ifdef WARP
`define CY_BLK_DIR "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "$CYPRESS_DIR\..\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`else
`define CY_BLK_DIR "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0"
`include "C:\Program Files (x86)\Cypress\PSoC Creator\3.0\PSoC Creator\psoc\content\cyprimitives\CyPrimitives.cylib\or_v1_0\or_v1_0.v"
`endif
// SCB_P4_v1_20(BitWidthReplacementStringRx=uint8, BitWidthReplacementStringTx=uint8, BufNum=1, Cond=#, DBGW_SCB_IP_V0=true, DBGW_SCB_IP_V1=false, EndCond=#endif, EzI2cBitWidthReplacementString=uint16, EzI2cClkFreqDes=1600, EzI2cClockFromTerm=false, EzI2cClockStretching=true, EzI2cDataRate=100, EzI2cIsPrimarySlaveAddressHex=true, EzI2cIsSecondarySlaveAddressHex=true, EzI2cMedianFilterEnable=true, EzI2cNumberOfAddresses=0, EzI2cOvsFactor=16, EzI2cPrimarySlaveAddress=8, EzI2cSecondarySlaveAddress=9, EzI2cSlaveAddressMask=254, EzI2cSubAddressSize=0, EzI2cWakeEnable=false, I2cAcceptAddress=false, I2cClkFreqDes=6400, I2cClockFromTerm=false, I2cDataRate=400, I2cExternIntrHandler=false, I2cIsSlaveAddressHex=true, I2cIsSlaveAddressMaskHex=true, I2cMedianFilterEnable=true, I2cMode=2, I2cOvsFactor=16, I2cOvsFactorHigh=8, I2cOvsFactorLow=8, I2cSlaveAddress=8, I2cSlaveAddressMask=254, I2cWakeEnable=false, PinName0Unconfig=spi_mosi_i2c_scl_uart_rx, PinName1Unconfig=spi_miso_i2c_sda_uart_tx, RemoveI2cPins=false, RemoveMisoSdaTx=true, RemoveMosiSclRx=true, RemoveMosiSclRxWake=true, RemoveScbClk=false, RemoveScbIrq=false, RemoveSpiMasterPins=true, RemoveSpiMasterSs0Pin=true, RemoveSpiMasterSs1Pin=true, RemoveSpiMasterSs2Pin=true, RemoveSpiMasterSs3Pin=true, RemoveSpiSclk=true, RemoveSpiSlavePins=true, RemoveSpiSs0=true, RemoveSpiSs1=true, RemoveSpiSs2=true, RemoveSpiSs3=true, RemoveUartRxPin=true, RemoveUartRxTxPin=true, RemoveUartRxWake=true, RemoveUartRxWakeupIrq=true, RemoveUartTxPin=true, ScbClkFreqDes=6400, ScbClockSelect=1, ScbClockTermEnable=false, ScbCustomIntrHandlerEnable=true, ScbInterruptTermEnable=false, ScbMisoSdaTxEnable=true, ScbMode=1, ScbModeHw=0, ScbMosiSclRxEnable=true, ScbRxWakeIrqEnable=false, ScbSclkEnable=false, ScbSs0Enable=false, ScbSs1Enable=false, ScbSs2Enable=false, ScbSs3Enable=false, SpiBitRate=1000, SpiBitsOrder=1, SpiClkFreqDes=16000, SpiClockFromTerm=false, SpiInterruptMode=0, SpiIntrMasterSpiDone=false, SpiIntrRxFull=false, SpiIntrRxNotEmpty=false, SpiIntrRxOverflow=false, SpiIntrRxTrigger=false, SpiIntrRxUnderflow=false, SpiIntrSlaveBusError=false, SpiIntrTxEmpty=false, SpiIntrTxNotFull=false, SpiIntrTxOverflow=false, SpiIntrTxTrigger=false, SpiIntrTxUnderflow=false, SpiLateMisoSampleEnable=false, SpiMedianFilterEnable=false, SpiMode=0, SpiNumberOfRxDataBits=8, SpiNumberOfSelectLines=1, SpiNumberOfTxDataBits=8, SpiOvsFactor=16, SpiRxBufferSize=8, SpiRxIntrMask=0, SpiRxTriggerLevel=7, SpiSclkMode=0, SpiSubMode=0, SpiTransferSeparation=1, SpiTxBufferSize=8, SpiTxIntrMask=0, SpiTxTriggerLevel=0, SpiWakeEnable=false, UartClkFreqDes=1382.4, UartClockFromTerm=false, UartDataRate=115200, UartDirection=3, UartDropOnFrameErr=false, UartDropOnParityErr=false, UartInterruptMode=0, UartIntrRxFrameErr=false, UartIntrRxFull=false, UartIntrRxNotEmpty=false, UartIntrRxOverflow=false, UartIntrRxParityErr=false, UartIntrRxTrigger=false, UartIntrRxUnderflow=false, UartIntrTxEmpty=false, UartIntrTxNotFull=false, UartIntrTxOverflow=false, UartIntrTxTrigger=false, UartIntrTxUartDone=false, UartIntrTxUartLostArb=false, UartIntrTxUartNack=false, UartIntrTxUnderflow=false, UartIrdaLowPower=false, UartIrdaPolarity=0, UartMedianFilterEnable=false, UartMpEnable=false, UartMpRxAcceptAddress=false, UartMpRxAddress=2, UartMpRxAddressMask=255, UartNumberOfDataBits=8, UartNumberOfStopBits=2, UartOvsFactor=12, UartParityType=2, UartRxBufferSize=8, UartRxEnable=true, UartRxIntrMask=0, UartRxTriggerLevel=7, UartSmCardRetryOnNack=false, UartSubMode=0, UartTxBufferSize=8, UartTxEnable=true, UartTxIntrMask=0, UartTxTriggerLevel=0, UartWakeEnable=false, CY_COMPONENT_NAME=SCB_P4_v1_20, CY_CONTROL_FILE=<:default:>, CY_FITTER_NAME=I2C_1, CY_INSTANCE_SHORT_NAME=I2C_1, CY_MAJOR_VERSION=1, CY_MINOR_VERSION=20, CY_REMOVE=false, CY_SUPPRESS_API_GEN=false, CY_VERSION=cydsfit No Version Information Found, INSTANCE_NAME=I2C_1, )
module SCB_P4_v1_20_0 (
sclk,
interrupt,
clock);
output sclk;
output interrupt;
input clock;
wire Net_427;
wire Net_416;
wire Net_245;
wire Net_676;
wire Net_452;
wire Net_459;
wire Net_496;
wire Net_660;
wire Net_656;
wire Net_687;
wire Net_703;
wire Net_682;
wire Net_422;
wire Net_379;
wire Net_555;
wire Net_387;
wire uncfg_rx_irq;
wire Net_458;
wire Net_596;
wire Net_252;
wire Net_547;
wire rx_irq;
wire [3:0] ss;
wire Net_467;
wire Net_655;
wire Net_663;
wire Net_581;
wire Net_474;
wire Net_651;
wire Net_580;
wire Net_654;
wire Net_653;
wire Net_652;
wire Net_284;
cy_clock_v1_0
#(.id("38321056-ba6d-401c-98e7-a21e84ee201e/81fcee8a-3b8b-4be1-9a5f-a5e2e619a938"),
.source_clock_id(""),
.divisor(0),
.period("156250000"),
.is_direct(0),
.is_digital(0))
SCBCLK
(.clock_out(Net_284));
ZeroTerminal ZeroTerminal_5 (
.z(Net_459));
// select_s_VM (cy_virtualmux_v1_0)
assign Net_652 = Net_459;
ZeroTerminal ZeroTerminal_4 (
.z(Net_452));
ZeroTerminal ZeroTerminal_3 (
.z(Net_676));
ZeroTerminal ZeroTerminal_2 (
.z(Net_245));
ZeroTerminal ZeroTerminal_1 (
.z(Net_416));
// rx_VM (cy_virtualmux_v1_0)
assign Net_654 = Net_452;
// rx_wake_VM (cy_virtualmux_v1_0)
assign Net_682 = uncfg_rx_irq;
// clock_VM (cy_virtualmux_v1_0)
assign Net_655 = Net_284;
// sclk_s_VM (cy_virtualmux_v1_0)
assign Net_653 = Net_416;
// mosi_s_VM (cy_virtualmux_v1_0)
assign Net_651 = Net_676;
// miso_m_VM (cy_virtualmux_v1_0)
assign Net_663 = Net_245;
wire [0:0] tmpOE__sda_net;
wire [0:0] tmpFB_0__sda_net;
wire [0:0] tmpINTERRUPT_0__sda_net;
electrical [0:0] tmpSIOVREF__sda_net;
cy_psoc3_pins_v1_10
#(.id("38321056-ba6d-401c-98e7-a21e84ee201e/5382e105-1382-4a2e-b9f4-3bb2feba71e0"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
sda
(.oe(tmpOE__sda_net),
.y({1'b0}),
.fb({tmpFB_0__sda_net[0:0]}),
.io({Net_581}),
.siovref(tmpSIOVREF__sda_net),
.interrupt({tmpINTERRUPT_0__sda_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__sda_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
wire [0:0] tmpOE__scl_net;
wire [0:0] tmpFB_0__scl_net;
wire [0:0] tmpINTERRUPT_0__scl_net;
electrical [0:0] tmpSIOVREF__scl_net;
cy_psoc3_pins_v1_10
#(.id("38321056-ba6d-401c-98e7-a21e84ee201e/22863ebe-a37b-476f-b252-6e49a8c00b12"),
.drive_mode(3'b100),
.ibuf_enabled(1'b1),
.init_dr_st(1'b1),
.input_clk_en(0),
.input_sync(1'b0),
.input_sync_mode(1'b0),
.intr_mode(2'b00),
.invert_in_clock(0),
.invert_in_clock_en(0),
.invert_in_reset(0),
.invert_out_clock(0),
.invert_out_clock_en(0),
.invert_out_reset(0),
.io_voltage(""),
.layout_mode("CONTIGUOUS"),
.oe_conn(1'b0),
.oe_reset(0),
.oe_sync(1'b0),
.output_clk_en(0),
.output_clock_mode(1'b0),
.output_conn(1'b0),
.output_mode(1'b0),
.output_reset(0),
.output_sync(1'b0),
.pa_in_clock(-1),
.pa_in_clock_en(-1),
.pa_in_reset(-1),
.pa_out_clock(-1),
.pa_out_clock_en(-1),
.pa_out_reset(-1),
.pin_aliases(""),
.pin_mode("B"),
.por_state(4),
.sio_group_cnt(0),
.sio_hyst(1'b0),
.sio_ibuf(""),
.sio_info(2'b00),
.sio_obuf(""),
.sio_refsel(""),
.sio_vtrip(""),
.slew_rate(1'b0),
.spanning(0),
.use_annotation(1'b0),
.vtrip(2'b00),
.width(1))
scl
(.oe(tmpOE__scl_net),
.y({1'b0}),
.fb({tmpFB_0__scl_net[0:0]}),
.io({Net_580}),
.siovref(tmpSIOVREF__scl_net),
.interrupt({tmpINTERRUPT_0__scl_net[0:0]}),
.in_clock({1'b0}),
.in_clock_en({1'b1}),
.in_reset({1'b0}),
.out_clock({1'b0}),
.out_clock_en({1'b1}),
.out_reset({1'b0}));
assign tmpOE__scl_net = (`CYDEV_CHIP_MEMBER_USED == `CYDEV_CHIP_MEMBER_3A && `CYDEV_CHIP_REVISION_USED < `CYDEV_CHIP_REVISION_3A_ES3) ? ~{1'b1} : {1'b1};
ZeroTerminal ZeroTerminal_7 (
.z(Net_427));
assign sclk = Net_284 | Net_427;
cy_isr_v1_0
#(.int_type(2'b10))
SCB_IRQ
(.int_signal(interrupt));
cy_m0s8_scb_v1_0 SCB (
.rx(Net_654),
.miso_m(Net_663),
.clock(Net_655),
.select_m(ss[3:0]),
.sclk_m(Net_687),
.mosi_s(Net_651),
.select_s(Net_652),
.sclk_s(Net_653),
.mosi_m(Net_660),
.scl(Net_580),
.sda(Net_581),
.tx(Net_656),
.miso_s(Net_703),
.interrupt(interrupt));
defparam SCB.scb_mode = 0;
endmodule
// top
module top ;
wire Net_9;
wire Net_8;
wire Net_7;
SCB_P4_v1_20_0 I2C_1 (
.sclk(Net_7),
.interrupt(Net_8),
.clock(1'b0));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:00:21 05/08/2014
// Design Name:
// Module Name: multi_cycle_Cpu
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Muliti_cycle_Cpu(
clk,
reset,
MIO_ready,
data_in,
gntInt,
Ireq,
Iack,
pc_out,
Inst,
mem_w,
Addr_out,
data_out,
CPU_MIO,
state,
cpu_stb_o,
intrrupt_en_o,
sel_o,
// Half_W,
Signext
);
input wire clk, reset, MIO_ready;
input wire [31: 0] data_in;
input wire [ 3: 0] gntInt; // INT grant
input wire Ireq; // INT request
output wire [31: 0] pc_out, Inst; //test
output wire [31: 0] Addr_out, data_out;
output wire [ 4: 0] state;
output wire mem_w, CPU_MIO;
output wire Signext;
output wire cpu_stb_o, Iack; // Bus requset and
output wire [31: 0] intrrupt_en_o; // Interrupt acknowlegement
output wire [3: 0] sel_o;
wire [31: 0] PC_Current;
wire [15: 0] imm;
wire [ 4: 0] InTcause; // Int cause, either syscall or INT
wire [ 3: 0] ALU_operation;
wire [ 1: 0] RegDst, ALUSrcB, ALUSrcA;
wire [ 2: 0] MemtoReg;
wire [ 2: 0] PCSource;
wire MemRead, MemWrite, IorD, IRWrite, RegWrite,
PCWrite, PCWriteCond, Beq, data2Mem, zero,
overflow, /*Signext,*/ WriteEPC, WriteCause,
WriteCp0, sysCause, WriteInt, Int_enm;
reg [ 3: 0] gntIntOut;
ctrl M1(
.clk (clk),
.reset (reset),
.Inst (Inst),
.MIO_ready (MIO_ready),
.MemRead (MemRead),
.MemWrite (MemWrite),
.CPU_MIO (CPU_MIO),
.IorD (IorD),
.IRWrite (IRWrite),
.RegDst (RegDst),
.RegWrite (RegWrite),
.MemtoReg (MemtoReg),
.data2Mem (data2Mem),
.ALUSrcA (ALUSrcA),
.ALUSrcB (ALUSrcB),
.PCSource (PCSource),
.PCWrite (PCWrite),
.PCWriteCond (PCWriteCond),
.Beq (Beq),
.ALU_operation (ALU_operation),
.state_out (state),
.zero (zero),
.overflow (overflow),
.Ireq (Ireq),
.Iack (Iack),
.Signext (Signext),
.WriteEPC (WriteEPC),
.WriteCause (WriteCause),
.WriteCp0 (WriteCp0),
.sysCause (sysCause),
.WriteIen (WriteIen),
.Int_en (Int_en),
.sel_o (sel_o)
//.Half_W (Half_W)
);
assign InTcause = {gntIntOut, sysCause}; // TODO: to be precise
always @(posedge clk) begin
gntIntOut <= gntInt & {4{Ireq}};
end
data_path M2(
.clk (clk),
.reset (reset),
.MIO_ready (MIO_ready),
.IorD (IorD),
.IRWrite (IRWrite),
.RegDst (RegDst),
.RegWrite (RegWrite),
.MemtoReg (MemtoReg),
.data2Mem (data2Mem),
.ALUSrcA (ALUSrcA),
.ALUSrcB (ALUSrcB),
.PCSource (PCSource),
.PCWrite (PCWrite),
.PCWriteCond (PCWriteCond),
.Beq (Beq),
.ALU_operation (ALU_operation),
.PC_Current (PC_Current),
.data2CPU (data_in),
.Inst_R (Inst),
.data_out (data_out),
.M_addr (Addr_out),
.zero (zero),
.overflow (overflow),
.Signext (Signext),
.WriteEPC (WriteEPC),
.WriteCause (WriteCause),
.WriteCp0 (WriteCp0),
.InTcause (InTcause),
.WriteIen (WriteIen),
.Int_en (Int_en),
.intrrupt_en_o (intrrupt_en_o)
);
assign mem_w = MemWrite && ~MemRead;
assign cpu_stb_o = MemWrite | MemRead; // Used for wishbone interface
assign pc_out = PC_Current;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: mask_to_zero
// Description: Selects active region from input data, bit reverses and masks LS
// bits to zero depending on the position of the leading zero identified
// by lzd.v
//////////////////////////////////////////////////////////////////////////////////
module mask_to_zero(
input clk,
input [14:0] data_in,
input [5:0] lz_pos,
output [14:0] data_out
);
wire [14:0] data_in_rev;
reg [14:0] data_in_r = 15'd0;
reg [14:0] data = 15'd0;
assign data_in_rev = {data_in[0], data_in[1], data_in[2], data_in[3], data_in[4],
data_in[5], data_in[6], data_in[7], data_in[8], data_in[9],
data_in[10], data_in[11], data_in[12], data_in[13], data_in[14]};
always @ (posedge clk) begin
data_in_r <= data_in_rev;
case (lz_pos)
6'd61: data <= data_in_r & 15'b111111111111111;
6'd60: data <= data_in_r & 15'b011111111111111;
6'd59: data <= data_in_r & 15'b101111111111111;
6'd58: data <= data_in_r & 15'b110111111111111;
6'd57: data <= data_in_r & 15'b111011111111111;
6'd56: data <= data_in_r & 15'b111101111111111;
6'd55: data <= data_in_r & 15'b111110111111111;
6'd54: data <= data_in_r & 15'b111111011111111;
6'd53: data <= data_in_r & 15'b111111101111111;
6'd52: data <= data_in_r & 15'b111111110111111;
6'd51: data <= data_in_r & 15'b111111111011111;
6'd50: data <= data_in_r & 15'b111111111101111;
6'd49: data <= data_in_r & 15'b111111111110111;
6'd48: data <= data_in_r & 15'b111111111111011;
6'd47: data <= data_in_r & 15'b111111111111101;
6'd46: data <= data_in_r & 15'b111111111111110;
default: data <= data_in_r & 15'b111111111111111;
endcase
end
assign data_out = data;
endmodule
|
// Accellera Standard V2.3 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2008. All rights reserved.
`ifdef OVL_ASSERT_ON
wire xzcheck_enable;
reg xzcheck_window = 0;
`ifdef OVL_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
assign xzcheck_enable = 1'b0;
`else
assign xzcheck_enable = 1'b1;
always @ (posedge clk)
begin
if (reset_n != 1'b0)
begin
if (!xzcheck_window && start_event == 1'b1)
xzcheck_window <= 1'b1;
else if (xzcheck_window && end_event == 1'b1)
xzcheck_window <= 1'b0;
end
else
begin
xzcheck_window <= 1'b0;
end
end
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
generate
case (property_type)
`OVL_ASSERT_2STATE,
`OVL_ASSERT: begin: assert_checks
assert_window_assert
assert_window_assert (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.end_event(end_event),
.xzcheck_window(xzcheck_window),
.xzcheck_enable(xzcheck_enable));
end
`OVL_ASSUME_2STATE,
`OVL_ASSUME: begin: assume_checks
assert_window_assume
assert_window_assume (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.end_event(end_event),
.xzcheck_window(xzcheck_window),
.xzcheck_enable(xzcheck_enable));
end
`OVL_IGNORE: begin: ovl_ignore
//do nothing
end
default: initial ovl_error_t(`OVL_FIRE_2STATE,"");
endcase
endgenerate
`endif
`ifdef OVL_COVER_ON
generate
if (coverage_level != `OVL_COVER_NONE)
begin: cover_checks
assert_window_cover #(
.OVL_COVER_BASIC_ON(OVL_COVER_BASIC_ON))
assert_window_cover (
.clk(clk),
.reset_n(`OVL_RESET_SIGNAL),
.test_expr(test_expr),
.start_event(start_event),
.end_event(end_event));
end
endgenerate
`endif
`endmodule //Required to pair up with already used "`module" in file assert_window.vlib
//Module to be replicated for assert checks
//This module is bound to a PSL vunits with assert checks
module assert_window_assert (clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable);
input clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable;
endmodule
//Module to be replicated for assume checks
//This module is bound to a PSL vunits with assume checks
module assert_window_assume (clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable);
input clk, reset_n, test_expr, start_event, end_event, xzcheck_window, xzcheck_enable;
endmodule
//Module to be replicated for cover properties
//This module is bound to a PSL vunit with cover properties
module assert_window_cover (clk, reset_n, test_expr, start_event, end_event);
parameter OVL_COVER_BASIC_ON = 1;
input clk, reset_n, test_expr, start_event, end_event;
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_set_verbosity O 1 const
// RDY_server_reset_request_put O 1 reg
// RDY_server_reset_response_get O 1
// valid O 1
// addr O 64 reg
// word64 O 64
// st_amo_val O 64
// exc O 1
// exc_code O 4 reg
// RDY_server_flush_request_put O 1 reg
// RDY_server_flush_response_get O 1
// RDY_tlb_flush O 1 const
// mem_master_awvalid O 1 reg
// mem_master_awid O 4 reg
// mem_master_awaddr O 64 reg
// mem_master_awlen O 8 reg
// mem_master_awsize O 3 reg
// mem_master_awburst O 2 reg
// mem_master_awlock O 1 reg
// mem_master_awcache O 4 reg
// mem_master_awprot O 3 reg
// mem_master_awqos O 4 reg
// mem_master_awregion O 4 reg
// mem_master_wvalid O 1 reg
// mem_master_wdata O 64 reg
// mem_master_wstrb O 8 reg
// mem_master_wlast O 1 reg
// mem_master_bready O 1 reg
// mem_master_arvalid O 1 reg
// mem_master_arid O 4 reg
// mem_master_araddr O 64 reg
// mem_master_arlen O 8 reg
// mem_master_arsize O 3 reg
// mem_master_arburst O 2 reg
// mem_master_arlock O 1 reg
// mem_master_arcache O 4 reg
// mem_master_arprot O 3 reg
// mem_master_arqos O 4 reg
// mem_master_arregion O 4 reg
// mem_master_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// req_op I 2
// req_f3 I 3
// req_amo_funct7 I 7 reg
// req_addr I 64
// req_st_value I 64
// req_priv I 2 unused
// req_sstatus_SUM I 1 unused
// req_mstatus_MXR I 1 unused
// req_satp I 64 unused
// mem_master_awready I 1
// mem_master_wready I 1
// mem_master_bvalid I 1
// mem_master_bid I 4 reg
// mem_master_bresp I 2 reg
// mem_master_arready I 1
// mem_master_rvalid I 1
// mem_master_rid I 4 reg
// mem_master_rdata I 64 reg
// mem_master_rresp I 2 reg
// mem_master_rlast I 1 reg
// EN_set_verbosity I 1
// EN_server_reset_request_put I 1
// EN_server_reset_response_get I 1
// EN_req I 1
// EN_server_flush_request_put I 1
// EN_server_flush_response_get I 1
// EN_tlb_flush I 1 unused
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkMMU_Cache(CLK,
RST_N,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
EN_server_reset_request_put,
RDY_server_reset_request_put,
EN_server_reset_response_get,
RDY_server_reset_response_get,
req_op,
req_f3,
req_amo_funct7,
req_addr,
req_st_value,
req_priv,
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
EN_req,
valid,
addr,
word64,
st_amo_val,
exc,
exc_code,
EN_server_flush_request_put,
RDY_server_flush_request_put,
EN_server_flush_response_get,
RDY_server_flush_response_get,
EN_tlb_flush,
RDY_tlb_flush,
mem_master_awvalid,
mem_master_awid,
mem_master_awaddr,
mem_master_awlen,
mem_master_awsize,
mem_master_awburst,
mem_master_awlock,
mem_master_awcache,
mem_master_awprot,
mem_master_awqos,
mem_master_awregion,
mem_master_awready,
mem_master_wvalid,
mem_master_wdata,
mem_master_wstrb,
mem_master_wlast,
mem_master_wready,
mem_master_bvalid,
mem_master_bid,
mem_master_bresp,
mem_master_bready,
mem_master_arvalid,
mem_master_arid,
mem_master_araddr,
mem_master_arlen,
mem_master_arsize,
mem_master_arburst,
mem_master_arlock,
mem_master_arcache,
mem_master_arprot,
mem_master_arqos,
mem_master_arregion,
mem_master_arready,
mem_master_rvalid,
mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast,
mem_master_rready);
parameter [0 : 0] dmem_not_imem = 1'b0;
input CLK;
input RST_N;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method server_reset_request_put
input EN_server_reset_request_put;
output RDY_server_reset_request_put;
// action method server_reset_response_get
input EN_server_reset_response_get;
output RDY_server_reset_response_get;
// action method req
input [1 : 0] req_op;
input [2 : 0] req_f3;
input [6 : 0] req_amo_funct7;
input [63 : 0] req_addr;
input [63 : 0] req_st_value;
input [1 : 0] req_priv;
input req_sstatus_SUM;
input req_mstatus_MXR;
input [63 : 0] req_satp;
input EN_req;
// value method valid
output valid;
// value method addr
output [63 : 0] addr;
// value method word64
output [63 : 0] word64;
// value method st_amo_val
output [63 : 0] st_amo_val;
// value method exc
output exc;
// value method exc_code
output [3 : 0] exc_code;
// action method server_flush_request_put
input EN_server_flush_request_put;
output RDY_server_flush_request_put;
// action method server_flush_response_get
input EN_server_flush_response_get;
output RDY_server_flush_response_get;
// action method tlb_flush
input EN_tlb_flush;
output RDY_tlb_flush;
// value method mem_master_m_awvalid
output mem_master_awvalid;
// value method mem_master_m_awid
output [3 : 0] mem_master_awid;
// value method mem_master_m_awaddr
output [63 : 0] mem_master_awaddr;
// value method mem_master_m_awlen
output [7 : 0] mem_master_awlen;
// value method mem_master_m_awsize
output [2 : 0] mem_master_awsize;
// value method mem_master_m_awburst
output [1 : 0] mem_master_awburst;
// value method mem_master_m_awlock
output mem_master_awlock;
// value method mem_master_m_awcache
output [3 : 0] mem_master_awcache;
// value method mem_master_m_awprot
output [2 : 0] mem_master_awprot;
// value method mem_master_m_awqos
output [3 : 0] mem_master_awqos;
// value method mem_master_m_awregion
output [3 : 0] mem_master_awregion;
// value method mem_master_m_awuser
// action method mem_master_m_awready
input mem_master_awready;
// value method mem_master_m_wvalid
output mem_master_wvalid;
// value method mem_master_m_wdata
output [63 : 0] mem_master_wdata;
// value method mem_master_m_wstrb
output [7 : 0] mem_master_wstrb;
// value method mem_master_m_wlast
output mem_master_wlast;
// value method mem_master_m_wuser
// action method mem_master_m_wready
input mem_master_wready;
// action method mem_master_m_bvalid
input mem_master_bvalid;
input [3 : 0] mem_master_bid;
input [1 : 0] mem_master_bresp;
// value method mem_master_m_bready
output mem_master_bready;
// value method mem_master_m_arvalid
output mem_master_arvalid;
// value method mem_master_m_arid
output [3 : 0] mem_master_arid;
// value method mem_master_m_araddr
output [63 : 0] mem_master_araddr;
// value method mem_master_m_arlen
output [7 : 0] mem_master_arlen;
// value method mem_master_m_arsize
output [2 : 0] mem_master_arsize;
// value method mem_master_m_arburst
output [1 : 0] mem_master_arburst;
// value method mem_master_m_arlock
output mem_master_arlock;
// value method mem_master_m_arcache
output [3 : 0] mem_master_arcache;
// value method mem_master_m_arprot
output [2 : 0] mem_master_arprot;
// value method mem_master_m_arqos
output [3 : 0] mem_master_arqos;
// value method mem_master_m_arregion
output [3 : 0] mem_master_arregion;
// value method mem_master_m_aruser
// action method mem_master_m_arready
input mem_master_arready;
// action method mem_master_m_rvalid
input mem_master_rvalid;
input [3 : 0] mem_master_rid;
input [63 : 0] mem_master_rdata;
input [1 : 0] mem_master_rresp;
input mem_master_rlast;
// value method mem_master_m_rready
output mem_master_rready;
// signals for module outputs
reg [63 : 0] word64;
wire [63 : 0] addr,
mem_master_araddr,
mem_master_awaddr,
mem_master_wdata,
st_amo_val;
wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
wire [3 : 0] exc_code,
mem_master_arcache,
mem_master_arid,
mem_master_arqos,
mem_master_arregion,
mem_master_awcache,
mem_master_awid,
mem_master_awqos,
mem_master_awregion;
wire [2 : 0] mem_master_arprot,
mem_master_arsize,
mem_master_awprot,
mem_master_awsize;
wire [1 : 0] mem_master_arburst, mem_master_awburst;
wire RDY_server_flush_request_put,
RDY_server_flush_response_get,
RDY_server_reset_request_put,
RDY_server_reset_response_get,
RDY_set_verbosity,
RDY_tlb_flush,
exc,
mem_master_arlock,
mem_master_arvalid,
mem_master_awlock,
mem_master_awvalid,
mem_master_bready,
mem_master_rready,
mem_master_wlast,
mem_master_wvalid,
valid;
// inlined wires
wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
ctr_wr_rsps_pending_crg$port1__write_1,
ctr_wr_rsps_pending_crg$port2__read,
ctr_wr_rsps_pending_crg$port3__read;
wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;
// register cfg_verbosity
reg [3 : 0] cfg_verbosity;
wire [3 : 0] cfg_verbosity$D_IN;
wire cfg_verbosity$EN;
// register ctr_wr_rsps_pending_crg
reg [3 : 0] ctr_wr_rsps_pending_crg;
wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
wire ctr_wr_rsps_pending_crg$EN;
// register rg_addr
reg [63 : 0] rg_addr;
wire [63 : 0] rg_addr$D_IN;
wire rg_addr$EN;
// register rg_amo_funct7
reg [6 : 0] rg_amo_funct7;
wire [6 : 0] rg_amo_funct7$D_IN;
wire rg_amo_funct7$EN;
// register rg_cset_in_cache
reg [5 : 0] rg_cset_in_cache;
wire [5 : 0] rg_cset_in_cache$D_IN;
wire rg_cset_in_cache$EN;
// register rg_error_during_refill
reg rg_error_during_refill;
wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;
// register rg_exc_code
reg [3 : 0] rg_exc_code;
reg [3 : 0] rg_exc_code$D_IN;
wire rg_exc_code$EN;
// register rg_f3
reg [2 : 0] rg_f3;
wire [2 : 0] rg_f3$D_IN;
wire rg_f3$EN;
// register rg_ld_val
reg [63 : 0] rg_ld_val;
reg [63 : 0] rg_ld_val$D_IN;
wire rg_ld_val$EN;
// register rg_lower_word32
reg [31 : 0] rg_lower_word32;
wire [31 : 0] rg_lower_word32$D_IN;
wire rg_lower_word32$EN;
// register rg_lower_word32_full
reg rg_lower_word32_full;
wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;
// register rg_lrsc_pa
reg [63 : 0] rg_lrsc_pa;
wire [63 : 0] rg_lrsc_pa$D_IN;
wire rg_lrsc_pa$EN;
// register rg_lrsc_valid
reg rg_lrsc_valid;
wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;
// register rg_op
reg [1 : 0] rg_op;
wire [1 : 0] rg_op$D_IN;
wire rg_op$EN;
// register rg_pa
reg [63 : 0] rg_pa;
wire [63 : 0] rg_pa$D_IN;
wire rg_pa$EN;
// register rg_pte_pa
reg [63 : 0] rg_pte_pa;
wire [63 : 0] rg_pte_pa$D_IN;
wire rg_pte_pa$EN;
// register rg_st_amo_val
reg [63 : 0] rg_st_amo_val;
wire [63 : 0] rg_st_amo_val$D_IN;
wire rg_st_amo_val$EN;
// register rg_state
reg [4 : 0] rg_state;
reg [4 : 0] rg_state$D_IN;
wire rg_state$EN;
// register rg_victim_way
reg rg_victim_way;
wire rg_victim_way$D_IN, rg_victim_way$EN;
// register rg_word64_set_in_cache
reg [8 : 0] rg_word64_set_in_cache;
wire [8 : 0] rg_word64_set_in_cache$D_IN;
wire rg_word64_set_in_cache$EN;
// ports of submodule f_fabric_write_reqs
reg [130 : 0] f_fabric_write_reqs$D_IN;
wire [130 : 0] f_fabric_write_reqs$D_OUT;
wire f_fabric_write_reqs$CLR,
f_fabric_write_reqs$DEQ,
f_fabric_write_reqs$EMPTY_N,
f_fabric_write_reqs$ENQ,
f_fabric_write_reqs$FULL_N;
// ports of submodule f_reset_reqs
wire f_reset_reqs$CLR,
f_reset_reqs$DEQ,
f_reset_reqs$D_IN,
f_reset_reqs$D_OUT,
f_reset_reqs$EMPTY_N,
f_reset_reqs$ENQ,
f_reset_reqs$FULL_N;
// ports of submodule f_reset_rsps
wire f_reset_rsps$CLR,
f_reset_rsps$DEQ,
f_reset_rsps$D_IN,
f_reset_rsps$D_OUT,
f_reset_rsps$EMPTY_N,
f_reset_rsps$ENQ,
f_reset_rsps$FULL_N;
// ports of submodule master_xactor_f_rd_addr
wire [96 : 0] master_xactor_f_rd_addr$D_IN, master_xactor_f_rd_addr$D_OUT;
wire master_xactor_f_rd_addr$CLR,
master_xactor_f_rd_addr$DEQ,
master_xactor_f_rd_addr$EMPTY_N,
master_xactor_f_rd_addr$ENQ,
master_xactor_f_rd_addr$FULL_N;
// ports of submodule master_xactor_f_rd_data
wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
wire master_xactor_f_rd_data$CLR,
master_xactor_f_rd_data$DEQ,
master_xactor_f_rd_data$EMPTY_N,
master_xactor_f_rd_data$ENQ,
master_xactor_f_rd_data$FULL_N;
// ports of submodule master_xactor_f_wr_addr
wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
wire master_xactor_f_wr_addr$CLR,
master_xactor_f_wr_addr$DEQ,
master_xactor_f_wr_addr$EMPTY_N,
master_xactor_f_wr_addr$ENQ,
master_xactor_f_wr_addr$FULL_N;
// ports of submodule master_xactor_f_wr_data
wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
wire master_xactor_f_wr_data$CLR,
master_xactor_f_wr_data$DEQ,
master_xactor_f_wr_data$EMPTY_N,
master_xactor_f_wr_data$ENQ,
master_xactor_f_wr_data$FULL_N;
// ports of submodule master_xactor_f_wr_resp
wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
wire master_xactor_f_wr_resp$CLR,
master_xactor_f_wr_resp$DEQ,
master_xactor_f_wr_resp$EMPTY_N,
master_xactor_f_wr_resp$ENQ,
master_xactor_f_wr_resp$FULL_N;
// ports of submodule ram_state_and_ctag_cset
wire [105 : 0] ram_state_and_ctag_cset$DIA,
ram_state_and_ctag_cset$DIB,
ram_state_and_ctag_cset$DOB;
wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
wire ram_state_and_ctag_cset$ENA,
ram_state_and_ctag_cset$ENB,
ram_state_and_ctag_cset$WEA,
ram_state_and_ctag_cset$WEB;
// ports of submodule ram_word64_set
reg [127 : 0] ram_word64_set$DIB;
reg [8 : 0] ram_word64_set$ADDRB;
wire [127 : 0] ram_word64_set$DIA, ram_word64_set$DOB;
wire [8 : 0] ram_word64_set$ADDRA;
wire ram_word64_set$ENA,
ram_word64_set$ENB,
ram_word64_set$WEA,
ram_word64_set$WEB;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr;
wire soc_map$m_is_mem_addr;
// rule scheduling signals
wire CAN_FIRE_RL_rl_ST_AMO_response,
CAN_FIRE_RL_rl_cache_refill_rsps_loop,
CAN_FIRE_RL_rl_discard_write_rsp,
CAN_FIRE_RL_rl_drive_exception_rsp,
CAN_FIRE_RL_rl_fabric_send_write_req,
CAN_FIRE_RL_rl_io_AMO_SC_req,
CAN_FIRE_RL_rl_io_AMO_op_req,
CAN_FIRE_RL_rl_io_AMO_read_rsp,
CAN_FIRE_RL_rl_io_read_req,
CAN_FIRE_RL_rl_io_read_rsp,
CAN_FIRE_RL_rl_io_write_req,
CAN_FIRE_RL_rl_maintain_io_read_rsp,
CAN_FIRE_RL_rl_probe_and_immed_rsp,
CAN_FIRE_RL_rl_rereq,
CAN_FIRE_RL_rl_reset,
CAN_FIRE_RL_rl_start_cache_refill,
CAN_FIRE_RL_rl_start_reset,
CAN_FIRE_mem_master_m_arready,
CAN_FIRE_mem_master_m_awready,
CAN_FIRE_mem_master_m_bvalid,
CAN_FIRE_mem_master_m_rvalid,
CAN_FIRE_mem_master_m_wready,
CAN_FIRE_req,
CAN_FIRE_server_flush_request_put,
CAN_FIRE_server_flush_response_get,
CAN_FIRE_server_reset_request_put,
CAN_FIRE_server_reset_response_get,
CAN_FIRE_set_verbosity,
CAN_FIRE_tlb_flush,
WILL_FIRE_RL_rl_ST_AMO_response,
WILL_FIRE_RL_rl_cache_refill_rsps_loop,
WILL_FIRE_RL_rl_discard_write_rsp,
WILL_FIRE_RL_rl_drive_exception_rsp,
WILL_FIRE_RL_rl_fabric_send_write_req,
WILL_FIRE_RL_rl_io_AMO_SC_req,
WILL_FIRE_RL_rl_io_AMO_op_req,
WILL_FIRE_RL_rl_io_AMO_read_rsp,
WILL_FIRE_RL_rl_io_read_req,
WILL_FIRE_RL_rl_io_read_rsp,
WILL_FIRE_RL_rl_io_write_req,
WILL_FIRE_RL_rl_maintain_io_read_rsp,
WILL_FIRE_RL_rl_probe_and_immed_rsp,
WILL_FIRE_RL_rl_rereq,
WILL_FIRE_RL_rl_reset,
WILL_FIRE_RL_rl_start_cache_refill,
WILL_FIRE_RL_rl_start_reset,
WILL_FIRE_mem_master_m_arready,
WILL_FIRE_mem_master_m_awready,
WILL_FIRE_mem_master_m_bvalid,
WILL_FIRE_mem_master_m_rvalid,
WILL_FIRE_mem_master_m_wready,
WILL_FIRE_req,
WILL_FIRE_server_flush_request_put,
WILL_FIRE_server_flush_response_get,
WILL_FIRE_server_reset_request_put,
WILL_FIRE_server_reset_response_get,
WILL_FIRE_set_verbosity,
WILL_FIRE_tlb_flush;
// inputs to muxes for submodule ports
wire [130 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
MUX_f_fabric_write_reqs$enq_1__VAL_2,
MUX_f_fabric_write_reqs$enq_1__VAL_3;
wire [127 : 0] MUX_ram_word64_set$a_put_3__VAL_1,
MUX_ram_word64_set$a_put_3__VAL_2;
wire [105 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
MUX_rg_ld_val$write_1__VAL_2;
wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2,
MUX_ram_word64_set$b_put_2__VAL_4;
wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
wire [4 : 0] MUX_rg_state$write_1__VAL_1,
MUX_rg_state$write_1__VAL_10,
MUX_rg_state$write_1__VAL_12,
MUX_rg_state$write_1__VAL_3;
wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1;
wire MUX_dw_output_ld_val$wset_1__SEL_1,
MUX_dw_output_ld_val$wset_1__SEL_2,
MUX_dw_output_ld_val$wset_1__SEL_3,
MUX_dw_output_ld_val$wset_1__SEL_4,
MUX_f_fabric_write_reqs$enq_1__SEL_2,
MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
MUX_ram_state_and_ctag_cset$b_put_3__SEL_1,
MUX_ram_word64_set$a_put_1__SEL_1,
MUX_ram_word64_set$b_put_1__SEL_2,
MUX_rg_error_during_refill$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_1,
MUX_rg_exc_code$write_1__SEL_2,
MUX_rg_exc_code$write_1__SEL_3,
MUX_rg_ld_val$write_1__SEL_2,
MUX_rg_lrsc_valid$write_1__SEL_2,
MUX_rg_state$write_1__SEL_10,
MUX_rg_state$write_1__SEL_12,
MUX_rg_state$write_1__SEL_13,
MUX_rg_state$write_1__SEL_2,
MUX_rg_state$write_1__SEL_3;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h3069;
reg [31 : 0] v__h4085;
reg [31 : 0] v__h4184;
reg [31 : 0] v__h4333;
reg [31 : 0] v__h19627;
reg [31 : 0] v__h23343;
reg [31 : 0] v__h26661;
reg [31 : 0] v__h27400;
reg [31 : 0] v__h27641;
reg [31 : 0] v__h30037;
reg [31 : 0] v__h30387;
reg [31 : 0] v__h31489;
reg [31 : 0] v__h31596;
reg [31 : 0] v__h31701;
reg [31 : 0] v__h31781;
reg [31 : 0] v__h31991;
reg [31 : 0] v__h32109;
reg [31 : 0] v__h32403;
reg [31 : 0] v__h32578;
reg [31 : 0] v__h34837;
reg [31 : 0] v__h32674;
reg [31 : 0] v__h35444;
reg [31 : 0] v__h35405;
reg [31 : 0] v__h3617;
reg [31 : 0] v__h35793;
reg [31 : 0] v__h3063;
reg [31 : 0] v__h3611;
reg [31 : 0] v__h4079;
reg [31 : 0] v__h4178;
reg [31 : 0] v__h4327;
reg [31 : 0] v__h19621;
reg [31 : 0] v__h23337;
reg [31 : 0] v__h26655;
reg [31 : 0] v__h27394;
reg [31 : 0] v__h27635;
reg [31 : 0] v__h30031;
reg [31 : 0] v__h30381;
reg [31 : 0] v__h31483;
reg [31 : 0] v__h31590;
reg [31 : 0] v__h31695;
reg [31 : 0] v__h31775;
reg [31 : 0] v__h31985;
reg [31 : 0] v__h32103;
reg [31 : 0] v__h32397;
reg [31 : 0] v__h32572;
reg [31 : 0] v__h32668;
reg [31 : 0] v__h34831;
reg [31 : 0] v__h35399;
reg [31 : 0] v__h35438;
reg [31 : 0] v__h35787;
// synopsys translate_on
// remaining internal signals
reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q30,
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q33,
CASE_rg_addr_BITS_2_TO_0_0x0_result1267_0x4_re_ETC__q34,
CASE_rg_addr_BITS_2_TO_0_0x0_result1332_0x4_re_ETC__q35,
CASE_rg_addr_BITS_2_TO_0_0x0_result4545_0x4_re_ETC__q50,
CASE_rg_addr_BITS_2_TO_0_0x0_result9447_0x4_re_ETC__q29,
CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_27_EQ__ETC__q52,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825,
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343,
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382,
_theResult_____2__h23867,
_theResult_____2__h32750,
ld_val__h30496,
mem_req_wr_data_wdata__h2820,
n__h20793,
n__h23729,
new_ld_val__h32704,
old_word64__h20782,
w1__h23859,
w1__h32738,
w1__h32742;
reg [7 : 0] mem_req_wr_data_wstrb__h2821;
reg [2 : 0] value__h32290, x__h2641;
wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d444,
IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d521,
IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d443,
IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d520,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_1_E_ETC___d351,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844,
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336,
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451,
IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d528,
_theResult___snd_fst__h2828,
cline_fabric_addr__h26714,
new_st_val__h23565,
new_st_val__h23871,
new_st_val__h23962,
new_st_val__h24942,
new_st_val__h24946,
new_st_val__h24950,
new_st_val__h24954,
new_st_val__h24959,
new_st_val__h24965,
new_st_val__h24970,
new_st_val__h32754,
new_st_val__h32845,
new_st_val__h34705,
new_st_val__h34709,
new_st_val__h34713,
new_st_val__h34717,
new_st_val__h34722,
new_st_val__h34728,
new_st_val__h34733,
new_value__h22433,
new_value__h6006,
result__h18715,
result__h18743,
result__h18771,
result__h18799,
result__h18827,
result__h18855,
result__h18883,
result__h18911,
result__h18956,
result__h18984,
result__h19012,
result__h19040,
result__h19068,
result__h19096,
result__h19124,
result__h19152,
result__h19197,
result__h19225,
result__h19253,
result__h19281,
result__h19322,
result__h19350,
result__h19378,
result__h19406,
result__h19447,
result__h19475,
result__h19514,
result__h19542,
result__h30556,
result__h30586,
result__h30613,
result__h30640,
result__h30667,
result__h30694,
result__h30721,
result__h30748,
result__h30792,
result__h30819,
result__h30846,
result__h30873,
result__h30900,
result__h30927,
result__h30954,
result__h30981,
result__h31025,
result__h31052,
result__h31079,
result__h31106,
result__h31146,
result__h31173,
result__h31200,
result__h31227,
result__h31267,
result__h31294,
result__h31332,
result__h31359,
result__h32933,
result__h33841,
result__h33869,
result__h33897,
result__h33925,
result__h33953,
result__h33981,
result__h34009,
result__h34054,
result__h34082,
result__h34110,
result__h34138,
result__h34166,
result__h34194,
result__h34222,
result__h34250,
result__h34295,
result__h34323,
result__h34351,
result__h34379,
result__h34420,
result__h34448,
result__h34476,
result__h34504,
result__h34545,
result__h34573,
result__h34612,
result__h34640,
w1___1__h23930,
w1___1__h32813,
w2___1__h32814,
w2__h32744,
word64__h5839,
x__h20014,
x__h32733,
x__h6029,
y__h12359,
y__h6030,
y__h6044;
wire [31 : 0] IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC__q31,
ld_val0496_BITS_31_TO_0__q38,
ld_val0496_BITS_63_TO_32__q45,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
rg_st_amo_val_BITS_31_TO_0__q32,
w12738_BITS_31_TO_0__q51,
word64839_BITS_31_TO_0__q17,
word64839_BITS_63_TO_32__q24;
wire [15 : 0] ld_val0496_BITS_15_TO_0__q37,
ld_val0496_BITS_31_TO_16__q41,
ld_val0496_BITS_47_TO_32__q44,
ld_val0496_BITS_63_TO_48__q48,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q6,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
word64839_BITS_15_TO_0__q16,
word64839_BITS_31_TO_16__q20,
word64839_BITS_47_TO_32__q23,
word64839_BITS_63_TO_48__q27;
wire [7 : 0] ld_val0496_BITS_15_TO_8__q39,
ld_val0496_BITS_23_TO_16__q40,
ld_val0496_BITS_31_TO_24__q42,
ld_val0496_BITS_39_TO_32__q43,
ld_val0496_BITS_47_TO_40__q46,
ld_val0496_BITS_55_TO_48__q47,
ld_val0496_BITS_63_TO_56__q49,
ld_val0496_BITS_7_TO_0__q36,
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5,
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8,
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q9,
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
strobe64__h2758,
strobe64__h2760,
strobe64__h2762,
word64839_BITS_15_TO_8__q18,
word64839_BITS_23_TO_16__q19,
word64839_BITS_31_TO_24__q21,
word64839_BITS_39_TO_32__q22,
word64839_BITS_47_TO_40__q25,
word64839_BITS_55_TO_48__q26,
word64839_BITS_63_TO_56__q28,
word64839_BITS_7_TO_0__q15;
wire [5 : 0] shift_bits__h2608;
wire [4 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d148,
IF_rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d150,
IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d149;
wire [3 : 0] access_exc_code__h2376, b__h26615;
wire [1 : 0] tmp__h26876, tmp__h26877;
wire IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d118,
NOT_cfg_verbosity_read__9_ULE_1_0___d41,
NOT_cfg_verbosity_read__9_ULE_2_94___d595,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d158,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d357,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d365,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d368,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d374,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d378,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d389,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d531,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d543,
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d573,
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d117,
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d164,
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d366,
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d371,
NOT_req_f3_BITS_1_TO_0_29_EQ_0b0_30_31_AND_NOT_ETC___d950,
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d145,
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d526,
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546,
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d554,
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566,
NOT_rg_op_1_EQ_1_9_70_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d386,
NOT_rg_op_1_EQ_1_9_70_AND_ram_state_and_ctag_c_ETC___d375,
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d384,
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d544,
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d548,
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d552,
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d120,
lrsc_result__h20004,
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113,
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107,
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d161,
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d172,
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d355,
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d568,
req_f3_BITS_1_TO_0_29_EQ_0b0_30_OR_req_f3_BITS_ETC___d959,
rg_addr_7_EQ_rg_lrsc_pa_5___d162,
rg_amo_funct7_4_BITS_6_TO_2_5_EQ_0b10_6_AND_ra_ETC___d360,
rg_lrsc_pa_5_EQ_rg_addr_7___d96,
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d135,
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d166,
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d176,
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d178,
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d181,
rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d174,
rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d387,
rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d524,
rg_op_1_EQ_2_3_AND_rg_amo_funct7_4_BITS_6_TO_2_ETC___d558,
rg_state_4_EQ_13_44_AND_rg_op_1_EQ_0_2_OR_rg_o_ETC___d646;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method server_reset_request_put
assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;
// action method server_reset_response_get
assign RDY_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_reset_response_get =
!f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;
// action method req
assign CAN_FIRE_req = 1'd1 ;
assign WILL_FIRE_req = EN_req ;
// value method valid
assign valid = dw_valid$whas ;
// value method addr
assign addr = rg_addr ;
// value method word64
always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
ld_val__h30496 or
MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32704 or
MUX_dw_output_ld_val$wset_1__SEL_3 or
MUX_dw_output_ld_val$wset_1__VAL_3 or
MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h30496;
MUX_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h32704;
MUX_dw_output_ld_val$wset_1__SEL_3:
word64 = MUX_dw_output_ld_val$wset_1__VAL_3;
MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val;
default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
// value method st_amo_val
assign st_amo_val =
MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;
// value method exc
assign exc = rg_state == 5'd4 ;
// value method exc_code
assign exc_code = rg_exc_code ;
// action method server_flush_request_put
assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;
// action method server_flush_response_get
assign RDY_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign CAN_FIRE_server_flush_response_get =
f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;
// action method tlb_flush
assign RDY_tlb_flush = 1'd1 ;
assign CAN_FIRE_tlb_flush = 1'd1 ;
assign WILL_FIRE_tlb_flush = EN_tlb_flush ;
// value method mem_master_m_awvalid
assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;
// value method mem_master_m_awid
assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;
// value method mem_master_m_awaddr
assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;
// value method mem_master_m_awlen
assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;
// value method mem_master_m_awsize
assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;
// value method mem_master_m_awburst
assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;
// value method mem_master_m_awlock
assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;
// value method mem_master_m_awcache
assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;
// value method mem_master_m_awprot
assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;
// value method mem_master_m_awqos
assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;
// value method mem_master_m_awregion
assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;
// action method mem_master_m_awready
assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
assign WILL_FIRE_mem_master_m_awready = 1'd1 ;
// value method mem_master_m_wvalid
assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;
// value method mem_master_m_wdata
assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;
// value method mem_master_m_wstrb
assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;
// value method mem_master_m_wlast
assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;
// action method mem_master_m_wready
assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
assign WILL_FIRE_mem_master_m_wready = 1'd1 ;
// action method mem_master_m_bvalid
assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;
// value method mem_master_m_bready
assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;
// value method mem_master_m_arvalid
assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;
// value method mem_master_m_arid
assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;
// value method mem_master_m_araddr
assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;
// value method mem_master_m_arlen
assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;
// value method mem_master_m_arsize
assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;
// value method mem_master_m_arburst
assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;
// value method mem_master_m_arlock
assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;
// value method mem_master_m_arcache
assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;
// value method mem_master_m_arprot
assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;
// value method mem_master_m_arqos
assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;
// value method mem_master_m_arregion
assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;
// action method mem_master_m_arready
assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
assign WILL_FIRE_mem_master_m_arready = 1'd1 ;
// action method mem_master_m_rvalid
assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;
// value method mem_master_m_rready
assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;
// submodule f_fabric_write_reqs
FIFO2 #(.width(32'd131), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_fabric_write_reqs$D_IN),
.ENQ(f_fabric_write_reqs$ENQ),
.DEQ(f_fabric_write_reqs$DEQ),
.CLR(f_fabric_write_reqs$CLR),
.D_OUT(f_fabric_write_reqs$D_OUT),
.FULL_N(f_fabric_write_reqs$FULL_N),
.EMPTY_N(f_fabric_write_reqs$EMPTY_N));
// submodule f_reset_reqs
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_reqs$D_IN),
.ENQ(f_reset_reqs$ENQ),
.DEQ(f_reset_reqs$DEQ),
.CLR(f_reset_reqs$CLR),
.D_OUT(f_reset_reqs$D_OUT),
.FULL_N(f_reset_reqs$FULL_N),
.EMPTY_N(f_reset_reqs$EMPTY_N));
// submodule f_reset_rsps
FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
.CLK(CLK),
.D_IN(f_reset_rsps$D_IN),
.ENQ(f_reset_rsps$ENQ),
.DEQ(f_reset_rsps$DEQ),
.CLR(f_reset_rsps$CLR),
.D_OUT(f_reset_rsps$D_OUT),
.FULL_N(f_reset_rsps$FULL_N),
.EMPTY_N(f_reset_rsps$EMPTY_N));
// submodule master_xactor_f_rd_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_addr$D_IN),
.ENQ(master_xactor_f_rd_addr$ENQ),
.DEQ(master_xactor_f_rd_addr$DEQ),
.CLR(master_xactor_f_rd_addr$CLR),
.D_OUT(master_xactor_f_rd_addr$D_OUT),
.FULL_N(master_xactor_f_rd_addr$FULL_N),
.EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));
// submodule master_xactor_f_rd_data
FIFO2 #(.width(32'd71),
.guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_rd_data$D_IN),
.ENQ(master_xactor_f_rd_data$ENQ),
.DEQ(master_xactor_f_rd_data$DEQ),
.CLR(master_xactor_f_rd_data$CLR),
.D_OUT(master_xactor_f_rd_data$D_OUT),
.FULL_N(master_xactor_f_rd_data$FULL_N),
.EMPTY_N(master_xactor_f_rd_data$EMPTY_N));
// submodule master_xactor_f_wr_addr
FIFO2 #(.width(32'd97),
.guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_addr$D_IN),
.ENQ(master_xactor_f_wr_addr$ENQ),
.DEQ(master_xactor_f_wr_addr$DEQ),
.CLR(master_xactor_f_wr_addr$CLR),
.D_OUT(master_xactor_f_wr_addr$D_OUT),
.FULL_N(master_xactor_f_wr_addr$FULL_N),
.EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));
// submodule master_xactor_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_data$D_IN),
.ENQ(master_xactor_f_wr_data$ENQ),
.DEQ(master_xactor_f_wr_data$DEQ),
.CLR(master_xactor_f_wr_data$CLR),
.D_OUT(master_xactor_f_wr_data$D_OUT),
.FULL_N(master_xactor_f_wr_data$FULL_N),
.EMPTY_N(master_xactor_f_wr_data$EMPTY_N));
// submodule master_xactor_f_wr_resp
FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(master_xactor_f_wr_resp$D_IN),
.ENQ(master_xactor_f_wr_resp$ENQ),
.DEQ(master_xactor_f_wr_resp$DEQ),
.CLR(master_xactor_f_wr_resp$CLR),
.D_OUT(master_xactor_f_wr_resp$D_OUT),
.FULL_N(master_xactor_f_wr_resp$FULL_N),
.EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));
// submodule ram_state_and_ctag_cset
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd6),
.DATA_WIDTH(32'd106),
.MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_state_and_ctag_cset$ADDRA),
.ADDRB(ram_state_and_ctag_cset$ADDRB),
.DIA(ram_state_and_ctag_cset$DIA),
.DIB(ram_state_and_ctag_cset$DIB),
.WEA(ram_state_and_ctag_cset$WEA),
.WEB(ram_state_and_ctag_cset$WEB),
.ENA(ram_state_and_ctag_cset$ENA),
.ENB(ram_state_and_ctag_cset$ENB),
.DOA(),
.DOB(ram_state_and_ctag_cset$DOB));
// submodule ram_word64_set
BRAM2 #(.PIPELINED(1'd0),
.ADDR_WIDTH(32'd9),
.DATA_WIDTH(32'd128),
.MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK),
.CLKB(CLK),
.ADDRA(ram_word64_set$ADDRA),
.ADDRB(ram_word64_set$ADDRB),
.DIA(ram_word64_set$DIA),
.DIB(ram_word64_set$DIB),
.WEA(ram_word64_set$WEA),
.WEB(ram_word64_set$WEB),
.ENA(ram_word64_set$ENA),
.ENB(ram_word64_set$ENB),
.DOA(),
.DOB(ram_word64_set$DOB));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_near_mem_io_addr_base(),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(),
.m_plic_addr_base(),
.m_plic_addr_size(),
.m_plic_addr_lim(),
.m_uart0_addr_base(),
.m_uart0_addr_size(),
.m_uart0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_mem0_controller_addr_base(),
.m_mem0_controller_addr_size(),
.m_mem0_controller_addr_lim(),
.m_tcm_addr_base(),
.m_tcm_addr_size(),
.m_tcm_addr_lim(),
.m_is_mem_addr(soc_map$m_is_mem_addr),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_rl_fabric_send_write_req
assign CAN_FIRE_RL_rl_fabric_send_write_req =
f_fabric_write_reqs$EMPTY_N && master_xactor_f_wr_addr$FULL_N &&
master_xactor_f_wr_data$FULL_N ;
assign WILL_FIRE_RL_rl_fabric_send_write_req =
CAN_FIRE_RL_rl_fabric_send_write_req ;
// rule RL_rl_reset
assign CAN_FIRE_RL_rl_reset = WILL_FIRE_RL_rl_reset ;
assign WILL_FIRE_RL_rl_reset =
(rg_cset_in_cache != 6'd63 ||
f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
rg_state == 5'd1 ;
// rule RL_rl_probe_and_immed_rsp
assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d120 &&
rg_state == 5'd3 ;
assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
CAN_FIRE_RL_rl_probe_and_immed_rsp &&
!WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_start_cache_refill
assign CAN_FIRE_RL_rl_start_cache_refill =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd9 &&
b__h26615 == 4'd0 ;
assign WILL_FIRE_RL_rl_start_cache_refill =
CAN_FIRE_RL_rl_start_cache_refill &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_cache_refill_rsps_loop
assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd10 ;
assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
!WILL_FIRE_RL_rl_start_reset &&
!EN_req ;
// rule RL_rl_rereq
assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
assign WILL_FIRE_RL_rl_rereq =
CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;
// rule RL_rl_ST_AMO_response
assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;
// rule RL_rl_io_read_req
assign CAN_FIRE_RL_rl_io_read_req =
master_xactor_f_rd_addr$FULL_N &&
rg_state_4_EQ_13_44_AND_rg_op_1_EQ_0_2_OR_rg_o_ETC___d646 ;
assign WILL_FIRE_RL_rl_io_read_req =
CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_read_rsp
assign CAN_FIRE_RL_rl_io_read_rsp =
master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd14 ;
assign WILL_FIRE_RL_rl_io_read_rsp =
CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_maintain_io_read_rsp
assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
CAN_FIRE_RL_rl_maintain_io_read_rsp ;
// rule RL_rl_io_write_req
assign CAN_FIRE_RL_rl_io_write_req =
f_fabric_write_reqs$FULL_N && rg_state == 5'd13 &&
rg_op == 2'd1 ;
assign WILL_FIRE_RL_rl_io_write_req =
CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_SC_req
assign CAN_FIRE_RL_rl_io_AMO_SC_req =
rg_state == 5'd13 && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_SC_req =
CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_op_req
assign CAN_FIRE_RL_rl_io_AMO_op_req =
master_xactor_f_rd_addr$FULL_N && rg_state == 5'd13 &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] != 5'b00010 &&
rg_amo_funct7[6:2] != 5'b00011 ;
assign WILL_FIRE_RL_rl_io_AMO_op_req =
CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;
// rule RL_rl_io_AMO_read_rsp
assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
master_xactor_f_rd_data$EMPTY_N &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
f_fabric_write_reqs$FULL_N) &&
rg_state == 5'd16 ;
assign WILL_FIRE_RL_rl_io_AMO_read_rsp = MUX_rg_state$write_1__SEL_3 ;
// rule RL_rl_discard_write_rsp
assign CAN_FIRE_RL_rl_discard_write_rsp =
b__h26615 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
assign WILL_FIRE_RL_rl_discard_write_rsp =
CAN_FIRE_RL_rl_discard_write_rsp ;
// rule RL_rl_drive_exception_rsp
assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
// rule RL_rl_start_reset
assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_2 ;
// inputs to muxes for submodule ports
assign MUX_dw_output_ld_val$wset_1__SEL_1 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_dw_output_ld_val$wset_1__SEL_3 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d181 ;
assign MUX_dw_output_ld_val$wset_1__SEL_4 =
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d526 ;
assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_state_and_ctag_cset$b_put_3__SEL_1 =
EN_req &&
req_f3_BITS_1_TO_0_29_EQ_0b0_30_OR_req_f3_BITS_ETC___d959 ;
assign MUX_ram_word64_set$a_put_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
assign MUX_ram_word64_set$b_put_1__SEL_2 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] != 3'd7 ;
assign MUX_rg_error_during_refill$write_1__SEL_1 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_1 =
EN_req &&
NOT_req_f3_BITS_1_TO_0_29_EQ_0b0_30_31_AND_NOT_ETC___d950 ;
assign MUX_rg_exc_code$write_1__SEL_2 =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_exc_code$write_1__SEL_3 =
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
assign MUX_rg_ld_val$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d378 ;
assign MUX_rg_lrsc_valid$write_1__SEL_2 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d176 ;
assign MUX_rg_state$write_1__SEL_2 =
f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
assign MUX_rg_state$write_1__SEL_3 =
CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;
assign MUX_rg_state$write_1__SEL_10 =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 ;
assign MUX_rg_state$write_1__SEL_12 =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(dmem_not_imem && !soc_map$m_is_mem_addr ||
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d135 ||
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d145) ;
assign MUX_rg_state$write_1__SEL_13 =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign MUX_dw_output_ld_val$wset_1__VAL_3 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
new_value__h6006 :
new_value__h22433 ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h32733 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
{ rg_f3,
rg_addr,
IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d528 } ;
assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
{ rg_f3, rg_pa, rg_st_amo_val } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
{ 4'd0, rg_pa, 8'd0, value__h32290, 18'd65536 } ;
assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
{ 4'd0, cline_fabric_addr__h26714, 29'd15532032 } ;
assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
{ rg_victim_way || ram_state_and_ctag_cset$DOB[105],
rg_victim_way ?
rg_pa[63:12] :
ram_state_and_ctag_cset$DOB[104:53],
!rg_victim_way || ram_state_and_ctag_cset$DOB[52],
rg_victim_way ?
ram_state_and_ctag_cset$DOB[51:0] :
rg_pa[63:12] } ;
assign MUX_ram_word64_set$a_put_3__VAL_1 =
rg_victim_way ?
{ master_xactor_f_rd_data$D_OUT[66:3],
ram_word64_set$DOB[63:0] } :
{ ram_word64_set$DOB[127:64],
master_xactor_f_rd_data$D_OUT[66:3] } ;
assign MUX_ram_word64_set$a_put_3__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
{ IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d443,
IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d444 } :
{ IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d520,
IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d521 } ;
assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ;
assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
assign MUX_rg_ld_val$write_1__VAL_2 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
x__h20014 :
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 ;
assign MUX_rg_state$write_1__VAL_1 =
NOT_req_f3_BITS_1_TO_0_29_EQ_0b0_30_31_AND_NOT_ETC___d950 ?
5'd4 :
5'd3 ;
assign MUX_rg_state$write_1__VAL_3 =
(master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
assign MUX_rg_state$write_1__VAL_10 =
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) ?
5'd4 :
5'd11 ;
assign MUX_rg_state$write_1__VAL_12 =
(dmem_not_imem && !soc_map$m_is_mem_addr) ?
5'd13 :
IF_rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d150 ;
// inlined wires
assign dw_valid$whas =
(WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp) &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d181 ||
WILL_FIRE_RL_rl_drive_exception_rsp ||
WILL_FIRE_RL_rl_maintain_io_read_rsp ||
WILL_FIRE_RL_rl_ST_AMO_response ;
assign ctr_wr_rsps_pending_crg$port0__write_1 =
ctr_wr_rsps_pending_crg + 4'd1 ;
assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h26615 - 4'd1 ;
assign ctr_wr_rsps_pending_crg$port2__read =
CAN_FIRE_RL_rl_discard_write_rsp ?
ctr_wr_rsps_pending_crg$port1__write_1 :
b__h26615 ;
assign ctr_wr_rsps_pending_crg$EN_port2__write =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
assign ctr_wr_rsps_pending_crg$port3__read =
ctr_wr_rsps_pending_crg$EN_port2__write ?
4'd0 :
ctr_wr_rsps_pending_crg$port2__read ;
// register cfg_verbosity
assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign cfg_verbosity$EN = EN_set_verbosity ;
// register ctr_wr_rsps_pending_crg
assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;
// register rg_addr
assign rg_addr$D_IN = req_addr ;
assign rg_addr$EN = EN_req ;
// register rg_amo_funct7
assign rg_amo_funct7$D_IN = req_amo_funct7 ;
assign rg_amo_funct7$EN = EN_req ;
// register rg_cset_in_cache
assign rg_cset_in_cache$D_IN =
WILL_FIRE_RL_rl_reset ?
MUX_rg_cset_in_cache$write_1__VAL_1 :
6'd0 ;
assign rg_cset_in_cache$EN =
WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;
// register rg_error_during_refill
assign rg_error_during_refill$D_IN =
MUX_rg_error_during_refill$write_1__SEL_1 ;
assign rg_error_during_refill$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_exc_code
always@(MUX_rg_exc_code$write_1__SEL_1 or
MUX_rg_exc_code$write_1__VAL_1 or
MUX_rg_exc_code$write_1__SEL_2 or
MUX_rg_exc_code$write_1__SEL_3 or
MUX_rg_error_during_refill$write_1__SEL_1 or access_exc_code__h2376)
case (1'b1)
MUX_rg_exc_code$write_1__SEL_1:
rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
MUX_rg_error_during_refill$write_1__SEL_1:
rg_exc_code$D_IN = access_exc_code__h2376;
default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
endcase
assign rg_exc_code$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
EN_req &&
NOT_req_f3_BITS_1_TO_0_29_EQ_0b0_30_31_AND_NOT_ETC___d950 ;
// register rg_f3
assign rg_f3$D_IN = req_f3 ;
assign rg_f3$EN = EN_req ;
// register rg_ld_val
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
new_ld_val__h32704 or
MUX_rg_ld_val$write_1__SEL_2 or
MUX_rg_ld_val$write_1__VAL_2 or
WILL_FIRE_RL_rl_io_read_rsp or
ld_val__h30496 or WILL_FIRE_RL_rl_io_AMO_SC_req)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h32704;
MUX_rg_ld_val$write_1__SEL_2:
rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h30496;
WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign rg_ld_val$EN =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d378 ||
WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_io_AMO_SC_req ;
// register rg_lower_word32
assign rg_lower_word32$D_IN = 32'h0 ;
assign rg_lower_word32$EN = 1'b0 ;
// register rg_lower_word32_full
assign rg_lower_word32_full$D_IN = 1'd0 ;
assign rg_lower_word32_full$EN =
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_lrsc_pa
assign rg_lrsc_pa$D_IN = rg_addr ;
assign rg_lrsc_pa$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7_4_BITS_6_TO_2_5_EQ_0b10_6_AND_ra_ETC___d360 ;
// register rg_lrsc_valid
assign rg_lrsc_valid$D_IN =
MUX_rg_lrsc_valid$write_1__SEL_2 &&
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d178 ;
assign rg_lrsc_valid$EN =
WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d176 ||
WILL_FIRE_RL_rl_start_reset ;
// register rg_op
assign rg_op$D_IN = req_op ;
assign rg_op$EN = EN_req ;
// register rg_pa
assign rg_pa$D_IN = EN_req ? req_addr : rg_addr ;
assign rg_pa$EN = EN_req || WILL_FIRE_RL_rl_probe_and_immed_rsp ;
// register rg_pte_pa
assign rg_pte_pa$D_IN = 64'h0 ;
assign rg_pte_pa$EN = 1'b0 ;
// register rg_st_amo_val
assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h23565 ;
assign rg_st_amo_val$EN =
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d573 ||
EN_req ;
// register rg_state
always@(EN_req or
MUX_rg_state$write_1__VAL_1 or
WILL_FIRE_RL_rl_start_reset or
WILL_FIRE_RL_rl_io_AMO_read_rsp or
MUX_rg_state$write_1__VAL_3 or
WILL_FIRE_RL_rl_io_AMO_op_req or
WILL_FIRE_RL_rl_io_AMO_SC_req or
WILL_FIRE_RL_rl_io_write_req or
WILL_FIRE_RL_rl_io_read_rsp or
WILL_FIRE_RL_rl_io_read_req or
WILL_FIRE_RL_rl_rereq or
MUX_rg_state$write_1__SEL_10 or
MUX_rg_state$write_1__VAL_10 or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_rg_state$write_1__SEL_12 or
MUX_rg_state$write_1__VAL_12 or MUX_rg_state$write_1__SEL_13)
case (1'b1)
EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_1;
WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
WILL_FIRE_RL_rl_io_AMO_read_rsp:
rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
rg_state$D_IN = 5'd12;
WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
MUX_rg_state$write_1__SEL_10:
rg_state$D_IN = MUX_rg_state$write_1__VAL_10;
WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
MUX_rg_state$write_1__SEL_12:
rg_state$D_IN = MUX_rg_state$write_1__VAL_12;
MUX_rg_state$write_1__SEL_13: rg_state$D_IN = 5'd2;
default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
endcase
assign rg_state$EN =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 ||
MUX_rg_state$write_1__SEL_12 ||
WILL_FIRE_RL_rl_io_AMO_read_rsp ||
WILL_FIRE_RL_rl_io_read_rsp ||
EN_req ||
WILL_FIRE_RL_rl_start_reset ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ||
WILL_FIRE_RL_rl_io_AMO_SC_req ||
WILL_FIRE_RL_rl_io_write_req ||
WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_io_AMO_op_req ;
// register rg_victim_way
assign rg_victim_way$D_IN = tmp__h26877[0] ;
assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;
// register rg_word64_set_in_cache
assign rg_word64_set_in_cache$D_IN =
MUX_ram_word64_set$b_put_1__SEL_2 ?
MUX_ram_word64_set$b_put_2__VAL_2 :
MUX_ram_word64_set$b_put_2__VAL_4 ;
assign rg_word64_set_in_cache$EN =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule f_fabric_write_reqs
always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_1 or
MUX_f_fabric_write_reqs$enq_1__SEL_2 or
MUX_f_fabric_write_reqs$enq_1__VAL_2 or
WILL_FIRE_RL_rl_io_write_req or
MUX_f_fabric_write_reqs$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
MUX_dw_output_ld_val$wset_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
MUX_f_fabric_write_reqs$enq_1__SEL_2:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
WILL_FIRE_RL_rl_io_write_req:
f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
default: f_fabric_write_reqs$D_IN =
131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign f_fabric_write_reqs$ENQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d526 ||
WILL_FIRE_RL_rl_io_write_req ;
assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign f_fabric_write_reqs$CLR = 1'b0 ;
// submodule f_reset_reqs
assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
assign f_reset_reqs$ENQ =
EN_server_reset_request_put || EN_server_flush_request_put ;
assign f_reset_reqs$DEQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_reqs$CLR = 1'b0 ;
// submodule f_reset_rsps
assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
assign f_reset_rsps$ENQ =
WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
assign f_reset_rsps$DEQ =
EN_server_flush_response_get || EN_server_reset_response_get ;
assign f_reset_rsps$CLR = 1'b0 ;
// submodule master_xactor_f_rd_addr
assign master_xactor_f_rd_addr$D_IN =
MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
MUX_master_xactor_f_rd_addr$enq_1__VAL_1 :
MUX_master_xactor_f_rd_addr$enq_1__VAL_2 ;
assign master_xactor_f_rd_addr$ENQ =
WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ||
WILL_FIRE_RL_rl_start_cache_refill ;
assign master_xactor_f_rd_addr$DEQ =
master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
assign master_xactor_f_rd_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_rd_data
assign master_xactor_f_rd_data$D_IN =
{ mem_master_rid,
mem_master_rdata,
mem_master_rresp,
mem_master_rlast } ;
assign master_xactor_f_rd_data$ENQ =
mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
assign master_xactor_f_rd_data$DEQ =
WILL_FIRE_RL_rl_io_AMO_read_rsp || WILL_FIRE_RL_rl_io_read_rsp ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop ;
assign master_xactor_f_rd_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_addr
assign master_xactor_f_wr_addr$D_IN =
{ 4'd0,
f_fabric_write_reqs$D_OUT[127:64],
8'd0,
x__h2641,
18'd65536 } ;
assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_addr$DEQ =
master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
assign master_xactor_f_wr_addr$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_data
assign master_xactor_f_wr_data$D_IN =
{ mem_req_wr_data_wdata__h2820,
mem_req_wr_data_wstrb__h2821,
1'd1 } ;
assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
assign master_xactor_f_wr_data$DEQ =
master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
assign master_xactor_f_wr_data$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule master_xactor_f_wr_resp
assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
assign master_xactor_f_wr_resp$ENQ =
mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
assign master_xactor_f_wr_resp$CLR =
WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
// submodule ram_state_and_ctag_cset
assign ram_state_and_ctag_cset$ADDRA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
rg_addr[11:6] :
rg_cset_in_cache ;
assign ram_state_and_ctag_cset$ADDRB =
MUX_ram_state_and_ctag_cset$b_put_3__SEL_1 ?
req_addr[11:6] :
rg_addr[11:6] ;
assign ram_state_and_ctag_cset$DIA =
MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
106'h15555555555554AAAAAAAAAAAAA ;
assign ram_state_and_ctag_cset$DIB =
MUX_ram_state_and_ctag_cset$b_put_3__SEL_1 ?
106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ :
106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
assign ram_state_and_ctag_cset$WEA = 1'd1 ;
assign ram_state_and_ctag_cset$WEB = 1'd0 ;
assign ram_state_and_ctag_cset$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd0 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_reset ;
assign ram_state_and_ctag_cset$ENB =
EN_req &&
req_f3_BITS_1_TO_0_29_EQ_0b0_30_OR_req_f3_BITS_ETC___d959 ||
WILL_FIRE_RL_rl_rereq ;
// submodule ram_word64_set
assign ram_word64_set$ADDRA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
rg_word64_set_in_cache :
rg_addr[11:3] ;
always@(MUX_ram_state_and_ctag_cset$b_put_3__SEL_1 or
req_addr or
MUX_ram_word64_set$b_put_1__SEL_2 or
MUX_ram_word64_set$b_put_2__VAL_2 or
WILL_FIRE_RL_rl_rereq or
rg_addr or
WILL_FIRE_RL_rl_start_cache_refill or
MUX_ram_word64_set$b_put_2__VAL_4)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_3__SEL_1:
ram_word64_set$ADDRB = req_addr[11:3];
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2;
WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3];
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4;
default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ;
endcase
end
assign ram_word64_set$DIA =
MUX_ram_word64_set$a_put_1__SEL_1 ?
MUX_ram_word64_set$a_put_3__VAL_1 :
MUX_ram_word64_set$a_put_3__VAL_2 ;
always@(MUX_ram_state_and_ctag_cset$b_put_3__SEL_1 or
MUX_ram_word64_set$b_put_1__SEL_2 or
WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
begin
case (1'b1) // synopsys parallel_case
MUX_ram_state_and_ctag_cset$b_put_3__SEL_1:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
MUX_ram_word64_set$b_put_1__SEL_2:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_rereq:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
WILL_FIRE_RL_rl_start_cache_refill:
ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
default: ram_word64_set$DIB =
128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign ram_word64_set$WEA = 1'd1 ;
assign ram_word64_set$WEB = 1'd0 ;
assign ram_word64_set$ENA =
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d389 ;
assign ram_word64_set$ENB =
EN_req &&
req_f3_BITS_1_TO_0_29_EQ_0b0_30_OR_req_f3_BITS_ETC___d959 ||
WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] != 3'd7 ||
WILL_FIRE_RL_rl_rereq ||
WILL_FIRE_RL_rl_start_cache_refill ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = rg_addr ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d148 =
((!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113)) ?
5'd9 :
5'd12 ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d444 =
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ?
n__h20793 :
ram_word64_set$DOB[63:0] ;
assign IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d521 =
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ?
n__h23729 :
ram_word64_set$DOB[63:0] ;
assign IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d443 =
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ?
n__h20793 :
ram_word64_set$DOB[127:64] ;
assign IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d520 =
(ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ?
n__h23729 :
ram_word64_set$DOB[127:64] ;
assign IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_1_E_ETC___d351 =
(rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
assign IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844 =
(rg_addr[2:0] == 3'h0) ? ld_val__h30496 : 64'd0 ;
assign IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336 =
(rg_addr[2:0] == 3'h0) ? word64__h5839 : 64'd0 ;
assign IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC__q31 =
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343[31:0] ;
assign IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 =
(rg_f3 == 3'b010) ?
{ {32{rg_st_amo_val_BITS_31_TO_0__q32[31]}},
rg_st_amo_val_BITS_31_TO_0__q32 } :
rg_st_amo_val ;
assign IF_rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d150 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
5'd9 :
IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d149 ;
assign IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d118 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20004 ||
f_fabric_write_reqs$FULL_N :
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d117 ;
assign IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d149 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
5'd12 :
IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d148 ;
assign IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d528 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
rg_st_amo_val :
new_st_val__h23565 ;
assign NOT_cfg_verbosity_read__9_ULE_1_0___d41 = cfg_verbosity > 4'd1 ;
assign NOT_cfg_verbosity_read__9_ULE_2_94___d595 = cfg_verbosity > 4'd2 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d158 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 &&
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d357 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d355 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d365 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d355 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d368 =
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d366 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d374 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d371 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d378 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
NOT_rg_op_1_EQ_1_9_70_AND_ram_state_and_ctag_c_ETC___d375) ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d389 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d387 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d531 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
rg_addr_7_EQ_rg_lrsc_pa_5___d162 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d543 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d573 =
(!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
NOT_rg_op_1_EQ_1_9_70_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d386 ;
assign NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d117 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ||
f_fabric_write_reqs$FULL_N ;
assign NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d164 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 &&
rg_addr_7_EQ_rg_lrsc_pa_5___d162 ;
assign NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d366 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d371 =
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
rg_addr_7_EQ_rg_lrsc_pa_5___d162 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign NOT_req_f3_BITS_1_TO_0_29_EQ_0b0_30_31_AND_NOT_ETC___d950 =
req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
(req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
(req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
assign NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d145 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_5_EQ_rg_addr_7___d96) ;
assign NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d526 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d524 ||
NOT_rg_op_1_EQ_1_9_70_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d386) ;
assign NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d544 ;
assign NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d554 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d552 ;
assign NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566 =
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d355 ;
assign NOT_rg_op_1_EQ_1_9_70_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d386 =
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ;
assign NOT_rg_op_1_EQ_1_9_70_AND_ram_state_and_ctag_c_ETC___d375 =
rg_op != 2'd1 &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ;
assign NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d384 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_5_EQ_rg_addr_7___d96) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ;
assign NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d544 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_5_EQ_rg_addr_7___d96) &&
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d355 ;
assign NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d548 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_5_EQ_rg_addr_7___d96) &&
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d366 ;
assign NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d552 =
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_5_EQ_rg_addr_7___d96) &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign _theResult___snd_fst__h2828 =
f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2608 ;
assign access_exc_code__h2376 =
dmem_not_imem ?
((rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
4'd5 :
4'd7) :
4'd1 ;
assign b__h26615 =
CAN_FIRE_RL_rl_fabric_send_write_req ?
ctr_wr_rsps_pending_crg$port0__write_1 :
ctr_wr_rsps_pending_crg ;
assign cline_fabric_addr__h26714 = { rg_pa[63:6], 6'd0 } ;
assign dmem_not_imem_AND_NOT_soc_map_m_is_mem_addr_rg_ETC___d120 =
dmem_not_imem && !soc_map$m_is_mem_addr || rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
IF_rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_ETC___d118 ;
assign ld_val0496_BITS_15_TO_0__q37 = ld_val__h30496[15:0] ;
assign ld_val0496_BITS_15_TO_8__q39 = ld_val__h30496[15:8] ;
assign ld_val0496_BITS_23_TO_16__q40 = ld_val__h30496[23:16] ;
assign ld_val0496_BITS_31_TO_0__q38 = ld_val__h30496[31:0] ;
assign ld_val0496_BITS_31_TO_16__q41 = ld_val__h30496[31:16] ;
assign ld_val0496_BITS_31_TO_24__q42 = ld_val__h30496[31:24] ;
assign ld_val0496_BITS_39_TO_32__q43 = ld_val__h30496[39:32] ;
assign ld_val0496_BITS_47_TO_32__q44 = ld_val__h30496[47:32] ;
assign ld_val0496_BITS_47_TO_40__q46 = ld_val__h30496[47:40] ;
assign ld_val0496_BITS_55_TO_48__q47 = ld_val__h30496[55:48] ;
assign ld_val0496_BITS_63_TO_32__q45 = ld_val__h30496[63:32] ;
assign ld_val0496_BITS_63_TO_48__q48 = ld_val__h30496[63:48] ;
assign ld_val0496_BITS_63_TO_56__q49 = ld_val__h30496[63:56] ;
assign ld_val0496_BITS_7_TO_0__q36 = ld_val__h30496[7:0] ;
assign lrsc_result__h20004 =
!rg_lrsc_valid || !rg_lrsc_pa_5_EQ_rg_addr_7___d96 ;
assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
master_xactor_f_rd_data$D_OUT[10:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
master_xactor_f_rd_data$D_OUT[18:11] ;
assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
master_xactor_f_rd_data$D_OUT[18:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 =
master_xactor_f_rd_data$D_OUT[26:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 =
master_xactor_f_rd_data$D_OUT[34:19] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8 =
master_xactor_f_rd_data$D_OUT[34:27] ;
assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
master_xactor_f_rd_data$D_OUT[34:3] ;
assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q9 =
master_xactor_f_rd_data$D_OUT[42:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q6 =
master_xactor_f_rd_data$D_OUT[50:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
master_xactor_f_rd_data$D_OUT[50:43] ;
assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
master_xactor_f_rd_data$D_OUT[58:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
master_xactor_f_rd_data$D_OUT[66:35] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
master_xactor_f_rd_data$D_OUT[66:51] ;
assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
master_xactor_f_rd_data$D_OUT[66:59] ;
assign new_st_val__h23565 =
(rg_f3 == 3'b010) ?
new_st_val__h23871 :
_theResult_____2__h23867 ;
assign new_st_val__h23871 = { 32'd0, _theResult_____2__h23867[31:0] } ;
assign new_st_val__h23962 =
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 +
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 ;
assign new_st_val__h24942 = w1__h23859 ^ w2__h32744 ;
assign new_st_val__h24946 = w1__h23859 & w2__h32744 ;
assign new_st_val__h24950 = w1__h23859 | w2__h32744 ;
assign new_st_val__h24954 =
(w1__h23859 < w2__h32744) ? w1__h23859 : w2__h32744 ;
assign new_st_val__h24959 =
(w1__h23859 <= w2__h32744) ? w2__h32744 : w1__h23859 ;
assign new_st_val__h24965 =
((IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 ^
64'h8000000000000000) <
(IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 ^
64'h8000000000000000)) ?
w1__h23859 :
w2__h32744 ;
assign new_st_val__h24970 =
((IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 ^
64'h8000000000000000) <=
(IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 ^
64'h8000000000000000)) ?
w2__h32744 :
w1__h23859 ;
assign new_st_val__h32754 = { 32'd0, _theResult_____2__h32750[31:0] } ;
assign new_st_val__h32845 =
new_ld_val__h32704 +
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 ;
assign new_st_val__h34705 = w1__h32742 ^ w2__h32744 ;
assign new_st_val__h34709 = w1__h32742 & w2__h32744 ;
assign new_st_val__h34713 = w1__h32742 | w2__h32744 ;
assign new_st_val__h34717 =
(w1__h32742 < w2__h32744) ? w1__h32742 : w2__h32744 ;
assign new_st_val__h34722 =
(w1__h32742 <= w2__h32744) ? w2__h32744 : w1__h32742 ;
assign new_st_val__h34728 =
((new_ld_val__h32704 ^ 64'h8000000000000000) <
(IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 ^
64'h8000000000000000)) ?
w1__h32742 :
w2__h32744 ;
assign new_st_val__h34733 =
((new_ld_val__h32704 ^ 64'h8000000000000000) <=
(IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_rg_st_amo_val_ETC___d451 ^
64'h8000000000000000)) ?
w2__h32744 :
w1__h32742 ;
assign new_value__h22433 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
64'd1 :
CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_27_EQ__ETC__q52 ;
assign new_value__h6006 =
(rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
word64__h5839 :
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 ;
assign ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113 =
ram_state_and_ctag_cset$DOB[104:53] == rg_addr[63:12] ;
assign ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 =
ram_state_and_ctag_cset$DOB[51:0] == rg_addr[63:12] ;
assign ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d161 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00010 ;
assign ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d172 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
rg_addr_7_EQ_rg_lrsc_pa_5___d162 ;
assign ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d355 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d568 =
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) &&
rg_addr_7_EQ_rg_lrsc_pa_5___d162 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign req_f3_BITS_1_TO_0_29_EQ_0b0_30_OR_req_f3_BITS_ETC___d959 =
req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
assign result__h18715 =
{ {56{word64839_BITS_7_TO_0__q15[7]}},
word64839_BITS_7_TO_0__q15 } ;
assign result__h18743 =
{ {56{word64839_BITS_15_TO_8__q18[7]}},
word64839_BITS_15_TO_8__q18 } ;
assign result__h18771 =
{ {56{word64839_BITS_23_TO_16__q19[7]}},
word64839_BITS_23_TO_16__q19 } ;
assign result__h18799 =
{ {56{word64839_BITS_31_TO_24__q21[7]}},
word64839_BITS_31_TO_24__q21 } ;
assign result__h18827 =
{ {56{word64839_BITS_39_TO_32__q22[7]}},
word64839_BITS_39_TO_32__q22 } ;
assign result__h18855 =
{ {56{word64839_BITS_47_TO_40__q25[7]}},
word64839_BITS_47_TO_40__q25 } ;
assign result__h18883 =
{ {56{word64839_BITS_55_TO_48__q26[7]}},
word64839_BITS_55_TO_48__q26 } ;
assign result__h18911 =
{ {56{word64839_BITS_63_TO_56__q28[7]}},
word64839_BITS_63_TO_56__q28 } ;
assign result__h18956 = { 56'd0, word64__h5839[7:0] } ;
assign result__h18984 = { 56'd0, word64__h5839[15:8] } ;
assign result__h19012 = { 56'd0, word64__h5839[23:16] } ;
assign result__h19040 = { 56'd0, word64__h5839[31:24] } ;
assign result__h19068 = { 56'd0, word64__h5839[39:32] } ;
assign result__h19096 = { 56'd0, word64__h5839[47:40] } ;
assign result__h19124 = { 56'd0, word64__h5839[55:48] } ;
assign result__h19152 = { 56'd0, word64__h5839[63:56] } ;
assign result__h19197 =
{ {48{word64839_BITS_15_TO_0__q16[15]}},
word64839_BITS_15_TO_0__q16 } ;
assign result__h19225 =
{ {48{word64839_BITS_31_TO_16__q20[15]}},
word64839_BITS_31_TO_16__q20 } ;
assign result__h19253 =
{ {48{word64839_BITS_47_TO_32__q23[15]}},
word64839_BITS_47_TO_32__q23 } ;
assign result__h19281 =
{ {48{word64839_BITS_63_TO_48__q27[15]}},
word64839_BITS_63_TO_48__q27 } ;
assign result__h19322 = { 48'd0, word64__h5839[15:0] } ;
assign result__h19350 = { 48'd0, word64__h5839[31:16] } ;
assign result__h19378 = { 48'd0, word64__h5839[47:32] } ;
assign result__h19406 = { 48'd0, word64__h5839[63:48] } ;
assign result__h19447 =
{ {32{word64839_BITS_31_TO_0__q17[31]}},
word64839_BITS_31_TO_0__q17 } ;
assign result__h19475 =
{ {32{word64839_BITS_63_TO_32__q24[31]}},
word64839_BITS_63_TO_32__q24 } ;
assign result__h19514 = { 32'd0, word64__h5839[31:0] } ;
assign result__h19542 = { 32'd0, word64__h5839[63:32] } ;
assign result__h30556 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
assign result__h30586 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
assign result__h30613 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5[7]}},
master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 } ;
assign result__h30640 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8[7]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q8 } ;
assign result__h30667 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q9[7]}},
master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q9 } ;
assign result__h30694 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
assign result__h30721 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
assign result__h30748 =
{ {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
assign result__h30792 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
assign result__h30819 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
assign result__h30846 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
assign result__h30873 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
assign result__h30900 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
assign result__h30927 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
assign result__h30954 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
assign result__h30981 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
assign result__h31025 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
assign result__h31052 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7[15]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q7 } ;
assign result__h31079 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q6[15]}},
master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q6 } ;
assign result__h31106 =
{ {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
assign result__h31146 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
assign result__h31173 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
assign result__h31200 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
assign result__h31227 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
assign result__h31267 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
assign result__h31294 =
{ {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
assign result__h31332 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
assign result__h31359 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
assign result__h32933 =
{ {56{ld_val0496_BITS_7_TO_0__q36[7]}},
ld_val0496_BITS_7_TO_0__q36 } ;
assign result__h33841 =
{ {56{ld_val0496_BITS_15_TO_8__q39[7]}},
ld_val0496_BITS_15_TO_8__q39 } ;
assign result__h33869 =
{ {56{ld_val0496_BITS_23_TO_16__q40[7]}},
ld_val0496_BITS_23_TO_16__q40 } ;
assign result__h33897 =
{ {56{ld_val0496_BITS_31_TO_24__q42[7]}},
ld_val0496_BITS_31_TO_24__q42 } ;
assign result__h33925 =
{ {56{ld_val0496_BITS_39_TO_32__q43[7]}},
ld_val0496_BITS_39_TO_32__q43 } ;
assign result__h33953 =
{ {56{ld_val0496_BITS_47_TO_40__q46[7]}},
ld_val0496_BITS_47_TO_40__q46 } ;
assign result__h33981 =
{ {56{ld_val0496_BITS_55_TO_48__q47[7]}},
ld_val0496_BITS_55_TO_48__q47 } ;
assign result__h34009 =
{ {56{ld_val0496_BITS_63_TO_56__q49[7]}},
ld_val0496_BITS_63_TO_56__q49 } ;
assign result__h34054 = { 56'd0, ld_val__h30496[7:0] } ;
assign result__h34082 = { 56'd0, ld_val__h30496[15:8] } ;
assign result__h34110 = { 56'd0, ld_val__h30496[23:16] } ;
assign result__h34138 = { 56'd0, ld_val__h30496[31:24] } ;
assign result__h34166 = { 56'd0, ld_val__h30496[39:32] } ;
assign result__h34194 = { 56'd0, ld_val__h30496[47:40] } ;
assign result__h34222 = { 56'd0, ld_val__h30496[55:48] } ;
assign result__h34250 = { 56'd0, ld_val__h30496[63:56] } ;
assign result__h34295 =
{ {48{ld_val0496_BITS_15_TO_0__q37[15]}},
ld_val0496_BITS_15_TO_0__q37 } ;
assign result__h34323 =
{ {48{ld_val0496_BITS_31_TO_16__q41[15]}},
ld_val0496_BITS_31_TO_16__q41 } ;
assign result__h34351 =
{ {48{ld_val0496_BITS_47_TO_32__q44[15]}},
ld_val0496_BITS_47_TO_32__q44 } ;
assign result__h34379 =
{ {48{ld_val0496_BITS_63_TO_48__q48[15]}},
ld_val0496_BITS_63_TO_48__q48 } ;
assign result__h34420 = { 48'd0, ld_val__h30496[15:0] } ;
assign result__h34448 = { 48'd0, ld_val__h30496[31:16] } ;
assign result__h34476 = { 48'd0, ld_val__h30496[47:32] } ;
assign result__h34504 = { 48'd0, ld_val__h30496[63:48] } ;
assign result__h34545 =
{ {32{ld_val0496_BITS_31_TO_0__q38[31]}},
ld_val0496_BITS_31_TO_0__q38 } ;
assign result__h34573 =
{ {32{ld_val0496_BITS_63_TO_32__q45[31]}},
ld_val0496_BITS_63_TO_32__q45 } ;
assign result__h34612 = { 32'd0, ld_val__h30496[31:0] } ;
assign result__h34640 = { 32'd0, ld_val__h30496[63:32] } ;
assign rg_addr_7_EQ_rg_lrsc_pa_5___d162 = rg_addr == rg_lrsc_pa ;
assign rg_amo_funct7_4_BITS_6_TO_2_5_EQ_0b10_6_AND_ra_ETC___d360 =
rg_amo_funct7[6:2] == 5'b00010 &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ;
assign rg_lrsc_pa_5_EQ_rg_addr_7___d96 = rg_lrsc_pa == rg_addr ;
assign rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d135 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(!ram_state_and_ctag_cset$DOB[52] ||
!ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107) &&
(!ram_state_and_ctag_cset$DOB[105] ||
!ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ;
assign rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d166 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d161 ||
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d164) ;
assign rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d176 =
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d166 ||
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d174 ;
assign rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d178 =
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
(ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107 ||
ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113) ;
assign rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d181 =
rg_op_1_EQ_0_2_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d178 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20004 ;
assign rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d174 =
rg_op == 2'd1 && rg_addr_7_EQ_rg_lrsc_pa_5___d162 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d172 ;
assign rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d387 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d384 ||
NOT_rg_op_1_EQ_1_9_70_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d386 ;
assign rg_op_1_EQ_1_9_OR_rg_op_1_EQ_2_3_AND_rg_amo_fu_ETC___d524 =
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
rg_lrsc_valid && rg_lrsc_pa_5_EQ_rg_addr_7___d96) ;
assign rg_op_1_EQ_2_3_AND_rg_amo_funct7_4_BITS_6_TO_2_ETC___d558 =
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
lrsc_result__h20004 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 ;
assign rg_st_amo_val_BITS_31_TO_0__q32 = rg_st_amo_val[31:0] ;
assign rg_state_4_EQ_13_44_AND_rg_op_1_EQ_0_2_OR_rg_o_ETC___d646 =
rg_state == 5'd13 &&
(rg_op == 2'd0 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
b__h26615 == 4'd0 ;
assign shift_bits__h2608 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
assign strobe64__h2758 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2760 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
assign strobe64__h2762 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
assign tmp__h26876 = { 1'd0, rg_victim_way } ;
assign tmp__h26877 = tmp__h26876 + 2'd1 ;
assign w12738_BITS_31_TO_0__q51 = w1__h32738[31:0] ;
assign w1___1__h23930 =
{ 32'd0,
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343[31:0] } ;
assign w1___1__h32813 = { 32'd0, w1__h32738[31:0] } ;
assign w2___1__h32814 = { 32'd0, rg_st_amo_val[31:0] } ;
assign w2__h32744 = (rg_f3 == 3'b010) ? w2___1__h32814 : rg_st_amo_val ;
assign word64839_BITS_15_TO_0__q16 = word64__h5839[15:0] ;
assign word64839_BITS_15_TO_8__q18 = word64__h5839[15:8] ;
assign word64839_BITS_23_TO_16__q19 = word64__h5839[23:16] ;
assign word64839_BITS_31_TO_0__q17 = word64__h5839[31:0] ;
assign word64839_BITS_31_TO_16__q20 = word64__h5839[31:16] ;
assign word64839_BITS_31_TO_24__q21 = word64__h5839[31:24] ;
assign word64839_BITS_39_TO_32__q22 = word64__h5839[39:32] ;
assign word64839_BITS_47_TO_32__q23 = word64__h5839[47:32] ;
assign word64839_BITS_47_TO_40__q25 = word64__h5839[47:40] ;
assign word64839_BITS_55_TO_48__q26 = word64__h5839[55:48] ;
assign word64839_BITS_63_TO_32__q24 = word64__h5839[63:32] ;
assign word64839_BITS_63_TO_48__q27 = word64__h5839[63:48] ;
assign word64839_BITS_63_TO_56__q28 = word64__h5839[63:56] ;
assign word64839_BITS_7_TO_0__q15 = word64__h5839[7:0] ;
assign word64__h5839 = x__h6029 | y__h6030 ;
assign x__h20014 = { 63'd0, lrsc_result__h20004 } ;
assign x__h32733 =
(rg_f3 == 3'b010) ?
new_st_val__h32754 :
_theResult_____2__h32750 ;
assign x__h6029 = ram_word64_set$DOB[63:0] & y__h6044 ;
assign y__h12359 =
{64{ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113}} ;
assign y__h6030 = ram_word64_set$DOB[127:64] & y__h12359 ;
assign y__h6044 =
{64{ram_state_and_ctag_cset$DOB[52] &&
ram_state_and_ctag_cset_b_read__02_BITS_51_TO__ETC___d107}} ;
always@(f_fabric_write_reqs$D_OUT)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0: x__h2641 = 3'b0;
2'b01: x__h2641 = 3'b001;
2'b10: x__h2641 = 3'b010;
2'b11: x__h2641 = 3'b011;
endcase
end
always@(rg_f3)
begin
case (rg_f3[1:0])
2'b0: value__h32290 = 3'b0;
2'b01: value__h32290 = 3'b001;
2'b10: value__h32290 = 3'b010;
2'd3: value__h32290 = 3'b011;
endcase
end
always@(f_fabric_write_reqs$D_OUT or
strobe64__h2758 or strobe64__h2760 or strobe64__h2762)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0: mem_req_wr_data_wstrb__h2821 = strobe64__h2758;
2'b01: mem_req_wr_data_wstrb__h2821 = strobe64__h2760;
2'b10: mem_req_wr_data_wstrb__h2821 = strobe64__h2762;
2'b11: mem_req_wr_data_wstrb__h2821 = 8'b11111111;
endcase
end
always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h2828)
begin
case (f_fabric_write_reqs$D_OUT[129:128])
2'b0, 2'b01, 2'b10:
mem_req_wr_data_wdata__h2820 = _theResult___snd_fst__h2828;
2'd3: mem_req_wr_data_wdata__h2820 = f_fabric_write_reqs$D_OUT[63:0];
endcase
end
always@(ram_state_and_ctag_cset$DOB or
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113 or
ram_word64_set$DOB)
begin
case (ram_state_and_ctag_cset$DOB[105] &&
ram_state_and_ctag_cset_b_read__02_BITS_104_TO_ETC___d113)
1'd0: old_word64__h20782 = ram_word64_set$DOB[63:0];
1'd1: old_word64__h20782 = ram_word64_set$DOB[127:64];
endcase
end
always@(rg_addr or
result__h18715 or
result__h18743 or
result__h18771 or
result__h18799 or
result__h18827 or
result__h18855 or result__h18883 or result__h18911)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18715;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18743;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18771;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18799;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18827;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18855;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18883;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 =
result__h18911;
endcase
end
always@(rg_addr or
result__h18956 or
result__h18984 or
result__h19012 or
result__h19040 or
result__h19068 or
result__h19096 or result__h19124 or result__h19152)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h18956;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h18984;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h19012;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h19040;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h19068;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h19096;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h19124;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 =
result__h19152;
endcase
end
always@(rg_addr or
result__h19197 or
result__h19225 or result__h19253 or result__h19281)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 =
result__h19197;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 =
result__h19225;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 =
result__h19253;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 =
result__h19281;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 =
64'd0;
endcase
end
always@(rg_addr or
result__h19322 or
result__h19350 or result__h19378 or result__h19406)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 =
result__h19322;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 =
result__h19350;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 =
result__h19378;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 =
result__h19406;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 =
64'd0;
endcase
end
always@(rg_addr or result__h19514 or result__h19542)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334 =
result__h19514;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334 =
result__h19542;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334 =
64'd0;
endcase
end
always@(rg_addr or result__h19447 or result__h19475)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result9447_0x4_re_ETC__q29 =
result__h19447;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result9447_0x4_re_ETC__q29 =
result__h19475;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result9447_0x4_re_ETC__q29 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 or
CASE_rg_addr_BITS_2_TO_0_0x0_result9447_0x4_re_ETC__q29 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334)
begin
case (rg_f3)
3'b0:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283;
3'b001:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313;
3'b010:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
CASE_rg_addr_BITS_2_TO_0_0x0_result9447_0x4_re_ETC__q29;
3'b011:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336;
3'b100:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300;
3'b101:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322;
3'b110:
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334;
3'd7: IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC___d343 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 or
w1___1__h23930 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334)
begin
case (rg_f3)
3'b0:
w1__h23859 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283;
3'b001:
w1__h23859 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313;
3'b010: w1__h23859 = w1___1__h23930;
3'b011:
w1__h23859 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336;
3'b100:
w1__h23859 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300;
3'b101:
w1__h23859 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322;
3'b110:
w1__h23859 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334;
3'd7: w1__h23859 = 64'd0;
endcase
end
always@(rg_addr or old_word64__h20782 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433 =
{ old_word64__h20782[63:16], rg_st_amo_val[15:0] };
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433 =
{ old_word64__h20782[63:32],
rg_st_amo_val[15:0],
old_word64__h20782[15:0] };
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433 =
{ old_word64__h20782[63:48],
rg_st_amo_val[15:0],
old_word64__h20782[31:0] };
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433 =
{ rg_st_amo_val[15:0], old_word64__h20782[47:0] };
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433 =
old_word64__h20782;
endcase
end
always@(rg_addr or old_word64__h20782 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:8], rg_st_amo_val[7:0] };
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:16],
rg_st_amo_val[7:0],
old_word64__h20782[7:0] };
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:24],
rg_st_amo_val[7:0],
old_word64__h20782[15:0] };
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:32],
rg_st_amo_val[7:0],
old_word64__h20782[23:0] };
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:40],
rg_st_amo_val[7:0],
old_word64__h20782[31:0] };
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:48],
rg_st_amo_val[7:0],
old_word64__h20782[39:0] };
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ old_word64__h20782[63:56],
rg_st_amo_val[7:0],
old_word64__h20782[47:0] };
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 =
{ rg_st_amo_val[7:0], old_word64__h20782[55:0] };
endcase
end
always@(rg_addr or old_word64__h20782 or rg_st_amo_val)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q30 =
{ old_word64__h20782[63:32], rg_st_amo_val[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q30 =
{ rg_st_amo_val[31:0], old_word64__h20782[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q30 =
old_word64__h20782;
endcase
end
always@(rg_f3 or
old_word64__h20782 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q30 or
rg_st_amo_val)
begin
case (rg_f3)
3'b0:
n__h20793 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d424;
3'b001:
n__h20793 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d433;
3'b010:
n__h20793 = CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q30;
3'b011: n__h20793 = rg_st_amo_val;
default: n__h20793 = old_word64__h20782;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313 or
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC__q31 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334)
begin
case (rg_f3)
3'b0:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d283;
3'b001:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d313;
3'b010:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
{ {32{IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC__q31[31]}},
IF_rg_f3_50_EQ_0b0_51_THEN_IF_rg_addr_7_BITS_2_ETC__q31 };
3'b011:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_ram_ETC___d336;
3'b100:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d300;
3'b101:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d322;
3'b110:
IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d334;
3'd7: IF_rg_f3_50_EQ_0b10_23_THEN_SEXT_IF_rg_f3_50_E_ETC___d382 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h24970 or
new_st_val__h23962 or
w2__h32744 or
new_st_val__h24942 or
new_st_val__h24950 or
new_st_val__h24946 or
new_st_val__h24965 or new_st_val__h24954 or new_st_val__h24959)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h23867 = new_st_val__h23962;
5'b00001: _theResult_____2__h23867 = w2__h32744;
5'b00100: _theResult_____2__h23867 = new_st_val__h24942;
5'b01000: _theResult_____2__h23867 = new_st_val__h24950;
5'b01100: _theResult_____2__h23867 = new_st_val__h24946;
5'b10000: _theResult_____2__h23867 = new_st_val__h24965;
5'b11000: _theResult_____2__h23867 = new_st_val__h24954;
5'b11100: _theResult_____2__h23867 = new_st_val__h24959;
default: _theResult_____2__h23867 = new_st_val__h24970;
endcase
end
always@(rg_addr or old_word64__h20782 or new_st_val__h23565)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510 =
{ old_word64__h20782[63:16], new_st_val__h23565[15:0] };
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510 =
{ old_word64__h20782[63:32],
new_st_val__h23565[15:0],
old_word64__h20782[15:0] };
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510 =
{ old_word64__h20782[63:48],
new_st_val__h23565[15:0],
old_word64__h20782[31:0] };
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510 =
{ new_st_val__h23565[15:0], old_word64__h20782[47:0] };
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510 =
old_word64__h20782;
endcase
end
always@(rg_addr or old_word64__h20782 or new_st_val__h23565)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:8], new_st_val__h23565[7:0] };
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:16],
new_st_val__h23565[7:0],
old_word64__h20782[7:0] };
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:24],
new_st_val__h23565[7:0],
old_word64__h20782[15:0] };
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:32],
new_st_val__h23565[7:0],
old_word64__h20782[23:0] };
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:40],
new_st_val__h23565[7:0],
old_word64__h20782[31:0] };
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:48],
new_st_val__h23565[7:0],
old_word64__h20782[39:0] };
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ old_word64__h20782[63:56],
new_st_val__h23565[7:0],
old_word64__h20782[47:0] };
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 =
{ new_st_val__h23565[7:0], old_word64__h20782[55:0] };
endcase
end
always@(rg_addr or old_word64__h20782 or new_st_val__h23565)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q33 =
{ old_word64__h20782[63:32], new_st_val__h23565[31:0] };
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q33 =
{ new_st_val__h23565[31:0], old_word64__h20782[31:0] };
default: CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q33 =
old_word64__h20782;
endcase
end
always@(rg_f3 or
old_word64__h20782 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510 or
CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q33 or
new_st_val__h23565)
begin
case (rg_f3)
3'b0:
n__h23729 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d501;
3'b001:
n__h23729 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEL_ETC___d510;
3'b010:
n__h23729 = CASE_rg_addr_BITS_2_TO_0_0x0_old_word640782_BI_ETC__q33;
3'b011: n__h23729 = new_st_val__h23565;
default: n__h23729 = old_word64__h20782;
endcase
end
always@(rg_addr or
result__h31146 or
result__h31173 or result__h31200 or result__h31227)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724 =
result__h31146;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724 =
result__h31173;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724 =
result__h31200;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724 =
result__h31227;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724 =
64'd0;
endcase
end
always@(rg_addr or
result__h31025 or
result__h31052 or result__h31079 or result__h31106)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716 =
result__h31025;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716 =
result__h31052;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716 =
result__h31079;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716 =
result__h31106;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716 =
64'd0;
endcase
end
always@(rg_addr or
result__h30792 or
result__h30819 or
result__h30846 or
result__h30873 or
result__h30900 or
result__h30927 or result__h30954 or result__h30981)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30792;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30819;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30846;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30873;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30900;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30927;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30954;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 =
result__h30981;
endcase
end
always@(rg_addr or
result__h30556 or
result__h30586 or
result__h30613 or
result__h30640 or
result__h30667 or
result__h30694 or result__h30721 or result__h30748)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30556;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30586;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30613;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30640;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30667;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30694;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30721;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 =
result__h30748;
endcase
end
always@(rg_addr or result__h31267 or result__h31294)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1267_0x4_re_ETC__q34 =
result__h31267;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1267_0x4_re_ETC__q34 =
result__h31294;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1267_0x4_re_ETC__q34 =
64'd0;
endcase
end
always@(rg_addr or result__h31332 or result__h31359)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result1332_0x4_re_ETC__q35 =
result__h31332;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result1332_0x4_re_ETC__q35 =
result__h31359;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result1332_0x4_re_ETC__q35 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1267_0x4_re_ETC__q34 or
rg_addr or
master_xactor_f_rd_data$D_OUT or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724 or
CASE_rg_addr_BITS_2_TO_0_0x0_result1332_0x4_re_ETC__q35)
begin
case (rg_f3)
3'b0:
ld_val__h30496 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d688;
3'b001:
ld_val__h30496 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d716;
3'b010:
ld_val__h30496 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1267_0x4_re_ETC__q34;
3'b011:
ld_val__h30496 =
(rg_addr[2:0] == 3'h0) ?
master_xactor_f_rd_data$D_OUT[66:3] :
64'd0;
3'b100:
ld_val__h30496 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d704;
3'b101:
ld_val__h30496 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d724;
3'b110:
ld_val__h30496 =
CASE_rg_addr_BITS_2_TO_0_0x0_result1332_0x4_re_ETC__q35;
3'd7: ld_val__h30496 = 64'd0;
endcase
end
always@(rg_addr or result__h34612 or result__h34640)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843 =
result__h34612;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843 =
result__h34640;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843 =
64'd0;
endcase
end
always@(rg_addr or
result__h34295 or
result__h34323 or result__h34351 or result__h34379)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 =
result__h34295;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 =
result__h34323;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 =
result__h34351;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 =
result__h34379;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 =
64'd0;
endcase
end
always@(rg_addr or
result__h34420 or
result__h34448 or result__h34476 or result__h34504)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 =
result__h34420;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 =
result__h34448;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 =
result__h34476;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 =
result__h34504;
default: IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 =
64'd0;
endcase
end
always@(rg_addr or
result__h34054 or
result__h34082 or
result__h34110 or
result__h34138 or
result__h34166 or
result__h34194 or result__h34222 or result__h34250)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34054;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34082;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34110;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34138;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34166;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34194;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34222;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 =
result__h34250;
endcase
end
always@(rg_addr or
result__h32933 or
result__h33841 or
result__h33869 or
result__h33897 or
result__h33925 or
result__h33953 or result__h33981 or result__h34009)
begin
case (rg_addr[2:0])
3'h0:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h32933;
3'h1:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h33841;
3'h2:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h33869;
3'h3:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h33897;
3'h4:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h33925;
3'h5:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h33953;
3'h6:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h33981;
3'h7:
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 =
result__h34009;
endcase
end
always@(rg_addr or result__h34545 or result__h34573)
begin
case (rg_addr[2:0])
3'h0:
CASE_rg_addr_BITS_2_TO_0_0x0_result4545_0x4_re_ETC__q50 =
result__h34545;
3'h4:
CASE_rg_addr_BITS_2_TO_0_0x0_result4545_0x4_re_ETC__q50 =
result__h34573;
default: CASE_rg_addr_BITS_2_TO_0_0x0_result4545_0x4_re_ETC__q50 =
64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 or
CASE_rg_addr_BITS_2_TO_0_0x0_result4545_0x4_re_ETC__q50 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843)
begin
case (rg_f3)
3'b0:
w1__h32738 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797;
3'b001:
w1__h32738 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825;
3'b010:
w1__h32738 =
CASE_rg_addr_BITS_2_TO_0_0x0_result4545_0x4_re_ETC__q50;
3'b011:
w1__h32738 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844;
3'b100:
w1__h32738 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813;
3'b101:
w1__h32738 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833;
3'b110:
w1__h32738 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843;
3'd7: w1__h32738 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 or
w1___1__h32813 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843)
begin
case (rg_f3)
3'b0:
w1__h32742 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797;
3'b001:
w1__h32742 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825;
3'b010: w1__h32742 = w1___1__h32813;
3'b011:
w1__h32742 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844;
3'b100:
w1__h32742 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813;
3'b101:
w1__h32742 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833;
3'b110:
w1__h32742 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843;
3'd7: w1__h32742 = 64'd0;
endcase
end
always@(rg_f3 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825 or
w12738_BITS_31_TO_0__q51 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833 or
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843)
begin
case (rg_f3)
3'b0:
new_ld_val__h32704 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d797;
3'b001:
new_ld_val__h32704 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_SEX_ETC___d825;
3'b010:
new_ld_val__h32704 =
{ {32{w12738_BITS_31_TO_0__q51[31]}},
w12738_BITS_31_TO_0__q51 };
3'b011:
new_ld_val__h32704 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_IF__ETC___d844;
3'b100:
new_ld_val__h32704 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d813;
3'b101:
new_ld_val__h32704 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d833;
3'b110:
new_ld_val__h32704 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_0_C_ETC___d843;
3'd7: new_ld_val__h32704 = 64'd0;
endcase
end
always@(rg_amo_funct7 or
new_st_val__h34733 or
new_st_val__h32845 or
w2__h32744 or
new_st_val__h34705 or
new_st_val__h34713 or
new_st_val__h34709 or
new_st_val__h34728 or new_st_val__h34717 or new_st_val__h34722)
begin
case (rg_amo_funct7[6:2])
5'b0: _theResult_____2__h32750 = new_st_val__h32845;
5'b00001: _theResult_____2__h32750 = w2__h32744;
5'b00100: _theResult_____2__h32750 = new_st_val__h34705;
5'b01000: _theResult_____2__h32750 = new_st_val__h34713;
5'b01100: _theResult_____2__h32750 = new_st_val__h34709;
5'b10000: _theResult_____2__h32750 = new_st_val__h34728;
5'b11000: _theResult_____2__h32750 = new_st_val__h34717;
5'b11100: _theResult_____2__h32750 = new_st_val__h34722;
default: _theResult_____2__h32750 = new_st_val__h34733;
endcase
end
always@(rg_f3 or IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_1_E_ETC___d351)
begin
case (rg_f3)
3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_27_EQ__ETC__q52 =
IF_rg_addr_7_BITS_2_TO_0_27_EQ_0x0_52_THEN_1_E_ETC___d351;
3'd7: CASE_rg_f3_0b0_IF_rg_addr_7_BITS_2_TO_0_27_EQ__ETC__q52 = 64'd0;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
end
else
begin
if (cfg_verbosity$EN)
cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
if (ctr_wr_rsps_pending_crg$EN)
ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
ctr_wr_rsps_pending_crg$D_IN;
if (rg_cset_in_cache$EN)
rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
if (rg_lower_word32_full$EN)
rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
rg_lower_word32_full$D_IN;
if (rg_lrsc_valid$EN)
rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
end
if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
if (rg_amo_funct7$EN)
rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
if (rg_error_during_refill$EN)
rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
rg_error_during_refill$D_IN;
if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
if (rg_lower_word32$EN)
rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
if (rg_st_amo_val$EN)
rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
if (rg_victim_way$EN)
rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
if (rg_word64_set_in_cache$EN)
rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY
rg_word64_set_in_cache$D_IN;
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
cfg_verbosity = 4'hA;
ctr_wr_rsps_pending_crg = 4'hA;
rg_addr = 64'hAAAAAAAAAAAAAAAA;
rg_amo_funct7 = 7'h2A;
rg_cset_in_cache = 6'h2A;
rg_error_during_refill = 1'h0;
rg_exc_code = 4'hA;
rg_f3 = 3'h2;
rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
rg_lower_word32 = 32'hAAAAAAAA;
rg_lower_word32_full = 1'h0;
rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
rg_lrsc_valid = 1'h0;
rg_op = 2'h2;
rg_pa = 64'hAAAAAAAAAAAAAAAA;
rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
rg_state = 5'h0A;
rg_victim_way = 1'h0;
rg_word64_set_in_cache = 9'h0AA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
ctr_wr_rsps_pending_crg == 4'd15)
begin
v__h3069 = $stime;
#0;
end
v__h3063 = v__h3069 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
ctr_wr_rsps_pending_crg == 4'd15)
$display("%0d: ERROR: CreditCounter: overflow", v__h3063);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
ctr_wr_rsps_pending_crg == 4'd15)
$finish(32'd1);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", f_fabric_write_reqs$D_OUT[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", x__h2641);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", mem_req_wr_data_wdata__h2820);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", mem_req_wr_data_wstrb__h2821);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_fabric_send_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
begin
v__h4085 = $stime;
#0;
end
v__h4079 = v__h4085 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
cfg_verbosity != 4'd0 &&
!f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4079,
"D_MMU_Cache",
$signed(32'd64),
$signed(32'd2));
else
$display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
v__h4079,
"I_MMU_Cache",
$signed(32'd64),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
f_reset_reqs$D_OUT)
begin
v__h4184 = $stime;
#0;
end
v__h4178 = v__h4184 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
f_reset_reqs$D_OUT)
if (dmem_not_imem)
$display("%0d: %s.rl_reset: Flushed", v__h4178, "D_MMU_Cache");
else
$display("%0d: %s.rl_reset: Flushed", v__h4178, "I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h4333 = $stime;
#0;
end
v__h4327 = v__h4333 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4327,
"D_MMU_Cache",
rg_addr);
else
$display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
v__h4327,
"I_MMU_Cache",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" eaddr = {CTag 0x%0h CSet 0x%0h Word64 0x%0h Byte 0x%0h}",
rg_addr[63:12],
rg_addr[11:6],
rg_addr[5:3],
rg_addr[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" CSet 0x%0x: (state, tag):", rg_addr[11:6]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
ram_state_and_ctag_cset$DOB[52])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
!ram_state_and_ctag_cset$DOB[52])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
ram_state_and_ctag_cset$DOB[52])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
!ram_state_and_ctag_cset$DOB[52])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" (");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
ram_state_and_ctag_cset$DOB[105])
$write("CTAG_CLEAN");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
!ram_state_and_ctag_cset$DOB[105])
$write("CTAG_EMPTY");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
ram_state_and_ctag_cset$DOB[105])
$write(", 0x%0x", ram_state_and_ctag_cset$DOB[104:53]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
!ram_state_and_ctag_cset$DOB[105])
$write(", --");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(")");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" 0x%0x", ram_word64_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" 0x%0x", ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" TLB result: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("VM_Xlate_Result { ", "outcome: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("VM_XLATE_OK");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "pa: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "exc_code: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'hA, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp && dmem_not_imem &&
!soc_map$m_is_mem_addr &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" => IO_REQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d158)
$display(" ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
$signed(32'd1),
1'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d357)
begin
v__h19627 = $stime;
#0;
end
v__h19621 = v__h19627 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d357)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19621,
"D_MMU_Cache",
rg_addr,
word64__h5839,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h19621,
"I_MMU_Cache",
rg_addr,
word64__h5839,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d365)
$display(" AMO LR: reserving PA 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d357)
$display(" Read-hit: addr 0x%0h word64 0x%0h",
rg_addr,
word64__h5839);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d368)
$display(" Read Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d374)
$display(" AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
rg_lrsc_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d531)
$display(" ST: cancelling LR/SC reservation for PA", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
rg_lrsc_valid &&
!rg_lrsc_pa_5_EQ_rg_addr_7___d96 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
rg_lrsc_pa,
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op == 2'd2 &&
rg_amo_funct7[6:2] == 5'b00011 &&
!rg_lrsc_valid &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" AMO SC: fail due to invalid LR/SC reservation");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
NOT_dmem_not_imem_53_OR_soc_map_m_is_mem_addr__ETC___d543)
$display(" AMO SC result = %0d", lrsc_result__h20004);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546)
$display(" Write-Cache-Hit: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d444);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d443);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d546)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
(rg_op == 2'd1 ||
rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
NOT_rg_op_1_EQ_2_3_37_OR_NOT_rg_amo_funct7_4_B_ETC___d548)
$display(" Write-Cache-Miss: pa 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d554)
$display(" Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
rg_addr,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d554)
$display(" => rl_write_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_2_3_AND_rg_amo_funct7_4_BITS_6_TO_2_ETC___d558)
begin
v__h23343 = $stime;
#0;
end
v__h23337 = v__h23343 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_2_3_AND_rg_amo_funct7_4_BITS_6_TO_2_ETC___d558)
if (dmem_not_imem)
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23337,
"D_MMU_Cache",
rg_addr,
64'd1,
64'd0);
else
$display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
v__h23337,
"I_MMU_Cache",
rg_addr,
64'd1,
64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op_1_EQ_2_3_AND_rg_amo_funct7_4_BITS_6_TO_2_ETC___d558)
$display(" AMO SC: Fail response for addr 0x%0h", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
NOT_ram_state_and_ctag_cset_b_read__02_BIT_52__ETC___d366)
$display(" AMO Miss: -> CACHE_START_REFILL.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$display(" AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
rg_addr,
rg_amo_funct7,
rg_f3,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$display(" PA 0x%0h ", rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$display(" Cache word64 0x%0h, load-result 0x%0h",
word64__h5839,
word64__h5839);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$display(" 0x%0h op 0x%0h -> 0x%0h",
word64__h5839,
word64__h5839,
new_st_val__h23565);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$write(" New Word64_Set:");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_addr[5:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$write(" 0x%0x",
IF_NOT_ram_state_and_ctag_cset_b_read__02_BIT__ETC___d521);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$write(" 0x%0x",
IF_ram_state_and_ctag_cset_b_read__02_BIT_105__ETC___d520);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
NOT_rg_op_1_EQ_0_2_36_AND_NOT_rg_op_1_EQ_2_3_3_ETC___d566)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
(!dmem_not_imem || soc_map$m_is_mem_addr) &&
rg_op != 2'd0 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
rg_op != 2'd1 &&
(rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
ram_state_and_ctag_cset_b_read__02_BIT_52_03_A_ETC___d568)
$display(" AMO_op: cancelling LR/SC reservation for PA",
rg_addr);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h26661 = $stime;
#0;
end
v__h26655 = v__h26661 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_start_cache_refill: ",
v__h26655,
"D_MMU_Cache");
else
$display("%0d: %s.rl_start_cache_refill: ",
v__h26655,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", cline_fabric_addr__h26714);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 8'd7);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 3'b011);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_cache_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" Victim way %0d; => CACHE_REFILL", tmp__h26877[0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
begin
v__h27400 = $stime;
#0;
end
v__h27394 = v__h27400 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27394,
"D_MMU_Cache");
else
$display("%0d: %s.rl_cache_refill_rsps_loop:",
v__h27394,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h27641 = $stime;
#0;
end
v__h27635 = v__h27641 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27635,
"D_MMU_Cache",
access_exc_code__h2376);
else
$display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
v__h27635,
"I_MMU_Cache",
access_exc_code__h2376);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 &&
(master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
rg_error_during_refill) &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" => MODULE_EXCEPTION_RSP");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
rg_word64_set_in_cache[2:0] == 3'd7 &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
!rg_error_during_refill &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" => CACHE_REREQ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$display(" Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new",
rg_word64_set_in_cache,
rg_word64_set_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_word64_set_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" 0x%0x", ram_word64_set$DOB[63:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" 0x%0x", ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" CSet 0x%0x, Word64 0x%0x: ",
rg_addr[11:6],
rg_word64_set_in_cache[2:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" 0x%0x",
rg_victim_way ?
ram_word64_set$DOB[63:0] :
master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write(" 0x%0x",
rg_victim_way ?
master_xactor_f_rd_data$D_OUT[66:3] :
ram_word64_set$DOB[127:64]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
NOT_cfg_verbosity_read__9_ULE_2_94___d595)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_rereq && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
rg_addr[11:6],
rg_addr[11:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h30037 = $stime;
#0;
end
v__h30031 = v__h30037 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30031,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h paddr %0h",
v__h30031,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", value__h32290);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h30387 = $stime;
#0;
end
v__h30381 = v__h30387 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30381,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h30381,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h31489 = $stime;
#0;
end
v__h31483 = v__h31489 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31483,
"D_MMU_Cache",
rg_addr,
ld_val__h30496);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31483,
"I_MMU_Cache",
rg_addr,
ld_val__h30496);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h31596 = $stime;
#0;
end
v__h31590 = v__h31596 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31590,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
v__h31590,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h31701 = $stime;
#0;
end
v__h31695 = v__h31701 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31695,
"D_MMU_Cache",
rg_addr,
rg_ld_val);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h31695,
"I_MMU_Cache",
rg_addr,
rg_ld_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h31781 = $stime;
#0;
end
v__h31775 = v__h31781 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31775,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_write_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31775,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_write_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h31991 = $stime;
#0;
end
v__h31985 = v__h31991 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31985,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h31985,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" FAIL due to I/O address.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_SC_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h32109 = $stime;
#0;
end
v__h32103 = v__h32109 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32103,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h paddr %0h",
v__h32103,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" To fabric: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 8'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", value__h32290);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 2'b01);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'b0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 3'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 4'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'h0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_op_req &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h32403 = $stime;
#0;
end
v__h32397 = v__h32403 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32397,
"D_MMU_Cache",
rg_addr,
rg_pa);
else
$display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h paddr 0x%0h",
v__h32397,
"I_MMU_Cache",
rg_addr,
rg_pa);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
master_xactor_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
!master_xactor_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h32578 = $stime;
#0;
end
v__h32572 = v__h32578 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32572,
"D_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
else
$display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h vaddr %0h paddr %0h word64 0x%0h",
v__h32572,
"I_MMU_Cache",
rg_f3,
rg_addr,
rg_pa,
rg_st_amo_val);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h34837 = $stime;
#0;
end
v__h34831 = v__h34837 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h34831,
"D_MMU_Cache",
rg_addr,
new_ld_val__h32704);
else
$display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
v__h34831,
"I_MMU_Cache",
rg_addr,
new_ld_val__h32704);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" => rl_ST_AMO_response");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h32674 = $stime;
#0;
end
v__h32668 = v__h32674 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32668,
"D_MMU_Cache");
else
$display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
v__h32668,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h35444 = $stime;
#0;
end
v__h35438 = v__h35444 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
if (dmem_not_imem)
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35438,
"D_MMU_Cache",
$unsigned(b__h26615));
else
$write("%0d: %s.rl_discard_write_rsp: pending %0d ",
v__h35438,
"I_MMU_Cache",
$unsigned(b__h26615));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
begin
v__h35405 = $stime;
#0;
end
v__h35399 = v__h35405 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
if (dmem_not_imem)
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35399,
"D_MMU_Cache");
else
$display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
v__h35399,
"I_MMU_Cache");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_discard_write_rsp &&
master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
begin
v__h3617 = $stime;
#0;
end
v__h3611 = v__h3617 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_start_reset)
if (dmem_not_imem)
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3611,
"D_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd64),
$signed(32'd8));
else
$display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
v__h3611,
"I_MMU_Cache",
$signed(32'd8),
$signed(32'd2),
$signed(32'd64),
$signed(32'd8));
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
begin
v__h35793 = $stime;
#0;
end
v__h35787 = v__h35793 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write("%0d: %m.req: op:", v__h35787);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 && req_op == 2'd0)
$write("CACHE_LD");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 && req_op == 2'd1)
$write("CACHE_ST");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
req_op != 2'd0 &&
req_op != 2'd1)
$write("CACHE_AMO");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" f3:%0d addr:0x%0h st_value:0x%0h",
req_f3,
req_addr,
req_st_value,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" priv:");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
req_priv == 2'b0)
$write("U");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
req_priv == 2'b01)
$write("S");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
req_priv == 2'b11)
$write("M");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41 &&
req_priv != 2'b0 &&
req_priv != 2'b01 &&
req_priv != 2'b11)
$write("RESERVED");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
req_sstatus_SUM,
req_mstatus_MXR,
req_satp,
"\n");
if (RST_N != `BSV_RESET_VALUE)
if (EN_req && NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" amo_funct7 = 0x%0h", req_amo_funct7);
if (RST_N != `BSV_RESET_VALUE)
if (EN_req &&
req_f3_BITS_1_TO_0_29_EQ_0b0_30_OR_req_f3_BITS_ETC___d959 &&
NOT_cfg_verbosity_read__9_ULE_1_0___d41)
$display(" fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
req_addr[11:6],
req_addr[11:3]);
end
// synopsys translate_on
endmodule // mkMMU_Cache
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR2_TB_V
`define SKY130_FD_SC_LP__NOR2_TB_V
/**
* nor2: 2-input NOR.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__nor2.v"
module top();
// Inputs are registered
reg A;
reg B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A = 1'bX;
B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A = 1'b0;
#40 B = 1'b0;
#60 VGND = 1'b0;
#80 VNB = 1'b0;
#100 VPB = 1'b0;
#120 VPWR = 1'b0;
#140 A = 1'b1;
#160 B = 1'b1;
#180 VGND = 1'b1;
#200 VNB = 1'b1;
#220 VPB = 1'b1;
#240 VPWR = 1'b1;
#260 A = 1'b0;
#280 B = 1'b0;
#300 VGND = 1'b0;
#320 VNB = 1'b0;
#340 VPB = 1'b0;
#360 VPWR = 1'b0;
#380 VPWR = 1'b1;
#400 VPB = 1'b1;
#420 VNB = 1'b1;
#440 VGND = 1'b1;
#460 B = 1'b1;
#480 A = 1'b1;
#500 VPWR = 1'bx;
#520 VPB = 1'bx;
#540 VNB = 1'bx;
#560 VGND = 1'bx;
#580 B = 1'bx;
#600 A = 1'bx;
end
sky130_fd_sc_lp__nor2 dut (.A(A), .B(B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR2_TB_V
|
/*
* Copyright (c) 2013, Quan Nguyen
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
module translater (
input clk,
input reset,
input vm_enable,
input launch_translation,
output reg [31:0] physical_address,
input [31:0] virtual_address,
output translation_complete,
input [31:0] ptbr,
input flush_tlb,
/* memory interface */
output reg [31:0] translate_addr,
output translate_mem_enable,
input [31:0] request_data,
input translate_data_valid
);
wire [31:0] tlb_output_address;
wire tlb_hit;
wire translation_required;
localparam S_IDLE = 2'd0;
localparam S_TLB = 2'd1;
localparam S_TRAN_PPN1 = 2'd2;
localparam S_TRAN_PPN0 = 2'd3;
reg [31:0] address;
reg [1:0] state;
reg [1:0] next_state;
always @ (posedge clk) begin
if (reset)
state <= S_IDLE;
else
state <= next_state;
end
always @ (posedge clk) begin
if (reset)
address <= 0;
else if (state == S_IDLE && launch_translation)
address <= virtual_address;
end
always @ (*) begin
case (state)
S_IDLE:
next_state = launch_translation ? S_TLB : S_IDLE;
S_TLB:
if (tlb_hit)
next_state = S_IDLE;
else if (translation_required)
next_state = S_TRAN_PPN1;
else
next_state = S_TLB;
S_TRAN_PPN1:
next_state = translate_data_valid ? S_TRAN_PPN0 : S_TRAN_PPN1;
S_TRAN_PPN0:
next_state = translate_data_valid ? S_IDLE : S_TRAN_PPN0;
default:
next_state = S_IDLE;
endcase
end
reg [31:0] ppn1_data;
reg ppn1_valid;
reg [31:0] ppn0_data;
reg ppn0_valid;
always @ (posedge clk) begin
if (reset) begin
ppn1_valid <= 0;
ppn1_data <= 0;
ppn0_valid <= 0;
ppn0_data <= 0;
end else begin
if (state == S_IDLE && launch_translation) begin
ppn1_valid <= 0;
ppn1_data <= 0;
ppn0_valid <= 0;
ppn0_data <= 0;
end else if (state == S_TRAN_PPN1 && translate_data_valid) begin
ppn1_data <= request_data;
ppn1_valid <= 1;
end else if (state == S_TRAN_PPN0 && translate_data_valid) begin
ppn0_data <= request_data;
ppn0_valid <= 1;
end
end
end
always @ (*) begin
case (state)
S_TRAN_PPN1:
translate_addr = {ptbr[31:12], address[31:22], 2'b0};
S_TRAN_PPN0:
translate_addr = {ppn1_data[31:12], address[21:12], 2'b0};
default:
translate_addr = 32'b0;
endcase
end
assign translate_mem_enable = (state == S_TRAN_PPN1) || (state == S_TRAN_PPN0);
assign translation_complete = (state == S_IDLE);
/* Latch inferred. */
always @ (*) begin
if (translation_complete)
if (tlb_hit)
physical_address = {tlb_output_address[31:12], address[11:0]};
else
physical_address = {ppn0_data[31:12], address[11:0]};
end
/* TLB */
wire tlb_enable = (state == S_TLB);
tlb tlb(.clk(clk), .reset(reset), .flush(flush_tlb),
.vm_enable(vm_enable), .enable(tlb_enable),
.virtual_address(virtual_address), .physical_address(tlb_output_address),
.tlb_hit(tlb_hit), .translation_required(translation_required),
.translated_address(physical_address), .translation_complete(translation_complete));
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SDFXTP_FUNCTIONAL_V
`define SKY130_FD_SC_LP__SDFXTP_FUNCTIONAL_V
/**
* sdfxtp: Scan delay flop, non-inverted clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_dff_p/sky130_fd_sc_lp__udp_dff_p.v"
`celldefine
module sky130_fd_sc_lp__sdfxtp (
Q ,
CLK,
D ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input SCD;
input SCE;
// Local signals
wire buf_Q ;
wire mux_out;
// Delay Name Output Other arguments
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out, D, SCD, SCE );
sky130_fd_sc_lp__udp_dff$P `UNIT_DELAY dff0 (buf_Q , mux_out, CLK );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SDFXTP_FUNCTIONAL_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Matt Myers.
`define checkd(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got=%0d exp=%0d\n", `__FILE__,`__LINE__, (gotv), (expv)); $stop; end while(0);
package config_pkg;
typedef struct packed {
int UPPER0;
struct packed {
int USE_QUAD0;
int USE_QUAD1;
int USE_QUAD2;
} mac;
int UPPER2;
} config_struct;
function automatic config_struct static_config(int selector);
config_struct return_config;
return_config = '0;
return_config.UPPER0 = 10;
return_config.UPPER2 = 20;
return_config.mac.USE_QUAD0 = 4;
return_config.mac.USE_QUAD2 = 6;
case (selector)
1: return_config.mac.USE_QUAD1 = 5;
endcase
return return_config;
endfunction
endpackage : config_pkg
module t;
import config_pkg::*;
localparam config_struct MY_CONFIG = static_config(1);
struct_submodule #(.MY_CONFIG(MY_CONFIG)) a_submodule_I ();
endmodule : t
module struct_submodule
import config_pkg::*;
#(parameter config_struct MY_CONFIG = '0);
initial begin
`checkd(MY_CONFIG.UPPER0, 10);
`checkd(MY_CONFIG.mac.USE_QUAD0, 4);
`checkd(MY_CONFIG.mac.USE_QUAD1, 5);
`checkd(MY_CONFIG.mac.USE_QUAD2, 6);
`checkd(MY_CONFIG.UPPER2, 20);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule : struct_submodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NAND3B_SYMBOL_V
`define SKY130_FD_SC_LS__NAND3B_SYMBOL_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ls__nand3b (
//# {{data|Data Signals}}
input A_N,
input B ,
input C ,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__NAND3B_SYMBOL_V
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter UNCHANGE_START = 1'b0;
parameter UNCHANGE_CHECK = 1'b1;
reg [width-1:0] r_test_expr;
reg r_state;
integer i;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=UNCHANGE_START;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
UNCHANGE_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_state <= UNCHANGE_CHECK;
r_test_expr <= test_expr;
i <= num_cks;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
UNCHANGE_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START && i > 0)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
`endif // OVL_ASSERT_ON
end
end
else if (i > 0) begin
i <= i-1;
end
// go to start state on last check
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_state <= UNCHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
end
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_test_expr != test_expr) &&
!(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression changed value within num_cks from the start event asserted");
end
`endif // OVL_ASSERT_ON
r_test_expr <= test_expr;
end
endcase
end
else begin
r_state<=UNCHANGE_START;
i <= 0;
`ifdef OVL_INIT_REG
r_test_expr <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_SHARED_CODE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O31A_TB_V
`define SKY130_FD_SC_HD__O31A_TB_V
/**
* o31a: 3-input OR into 2-input AND.
*
* X = ((A1 | A2 | A3) & B1)
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__o31a.v"
module top();
// Inputs are registered
reg A1;
reg A2;
reg A3;
reg B1;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1 = 1'bX;
A2 = 1'bX;
A3 = 1'bX;
B1 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1 = 1'b0;
#40 A2 = 1'b0;
#60 A3 = 1'b0;
#80 B1 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1 = 1'b1;
#200 A2 = 1'b1;
#220 A3 = 1'b1;
#240 B1 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1 = 1'b0;
#360 A2 = 1'b0;
#380 A3 = 1'b0;
#400 B1 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B1 = 1'b1;
#600 A3 = 1'b1;
#620 A2 = 1'b1;
#640 A1 = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B1 = 1'bx;
#760 A3 = 1'bx;
#780 A2 = 1'bx;
#800 A1 = 1'bx;
end
sky130_fd_sc_hd__o31a dut (.A1(A1), .A2(A2), .A3(A3), .B1(B1), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O31A_TB_V
|
(** * Hoare2: Hoare Logic, Part II *)
Require Export Hoare.
(* ####################################################### *)
(** * Decorated Programs *)
(** The beauty of Hoare Logic is that it is _compositional_ --
the structure of proofs exactly follows the structure of programs.
This suggests that we can record the essential ideas of a proof
informally (leaving out some low-level calculational details) by
decorating programs with appropriate assertions around each
statement. Such a _decorated program_ carries with it
an (informal) proof of its own correctness. *)
(** For example, here is a complete decorated program: *)
(**
{{ True }} ->>
{{ m = m }}
X ::= m;
{{ X = m }} ->>
{{ X = m /\ p = p }}
Z ::= p;
{{ X = m /\ Z = p }} ->>
{{ Z - X = p - m }}
WHILE X <> 0 DO
{{ Z - X = p - m /\ X <> 0 }} ->>
{{ (Z - 1) - (X - 1) = p - m }}
Z ::= Z - 1;
{{ Z - (X - 1) = p - m }}
X ::= X - 1
{{ Z - X = p - m }}
END;
{{ Z - X = p - m /\ ~ (X <> 0) }} ->>
{{ Z = p - m }} ->>
*)
(** Concretely, a decorated program consists of the program text
interleaved with assertions. To check that a decorated program
represents a valid proof, we check that each individual command is
_locally consistent_ with its accompanying assertions in the
following sense: *)
(**
- [SKIP] is locally consistent if its precondition and
postcondition are the same:
{{ P }}
SKIP
{{ P }}
- The sequential composition of [c1] and [c2] is locally
consistent (with respect to assertions [P] and [R]) if [c1] is
locally consistent (with respect to [P] and [Q]) and [c2] is
locally consistent (with respect to [Q] and [R]):
{{ P }}
c1;
{{ Q }}
c2
{{ R }}
- An assignment is locally consistent if its precondition is
the appropriate substitution of its postcondition:
{{ P [X |-> a] }}
X ::= a
{{ P }}
- A conditional is locally consistent (with respect to assertions
[P] and [Q]) if the assertions at the top of its "then" and
"else" branches are exactly [P /\ b] and [P /\ ~b] and if its "then"
branch is locally consistent (with respect to [P /\ b] and [Q])
and its "else" branch is locally consistent (with respect to
[P /\ ~b] and [Q]):
{{ P }}
IFB b THEN
{{ P /\ b }}
c1
{{ Q }}
ELSE
{{ P /\ ~b }}
c2
{{ Q }}
FI
{{ Q }}
- A while loop with precondition [P] is locally consistent if its
postcondition is [P /\ ~b] and if the pre- and postconditions of
its body are exactly [P /\ b] and [P]:
{{ P }}
WHILE b DO
{{ P /\ b }}
c1
{{ P }}
END
{{ P /\ ~b }}
- A pair of assertions separated by [->>] is locally consistent if
the first implies the second (in all states):
{{ P }} ->>
{{ P' }}
This corresponds to the application of [hoare_consequence] and
is the only place in a decorated program where checking if
decorations are correct is not fully mechanical and syntactic,
but involves logical and/or arithmetic reasoning.
*)
(** We have seen above how _verifying_ the correctness of a
given proof involves checking that every single command is locally
consistent with the accompanying assertions. If we are instead
interested in _finding_ a proof for a given specification we need
to discover the right assertions. This can be done in an almost
automatic way, with the exception of finding loop invariants,
which is the subject of in the next section. In the reminder of
this section we explain in detail how to construct decorations for
several simple programs that don't involve non-trivial loop
invariants. *)
(* ####################################################### *)
(** ** Example: Swapping Using Addition and Subtraction *)
(** Here is a program that swaps the values of two variables using
addition and subtraction (instead of by assigning to a temporary
variable).
X ::= X + Y;
Y ::= X - Y;
X ::= X - Y
We can prove using decorations that this program is correct --
i.e., it always swaps the values of variables [X] and [Y]. *)
(**
(1) {{ X = m /\ Y = n }} ->>
(2) {{ (X + Y) - ((X + Y) - Y) = n /\ (X + Y) - Y = m }}
X ::= X + Y;
(3) {{ X - (X - Y) = n /\ X - Y = m }}
Y ::= X - Y;
(4) {{ X - Y = n /\ Y = m }}
X ::= X - Y
(5) {{ X = n /\ Y = m }}
The decorations were constructed as follows:
- We begin with the undecorated program (the unnumbered lines).
- We then add the specification -- i.e., the outer
precondition (1) and postcondition (5). In the precondition we
use auxiliary variables (parameters) [m] and [n] to remember
the initial values of variables [X] and respectively [Y], so
that we can refer to them in the postcondition (5).
- We work backwards mechanically starting from (5) all the way
to (2). At each step, we obtain the precondition of the
assignment from its postcondition by substituting the assigned
variable with the right-hand-side of the assignment. For
instance, we obtain (4) by substituting [X] with [X - Y]
in (5), and (3) by substituting [Y] with [X - Y] in (4).
- Finally, we verify that (1) logically implies (2) -- i.e.,
that the step from (1) to (2) is a valid use of the law of
consequence. For this we substitute [X] by [m] and [Y] by [n]
and calculate as follows:
(m + n) - ((m + n) - n) = n /\ (m + n) - n = m
(m + n) - m = n /\ m = m
n = n /\ m = m
(Note that, since we are working with natural numbers, not
fixed-size machine integers, we don't need to worry about the
possibility of arithmetic overflow anywhere in this argument.)
*)
(* ####################################################### *)
(** ** Example: Simple Conditionals *)
(** Here is a simple decorated program using conditionals:
(1) {{True}}
IFB X <= Y THEN
(2) {{True /\ X <= Y}} ->>
(3) {{(Y - X) + X = Y \/ (Y - X) + Y = X}}
Z ::= Y - X
(4) {{Z + X = Y \/ Z + Y = X}}
ELSE
(5) {{True /\ ~(X <= Y) }} ->>
(6) {{(X - Y) + X = Y \/ (X - Y) + Y = X}}
Z ::= X - Y
(7) {{Z + X = Y \/ Z + Y = X}}
FI
(8) {{Z + X = Y \/ Z + Y = X}}
These decorations were constructed as follows:
- We start with the outer precondition (1) and postcondition (8).
- We follow the format dictated by the [hoare_if] rule and copy the
postcondition (8) to (4) and (7). We conjoin the precondition (1)
with the guard of the conditional to obtain (2). We conjoin (1)
with the negated guard of the conditional to obtain (5).
- In order to use the assignment rule and obtain (3), we substitute
[Z] by [Y - X] in (4). To obtain (6) we substitute [Z] by [X - Y]
in (7).
- Finally, we verify that (2) implies (3) and (5) implies (6). Both
of these implications crucially depend on the ordering of [X] and
[Y] obtained from the guard. For instance, knowing that [X <= Y]
ensures that subtracting [X] from [Y] and then adding back [X]
produces [Y], as required by the first disjunct of (3). Similarly,
knowing that [~(X <= Y)] ensures that subtracting [Y] from [X] and
then adding back [Y] produces [X], as needed by the second
disjunct of (6). Note that [n - m + m = n] does _not_ hold for
arbitrary natural numbers [n] and [m] (for example, [3 - 5 + 5 =
5]). *)
(** **** Exercise: 2 stars (if_minus_plus_reloaded) *)
(** Fill in valid decorations for the following program:
{{ True }}
IFB X <= Y THEN
{{ X <= Y }} ->>
{{ Y = X + (Y - X) }}
Z ::= Y - X
{{ Y = X + Z }}
ELSE
{{ ~(X <= Y) }} ->>
{{ X + Z = X + Z }}
Y ::= X + Z
{{ Y = X + Z }}
FI
{{ Y = X + Z }}
*)
(* ####################################################### *)
(** ** Example: Reduce to Zero (Trivial Loop) *)
(** Here is a [WHILE] loop that is so simple it needs no
invariant (i.e., the invariant [True] will do the job).
(1) {{ True }}
WHILE X <> 0 DO
(2) {{ True /\ X <> 0 }} ->>
(3) {{ True }}
X ::= X - 1
(4) {{ True }}
END
(5) {{ True /\ X = 0 }} ->>
(6) {{ X = 0 }}
The decorations can be constructed as follows:
- Start with the outer precondition (1) and postcondition (6).
- Following the format dictated by the [hoare_while] rule, we copy
(1) to (4). We conjoin (1) with the guard to obtain (2) and with
the negation of the guard to obtain (5). Note that, because the
outer postcondition (6) does not syntactically match (5), we need a
trivial use of the consequence rule from (5) to (6).
- Assertion (3) is the same as (4), because [X] does not appear in
[4], so the substitution in the assignment rule is trivial.
- Finally, the implication between (2) and (3) is also trivial.
*)
(** From this informal proof, it is easy to read off a formal proof
using the Coq versions of the Hoare rules. Note that we do _not_
unfold the definition of [hoare_triple] anywhere in this proof --
the idea is to use the Hoare rules as a "self-contained" logic for
reasoning about programs. *)
Definition reduce_to_zero' : com :=
WHILE BNot (BEq (AId X) (ANum 0)) DO
X ::= AMinus (AId X) (ANum 1)
END.
Theorem reduce_to_zero_correct' :
{{fun st => True}}
reduce_to_zero'
{{fun st => st X = 0}}.
Proof.
unfold reduce_to_zero'.
(* First we need to transform the postcondition so
that hoare_while will apply. *)
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
(* Need to massage precondition before [hoare_asgn] applies *)
eapply hoare_consequence_pre. apply hoare_asgn.
(* Proving trivial implication (2) ->> (3) *)
intros st [HT Hbp]. unfold assn_sub. apply I.
Case "Invariant and negated guard imply postcondition".
intros st [Inv GuardFalse].
unfold bassn in GuardFalse. simpl in GuardFalse.
(* SearchAbout helps to find the right lemmas *)
SearchAbout [not true].
rewrite not_true_iff_false in GuardFalse.
SearchAbout [negb false].
rewrite negb_false_iff in GuardFalse.
SearchAbout [beq_nat true].
apply beq_nat_true in GuardFalse.
apply GuardFalse. Qed.
(* ####################################################### *)
(** ** Example: Division *)
(** The following Imp program calculates the integer division and
remainder of two numbers [m] and [n] that are arbitrary constants
in the program.
X ::= m;
Y ::= 0;
WHILE n <= X DO
X ::= X - n;
Y ::= Y + 1
END;
In other words, if we replace [m] and [n] by concrete numbers and
execute the program, it will terminate with the variable [X] set
to the remainder when [m] is divided by [n] and [Y] set to the
quotient. *)
(** In order to give a specification to this program we need to
remember that dividing [m] by [n] produces a reminder [X] and a
quotient [Y] so that [n * Y + X = m /\ X < n].
It turns out that we get lucky with this program and don't have to
think very hard about the loop invariant: the invariant is the
just first conjunct [n * Y + X = m], so we use that to decorate
the program.
(1) {{ True }} ->>
(2) {{ n * 0 + m = m }}
X ::= m;
(3) {{ n * 0 + X = m }}
Y ::= 0;
(4) {{ n * Y + X = m }}
WHILE n <= X DO
(5) {{ n * Y + X = m /\ n <= X }} ->>
(6) {{ n * (Y + 1) + (X - n) = m }}
X ::= X - n;
(7) {{ n * (Y + 1) + X = m }}
Y ::= Y + 1
(8) {{ n * Y + X = m }}
END
(9) {{ n * Y + X = m /\ X < n }}
Assertions (4), (5), (8), and (9) are derived mechanically from
the invariant and the loop's guard. Assertions (8), (7), and (6)
are derived using the assignment rule going backwards from (8) to
(6). Assertions (4), (3), and (2) are again backwards applications
of the assignment rule.
Now that we've decorated the program it only remains to check that
the two uses of the consequence rule are correct -- i.e., that (1)
implies (2) and that (5) implies (6). This is indeed the case, so
we have a valid decorated program.
*)
(* ####################################################### *)
(** * Finding Loop Invariants *)
(** Once the outermost precondition and postcondition are chosen, the
only creative part in verifying programs with Hoare Logic is
finding the right loop invariants. The reason this is difficult
is the same as the reason that doing inductive mathematical proofs
requires creativity: strengthening the loop invariant (or the
induction hypothesis) means that you have a stronger assumption to
work with when trying to establish the postcondition of the loop
body (complete the induction step of the proof), but it also means
that the loop body postcondition itself is harder to prove!
This section is dedicated to teaching you how to approach the
challenge of finding loop invariants using a series of examples
and exercises. *)
(** ** Example: Slow Subtraction *)
(** The following program subtracts the value of [X] from the value of
[Y] by repeatedly decrementing both [X] and [Y]. We want to verify its
correctness with respect to the following specification:
{{ X = m /\ Y = n }}
WHILE X <> 0 DO
Y ::= Y - 1;
X ::= X - 1
END
{{ Y = n - m }}
To verify this program we need to find an invariant [I] for the
loop. As a first step we can leave [I] as an unknown and build a
_skeleton_ for the proof by applying backward the rules for local
consistency. This process leads to the following skeleton:
(1) {{ X = m /\ Y = n }} ->> (a)
(2) {{ I }}
WHILE X <> 0 DO
(3) {{ I /\ X <> 0 }} ->> (c)
(4) {{ I[X |-> X-1][Y |-> Y-1] }}
Y ::= Y - 1;
(5) {{ I[X |-> X-1] }}
X ::= X - 1
(6) {{ I }}
END
(7) {{ I /\ ~(X <> 0) }} ->> (b)
(8) {{ Y = n - m }}
By examining this skeleton, we can see that any valid [I] will
have to respect three conditions:
- (a) it must be weak enough to be implied by the loop's
precondition, i.e. (1) must imply (2);
- (b) it must be strong enough to imply the loop's postcondition,
i.e. (7) must imply (8);
- (c) it must be preserved by one iteration of the loop, i.e. (3)
must imply (4). *)
(** These conditions are actually independent of the particular
program and specification we are considering. Indeed, every loop
invariant has to satisfy them. One way to find an invariant that
simultaneously satisfies these three conditions is by using an
iterative process: start with a "candidate" invariant (e.g. a
guess or a heuristic choice) and check the three conditions above;
if any of the checks fails, try to use the information that we get
from the failure to produce another (hopefully better) candidate
invariant, and repeat the process.
For instance, in the reduce-to-zero example above, we saw that,
for a very simple loop, choosing [True] as an invariant did the
job. So let's try it again here! I.e., let's instantiate [I] with
[True] in the skeleton above see what we get...
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ True }}
WHILE X <> 0 DO
(3) {{ True /\ X <> 0 }} ->> (c - OK)
(4) {{ True }}
Y ::= Y - 1;
(5) {{ True }}
X ::= X - 1
(6) {{ True }}
END
(7) {{ True /\ X = 0 }} ->> (b - WRONG!)
(8) {{ Y = n - m }}
While conditions (a) and (c) are trivially satisfied,
condition (b) is wrong, i.e. it is not the case that (7) [True /\
X = 0] implies (8) [Y = n - m]. In fact, the two assertions are
completely unrelated and it is easy to find a counterexample (say,
[Y = X = m = 0] and [n = 1]).
If we want (b) to hold, we need to strengthen the invariant so
that it implies the postcondition (8). One very simple way to do
this is to let the invariant _be_ the postcondition. So let's
return to our skeleton, instantiate [I] with [Y = n - m], and
check conditions (a) to (c) again.
(1) {{ X = m /\ Y = n }} ->> (a - WRONG!)
(2) {{ Y = n - m }}
WHILE X <> 0 DO
(3) {{ Y = n - m /\ X <> 0 }} ->> (c - WRONG!)
(4) {{ Y - 1 = n - m }}
Y ::= Y - 1;
(5) {{ Y = n - m }}
X ::= X - 1
(6) {{ Y = n - m }}
END
(7) {{ Y = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
This time, condition (b) holds trivially, but (a) and (c) are
broken. Condition (a) requires that (1) [X = m /\ Y = n]
implies (2) [Y = n - m]. If we substitute [X] by [m] we have to
show that [m = n - m] for arbitrary [m] and [n], which does not
hold (for instance, when [m = n = 1]). Condition (c) requires that
[n - m - 1 = n - m], which fails, for instance, for [n = 1] and [m =
0]. So, although [Y = n - m] holds at the end of the loop, it does
not hold from the start, and it doesn't hold on each iteration;
it is not a correct invariant.
This failure is not very surprising: the variable [Y] changes
during the loop, while [m] and [n] are constant, so the assertion
we chose didn't have much chance of being an invariant!
To do better, we need to generalize (8) to some statement that is
equivalent to (8) when [X] is [0], since this will be the case
when the loop terminates, and that "fills the gap" in some
appropriate way when [X] is nonzero. Looking at how the loop
works, we can observe that [X] and [Y] are decremented together
until [X] reaches [0]. So, if [X = 2] and [Y = 5] initially,
after one iteration of the loop we obtain [X = 1] and [Y = 4];
after two iterations [X = 0] and [Y = 3]; and then the loop stops.
Notice that the difference between [Y] and [X] stays constant
between iterations; initially, [Y = n] and [X = m], so this
difference is always [n - m]. So let's try instantiating [I] in
the skeleton above with [Y - X = n - m].
(1) {{ X = m /\ Y = n }} ->> (a - OK)
(2) {{ Y - X = n - m }}
WHILE X <> 0 DO
(3) {{ Y - X = n - m /\ X <> 0 }} ->> (c - OK)
(4) {{ (Y - 1) - (X - 1) = n - m }}
Y ::= Y - 1;
(5) {{ Y - (X - 1) = n - m }}
X ::= X - 1
(6) {{ Y - X = n - m }}
END
(7) {{ Y - X = n - m /\ X = 0 }} ->> (b - OK)
(8) {{ Y = n - m }}
Success! Conditions (a), (b) and (c) all hold now. (To
verify (c), we need to check that, under the assumption that [X <>
0], we have [Y - X = (Y - 1) - (X - 1)]; this holds for all
natural numbers [X] and [Y].) *)
(* ####################################################### *)
(** ** Exercise: Slow Assignment *)
(** **** Exercise: 2 stars (slow_assignment) *)
(** A roundabout way of assigning a number currently stored in [X] to
the variable [Y] is to start [Y] at [0], then decrement [X] until
it hits [0], incrementing [Y] at each step. Here is a program that
implements this idea:
{{ X = m }}
Y ::= 0;
WHILE X <> 0 DO
X ::= X - 1;
Y ::= Y + 1;
END
{{ Y = m }}
Write an informal decorated program showing that this is correct. *)
(* FILL IN HERE
{{ X = m }} ->>
{{ X = m /\ Y = Y }}
Y ::= 0;
{{ X = m /\ Y = 0 }} ->>
{{ X + Y = m }}
WHILE X <> 0 DO
{{ X + Y = m /\ X <> 0 }} ->>
{{ (X-1) + (Y+1) = m }}
X ::= X - 1;
{{ X + (Y+1) = m }}
Y ::= Y + 1;
{{ X + Y = m }}
END
{{ I /\ ~(X <> 0) }} ->>
{{ Y = m }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Slow Addition *)
(** **** Exercise: 3 stars, optional (add_slowly_decoration) *)
(** The following program adds the variable X into the variable Z
by repeatedly decrementing X and incrementing Z.
WHILE X <> 0 DO
Z ::= Z + 1;
X ::= X - 1
END
Following the pattern of the [subtract_slowly] example above, pick
a precondition and postcondition that give an appropriate
specification of [add_slowly]; then (informally) decorate the
program accordingly. *)
(*
{{ Z = n /\ X = m }} ->>
{{ Z + X = n + m }}
WHILE X <> 0 DO
{{ Z + X = n + m /\ X <> 0 }} ->>
{{ (Z+1) + (X-1) = n + m }}
Z ::= Z + 1;
{{ Z + (X-1) = n + m }}
X ::= X - 1
{{ Z + X = n + m }}
END
{{ Z + X = n + m /\ ~(X <> 0) }} ->>
{{ Z = n + m }}
*)
(** [] *)
(* ####################################################### *)
(** ** Example: Parity *)
(** Here is a cute little program for computing the parity of the
value initially stored in [X] (due to Daniel Cristofani).
{{ X = m }}
WHILE 2 <= X DO
X ::= X - 2
END
{{ X = parity m }}
The mathematical [parity] function used in the specification is
defined in Coq as follows: *)
Fixpoint parity x :=
match x with
| 0 => 0
| 1 => 1
| S (S x') => parity x'
end.
(** The postcondition does not hold at the beginning of the loop,
since [m = parity m] does not hold for an arbitrary [m], so we
cannot use that as an invariant. To find an invariant that works,
let's think a bit about what this loop does. On each iteration it
decrements [X] by [2], which preserves the parity of [X]. So the
parity of [X] does not change, i.e. it is invariant. The initial
value of [X] is [m], so the parity of [X] is always equal to the
parity of [m]. Using [parity X = parity m] as an invariant we
obtain the following decorated program:
{{ X = m }} ->> (a - OK)
{{ parity X = parity m }}
WHILE 2 <= X DO
{{ parity X = parity m /\ 2 <= X }} ->> (c - OK)
{{ parity (X-2) = parity m }}
X ::= X - 2
{{ parity X = parity m }}
END
{{ parity X = parity m /\ X < 2 }} ->> (b - OK)
{{ X = parity m }}
With this invariant, conditions (a), (b), and (c) are all
satisfied. For verifying (b), we observe that, when [X < 2], we
have [parity X = X] (we can easily see this in the definition of
[parity]). For verifying (c), we observe that, when [2 <= X], we
have [parity X = parity (X-2)]. *)
(** **** Exercise: 3 stars, optional (parity_formal) *)
(** Translate this proof to Coq. Refer to the reduce-to-zero example
for ideas. You may find the following two lemmas useful: *)
Lemma parity_ge_2 : forall x,
2 <= x ->
parity (x - 2) = parity x.
Proof.
induction x; intro. reflexivity.
destruct x. inversion H. inversion H1.
simpl. rewrite <- minus_n_O. reflexivity.
Qed.
Lemma parity_lt_2 : forall x,
~ 2 <= x ->
parity (x) = x.
Proof.
intros. induction x. reflexivity. destruct x. reflexivity.
apply ex_falso_quodlibet. apply H. omega.
Qed.
Theorem parity_correct : forall m,
{{ fun st => st X = m }}
WHILE BLe (ANum 2) (AId X) DO
X ::= AMinus (AId X) (ANum 2)
END
{{ fun st => st X = parity m }}.
Proof.
intro m.
eapply hoare_consequence.
apply hoare_while with (P:=fun st => parity (st X) = parity m).
Case "Body preserves invariant".
eapply hoare_consequence_pre.
apply hoare_asgn. intros st [Hpar Hb].
unfold assn_sub, update. simpl. rewrite <- Hpar. apply parity_ge_2.
unfold bassn, beval, aeval in Hb. apply ble_nat_true in Hb. assumption.
Case "Pre condition".
intros st H. rewrite H. reflexivity.
Case "Post condition".
intros st [Hpar Hb]. rewrite <- Hpar. symmetry. apply parity_lt_2.
unfold bassn,beval,aeval in Hb. rewrite not_true_iff_false in Hb.
apply ble_nat_false in Hb. assumption.
Qed.
(** [] *)
(* ####################################################### *)
(** ** Example: Finding Square Roots *)
(** The following program computes the square root of [X]
by naive iteration:
{{ X=m }}
Z ::= 0;
WHILE (Z+1)*(Z+1) <= X DO
Z ::= Z+1
END
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
*)
(** As above, we can try to use the postcondition as a candidate
invariant, obtaining the following decorated program:
(1) {{ X=m }} ->> (a - second conjunct of (2) WRONG!)
(2) {{ 0*0 <= m /\ m<1*1 }}
Z ::= 0;
(3) {{ Z*Z <= m /\ m<(Z+1)*(Z+1) }}
WHILE (Z+1)*(Z+1) <= X DO
(4) {{ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - WRONG!)
(5) {{ (Z+1)*(Z+1)<=m /\ m<(Z+2)*(Z+2) }}
Z ::= Z+1
(6) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
END
(7) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
(8) {{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This didn't work very well: both conditions (a) and (c) failed.
Looking at condition (c), we see that the second conjunct of (4)
is almost the same as the first conjunct of (5), except that (4)
mentions [X] while (5) mentions [m]. But note that [X] is never
assigned in this program, so we should have [X=m], but we didn't
propagate this information from (1) into the loop invariant.
Also, looking at the second conjunct of (8), it seems quite
hopeless as an invariant -- and we don't even need it, since we
can obtain it from the negation of the guard (third conjunct
in (7)), again under the assumption that [X=m].
So we now try [X=m /\ Z*Z <= m] as the loop invariant:
{{ X=m }} ->> (a - OK)
{{ X=m /\ 0*0 <= m }}
Z ::= 0;
{{ X=m /\ Z*Z <= m }}
WHILE (Z+1)*(Z+1) <= X DO
{{ X=m /\ Z*Z<=m /\ (Z+1)*(Z+1)<=X }} ->> (c - OK)
{{ X=m /\ (Z+1)*(Z+1)<=m }}
Z ::= Z+1
{{ X=m /\ Z*Z<=m }}
END
{{ X=m /\ Z*Z<=m /\ X<(Z+1)*(Z+1) }} ->> (b - OK)
{{ Z*Z<=m /\ m<(Z+1)*(Z+1) }}
This works, since conditions (a), (b), and (c) are now all
trivially satisfied.
Very often, if a variable is used in a loop in a read-only
fashion (i.e., it is referred to by the program or by the
specification and it is not changed by the loop) it is necessary
to add the fact that it doesn't change to the loop invariant. *)
(* ####################################################### *)
(** ** Example: Squaring *)
(** Here is a program that squares [X] by repeated addition:
{{ X = m }}
Y ::= 0;
Z ::= 0;
WHILE Y <> X DO
Z ::= Z + X;
Y ::= Y + 1
END
{{ Z = m*m }}
*)
(** The first thing to note is that the loop reads [X] but doesn't
change its value. As we saw in the previous example, in such cases
it is a good idea to add [X = m] to the invariant. The other thing
we often use in the invariant is the postcondition, so let's add
that too, leading to the invariant candidate [Z = m * m /\ X = m].
{{ X = m }} ->> (a - WRONG)
{{ 0 = m*m /\ X = m }}
Y ::= 0;
{{ 0 = m*m /\ X = m }}
Z ::= 0;
{{ Z = m*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - WRONG)
{{ Z+X = m*m /\ X = m }}
Z ::= Z + X;
{{ Z = m*m /\ X = m }}
Y ::= Y + 1
{{ Z = m*m /\ X = m }}
END
{{ Z = m*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
Conditions (a) and (c) fail because of the [Z = m*m] part. While
[Z] starts at [0] and works itself up to [m*m], we can't expect
[Z] to be [m*m] from the start. If we look at how [Z] progesses
in the loop, after the 1st iteration [Z = m], after the 2nd
iteration [Z = 2*m], and at the end [Z = m*m]. Since the variable
[Y] tracks how many times we go through the loop, we derive the
new invariant candidate [Z = Y*m /\ X = m].
{{ X = m }} ->> (a - OK)
{{ 0 = 0*m /\ X = m }}
Y ::= 0;
{{ 0 = Y*m /\ X = m }}
Z ::= 0;
{{ Z = Y*m /\ X = m }}
WHILE Y <> X DO
{{ Z = Y*m /\ X = m /\ Y <> X }} ->> (c - OK)
{{ Z+X = (Y+1)*m /\ X = m }}
Z ::= Z + X;
{{ Z = (Y+1)*m /\ X = m }}
Y ::= Y + 1
{{ Z = Y*m /\ X = m }}
END
{{ Z = Y*m /\ X = m /\ Y = X }} ->> (b - OK)
{{ Z = m*m }}
This new invariant makes the proof go through: all three
conditions are easy to check.
It is worth comparing the postcondition [Z = m*m] and the [Z =
Y*m] conjunct of the invariant. It is often the case that one has
to replace auxiliary variabes (parameters) with variables -- or
with expressions involving both variables and parameters (like
[m - Y]) -- when going from postconditions to invariants. *)
(* ####################################################### *)
(** ** Exercise: Factorial *)
(** **** Exercise: 3 stars (factorial) *)
(** Recall that [n!] denotes the factorial of [n] (i.e. [n! =
1*2*...*n]). Here is an Imp program that calculates the factorial
of the number initially stored in the variable [X] and puts it in
the variable [Y]:
{{ X = m }} ;
Y ::= 1
WHILE X <> 0
DO
Y ::= Y * X
X ::= X - 1
END
{{ Y = m! }}
Fill in the blanks in following decorated program:
{{ X = m }} ->>
{{ 1 = m! / X! }}
Y ::= 1;
{{ Y = m! / X! }}
WHILE X <> 0
DO {{ Y = m! / X! /\ X <> 0 }} ->>
{{ Y*X = m! / (X-1)! }}
Y ::= Y * X;
{{ Y = m! / (X-1)! }}
X ::= X - 1
{{ Y = m! / X! }}
END
{{ Y = m! / X! /\ ~ (X <> 0) }} ->>
{{ Y = m! }}
*)
(** [] *)
(* ####################################################### *)
(** ** Exercise: Min *)
(** **** Exercise: 3 stars (Min_Hoare) *)
(** Fill in valid decorations for the following program.
For the => steps in your annotations, you may rely (silently) on the
following facts about min
Lemma lemma1 : forall x y,
(x=0 \/ y=0) -> min x y = 0.
Lemma lemma2 : forall x y,
min (x-1) (y-1) = (min x y) - 1.
plus, as usual, standard high-school algebra.
{{ True }} ->>
{{ a = a /\ b = b /\ 0 = 0 }}
X ::= a;
{{ X = a /\ b = b /\ 0 = 0 }}
Y ::= b;
{{ X = a /\ Y = b /\ 0 = 0 }}
Z ::= 0;
{{ X = a /\ Y = b /\ Z = 0 }}
WHILE (X <> 0 /\ Y <> 0) DO
{{ Z = min a b - min X Y /\ X <> 0 /\ Y <> 0 }} ->>
{{ Z + 1 = min a b - min (X - 1) (Y - 1) }}
X := X - 1;
{{ Z + 1 = min a b - min X (Y - 1) }}
Y := Y - 1;
{{ Z + 1 = min a b - min X Y }}
Z := Z + 1;
{{ Z = min a b - min X Y }}
END
{{ Z = min a b - min X Y /\ ~( X <> 0 /\ Y <> 0) }} ->>
{{ Z = min a b }}
*)
(** **** Exercise: 3 stars (two_loops) *)
(** Here is a very inefficient way of adding 3 numbers:
X ::= 0;
Y ::= 0;
Z ::= c;
WHILE X <> a DO
X ::= X + 1;
Z ::= Z + 1
END;
WHILE Y <> b DO
Y ::= Y + 1;
Z ::= Z + 1
END
Show that it does what it should by filling in the blanks in the
following decorated program.
{{ True }} ->>
{{ 0 = 0 /\ 0 = 0 /\ c = c }}
X ::= 0;
{{ X = 0 /\ 0 = 0 /\ c = c }}
Y ::= 0;
{{ X = 0 /\ Y = 0 /\ c = c }}
Z ::= c;
{{ X = 0 /\ Y = 0 /\ Z = c }}
WHILE X <> a DO
{{ Z = c + X + Y /\ X <> a }} ->>
{{ Z + 1 = c + (X + 1) + Y }}
X ::= X + 1;
{{ Z + 1 = c + X + Y }}
Z ::= Z + 1
{{ Z = c + X + Y }}
END;
{{ Z = c + X + Y /\ ~ ( X <> a) }} ->>
{{ Z = c + a + Y }}
WHILE Y <> b DO
{{ Z = c + a + Y /\ Y <> b }} ->>
{{ Z + 1 = c + a + Y + 1 }}
Y ::= Y + 1;
{{ Z + 1 = c + a + Y }}
Z ::= Z + 1
{{ Z = c + a + Y }}
END
{{ Z = c + a + Y /\ ~ ( Y <> b ) }} ->>
{{ Z = a + b + c }}
*)
(* ####################################################### *)
(** ** Exercise: Power Series *)
(** **** Exercise: 4 stars, optional (dpow2_down) *)
(** Here is a program that computes the series:
[1 + 2 + 2^2 + ... + 2^m = 2^(m+1) - 1]
X ::= 0;
Y ::= 1;
Z ::= 1;
WHILE X <> m DO
Z ::= 2 * Z;
Y ::= Y + Z;
X ::= X + 1;
END
Write a decorated program for this. *)
(*
{{ 0 = 0 /\ 1 = 1 /\ 1 = 1 }}
X ::= 0;
Y ::= 1;
Z ::= 1;
{{ X = 0 /\ Y = 1 /\ Z = 1 }} ->>
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ X = 0}}
WHILE X <> m DO
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ X <> m}} ->>
{{ Y = 2^(X+1) - 1 /\ 2*Z = 2^(X+1) }}
Z ::= 2 * Z;
{{ Y = 2^(X+1) - 1 /\ Z = 2^(X+1) }} ->>
{{ Y + Z = 2^(X+1) - 1 + 2^(X+1) /\ Z = 2^(X+1) }}
Y ::= Y + Z;
{{ Y = 2^(X+1) - 1 + 2^(X+1)}} ->>
{{ Y = 2^(X+1+1) - 1 /\ Z = 2^(X+1) }}
X ::= X + 1;
{{ Y = 2^(X+1) - 1 /\ Z = 2^X }}
END
{{ Y = 2^(X+1) - 1 /\ Z = 2^X /\ ~ (X <> m) }} ->>
{{ Y = 2^(m+1) - 1 }}
*)
(* ####################################################### *)
(** * Weakest Preconditions (Advanced) *)
(** Some Hoare triples are more interesting than others.
For example,
{{ False }} X ::= Y + 1 {{ X <= 5 }}
is _not_ very interesting: although it is perfectly valid, it
tells us nothing useful. Since the precondition isn't satisfied
by any state, it doesn't describe any situations where we can use
the command [X ::= Y + 1] to achieve the postcondition [X <= 5].
By contrast,
{{ Y <= 4 /\ Z = 0 }} X ::= Y + 1 {{ X <= 5 }}
is useful: it tells us that, if we can somehow create a situation
in which we know that [Y <= 4 /\ Z = 0], then running this command
will produce a state satisfying the postcondition. However, this
triple is still not as useful as it could be, because the [Z = 0]
clause in the precondition actually has nothing to do with the
postcondition [X <= 5]. The _most_ useful triple (for a given
command and postcondition) is this one:
{{ Y <= 4 }} X ::= Y + 1 {{ X <= 5 }}
In other words, [Y <= 4] is the _weakest_ valid precondition of
the command [X ::= Y + 1] for the postcondition [X <= 5]. *)
(** In general, we say that "[P] is the weakest precondition of
command [c] for postcondition [Q]" if [{{P}} c {{Q}}] and if,
whenever [P'] is an assertion such that [{{P'}} c {{Q}}], we have
[P' st] implies [P st] for all states [st]. *)
Definition is_wp P c Q :=
{{P}} c {{Q}} /\
forall P', {{P'}} c {{Q}} -> (P' ->> P).
(** That is, [P] is the weakest precondition of [c] for [Q]
if (a) [P] _is_ a precondition for [Q] and [c], and (b) [P] is the
_weakest_ (easiest to satisfy) assertion that guarantees [Q] after
executing [c]. *)
(** **** Exercise: 1 star, optional (wp) *)
(** What are the weakest preconditions of the following commands
for the following postconditions?
1) {{ X = 5 }} SKIP {{ X = 5 }}
2) {{ Y + Z = 5 }} X ::= Y + Z {{ X = 5 }}
3) {{ True }} X ::= Y {{ X = Y }}
4) {{ X = 0 /\ Z = 4 \/ X <> 0 /\ W = 3 }}
IFB X == 0 THEN Y ::= Z + 1 ELSE Y ::= W + 2 FI
{{ Y = 5 }}
5) {{ False }}
X ::= 5
{{ X = 0 }}
6) {{ True }}
WHILE True DO X ::= 0 END
{{ X = 0 }}
*)
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (is_wp_formal) *)
(** Prove formally using the definition of [hoare_triple] that [Y <= 4]
is indeed the weakest precondition of [X ::= Y + 1] with respect to
postcondition [X <= 5]. *)
Theorem is_wp_example :
is_wp (fun st => st Y <= 4)
(X ::= APlus (AId Y) (ANum 1)) (fun st => st X <= 5).
Proof.
unfold is_wp. split.
Case "{{P}} c {{Q}}".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assert_implies, assn_sub, aeval, update. intros st H. simpl. omega.
Case "P' ->> P".
unfold assert_implies, hoare_triple.
intros P Hassn st HP.
apply Hassn with (st' := update st X (aeval st (APlus (AId Y) (ANum 1)))) in HP.
unfold update, aeval in HP. simpl in HP. omega. constructor. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_weakest) *)
(** Show that the precondition in the rule [hoare_asgn] is in fact the
weakest precondition. *)
Theorem hoare_asgn_weakest : forall Q X a,
is_wp (Q [X |-> a]) (X ::= a) Q.
Proof.
unfold is_wp. intros Q X a. split.
Case "{{P}} c {{Q}}". apply hoare_asgn.
Case "P' ->> P".
unfold assert_implies, hoare_triple, assn_sub. intros P Hassn st HP.
apply Hassn with (st:=st). constructor. reflexivity. assumption.
Qed.
(** [] *)
(** **** Exercise: 2 stars, advanced, optional (hoare_havoc_weakest) *)
(** Show that your [havoc_pre] rule from the [himp_hoare] exercise
in the [Hoare] chapter returns the weakest precondition. *)
Module Himp2.
Import Himp.
Lemma hoare_havoc_weakest : forall (P Q : Assertion) (X : id),
{{ P }} HAVOC X {{ Q }} ->
P ->> havoc_pre X Q.
Proof.
unfold assert_implies, havoc_pre. intros P Q X H st HP n.
apply (H st). constructor. assumption.
Qed.
End Himp2.
(** [] *)
(* ####################################################### *)
(** * Formal Decorated Programs (Advanced) *)
(** The informal conventions for decorated programs amount to a way of
displaying Hoare triples in which commands are annotated with
enough embedded assertions that checking the validity of the
triple is reduced to simple logical and algebraic calculations
showing that some assertions imply others. In this section, we
show that this informal presentation style can actually be made
completely formal and indeed that checking the validity of
decorated programs can mostly be automated. *)
(** ** Syntax *)
(** The first thing we need to do is to formalize a variant of the
syntax of commands with embedded assertions. We call the new
commands _decorated commands_, or [dcom]s. *)
Inductive dcom : Type :=
| DCSkip : Assertion -> dcom
| DCSeq : dcom -> dcom -> dcom
| DCAsgn : id -> aexp -> Assertion -> dcom
| DCIf : bexp -> Assertion -> dcom -> Assertion -> dcom
-> Assertion-> dcom
| DCWhile : bexp -> Assertion -> dcom -> Assertion -> dcom
| DCPre : Assertion -> dcom -> dcom
| DCPost : dcom -> Assertion -> dcom.
Tactic Notation "dcom_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "Skip" | Case_aux c "Seq" | Case_aux c "Asgn"
| Case_aux c "If" | Case_aux c "While"
| Case_aux c "Pre" | Case_aux c "Post" ].
Notation "'SKIP' {{ P }}"
:= (DCSkip P)
(at level 10) : dcom_scope.
Notation "l '::=' a {{ P }}"
:= (DCAsgn l a P)
(at level 60, a at next level) : dcom_scope.
Notation "'WHILE' b 'DO' {{ Pbody }} d 'END' {{ Ppost }}"
:= (DCWhile b Pbody d Ppost)
(at level 80, right associativity) : dcom_scope.
Notation "'IFB' b 'THEN' {{ P }} d 'ELSE' {{ P' }} d' 'FI' {{ Q }}"
:= (DCIf b P d P' d' Q)
(at level 80, right associativity) : dcom_scope.
Notation "'->>' {{ P }} d"
:= (DCPre P d)
(at level 90, right associativity) : dcom_scope.
Notation "{{ P }} d"
:= (DCPre P d)
(at level 90) : dcom_scope.
Notation "d '->>' {{ P }}"
:= (DCPost d P)
(at level 80, right associativity) : dcom_scope.
Notation " d ;; d' "
:= (DCSeq d d')
(at level 80, right associativity) : dcom_scope.
Delimit Scope dcom_scope with dcom.
(** To avoid clashing with the existing [Notation] definitions
for ordinary [com]mands, we introduce these notations in a special
scope called [dcom_scope], and we wrap examples with the
declaration [% dcom] to signal that we want the notations to be
interpreted in this scope.
Careful readers will note that we've defined two notations for the
[DCPre] constructor, one with and one without a [->>]. The
"without" version is intended to be used to supply the initial
precondition at the very top of the program. *)
Example dec_while : dcom := (
{{ fun st => True }}
WHILE (BNot (BEq (AId X) (ANum 0)))
DO
{{ fun st => True /\ st X <> 0}}
X ::= (AMinus (AId X) (ANum 1))
{{ fun _ => True }}
END
{{ fun st => True /\ st X = 0}} ->>
{{ fun st => st X = 0 }}
) % dcom.
(** It is easy to go from a [dcom] to a [com] by erasing all
annotations. *)
Fixpoint extract (d:dcom) : com :=
match d with
| DCSkip _ => SKIP
| DCSeq d1 d2 => (extract d1 ;; extract d2)
| DCAsgn X a _ => X ::= a
| DCIf b _ d1 _ d2 _ => IFB b THEN extract d1 ELSE extract d2 FI
| DCWhile b _ d _ => WHILE b DO extract d END
| DCPre _ d => extract d
| DCPost d _ => extract d
end.
(** The choice of exactly where to put assertions in the definition of
[dcom] is a bit subtle. The simplest thing to do would be to
annotate every [dcom] with a precondition and postcondition. But
this would result in very verbose programs with a lot of repeated
annotations: for example, a program like [SKIP;SKIP] would have to
be annotated as
{{P}} ({{P}} SKIP {{P}}) ;; ({{P}} SKIP {{P}}) {{P}},
with pre- and post-conditions on each [SKIP], plus identical pre-
and post-conditions on the semicolon!
Instead, the rule we've followed is this:
- The _post_-condition expected by each [dcom] [d] is embedded in [d]
- The _pre_-condition is supplied by the context. *)
(** In other words, the invariant of the representation is that a
[dcom] [d] together with a precondition [P] determines a Hoare
triple [{{P}} (extract d) {{post d}}], where [post] is defined as
follows: *)
Fixpoint post (d:dcom) : Assertion :=
match d with
| DCSkip P => P
| DCSeq d1 d2 => post d2
| DCAsgn X a Q => Q
| DCIf _ _ d1 _ d2 Q => Q
| DCWhile b Pbody c Ppost => Ppost
| DCPre _ d => post d
| DCPost c Q => Q
end.
(** Similarly, we can extract the "initial precondition" from a
decorated program. *)
Fixpoint pre (d:dcom) : Assertion :=
match d with
| DCSkip P => fun st => True
| DCSeq c1 c2 => pre c1
| DCAsgn X a Q => fun st => True
| DCIf _ _ t _ e _ => fun st => True
| DCWhile b Pbody c Ppost => fun st => True
| DCPre P c => P
| DCPost c Q => pre c
end.
(** This function is not doing anything sophisticated like calculating
a weakest precondition; it just recursively searches for an
explicit annotation at the very beginning of the program,
returning default answers for programs that lack an explicit
precondition (like a bare assignment or [SKIP]). *)
(** Using [pre] and [post], and assuming that we adopt the convention
of always supplying an explicit precondition annotation at the
very beginning of our decorated programs, we can express what it
means for a decorated program to be correct as follows: *)
Definition dec_correct (d:dcom) :=
{{pre d}} (extract d) {{post d}}.
(** To check whether this Hoare triple is _valid_, we need a way to
extract the "proof obligations" from a decorated program. These
obligations are often called _verification conditions_, because
they are the facts that must be verified to see that the
decorations are logically consistent and thus add up to a complete
proof of correctness. *)
(** ** Extracting Verification Conditions *)
(** The function [verification_conditions] takes a [dcom] [d] together
with a precondition [P] and returns a _proposition_ that, if it
can be proved, implies that the triple [{{P}} (extract d) {{post d}}]
is valid. *)
(** It does this by walking over [d] and generating a big
conjunction including all the "local checks" that we listed when
we described the informal rules for decorated programs. (Strictly
speaking, we need to massage the informal rules a little bit to
add some uses of the rule of consequence, but the correspondence
should be clear.) *)
Fixpoint verification_conditions (P : Assertion) (d:dcom) : Prop :=
match d with
| DCSkip Q =>
(P ->> Q)
| DCSeq d1 d2 =>
verification_conditions P d1
/\ verification_conditions (post d1) d2
| DCAsgn X a Q =>
(P ->> Q [X |-> a])
| DCIf b P1 d1 P2 d2 Q =>
((fun st => P st /\ bassn b st) ->> P1)
/\ ((fun st => P st /\ ~ (bassn b st)) ->> P2)
/\ (Q <<->> post d1) /\ (Q <<->> post d2)
/\ verification_conditions P1 d1
/\ verification_conditions P2 d2
| DCWhile b Pbody d Ppost =>
(* post d is the loop invariant and the initial precondition *)
(P ->> post d)
/\ (Pbody <<->> (fun st => post d st /\ bassn b st))
/\ (Ppost <<->> (fun st => post d st /\ ~(bassn b st)))
/\ verification_conditions Pbody d
| DCPre P' d =>
(P ->> P') /\ verification_conditions P' d
| DCPost d Q =>
verification_conditions P d /\ (post d ->> Q)
end.
(** And now, the key theorem, which states that
[verification_conditions] does its job correctly. Not
surprisingly, we need to use each of the Hoare Logic rules at some
point in the proof. *)
(** We have used _in_ variants of several tactics before to
apply them to values in the context rather than the goal. An
extension of this idea is the syntax [tactic in *], which applies
[tactic] in the goal and every hypothesis in the context. We most
commonly use this facility in conjunction with the [simpl] tactic,
as below. *)
Theorem verification_correct : forall d P,
verification_conditions P d -> {{P}} (extract d) {{post d}}.
Proof.
dcom_cases (induction d) Case; intros P H; simpl in *.
Case "Skip".
eapply hoare_consequence_pre.
apply hoare_skip.
assumption.
Case "Seq".
inversion H as [H1 H2]. clear H.
eapply hoare_seq.
apply IHd2. apply H2.
apply IHd1. apply H1.
Case "Asgn".
eapply hoare_consequence_pre.
apply hoare_asgn.
assumption.
Case "If".
inversion H as [HPre1 [HPre2 [[Hd11 Hd12]
[[Hd21 Hd22] [HThen HElse]]]]].
clear H.
apply IHd1 in HThen. clear IHd1.
apply IHd2 in HElse. clear IHd2.
apply hoare_if.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
Case "While".
inversion H as [Hpre [[Hbody1 Hbody2] [[Hpost1 Hpost2] Hd]]];
subst; clear H.
eapply hoare_consequence_pre; eauto.
eapply hoare_consequence_post; eauto.
apply hoare_while.
eapply hoare_consequence_pre; eauto.
Case "Pre".
inversion H as [HP Hd]; clear H.
eapply hoare_consequence_pre. apply IHd. apply Hd. assumption.
Case "Post".
inversion H as [Hd HQ]; clear H.
eapply hoare_consequence_post. apply IHd. apply Hd. assumption.
Qed.
(** ** Examples *)
(** The propositions generated by [verification_conditions] are fairly
big, and they contain many conjuncts that are essentially trivial. *)
Eval simpl in (verification_conditions (fun st => True) dec_while).
(**
==>
(((fun _ : state => True) ->> (fun _ : state => True)) /\
((fun _ : state => True) ->> (fun _ : state => True)) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) =
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) /\
(fun st : state => True /\ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun _ : state => True) [X |-> AMinus (AId X) (ANum 1)]) /\
(fun st : state => True /\ ~ bassn (BNot (BEq (AId X) (ANum 0))) st) ->>
(fun st : state => st X = 0)
*)
(** In principle, we could certainly work with them using just the
tactics we have so far, but we can make things much smoother with
a bit of automation. We first define a custom [verify] tactic
that applies splitting repeatedly to turn all the conjunctions
into separate subgoals and then uses [omega] and [eauto] (a handy
general-purpose automation tactic that we'll discuss in detail
later) to deal with as many of them as possible. *)
Lemma ble_nat_true_iff : forall n m : nat,
ble_nat n m = true <-> n <= m.
Proof.
intros n m. split. apply ble_nat_true.
generalize dependent m. induction n; intros m H. reflexivity.
simpl. destruct m. inversion H.
apply le_S_n in H. apply IHn. assumption.
Qed.
Lemma ble_nat_false_iff : forall n m : nat,
ble_nat n m = false <-> ~(n <= m).
Proof.
intros n m. split. apply ble_nat_false.
generalize dependent m. induction n; intros m H.
apply ex_falso_quodlibet. apply H. apply le_0_n.
simpl. destruct m. reflexivity.
apply IHn. intro Hc. apply H. apply le_n_S. assumption.
Qed.
Tactic Notation "verify" :=
apply verification_correct;
repeat split;
simpl; unfold assert_implies;
unfold bassn in *; unfold beval in *; unfold aeval in *;
unfold assn_sub; intros;
repeat rewrite update_eq;
repeat (rewrite update_neq; [| (intro X; inversion X)]);
simpl in *;
repeat match goal with [H : _ /\ _ |- _] => destruct H end;
repeat rewrite not_true_iff_false in *;
repeat rewrite not_false_iff_true in *;
repeat rewrite negb_true_iff in *;
repeat rewrite negb_false_iff in *;
repeat rewrite beq_nat_true_iff in *;
repeat rewrite beq_nat_false_iff in *;
repeat rewrite ble_nat_true_iff in *;
repeat rewrite ble_nat_false_iff in *;
try subst;
repeat
match goal with
[st : state |- _] =>
match goal with
[H : st _ = _ |- _] => rewrite -> H in *; clear H
| [H : _ = st _ |- _] => rewrite <- H in *; clear H
end
end;
try eauto; try omega.
(** What's left after [verify] does its thing is "just the interesting
parts" of checking that the decorations are correct. For very
simple examples [verify] immediately solves the goal (provided
that the annotations are correct). *)
Theorem dec_while_correct :
dec_correct dec_while.
Proof. verify. Qed.
(** Another example (formalizing a decorated program we've seen
before): *)
Example subtract_slowly_dec (m:nat) (p:nat) : dcom := (
{{ fun st => st X = m /\ st Z = p }} ->>
{{ fun st => st Z - st X = p - m }}
WHILE BNot (BEq (AId X) (ANum 0))
DO {{ fun st => st Z - st X = p - m /\ st X <> 0 }} ->>
{{ fun st => (st Z - 1) - (st X - 1) = p - m }}
Z ::= AMinus (AId Z) (ANum 1)
{{ fun st => st Z - (st X - 1) = p - m }} ;;
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st Z - st X = p - m }}
END
{{ fun st => st Z - st X = p - m /\ st X = 0 }} ->>
{{ fun st => st Z = p - m }}
) % dcom.
Theorem subtract_slowly_dec_correct : forall m p,
dec_correct (subtract_slowly_dec m p).
Proof. intros m p. verify. (* this grinds for a bit! *) Qed.
(** **** Exercise: 3 stars, advanced (slow_assignment_dec) *)
(** In the [slow_assignment] exercise above, we saw a roundabout way
of assigning a number currently stored in [X] to the variable [Y]:
start [Y] at [0], then decrement [X] until it hits [0],
incrementing [Y] at each step.
Write a _formal_ version of this decorated program and prove it
correct. *)
Example slow_assignment_dec (m:nat) : dcom := (
{{ fun st => st X = m }} ->>
{{ fun st => st X = m /\ st Y = st Y }}
Y ::= ANum 0
{{ fun st => st X = m /\ st Y = 0 }} ;;
->>
{{ fun st => st X + st Y = m }}
WHILE BNot (BEq (AId X) (ANum 0)) DO
{{ fun st => st X + st Y = m /\ st X <> 0 }} ->>
{{ fun st => (st X - 1) + (st Y + 1) = m }}
X ::= AMinus (AId X) (ANum 1)
{{ fun st => st X + (st Y + 1) = m }} ;;
Y ::= APlus (AId Y) (ANum 1)
{{ fun st => st X + st Y = m }}
END
{{ fun st => st X + st Y = m /\ ~(st X <> 0) }} ->>
{{ fun st => st Y = m }}
) % dcom.
Theorem slow_assignment_dec_correct : forall m,
dec_correct (slow_assignment_dec m).
Proof. intro m. verify. Qed.
(** [] *)
(** **** Exercise: 4 stars, advanced (factorial_dec) *)
(** Remember the factorial function we worked with before: *)
Fixpoint real_fact (n:nat) : nat :=
match n with
| O => 1
| S n' => n * (real_fact n')
end.
Lemma real_fact_succ : forall n,
real_fact (n+1) = (n+1) * real_fact n.
Proof.
intros n. replace (n+1) with (S n) by omega. reflexivity.
Qed.
(** Following the pattern of [subtract_slowly_dec], write a decorated
program that implements the factorial function and prove it
correct. *)
Example factorial_dec (n:nat) : dcom := (
{{ fun _ => True }}
X ::= ANum 1
{{ fun st => st X = 1 }} ;;
Y ::= ANum 1
{{ fun st => st X = 1 /\ st Y = 1 }} ;;
->>
{{ fun st => st Y = real_fact (st X) }}
WHILE BNot (BEq (AId X) (ANum n)) DO
{{ fun st => st Y = real_fact (st X) /\ st X <> n }}
->>
{{ fun st => (st X + 1) * st Y = real_fact ((st X) + 1) }}
X ::= APlus (AId X) (ANum 1)
{{ fun st => st X * st Y = real_fact (st X) }} ;;
Y ::= AMult (AId X) (AId Y)
{{ fun st => st Y = real_fact (st X) }}
END
{{ fun st => st Y = real_fact (st X) /\ ~ (st X <> n) }} ->>
{{ fun st => st Y = real_fact n }}
) % dcom.
Theorem factorial_dec_correct : forall n,
dec_correct (factorial_dec n).
Proof.
intro n. verify. symmetry. apply real_fact_succ.
assert ({st X = n} + {st X <> n}) by (apply eq_nat_dec).
inversion H; clear H. auto.
apply H0 in H1. inversion H1.
Qed.
(* FILL IN HERE *)
(** [] *)
(* $Date: 2013-07-17 16:19:11 -0400 (Wed, 17 Jul 2013) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14_V
`define SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14_V
/**
* sleep_sergate_plv: connect vpr to virtpwr when not in sleep mode.
*
* Verilog wrapper for sleep_sergate_plv with size of 14 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__sleep_sergate_plv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_14 (
VIRTPWR,
SLEEP ,
VPWR ,
VPB ,
VNB
);
output VIRTPWR;
input SLEEP ;
input VPWR ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP),
.VPWR(VPWR),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__sleep_sergate_plv_14 (
VIRTPWR,
SLEEP
);
output VIRTPWR;
input SLEEP ;
// Voltage supply signals
supply1 VPWR;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__sleep_sergate_plv base (
.VIRTPWR(VIRTPWR),
.SLEEP(SLEEP)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__SLEEP_SERGATE_PLV_14_V
|
// 74181 4-bit ALU
module alu181(
input [3:0] a, b,
input m,
input c_,
input [3:0] s,
output [3:0] f,
output g, p,
output co_,
output eq
);
wire [3:0] s0 = {4{s[0]}};
wire [3:0] s1 = {4{s[1]}};
wire [3:0] s2 = {4{s[2]}};
wire [3:0] s3 = {4{s[3]}};
wire [3:0] u = ~((a) | (b & s0) | (~b & s1)); // 3 ands
wire [3:0] v = ~((~b & s2 & a) | (b & s3 & a)); // 2 ands
wire [3:0] w = u ^ v;
wire [3:0] z;
assign z[0] = ~(~m & c_);
assign z[1] = ~(~m & ((u[0]) | (v[0] & c_)));
assign z[2] = ~(~m & ((u[1]) | (u[0] & v[1]) | (v[1] & v[0] & c_)));
assign z[3] = ~(~m & ((u[2]) | (v[2] & u[1]) | (v[2] & u[0] & v[1]) | (v[2] & v[1] & v[0] & c_)));
assign g = ~((u[0] & v[1] & v[2] & v[3]) | (u[1] & v[2] & v[3]) | (u[2] & v[3]) | (u[3]));
assign p = ~(&v);
wire g2 = ~(&v & c_);
assign co_ = ~g2 | ~g;
assign f = w ^ z;
assign eq = &f;
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
module top (
input wire clk,
input wire rx,
output wire tx,
input wire [15:0] sw,
output wire [15:0] led
);
RAM32X1D #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram3 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.DPRA4 (sw[10]),
.DPRA3 (sw[9]),
.DPRA2 (sw[8]),
.DPRA1 (sw[7]),
.DPRA0 (sw[6]),
.SPO (led[0]),
.DPO (led[1]),
.D (sw[13]),
.WE (sw[15])
);
RAM32X1D #(
.INIT(32'b00000000_00000000_00000000_00000010)
) ram4 (
.WCLK (clk),
.A4 (sw[4]),
.A3 (sw[3]),
.A2 (sw[2]),
.A1 (sw[1]),
.A0 (sw[0]),
.DPRA4 (sw[10]),
.DPRA3 (sw[9]),
.DPRA2 (sw[8]),
.DPRA1 (sw[7]),
.DPRA0 (sw[6]),
.SPO (led[2]),
.DPO (led[3]),
.D (sw[12]),
.WE (sw[15])
);
assign led[15:4] = sw[15:4];
assign tx = rx;
endmodule
|
////////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2012, Ameer M. Abdelhadi; [email protected]. All rights reserved. //
// //
// Redistribution and use in source and binary forms, with or without //
// modification, are permitted provided that the following conditions are met: //
// * Redistributions of source code must retain the above copyright //
// notice, this list of conditions and the following disclaimer. //
// * Redistributions in binary form must reproduce the above copyright //
// notice, this list of conditions and the following disclaimer in the //
// documentation and/or other materials provided with the distribution. //
// * Neither the name of the University of British Columbia (UBC) nor the names //
// of its contributors may be used to endorse or promote products //
// derived from this software without specific prior written permission. //
// //
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" //
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE //
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE //
// DISCLAIMED. IN NO EVENT SHALL University of British Columbia (UBC) BE LIABLE //
// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL //
// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR //
// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER //
// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, //
// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE //
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
////////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////////
// rstgen.v: reset generator, based on lfsr counter //
// //
// Ameer M.S. Abdelhadi ([email protected]; [email protected]), May 2012 //
////////////////////////////////////////////////////////////////////////////////////
`include "math.v"
module rstgen
#( parameter WID = 16 ) // LOG2 reset cycles
( input clk , // input clock
input rsti , // input reset; pass 1'b0 if not required
output rsto ); // output reset
// lfsr count output
reg [WID-1:0] cnt;
// lfst feedback function
wire fb;
lfsr_fb #( .WID(WID) ) // integer: register width, up to 168.
lfsr_fb_inst ( .cnt(cnt) , // input clock
.fb (fb ) ); // output random count number
localparam LASTCNT = {1'b1,{(WID-1){1'b0}}}; // last lfsr number before rolling back to all 0's
wire is_last = (cnt == LASTCNT) ; // last lfsr number reached
always @(posedge clk or posedge rsti)
if (rsti ) cnt <= {WID{1'b0}} ;
else if (is_last) cnt <= LASTCNT ;
else cnt <= {cnt[WID-2:0],fb};
reg is_last_rh;
always @(posedge clk or posedge rsti)
if (rsti) is_last_rh <= 1'b0 ;
else is_last_rh <= is_last;
//reg is_last_rl;
//always @(negedge clk or posedge rsti)
// if (rsti) is_last_rl <= 1'b0 ;
// else is_last_rl <= is_last_rh;
assign rsto = !is_last_rh;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFBBP_TB_V
`define SKY130_FD_SC_MS__DFBBP_TB_V
/**
* dfbbp: Delay flop, inverted set, inverted reset,
* complementary outputs.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__dfbbp.v"
module top();
// Inputs are registered
reg D;
reg SET_B;
reg RESET_B;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Q;
wire Q_N;
initial
begin
// Initial state is x for all inputs.
D = 1'bX;
RESET_B = 1'bX;
SET_B = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 D = 1'b0;
#40 RESET_B = 1'b0;
#60 SET_B = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 D = 1'b1;
#180 RESET_B = 1'b1;
#200 SET_B = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 D = 1'b0;
#320 RESET_B = 1'b0;
#340 SET_B = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 SET_B = 1'b1;
#540 RESET_B = 1'b1;
#560 D = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 SET_B = 1'bx;
#680 RESET_B = 1'bx;
#700 D = 1'bx;
end
// Create a clock
reg CLK;
initial
begin
CLK = 1'b0;
end
always
begin
#5 CLK = ~CLK;
end
sky130_fd_sc_ms__dfbbp dut (.D(D), .SET_B(SET_B), .RESET_B(RESET_B), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Q(Q), .Q_N(Q_N), .CLK(CLK));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFBBP_TB_V
|
// ------------------------------------------------------------------------- //
// inst_decoder.v
//
// This module decodes instructions to control dataflow of our processor.
//
// Alex Interrante-Grant
// James Massucco
// 10/29/2016
// ------------------------------------------------------------------------- //
module inst_decoder(
input [15:0] instruction,
output reg [3:0] opcode, // Maybe not used...
output reg [1:0] rs_addr,
output reg [1:0] rt_addr,
output reg [1:0] rd_addr,
output reg [7:0] immediate,
output reg RegDst,
output reg RegWrite,
output reg ALUSrc1,
output reg ALUSrc2,
output reg [2:0] ALUOp,
output reg MemWrite,
output reg MemToReg
);
always @(instruction) begin
opcode = instruction[15:12];
rs_addr = instruction[11:10];
rt_addr = instruction[9:8];
rd_addr = instruction[7:6];
immediate = instruction[7:0];
case (instruction[15:12])
0:
begin
RegDst = 0;
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 1;
ALUOp = 0;
MemWrite = 0;
MemToReg = 1;
end
1:
begin
RegDst = 0;
RegWrite = 0;
ALUSrc1 = 0; //changed
ALUSrc2 = 1;
ALUOp = 0;
MemWrite = 1;
MemToReg = 0;
end
2:
begin
RegDst = 1; //changed
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 0;
MemWrite = 0;
MemToReg = 0;
end
3:
begin
RegDst = 0;
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 1;
ALUOp = 0;
MemWrite = 0;
MemToReg = 0;
end
4:
begin
RegDst = 1; //changed
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 1;
MemWrite = 0;
MemToReg = 0;
end
5:
begin
RegDst = 1; //changed
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 2;
MemWrite = 0;
MemToReg = 0;
end
6:
begin
RegDst = 0;
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 1; //changed
ALUOp = 2;
MemWrite = 0;
MemToReg = 0;
end
7:
begin
RegDst = 1; //changed
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 3;
MemWrite = 0;
MemToReg = 0;
end
8:
begin
RegDst = 0;
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 3;
MemWrite = 0;
MemToReg = 0;
end
9:
begin
RegDst = 0;
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 1;
ALUOp = 4;
MemWrite = 0;
MemToReg = 0;
end
10:
begin
RegDst = 0;
RegWrite = 1;
ALUSrc1 = 0;
ALUSrc2 = 1;
ALUOp = 5;
MemWrite = 0;
MemToReg = 0;
end
11:
begin
RegDst = 0;
RegWrite = 0;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 6;
MemWrite = 0;
MemToReg = 0;
end
12:
begin
RegDst = 0;
RegWrite = 0;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 7;
MemWrite = 0;
MemToReg = 0;
end
13:
begin
RegDst = 1; //changed
RegWrite = 1;
ALUSrc1 = 1;
ALUSrc2 = 0;
ALUOp = 2;
MemWrite = 0;
MemToReg = 0;
end
default
begin
RegDst = 0;
RegWrite = 0;
ALUSrc1 = 0;
ALUSrc2 = 0;
ALUOp = 0;
MemWrite = 0;
MemToReg = 0;
end
endcase
end
endmodule
|
(** * Logic: Logic in Coq *)
Require Export MoreCoq.
(** Coq's built-in logic is very small: the only primitives are
[Inductive] definitions, universal quantification ([forall]), and
implication ([->]), while all the other familiar logical
connectives -- conjunction, disjunction, negation, existential
quantification, even equality -- can be encoded using just these.
This chapter explains the encodings and shows how the tactics
we've seen can be used to carry out standard forms of logical
reasoning involving these connectives. *)
(* ########################################################### *)
(** * Propositions *)
(** In previous chapters, we have seen many examples of factual
claims (_propositions_) and ways of presenting evidence of their
truth (_proofs_). In particular, we have worked extensively with
_equality propositions_ of the form [e1 = e2], with
implications ([P -> Q]), and with quantified propositions
([forall x, P]).
*)
(** In Coq, the type of things that can (potentially)
be proven is [Prop]. *)
(** Here is an example of a provable proposition: *)
Check (3 = 3).
(* ===> Prop *)
(** Here is an example of an unprovable proposition: *)
Check (forall (n:nat), n = 2).
(* ===> Prop *)
(** Recall that [Check] asks Coq to tell us the type of the indicated
expression. *)
(* ########################################################### *)
(** * Proofs and Evidence *)
(** In Coq, propositions have the same status as other types, such as
[nat]. Just as the natural numbers [0], [1], [2], etc. inhabit
the type [nat], a Coq proposition [P] is inhabited by its
_proofs_. We will refer to such inhabitants as _proof term_ or
_proof object_ or _evidence_ for the truth of [P].
In Coq, when we state and then prove a lemma such as:
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
the tactics we use within the [Proof]...[Qed] keywords tell Coq
how to construct a proof term that inhabits the proposition. In
this case, the proposition [0 * 3 = 0] is justified by a
combination of the _definition_ of [mult], which says that [0 * 3]
_simplifies_ to just [0], and the _reflexive_ principle of
equality, which says that [0 = 0].
*)
(** *** *)
Lemma silly : 0 * 3 = 0.
Proof. reflexivity. Qed.
(** We can see which proof term Coq constructs for a given Lemma by
using the [Print] directive: *)
Print silly.
(* ===> silly = eq_refl : 0 * 3 = 0 *)
(** Here, the [eq_refl] proof term witnesses the equality. (More on equality later!)*)
(** ** Implications _are_ functions *)
(** Just as we can implement natural number multiplication as a
function:
[
mult : nat -> nat -> nat
]
The _proof term_ for an implication [P -> Q] is a _function_ that takes evidence for [P] as input and produces evidence for [Q] as its output.
*)
Lemma silly_implication : (1 + 1) = 2 -> 0 * 3 = 0.
Proof. intros H. reflexivity. Qed.
(** We can see that the proof term for the above lemma is indeed a
function: *)
Print silly_implication.
(* ===> silly_implication = fun _ : 1 + 1 = 2 => eq_refl
: 1 + 1 = 2 -> 0 * 3 = 0 *)
(** ** Defining Propositions *)
(** Just as we can create user-defined inductive types (like the
lists, binary representations of natural numbers, etc., that we
seen before), we can also create _user-defined_ propositions.
Question: How do you define the meaning of a proposition?
*)
(** *** *)
(** The meaning of a proposition is given by _rules_ and _definitions_
that say how to construct _evidence_ for the truth of the
proposition from other evidence.
- Typically, rules are defined _inductively_, just like any other datatype.
- Sometimes a proposition is declared to be true without substantiating evidence. Such propositions are called _axioms_.
In this, and subsequence chapters, we'll see more about how these
proof terms work in more detail.
*)
(* ########################################################### *)
(** * Conjunction (Logical "and") *)
(** The logical conjunction of propositions [P] and [Q] can be
represented using an [Inductive] definition with one
constructor. *)
Inductive and (P Q : Prop) : Prop :=
conj : P -> Q -> (and P Q).
(** The intuition behind this definition is simple: to
construct evidence for [and P Q], we must provide evidence
for [P] and evidence for [Q]. More precisely:
- [conj p q] can be taken as evidence for [and P Q] if [p]
is evidence for [P] and [q] is evidence for [Q]; and
- this is the _only_ way to give evidence for [and P Q] --
that is, if someone gives us evidence for [and P Q], we
know it must have the form [conj p q], where [p] is
evidence for [P] and [q] is evidence for [Q].
Since we'll be using conjunction a lot, let's introduce a more
familiar-looking infix notation for it. *)
Notation "P /\ Q" := (and P Q) : type_scope.
(** (The [type_scope] annotation tells Coq that this notation
will be appearing in propositions, not values.) *)
(** Consider the "type" of the constructor [conj]: *)
Check conj.
(* ===> forall P Q : Prop, P -> Q -> P /\ Q *)
(** Notice that it takes 4 inputs -- namely the propositions [P]
and [Q] and evidence for [P] and [Q] -- and returns as output the
evidence of [P /\ Q]. *)
(** ** "Introducing" Conjuctions *)
(** Besides the elegance of building everything up from a tiny
foundation, what's nice about defining conjunction this way is
that we can prove statements involving conjunction using the
tactics that we already know. For example, if the goal statement
is a conjuction, we can prove it by applying the single
constructor [conj], which (as can be seen from the type of [conj])
solves the current goal and leaves the two parts of the
conjunction as subgoals to be proved separately. *)
Theorem and_example :
(0 = 0) /\ (4 = mult 2 2).
Proof.
apply conj.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** Just for convenience, we can use the tactic [split] as a shorthand for
[apply conj]. *)
Theorem and_example' :
(0 = 0) /\ (4 = mult 2 2).
Proof.
split.
Case "left". reflexivity.
Case "right". reflexivity. Qed.
(** ** "Eliminating" conjunctions *)
(** Conversely, the [inversion] tactic can be used to take a
conjunction hypothesis in the context, calculate what evidence
must have been used to build it, and add variables representing
this evidence to the proof context. *)
Theorem proj1 : forall P Q : Prop,
P /\ Q -> P.
Proof.
intros P Q H.
inversion H as [HP HQ].
apply HP. Qed.
(** **** Exercise: 1 star, optional (proj2) *)
Theorem proj2 : forall P Q : Prop,
P /\ Q -> Q.
Proof.
intros P Q H.
inversion H. apply H1. Qed.
(** [] *)
Theorem and_commut : forall P Q : Prop,
P /\ Q -> Q /\ P.
Proof.
intros P Q H.
inversion H as [HP HQ].
split.
Case "left". apply HQ.
Case "right". apply HP. Qed.
(** **** Exercise: 2 stars (and_assoc) *)
(** In the following proof, notice how the _nested pattern_ in the
[inversion] breaks the hypothesis [H : P /\ (Q /\ R)] down into
[HP: P], [HQ : Q], and [HR : R]. Finish the proof from there: *)
Theorem and_assoc : forall P Q R : Prop,
P /\ (Q /\ R) -> (P /\ Q) /\ R.
Proof.
intros P Q R H.
inversion H as [HP [HQ HR]].
repeat (split; try (assumption)). Qed.
(** [] *)
(* ###################################################### *)
(** * Iff *)
(** The handy "if and only if" connective is just the conjunction of
two implications. *)
Definition iff (P Q : Prop) := (P -> Q) /\ (Q -> P).
Notation "P <-> Q" := (iff P Q)
(at level 95, no associativity)
: type_scope.
Theorem iff_implies : forall P Q : Prop,
(P <-> Q) -> P -> Q.
Proof.
intros P Q H.
inversion H as [HAB HBA]. apply HAB. Qed.
Theorem iff_sym : forall P Q : Prop,
(P <-> Q) -> (Q <-> P).
Proof.
(* WORKED IN CLASS *)
intros P Q H.
inversion H as [HAB HBA].
split.
Case "->". apply HBA.
Case "<-". apply HAB. Qed.
(** **** Exercise: 1 star, optional (iff_properties) *)
(** Using the above proof that [<->] is symmetric ([iff_sym]) as
a guide, prove that it is also reflexive and transitive. *)
Theorem iff_refl : forall P : Prop,
P <-> P.
Proof.
intros P.
unfold iff.
split; intros H; apply H. Qed.
Theorem iff_trans : forall P Q R : Prop,
(P <-> Q) -> (Q <-> R) -> (P <-> R).
Proof.
unfold iff.
intros P Q R H1 H2.
inversion H1 as [PQ QP]. inversion H2 as [QR RQ].
split; intros H.
Case "left". apply QR. apply PQ. apply H.
Case "right". apply QP. apply RQ. apply H.
Qed.
(** Hint: If you have an iff hypothesis in the context, you can use
[inversion] to break it into two separate implications. (Think
about why this works.) *)
(** [] *)
(** Some of Coq's tactics treat [iff] statements specially, thus
avoiding the need for some low-level manipulation when reasoning
with them. In particular, [rewrite] can be used with [iff]
statements, not just equalities. *)
(* ############################################################ *)
(** * Disjunction (Logical "or") *)
(** ** Implementing Disjunction *)
(** Disjunction ("logical or") can also be defined as an
inductive proposition. *)
Inductive or (P Q : Prop) : Prop :=
| or_introl : P -> or P Q
| or_intror : Q -> or P Q.
Notation "P \/ Q" := (or P Q) : type_scope.
(** Consider the "type" of the constructor [or_introl]: *)
Check or_introl.
(* ===> forall P Q : Prop, P -> P \/ Q *)
(** It takes 3 inputs, namely the propositions [P], [Q] and
evidence of [P], and returns, as output, the evidence of [P \/ Q].
Next, look at the type of [or_intror]: *)
Check or_intror.
(* ===> forall P Q : Prop, Q -> P \/ Q *)
(** It is like [or_introl] but it requires evidence of [Q]
instead of evidence of [P]. *)
(** Intuitively, there are two ways of giving evidence for [P \/ Q]:
- give evidence for [P] (and say that it is [P] you are giving
evidence for -- this is the function of the [or_introl]
constructor), or
- give evidence for [Q], tagged with the [or_intror]
constructor. *)
(** *** *)
(** Since [P \/ Q] has two constructors, doing [inversion] on a
hypothesis of type [P \/ Q] yields two subgoals. *)
Theorem or_commut : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". apply or_intror. apply HP.
Case "right". apply or_introl. apply HQ. Qed.
(** From here on, we'll use the shorthand tactics [left] and [right]
in place of [apply or_introl] and [apply or_intror]. *)
Theorem or_commut' : forall P Q : Prop,
P \/ Q -> Q \/ P.
Proof.
intros P Q H.
inversion H as [HP | HQ].
Case "left". right. apply HP.
Case "right". left. apply HQ. Qed.
Theorem or_distributes_over_and_1 : forall P Q R : Prop,
P \/ (Q /\ R) -> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. intros H. inversion H as [HP | [HQ HR]].
Case "left". split.
SCase "left". left. apply HP.
SCase "right". left. apply HP.
Case "right". split.
SCase "left". right. apply HQ.
SCase "right". right. apply HR. Qed.
(** **** Exercise: 2 stars (or_distributes_over_and_2) *)
Theorem or_distributes_over_and_2 : forall P Q R : Prop,
(P \/ Q) /\ (P \/ R) -> P \/ (Q /\ R).
Proof.
intros P Q R H.
inversion H as [[HP | HQ] [HPP | HR]];
repeat (try (left; assumption)).
right. split; assumption.
Qed.
(** [] *)
(** **** Exercise: 1 star, optional (or_distributes_over_and) *)
Theorem or_distributes_over_and : forall P Q R : Prop,
P \/ (Q /\ R) <-> (P \/ Q) /\ (P \/ R).
Proof.
intros P Q R. unfold iff.
split.
Case "left". apply or_distributes_over_and_1.
Case "right". apply or_distributes_over_and_2.
Qed.
(** [] *)
(* ################################################### *)
(** ** Relating [/\] and [\/] with [andb] and [orb] (advanced) *)
(** We've already seen several places where analogous structures
can be found in Coq's computational ([Type]) and logical ([Prop])
worlds. Here is one more: the boolean operators [andb] and [orb]
are clearly analogs of the logical connectives [/\] and [\/].
This analogy can be made more precise by the following theorems,
which show how to translate knowledge about [andb] and [orb]'s
behaviors on certain inputs into propositional facts about those
inputs. *)
Theorem andb_prop : forall b c,
andb b c = true -> b = true /\ c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
destruct b.
Case "b = true". destruct c.
SCase "c = true". apply conj. reflexivity. reflexivity.
SCase "c = false". inversion H.
Case "b = false". inversion H. Qed.
Theorem andb_true_intro : forall b c,
b = true /\ c = true -> andb b c = true.
Proof.
(* WORKED IN CLASS *)
intros b c H.
inversion H.
rewrite H0. rewrite H1. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (bool_prop) *)
Theorem andb_false : forall b c,
andb b c = false -> b = false \/ c = false.
Proof.
intros b c H.
destruct b, c; try (left; reflexivity); try (right; reflexivity).
Case "tt". inversion H. (* contra *)
Qed.
Theorem orb_prop : forall b c,
orb b c = true -> b = true \/ c = true.
Proof.
intros b c H.
destruct b, c; try (left; reflexivity); try (right; reflexivity).
Case "ff". inversion H.
Qed.
Theorem orb_false_elim : forall b c,
orb b c = false -> b = false /\ c = false.
Proof.
intros b c H.
destruct b, c; inversion H.
Case "ff". split; reflexivity.
Qed.
(** [] *)
(* ################################################### *)
(** * Falsehood *)
(** Logical falsehood can be represented in Coq as an inductively
defined proposition with no constructors. *)
Inductive False : Prop := .
(** Intuition: [False] is a proposition for which there is no way
to give evidence. *)
(** Since [False] has no constructors, inverting an assumption
of type [False] always yields zero subgoals, allowing us to
immediately prove any goal. *)
Theorem False_implies_nonsense :
False -> 2 + 2 = 5.
Proof.
intros contra.
inversion contra. Qed.
(** How does this work? The [inversion] tactic breaks [contra] into
each of its possible cases, and yields a subgoal for each case.
As [contra] is evidence for [False], it has _no_ possible cases,
hence, there are no possible subgoals and the proof is done. *)
(** *** *)
(** Conversely, the only way to prove [False] is if there is already
something nonsensical or contradictory in the context: *)
Theorem nonsense_implies_False :
2 + 2 = 5 -> False.
Proof.
intros contra.
inversion contra. Qed.
(** Actually, since the proof of [False_implies_nonsense]
doesn't actually have anything to do with the specific nonsensical
thing being proved; it can easily be generalized to work for an
arbitrary [P]: *)
Theorem ex_falso_quodlibet : forall (P:Prop),
False -> P.
Proof.
(* WORKED IN CLASS *)
intros P contra.
inversion contra. Qed.
(** The Latin _ex falso quodlibet_ means, literally, "from
falsehood follows whatever you please." This theorem is also
known as the _principle of explosion_. *)
(* #################################################### *)
(** ** Truth *)
(** Since we have defined falsehood in Coq, one might wonder whether
it is possible to define truth in the same way. We can. *)
(** **** Exercise: 2 stars, advanced (True) *)
(** Define [True] as another inductively defined proposition. (The
intution is that [True] should be a proposition for which it is
trivial to give evidence.) *)
Inductive True : Prop := True_.
(** [] *)
(** However, unlike [False], which we'll use extensively, [True] is
used fairly rarely. By itself, it is trivial (and therefore
uninteresting) to prove as a goal, and it carries no useful
information as a hypothesis. But it can be useful when defining
complex [Prop]s using conditionals, or as a parameter to
higher-order [Prop]s. *)
(* #################################################### *)
(** * Negation *)
(** The logical complement of a proposition [P] is written [not
P] or, for shorthand, [~P]: *)
Definition not (P:Prop) := P -> False.
(** The intuition is that, if [P] is not true, then anything at
all (even [False]) follows from assuming [P]. *)
Notation "~ x" := (not x) : type_scope.
Check not.
(* ===> Prop -> Prop *)
(** It takes a little practice to get used to working with
negation in Coq. Even though you can see perfectly well why
something is true, it can be a little hard at first to get things
into the right configuration so that Coq can see it! Here are
proofs of a few familiar facts about negation to get you warmed
up. *)
Theorem not_False :
~ False.
Proof.
unfold not. intros H. inversion H. Qed.
(** *** *)
Theorem contradiction_implies_anything : forall P Q : Prop,
(P /\ ~P) -> Q.
Proof.
(* WORKED IN CLASS *)
intros P Q H. inversion H as [HP HNA]. unfold not in HNA.
apply HNA in HP. inversion HP. Qed.
Theorem double_neg : forall P : Prop,
P -> ~~P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not. intros G. apply G. apply H. Qed.
(** **** Exercise: 2 stars, advanced (double_neg_inf) *)
(** Write an informal proof of [double_neg]:
_Theorem_: [P] implies [~~P], for any proposition [P].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 2 stars (contrapositive) *)
Theorem contrapositive : forall P Q : Prop,
(P -> Q) -> (~Q -> ~P).
Proof.
intros P Q HPQ.
unfold not. intros HQ HP.
apply HQ. apply HPQ. apply HP.
Qed.
(** [] *)
(** **** Exercise: 1 star (not_both_true_and_false) *)
Theorem not_both_true_and_false : forall P : Prop,
~ (P /\ ~P).
Proof.
intros P. unfold not. intros H. inversion H.
apply H1. apply H0.
Qed.
(** [] *)
(** **** Exercise: 1 star, advanced (informal_not_PNP) *)
(** Write an informal proof (in English) of the proposition [forall P
: Prop, ~(P /\ ~P)]. *)
(* FILL IN HERE *)
(** [] *)
(** *** Constructive logic *)
(** Note that some theorems that are true in classical logic are _not_
provable in Coq's (constructive) logic. E.g., let's look at how
this proof gets stuck... *)
Theorem classic_double_neg : forall P : Prop,
~~P -> P.
Proof.
(* WORKED IN CLASS *)
intros P H. unfold not in H.
(* But now what? There is no way to "invent" evidence for [~P]
from evidence for [P]. *)
Abort.
(** **** Exercise: 5 stars, advanced, optional (classical_axioms) *)
(** For those who like a challenge, here is an exercise
taken from the Coq'Art book (p. 123). The following five
statements are often considered as characterizations of
classical logic (as opposed to constructive logic, which is
what is "built in" to Coq). We can't prove them in Coq, but
we can consistently add any one of them as an unproven axiom
if we wish to work in classical logic. Prove that these five
propositions are equivalent. *)
Definition peirce := forall P Q: Prop,
((P->Q)->P)->P.
Definition classic := forall P:Prop,
~~P -> P.
Definition excluded_middle := forall P:Prop,
P \/ ~P.
Definition de_morgan_not_and_not := forall P Q:Prop,
~(~P /\ ~Q) -> P\/Q.
Definition implies_to_or := forall P Q:Prop,
(P->Q) -> (~P\/Q).
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars (excluded_middle_irrefutable) *)
(** This theorem implies that it is always safe to add a decidability
axiom (i.e. an instance of excluded middle) for any _particular_ Prop [P].
Why? Because we cannot prove the negation of such an axiom; if we could,
we would have both [~ (P \/ ~P)] and [~ ~ (P \/ ~P)], a contradiction. *)
Theorem excluded_middle_irrefutable: forall (P:Prop), ~ ~ (P \/ ~ P).
Proof.
intros P. unfold not. intros H. apply H. right. intros HP. apply H. left. apply HP.
Qed.
(* ########################################################## *)
(** ** Inequality *)
(** Saying [x <> y] is just the same as saying [~(x = y)]. *)
Notation "x <> y" := (~ (x = y)) : type_scope.
(** Since inequality involves a negation, it again requires
a little practice to be able to work with it fluently. Here
is one very useful trick. If you are trying to prove a goal
that is nonsensical (e.g., the goal state is [false = true]),
apply the lemma [ex_falso_quodlibet] to change the goal to
[False]. This makes it easier to use assumptions of the form
[~P] that are available in the context -- in particular,
assumptions of the form [x<>y]. *)
Theorem not_false_then_true : forall b : bool,
b <> false -> b = true.
Proof.
intros b H. destruct b.
Case "b = true". reflexivity.
Case "b = false".
unfold not in H.
apply ex_falso_quodlibet.
apply H. reflexivity. Qed.
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** *** *)
(** **** Exercise: 2 stars (false_beq_nat) *)
Theorem false_beq_nat : forall n m : nat,
n <> m ->
beq_nat n m = false.
Proof.
induction n; intros m H; destruct m.
Case "n = 0".
SCase "m = 0". simpl. apply ex_falso_quodlibet. apply H. reflexivity.
SCase "m = Sm". reflexivity.
Case "n = Sn'".
SCase "m = 0". reflexivity.
SCase "m = Sm". simpl. apply IHn. unfold not. intros H1. apply H. rewrite H1. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (beq_nat_false) *)
Theorem beq_nat_false : forall n m,
beq_nat n m = false -> n <> m.
Proof.
unfold not.
induction n; destruct m; simpl; intros H0 H1; inversion H0; inversion H1.
Case "n=Sn,m=Sm". rewrite H3 in H2. rewrite <- beq_nat_refl in H2. inversion H2.
Qed.
(** [] *)
(* $Date: 2014-06-05 07:22:21 -0400 (Thu, 05 Jun 2014) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
`define SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V
/**
* lpflow_lsbuf_lh_isowell: Level-shift buffer, low-to-high, isolated
* well on input buffer, no taps,
* double-row-height cell.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell (
X,
A
);
// Module ports
output X;
input A;
// Name Output Other arguments
buf buf0 (X , A );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_LSBUF_LH_ISOWELL_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__FA_4_V
`define SKY130_FD_SC_HS__FA_4_V
/**
* fa: Full adder.
*
* Verilog wrapper for fa with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__fa.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN ,
VPWR,
VGND
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
input VPWR;
input VGND;
sky130_fd_sc_hs__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__fa_4 (
COUT,
SUM ,
A ,
B ,
CIN
);
output COUT;
output SUM ;
input A ;
input B ;
input CIN ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__fa base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.CIN(CIN)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__FA_4_V
|
module ereset (/*AUTOARG*/
// Outputs
reset, chip_resetb,
// Inputs
hard_reset, soft_reset
);
//inputs
input hard_reset; // hardware reset from external block
input soft_reset; // soft reset drive by register (level)
//outputs
output reset; //reset for elink
output chip_resetb; //reset for epiphany
//Reset for link logic
assign reset = hard_reset | soft_reset;
//May become more sophisticated later..
//(for example, for epiphany reset, you might want to include some
//some hard coded logic to avoid reset edge errata)
//also, for multi chip boards, since the coordinates are sampled on
//the rising edge of chip_resetb it may be beneficial to have one
//reset per chip and to stagger the
assign chip_resetb = ~(hard_reset | soft_reset);
endmodule // ereset
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <[email protected]>
Contributed by Fred Huettig <[email protected]>
Contributed by Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__FAH_BEHAVIORAL_V
`define SKY130_FD_SC_LS__FAH_BEHAVIORAL_V
/**
* fah: Full adder.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__fah (
COUT,
SUM ,
A ,
B ,
CI
);
// Module ports
output COUT;
output SUM ;
input A ;
input B ;
input CI ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire xor0_out_SUM;
wire a_b ;
wire a_ci ;
wire b_ci ;
wire or0_out_COUT;
// Name Output Other arguments
xor xor0 (xor0_out_SUM, A, B, CI );
buf buf0 (SUM , xor0_out_SUM );
and and0 (a_b , A, B );
and and1 (a_ci , A, CI );
and and2 (b_ci , B, CI );
or or0 (or0_out_COUT, a_b, a_ci, b_ci);
buf buf1 (COUT , or0_out_COUT );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__FAH_BEHAVIORAL_V |
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
// Date : Tue Oct 17 19:49:29 2017
// Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_rst_ps7_0_100M_0_sim_netlist.v
// Design : ip_design_rst_ps7_0_100M_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync
(lpf_asr_reg,
scndry_out,
lpf_asr,
asr_lpf,
p_1_in,
p_2_in,
aux_reset_in,
slowest_sync_clk);
output lpf_asr_reg;
output scndry_out;
input lpf_asr;
input [0:0]asr_lpf;
input p_1_in;
input p_2_in;
input aux_reset_in;
input slowest_sync_clk;
wire asr_d1;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire lpf_asr;
wire lpf_asr_reg;
wire p_1_in;
wire p_2_in;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(asr_d1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT1 #(
.INIT(2'h1))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1
(.I0(aux_reset_in),
.O(asr_d1));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_asr_i_1
(.I0(lpf_asr),
.I1(asr_lpf),
.I2(scndry_out),
.I3(p_1_in),
.I4(p_2_in),
.O(lpf_asr_reg));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0
(lpf_exr_reg,
scndry_out,
lpf_exr,
p_3_out,
mb_debug_sys_rst,
ext_reset_in,
slowest_sync_clk);
output lpf_exr_reg;
output scndry_out;
input lpf_exr;
input [2:0]p_3_out;
input mb_debug_sys_rst;
input ext_reset_in;
input slowest_sync_clk;
wire \GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ;
wire ext_reset_in;
wire lpf_exr;
wire lpf_exr_reg;
wire mb_debug_sys_rst;
wire [2:0]p_3_out;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
wire scndry_out;
wire slowest_sync_clk;
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0
(.I0(mb_debug_sys_rst),
.I1(ext_reset_in),
.O(\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to_i_1__0_n_0 ));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* XILINX_LEGACY_PRIM = "FDR" *)
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(slowest_sync_clk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(scndry_out),
.R(1'b0));
LUT5 #(
.INIT(32'hEAAAAAA8))
lpf_exr_i_1
(.I0(lpf_exr),
.I1(p_3_out[0]),
.I2(scndry_out),
.I3(p_3_out[1]),
.I4(p_3_out[2]),
.O(lpf_exr_reg));
endmodule
(* CHECK_LICENSE_TYPE = "ip_design_rst_ps7_0_100M_0,proc_sys_reset,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "proc_sys_reset,Vivado 2017.3" *)
(* NotValidForBitStream *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
(* x_interface_info = "xilinx.com:signal:clock:1.0 clock CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME clock, ASSOCIATED_RESET mb_reset:bus_struct_reset:interconnect_aresetn:peripheral_aresetn:peripheral_reset, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN ip_design_processing_system7_0_0_FCLK_CLK0" *) input slowest_sync_clk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 ext_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME ext_reset, BOARD.ASSOCIATED_PARAM RESET_BOARD_INTERFACE, POLARITY ACTIVE_LOW" *) input ext_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 aux_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME aux_reset, POLARITY ACTIVE_LOW" *) input aux_reset_in;
(* x_interface_info = "xilinx.com:signal:reset:1.0 dbg_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME dbg_reset, POLARITY ACTIVE_HIGH" *) input mb_debug_sys_rst;
input dcm_locked;
(* x_interface_info = "xilinx.com:signal:reset:1.0 mb_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME mb_rst, POLARITY ACTIVE_HIGH, TYPE PROCESSOR" *) output mb_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 bus_struct_reset RST" *) (* x_interface_parameter = "XIL_INTERFACENAME bus_struct_reset, POLARITY ACTIVE_HIGH, TYPE INTERCONNECT" *) output [0:0]bus_struct_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_high_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_high_rst, POLARITY ACTIVE_HIGH, TYPE PERIPHERAL" *) output [0:0]peripheral_reset;
(* x_interface_info = "xilinx.com:signal:reset:1.0 interconnect_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME interconnect_low_rst, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) output [0:0]interconnect_aresetn;
(* x_interface_info = "xilinx.com:signal:reset:1.0 peripheral_low_rst RST" *) (* x_interface_parameter = "XIL_INTERFACENAME peripheral_low_rst, POLARITY ACTIVE_LOW, TYPE PERIPHERAL" *) output [0:0]peripheral_aresetn;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* C_AUX_RESET_HIGH = "1'b0" *)
(* C_AUX_RST_WIDTH = "4" *)
(* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *)
(* C_FAMILY = "zynq" *)
(* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *)
(* C_NUM_PERP_ARESETN = "1" *)
(* C_NUM_PERP_RST = "1" *)
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset U0
(.aux_reset_in(aux_reset_in),
.bus_struct_reset(bus_struct_reset),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.interconnect_aresetn(interconnect_aresetn),
.mb_debug_sys_rst(mb_debug_sys_rst),
.mb_reset(mb_reset),
.peripheral_aresetn(peripheral_aresetn),
.peripheral_reset(peripheral_reset),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf
(lpf_int,
slowest_sync_clk,
dcm_locked,
aux_reset_in,
mb_debug_sys_rst,
ext_reset_in);
output lpf_int;
input slowest_sync_clk;
input dcm_locked;
input aux_reset_in;
input mb_debug_sys_rst;
input ext_reset_in;
wire \ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ;
wire \ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ;
wire Q;
wire [0:0]asr_lpf;
wire aux_reset_in;
wire dcm_locked;
wire ext_reset_in;
wire lpf_asr;
wire lpf_exr;
wire lpf_int;
wire lpf_int0__0;
wire mb_debug_sys_rst;
wire p_1_in;
wire p_2_in;
wire p_3_in1_in;
wire [3:0]p_3_out;
wire slowest_sync_clk;
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync \ACTIVE_LOW_AUX.ACT_LO_AUX
(.asr_lpf(asr_lpf),
.aux_reset_in(aux_reset_in),
.lpf_asr(lpf_asr),
.lpf_asr_reg(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.p_1_in(p_1_in),
.p_2_in(p_2_in),
.scndry_out(p_3_in1_in),
.slowest_sync_clk(slowest_sync_clk));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_cdc_sync_0 \ACTIVE_LOW_EXT.ACT_LO_EXT
(.ext_reset_in(ext_reset_in),
.lpf_exr(lpf_exr),
.lpf_exr_reg(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.mb_debug_sys_rst(mb_debug_sys_rst),
.p_3_out(p_3_out[2:0]),
.scndry_out(p_3_out[3]),
.slowest_sync_clk(slowest_sync_clk));
FDRE #(
.INIT(1'b0))
\AUX_LPF[1].asr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_in1_in),
.Q(p_2_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[2].asr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_2_in),
.Q(p_1_in),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\AUX_LPF[3].asr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_1_in),
.Q(asr_lpf),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[1].exr_lpf_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[3]),
.Q(p_3_out[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[2].exr_lpf_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(p_3_out[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\EXT_LPF[3].exr_lpf_reg[3]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[1]),
.Q(p_3_out[0]),
.R(1'b0));
(* XILINX_LEGACY_PRIM = "SRL16" *)
(* box_type = "PRIMITIVE" *)
(* srl_name = "U0/\EXT_LPF/POR_SRL_I " *)
SRL16E #(
.INIT(16'hFFFF))
POR_SRL_I
(.A0(1'b1),
.A1(1'b1),
.A2(1'b1),
.A3(1'b1),
.CE(1'b1),
.CLK(slowest_sync_clk),
.D(1'b0),
.Q(Q));
FDRE #(
.INIT(1'b0))
lpf_asr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_AUX.ACT_LO_AUX_n_0 ),
.Q(lpf_asr),
.R(1'b0));
FDRE #(
.INIT(1'b0))
lpf_exr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\ACTIVE_LOW_EXT.ACT_LO_EXT_n_0 ),
.Q(lpf_exr),
.R(1'b0));
LUT4 #(
.INIT(16'hFFEF))
lpf_int0
(.I0(Q),
.I1(lpf_asr),
.I2(dcm_locked),
.I3(lpf_exr),
.O(lpf_int0__0));
FDRE #(
.INIT(1'b0))
lpf_int_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(lpf_int0__0),
.Q(lpf_int),
.R(1'b0));
endmodule
(* C_AUX_RESET_HIGH = "1'b0" *) (* C_AUX_RST_WIDTH = "4" *) (* C_EXT_RESET_HIGH = "1'b0" *)
(* C_EXT_RST_WIDTH = "4" *) (* C_FAMILY = "zynq" *) (* C_NUM_BUS_RST = "1" *)
(* C_NUM_INTERCONNECT_ARESETN = "1" *) (* C_NUM_PERP_ARESETN = "1" *) (* C_NUM_PERP_RST = "1" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_proc_sys_reset
(slowest_sync_clk,
ext_reset_in,
aux_reset_in,
mb_debug_sys_rst,
dcm_locked,
mb_reset,
bus_struct_reset,
peripheral_reset,
interconnect_aresetn,
peripheral_aresetn);
input slowest_sync_clk;
input ext_reset_in;
input aux_reset_in;
input mb_debug_sys_rst;
input dcm_locked;
output mb_reset;
(* equivalent_register_removal = "no" *) output [0:0]bus_struct_reset;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_reset;
(* equivalent_register_removal = "no" *) output [0:0]interconnect_aresetn;
(* equivalent_register_removal = "no" *) output [0:0]peripheral_aresetn;
wire Bsr_out;
wire MB_out;
wire Pr_out;
wire SEQ_n_3;
wire SEQ_n_4;
wire aux_reset_in;
wire [0:0]bus_struct_reset;
wire dcm_locked;
wire ext_reset_in;
wire [0:0]interconnect_aresetn;
wire lpf_int;
wire mb_debug_sys_rst;
wire mb_reset;
wire [0:0]peripheral_aresetn;
wire [0:0]peripheral_reset;
wire slowest_sync_clk;
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_3),
.Q(interconnect_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N
(.C(slowest_sync_clk),
.CE(1'b1),
.D(SEQ_n_4),
.Q(peripheral_aresetn),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\BSR_OUT_DFF[0].FDRE_BSR
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Bsr_out),
.Q(bus_struct_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_lpf EXT_LPF
(.aux_reset_in(aux_reset_in),
.dcm_locked(dcm_locked),
.ext_reset_in(ext_reset_in),
.lpf_int(lpf_int),
.mb_debug_sys_rst(mb_debug_sys_rst),
.slowest_sync_clk(slowest_sync_clk));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
FDRE_inst
(.C(slowest_sync_clk),
.CE(1'b1),
.D(MB_out),
.Q(mb_reset),
.R(1'b0));
(* box_type = "PRIMITIVE" *)
FDRE #(
.INIT(1'b1),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\PR_OUT_DFF[0].FDRE_PER
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Pr_out),
.Q(peripheral_reset),
.R(1'b0));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr SEQ
(.\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N (SEQ_n_3),
.\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N (SEQ_n_4),
.Bsr_out(Bsr_out),
.MB_out(MB_out),
.Pr_out(Pr_out),
.lpf_int(lpf_int),
.slowest_sync_clk(slowest_sync_clk));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_sequence_psr
(MB_out,
Bsr_out,
Pr_out,
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ,
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ,
lpf_int,
slowest_sync_clk);
output MB_out;
output Bsr_out;
output Pr_out;
output \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
output \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
input lpf_int;
input slowest_sync_clk;
wire \ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ;
wire \ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ;
wire Bsr_out;
wire Core_i_1_n_0;
wire MB_out;
wire Pr_out;
wire \bsr_dec_reg_n_0_[0] ;
wire \bsr_dec_reg_n_0_[2] ;
wire bsr_i_1_n_0;
wire \core_dec[0]_i_1_n_0 ;
wire \core_dec[2]_i_1_n_0 ;
wire \core_dec_reg_n_0_[0] ;
wire \core_dec_reg_n_0_[1] ;
wire from_sys_i_1_n_0;
wire lpf_int;
wire p_0_in;
wire [2:0]p_3_out;
wire [2:0]p_5_out;
wire pr_dec0__0;
wire \pr_dec_reg_n_0_[0] ;
wire \pr_dec_reg_n_0_[2] ;
wire pr_i_1_n_0;
wire seq_clr;
wire [5:0]seq_cnt;
wire seq_cnt_en;
wire slowest_sync_clk;
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N_i_1
(.I0(Bsr_out),
.O(\ACTIVE_LOW_BSR_OUT_DFF[0].FDRE_BSR_N ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT1 #(
.INIT(2'h1))
\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N_i_1
(.I0(Pr_out),
.O(\ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
Core_i_1
(.I0(MB_out),
.I1(p_0_in),
.O(Core_i_1_n_0));
FDSE #(
.INIT(1'b1))
Core_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(Core_i_1_n_0),
.Q(MB_out),
.S(lpf_int));
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n SEQ_COUNTER
(.Q(seq_cnt),
.seq_clr(seq_clr),
.seq_cnt_en(seq_cnt_en),
.slowest_sync_clk(slowest_sync_clk));
LUT4 #(
.INIT(16'h0804))
\bsr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt[4]),
.O(p_5_out[0]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\bsr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\bsr_dec_reg_n_0_[0] ),
.O(p_5_out[2]));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[0]),
.Q(\bsr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\bsr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_5_out[2]),
.Q(\bsr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h2))
bsr_i_1
(.I0(Bsr_out),
.I1(\bsr_dec_reg_n_0_[2] ),
.O(bsr_i_1_n_0));
FDSE #(
.INIT(1'b1))
bsr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(bsr_i_1_n_0),
.Q(Bsr_out),
.S(lpf_int));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h8040))
\core_dec[0]_i_1
(.I0(seq_cnt[4]),
.I1(seq_cnt[3]),
.I2(seq_cnt[5]),
.I3(seq_cnt_en),
.O(\core_dec[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h8))
\core_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\core_dec_reg_n_0_[0] ),
.O(\core_dec[2]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\core_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[0]_i_1_n_0 ),
.Q(\core_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[1]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_dec0__0),
.Q(\core_dec_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\core_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(\core_dec[2]_i_1_n_0 ),
.Q(p_0_in),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
from_sys_i_1
(.I0(MB_out),
.I1(seq_cnt_en),
.O(from_sys_i_1_n_0));
FDSE #(
.INIT(1'b0))
from_sys_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(from_sys_i_1_n_0),
.Q(seq_cnt_en),
.S(lpf_int));
LUT4 #(
.INIT(16'h0210))
pr_dec0
(.I0(seq_cnt[0]),
.I1(seq_cnt[1]),
.I2(seq_cnt[2]),
.I3(seq_cnt_en),
.O(pr_dec0__0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h1080))
\pr_dec[0]_i_1
(.I0(seq_cnt_en),
.I1(seq_cnt[5]),
.I2(seq_cnt[3]),
.I3(seq_cnt[4]),
.O(p_3_out[0]));
LUT2 #(
.INIT(4'h8))
\pr_dec[2]_i_1
(.I0(\core_dec_reg_n_0_[1] ),
.I1(\pr_dec_reg_n_0_[0] ),
.O(p_3_out[2]));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[0]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[0]),
.Q(\pr_dec_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\pr_dec_reg[2]
(.C(slowest_sync_clk),
.CE(1'b1),
.D(p_3_out[2]),
.Q(\pr_dec_reg_n_0_[2] ),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
pr_i_1
(.I0(Pr_out),
.I1(\pr_dec_reg_n_0_[2] ),
.O(pr_i_1_n_0));
FDSE #(
.INIT(1'b1))
pr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(pr_i_1_n_0),
.Q(Pr_out),
.S(lpf_int));
FDRE #(
.INIT(1'b0))
seq_clr_reg
(.C(slowest_sync_clk),
.CE(1'b1),
.D(1'b1),
.Q(seq_clr),
.R(lpf_int));
endmodule
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_upcnt_n
(Q,
seq_clr,
seq_cnt_en,
slowest_sync_clk);
output [5:0]Q;
input seq_clr;
input seq_cnt_en;
input slowest_sync_clk;
wire [5:0]Q;
wire clear;
wire [5:0]q_int0;
wire seq_clr;
wire seq_cnt_en;
wire slowest_sync_clk;
LUT1 #(
.INIT(2'h1))
\q_int[0]_i_1
(.I0(Q[0]),
.O(q_int0[0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h6))
\q_int[1]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.O(q_int0[1]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h78))
\q_int[2]_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(Q[2]),
.O(q_int0[2]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h7F80))
\q_int[3]_i_1
(.I0(Q[1]),
.I1(Q[0]),
.I2(Q[2]),
.I3(Q[3]),
.O(q_int0[3]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h7FFF8000))
\q_int[4]_i_1
(.I0(Q[2]),
.I1(Q[0]),
.I2(Q[1]),
.I3(Q[3]),
.I4(Q[4]),
.O(q_int0[4]));
LUT1 #(
.INIT(2'h1))
\q_int[5]_i_1
(.I0(seq_clr),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\q_int[5]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[0]),
.I3(Q[2]),
.I4(Q[4]),
.I5(Q[5]),
.O(q_int0[5]));
FDRE #(
.INIT(1'b1))
\q_int_reg[0]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[0]),
.Q(Q[0]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[1]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[1]),
.Q(Q[1]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[2]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[2]),
.Q(Q[2]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[3]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[3]),
.Q(Q[3]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[4]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[4]),
.Q(Q[4]),
.R(clear));
FDRE #(
.INIT(1'b1))
\q_int_reg[5]
(.C(slowest_sync_clk),
.CE(seq_cnt_en),
.D(q_int0[5]),
.Q(Q[5]),
.R(clear));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
`define SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V
/**
* sedfxtp: Scan delay flop, data enable, non-inverted clock,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_mux_2to1/sky130_fd_sc_hd__udp_mux_2to1.v"
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_hd__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__sedfxtp (
Q ,
CLK,
D ,
DE ,
SCD,
SCE
);
// Module ports
output Q ;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire DE_delayed ;
wire SCD_delayed;
wire SCE_delayed;
wire CLK_delayed;
wire mux_out ;
wire de_d ;
wire awake ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
// Name Output Other arguments
sky130_fd_sc_hd__udp_mux_2to1 mux_2to10 (mux_out, de_d, SCD_delayed, SCE_delayed );
sky130_fd_sc_hd__udp_mux_2to1 mux_2to11 (de_d , buf_Q, D_delayed, DE_delayed );
sky130_fd_sc_hd__udp_dff$P_pp$PG$N dff0 (buf_Q , mux_out, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond1 = ( awake && ( SCE_delayed === 1'b0 ) && ( DE_delayed === 1'b1 ) );
assign cond2 = ( awake && ( SCE_delayed === 1'b1 ) );
assign cond3 = ( awake && ( DE_delayed === 1'b1 ) && ( D_delayed !== SCD_delayed ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__SEDFXTP_BEHAVIORAL_V |
//------------------------------------------------------------------------------
//
// Copyright 2011, Benjamin Gelb. All Rights Reserved.
// See LICENSE file for copying permission.
//
//------------------------------------------------------------------------------
//
// Author: Ben Gelb ([email protected])
//
// Brief Description:
// Quick and dirty test harness for DVB-S encoder "core"
//
//------------------------------------------------------------------------------
`ifndef _ZL_DVB_S_CORE_TB_V_
`define _ZL_DVB_S_CORE_TB_V_
`timescale 1ns/1ps
module zl_dvb_s_core_tb ();
reg clk;
reg rst_n;
reg [7:0] data_in;
reg data_in_req;
wire data_in_ack;
initial begin
clk = 0;
forever clk = #10 ~clk;
end
integer infile;
integer outfile;
wire data_out_req;
wire data_out_i;
wire data_out_q;
initial begin
rst_n = 0;
data_in_req = 0;
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
rst_n = 1;
infile = $fopen("test.m2v","r");
data_in = $fgetc(infile);
while (!$feof(infile)) begin
data_in_req = 1'b1;
wait(data_in_ack && clk);
wait(data_in_ack && !clk);
data_in = $fgetc(infile);
end
data_in_req = 1'b0;
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(clk);
wait(!clk);
wait(!data_out_req);
wait(clk);
wait(!clk);
$fclose(infile);
$fclose(outfile);
$finish;
end
initial begin
wait(!rst_n);
wait(rst_n);
outfile = $fopen("out.bin", "w");
while(1) begin
wait(!clk);
wait(clk);
if(data_out_req) begin
$fwrite(outfile, "%c", data_out_i);
$fwrite(outfile, "%c", data_out_q);
end
end
end
zl_dvb_s_core uut
(
.clk(clk),
.rst_n(rst_n),
//
.data_in(data_in),
.data_in_req(data_in_req),
.data_in_ack(data_in_ack),
//
.data_out_i(data_out_i),
.data_out_q(data_out_q),
.data_out_req(data_out_req),
.data_out_ack(data_out_req)
);
endmodule // zl_dvb_s_core_tb
`endif // _ZL_DVB_S_CORE_TB_V_
|
/*
Copyright (c) 2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* 10G Ethernet PHY RX
*/
module eth_phy_10g_rx #
(
parameter DATA_WIDTH = 64,
parameter CTRL_WIDTH = (DATA_WIDTH/8),
parameter HDR_WIDTH = 2,
parameter BIT_REVERSE = 0,
parameter SCRAMBLER_DISABLE = 0,
parameter PRBS31_ENABLE = 0,
parameter SERDES_PIPELINE = 0,
parameter BITSLIP_HIGH_CYCLES = 1,
parameter BITSLIP_LOW_CYCLES = 8,
parameter COUNT_125US = 125000/6.4
)
(
input wire clk,
input wire rst,
/*
* XGMII interface
*/
output wire [DATA_WIDTH-1:0] xgmii_rxd,
output wire [CTRL_WIDTH-1:0] xgmii_rxc,
/*
* SERDES interface
*/
input wire [DATA_WIDTH-1:0] serdes_rx_data,
input wire [HDR_WIDTH-1:0] serdes_rx_hdr,
output wire serdes_rx_bitslip,
/*
* Status
*/
output wire [6:0] rx_error_count,
output wire rx_bad_block,
output wire rx_block_lock,
output wire rx_high_ber,
/*
* Configuration
*/
input wire rx_prbs31_enable
);
// bus width assertions
initial begin
if (DATA_WIDTH != 64) begin
$error("Error: Interface width must be 64");
$finish;
end
if (CTRL_WIDTH * 8 != DATA_WIDTH) begin
$error("Error: Interface requires byte (8-bit) granularity");
$finish;
end
if (HDR_WIDTH != 2) begin
$error("Error: HDR_WIDTH must be 2");
$finish;
end
end
wire [DATA_WIDTH-1:0] encoded_rx_data;
wire [HDR_WIDTH-1:0] encoded_rx_hdr;
eth_phy_10g_rx_if #(
.DATA_WIDTH(DATA_WIDTH),
.HDR_WIDTH(HDR_WIDTH),
.BIT_REVERSE(BIT_REVERSE),
.SCRAMBLER_DISABLE(SCRAMBLER_DISABLE),
.PRBS31_ENABLE(PRBS31_ENABLE),
.SERDES_PIPELINE(SERDES_PIPELINE),
.BITSLIP_HIGH_CYCLES(BITSLIP_HIGH_CYCLES),
.BITSLIP_LOW_CYCLES(BITSLIP_LOW_CYCLES),
.COUNT_125US(COUNT_125US)
)
eth_phy_10g_rx_if_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.serdes_rx_data(serdes_rx_data),
.serdes_rx_hdr(serdes_rx_hdr),
.serdes_rx_bitslip(serdes_rx_bitslip),
.rx_error_count(rx_error_count),
.rx_block_lock(rx_block_lock),
.rx_high_ber(rx_high_ber),
.rx_prbs31_enable(rx_prbs31_enable)
);
xgmii_baser_dec_64 #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.HDR_WIDTH(HDR_WIDTH)
)
xgmii_baser_dec_inst (
.clk(clk),
.rst(rst),
.encoded_rx_data(encoded_rx_data),
.encoded_rx_hdr(encoded_rx_hdr),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.rx_bad_block(rx_bad_block)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__O21BA_FUNCTIONAL_PP_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire nor1_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A1, A2 );
nor nor1 (nor1_out_X , B1_N, nor0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, nor1_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_FUNCTIONAL_PP_V |
module microblaze (clk, reset_, led);
input clk, reset_;
output [7:0] led;
wire reset;
wire [31:0] tr_instruction;
wire tr_valid_instruction;
wire [31:0] tr_pc;
wire tr_reg_write;
wire [4:0] tr_reg_addr;
wire [14:0] tr_msr_reg;
wire [31:0] tr_new_reg_val;
wire tr_jump_taken;
wire tr_delay_slot;
wire [31:0] tr_data_addr;
wire tr_data_access;
wire tr_data_read;
wire tr_data_write;
wire [31:0] tr_data_write_val;
wire [3:0] tr_data_byte_en;
wire tr_halted;
// Top-level circuit module that instantiates the MicroBlaze CPU but otherwise
// provides no logic.
// **GOTCHA** Reset on MCS is active high, not active low!
assign reset = ~reset_;
microblaze_mcs_v1_4 mcs_0 (
.Clk(clk), // input 32Mhz clk
.Reset(reset), // input **active high** reset
.GPO1(led), // output [7:0] GPO1
// Trace bus connections: for waveform debugging, only
.Trace_Instruction(tr_instruction),
.Trace_Valid_Instr(tr_valid_instruction),
.Trace_PC(tr_pc),
.Trace_Reg_Write(tr_reg_write),
.Trace_Reg_Addr(tr_reg_addr),
.Trace_MSR_Reg(tr_msr_reg),
.Trace_New_Reg_Value(tr_new_reg_val),
.Trace_Jump_Taken(tr_jump_taken),
.Trace_Delay_Slot(tr_delay_slot),
.Trace_Data_Address(tr_data_addr),
.Trace_Data_Access(tr_data_access),
.Trace_Data_Read(tr_data_read),
.Trace_Data_Write(tr_data_write),
.Trace_Data_Write_Value(tr_data_write_val),
.Trace_Data_Byte_Enable(tr_data_byte_en),
.Trace_MB_Halted(tr_halted)
);
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2015, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
`timescale 1ns/1ns
`include "trellis.vh"
`include "riffa.vh"
module riffa
#(
parameter C_PCI_DATA_WIDTH = 128,
parameter C_NUM_CHNL = 12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
parameter C_VENDOR = "ALTERA",
parameter C_FPGA_NAME = "FPGA",
parameter C_DEPTH_PACKETS = 10
)
(
input CLK,
input RST_IN,
output RST_OUT,
// Interface: RXC Engine
input [C_PCI_DATA_WIDTH-1:0] RXC_DATA,
input RXC_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE,
input RXC_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET,
input RXC_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET,
input [`SIG_LBE_W-1:0] RXC_META_LDWBE,
input [`SIG_FBE_W-1:0] RXC_META_FDWBE,
input [`SIG_TAG_W-1:0] RXC_META_TAG,
input [`SIG_LOWADDR_W-1:0] RXC_META_ADDR,
input [`SIG_TYPE_W-1:0] RXC_META_TYPE,
input [`SIG_LEN_W-1:0] RXC_META_LENGTH,
input [`SIG_BYTECNT_W-1:0] RXC_META_BYTES_REMAINING,
input [`SIG_CPLID_W-1:0] RXC_META_COMPLETER_ID,
input RXC_META_EP,
// Interface: RXR Engine
input [C_PCI_DATA_WIDTH-1:0] RXR_DATA,
input RXR_DATA_VALID,
input [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE,
input RXR_DATA_START_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET,
input RXR_DATA_END_FLAG,
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET,
input [`SIG_FBE_W-1:0] RXR_META_FDWBE,
input [`SIG_LBE_W-1:0] RXR_META_LDWBE,
input [`SIG_TC_W-1:0] RXR_META_TC,
input [`SIG_ATTR_W-1:0] RXR_META_ATTR,
input [`SIG_TAG_W-1:0] RXR_META_TAG,
input [`SIG_TYPE_W-1:0] RXR_META_TYPE,
input [`SIG_ADDR_W-1:0] RXR_META_ADDR,
input [`SIG_BARDECODE_W-1:0] RXR_META_BAR_DECODED,
input [`SIG_REQID_W-1:0] RXR_META_REQUESTER_ID,
input [`SIG_LEN_W-1:0] RXR_META_LENGTH,
input RXR_META_EP,
// Interface: TXC Engine
output [C_PCI_DATA_WIDTH-1:0] TXC_DATA,
output TXC_DATA_VALID,
output TXC_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET,
output TXC_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET,
input TXC_DATA_READY,
output TXC_META_VALID,
output [`SIG_FBE_W-1:0] TXC_META_FDWBE,
output [`SIG_LBE_W-1:0] TXC_META_LDWBE,
output [`SIG_LOWADDR_W-1:0] TXC_META_ADDR,
output [`SIG_TYPE_W-1:0] TXC_META_TYPE,
output [`SIG_LEN_W-1:0] TXC_META_LENGTH,
output [`SIG_BYTECNT_W-1:0] TXC_META_BYTE_COUNT,
output [`SIG_TAG_W-1:0] TXC_META_TAG,
output [`SIG_REQID_W-1:0] TXC_META_REQUESTER_ID,
output [`SIG_TC_W-1:0] TXC_META_TC,
output [`SIG_ATTR_W-1:0] TXC_META_ATTR,
output TXC_META_EP,
input TXC_META_READY,
input TXC_SENT,
// Interface: TXR Engine
output TXR_DATA_VALID,
output [C_PCI_DATA_WIDTH-1:0] TXR_DATA,
output TXR_DATA_START_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET,
output TXR_DATA_END_FLAG,
output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET,
input TXR_DATA_READY,
output TXR_META_VALID,
output [`SIG_FBE_W-1:0] TXR_META_FDWBE,
output [`SIG_LBE_W-1:0] TXR_META_LDWBE,
output [`SIG_ADDR_W-1:0] TXR_META_ADDR,
output [`SIG_LEN_W-1:0] TXR_META_LENGTH,
output [`SIG_TAG_W-1:0] TXR_META_TAG,
output [`SIG_TC_W-1:0] TXR_META_TC,
output [`SIG_ATTR_W-1:0] TXR_META_ATTR,
output [`SIG_TYPE_W-1:0] TXR_META_TYPE,
output TXR_META_EP,
input TXR_META_READY,
input TXR_SENT,
// Interface: Configuration
input [`SIG_CPLID_W-1:0] CONFIG_COMPLETER_ID,
input CONFIG_BUS_MASTER_ENABLE,
input [`SIG_LINKWIDTH_W-1:0] CONFIG_LINK_WIDTH,
input [`SIG_LINKRATE_W-1:0] CONFIG_LINK_RATE,
input [`SIG_MAXREAD_W-1:0] CONFIG_MAX_READ_REQUEST_SIZE,
input [`SIG_MAXPAYLOAD_W-1:0] CONFIG_MAX_PAYLOAD_SIZE,
input [`SIG_FC_CPLD_W-1:0] CONFIG_MAX_CPL_DATA, // Receive credit limit for data
input [`SIG_FC_CPLH_W-1:0] CONFIG_MAX_CPL_HDR, // Receive credit limit for headers
input CONFIG_INTERRUPT_MSIENABLE,
input CONFIG_CPL_BOUNDARY_SEL,
// Interrupt Request
input INTR_MSI_RDY, // High when interrupt is able to be sent
output INTR_MSI_REQUEST, // High to request interrupt, when both INTR_MSI_RDY and INTR_MSI_RE
input [C_NUM_CHNL-1:0] CHNL_RX_CLK,
output [C_NUM_CHNL-1:0] CHNL_RX,
input [C_NUM_CHNL-1:0] CHNL_RX_ACK,
output [C_NUM_CHNL-1:0] CHNL_RX_LAST,
output [(C_NUM_CHNL*32)-1:0] CHNL_RX_LEN,
output [(C_NUM_CHNL*31)-1:0] CHNL_RX_OFF,
output [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_RX_DATA,
output [C_NUM_CHNL-1:0] CHNL_RX_DATA_VALID,
input [C_NUM_CHNL-1:0] CHNL_RX_DATA_REN,
input [C_NUM_CHNL-1:0] CHNL_TX_CLK,
input [C_NUM_CHNL-1:0] CHNL_TX,
output [C_NUM_CHNL-1:0] CHNL_TX_ACK,
input [C_NUM_CHNL-1:0] CHNL_TX_LAST,
input [(C_NUM_CHNL*32)-1:0] CHNL_TX_LEN,
input [(C_NUM_CHNL*31)-1:0] CHNL_TX_OFF,
input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA,
input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID,
output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN
);
`include "functions.vh"
localparam C_MAX_READ_REQ = clog2s(C_MAX_READ_REQ_BYTES)-7; // Max read: 000=128B; 001=256B; 010=512B; 011=1024B; 100=2048B; 101=4096B
localparam C_NUM_CHNL_WIDTH = clog2s(C_NUM_CHNL);
localparam C_PCI_DATA_WORD_WIDTH = clog2s((C_PCI_DATA_WIDTH/32)+1);
localparam C_NUM_VECTORS = 2;
localparam C_VECTOR_WIDTH = 32;
// Interface: Reorder Buffer Output
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngMainDataEn; // Start offset and end offset
wire [C_PCI_DATA_WIDTH-1:0] wRxEngData;
wire [C_NUM_CHNL-1:0] wRxEngMainDone;
wire [C_NUM_CHNL-1:0] wRxEngMainErr;
// Interface: Reorder Buffer to SG RX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgRxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgRxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgRxErr;
// Interface: Reorder Buffer to SG TX engines
wire [(C_NUM_CHNL*C_PCI_DATA_WORD_WIDTH)-1:0] wRxEngSgTxDataEn;
wire [C_NUM_CHNL-1:0] wRxEngSgTxDone;
wire [C_NUM_CHNL-1:0] wRxEngSgTxErr;
// Interface: Channel TX Write
wire [C_NUM_CHNL-1:0] wTxEngWrReq;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngWrAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngWrLen;
wire [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] wTxEngWrData;
wire [C_NUM_CHNL-1:0] wTxEngWrDataRen;
wire [C_NUM_CHNL-1:0] wTxEngWrAck;
wire [C_NUM_CHNL-1:0] wTxEngWrSent;
// Interface: Channel TX Read
wire [C_NUM_CHNL-1:0] wTxEngRdReq;
wire [(C_NUM_CHNL*2)-1:0] wTxEngRdSgChnl;
wire [(C_NUM_CHNL*`SIG_ADDR_W)-1:0] wTxEngRdAddr;
wire [(C_NUM_CHNL*`SIG_LEN_W)-1:0] wTxEngRdLen;
wire [C_NUM_CHNL-1:0] wTxEngRdAck;
// Interface: Channel Interrupts
wire [C_NUM_CHNL-1:0] wChnlSgRxBufRecvd;
wire [C_NUM_CHNL-1:0] wChnlRxDone;
wire [C_NUM_CHNL-1:0] wChnlTxRequest;
wire [C_NUM_CHNL-1:0] wChnlTxDone;
wire [C_NUM_CHNL-1:0] wChnlSgTxBufRecvd;
wire wInternalTagValid;
wire [5:0] wInternalTag;
wire wExternalTagValid;
wire [C_TAG_WIDTH-1:0] wExternalTag;
// Interface: Channel - PIO Read
wire [C_NUM_CHNL-1:0] wChnlTxLenReady;
wire [(`SIG_TXRLEN_W*C_NUM_CHNL)-1:0] wChnlTxReqLen;
wire [C_NUM_CHNL-1:0] wChnlTxOfflastReady;
wire [(`SIG_OFFLAST_W*C_NUM_CHNL)-1:0] wChnlTxOfflast;
wire wCoreSettingsReady;
wire [`SIG_CORESETTINGS_W-1:0] wCoreSettings;
wire [C_NUM_VECTORS-1:0] wIntrVectorReady;
wire [C_NUM_VECTORS*C_VECTOR_WIDTH-1:0] wIntrVector;
wire [C_NUM_CHNL-1:0] wChnlTxDoneReady;
wire [(`SIG_TXDONELEN_W*C_NUM_CHNL)-1:0] wChnlTxDoneLen;
wire [C_NUM_CHNL-1:0] wChnlRxDoneReady;
wire [(`SIG_RXDONELEN_W*C_NUM_CHNL)-1:0] wChnlRxDoneLen;
wire wChnlNameReady;
// Interface: Channel - PIO Write
wire [31:0] wChnlReqData;
wire [C_NUM_CHNL-1:0] wChnlSgRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgRxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxLenValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrLoValid;
wire [C_NUM_CHNL-1:0] wChnlSgTxAddrHiValid;
wire [C_NUM_CHNL-1:0] wChnlRxLenValid;
wire [C_NUM_CHNL-1:0] wChnlRxOfflastValid;
wire wRxBufSpaceAvail;
wire wTxEngRdReqSent;
wire wRxEngRdComplete;
reg [4:0] rWideRst;
reg rRst;
genvar i;
assign wRxEngRdComplete = RXC_DATA_END_FLAG & RXC_DATA_VALID &
(RXC_META_LENGTH >= RXC_META_BYTES_REMAINING[`SIG_BYTECNT_W-1:2]);// TODO: Retime (if possible)
assign wCoreSettings = {9'd0, C_PCI_DATA_WIDTH[8:5], CONFIG_MAX_PAYLOAD_SIZE, CONFIG_MAX_READ_REQUEST_SIZE, CONFIG_LINK_RATE[1:0], CONFIG_LINK_WIDTH, CONFIG_BUS_MASTER_ENABLE, C_NUM_CHNL[3:0]};
assign RST_OUT = rRst;
always @ (posedge CLK) begin
rRst <= #1 rWideRst[4];
if (RST_IN | (wCoreSettingsReady /*& wRxEngReqRdDone*/)) // TODO:
rWideRst <= #1 5'b11111;
else
rWideRst <= (rWideRst<<1);
end
reorder_queue
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES(C_MAX_READ_REQ_BYTES),
.C_TAG_WIDTH(C_TAG_WIDTH)
)
reorderQueue
(
.RST (rRst),
.VALID (RXC_DATA_VALID),
.DATA_START_FLAG (RXC_DATA_START_FLAG),
.DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (RXC_DATA_END_FLAG),
.DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (RXC_DATA),
.DATA_EN (RXC_DATA_WORD_ENABLE),
.DONE (wRxEngRdComplete),
.ERR (RXC_META_EP),
.TAG (RXC_META_TAG[C_TAG_WIDTH-1:0]),
.INT_TAG (wInternalTag),
.INT_TAG_VALID (wInternalTagValid),
.EXT_TAG (wExternalTag),
.EXT_TAG_VALID (wExternalTagValid),
.ENG_DATA (wRxEngData),
.MAIN_DATA_EN (wRxEngMainDataEn),
.MAIN_DONE (wRxEngMainDone),
.MAIN_ERR (wRxEngMainErr),
.SG_RX_DATA_EN (wRxEngSgRxDataEn),
.SG_RX_DONE (wRxEngSgRxDone),
.SG_RX_ERR (wRxEngSgRxErr),
.SG_TX_DATA_EN (wRxEngSgTxDataEn),
.SG_TX_DONE (wRxEngSgTxDone),
.SG_TX_ERR (wRxEngSgTxErr),
/*AUTOINST*/
// Inputs
.CLK (CLK));
registers
#(// Parameters
.C_PIPELINE_OUTPUT (1),
.C_PIPELINE_INPUT (1),
/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_MAX_READ_REQ_BYTES (C_MAX_READ_REQ_BYTES),
.C_VENDOR (C_VENDOR),
.C_NUM_VECTORS (C_NUM_VECTORS),
.C_VECTOR_WIDTH (C_VECTOR_WIDTH),
.C_FPGA_NAME (C_FPGA_NAME))
reg_inst
(// Outputs
// Write Interfaces
.CHNL_REQ_DATA (wChnlReqData[31:0]),
.CHNL_SGRX_LEN_VALID (wChnlSgRxLenValid),
.CHNL_SGRX_ADDRLO_VALID (wChnlSgRxAddrLoValid),
.CHNL_SGRX_ADDRHI_VALID (wChnlSgRxAddrHiValid),
.CHNL_SGTX_LEN_VALID (wChnlSgTxLenValid),
.CHNL_SGTX_ADDRLO_VALID (wChnlSgTxAddrLoValid),
.CHNL_SGTX_ADDRHI_VALID (wChnlSgTxAddrHiValid),
.CHNL_RX_LEN_VALID (wChnlRxLenValid),
.CHNL_RX_OFFLAST_VALID (wChnlRxOfflastValid),
// Read Interfaces
.CHNL_TX_LEN_READY (wChnlTxLenReady),
.CHNL_TX_OFFLAST_READY (wChnlTxOfflastReady),
.CORE_SETTINGS_READY (wCoreSettingsReady),
.INTR_VECTOR_READY (wIntrVectorReady),
.CHNL_TX_DONE_READY (wChnlTxDoneReady),
.CHNL_RX_DONE_READY (wChnlRxDoneReady),
.CHNL_NAME_READY (wChnlNameReady), // TODO: Could do this on a per-channel basis
// Inputs
// Read Data
.CORE_SETTINGS (wCoreSettings),
.CHNL_TX_REQLEN (wChnlTxReqLen),
.CHNL_TX_OFFLAST (wChnlTxOfflast),
.CHNL_TX_DONELEN (wChnlTxDoneLen),
.CHNL_RX_DONELEN (wChnlRxDoneLen),
.INTR_VECTOR (wIntrVector),
.RST_IN (rRst),
/*AUTOINST*/
// Outputs
.TXC_DATA_VALID (TXC_DATA_VALID),
.TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXC_DATA_START_FLAG (TXC_DATA_START_FLAG),
.TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_DATA_END_FLAG (TXC_DATA_END_FLAG),
.TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXC_META_VALID (TXC_META_VALID),
.TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]),
.TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]),
.TXC_META_ADDR (TXC_META_ADDR[`SIG_LOWADDR_W-1:0]),
.TXC_META_TYPE (TXC_META_TYPE[`SIG_TYPE_W-1:0]),
.TXC_META_LENGTH (TXC_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_META_BYTE_COUNT (TXC_META_BYTE_COUNT[`SIG_BYTECNT_W-1:0]),
.TXC_META_TAG (TXC_META_TAG[`SIG_TAG_W-1:0]),
.TXC_META_REQUESTER_ID (TXC_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.TXC_META_TC (TXC_META_TC[`SIG_TC_W-1:0]),
.TXC_META_ATTR (TXC_META_ATTR[`SIG_ATTR_W-1:0]),
.TXC_META_EP (TXC_META_EP),
// Inputs
.CLK (CLK),
.RXR_DATA (RXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.RXR_DATA_VALID (RXR_DATA_VALID),
.RXR_DATA_START_FLAG (RXR_DATA_START_FLAG),
.RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]),
.RXR_DATA_END_FLAG (RXR_DATA_END_FLAG),
.RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]),
.RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]),
.RXR_META_ATTR (RXR_META_ATTR[`SIG_ATTR_W-1:0]),
.RXR_META_TAG (RXR_META_TAG[`SIG_TAG_W-1:0]),
.RXR_META_TYPE (RXR_META_TYPE[`SIG_TYPE_W-1:0]),
.RXR_META_ADDR (RXR_META_ADDR[`SIG_ADDR_W-1:0]),
.RXR_META_BAR_DECODED (RXR_META_BAR_DECODED[`SIG_BARDECODE_W-1:0]),
.RXR_META_REQUESTER_ID (RXR_META_REQUESTER_ID[`SIG_REQID_W-1:0]),
.RXR_META_LENGTH (RXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXC_DATA_READY (TXC_DATA_READY),
.TXC_META_READY (TXC_META_READY));
// Track receive buffer flow control credits (header & Data)
recv_credit_flow_ctrl rc_fc
(
// Outputs
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
// Inputs
.RX_ENG_RD_DONE (wRxEngRdComplete),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
.RST (rRst),
/*AUTOINST*/
// Inputs
.CLK (CLK),
.CONFIG_MAX_READ_REQUEST_SIZE (CONFIG_MAX_READ_REQUEST_SIZE[2:0]),
.CONFIG_MAX_CPL_DATA (CONFIG_MAX_CPL_DATA[11:0]),
.CONFIG_MAX_CPL_HDR (CONFIG_MAX_CPL_HDR[7:0]),
.CONFIG_CPL_BOUNDARY_SEL (CONFIG_CPL_BOUNDARY_SEL));
// Connect the interrupt vector and controller.
interrupt
#(
.C_NUM_CHNL (C_NUM_CHNL)
)
intr
(// Inputs
.RST (rRst),
.RX_SG_BUF_RECVD (wChnlSgRxBufRecvd),
.RX_TXN_DONE (wChnlRxDone),
.TX_TXN (wChnlTxRequest),
.TX_SG_BUF_RECVD (wChnlSgTxBufRecvd),
.TX_TXN_DONE (wChnlTxDone),
.VECT_0_RST (wIntrVectorReady[0]),
.VECT_1_RST (wIntrVectorReady[1]),
.VECT_RST (TXC_DATA[31:0]),
.VECT_0 (wIntrVector[31:0]),
.VECT_1 (wIntrVector[63:32]),
.INTR_LEGACY_CLR (1'd0),
/*AUTOINST*/
// Outputs
.INTR_MSI_REQUEST (INTR_MSI_REQUEST),
// Inputs
.CLK (CLK),
.CONFIG_INTERRUPT_MSIENABLE (CONFIG_INTERRUPT_MSIENABLE),
.INTR_MSI_RDY (INTR_MSI_RDY));
tx_multiplexer
#(/*AUTOINSTPARAM*/
// Parameters
.C_PCI_DATA_WIDTH (C_PCI_DATA_WIDTH),
.C_NUM_CHNL (C_NUM_CHNL),
.C_TAG_WIDTH (C_TAG_WIDTH),
.C_VENDOR (C_VENDOR),
.C_DEPTH_PACKETS (C_DEPTH_PACKETS))
tx_mux_inst
(
// Outputs
.WR_DATA_REN (wTxEngWrDataRen[C_NUM_CHNL-1:0]),
.WR_ACK (wTxEngWrAck[C_NUM_CHNL-1:0]),
.RD_ACK (wTxEngRdAck[C_NUM_CHNL-1:0]),
.INT_TAG (wInternalTag[5:0]),
.INT_TAG_VALID (wInternalTagValid),
.TX_ENG_RD_REQ_SENT (wTxEngRdReqSent),
// Inputs
.RST_IN (rRst),
.WR_REQ (wTxEngWrReq[C_NUM_CHNL-1:0]),
.WR_ADDR (wTxEngWrAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.WR_LEN (wTxEngWrLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.WR_DATA (wTxEngWrData[(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0]),
.WR_SENT (wTxEngWrSent[C_NUM_CHNL-1:0]),
.RD_REQ (wTxEngRdReq[C_NUM_CHNL-1:0]),
.RD_SG_CHNL (wTxEngRdSgChnl[(C_NUM_CHNL*2)-1:0]),
.RD_ADDR (wTxEngRdAddr[(C_NUM_CHNL*`SIG_ADDR_W)-1:0]),
.RD_LEN (wTxEngRdLen[(C_NUM_CHNL*`SIG_LEN_W)-1:0]),
.EXT_TAG (wExternalTag[C_TAG_WIDTH-1:0]),
.EXT_TAG_VALID (wExternalTagValid),
.RXBUF_SPACE_AVAIL (wRxBufSpaceAvail),
/*AUTOINST*/
// Outputs
.TXR_DATA_VALID (TXR_DATA_VALID),
.TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]),
.TXR_DATA_START_FLAG (TXR_DATA_START_FLAG),
.TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_DATA_END_FLAG (TXR_DATA_END_FLAG),
.TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.TXR_META_VALID (TXR_META_VALID),
.TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]),
.TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]),
.TXR_META_ADDR (TXR_META_ADDR[`SIG_ADDR_W-1:0]),
.TXR_META_LENGTH (TXR_META_LENGTH[`SIG_LEN_W-1:0]),
.TXR_META_TAG (TXR_META_TAG[`SIG_TAG_W-1:0]),
.TXR_META_TC (TXR_META_TC[`SIG_TC_W-1:0]),
.TXR_META_ATTR (TXR_META_ATTR[`SIG_ATTR_W-1:0]),
.TXR_META_TYPE (TXR_META_TYPE[`SIG_TYPE_W-1:0]),
.TXR_META_EP (TXR_META_EP),
// Inputs
.CLK (CLK),
.TXR_DATA_READY (TXR_DATA_READY),
.TXR_META_READY (TXR_META_READY),
.TXR_SENT (TXR_SENT));
// Generate and link up the channels.
generate
for (i = 0; i < C_NUM_CHNL; i = i + 1) begin : channels
channel
#(
.C_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_MAX_READ_REQ(C_MAX_READ_REQ)
)
channel
(
.RST(rRst),
.CLK(CLK),
.CONFIG_MAX_READ_REQUEST_SIZE(CONFIG_MAX_READ_REQUEST_SIZE),
.CONFIG_MAX_PAYLOAD_SIZE(CONFIG_MAX_PAYLOAD_SIZE),
.PIO_DATA(wChnlReqData),
.ENG_DATA(wRxEngData),
.SG_RX_BUF_RECVD(wChnlSgRxBufRecvd[i]),
.SG_TX_BUF_RECVD(wChnlSgTxBufRecvd[i]),
.TXN_TX(wChnlTxRequest[i]),
.TXN_TX_DONE(wChnlTxDone[i]),
.TXN_RX_DONE(wChnlRxDone[i]),
.SG_RX_BUF_LEN_VALID(wChnlSgRxLenValid[i]),
.SG_RX_BUF_ADDR_HI_VALID(wChnlSgRxAddrHiValid[i]),
.SG_RX_BUF_ADDR_LO_VALID(wChnlSgRxAddrLoValid[i]),
.SG_TX_BUF_LEN_VALID(wChnlSgTxLenValid[i]),
.SG_TX_BUF_ADDR_HI_VALID(wChnlSgTxAddrHiValid[i]),
.SG_TX_BUF_ADDR_LO_VALID(wChnlSgTxAddrLoValid[i]),
.TXN_RX_LEN_VALID(wChnlRxLenValid[i]),
.TXN_RX_OFF_LAST_VALID(wChnlRxOfflastValid[i]),
.TXN_RX_DONE_LEN(wChnlRxDoneLen[(`SIG_RXDONELEN_W*i) +: `SIG_RXDONELEN_W]),
.TXN_RX_DONE_ACK(wChnlRxDoneReady[i]),
.TXN_TX_ACK(wChnlTxLenReady[i]), // ACK'd on length read
.TXN_TX_LEN(wChnlTxReqLen[(`SIG_TXRLEN_W*i) +: `SIG_TXRLEN_W]),
.TXN_TX_OFF_LAST(wChnlTxOfflast[(`SIG_OFFLAST_W*i) +: `SIG_OFFLAST_W]),
.TXN_TX_DONE_LEN(wChnlTxDoneLen[(`SIG_TXDONELEN_W*i) +:`SIG_TXDONELEN_W]),
.TXN_TX_DONE_ACK(wChnlTxDoneReady[i]),
.RX_REQ(wTxEngRdReq[i]),
.RX_REQ_ACK(wTxEngRdAck[i]),
.RX_REQ_TAG(wTxEngRdSgChnl[(2*i) +:2]),// TODO: `SIG_INTERNALTAG_W
.RX_REQ_ADDR(wTxEngRdAddr[(`SIG_ADDR_W*i) +:`SIG_ADDR_W]),
.RX_REQ_LEN(wTxEngRdLen[(`SIG_LEN_W*i) +:`SIG_LEN_W]),
.TX_REQ(wTxEngWrReq[i]),
.TX_REQ_ACK(wTxEngWrAck[i]),
.TX_ADDR(wTxEngWrAddr[(`SIG_ADDR_W*i) +: `SIG_ADDR_W]),
.TX_LEN(wTxEngWrLen[(`SIG_LEN_W*i) +: `SIG_LEN_W]),
.TX_DATA(wTxEngWrData[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.TX_DATA_REN(wTxEngWrDataRen[i]),
.TX_SENT(wTxEngWrSent[i]),
.MAIN_DATA_EN(wRxEngMainDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.MAIN_DONE(wRxEngMainDone[i]),
.MAIN_ERR(wRxEngMainErr[i]),
.SG_RX_DATA_EN(wRxEngSgRxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_RX_DONE(wRxEngSgRxDone[i]),
.SG_RX_ERR(wRxEngSgRxErr[i]),
.SG_TX_DATA_EN(wRxEngSgTxDataEn[(C_PCI_DATA_WORD_WIDTH*i) +:C_PCI_DATA_WORD_WIDTH]),
.SG_TX_DONE(wRxEngSgTxDone[i]),
.SG_TX_ERR(wRxEngSgTxErr[i]),
.CHNL_RX_CLK(CHNL_RX_CLK[i]),
.CHNL_RX(CHNL_RX[i]),
.CHNL_RX_ACK(CHNL_RX_ACK[i]),
.CHNL_RX_LAST(CHNL_RX_LAST[i]),
.CHNL_RX_LEN(CHNL_RX_LEN[(32*i) +:32]),
.CHNL_RX_OFF(CHNL_RX_OFF[(31*i) +:31]),
.CHNL_RX_DATA(CHNL_RX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_RX_DATA_VALID(CHNL_RX_DATA_VALID[i]),
.CHNL_RX_DATA_REN(CHNL_RX_DATA_REN[i]),
.CHNL_TX_CLK(CHNL_TX_CLK[i]),
.CHNL_TX(CHNL_TX[i]),
.CHNL_TX_ACK(CHNL_TX_ACK[i]),
.CHNL_TX_LAST(CHNL_TX_LAST[i]),
.CHNL_TX_LEN(CHNL_TX_LEN[(32*i) +:32]),
.CHNL_TX_OFF(CHNL_TX_OFF[(31*i) +:31]),
.CHNL_TX_DATA(CHNL_TX_DATA[(C_PCI_DATA_WIDTH*i) +:C_PCI_DATA_WIDTH]),
.CHNL_TX_DATA_VALID(CHNL_TX_DATA_VALID[i]),
.CHNL_TX_DATA_REN(CHNL_TX_DATA_REN[i])
);
end
endgenerate
endmodule
// Local Variables:
// verilog-library-directories:("." "registers/" "import")
// End:
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLYBUF4S25KAPWR_BLACKBOX_V
`define SKY130_FD_SC_LP__DLYBUF4S25KAPWR_BLACKBOX_V
/**
* dlybuf4s25kapwr: Delay Buffer 4-stage 0.25um length inner stage
* gates on keep-alive power rail.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__dlybuf4s25kapwr (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR ;
supply0 VGND ;
supply1 KAPWR;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLYBUF4S25KAPWR_BLACKBOX_V
|
/* verilator lint_off WIDTH */
/* verilator lint_off UNUSED */
module scanline(
input clock,
// meta data
input isDrawArea,
input isOsdBgArea,
input isScanline,
input [8:0] scanline_intensity,
// ...
input [23:0] data,
output reg [23:0] data_out
);
localparam ONE_TO_ONE = 9'd_256;
reg [23:0] alpha_data;
reg [8:0] alpha_alpha;
wire [23:0] alpha_out;
alpha_calc ac (
.clock(clock),
.data(alpha_data),
.alpha(alpha_alpha),
.data_out(alpha_out)
);
function [8:0] trunc_osdbg(
input[16:0] value
);
trunc_osdbg = value[16:8];
endfunction
reg isOsdBgArea_q, isDrawArea_q, isScanline_q;
reg [23:0] data_q;
always @(posedge clock) begin
data_q <= data;
{ isOsdBgArea_q, isDrawArea_q, isScanline_q } <= { isOsdBgArea, isDrawArea, isScanline };
case ({ isOsdBgArea_q, isDrawArea_q })
2'b_01: begin
alpha_data <= data_q;
alpha_alpha <= (isScanline_q ? scanline_intensity : ONE_TO_ONE);
end
2'b_11: begin
alpha_data <= data_q;
alpha_alpha <= ONE_TO_ONE;
end
default: begin
alpha_data <= 24'h00;
alpha_alpha <= ONE_TO_ONE;
end
endcase
data_out <= alpha_out;
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
`define SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V
/**
* dfrtn: Delay flop, inverted reset, inverted clock,
* complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pg_n/sky130_fd_sc_hd__udp_dff_pr_pp_pg_n.v"
`celldefine
module sky130_fd_sc_hd__dfrtn (
Q ,
CLK_N ,
D ,
RESET_B
);
// Module ports
output Q ;
input CLK_N ;
input D ;
input RESET_B;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire buf_Q ;
wire RESET ;
wire intclk ;
reg notifier ;
wire D_delayed ;
wire RESET_B_delayed;
wire CLK_N_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
not not1 (intclk, CLK_N_delayed );
sky130_fd_sc_hd__udp_dff$PR_pp$PG$N dff0 (buf_Q , D_delayed, intclk, RESET, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
assign cond0 = ( awake && ( RESET_B_delayed === 1'b1 ) );
assign cond1 = ( awake && ( RESET_B === 1'b1 ) );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTN_BEHAVIORAL_V |
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file k7_mBuf_128x72.v when simulating
// the core, k7_mBuf_128x72. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module k7_mBuf_128x72(
clk,
rst,
din,
wr_en,
rd_en,
dout,
full,
empty,
prog_full
);
input clk;
input rst;
input [71 : 0] din;
input wr_en;
input rd_en;
output [71 : 0] dout;
output full;
output empty;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(9),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(72),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(72),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(6),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(4),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(128),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(127),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(9),
.C_RD_DEPTH(512),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(9),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(0),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(9),
.C_WR_DEPTH(512),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(9),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.RST(rst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.SRST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// Copyright (C) 2017-2020 The Project X-Ray Authors.
//
// Use of this source code is governed by a ISC-style
// license that can be found in the LICENSE file or at
// https://opensource.org/licenses/ISC
//
// SPDX-License-Identifier: ISC
`default_nettype none
// ============================================================================
module message_formatter #
(
parameter WIDTH = 24, // Word length in bits. MUST be a multiply of 4
parameter COUNT = 2, // Word count
parameter TX_INTERVAL = 4 // Character transmission interval
)
(
// Clock and reset
input wire CLK,
input wire RST,
// Data input
input wire I_STB,
input wire [(WIDTH*COUNT)-1:0] I_DAT,
// ASCII output
output wire O_STB,
output wire [7:0] O_DAT
);
// ============================================================================
// Total input data word width
localparam TOTAL_WIDTH = WIDTH * COUNT;
// ============================================================================
// FSM states
integer fsm;
localparam FSM_IDLE = 'h00;
localparam FSM_TX_HEX = 'h11;
localparam FSM_TX_CR = 'h21;
localparam FSM_TX_LF = 'h22;
localparam FSM_TX_SEP = 'h31;
// ============================================================================
// TX interval counter
reg [24:0] tx_dly_cnt;
reg tx_req;
wire tx_rdy;
always @(posedge CLK)
if (RST)
tx_dly_cnt <= -1;
else if (!tx_rdy)
tx_dly_cnt <= tx_dly_cnt - 1;
else if ( tx_rdy && tx_req)
tx_dly_cnt <= TX_INTERVAL - 2;
assign tx_rdy = tx_dly_cnt[24];
always @(posedge CLK)
if (RST)
tx_req <= 1'b0;
else case (fsm)
FSM_TX_HEX: tx_req <= 1'b1;
FSM_TX_SEP: tx_req <= 1'b1;
FSM_TX_CR: tx_req <= 1'b1;
FSM_TX_LF: tx_req <= 1'b1;
default: tx_req <= 1'b0;
endcase
// ============================================================================
// Word and char counter
reg [7:0] char_cnt;
reg [7:0] word_cnt;
always @(posedge CLK)
if (fsm == FSM_IDLE || fsm == FSM_TX_SEP)
char_cnt <= (WIDTH/4) - 1;
else if (tx_rdy && fsm == FSM_TX_HEX)
char_cnt <= char_cnt - 1;
always @(posedge CLK)
if (fsm == FSM_IDLE)
word_cnt <= COUNT - 1;
else if (tx_rdy && fsm == FSM_TX_SEP)
word_cnt <= word_cnt - 1;
// ============================================================================
// Data shift register
reg [TOTAL_WIDTH-1:0] sr_reg;
wire [3:0] sr_dat;
always @(posedge CLK)
if (fsm == FSM_IDLE && I_STB)
sr_reg <= I_DAT;
else if (fsm == FSM_TX_HEX && tx_rdy)
sr_reg <= sr_reg << 4;
assign sr_dat = sr_reg[TOTAL_WIDTH-1:TOTAL_WIDTH-4];
// ============================================================================
// Control FSM
always @(posedge CLK)
if (RST)
fsm <= FSM_IDLE;
else case (fsm)
FSM_IDLE: if (I_STB) fsm <= FSM_TX_HEX;
FSM_TX_HEX:
if (tx_rdy && (char_cnt == 0) && (word_cnt == 0))
fsm <= FSM_TX_CR;
else if (tx_rdy && (char_cnt == 0)) fsm <= FSM_TX_SEP;
else if (tx_rdy && (char_cnt != 0)) fsm <= FSM_TX_HEX;
FSM_TX_SEP: if (tx_rdy) fsm <= FSM_TX_HEX;
FSM_TX_CR: if (tx_rdy) fsm <= FSM_TX_LF;
FSM_TX_LF: if (tx_rdy) fsm <= FSM_IDLE;
endcase
// ============================================================================
// Data to ASCII converter
reg o_stb;
reg [7:0] o_dat;
always @(posedge CLK or posedge RST)
if (RST)
o_stb <= 1'd0;
else
o_stb <= tx_req & tx_rdy;
always @(posedge CLK)
if (fsm == FSM_TX_CR)
o_dat <= 8'h0D;
else if (fsm == FSM_TX_LF)
o_dat <= 8'h0A;
else if (fsm == FSM_TX_SEP)
o_dat <= "_";
else if (fsm == FSM_TX_HEX) case (sr_dat)
4'h0: o_dat <= "0";
4'h1: o_dat <= "1";
4'h2: o_dat <= "2";
4'h3: o_dat <= "3";
4'h4: o_dat <= "4";
4'h5: o_dat <= "5";
4'h6: o_dat <= "6";
4'h7: o_dat <= "7";
4'h8: o_dat <= "8";
4'h9: o_dat <= "9";
4'hA: o_dat <= "A";
4'hB: o_dat <= "B";
4'hC: o_dat <= "C";
4'hD: o_dat <= "D";
4'hE: o_dat <= "E";
4'hF: o_dat <= "F";
endcase
assign O_STB = o_stb;
assign O_DAT = o_dat;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:59:30 06/14/2016
// Design Name:
// Module Name: LZD_2bit_tb
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
// Testbench for all Leading zero detectors
module LZD_2bit_tb;
reg [1:0]in;
wire valid;
wire out;
parameter n=4; // parameter for convenience of code utilization
integer i;
LZD_2bit tb1( .in(in), .out(out), .valid(valid));
initial
begin
for( i=0; i<n; i=i+1)
#10 assign in= {i}; // loop is used to assign values to input
end
endmodule
module LZD_4bit_tb;
reg [3:0]in;
wire valid;
wire [1:0]out;
parameter n=16; // parameter declaration for convenience of code reutilization
integer i; // integer for "for loop"
LZD_4bit tb2( .in(in), .out(out), .valid(valid)); // instantiation
initial
begin
for( i=0; i<n; i=i+1)
#10 assign in= {i}; // loop to assign values
end
endmodule
// LZD_8bit testbench
module LZD_8bit_tb;
reg [7:0]in;
wire valid;
wire [2:0]out;
parameter n=256;
integer i,j;
LZD_8bit tb3( .in(in), .out(out), .valid(valid));
initial
begin
assign j=1;
for( i=0; i<n; i=i+j)
begin
#5 assign in= {i};
j=j*2;
end
end
endmodule
module LZD_16bit_tb;
reg [15:0]in;
wire valid;
wire [3:0]out;
parameter n=65536;
integer i,j;
LZD_16bit tb4( .in(in), .out(out), .valid(valid));
initial
begin
assign j=1;
for( i=0; i<n; i=i+j)
begin
#1 assign in= {i};
assign j=j*2;
end
end
endmodule
module LZD_32bit_tb;
reg [31:0]in;
wire valid;
wire [4:0]out;
parameter n=65536;
integer i,j;
LZD_32bit tb5( .in(in), .out(out), .valid(valid));
initial
begin
assign j=1;
for( i=0; i<n; i=i+j)
begin
#1 assign in= {i};
assign j=j*2;
end
end
endmodule
module LZD_48bit_tb;
reg [47:0]in;
wire valid;
wire [5:0]out;
parameter n=65536;
integer i;
LZD_48bit tb6( .in(in), .out(out), .valid(valid));
initial
begin
for( i=1; i<n; i=i*2) // loop for complete test coverage of 48bit LZD
begin
#5 in[47:0]<= {{i[15:0]},{i[31:0]}};
// #5 in[47:0]<= {{i[31:0]},{i[15:0]}};
// #5 in[47:0]<= {{16'b0},{i[31:0]}};
end
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: LKB
// Engineer: Leonhard Neuhaus
//
// Create Date: 18.02.2016 11:42:49
// Design Name:
// Module Name: red_pitaya_lpf_block
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
/* This module takes a signed input signal of SIGNALBITS, multiplies it by a
gain ranging from 1 to 2**(SIGNALBITS-1)-1, and subtracts it from a custom
setpoint before outputting the signal. The multiplication factor is the
result from taking the absolute value of the output signal and integrating
it. That way, the output signal will be stabilized at setpoint up to the
unity-gain frequency of the integrator, but its higher-frequency components
will pass through. One useful application of this is to make a pdh signal
more robust to amplitude fluctuations that it already is, as even away from
the zero crossing of the error signal, where the pdh amplitude is
proportional to the DC power, the effective DC power after this module is
constant (and equal to the setpoint). */
module red_pitaya_normalizer_block
#(
parameter ISR = 24,
parameter SIGNALBITS = 14, //bitwidth of signals
parameter GAINBITS = 16 //minimum allowed filter bandwidth
)
(
input clk_i,
input rstn_i ,
input [SHIFTBITS:0] shift,
input filter_on,
input highpass,
input signed [SIGNALBITS-1:0] signal_i,
input signed [SIGNALBITS-1:0] inputoffset_i,
input [SIGNALBITS-2:0] setpoint_i,
input signed [GAINBITS-1:0] gain_i,
output signed [SIGNALBITS-1:0] signal_o
);
// add an offset to the (analog) input value
wire signed [SIGNALBITS+1-1:0] in_subtracted;
wire [SIGNALBITS-1:0] in_abs;
assign in_subtracted = signal_i - inputoffset_i;
// make input positive, but don't add the extra bit. That gives a tiny
// offset to negative signals (1 bit, but avoid special treatment for the
// stragne number
assign in_abs = in_subtracted[SIGNALBITS] ? ((~in_subtracted) /*+'b1*/) : in_subtracted;
// buffer
reg [SIGNALBITS-1:0] input;
always @(posedge clk_i) begin
input <= in_abs[SIGNALBITS-1:0];
end
// now, input is in principle a 13 bit number, unless something went really
// wrong with the input offset (in which case its 14 bits unsigned)
// multiply input by integral factor, add something for rounding
// integral goes from 1 to 2**(SIGNALBITS)-1
// input goes from 0 to 2**(SIGNALBITS)-1, but the MSB should be zero
// so product goes from 0 to 2**(2*SIGNALBITS)-1, but MSB should be zero
// we rescale product to product_done taking only the highest SIGNALBITS+1
// bits, of which only SIGNALBITS carry any information
wire [SIGNALBITS-1:0] integral;
wire [SIGNALBITS*2-1:0] product;
assign product = input * integral; // no rounding since unsigned arithmetic
wire [SIGNALBITS*2:0] product_signed;
wire [SIGNALBITS*2:0] setpoint_signed;
assign product_signed = {1'b0, product};
// first sign bit (0), then the MSB mentioned above, then the SIGNALBITS-1 of
// relevant information
wire signed setpoint_signed = {1'b0, 1'b0, setpoint_i, {SIGNALBITS{1'b0}};
// error doesnt need extra bit since we subtract 2 positive numbers
reg signed [SIGNALBITS*2:0] error;
always @(posedge clk_i) begin
error <= setpoint_signed - product_signed;
end
// crop the number by throwing away the 2 most significant bits
reg signed [SIGNALBITS-1:0] error_done;
always @(posedge clk_i) begin
// pos saturation
if ({error[SIGNALBITS*2], (|(error[SIGNALBITS*2-1:SIGNALBITS*2-2]))} == 2'b01)
error_done <= {1'b0, {SIGNALBITS-1{1'b1}}};
else if ({error[SIGNALBITS*2], (&(error[SIGNALBITS*2-1:SIGNALBITS*2-2]))} == 2'b10)
error_done <= {1'b1, {SIGNALBITS-1{1'b0}}};
else
error_done <= error[SIGNALBITS*2-2:SIGNALBITS-2];
end
assign signal_o = filter_on ? error_done : signal_i;
// gain calculation
// negative gain because of error calculation (setpoint - product)
// therefore just need a positive integrator
reg signed [SIGNALBITS: 0] int_sum;
always @(posedge clk_i) begin
int_sum <= $signed(int_sat) + $signed(error_done);
end
// Integrator - 2 cycles delay (but treat similar to proportional since it
// will become negligible at high frequencies where delay is important)
localparam IBW = ISR+SIGNALBITS;
reg [SIGNALBITS+GAINBITS-1: 0] ki_mult ;
wire [IBW : 0] int_sum ;
reg [IBW-1: 0] int_reg ;
wire [IBW-ISR-1: 0] int_shr ;
always @(posedge clk_i) begin
if (rstn_i == 1'b0) begin
ki_mult <= {SIGNALBITS+GAINBITS{1'b0}};
int_reg <= {IBW{1'b0}};
end
else begin
ki_mult <= $signed(error_done) * $signed(gain_i) ;
if (ival_write)
int_reg <= { {IBW-16-ISR{set_ival[16-1]}},set_ival[16-1:0],{ISR{1'b0}}};
else if (int_sum[IBW+1-1:IBW+1-2] == 2'b01) // positive saturation
int_reg <= {1'b0,{IBW-1{1'b1}}};
else if (int_sum[IBW+1-1:IBW+1-2] == 2'b10) // negative saturation
int_reg <= {1'b1,{IBW-1{1'b0}}};
else
int_reg <= int_sum[IBW-1:0]; // use sum as it is
end
end
assign int_sum = $signed(ki_mult) + $signed(int_reg) ;
assign int_shr = $signed(int_reg[IBW-1:ISR]) ;
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR3B_PP_SYMBOL_V
`define SKY130_FD_SC_LP__NOR3B_PP_SYMBOL_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__nor3b (
//# {{data|Data Signals}}
input A ,
input B ,
input C_N ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR3B_PP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Jafet Chaves Barrantes
//
// Create Date: 21:28:51 04/04/2016
// Design Name:
// Module Name: contador_AD_HH_2dig
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module contador_AD_HH_2dig
(
input wire clk,
input wire reset,
input wire [3:0]en_count,
input wire enUP,
input wire enDOWN,
output wire [7:0] data_HH//Dígitos BCD ya concatenados hacia los registros(8 bits)
);
localparam N = 5; // Para definir el número de bits del contador (hasta 23->5 bits)
//Declaración de señales
reg [N-1:0] q_act, q_next;
wire [N-1:0] count_data;
reg [3:0] digit1, digit0;
//Descripción del comportamiento
always@(posedge clk, posedge reset)
begin
if(reset)
begin
q_act <= 5'b0;
end
else
begin
q_act <= q_next;
end
end
//Lógica de salida
always@*
begin
if (en_count == 3)
begin
if (enUP)
begin
if (q_act >= 5'd23) q_next = 5'd0;
else q_next = q_act + 5'd1;
end
else if (enDOWN)
begin
if (q_act == 5'd0) q_next = 5'd23;
else q_next = q_act - 5'd1;
end
else q_next = q_act;
end
else q_next = q_act;
end
assign count_data = q_act;
//Decodificación BCD (2 dígitos)
always@*
begin
case(count_data)
5'd0: begin digit1 = 4'b0000; digit0 = 4'b0000; end
5'd1: begin digit1 = 4'b0000; digit0 = 4'b0001; end
5'd2: begin digit1 = 4'b0000; digit0 = 4'b0010; end
5'd3: begin digit1 = 4'b0000; digit0 = 4'b0011; end
5'd4: begin digit1 = 4'b0000; digit0 = 4'b0100; end
5'd5: begin digit1 = 4'b0000; digit0 = 4'b0101; end
5'd6: begin digit1 = 4'b0000; digit0 = 4'b0110; end
5'd7: begin digit1 = 4'b0000; digit0 = 4'b0111; end
5'd8: begin digit1 = 4'b0000; digit0 = 4'b1000; end
5'd9: begin digit1 = 4'b0000; digit0 = 4'b1001; end
5'd10: begin digit1 = 4'b0001; digit0 = 4'b0000; end
5'd11: begin digit1 = 4'b0001; digit0 = 4'b0001; end
5'd12: begin digit1 = 4'b0001; digit0 = 4'b0010; end
5'd13: begin digit1 = 4'b0001; digit0 = 4'b0011; end
5'd14: begin digit1 = 4'b0001; digit0 = 4'b0100; end
5'd15: begin digit1 = 4'b0001; digit0 = 4'b0101; end
5'd16: begin digit1 = 4'b0001; digit0 = 4'b0110; end
5'd17: begin digit1 = 4'b0001; digit0 = 4'b0111; end
5'd18: begin digit1 = 4'b0001; digit0 = 4'b1000; end
5'd19: begin digit1 = 4'b0001; digit0 = 4'b1001; end
5'd20: begin digit1 = 4'b0010; digit0 = 4'b0000; end
5'd21: begin digit1 = 4'b0010; digit0 = 4'b0001; end
5'd22: begin digit1 = 4'b0010; digit0 = 4'b0010; end
5'd23: begin digit1 = 4'b0010; digit0 = 4'b0011; end
default: begin digit1 = 0; digit0 = 0; end
endcase
end
assign data_HH = {digit1,digit0};
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// parameters for array sizes
localparam WA = 8; // address dimension size
localparam WB = 8; // bit dimension size
localparam NO = 10; // number of access events
// 2D packed arrays
logic [WA-1:0] [WB-1:0] array_bg; // big endian array
/* verilator lint_off LITENDIAN */
logic [0:WA-1] [0:WB-1] array_lt; // little endian array
/* verilator lint_on LITENDIAN */
integer cnt = 0;
// event counter
always @ (posedge clk) begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) array_bg <= {WA *WB{1'bx} };
else if (cnt[30:2]==1) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==2) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==3) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==4) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==5) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==6) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==7) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==8) array_bg <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==9) array_bg <= {WA{ {WB{1'bx}} }};
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_bg <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_bg [WA/2-1:0 ] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_bg [WA -1:WA/2] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_bg [ 0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_bg [WA -1 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_bg [ 0 ][WB/2-1:0 ] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_bg [WA -1 ][WB -1:WB/2] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_bg [ 0 ][ 0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_bg [WA -1 ][WB -1 ] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (array_bg !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (array_bg !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (array_bg !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==6) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==7) begin if (array_bg !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==8) begin if (array_bg !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) begin $display("%b", array_bg); $stop(); end end
else if (cnt[30:2]==9) begin if (array_bg !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_bg !== {WA *WB {1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_bg !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_bg [WA/2-1:0 ] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_bg [WA -1:WA/2] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_bg [ 0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_bg [WA -1 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_bg [ 0 ][WB/2-1:0 ] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_bg [WA -1 ][WB -1:WB/2] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_bg [ 0 ][ 0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_bg [WA -1 ][WB -1 ] !== {1 *1 +0{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to x)
if (cnt[30:2]==0) array_lt <= {WA *WB{1'bx} };
else if (cnt[30:2]==1) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==2) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==3) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==4) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==5) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==6) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==7) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==8) array_lt <= {WA{ {WB{1'bx}} }};
else if (cnt[30:2]==9) array_lt <= {WA{ {WB{1'bx}} }};
end else if (cnt[1:0]==2'd1) begin
// write value to array
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) array_lt <= {WA *WB +0{1'b1}};
else if (cnt[30:2]==2) array_lt [0 :WA/2-1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==3) array_lt [WA/2:WA -1] <= {WA/2*WB +0{1'b1}};
else if (cnt[30:2]==4) array_lt [0 ] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==5) array_lt [ WA -1] <= {1 *WB +0{1'b1}};
else if (cnt[30:2]==6) array_lt [0 ][0 :WB/2-1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==7) array_lt [ WA -1][WB/2:WB -1] <= {1 *WB/2+0{1'b1}};
else if (cnt[30:2]==8) array_lt [0 ][0 ] <= {1 *1 +0{1'b1}};
else if (cnt[30:2]==9) array_lt [ WA -1][ WB -1] <= {1 *1 +0{1'b1}};
end else if (cnt[1:0]==2'd2) begin
// check array value
if (cnt[30:2]==0) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (array_lt !== 64'b1111111111111111111111111111111111111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (array_lt !== 64'b11111111111111111111111111111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111111111111111111111111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (array_lt !== 64'b11111111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx11111111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==6) begin if (array_lt !== 64'b1111xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==7) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1111) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==8) begin if (array_lt !== 64'b1xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx) begin $display("%b", array_lt); $stop(); end end
else if (cnt[30:2]==9) begin if (array_lt !== 64'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1) begin $display("%b", array_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from array (not a very good test for now)
if (cnt[30:2]==0) begin if (array_lt !== {WA *WB {1'bx}}) $stop(); end
else if (cnt[30:2]==1) begin if (array_lt !== {WA *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (array_lt [0 :WA/2-1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (array_lt [WA/2:WA -1] !== {WA/2*WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (array_lt [0 ] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (array_lt [ WA -1] !== {1 *WB +0{1'b1}}) $stop(); end
else if (cnt[30:2]==6) begin if (array_lt [0 ][0 :WB/2-1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==7) begin if (array_lt [ WA -1][WB/2:WB -1] !== {1 *WB/2+0{1'b1}}) $stop(); end
else if (cnt[30:2]==8) begin if (array_lt [0 ][0 ] !== {1 *1 +0{1'b1}}) $stop(); end
else if (cnt[30:2]==9) begin if (array_lt [ WA -1][ WB -1] !== {1 *1 +0{1'b1}}) $stop(); end
end
endmodule
|
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Wed Apr 06 16:08:54 2016
//Host : WK116 running 64-bit major release (build 9200)
//Command : generate_target PmodAMP2.bd
//Design : PmodAMP2
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "PmodAMP2,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=PmodAMP2,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=6,numReposBlks=6,numNonXlnxBlks=2,numHierBlks=0,maxHierDepth=0,synth_mode=Global}" *) (* HW_HANDOFF = "PmodAMP2.hwdef" *)
module PmodAMP2
(GPIO_AXI_araddr,
GPIO_AXI_arready,
GPIO_AXI_arvalid,
GPIO_AXI_awaddr,
GPIO_AXI_awready,
GPIO_AXI_awvalid,
GPIO_AXI_bready,
GPIO_AXI_bresp,
GPIO_AXI_bvalid,
GPIO_AXI_rdata,
GPIO_AXI_rready,
GPIO_AXI_rresp,
GPIO_AXI_rvalid,
GPIO_AXI_wdata,
GPIO_AXI_wready,
GPIO_AXI_wstrb,
GPIO_AXI_wvalid,
PWM_AXI_araddr,
PWM_AXI_arprot,
PWM_AXI_arready,
PWM_AXI_arvalid,
PWM_AXI_awaddr,
PWM_AXI_awprot,
PWM_AXI_awready,
PWM_AXI_awvalid,
PWM_AXI_bready,
PWM_AXI_bresp,
PWM_AXI_bvalid,
PWM_AXI_rdata,
PWM_AXI_rready,
PWM_AXI_rresp,
PWM_AXI_rvalid,
PWM_AXI_wdata,
PWM_AXI_wready,
PWM_AXI_wstrb,
PWM_AXI_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
PWM_interrupt,
s_axi_aclk,
s_axi_aresetn);
input [8:0]GPIO_AXI_araddr;
output GPIO_AXI_arready;
input GPIO_AXI_arvalid;
input [8:0]GPIO_AXI_awaddr;
output GPIO_AXI_awready;
input GPIO_AXI_awvalid;
input GPIO_AXI_bready;
output [1:0]GPIO_AXI_bresp;
output GPIO_AXI_bvalid;
output [31:0]GPIO_AXI_rdata;
input GPIO_AXI_rready;
output [1:0]GPIO_AXI_rresp;
output GPIO_AXI_rvalid;
input [31:0]GPIO_AXI_wdata;
output GPIO_AXI_wready;
input [3:0]GPIO_AXI_wstrb;
input GPIO_AXI_wvalid;
input [3:0]PWM_AXI_araddr;
input [2:0]PWM_AXI_arprot;
output PWM_AXI_arready;
input PWM_AXI_arvalid;
input [3:0]PWM_AXI_awaddr;
input [2:0]PWM_AXI_awprot;
output PWM_AXI_awready;
input PWM_AXI_awvalid;
input PWM_AXI_bready;
output [1:0]PWM_AXI_bresp;
output PWM_AXI_bvalid;
output [31:0]PWM_AXI_rdata;
input PWM_AXI_rready;
output [1:0]PWM_AXI_rresp;
output PWM_AXI_rvalid;
input [31:0]PWM_AXI_wdata;
output PWM_AXI_wready;
input [3:0]PWM_AXI_wstrb;
input PWM_AXI_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
output wire PWM_interrupt;
input s_axi_aclk;
input s_axi_aresetn;
wire PWM_0_pwm;
wire [3:0]PWM_AXI_1_ARADDR;
wire [2:0]PWM_AXI_1_ARPROT;
wire PWM_AXI_1_ARREADY;
wire PWM_AXI_1_ARVALID;
wire [3:0]PWM_AXI_1_AWADDR;
wire [2:0]PWM_AXI_1_AWPROT;
wire PWM_AXI_1_AWREADY;
wire PWM_AXI_1_AWVALID;
wire PWM_AXI_1_BREADY;
wire [1:0]PWM_AXI_1_BRESP;
wire PWM_AXI_1_BVALID;
wire [31:0]PWM_AXI_1_RDATA;
wire PWM_AXI_1_RREADY;
wire [1:0]PWM_AXI_1_RRESP;
wire PWM_AXI_1_RVALID;
wire [31:0]PWM_AXI_1_WDATA;
wire PWM_AXI_1_WREADY;
wire [3:0]PWM_AXI_1_WSTRB;
wire PWM_AXI_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [2:0]axi_gpio_0_gpio_io_o;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
wire [0:0]xlslice_0_Dout;
wire [0:0]xlslice_1_Dout;
wire [0:0]xlslice_2_Dout;
assign GPIO_AXI_arready = S_AXI_1_ARREADY;
assign GPIO_AXI_awready = S_AXI_1_AWREADY;
assign GPIO_AXI_bresp[1:0] = S_AXI_1_BRESP;
assign GPIO_AXI_bvalid = S_AXI_1_BVALID;
assign GPIO_AXI_rdata[31:0] = S_AXI_1_RDATA;
assign GPIO_AXI_rresp[1:0] = S_AXI_1_RRESP;
assign GPIO_AXI_rvalid = S_AXI_1_RVALID;
assign GPIO_AXI_wready = S_AXI_1_WREADY;
assign PWM_AXI_1_ARADDR = PWM_AXI_araddr[3:0];
assign PWM_AXI_1_ARPROT = PWM_AXI_arprot[2:0];
assign PWM_AXI_1_ARVALID = PWM_AXI_arvalid;
assign PWM_AXI_1_AWADDR = PWM_AXI_awaddr[3:0];
assign PWM_AXI_1_AWPROT = PWM_AXI_awprot[2:0];
assign PWM_AXI_1_AWVALID = PWM_AXI_awvalid;
assign PWM_AXI_1_BREADY = PWM_AXI_bready;
assign PWM_AXI_1_RREADY = PWM_AXI_rready;
assign PWM_AXI_1_WDATA = PWM_AXI_wdata[31:0];
assign PWM_AXI_1_WSTRB = PWM_AXI_wstrb[3:0];
assign PWM_AXI_1_WVALID = PWM_AXI_wvalid;
assign PWM_AXI_arready = PWM_AXI_1_ARREADY;
assign PWM_AXI_awready = PWM_AXI_1_AWREADY;
assign PWM_AXI_bresp[1:0] = PWM_AXI_1_BRESP;
assign PWM_AXI_bvalid = PWM_AXI_1_BVALID;
assign PWM_AXI_rdata[31:0] = PWM_AXI_1_RDATA;
assign PWM_AXI_rresp[1:0] = PWM_AXI_1_RRESP;
assign PWM_AXI_rvalid = PWM_AXI_1_RVALID;
assign PWM_AXI_wready = PWM_AXI_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = GPIO_AXI_araddr[8:0];
assign S_AXI_1_ARVALID = GPIO_AXI_arvalid;
assign S_AXI_1_AWADDR = GPIO_AXI_awaddr[8:0];
assign S_AXI_1_AWVALID = GPIO_AXI_awvalid;
assign S_AXI_1_BREADY = GPIO_AXI_bready;
assign S_AXI_1_RREADY = GPIO_AXI_rready;
assign S_AXI_1_WDATA = GPIO_AXI_wdata[31:0];
assign S_AXI_1_WSTRB = GPIO_AXI_wstrb[3:0];
assign S_AXI_1_WVALID = GPIO_AXI_wvalid;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodAMP2_PWM_0_0 PWM_0
(.pwm(PWM_0_pwm),
.interrupt(PWM_interrupt),
.pwm_axi_aclk(s_axi_aclk_1),
.pwm_axi_araddr(PWM_AXI_1_ARADDR),
.pwm_axi_aresetn(s_axi_aresetn_1),
.pwm_axi_arprot(PWM_AXI_1_ARPROT),
.pwm_axi_arready(PWM_AXI_1_ARREADY),
.pwm_axi_arvalid(PWM_AXI_1_ARVALID),
.pwm_axi_awaddr(PWM_AXI_1_AWADDR),
.pwm_axi_awprot(PWM_AXI_1_AWPROT),
.pwm_axi_awready(PWM_AXI_1_AWREADY),
.pwm_axi_awvalid(PWM_AXI_1_AWVALID),
.pwm_axi_bready(PWM_AXI_1_BREADY),
.pwm_axi_bresp(PWM_AXI_1_BRESP),
.pwm_axi_bvalid(PWM_AXI_1_BVALID),
.pwm_axi_rdata(PWM_AXI_1_RDATA),
.pwm_axi_rready(PWM_AXI_1_RREADY),
.pwm_axi_rresp(PWM_AXI_1_RRESP),
.pwm_axi_rvalid(PWM_AXI_1_RVALID),
.pwm_axi_wdata(PWM_AXI_1_WDATA),
.pwm_axi_wready(PWM_AXI_1_WREADY),
.pwm_axi_wstrb(PWM_AXI_1_WSTRB),
.pwm_axi_wvalid(PWM_AXI_1_WVALID));
PmodAMP2_axi_gpio_0_0 axi_gpio_0
(.gpio_io_o(axi_gpio_0_gpio_io_o),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodAMP2_pmod_bridge_0_0 pmod_bridge_0
(.in0_O(PWM_0_pwm),
.in0_T(0),
.in1_O(xlslice_0_Dout),
.in1_T(0),
.in2_O(xlslice_1_Dout),
.in2_T(0),
.in3_O(xlslice_2_Dout),
.in3_T(0),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
PmodAMP2_xlslice_0_0 xlslice_0
(.Din(axi_gpio_0_gpio_io_o),
.Dout(xlslice_0_Dout));
PmodAMP2_xlslice_0_1 xlslice_1
(.Din(axi_gpio_0_gpio_io_o),
.Dout(xlslice_1_Dout));
PmodAMP2_xlslice_0_2 xlslice_2
(.Din(axi_gpio_0_gpio_io_o),
.Dout(xlslice_2_Dout));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__DFRTP_SYMBOL_V
`define SKY130_FD_SC_HD__DFRTP_SYMBOL_V
/**
* dfrtp: Delay flop, inverted reset, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__dfrtp (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{control|Control Signals}}
input RESET_B,
//# {{clocks|Clocking}}
input CLK
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__DFRTP_SYMBOL_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Case Western Reserve University
// Engineer: Matt McConnell
//
// Create Date: 22:29:00 09/09/2017
// Project Name: EECS301 Digital Design
// Design Name: Lab #4 Project
// Module Name: Key_Synchronizer_Bank
// Target Devices: Altera Cyclone V
// Tool versions: Quartus v17.0
// Description: Key Synchronizer Bank
//
// Dependencies:
//
//////////////////////////////////////////////////////////////////////////////////
module Key_Synchronizer_Bank
#(
parameter KEY_SYNC_CHANNELS = 1,
parameter CLK_RATE_HZ = 50000000, // Hz
parameter KEY_LOCK_DELAY = 800000000 // 800 mS
)
(
// Input Signals
input [KEY_SYNC_CHANNELS-1:0] KEY,
// Output Signals
output [KEY_SYNC_CHANNELS-1:0] KEY_EVENT,
// System Signals
input CLK
);
//
// Key Input Synchronizers
//
genvar i;
generate
begin
for (i = 0; i < KEY_SYNC_CHANNELS; i=i+1)
begin : key_sync_gen
Key_Synchronizer_Module
#(
.CLK_RATE_HZ( CLK_RATE_HZ ),
.KEY_LOCK_DELAY( KEY_LOCK_DELAY )
)
key_synchronizer
(
// Input Signals
.KEY( KEY[i] ),
// Output Signals
.KEY_EVENT( KEY_EVENT[i] ),
// System Signals
.CLK( CLK )
);
end
end
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module sky130_fd_io__top_sio_macro (
IN,
IN_H,
TIE_LO_ESD,
AMUXBUS_A,
AMUXBUS_B,
PAD,
PAD_A_ESD_0_H,
PAD_A_ESD_1_H,
PAD_A_NOESD_H,
VINREF_DFT,
VOUTREF_DFT,
DFT_REFGEN,
DM0,
DM1,
HLD_H_N,
HLD_H_N_REFGEN,
HLD_OVR,
IBUF_SEL,
IBUF_SEL_REFGEN,
INP_DIS,
ENABLE_H,
ENABLE_VDDA_H,
OE_N,
OUT,
SLOW,
VOH_SEL,
VOHREF,
VREF_SEL,
VREG_EN,
VREG_EN_REFGEN,
VTRIP_SEL,
VTRIP_SEL_REFGEN
);
wire VOUTREF;
wire VINREF;
wire REFLEAK_BIAS;
supply1 vddio;
supply1 vddio_q;
supply1 vdda;
supply1 vccd;
supply1 vswitch;
supply1 vcchib;
supply0 vssd;
supply0 vssio;
supply0 vssio_q;
supply0 vssa;
inout AMUXBUS_A;
inout AMUXBUS_B;
inout VINREF_DFT;
inout VOUTREF_DFT;
input DFT_REFGEN;
input HLD_H_N_REFGEN;
input IBUF_SEL_REFGEN;
input ENABLE_VDDA_H;
input ENABLE_H;
input VOHREF;
input VREG_EN_REFGEN;
input VTRIP_SEL_REFGEN;
output [1:0] TIE_LO_ESD;
output [1:0] IN_H;
output [1:0] IN;
inout [1:0] PAD_A_NOESD_H;
inout [1:0] PAD;
inout [1:0] PAD_A_ESD_1_H;
inout [1:0] PAD_A_ESD_0_H;
input [1:0] SLOW;
input [1:0] VTRIP_SEL;
input [1:0] HLD_H_N;
input [1:0] VREG_EN;
input [2:0] VOH_SEL;
input [1:0] INP_DIS;
input [1:0] HLD_OVR;
input [1:0] OE_N;
input [1:0] VREF_SEL;
input [1:0] IBUF_SEL;
input [2:0] DM0;
input [2:0] DM1;
input [1:0] OUT;
reg notifier_enable_h_refgen,
notifier_vtrip_sel_refgen,
notifier_vreg_en_refgen,
notifier_ibuf_sel_refgen,
notifier_vref_sel,
notifier_vref_sel_int,
notifier_voh_sel,
notifier_dft_refgen;
reg notifier_enable_h_0;
reg notifier_hld_ovr_0;
reg notifier_dm_0;
reg notifier_inp_dis_0;
reg notifier_vtrip_sel_0;
reg notifier_slow_0;
reg notifier_oe_n_0;
reg notifier_out_0;
reg notifier_vreg_en_0;
reg notifier_ibuf_sel_0;
reg notifier_enable_h_1;
reg notifier_hld_ovr_1;
reg notifier_dm_1;
reg notifier_inp_dis_1;
reg notifier_vtrip_sel_1;
reg notifier_slow_1;
reg notifier_oe_n_1;
reg notifier_out_1;
reg notifier_vreg_en_1;
reg notifier_ibuf_sel_1;
wire enable_vdda_h_and_enable_h = ENABLE_VDDA_H==1'b1 && ENABLE_H==1'b1;
specify
if ( VTRIP_SEL[1]==1'b1) ( INP_DIS[1] => IN[1] ) = (3.422:0:3.422 , 2.337:0:2.337);
if ( VTRIP_SEL[1]==1'b1) ( INP_DIS[1] => IN_H[1] ) = (3.271:0:3.271 , 2.210:0:2.210);
if ( VTRIP_SEL[1]==1'b1) ( PAD[1] => IN[1] ) = (0.798:0:0.798 , 0.959:0:0.959);
if ( VTRIP_SEL[1]==1'b1) ( PAD[1] => IN_H[1] ) = (0.931:0:0.931 , 0.935:0:0.935);
if ( VTRIP_SEL[0]==1'b1) ( INP_DIS[0] => IN[0] ) = (3.422:0:3.422 , 2.337:0:2.337);
if ( VTRIP_SEL[0]==1'b1) ( INP_DIS[0] => IN_H[0] ) = (3.271:0:3.271 , 2.210:0:2.210);
if ( VTRIP_SEL[0]==1'b1) ( PAD[0] => IN[0] ) = (0.798:0:0.798 , 0.959:0:0.959);
if ( VTRIP_SEL[0]==1'b1) ( PAD[0] => IN_H[0] ) = (0.931:0:0.931 , 0.935:0:0.935);
if ( VTRIP_SEL[1]==1'b0) ( INP_DIS[1] => IN[1] ) = (3.422:0:3.422 , 2.337:0:2.337);
if ( VTRIP_SEL[1]==1'b0) ( INP_DIS[1] => IN_H[1] ) = (3.271:0:3.271 , 2.209:0:2.209);
if ( VTRIP_SEL[1]==1'b0) ( PAD[1] => IN[1] ) = (0.816:0:0.816 , 0.866:0:0.866);
if ( VTRIP_SEL[1]==1'b0) ( PAD[1] => IN_H[1] ) = (0.950:0:0.950 , 0.841:0:0.841);
if ( VTRIP_SEL[0]==1'b0) ( INP_DIS[0] => IN[0] ) = (3.422:0:3.422 , 2.337:0:2.337);
if ( VTRIP_SEL[0]==1'b0) ( INP_DIS[0] => IN_H[0] ) = (3.271:0:3.271 , 2.209:0:2.209);
if ( VTRIP_SEL[0]==1'b0) ( PAD[0] => IN[0] ) = (0.816:0:0.816 , 0.866:0:0.866);
if ( VTRIP_SEL[0]==1'b0) ( PAD[0] => IN_H[0] ) = (0.950:0:0.950 , 0.841:0:0.841);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b0 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b1 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b0 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b1 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b0 & SLOW[0] == 1'b0 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b0 & SLOW[0] == 1'b1 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b1 & SLOW[0] == 1'b0 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b1 & SLOW[0] == 1'b1 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b0 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b1 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b0 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b1 ) ( OE_N[0] => PAD[0] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b0 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b1 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b0 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b0 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b1 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b0 & SLOW[0] == 1'b0 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b0 & SLOW[0] == 1'b1 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b1 & SLOW[0] == 1'b0 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b0 & DM0[0] == 1'b1 & SLOW[0] == 1'b1 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b0 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b0 & SLOW[0] == 1'b1 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b0 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM0[2] == 1'b1 & DM0[1] == 1'b1 & DM0[0] == 1'b1 & SLOW[0] == 1'b1 & OE_N[0] == 1'b0 ) ( OUT[0] => PAD[0] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b0 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b1 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b0 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b1 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b0 & SLOW[1] == 1'b0 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b0 & SLOW[1] == 1'b1 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b1 & SLOW[1] == 1'b0 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b1 & SLOW[1] == 1'b1 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b0 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b1 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b0 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b1 ) ( OE_N[1] => PAD[1] ) = (0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0 , 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b0 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b1 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b0 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b0 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b1 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b0 & SLOW[1] == 1'b0 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b0 & SLOW[1] == 1'b1 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b1 & SLOW[1] == 1'b0 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b0 & DM1[0] == 1'b1 & SLOW[1] == 1'b1 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b0 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b0 & SLOW[1] == 1'b1 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b0 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
if ( DM1[2] == 1'b1 & DM1[1] == 1'b1 & DM1[0] == 1'b1 & SLOW[1] == 1'b1 & OE_N[1] == 1'b0 ) ( OUT[1] => PAD[1] ) = (0:0:0, 0:0:0);
specparam t_setup=5;
specparam t_hold=5;
$width (posedge HLD_H_N[1], (15.500:0:15.500));
$width (negedge HLD_H_N[1], (15.500:0:15.500));
$width (negedge HLD_H_N[0], (15.500:0:15.500));
$width (posedge HLD_H_N[0], (15.500:0:15.500));
$width (posedge HLD_H_N_REFGEN, (15.500:0:15.500));
$width (negedge HLD_H_N_REFGEN, (15.500:0:15.500));
$width (negedge HLD_OVR[1], (15.500:0:15.500));
$width (posedge HLD_OVR[1], (15.500:0:15.500));
$width (negedge HLD_OVR[0], (15.500:0:15.500));
$width (posedge HLD_OVR[0], (15.500:0:15.500));
$setuphold (negedge ENABLE_H, posedge HLD_H_N_REFGEN, t_setup, t_hold, notifier_enable_h_refgen);
$setuphold (negedge ENABLE_H, negedge HLD_H_N_REFGEN, t_setup, t_hold, notifier_enable_h_refgen);
$setuphold (posedge ENABLE_H, posedge HLD_H_N_REFGEN, t_setup, t_hold, notifier_enable_h_refgen);
$setuphold (posedge ENABLE_H, negedge HLD_H_N_REFGEN, t_setup, t_hold, notifier_enable_h_refgen);
$setuphold (negedge HLD_H_N_REFGEN, posedge VTRIP_SEL_REFGEN, t_setup, t_hold, notifier_vtrip_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VTRIP_SEL_REFGEN, t_setup, t_hold, notifier_vtrip_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VREG_EN_REFGEN, t_setup, t_hold, notifier_vreg_en_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VREG_EN_REFGEN, t_setup, t_hold, notifier_vreg_en_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge IBUF_SEL_REFGEN, t_setup, t_hold, notifier_ibuf_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge IBUF_SEL_REFGEN, t_setup, t_hold, notifier_ibuf_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VOH_SEL[0], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VOH_SEL[1], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge VOH_SEL[2], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VOH_SEL[0], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VOH_SEL[1], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge VOH_SEL[2], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, posedge DFT_REFGEN, t_setup, t_hold, notifier_dft_refgen, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge HLD_H_N_REFGEN, negedge DFT_REFGEN, t_setup, t_hold, notifier_dft_refgen, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VTRIP_SEL_REFGEN, t_setup, t_hold, notifier_vtrip_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VTRIP_SEL_REFGEN, t_setup, t_hold, notifier_vtrip_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VREG_EN_REFGEN, t_setup, t_hold, notifier_vreg_en_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VREG_EN_REFGEN, t_setup, t_hold, notifier_vreg_en_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge IBUF_SEL_REFGEN, t_setup, t_hold, notifier_ibuf_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge IBUF_SEL_REFGEN, t_setup, t_hold, notifier_ibuf_sel_refgen, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VREF_SEL[0], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VREF_SEL[1], t_setup, t_hold, notifier_vref_sel_int, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VOH_SEL[0], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VOH_SEL[1], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge VOH_SEL[2], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VOH_SEL[0], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VOH_SEL[1], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge VOH_SEL[2], t_setup, t_hold, notifier_voh_sel, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, posedge DFT_REFGEN, t_setup, t_hold, notifier_dft_refgen, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (posedge HLD_H_N_REFGEN, negedge DFT_REFGEN, t_setup, t_hold, notifier_dft_refgen, enable_vdda_h_and_enable_h==1'b1, enable_vdda_h_and_enable_h==1'b1);
$setuphold (negedge ENABLE_H, posedge HLD_H_N[0], t_setup, t_hold, notifier_enable_h_0);
$setuphold (negedge ENABLE_H, negedge HLD_H_N[0], t_setup, t_hold, notifier_enable_h_0);
$setuphold (posedge ENABLE_H, posedge HLD_H_N[0], t_setup, t_hold, notifier_enable_h_0);
$setuphold (posedge ENABLE_H, negedge HLD_H_N[0], t_setup, t_hold, notifier_enable_h_0);
$setuphold (negedge HLD_H_N[0], posedge HLD_OVR[0], t_setup, t_hold, notifier_hld_ovr_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge HLD_OVR[0], t_setup, t_hold, notifier_hld_ovr_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge DM0[2], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge DM0[2], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge DM0[1], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge DM0[1], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge DM0[0], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge DM0[0], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge INP_DIS[0], t_setup, t_hold, notifier_inp_dis_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge INP_DIS[0], t_setup, t_hold, notifier_inp_dis_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge VTRIP_SEL[0], t_setup, t_hold, notifier_vtrip_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge VTRIP_SEL[0], t_setup, t_hold, notifier_vtrip_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge SLOW[0], t_setup, t_hold, notifier_slow_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge SLOW[0], t_setup, t_hold, notifier_slow_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge OE_N[0], t_setup, t_hold, notifier_oe_n_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge OE_N[0], t_setup, t_hold, notifier_oe_n_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge OUT[0], t_setup, t_hold, notifier_out_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge OUT[0], t_setup, t_hold, notifier_out_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge VREG_EN[0], t_setup, t_hold, notifier_vreg_en_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge VREG_EN[0], t_setup, t_hold, notifier_vreg_en_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], posedge IBUF_SEL[0], t_setup, t_hold, notifier_ibuf_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[0], negedge IBUF_SEL[0], t_setup, t_hold, notifier_ibuf_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge HLD_OVR[0], t_setup, t_hold, notifier_hld_ovr_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge HLD_OVR[0], t_setup, t_hold, notifier_hld_ovr_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge DM0[2], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge DM0[2], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge DM0[1], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge DM0[1], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge DM0[0], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge DM0[0], t_setup, t_hold, notifier_dm_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge INP_DIS[0], t_setup, t_hold, notifier_inp_dis_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge INP_DIS[0], t_setup, t_hold, notifier_inp_dis_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge VTRIP_SEL[0], t_setup, t_hold, notifier_vtrip_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge VTRIP_SEL[0], t_setup, t_hold, notifier_vtrip_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge SLOW[0], t_setup, t_hold, notifier_slow_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge SLOW[0], t_setup, t_hold, notifier_slow_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge OE_N[0], t_setup, t_hold, notifier_oe_n_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge OE_N[0], t_setup, t_hold, notifier_oe_n_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge OUT[0], t_setup, t_hold, notifier_out_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge OUT[0], t_setup, t_hold, notifier_out_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge VREG_EN[0], t_setup, t_hold, notifier_vreg_en_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge VREG_EN[0], t_setup, t_hold, notifier_vreg_en_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], posedge IBUF_SEL[0], t_setup, t_hold, notifier_ibuf_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[0], negedge IBUF_SEL[0], t_setup, t_hold, notifier_ibuf_sel_0, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge ENABLE_H, posedge HLD_H_N[1], t_setup, t_hold, notifier_enable_h_1);
$setuphold (negedge ENABLE_H, negedge HLD_H_N[1], t_setup, t_hold, notifier_enable_h_1);
$setuphold (posedge ENABLE_H, posedge HLD_H_N[1], t_setup, t_hold, notifier_enable_h_1);
$setuphold (posedge ENABLE_H, negedge HLD_H_N[1], t_setup, t_hold, notifier_enable_h_1);
$setuphold (negedge HLD_H_N[1], posedge HLD_OVR[1], t_setup, t_hold, notifier_hld_ovr_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge HLD_OVR[1], t_setup, t_hold, notifier_hld_ovr_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge DM1[2], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge DM1[2], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge DM1[1], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge DM1[1], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge DM1[0], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge DM1[0], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge INP_DIS[1], t_setup, t_hold, notifier_inp_dis_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge INP_DIS[1], t_setup, t_hold, notifier_inp_dis_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge VTRIP_SEL[1], t_setup, t_hold, notifier_vtrip_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge VTRIP_SEL[1], t_setup, t_hold, notifier_vtrip_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge SLOW[1], t_setup, t_hold, notifier_slow_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge SLOW[1], t_setup, t_hold, notifier_slow_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge OE_N[1], t_setup, t_hold, notifier_oe_n_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge OE_N[1], t_setup, t_hold, notifier_oe_n_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge OUT[1], t_setup, t_hold, notifier_out_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge OUT[1], t_setup, t_hold, notifier_out_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge VREG_EN[1], t_setup, t_hold, notifier_vreg_en_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge VREG_EN[1], t_setup, t_hold, notifier_vreg_en_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], posedge IBUF_SEL[1], t_setup, t_hold, notifier_ibuf_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (negedge HLD_H_N[1], negedge IBUF_SEL[1], t_setup, t_hold, notifier_ibuf_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge HLD_OVR[1], t_setup, t_hold, notifier_hld_ovr_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge HLD_OVR[1], t_setup, t_hold, notifier_hld_ovr_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge DM1[2], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge DM1[2], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge DM1[1], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge DM1[1], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge DM1[0], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge DM1[0], t_setup, t_hold, notifier_dm_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge INP_DIS[1], t_setup, t_hold, notifier_inp_dis_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge INP_DIS[1], t_setup, t_hold, notifier_inp_dis_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge VTRIP_SEL[1], t_setup, t_hold, notifier_vtrip_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge VTRIP_SEL[1], t_setup, t_hold, notifier_vtrip_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge SLOW[1], t_setup, t_hold, notifier_slow_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge SLOW[1], t_setup, t_hold, notifier_slow_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge OE_N[1], t_setup, t_hold, notifier_oe_n_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge OE_N[1], t_setup, t_hold, notifier_oe_n_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge OUT[1], t_setup, t_hold, notifier_out_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge OUT[1], t_setup, t_hold, notifier_out_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge VREG_EN[1], t_setup, t_hold, notifier_vreg_en_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge VREG_EN[1], t_setup, t_hold, notifier_vreg_en_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], posedge IBUF_SEL[1], t_setup, t_hold, notifier_ibuf_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
$setuphold (posedge HLD_H_N[1], negedge IBUF_SEL[1], t_setup, t_hold, notifier_ibuf_sel_1, ENABLE_H==1'b1, ENABLE_H==1'b1);
endspecify
assign REFGEN.NOTIFIER_ENABLE_H = notifier_enable_h_refgen;
assign REFGEN.NOTIFIER_VTRIP_SEL = notifier_vtrip_sel_refgen;
assign REFGEN.NOTIFIER_VREG_EN = notifier_vreg_en_refgen;
assign REFGEN.NOTIFIER_IBUF_SEL = notifier_ibuf_sel_refgen;
assign REFGEN.notifier_vref_sel = notifier_vref_sel;
assign REFGEN.notifier_vref_sel_int = notifier_vref_sel_int;
assign REFGEN.notifier_voh_sel = notifier_voh_sel;
assign REFGEN.notifier_dft_refgen = notifier_dft_refgen;
assign SIO_PAIR_0_.NOTIFIER_ENABLE_H = notifier_enable_h_0;
assign SIO_PAIR_0_.NOTIFIER_HLD_OVR = notifier_hld_ovr_0;
assign SIO_PAIR_0_.NOTIFIER_DM = notifier_dm_0;
assign SIO_PAIR_0_.NOTIFIER_INP_DIS = notifier_inp_dis_0;
assign SIO_PAIR_0_.NOTIFIER_VTRIP_SEL = notifier_vtrip_sel_0;
assign SIO_PAIR_0_.NOTIFIER_SLOW = notifier_slow_0;
assign SIO_PAIR_0_.NOTIFIER_OE_N = notifier_oe_n_0;
assign SIO_PAIR_0_.NOTIFIER_OUT = notifier_out_0;
assign SIO_PAIR_0_.NOTIFIER_VREG_EN = notifier_vreg_en_0;
assign SIO_PAIR_0_.NOTIFIER_IBUF_SEL = notifier_ibuf_sel_0;
assign SIO_PAIR_1_.NOTIFIER_ENABLE_H = notifier_enable_h_1;
assign SIO_PAIR_1_.NOTIFIER_HLD_OVR = notifier_hld_ovr_1;
assign SIO_PAIR_1_.NOTIFIER_DM = notifier_dm_1;
assign SIO_PAIR_1_.NOTIFIER_INP_DIS = notifier_inp_dis_1;
assign SIO_PAIR_1_.NOTIFIER_VTRIP_SEL = notifier_vtrip_sel_1;
assign SIO_PAIR_1_.NOTIFIER_SLOW = notifier_slow_1;
assign SIO_PAIR_1_.NOTIFIER_OE_N = notifier_oe_n_1;
assign SIO_PAIR_1_.NOTIFIER_OUT = notifier_out_1;
assign SIO_PAIR_1_.NOTIFIER_VREG_EN = notifier_vreg_en_1;
assign SIO_PAIR_1_.NOTIFIER_IBUF_SEL = notifier_ibuf_sel_1;
sky130_fd_io__top_refgen_new REFGEN (
.VOH_SEL (VOH_SEL[2:0]),
.VREF_SEL (VREF_SEL[1:0]),
.VOHREF (VOHREF),
.VINREF_DFT (VINREF_DFT),
.VOUTREF_DFT (VOUTREF_DFT),
.DFT_REFGEN (DFT_REFGEN),
.AMUXBUS_A (AMUXBUS_A),
.AMUXBUS_B (AMUXBUS_B),
.VOUTREF (VOUTREF),
.VREG_EN (VREG_EN_REFGEN),
.IBUF_SEL (IBUF_SEL_REFGEN),
.VINREF (VINREF),
.VTRIP_SEL (VTRIP_SEL_REFGEN),
.ENABLE_H (ENABLE_H),
.ENABLE_VDDA_H (ENABLE_VDDA_H),
.HLD_H_N (HLD_H_N_REFGEN),
.REFLEAK_BIAS (REFLEAK_BIAS)
);
sky130_fd_io__top_sio SIO_PAIR_1_ (
.PAD (PAD[1]),
.IN_H (IN_H[1]),
.DM (DM1[2:0]),
.HLD_H_N (HLD_H_N[1]),
.PAD_A_ESD_1_H (PAD_A_ESD_1_H[1]),
.PAD_A_ESD_0_H (PAD_A_ESD_0_H[1]),
.ENABLE_H (ENABLE_H),
.OUT (OUT[1]),
.OE_N (OE_N[1]),
.SLOW (SLOW[1]),
.VTRIP_SEL (VTRIP_SEL[1]),
.INP_DIS (INP_DIS[1]),
.TIE_LO_ESD (TIE_LO_ESD[1]),
.IN (IN[1]),
.VINREF (VINREF),
.VOUTREF (VOUTREF),
.REFLEAK_BIAS (REFLEAK_BIAS),
.PAD_A_NOESD_H (PAD_A_NOESD_H[1]),
.VREG_EN (VREG_EN[1]),
.IBUF_SEL (IBUF_SEL[1]),
.HLD_OVR (HLD_OVR[1])
);
sky130_fd_io__top_sio SIO_PAIR_0_ (
.PAD (PAD[0]),
.IN_H (IN_H[0]),
.DM (DM0[2:0]),
.HLD_H_N (HLD_H_N[0]),
.PAD_A_ESD_1_H (PAD_A_ESD_1_H[0]),
.PAD_A_ESD_0_H (PAD_A_ESD_0_H[0]),
.ENABLE_H (ENABLE_H),
.OUT (OUT[0]),
.OE_N (OE_N[0]),
.SLOW (SLOW[0]),
.VTRIP_SEL (VTRIP_SEL[0]),
.INP_DIS (INP_DIS[0]),
.TIE_LO_ESD (TIE_LO_ESD[0]),
.IN (IN[0]),
.VINREF (VINREF),
.VOUTREF (VOUTREF),
.REFLEAK_BIAS (REFLEAK_BIAS),
.PAD_A_NOESD_H (PAD_A_NOESD_H[0]),
.VREG_EN (VREG_EN[0]),
.IBUF_SEL (IBUF_SEL[0]),
.HLD_OVR (HLD_OVR[0])
);
endmodule
|
/*
Copyright (C) 2016 Cedric Orban
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
`include "DeepGATE_include.v"
module DeepGATE_top(
// 50MHz clock input
input clk,
// Input from reset button (active low)
input rst_n,
// cclk input from AVR, high when AVR is ready
input cclk,
// Outputs to the 8 onboard LEDs
output wire [7:0]led,
// Raspberry Pi Interface
input RaspberrySPI_SS,
input RaspberrySPI_SCLK,
input RaspberrySPI_MOSI,
output reg RaspberrySPI_MISO,
// AVR SPI connections
output spi_miso,
input spi_ss,
input spi_mosi,
input spi_sck,
// AVR ADC channel select
output [3:0] spi_channel,
// Serial connections
input avr_tx, // AVR Tx => FPGA Rx
output avr_rx, // AVR Rx => FPGA Tx
input avr_rx_busy, // AVR Rx buffer full
//SDRAM interface
output sdram_clk,
output sdram_cle,
output sdram_dqm,
output sdram_cs,
output sdram_we,
output sdram_cas,
output sdram_ras,
output [1:0] sdram_ba,
output [12:0] sdram_a,
inout [7:0] sdram_dq
);
`include "networkParam_include.v"
wire rst = ~rst_n; //becomes active high
wire [7:0] tx_data;
wire tx_busy;
wire [7:0] rx_data;
wire new_rx_data;
reg [7:0] tx_data_buffer = 0;
reg [7:0] rx_data_buffer = 0;
reg new_tx_data = 0;
avr_interface AVR (
.clk (clk),
.rst (rst),
.cclk (cclk),
.spi_miso (spi_miso),
.spi_mosi (spi_mosi),
.spi_sck (spi_sck),
.spi_ss (spi_ss),
.spi_channel (spi_channel),
.tx (avr_rx),
.rx (avr_tx),
.channel (4'd15),
.tx_data (tx_data),
.new_tx_data (new_tx_data),
.tx_busy (tx_busy),
.tx_block (avr_rx_busy),
.rx_data (rx_data),
.new_rx_data (new_rx_data)
);
wire [31:0] sdramDataOut;
wire [22:0] sdramAddr;
wire sdramBusy;
wire sdramOutValid;
reg [31:0] sdramDataIn;
reg sdramInValid;
reg sdramRW = 0;
sdram SDRAM (
.clk (clk),
.rst (rst),
// these signals go directly to the IO pins
.sdram_clk (sdram_clk),
.sdram_cle (sdram_cle),
.sdram_cs (sdram_cs),
.sdram_cas (sdram_cas),
.sdram_ras (sdram_ras),
.sdram_we (sdram_we),
.sdram_dqm (sdram_dqm),
.sdram_ba (sdram_ba),
.sdram_a (sdram_a),
.sdram_dq (sdram_dq),
// User interface
.addr (sdramAddr), // address to read/write
.rw (sdramRW), // 1 = write, 0 = read
.data_in (sdramDataIn), // data from a read
.data_out (sdramDataOut), // data for a write
.busy (sdramBusy), // controller is busy when high
.in_valid (sdramInValid), // pulse high to initiate a read/write
.out_valid (sdramOutValid) // pulses high when data from read is valid
);
wire [7:0] networkOut;
wire networkIdle;
wire networkDataReady;
wire [7:0] networkTestData;
reg [31:0] transferCnt = 0;
reg [7:0] testData = 0;
reg [7:0] networkAddr = 0;
reg procBegin = 0;
reg procBeginFlag = 0;
reg networkWriteEn = 0;
reg [7:0] networkDataIn = 0;
tileNetwork MLPNN( //multi-layer perceptron neural network
.clk (clk),
.procBegin (procBegin),
.dataIn (networkDataIn),
.wr (networkWriteEn),
.wr_addr (networkAddr),
.weightDataIn (48'hBABEFACEBABE),
.networkIdle (networkIdle),
.networkOut (networkOut),
.dataReady (networkDataReady)
);
reg start = 0;
reg transfer = 0;
reg dataSent = 0;
reg first = 0;
reg [22:0] readAddr = 0;
reg [22:0] writeAddr = 0;
reg [22:0] stopAddr = 0;
reg [23:0] command = 0;
reg [79:0] test_reg = 0;
reg [31:0] readCnt = 0;
reg [7:0] dataRAM [783 : 0];
reg [7:0] hold = 0;
//initial begin
//$readmemh("C:/Users/cedric/Documents/UCF/C Programs/DeepGateDataGeneration/DeepGateDataGeneration/randomNetworkData.txt", dataRAM);
//end
assign tx_data = !start ? tx_data_buffer : test_reg[7:0];
assign led = rx_data_buffer;
assign sdramAddr = !transfer ? writeAddr : readAddr;
always@(posedge clk) begin
sdramRW <= 0;
sdramInValid <= 0;
procBegin <= 0;
new_tx_data <= 0;
if(new_rx_data && !transfer) begin
writeAddr <= writeAddr + 1'b1;
rx_data_buffer <= rx_data;
dataRAM[writeAddr] <= rx_data;
command <= {command[15:0], rx_data};
end
else if(!tx_busy && !new_tx_data && (transfer || start)) begin
new_tx_data <= 1'b1;
readAddr <= readAddr + 1'b1;
tx_data_buffer <= dataRAM[readAddr];
end
if(writeAddr == 784) begin
writeAddr <= 0;
transfer <= 1;
end
if(readAddr == 784) begin
transfer <= 0;
readAddr <= 0;
end
if(transfer)
readCnt <= readCnt + 1'b1;
//if(sdramOutValid)
//tx_data_buffer <= sdramDataOut;
if(!sdramBusy && !sdramInValid) begin
if(!transfer) begin
sdramDataIn <= rx_data_buffer;
sdramRW <= 1;
end
sdramInValid <= 1;
end
/*
if(command == 24'h242424) begin //$$$ in ASCII
//transfer <= 1;
writeAddr <= 0;
stopAddr <= writeAddr;
command <= 0;
end
*/
if(command == 24'h262626) //&&& in ASCII
start <= 1;
if(networkDataReady)
test_reg <= {test_reg[71:0], networkOut};
else if(!networkDataReady && !tx_busy && !new_tx_data)
test_reg <= {test_reg[71:0], test_reg[79:72]} ;
if(start && networkIdle && !procBeginFlag) begin
procBegin <= 1;
procBeginFlag <= 1;
end
if(((procBeginFlag && !procBegin && transferCnt == 0) || (transferCnt > 0 && transferCnt < 784)) && !hold) begin
transferCnt <= transferCnt + 1'b1;
networkDataIn <= dataRAM[transferCnt];
end
if(transferCnt == 784) begin
hold <= hold + 1'b1;
if(hold == 10) begin
transferCnt <= 0;
hold <= 0;
end
end
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Expert(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Wed Oct 19 14:30:11 2016
/////////////////////////////////////////////////////////////
module add_sub_carry_out_W26_DW01_add_1 ( A, B, CI, SUM, CO );
input [26:0] A;
input [26:0] B;
output [26:0] SUM;
input CI;
output CO;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n12, n13, n14, n15, n16, n17,
n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45,
n46, n47, n48, n49, n50, n51, n53, n54, n55, n56, n57, n58, n59, n60,
n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n76;
CMPR32X2TS U2 ( .A(A[25]), .B(B[25]), .C(n12), .CO(SUM[26]), .S(SUM[25]) );
AFHCINX2TS U3 ( .CIN(n13), .B(A[24]), .A(B[24]), .S(SUM[24]), .CO(n12) );
AFHCONX2TS U4 ( .A(B[23]), .B(A[23]), .CI(n14), .CON(n13), .S(SUM[23]) );
AFHCINX2TS U5 ( .CIN(n15), .B(A[22]), .A(B[22]), .S(SUM[22]), .CO(n14) );
AFHCONX2TS U6 ( .A(B[21]), .B(A[21]), .CI(n16), .CON(n15), .S(SUM[21]) );
AFHCINX2TS U7 ( .CIN(n17), .B(A[20]), .A(B[20]), .S(SUM[20]), .CO(n16) );
AFHCONX2TS U8 ( .A(B[19]), .B(A[19]), .CI(n18), .CON(n17), .S(SUM[19]) );
AFHCINX2TS U9 ( .CIN(n19), .B(A[18]), .A(B[18]), .S(SUM[18]), .CO(n18) );
AFHCONX2TS U10 ( .A(B[17]), .B(A[17]), .CI(n20), .CON(n19), .S(SUM[17]) );
AFHCINX2TS U11 ( .CIN(n21), .B(A[16]), .A(B[16]), .S(SUM[16]), .CO(n20) );
AFHCONX2TS U12 ( .A(B[15]), .B(A[15]), .CI(n22), .CON(n21), .S(SUM[15]) );
AFHCINX2TS U13 ( .CIN(n23), .B(A[14]), .A(B[14]), .S(SUM[14]), .CO(n22) );
AFHCONX2TS U14 ( .A(B[13]), .B(A[13]), .CI(n24), .CON(n23), .S(SUM[13]) );
AFHCINX2TS U15 ( .CIN(n25), .B(A[12]), .A(B[12]), .S(SUM[12]), .CO(n24) );
AFHCONX2TS U16 ( .A(B[11]), .B(A[11]), .CI(n26), .CON(n25), .S(SUM[11]) );
AFHCINX2TS U17 ( .CIN(n27), .B(A[10]), .A(B[10]), .S(SUM[10]), .CO(n26) );
XOR2X1TS U26 ( .A(n35), .B(n2), .Y(SUM[8]) );
XOR2X1TS U43 ( .A(n46), .B(n4), .Y(SUM[6]) );
XOR2X1TS U49 ( .A(n51), .B(n5), .Y(SUM[5]) );
XOR2X1TS U74 ( .A(n65), .B(n8), .Y(SUM[2]) );
XOR2X1TS U80 ( .A(n9), .B(n70), .Y(SUM[1]) );
NOR2X1TS U95 ( .A(A[4]), .B(B[4]), .Y(n54) );
NOR2X1TS U96 ( .A(A[2]), .B(B[2]), .Y(n63) );
NOR2X1TS U97 ( .A(A[6]), .B(B[6]), .Y(n44) );
NOR2X1TS U98 ( .A(A[8]), .B(B[8]), .Y(n33) );
NOR2X1TS U99 ( .A(A[3]), .B(B[3]), .Y(n60) );
NOR2X1TS U100 ( .A(A[7]), .B(B[7]), .Y(n41) );
NOR2X1TS U101 ( .A(A[5]), .B(B[5]), .Y(n49) );
NOR2X1TS U102 ( .A(A[9]), .B(B[9]), .Y(n30) );
INVX2TS U103 ( .A(n36), .Y(n35) );
AOI21X1TS U104 ( .A0(n56), .A1(n47), .B0(n48), .Y(n46) );
INVX2TS U105 ( .A(n57), .Y(n56) );
INVX2TS U106 ( .A(n66), .Y(n65) );
AOI21X1TS U107 ( .A0(n58), .A1(n66), .B0(n59), .Y(n57) );
NOR2X1TS U108 ( .A(n63), .B(n60), .Y(n58) );
OAI21X1TS U109 ( .A0(n60), .A1(n64), .B0(n61), .Y(n59) );
OAI21X1TS U110 ( .A0(n67), .A1(n70), .B0(n68), .Y(n66) );
OAI21X1TS U111 ( .A0(n57), .A1(n37), .B0(n38), .Y(n36) );
NAND2X1TS U112 ( .A(n47), .B(n39), .Y(n37) );
AOI21X1TS U113 ( .A0(n39), .A1(n48), .B0(n40), .Y(n38) );
NOR2X1TS U114 ( .A(n44), .B(n41), .Y(n39) );
OAI21X1TS U115 ( .A0(n49), .A1(n55), .B0(n50), .Y(n48) );
OAI21X1TS U116 ( .A0(n41), .A1(n45), .B0(n42), .Y(n40) );
NOR2X1TS U117 ( .A(n54), .B(n49), .Y(n47) );
OAI21X1TS U118 ( .A0(n35), .A1(n33), .B0(n34), .Y(n32) );
OAI21X1TS U119 ( .A0(n65), .A1(n63), .B0(n64), .Y(n62) );
OAI21X1TS U120 ( .A0(n46), .A1(n44), .B0(n45), .Y(n43) );
AOI21X1TS U121 ( .A0(n56), .A1(n76), .B0(n53), .Y(n51) );
INVX2TS U122 ( .A(n55), .Y(n53) );
NAND2X1TS U123 ( .A(n76), .B(n55), .Y(n6) );
NAND2BX1TS U124 ( .AN(n60), .B(n61), .Y(n7) );
NAND2BX1TS U125 ( .AN(n41), .B(n42), .Y(n3) );
NAND2BX1TS U126 ( .AN(n30), .B(n31), .Y(n1) );
NAND2BX1TS U127 ( .AN(n67), .B(n68), .Y(n9) );
NAND2BX1TS U128 ( .AN(n63), .B(n64), .Y(n8) );
NAND2BX1TS U129 ( .AN(n44), .B(n45), .Y(n4) );
NAND2BX1TS U130 ( .AN(n33), .B(n34), .Y(n2) );
NAND2BX1TS U131 ( .AN(n49), .B(n50), .Y(n5) );
INVX2TS U132 ( .A(n54), .Y(n76) );
AOI21X1TS U133 ( .A0(n36), .A1(n28), .B0(n29), .Y(n27) );
NOR2X1TS U134 ( .A(n33), .B(n30), .Y(n28) );
OAI21X1TS U135 ( .A0(n30), .A1(n34), .B0(n31), .Y(n29) );
NAND2X1TS U136 ( .A(A[4]), .B(B[4]), .Y(n55) );
NOR2X1TS U137 ( .A(A[1]), .B(B[1]), .Y(n67) );
NAND2X1TS U138 ( .A(A[2]), .B(B[2]), .Y(n64) );
NAND2X1TS U139 ( .A(A[6]), .B(B[6]), .Y(n45) );
NAND2X1TS U140 ( .A(A[8]), .B(B[8]), .Y(n34) );
NAND2X1TS U141 ( .A(A[0]), .B(B[0]), .Y(n70) );
NAND2X1TS U142 ( .A(A[1]), .B(B[1]), .Y(n68) );
NAND2X1TS U143 ( .A(A[3]), .B(B[3]), .Y(n61) );
NAND2X1TS U144 ( .A(A[5]), .B(B[5]), .Y(n50) );
NAND2X1TS U145 ( .A(A[7]), .B(B[7]), .Y(n42) );
NAND2X1TS U146 ( .A(A[9]), .B(B[9]), .Y(n31) );
XNOR2X1TS U147 ( .A(n32), .B(n1), .Y(SUM[9]) );
NAND2BX1TS U148 ( .AN(n69), .B(n70), .Y(n10) );
NOR2X1TS U149 ( .A(A[0]), .B(B[0]), .Y(n69) );
INVX2TS U150 ( .A(n10), .Y(SUM[0]) );
XNOR2X1TS U151 ( .A(n62), .B(n7), .Y(SUM[3]) );
XNOR2X1TS U152 ( .A(n56), .B(n6), .Y(SUM[4]) );
XNOR2X1TS U153 ( .A(n43), .B(n3), .Y(SUM[7]) );
endmodule
module add_sub_carry_out_W26_DW01_sub_1 ( A, B, CI, DIFF, CO );
input [26:0] A;
input [26:0] B;
output [26:0] DIFF;
input CI;
output CO;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n52, n53, n54, n55, n56, n57, n58, n59,
n60, n61, n62, n63, n64, n65, n66, n67, n68, n74, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103;
CMPR32X2TS U2 ( .A(n78), .B(A[25]), .C(n11), .CO(n10), .S(DIFF[25]) );
AFHCINX2TS U3 ( .CIN(n12), .B(n79), .A(A[24]), .S(DIFF[24]), .CO(n11) );
AFHCONX2TS U4 ( .A(A[23]), .B(n80), .CI(n13), .CON(n12), .S(DIFF[23]) );
AFHCINX2TS U5 ( .CIN(n14), .B(n81), .A(A[22]), .S(DIFF[22]), .CO(n13) );
AFHCONX2TS U6 ( .A(A[21]), .B(n82), .CI(n15), .CON(n14), .S(DIFF[21]) );
AFHCINX2TS U7 ( .CIN(n16), .B(n83), .A(A[20]), .S(DIFF[20]), .CO(n15) );
AFHCONX2TS U8 ( .A(A[19]), .B(n84), .CI(n17), .CON(n16), .S(DIFF[19]) );
AFHCINX2TS U9 ( .CIN(n18), .B(n85), .A(A[18]), .S(DIFF[18]), .CO(n17) );
AFHCONX2TS U10 ( .A(A[17]), .B(n86), .CI(n19), .CON(n18), .S(DIFF[17]) );
AFHCINX2TS U11 ( .CIN(n20), .B(n87), .A(A[16]), .S(DIFF[16]), .CO(n19) );
AFHCONX2TS U12 ( .A(A[15]), .B(n88), .CI(n21), .CON(n20), .S(DIFF[15]) );
AFHCINX2TS U13 ( .CIN(n22), .B(n89), .A(A[14]), .S(DIFF[14]), .CO(n21) );
AFHCONX2TS U14 ( .A(A[13]), .B(n90), .CI(n23), .CON(n22), .S(DIFF[13]) );
AFHCINX2TS U15 ( .CIN(n24), .B(n91), .A(A[12]), .S(DIFF[12]), .CO(n23) );
AFHCONX2TS U16 ( .A(A[11]), .B(n92), .CI(n25), .CON(n24), .S(DIFF[11]) );
AFHCINX2TS U17 ( .CIN(n26), .B(n93), .A(A[10]), .S(DIFF[10]), .CO(n25) );
XOR2X1TS U26 ( .A(n34), .B(n2), .Y(DIFF[8]) );
XOR2X1TS U43 ( .A(n45), .B(n4), .Y(DIFF[6]) );
XOR2X1TS U49 ( .A(n50), .B(n5), .Y(DIFF[5]) );
XOR2X1TS U74 ( .A(n64), .B(n8), .Y(DIFF[2]) );
XOR2X1TS U80 ( .A(n9), .B(n68), .Y(DIFF[1]) );
NOR2X1TS U118 ( .A(n99), .B(A[4]), .Y(n53) );
NOR2X1TS U119 ( .A(n101), .B(A[2]), .Y(n62) );
NOR2X1TS U120 ( .A(n97), .B(A[6]), .Y(n43) );
NOR2X1TS U121 ( .A(n95), .B(A[8]), .Y(n32) );
NOR2X1TS U122 ( .A(n100), .B(A[3]), .Y(n59) );
NOR2X1TS U123 ( .A(n96), .B(A[7]), .Y(n40) );
NOR2X1TS U124 ( .A(n98), .B(A[5]), .Y(n48) );
NOR2X1TS U125 ( .A(n94), .B(A[9]), .Y(n29) );
AOI21X1TS U126 ( .A0(n55), .A1(n46), .B0(n47), .Y(n45) );
INVX2TS U127 ( .A(n56), .Y(n55) );
INVX2TS U128 ( .A(n35), .Y(n34) );
INVX2TS U129 ( .A(n65), .Y(n64) );
AOI21X1TS U130 ( .A0(n57), .A1(n65), .B0(n58), .Y(n56) );
NOR2X1TS U131 ( .A(n62), .B(n59), .Y(n57) );
OAI21X1TS U132 ( .A0(n59), .A1(n63), .B0(n60), .Y(n58) );
OAI21X1TS U133 ( .A0(n66), .A1(n68), .B0(n67), .Y(n65) );
OAI21X1TS U134 ( .A0(n56), .A1(n36), .B0(n37), .Y(n35) );
NAND2X1TS U135 ( .A(n46), .B(n38), .Y(n36) );
AOI21X1TS U136 ( .A0(n38), .A1(n47), .B0(n39), .Y(n37) );
NOR2X1TS U137 ( .A(n43), .B(n40), .Y(n38) );
OAI21X1TS U138 ( .A0(n48), .A1(n54), .B0(n49), .Y(n47) );
OAI21X1TS U139 ( .A0(n40), .A1(n44), .B0(n41), .Y(n39) );
OAI21X1TS U140 ( .A0(n29), .A1(n33), .B0(n30), .Y(n28) );
NOR2X1TS U141 ( .A(n53), .B(n48), .Y(n46) );
OAI21X1TS U142 ( .A0(n34), .A1(n32), .B0(n33), .Y(n31) );
OAI21X1TS U143 ( .A0(n64), .A1(n62), .B0(n63), .Y(n61) );
OAI21X1TS U144 ( .A0(n45), .A1(n43), .B0(n44), .Y(n42) );
AOI21X1TS U145 ( .A0(n55), .A1(n74), .B0(n52), .Y(n50) );
INVX2TS U146 ( .A(n54), .Y(n52) );
NAND2X1TS U147 ( .A(n74), .B(n54), .Y(n6) );
NAND2BX1TS U148 ( .AN(n59), .B(n60), .Y(n7) );
NAND2BX1TS U149 ( .AN(n40), .B(n41), .Y(n3) );
NAND2BX1TS U150 ( .AN(n29), .B(n30), .Y(n1) );
NAND2BX1TS U151 ( .AN(n62), .B(n63), .Y(n8) );
NAND2BX1TS U152 ( .AN(n43), .B(n44), .Y(n4) );
NAND2BX1TS U153 ( .AN(n32), .B(n33), .Y(n2) );
INVX2TS U154 ( .A(n53), .Y(n74) );
NAND2BX1TS U155 ( .AN(n48), .B(n49), .Y(n5) );
NAND2BX1TS U156 ( .AN(n66), .B(n67), .Y(n9) );
INVX2TS U157 ( .A(B[12]), .Y(n91) );
INVX2TS U158 ( .A(B[14]), .Y(n89) );
INVX2TS U159 ( .A(B[16]), .Y(n87) );
INVX2TS U160 ( .A(B[18]), .Y(n85) );
INVX2TS U161 ( .A(B[20]), .Y(n83) );
INVX2TS U162 ( .A(B[22]), .Y(n81) );
INVX2TS U163 ( .A(B[10]), .Y(n93) );
AOI21X1TS U164 ( .A0(n35), .A1(n27), .B0(n28), .Y(n26) );
NOR2X1TS U165 ( .A(n32), .B(n29), .Y(n27) );
INVX2TS U166 ( .A(B[11]), .Y(n92) );
INVX2TS U167 ( .A(B[13]), .Y(n90) );
INVX2TS U168 ( .A(B[15]), .Y(n88) );
INVX2TS U169 ( .A(B[17]), .Y(n86) );
INVX2TS U170 ( .A(B[19]), .Y(n84) );
INVX2TS U171 ( .A(B[21]), .Y(n82) );
INVX2TS U172 ( .A(B[23]), .Y(n80) );
NAND2X1TS U173 ( .A(n99), .B(A[4]), .Y(n54) );
INVX2TS U174 ( .A(B[24]), .Y(n79) );
NOR2X1TS U175 ( .A(n102), .B(A[1]), .Y(n66) );
INVX2TS U176 ( .A(B[25]), .Y(n78) );
NAND2X1TS U177 ( .A(n101), .B(A[2]), .Y(n63) );
NAND2X1TS U178 ( .A(n97), .B(A[6]), .Y(n44) );
NAND2X1TS U179 ( .A(n95), .B(A[8]), .Y(n33) );
NAND2X1TS U180 ( .A(n102), .B(A[1]), .Y(n67) );
NAND2X1TS U181 ( .A(n100), .B(A[3]), .Y(n60) );
NAND2X1TS U182 ( .A(n98), .B(A[5]), .Y(n49) );
NAND2X1TS U183 ( .A(n96), .B(A[7]), .Y(n41) );
NAND2X1TS U184 ( .A(n94), .B(A[9]), .Y(n30) );
NOR2X1TS U185 ( .A(n103), .B(A[0]), .Y(n68) );
INVX2TS U186 ( .A(n10), .Y(DIFF[26]) );
INVX2TS U187 ( .A(B[1]), .Y(n102) );
INVX2TS U188 ( .A(B[3]), .Y(n100) );
INVX2TS U189 ( .A(B[7]), .Y(n96) );
INVX2TS U190 ( .A(B[5]), .Y(n98) );
INVX2TS U191 ( .A(B[4]), .Y(n99) );
INVX2TS U192 ( .A(B[9]), .Y(n94) );
INVX2TS U193 ( .A(B[2]), .Y(n101) );
INVX2TS U194 ( .A(B[6]), .Y(n97) );
INVX2TS U195 ( .A(B[8]), .Y(n95) );
INVX2TS U196 ( .A(B[0]), .Y(n103) );
XNOR2X1TS U197 ( .A(n31), .B(n1), .Y(DIFF[9]) );
XNOR2X1TS U198 ( .A(n103), .B(A[0]), .Y(DIFF[0]) );
XNOR2X1TS U199 ( .A(n61), .B(n7), .Y(DIFF[3]) );
XNOR2X1TS U200 ( .A(n55), .B(n6), .Y(DIFF[4]) );
XNOR2X1TS U201 ( .A(n42), .B(n3), .Y(DIFF[7]) );
endmodule
module add_sub_carry_out_W26 ( op_mode, Data_A, Data_B, Data_S );
input [25:0] Data_A;
input [25:0] Data_B;
output [26:0] Data_S;
input op_mode;
wire N3, N4, N5, N6, N7, N8, N9, N10, N11, N12, N13, N14, N15, N16, N17,
N18, N19, N20, N21, N22, N23, N24, N25, N26, N27, N28, N29, N30, N31,
N32, N33, N34, N35, N36, N37, N38, N39, N40, N41, N42, N43, N44, N45,
N46, N47, N48, N49, N50, N51, N52, N53, N54, N55, N56, n1, n2;
add_sub_carry_out_W26_DW01_add_1 add_36 ( .A({1'b0, Data_A}), .B({1'b0,
Data_B}), .CI(1'b0), .SUM({N56, N55, N54, N53, N52, N51, N50, N49, N48,
N47, N46, N45, N44, N43, N42, N41, N40, N39, N38, N37, N36, N35, N34,
N33, N32, N31, N30}) );
add_sub_carry_out_W26_DW01_sub_1 sub_34 ( .A({1'b0, Data_A}), .B({1'b0,
Data_B}), .CI(1'b0), .DIFF({N29, N28, N27, N26, N25, N24, N23, N22,
N21, N20, N19, N18, N17, N16, N15, N14, N13, N12, N11, N10, N9, N8, N7,
N6, N5, N4, N3}) );
CLKBUFX2TS U3 ( .A(n1), .Y(n2) );
CLKMX2X2TS U4 ( .A(N56), .B(N29), .S0(op_mode), .Y(Data_S[26]) );
CLKMX2X2TS U5 ( .A(N53), .B(N26), .S0(op_mode), .Y(Data_S[23]) );
CLKMX2X2TS U6 ( .A(N54), .B(N27), .S0(op_mode), .Y(Data_S[24]) );
CLKMX2X2TS U7 ( .A(N55), .B(N28), .S0(op_mode), .Y(Data_S[25]) );
CLKMX2X2TS U8 ( .A(N48), .B(N21), .S0(n1), .Y(Data_S[18]) );
CLKMX2X2TS U9 ( .A(N49), .B(N22), .S0(n1), .Y(Data_S[19]) );
CLKMX2X2TS U10 ( .A(N50), .B(N23), .S0(op_mode), .Y(Data_S[20]) );
CLKMX2X2TS U11 ( .A(N51), .B(N24), .S0(op_mode), .Y(Data_S[21]) );
CLKMX2X2TS U12 ( .A(N52), .B(N25), .S0(op_mode), .Y(Data_S[22]) );
CLKMX2X2TS U13 ( .A(N44), .B(N17), .S0(op_mode), .Y(Data_S[14]) );
CLKMX2X2TS U14 ( .A(N45), .B(N18), .S0(op_mode), .Y(Data_S[15]) );
CLKMX2X2TS U15 ( .A(N46), .B(N19), .S0(n1), .Y(Data_S[16]) );
CLKMX2X2TS U16 ( .A(N47), .B(N20), .S0(n1), .Y(Data_S[17]) );
CLKMX2X2TS U17 ( .A(N36), .B(N9), .S0(n2), .Y(Data_S[6]) );
CLKMX2X2TS U18 ( .A(N39), .B(N12), .S0(n2), .Y(Data_S[9]) );
CLKMX2X2TS U19 ( .A(N40), .B(N13), .S0(n1), .Y(Data_S[10]) );
CLKMX2X2TS U20 ( .A(N41), .B(N14), .S0(n1), .Y(Data_S[11]) );
CLKMX2X2TS U21 ( .A(N42), .B(N15), .S0(n1), .Y(Data_S[12]) );
CLKMX2X2TS U22 ( .A(N43), .B(N16), .S0(n1), .Y(Data_S[13]) );
CLKMX2X2TS U23 ( .A(N30), .B(N3), .S0(n2), .Y(Data_S[0]) );
CLKMX2X2TS U24 ( .A(N31), .B(N4), .S0(n2), .Y(Data_S[1]) );
CLKMX2X2TS U25 ( .A(N32), .B(N5), .S0(n2), .Y(Data_S[2]) );
CLKMX2X2TS U26 ( .A(N33), .B(N6), .S0(n2), .Y(Data_S[3]) );
CLKMX2X2TS U27 ( .A(N34), .B(N7), .S0(n2), .Y(Data_S[4]) );
CLKMX2X2TS U28 ( .A(N35), .B(N8), .S0(n2), .Y(Data_S[5]) );
CLKMX2X2TS U29 ( .A(N37), .B(N10), .S0(n2), .Y(Data_S[7]) );
CLKMX2X2TS U30 ( .A(N38), .B(N11), .S0(n2), .Y(Data_S[8]) );
CLKBUFX2TS U31 ( .A(op_mode), .Y(n1) );
endmodule
module RegisterAdd_W26 ( clk, rst, load, D, Q );
input [25:0] D;
output [25:0] Q;
input clk, rst, load;
wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37, n38,
n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n53,
n19, n20, n21, n22, n23, n24, n59;
DFFRX2TS \Q_reg[25] ( .D(n53), .CK(clk), .RN(n20), .Q(Q[25]) );
DFFRX2TS \Q_reg[24] ( .D(n51), .CK(clk), .RN(n20), .Q(Q[24]) );
DFFRX2TS \Q_reg[23] ( .D(n50), .CK(clk), .RN(n59), .Q(Q[23]) );
DFFRX2TS \Q_reg[22] ( .D(n49), .CK(clk), .RN(n59), .Q(Q[22]) );
DFFRX2TS \Q_reg[21] ( .D(n48), .CK(clk), .RN(n59), .Q(Q[21]) );
DFFRX2TS \Q_reg[20] ( .D(n47), .CK(clk), .RN(n59), .Q(Q[20]) );
DFFRX2TS \Q_reg[19] ( .D(n46), .CK(clk), .RN(n59), .Q(Q[19]) );
DFFRX2TS \Q_reg[18] ( .D(n45), .CK(clk), .RN(n59), .Q(Q[18]) );
DFFRX2TS \Q_reg[17] ( .D(n44), .CK(clk), .RN(n19), .Q(Q[17]), .QN(n18) );
DFFRX2TS \Q_reg[16] ( .D(n43), .CK(clk), .RN(n19), .Q(Q[16]), .QN(n17) );
DFFRX2TS \Q_reg[15] ( .D(n42), .CK(clk), .RN(n19), .Q(Q[15]), .QN(n16) );
DFFRX2TS \Q_reg[14] ( .D(n41), .CK(clk), .RN(n19), .Q(Q[14]), .QN(n15) );
DFFRX2TS \Q_reg[13] ( .D(n40), .CK(clk), .RN(n19), .Q(Q[13]), .QN(n14) );
DFFRX2TS \Q_reg[12] ( .D(n39), .CK(clk), .RN(n19), .Q(Q[12]), .QN(n13) );
DFFRX2TS \Q_reg[11] ( .D(n38), .CK(clk), .RN(n19), .Q(Q[11]), .QN(n12) );
DFFRX2TS \Q_reg[10] ( .D(n37), .CK(clk), .RN(n19), .Q(Q[10]), .QN(n11) );
DFFRX2TS \Q_reg[9] ( .D(n36), .CK(clk), .RN(n19), .Q(Q[9]), .QN(n10) );
DFFRX2TS \Q_reg[8] ( .D(n35), .CK(clk), .RN(n19), .Q(Q[8]), .QN(n9) );
DFFRX2TS \Q_reg[7] ( .D(n34), .CK(clk), .RN(n20), .Q(Q[7]), .QN(n8) );
DFFRX2TS \Q_reg[6] ( .D(n33), .CK(clk), .RN(n20), .Q(Q[6]), .QN(n7) );
DFFRX2TS \Q_reg[5] ( .D(n32), .CK(clk), .RN(n20), .Q(Q[5]), .QN(n6) );
DFFRX2TS \Q_reg[4] ( .D(n31), .CK(clk), .RN(n20), .Q(Q[4]), .QN(n5) );
DFFRX2TS \Q_reg[3] ( .D(n30), .CK(clk), .RN(n20), .Q(Q[3]), .QN(n4) );
DFFRX2TS \Q_reg[2] ( .D(n29), .CK(clk), .RN(n20), .Q(Q[2]), .QN(n3) );
DFFRX2TS \Q_reg[1] ( .D(n28), .CK(clk), .RN(n20), .Q(Q[1]), .QN(n2) );
DFFRX2TS \Q_reg[0] ( .D(n27), .CK(clk), .RN(n20), .Q(Q[0]), .QN(n1) );
CLKBUFX2TS U2 ( .A(n21), .Y(n23) );
CLKBUFX2TS U3 ( .A(n21), .Y(n24) );
CLKBUFX2TS U4 ( .A(n59), .Y(n19) );
CLKBUFX2TS U5 ( .A(n59), .Y(n20) );
CLKMX2X2TS U6 ( .A(Q[23]), .B(D[23]), .S0(n24), .Y(n50) );
CLKMX2X2TS U7 ( .A(Q[24]), .B(D[24]), .S0(n22), .Y(n51) );
CLKMX2X2TS U8 ( .A(Q[25]), .B(D[25]), .S0(n22), .Y(n53) );
CLKMX2X2TS U9 ( .A(Q[18]), .B(D[18]), .S0(n24), .Y(n45) );
CLKMX2X2TS U10 ( .A(Q[19]), .B(D[19]), .S0(n22), .Y(n46) );
CLKMX2X2TS U11 ( .A(Q[20]), .B(D[20]), .S0(n22), .Y(n47) );
CLKMX2X2TS U12 ( .A(Q[21]), .B(D[21]), .S0(n22), .Y(n48) );
CLKMX2X2TS U13 ( .A(Q[22]), .B(D[22]), .S0(n22), .Y(n49) );
OAI2BB2XLTS U14 ( .B0(n15), .B1(n23), .A0N(D[14]), .A1N(load), .Y(n41) );
OAI2BB2XLTS U15 ( .B0(n16), .B1(n23), .A0N(D[15]), .A1N(load), .Y(n42) );
OAI2BB2XLTS U16 ( .B0(n17), .B1(n23), .A0N(D[16]), .A1N(n21), .Y(n43) );
OAI2BB2XLTS U17 ( .B0(n18), .B1(n23), .A0N(D[17]), .A1N(n21), .Y(n44) );
OAI2BB2XLTS U18 ( .B0(n7), .B1(n24), .A0N(D[6]), .A1N(n22), .Y(n33) );
OAI2BB2XLTS U19 ( .B0(n10), .B1(n24), .A0N(D[9]), .A1N(n21), .Y(n36) );
OAI2BB2XLTS U20 ( .B0(n11), .B1(n23), .A0N(D[10]), .A1N(load), .Y(n37) );
OAI2BB2XLTS U21 ( .B0(n12), .B1(n23), .A0N(D[11]), .A1N(load), .Y(n38) );
OAI2BB2XLTS U22 ( .B0(n13), .B1(n23), .A0N(D[12]), .A1N(load), .Y(n39) );
OAI2BB2XLTS U23 ( .B0(n14), .B1(n23), .A0N(D[13]), .A1N(load), .Y(n40) );
OAI2BB2XLTS U24 ( .B0(n1), .B1(n23), .A0N(n21), .A1N(D[0]), .Y(n27) );
OAI2BB2XLTS U25 ( .B0(n2), .B1(n24), .A0N(D[1]), .A1N(n21), .Y(n28) );
OAI2BB2XLTS U26 ( .B0(n3), .B1(n24), .A0N(D[2]), .A1N(n21), .Y(n29) );
OAI2BB2XLTS U27 ( .B0(n4), .B1(n24), .A0N(D[3]), .A1N(load), .Y(n30) );
OAI2BB2XLTS U28 ( .B0(n5), .B1(n24), .A0N(D[4]), .A1N(n21), .Y(n31) );
OAI2BB2XLTS U29 ( .B0(n6), .B1(n24), .A0N(D[5]), .A1N(n22), .Y(n32) );
OAI2BB2XLTS U30 ( .B0(n8), .B1(n24), .A0N(D[7]), .A1N(n22), .Y(n34) );
OAI2BB2XLTS U31 ( .B0(n9), .B1(n23), .A0N(D[8]), .A1N(n22), .Y(n35) );
CLKBUFX2TS U32 ( .A(load), .Y(n21) );
CLKBUFX2TS U33 ( .A(load), .Y(n22) );
INVX2TS U34 ( .A(rst), .Y(n59) );
endmodule
module RegisterAdd_W1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n3, n2;
DFFRX2TS \Q_reg[0] ( .D(n3), .CK(clk), .RN(n2), .Q(Q[0]) );
CLKMX2X2TS U2 ( .A(Q[0]), .B(D[0]), .S0(load), .Y(n3) );
INVX2TS U3 ( .A(rst), .Y(n2) );
endmodule
module Add_Subt ( clk, rst, load_i, Add_Sub_op_i, Data_A_i, PreData_B_i,
Data_Result_o, FSM_C_o );
input [25:0] Data_A_i;
input [25:0] PreData_B_i;
output [25:0] Data_Result_o;
input clk, rst, load_i, Add_Sub_op_i;
output FSM_C_o;
wire [26:0] S_to_D;
add_sub_carry_out_W26 Sgf_AS ( .op_mode(Add_Sub_op_i), .Data_A(Data_A_i),
.Data_B(PreData_B_i), .Data_S(S_to_D) );
RegisterAdd_W26 Add_Subt_Result ( .clk(clk), .rst(rst), .load(load_i), .D(
S_to_D[25:0]), .Q(Data_Result_o) );
RegisterAdd_W1 Add_overflow_Result ( .clk(clk), .rst(rst), .load(load_i),
.D(S_to_D[26]), .Q(FSM_C_o) );
endmodule
|
// Author: Hugues CREUSY
// February 2004
// Verilog model
// project: M25P40 25 MHz,
// release: 1.1
// These Verilog HDL models are provided "as is" without warranty
// of any kind, included but not limited to, implied warranty
// of merchantability and fitness for a particular purpose.
`timescale 1ns/1ns
`include "parameter.v"
module m25p40(c,data_in,s,w,hold,data_out);
input c;
input data_in;
input s;
input w;
input hold;
output data_out;
///reg data_out;
wire [(`NB_BIT_ADD_MEM-1):0] adresse;
wire [(`NB_BIT_DATA-1):0] dtr;
wire [(`NB_BIT_DATA-1):0] data_to_write;
wire [(`LSB_TO_CODE_PAGE-1):0] page_index;
wire wr_op;
wire rd_op;
wire s_en;
wire b_en;
wire add_pp_en;
wire pp_en;
wire r_en;
wire d_req;
wire clck;
wire srwd_wrsr;
wire write_protect;
wire wrsr;
assign clck = c ;
memory_access mem_access(adresse, b_en, s_en, add_pp_en, pp_en, r_en, d_req, data_to_write, page_index, dtr);
acdc_check acdc_watch(clck, data_in, s, hold, wr_op, rd_op, srwd_wrsr, write_protect, wrsr);
internal_logic spi_decoder(clck, data_in, w, s, hold, dtr, data_out, data_to_write, page_index, adresse, wr_op, rd_op, b_en, s_en, add_pp_en, pp_en, r_en, d_req,srwd_wrsr, write_protect, wrsr);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_FUNCTIONAL_V
`define SKY130_FD_SC_LS__AND3B_FUNCTIONAL_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ls__and3b (
X ,
A_N,
B ,
C
);
// Module ports
output X ;
input A_N;
input B ;
input C ;
// Local signals
wire not0_out ;
wire and0_out_X;
// Name Output Other arguments
not not0 (not0_out , A_N );
and and0 (and0_out_X, C, not0_out, B );
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_FUNCTIONAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__EINVN_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__EINVN_FUNCTIONAL_PP_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire pwrgood_pp0_out_A ;
wire pwrgood_pp1_out_teb;
// Name Output Other arguments
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_A , A, VPWR, VGND );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp1 (pwrgood_pp1_out_teb, TE_B, VPWR, VGND );
notif0 notif00 (Z , pwrgood_pp0_out_A, pwrgood_pp1_out_teb);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__EINVN_FUNCTIONAL_PP_V |
//Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
//Date : Wed Mar 09 18:07:30 2016
//Host : WK116 running 64-bit major release (build 9200)
//Command : generate_target PmodACL2.bd
//Design : PmodACL2
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module PmodACL2
(AXI_LITE_GPIO_araddr,
AXI_LITE_GPIO_arready,
AXI_LITE_GPIO_arvalid,
AXI_LITE_GPIO_awaddr,
AXI_LITE_GPIO_awready,
AXI_LITE_GPIO_awvalid,
AXI_LITE_GPIO_bready,
AXI_LITE_GPIO_bresp,
AXI_LITE_GPIO_bvalid,
AXI_LITE_GPIO_rdata,
AXI_LITE_GPIO_rready,
AXI_LITE_GPIO_rresp,
AXI_LITE_GPIO_rvalid,
AXI_LITE_GPIO_wdata,
AXI_LITE_GPIO_wready,
AXI_LITE_GPIO_wstrb,
AXI_LITE_GPIO_wvalid,
AXI_LITE_SPI_araddr,
AXI_LITE_SPI_arready,
AXI_LITE_SPI_arvalid,
AXI_LITE_SPI_awaddr,
AXI_LITE_SPI_awready,
AXI_LITE_SPI_awvalid,
AXI_LITE_SPI_bready,
AXI_LITE_SPI_bresp,
AXI_LITE_SPI_bvalid,
AXI_LITE_SPI_rdata,
AXI_LITE_SPI_rready,
AXI_LITE_SPI_rresp,
AXI_LITE_SPI_rvalid,
AXI_LITE_SPI_wdata,
AXI_LITE_SPI_wready,
AXI_LITE_SPI_wstrb,
AXI_LITE_SPI_wvalid,
Pmod_out_pin10_i,
Pmod_out_pin10_o,
Pmod_out_pin10_t,
Pmod_out_pin1_i,
Pmod_out_pin1_o,
Pmod_out_pin1_t,
Pmod_out_pin2_i,
Pmod_out_pin2_o,
Pmod_out_pin2_t,
Pmod_out_pin3_i,
Pmod_out_pin3_o,
Pmod_out_pin3_t,
Pmod_out_pin4_i,
Pmod_out_pin4_o,
Pmod_out_pin4_t,
Pmod_out_pin7_i,
Pmod_out_pin7_o,
Pmod_out_pin7_t,
Pmod_out_pin8_i,
Pmod_out_pin8_o,
Pmod_out_pin8_t,
Pmod_out_pin9_i,
Pmod_out_pin9_o,
Pmod_out_pin9_t,
ext_spi_clk,
s_axi_aclk,
s_axi_aresetn);
input [8:0]AXI_LITE_GPIO_araddr;
output AXI_LITE_GPIO_arready;
input AXI_LITE_GPIO_arvalid;
input [8:0]AXI_LITE_GPIO_awaddr;
output AXI_LITE_GPIO_awready;
input AXI_LITE_GPIO_awvalid;
input AXI_LITE_GPIO_bready;
output [1:0]AXI_LITE_GPIO_bresp;
output AXI_LITE_GPIO_bvalid;
output [31:0]AXI_LITE_GPIO_rdata;
input AXI_LITE_GPIO_rready;
output [1:0]AXI_LITE_GPIO_rresp;
output AXI_LITE_GPIO_rvalid;
input [31:0]AXI_LITE_GPIO_wdata;
output AXI_LITE_GPIO_wready;
input [3:0]AXI_LITE_GPIO_wstrb;
input AXI_LITE_GPIO_wvalid;
input [6:0]AXI_LITE_SPI_araddr;
output AXI_LITE_SPI_arready;
input AXI_LITE_SPI_arvalid;
input [6:0]AXI_LITE_SPI_awaddr;
output AXI_LITE_SPI_awready;
input AXI_LITE_SPI_awvalid;
input AXI_LITE_SPI_bready;
output [1:0]AXI_LITE_SPI_bresp;
output AXI_LITE_SPI_bvalid;
output [31:0]AXI_LITE_SPI_rdata;
input AXI_LITE_SPI_rready;
output [1:0]AXI_LITE_SPI_rresp;
output AXI_LITE_SPI_rvalid;
input [31:0]AXI_LITE_SPI_wdata;
output AXI_LITE_SPI_wready;
input [3:0]AXI_LITE_SPI_wstrb;
input AXI_LITE_SPI_wvalid;
input Pmod_out_pin10_i;
output Pmod_out_pin10_o;
output Pmod_out_pin10_t;
input Pmod_out_pin1_i;
output Pmod_out_pin1_o;
output Pmod_out_pin1_t;
input Pmod_out_pin2_i;
output Pmod_out_pin2_o;
output Pmod_out_pin2_t;
input Pmod_out_pin3_i;
output Pmod_out_pin3_o;
output Pmod_out_pin3_t;
input Pmod_out_pin4_i;
output Pmod_out_pin4_o;
output Pmod_out_pin4_t;
input Pmod_out_pin7_i;
output Pmod_out_pin7_o;
output Pmod_out_pin7_t;
input Pmod_out_pin8_i;
output Pmod_out_pin8_o;
output Pmod_out_pin8_t;
input Pmod_out_pin9_i;
output Pmod_out_pin9_o;
output Pmod_out_pin9_t;
input ext_spi_clk;
input s_axi_aclk;
input s_axi_aresetn;
wire [6:0]AXI_LITE_1_ARADDR;
wire AXI_LITE_1_ARREADY;
wire AXI_LITE_1_ARVALID;
wire [6:0]AXI_LITE_1_AWADDR;
wire AXI_LITE_1_AWREADY;
wire AXI_LITE_1_AWVALID;
wire AXI_LITE_1_BREADY;
wire [1:0]AXI_LITE_1_BRESP;
wire AXI_LITE_1_BVALID;
wire [31:0]AXI_LITE_1_RDATA;
wire AXI_LITE_1_RREADY;
wire [1:0]AXI_LITE_1_RRESP;
wire AXI_LITE_1_RVALID;
wire [31:0]AXI_LITE_1_WDATA;
wire AXI_LITE_1_WREADY;
wire [3:0]AXI_LITE_1_WSTRB;
wire AXI_LITE_1_WVALID;
wire [8:0]S_AXI_1_ARADDR;
wire S_AXI_1_ARREADY;
wire S_AXI_1_ARVALID;
wire [8:0]S_AXI_1_AWADDR;
wire S_AXI_1_AWREADY;
wire S_AXI_1_AWVALID;
wire S_AXI_1_BREADY;
wire [1:0]S_AXI_1_BRESP;
wire S_AXI_1_BVALID;
wire [31:0]S_AXI_1_RDATA;
wire S_AXI_1_RREADY;
wire [1:0]S_AXI_1_RRESP;
wire S_AXI_1_RVALID;
wire [31:0]S_AXI_1_WDATA;
wire S_AXI_1_WREADY;
wire [3:0]S_AXI_1_WSTRB;
wire S_AXI_1_WVALID;
wire [3:0]axi_gpio_0_GPIO_TRI_I;
wire [3:0]axi_gpio_0_GPIO_TRI_O;
wire [3:0]axi_gpio_0_GPIO_TRI_T;
wire axi_quad_spi_0_SPI_0_IO0_I;
wire axi_quad_spi_0_SPI_0_IO0_O;
wire axi_quad_spi_0_SPI_0_IO0_T;
wire axi_quad_spi_0_SPI_0_IO1_I;
wire axi_quad_spi_0_SPI_0_IO1_O;
wire axi_quad_spi_0_SPI_0_IO1_T;
wire axi_quad_spi_0_SPI_0_SCK_I;
wire axi_quad_spi_0_SPI_0_SCK_O;
wire axi_quad_spi_0_SPI_0_SCK_T;
wire axi_quad_spi_0_SPI_0_SS_I;
wire [0:0]axi_quad_spi_0_SPI_0_SS_O;
wire axi_quad_spi_0_SPI_0_SS_T;
wire ext_spi_clk_1;
wire pmod_bridge_0_Pmod_out_PIN10_I;
wire pmod_bridge_0_Pmod_out_PIN10_O;
wire pmod_bridge_0_Pmod_out_PIN10_T;
wire pmod_bridge_0_Pmod_out_PIN1_I;
wire pmod_bridge_0_Pmod_out_PIN1_O;
wire pmod_bridge_0_Pmod_out_PIN1_T;
wire pmod_bridge_0_Pmod_out_PIN2_I;
wire pmod_bridge_0_Pmod_out_PIN2_O;
wire pmod_bridge_0_Pmod_out_PIN2_T;
wire pmod_bridge_0_Pmod_out_PIN3_I;
wire pmod_bridge_0_Pmod_out_PIN3_O;
wire pmod_bridge_0_Pmod_out_PIN3_T;
wire pmod_bridge_0_Pmod_out_PIN4_I;
wire pmod_bridge_0_Pmod_out_PIN4_O;
wire pmod_bridge_0_Pmod_out_PIN4_T;
wire pmod_bridge_0_Pmod_out_PIN7_I;
wire pmod_bridge_0_Pmod_out_PIN7_O;
wire pmod_bridge_0_Pmod_out_PIN7_T;
wire pmod_bridge_0_Pmod_out_PIN8_I;
wire pmod_bridge_0_Pmod_out_PIN8_O;
wire pmod_bridge_0_Pmod_out_PIN8_T;
wire pmod_bridge_0_Pmod_out_PIN9_I;
wire pmod_bridge_0_Pmod_out_PIN9_O;
wire pmod_bridge_0_Pmod_out_PIN9_T;
wire s_axi_aclk_1;
wire s_axi_aresetn_1;
assign AXI_LITE_1_ARADDR = AXI_LITE_SPI_araddr[6:0];
assign AXI_LITE_1_ARVALID = AXI_LITE_SPI_arvalid;
assign AXI_LITE_1_AWADDR = AXI_LITE_SPI_awaddr[6:0];
assign AXI_LITE_1_AWVALID = AXI_LITE_SPI_awvalid;
assign AXI_LITE_1_BREADY = AXI_LITE_SPI_bready;
assign AXI_LITE_1_RREADY = AXI_LITE_SPI_rready;
assign AXI_LITE_1_WDATA = AXI_LITE_SPI_wdata[31:0];
assign AXI_LITE_1_WSTRB = AXI_LITE_SPI_wstrb[3:0];
assign AXI_LITE_1_WVALID = AXI_LITE_SPI_wvalid;
assign AXI_LITE_GPIO_arready = S_AXI_1_ARREADY;
assign AXI_LITE_GPIO_awready = S_AXI_1_AWREADY;
assign AXI_LITE_GPIO_bresp[1:0] = S_AXI_1_BRESP;
assign AXI_LITE_GPIO_bvalid = S_AXI_1_BVALID;
assign AXI_LITE_GPIO_rdata[31:0] = S_AXI_1_RDATA;
assign AXI_LITE_GPIO_rresp[1:0] = S_AXI_1_RRESP;
assign AXI_LITE_GPIO_rvalid = S_AXI_1_RVALID;
assign AXI_LITE_GPIO_wready = S_AXI_1_WREADY;
assign AXI_LITE_SPI_arready = AXI_LITE_1_ARREADY;
assign AXI_LITE_SPI_awready = AXI_LITE_1_AWREADY;
assign AXI_LITE_SPI_bresp[1:0] = AXI_LITE_1_BRESP;
assign AXI_LITE_SPI_bvalid = AXI_LITE_1_BVALID;
assign AXI_LITE_SPI_rdata[31:0] = AXI_LITE_1_RDATA;
assign AXI_LITE_SPI_rresp[1:0] = AXI_LITE_1_RRESP;
assign AXI_LITE_SPI_rvalid = AXI_LITE_1_RVALID;
assign AXI_LITE_SPI_wready = AXI_LITE_1_WREADY;
assign Pmod_out_pin10_o = pmod_bridge_0_Pmod_out_PIN10_O;
assign Pmod_out_pin10_t = pmod_bridge_0_Pmod_out_PIN10_T;
assign Pmod_out_pin1_o = pmod_bridge_0_Pmod_out_PIN1_O;
assign Pmod_out_pin1_t = pmod_bridge_0_Pmod_out_PIN1_T;
assign Pmod_out_pin2_o = pmod_bridge_0_Pmod_out_PIN2_O;
assign Pmod_out_pin2_t = pmod_bridge_0_Pmod_out_PIN2_T;
assign Pmod_out_pin3_o = pmod_bridge_0_Pmod_out_PIN3_O;
assign Pmod_out_pin3_t = pmod_bridge_0_Pmod_out_PIN3_T;
assign Pmod_out_pin4_o = pmod_bridge_0_Pmod_out_PIN4_O;
assign Pmod_out_pin4_t = pmod_bridge_0_Pmod_out_PIN4_T;
assign Pmod_out_pin7_o = pmod_bridge_0_Pmod_out_PIN7_O;
assign Pmod_out_pin7_t = pmod_bridge_0_Pmod_out_PIN7_T;
assign Pmod_out_pin8_o = pmod_bridge_0_Pmod_out_PIN8_O;
assign Pmod_out_pin8_t = pmod_bridge_0_Pmod_out_PIN8_T;
assign Pmod_out_pin9_o = pmod_bridge_0_Pmod_out_PIN9_O;
assign Pmod_out_pin9_t = pmod_bridge_0_Pmod_out_PIN9_T;
assign S_AXI_1_ARADDR = AXI_LITE_GPIO_araddr[8:0];
assign S_AXI_1_ARVALID = AXI_LITE_GPIO_arvalid;
assign S_AXI_1_AWADDR = AXI_LITE_GPIO_awaddr[8:0];
assign S_AXI_1_AWVALID = AXI_LITE_GPIO_awvalid;
assign S_AXI_1_BREADY = AXI_LITE_GPIO_bready;
assign S_AXI_1_RREADY = AXI_LITE_GPIO_rready;
assign S_AXI_1_WDATA = AXI_LITE_GPIO_wdata[31:0];
assign S_AXI_1_WSTRB = AXI_LITE_GPIO_wstrb[3:0];
assign S_AXI_1_WVALID = AXI_LITE_GPIO_wvalid;
assign ext_spi_clk_1 = ext_spi_clk;
assign pmod_bridge_0_Pmod_out_PIN10_I = Pmod_out_pin10_i;
assign pmod_bridge_0_Pmod_out_PIN1_I = Pmod_out_pin1_i;
assign pmod_bridge_0_Pmod_out_PIN2_I = Pmod_out_pin2_i;
assign pmod_bridge_0_Pmod_out_PIN3_I = Pmod_out_pin3_i;
assign pmod_bridge_0_Pmod_out_PIN4_I = Pmod_out_pin4_i;
assign pmod_bridge_0_Pmod_out_PIN7_I = Pmod_out_pin7_i;
assign pmod_bridge_0_Pmod_out_PIN8_I = Pmod_out_pin8_i;
assign pmod_bridge_0_Pmod_out_PIN9_I = Pmod_out_pin9_i;
assign s_axi_aclk_1 = s_axi_aclk;
assign s_axi_aresetn_1 = s_axi_aresetn;
PmodACL2_axi_gpio_0_0 axi_gpio_0
(.gpio_io_i(axi_gpio_0_GPIO_TRI_I),
.gpio_io_o(axi_gpio_0_GPIO_TRI_O),
.gpio_io_t(axi_gpio_0_GPIO_TRI_T),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(S_AXI_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(S_AXI_1_ARREADY),
.s_axi_arvalid(S_AXI_1_ARVALID),
.s_axi_awaddr(S_AXI_1_AWADDR),
.s_axi_awready(S_AXI_1_AWREADY),
.s_axi_awvalid(S_AXI_1_AWVALID),
.s_axi_bready(S_AXI_1_BREADY),
.s_axi_bresp(S_AXI_1_BRESP),
.s_axi_bvalid(S_AXI_1_BVALID),
.s_axi_rdata(S_AXI_1_RDATA),
.s_axi_rready(S_AXI_1_RREADY),
.s_axi_rresp(S_AXI_1_RRESP),
.s_axi_rvalid(S_AXI_1_RVALID),
.s_axi_wdata(S_AXI_1_WDATA),
.s_axi_wready(S_AXI_1_WREADY),
.s_axi_wstrb(S_AXI_1_WSTRB),
.s_axi_wvalid(S_AXI_1_WVALID));
PmodACL2_axi_quad_spi_0_0 axi_quad_spi_0
(.ext_spi_clk(ext_spi_clk_1),
.io0_i(axi_quad_spi_0_SPI_0_IO0_I),
.io0_o(axi_quad_spi_0_SPI_0_IO0_O),
.io0_t(axi_quad_spi_0_SPI_0_IO0_T),
.io1_i(axi_quad_spi_0_SPI_0_IO1_I),
.io1_o(axi_quad_spi_0_SPI_0_IO1_O),
.io1_t(axi_quad_spi_0_SPI_0_IO1_T),
.s_axi_aclk(s_axi_aclk_1),
.s_axi_araddr(AXI_LITE_1_ARADDR),
.s_axi_aresetn(s_axi_aresetn_1),
.s_axi_arready(AXI_LITE_1_ARREADY),
.s_axi_arvalid(AXI_LITE_1_ARVALID),
.s_axi_awaddr(AXI_LITE_1_AWADDR),
.s_axi_awready(AXI_LITE_1_AWREADY),
.s_axi_awvalid(AXI_LITE_1_AWVALID),
.s_axi_bready(AXI_LITE_1_BREADY),
.s_axi_bresp(AXI_LITE_1_BRESP),
.s_axi_bvalid(AXI_LITE_1_BVALID),
.s_axi_rdata(AXI_LITE_1_RDATA),
.s_axi_rready(AXI_LITE_1_RREADY),
.s_axi_rresp(AXI_LITE_1_RRESP),
.s_axi_rvalid(AXI_LITE_1_RVALID),
.s_axi_wdata(AXI_LITE_1_WDATA),
.s_axi_wready(AXI_LITE_1_WREADY),
.s_axi_wstrb(AXI_LITE_1_WSTRB),
.s_axi_wvalid(AXI_LITE_1_WVALID),
.sck_i(axi_quad_spi_0_SPI_0_SCK_I),
.sck_o(axi_quad_spi_0_SPI_0_SCK_O),
.sck_t(axi_quad_spi_0_SPI_0_SCK_T),
.ss_i(axi_quad_spi_0_SPI_0_SS_I),
.ss_o(axi_quad_spi_0_SPI_0_SS_O),
.ss_t(axi_quad_spi_0_SPI_0_SS_T));
PmodACL2_pmod_bridge_0_0 pmod_bridge_0
(.in0_I(axi_quad_spi_0_SPI_0_SS_I),
.in0_O(axi_quad_spi_0_SPI_0_SS_O),
.in0_T(axi_quad_spi_0_SPI_0_SS_T),
.in1_I(axi_quad_spi_0_SPI_0_IO0_I),
.in1_O(axi_quad_spi_0_SPI_0_IO0_O),
.in1_T(axi_quad_spi_0_SPI_0_IO0_T),
.in2_I(axi_quad_spi_0_SPI_0_IO1_I),
.in2_O(axi_quad_spi_0_SPI_0_IO1_O),
.in2_T(axi_quad_spi_0_SPI_0_IO1_T),
.in3_I(axi_quad_spi_0_SPI_0_SCK_I),
.in3_O(axi_quad_spi_0_SPI_0_SCK_O),
.in3_T(axi_quad_spi_0_SPI_0_SCK_T),
.in_bottom_bus_I(axi_gpio_0_GPIO_TRI_I),
.in_bottom_bus_O(axi_gpio_0_GPIO_TRI_O),
.in_bottom_bus_T(axi_gpio_0_GPIO_TRI_T),
.out0_I(pmod_bridge_0_Pmod_out_PIN1_I),
.out0_O(pmod_bridge_0_Pmod_out_PIN1_O),
.out0_T(pmod_bridge_0_Pmod_out_PIN1_T),
.out1_I(pmod_bridge_0_Pmod_out_PIN2_I),
.out1_O(pmod_bridge_0_Pmod_out_PIN2_O),
.out1_T(pmod_bridge_0_Pmod_out_PIN2_T),
.out2_I(pmod_bridge_0_Pmod_out_PIN3_I),
.out2_O(pmod_bridge_0_Pmod_out_PIN3_O),
.out2_T(pmod_bridge_0_Pmod_out_PIN3_T),
.out3_I(pmod_bridge_0_Pmod_out_PIN4_I),
.out3_O(pmod_bridge_0_Pmod_out_PIN4_O),
.out3_T(pmod_bridge_0_Pmod_out_PIN4_T),
.out4_I(pmod_bridge_0_Pmod_out_PIN7_I),
.out4_O(pmod_bridge_0_Pmod_out_PIN7_O),
.out4_T(pmod_bridge_0_Pmod_out_PIN7_T),
.out5_I(pmod_bridge_0_Pmod_out_PIN8_I),
.out5_O(pmod_bridge_0_Pmod_out_PIN8_O),
.out5_T(pmod_bridge_0_Pmod_out_PIN8_T),
.out6_I(pmod_bridge_0_Pmod_out_PIN9_I),
.out6_O(pmod_bridge_0_Pmod_out_PIN9_O),
.out6_T(pmod_bridge_0_Pmod_out_PIN9_T),
.out7_I(pmod_bridge_0_Pmod_out_PIN10_I),
.out7_O(pmod_bridge_0_Pmod_out_PIN10_O),
.out7_T(pmod_bridge_0_Pmod_out_PIN10_T));
endmodule
|
(** * Poly: Polymorphism and Higher-Order Functions *)
(* $Date: 2012-09-08 20:51:57 -0400 (Sat, 08 Sep 2012) $ *)
Require Export Lists.
(* ###################################################### *)
(** * Polymorphism *)
(* ###################################################### *)
(** ** Polymorphic Lists *)
(** Up to this point, we've been working with lists of numbers.
Of course, interesting programs also need to be able to manipulate
lists whose elements are drawn from other types -- lists of
strings, lists of booleans, lists of lists, etc. We _could_ just
define a new inductive datatype for each of these, for
example... *)
Inductive boollist : Type :=
| bool_nil : boollist
| bool_cons : bool -> boollist -> boollist.
(** ... but this would quickly become tedious, partly because we
have to make up different constructor names for each datatype, but
mostly because we would also need to define new versions of all
our list manipulating functions ([length], [rev], etc.) for each
new datatype definition. *)
(** To avoid all this repetition, Coq supports _polymorphic_
inductive type definitions. For example, here is a polymorphic
list datatype. *)
Inductive list (X:Type) : Type :=
| nil : list X
| cons : X -> list X -> list X.
(** This is exactly like the definition of [natlist] from the
previous chapter, except that the [nat] argument to the [cons]
constructor has been replaced by an arbitrary type [X], a binding
for [X] has been added to the header, and the occurrences of
[natlist] in the types of the constructors have been replaced by
[list X]. (We can re-use the constructor names [nil] and [cons]
because the earlier definition of [natlist] was inside of a
[Module] definition that is now out of scope.) *)
(** What sort of thing is [list] itself? One good way to think
about it is that [list] is a _function_ from [Type]s to
[Inductive] definitions; or, to put it another way, [list] is a
function from [Type]s to [Type]s. For any particular type [X],
the type [list X] is an [Inductive]ly defined set of lists whose
elements are things of type [X]. *)
(** With this definition, when we use the constructors [nil] and
[cons] to build lists, we need to tell Coq the type of the
elements in the lists we are building -- that is, [nil] and [cons]
are now _polymorphic constructors_. Observe the types of these
constructors: *)
Check nil.
(* ===> nil : forall X : Type, list X *)
Check cons.
(* ===> cons : forall X : Type, X -> list X -> list X *)
(** (Side note on notation: In .v files, the "forall" quantifier is
spelled out in letters. In the generated HTML files, [forall] is
usually typeset as the usual mathematical "upside down A," but
you'll see the spelled-out "forall" in a few places. This is just
a quirk of typesetting: there is no difference in meaning. *)
(** The "[forall X]" in these types should be read as an
additional argument to the constructors that determines the
expected types of the arguments that follow. When [nil] and
[cons] are used, these arguments are supplied in the same way as
the others. For example, the list containing [2] and [1] is
written like this: *)
Check (cons nat 2 (cons nat 1 (nil nat))).
(** (We've gone back to writing [nil] and [cons] explicitly here
because we haven't yet defined the [ [] ] and [::] notations for
the new version of lists. We'll do that in a bit.) *)
(** We can now go back and make polymorphic (or "generic")
versions of all the list-processing functions that we wrote
before. Here is [length], for example: *)
Fixpoint length (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length X t)
end.
(** Note that the uses of [nil] and [cons] in [match] patterns
do not require any type annotations: we already know that the list
[l] contains elements of type [X], so there's no reason to include
[X] in the pattern. (More formally, the type [X] is a parameter
of the whole definition of [list], not of the individual
constructors. We'll come back to this point later.)
As with [nil] and [cons], we can use [length] by applying it first
to a type and then to its list argument: *)
Example test_length1 :
length nat (cons nat 1 (cons nat 2 (nil nat))) = 2.
Proof. reflexivity. Qed.
(** To use our length with other kinds of lists, we simply
instantiate it with an appropriate type parameter: *)
Example test_length2 :
length bool (cons bool true (nil bool)) = 1.
Proof. reflexivity. Qed.
(** Let's close this subsection by re-implementing a few other
standard list functions on our new polymorphic lists: *)
Fixpoint app (X : Type) (l1 l2 : list X)
: (list X) :=
match l1 with
| nil => l2
| cons h t => cons X h (app X t l2)
end.
Fixpoint snoc (X:Type) (l:list X) (v:X) : (list X) :=
match l with
| nil => cons X v (nil X)
| cons h t => cons X h (snoc X t v)
end.
Fixpoint rev (X:Type) (l:list X) : list X :=
match l with
| nil => nil X
| cons h t => snoc X (rev X t) h
end.
Example test_rev1 :
rev nat (cons nat 1 (cons nat 2 (nil nat)))
= (cons nat 2 (cons nat 1 (nil nat))).
Proof. reflexivity. Qed.
Example test_rev2:
rev bool (nil bool) = nil bool.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** *** Type Annotation Inference *)
(** Let's write the definition of [app] again, but this time we won't
specify the types of any of the arguments. Will Coq still accept
it? *)
Fixpoint app' X l1 l2 : list X :=
match l1 with
| nil => l2
| cons h t => cons X h (app' X t l2)
end.
(** Indeed it will. Let's see what type Coq has assigned to [app']: *)
Check app'.
Check app.
(** It has exactly the same type type as [app]. Coq was able to
use a process called _type inference_ to deduce what the types of
[X], [l1], and [l2] must be, based on how they are used. For
example, since [X] is used as an argument to [cons], it must be a
[Type], since [cons] expects a [Type] as its first argument;
matching [l1] with [nil] and [cons] means it must be a [list]; and
so on.
This powerful facility means we don't always have to write
explicit type annotations everywhere, although explicit type
annotations are still quite useful as documentation and sanity
checks. You should try to find a balance in your own code between
too many type annotations (so many that they clutter and distract)
and too few (which forces readers to perform type inference in
their heads in order to understand your code). *)
(* ###################################################### *)
(** *** Type Argument Synthesis *)
(** Whenever we use a polymorphic function, we need to pass it
one or more types in addition to its other arguments. For
example, the recursive call in the body of the [length] function
above must pass along the type [X]. But just like providing
explicit type annotations everywhere, this is heavy and verbose.
Since the second argument to [length] is a list of [X]s, it seems
entirely obvious that the first argument can only be [X] -- why
should we have to write it explicitly?
Fortunately, Coq permits us to avoid this kind of redundancy. In
place of any type argument we can write the "implicit argument"
[_], which can be read as "Please figure out for yourself what
type belongs here." More precisely, when Coq encounters a [_], it
will attempt to _unify_ all locally available information -- the
type of the function being applied, the types of the other
arguments, and the type expected by the context in which the
application appears -- to determine what concrete type should
replace the [_].
This may sound similar to type annotation inference -- and,
indeed, the two procedures rely on the same underlying mechanisms.
Instead of simply omitting the types of some arguments to a
function, like
app' X l1 l2 : list X :=
we can also replace the types with [_], like
app' (X : _) (l1 l2 : _) : list X :=
which tells Coq to attempt to infer the missing information, just
as with argument synthesis.
Using implicit arguments, the [length] function can be written
like this: *)
Fixpoint length' (X:Type) (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length' _ t)
end.
(** In this instance, we don't save much by writing [_] instead of
[X]. But in many cases the difference can be significant. For
example, suppose we want to write down a list containing the
numbers [1], [2], and [3]. Instead of writing this... *)
Definition list123 :=
cons nat 1 (cons nat 2 (cons nat 3 (nil nat))).
(** ...we can use argument synthesis to write this: *)
Definition list123' := cons _ 1 (cons _ 2 (cons _ 3 (nil _))).
(* ###################################################### *)
(** *** Implicit Arguments *)
(** If fact, we can go further. To avoid having to sprinkle [_]'s
throughout our programs, we can tell Coq _always_ to infer the
type argument(s) of a given function. *)
Implicit Arguments nil [[X]].
Implicit Arguments cons [[X]].
Implicit Arguments length [[X]].
Implicit Arguments app [[X]].
Implicit Arguments rev [[X]].
Implicit Arguments snoc [[X]].
(* note: no _ arguments required... *)
Definition list123'' := cons 1 (cons 2 (cons 3 nil)).
Check (length list123'').
(** Alternatively, we can declare an argument to be implicit while
defining the function itself, by surrounding the argument in curly
braces. For example: *)
Fixpoint length'' {X:Type} (l:list X) : nat :=
match l with
| nil => 0
| cons h t => S (length'' t)
end.
(** (Note that we didn't even have to provide a type argument to
the recursive call to [length''].) We will use this style
whenever possible, although we will continue to use use explicit
[Implicit Argument] declarations for [Inductive] constructors. *)
(** One small problem with declaring arguments [Implicit] is
that, occasionally, Coq does not have enough local information to
determine a type argument; in such cases, we need to tell Coq that
we want to give the argument explicitly this time, even though
we've globally declared it to be [Implicit]. For example, if we
write: *)
(* Definition mynil := nil. *)
(** If we uncomment this definition, Coq will give us an error,
because it doesn't know what type argument to supply to [nil]. We
can help it by providing an explicit type declaration (so that Coq
has more information available when it gets to the "application"
of [nil]): *)
Definition mynil : list nat := nil.
(** Alternatively, we can force the implicit arguments to be explicit by
prefixing the function name with [@]. *)
Check @nil.
Definition mynil' := @nil nat.
(** Using argument synthesis and implicit arguments, we can
define convenient notation for lists, as before. Since we have
made the constructor type arguments implicit, Coq will know to
automatically infer these when we use the notations. *)
Notation "x :: y" := (cons x y)
(at level 60, right associativity).
Notation "[ ]" := nil.
Notation "[ x , .. , y ]" := (cons x .. (cons y []) ..).
Notation "x ++ y" := (app x y)
(at level 60, right associativity).
(** Now lists can be written just the way we'd hope: *)
Definition list123''' := [1, 2, 3].
(* ###################################################### *)
(** *** Exercises: Polymorphic Lists *)
(** **** Exercise: 2 stars, optional (poly_exercises) *)
(** Here are a few simple exercises, just like ones in the [Lists]
chapter, for practice with polymorphism. Fill in the definitions
and complete the proofs below. *)
Fixpoint repeat (X : Type) (n : X) (count : nat) : list X :=
match count with
| O => nil
| S n' => n :: repeat X n n'
end.
Example test_repeat1:
repeat bool true 2 = cons true (cons true nil).
Proof. reflexivity. Qed.
Theorem nil_app : forall X:Type, forall l:list X,
app [] l = l.
Proof.
intros. reflexivity. Qed.
Theorem rev_snoc : forall X : Type,
forall v : X,
forall s : list X,
rev (snoc s v) = v :: (rev s).
Proof.
intros. induction s as [| h t].
Case "s = []".
reflexivity.
Case "s = h :: t".
simpl. rewrite -> IHt. reflexivity. Qed.
Theorem ass_app :
forall (X:Type), forall (l1 l2 l3:list X),
(l1 ++ l2) ++ l3 = l1 ++ (l2 ++ l3).
Proof.
intros. induction l1 as [| n l1'].
Case "l1 = nil".
reflexivity.
Case "l1 = cons n l1'".
simpl. rewrite -> IHl1'. reflexivity. Qed.
Theorem nil_end_app :
forall (X:Type), forall (l:list X),
app l [] = l.
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. rewrite -> IHt. reflexivity. Qed.
Theorem sing_end_app :
forall (X:Type), forall (l:list X) (n:X),
app l [n] = snoc l n.
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. rewrite -> IHt. reflexivity. Qed.
Theorem rev_app :
forall (X:Type), forall (l m: list X),
rev (l ++ m) = rev m ++ rev l.
Proof.
intros. induction l as [| h t].
Case "l = []".
simpl. rewrite -> nil_end_app. reflexivity.
Case "l = h :: t".
simpl. rewrite <- sing_end_app. rewrite -> IHt. rewrite -> ass_app.
rewrite -> sing_end_app. reflexivity. Qed.
Theorem rev_involutive : forall X : Type, forall l : list X,
rev (rev l) = l.
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. rewrite <- sing_end_app. rewrite -> rev_app. rewrite -> IHt.
reflexivity. Qed.
Theorem snoc_with_append : forall X : Type,
forall l1 l2 : list X,
forall v : X,
snoc (l1 ++ l2) v = l1 ++ (snoc l2 v).
Proof.
intros. induction l1 as [| h1 t1].
Case "l1 = []".
reflexivity.
Case "l1 = h1 :: t1".
simpl. rewrite -> IHt1. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Pairs *)
(** Following the same pattern, the type definition we gave in
the last chapter for pairs of numbers can be generalized to
_polymorphic pairs_ (or _products_): *)
Inductive prod (X Y : Type) : Type :=
pair : X -> Y -> prod X Y.
Implicit Arguments pair [[X] [Y]].
(** As with lists, we make the type arguments implicit and define the
familiar concrete notation. *)
Notation "( x , y )" := (pair x y).
(** We can also use the [Notation] mechanism to define the standard
notation for pair _types_: *)
Notation "X * Y" := (prod X Y) : type_scope.
(** (The annotation [: type_scope] tells Coq that this abbreviation
should be used when parsing types. This avoids a clash with the
multiplication symbol.) *)
(** A note of caution: it is easy at first to get [(x,y)] and
[X*Y] confused. Remember that [(x,y)] is a _value_ built from two
other values; [X*Y] is a _type_ built from two other types. If
[x] has type [X] and [y] has type [Y], then [(x,y)] has type
[X*Y]. *)
(** The first and second projection functions now look pretty
much as they would in any functional programming language. *)
Definition fst {X Y : Type} (p : X * Y) : X :=
match p with (x,y) => x end.
Definition snd {X Y : Type} (p : X * Y) : Y :=
match p with (x,y) => y end.
(** The following function takes two lists and combines them
into a list of pairs. In many functional programming languages,
it is called [zip]. We call it [combine] for consistency with
Coq's standard library. *)
(** Note that the pair notation can be used both in expressions and in
patterns... *)
Fixpoint combine {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match (lx,ly) with
| ([],_) => []
| (_,[]) => []
| (x::tx, y::ty) => (x,y) :: (combine tx ty)
end.
(** Indeed, when no ambiguity results, we can even drop the enclosing
parens: *)
Fixpoint combine' {X Y : Type} (lx : list X) (ly : list Y)
: list (X*Y) :=
match lx,ly with
| [],_ => []
| _,[] => []
| x::tx, y::ty => (x,y) :: (combine' tx ty)
end.
(** **** Exercise: 1 star, optional (combine_checks) *)
(** Try answering the following questions on paper and
checking your answers in coq:
- What is the type of [combine] (i.e., what does [Check
@combine] print?)
- What does
Eval simpl in (combine [1,2] [false,false,true,true]).
print? []
*)
(* - forall X Y : Type, list X -> list Y -> list (X * Y)
- [(1,false),(2,false)] *)
(** **** Exercise: 2 stars, recommended (split) *)
(** The function [split] is the right inverse of combine: it takes a
list of pairs and returns a pair of lists. In many functional
programing languages, this function is called [unzip].
Uncomment the material below and fill in the definition of
[split]. Make sure it passes the given unit tests. *)
Fixpoint split {X Y : Type} (l:list (X * Y)) : list X * list Y :=
match l with
| [] => ([],[])
| (x,y) :: l' => match split l' with
| (lx,ly) => (x :: lx, y :: ly)
end
end.
Example test_split:
split [(1,false),(2,false)] = ([1,2],[false,false]).
Proof. reflexivity. Qed.
(** (If you're reading the HTML version of this file, note that
there's an unresolved typesetting problem in the example: several
square brackets are missing. Refer to the .v file for the correct
version. *)
(** [] *)
(* ###################################################### *)
(** ** Polymorphic Options *)
(** One last polymorphic type for now: _polymorphic options_.
The type declaration generalizes the one for [natoption] in the
previous chapter: *)
Inductive option (X:Type) : Type :=
| Some : X -> option X
| None : option X.
Implicit Arguments Some [[X]].
Implicit Arguments None [[X]].
(** We can now rewrite the [index] function so that it works
with any type of lists. *)
Fixpoint index {X : Type} (n : nat)
(l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Example test_index1 : index 0 [4,5,6,7] = Some 4.
Proof. reflexivity. Qed.
Example test_index2 : index 1 [[1],[2]] = Some [2].
Proof. reflexivity. Qed.
Example test_index3 : index 2 [true] = None.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (hd_opt_poly) *)
(** Complete the definition of a polymorphic version of the
[hd_opt] function from the last chapter. Be sure that it
passes the unit tests below. *)
Definition hd_opt {X : Type} (l : list X) : option X :=
match l with
| [] => None
| h :: t => Some h
end.
(** Once again, to force the implicit arguments to be explicit,
we can use [@] before the name of the function. *)
Check @hd_opt.
Example test_hd_opt1 : hd_opt [1,2] = Some 1.
Proof. reflexivity. Qed.
Example test_hd_opt2 : hd_opt [[1],[2]] = Some [1].
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** * Functions as Data *)
(* ###################################################### *)
(** ** Higher-Order Functions *)
(** Like many other modern programming languages -- including
all _functional languages_ (ML, Haskell, Scheme, etc.) -- Coq
treats functions as first-class citizens, allowing functions to be
passed as arguments to other functions, returned as results,
stored in data structures, etc.
Functions that manipulate other functions are often called
_higher-order_ functions. Here's a simple one: *)
Definition doit3times {X:Type} (f:X->X) (n:X) : X :=
f (f (f n)).
(** The argument [f] here is itself a function (from [X] to
[X]); the body of [doit3times] applies [f] three times to some
value [n]. *)
Check @doit3times.
(* ===> doit3times : forall X : Type, (X -> X) -> X -> X *)
Example test_doit3times: doit3times minustwo 9 = 3.
Proof. reflexivity. Qed.
Example test_doit3times': doit3times negb true = false.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Partial Application *)
(** In fact, the multiple-argument functions we have already
seen are also examples of passing functions as data. To see why,
recall the type of [plus]. *)
Check plus.
(* ==> nat -> nat -> nat *)
(** Each [->] in this expression is actually a _binary_ operator
on types. (This is the same as saying that Coq primitively
supports only one-argument functions -- do you see why?) This
operator is _right-associative_, so the type of [plus] is really a
shorthand for [nat -> (nat -> nat)] -- i.e., it can be read as
saying that "[plus] is a one-argument function that takes a [nat]
and returns a one-argument function that takes another [nat] and
returns a [nat]." In the examples above, we have always applied
[plus] to both of its arguments at once, but if we like we can
supply just the first. This is called _partial application_. *)
Definition plus3 := plus 3.
Check plus3.
Example test_plus3 : plus3 4 = 7.
Proof. reflexivity. Qed.
Example test_plus3' : doit3times plus3 0 = 9.
Proof. reflexivity. Qed.
Example test_plus3'' : doit3times (plus 3) 0 = 9.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Digression: Currying *)
(** **** Exercise: 2 stars, optional (currying) *)
(** In Coq, a function [f : A -> B -> C] really has the type [A
-> (B -> C)]. That is, if you give [f] a value of type [A], it
will give you function [f' : B -> C]. If you then give [f'] a
value of type [B], it will return a value of type [C]. This
allows for partial application, as in [plus3]. Processing a list
of arguments with functions that return functions is called
_currying_, in honor of the logician Haskell Curry.
Conversely, we can reinterpret the type [A -> B -> C] as [(A *
B) -> C]. This is called _uncurrying_. With an uncurried binary
function, both arguments must be given at once as a pair; there is
no partial application. *)
(** We can define currying as follows: *)
Definition prod_curry {X Y Z : Type}
(f : X * Y -> Z) (x : X) (y : Y) : Z := f (x, y).
(** As an exercise, define its inverse, [prod_uncurry]. Then prove
the theorems below to show that the two are inverses. *)
Definition prod_uncurry {X Y Z : Type}
(f : X -> Y -> Z) (p : X * Y) : Z := f (fst p) (snd p).
(** (Thought exercise: before running these commands, can you
calculate the types of [prod_curry] and [prod_uncurry]?) *)
Check @prod_curry.
Check @prod_uncurry.
Theorem uncurry_curry : forall (X Y Z : Type) (f : X -> Y -> Z) x y,
prod_curry (prod_uncurry f) x y = f x y.
Proof.
reflexivity. Qed.
Theorem surjective_pairing :
forall (X Y : Type) (p : X * Y),
p = (fst p, snd p).
Proof.
intros. destruct p as (n,m). simpl. reflexivity. Qed.
Theorem curry_uncurry : forall (X Y Z : Type)
(f : (X * Y) -> Z) (p : X * Y),
prod_uncurry (prod_curry f) p = f p.
Proof.
intros. unfold prod_uncurry. unfold prod_curry.
rewrite <- surjective_pairing. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Filter *)
(** Here is a useful higher-order function, which takes a list
of [X]s and a _predicate_ on [X] (a function from [X] to [bool])
and "filters" the list, returning a new list containing just those
elements for which the predicate returns [true]. *)
Fixpoint filter {X:Type} (test: X->bool) (l:list X)
: (list X) :=
match l with
| [] => []
| h :: t => if test h then h :: (filter test t)
else filter test t
end.
(** For example, if we apply [filter] to the predicate [evenb]
and a list of numbers [l], it returns a list containing just the
even members of [l]. *)
Example test_filter1: filter evenb [1,2,3,4] = [2,4].
Proof. reflexivity. Qed.
Definition length_is_1 {X : Type} (l : list X) : bool :=
beq_nat (length l) 1.
Example test_filter2:
filter length_is_1
[ [1, 2], [3], [4], [5,6,7], [], [8] ]
= [ [3], [4], [8] ].
Proof. reflexivity. Qed.
(** We can use [filter] to give a concise version of the
[countoddmembers] function from the [Lists] chapter. *)
Definition countoddmembers' (l:list nat) : nat :=
length (filter oddb l).
Example test_countoddmembers'1: countoddmembers' [1,0,3,1,4,5] = 4.
Proof. reflexivity. Qed.
Example test_countoddmembers'2: countoddmembers' [0,2,4] = 0.
Proof. reflexivity. Qed.
Example test_countoddmembers'3: countoddmembers' nil = 0.
Proof. reflexivity. Qed.
(* ###################################################### *)
(** ** Anonymous Functions *)
(** It is a little annoying to be forced to define the function
[length_is_1] and give it a name just to be able to pass it as an
argument to [filter], since we will probably never use it again.
Moreover, this is not an isolated example. When using
higher-order functions, we often want to pass as arguments
"one-off" functions that we will never use again; having to give
each of these functions a name would be tedious.
Fortunately, there is a better way. It is also possible to
construct a function "on the fly" without declaring it at the top
level or giving it a name; this is analogous to the notation we've
been using for writing down constant lists, natural numbers, and
so on. *)
Example test_anon_fun':
doit3times (fun n => n * n) 2 = 256.
Proof. reflexivity. Qed.
(** Here is the motivating example from before, rewritten to use
an anonymous function. *)
Example test_filter2':
filter (fun l => beq_nat (length l) 1)
[ [1, 2], [3], [4], [5,6,7], [], [8] ]
= [ [3], [4], [8] ].
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (filter_even_gt7) *)
(** Use [filter] (instead of [Fixpoint]) to write a Coq function
[filter_even_gt7] which takes a list of natural numbers as input
and keeps only those numbers which are even and greater than 7. *)
Definition filter_even_gt7 (l : list nat) : list nat :=
filter (fun n => andb (evenb n) (negb (ble_nat n 7))) l.
Example test_filter_even_gt7_1 :
filter_even_gt7 [1,2,6,9,10,3,12,8] = [10,12,8].
Proof. reflexivity. Qed.
Example test_filter_even_gt7_2 :
filter_even_gt7 [5,2,6,19,129] = [].
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (partition) *)
(** Use [filter] to write a Coq function [partition]:
partition : forall X : Type,
(X -> bool) -> list X -> list X * list X
Given a set [X], a test function of type [X -> bool] and a [list
X], [partition] should return a pair of lists. The first member of
the pair is the sublist of the original list containing the
elements that satisfy the test, and the second is the sublist
containing those that fail the test. The order of elements in the
two sublists should be the same as their order in the original
list.
*)
Definition partition {X : Type} (test : X -> bool) (l : list X)
: list X * list X :=
(filter test l, filter (fun x => negb (test x)) l).
Example test_partition1: partition oddb [1,2,3,4,5] = ([1,3,5], [2,4]).
Proof. reflexivity. Qed.
Example test_partition2: partition (fun x => false) [5,9,0] = ([], [5,9,0]).
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################### *)
(** ** Map *)
(** Another handy higher-order function is called [map]. *)
Fixpoint map {X Y:Type} (f:X->Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => (f h) :: (map f t)
end.
(** It takes a function [f] and a list [ l = [n1, n2, n3, ...] ]
and returns the list [ [f n1, f n2, f n3,...] ], where [f] has
been applied to each element of [l] in turn. For example: *)
Example test_map1: map (plus 3) [2,0,2] = [5,3,5].
Proof. reflexivity. Qed.
(** The element types of the input and output lists need not be
the same ([map] takes _two_ type arguments, [X] and [Y]). This
version of [map] can thus be applied to a list of numbers and a
function from numbers to booleans to yield a list of booleans: *)
Example test_map2: map oddb [2,1,2,5] = [false,true,false,true].
Proof. reflexivity. Qed.
(** It can even be applied to a list of numbers and
a function from numbers to _lists_ of booleans to
yield a list of lists of booleans: *)
Example test_map3:
map (fun n => [evenb n,oddb n]) [2,1,2,5]
= [[true,false],[false,true],[true,false],[false,true]].
Proof. reflexivity. Qed.
(** **** Exercise: 3 stars, optional (map_rev) *)
(** Show that [map] and [rev] commute. You may need to define an
auxiliary lemma. *)
Theorem map_snoc :
forall (X Y : Type) (f : X -> Y) (l : list X) (x : X),
map f (snoc l x) = snoc (map f l) (f x).
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. rewrite -> IHt. reflexivity. Qed.
Theorem map_rev : forall (X Y : Type) (f : X -> Y) (l : list X),
map f (rev l) = rev (map f l).
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. rewrite -> map_snoc. rewrite -> IHt. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, recommended (flat_map) *)
(** The function [map] maps a [list X] to a [list Y] using a function
of type [X -> Y]. We can define a similar function, [flat_map],
which maps a [list X] to a [list Y] using a function [f] of type
[X -> list Y]. Your definition should work by 'flattening' the
results of [f], like so:
flat_map (fun n => [n,n+1,n+2]) [1,5,10]
= [1, 2, 3, 5, 6, 7, 10, 11, 12].
*)
Fixpoint flat_map {X Y:Type} (f:X -> list Y) (l:list X)
: (list Y) :=
match l with
| [] => []
| h :: t => f h ++ flat_map f t
end.
Example test_flat_map1:
flat_map (fun n => [n,n,n]) [1,5,4]
= [1, 1, 1, 5, 5, 5, 4, 4, 4].
Proof. reflexivity. Qed.
(** [] *)
(** Lists are not the only inductive type that we can write a
[map] function for. Here is the definition of [map] for the
[option] type: *)
Definition option_map {X Y : Type} (f : X -> Y) (xo : option X)
: option Y :=
match xo with
| None => None
| Some x => Some (f x)
end.
(** **** Exercise: 2 stars, optional (implicit_args) *)
(** The definitions and uses of [filter] and [map] use implicit
arguments in many places. Replace the curly braces around the
implicit arguments with parentheses, and then fill in explicit
type parameters where necessary and use Coq to check that you've
done so correctly. This exercise is not to be turned in; it is
probably easiest to do it on a _copy_ of this file that you can
throw away afterwards. [] *)
(* ###################################################### *)
(** ** Fold *)
(** An even more powerful higher-order function is called
[fold]. This function is the inspiration for the "[reduce]"
operation that lies at the heart of Google's map/reduce
distributed programming framework. *)
Fixpoint fold {X Y:Type} (f: X->Y->Y) (l:list X) (b:Y) : Y :=
match l with
| nil => b
| h :: t => f h (fold f t b)
end.
(** Intuitively, the behavior of the [fold] operation is to
insert a given binary operator [f] between every pair of elements
in a given list. For example, [ fold plus [1,2,3,4] ] intuitively
means [1+2+3+4]. To make this precise, we also need a "starting
element" that serves as the initial second input to [f]. So, for
example,
fold plus [1,2,3,4] 0
yields
1 + (2 + (3 + (4 + 0))).
Here are some more examples:
*)
Check (fold plus).
Eval simpl in (fold plus [1,2,3,4] 0).
Example fold_example1 : fold mult [1,2,3,4] 1 = 24.
Proof. reflexivity. Qed.
Example fold_example2 : fold andb [true,true,false,true] true = false.
Proof. reflexivity. Qed.
Example fold_example3 : fold app [[1],[],[2,3],[4]] [] = [1,2,3,4].
Proof. reflexivity. Qed.
(** **** Exercise: 1 star, optional (fold_types_different) *)
(** Observe that the type of [fold] is parameterized by _two_ type
variables, [X] and [Y], and the parameter [f] is a binary operator
that takes an [X] and a [Y] and returns a [Y]. Can you think of a
situation where it would be useful for [X] and [Y] to be
different? *)
(* ###################################################### *)
(** ** Functions For Constructing Functions *)
(** Most of the higher-order functions we have talked about so
far take functions as _arguments_. Now let's look at some
examples involving _returning_ functions as the results of other
functions.
To begin, here is a function that takes a value [x] (drawn from
some type [X]) and returns a function from [nat] to [X] that
yields [x] whenever it is called, ignoring its [nat] argument. *)
Definition constfun {X: Type} (x: X) : nat->X :=
fun (k:nat) => x.
Definition ftrue := constfun true.
Example constfun_example1 : ftrue 0 = true.
Proof. reflexivity. Qed.
Example constfun_example2 : (constfun 5) 99 = 5.
Proof. reflexivity. Qed.
(** Similarly, but a bit more interestingly, here is a function
that takes a function [f] from numbers to some type [X], a number
[k], and a value [x], and constructs a function that behaves
exactly like [f] except that, when called with the argument [k],
it returns [x]. *)
Definition override {X: Type} (f: nat->X) (k:nat) (x:X) : nat->X:=
fun (k':nat) => if beq_nat k k' then x else f k'.
(** For example, we can apply [override] twice to obtain a
function from numbers to booleans that returns [false] on [1] and
[3] and returns [true] on all other arguments. *)
Definition fmostlytrue := override (override ftrue 1 false) 3 false.
Example override_example1 : fmostlytrue 0 = true.
Proof. reflexivity. Qed.
Example override_example2 : fmostlytrue 1 = false.
Proof. reflexivity. Qed.
Example override_example3 : fmostlytrue 2 = true.
Proof. reflexivity. Qed.
Example override_example4 : fmostlytrue 3 = false.
Proof. reflexivity. Qed.
(** **** Exercise: 1 star (override_example) *)
(** Before starting to work on the following proof, make sure you
understand exactly what the theorem is saying and can paraphrase
it in your own words. The proof itself is straightforward. *)
Theorem override_example : forall (b:bool),
(override (constfun b) 3 true) 2 = b.
Proof.
intros. unfold override. unfold constfun. reflexivity. Qed.
(** [] *)
(** We'll use function overriding heavily in parts of the rest of the
course, and we will end up needing to know quite a bit about its
properties. To prove these properties, though, we need to know
about a few more of Coq's tactics; developing these is the main
topic of the rest of the chapter. *)
(* ##################################################### *)
(* ##################################################### *)
(** * Optional Material *)
(** ** Non-Uniform Inductive Families (GADTs) *)
(** _This section needs more text_! *)
(** Recall the definition of lists of booleans:
Inductive boollist : Type :=
boolnil : boollist
| boolcons : bool -> boollist -> boollist.
*)
(** We saw how it could be generalized to "polymorphic lists" with
elements of an arbitrary type [X]. Here's another way of
generalizing it: an inductive family of "length-indexed" lists of
booleans: *)
Inductive boolllist : nat -> Type :=
boollnil : boolllist O
| boollcons : forall n, bool -> boolllist n -> boolllist (S n).
Implicit Arguments boollcons [[n]].
Check (boollcons true (boollcons false (boollcons true boollnil))).
Fixpoint blapp {n1} (l1: boolllist n1)
{n2} (l2: boolllist n2)
: boolllist (n1 + n2) :=
match l1 with
| boollnil => l2
| boollcons _ h t => boollcons h (blapp t l2)
end.
(** Of course, these generalizions can be combined. Here's the
length-indexed polymorphic version: *)
Inductive llist (X:Type) : nat -> Type :=
lnil : llist X O
| lcons : forall n, X -> llist X n -> llist X (S n).
Implicit Arguments lnil [[X]].
Implicit Arguments lcons [[X] [n]].
Check (lcons true (lcons false (lcons true lnil))).
Fixpoint lapp (X:Type)
{n1} (l1: llist X n1)
{n2} (l2: llist X n2)
: llist X (n1 + n2) :=
match l1 with
| lnil => l2
| lcons _ h t => lcons h (lapp X t l2)
end.
(* ###################################################### *)
(** * More About Coq *)
(* ###################################################### *)
(** ** The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n,o] = [n,p] ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with "[rewrite -> eq2. reflexivity.]"
as we have done several times above. But we can achieve the
same effect in a single step by using the [apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q,o] = [r,p]) ->
[n,o] = [m,p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
intros. apply H. rewrite -> H0. reflexivity. Qed.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Admitted.
(** In this case we can use the [symmetry] tactic, which
switches the left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will do a [simpl] step first. *)
apply H. Qed.
(** **** Exercise: 3 stars, recommended (apply_exercise1) *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
intros. rewrite -> H. symmetry. apply rev_involutive. Qed.
(** [] *)
(** **** Exercise: 1 star (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
They are related, but apply is more to do with implications; we can control
the direction of rewrite with -> and of apply with symmetry. Maybe it is
useful to use apply for a conditional, rewrite for something else.
*)
(** [] *)
(* ###################################################### *)
(** ** The [unfold] Tactic *)
(** Sometimes, a proof will get stuck because Coq doesn't
automatically expand a function call into its definition. (This
is a feature, not a bug: if Coq automatically expanded everything
possible, our proof goals would quickly become enormous -- hard to
read and slow for Coq to manipulate!) *)
Theorem unfold_example_bad : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
(* At this point, we'd like to do [rewrite -> H], since
[plus3 n] is definitionally equal to [3 + n]. However,
Coq doesn't automatically expand [plus3 n] to its
definition. *)
Admitted.
(** The [unfold] tactic can be used to explicitly replace a
defined name by the right-hand side of its definition. *)
Theorem unfold_example : forall m n,
3 + n = m ->
plus3 n + 1 = m + 1.
Proof.
intros m n H.
unfold plus3.
rewrite -> H.
reflexivity. Qed.
(** Now we can prove a first property of [override]: If we
override a function at some argument [k] and then look up [k], we
get back the overridden value. *)
Theorem override_eq : forall {X:Type} x k (f:nat->X),
(override f k x) k = x.
Proof.
intros X x k f.
unfold override.
rewrite <- beq_nat_refl.
reflexivity. Qed.
(** This proof was straightforward, but note that it requires
[unfold] to expand the definition of [override]. *)
(** **** Exercise: 2 stars (override_neq) *)
Theorem override_neq : forall {X:Type} x1 x2 k1 k2 (f : nat->X),
f k1 = x1 ->
beq_nat k2 k1 = false ->
(override f k2 x2) k1 = x1.
Proof.
intros. unfold override. rewrite -> H0. rewrite -> H. reflexivity. Qed.
(** [] *)
(** As the inverse of [unfold], Coq also provides a tactic
[fold], which can be used to "unexpand" a definition. It is used
much less often. *)
(* ###################################################### *)
(** ** Inversion *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic, called [inversion], that allows us to
exploit these principles in making proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n,m] = [o,o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
intros. inversion H0. reflexivity. Qed.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
intros. inversion H. Qed.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication, provable by standard equational reasoning, is a
useful fact to record for cases we will see several times. *)
Lemma eq_remove_S : forall n m,
n = m -> S n = S m.
Proof. intros n m eq. rewrite -> eq. reflexivity. Qed.
(** Here's another illustration of [inversion]. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []". intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'". intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply eq_remove_S. apply IHl'. inversion eq. reflexivity. Qed.
(* ###################################################### *)
(** ** Varying the Induction Hypothesis *)
(** Here is a more realistic use of inversion to prove a
property that is useful in many places later on... *)
Theorem beq_nat_eq_FAILED : forall n m,
true = beq_nat n m -> n = m.
Proof.
intros n m H. induction n as [| n'].
Case "n = 0".
destruct m as [| m'].
SCase "m = 0". reflexivity.
SCase "m = S m'". simpl in H. inversion H.
Case "n = S n'".
destruct m as [| m'].
SCase "m = 0". simpl in H. inversion H.
SCase "m = S m'".
apply eq_remove_S.
(* stuck here because the induction hypothesis
talks about an extremely specific m *)
Admitted.
(** The inductive proof above fails because we've set up things so
that the induction hypothesis (in the second subgoal generated by
the [induction] tactic) is
[ true = beq_nat n' m -> n' = m ].
This hypothesis makes a statement about [n'] together with the
_particular_ natural number [m] -- that is, the number [m], which
was introduced into the context by the [intros] at the top of the
proof, is "held constant" in the induction hypothesis. This
induction hypothesis is not strong enough to make the induction
step of the proof go through.
If we set up the proof slightly differently by introducing just
[n] into the context at the top, then we get an induction
hypothesis that makes a stronger claim:
[ forall m : nat, true = beq_nat n' m -> n' = m ]
Setting up the induction hypothesis this way makes the proof of
[beq_nat_eq] go through: *)
Theorem beq_nat_eq : forall n m,
true = beq_nat n m -> n = m.
Proof.
intros n. induction n as [| n'].
Case "n = 0".
intros m. destruct m as [| m'].
SCase "m = 0". reflexivity.
SCase "m = S m'". simpl. intros contra. inversion contra.
Case "n = S n'".
intros m. destruct m as [| m'].
SCase "m = 0". simpl. intros contra. inversion contra.
SCase "m = S m'". simpl. intros H.
apply eq_remove_S. apply IHn'. apply H. Qed.
(** Similar issues will come up in _many_ of the proofs below. If you
ever find yourself in a situation where the induction hypothesis
is insufficient to establish the goal, consider going back and
doing fewer [intros] to make the IH stronger. *)
(** **** Exercise: 2 stars (beq_nat_eq_informal) *)
(** Give an informal proof of [beq_nat_eq]. *)
(* Proof by induction on n.
- Case n = 0: If m is not 0, then we have a contradiction.
- Case n = S n'. If m is 0, then we have a contradiction. If m = S m'
and n' does not equal m', then we have a contradiction. *)
(** [] *)
(** **** Exercise: 3 stars (beq_nat_eq') *)
(** We can also prove beq_nat_eq by induction on [m], though we have
to be a little careful about which order we introduce the
variables, so that we get a general enough induction hypothesis --
this is done for you below. Finish the following proof. To get
maximum benefit from the exercise, try first to do it without
looking back at the one above. *)
Theorem beq_nat_eq' : forall m n,
beq_nat n m = true -> n = m.
Proof.
intros m. induction m as [| m'].
Case "m = O".
intros n. destruct n as [| n'].
SCase "n = O".
intros H. reflexivity.
SCase "n = S n'".
intros H. inversion H.
Case "m = S m'".
intros n. destruct n as [| n'].
SCase "n = O".
intros H. inversion H.
SCase "n = S n'".
intros H. apply eq_remove_S. inversion H. apply IHm'. apply H1. Qed.
(** [] *)
(* ###################################################### *)
(** *** Practice Session *)
(** **** Exercise: 2 stars, optional (practice) *)
(** Some nontrivial but not-too-complicated proofs to work together in
class, and some for you to work as exercises. Some of the
exercises may involve applying lemmas from earlier lectures or
homeworks. *)
Theorem beq_nat_0_l : forall n,
true = beq_nat 0 n -> 0 = n.
Proof.
intros. apply beq_nat_eq. apply H. Qed.
Theorem beq_nat_0_r : forall n,
true = beq_nat n 0 -> 0 = n.
Proof.
intros. destruct n as [| n'].
Case "n = O".
reflexivity.
Case "n = S n'".
inversion H. Qed.
(** [] *)
(** **** Exercise: 3 stars (apply_exercise2) *)
(** In the following proof opening, notice that we don't introduce [m]
before performing induction. This leaves it general, so that the
IH doesn't specify a particular [m], but lets us pick. Finish the
proof. *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
intros n. induction n as [| n'].
Case "n = O".
intros m. destruct m as [| m'].
SCase "m = O".
reflexivity.
SCase "m = S m'".
reflexivity.
Case "n = S n'".
intros m. destruct m as [| m'].
SCase "m = O".
reflexivity.
SCase "m = S m'".
simpl. apply IHn'. Qed.
(** [] *)
(** **** Exercise: 3 stars (beq_nat_sym_informal) *)
(** Provide an informal proof of this lemma that corresponds
to your formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof: By induction on n.
- Case n = 0: Straightforward.
- Case n = S n': If m = S m', then by the injectivity of the
constructors we only need to show beq_nat n' m' = beq_nat m' n',
which we have immediately induction hypothesis.
[]
*)
(* ###################################################### *)
(** ** Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars, recommended (plus_n_n_injective) *)
(** You can practice using the "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = 0".
intros m H. destruct m as [| m'].
SCase "m = 0".
reflexivity.
SCase "m = S m'".
inversion H.
Case "n = S n'".
intros m H. destruct m as [| m'].
SCase "m = 0".
inversion H.
SCase "m = S m'".
inversion H. rewrite <- plus_n_Sm in H1. symmetry in H1.
rewrite <- plus_n_Sm in H1. apply eq_add_S in H1. symmetry in H1.
apply IHn' in H1. apply eq_remove_S in H1. apply H1. Qed.
(** [] *)
(* ###################################################### *)
(** ** Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases. *)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall {X:Type} x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
intros. unfold override. destruct (beq_nat k1 k2).
Case "beq_nat k1 k2 = true". reflexivity.
Case "beq_nat k1 k2 = false". reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (combine_split) *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
intros X Y l. induction l as [| [x y] l'].
Case "l = []".
intros l1 l2 H. inversion H. reflexivity.
Case "l = (x,y) :: l'".
intros l1 l2 H. inversion H. destruct (split l').
inversion H1. simpl. rewrite -> IHl'. reflexivity.
reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (split_combine) *)
(** Thought exercise: We have just proven that for all lists of pairs,
[combine] is the inverse of [split]. How would you state the
theorem showing that [split] is the inverse of [combine]?
Hint: what property do you need of [l1] and [l2] for [split]
[combine l1 l2 = (l1,l2)] to be true?
State this theorem in Coq, and prove it. (Be sure to leave your
induction hypothesis general by not doing [intros] on more things
than necessary.) *)
Theorem length_nil_inv :
forall X (l : list X), length l = 0 -> l = [].
Proof.
intros. destruct l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
inversion H. Qed.
Theorem split_combine :
forall X Y (l : list (X * Y)) l1 l2,
length l1 = length l2 ->
combine l1 l2 = l ->
split l = (l1, l2).
Proof.
intros X Y l. induction l as [| [x y] l'].
Case "l = []".
intros l1 l2 H1 H2. destruct l1 as [| x' l1'].
SCase "l1 = []".
simpl in H1. symmetry in H1. apply length_nil_inv in H1. rewrite -> H1.
reflexivity.
SCase "l1 = x' :: l1'".
simpl in H1. inversion H2. destruct l2 as [| y' l2'].
SSCase "l2 = []". inversion H1.
SSCase "l2 = y' :: l2'". inversion H2.
Case "l = (x,y) :: l'".
intros l1 l2 H1 H2. simpl. destruct (split l').
destruct l1 as [| x' l1'].
SCase "l1 = []".
inversion H2.
SCase "l1 = x' :: l1'".
destruct l2 as [| y' l2'].
SSCase "l2 = []".
inversion H2.
SSCase "l2 = y' :: l2'".
inversion H1. inversion H2. apply IHl' in H0. inversion H0. reflexivity.
apply H5. Qed.
(** [] *)
(* ###################################################### *)
(** ** The [remember] Tactic *)
(** (Note: the [remember] tactic is not strictly needed until a
bit later, so if necessary this section can be skipped and
returned to when needed.) *)
(** We have seen how the [destruct] tactic can be used to
perform case analysis of the results of arbitrary computations.
If [e] is an expression whose type is some inductively defined
type [T], then, for each constructor [c] of [T], [destruct e]
generates a subgoal in which all occurrences of [e] (in the goal
and in the context) are replaced by [c].
Sometimes, however, this substitution process loses information
that we need in order to complete the proof. For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Admitted.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep at
least one of these because we need to be able to reason that
since, in this branch of the case analysis, [beq_nat n 3 = true],
it must be that [n = 3], from which it follows that [n] is odd.
What we would really like is not to use [destruct] directly on
[beq_nat n 3] and substitute away all occurrences of this
expression, but rather to use [destruct] on something else that is
_equal_ to [beq_nat n 3]. For example, if we had a variable that
we knew was equal to [beq_nat n 3], we could [destruct] this
variable instead.
The [remember] tactic allows us to introduce such a variable. *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
remember (beq_nat n 3) as e3.
(* At this point, the context has been enriched with a new
variable [e3] and an assumption that [e3 = beq_nat n 3].
Now if we do [destruct e3]... *)
destruct e3.
(* ... the variable [e3] gets substituted away (it
disappears completely) and we are left with the same
state as at the point where we got stuck above, except
that the context still contains the extra equality
assumption -- now with [true] substituted for [e3] --
which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_eq in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the
body of the function we are reasoning about, we can
use [remember] again in the same way, allowing us
to finish the proof. *)
remember (beq_nat n 5) as e5. destruct e5.
SCase "e5 = true".
apply beq_nat_eq in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall {X:Type} x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
intros. unfold override. remember (beq_nat k1 k2) as b. destruct b.
Case "b = true".
apply beq_nat_eq in Heqb. rewrite <- Heqb. rewrite -> H. reflexivity.
Case "b = false".
reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, optional (filter_exercise) *)
(** This one is a bit challenging. Be sure your initial [intros] go
only up through the parameter on which you want to do
induction! *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
intros X test x l. induction l as [| h t].
Case "l = []".
intros lf H. inversion H.
Case "l = h :: t".
intros lf H. inversion H. remember (test h) as b. destruct b.
SCase "b = true".
inversion H1. rewrite <- H2. symmetry. apply Heqb.
SCase "b = false".
apply IHt in H1. apply H1. Qed.
(** [] *)
(* ###################################################### *)
(** ** The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a,b] = [c,d] ->
[c,d] = [e,f] ->
[a,b] = [e,f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall {X:Type} (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a,b] = [c,d] ->
[c,d] = [e,f] ->
[a,b] = [e,f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c,d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: apply trans_eq with [c,d]. *)
(** **** Exercise: 3 stars, recommended (apply_exercises) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
intros n m o p eq1 eq2. apply trans_eq with m. apply eq2. apply eq1. Qed.
Theorem beq_nat_trans : forall n m p,
true = beq_nat n m ->
true = beq_nat m p ->
true = beq_nat n p.
Proof.
intros n m p eq1 eq2. apply beq_nat_eq in eq1. rewrite <- eq1 in eq2.
apply eq2. Qed.
Theorem override_permute : forall {X:Type} x1 x2 k1 k2 k3 (f : nat->X),
false = beq_nat k2 k1 ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
intros. unfold override. remember (beq_nat k1 k3) as b1. destruct b1.
Case "b1 = true".
apply beq_nat_eq in Heqb1. rewrite -> Heqb1 in H. rewrite <- H. reflexivity.
Case "b1 = false".
reflexivity. Qed.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics -- enough to
do pretty much everything we'll want for a while. We'll introduce
one or two more as we go along through the next few lectures, and
later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [remember (e) as x]:
give a name ([x]) to an expression ([e]) so that we can
destruct [x] without "losing" [e]
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 2 stars, optional (fold_length) *)
(** Many common functions on lists can be implemented in terms of
[fold]. For example, here is an alternate definition of [length]: *)
Definition fold_length {X : Type} (l : list X) : nat :=
fold (fun _ n => S n) l 0.
Example test_fold_length1 : fold_length [4,7,0] = 3.
Proof. reflexivity. Qed.
(** Prove the correctness of [fold_length]. *)
Theorem fold_length_correct : forall X (l : list X),
fold_length l = length l.
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. unfold fold_length. simpl. unfold fold_length in IHt.
rewrite -> IHt. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars, recommended (fold_map) *)
(** We can also define [map] in terms of [fold]. Finish [fold_map]
below. *)
Definition fold_map {X Y:Type} (f : X -> Y) (l : list X) : list Y :=
fold (fun x l' => f x :: l') l [].
(** Write down a theorem in Coq stating that [fold_map] is correct,
and prove it. *)
Theorem fold_map_correct :
forall X Y (f : X -> Y) (l : list X),
fold_map f l = map f l.
Proof.
intros. induction l as [| h t].
Case "l = []".
reflexivity.
Case "l = h :: t".
simpl. unfold fold_map. simpl. unfold fold_map in IHt.
rewrite -> IHt. reflexivity. Qed.
(** [] *)
Module MumbleBaz.
(** **** Exercise: 2 stars, optional (mumble_grumble) *)
(** Consider the following two inductively defined types. *)
Inductive mumble : Type :=
| a : mumble
| b : mumble -> nat -> mumble
| c : mumble.
Inductive grumble (X:Type) : Type :=
| d : mumble -> grumble X
| e : X -> grumble X.
(** Which of the following are well-typed elements of [grumble X] for
some type [X]?
- [d (b a 5)] no
- [d mumble (b a 5)] yes
- [d bool (b a 5)] yes
- [e bool true] yes
- [e mumble (b c 0)] yes
- [e bool (b c 0)] no
- [c] no
[] *)
(** **** Exercise: 2 stars, optional (baz_num_elts) *)
(** Consider the following inductive definition: *)
Inductive baz : Type :=
| x : baz -> baz
| y : baz -> bool -> baz.
(** How _many_ elements does the type [baz] have?
I want to say zero, since there is no base type.
[] *)
End MumbleBaz.
(** **** Exercise: 4 stars, recommended (forall_exists_challenge) *)
(** Challenge problem: Define two recursive [Fixpoints],
[forallb] and [existsb]. The first checks whether every
element in a list satisfies a given predicate:
forallb oddb [1,3,5,7,9] = true
forallb negb [false,false] = true
forallb evenb [0,2,4,5] = false
forallb (beq_nat 5) [] = true
The function [existsb] checks whether there exists an element in
the list that satisfies a given predicate:
existsb (beq_nat 5) [0,2,3,6] = false
existsb (andb true) [true,true,false] = true
existsb oddb [1,0,0,0,0,3] = true
existsb evenb [] = false
Next, create a _nonrecursive_ [Definition], [existsb'], using
[forallb] and [negb].
Prove that [existsb'] and [existsb] have the same behavior.
*)
Fixpoint forallb {X:Type} (f:X -> bool) (l:list X) : bool :=
match l with
| [] => true
| x :: l' => if f x then forallb f l' else false
end.
Fixpoint existsb {X:Type} (f:X -> bool) (l:list X) : bool :=
match l with
| [] => false
| x :: l' => if f x then true else existsb f l'
end.
Definition existsb' {X:Type} (f:X -> bool) (l:list X) : bool :=
negb (forallb (fun x => negb (f x)) l).
Theorem forall_exists_challenge :
forall X (f:X -> bool) (l:list X),
existsb f l = existsb' f l.
Proof.
intros. induction l as [| h t].
Case "l = []".
unfold existsb'. reflexivity.
Case "l = h :: t".
unfold existsb'. simpl. remember (f h) as b. destruct b.
SCase "f h = true".
reflexivity.
SCase "f h = false".
simpl. unfold existsb' in IHt. rewrite -> IHt. reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars, optional (index_informal) *)
(** Recall the definition of the [index] function:
Fixpoint index {X : Type} (n : nat) (l : list X) : option X :=
match l with
| [] => None
| a :: l' => if beq_nat n O then Some a else index (pred n) l'
end.
Write an informal proof of the following theorem:
forall X n l, length l = n -> @index X (S n) l = None.
Proof: By induction on n.
- Case n = 0: Immediate by the definition of index since l = [].
- Case n = S n': Then l = h :: t with length t = n'. We must show that
@index X (S (S n')) (h :: t) = None. It suffices to show that
@index X (S n') t = None, which we have immediately by induction.
The formal proof is below:
*)
Theorem index_formal :
forall (X:Type) (n:nat) (l:list X),
length l = n -> @index X (S n) l = None.
Proof.
intros X n. induction n as [| n'].
Case "n = 0".
intros l H. apply length_nil_inv in H. rewrite -> H. reflexivity.
Case "n = S n'".
intros l H. destruct l as [| h t].
SCase "l = []".
inversion H.
SCase "l = h :: t".
inversion H. apply IHn' in H1. simpl. inversion H. rewrite -> H2.
apply IHn'. apply H2. Qed.
(** [] *)
|
//==================================================================================================
// Filename : antares_hazard_unit.v
// Created On : Fri Sep 4 22:32:20 2015
// Last Modified : Sat Nov 07 12:03:58 2015
// Revision : 1.0
// Author : Angel Terrones
// Company : Universidad Simón Bolívar
// Email : [email protected]
//
// Description : Hazard detection and pipeline control unit.
//==================================================================================================
`include "antares_defines.v"
module antares_hazard_unit (
input [7:0] DP_Hazards, //
input [4:0] id_rs, // Rs @ ID stage
input [4:0] id_rt, // Rt @ ID stage
input [4:0] ex_rs, // Rs @ EX stage
input [4:0] ex_rt, // Rt @ EX stage
input [4:0] ex_gpr_wa, // Write Address @ EX stage
input [4:0] mem_gpr_wa, // Write Address @ MEM stage
input [4:0] wb_gpr_wa, // Write Address @ WB stage
input ex_gpr_we, // GPR write enable @ EX
input mem_gpr_we, // GPR write enable @ MEM
input wb_gpr_we, // GPR write enable @ WB
input mem_mem_write, //
input mem_mem_read, //
input ex_request_stall, // Ex unit request a stall
input dmem_request_stall, // LSU: stall for Data access
input imem_request_stall, // LSU: stall for Instruction Fetch
input if_exception_stall, // Stall waiting for possible exception
input id_exception_stall, // Stall waiting for possible exception
input ex_exception_stall, // Stall waiting for possible exception
input mem_exception_stall, //
output [1:0] forward_id_rs, // Forwarding Rs multiplexer: Selector @ ID
output [1:0] forward_id_rt, // Forwarding Rt multiplexer: Selector @ ID
output [1:0] forward_ex_rs, // Forwarding Rs multiplexer: Selector @ EX
output [1:0] forward_ex_rt, // Forwarding Rt multiplexer: Selector @ EX
output if_stall, // Stall pipeline register
output id_stall, // Stall pipeline register
output ex_stall, // Stall pipeline register
//output ex_stall_unit; // Stall the EX unit.
output mem_stall, // Stall pipeline register
output wb_stall // Stall pipeline register
);
//--------------------------------------------------------------------------
// Signal Declaration: wire
//--------------------------------------------------------------------------
// no forwarding if reading register zero
wire ex_wa_nz;
wire mem_wa_nz;
wire wb_wa_nz;
// Need/Want signals
wire WantRsID;
wire WantRtID;
wire WantRsEX;
wire WantRtEX;
wire NeedRsID;
wire NeedRtID;
wire NeedRsEX;
wire NeedRtEX;
// verify match: register address and write address (EX, MEM & WB)
wire id_ex_rs_match;
wire id_ex_rt_match;
wire id_mem_rs_match;
wire id_mem_rt_match;
wire id_wb_rs_match;
wire id_wb_rt_match;
wire ex_mem_rs_match;
wire ex_mem_rt_match;
wire ex_wb_rs_match;
wire ex_wb_rt_match;
// stall signals
wire stall_id_1;
wire stall_id_2;
wire stall_id_3;
wire stall_id_4;
wire stall_ex_1;
wire stall_ex_2;
// forward signals
wire forward_mem_id_rs;
wire forward_mem_id_rt;
wire forward_wb_id_rs;
wire forward_wb_id_rt;
wire forward_mem_ex_rs;
wire forward_mem_ex_rt;
wire forward_wb_ex_rs;
wire forward_wb_ex_rt;
//--------------------------------------------------------------------------
// assignments
//--------------------------------------------------------------------------
assign WantRsID = DP_Hazards[7];
assign NeedRsID = DP_Hazards[6];
assign WantRtID = DP_Hazards[5];
assign NeedRtID = DP_Hazards[4];
assign WantRsEX = DP_Hazards[3];
assign NeedRsEX = DP_Hazards[2];
assign WantRtEX = DP_Hazards[1];
assign NeedRtEX = DP_Hazards[0];
// Check if the register to use is $zero
assign ex_wa_nz = |(ex_gpr_wa);
assign mem_wa_nz = |(mem_gpr_wa);
assign wb_wa_nz = |(wb_gpr_wa);
// ID dependencies
assign id_ex_rs_match = (ex_wa_nz) & (id_rs == ex_gpr_wa) & (WantRsID | NeedRsID) & ex_gpr_we;
assign id_ex_rt_match = (ex_wa_nz) & (id_rt == ex_gpr_wa) & (WantRtID | NeedRtID) & ex_gpr_we;
assign id_mem_rs_match = (mem_wa_nz) & (id_rs == mem_gpr_wa) & (WantRsID | NeedRsID) & mem_gpr_we;
assign id_mem_rt_match = (mem_wa_nz) & (id_rt == mem_gpr_wa) & (WantRtID | NeedRtID) & mem_gpr_we;
assign id_wb_rs_match = (wb_wa_nz) & (id_rs == wb_gpr_wa) & (WantRsID | NeedRsID) & wb_gpr_we;
assign id_wb_rt_match = (wb_wa_nz) & (id_rt == wb_gpr_wa) & (WantRtID | NeedRtID) & wb_gpr_we;
// EX dependencies
assign ex_mem_rs_match = (mem_wa_nz) & (ex_rs == mem_gpr_wa) & (WantRsEX | NeedRsEX) & mem_gpr_we;
assign ex_mem_rt_match = (mem_wa_nz) & (ex_rt == mem_gpr_wa) & (WantRtEX | NeedRtEX) & mem_gpr_we;
assign ex_wb_rs_match = (wb_wa_nz) & (ex_rs == wb_gpr_wa) & (WantRsEX | NeedRsEX) & wb_gpr_we;
assign ex_wb_rt_match = (wb_wa_nz) & (ex_rt == wb_gpr_wa) & (WantRtEX | NeedRtEX) & wb_gpr_we;
// stall signals
assign stall_id_1 = id_ex_rs_match & NeedRsID; // Needs data from EX (Rs)
assign stall_id_2 = id_ex_rt_match & NeedRtID; // Needs data from EX (Rt)
assign stall_id_3 = id_mem_rs_match & NeedRsID & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rs)
assign stall_id_4 = id_mem_rt_match & NeedRtID & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rt)
assign stall_ex_1 = ex_mem_rs_match & NeedRsEX & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rs)
assign stall_ex_2 = ex_mem_rt_match & NeedRtEX & (mem_mem_read | mem_mem_write); // Needs data from MEM (Rt)
// forwarding signals
assign forward_mem_id_rs = id_mem_rs_match & ~(mem_mem_read | mem_mem_write); // forward if not mem access
assign forward_mem_id_rt = id_mem_rt_match & ~(mem_mem_read | mem_mem_write); // forward if not mem access;
assign forward_wb_id_rs = id_wb_rs_match;
assign forward_wb_id_rt = id_wb_rt_match;
assign forward_mem_ex_rs = ex_mem_rs_match & ~(mem_mem_read | mem_mem_write);
assign forward_mem_ex_rt = ex_mem_rt_match & ~(mem_mem_read | mem_mem_write);
assign forward_wb_ex_rs = ex_wb_rs_match;
assign forward_wb_ex_rt = ex_wb_rt_match;
//--------------------------------------------------------------------------
// Assign stall signals
//--------------------------------------------------------------------------
assign wb_stall = mem_stall;
assign mem_stall = dmem_request_stall | mem_exception_stall | if_stall; // check the if_stall
assign ex_stall = stall_ex_1 | stall_ex_2 | ex_exception_stall | ex_request_stall | mem_stall;
assign id_stall = stall_id_1 | stall_id_2 | stall_id_3 | stall_id_4 | id_exception_stall | ex_stall;
assign if_stall = imem_request_stall | if_exception_stall;
//--------------------------------------------------------------------------
// forwarding control signals
//--------------------------------------------------------------------------
// sel | ID stage | EX stage
//--------------------------------------------------------------------------
// 00 -> ID (no forwarding) | EX (no forwarding)
// 01 -> MEM | MEM
// 10 -> WB | WB
// 11 -> don't care | don't care
//--------------------------------------------------------------------------
assign forward_id_rs = (forward_mem_id_rs) ? 2'b01 : ((forward_wb_id_rs) ? 2'b10 : 2'b00);
assign forward_id_rt = (forward_mem_id_rt) ? 2'b01 : ((forward_wb_id_rt) ? 2'b10 : 2'b00);
assign forward_ex_rs = (forward_mem_ex_rs) ? 2'b01 : ((forward_wb_ex_rs) ? 2'b10 : 2'b00);
assign forward_ex_rt = (forward_mem_ex_rt) ? 2'b01 : ((forward_wb_ex_rt) ? 2'b10 : 2'b00);
endmodule // antares_hazard_unit
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__O2BB2A_BLACKBOX_V
`define SKY130_FD_SC_HS__O2BB2A_BLACKBOX_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__O2BB2A_BLACKBOX_V
|
// soc_system_hps_0_hps_io.v
// This file was auto-generated from altera_hps_io_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 14.1 188 at 2015.01.20.10:18:06
`timescale 1 ps / 1 ps
module soc_system_hps_0_hps_io (
output wire [14:0] mem_a, // memory.mem_a
output wire [2:0] mem_ba, // .mem_ba
output wire mem_ck, // .mem_ck
output wire mem_ck_n, // .mem_ck_n
output wire mem_cke, // .mem_cke
output wire mem_cs_n, // .mem_cs_n
output wire mem_ras_n, // .mem_ras_n
output wire mem_cas_n, // .mem_cas_n
output wire mem_we_n, // .mem_we_n
output wire mem_reset_n, // .mem_reset_n
inout wire [31:0] mem_dq, // .mem_dq
inout wire [3:0] mem_dqs, // .mem_dqs
inout wire [3:0] mem_dqs_n, // .mem_dqs_n
output wire mem_odt, // .mem_odt
output wire [3:0] mem_dm, // .mem_dm
input wire oct_rzqin, // .oct_rzqin
output wire hps_io_emac1_inst_TX_CLK, // hps_io.hps_io_emac1_inst_TX_CLK
output wire hps_io_emac1_inst_TXD0, // .hps_io_emac1_inst_TXD0
output wire hps_io_emac1_inst_TXD1, // .hps_io_emac1_inst_TXD1
output wire hps_io_emac1_inst_TXD2, // .hps_io_emac1_inst_TXD2
output wire hps_io_emac1_inst_TXD3, // .hps_io_emac1_inst_TXD3
input wire hps_io_emac1_inst_RXD0, // .hps_io_emac1_inst_RXD0
inout wire hps_io_emac1_inst_MDIO, // .hps_io_emac1_inst_MDIO
output wire hps_io_emac1_inst_MDC, // .hps_io_emac1_inst_MDC
input wire hps_io_emac1_inst_RX_CTL, // .hps_io_emac1_inst_RX_CTL
output wire hps_io_emac1_inst_TX_CTL, // .hps_io_emac1_inst_TX_CTL
input wire hps_io_emac1_inst_RX_CLK, // .hps_io_emac1_inst_RX_CLK
input wire hps_io_emac1_inst_RXD1, // .hps_io_emac1_inst_RXD1
input wire hps_io_emac1_inst_RXD2, // .hps_io_emac1_inst_RXD2
input wire hps_io_emac1_inst_RXD3, // .hps_io_emac1_inst_RXD3
inout wire hps_io_sdio_inst_CMD, // .hps_io_sdio_inst_CMD
inout wire hps_io_sdio_inst_D0, // .hps_io_sdio_inst_D0
inout wire hps_io_sdio_inst_D1, // .hps_io_sdio_inst_D1
output wire hps_io_sdio_inst_CLK, // .hps_io_sdio_inst_CLK
inout wire hps_io_sdio_inst_D2, // .hps_io_sdio_inst_D2
inout wire hps_io_sdio_inst_D3, // .hps_io_sdio_inst_D3
inout wire hps_io_usb1_inst_D0, // .hps_io_usb1_inst_D0
inout wire hps_io_usb1_inst_D1, // .hps_io_usb1_inst_D1
inout wire hps_io_usb1_inst_D2, // .hps_io_usb1_inst_D2
inout wire hps_io_usb1_inst_D3, // .hps_io_usb1_inst_D3
inout wire hps_io_usb1_inst_D4, // .hps_io_usb1_inst_D4
inout wire hps_io_usb1_inst_D5, // .hps_io_usb1_inst_D5
inout wire hps_io_usb1_inst_D6, // .hps_io_usb1_inst_D6
inout wire hps_io_usb1_inst_D7, // .hps_io_usb1_inst_D7
input wire hps_io_usb1_inst_CLK, // .hps_io_usb1_inst_CLK
output wire hps_io_usb1_inst_STP, // .hps_io_usb1_inst_STP
input wire hps_io_usb1_inst_DIR, // .hps_io_usb1_inst_DIR
input wire hps_io_usb1_inst_NXT, // .hps_io_usb1_inst_NXT
output wire hps_io_spim1_inst_CLK, // .hps_io_spim1_inst_CLK
output wire hps_io_spim1_inst_MOSI, // .hps_io_spim1_inst_MOSI
input wire hps_io_spim1_inst_MISO, // .hps_io_spim1_inst_MISO
output wire hps_io_spim1_inst_SS0, // .hps_io_spim1_inst_SS0
input wire hps_io_uart0_inst_RX, // .hps_io_uart0_inst_RX
output wire hps_io_uart0_inst_TX, // .hps_io_uart0_inst_TX
inout wire hps_io_i2c0_inst_SDA, // .hps_io_i2c0_inst_SDA
inout wire hps_io_i2c0_inst_SCL, // .hps_io_i2c0_inst_SCL
inout wire hps_io_i2c1_inst_SDA, // .hps_io_i2c1_inst_SDA
inout wire hps_io_i2c1_inst_SCL, // .hps_io_i2c1_inst_SCL
inout wire hps_io_gpio_inst_GPIO09, // .hps_io_gpio_inst_GPIO09
inout wire hps_io_gpio_inst_GPIO35, // .hps_io_gpio_inst_GPIO35
inout wire hps_io_gpio_inst_GPIO40, // .hps_io_gpio_inst_GPIO40
inout wire hps_io_gpio_inst_GPIO53, // .hps_io_gpio_inst_GPIO53
inout wire hps_io_gpio_inst_GPIO54, // .hps_io_gpio_inst_GPIO54
inout wire hps_io_gpio_inst_GPIO61 // .hps_io_gpio_inst_GPIO61
);
soc_system_hps_0_hps_io_border border (
.mem_a (mem_a), // memory.mem_a
.mem_ba (mem_ba), // .mem_ba
.mem_ck (mem_ck), // .mem_ck
.mem_ck_n (mem_ck_n), // .mem_ck_n
.mem_cke (mem_cke), // .mem_cke
.mem_cs_n (mem_cs_n), // .mem_cs_n
.mem_ras_n (mem_ras_n), // .mem_ras_n
.mem_cas_n (mem_cas_n), // .mem_cas_n
.mem_we_n (mem_we_n), // .mem_we_n
.mem_reset_n (mem_reset_n), // .mem_reset_n
.mem_dq (mem_dq), // .mem_dq
.mem_dqs (mem_dqs), // .mem_dqs
.mem_dqs_n (mem_dqs_n), // .mem_dqs_n
.mem_odt (mem_odt), // .mem_odt
.mem_dm (mem_dm), // .mem_dm
.oct_rzqin (oct_rzqin), // .oct_rzqin
.hps_io_emac1_inst_TX_CLK (hps_io_emac1_inst_TX_CLK), // hps_io.hps_io_emac1_inst_TX_CLK
.hps_io_emac1_inst_TXD0 (hps_io_emac1_inst_TXD0), // .hps_io_emac1_inst_TXD0
.hps_io_emac1_inst_TXD1 (hps_io_emac1_inst_TXD1), // .hps_io_emac1_inst_TXD1
.hps_io_emac1_inst_TXD2 (hps_io_emac1_inst_TXD2), // .hps_io_emac1_inst_TXD2
.hps_io_emac1_inst_TXD3 (hps_io_emac1_inst_TXD3), // .hps_io_emac1_inst_TXD3
.hps_io_emac1_inst_RXD0 (hps_io_emac1_inst_RXD0), // .hps_io_emac1_inst_RXD0
.hps_io_emac1_inst_MDIO (hps_io_emac1_inst_MDIO), // .hps_io_emac1_inst_MDIO
.hps_io_emac1_inst_MDC (hps_io_emac1_inst_MDC), // .hps_io_emac1_inst_MDC
.hps_io_emac1_inst_RX_CTL (hps_io_emac1_inst_RX_CTL), // .hps_io_emac1_inst_RX_CTL
.hps_io_emac1_inst_TX_CTL (hps_io_emac1_inst_TX_CTL), // .hps_io_emac1_inst_TX_CTL
.hps_io_emac1_inst_RX_CLK (hps_io_emac1_inst_RX_CLK), // .hps_io_emac1_inst_RX_CLK
.hps_io_emac1_inst_RXD1 (hps_io_emac1_inst_RXD1), // .hps_io_emac1_inst_RXD1
.hps_io_emac1_inst_RXD2 (hps_io_emac1_inst_RXD2), // .hps_io_emac1_inst_RXD2
.hps_io_emac1_inst_RXD3 (hps_io_emac1_inst_RXD3), // .hps_io_emac1_inst_RXD3
.hps_io_sdio_inst_CMD (hps_io_sdio_inst_CMD), // .hps_io_sdio_inst_CMD
.hps_io_sdio_inst_D0 (hps_io_sdio_inst_D0), // .hps_io_sdio_inst_D0
.hps_io_sdio_inst_D1 (hps_io_sdio_inst_D1), // .hps_io_sdio_inst_D1
.hps_io_sdio_inst_CLK (hps_io_sdio_inst_CLK), // .hps_io_sdio_inst_CLK
.hps_io_sdio_inst_D2 (hps_io_sdio_inst_D2), // .hps_io_sdio_inst_D2
.hps_io_sdio_inst_D3 (hps_io_sdio_inst_D3), // .hps_io_sdio_inst_D3
.hps_io_usb1_inst_D0 (hps_io_usb1_inst_D0), // .hps_io_usb1_inst_D0
.hps_io_usb1_inst_D1 (hps_io_usb1_inst_D1), // .hps_io_usb1_inst_D1
.hps_io_usb1_inst_D2 (hps_io_usb1_inst_D2), // .hps_io_usb1_inst_D2
.hps_io_usb1_inst_D3 (hps_io_usb1_inst_D3), // .hps_io_usb1_inst_D3
.hps_io_usb1_inst_D4 (hps_io_usb1_inst_D4), // .hps_io_usb1_inst_D4
.hps_io_usb1_inst_D5 (hps_io_usb1_inst_D5), // .hps_io_usb1_inst_D5
.hps_io_usb1_inst_D6 (hps_io_usb1_inst_D6), // .hps_io_usb1_inst_D6
.hps_io_usb1_inst_D7 (hps_io_usb1_inst_D7), // .hps_io_usb1_inst_D7
.hps_io_usb1_inst_CLK (hps_io_usb1_inst_CLK), // .hps_io_usb1_inst_CLK
.hps_io_usb1_inst_STP (hps_io_usb1_inst_STP), // .hps_io_usb1_inst_STP
.hps_io_usb1_inst_DIR (hps_io_usb1_inst_DIR), // .hps_io_usb1_inst_DIR
.hps_io_usb1_inst_NXT (hps_io_usb1_inst_NXT), // .hps_io_usb1_inst_NXT
.hps_io_spim1_inst_CLK (hps_io_spim1_inst_CLK), // .hps_io_spim1_inst_CLK
.hps_io_spim1_inst_MOSI (hps_io_spim1_inst_MOSI), // .hps_io_spim1_inst_MOSI
.hps_io_spim1_inst_MISO (hps_io_spim1_inst_MISO), // .hps_io_spim1_inst_MISO
.hps_io_spim1_inst_SS0 (hps_io_spim1_inst_SS0), // .hps_io_spim1_inst_SS0
.hps_io_uart0_inst_RX (hps_io_uart0_inst_RX), // .hps_io_uart0_inst_RX
.hps_io_uart0_inst_TX (hps_io_uart0_inst_TX), // .hps_io_uart0_inst_TX
.hps_io_i2c0_inst_SDA (hps_io_i2c0_inst_SDA), // .hps_io_i2c0_inst_SDA
.hps_io_i2c0_inst_SCL (hps_io_i2c0_inst_SCL), // .hps_io_i2c0_inst_SCL
.hps_io_i2c1_inst_SDA (hps_io_i2c1_inst_SDA), // .hps_io_i2c1_inst_SDA
.hps_io_i2c1_inst_SCL (hps_io_i2c1_inst_SCL), // .hps_io_i2c1_inst_SCL
.hps_io_gpio_inst_GPIO09 (hps_io_gpio_inst_GPIO09), // .hps_io_gpio_inst_GPIO09
.hps_io_gpio_inst_GPIO35 (hps_io_gpio_inst_GPIO35), // .hps_io_gpio_inst_GPIO35
.hps_io_gpio_inst_GPIO40 (hps_io_gpio_inst_GPIO40), // .hps_io_gpio_inst_GPIO40
.hps_io_gpio_inst_GPIO53 (hps_io_gpio_inst_GPIO53), // .hps_io_gpio_inst_GPIO53
.hps_io_gpio_inst_GPIO54 (hps_io_gpio_inst_GPIO54), // .hps_io_gpio_inst_GPIO54
.hps_io_gpio_inst_GPIO61 (hps_io_gpio_inst_GPIO61) // .hps_io_gpio_inst_GPIO61
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NOR3B_BLACKBOX_V
`define SKY130_FD_SC_MS__NOR3B_BLACKBOX_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__nor3b (
Y ,
A ,
B ,
C_N
);
output Y ;
input A ;
input B ;
input C_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NOR3B_BLACKBOX_V
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * Copyright INRIA, CNRS and contributors *)
(* <O___,, * (see version control and CREDITS file for authors & dates) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
Require Import PeanoNat.
Set Implicit Arguments.
(* Set Universe Polymorphism. *)
(******************************************************************)
(** * Basics: definition of polymorphic lists and some operations *)
(******************************************************************)
(** The definition of [list] is now in [Init/Datatypes],
as well as the definitions of [length] and [app] *)
#[local] Open Scope bool_scope.
Open Scope list_scope.
(** Standard notations for lists.
In a special module to avoid conflicts. *)
Module ListNotations.
Notation "[ ]" := nil (format "[ ]") : list_scope.
Notation "[ x ]" := (cons x nil) : list_scope.
Notation "[ x ; y ; .. ; z ]" := (cons x (cons y .. (cons z nil) ..)) : list_scope.
End ListNotations.
Import ListNotations.
Section Lists.
Variable A : Type.
(** Head and tail *)
Definition hd (default:A) (l:list A) :=
match l with
| [] => default
| x :: _ => x
end.
Definition hd_error (l:list A) :=
match l with
| [] => None
| x :: _ => Some x
end.
Definition tl (l:list A) :=
match l with
| [] => nil
| a :: m => m
end.
(** The [In] predicate *)
Fixpoint In (a:A) (l:list A) : Prop :=
match l with
| [] => False
| b :: m => b = a \/ In a m
end.
End Lists.
Section Facts.
Variable A : Type.
(** *** Generic facts *)
(** Discrimination *)
Theorem nil_cons (x:A) (l:list A) : [] <> x :: l.
Proof.
discriminate.
Qed.
(** Destruction *)
Theorem destruct_list (l : list A) : {x:A & {tl:list A | l = x::tl}}+{l = []}.
Proof.
induction l as [|a tail].
right; reflexivity.
left; exists a, tail; reflexivity.
Qed.
Lemma hd_error_tl_repr l (a:A) r :
hd_error l = Some a /\ tl l = r <-> l = a :: r.
Proof.
destruct l as [|x xs]; [easy|cbn;split].
- now intros [[= ->] ->].
- now intros [= -> ->].
Qed.
Lemma hd_error_some_nil l (a:A) : hd_error l = Some a -> l <> nil.
Proof. unfold hd_error. destruct l; now discriminate. Qed.
Theorem length_zero_iff_nil (l : list A):
length l = 0 <-> l = [].
Proof.
split; [now destruct l | now intros ->].
Qed.
(** *** Head and tail *)
Theorem hd_error_nil : hd_error (@nil A) = None.
Proof.
reflexivity.
Qed.
Theorem hd_error_cons (l : list A) (x : A) : hd_error (x::l) = Some x.
Proof.
reflexivity.
Qed.
(**************************)
(** *** Facts about [app] *)
(**************************)
(** Discrimination *)
Theorem app_cons_not_nil (x y:list A) (a:A) : [] <> x ++ a :: y.
Proof.
now destruct x.
Qed.
(** Concat with [nil] *)
Theorem app_nil_l (l:list A) : [] ++ l = l.
Proof.
reflexivity.
Qed.
Theorem app_nil_r (l:list A) : l ++ [] = l.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_nil_end (l:list A) : l = l ++ [].
Proof. symmetry; apply app_nil_r. Qed.
(* end hide *)
(** [app] is associative *)
Theorem app_assoc (l m n:list A) : l ++ m ++ n = (l ++ m) ++ n.
Proof.
induction l; simpl; f_equal; auto.
Qed.
(* begin hide *)
(* Deprecated *)
Theorem app_assoc_reverse (l m n:list A) : (l ++ m) ++ n = l ++ m ++ n.
Proof. symmetry; apply app_assoc. Qed.
(* end hide *)
(** [app] commutes with [cons] *)
Theorem app_comm_cons (x y:list A) (a:A) : a :: (x ++ y) = (a :: x) ++ y.
Proof.
reflexivity.
Qed.
(** Facts deduced from the result of a concatenation *)
Theorem app_eq_nil (l l':list A) : l ++ l' = [] -> l = [] /\ l' = [].
Proof.
now destruct l, l'.
Qed.
Theorem app_eq_unit (x y:list A) (a:A) :
x ++ y = [a] -> x = [] /\ y = [a] \/ x = [a] /\ y = [].
Proof.
destruct x; cbn.
- intros ->. now left.
- intros [= -> [-> ->] %app_eq_nil]. now right.
Qed.
Lemma elt_eq_unit l1 l2 (a b : A) :
l1 ++ a :: l2 = [b] -> a = b /\ l1 = [] /\ l2 = [].
Proof.
intros Heq.
apply app_eq_unit in Heq.
now destruct Heq as [[Heq1 Heq2]|[Heq1 Heq2]]; inversion_clear Heq2.
Qed.
Theorem app_eq_app X (x1 x2 y1 y2: list X) : x1++x2 = y1++y2 ->
exists l, (x1 = y1++l /\ y2 = l++x2) \/ (y1 = x1++l /\ x2 = l++y2).
Proof.
revert y1. induction x1 as [|a x1 IH].
- cbn. intros y1 ->. exists y1. now right.
- intros [|b y1]; cbn.
+ intros <-. exists (a :: x1). now left.
+ intros [=-> [l Hl] %IH]. exists l.
now destruct Hl as [[-> ->]|[-> ->]]; [left|right].
Qed.
Lemma app_inj_tail :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] -> x = y /\ a = b.
Proof.
intros x y a b [l [[-> Hl %eq_sym]|[-> Hl %eq_sym]]] %app_eq_app;
apply elt_eq_unit in Hl as [? [-> ?]]; now rewrite app_nil_r.
Qed.
Lemma app_inj_tail_iff :
forall (x y:list A) (a b:A), x ++ [a] = y ++ [b] <-> x = y /\ a = b.
Proof.
intros. now split; [apply app_inj_tail|intros [-> ->]].
Qed.
(** Compatibility with other operations *)
Lemma app_length : forall l l' : list A, length (l++l') = length l + length l'.
Proof.
intro l; induction l; simpl; auto.
Qed.
Lemma last_length : forall (l : list A) a, length (l ++ a :: nil) = S (length l).
Proof.
intros ; rewrite app_length ; simpl.
rewrite Nat.add_succ_r, Nat.add_0_r; reflexivity.
Qed.
Lemma app_inv_head_iff:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 <-> l1 = l2.
Proof.
intro l; induction l as [|? l IHl]; split; intros H; simpl; auto.
- apply IHl. inversion H. auto.
- subst. auto.
Qed.
Lemma app_inv_head:
forall l l1 l2 : list A, l ++ l1 = l ++ l2 -> l1 = l2.
Proof.
apply app_inv_head_iff.
Qed.
Lemma app_inv_tail:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l -> l1 = l2.
Proof.
intros l. induction l as [|a l IHl].
- intros ? ?. now rewrite !app_nil_r.
- intros ? ?. change (a :: l) with ([a] ++ l).
rewrite !app_assoc. now intros [? ?] %IHl %app_inj_tail_iff.
Qed.
Lemma app_inv_tail_iff:
forall l l1 l2 : list A, l1 ++ l = l2 ++ l <-> l1 = l2.
Proof.
split; [apply app_inv_tail | now intros ->].
Qed.
(************************)
(** *** Facts about [In] *)
(************************)
(** Characterization of [In] *)
Theorem in_eq : forall (a:A) (l:list A), In a (a :: l).
Proof.
simpl; auto.
Qed.
Theorem in_cons : forall (a b:A) (l:list A), In b l -> In b (a :: l).
Proof.
simpl; auto.
Qed.
Theorem not_in_cons (x a : A) (l : list A):
~ In x (a::l) <-> x<>a /\ ~ In x l.
Proof.
simpl. intuition.
Qed.
Theorem in_nil : forall a:A, ~ In a [].
Proof.
unfold not; intros a H; inversion_clear H.
Qed.
Lemma in_app_or : forall (l m:list A) (a:A), In a (l ++ m) -> In a l \/ In a m.
Proof.
intros l m a. induction l; cbn; tauto.
Qed.
Lemma in_or_app : forall (l m:list A) (a:A), In a l \/ In a m -> In a (l ++ m).
Proof.
intros l m a. induction l; cbn; tauto.
Qed.
Lemma in_app_iff : forall l l' (a:A), In a (l++l') <-> In a l \/ In a l'.
Proof.
split; auto using in_app_or, in_or_app.
Qed.
Theorem in_split : forall x (l:list A), In x l -> exists l1 l2, l = l1++x::l2.
Proof.
intros x l; induction l as [|a l IHl]; simpl; [destruct 1|destruct 1 as [?|H]].
subst a; auto.
exists [], l; auto.
destruct (IHl H) as (l1,(l2,H0)).
exists (a::l1), l2; simpl. apply f_equal. auto.
Qed.
Lemma in_elt : forall (x:A) l1 l2, In x (l1 ++ x :: l2).
Proof.
intros.
apply in_or_app.
right; left; reflexivity.
Qed.
Lemma in_elt_inv : forall (x y : A) l1 l2,
In x (l1 ++ y :: l2) -> x = y \/ In x (l1 ++ l2).
Proof.
intros x y l1 l2 Hin.
apply in_app_or in Hin.
destruct Hin as [Hin|[Hin|Hin]]; [right|left|right]; try apply in_or_app; intuition.
Qed.
(** Inversion *)
Lemma in_inv : forall (a b:A) (l:list A), In b (a :: l) -> a = b \/ In b l.
Proof. easy. Qed.
(** Decidability of [In] *)
Theorem in_dec :
(forall x y:A, {x = y} + {x <> y}) ->
forall (a:A) (l:list A), {In a l} + {~ In a l}.
Proof.
intros H a l; induction l as [| a0 l IHl].
right; apply in_nil.
destruct (H a0 a); simpl; auto.
destruct IHl; simpl; auto.
right; unfold not; intros [Hc1| Hc2]; auto.
Defined.
End Facts.
#[global]
Hint Resolve app_assoc app_assoc_reverse: datatypes.
#[global]
Hint Resolve app_comm_cons app_cons_not_nil: datatypes.
#[global]
Hint Immediate app_eq_nil: datatypes.
#[global]
Hint Resolve app_eq_unit app_inj_tail: datatypes.
#[global]
Hint Resolve in_eq in_cons in_inv in_nil in_app_or in_or_app: datatypes.
(*******************************************)
(** * Operations on the elements of a list *)
(*******************************************)
Section Elts.
Variable A : Type.
(*****************************)
(** ** Nth element of a list *)
(*****************************)
Fixpoint nth (n:nat) (l:list A) (default:A) {struct l} : A :=
match n, l with
| O, x :: l' => x
| O, other => default
| S m, [] => default
| S m, x :: t => nth m t default
end.
Fixpoint nth_ok (n:nat) (l:list A) (default:A) {struct l} : bool :=
match n, l with
| O, x :: l' => true
| O, other => false
| S m, [] => false
| S m, x :: t => nth_ok m t default
end.
Lemma nth_in_or_default :
forall (n:nat) (l:list A) (d:A), {In (nth n l d) l} + {nth n l d = d}.
Proof.
intros n l d; revert n; induction l as [|? ? IHl].
- intro n; right; destruct n; trivial.
- intros [|n]; simpl.
* left; auto.
* destruct (IHl n); auto.
Qed.
Lemma nth_S_cons :
forall (n:nat) (l:list A) (d a:A),
In (nth n l d) l -> In (nth (S n) (a :: l) d) (a :: l).
Proof.
simpl; auto.
Qed.
Fixpoint nth_error (l:list A) (n:nat) {struct n} : option A :=
match n, l with
| O, x :: _ => Some x
| S n, _ :: l => nth_error l n
| _, _ => None
end.
Definition nth_default (default:A) (l:list A) (n:nat) : A :=
match nth_error l n with
| Some x => x
| None => default
end.
Lemma nth_default_eq :
forall n l (d:A), nth_default d l n = nth n l d.
Proof.
unfold nth_default; intro n; induction n; intros [ | ] ?; simpl; auto.
Qed.
(** Results about [nth] *)
Lemma nth_In :
forall (n:nat) (l:list A) (d:A), n < length l -> In (nth n l d) l.
Proof.
unfold lt; intro n; induction n as [| n hn]; simpl; intro l.
- destruct l; simpl; [ inversion 2 | auto ].
- destruct l; simpl.
* inversion 2.
* intros d ie; right; apply hn. now apply Nat.succ_le_mono.
Qed.
Lemma In_nth l x d : In x l ->
exists n, n < length l /\ nth n l d = x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|H].
* subst; exists 0; simpl; auto using Nat.lt_0_succ.
* destruct (IH H) as (n & Hn & Hn').
apply Nat.succ_lt_mono in Hn. now exists (S n).
Qed.
Lemma nth_overflow : forall l n d, length l <= n -> nth n l d = d.
Proof.
intro l; induction l as [|? ? IHl]; intro n; destruct n;
simpl; intros d H; auto.
- inversion H.
- apply IHl. now apply Nat.succ_le_mono.
Qed.
Lemma nth_indep :
forall l n d d', n < length l -> nth n l d = nth n l d'.
Proof.
intro l; induction l as [|? ? IHl].
- inversion 1.
- intros [|n] d d'; [intros; reflexivity|].
intros H. apply IHl. now apply Nat.succ_lt_mono.
Qed.
Lemma app_nth1 :
forall l l' d n, n < length l -> nth n (l++l') d = nth n l d.
Proof.
intro l; induction l as [|? ? IHl].
- inversion 1.
- intros l' d [|n]; simpl; [intros; reflexivity|].
intros H. apply IHl. now apply Nat.succ_lt_mono.
Qed.
Lemma app_nth2 :
forall l l' d n, n >= length l -> nth n (l++l') d = nth (n-length l) l' d.
Proof.
intro l; induction l as [|? ? IHl]; intros l' d [|n]; auto.
- inversion 1.
- intros; simpl; rewrite IHl; [reflexivity|now apply Nat.succ_le_mono].
Qed.
Lemma app_nth2_plus : forall l l' d n,
nth (length l + n) (l ++ l') d = nth n l' d.
Proof.
intros.
now rewrite app_nth2, Nat.add_comm, Nat.add_sub; [|apply Nat.le_add_r].
Qed.
Lemma nth_middle : forall l l' a d,
nth (length l) (l ++ a :: l') d = a.
Proof.
intros.
rewrite <- Nat.add_0_r at 1.
apply app_nth2_plus.
Qed.
Lemma nth_split n l d : n < length l ->
exists l1, exists l2, l = l1 ++ nth n l d :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|a l] H; try easy.
- exists nil; exists l; now simpl.
- destruct (IH l) as (l1 & l2 & Hl & Hl1); [now apply Nat.succ_lt_mono|].
exists (a::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_ext : forall l l' d d', length l = length l' ->
(forall n, n < length l -> nth n l d = nth n l' d') -> l = l'.
Proof.
intro l; induction l as [|a l IHl];
intros l' d d' Hlen Hnth; destruct l' as [| b l'].
- reflexivity.
- inversion Hlen.
- inversion Hlen.
- change a with (nth 0 (a :: l) d).
change b with (nth 0 (b :: l') d').
rewrite Hnth; f_equal.
+ apply IHl with d d'; [ now inversion Hlen | ].
intros n Hlen'; apply (Hnth (S n)).
now apply (Nat.succ_lt_mono n (length l)).
+ simpl; apply Nat.lt_0_succ.
Qed.
(** Results about [nth_error] *)
Lemma nth_error_In l n x : nth_error l n = Some x -> In x l.
Proof.
revert n. induction l as [|a l IH]; intros [|n]; simpl; try easy.
- injection 1; auto.
- eauto.
Qed.
Lemma In_nth_error l x : In x l -> exists n, nth_error l n = Some x.
Proof.
induction l as [|a l IH].
- easy.
- intros [H|[n ?] %IH].
+ subst; now exists 0.
+ now exists (S n).
Qed.
Lemma nth_error_None l n : nth_error l n = None <-> length l <= n.
Proof.
revert n. induction l as [|? ? IHl]; intro n; destruct n; simpl.
- split; auto.
- now split; intros; [apply Nat.le_0_l|].
- now split; [|intros ? %Nat.nle_succ_0].
- now rewrite IHl, Nat.succ_le_mono.
Qed.
Lemma nth_error_Some l n : nth_error l n <> None <-> n < length l.
Proof.
revert n. induction l as [|? ? IHl]; intro n; destruct n; simpl.
- split; [now destruct 1 | inversion 1].
- split; [now destruct 1 | inversion 1].
- now split; intros; [apply Nat.lt_0_succ|].
- now rewrite IHl, Nat.succ_lt_mono.
Qed.
Lemma nth_error_split l n a : nth_error l n = Some a ->
exists l1, exists l2, l = l1 ++ a :: l2 /\ length l1 = n.
Proof.
revert l.
induction n as [|n IH]; intros [|x l] H; [easy| |easy|].
- exists nil; exists l. now injection H as [= ->].
- destruct (IH _ H) as (l1 & l2 & H1 & H2).
exists (x::l1); exists l2; simpl; split; now f_equal.
Qed.
Lemma nth_error_app1 l l' n : n < length l ->
nth_error (l++l') n = nth_error l n.
Proof.
revert l.
induction n as [|n IHn]; intros [|a l] H; [easy ..|].
cbn. now apply IHn, Nat.succ_le_mono.
Qed.
Lemma nth_error_app2 l l' n : length l <= n ->
nth_error (l++l') n = nth_error l' (n-length l).
Proof.
revert l.
induction n as [|n IHn]; intros [|a l] H; [easy ..|].
cbn. now apply IHn, Nat.succ_le_mono.
Qed.
(** Results directly relating [nth] and [nth_error] *)
Lemma nth_error_nth : forall (l : list A) (n : nat) (x d : A),
nth_error l n = Some x -> nth n l d = x.
Proof.
intros l n x d H.
apply nth_error_split in H. destruct H as [l1 [l2 [H H']]].
subst. rewrite app_nth2; [|auto].
rewrite Nat.sub_diag. reflexivity.
Qed.
Lemma nth_error_nth' : forall (l : list A) (n : nat) (d : A),
n < length l -> nth_error l n = Some (nth n l d).
Proof.
intros l n d H.
apply (nth_split _ d) in H. destruct H as [l1 [l2 [H H']]].
subst. rewrite H. rewrite nth_error_app2; [|auto].
rewrite app_nth2; [| auto]. repeat (rewrite Nat.sub_diag). reflexivity.
Qed.
(******************************)
(** ** Last element of a list *)
(******************************)
(** [last l d] returns the last element of the list [l],
or the default value [d] if [l] is empty. *)
Fixpoint last (l:list A) (d:A) : A :=
match l with
| [] => d
| [a] => a
| a :: l => last l d
end.
Lemma last_last : forall l a d, last (l ++ [a]) d = a.
Proof.
intro l; induction l as [|? l IHl]; intros; [ reflexivity | ].
simpl; rewrite IHl.
destruct l; reflexivity.
Qed.
(** [removelast l] remove the last element of [l] *)
Fixpoint removelast (l:list A) : list A :=
match l with
| [] => []
| [a] => []
| a :: l => a :: removelast l
end.
Lemma app_removelast_last :
forall l d, l <> [] -> l = removelast l ++ [last l d].
Proof.
intro l; induction l as [|? l IHl].
destruct 1; auto.
intros d _.
destruct l as [|a0 l]; auto.
pattern (a0::l) at 1; rewrite IHl with d; auto; discriminate.
Qed.
Lemma exists_last :
forall l, l <> [] -> { l' : (list A) & { a : A | l = l' ++ [a]}}.
Proof.
intro l; induction l as [|a l IHl].
destruct 1; auto.
intros _.
destruct l.
exists [], a; auto.
destruct IHl as [l' (a',H)]; try discriminate.
rewrite H.
exists (a::l'), a'; auto.
Qed.
Lemma removelast_app :
forall l l', l' <> [] -> removelast (l++l') = l ++ removelast l'.
Proof.
intro l; induction l as [|? l IHl]; [easy|].
intros l' H. cbn. rewrite <- IHl by assumption.
now destruct l, l'.
Qed.
Lemma removelast_last : forall l a, removelast (l ++ [a]) = l.
Proof.
intros. rewrite removelast_app.
- apply app_nil_r.
- intros Heq; inversion Heq.
Qed.
(*****************)
(** ** Remove *)
(*****************)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Fixpoint remove (x : A) (l : list A) : list A :=
match l with
| [] => []
| y::tl => if (eq_dec x y) then remove x tl else y::(remove x tl)
end.
Lemma remove_cons : forall x l, remove x (x :: l) = remove x l.
Proof.
intros x l; simpl; destruct (eq_dec x x); [ reflexivity | now exfalso ].
Qed.
Lemma remove_app : forall x l1 l2,
remove x (l1 ++ l2) = remove x l1 ++ remove x l2.
Proof.
intros x l1; induction l1 as [|a l1 IHl1]; intros l2; simpl.
- reflexivity.
- destruct (eq_dec x a).
+ apply IHl1.
+ rewrite <- app_comm_cons; f_equal.
apply IHl1.
Qed.
Theorem remove_In : forall (l : list A) (x : A), ~ In x (remove x l).
Proof.
intro l; induction l as [|x l IHl]; auto.
intro y; simpl; destruct (eq_dec y x) as [yeqx | yneqx].
apply IHl.
unfold not; intro HF; simpl in HF; destruct HF; auto.
apply (IHl y); assumption.
Qed.
Lemma notin_remove: forall l x, ~ In x l -> remove x l = l.
Proof.
intros l x; induction l as [|y l IHl]; simpl; intros Hnin.
- reflexivity.
- destruct (eq_dec x y); [subst|f_equal]; tauto.
Qed.
Lemma in_remove: forall l x y, In x (remove y l) -> In x l /\ x <> y.
Proof.
intro l; induction l as [|z l IHl]; intros x y Hin.
- inversion Hin.
- simpl in Hin.
destruct (eq_dec y z) as [Heq|Hneq]; subst; split.
+ right; now apply IHl with z.
+ intros Heq; revert Hin; subst; apply remove_In.
+ inversion Hin; subst; [left; reflexivity|right].
now apply IHl with y.
+ destruct Hin as [Hin|Hin]; subst.
* now intros Heq; apply Hneq.
* intros Heq; revert Hin; subst; apply remove_In.
Qed.
Lemma in_in_remove : forall l x y, x <> y -> In x l -> In x (remove y l).
Proof.
intro l; induction l as [|z l IHl]; simpl; intros x y Hneq Hin.
- apply Hin.
- destruct (eq_dec y z); subst.
+ destruct Hin.
* exfalso; now apply Hneq.
* now apply IHl.
+ simpl; destruct Hin; [now left|right].
now apply IHl.
Qed.
Lemma remove_remove_comm : forall l x y,
remove x (remove y l) = remove y (remove x l).
Proof.
intro l; induction l as [| z l IHl]; simpl; intros x y.
- reflexivity.
- destruct (eq_dec y z); simpl; destruct (eq_dec x z); try rewrite IHl; auto.
+ subst; symmetry; apply remove_cons.
+ simpl; destruct (eq_dec y z); tauto.
Qed.
Lemma remove_remove_eq : forall l x, remove x (remove x l) = remove x l.
Proof. intros l x; now rewrite (notin_remove _ _ (remove_In l x)). Qed.
Lemma remove_length_le : forall l x, length (remove x l) <= length l.
Proof.
intro l; induction l as [|y l IHl]; simpl; intros x; trivial.
destruct (eq_dec x y); simpl.
- rewrite IHl; constructor; reflexivity.
- apply (proj1 (Nat.succ_le_mono _ _) (IHl x)).
Qed.
Lemma remove_length_lt : forall l x, In x l -> length (remove x l) < length l.
Proof.
intro l; induction l as [|y l IHl]; simpl; intros x Hin.
- contradiction Hin.
- destruct Hin as [-> | Hin].
+ destruct (eq_dec x x); [|easy].
apply Nat.lt_succ_r, remove_length_le.
+ specialize (IHl _ Hin); destruct (eq_dec x y); simpl; auto.
now apply Nat.succ_lt_mono in IHl.
Qed.
(******************************************)
(** ** Counting occurrences of an element *)
(******************************************)
Fixpoint count_occ (l : list A) (x : A) : nat :=
match l with
| [] => 0
| y :: tl =>
let n := count_occ tl x in
if eq_dec y x then S n else n
end.
(** Compatibility of count_occ with operations on list *)
Theorem count_occ_In l x : In x l <-> count_occ l x > 0.
Proof.
induction l as [|y l IHl]; simpl.
- split; [destruct 1 | apply Nat.nlt_0_r].
- destruct eq_dec as [->|Hneq]; rewrite IHl; intuition (apply Nat.lt_0_succ).
Qed.
Theorem count_occ_not_In l x : ~ In x l <-> count_occ l x = 0.
Proof.
rewrite count_occ_In. unfold gt. now rewrite Nat.nlt_ge, Nat.le_0_r.
Qed.
Lemma count_occ_nil x : count_occ [] x = 0.
Proof.
reflexivity.
Qed.
Theorem count_occ_inv_nil l :
(forall x:A, count_occ l x = 0) <-> l = [].
Proof.
split.
- induction l as [|x l]; trivial.
intros H. specialize (H x). simpl in H.
destruct eq_dec as [_|NEQ]; [discriminate|now elim NEQ].
- now intros ->.
Qed.
Lemma count_occ_cons_eq l x y :
x = y -> count_occ (x::l) y = S (count_occ l y).
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_cons_neq l x y :
x <> y -> count_occ (x::l) y = count_occ l y.
Proof.
intros H. simpl. now destruct (eq_dec x y).
Qed.
Lemma count_occ_app l1 l2 x :
count_occ (l1 ++ l2) x = count_occ l1 x + count_occ l2 x.
Proof.
induction l1 as [ | h l1 IHl1]; cbn; auto.
now destruct (eq_dec h x); [ rewrite IHl1 | ].
Qed.
Lemma count_occ_elt_eq l1 l2 x y : x = y ->
count_occ (l1 ++ x :: l2) y = S (count_occ (l1 ++ l2) y).
Proof.
intros ->.
rewrite ? count_occ_app; cbn.
destruct (eq_dec y y) as [Heq | Hneq];
[ apply Nat.add_succ_r | now contradiction Hneq ].
Qed.
Lemma count_occ_elt_neq l1 l2 x y : x <> y ->
count_occ (l1 ++ x :: l2) y = count_occ (l1 ++ l2) y.
Proof.
intros Hxy.
rewrite ? count_occ_app; cbn.
now destruct (eq_dec x y) as [Heq | Hneq]; [ contradiction Hxy | ].
Qed.
Lemma count_occ_bound x l : count_occ l x <= length l.
Proof.
induction l as [|h l]; cbn; auto.
destruct (eq_dec h x); [ apply (proj1 (Nat.succ_le_mono _ _)) | ]; intuition.
Qed.
End Elts.
(*******************************)
(** * Manipulating whole lists *)
(*******************************)
Section ListOps.
Variable A : Type.
(*************************)
(** ** Reverse *)
(*************************)
Fixpoint rev (l:list A) : list A :=
match l with
| [] => []
| x :: l' => rev l' ++ [x]
end.
Lemma rev_app_distr : forall x y:list A, rev (x ++ y) = rev y ++ rev x.
Proof.
intros x y; induction x as [| a l IHl]; cbn.
- now rewrite app_nil_r.
- now rewrite IHl, app_assoc.
Qed.
Remark rev_unit : forall (l:list A) (a:A), rev (l ++ [a]) = a :: rev l.
Proof.
intros l a. apply rev_app_distr.
Qed.
Lemma rev_involutive : forall l:list A, rev (rev l) = l.
Proof.
intro l; induction l as [| a l IHl].
- reflexivity.
- cbn. now rewrite rev_unit, IHl.
Qed.
Lemma rev_eq_app : forall l l1 l2, rev l = l1 ++ l2 -> l = rev l2 ++ rev l1.
Proof.
intros l l1 l2 Heq.
rewrite <- (rev_involutive l), Heq.
apply rev_app_distr.
Qed.
(*********************************************)
(** Reverse Induction Principle on Lists *)
(*********************************************)
Lemma rev_list_ind : forall P:list A-> Prop,
P [] ->
(forall (a:A) (l:list A), P (rev l) -> P (rev (a :: l))) ->
forall l:list A, P (rev l).
Proof.
intros P ? ? l; induction l; auto.
Qed.
Theorem rev_ind : forall P:list A -> Prop,
P [] ->
(forall (x:A) (l:list A), P l -> P (l ++ [x])) -> forall l:list A, P l.
Proof.
intros P ? ? l. rewrite <- (rev_involutive l).
apply (rev_list_ind P); cbn; auto.
Qed.
(** Compatibility with other operations *)
Lemma in_rev : forall l x, In x l <-> In x (rev l).
Proof.
intro l; induction l as [|? ? IHl]; [easy|].
intros. cbn. rewrite in_app_iff, IHl. cbn. tauto.
Qed.
Lemma rev_length : forall l, length (rev l) = length l.
Proof.
intro l; induction l as [|? l IHl];simpl; auto.
now rewrite app_length, IHl, Nat.add_comm.
Qed.
Lemma rev_nth : forall l d n, n < length l ->
nth n (rev l) d = nth (length l - S n) l d.
Proof.
intros l d; induction l as [|a l IHl] using rev_ind; [easy|].
rewrite rev_app_distr, app_length, Nat.add_comm. cbn. intros [|n].
- now rewrite Nat.sub_0_r, nth_middle.
- intros Hn %Nat.succ_lt_mono.
rewrite (IHl _ Hn), app_nth1; [reflexivity|].
apply Nat.sub_lt; [assumption|apply Nat.lt_0_succ].
Qed.
(** An alternative tail-recursive definition for reverse *)
Fixpoint rev_append (l l': list A) : list A :=
match l with
| [] => l'
| a::l => rev_append l (a::l')
end.
Definition rev' l : list A := rev_append l [].
Lemma rev_append_rev : forall l l', rev_append l l' = rev l ++ l'.
Proof.
intro l; induction l; simpl; auto; intros.
rewrite <- app_assoc; firstorder.
Qed.
Lemma rev_alt : forall l, rev l = rev_append l [].
Proof.
intros; rewrite rev_append_rev.
rewrite app_nil_r; trivial.
Qed.
(*************************)
(** ** Concatenation *)
(*************************)
Fixpoint concat (l : list (list A)) : list A :=
match l with
| nil => nil
| cons x l => x ++ concat l
end.
Lemma concat_nil : concat nil = nil.
Proof.
reflexivity.
Qed.
Lemma concat_cons : forall x l, concat (cons x l) = x ++ concat l.
Proof.
reflexivity.
Qed.
Lemma concat_app : forall l1 l2, concat (l1 ++ l2) = concat l1 ++ concat l2.
Proof.
intros l1; induction l1 as [|x l1 IH]; intros l2; simpl.
- reflexivity.
- rewrite IH; apply app_assoc.
Qed.
Lemma in_concat : forall l y,
In y (concat l) <-> exists x, In x l /\ In y x.
Proof.
intro l; induction l as [|a l IHl]; simpl; intro y; split; intros H.
contradiction.
destruct H as (x,(H,_)); contradiction.
destruct (in_app_or _ _ _ H) as [H0|H0].
exists a; auto.
destruct (IHl y) as (H1,_); destruct (H1 H0) as (x,(H2,H3)).
exists x; auto.
apply in_or_app.
destruct H as (x,(H0,H1)); destruct H0.
subst; auto.
right; destruct (IHl y) as (_,H2); apply H2.
exists x; auto.
Qed.
(***********************************)
(** ** Decidable equality on lists *)
(***********************************)
Hypothesis eq_dec : forall (x y : A), {x = y}+{x <> y}.
Lemma list_eq_dec : forall l l':list A, {l = l'} + {l <> l'}.
Proof. decide equality. Defined.
End ListOps.
(***************************************************)
(** * Applying functions to the elements of a list *)
(***************************************************)
(************)
(** ** Map *)
(************)
Section Map.
Variables (A : Type) (B : Type).
Variable f : A -> B.
Fixpoint map (l:list A) : list B :=
match l with
| [] => []
| a :: t => (f a) :: (map t)
end.
Lemma map_cons (x:A)(l:list A) : map (x::l) = (f x) :: (map l).
Proof.
reflexivity.
Qed.
Lemma in_map :
forall (l:list A) (x:A), In x l -> In (f x) (map l).
Proof.
intro l; induction l; firstorder (subst; auto).
Qed.
Lemma in_map_iff : forall l y, In y (map l) <-> exists x, f x = y /\ In x l.
Proof.
intro l; induction l; firstorder (subst; auto).
Qed.
Lemma map_length : forall l, length (map l) = length l.
Proof.
intro l; induction l; simpl; auto.
Qed.
Lemma map_nth : forall l d n,
nth n (map l) (f d) = f (nth n l d).
Proof.
intro l; induction l; simpl map; intros d n; destruct n; firstorder.
Qed.
Lemma nth_error_map : forall n l,
nth_error (map l) n = option_map f (nth_error l n).
Proof.
intro n. induction n as [|n IHn]; intro l.
- now destruct l.
- destruct l as [|? l]; [reflexivity|exact (IHn l)].
Qed.
Lemma map_nth_error : forall n l d,
nth_error l n = Some d -> nth_error (map l) n = Some (f d).
Proof.
intros n l d H. now rewrite nth_error_map, H.
Qed.
Lemma map_app : forall l l',
map (l++l') = (map l)++(map l').
Proof.
intro l; induction l as [|a l IHl]; simpl; auto.
intros; rewrite IHl; auto.
Qed.
Lemma map_last : forall l a,
map (l ++ [a]) = (map l) ++ [f a].
Proof.
intro l; induction l as [|a l IHl]; intros; [ reflexivity | ].
simpl; rewrite IHl; reflexivity.
Qed.
Lemma map_rev : forall l, map (rev l) = rev (map l).
Proof.
intro l; induction l as [|a l IHl]; simpl; auto.
rewrite map_app.
rewrite IHl; auto.
Qed.
Lemma map_eq_nil : forall l, map l = [] -> l = [].
Proof.
intro l; destruct l; simpl; reflexivity || discriminate.
Qed.
Lemma map_eq_cons : forall l l' b,
map l = b :: l' -> exists a tl, l = a :: tl /\ f a = b /\ map tl = l'.
Proof.
intros l l' b Heq.
destruct l as [|a l]; inversion_clear Heq.
exists a, l; repeat split.
Qed.
Lemma map_eq_app : forall l l1 l2,
map l = l1 ++ l2 -> exists l1' l2', l = l1' ++ l2' /\ map l1' = l1 /\ map l2' = l2.
Proof.
intro l; induction l as [|a l IHl]; simpl; intros l1 l2 Heq.
- symmetry in Heq; apply app_eq_nil in Heq; destruct Heq; subst.
exists nil, nil; repeat split.
- destruct l1; simpl in Heq; inversion Heq as [[Heq2 Htl]].
+ exists nil, (a :: l); repeat split.
+ destruct (IHl _ _ Htl) as (l1' & l2' & ? & ? & ?); subst.
exists (a :: l1'), l2'; repeat split.
Qed.
(** [map] and count of occurrences *)
Hypothesis decA: forall x1 x2 : A, {x1 = x2} + {x1 <> x2}.
Hypothesis decB: forall y1 y2 : B, {y1 = y2} + {y1 <> y2}.
Hypothesis Hfinjective: forall x1 x2: A, (f x1) = (f x2) -> x1 = x2.
Theorem count_occ_map x l:
count_occ decA l x = count_occ decB (map l) (f x).
Proof.
revert x. induction l as [| a l' Hrec]; intro x; simpl.
- reflexivity.
- specialize (Hrec x).
destruct (decA a x) as [H1|H1], (decB (f a) (f x)) as [H2|H2].
+ rewrite Hrec. reflexivity.
+ contradiction H2. rewrite H1. reflexivity.
+ specialize (Hfinjective H2). contradiction H1.
+ assumption.
Qed.
End Map.
(*****************)
(** ** Flat Map *)
(*****************)
Section FlatMap.
Variables (A : Type) (B : Type).
Variable f : A -> list B.
(** [flat_map] *)
Definition flat_map :=
fix flat_map (l:list A) : list B :=
match l with
| nil => nil
| cons x t => (f x)++(flat_map t)
end.
Lemma flat_map_concat_map l :
flat_map l = concat (map f l).
Proof.
induction l as [|x l IH]; simpl.
- reflexivity.
- rewrite IH; reflexivity.
Qed.
Lemma flat_map_app l1 l2 :
flat_map (l1 ++ l2) = flat_map l1 ++ flat_map l2.
Proof.
now rewrite !flat_map_concat_map, map_app, concat_app.
Qed.
Lemma in_flat_map l y :
In y (flat_map l) <-> exists x, In x l /\ In y (f x).
Proof.
rewrite flat_map_concat_map, in_concat.
split.
- intros [l' [[x [<- ?]] %in_map_iff ?]].
now exists x.
- intros [x [? ?]]. exists (f x).
now split; [apply in_map|].
Qed.
End FlatMap.
Lemma concat_map : forall A B (f : A -> B) l, map f (concat l) = concat (map (map f) l).
Proof.
intros A B f l; induction l as [|x l IH]; simpl.
- reflexivity.
- rewrite map_app, IH; reflexivity.
Qed.
Lemma remove_concat A (eq_dec : forall x y : A, {x = y}+{x <> y}) : forall l x,
remove eq_dec x (concat l) = flat_map (remove eq_dec x) l.
Proof.
intros l x; induction l as [|? ? IHl]; [ reflexivity | simpl ].
rewrite remove_app, IHl; reflexivity.
Qed.
Lemma map_id : forall (A :Type) (l : list A),
map (fun x => x) l = l.
Proof.
intros A l; induction l as [|? ? IHl]; simpl; auto; rewrite IHl; auto.
Qed.
Lemma map_map : forall (A B C:Type)(f:A->B)(g:B->C) l,
map g (map f l) = map (fun x => g (f x)) l.
Proof.
intros A B C f g l; induction l as [|? ? IHl]; simpl; auto.
rewrite IHl; auto.
Qed.
Lemma map_ext_in :
forall (A B : Type)(f g:A->B) l, (forall a, In a l -> f a = g a) -> map f l = map g l.
Proof.
intros A B f g l; induction l as [|? ? IHl]; simpl; auto.
intros H; rewrite H by intuition; rewrite IHl; auto.
Qed.
Lemma ext_in_map :
forall (A B : Type)(f g:A->B) l, map f l = map g l -> forall a, In a l -> f a = g a.
Proof. intros A B f g l; induction l; intros [=] ? []; subst; auto. Qed.
Arguments ext_in_map [A B f g l].
Lemma map_ext_in_iff :
forall (A B : Type)(f g:A->B) l, map f l = map g l <-> forall a, In a l -> f a = g a.
Proof. split; [apply ext_in_map | apply map_ext_in]. Qed.
Arguments map_ext_in_iff {A B f g l}.
Lemma map_ext :
forall (A B : Type)(f g:A->B), (forall a, f a = g a) -> forall l, map f l = map g l.
Proof.
intros; apply map_ext_in; auto.
Qed.
Lemma flat_map_ext : forall (A B : Type)(f g : A -> list B),
(forall a, f a = g a) -> forall l, flat_map f l = flat_map g l.
Proof.
intros A B f g Hext l.
rewrite 2 flat_map_concat_map.
now rewrite (map_ext _ g).
Qed.
Lemma nth_nth_nth_map A : forall (l : list A) n d ln dn, n < length ln \/ length l <= dn ->
nth (nth n ln dn) l d = nth n (map (fun x => nth x l d) ln) d.
Proof.
intros l n d ln dn Hlen.
rewrite <- (map_nth (fun m => nth m l d)).
destruct Hlen.
- apply nth_indep. now rewrite map_length.
- now rewrite (nth_overflow l).
Qed.
(************************************)
(** Left-to-right iterator on lists *)
(************************************)
Section Fold_Left_Recursor.
Variables (A : Type) (B : Type).
Variable f : A -> B -> A.
Fixpoint fold_left (l:list B) (a0:A) : A :=
match l with
| nil => a0
| cons b t => fold_left t (f a0 b)
end.
Lemma fold_left_app : forall (l l':list B)(i:A),
fold_left (l++l') i = fold_left l' (fold_left l i).
Proof.
now intro l; induction l; cbn.
Qed.
End Fold_Left_Recursor.
Lemma fold_left_length :
forall (A:Type)(l:list A), fold_left (fun x _ => S x) l 0 = length l.
Proof.
intros A l. induction l as [|? ? IH] using rev_ind; [reflexivity|].
now rewrite fold_left_app, app_length, IH, Nat.add_comm.
Qed.
(************************************)
(** Right-to-left iterator on lists *)
(************************************)
Section Fold_Right_Recursor.
Variables (A : Type) (B : Type).
Variable f : B -> A -> A.
Variable a0 : A.
Fixpoint fold_right (l:list B) : A :=
match l with
| nil => a0
| cons b t => f b (fold_right t)
end.
End Fold_Right_Recursor.
Lemma fold_right_app : forall (A B:Type)(f:A->B->B) l l' i,
fold_right f i (l++l') = fold_right f (fold_right f i l') l.
Proof.
intros A B f l; induction l.
simpl; auto.
simpl; intros.
f_equal; auto.
Qed.
Lemma fold_left_rev_right : forall (A B:Type)(f:A->B->B) l i,
fold_right f i (rev l) = fold_left (fun x y => f y x) l i.
Proof.
intros A B f l; induction l.
simpl; auto.
intros.
simpl.
rewrite fold_right_app; simpl; auto.
Qed.
Theorem fold_symmetric :
forall (A : Type) (f : A -> A -> A),
(forall x y z : A, f x (f y z) = f (f x y) z) ->
forall (a0 : A), (forall y : A, f a0 y = f y a0) ->
forall (l : list A), fold_left f l a0 = fold_right f a0 l.
Proof.
intros A f assoc a0 comma0 l.
induction l as [ | a1 l IHl]; [ simpl; reflexivity | ].
simpl. rewrite <- IHl. clear IHl. revert a1.
induction l as [|? ? IHl]; [ auto | ].
simpl. intro. rewrite <- assoc. rewrite IHl. rewrite IHl. auto.
Qed.
(** [(list_power x y)] is [y^x], or the set of sequences of elts of [y]
indexed by elts of [x], sorted in lexicographic order. *)
Fixpoint list_power (A B:Type)(l:list A) (l':list B) :
list (list (A * B)) :=
match l with
| nil => cons nil nil
| cons x t =>
flat_map (fun f:list (A * B) => map (fun y:B => cons (x, y) f) l')
(list_power t l')
end.
(*************************************)
(** ** Boolean operations over lists *)
(*************************************)
Section Bool.
Variable A : Type.
Variable f : A -> bool.
(** find whether a boolean function can be satisfied by an
elements of the list. *)
Fixpoint existsb (l:list A) : bool :=
match l with
| nil => false
| a::l => f a || existsb l
end.
Lemma existsb_exists :
forall l, existsb l = true <-> exists x, In x l /\ f x = true.
Proof.
intro l; induction l as [ | a m IH ]; split; simpl.
- easy.
- intros [x [[]]].
- destruct (f a) eqn:Ha.
+ intros _. exists a. tauto.
+ intros [x [? ?]] %IH. exists x. tauto.
- intros [ x [ [ Hax | Hxm ] Hfx ] ].
+ now rewrite Hax, Hfx.
+ destruct IH as [ _ -> ]; eauto with bool.
Qed.
Lemma existsb_nth : forall l n d, n < length l ->
existsb l = false -> f (nth n l d) = false.
Proof.
intro l; induction l as [|a ? IHl]; [easy|].
cbn. intros [|n]; [now destruct (f a)|].
intros d ? %Nat.succ_lt_mono.
now destruct (f a); [|apply IHl].
Qed.
Lemma existsb_app : forall l1 l2,
existsb (l1++l2) = existsb l1 || existsb l2.
Proof.
intro l1; induction l1 as [|a ? ?]; intros l2; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** find whether a boolean function is satisfied by
all the elements of a list. *)
Fixpoint forallb (l:list A) : bool :=
match l with
| nil => true
| a::l => f a && forallb l
end.
Lemma forallb_forall :
forall l, forallb l = true <-> (forall x, In x l -> f x = true).
Proof.
intro l; induction l as [|a l IHl]; simpl; [ tauto | split; intro H ].
+ destruct (andb_prop _ _ H); intros a' [?|?].
- congruence.
- apply IHl; assumption.
+ apply andb_true_intro; split.
- apply H; left; reflexivity.
- apply IHl; intros; apply H; right; assumption.
Qed.
Lemma forallb_app :
forall l1 l2, forallb (l1++l2) = forallb l1 && forallb l2.
Proof.
intro l1; induction l1 as [|a ? ?]; simpl.
solve[auto].
case (f a); simpl; solve[auto].
Qed.
(** [filter] *)
Fixpoint filter (l:list A) : list A :=
match l with
| nil => nil
| x :: l => if f x then x::(filter l) else filter l
end.
Lemma filter_In : forall x l, In x (filter l) <-> In x l /\ f x = true.
Proof.
intros x l; induction l as [|a ? ?]; simpl.
- tauto.
- intros.
case_eq (f a); intros; simpl; intuition congruence.
Qed.
Lemma filter_app (l l':list A) :
filter (l ++ l') = filter l ++ filter l'.
Proof.
induction l as [|x l IH]; simpl; trivial.
destruct (f x); simpl; now rewrite IH.
Qed.
Lemma concat_filter_map : forall (l : list (list A)),
concat (map filter l) = filter (concat l).
Proof.
intro l; induction l as [| v l IHl]; [auto|].
simpl. rewrite IHl. rewrite filter_app. reflexivity.
Qed.
(** [find] *)
Fixpoint find (l:list A) : option A :=
match l with
| nil => None
| x :: tl => if f x then Some x else find tl
end.
Lemma find_some l x : find l = Some x -> In x l /\ f x = true.
Proof.
induction l as [|a l IH]; simpl; [easy| ].
case_eq (f a); intros Ha Eq.
* injection Eq as [= ->]; auto.
* destruct (IH Eq); auto.
Qed.
Lemma find_none l : find l = None -> forall x, In x l -> f x = false.
Proof.
induction l as [|a l IH]; simpl; [easy|].
case_eq (f a); intros Ha Eq x IN; [easy|].
destruct IN as [<-|IN]; auto.
Qed.
(** [partition] *)
Fixpoint partition (l:list A) : list A * list A :=
match l with
| nil => (nil, nil)
| x :: tl => let (g,d) := partition tl in
if f x then (x::g,d) else (g,x::d)
end.
Theorem partition_cons1 a l l1 l2:
partition l = (l1, l2) ->
f a = true ->
partition (a::l) = (a::l1, l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_cons2 a l l1 l2:
partition l = (l1, l2) ->
f a=false ->
partition (a::l) = (l1, a::l2).
Proof.
simpl. now intros -> ->.
Qed.
Theorem partition_length l l1 l2:
partition l = (l1, l2) ->
length l = length l1 + length l2.
Proof.
revert l1 l2. induction l as [ | a l' Hrec]; intros l1 l2.
- now intros [= <- <- ].
- simpl. destruct (f a), (partition l') as (left, right);
intros [= <- <- ]; simpl; rewrite (Hrec left right); auto.
Qed.
Theorem partition_inv_nil (l : list A):
partition l = ([], []) <-> l = [].
Proof.
split.
- destruct l as [|a l'].
* intuition.
* simpl. destruct (f a), (partition l'); now intros [= -> ->].
- now intros ->.
Qed.
Theorem elements_in_partition l l1 l2:
partition l = (l1, l2) ->
forall x:A, In x l <-> In x l1 \/ In x l2.
Proof.
revert l1 l2. induction l as [| a l' Hrec]; simpl; intros l1 l2 Eq x.
- injection Eq as [= <- <-]. tauto.
- destruct (partition l') as (left, right).
specialize (Hrec left right eq_refl x).
destruct (f a); injection Eq as [= <- <-]; simpl; tauto.
Qed.
End Bool.
(*******************************)
(** ** Further filtering facts *)
(*******************************)
Section Filtering.
Variables (A : Type).
Lemma filter_ext_in : forall (f g : A -> bool) (l : list A),
(forall a, In a l -> f a = g a) -> filter f l = filter g l.
Proof.
intros f g l. induction l as [| a l IHl]; [easy|cbn].
intros H. rewrite (H a) by (now left).
destruct (g a); [f_equal|]; apply IHl; intros; apply H; now right.
Qed.
Lemma ext_in_filter : forall (f g : A -> bool) (l : list A),
filter f l = filter g l -> (forall a, In a l -> f a = g a).
Proof.
intros f g l. induction l as [| a l IHl]; [easy|cbn].
intros H. assert (Ha : f a = g a).
- pose proof (Hf := proj1 (filter_In f a l)).
pose proof (Hg := proj1 (filter_In g a l)).
destruct (f a), (g a); [reflexivity| | |reflexivity].
+ symmetry. apply Hg. rewrite <- H. now left.
+ apply Hf. rewrite H. now left.
- intros b [<-|Hbl]; [assumption|].
apply IHl; [|assumption].
destruct (f a), (g a); congruence.
Qed.
Lemma filter_ext_in_iff : forall (f g : A -> bool) (l : list A),
filter f l = filter g l <-> (forall a, In a l -> f a = g a).
Proof.
split; [apply ext_in_filter | apply filter_ext_in].
Qed.
Lemma filter_map : forall (f g : A -> bool) (l : list A),
filter f l = filter g l <-> map f l = map g l.
Proof.
intros f g l. now rewrite filter_ext_in_iff, map_ext_in_iff.
Qed.
Lemma filter_ext : forall (f g : A -> bool),
(forall a, f a = g a) -> forall l, filter f l = filter g l.
Proof.
intros f g H l. rewrite filter_map. apply map_ext. assumption.
Qed.
(** Remove by filtering *)
Hypothesis eq_dec : forall x y : A, {x = y}+{x <> y}.
Definition remove' (x : A) : list A -> list A :=
filter (fun y => if eq_dec x y then false else true).
Lemma remove_alt (x : A) (l : list A) : remove' x l = remove eq_dec x l.
Proof.
induction l; [reflexivity|].
simpl. now destruct eq_dec; [|f_equal].
Qed.
(** Counting occurrences by filtering *)
Definition count_occ' (l : list A) (x : A) : nat :=
length (filter (fun y => if eq_dec y x then true else false) l).
Lemma count_occ_alt (l : list A) (x : A) :
count_occ' l x = count_occ eq_dec l x.
Proof.
unfold count_occ'. induction l; [reflexivity|].
simpl. now destruct eq_dec; simpl; [f_equal|].
Qed.
End Filtering.
(******************************************************)
(** ** Operations on lists of pairs or lists of lists *)
(******************************************************)
Section ListPairs.
Variables (A : Type) (B : Type).
(** [split] derives two lists from a list of pairs *)
Fixpoint split (l:list (A*B)) : list A * list B :=
match l with
| [] => ([], [])
| (x,y) :: tl => let (left,right) := split tl in (x::left, y::right)
end.
Lemma in_split_l : forall (l:list (A*B))(p:A*B),
In p l -> In (fst p) (fst (split l)).
Proof.
intro l. induction l as [|[? ?] l IHl]; [easy|].
intros [? ?]. cbn.
now intros [[=]|? %IHl]; destruct (split l); [left|right].
Qed.
Lemma in_split_r : forall (l:list (A*B))(p:A*B),
In p l -> In (snd p) (snd (split l)).
Proof.
intro l. induction l as [|[? ?] l IHl]; [easy|].
intros [? ?]. cbn.
now intros [[=]|? %IHl]; destruct (split l); [left|right].
Qed.
Lemma split_nth : forall (l:list (A*B))(n:nat)(d:A*B),
nth n l d = (nth n (fst (split l)) (fst d), nth n (snd (split l)) (snd d)).
Proof.
intro l; induction l as [|a l IHl].
intros n d; destruct n; destruct d; simpl; auto.
intros n d; destruct n; destruct d; simpl; auto.
destruct a; destruct (split l); simpl; auto.
destruct a; destruct (split l); simpl in *; auto.
apply IHl.
Qed.
Lemma split_length_l : forall (l:list (A*B)),
length (fst (split l)) = length l.
Proof.
intro l; induction l as [|a l IHl]; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
Lemma split_length_r : forall (l:list (A*B)),
length (snd (split l)) = length l.
Proof.
intro l; induction l as [|a l IHl]; simpl; auto.
destruct a; destruct (split l); simpl; auto.
Qed.
(** [combine] is the opposite of [split].
Lists given to [combine] are meant to be of same length.
If not, [combine] stops on the shorter list *)
Fixpoint combine (l : list A) (l' : list B) : list (A*B) :=
match l,l' with
| x::tl, y::tl' => (x,y)::(combine tl tl')
| _, _ => nil
end.
Lemma split_combine : forall (l: list (A*B)),
forall l1 l2, split l = (l1, l2) -> combine l1 l2 = l.
Proof.
intro l; induction l as [|a l IHl].
simpl; auto.
all: intuition; inversion H; auto.
destruct (split l); simpl in *.
inversion H1; subst; simpl.
f_equal; auto.
Qed.
Lemma combine_split : forall (l:list A)(l':list B), length l = length l' ->
split (combine l l') = (l,l').
Proof.
intro l; induction l as [|a l IHl]; intro l'; destruct l';
simpl; trivial; try discriminate.
now intros [= ->%IHl].
Qed.
Lemma in_combine_l : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In x l.
Proof.
intro l; induction l as [|a l IHl].
simpl; auto.
intro l'; destruct l' as [|a0 l']; simpl; auto; intros x y H.
contradiction.
destruct H as [H|H].
injection H; auto.
right; apply IHl with l' y; auto.
Qed.
Lemma in_combine_r : forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (combine l l') -> In y l'.
Proof.
intro l; induction l as [|? ? IHl].
simpl; intros; contradiction.
intro l'; destruct l'; simpl; auto; intros x y H.
destruct H as [H|H].
injection H; auto.
right; apply IHl with x; auto.
Qed.
Lemma combine_length : forall (l:list A)(l':list B),
length (combine l l') = min (length l) (length l').
Proof.
intro l; induction l.
simpl; auto.
intro l'; destruct l'; simpl; auto.
Qed.
Lemma combine_nth : forall (l:list A)(l':list B)(n:nat)(x:A)(y:B),
length l = length l' ->
nth n (combine l l') (x,y) = (nth n l x, nth n l' y).
Proof.
intro l; induction l; intro l'; destruct l'; intros n x y; try discriminate.
destruct n; simpl; auto.
destruct n; simpl in *; auto.
Qed.
(** [list_prod] has the same signature as [combine], but unlike
[combine], it adds every possible pairs, not only those at the
same position. *)
Fixpoint list_prod (l:list A) (l':list B) :
list (A * B) :=
match l with
| nil => nil
| cons x t => (map (fun y:B => (x, y)) l')++(list_prod t l')
end.
Lemma in_prod_aux :
forall (x:A) (y:B) (l:list B),
In y l -> In (x, y) (map (fun y0:B => (x, y0)) l).
Proof.
intros x y l; induction l;
[ simpl; auto
| simpl; destruct 1 as [H1| ];
[ left; rewrite H1; trivial | right; auto ] ].
Qed.
Lemma in_prod :
forall (l:list A) (l':list B) (x:A) (y:B),
In x l -> In y l' -> In (x, y) (list_prod l l').
Proof.
intro l; induction l;
[ simpl; tauto
| simpl; intros l' x y H H0; apply in_or_app; destruct H as [H|H];
[ left; rewrite H; apply in_prod_aux; assumption | right; auto ] ].
Qed.
Lemma in_prod_iff :
forall (l:list A)(l':list B)(x:A)(y:B),
In (x,y) (list_prod l l') <-> In x l /\ In y l'.
Proof.
intros l l' x y; split; [ | intros H; now apply in_prod ].
induction l as [|a l IHl]; cbn; [easy|].
intros [[? [[= -> ->] ?]] %in_map_iff|] %in_app_or; tauto.
Qed.
Lemma prod_length : forall (l:list A)(l':list B),
length (list_prod l l') = (length l) * (length l').
Proof.
intro l; induction l as [|? ? IHl]; simpl; [easy|].
intros. now rewrite app_length, map_length, IHl.
Qed.
End ListPairs.
(*****************************************)
(** * Miscellaneous operations on lists *)
(*****************************************)
(******************************)
(** ** Length order of lists *)
(******************************)
Section length_order.
Variable A : Type.
Definition lel (l m:list A) := length l <= length m.
Variables a b : A.
Variables l m n : list A.
Lemma lel_refl : lel l l.
Proof.
now apply Nat.le_refl.
Qed.
Lemma lel_trans : lel l m -> lel m n -> lel l n.
Proof.
unfold lel; intros.
now_show (length l <= length n).
now apply Nat.le_trans with (length m).
Qed.
Lemma lel_cons_cons : lel l m -> lel (a :: l) (b :: m).
Proof.
now intros ? %Nat.succ_le_mono.
Qed.
Lemma lel_cons : lel l m -> lel l (b :: m).
Proof.
intros. now apply Nat.le_le_succ_r.
Qed.
Lemma lel_tail : lel (a :: l) (b :: m) -> lel l m.
Proof.
intros. now apply Nat.succ_le_mono.
Qed.
Lemma lel_nil : forall l':list A, lel l' nil -> nil = l'.
Proof.
intro l'; elim l'; [now intros|].
now intros a' y H H0 %Nat.nle_succ_0.
Qed.
End length_order.
#[global]
Hint Resolve lel_refl lel_cons_cons lel_cons lel_nil lel_nil nil_cons:
datatypes.
(******************************)
(** ** Set inclusion on list *)
(******************************)
Section SetIncl.
Variable A : Type.
Definition incl (l m:list A) := forall a:A, In a l -> In a m.
#[local]
Hint Unfold incl : core.
Lemma incl_nil_l : forall l, incl nil l.
Proof.
intros l a Hin; inversion Hin.
Qed.
Lemma incl_l_nil : forall l, incl l nil -> l = nil.
Proof.
intro l; destruct l as [|a l]; intros Hincl.
- reflexivity.
- exfalso; apply Hincl with a; simpl; auto.
Qed.
Lemma incl_refl : forall l:list A, incl l l.
Proof.
auto.
Qed.
#[local]
Hint Resolve incl_refl : core.
Lemma incl_tl : forall (a:A) (l m:list A), incl l m -> incl l (a :: m).
Proof.
auto with datatypes.
Qed.
#[local]
Hint Immediate incl_tl : core.
Lemma incl_tran : forall l m n:list A, incl l m -> incl m n -> incl l n.
Proof.
auto.
Qed.
Lemma incl_appl : forall l m n:list A, incl l n -> incl l (n ++ m).
Proof.
auto with datatypes.
Qed.
#[local]
Hint Immediate incl_appl : core.
Lemma incl_appr : forall l m n:list A, incl l n -> incl l (m ++ n).
Proof.
auto with datatypes.
Qed.
#[local]
Hint Immediate incl_appr : core.
Lemma incl_cons :
forall (a:A) (l m:list A), In a m -> incl l m -> incl (a :: l) m.
Proof.
now intros a l m ? H b [<-|]; [|apply H].
Qed.
#[local]
Hint Resolve incl_cons : core.
Lemma incl_cons_inv : forall (a:A) (l m:list A),
incl (a :: l) m -> In a m /\ incl l m.
Proof.
intros a l m Hi.
split; [ | intros ? ? ]; apply Hi; simpl; auto.
Qed.
Lemma incl_app : forall l m n:list A, incl l n -> incl m n -> incl (l ++ m) n.
Proof.
unfold incl; simpl; intros l m n H H0 a H1.
now_show (In a n).
elim (in_app_or _ _ _ H1); auto.
Qed.
#[local]
Hint Resolve incl_app : core.
Lemma incl_app_app : forall l1 l2 m1 m2:list A,
incl l1 m1 -> incl l2 m2 -> incl (l1 ++ l2) (m1 ++ m2).
Proof.
intros.
apply incl_app; [ apply incl_appl | apply incl_appr]; assumption.
Qed.
Lemma incl_app_inv : forall l1 l2 m : list A,
incl (l1 ++ l2) m -> incl l1 m /\ incl l2 m.
Proof.
intro l1; induction l1 as [|a l1 IHl1]; intros l2 m Hin; split; auto.
- apply incl_nil_l.
- intros b Hb; inversion_clear Hb; subst; apply Hin.
+ now constructor.
+ simpl; apply in_cons.
apply incl_appl with l1; [ apply incl_refl | assumption ].
- apply IHl1.
now apply incl_cons_inv in Hin.
Qed.
Lemma incl_filter f l : incl (filter f l) l.
Proof. intros x Hin; now apply filter_In in Hin. Qed.
Lemma remove_incl (eq_dec : forall x y : A, {x = y} + {x <> y}) : forall l1 l2 x,
incl l1 l2 -> incl (remove eq_dec x l1) (remove eq_dec x l2).
Proof.
intros l1 l2 x Hincl y Hin.
apply in_remove in Hin; destruct Hin as [Hin Hneq].
apply in_in_remove; intuition.
Qed.
End SetIncl.
Lemma incl_map A B (f : A -> B) l1 l2 : incl l1 l2 -> incl (map f l1) (map f l2).
Proof.
intros Hincl x Hinx.
destruct (proj1 (in_map_iff _ _ _) Hinx) as [y [<- Hiny]].
now apply in_map, Hincl.
Qed.
#[global]
Hint Resolve incl_refl incl_tl incl_tran incl_appl incl_appr incl_cons
incl_app incl_map: datatypes.
(**************************************)
(** * Cutting a list at some position *)
(**************************************)
Section Cutting.
Variable A : Type.
Fixpoint firstn (n:nat)(l:list A) : list A :=
match n with
| 0 => nil
| S n => match l with
| nil => nil
| a::l => a::(firstn n l)
end
end.
Lemma firstn_nil n: firstn n [] = [].
Proof. induction n; now simpl. Qed.
Lemma firstn_cons n a l: firstn (S n) (a::l) = a :: (firstn n l).
Proof. now simpl. Qed.
Lemma firstn_all l: firstn (length l) l = l.
Proof. induction l as [| ? ? H]; simpl; [reflexivity | now rewrite H]. Qed.
Lemma firstn_all2 n: forall (l:list A), (length l) <= n -> firstn n l = l.
Proof. induction n as [|k iHk].
- intro l. inversion 1 as [H1|?].
rewrite (length_zero_iff_nil l) in H1. subst. now simpl.
- intro l; destruct l as [|x xs]; simpl.
* now reflexivity.
* simpl. intro H. f_equal. apply iHk. now apply Nat.succ_le_mono.
Qed.
Lemma firstn_O l: firstn 0 l = [].
Proof. now simpl. Qed.
Lemma firstn_le_length n: forall l:list A, length (firstn n l) <= n.
Proof.
induction n as [|k iHk]; simpl; [auto | intro l; destruct l as [|x xs]; simpl].
- now apply Nat.le_0_l.
- now rewrite <- Nat.succ_le_mono.
Qed.
Lemma firstn_length_le: forall l:list A, forall n:nat,
n <= length l -> length (firstn n l) = n.
Proof. intro l; induction l as [|x xs Hrec].
- simpl. intros n H. apply Nat.le_0_r in H. now subst.
- intro n; destruct n as [|n].
* now simpl.
* simpl. intro H. f_equal. apply Hrec. now apply Nat.succ_le_mono.
Qed.
Lemma firstn_app n:
forall l1 l2,
firstn n (l1 ++ l2) = (firstn n l1) ++ (firstn (n - length l1) l2).
Proof. induction n as [|k iHk]; intros l1 l2.
- now simpl.
- destruct l1 as [|x xs].
* reflexivity.
* rewrite <- app_comm_cons. simpl. f_equal. apply iHk.
Qed.
Lemma firstn_app_2 n:
forall l1 l2,
firstn ((length l1) + n) (l1 ++ l2) = l1 ++ firstn n l2.
Proof. induction n as [| k iHk];intros l1 l2.
- unfold firstn at 2. rewrite Nat.add_0_r, app_nil_r.
rewrite firstn_app. rewrite Nat.sub_diag.
unfold firstn at 2. rewrite app_nil_r. apply firstn_all.
- destruct l2 as [|x xs].
* simpl. rewrite app_nil_r. apply firstn_all2. now apply Nat.le_add_r.
* rewrite firstn_app. assert (H0 : (length l1 + S k - length l1) = S k).
now rewrite Nat.add_comm, Nat.add_sub.
rewrite H0, firstn_all2; [reflexivity | now apply Nat.le_add_r].
Qed.
Lemma firstn_firstn:
forall l:list A,
forall i j : nat,
firstn i (firstn j l) = firstn (min i j) l.
Proof. intro l; induction l as [|x xs Hl].
- intros. simpl. now rewrite ?firstn_nil.
- intros [|i]; [easy|].
intros [|j]; [easy|].
cbn. f_equal. apply Hl.
Qed.
Fixpoint skipn (n:nat)(l:list A) : list A :=
match n with
| 0 => l
| S n => match l with
| nil => nil
| a::l => skipn n l
end
end.
Lemma firstn_skipn_comm : forall m n l,
firstn m (skipn n l) = skipn n (firstn (n + m) l).
Proof. now intros m n; induction n; intros []; simpl; destruct m. Qed.
Lemma skipn_firstn_comm : forall m n l,
skipn m (firstn n l) = firstn (n - m) (skipn m l).
Proof. now intro m; induction m; intros [] []; simpl; rewrite ?firstn_nil. Qed.
Lemma skipn_O : forall l, skipn 0 l = l.
Proof. reflexivity. Qed.
Lemma skipn_nil : forall n, skipn n ([] : list A) = [].
Proof. now intros []. Qed.
Lemma skipn_cons n a l: skipn (S n) (a::l) = skipn n l.
Proof. reflexivity. Qed.
Lemma skipn_all : forall l, skipn (length l) l = nil.
Proof. now intro l; induction l. Qed.
#[deprecated(since="8.12",note="Use skipn_all instead.")] Notation skipn_none := skipn_all.
Lemma skipn_all2 n: forall l, length l <= n -> skipn n l = [].
Proof.
intros l L%Nat.sub_0_le; rewrite <-(firstn_all l) at 1.
now rewrite skipn_firstn_comm, L.
Qed.
Lemma firstn_skipn : forall n l, firstn n l ++ skipn n l = l.
Proof.
intro n; induction n.
simpl; auto.
intro l; destruct l; simpl; auto.
f_equal; auto.
Qed.
Lemma firstn_length : forall n l, length (firstn n l) = min n (length l).
Proof.
intro n; induction n; intro l; destruct l; simpl; auto.
Qed.
Lemma skipn_length n :
forall l, length (skipn n l) = length l - n.
Proof.
induction n.
- intros l; simpl; rewrite Nat.sub_0_r; reflexivity.
- intro l; destruct l; simpl; auto.
Qed.
Lemma skipn_app n : forall l1 l2,
skipn n (l1 ++ l2) = (skipn n l1) ++ (skipn (n - length l1) l2).
Proof. induction n; auto; intros [|]; simpl; auto. Qed.
Lemma firstn_skipn_rev: forall x l,
firstn x l = rev (skipn (length l - x) (rev l)).
Proof.
intros x l; rewrite <-(firstn_skipn x l) at 3.
rewrite rev_app_distr, skipn_app, rev_app_distr, rev_length,
skipn_length, Nat.sub_diag; simpl; rewrite rev_involutive.
rewrite <-app_nil_r at 1; f_equal; symmetry; apply length_zero_iff_nil.
repeat rewrite rev_length, skipn_length; apply Nat.sub_diag.
Qed.
Lemma firstn_rev: forall x l,
firstn x (rev l) = rev (skipn (length l - x) l).
Proof.
now intros x l; rewrite firstn_skipn_rev, rev_involutive, rev_length.
Qed.
Lemma skipn_rev: forall x l,
skipn x (rev l) = rev (firstn (length l - x) l).
Proof.
intros x l; rewrite firstn_skipn_rev, rev_involutive, <-rev_length.
destruct (Nat.le_ge_cases (length (rev l)) x) as [L | L].
- rewrite skipn_all2; [apply Nat.sub_0_le in L | trivial].
now rewrite L, Nat.sub_0_r, skipn_all.
- f_equal. now apply Nat.eq_sym, Nat.add_sub_eq_l, Nat.sub_add.
Qed.
Lemma removelast_firstn : forall n l, n < length l ->
removelast (firstn (S n) l) = firstn n l.
Proof.
intro n; induction n as [|n IHn]; intros [|? l]; [easy ..|].
cbn [length firstn]. destruct l.
- now intros ? %Nat.succ_lt_mono.
- now intros <- %Nat.succ_lt_mono %IHn.
Qed.
Lemma removelast_firstn_len : forall l,
removelast l = firstn (pred (length l)) l.
Proof.
intro l; induction l as [|a l IHl]; [ reflexivity | simpl ].
destruct l; [ | rewrite IHl ]; reflexivity.
Qed.
Lemma firstn_removelast : forall n l, n < length l ->
firstn n (removelast l) = firstn n l.
Proof.
intro n; induction n as [|n IHn]; intros [|? l]; [easy ..|].
cbn [length firstn]. destruct l.
- now intros ? %Nat.succ_lt_mono.
- now intros <- %Nat.succ_lt_mono %IHn.
Qed.
End Cutting.
Section CuttingMap.
Variables A B : Type.
Variable f : A -> B.
Lemma firstn_map : forall n l,
firstn n (map f l) = map f (firstn n l).
Proof.
intro n; induction n; intros []; simpl; f_equal; trivial.
Qed.
Lemma skipn_map : forall n l,
skipn n (map f l) = map f (skipn n l).
Proof.
intro n; induction n; intros []; simpl; trivial.
Qed.
End CuttingMap.
(**************************************************************)
(** ** Combining pairs of lists of possibly-different lengths *)
(**************************************************************)
Section Combining.
Variables (A B : Type).
Lemma combine_nil : forall (l : list A),
combine l (@nil B) = @nil (A*B).
Proof.
intros l.
apply length_zero_iff_nil.
rewrite combine_length. simpl. rewrite Nat.min_0_r.
reflexivity.
Qed.
Lemma combine_firstn_l : forall (l : list A) (l' : list B),
combine l l' = combine l (firstn (length l) l').
Proof.
intro l; induction l as [| x l IHl]; intros l'; [reflexivity|].
destruct l' as [| x' l']; [reflexivity|].
simpl. specialize IHl with l'. rewrite <- IHl.
reflexivity.
Qed.
Lemma combine_firstn_r : forall (l : list A) (l' : list B),
combine l l' = combine (firstn (length l') l) l'.
Proof.
intros l l'. generalize dependent l.
induction l' as [| x' l' IHl']; intros l.
- simpl. apply combine_nil.
- destruct l as [| x l]; [reflexivity|].
simpl. specialize IHl' with l. rewrite <- IHl'.
reflexivity.
Qed.
Lemma combine_firstn : forall (l : list A) (l' : list B) (n : nat),
firstn n (combine l l') = combine (firstn n l) (firstn n l').
Proof.
intro l; induction l as [| x l IHl]; intros l' n.
- simpl. repeat (rewrite firstn_nil). reflexivity.
- destruct l' as [| x' l'].
+ simpl. repeat (rewrite firstn_nil). rewrite combine_nil. reflexivity.
+ simpl. destruct n as [| n]; [reflexivity|].
repeat (rewrite firstn_cons). simpl.
rewrite IHl. reflexivity.
Qed.
End Combining.
(**********************************************************************)
(** ** Predicate for List addition/removal (no need for decidability) *)
(**********************************************************************)
Section Add.
Variable A : Type.
(* [Add a l l'] means that [l'] is exactly [l], with [a] added
once somewhere *)
Inductive Add (a:A) : list A -> list A -> Prop :=
| Add_head l : Add a l (a::l)
| Add_cons x l l' : Add a l l' -> Add a (x::l) (x::l').
Lemma Add_app a l1 l2 : Add a (l1++l2) (l1++a::l2).
Proof.
induction l1; simpl; now constructor.
Qed.
Lemma Add_split a l l' :
Add a l l' -> exists l1 l2, l = l1++l2 /\ l' = l1++a::l2.
Proof.
induction 1 as [l|x ? ? ? IHAdd].
- exists nil; exists l; split; trivial.
- destruct IHAdd as (l1 & l2 & Hl & Hl').
exists (x::l1); exists l2; split; simpl; f_equal; trivial.
Qed.
Lemma Add_in a l l' : Add a l l' ->
forall x, In x l' <-> In x (a::l).
Proof.
induction 1 as [|? ? ? ? IHAdd]; intros; simpl in *; rewrite ?IHAdd; tauto.
Qed.
Lemma Add_length a l l' : Add a l l' -> length l' = S (length l).
Proof.
induction 1; simpl; now auto.
Qed.
Lemma Add_inv a l : In a l -> exists l', Add a l' l.
Proof.
intro Ha. destruct (in_split _ _ Ha) as (l1 & l2 & ->).
exists (l1 ++ l2). apply Add_app.
Qed.
Lemma incl_Add_inv a l u v :
~In a l -> incl (a::l) v -> Add a u v -> incl l u.
Proof.
intros Ha H AD y Hy.
assert (Hy' : In y (a::u)).
{ rewrite <- (Add_in AD). apply H; simpl; auto. }
destruct Hy'; [ subst; now elim Ha | trivial ].
Qed.
End Add.
(********************************)
(** ** Lists without redundancy *)
(********************************)
Section ReDun.
Variable A : Type.
Inductive NoDup : list A -> Prop :=
| NoDup_nil : NoDup nil
| NoDup_cons : forall x l, ~ In x l -> NoDup l -> NoDup (x::l).
Lemma NoDup_Add a l l' : Add a l l' -> (NoDup l' <-> NoDup l /\ ~In a l).
Proof.
induction 1 as [l|x l l' AD IH].
- split; [ inversion_clear 1; now split | now constructor ].
- split.
+ inversion_clear 1. rewrite IH in *. rewrite (Add_in AD) in *.
simpl in *; split; try constructor; intuition.
+ intros (N,IN). inversion_clear N. constructor.
* rewrite (Add_in AD); simpl in *; intuition.
* apply IH. split; trivial. simpl in *; intuition.
Qed.
Lemma NoDup_remove l l' a :
NoDup (l++a::l') -> NoDup (l++l') /\ ~In a (l++l').
Proof.
apply NoDup_Add. apply Add_app.
Qed.
Lemma NoDup_remove_1 l l' a : NoDup (l++a::l') -> NoDup (l++l').
Proof.
intros. now apply NoDup_remove with a.
Qed.
Lemma NoDup_remove_2 l l' a : NoDup (l++a::l') -> ~In a (l++l').
Proof.
intros. now apply NoDup_remove.
Qed.
Theorem NoDup_cons_iff a l:
NoDup (a::l) <-> ~ In a l /\ NoDup l.
Proof.
split.
+ inversion_clear 1. now split.
+ now constructor.
Qed.
Lemma NoDup_rev l : NoDup l -> NoDup (rev l).
Proof.
induction l as [|a l IHl]; simpl; intros Hnd; [ constructor | ].
inversion_clear Hnd as [ | ? ? Hnin Hndl ].
assert (Add a (rev l) (rev l ++ a :: nil)) as Hadd
by (rewrite <- (app_nil_r (rev l)) at 1; apply Add_app).
apply NoDup_Add in Hadd; apply Hadd; intuition.
now apply Hnin, in_rev.
Qed.
Lemma NoDup_filter f l : NoDup l -> NoDup (filter f l).
Proof.
induction l as [|a l IHl]; simpl; intros Hnd; auto.
apply NoDup_cons_iff in Hnd.
destruct (f a); [ | intuition ].
apply NoDup_cons_iff; split; [intro H|]; intuition.
apply filter_In in H; intuition.
Qed.
(** Effective computation of a list without duplicates *)
Hypothesis decA: forall x y : A, {x = y} + {x <> y}.
Fixpoint nodup (l : list A) : list A :=
match l with
| [] => []
| x::xs => if in_dec decA x xs then nodup xs else x::(nodup xs)
end.
Lemma nodup_fixed_point (l : list A) :
NoDup l -> nodup l = l.
Proof.
induction l as [| x l IHl]; [auto|]. intros H.
simpl. destruct (in_dec decA x l) as [Hx | Hx]; rewrite NoDup_cons_iff in H.
- destruct H as [H' _]. contradiction.
- destruct H as [_ H']. apply IHl in H'. rewrite -> H'. reflexivity.
Qed.
Lemma nodup_In l x : In x (nodup l) <-> In x l.
Proof.
induction l as [|a l' Hrec]; simpl.
- reflexivity.
- destruct (in_dec decA a l'); simpl; rewrite Hrec.
* now intuition subst.
* reflexivity.
Qed.
Lemma nodup_incl l1 l2 : incl l1 (nodup l2) <-> incl l1 l2.
Proof.
split; intros Hincl a Ha; apply nodup_In; intuition.
Qed.
Lemma NoDup_nodup l: NoDup (nodup l).
Proof.
induction l as [|a l' Hrec]; simpl.
- constructor.
- destruct (in_dec decA a l'); simpl.
* assumption.
* constructor; [ now rewrite nodup_In | assumption].
Qed.
Lemma nodup_inv k l a : nodup k = a :: l -> ~ In a l.
Proof.
intros H.
assert (H' : NoDup (a::l)).
{ rewrite <- H. apply NoDup_nodup. }
now inversion_clear H'.
Qed.
Theorem NoDup_count_occ l:
NoDup l <-> (forall x:A, count_occ decA l x <= 1).
Proof.
induction l as [| a l' Hrec].
- simpl; split; auto. constructor.
- rewrite NoDup_cons_iff, Hrec, (count_occ_not_In decA). clear Hrec. split.
+ intros (Ha, H) x. simpl. destruct (decA a x); auto.
subst; now rewrite Ha.
+ intro H; split.
* specialize (H a). rewrite count_occ_cons_eq in H; trivial.
now inversion H.
* intros x. specialize (H x). simpl in *. destruct (decA a x); auto.
now apply Nat.lt_le_incl.
Qed.
Theorem NoDup_count_occ' l:
NoDup l <-> (forall x:A, In x l -> count_occ decA l x = 1).
Proof.
rewrite NoDup_count_occ.
setoid_rewrite (count_occ_In decA). unfold gt, lt in *.
split; intros H x; specialize (H x);
set (n := count_occ decA l x) in *; clearbody n.
(* the rest would be solved by omega if we had it here... *)
- now apply Nat.le_antisymm.
- destruct (Nat.le_gt_cases 1 n); trivial.
+ rewrite H; trivial.
+ now apply Nat.lt_le_incl.
Qed.
(** Alternative characterisations of being without duplicates,
thanks to [nth_error] and [nth] *)
Lemma NoDup_nth_error l :
NoDup l <->
(forall i j, i<length l -> nth_error l i = nth_error l j -> i = j).
Proof.
split.
{ intros H; induction H as [|a l Hal Hl IH]; intros i j Hi E.
- inversion Hi.
- destruct i, j; simpl in *; auto.
* elim Hal. eapply nth_error_In; eauto.
* elim Hal. eapply nth_error_In; eauto.
* f_equal. now apply IH;[apply Nat.succ_lt_mono|]. }
{ induction l as [|a l IHl]; intros H; constructor.
* intro Ha. apply In_nth_error in Ha. destruct Ha as (n,Hn).
assert (n < length l) by (now rewrite <- nth_error_Some, Hn).
specialize (H 0 (S n)). simpl in H. now discriminate H; [apply Nat.lt_0_succ|].
* apply IHl.
intros i j Hi %Nat.succ_lt_mono E. now apply eq_add_S, H. }
Qed.
Lemma NoDup_nth l d :
NoDup l <->
(forall i j, i<length l -> j<length l ->
nth i l d = nth j l d -> i = j).
Proof.
rewrite NoDup_nth_error. split.
- intros H i j ? ? E. apply H; [assumption|].
now rewrite !(nth_error_nth' l d), E.
- intros H i j ? E. assert (j < length l).
{ apply nth_error_Some. rewrite <- E. now apply nth_error_Some. }
apply H; [assumption ..|].
rewrite !(nth_error_nth' l d) in E; congruence.
Qed.
(** Having [NoDup] hypotheses bring more precise facts about [incl]. *)
Lemma NoDup_incl_length l l' :
NoDup l -> incl l l' -> length l <= length l'.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH]; simpl.
- intros. now apply Nat.le_0_l.
- intros l' H.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_length AD). apply le_n_S. apply IH.
now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_length_incl l l' :
NoDup l -> length l' <= length l -> incl l l' -> incl l' l.
Proof.
intros N. revert l'. induction N as [|a l Hal N IH].
- intro l'; destruct l'; easy.
- intros l' E H x Hx.
destruct (Add_inv a l') as (l'', AD). { apply H; simpl; auto. }
rewrite (Add_in AD) in Hx. simpl in Hx.
destruct Hx as [Hx|Hx]; [left; trivial|right].
revert x Hx. apply (IH l''); trivial.
* apply Nat.succ_le_mono. now rewrite <- (Add_length AD).
* now apply incl_Add_inv with a l'.
Qed.
Lemma NoDup_incl_NoDup (l l' : list A) : NoDup l ->
length l' <= length l -> incl l l' -> NoDup l'.
Proof.
revert l'; induction l as [|a l IHl]; simpl; intros l' Hnd Hlen Hincl.
- now destruct l'; inversion Hlen.
- assert (In a l') as Ha by now apply Hincl; left.
apply in_split in Ha as [l1' [l2' ->]].
inversion_clear Hnd as [|? ? Hnin Hnd'].
apply (NoDup_Add (Add_app a l1' l2')); split.
+ apply IHl; auto.
* rewrite app_length.
rewrite app_length in Hlen; simpl in Hlen; rewrite Nat.add_succ_r in Hlen.
now apply Nat.succ_le_mono.
* apply (incl_Add_inv (u:= l1' ++ l2')) in Hincl; auto.
apply Add_app.
+ intros Hnin'.
assert (incl (a :: l) (l1' ++ l2')) as Hincl''.
{ apply incl_tran with (l1' ++ a :: l2'); auto.
intros x Hin.
apply in_app_or in Hin as [Hin|[->|Hin]]; intuition. }
apply NoDup_incl_length in Hincl''; [ | now constructor ].
apply (Nat.nle_succ_diag_l (length l1' + length l2')).
rewrite_all app_length.
simpl in Hlen; rewrite Nat.add_succ_r in Hlen.
now transitivity (S (length l)).
Qed.
End ReDun.
(** NoDup and map *)
(** NB: the reciprocal result holds only for injective functions,
see FinFun.v *)
Lemma NoDup_map_inv A B (f:A->B) l : NoDup (map f l) -> NoDup l.
Proof.
induction l; simpl; inversion_clear 1; subst; constructor; auto.
intro H. now apply (in_map f) in H.
Qed.
(***********************************)
(** ** Sequence of natural numbers *)
(***********************************)
Section NatSeq.
(** [seq] computes the sequence of [len] contiguous integers
that starts at [start]. For instance, [seq 2 3] is [2::3::4::nil]. *)
Fixpoint seq (start len:nat) : list nat :=
match len with
| 0 => nil
| S len => start :: seq (S start) len
end.
Lemma cons_seq : forall len start, start :: seq (S start) len = seq start (S len).
Proof.
reflexivity.
Qed.
Lemma seq_length : forall len start, length (seq start len) = len.
Proof.
intro len; induction len; simpl; auto.
Qed.
Lemma seq_nth : forall len start n d,
n < len -> nth n (seq start len) d = start+n.
Proof.
intro len; induction len as [|len IHlen]; intros start n d H.
inversion H.
simpl seq.
destruct n; simpl. now rewrite Nat.add_0_r.
now rewrite IHlen; [rewrite Nat.add_succ_r|apply Nat.succ_lt_mono].
Qed.
Lemma seq_shift : forall len start,
map S (seq start len) = seq (S start) len.
Proof.
intro len; induction len as [|len IHlen]; simpl; auto.
intros.
now rewrite IHlen.
Qed.
Lemma in_seq len start n :
In n (seq start len) <-> start <= n < start+len.
Proof.
revert start. induction len as [|len IHlen]; simpl; intros start.
- rewrite Nat.add_0_r. split;[easy|].
intros (H,H'). apply (Nat.lt_irrefl start).
eapply Nat.le_lt_trans; eassumption.
- rewrite IHlen, Nat.add_succ_r; simpl; split.
+ intros [H|H]; subst; intuition.
* apply -> Nat.succ_le_mono. apply Nat.le_add_r.
* now apply Nat.lt_le_incl.
+ intros (H,H'). inversion H.
* now left.
* right. subst. now split; [apply -> Nat.succ_le_mono|].
Qed.
Lemma seq_NoDup len start : NoDup (seq start len).
Proof.
revert start; induction len as [|len IH];
intros start; simpl; constructor; trivial.
rewrite in_seq. intros (H,_). now apply (Nat.lt_irrefl start).
Qed.
Lemma seq_app : forall len1 len2 start,
seq start (len1 + len2) = seq start len1 ++ seq (start + len1) len2.
Proof.
intro len1; induction len1 as [|len1' IHlen]; intros; simpl in *.
- now rewrite Nat.add_0_r.
- now rewrite Nat.add_succ_r, IHlen.
Qed.
Lemma seq_S : forall len start, seq start (S len) = seq start len ++ [start + len].
Proof.
intros len start.
change [start + len] with (seq (start + len) 1).
rewrite <- seq_app.
rewrite Nat.add_succ_r, Nat.add_0_r; reflexivity.
Qed.
End NatSeq.
Section Exists_Forall.
(** * Existential and universal predicates over lists *)
Variable A:Type.
Section One_predicate.
Variable P:A->Prop.
Inductive Exists : list A -> Prop :=
| Exists_cons_hd : forall x l, P x -> Exists (x::l)
| Exists_cons_tl : forall x l, Exists l -> Exists (x::l).
#[local]
Hint Constructors Exists : core.
Lemma Exists_exists (l:list A) :
Exists l <-> (exists x, In x l /\ P x).
Proof.
split.
- induction 1; firstorder.
- induction l; firstorder (subst; auto).
Qed.
Lemma Exists_nth l :
Exists l <-> exists i d, i < length l /\ P (nth i l d).
Proof.
split.
- intros HE; apply Exists_exists in HE.
destruct HE as [a [Hin HP]].
apply (In_nth _ _ a) in Hin; destruct Hin as [i [Hl Heq]].
rewrite <- Heq in HP.
now exists i; exists a.
- intros [i [d [Hl HP]]].
apply Exists_exists; exists (nth i l d); split.
apply nth_In; assumption.
assumption.
Qed.
Lemma Exists_nil : Exists nil <-> False.
Proof. split; inversion 1. Qed.
Lemma Exists_cons x l:
Exists (x::l) <-> P x \/ Exists l.
Proof. split; inversion 1; auto. Qed.
Lemma Exists_app l1 l2 :
Exists (l1 ++ l2) <-> Exists l1 \/ Exists l2.
Proof.
induction l1; simpl; split; intros HE; try now intuition.
- inversion_clear HE; intuition.
- destruct HE as [HE|HE]; intuition.
inversion_clear HE; intuition.
Qed.
Lemma Exists_rev l : Exists l -> Exists (rev l).
Proof.
induction l; intros HE; intuition.
inversion_clear HE; simpl; apply Exists_app; intuition.
Qed.
Lemma Exists_dec l:
(forall x:A, {P x} + { ~ P x }) ->
{Exists l} + {~ Exists l}.
Proof.
intro Pdec. induction l as [|a l' Hrec].
- right. abstract now rewrite Exists_nil.
- destruct Hrec as [Hl'|Hl'].
+ left. now apply Exists_cons_tl.
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Exists_cons_hd.
* right. abstract now inversion 1.
Defined.
Lemma Exists_fold_right l :
Exists l <-> fold_right (fun x => or (P x)) False l.
Proof.
induction l; simpl; split; intros HE; try now inversion HE; intuition.
Qed.
Lemma incl_Exists l1 l2 : incl l1 l2 -> Exists l1 -> Exists l2.
Proof.
intros Hincl HE.
apply Exists_exists in HE; destruct HE as [a [Hin HP]].
apply Exists_exists; exists a; intuition.
Qed.
Inductive Forall : list A -> Prop :=
| Forall_nil : Forall nil
| Forall_cons : forall x l, P x -> Forall l -> Forall (x::l).
#[local]
Hint Constructors Forall : core.
Lemma Forall_inv : forall (a:A) l, Forall (a :: l) -> P a.
Proof.
intros a l H; inversion H; trivial.
Qed.
Theorem Forall_inv_tail : forall (a:A) l, Forall (a :: l) -> Forall l.
Proof.
intros a l H; inversion H; trivial.
Qed.
Lemma Forall_nil_iff : Forall [] <-> True.
Proof.
easy.
Qed.
Lemma Forall_cons_iff : forall (a:A) l, Forall (a :: l) <-> P a /\ Forall l.
Proof.
intros. now split; [intro H; inversion H|constructor].
Qed.
Lemma Forall_forall (l:list A):
Forall l <-> (forall x, In x l -> P x).
Proof.
split.
- induction 1; firstorder (subst; auto).
- induction l; firstorder auto with datatypes.
Qed.
Lemma Forall_nth l :
Forall l <-> forall i d, i < length l -> P (nth i l d).
Proof.
split.
- intros HF i d Hl.
apply (Forall_forall l).
assumption.
apply nth_In; assumption.
- intros HF.
apply Forall_forall; intros a Hin.
apply (In_nth _ _ a) in Hin; destruct Hin as [i [Hl Heq]].
rewrite <- Heq; intuition.
Qed.
Lemma Forall_app l1 l2 :
Forall (l1 ++ l2) <-> Forall l1 /\ Forall l2.
Proof.
induction l1 as [|a l1 IH]; cbn.
- now rewrite Forall_nil_iff.
- now rewrite !Forall_cons_iff, IH, and_assoc.
Qed.
Lemma Forall_elt a l1 l2 : Forall (l1 ++ a :: l2) -> P a.
Proof.
intros HF; apply Forall_app in HF; destruct HF as [HF1 HF2]; now inversion HF2.
Qed.
Lemma Forall_rev l : Forall l -> Forall (rev l).
Proof.
induction l; intros HF; [assumption|].
inversion_clear HF; simpl; apply Forall_app; intuition.
Qed.
Lemma Forall_rect : forall (Q : list A -> Type),
Q [] -> (forall b l, P b -> Q (b :: l)) -> forall l, Forall l -> Q l.
Proof.
intros Q H H' l; induction l; intro; [|eapply H', Forall_inv]; eassumption.
Qed.
Lemma Forall_dec :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A, {Forall l} + {~ Forall l}.
Proof.
intros Pdec l. induction l as [|a l' Hrec].
- left. apply Forall_nil.
- destruct Hrec as [Hl'|Hl'].
+ destruct (Pdec a) as [Ha|Ha].
* left. now apply Forall_cons.
* right. abstract now inversion 1.
+ right. abstract now inversion 1.
Defined.
Lemma Forall_fold_right l :
Forall l <-> fold_right (fun x => and (P x)) True l.
Proof.
induction l; simpl; split; intros HF; try now inversion HF; intuition.
Qed.
Lemma incl_Forall l1 l2 : incl l2 l1 -> Forall l1 -> Forall l2.
Proof.
intros Hincl HF.
apply Forall_forall; intros a Ha.
apply (Forall_forall l1); intuition.
Qed.
End One_predicate.
Lemma map_ext_Forall B : forall (f g : A -> B) l,
Forall (fun x => f x = g x) l -> map f l = map g l.
Proof.
intros; apply map_ext_in, Forall_forall; assumption.
Qed.
Theorem Exists_impl : forall (P Q : A -> Prop), (forall a : A, P a -> Q a) ->
forall l, Exists P l -> Exists Q l.
Proof.
intros P Q H l H0.
induction H0 as [x l H0|x l H0 IHExists].
apply (Exists_cons_hd Q x l (H x H0)).
apply (Exists_cons_tl x IHExists).
Qed.
Lemma Exists_or : forall (P Q : A -> Prop) l,
Exists P l \/ Exists Q l -> Exists (fun x => P x \/ Q x) l.
Proof.
intros P Q l; induction l as [|a l IHl]; intros [H | H]; inversion H; subst.
1,3: apply Exists_cons_hd; auto.
all: apply Exists_cons_tl, IHl; auto.
Qed.
Lemma Exists_or_inv : forall (P Q : A -> Prop) l,
Exists (fun x => P x \/ Q x) l -> Exists P l \/ Exists Q l.
Proof.
intros P Q l; induction l as [|a l IHl];
intro Hl; inversion Hl as [ ? ? H | ? ? H ]; subst.
- inversion H; now repeat constructor.
- destruct (IHl H); now repeat constructor.
Qed.
Lemma Forall_impl : forall (P Q : A -> Prop), (forall a, P a -> Q a) ->
forall l, Forall P l -> Forall Q l.
Proof.
intros P Q H l. rewrite !Forall_forall. firstorder.
Qed.
Lemma Forall_and : forall (P Q : A -> Prop) l,
Forall P l -> Forall Q l -> Forall (fun x => P x /\ Q x) l.
Proof.
intros P Q l; induction l; intros HP HQ; constructor; inversion HP; inversion HQ; auto.
Qed.
Lemma Forall_and_inv : forall (P Q : A -> Prop) l,
Forall (fun x => P x /\ Q x) l -> Forall P l /\ Forall Q l.
Proof.
intros P Q l; induction l; intro Hl; split; constructor; inversion Hl; firstorder.
Qed.
Lemma Forall_Exists_neg (P:A->Prop)(l:list A) :
Forall (fun x => ~ P x) l <-> ~(Exists P l).
Proof.
rewrite Forall_forall, Exists_exists. firstorder.
Qed.
Lemma Exists_Forall_neg (P:A->Prop)(l:list A) :
(forall x, P x \/ ~P x) ->
Exists (fun x => ~ P x) l <-> ~(Forall P l).
Proof.
intro Dec.
split.
- rewrite Forall_forall, Exists_exists; firstorder.
- intros NF.
induction l as [|a l IH].
+ destruct NF. constructor.
+ destruct (Dec a) as [Ha|Ha].
* apply Exists_cons_tl, IH. contradict NF. now constructor.
* now apply Exists_cons_hd.
Qed.
Lemma neg_Forall_Exists_neg (P:A->Prop) (l:list A) :
(forall x:A, {P x} + { ~ P x }) ->
~ Forall P l ->
Exists (fun x => ~ P x) l.
Proof.
intro Dec.
apply Exists_Forall_neg; intros x.
destruct (Dec x); auto.
Qed.
Lemma Forall_Exists_dec (P:A->Prop) :
(forall x:A, {P x} + { ~ P x }) ->
forall l:list A,
{Forall P l} + {Exists (fun x => ~ P x) l}.
Proof.
intros Pdec l.
destruct (Forall_dec P Pdec l); [left|right]; trivial.
now apply neg_Forall_Exists_neg.
Defined.
Lemma incl_Forall_in_iff l l' :
incl l l' <-> Forall (fun x => In x l') l.
Proof. now rewrite Forall_forall; split. Qed.
End Exists_Forall.
#[global]
Hint Constructors Exists : core.
#[global]
Hint Constructors Forall : core.
Lemma Exists_map A B (f : A -> B) P l :
Exists P (map f l) <-> Exists (fun x => P (f x)) l.
Proof.
induction l as [|a l IHl].
- cbn. now rewrite Exists_nil.
- cbn. now rewrite ?Exists_cons, IHl.
Qed.
Lemma Exists_concat A P (ls : list (list A)) :
Exists P (concat ls) <-> Exists (Exists P) ls.
Proof.
induction ls as [|l ls IHls].
- cbn. now rewrite Exists_nil.
- cbn. now rewrite Exists_app, Exists_cons, IHls.
Qed.
Lemma Exists_flat_map A B P ls (f : A -> list B) :
Exists P (flat_map f ls) <-> Exists (fun d => Exists P (f d)) ls.
Proof.
now rewrite flat_map_concat_map, Exists_concat, Exists_map.
Qed.
Lemma Forall_map A B (f : A -> B) P l :
Forall P (map f l) <-> Forall (fun x => P (f x)) l.
Proof.
induction l as [|a l IHl]; cbn.
- now rewrite !Forall_nil_iff.
- now rewrite !Forall_cons_iff, IHl.
Qed.
Lemma Forall_concat A P (ls : list (list A)) :
Forall P (concat ls) <-> Forall (Forall P) ls.
Proof.
induction ls as [|l ls IHls]; cbn.
- now rewrite !Forall_nil_iff.
- now rewrite Forall_app, Forall_cons_iff, IHls.
Qed.
Lemma Forall_flat_map A B P ls (f : A -> list B) :
Forall P (flat_map f ls) <-> Forall (fun d => Forall P (f d)) ls.
Proof.
now rewrite flat_map_concat_map, Forall_concat, Forall_map.
Qed.
Lemma exists_Forall A B : forall (P : A -> B -> Prop) l,
(exists k, Forall (P k) l) -> Forall (fun x => exists k, P k x) l.
Proof.
intros P l; induction l as [|a l IHl]; intros [k HF]; constructor; inversion_clear HF.
- now exists k.
- now apply IHl; exists k.
Qed.
Lemma Forall_image A B : forall (f : A -> B) l,
Forall (fun y => exists x, y = f x) l <-> exists l', l = map f l'.
Proof.
intros f l; induction l as [|a l IHl]; split; intros HF.
- exists nil; reflexivity.
- constructor.
- apply Forall_cons_iff in HF as [[x ->] [l' ->] %IHl].
now exists (x :: l').
- destruct HF as [l' Heq].
symmetry in Heq; apply map_eq_cons in Heq.
destruct Heq as (x & tl & ? & ? & ?); subst.
constructor.
+ now exists x.
+ now apply IHl; exists tl.
Qed.
Lemma concat_nil_Forall A : forall (l : list (list A)),
concat l = nil <-> Forall (fun x => x = nil) l.
Proof.
intro l; induction l as [|a l IHl]; simpl; split; intros Hc; auto.
- apply app_eq_nil in Hc.
constructor; firstorder.
- inversion Hc; subst; simpl.
now apply IHl.
Qed.
Lemma in_flat_map_Exists A B : forall (f : A -> list B) x l,
In x (flat_map f l) <-> Exists (fun y => In x (f y)) l.
Proof.
intros f x l; rewrite in_flat_map.
split; apply Exists_exists.
Qed.
Lemma notin_flat_map_Forall A B : forall (f : A -> list B) x l,
~ In x (flat_map f l) <-> Forall (fun y => ~ In x (f y)) l.
Proof.
intros f x l; rewrite Forall_Exists_neg.
apply not_iff_compat, in_flat_map_Exists.
Qed.
Section Forall2.
(** [Forall2]: stating that elements of two lists are pairwise related. *)
Variables A B : Type.
Variable R : A -> B -> Prop.
Inductive Forall2 : list A -> list B -> Prop :=
| Forall2_nil : Forall2 [] []
| Forall2_cons : forall x y l l',
R x y -> Forall2 l l' -> Forall2 (x::l) (y::l').
#[local]
Hint Constructors Forall2 : core.
Theorem Forall2_refl : Forall2 [] [].
Proof. intros; apply Forall2_nil. Qed.
Theorem Forall2_app_inv_l : forall l1 l2 l',
Forall2 (l1 ++ l2) l' ->
exists l1' l2', Forall2 l1 l1' /\ Forall2 l2 l2' /\ l' = l1' ++ l2'.
Proof.
intro l1; induction l1 as [|a l1 IHl1]; intros l2 l' H.
exists [], l'; auto.
simpl in H; inversion H as [|? y ? ? ? H4]; subst; clear H.
apply IHl1 in H4 as (l1' & l2' & Hl1 & Hl2 & ->).
exists (y::l1'), l2'; simpl; auto.
Qed.
Theorem Forall2_app_inv_r : forall l1' l2' l,
Forall2 l (l1' ++ l2') ->
exists l1 l2, Forall2 l1 l1' /\ Forall2 l2 l2' /\ l = l1 ++ l2.
Proof.
intro l1'; induction l1' as [|a l1' IHl1']; intros l2' l H.
exists [], l; auto.
simpl in H; inversion H as [|x ? ? ? ? H4]; subst; clear H.
apply IHl1' in H4 as (l1 & l2 & Hl1 & Hl2 & ->).
exists (x::l1), l2; simpl; auto.
Qed.
Theorem Forall2_app : forall l1 l2 l1' l2',
Forall2 l1 l1' -> Forall2 l2 l2' -> Forall2 (l1 ++ l2) (l1' ++ l2').
Proof.
intros l1 l2 l1' l2' H H0. induction l1 in l1', H, H0 |- *; inversion H; subst; simpl; auto.
Qed.
End Forall2.
#[global]
Hint Constructors Forall2 : core.
Section ForallPairs.
(** [ForallPairs] : specifies that a certain relation should
always hold when inspecting all possible pairs of elements of a list. *)
Variable A : Type.
Variable R : A -> A -> Prop.
Definition ForallPairs l :=
forall a b, In a l -> In b l -> R a b.
(** [ForallOrdPairs] : we still check a relation over all pairs
of elements of a list, but now the order of elements matters. *)
Inductive ForallOrdPairs : list A -> Prop :=
| FOP_nil : ForallOrdPairs nil
| FOP_cons : forall a l,
Forall (R a) l -> ForallOrdPairs l -> ForallOrdPairs (a::l).
#[local]
Hint Constructors ForallOrdPairs : core.
Lemma ForallOrdPairs_In : forall l,
ForallOrdPairs l ->
forall x y, In x l -> In y l -> x=y \/ R x y \/ R y x.
Proof.
induction 1.
inversion 1.
simpl; destruct 1; destruct 1; subst; auto.
right; left. apply -> Forall_forall; eauto.
right; right. apply -> Forall_forall; eauto.
Qed.
(** [ForallPairs] implies [ForallOrdPairs]. The reverse implication is true
only when [R] is symmetric and reflexive. *)
Lemma ForallPairs_ForallOrdPairs l: ForallPairs l -> ForallOrdPairs l.
Proof.
induction l as [|a l IHl]; [easy|].
intros H. constructor.
- rewrite Forall_forall. intros; apply H; simpl; auto.
- apply IHl. red; intros; apply H; simpl; auto.
Qed.
Lemma ForallOrdPairs_ForallPairs :
(forall x, R x x) ->
(forall x y, R x y -> R y x) ->
forall l, ForallOrdPairs l -> ForallPairs l.
Proof.
intros Refl Sym l Hl x y Hx Hy.
destruct (ForallOrdPairs_In Hl _ _ Hx Hy); subst; intuition.
Qed.
End ForallPairs.
Section Repeat.
Variable A : Type.
Fixpoint repeat (x : A) (n: nat ) :=
match n with
| O => []
| S k => x::(repeat x k)
end.
Theorem repeat_length x n:
length (repeat x n) = n.
Proof.
induction n as [| k Hrec]; simpl; rewrite ?Hrec; reflexivity.
Qed.
Theorem repeat_spec n x y:
In y (repeat x n) -> y=x.
Proof.
induction n as [|k Hrec]; simpl; destruct 1; auto.
Qed.
Lemma repeat_cons n a :
a :: repeat a n = repeat a n ++ (a :: nil).
Proof.
induction n as [|n IHn]; simpl.
- reflexivity.
- f_equal; apply IHn.
Qed.
Lemma repeat_app x n m :
repeat x (n + m) = repeat x n ++ repeat x m.
Proof.
induction n as [|n IHn]; simpl; auto.
now rewrite IHn.
Qed.
Lemma repeat_eq_app x n l1 l2 :
repeat x n = l1 ++ l2 -> repeat x (length l1) = l1 /\ repeat x (length l2) = l2.
Proof.
revert n; induction l1 as [|a l1 IHl1]; simpl; intros n Hr; subst.
- repeat split; now rewrite repeat_length.
- destruct n; inversion Hr as [ [Heq Hr0] ]; subst.
now apply IHl1 in Hr0 as [-> ->].
Qed.
Lemma repeat_eq_cons x y n l :
repeat x n = y :: l -> x = y /\ repeat x (pred n) = l.
Proof.
intros Hr.
destruct n; inversion_clear Hr; auto.
Qed.
Lemma repeat_eq_elt x y n l1 l2 :
repeat x n = l1 ++ y :: l2 -> x = y /\ repeat x (length l1) = l1 /\ repeat x (length l2) = l2.
Proof.
intros Hr; apply repeat_eq_app in Hr as [Hr1 Hr2]; subst.
apply repeat_eq_cons in Hr2; intuition.
Qed.
Lemma Forall_eq_repeat x l :
Forall (eq x) l -> l = repeat x (length l).
Proof.
induction l as [|a l IHl]; simpl; intros HF; auto.
inversion_clear HF as [ | ? ? ? HF']; subst.
now rewrite (IHl HF') at 1.
Qed.
Hypothesis decA : forall x y : A, {x = y}+{x <> y}.
Lemma count_occ_repeat_eq x y n : x = y -> count_occ decA (repeat y n) x = n.
Proof.
intros ->.
induction n; cbn; auto.
destruct (decA y y); auto.
exfalso; intuition.
Qed.
Lemma count_occ_repeat_neq x y n : x <> y -> count_occ decA (repeat y n) x = 0.
Proof.
intros Hneq.
induction n; cbn; auto.
destruct (decA y x); auto.
exfalso; intuition.
Qed.
Lemma count_occ_unique x l : count_occ decA l x = length l -> l = repeat x (length l).
Proof.
induction l as [|h l]; cbn; intros Hocc; auto.
destruct (decA h x).
- f_equal; intuition.
- assert (Hb := count_occ_bound decA x l).
rewrite Hocc in Hb.
exfalso; apply (Nat.nle_succ_diag_l _ Hb).
Qed.
Lemma count_occ_repeat_excl x l :
(forall y, y <> x -> count_occ decA l y = 0) -> l = repeat x (length l).
Proof.
intros Hocc.
apply Forall_eq_repeat, Forall_forall; intros z Hin.
destruct (decA z x) as [Heq|Hneq]; auto.
apply Hocc, count_occ_not_In in Hneq; intuition.
Qed.
Lemma count_occ_sgt l x : l = x :: nil <->
count_occ decA l x = 1 /\ forall y, y <> x -> count_occ decA l y = 0.
Proof.
split.
- intros ->; cbn; split; intros; destruct decA; subst; intuition.
- intros [Heq Hneq].
apply count_occ_repeat_excl in Hneq.
rewrite Hneq, count_occ_repeat_eq in Heq; trivial.
now rewrite Heq in Hneq.
Qed.
Lemma nth_repeat a m n :
nth n (repeat a m) a = a.
Proof.
revert n. induction m as [|m IHm].
- now intros [|n].
- intros [|n]; [reflexivity|exact (IHm n)].
Qed.
Lemma nth_error_repeat a m n :
n < m -> nth_error (repeat a m) n = Some a.
Proof.
intro Hnm. rewrite (nth_error_nth' _ a).
- now rewrite nth_repeat.
- now rewrite repeat_length.
Qed.
End Repeat.
Lemma repeat_to_concat A n (a:A) :
repeat a n = concat (repeat [a] n).
Proof.
induction n as [|n IHn]; simpl.
- reflexivity.
- f_equal; apply IHn.
Qed.
(** Sum of elements of a list of [nat]: [list_sum] *)
Definition list_sum l := fold_right plus 0 l.
Lemma list_sum_app : forall l1 l2,
list_sum (l1 ++ l2) = list_sum l1 + list_sum l2.
Proof.
intro l1; induction l1 as [|a l1 IHl1]; intros l2; [ reflexivity | ].
simpl; rewrite IHl1.
apply Nat.add_assoc.
Qed.
(** Max of elements of a list of [nat]: [list_max] *)
Definition list_max l := fold_right max 0 l.
Lemma list_max_app : forall l1 l2,
list_max (l1 ++ l2) = max (list_max l1) (list_max l2).
Proof.
intro l1; induction l1 as [|a l1 IHl1]; intros l2; [ reflexivity | ].
now simpl; rewrite IHl1, Nat.max_assoc.
Qed.
Lemma list_max_le : forall l n,
list_max l <= n <-> Forall (fun k => k <= n) l.
Proof.
intro l; induction l as [|a l IHl]; simpl; intros n; split.
- now intros.
- intros. now apply Nat.le_0_l.
- intros [? ?] %Nat.max_lub_iff. now constructor; [|apply IHl].
- now rewrite Forall_cons_iff, <- IHl, Nat.max_lub_iff.
Qed.
Lemma list_max_lt : forall l n, l <> nil ->
list_max l < n <-> Forall (fun k => k < n) l.
Proof.
intro l; induction l as [|a l IHl]; simpl; intros n Hnil; split; intros H; intuition.
- destruct l.
+ repeat constructor.
now simpl in H; rewrite Nat.max_0_r in H.
+ apply Nat.max_lub_lt_iff in H.
now constructor; [ | apply IHl ].
- destruct l; inversion_clear H as [ | ? ? Hlt HF ].
+ now simpl; rewrite Nat.max_0_r.
+ apply IHl in HF.
* now apply Nat.max_lub_lt_iff.
* intros Heq; inversion Heq.
Qed.
(** * Inversion of predicates over lists based on head symbol *)
Ltac is_list_constr c :=
match c with
| nil => idtac
| (_::_) => idtac
| _ => fail
end.
Ltac invlist f :=
match goal with
| H:f ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| H:f _ _ _ _ ?l |- _ => is_list_constr l; inversion_clear H; invlist f
| _ => idtac
end.
(** * Exporting hints and tactics *)
Global Hint Rewrite
rev_involutive (* rev (rev l) = l *)
rev_unit (* rev (l ++ a :: nil) = a :: rev l *)
map_nth (* nth n (map f l) (f d) = f (nth n l d) *)
map_length (* length (map f l) = length l *)
seq_length (* length (seq start len) = len *)
app_length (* length (l ++ l') = length l + length l' *)
rev_length (* length (rev l) = length l *)
app_nil_r (* l ++ nil = l *)
: list.
Ltac simpl_list := autorewrite with list.
Ltac ssimpl_list := autorewrite with list using simpl.
(* begin hide *)
(* Compatibility notations after the migration of [list] to [Datatypes] *)
Notation list := list (only parsing).
Notation list_rect := list_rect (only parsing).
Notation list_rec := list_rec (only parsing).
Notation list_ind := list_ind (only parsing).
Notation nil := nil (only parsing).
Notation cons := cons (only parsing).
Notation length := length (only parsing).
Notation app := app (only parsing).
(* Compatibility Names *)
Notation tail := tl (only parsing).
Notation head := hd_error (only parsing).
Notation head_nil := hd_error_nil (only parsing).
Notation head_cons := hd_error_cons (only parsing).
Notation ass_app := app_assoc (only parsing).
Notation app_ass := app_assoc_reverse (only parsing).
Notation In_split := in_split (only parsing).
Notation In_rev := in_rev (only parsing).
Notation In_dec := in_dec (only parsing).
Notation distr_rev := rev_app_distr (only parsing).
Notation rev_acc := rev_append (only parsing).
Notation rev_acc_rev := rev_append_rev (only parsing).
Notation AllS := Forall (only parsing). (* was formerly in TheoryList *)
#[global]
Hint Resolve app_nil_end : datatypes.
(* end hide *)
(* Unset Universe Polymorphism. *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND3B_1_V
`define SKY130_FD_SC_LS__AND3B_1_V
/**
* and3b: 3-input AND, first input inverted.
*
* Verilog wrapper for and3b with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__and3b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_1 (
X ,
A_N ,
B ,
C ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__and3b_1 (
X ,
A_N,
B ,
C
);
output X ;
input A_N;
input B ;
input C ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__and3b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND3B_1_V
|
`timescale 1 ps / 1 ps
(* CORE_GENERATION_INFO = "zynq_1,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLanguage=VERILOG,numBlks=2,numReposBlks=2,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,da_axi4_cnt=1}" *)
module zynq_1
(DDR_addr,
DDR_ba,
DDR_cas_n,
DDR_ck_n,
DDR_ck_p,
DDR_cke,
DDR_cs_n,
DDR_dm,
DDR_dq,
DDR_dqs_n,
DDR_dqs_p,
DDR_odt,
DDR_ras_n,
DDR_reset_n,
DDR_we_n,
FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp,
FIXED_IO_mio,
FIXED_IO_ps_clk,
FIXED_IO_ps_porb,
FIXED_IO_ps_srstb);
inout [14:0]DDR_addr;
inout [2:0]DDR_ba;
inout DDR_cas_n;
inout DDR_ck_n;
inout DDR_ck_p;
inout DDR_cke;
inout DDR_cs_n;
inout [3:0]DDR_dm;
inout [31:0]DDR_dq;
inout [3:0]DDR_dqs_n;
inout [3:0]DDR_dqs_p;
inout DDR_odt;
inout DDR_ras_n;
inout DDR_reset_n;
inout DDR_we_n;
inout FIXED_IO_ddr_vrn;
inout FIXED_IO_ddr_vrp;
inout [53:0]FIXED_IO_mio;
inout FIXED_IO_ps_clk;
inout FIXED_IO_ps_porb;
inout FIXED_IO_ps_srstb;
wire GND_1;
wire VCC_1;
wire [14:0]processing_system7_1_ddr_ADDR;
wire [2:0]processing_system7_1_ddr_BA;
wire processing_system7_1_ddr_CAS_N;
wire processing_system7_1_ddr_CKE;
wire processing_system7_1_ddr_CK_N;
wire processing_system7_1_ddr_CK_P;
wire processing_system7_1_ddr_CS_N;
wire [3:0]processing_system7_1_ddr_DM;
wire [31:0]processing_system7_1_ddr_DQ;
wire [3:0]processing_system7_1_ddr_DQS_N;
wire [3:0]processing_system7_1_ddr_DQS_P;
wire processing_system7_1_ddr_ODT;
wire processing_system7_1_ddr_RAS_N;
wire processing_system7_1_ddr_RESET_N;
wire processing_system7_1_ddr_WE_N;
wire processing_system7_1_fclk_clk0;
wire processing_system7_1_fclk_reset0_n;
wire processing_system7_1_fixed_io_DDR_VRN;
wire processing_system7_1_fixed_io_DDR_VRP;
wire [53:0]processing_system7_1_fixed_io_MIO;
wire processing_system7_1_fixed_io_PS_CLK;
wire processing_system7_1_fixed_io_PS_PORB;
wire processing_system7_1_fixed_io_PS_SRSTB;
GND GND
(.G(GND_1));
VCC VCC
(.P(VCC_1));
zynq_1_proc_sys_reset_1_0 proc_sys_reset_1
(.aux_reset_in(VCC_1),
.dcm_locked(VCC_1),
.ext_reset_in(processing_system7_1_fclk_reset0_n),
.mb_debug_sys_rst(GND_1),
.slowest_sync_clk(processing_system7_1_fclk_clk0));
zynq_1_processing_system7_1_0 processing_system7_1
(.DDR_Addr(DDR_addr[14:0]),
.DDR_BankAddr(DDR_ba[2:0]),
.DDR_CAS_n(DDR_cas_n),
.DDR_CKE(DDR_cke),
.DDR_CS_n(DDR_cs_n),
.DDR_Clk(DDR_ck_p),
.DDR_Clk_n(DDR_ck_n),
.DDR_DM(DDR_dm[3:0]),
.DDR_DQ(DDR_dq[31:0]),
.DDR_DQS(DDR_dqs_p[3:0]),
.DDR_DQS_n(DDR_dqs_n[3:0]),
.DDR_DRSTB(DDR_reset_n),
.DDR_ODT(DDR_odt),
.DDR_RAS_n(DDR_ras_n),
.DDR_VRN(FIXED_IO_ddr_vrn),
.DDR_VRP(FIXED_IO_ddr_vrp),
.DDR_WEB(DDR_we_n),
.FCLK_CLK0(processing_system7_1_fclk_clk0),
.FCLK_RESET0_N(processing_system7_1_fclk_reset0_n),
.MIO(FIXED_IO_mio[53:0]),
.M_AXI_GP0_ACLK(processing_system7_1_fclk_clk0),
.M_AXI_GP0_ARREADY(GND_1),
.M_AXI_GP0_AWREADY(GND_1),
.M_AXI_GP0_BID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.M_AXI_GP0_BRESP({GND_1,GND_1}),
.M_AXI_GP0_BVALID(GND_1),
.M_AXI_GP0_RDATA({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.M_AXI_GP0_RID({GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1,GND_1}),
.M_AXI_GP0_RLAST(GND_1),
.M_AXI_GP0_RRESP({GND_1,GND_1}),
.M_AXI_GP0_RVALID(GND_1),
.M_AXI_GP0_WREADY(GND_1),
.PS_CLK(FIXED_IO_ps_clk),
.PS_PORB(FIXED_IO_ps_porb),
.PS_SRSTB(FIXED_IO_ps_srstb),
.TTC0_CLK0_IN(processing_system7_1_fclk_clk0),
.TTC0_CLK1_IN(processing_system7_1_fclk_clk0),
.TTC0_CLK2_IN(processing_system7_1_fclk_clk0));
endmodule
|
// MBT 9/3/2016
//
// note: this does a reduction
//
`define bsg_andr_macro(bits) \
if (harden_p && (width_p<=bits)) \
begin: macro \
wire [bits-1:0] widen = bits ' (i); \
bsg_rp_tsmc_40_reduce_and_b``bits andr(.i(widen),.o); \
end
module bsg_reduce #(parameter `BSG_INV_PARAM(width_p )
, parameter xor_p = 0
, parameter and_p = 0
, parameter or_p = 0
, parameter harden_p = 0
)
(input [width_p-1:0] i
, output o
);
// synopsys translate_off
initial
assert( $countones({xor_p & 1'b1, and_p & 1'b1, or_p & 1'b1}) == 1)
else $error("bsg_scan: only one function may be selected\n");
// synopsys translate_on
if (xor_p)
begin: xorr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = ^i;
end:xorr
else if (and_p)
begin: andr
if (width_p < 4)
begin: notmacro
assign o = &i;
end else
`bsg_andr_macro(4) else
`bsg_andr_macro(6) else
`bsg_andr_macro(8) else
`bsg_andr_macro(9) else
`bsg_andr_macro(12) else
`bsg_andr_macro(16) else
begin: notmacro
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = &i;
end
end
else if (or_p)
begin: orr
initial assert(harden_p==0) else $error("## %m unhandled bitstack case");
assign o = |i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_reduce)
|
///////////////////////////////////////////////////////
// Copyright (c) 2009 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 12.1
// \ \ Description :
// / /
// /__/ /\ Filename : BUFMR.v
// \ \ / \
// \__\/\__ \
//
// Revision: 1.0
// 05/24/12 - 661573 - Remove 100 ps delay
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module BUFMR (
O,
I
);
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
reg notifier;
`endif
output O;
input I;
buf B1 (O, I);
specify
( I => O) = (0:0:0, 0:0:0);
`ifdef XIL_TIMING
$period (posedge I, 0:0:0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// ==================================================================
// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<
// ------------------------------------------------------------------
// Copyright (c) 2006-2011 by Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// ------------------------------------------------------------------
//
// IMPORTANT: THIS FILE IS AUTO-GENERATED BY THE LATTICEMICO SYSTEM.
//
// Permission:
//
// Lattice Semiconductor grants permission to use this code
// pursuant to the terms of the Lattice Semiconductor Corporation
// Open Source License Agreement.
//
// Disclaimer:
//
// Lattice Semiconductor provides no warranty regarding the use or
// functionality of this code. It is the user's responsibility to
// verify the users design for consistency and functionality through
// the use of formal verification methods.
//
// --------------------------------------------------------------------
//
// Lattice Semiconductor Corporation
// 5555 NE Moore Court
// Hillsboro, OR 97214
// U.S.A
//
// TEL: 1-800-Lattice (USA and Canada)
// 503-286-8001 (other locations)
//
// web: http://www.latticesemi.com/
// email: [email protected]
//
// --------------------------------------------------------------------
// FILE DETAILS
// Project : LatticeMico32
// File : lm32_top.v
// Title : Top-level of CPU.
// Dependencies : lm32_include.v
// Version : 6.1.17
// : removed SPI - 04/12/07
// Version : 7.0SP2, 3.0
// : No Change
// Version : 3.1
// : No Change
// Version : 3.9
// : Support added for 'Fast Download' register in Debugger
// =============================================================================
`include "lm32_include.v"
/////////////////////////////////////////////////////
// Module interface
/////////////////////////////////////////////////////
module lm32_top (
// ----- Inputs -------
clk_i,
rst_i,
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
at_debug,
`endif
`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
interrupt_n,
`endif
// From user logic
`ifdef CFG_USER_ENABLED
user_result,
user_complete,
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_I,
I_ACK_I,
I_ERR_I,
I_RTY_I,
`endif
// Data Wishbone master
D_DAT_I,
D_ACK_I,
D_ERR_I,
D_RTY_I,
// Debug Slave port WishboneInterface
DEBUG_ADR_I,
DEBUG_DAT_I,
DEBUG_SEL_I,
DEBUG_WE_I,
DEBUG_CTI_I,
DEBUG_BTE_I,
DEBUG_LOCK_I,
DEBUG_CYC_I,
DEBUG_STB_I,
// ----- Outputs -------
`ifdef CFG_USER_ENABLED
user_valid,
user_opcode,
user_operand_0,
user_operand_1,
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
I_DAT_O,
I_ADR_O,
I_CYC_O,
I_SEL_O,
I_STB_O,
I_WE_O,
I_CTI_O,
I_LOCK_O,
I_BTE_O,
`endif
// Data Wishbone master
D_DAT_O,
D_ADR_O,
D_CYC_O,
D_SEL_O,
D_STB_O,
D_WE_O,
D_CTI_O,
D_LOCK_O,
D_BTE_O,
// Debug Slave port WishboneInterface
DEBUG_ACK_O,
DEBUG_ERR_O,
DEBUG_RTY_O,
DEBUG_DAT_O
);
/////////////////////////////////////////////////////
// Inputs
/////////////////////////////////////////////////////
input clk_i; // Clock
input rst_i; // Reset
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
input at_debug; // GPIO input that maps EBA to DEBA
`endif
`endif
`ifdef CFG_INTERRUPTS_ENABLED
input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
`endif
`ifdef CFG_USER_ENABLED
input [`LM32_WORD_RNG] user_result; // User-defined instruction result
input user_complete; // Indicates the user-defined instruction result is valid
`endif
`ifdef CFG_IWB_ENABLED
input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
input I_ACK_I; // Instruction Wishbone interface acknowledgement
input I_ERR_I; // Instruction Wishbone interface error
input I_RTY_I; // Instruction Wishbone interface retry
`endif
input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
input D_ACK_I; // Data Wishbone interface acknowledgement
input D_ERR_I; // Data Wishbone interface error
input D_RTY_I; // Data Wishbone interface retry
input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address
input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data
input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select
input DEBUG_WE_I; // Debug monitor Wishbone interface write enable
input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type
input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type
input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer
input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle
input DEBUG_STB_I; // Debug monitor Wishbone interface strobe
/////////////////////////////////////////////////////
// Outputs
/////////////////////////////////////////////////////
`ifdef CFG_USER_ENABLED
output user_valid; // Indicates that user_opcode and user_operand_* are valid
wire user_valid;
output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
reg [`LM32_USER_OPCODE_RNG] user_opcode;
output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
wire [`LM32_WORD_RNG] user_operand_0;
output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
wire [`LM32_WORD_RNG] user_operand_1;
`endif
`ifdef CFG_IWB_ENABLED
output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
wire [`LM32_WORD_RNG] I_DAT_O;
output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
wire [`LM32_WORD_RNG] I_ADR_O;
output I_CYC_O; // Instruction Wishbone interface cycle
wire I_CYC_O;
output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
output I_STB_O; // Instruction Wishbone interface strobe
wire I_STB_O;
output I_WE_O; // Instruction Wishbone interface write enable
wire I_WE_O;
output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
wire [`LM32_CTYPE_RNG] I_CTI_O;
output I_LOCK_O; // Instruction Wishbone interface lock bus
wire I_LOCK_O;
output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
wire [`LM32_BTYPE_RNG] I_BTE_O;
`endif
output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
wire [`LM32_WORD_RNG] D_DAT_O;
output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
wire [`LM32_WORD_RNG] D_ADR_O;
output D_CYC_O; // Data Wishbone interface cycle
wire D_CYC_O;
output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
output D_STB_O; // Data Wishbone interface strobe
wire D_STB_O;
output D_WE_O; // Data Wishbone interface write enable
wire D_WE_O;
output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
wire [`LM32_CTYPE_RNG] D_CTI_O;
output D_LOCK_O; // Date Wishbone interface lock bus
wire D_LOCK_O;
output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
wire [`LM32_BTYPE_RNG] D_BTE_O;
output DEBUG_ACK_O; // Debug monitor Wishbone ack
wire DEBUG_ACK_O;
output DEBUG_ERR_O; // Debug monitor Wishbone error
wire DEBUG_ERR_O;
output DEBUG_RTY_O; // Debug monitor Wishbone retry
wire DEBUG_RTY_O;
output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data
wire [`LM32_WORD_RNG] DEBUG_DAT_O;
/////////////////////////////////////////////////////
// Internal nets and registers
/////////////////////////////////////////////////////
`ifdef CFG_JTAG_ENABLED
// Signals between JTAG interface and CPU
wire [`LM32_BYTE_RNG] jtag_reg_d;
`ifdef CFG_FAST_DOWNLOAD_ENABLED
wire [`DOWNLOAD_BUFFER_SIZE-1:0] jtag_reg_q;
`else
wire [7:0] jtag_reg_q;
`endif
wire jtag_update;
wire [2:0] jtag_reg_addr_d;
wire [2:0] jtag_reg_addr_q;
wire jtck;
wire jrstn;
`endif
`ifdef CFG_TRACE_ENABLED
// PC trace signals
wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
wire trace_pc_valid; // Indicates that a new trace PC is valid
wire trace_exception; // Indicates an exception has occured
wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
wire trace_eret; // Indicates an eret instruction has been executed
`ifdef CFG_DEBUG_ENABLED
wire trace_bret; // Indicates a bret instruction has been executed
`endif
`endif
/////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////
`include "lm32_functions.v"
/////////////////////////////////////////////////////
// Instantiations
/////////////////////////////////////////////////////
// LM32 CPU
lm32_cpu cpu (
// ----- Inputs -------
.clk_i (clk_i),
`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
.clk_n_i (clk_n),
`endif
.rst_i (rst_i),
`ifdef CFG_DEBUG_ENABLED
`ifdef CFG_ALTERNATE_EBA
.at_debug (at_debug),
`endif
`endif
// From external devices
`ifdef CFG_INTERRUPTS_ENABLED
.interrupt_n (interrupt_n),
`endif
// From user logic
`ifdef CFG_USER_ENABLED
.user_result (user_result),
.user_complete (user_complete),
`endif
`ifdef CFG_JTAG_ENABLED
// From JTAG
.jtag_clk (jtck),
.jtag_update (jtag_update),
.jtag_reg_q (jtag_reg_q),
.jtag_reg_addr_q (jtag_reg_addr_q),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_I (I_DAT_I),
.I_ACK_I (I_ACK_I),
.I_ERR_I (I_ERR_I),
.I_RTY_I (I_RTY_I),
`endif
// Data Wishbone master
.D_DAT_I (D_DAT_I),
.D_ACK_I (D_ACK_I),
.D_ERR_I (D_ERR_I),
.D_RTY_I (D_RTY_I),
// ----- Outputs -------
`ifdef CFG_TRACE_ENABLED
.trace_pc (trace_pc),
.trace_pc_valid (trace_pc_valid),
.trace_exception (trace_exception),
.trace_eid (trace_eid),
.trace_eret (trace_eret),
`ifdef CFG_DEBUG_ENABLED
.trace_bret (trace_bret),
`endif
`endif
`ifdef CFG_JTAG_ENABLED
.jtag_reg_d (jtag_reg_d),
.jtag_reg_addr_d (jtag_reg_addr_d),
`endif
`ifdef CFG_USER_ENABLED
.user_valid (user_valid),
.user_opcode (user_opcode),
.user_operand_0 (user_operand_0),
.user_operand_1 (user_operand_1),
`endif
`ifdef CFG_IWB_ENABLED
// Instruction Wishbone master
.I_DAT_O (I_DAT_O),
.I_ADR_O (I_ADR_O),
.I_CYC_O (I_CYC_O),
.I_SEL_O (I_SEL_O),
.I_STB_O (I_STB_O),
.I_WE_O (I_WE_O),
.I_CTI_O (I_CTI_O),
.I_LOCK_O (I_LOCK_O),
.I_BTE_O (I_BTE_O),
`endif
// Data Wishbone master
.D_DAT_O (D_DAT_O),
.D_ADR_O (D_ADR_O),
.D_CYC_O (D_CYC_O),
.D_SEL_O (D_SEL_O),
.D_STB_O (D_STB_O),
.D_WE_O (D_WE_O),
.D_CTI_O (D_CTI_O),
.D_LOCK_O (D_LOCK_O),
.D_BTE_O (D_BTE_O)
);
wire TRACE_ACK_O;
wire [`LM32_WORD_RNG] TRACE_DAT_O;
`ifdef CFG_TRACE_ENABLED
lm32_trace trace_module (.clk_i (clk_i),
.rst_i (rst_i),
.stb_i (DEBUG_STB_I & DEBUG_ADR_I[13]),
.we_i (DEBUG_WE_I),
.sel_i (DEBUG_SEL_I),
.dat_i (DEBUG_DAT_I),
.adr_i (DEBUG_ADR_I),
.trace_pc (trace_pc),
.trace_eid (trace_eid),
.trace_eret (trace_eret),
.trace_bret (trace_bret),
.trace_pc_valid (trace_pc_valid),
.trace_exception (trace_exception),
.ack_o (TRACE_ACK_O),
.dat_o (TRACE_DAT_O));
`else
assign TRACE_ACK_O = 0;
assign TRACE_DAT_O = 0;
`endif
`ifdef DEBUG_ROM
wire ROM_ACK_O;
wire [`LM32_WORD_RNG] ROM_DAT_O;
assign DEBUG_ACK_O = DEBUG_ADR_I[13] ? TRACE_ACK_O : ROM_ACK_O;
assign DEBUG_DAT_O = DEBUG_ADR_I[13] ? TRACE_DAT_O : ROM_DAT_O;
// ROM monitor
lm32_monitor debug_rom (
// ----- Inputs -------
.clk_i (clk_i),
.rst_i (rst_i),
.MON_ADR_I (DEBUG_ADR_I[10:2]),
.MON_STB_I (DEBUG_STB_I & ~DEBUG_ADR_I[13]),
.MON_CYC_I (DEBUG_CYC_I & ~DEBUG_ADR_I[13]),
.MON_WE_I (DEBUG_WE_I),
.MON_SEL_I (DEBUG_SEL_I),
.MON_DAT_I (DEBUG_DAT_I),
// ----- Outputs ------
.MON_RTY_O (DEBUG_RTY_O),
.MON_ERR_O (DEBUG_ERR_O),
.MON_ACK_O (ROM_ACK_O),
.MON_DAT_O (ROM_DAT_O)
);
`endif
`ifdef CFG_JTAG_ENABLED
// JTAG cores
jtag_cores jtag_cores (
// ----- Inputs -----
`ifdef INCLUDE_LM32
.reg_d (jtag_reg_d),
.reg_addr_d (jtag_reg_addr_d),
`endif
// ----- Outputs -----
`ifdef INCLUDE_LM32
.reg_update (jtag_update),
.reg_q (jtag_reg_q),
.reg_addr_q (jtag_reg_addr_q),
`endif
.jtck (jtck),
.jrstn (jrstn)
);
`endif
endmodule
|
module voice(clk, gate, note, pitch, detune, mix, wave_form, signal_out, ss1, ss2, ss3, ss4, ss5, ss6, ss7);
input wire clk;
input wire gate;
input wire [6:0] note;
input wire [6:0] detune;
input wire [6:0] mix;
input wire [13:0] pitch;
output wire [7:0] signal_out;
//input wire [31:0] adder;
input wire [2:0] wave_form;
output wire [7:0] ss1, ss2, ss3, ss4, ss5, ss6, ss7;
// wave_forms
parameter SAW = 3'b000;
parameter SQUARE = 3'b001; //with PWM
parameter TRIANGLE = 3'b010;
parameter SINE = 3'b011;
parameter RAMP = 3'b100;
parameter SAW_TRI = 3'b101;
parameter SUPERSAW = 3'b110;
parameter NOISE = 3'b111;
reg [1:0] gate_prev;
initial gate_prev<=2'b00;
always @(posedge clk) gate_prev <= {gate_prev[0], gate};
wire TRIG = (gate_prev==2'b01);
wire [31:0] adder_center;
note_pitch2dds transl1(clk, note, pitch, adder_center);
wire [31:0] vco_out;
dds #(.WIDTH(32)) vco(.clk(clk), .adder(adder_center), .signal_out(vco_out));
wire [31:0] vco_out1;
wire [31:0] vco_out2;
wire [31:0] vco_out3;
wire [31:0] vco_out4;
wire [31:0] vco_out5;
wire [31:0] vco_out6;
wire [31:0] adder_vco1 = adder_center - ((adder_center*((16'd07210*detune)>>8))>>16);
wire [31:0] adder_vco2 = adder_center - ((adder_center*((16'd04121*detune)>>8))>>16);
wire [31:0] adder_vco3 = adder_center - ((adder_center*((16'd01279*detune)>>8))>>16);
wire [31:0] adder_vco4 = adder_center + ((adder_center*((16'd01304*detune)>>8))>>16);
wire [31:0] adder_vco5 = adder_center + ((adder_center*((16'd04074*detune)>>8))>>16);
wire [31:0] adder_vco6 = adder_center + ((adder_center*((16'd07042*detune)>>8))>>16);
dds #(.WIDTH(32)) vco1(.clk(clk), .adder(adder_vco1), .signal_out(vco_out1));
dds #(.WIDTH(32)) vco2(.clk(clk), .adder(adder_vco2), .signal_out(vco_out2));
dds #(.WIDTH(32)) vco3(.clk(clk), .adder(adder_vco3), .signal_out(vco_out3));
dds #(.WIDTH(32)) vco4(.clk(clk), .adder(adder_vco4), .signal_out(vco_out4));
dds #(.WIDTH(32)) vco5(.clk(clk), .adder(adder_vco5), .signal_out(vco_out5));
dds #(.WIDTH(32)) vco6(.clk(clk), .adder(adder_vco6), .signal_out(vco_out6));
wire [7:0] saw_out = vco_out[31:31-7];
wire [7:0] square_out = (vco_out[31:31-7] > 127) ? 8'b11111111 : 1'b00000000;
wire [7:0] tri_out = (saw_out>8'd191) ? 7'd127 + ((saw_out << 1) - 9'd511) :
(saw_out>8'd063) ? 8'd255 - ((saw_out << 1) - 7'd127) : 7'd127 + (saw_out << 1);
//SINE table
wire [7:0] sine_out;
sine sine_rom(.address(vco_out[31:31-7]),
.q(sine_out),
.clock(clk));
wire [7:0] ramp_out = -saw_out;
wire [7:0] saw_tri_out = (saw_out > 7'd127) ? -saw_out : 8'd127 + saw_out;
//supersaw table
wire [7:0] supersaw_out;
reg [10:0] phase1;
reg [10:0] phase2;
reg [10:0] phase3;
reg [10:0] phase4;
reg [10:0] phase5;
reg [10:0] phase6;
reg [10:0] phase7;
initial begin
phase1 <= 11'd0412;
phase2 <= 11'd0222;
phase3 <= 11'd056;
phase4 <= 11'd1412;
phase5 <= 11'd2412;
phase6 <= 11'd0412;
phase7 <= 11'd22;
end
wire [7:0] rnd_ph_shift1;
wire [7:0] rnd_ph_shift2;
wire [7:0] rnd_ph_shift3;
wire [7:0] rnd_ph_shift4;
wire [7:0] rnd_ph_shift5;
wire [7:0] rnd_ph_shift6;
wire [7:0] rnd_ph_shift7;
rndx #(.WIDTH(8), .INIT_VAL(32'hF1928374)) random8_ss1(.clk(clk), .signal_out(rnd_ph_shift1));
rndx #(.WIDTH(8), .INIT_VAL(32'hF1234567)) random8_ss2(.clk(clk), .signal_out(rnd_ph_shift2));
rndx #(.WIDTH(8), .INIT_VAL(32'hF2345678)) random8_ss3(.clk(clk), .signal_out(rnd_ph_shift3));
rndx #(.WIDTH(8), .INIT_VAL(32'hF3456789)) random8_ss4(.clk(clk), .signal_out(rnd_ph_shift4));
rndx #(.WIDTH(8), .INIT_VAL(32'hF4567891)) random8_ss5(.clk(clk), .signal_out(rnd_ph_shift5));
rndx #(.WIDTH(8), .INIT_VAL(32'hF5678911)) random8_ss6(.clk(clk), .signal_out(rnd_ph_shift6));
rndx #(.WIDTH(8), .INIT_VAL(32'hF6789112)) random8_ss7(.clk(clk), .signal_out(rnd_ph_shift7));
rndx #(.WIDTH(8), .INIT_VAL(32'hF7891986)) random8_ss8(.clk(clk), .signal_out(rnd_ph_shift8));
always @(posedge clk) begin
if (TRIG) begin
phase1 <= phase1 + rnd_ph_shift1;
phase2 <= phase2 + rnd_ph_shift2;
phase3 <= phase3 + rnd_ph_shift3;
phase4 <= phase4 + rnd_ph_shift4;
phase5 <= phase5 + rnd_ph_shift5;
phase6 <= phase6 + rnd_ph_shift6;
phase7 <= phase7 + rnd_ph_shift7;
end
end
wire [10:0] supersaw_rom_addr1 = vco_out1[31:31-10] + phase1;
wire [10:0] supersaw_rom_addr2 = vco_out2[31:31-10] + phase2;
wire [10:0] supersaw_rom_addr3 = vco_out3[31:31-10] + phase3;
wire [10:0] supersaw_rom_addr4 = vco_out[31:31-10] + phase4;
wire [10:0] supersaw_rom_addr5 = vco_out4[31:31-10] + phase5;
wire [10:0] supersaw_rom_addr6 = vco_out5[31:31-10] + phase6;
wire [10:0] supersaw_rom_addr7 = vco_out6[31:31-10] + phase7;
wire [7:0] supersaw_out1;
wire [7:0] supersaw_out2;
wire [7:0] supersaw_out3;
wire [7:0] supersaw_out4;
wire [7:0] supersaw_out5;
wire [7:0] supersaw_out6;
wire [7:0] supersaw_out7;
supersaw supersaw_rom1(.address(supersaw_rom_addr1),
.q(supersaw_out1),
.clock(clk));
supersaw supersaw_rom2(.address(supersaw_rom_addr2),
.q(supersaw_out2),
.clock(clk));
supersaw supersaw_rom3(.address(supersaw_rom_addr3),
.q(supersaw_out3),
.clock(clk));
supersaw supersaw_rom4(.address(supersaw_rom_addr4),
.q(supersaw_out4),
.clock(clk));
supersaw supersaw_rom5(.address(supersaw_rom_addr5),
.q(supersaw_out5),
.clock(clk));
supersaw supersaw_rom6(.address(supersaw_rom_addr6),
.q(supersaw_out6),
.clock(clk));
supersaw supersaw_rom7(.address(supersaw_rom_addr7),
.q(supersaw_out7),
.clock(clk));
wire [7:0] center_volume = (mix==7'd00) ? 8'd0254 :
(mix==7'd01) ? 8'd0253 :
(mix==7'd02) ? 8'd0252 :
(mix==7'd03) ? 8'd0251 :
(mix==7'd04) ? 8'd0250 :
(mix==7'd05) ? 8'd0249 :
(mix==7'd06) ? 8'd0248 :
(mix==7'd07) ? 8'd0247 :
(mix==7'd08) ? 8'd0246 :
(mix==7'd09) ? 8'd0244 :
(mix==7'd010) ? 8'd0243 :
(mix==7'd011) ? 8'd0242 :
(mix==7'd012) ? 8'd0241 :
(mix==7'd013) ? 8'd0240 :
(mix==7'd014) ? 8'd0239 :
(mix==7'd015) ? 8'd0238 :
(mix==7'd016) ? 8'd0237 :
(mix==7'd017) ? 8'd0236 :
(mix==7'd018) ? 8'd0234 :
(mix==7'd019) ? 8'd0233 :
(mix==7'd020) ? 8'd0232 :
(mix==7'd021) ? 8'd0231 :
(mix==7'd022) ? 8'd0230 :
(mix==7'd023) ? 8'd0229 :
(mix==7'd024) ? 8'd0228 :
(mix==7'd025) ? 8'd0227 :
(mix==7'd026) ? 8'd0226 :
(mix==7'd027) ? 8'd0224 :
(mix==7'd028) ? 8'd0223 :
(mix==7'd029) ? 8'd0222 :
(mix==7'd030) ? 8'd0221 :
(mix==7'd031) ? 8'd0220 :
(mix==7'd032) ? 8'd0219 :
(mix==7'd033) ? 8'd0218 :
(mix==7'd034) ? 8'd0217 :
(mix==7'd035) ? 8'd0216 :
(mix==7'd036) ? 8'd0214 :
(mix==7'd037) ? 8'd0213 :
(mix==7'd038) ? 8'd0212 :
(mix==7'd039) ? 8'd0211 :
(mix==7'd040) ? 8'd0210 :
(mix==7'd041) ? 8'd0209 :
(mix==7'd042) ? 8'd0208 :
(mix==7'd043) ? 8'd0207 :
(mix==7'd044) ? 8'd0206 :
(mix==7'd045) ? 8'd0204 :
(mix==7'd046) ? 8'd0203 :
(mix==7'd047) ? 8'd0202 :
(mix==7'd048) ? 8'd0201 :
(mix==7'd049) ? 8'd0200 :
(mix==7'd050) ? 8'd0199 :
(mix==7'd051) ? 8'd0198 :
(mix==7'd052) ? 8'd0197 :
(mix==7'd053) ? 8'd0196 :
(mix==7'd054) ? 8'd0194 :
(mix==7'd055) ? 8'd0193 :
(mix==7'd056) ? 8'd0192 :
(mix==7'd057) ? 8'd0191 :
(mix==7'd058) ? 8'd0190 :
(mix==7'd059) ? 8'd0189 :
(mix==7'd060) ? 8'd0188 :
(mix==7'd061) ? 8'd0187 :
(mix==7'd062) ? 8'd0186 :
(mix==7'd063) ? 8'd0184 :
(mix==7'd064) ? 8'd0183 :
(mix==7'd065) ? 8'd0182 :
(mix==7'd066) ? 8'd0181 :
(mix==7'd067) ? 8'd0180 :
(mix==7'd068) ? 8'd0179 :
(mix==7'd069) ? 8'd0178 :
(mix==7'd070) ? 8'd0177 :
(mix==7'd071) ? 8'd0176 :
(mix==7'd072) ? 8'd0174 :
(mix==7'd073) ? 8'd0173 :
(mix==7'd074) ? 8'd0172 :
(mix==7'd075) ? 8'd0171 :
(mix==7'd076) ? 8'd0170 :
(mix==7'd077) ? 8'd0169 :
(mix==7'd078) ? 8'd0168 :
(mix==7'd079) ? 8'd0167 :
(mix==7'd080) ? 8'd0166 :
(mix==7'd081) ? 8'd0164 :
(mix==7'd082) ? 8'd0163 :
(mix==7'd083) ? 8'd0162 :
(mix==7'd084) ? 8'd0161 :
(mix==7'd085) ? 8'd0160 :
(mix==7'd086) ? 8'd0159 :
(mix==7'd087) ? 8'd0158 :
(mix==7'd088) ? 8'd0157 :
(mix==7'd089) ? 8'd0156 :
(mix==7'd090) ? 8'd0154 :
(mix==7'd091) ? 8'd0153 :
(mix==7'd092) ? 8'd0152 :
(mix==7'd093) ? 8'd0151 :
(mix==7'd094) ? 8'd0150 :
(mix==7'd095) ? 8'd0149 :
(mix==7'd096) ? 8'd0148 :
(mix==7'd097) ? 8'd0147 :
(mix==7'd098) ? 8'd0146 :
(mix==7'd099) ? 8'd0144 :
(mix==7'd0100) ? 8'd0143 :
(mix==7'd0101) ? 8'd0142 :
(mix==7'd0102) ? 8'd0141 :
(mix==7'd0103) ? 8'd0140 :
(mix==7'd0104) ? 8'd0139 :
(mix==7'd0105) ? 8'd0138 :
(mix==7'd0106) ? 8'd0137 :
(mix==7'd0107) ? 8'd0136 :
(mix==7'd0108) ? 8'd0134 :
(mix==7'd0109) ? 8'd0133 :
(mix==7'd0110) ? 8'd0132 :
(mix==7'd0111) ? 8'd0131 :
(mix==7'd0112) ? 8'd0130 :
(mix==7'd0113) ? 8'd0129 :
(mix==7'd0114) ? 8'd0128 :
(mix==7'd0115) ? 8'd0127 :
(mix==7'd0116) ? 8'd0125 :
(mix==7'd0117) ? 8'd0124 :
(mix==7'd0118) ? 8'd0123 :
(mix==7'd0119) ? 8'd0122 :
(mix==7'd0120) ? 8'd0121 :
(mix==7'd0121) ? 8'd0120 :
(mix==7'd0122) ? 8'd0119 :
(mix==7'd0123) ? 8'd0118 :
(mix==7'd0124) ? 8'd0117 :
(mix==7'd0125) ? 8'd0115 :
(mix==7'd0126) ? 8'd0114 :
(mix==7'd0127) ? 8'd0113 : 8'd0255 ;
wire [7:0] side_volume = (mix==7'd00) ? 8'd011 :
(mix==7'd01) ? 8'd014 :
(mix==7'd02) ? 8'd016 :
(mix==7'd03) ? 8'd019 :
(mix==7'd04) ? 8'd021 :
(mix==7'd05) ? 8'd024 :
(mix==7'd06) ? 8'd026 :
(mix==7'd07) ? 8'd029 :
(mix==7'd08) ? 8'd031 :
(mix==7'd09) ? 8'd034 :
(mix==7'd010) ? 8'd036 :
(mix==7'd011) ? 8'd038 :
(mix==7'd012) ? 8'd041 :
(mix==7'd013) ? 8'd043 :
(mix==7'd014) ? 8'd045 :
(mix==7'd015) ? 8'd047 :
(mix==7'd016) ? 8'd050 :
(mix==7'd017) ? 8'd052 :
(mix==7'd018) ? 8'd054 :
(mix==7'd019) ? 8'd056 :
(mix==7'd020) ? 8'd058 :
(mix==7'd021) ? 8'd060 :
(mix==7'd022) ? 8'd062 :
(mix==7'd023) ? 8'd064 :
(mix==7'd024) ? 8'd066 :
(mix==7'd025) ? 8'd068 :
(mix==7'd026) ? 8'd070 :
(mix==7'd027) ? 8'd072 :
(mix==7'd028) ? 8'd074 :
(mix==7'd029) ? 8'd076 :
(mix==7'd030) ? 8'd078 :
(mix==7'd031) ? 8'd080 :
(mix==7'd032) ? 8'd082 :
(mix==7'd033) ? 8'd084 :
(mix==7'd034) ? 8'd085 :
(mix==7'd035) ? 8'd087 :
(mix==7'd036) ? 8'd089 :
(mix==7'd037) ? 8'd091 :
(mix==7'd038) ? 8'd092 :
(mix==7'd039) ? 8'd094 :
(mix==7'd040) ? 8'd096 :
(mix==7'd041) ? 8'd097 :
(mix==7'd042) ? 8'd099 :
(mix==7'd043) ? 8'd0101 :
(mix==7'd044) ? 8'd0102 :
(mix==7'd045) ? 8'd0104 :
(mix==7'd046) ? 8'd0105 :
(mix==7'd047) ? 8'd0107 :
(mix==7'd048) ? 8'd0108 :
(mix==7'd049) ? 8'd0110 :
(mix==7'd050) ? 8'd0111 :
(mix==7'd051) ? 8'd0112 :
(mix==7'd052) ? 8'd0114 :
(mix==7'd053) ? 8'd0115 :
(mix==7'd054) ? 8'd0117 :
(mix==7'd055) ? 8'd0118 :
(mix==7'd056) ? 8'd0119 :
(mix==7'd057) ? 8'd0120 :
(mix==7'd058) ? 8'd0122 :
(mix==7'd059) ? 8'd0123 :
(mix==7'd060) ? 8'd0124 :
(mix==7'd061) ? 8'd0125 :
(mix==7'd062) ? 8'd0126 :
(mix==7'd063) ? 8'd0127 :
(mix==7'd064) ? 8'd0129 :
(mix==7'd065) ? 8'd0130 :
(mix==7'd066) ? 8'd0131 :
(mix==7'd067) ? 8'd0132 :
(mix==7'd068) ? 8'd0133 :
(mix==7'd069) ? 8'd0134 :
(mix==7'd070) ? 8'd0135 :
(mix==7'd071) ? 8'd0136 :
(mix==7'd072) ? 8'd0136 :
(mix==7'd073) ? 8'd0137 :
(mix==7'd074) ? 8'd0138 :
(mix==7'd075) ? 8'd0139 :
(mix==7'd076) ? 8'd0140 :
(mix==7'd077) ? 8'd0141 :
(mix==7'd078) ? 8'd0141 :
(mix==7'd079) ? 8'd0142 :
(mix==7'd080) ? 8'd0143 :
(mix==7'd081) ? 8'd0144 :
(mix==7'd082) ? 8'd0144 :
(mix==7'd083) ? 8'd0145 :
(mix==7'd084) ? 8'd0146 :
(mix==7'd085) ? 8'd0146 :
(mix==7'd086) ? 8'd0147 :
(mix==7'd087) ? 8'd0147 :
(mix==7'd088) ? 8'd0148 :
(mix==7'd089) ? 8'd0148 :
(mix==7'd090) ? 8'd0149 :
(mix==7'd091) ? 8'd0149 :
(mix==7'd092) ? 8'd0150 :
(mix==7'd093) ? 8'd0150 :
(mix==7'd094) ? 8'd0151 :
(mix==7'd095) ? 8'd0151 :
(mix==7'd096) ? 8'd0151 :
(mix==7'd097) ? 8'd0152 :
(mix==7'd098) ? 8'd0152 :
(mix==7'd099) ? 8'd0152 :
(mix==7'd0100) ? 8'd0153 :
(mix==7'd0101) ? 8'd0153 :
(mix==7'd0102) ? 8'd0153 :
(mix==7'd0103) ? 8'd0153 :
(mix==7'd0104) ? 8'd0153 :
(mix==7'd0105) ? 8'd0153 :
(mix==7'd0106) ? 8'd0154 :
(mix==7'd0107) ? 8'd0154 :
(mix==7'd0108) ? 8'd0154 :
(mix==7'd0109) ? 8'd0154 :
(mix==7'd0110) ? 8'd0154 :
(mix==7'd0111) ? 8'd0154 :
(mix==7'd0112) ? 8'd0154 :
(mix==7'd0113) ? 8'd0154 :
(mix==7'd0114) ? 8'd0154 :
(mix==7'd0115) ? 8'd0154 :
(mix==7'd0116) ? 8'd0153 :
(mix==7'd0117) ? 8'd0153 :
(mix==7'd0118) ? 8'd0153 :
(mix==7'd0119) ? 8'd0153 :
(mix==7'd0120) ? 8'd0153 :
(mix==7'd0121) ? 8'd0153 :
(mix==7'd0122) ? 8'd0152 :
(mix==7'd0123) ? 8'd0152 :
(mix==7'd0124) ? 8'd0152 :
(mix==7'd0125) ? 8'd0151 :
(mix==7'd0126) ? 8'd0151 :
(mix==7'd0127) ? 8'd0151 : 8'd0151;
//wire [15:0] supersaw_out4_mix16 = supersaw_out4 * center_volume;
//wire [7:0] supersaw_out4_mix = supersaw_out4_mix16 >> 8;
//wire [15:0] supersaw_out1_mix16 = supersaw_out1 * side_volume;
//wire [15:0] supersaw_out2_mix16 = supersaw_out2 * side_volume;
//wire [15:0] supersaw_out3_mix16 = supersaw_out3 * side_volume;
//wire [15:0] supersaw_out5_mix16 = supersaw_out5 * side_volume;
//wire [15:0] supersaw_out6_mix16 = supersaw_out6 * side_volume;
//wire [15:0] supersaw_out7_mix16 = supersaw_out7 * side_volume;
//wire [7:0] supersaw_out1_mix = supersaw_out1_mix16 >> 8;
//wire [7:0] supersaw_out2_mix = supersaw_out2_mix16 >> 8;
//wire [7:0] supersaw_out3_mix = supersaw_out3_mix16 >> 8;
//wire [7:0] supersaw_out5_mix = supersaw_out5_mix16 >> 8;
//wire [7:0] supersaw_out6_mix = supersaw_out6_mix16 >> 8;
//wire [7:0] supersaw_out7_mix = supersaw_out7_mix16 >> 8;
wire [7:0] supersaw_out1_mix;
wire [7:0] supersaw_out2_mix;
wire [7:0] supersaw_out3_mix;
wire [7:0] supersaw_out4_mix;
wire [7:0] supersaw_out5_mix;
wire [7:0] supersaw_out6_mix;
wire [7:0] supersaw_out7_mix;
svca #(.WIDTH(8)) digital_vca_t4(.in(supersaw_out4) , .cv(supersaw_out4), .signal_out(supersaw_out4_mix));
svca #(.WIDTH(8)) digital_vca_t1(.in(supersaw_out1) , .cv(side_volume), .signal_out(supersaw_out1_mix));
svca #(.WIDTH(8)) digital_vca_t2(.in(supersaw_out2) , .cv(side_volume), .signal_out(supersaw_out2_mix));
svca #(.WIDTH(8)) digital_vca_t3(.in(supersaw_out3) , .cv(side_volume), .signal_out(supersaw_out3_mix));
svca #(.WIDTH(8)) digital_vca_t5(.in(supersaw_out5) , .cv(side_volume), .signal_out(supersaw_out5_mix));
svca #(.WIDTH(8)) digital_vca_t6(.in(supersaw_out6) , .cv(side_volume), .signal_out(supersaw_out6_mix));
svca #(.WIDTH(8)) digital_vca_t7(.in(supersaw_out7) , .cv(side_volume), .signal_out(supersaw_out7_mix));
assign ss1 = supersaw_out1_mix;
assign ss2 = supersaw_out2_mix;
assign ss3 = supersaw_out3_mix;
assign ss4 = supersaw_out4_mix;
assign ss5 = supersaw_out5_mix;
assign ss6 = supersaw_out6_mix;
assign ss7 = supersaw_out7_mix;
//noise
reg [7:0] noise_reg;
wire [7:0] noise_out = noise_reg;
wire [7:0] noise_sig;
//16000 hz GENERATOR
wire clk16000;
frq1divmod1 divider1(clk, 25'd1563, clk16000); //50000000 / 16000 / 2 = 1563
reg [1:0] clk16000_prev=2'b00;
always @(posedge clk) clk16000_prev <= {clk16000_prev[0], clk16000};
wire clk16000_posege = (clk16000_prev==2'b01);
rndx #(.WIDTH(8)) random8(.clk(clk), .signal_out(noise_sig));
always @(posedge clk) begin
if (clk16000_posege) begin
noise_reg <= noise_sig;
end
end
//signal_out
assign signal_out = (wave_form == SAW) ? saw_out :
(wave_form == SQUARE) ? square_out :
(wave_form == TRIANGLE) ? tri_out :
(wave_form == SINE) ? sine_out :
(wave_form == RAMP) ? ramp_out :
(wave_form == SAW_TRI) ? saw_tri_out :
(wave_form == SUPERSAW) ? supersaw_out :
(wave_form == NOISE) ? noise_out : 8'd127;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
`define SKY130_FD_SC_HD__A41O_BEHAVIORAL_V
/**
* a41o: 4-input AND into first input of 2-input OR.
*
* X = ((A1 & A2 & A3 & A4) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hd__a41o (
X ,
A1,
A2,
A3,
A4,
B1
);
// Module ports
output X ;
input A1;
input A2;
input A3;
input A4;
input B1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire or0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2, A3, A4 );
or or0 (or0_out_X, and0_out, B1 );
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HD__A41O_BEHAVIORAL_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A211OI_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__A211OI_BEHAVIORAL_V
/**
* a211oi: 2-input AND into first input of 3-input NOR.
*
* Y = !((A1 & A2) | B1 | C1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__a211oi (
Y ,
A1,
A2,
B1,
C1
);
// Module ports
output Y ;
input A1;
input A2;
input B1;
input C1;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
nor nor0 (nor0_out_Y, and0_out, B1, C1);
buf buf0 (Y , nor0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A211OI_BEHAVIORAL_V |
`timescale 1ns / 1ps
`default_nettype none
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 10/15/2015 07:58:09 AM
// Design Name:
// Module Name: SerialServo_tb
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module SerialHandler_tb;
parameter POSITION_WIDTH = 11;
reg clk;
reg rst;
reg ext_clk;
reg ext_flush;
reg serial;
wire [POSITION_WIDTH-1:0] position_output;
reg [7:0] data_in [1:0];
SerialHandler U0(
.clk100MHz(clk),
.rst(rst),
.ext_clk(ext_clk),
.ext_flush(ext_flush),
.serial(serial),
.ser_pos(position_output)
);
integer i = 0;
integer state = 0;
initial
begin
ext_clk = 0;
rst = 1;
ext_flush = 0;
serial = 0;
//serial_register[0] = 16'b0_00000_1111111111;
data_in[0] = 8'b11111_111;
data_in[1] = 8'b1111_1111;
#5
ext_flush = 1;
rst = 0;
#5
ext_flush = 0;
state = 1;
for(i = 0; i < 7; i=i+1) begin
#5
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[0][7-i];
#5
ext_clk = 1;
#1
clk = 1;
#1
clk = 0;
end
state = 2;
for(i = 0; i < 7; i=i+1) begin
#5
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[1][7-i];
#5
ext_clk = 1;
#1
clk = 1;
#1
clk = 0;
end
state = 3;
for(i = 0; i < 7; i=i+1) begin
#5
clk = 0;
ext_clk = 0;
#1
clk = 1;
#1
clk = 0;
serial = data_in[1][i];
#5
ext_clk = 1;
#1
clk = 1;
#1
clk = 0;
end
#5
ext_flush = 1;
#5
ext_flush = 0;
#50
#10 $stop;
#5 $finish;
end
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04:21:51 09/27/2016
// Design Name: controller
// Module Name: C:/Users/Berserk/Dropbox/circuitry/2 sem/lab1/test.v
// Project Name: lab1
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: controller
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
reg clk;
reg reset;
// Outputs
wire red;
wire blue;
wire green;
// Instantiate the Unit Under Test (UUT)
controller uut (
.clk(clk),
.reset(reset),
.red(red),
.blue(blue),
.green(green)
);
event reset_trigger;
initial begin
forever begin
@ (reset_trigger);
@ (negedge clk);
reset = 1;
@ (negedge clk);
reset = 0;
end
end
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
#500000 -> reset_trigger;
end
always begin
#1 clk = ~clk;
end
endmodule
|
//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module usb_system_sysid_qsys_0 (
// inputs:
address,
clock,
reset_n,
// outputs:
readdata
)
;
output [ 31: 0] readdata;
input address;
input clock;
input reset_n;
wire [ 31: 0] readdata;
//control_slave, which is an e_avalon_slave
assign readdata = address ? 1411627075 : 0;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR4_1_V
`define SKY130_FD_SC_LS__NOR4_1_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog wrapper for nor4 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__nor4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_1 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__nor4_1 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__nor4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR4_1_V
|
/************************************************************************
* File Name : mod.v
* Version :
* Date :
* Description :
* Dependencies :
*
* Company : Beijing Soul Tech.
*
* Copyright (C) 2008 Beijing Soul tech.
*
***********************************************************************/
module mod(/*AUTOARG*/
// Outputs
m_src_getn, m_dst_putn, m_dst, m_dst_last, m_endn, m_cap,
// Inputs
wb_clk_i, m_reset, m_enable, dc, m_src, m_src_last,
m_src_almost_empty, m_src_empty, m_dst_almost_full, m_dst_full
);
input wb_clk_i;
input m_reset;
input m_enable;
wire wb_rst_i = m_reset;
input [23:0] dc;
output m_src_getn;
input [63:0] m_src;
input m_src_last;
input m_src_almost_empty;
input m_src_empty;
output m_dst_putn;
output [63:0] m_dst;
output m_dst_last;
input m_dst_almost_full;
input m_dst_full;
output m_endn;
output [7:0] m_cap;
// synopsys translate_off
pullup(m_dst_putn);
pullup(m_src_getn);
pullup(m_endn);
// synopsys translate_on
wire fo_full = m_dst_full || m_dst_almost_full;
wire src_empty = m_src_empty || m_src_almost_empty;
wire [15:0] en_out_data, de_out_data;
wire en_out_valid, de_out_valid;
wire en_out_done, de_out_done;
encode encode(.ce(dc[5] && m_enable),
.fi(m_src),
.clk(wb_clk_i),
.rst(wb_rst_i),
.data_o(en_out_data),
.done_o(en_out_done),
.valid_o(en_out_valid),
.m_last(m_src_last),
/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
// Inputs
.fo_full (fo_full),
.src_empty (src_empty));
decode decode(.ce(dc[6] && m_enable),
.fi(m_src),
.clk(wb_clk_i),
.rst(wb_rst_i),
.data_o(de_out_data),
.done_o(de_out_done),
.valid_o(de_out_valid),
.m_last(m_src_last),
/*AUTOINST*/
// Outputs
.m_src_getn (m_src_getn),
// Inputs
.fo_full (fo_full),
.src_empty (src_empty));
codeout codeout (/*AUTOINST*/
// Outputs
.m_dst (m_dst[63:0]),
.m_dst_putn (m_dst_putn),
.m_dst_last (m_dst_last),
.m_endn (m_endn),
// Inputs
.wb_clk_i (wb_clk_i),
.wb_rst_i (wb_rst_i),
.dc (dc[23:0]),
.en_out_data (en_out_data[15:0]),
.de_out_data (de_out_data[15:0]),
.en_out_valid (en_out_valid),
.de_out_valid (de_out_valid),
.en_out_done (en_out_done),
.de_out_done (de_out_done),
.m_enable (m_enable));
assign m_cap = {1'b1, /* decode */
1'b1, /* encode */
1'b0, /* memcpy */
1'b0,
1'b0,
1'b0,
1'b0};
endmodule // mod
// Local Variables:
// verilog-library-directories:("." "/p/hw/lzs/encode/rtl/verilog" "/p/hw/lzs/decode/rtl/verilog/")
// verilog-library-files:("/some/path/technology.v" "/some/path/tech2.v")
// verilog-library-extensions:(".v" ".h")
// End:
|
// Generated by PCI Express Compiler 10.1 [Altera, IP Toolbench 1.3.0 Build 197]
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2011 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
module pcie_4243_hip_s4gx_gen2_x8_128_core (
AvlClk_i,
CraAddress_i,
CraByteEnable_i,
CraChipSelect_i,
CraRead,
CraWrite,
CraWriteData_i,
Rstn_i,
RxmIrqNum_i,
RxmIrq_i,
RxmReadDataValid_i,
RxmReadData_i,
RxmWaitRequest_i,
TxsAddress_i,
TxsBurstCount_i,
TxsByteEnable_i,
TxsChipSelect_i,
TxsRead_i,
TxsWriteData_i,
TxsWrite_i,
aer_msi_num,
app_int_sts,
app_msi_num,
app_msi_req,
app_msi_tc,
core_clk_in,
cpl_err,
cpl_pending,
crst,
hpg_ctrler,
lmi_addr,
lmi_din,
lmi_rden,
lmi_wren,
npor,
pclk_central,
pclk_ch0,
pex_msi_num,
pld_clk,
pll_fixed_clk,
pm_auxpwr,
pm_data,
pm_event,
pme_to_cr,
rc_areset,
rc_inclk_eq_125mhz,
rc_pll_locked,
rc_rx_pll_locked_one,
rx_st_mask0,
rx_st_ready0,
srst,
test_in,
tx_st_data0,
tx_st_data0_p1,
tx_st_eop0,
tx_st_eop0_p1,
tx_st_err0,
tx_st_sop0,
tx_st_sop0_p1,
tx_st_valid0,
phystatus0_ext,
rxdata0_ext,
rxdatak0_ext,
rxelecidle0_ext,
rxstatus0_ext,
rxvalid0_ext,
phystatus1_ext,
rxdata1_ext,
rxdatak1_ext,
rxelecidle1_ext,
rxstatus1_ext,
rxvalid1_ext,
phystatus2_ext,
rxdata2_ext,
rxdatak2_ext,
rxelecidle2_ext,
rxstatus2_ext,
rxvalid2_ext,
phystatus3_ext,
rxdata3_ext,
rxdatak3_ext,
rxelecidle3_ext,
rxstatus3_ext,
rxvalid3_ext,
phystatus4_ext,
rxdata4_ext,
rxdatak4_ext,
rxelecidle4_ext,
rxstatus4_ext,
rxvalid4_ext,
phystatus5_ext,
rxdata5_ext,
rxdatak5_ext,
rxelecidle5_ext,
rxstatus5_ext,
rxvalid5_ext,
phystatus6_ext,
rxdata6_ext,
rxdatak6_ext,
rxelecidle6_ext,
rxstatus6_ext,
rxvalid6_ext,
phystatus7_ext,
rxdata7_ext,
rxdatak7_ext,
rxelecidle7_ext,
rxstatus7_ext,
rxvalid7_ext,
CraIrq_o,
CraReadData_o,
CraWaitRequest_o,
RxmAddress_o,
RxmBurstCount_o,
RxmByteEnable_o,
RxmRead_o,
RxmWriteData_o,
RxmWrite_o,
TxsReadDataValid_o,
TxsReadData_o,
TxsWaitRequest_o,
app_int_ack,
app_msi_ack,
avs_pcie_reconfig_readdata,
avs_pcie_reconfig_readdatavalid,
avs_pcie_reconfig_waitrequest,
core_clk_out,
derr_cor_ext_rcv0,
derr_cor_ext_rpl,
derr_rpl,
dl_ltssm,
dlup_exit,
eidle_infer_sel,
ev_128ns,
ev_1us,
hip_extraclkout,
hotrst_exit,
int_status,
l2_exit,
lane_act,
lmi_ack,
lmi_dout,
npd_alloc_1cred_vc0,
npd_cred_vio_vc0,
nph_alloc_1cred_vc0,
nph_cred_vio_vc0,
pme_to_sr,
r2c_err0,
rate_ext,
rc_gxb_powerdown,
rc_rx_analogreset,
rc_rx_digitalreset,
rc_tx_digitalreset,
reset_status,
rx_fifo_empty0,
rx_fifo_full0,
rx_st_bardec0,
rx_st_be0,
rx_st_be0_p1,
rx_st_data0,
rx_st_data0_p1,
rx_st_eop0,
rx_st_eop0_p1,
rx_st_err0,
rx_st_sop0,
rx_st_sop0_p1,
rx_st_valid0,
serr_out,
suc_spd_neg,
swdn_wake,
swup_hotrst,
test_out,
tl_cfg_add,
tl_cfg_ctl,
tl_cfg_ctl_wr,
tl_cfg_sts,
tl_cfg_sts_wr,
tx_cred0,
tx_deemph,
tx_fifo_empty0,
tx_fifo_full0,
tx_fifo_rdptr0,
tx_fifo_wrptr0,
tx_margin,
tx_st_ready0,
use_pcie_reconfig,
wake_oen,
powerdown0_ext,
rxpolarity0_ext,
txcompl0_ext,
txdata0_ext,
txdatak0_ext,
txdetectrx0_ext,
txelecidle0_ext,
powerdown1_ext,
rxpolarity1_ext,
txcompl1_ext,
txdata1_ext,
txdatak1_ext,
txdetectrx1_ext,
txelecidle1_ext,
powerdown2_ext,
rxpolarity2_ext,
txcompl2_ext,
txdata2_ext,
txdatak2_ext,
txdetectrx2_ext,
txelecidle2_ext,
powerdown3_ext,
rxpolarity3_ext,
txcompl3_ext,
txdata3_ext,
txdatak3_ext,
txdetectrx3_ext,
txelecidle3_ext,
powerdown4_ext,
rxpolarity4_ext,
txcompl4_ext,
txdata4_ext,
txdatak4_ext,
txdetectrx4_ext,
txelecidle4_ext,
powerdown5_ext,
rxpolarity5_ext,
txcompl5_ext,
txdata5_ext,
txdatak5_ext,
txdetectrx5_ext,
txelecidle5_ext,
powerdown6_ext,
rxpolarity6_ext,
txcompl6_ext,
txdata6_ext,
txdatak6_ext,
txdetectrx6_ext,
txelecidle6_ext,
powerdown7_ext,
rxpolarity7_ext,
txcompl7_ext,
txdata7_ext,
txdatak7_ext,
txdetectrx7_ext,
txelecidle7_ext);
input AvlClk_i;
input [11:0] CraAddress_i;
input [3:0] CraByteEnable_i;
input CraChipSelect_i;
input CraRead;
input CraWrite;
input [31:0] CraWriteData_i;
input Rstn_i;
input [5:0] RxmIrqNum_i;
input RxmIrq_i;
input RxmReadDataValid_i;
input [63:0] RxmReadData_i;
input RxmWaitRequest_i;
input [16:0] TxsAddress_i;
input [9:0] TxsBurstCount_i;
input [7:0] TxsByteEnable_i;
input TxsChipSelect_i;
input TxsRead_i;
input [63:0] TxsWriteData_i;
input TxsWrite_i;
input [4:0] aer_msi_num;
input app_int_sts;
input [4:0] app_msi_num;
input app_msi_req;
input [2:0] app_msi_tc;
input core_clk_in;
input [6:0] cpl_err;
input cpl_pending;
input crst;
input [4:0] hpg_ctrler;
input [11:0] lmi_addr;
input [31:0] lmi_din;
input lmi_rden;
input lmi_wren;
input npor;
input pclk_central;
input pclk_ch0;
input [4:0] pex_msi_num;
input pld_clk;
input pll_fixed_clk;
input pm_auxpwr;
input [9:0] pm_data;
input pm_event;
input pme_to_cr;
input rc_areset;
input rc_inclk_eq_125mhz;
input rc_pll_locked;
input rc_rx_pll_locked_one;
input rx_st_mask0;
input rx_st_ready0;
input srst;
input [39:0] test_in;
input [63:0] tx_st_data0;
input [63:0] tx_st_data0_p1;
input tx_st_eop0;
input tx_st_eop0_p1;
input tx_st_err0;
input tx_st_sop0;
input tx_st_sop0_p1;
input tx_st_valid0;
input phystatus0_ext;
input [7:0] rxdata0_ext;
input rxdatak0_ext;
input rxelecidle0_ext;
input [2:0] rxstatus0_ext;
input rxvalid0_ext;
input phystatus1_ext;
input [7:0] rxdata1_ext;
input rxdatak1_ext;
input rxelecidle1_ext;
input [2:0] rxstatus1_ext;
input rxvalid1_ext;
input phystatus2_ext;
input [7:0] rxdata2_ext;
input rxdatak2_ext;
input rxelecidle2_ext;
input [2:0] rxstatus2_ext;
input rxvalid2_ext;
input phystatus3_ext;
input [7:0] rxdata3_ext;
input rxdatak3_ext;
input rxelecidle3_ext;
input [2:0] rxstatus3_ext;
input rxvalid3_ext;
input phystatus4_ext;
input [7:0] rxdata4_ext;
input rxdatak4_ext;
input rxelecidle4_ext;
input [2:0] rxstatus4_ext;
input rxvalid4_ext;
input phystatus5_ext;
input [7:0] rxdata5_ext;
input rxdatak5_ext;
input rxelecidle5_ext;
input [2:0] rxstatus5_ext;
input rxvalid5_ext;
input phystatus6_ext;
input [7:0] rxdata6_ext;
input rxdatak6_ext;
input rxelecidle6_ext;
input [2:0] rxstatus6_ext;
input rxvalid6_ext;
input phystatus7_ext;
input [7:0] rxdata7_ext;
input rxdatak7_ext;
input rxelecidle7_ext;
input [2:0] rxstatus7_ext;
input rxvalid7_ext;
output CraIrq_o;
output [31:0] CraReadData_o;
output CraWaitRequest_o;
output [31:0] RxmAddress_o;
output [9:0] RxmBurstCount_o;
output [7:0] RxmByteEnable_o;
output RxmRead_o;
output [63:0] RxmWriteData_o;
output RxmWrite_o;
output TxsReadDataValid_o;
output [63:0] TxsReadData_o;
output TxsWaitRequest_o;
output app_int_ack;
output app_msi_ack;
output [15:0] avs_pcie_reconfig_readdata;
output avs_pcie_reconfig_readdatavalid;
output avs_pcie_reconfig_waitrequest;
output core_clk_out;
output derr_cor_ext_rcv0;
output derr_cor_ext_rpl;
output derr_rpl;
output [4:0] dl_ltssm;
output dlup_exit;
output [23:0] eidle_infer_sel;
output ev_128ns;
output ev_1us;
output [1:0] hip_extraclkout;
output hotrst_exit;
output [3:0] int_status;
output l2_exit;
output [3:0] lane_act;
output lmi_ack;
output [31:0] lmi_dout;
output npd_alloc_1cred_vc0;
output npd_cred_vio_vc0;
output nph_alloc_1cred_vc0;
output nph_cred_vio_vc0;
output pme_to_sr;
output r2c_err0;
output rate_ext;
output rc_gxb_powerdown;
output rc_rx_analogreset;
output rc_rx_digitalreset;
output rc_tx_digitalreset;
output reset_status;
output rx_fifo_empty0;
output rx_fifo_full0;
output [7:0] rx_st_bardec0;
output [7:0] rx_st_be0;
output [7:0] rx_st_be0_p1;
output [63:0] rx_st_data0;
output [63:0] rx_st_data0_p1;
output rx_st_eop0;
output rx_st_eop0_p1;
output rx_st_err0;
output rx_st_sop0;
output rx_st_sop0_p1;
output rx_st_valid0;
output serr_out;
output suc_spd_neg;
output swdn_wake;
output swup_hotrst;
output [63:0] test_out;
output [3:0] tl_cfg_add;
output [31:0] tl_cfg_ctl;
output tl_cfg_ctl_wr;
output [52:0] tl_cfg_sts;
output tl_cfg_sts_wr;
output [35:0] tx_cred0;
output [7:0] tx_deemph;
output tx_fifo_empty0;
output tx_fifo_full0;
output [3:0] tx_fifo_rdptr0;
output [3:0] tx_fifo_wrptr0;
output [23:0] tx_margin;
output tx_st_ready0;
output use_pcie_reconfig;
output wake_oen;
output [1:0] powerdown0_ext;
output rxpolarity0_ext;
output txcompl0_ext;
output [7:0] txdata0_ext;
output txdatak0_ext;
output txdetectrx0_ext;
output txelecidle0_ext;
output [1:0] powerdown1_ext;
output rxpolarity1_ext;
output txcompl1_ext;
output [7:0] txdata1_ext;
output txdatak1_ext;
output txdetectrx1_ext;
output txelecidle1_ext;
output [1:0] powerdown2_ext;
output rxpolarity2_ext;
output txcompl2_ext;
output [7:0] txdata2_ext;
output txdatak2_ext;
output txdetectrx2_ext;
output txelecidle2_ext;
output [1:0] powerdown3_ext;
output rxpolarity3_ext;
output txcompl3_ext;
output [7:0] txdata3_ext;
output txdatak3_ext;
output txdetectrx3_ext;
output txelecidle3_ext;
output [1:0] powerdown4_ext;
output rxpolarity4_ext;
output txcompl4_ext;
output [7:0] txdata4_ext;
output txdatak4_ext;
output txdetectrx4_ext;
output txelecidle4_ext;
output [1:0] powerdown5_ext;
output rxpolarity5_ext;
output txcompl5_ext;
output [7:0] txdata5_ext;
output txdatak5_ext;
output txdetectrx5_ext;
output txelecidle5_ext;
output [1:0] powerdown6_ext;
output rxpolarity6_ext;
output txcompl6_ext;
output [7:0] txdata6_ext;
output txdatak6_ext;
output txdetectrx6_ext;
output txelecidle6_ext;
output [1:0] powerdown7_ext;
output rxpolarity7_ext;
output txcompl7_ext;
output [7:0] txdata7_ext;
output txdatak7_ext;
output txdetectrx7_ext;
output txelecidle7_ext;
endmodule
|
// (c) Copyright 2006-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.6.1
// \ \ Application: MIG
// / / Filename: ddr2_infrastructure.v
// /___/ /\ Date Last Modified: $Date: 2010/11/26 18:26:02 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// Clock generation/distribution and reset synchronization
//Reference:
//Revision History:
// Rev 1.1 - Parameter CLK_TYPE added and logic for DIFFERENTIAL and
// SINGLE_ENDED added. PK. 6/20/08
// Rev 1.2 - Loacalparam CLK_GENERATOR added and logic for clocks generation
// using PLL or DCM added as generic code. PK. 10/14/08
// Rev 1.3 - Added parameter NOCLK200 with default value '0'. Used for
// controlling the instantiation of IBUFG for clk200. jul/03/09
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_infrastructure #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_36_1 module. Please refer to
// the mig_36_1 module for actual values.
parameter CLK_PERIOD = 3000,
parameter CLK_TYPE = "DIFFERENTIAL",
parameter DLL_FREQ_MODE = "HIGH",
parameter NOCLK200 = 0,
parameter RST_ACT_LOW = 1
)
(
input sys_clk_p,
input sys_clk_n,
input sys_clk,
input clk200_p,
input clk200_n,
input idly_clk_200,
output clk0,
output clk90,
output clk200,
output clkdiv0,
input sys_rst_n,
input idelay_ctrl_rdy,
output rst0,
output rst90,
output rst200,
output rstdiv0
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on PLL/DCM lock status)
localparam RST_SYNC_NUM = 25;
localparam CLK_PERIOD_NS = CLK_PERIOD / 1000.0;
localparam CLK_PERIOD_INT = CLK_PERIOD/1000;
// By default this Parameter (CLK_GENERATOR) value is "PLL". If this
// Parameter is set to "PLL", PLL is used to generate the design clocks.
// If this Parameter is set to "DCM",
// DCM is used to generate the design clocks.
localparam CLK_GENERATOR = "PLL";
wire clk0_bufg;
wire clk0_bufg_in;
wire clk90_bufg;
wire clk90_bufg_in;
wire clk200_bufg;
wire clk200_ibufg;
wire clkdiv0_bufg;
wire clkdiv0_bufg_in;
wire clkfbout_clkfbin;
wire locked;
reg [RST_SYNC_NUM-1:0] rst0_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst200_sync_r /* synthesis syn_maxfan = 10 */;
reg [RST_SYNC_NUM-1:0] rst90_sync_r /* synthesis syn_maxfan = 10 */;
reg [(RST_SYNC_NUM/2)-1:0] rstdiv0_sync_r /* synthesis syn_maxfan = 10 */;
wire rst_tmp;
wire sys_clk_ibufg;
wire sys_rst;
assign sys_rst = RST_ACT_LOW ? ~sys_rst_n: sys_rst_n;
assign clk0 = clk0_bufg;
assign clk90 = clk90_bufg;
assign clk200 = clk200_bufg;
assign clkdiv0 = clkdiv0_bufg;
generate
if(CLK_TYPE == "DIFFERENTIAL") begin : DIFF_ENDED_CLKS_INST
//***************************************************************************
// Differential input clock input buffers
//***************************************************************************
IBUFGDS_LVPECL_25 SYS_CLK_INST
(
.I (sys_clk_p),
.IB (sys_clk_n),
.O (sys_clk_ibufg)
);
IBUFGDS_LVPECL_25 IDLY_CLK_INST
(
.I (clk200_p),
.IB (clk200_n),
.O (clk200_ibufg)
);
end else if(CLK_TYPE == "SINGLE_ENDED") begin : SINGLE_ENDED_CLKS_INST
//**************************************************************************
// Single ended input clock input buffers
//**************************************************************************
IBUFG SYS_CLK_INST
(
.I (sys_clk),
.O (sys_clk_ibufg)
);
if ( NOCLK200 == 0 ) begin : IBUFG_INST
IBUFG IDLY_CLK_INST
(
.I (idly_clk_200),
.O (clk200_ibufg)
);
end
end
endgenerate
generate
if ( ((NOCLK200 == 0) && (CLK_TYPE == "SINGLE_ENDED")) || (CLK_TYPE == "DIFFERENTIAL") ) begin : BUFG_INST
BUFG CLK_200_BUFG
(
.O (clk200_bufg),
.I (clk200_ibufg)
);
end else begin : NO_BUFG
assign clk200_bufg = 1'b0;
end
endgenerate
//***************************************************************************
// Global clock generation and distribution
//***************************************************************************
generate
if (CLK_GENERATOR == "PLL") begin : gen_pll_adv
PLL_ADV #
(
.BANDWIDTH ("OPTIMIZED"),
.CLKIN1_PERIOD (CLK_PERIOD_NS),
.CLKIN2_PERIOD (10.000),
.CLKOUT0_DIVIDE (CLK_PERIOD_INT),
.CLKOUT1_DIVIDE (CLK_PERIOD_INT),
.CLKOUT2_DIVIDE (CLK_PERIOD_INT*2),
.CLKOUT3_DIVIDE (1),
.CLKOUT4_DIVIDE (1),
.CLKOUT5_DIVIDE (1),
.CLKOUT0_PHASE (0.000),
.CLKOUT1_PHASE (90.000),
.CLKOUT2_PHASE (0.000),
.CLKOUT3_PHASE (0.000),
.CLKOUT4_PHASE (0.000),
.CLKOUT5_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT2_DUTY_CYCLE (0.500),
.CLKOUT3_DUTY_CYCLE (0.500),
.CLKOUT4_DUTY_CYCLE (0.500),
.CLKOUT5_DUTY_CYCLE (0.500),
.COMPENSATION ("SYSTEM_SYNCHRONOUS"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (CLK_PERIOD_INT),
.CLKFBOUT_PHASE (0.0),
.REF_JITTER (0.005000)
)
u_pll_adv
(
.CLKFBIN (clkfbout_clkfbin),
.CLKINSEL (1'b1),
.CLKIN1 (sys_clk_ibufg),
.CLKIN2 (1'b0),
.DADDR (5'b0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'b0),
.DWE (1'b0),
.REL (1'b0),
.RST (sys_rst),
.CLKFBDCM (),
.CLKFBOUT (clkfbout_clkfbin),
.CLKOUTDCM0 (),
.CLKOUTDCM1 (),
.CLKOUTDCM2 (),
.CLKOUTDCM3 (),
.CLKOUTDCM4 (),
.CLKOUTDCM5 (),
.CLKOUT0 (clk0_bufg_in),
.CLKOUT1 (clk90_bufg_in),
.CLKOUT2 (clkdiv0_bufg_in),
.CLKOUT3 (),
.CLKOUT4 (),
.CLKOUT5 (),
.DO (),
.DRDY (),
.LOCKED (locked)
);
end else if (CLK_GENERATOR == "DCM") begin: gen_dcm_base
DCM_BASE #
(
.CLKIN_PERIOD (CLK_PERIOD_NS),
.CLKDV_DIVIDE (2.0),
.DLL_FREQUENCY_MODE (DLL_FREQ_MODE),
.DUTY_CYCLE_CORRECTION ("TRUE"),
.FACTORY_JF (16'hF0F0)
)
u_dcm_base
(
.CLK0 (clk0_bufg_in),
.CLK180 (),
.CLK270 (),
.CLK2X (),
.CLK2X180 (),
.CLK90 (clk90_bufg_in),
.CLKDV (clkdiv0_bufg_in),
.CLKFX (),
.CLKFX180 (),
.LOCKED (locked),
.CLKFB (clk0_bufg),
.CLKIN (sys_clk_ibufg),
.RST (sys_rst)
);
end
endgenerate
BUFG U_BUFG_CLK0
(
.O (clk0_bufg),
.I (clk0_bufg_in)
);
BUFG U_BUFG_CLK90
(
.O (clk90_bufg),
.I (clk90_bufg_in)
);
BUFG U_BUFG_CLKDIV0
(
.O (clkdiv0_bufg),
.I (clkdiv0_bufg_in)
);
//***************************************************************************
// Reset synchronization
// NOTES:
// 1. shut down the whole operation if the PLL/ DCM hasn't yet locked (and
// by inference, this means that external SYS_RST_IN has been asserted -
// PLL/DCM deasserts LOCKED as soon as SYS_RST_IN asserted)
// 2. In the case of all resets except rst200, also assert reset if the
// IDELAY master controller is not yet ready
// 3. asynchronously assert reset. This was we can assert reset even if
// there is no clock (needed for things like 3-stating output buffers).
// reset deassertion is synchronous.
//***************************************************************************
assign rst_tmp = sys_rst | ~locked | ~idelay_ctrl_rdy;
// synthesis attribute max_fanout of rst0_sync_r is 10
always @(posedge clk0_bufg or posedge rst_tmp)
if (rst_tmp)
rst0_sync_r <= {RST_SYNC_NUM{1'b1}};
else
// logical left shift by one (pads with 0)
rst0_sync_r <= rst0_sync_r << 1;
// synthesis attribute max_fanout of rstdiv0_sync_r is 10
always @(posedge clkdiv0_bufg or posedge rst_tmp)
if (rst_tmp)
rstdiv0_sync_r <= {(RST_SYNC_NUM/2){1'b1}};
else
// logical left shift by one (pads with 0)
rstdiv0_sync_r <= rstdiv0_sync_r << 1;
// synthesis attribute max_fanout of rst90_sync_r is 10
always @(posedge clk90_bufg or posedge rst_tmp)
if (rst_tmp)
rst90_sync_r <= {RST_SYNC_NUM{1'b1}};
else
rst90_sync_r <= rst90_sync_r << 1;
// make sure CLK200 doesn't depend on IDELAY_CTRL_RDY, else chicken n' egg
// synthesis attribute max_fanout of rst200_sync_r is 10
always @(posedge clk200_bufg or negedge locked)
if (!locked)
rst200_sync_r <= {RST_SYNC_NUM{1'b1}};
else
rst200_sync_r <= rst200_sync_r << 1;
assign rst0 = rst0_sync_r[RST_SYNC_NUM-1];
assign rst90 = rst90_sync_r[RST_SYNC_NUM-1];
assign rst200 = rst200_sync_r[RST_SYNC_NUM-1];
assign rstdiv0 = rstdiv0_sync_r[(RST_SYNC_NUM/2)-1];
endmodule
|
/* SPDX-License-Identifier: MIT */
/* (c) Copyright 2018 David M. Koltak, all rights reserved. */
/*
* rcn bus slave interface - zero cycle read delay (aka "fast")
*
*/
module rcn_slave_fast
(
input rst,
input clk,
input [68:0] rcn_in,
output [68:0] rcn_out,
output cs,
output wr,
output [3:0] mask,
output [23:0] addr,
output [31:0] wdata,
input [31:0] rdata
);
parameter ADDR_MASK = 0;
parameter ADDR_BASE = 1;
reg [68:0] rin;
reg [68:0] rout;
assign rcn_out = rout;
wire [23:0] my_mask = ADDR_MASK;
wire [23:0] my_base = ADDR_BASE;
wire my_req = rin[68] && rin[67] && ((rin[55:34] & my_mask[23:2]) == my_base[23:2]);
wire [68:0] my_resp;
always @ (posedge clk or posedge rst)
if (rst)
begin
rin <= 68'd0;
rout <= 68'd0;
end
else
begin
rin <= rcn_in;
rout <= (my_req) ? my_resp : rin;
end
assign cs = my_req;
assign wr = rin[66];
assign mask = rin[59:56];
assign addr = {rin[55:34], 2'd0};
assign wdata = rin[31:0];
assign my_resp = {1'b1, 1'b0, rin[66:32], rdata};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A2BB2O_TB_V
`define SKY130_FD_SC_HDLL__A2BB2O_TB_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a2bb2o.v"
module top();
// Inputs are registered
reg A1_N;
reg A2_N;
reg B1;
reg B2;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire X;
initial
begin
// Initial state is x for all inputs.
A1_N = 1'bX;
A2_N = 1'bX;
B1 = 1'bX;
B2 = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A1_N = 1'b0;
#40 A2_N = 1'b0;
#60 B1 = 1'b0;
#80 B2 = 1'b0;
#100 VGND = 1'b0;
#120 VNB = 1'b0;
#140 VPB = 1'b0;
#160 VPWR = 1'b0;
#180 A1_N = 1'b1;
#200 A2_N = 1'b1;
#220 B1 = 1'b1;
#240 B2 = 1'b1;
#260 VGND = 1'b1;
#280 VNB = 1'b1;
#300 VPB = 1'b1;
#320 VPWR = 1'b1;
#340 A1_N = 1'b0;
#360 A2_N = 1'b0;
#380 B1 = 1'b0;
#400 B2 = 1'b0;
#420 VGND = 1'b0;
#440 VNB = 1'b0;
#460 VPB = 1'b0;
#480 VPWR = 1'b0;
#500 VPWR = 1'b1;
#520 VPB = 1'b1;
#540 VNB = 1'b1;
#560 VGND = 1'b1;
#580 B2 = 1'b1;
#600 B1 = 1'b1;
#620 A2_N = 1'b1;
#640 A1_N = 1'b1;
#660 VPWR = 1'bx;
#680 VPB = 1'bx;
#700 VNB = 1'bx;
#720 VGND = 1'bx;
#740 B2 = 1'bx;
#760 B1 = 1'bx;
#780 A2_N = 1'bx;
#800 A1_N = 1'bx;
end
sky130_fd_sc_hdll__a2bb2o dut (.A1_N(A1_N), .A2_N(A2_N), .B1(B1), .B2(B2), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .X(X));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A2BB2O_TB_V
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